From: Luke Kenneth Casson Leighton Date: Fri, 5 Mar 2021 19:19:18 +0000 (+0000) Subject: rename sram_4k wishbone interface to actually like include "wishbone"? X-Git-Tag: LS180_RC3~185 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03fa0d23249a692b2b30b347de8e9dce1d494449;p=soclayout.git rename sram_4k wishbone interface to actually like include "wishbone"? --- diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.il b/experiments9/non_generated/full_core_4_4ksram_ls180.il index 933d33e..5f87ea6 100644 --- a/experiments9/non_generated/full_core_4_4ksram_ls180.il +++ b/experiments9/non_generated/full_core_4_4ksram_ls180.il @@ -1,5 +1,5 @@ # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 15288 +autoidx 15059 attribute \src "libresoc.v:5.1-333.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" @@ -30738,9 +30738,9 @@ module \adr_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:21041.7-21041.15" wire \initial @@ -30942,9 +30942,9 @@ module \adrok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:21103.7-21103.15" wire \initial @@ -32036,9 +32036,9 @@ module \alu0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -35145,9 +35145,9 @@ module \alu_alu0 wire input 18 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 28 \cr_a @@ -36176,9 +36176,9 @@ module \alu_branch0 wire input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 20 \cr_a @@ -36518,9 +36518,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" attribute \generator "nMigen" module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 12 \cr_a @@ -37036,9 +37036,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" attribute \generator "nMigen" module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 27 \cr_a @@ -38542,9 +38542,9 @@ module \alu_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:26073.7-26073.15" wire \initial @@ -38746,9 +38746,9 @@ module \alu_l$107 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:26135.7-26135.15" wire \initial @@ -38950,9 +38950,9 @@ module \alu_l$125 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:26197.7-26197.15" wire \initial @@ -39154,9 +39154,9 @@ module \alu_l$128 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:26259.7-26259.15" wire \initial @@ -39358,9 +39358,9 @@ module \alu_l$16 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:26321.7-26321.15" wire \initial @@ -39562,9 +39562,9 @@ module \alu_l$29 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:26383.7-26383.15" wire \initial @@ -39766,9 +39766,9 @@ module \alu_l$45 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:26445.7-26445.15" wire \initial @@ -39970,9 +39970,9 @@ module \alu_l$61 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:26507.7-26507.15" wire \initial @@ -40174,9 +40174,9 @@ module \alu_l$73 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:26569.7-26569.15" wire \initial @@ -40378,9 +40378,9 @@ module \alu_l$90 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:26631.7-26631.15" wire \initial @@ -40540,9 +40540,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0" attribute \generator "nMigen" module \alu_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -41554,9 +41554,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" attribute \generator "nMigen" module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 21 \cr_a @@ -42770,9 +42770,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" attribute \generator "nMigen" module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -43804,9 +43804,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" attribute \generator "nMigen" module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 16 \fast1 @@ -44365,9 +44365,9 @@ attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" attribute \generator "nMigen" module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 19 \fast1 @@ -45281,9 +45281,9 @@ module \alui_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:31347.7-31347.15" wire \initial @@ -45485,9 +45485,9 @@ module \alui_l$106 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:31409.7-31409.15" wire \initial @@ -45689,9 +45689,9 @@ module \alui_l$124 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:31471.7-31471.15" wire \initial @@ -45893,9 +45893,9 @@ module \alui_l$15 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:31533.7-31533.15" wire \initial @@ -46097,9 +46097,9 @@ module \alui_l$28 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:31595.7-31595.15" wire \initial @@ -46301,9 +46301,9 @@ module \alui_l$44 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:31657.7-31657.15" wire \initial @@ -46505,9 +46505,9 @@ module \alui_l$60 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:31719.7-31719.15" wire \initial @@ -46709,9 +46709,9 @@ module \alui_l$72 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:31781.7-31781.15" wire \initial @@ -46913,9 +46913,9 @@ module \alui_l$89 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:31843.7-31843.15" wire \initial @@ -50356,9 +50356,9 @@ module \branch0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 11 \cu_busy_o @@ -52593,9 +52593,9 @@ module \busy_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "libresoc.v:34308.7-34308.15" wire \initial @@ -56685,3451 +56685,3451 @@ module \clz connect \pair2 \sig_in [3:2] connect \pair0 \sig_in [1:0] end -attribute \src "libresoc.v:35981.1-48834.10" +attribute \src "libresoc.v:35981.1-48836.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core" attribute \generator "nMigen" module \core - attribute \src "libresoc.v:45800.3-45820.6" + attribute \src "libresoc.v:45802.3-45822.6" wire $0\core_terminate_o$next[0:0]$2588 - attribute \src "libresoc.v:42688.3-42689.49" + attribute \src "libresoc.v:42690.3-42691.49" wire $0\core_terminate_o[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $0\corebusy_o[0:0] - attribute \src "libresoc.v:45625.3-45651.6" + attribute \src "libresoc.v:45627.3-45653.6" wire width 2 $0\counter$next[1:0]$2565 - attribute \src "libresoc.v:42690.3-42691.31" + attribute \src "libresoc.v:42692.3-42693.31" wire width 2 $0\counter[1:0] - attribute \src "libresoc.v:46110.3-46118.6" + attribute \src "libresoc.v:46112.3-46120.6" wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 - attribute \src "libresoc.v:42624.3-42625.57" + attribute \src "libresoc.v:42626.3-42627.57" wire $0\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:46091.3-46099.6" + attribute \src "libresoc.v:46093.3-46101.6" wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 - attribute \src "libresoc.v:42626.3-42627.49" + attribute \src "libresoc.v:42628.3-42629.49" wire $0\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46129.3-46137.6" + attribute \src "libresoc.v:46131.3-46139.6" wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 - attribute \src "libresoc.v:42622.3-42623.49" + attribute \src "libresoc.v:42624.3-42625.49" wire $0\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46178.3-46186.6" + attribute \src "libresoc.v:46180.3-46188.6" wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 - attribute \src "libresoc.v:42620.3-42621.49" + attribute \src "libresoc.v:42622.3-42623.49" wire $0\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:46042.3-46050.6" + attribute \src "libresoc.v:46044.3-46052.6" wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 - attribute \src "libresoc.v:42628.3-42629.55" + attribute \src "libresoc.v:42630.3-42631.55" wire $0\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46197.3-46205.6" + attribute \src "libresoc.v:46199.3-46207.6" wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 - attribute \src "libresoc.v:42618.3-42619.63" + attribute \src "libresoc.v:42620.3-42621.63" wire $0\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46264.3-46272.6" + attribute \src "libresoc.v:46266.3-46274.6" wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 - attribute \src "libresoc.v:42614.3-42615.57" + attribute \src "libresoc.v:42616.3-42617.57" wire $0\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46216.3-46224.6" + attribute \src "libresoc.v:46218.3-46226.6" wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 - attribute \src "libresoc.v:42616.3-42617.59" + attribute \src "libresoc.v:42618.3-42619.59" wire $0\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46312.3-46320.6" + attribute \src "libresoc.v:46314.3-46322.6" wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 - attribute \src "libresoc.v:42612.3-42613.63" + attribute \src "libresoc.v:42614.3-42615.63" wire $0\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46331.3-46339.6" + attribute \src "libresoc.v:46333.3-46341.6" wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 - attribute \src "libresoc.v:42610.3-42611.59" + attribute \src "libresoc.v:42612.3-42613.59" wire $0\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:45264.3-45272.6" + attribute \src "libresoc.v:45266.3-45274.6" wire $0\dp_INT_ra_alu0_0$next[0:0]$2457 - attribute \src "libresoc.v:42686.3-42687.49" + attribute \src "libresoc.v:42688.3-42689.49" wire $0\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45283.3-45291.6" + attribute \src "libresoc.v:45285.3-45293.6" wire $0\dp_INT_ra_cr0_1$next[0:0]$2461 - attribute \src "libresoc.v:42684.3-42685.47" + attribute \src "libresoc.v:42686.3-42687.47" wire $0\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45359.3-45367.6" + attribute \src "libresoc.v:45361.3-45369.6" wire $0\dp_INT_ra_div0_5$next[0:0]$2485 - attribute \src "libresoc.v:42676.3-42677.49" + attribute \src "libresoc.v:42678.3-42679.49" wire $0\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45416.3-45424.6" + attribute \src "libresoc.v:45418.3-45426.6" wire $0\dp_INT_ra_ldst0_8$next[0:0]$2503 - attribute \src "libresoc.v:42670.3-42671.51" + attribute \src "libresoc.v:42672.3-42673.51" wire $0\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45321.3-45329.6" + attribute \src "libresoc.v:45323.3-45331.6" wire $0\dp_INT_ra_logical0_3$next[0:0]$2473 - attribute \src "libresoc.v:42680.3-42681.57" + attribute \src "libresoc.v:42682.3-42683.57" wire $0\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45378.3-45386.6" + attribute \src "libresoc.v:45380.3-45388.6" wire $0\dp_INT_ra_mul0_6$next[0:0]$2491 - attribute \src "libresoc.v:42674.3-42675.49" + attribute \src "libresoc.v:42676.3-42677.49" wire $0\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45397.3-45405.6" + attribute \src "libresoc.v:45399.3-45407.6" wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 - attribute \src "libresoc.v:42672.3-42673.59" + attribute \src "libresoc.v:42674.3-42675.59" wire $0\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45340.3-45348.6" + attribute \src "libresoc.v:45342.3-45350.6" wire $0\dp_INT_ra_spr0_4$next[0:0]$2479 - attribute \src "libresoc.v:42678.3-42679.49" + attribute \src "libresoc.v:42680.3-42681.49" wire $0\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45302.3-45310.6" + attribute \src "libresoc.v:45304.3-45312.6" wire $0\dp_INT_ra_trap0_2$next[0:0]$2467 - attribute \src "libresoc.v:42682.3-42683.51" + attribute \src "libresoc.v:42684.3-42685.51" wire $0\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45435.3-45443.6" + attribute \src "libresoc.v:45437.3-45445.6" wire $0\dp_INT_rb_alu0_0$next[0:0]$2509 - attribute \src "libresoc.v:42668.3-42669.49" + attribute \src "libresoc.v:42670.3-42671.49" wire $0\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:45454.3-45462.6" + attribute \src "libresoc.v:45456.3-45464.6" wire $0\dp_INT_rb_cr0_1$next[0:0]$2513 - attribute \src "libresoc.v:42666.3-42667.47" + attribute \src "libresoc.v:42668.3-42669.47" wire $0\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:45511.3-45519.6" + attribute \src "libresoc.v:45513.3-45521.6" wire $0\dp_INT_rb_div0_4$next[0:0]$2531 - attribute \src "libresoc.v:42660.3-42661.49" + attribute \src "libresoc.v:42662.3-42663.49" wire $0\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:45568.3-45576.6" + attribute \src "libresoc.v:45570.3-45578.6" wire $0\dp_INT_rb_ldst0_7$next[0:0]$2549 - attribute \src "libresoc.v:42654.3-42655.51" + attribute \src "libresoc.v:42656.3-42657.51" wire $0\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:45492.3-45500.6" + attribute \src "libresoc.v:45494.3-45502.6" wire $0\dp_INT_rb_logical0_3$next[0:0]$2525 - attribute \src "libresoc.v:42662.3-42663.57" + attribute \src "libresoc.v:42664.3-42665.57" wire $0\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:45530.3-45538.6" + attribute \src "libresoc.v:45532.3-45540.6" wire $0\dp_INT_rb_mul0_5$next[0:0]$2537 - attribute \src "libresoc.v:42658.3-42659.49" + attribute \src "libresoc.v:42660.3-42661.49" wire $0\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:45549.3-45557.6" + attribute \src "libresoc.v:45551.3-45559.6" wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 - attribute \src "libresoc.v:42656.3-42657.59" + attribute \src "libresoc.v:42658.3-42659.59" wire $0\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:45473.3-45481.6" + attribute \src "libresoc.v:45475.3-45483.6" wire $0\dp_INT_rb_trap0_2$next[0:0]$2519 - attribute \src "libresoc.v:42664.3-42665.51" + attribute \src "libresoc.v:42666.3-42667.51" wire $0\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:45606.3-45614.6" + attribute \src "libresoc.v:45608.3-45616.6" wire $0\dp_INT_rc_ldst0_1$next[0:0]$2559 - attribute \src "libresoc.v:42650.3-42651.51" + attribute \src "libresoc.v:42652.3-42653.51" wire $0\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:45587.3-45595.6" + attribute \src "libresoc.v:45589.3-45597.6" wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 - attribute \src "libresoc.v:42652.3-42653.59" + attribute \src "libresoc.v:42654.3-42655.59" wire $0\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46379.3-46387.6" + attribute \src "libresoc.v:46381.3-46389.6" wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 - attribute \src "libresoc.v:42608.3-42609.53" + attribute \src "libresoc.v:42610.3-42611.53" wire $0\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:45907.3-45915.6" + attribute \src "libresoc.v:45909.3-45917.6" wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 - attribute \src "libresoc.v:42636.3-42637.57" + attribute \src "libresoc.v:42638.3-42639.57" wire $0\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:45974.3-45982.6" + attribute \src "libresoc.v:45976.3-45984.6" wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 - attribute \src "libresoc.v:42632.3-42633.67" + attribute \src "libresoc.v:42634.3-42635.67" wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:45955.3-45963.6" + attribute \src "libresoc.v:45957.3-45965.6" wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 - attribute \src "libresoc.v:42634.3-42635.57" + attribute \src "libresoc.v:42636.3-42637.57" wire $0\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:46023.3-46031.6" + attribute \src "libresoc.v:46025.3-46033.6" wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 - attribute \src "libresoc.v:42630.3-42631.57" + attribute \src "libresoc.v:42632.3-42633.57" wire $0\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:45652.3-45660.6" + attribute \src "libresoc.v:45654.3-45662.6" wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 - attribute \src "libresoc.v:42648.3-42649.57" + attribute \src "libresoc.v:42650.3-42651.57" wire $0\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:45821.3-45829.6" + attribute \src "libresoc.v:45823.3-45831.6" wire $0\dp_XER_xer_so_div0_3$next[0:0]$2593 - attribute \src "libresoc.v:42642.3-42643.57" + attribute \src "libresoc.v:42644.3-42645.57" wire $0\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:45762.3-45770.6" + attribute \src "libresoc.v:45764.3-45772.6" wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 - attribute \src "libresoc.v:42646.3-42647.65" + attribute \src "libresoc.v:42648.3-42649.65" wire $0\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:45840.3-45848.6" + attribute \src "libresoc.v:45842.3-45850.6" wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 - attribute \src "libresoc.v:42640.3-42641.57" + attribute \src "libresoc.v:42642.3-42643.57" wire $0\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:45888.3-45896.6" + attribute \src "libresoc.v:45890.3-45898.6" wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 - attribute \src "libresoc.v:42638.3-42639.67" + attribute \src "libresoc.v:42640.3-42641.67" wire $0\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:45781.3-45789.6" + attribute \src "libresoc.v:45783.3-45791.6" wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 - attribute \src "libresoc.v:42644.3-42645.57" + attribute \src "libresoc.v:42646.3-42647.57" wire $0\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:46899.3-46927.6" + attribute \src "libresoc.v:46901.3-46929.6" wire $0\fus_cu_issue_i$13[0:0]$2768 - attribute \src "libresoc.v:47296.3-47324.6" + attribute \src "libresoc.v:47298.3-47326.6" wire $0\fus_cu_issue_i$16[0:0]$2830 - attribute \src "libresoc.v:47660.3-47688.6" + attribute \src "libresoc.v:47662.3-47690.6" wire $0\fus_cu_issue_i$19[0:0]$2864 - attribute \src "libresoc.v:48156.3-48184.6" + attribute \src "libresoc.v:48158.3-48186.6" wire $0\fus_cu_issue_i$22[0:0]$2889 - attribute \src "libresoc.v:43483.3-43511.6" + attribute \src "libresoc.v:43485.3-43513.6" wire $0\fus_cu_issue_i$25[0:0]$2356 - attribute \src "libresoc.v:43979.3-44007.6" + attribute \src "libresoc.v:43981.3-44009.6" wire $0\fus_cu_issue_i$28[0:0]$2381 - attribute \src "libresoc.v:44301.3-44329.6" + attribute \src "libresoc.v:44303.3-44331.6" wire $0\fus_cu_issue_i$31[0:0]$2400 - attribute \src "libresoc.v:44768.3-44796.6" + attribute \src "libresoc.v:44770.3-44798.6" wire $0\fus_cu_issue_i$34[0:0]$2424 - attribute \src "libresoc.v:45206.3-45234.6" + attribute \src "libresoc.v:45208.3-45236.6" wire $0\fus_cu_issue_i$37[0:0]$2447 - attribute \src "libresoc.v:46691.3-46719.6" + attribute \src "libresoc.v:46693.3-46721.6" wire $0\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46937.3-46965.6" + attribute \src "libresoc.v:46939.3-46967.6" wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2776 - attribute \src "libresoc.v:47334.3-47362.6" + attribute \src "libresoc.v:47336.3-47364.6" wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2838 - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47691.3-47719.6" wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2869 - attribute \src "libresoc.v:48185.3-48213.6" + attribute \src "libresoc.v:48187.3-48215.6" wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2894 - attribute \src "libresoc.v:43512.3-43540.6" + attribute \src "libresoc.v:43514.3-43542.6" wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2361 - attribute \src "libresoc.v:44008.3-44036.6" + attribute \src "libresoc.v:44010.3-44038.6" wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2386 - attribute \src "libresoc.v:44330.3-44358.6" + attribute \src "libresoc.v:44332.3-44360.6" wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2405 - attribute \src "libresoc.v:44797.3-44825.6" + attribute \src "libresoc.v:44799.3-44827.6" wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2429 - attribute \src "libresoc.v:45235.3-45263.6" + attribute \src "libresoc.v:45237.3-45265.6" wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2452 - attribute \src "libresoc.v:46729.3-46757.6" + attribute \src "libresoc.v:46731.3-46759.6" wire width 4 $0\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46606.3-46634.6" + attribute \src "libresoc.v:46608.3-46636.6" wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45916.3-45944.6" + attribute \src "libresoc.v:45918.3-45946.6" wire width 13 $0\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "libresoc.v:45983.3-46012.6" + attribute \src "libresoc.v:45985.3-46014.6" wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45983.3-46012.6" + attribute \src "libresoc.v:45985.3-46014.6" wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46436.3-46464.6" + attribute \src "libresoc.v:46438.3-46466.6" wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46653.3-46681.6" + attribute \src "libresoc.v:46655.3-46683.6" wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45859.3-45887.6" + attribute \src "libresoc.v:45861.3-45889.6" wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46235.3-46263.6" + attribute \src "libresoc.v:46237.3-46265.6" wire $0\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46350.3-46378.6" + attribute \src "libresoc.v:46352.3-46380.6" wire $0\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46521.3-46549.6" + attribute \src "libresoc.v:46523.3-46551.6" wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46568.3-46596.6" + attribute \src "libresoc.v:46570.3-46598.6" wire $0\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46148.3-46177.6" + attribute \src "libresoc.v:46150.3-46179.6" wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46148.3-46177.6" + attribute \src "libresoc.v:46150.3-46179.6" wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46483.3-46511.6" + attribute \src "libresoc.v:46485.3-46513.6" wire $0\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46061.3-46090.6" + attribute \src "libresoc.v:46063.3-46092.6" wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46061.3-46090.6" + attribute \src "libresoc.v:46063.3-46092.6" wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46398.3-46426.6" + attribute \src "libresoc.v:46400.3-46428.6" wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46283.3-46311.6" + attribute \src "libresoc.v:46285.3-46313.6" wire $0\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46984.3-47012.6" + attribute \src "libresoc.v:46986.3-47014.6" wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47069.3-47097.6" + attribute \src "libresoc.v:47071.3-47099.6" wire width 13 $0\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "libresoc.v:47154.3-47183.6" + attribute \src "libresoc.v:47156.3-47185.6" wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47154.3-47183.6" + attribute \src "libresoc.v:47156.3-47185.6" wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47107.3-47135.6" + attribute \src "libresoc.v:47109.3-47137.6" wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47022.3-47050.6" + attribute \src "libresoc.v:47024.3-47052.6" wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47249.3-47277.6" + attribute \src "libresoc.v:47251.3-47279.6" wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47211.3-47239.6" + attribute \src "libresoc.v:47213.3-47241.6" wire $0\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46814.3-46842.6" + attribute \src "libresoc.v:46816.3-46844.6" wire width 13 $0\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "libresoc.v:46861.3-46889.6" + attribute \src "libresoc.v:46863.3-46891.6" wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46767.3-46795.6" + attribute \src "libresoc.v:46769.3-46797.6" wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43921.3-43949.6" + attribute \src "libresoc.v:43923.3-43951.6" wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43570.3-43598.6" + attribute \src "libresoc.v:43572.3-43600.6" wire width 13 $0\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "libresoc.v:43599.3-43628.6" + attribute \src "libresoc.v:43601.3-43630.6" wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43599.3-43628.6" + attribute \src "libresoc.v:43601.3-43630.6" wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43747.3-43775.6" + attribute \src "libresoc.v:43749.3-43777.6" wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43950.3-43978.6" + attribute \src "libresoc.v:43952.3-43980.6" wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43541.3-43569.6" + attribute \src "libresoc.v:43543.3-43571.6" wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43689.3-43717.6" + attribute \src "libresoc.v:43691.3-43719.6" wire $0\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43776.3-43804.6" + attribute \src "libresoc.v:43778.3-43806.6" wire $0\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43863.3-43891.6" + attribute \src "libresoc.v:43865.3-43893.6" wire $0\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43892.3-43920.6" + attribute \src "libresoc.v:43894.3-43922.6" wire $0\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43659.3-43688.6" + attribute \src "libresoc.v:43661.3-43690.6" wire $0\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43659.3-43688.6" + attribute \src "libresoc.v:43661.3-43690.6" wire $0\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43834.3-43862.6" + attribute \src "libresoc.v:43836.3-43864.6" wire $0\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43629.3-43658.6" + attribute \src "libresoc.v:43631.3-43660.6" wire $0\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43629.3-43658.6" + attribute \src "libresoc.v:43631.3-43660.6" wire $0\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43805.3-43833.6" + attribute \src "libresoc.v:43807.3-43835.6" wire $0\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43718.3-43746.6" + attribute \src "libresoc.v:43720.3-43748.6" wire $0\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:48098.3-48126.6" + attribute \src "libresoc.v:48100.3-48128.6" wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47747.3-47775.6" + attribute \src "libresoc.v:47749.3-47777.6" wire width 13 $0\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "libresoc.v:47776.3-47805.6" + attribute \src "libresoc.v:47778.3-47807.6" wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47776.3-47805.6" + attribute \src "libresoc.v:47778.3-47807.6" wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47924.3-47952.6" + attribute \src "libresoc.v:47926.3-47954.6" wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48127.3-48155.6" + attribute \src "libresoc.v:48129.3-48157.6" wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47718.3-47746.6" + attribute \src "libresoc.v:47720.3-47748.6" wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47866.3-47894.6" + attribute \src "libresoc.v:47868.3-47896.6" wire $0\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47953.3-47981.6" + attribute \src "libresoc.v:47955.3-47983.6" wire $0\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48040.3-48068.6" + attribute \src "libresoc.v:48042.3-48070.6" wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:48069.3-48097.6" + attribute \src "libresoc.v:48071.3-48099.6" wire $0\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47836.3-47865.6" + attribute \src "libresoc.v:47838.3-47867.6" wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47836.3-47865.6" + attribute \src "libresoc.v:47838.3-47867.6" wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48011.3-48039.6" + attribute \src "libresoc.v:48013.3-48041.6" wire $0\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47806.3-47835.6" + attribute \src "libresoc.v:47808.3-47837.6" wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47806.3-47835.6" + attribute \src "libresoc.v:47808.3-47837.6" wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47982.3-48010.6" + attribute \src "libresoc.v:47984.3-48012.6" wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47895.3-47923.6" + attribute \src "libresoc.v:47897.3-47925.6" wire $0\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44066.3-44094.6" + attribute \src "libresoc.v:44068.3-44096.6" wire width 13 $0\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "libresoc.v:44095.3-44124.6" + attribute \src "libresoc.v:44097.3-44126.6" wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44095.3-44124.6" + attribute \src "libresoc.v:44097.3-44126.6" wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44272.3-44300.6" + attribute \src "libresoc.v:44274.3-44302.6" wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44037.3-44065.6" + attribute \src "libresoc.v:44039.3-44067.6" wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44214.3-44242.6" + attribute \src "libresoc.v:44216.3-44244.6" wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44243.3-44271.6" + attribute \src "libresoc.v:44245.3-44273.6" wire $0\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44155.3-44184.6" + attribute \src "libresoc.v:44157.3-44186.6" wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44155.3-44184.6" + attribute \src "libresoc.v:44157.3-44186.6" wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44125.3-44154.6" + attribute \src "libresoc.v:44127.3-44156.6" wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44125.3-44154.6" + attribute \src "libresoc.v:44127.3-44156.6" wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44185.3-44213.6" + attribute \src "libresoc.v:44187.3-44215.6" wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44388.3-44416.6" + attribute \src "libresoc.v:44390.3-44418.6" wire width 13 $0\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "libresoc.v:44417.3-44446.6" + attribute \src "libresoc.v:44419.3-44448.6" wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44417.3-44446.6" + attribute \src "libresoc.v:44419.3-44448.6" wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44565.3-44593.6" + attribute \src "libresoc.v:44567.3-44595.6" wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44623.3-44651.6" + attribute \src "libresoc.v:44625.3-44653.6" wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44739.3-44767.6" + attribute \src "libresoc.v:44741.3-44769.6" wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44359.3-44387.6" + attribute \src "libresoc.v:44361.3-44389.6" wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44536.3-44564.6" + attribute \src "libresoc.v:44538.3-44566.6" wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44681.3-44709.6" + attribute \src "libresoc.v:44683.3-44711.6" wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44710.3-44738.6" + attribute \src "libresoc.v:44712.3-44740.6" wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44477.3-44506.6" + attribute \src "libresoc.v:44479.3-44508.6" wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44477.3-44506.6" + attribute \src "libresoc.v:44479.3-44508.6" wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44594.3-44622.6" + attribute \src "libresoc.v:44596.3-44624.6" wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44652.3-44680.6" + attribute \src "libresoc.v:44654.3-44682.6" wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44447.3-44476.6" + attribute \src "libresoc.v:44449.3-44478.6" wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44447.3-44476.6" + attribute \src "libresoc.v:44449.3-44478.6" wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44507.3-44535.6" + attribute \src "libresoc.v:44509.3-44537.6" wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48243.3-48271.6" + attribute \src "libresoc.v:48245.3-48273.6" wire width 13 $0\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "libresoc.v:43425.3-43453.6" + attribute \src "libresoc.v:43427.3-43455.6" wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48214.3-48242.6" + attribute \src "libresoc.v:48216.3-48244.6" wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43454.3-43482.6" + attribute \src "libresoc.v:43456.3-43484.6" wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47515.3-47543.6" + attribute \src "libresoc.v:47517.3-47545.6" wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47419.3-47447.6" + attribute \src "libresoc.v:47421.3-47449.6" wire width 13 $0\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "libresoc.v:47457.3-47485.6" + attribute \src "libresoc.v:47459.3-47487.6" wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47372.3-47400.6" + attribute \src "libresoc.v:47374.3-47402.6" wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47544.3-47572.6" + attribute \src "libresoc.v:47546.3-47574.6" wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47631.3-47659.6" + attribute \src "libresoc.v:47633.3-47661.6" wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47486.3-47514.6" + attribute \src "libresoc.v:47488.3-47516.6" wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47602.3-47630.6" + attribute \src "libresoc.v:47604.3-47632.6" wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47573.3-47601.6" + attribute \src "libresoc.v:47575.3-47603.6" wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45090.3-45118.6" + attribute \src "libresoc.v:45092.3-45120.6" wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45061.3-45089.6" + attribute \src "libresoc.v:45063.3-45091.6" wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44855.3-44883.6" + attribute \src "libresoc.v:44857.3-44885.6" wire width 13 $0\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "libresoc.v:44884.3-44913.6" + attribute \src "libresoc.v:44886.3-44915.6" wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44884.3-44913.6" + attribute \src "libresoc.v:44886.3-44915.6" wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45177.3-45205.6" + attribute \src "libresoc.v:45179.3-45207.6" wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44826.3-44854.6" + attribute \src "libresoc.v:44828.3-44856.6" wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45003.3-45031.6" + attribute \src "libresoc.v:45005.3-45033.6" wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45032.3-45060.6" + attribute \src "libresoc.v:45034.3-45062.6" wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45148.3-45176.6" + attribute \src "libresoc.v:45150.3-45178.6" wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44973.3-45002.6" + attribute \src "libresoc.v:44975.3-45004.6" wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44973.3-45002.6" + attribute \src "libresoc.v:44975.3-45004.6" wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44943.3-44972.6" + attribute \src "libresoc.v:44945.3-44974.6" wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44943.3-44972.6" + attribute \src "libresoc.v:44945.3-44974.6" wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45119.3-45147.6" + attribute \src "libresoc.v:45121.3-45149.6" wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44914.3-44942.6" + attribute \src "libresoc.v:44916.3-44944.6" wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45292.3-45301.6" + attribute \src "libresoc.v:45294.3-45303.6" wire width 64 $0\fus_src1_i$42[63:0]$2464 - attribute \src "libresoc.v:45311.3-45320.6" + attribute \src "libresoc.v:45313.3-45322.6" wire width 64 $0\fus_src1_i$45[63:0]$2470 - attribute \src "libresoc.v:45330.3-45339.6" + attribute \src "libresoc.v:45332.3-45341.6" wire width 64 $0\fus_src1_i$48[63:0]$2476 - attribute \src "libresoc.v:45349.3-45358.6" + attribute \src "libresoc.v:45351.3-45360.6" wire width 64 $0\fus_src1_i$51[63:0]$2482 - attribute \src "libresoc.v:45368.3-45377.6" + attribute \src "libresoc.v:45370.3-45379.6" wire width 64 $0\fus_src1_i$54[63:0]$2488 - attribute \src "libresoc.v:45387.3-45396.6" + attribute \src "libresoc.v:45389.3-45398.6" wire width 64 $0\fus_src1_i$57[63:0]$2494 - attribute \src "libresoc.v:45406.3-45415.6" + attribute \src "libresoc.v:45408.3-45417.6" wire width 64 $0\fus_src1_i$60[63:0]$2500 - attribute \src "libresoc.v:45425.3-45434.6" + attribute \src "libresoc.v:45427.3-45436.6" wire width 64 $0\fus_src1_i$63[63:0]$2506 - attribute \src "libresoc.v:46206.3-46215.6" + attribute \src "libresoc.v:46208.3-46217.6" wire width 64 $0\fus_src1_i$86[63:0]$2669 - attribute \src "libresoc.v:45273.3-45282.6" + attribute \src "libresoc.v:45275.3-45284.6" wire width 64 $0\fus_src1_i[63:0] - attribute \src "libresoc.v:45463.3-45472.6" + attribute \src "libresoc.v:45465.3-45474.6" wire width 64 $0\fus_src2_i$64[63:0]$2516 - attribute \src "libresoc.v:45482.3-45491.6" + attribute \src "libresoc.v:45484.3-45493.6" wire width 64 $0\fus_src2_i$65[63:0]$2522 - attribute \src "libresoc.v:45501.3-45510.6" + attribute \src "libresoc.v:45503.3-45512.6" wire width 64 $0\fus_src2_i$66[63:0]$2528 - attribute \src "libresoc.v:45520.3-45529.6" + attribute \src "libresoc.v:45522.3-45531.6" wire width 64 $0\fus_src2_i$67[63:0]$2534 - attribute \src "libresoc.v:45539.3-45548.6" + attribute \src "libresoc.v:45541.3-45550.6" wire width 64 $0\fus_src2_i$68[63:0]$2540 - attribute \src "libresoc.v:45558.3-45567.6" + attribute \src "libresoc.v:45560.3-45569.6" wire width 64 $0\fus_src2_i$69[63:0]$2546 - attribute \src "libresoc.v:45577.3-45586.6" + attribute \src "libresoc.v:45579.3-45588.6" wire width 64 $0\fus_src2_i$70[63:0]$2552 - attribute \src "libresoc.v:46321.3-46330.6" + attribute \src "libresoc.v:46323.3-46332.6" wire width 64 $0\fus_src2_i$89[63:0]$2689 - attribute \src "libresoc.v:46388.3-46397.6" + attribute \src "libresoc.v:46390.3-46399.6" wire width 64 $0\fus_src2_i$91[63:0]$2702 - attribute \src "libresoc.v:45444.3-45453.6" + attribute \src "libresoc.v:45446.3-45455.6" wire width 64 $0\fus_src2_i[63:0] - attribute \src "libresoc.v:45615.3-45624.6" + attribute \src "libresoc.v:45617.3-45626.6" wire width 64 $0\fus_src3_i$71[63:0]$2562 - attribute \src "libresoc.v:45661.3-45670.6" + attribute \src "libresoc.v:45663.3-45672.6" wire $0\fus_src3_i$72[0:0]$2574 - attribute \src "libresoc.v:45771.3-45780.6" + attribute \src "libresoc.v:45773.3-45782.6" wire $0\fus_src3_i$73[0:0]$2581 - attribute \src "libresoc.v:45830.3-45839.6" + attribute \src "libresoc.v:45832.3-45841.6" wire $0\fus_src3_i$74[0:0]$2596 - attribute \src "libresoc.v:45849.3-45858.6" + attribute \src "libresoc.v:45851.3-45860.6" wire $0\fus_src3_i$75[0:0]$2602 - attribute \src "libresoc.v:46051.3-46060.6" + attribute \src "libresoc.v:46053.3-46062.6" wire width 32 $0\fus_src3_i$79[31:0]$2637 - attribute \src "libresoc.v:46119.3-46128.6" + attribute \src "libresoc.v:46121.3-46130.6" wire width 4 $0\fus_src3_i$83[3:0]$2650 - attribute \src "libresoc.v:46225.3-46234.6" + attribute \src "libresoc.v:46227.3-46236.6" wire width 64 $0\fus_src3_i$87[63:0]$2675 - attribute \src "libresoc.v:46273.3-46282.6" + attribute \src "libresoc.v:46275.3-46284.6" wire width 64 $0\fus_src3_i$88[63:0]$2682 - attribute \src "libresoc.v:45596.3-45605.6" + attribute \src "libresoc.v:45598.3-45607.6" wire width 64 $0\fus_src3_i[63:0] - attribute \src "libresoc.v:45897.3-45906.6" + attribute \src "libresoc.v:45899.3-45908.6" wire $0\fus_src4_i$76[0:0]$2609 - attribute \src "libresoc.v:45945.3-45954.6" + attribute \src "libresoc.v:45947.3-45956.6" wire width 2 $0\fus_src4_i$77[1:0]$2616 - attribute \src "libresoc.v:46100.3-46109.6" + attribute \src "libresoc.v:46102.3-46111.6" wire width 4 $0\fus_src4_i$80[3:0]$2644 - attribute \src "libresoc.v:46340.3-46349.6" + attribute \src "libresoc.v:46342.3-46351.6" wire width 64 $0\fus_src4_i$90[63:0]$2695 - attribute \src "libresoc.v:45790.3-45799.6" + attribute \src "libresoc.v:45792.3-45801.6" wire $0\fus_src4_i[0:0] - attribute \src "libresoc.v:46032.3-46041.6" + attribute \src "libresoc.v:46034.3-46043.6" wire width 2 $0\fus_src5_i$78[1:0]$2631 - attribute \src "libresoc.v:46138.3-46147.6" + attribute \src "libresoc.v:46140.3-46149.6" wire width 4 $0\fus_src5_i$84[3:0]$2656 - attribute \src "libresoc.v:46013.3-46022.6" + attribute \src "libresoc.v:46015.3-46024.6" wire width 2 $0\fus_src5_i[1:0] - attribute \src "libresoc.v:46187.3-46196.6" + attribute \src "libresoc.v:46189.3-46198.6" wire width 4 $0\fus_src6_i$85[3:0]$2663 - attribute \src "libresoc.v:45964.3-45973.6" + attribute \src "libresoc.v:45966.3-45975.6" wire width 2 $0\fus_src6_i[1:0] attribute \src "libresoc.v:35982.7-35982.20" wire $0\initial[0:0] - attribute \src "libresoc.v:46474.3-46482.6" + attribute \src "libresoc.v:46476.3-46484.6" wire $0\wr_pick_dly$1005$next[0:0]$2713 - attribute \src "libresoc.v:42602.3-42603.51" + attribute \src "libresoc.v:42604.3-42605.51" wire $0\wr_pick_dly$1005[0:0]$2307 - attribute \src "libresoc.v:41432.7-41432.32" + attribute \src "libresoc.v:41434.7-41434.32" wire $0\wr_pick_dly$1005[0:0]$2945 - attribute \src "libresoc.v:46512.3-46520.6" + attribute \src "libresoc.v:46514.3-46522.6" wire $0\wr_pick_dly$1026$next[0:0]$2717 - attribute \src "libresoc.v:42600.3-42601.51" + attribute \src "libresoc.v:42602.3-42603.51" wire $0\wr_pick_dly$1026[0:0]$2305 - attribute \src "libresoc.v:41436.7-41436.32" + attribute \src "libresoc.v:41438.7-41438.32" wire $0\wr_pick_dly$1026[0:0]$2947 - attribute \src "libresoc.v:46550.3-46558.6" + attribute \src "libresoc.v:46552.3-46560.6" wire $0\wr_pick_dly$1044$next[0:0]$2721 - attribute \src "libresoc.v:42598.3-42599.51" + attribute \src "libresoc.v:42600.3-42601.51" wire $0\wr_pick_dly$1044[0:0]$2303 - attribute \src "libresoc.v:41440.7-41440.32" + attribute \src "libresoc.v:41442.7-41442.32" wire $0\wr_pick_dly$1044[0:0]$2949 - attribute \src "libresoc.v:46559.3-46567.6" + attribute \src "libresoc.v:46561.3-46569.6" wire $0\wr_pick_dly$1066$next[0:0]$2724 - attribute \src "libresoc.v:42596.3-42597.51" + attribute \src "libresoc.v:42598.3-42599.51" wire $0\wr_pick_dly$1066[0:0]$2301 - attribute \src "libresoc.v:41444.7-41444.32" + attribute \src "libresoc.v:41446.7-41446.32" wire $0\wr_pick_dly$1066[0:0]$2951 - attribute \src "libresoc.v:46597.3-46605.6" + attribute \src "libresoc.v:46599.3-46607.6" wire $0\wr_pick_dly$1086$next[0:0]$2728 - attribute \src "libresoc.v:42594.3-42595.51" + attribute \src "libresoc.v:42596.3-42597.51" wire $0\wr_pick_dly$1086[0:0]$2299 - attribute \src "libresoc.v:41448.7-41448.32" + attribute \src "libresoc.v:41450.7-41450.32" wire $0\wr_pick_dly$1086[0:0]$2953 - attribute \src "libresoc.v:46635.3-46643.6" + attribute \src "libresoc.v:46637.3-46645.6" wire $0\wr_pick_dly$1106$next[0:0]$2732 - attribute \src "libresoc.v:42592.3-42593.51" + attribute \src "libresoc.v:42594.3-42595.51" wire $0\wr_pick_dly$1106[0:0]$2297 - attribute \src "libresoc.v:41452.7-41452.32" + attribute \src "libresoc.v:41454.7-41454.32" wire $0\wr_pick_dly$1106[0:0]$2955 - attribute \src "libresoc.v:46644.3-46652.6" + attribute \src "libresoc.v:46646.3-46654.6" wire $0\wr_pick_dly$1125$next[0:0]$2735 - attribute \src "libresoc.v:42590.3-42591.51" + attribute \src "libresoc.v:42592.3-42593.51" wire $0\wr_pick_dly$1125[0:0]$2295 - attribute \src "libresoc.v:41456.7-41456.32" + attribute \src "libresoc.v:41458.7-41458.32" wire $0\wr_pick_dly$1125[0:0]$2957 - attribute \src "libresoc.v:46682.3-46690.6" + attribute \src "libresoc.v:46684.3-46692.6" wire $0\wr_pick_dly$1143$next[0:0]$2739 - attribute \src "libresoc.v:42588.3-42589.51" + attribute \src "libresoc.v:42590.3-42591.51" wire $0\wr_pick_dly$1143[0:0]$2293 - attribute \src "libresoc.v:41460.7-41460.32" + attribute \src "libresoc.v:41462.7-41462.32" wire $0\wr_pick_dly$1143[0:0]$2959 - attribute \src "libresoc.v:46720.3-46728.6" + attribute \src "libresoc.v:46722.3-46730.6" wire $0\wr_pick_dly$1217$next[0:0]$2743 - attribute \src "libresoc.v:42586.3-42587.51" + attribute \src "libresoc.v:42588.3-42589.51" wire $0\wr_pick_dly$1217[0:0]$2291 - attribute \src "libresoc.v:41464.7-41464.32" + attribute \src "libresoc.v:41466.7-41466.32" wire $0\wr_pick_dly$1217[0:0]$2961 - attribute \src "libresoc.v:46758.3-46766.6" + attribute \src "libresoc.v:46760.3-46768.6" wire $0\wr_pick_dly$1245$next[0:0]$2747 - attribute \src "libresoc.v:42584.3-42585.51" + attribute \src "libresoc.v:42586.3-42587.51" wire $0\wr_pick_dly$1245[0:0]$2289 - attribute \src "libresoc.v:41468.7-41468.32" + attribute \src "libresoc.v:41470.7-41470.32" wire $0\wr_pick_dly$1245[0:0]$2963 - attribute \src "libresoc.v:46796.3-46804.6" + attribute \src "libresoc.v:46798.3-46806.6" wire $0\wr_pick_dly$1265$next[0:0]$2751 - attribute \src "libresoc.v:42582.3-42583.51" + attribute \src "libresoc.v:42584.3-42585.51" wire $0\wr_pick_dly$1265[0:0]$2287 - attribute \src "libresoc.v:41472.7-41472.32" + attribute \src "libresoc.v:41474.7-41474.32" wire $0\wr_pick_dly$1265[0:0]$2965 - attribute \src "libresoc.v:46805.3-46813.6" + attribute \src "libresoc.v:46807.3-46815.6" wire $0\wr_pick_dly$1285$next[0:0]$2754 - attribute \src "libresoc.v:42580.3-42581.51" + attribute \src "libresoc.v:42582.3-42583.51" wire $0\wr_pick_dly$1285[0:0]$2285 - attribute \src "libresoc.v:41476.7-41476.32" + attribute \src "libresoc.v:41478.7-41478.32" wire $0\wr_pick_dly$1285[0:0]$2967 - attribute \src "libresoc.v:46843.3-46851.6" + attribute \src "libresoc.v:46845.3-46853.6" wire $0\wr_pick_dly$1305$next[0:0]$2758 - attribute \src "libresoc.v:42578.3-42579.51" + attribute \src "libresoc.v:42580.3-42581.51" wire $0\wr_pick_dly$1305[0:0]$2283 - attribute \src "libresoc.v:41480.7-41480.32" + attribute \src "libresoc.v:41482.7-41482.32" wire $0\wr_pick_dly$1305[0:0]$2969 - attribute \src "libresoc.v:46852.3-46860.6" + attribute \src "libresoc.v:46854.3-46862.6" wire $0\wr_pick_dly$1325$next[0:0]$2761 - attribute \src "libresoc.v:42576.3-42577.51" + attribute \src "libresoc.v:42578.3-42579.51" wire $0\wr_pick_dly$1325[0:0]$2281 - attribute \src "libresoc.v:41484.7-41484.32" + attribute \src "libresoc.v:41486.7-41486.32" wire $0\wr_pick_dly$1325[0:0]$2971 - attribute \src "libresoc.v:46890.3-46898.6" + attribute \src "libresoc.v:46892.3-46900.6" wire $0\wr_pick_dly$1345$next[0:0]$2765 - attribute \src "libresoc.v:42574.3-42575.51" + attribute \src "libresoc.v:42576.3-42577.51" wire $0\wr_pick_dly$1345[0:0]$2279 - attribute \src "libresoc.v:41488.7-41488.32" + attribute \src "libresoc.v:41490.7-41490.32" wire $0\wr_pick_dly$1345[0:0]$2973 - attribute \src "libresoc.v:46928.3-46936.6" + attribute \src "libresoc.v:46930.3-46938.6" wire $0\wr_pick_dly$1392$next[0:0]$2773 - attribute \src "libresoc.v:42572.3-42573.51" + attribute \src "libresoc.v:42574.3-42575.51" wire $0\wr_pick_dly$1392[0:0]$2277 - attribute \src "libresoc.v:41492.7-41492.32" + attribute \src "libresoc.v:41494.7-41494.32" wire $0\wr_pick_dly$1392[0:0]$2975 - attribute \src "libresoc.v:46966.3-46974.6" + attribute \src "libresoc.v:46968.3-46976.6" wire $0\wr_pick_dly$1408$next[0:0]$2781 - attribute \src "libresoc.v:42570.3-42571.51" + attribute \src "libresoc.v:42572.3-42573.51" wire $0\wr_pick_dly$1408[0:0]$2275 - attribute \src "libresoc.v:41496.7-41496.32" + attribute \src "libresoc.v:41498.7-41498.32" wire $0\wr_pick_dly$1408[0:0]$2977 - attribute \src "libresoc.v:46975.3-46983.6" + attribute \src "libresoc.v:46977.3-46985.6" wire $0\wr_pick_dly$1424$next[0:0]$2784 - attribute \src "libresoc.v:42568.3-42569.51" + attribute \src "libresoc.v:42570.3-42571.51" wire $0\wr_pick_dly$1424[0:0]$2273 - attribute \src "libresoc.v:41500.7-41500.32" + attribute \src "libresoc.v:41502.7-41502.32" wire $0\wr_pick_dly$1424[0:0]$2979 - attribute \src "libresoc.v:47013.3-47021.6" + attribute \src "libresoc.v:47015.3-47023.6" wire $0\wr_pick_dly$1458$next[0:0]$2788 - attribute \src "libresoc.v:42566.3-42567.51" + attribute \src "libresoc.v:42568.3-42569.51" wire $0\wr_pick_dly$1458[0:0]$2271 - attribute \src "libresoc.v:41504.7-41504.32" + attribute \src "libresoc.v:41506.7-41506.32" wire $0\wr_pick_dly$1458[0:0]$2981 - attribute \src "libresoc.v:47051.3-47059.6" + attribute \src "libresoc.v:47053.3-47061.6" wire $0\wr_pick_dly$1474$next[0:0]$2792 - attribute \src "libresoc.v:42564.3-42565.51" + attribute \src "libresoc.v:42566.3-42567.51" wire $0\wr_pick_dly$1474[0:0]$2269 - attribute \src "libresoc.v:41508.7-41508.32" + attribute \src "libresoc.v:41510.7-41510.32" wire $0\wr_pick_dly$1474[0:0]$2983 - attribute \src "libresoc.v:47060.3-47068.6" + attribute \src "libresoc.v:47062.3-47070.6" wire $0\wr_pick_dly$1490$next[0:0]$2795 - attribute \src "libresoc.v:42562.3-42563.51" + attribute \src "libresoc.v:42564.3-42565.51" wire $0\wr_pick_dly$1490[0:0]$2267 - attribute \src "libresoc.v:41512.7-41512.32" + attribute \src "libresoc.v:41514.7-41514.32" wire $0\wr_pick_dly$1490[0:0]$2985 - attribute \src "libresoc.v:47098.3-47106.6" + attribute \src "libresoc.v:47100.3-47108.6" wire $0\wr_pick_dly$1506$next[0:0]$2799 - attribute \src "libresoc.v:42560.3-42561.51" + attribute \src "libresoc.v:42562.3-42563.51" wire $0\wr_pick_dly$1506[0:0]$2265 - attribute \src "libresoc.v:41516.7-41516.32" + attribute \src "libresoc.v:41518.7-41518.32" wire $0\wr_pick_dly$1506[0:0]$2987 - attribute \src "libresoc.v:47136.3-47144.6" + attribute \src "libresoc.v:47138.3-47146.6" wire $0\wr_pick_dly$1542$next[0:0]$2803 - attribute \src "libresoc.v:42558.3-42559.51" + attribute \src "libresoc.v:42560.3-42561.51" wire $0\wr_pick_dly$1542[0:0]$2263 - attribute \src "libresoc.v:41520.7-41520.32" + attribute \src "libresoc.v:41522.7-41522.32" wire $0\wr_pick_dly$1542[0:0]$2989 - attribute \src "libresoc.v:47145.3-47153.6" + attribute \src "libresoc.v:47147.3-47155.6" wire $0\wr_pick_dly$1558$next[0:0]$2806 - attribute \src "libresoc.v:42556.3-42557.51" + attribute \src "libresoc.v:42558.3-42559.51" wire $0\wr_pick_dly$1558[0:0]$2261 - attribute \src "libresoc.v:41524.7-41524.32" + attribute \src "libresoc.v:41526.7-41526.32" wire $0\wr_pick_dly$1558[0:0]$2991 - attribute \src "libresoc.v:47184.3-47192.6" + attribute \src "libresoc.v:47186.3-47194.6" wire $0\wr_pick_dly$1574$next[0:0]$2810 - attribute \src "libresoc.v:42554.3-42555.51" + attribute \src "libresoc.v:42556.3-42557.51" wire $0\wr_pick_dly$1574[0:0]$2259 - attribute \src "libresoc.v:41528.7-41528.32" + attribute \src "libresoc.v:41530.7-41530.32" wire $0\wr_pick_dly$1574[0:0]$2993 - attribute \src "libresoc.v:47193.3-47201.6" + attribute \src "libresoc.v:47195.3-47203.6" wire $0\wr_pick_dly$1590$next[0:0]$2813 - attribute \src "libresoc.v:42552.3-42553.51" + attribute \src "libresoc.v:42554.3-42555.51" wire $0\wr_pick_dly$1590[0:0]$2257 - attribute \src "libresoc.v:41532.7-41532.32" + attribute \src "libresoc.v:41534.7-41534.32" wire $0\wr_pick_dly$1590[0:0]$2995 - attribute \src "libresoc.v:47202.3-47210.6" + attribute \src "libresoc.v:47204.3-47212.6" wire $0\wr_pick_dly$1632$next[0:0]$2816 - attribute \src "libresoc.v:42550.3-42551.51" + attribute \src "libresoc.v:42552.3-42553.51" wire $0\wr_pick_dly$1632[0:0]$2255 - attribute \src "libresoc.v:41536.7-41536.32" + attribute \src "libresoc.v:41538.7-41538.32" wire $0\wr_pick_dly$1632[0:0]$2997 - attribute \src "libresoc.v:47240.3-47248.6" + attribute \src "libresoc.v:47242.3-47250.6" wire $0\wr_pick_dly$1651$next[0:0]$2820 - attribute \src "libresoc.v:42548.3-42549.51" + attribute \src "libresoc.v:42550.3-42551.51" wire $0\wr_pick_dly$1651[0:0]$2253 - attribute \src "libresoc.v:41540.7-41540.32" + attribute \src "libresoc.v:41542.7-41542.32" wire $0\wr_pick_dly$1651[0:0]$2999 - attribute \src "libresoc.v:47278.3-47286.6" + attribute \src "libresoc.v:47280.3-47288.6" wire $0\wr_pick_dly$1667$next[0:0]$2824 - attribute \src "libresoc.v:42546.3-42547.51" + attribute \src "libresoc.v:42548.3-42549.51" wire $0\wr_pick_dly$1667[0:0]$2251 - attribute \src "libresoc.v:41544.7-41544.32" + attribute \src "libresoc.v:41546.7-41546.32" wire $0\wr_pick_dly$1667[0:0]$3001 - attribute \src "libresoc.v:47287.3-47295.6" + attribute \src "libresoc.v:47289.3-47297.6" wire $0\wr_pick_dly$1683$next[0:0]$2827 - attribute \src "libresoc.v:42544.3-42545.51" + attribute \src "libresoc.v:42546.3-42547.51" wire $0\wr_pick_dly$1683[0:0]$2249 - attribute \src "libresoc.v:41548.7-41548.32" + attribute \src "libresoc.v:41550.7-41550.32" wire $0\wr_pick_dly$1683[0:0]$3003 - attribute \src "libresoc.v:47325.3-47333.6" + attribute \src "libresoc.v:47327.3-47335.6" wire $0\wr_pick_dly$1699$next[0:0]$2835 - attribute \src "libresoc.v:42542.3-42543.51" + attribute \src "libresoc.v:42544.3-42545.51" wire $0\wr_pick_dly$1699[0:0]$2247 - attribute \src "libresoc.v:41552.7-41552.32" + attribute \src "libresoc.v:41554.7-41554.32" wire $0\wr_pick_dly$1699[0:0]$3005 - attribute \src "libresoc.v:47363.3-47371.6" + attribute \src "libresoc.v:47365.3-47373.6" wire $0\wr_pick_dly$1743$next[0:0]$2843 - attribute \src "libresoc.v:42540.3-42541.51" + attribute \src "libresoc.v:42542.3-42543.51" wire $0\wr_pick_dly$1743[0:0]$2245 - attribute \src "libresoc.v:41556.7-41556.32" + attribute \src "libresoc.v:41558.7-41558.32" wire $0\wr_pick_dly$1743[0:0]$3007 - attribute \src "libresoc.v:47401.3-47409.6" + attribute \src "libresoc.v:47403.3-47411.6" wire $0\wr_pick_dly$1759$next[0:0]$2847 - attribute \src "libresoc.v:42538.3-42539.51" + attribute \src "libresoc.v:42540.3-42541.51" wire $0\wr_pick_dly$1759[0:0]$2243 - attribute \src "libresoc.v:41560.7-41560.32" + attribute \src "libresoc.v:41562.7-41562.32" wire $0\wr_pick_dly$1759[0:0]$3009 - attribute \src "libresoc.v:47410.3-47418.6" + attribute \src "libresoc.v:47412.3-47420.6" wire $0\wr_pick_dly$1783$next[0:0]$2850 - attribute \src "libresoc.v:42536.3-42537.51" + attribute \src "libresoc.v:42538.3-42539.51" wire $0\wr_pick_dly$1783[0:0]$2241 - attribute \src "libresoc.v:41564.7-41564.32" + attribute \src "libresoc.v:41566.7-41566.32" wire $0\wr_pick_dly$1783[0:0]$3011 - attribute \src "libresoc.v:47448.3-47456.6" + attribute \src "libresoc.v:47450.3-47458.6" wire $0\wr_pick_dly$1803$next[0:0]$2854 - attribute \src "libresoc.v:42534.3-42535.51" + attribute \src "libresoc.v:42536.3-42537.51" wire $0\wr_pick_dly$1803[0:0]$2239 - attribute \src "libresoc.v:41568.7-41568.32" + attribute \src "libresoc.v:41570.7-41570.32" wire $0\wr_pick_dly$1803[0:0]$3013 - attribute \src "libresoc.v:46465.3-46473.6" + attribute \src "libresoc.v:46467.3-46475.6" wire $0\wr_pick_dly$986$next[0:0]$2710 - attribute \src "libresoc.v:42604.3-42605.49" + attribute \src "libresoc.v:42606.3-42607.49" wire $0\wr_pick_dly$986[0:0]$2309 - attribute \src "libresoc.v:41572.7-41572.31" + attribute \src "libresoc.v:41574.7-41574.31" wire $0\wr_pick_dly$986[0:0]$3015 - attribute \src "libresoc.v:46427.3-46435.6" + attribute \src "libresoc.v:46429.3-46437.6" wire $0\wr_pick_dly$next[0:0]$2706 - attribute \src "libresoc.v:42606.3-42607.39" + attribute \src "libresoc.v:42608.3-42609.39" wire $0\wr_pick_dly[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $10\corebusy_o[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $11\corebusy_o[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $12\corebusy_o[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $13\corebusy_o[0:0] - attribute \src "libresoc.v:45800.3-45820.6" + attribute \src "libresoc.v:45802.3-45822.6" wire $1\core_terminate_o$next[0:0]$2589 - attribute \src "libresoc.v:38027.7-38027.30" + attribute \src "libresoc.v:38029.7-38029.30" wire $1\core_terminate_o[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $1\corebusy_o[0:0] - attribute \src "libresoc.v:45625.3-45651.6" + attribute \src "libresoc.v:45627.3-45653.6" wire width 2 $1\counter$next[1:0]$2566 - attribute \src "libresoc.v:38040.13-38040.27" + attribute \src "libresoc.v:38042.13-38042.27" wire width 2 $1\counter[1:0] - attribute \src "libresoc.v:46110.3-46118.6" + attribute \src "libresoc.v:46112.3-46120.6" wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 - attribute \src "libresoc.v:39181.7-39181.34" + attribute \src "libresoc.v:39183.7-39183.34" wire $1\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:46091.3-46099.6" + attribute \src "libresoc.v:46093.3-46101.6" wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 - attribute \src "libresoc.v:39185.7-39185.30" + attribute \src "libresoc.v:39187.7-39187.30" wire $1\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46129.3-46137.6" + attribute \src "libresoc.v:46131.3-46139.6" wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 - attribute \src "libresoc.v:39189.7-39189.30" + attribute \src "libresoc.v:39191.7-39191.30" wire $1\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46178.3-46186.6" + attribute \src "libresoc.v:46180.3-46188.6" wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 - attribute \src "libresoc.v:39193.7-39193.30" + attribute \src "libresoc.v:39195.7-39195.30" wire $1\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:46042.3-46050.6" + attribute \src "libresoc.v:46044.3-46052.6" wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 - attribute \src "libresoc.v:39197.7-39197.33" + attribute \src "libresoc.v:39199.7-39199.33" wire $1\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46197.3-46205.6" + attribute \src "libresoc.v:46199.3-46207.6" wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 - attribute \src "libresoc.v:39201.7-39201.37" + attribute \src "libresoc.v:39203.7-39203.37" wire $1\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46264.3-46272.6" + attribute \src "libresoc.v:46266.3-46274.6" wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 - attribute \src "libresoc.v:39205.7-39205.34" + attribute \src "libresoc.v:39207.7-39207.34" wire $1\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46216.3-46224.6" + attribute \src "libresoc.v:46218.3-46226.6" wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 - attribute \src "libresoc.v:39209.7-39209.35" + attribute \src "libresoc.v:39211.7-39211.35" wire $1\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46312.3-46320.6" + attribute \src "libresoc.v:46314.3-46322.6" wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 - attribute \src "libresoc.v:39213.7-39213.37" + attribute \src "libresoc.v:39215.7-39215.37" wire $1\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46331.3-46339.6" + attribute \src "libresoc.v:46333.3-46341.6" wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 - attribute \src "libresoc.v:39217.7-39217.35" + attribute \src "libresoc.v:39219.7-39219.35" wire $1\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:45264.3-45272.6" + attribute \src "libresoc.v:45266.3-45274.6" wire $1\dp_INT_ra_alu0_0$next[0:0]$2458 - attribute \src "libresoc.v:39221.7-39221.30" + attribute \src "libresoc.v:39223.7-39223.30" wire $1\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45283.3-45291.6" + attribute \src "libresoc.v:45285.3-45293.6" wire $1\dp_INT_ra_cr0_1$next[0:0]$2462 - attribute \src "libresoc.v:39225.7-39225.29" + attribute \src "libresoc.v:39227.7-39227.29" wire $1\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45359.3-45367.6" + attribute \src "libresoc.v:45361.3-45369.6" wire $1\dp_INT_ra_div0_5$next[0:0]$2486 - attribute \src "libresoc.v:39229.7-39229.30" + attribute \src "libresoc.v:39231.7-39231.30" wire $1\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45416.3-45424.6" + attribute \src "libresoc.v:45418.3-45426.6" wire $1\dp_INT_ra_ldst0_8$next[0:0]$2504 - attribute \src "libresoc.v:39233.7-39233.31" + attribute \src "libresoc.v:39235.7-39235.31" wire $1\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45321.3-45329.6" + attribute \src "libresoc.v:45323.3-45331.6" wire $1\dp_INT_ra_logical0_3$next[0:0]$2474 - attribute \src "libresoc.v:39237.7-39237.34" + attribute \src "libresoc.v:39239.7-39239.34" wire $1\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45378.3-45386.6" + attribute \src "libresoc.v:45380.3-45388.6" wire $1\dp_INT_ra_mul0_6$next[0:0]$2492 - attribute \src "libresoc.v:39241.7-39241.30" + attribute \src "libresoc.v:39243.7-39243.30" wire $1\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45397.3-45405.6" + attribute \src "libresoc.v:45399.3-45407.6" wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 - attribute \src "libresoc.v:39245.7-39245.35" + attribute \src "libresoc.v:39247.7-39247.35" wire $1\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45340.3-45348.6" + attribute \src "libresoc.v:45342.3-45350.6" wire $1\dp_INT_ra_spr0_4$next[0:0]$2480 - attribute \src "libresoc.v:39249.7-39249.30" + attribute \src "libresoc.v:39251.7-39251.30" wire $1\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45302.3-45310.6" + attribute \src "libresoc.v:45304.3-45312.6" wire $1\dp_INT_ra_trap0_2$next[0:0]$2468 - attribute \src "libresoc.v:39253.7-39253.31" + attribute \src "libresoc.v:39255.7-39255.31" wire $1\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45435.3-45443.6" + attribute \src "libresoc.v:45437.3-45445.6" wire $1\dp_INT_rb_alu0_0$next[0:0]$2510 - attribute \src "libresoc.v:39257.7-39257.30" + attribute \src "libresoc.v:39259.7-39259.30" wire $1\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:45454.3-45462.6" + attribute \src "libresoc.v:45456.3-45464.6" wire $1\dp_INT_rb_cr0_1$next[0:0]$2514 - attribute \src "libresoc.v:39261.7-39261.29" + attribute \src "libresoc.v:39263.7-39263.29" wire $1\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:45511.3-45519.6" + attribute \src "libresoc.v:45513.3-45521.6" wire $1\dp_INT_rb_div0_4$next[0:0]$2532 - attribute \src "libresoc.v:39265.7-39265.30" + attribute \src "libresoc.v:39267.7-39267.30" wire $1\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:45568.3-45576.6" + attribute \src "libresoc.v:45570.3-45578.6" wire $1\dp_INT_rb_ldst0_7$next[0:0]$2550 - attribute \src "libresoc.v:39269.7-39269.31" + attribute \src "libresoc.v:39271.7-39271.31" wire $1\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:45492.3-45500.6" + attribute \src "libresoc.v:45494.3-45502.6" wire $1\dp_INT_rb_logical0_3$next[0:0]$2526 - attribute \src "libresoc.v:39273.7-39273.34" + attribute \src "libresoc.v:39275.7-39275.34" wire $1\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:45530.3-45538.6" + attribute \src "libresoc.v:45532.3-45540.6" wire $1\dp_INT_rb_mul0_5$next[0:0]$2538 - attribute \src "libresoc.v:39277.7-39277.30" + attribute \src "libresoc.v:39279.7-39279.30" wire $1\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:45549.3-45557.6" + attribute \src "libresoc.v:45551.3-45559.6" wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 - attribute \src "libresoc.v:39281.7-39281.35" + attribute \src "libresoc.v:39283.7-39283.35" wire $1\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:45473.3-45481.6" + attribute \src "libresoc.v:45475.3-45483.6" wire $1\dp_INT_rb_trap0_2$next[0:0]$2520 - attribute \src "libresoc.v:39285.7-39285.31" + attribute \src "libresoc.v:39287.7-39287.31" wire $1\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:45606.3-45614.6" + attribute \src "libresoc.v:45608.3-45616.6" wire $1\dp_INT_rc_ldst0_1$next[0:0]$2560 - attribute \src "libresoc.v:39289.7-39289.31" + attribute \src "libresoc.v:39291.7-39291.31" wire $1\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:45587.3-45595.6" + attribute \src "libresoc.v:45589.3-45597.6" wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 - attribute \src "libresoc.v:39293.7-39293.35" + attribute \src "libresoc.v:39295.7-39295.35" wire $1\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46379.3-46387.6" + attribute \src "libresoc.v:46381.3-46389.6" wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 - attribute \src "libresoc.v:39297.7-39297.32" + attribute \src "libresoc.v:39299.7-39299.32" wire $1\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:45907.3-45915.6" + attribute \src "libresoc.v:45909.3-45917.6" wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 - attribute \src "libresoc.v:39301.7-39301.34" + attribute \src "libresoc.v:39303.7-39303.34" wire $1\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:45974.3-45982.6" + attribute \src "libresoc.v:45976.3-45984.6" wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 - attribute \src "libresoc.v:39305.7-39305.39" + attribute \src "libresoc.v:39307.7-39307.39" wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:45955.3-45963.6" + attribute \src "libresoc.v:45957.3-45965.6" wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 - attribute \src "libresoc.v:39309.7-39309.34" + attribute \src "libresoc.v:39311.7-39311.34" wire $1\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:46023.3-46031.6" + attribute \src "libresoc.v:46025.3-46033.6" wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 - attribute \src "libresoc.v:39313.7-39313.34" + attribute \src "libresoc.v:39315.7-39315.34" wire $1\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:45652.3-45660.6" + attribute \src "libresoc.v:45654.3-45662.6" wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 - attribute \src "libresoc.v:39317.7-39317.34" + attribute \src "libresoc.v:39319.7-39319.34" wire $1\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:45821.3-45829.6" + attribute \src "libresoc.v:45823.3-45831.6" wire $1\dp_XER_xer_so_div0_3$next[0:0]$2594 - attribute \src "libresoc.v:39321.7-39321.34" + attribute \src "libresoc.v:39323.7-39323.34" wire $1\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:45762.3-45770.6" + attribute \src "libresoc.v:45764.3-45772.6" wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 - attribute \src "libresoc.v:39325.7-39325.38" + attribute \src "libresoc.v:39327.7-39327.38" wire $1\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:45840.3-45848.6" + attribute \src "libresoc.v:45842.3-45850.6" wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 - attribute \src "libresoc.v:39329.7-39329.34" + attribute \src "libresoc.v:39331.7-39331.34" wire $1\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:45888.3-45896.6" + attribute \src "libresoc.v:45890.3-45898.6" wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 - attribute \src "libresoc.v:39333.7-39333.39" + attribute \src "libresoc.v:39335.7-39335.39" wire $1\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:45781.3-45789.6" + attribute \src "libresoc.v:45783.3-45791.6" wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 - attribute \src "libresoc.v:39337.7-39337.34" + attribute \src "libresoc.v:39339.7-39339.34" wire $1\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:46899.3-46927.6" + attribute \src "libresoc.v:46901.3-46929.6" wire $1\fus_cu_issue_i$13[0:0]$2769 - attribute \src "libresoc.v:47296.3-47324.6" + attribute \src "libresoc.v:47298.3-47326.6" wire $1\fus_cu_issue_i$16[0:0]$2831 - attribute \src "libresoc.v:47660.3-47688.6" + attribute \src "libresoc.v:47662.3-47690.6" wire $1\fus_cu_issue_i$19[0:0]$2865 - attribute \src "libresoc.v:48156.3-48184.6" + attribute \src "libresoc.v:48158.3-48186.6" wire $1\fus_cu_issue_i$22[0:0]$2890 - attribute \src "libresoc.v:43483.3-43511.6" + attribute \src "libresoc.v:43485.3-43513.6" wire $1\fus_cu_issue_i$25[0:0]$2357 - attribute \src "libresoc.v:43979.3-44007.6" + attribute \src "libresoc.v:43981.3-44009.6" wire $1\fus_cu_issue_i$28[0:0]$2382 - attribute \src "libresoc.v:44301.3-44329.6" + attribute \src "libresoc.v:44303.3-44331.6" wire $1\fus_cu_issue_i$31[0:0]$2401 - attribute \src "libresoc.v:44768.3-44796.6" + attribute \src "libresoc.v:44770.3-44798.6" wire $1\fus_cu_issue_i$34[0:0]$2425 - attribute \src "libresoc.v:45206.3-45234.6" + attribute \src "libresoc.v:45208.3-45236.6" wire $1\fus_cu_issue_i$37[0:0]$2448 - attribute \src "libresoc.v:46691.3-46719.6" + attribute \src "libresoc.v:46693.3-46721.6" wire $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46937.3-46965.6" + attribute \src "libresoc.v:46939.3-46967.6" wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2777 - attribute \src "libresoc.v:47334.3-47362.6" + attribute \src "libresoc.v:47336.3-47364.6" wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2839 - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47691.3-47719.6" wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2870 - attribute \src "libresoc.v:48185.3-48213.6" + attribute \src "libresoc.v:48187.3-48215.6" wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2895 - attribute \src "libresoc.v:43512.3-43540.6" + attribute \src "libresoc.v:43514.3-43542.6" wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2362 - attribute \src "libresoc.v:44008.3-44036.6" + attribute \src "libresoc.v:44010.3-44038.6" wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2387 - attribute \src "libresoc.v:44330.3-44358.6" + attribute \src "libresoc.v:44332.3-44360.6" wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2406 - attribute \src "libresoc.v:44797.3-44825.6" + attribute \src "libresoc.v:44799.3-44827.6" wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2430 - attribute \src "libresoc.v:45235.3-45263.6" + attribute \src "libresoc.v:45237.3-45265.6" wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2453 - attribute \src "libresoc.v:46729.3-46757.6" + attribute \src "libresoc.v:46731.3-46759.6" wire width 4 $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46606.3-46634.6" + attribute \src "libresoc.v:46608.3-46636.6" wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45916.3-45944.6" + attribute \src "libresoc.v:45918.3-45946.6" wire width 13 $1\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "libresoc.v:45983.3-46012.6" + attribute \src "libresoc.v:45985.3-46014.6" wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45983.3-46012.6" + attribute \src "libresoc.v:45985.3-46014.6" wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46436.3-46464.6" + attribute \src "libresoc.v:46438.3-46466.6" wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46653.3-46681.6" + attribute \src "libresoc.v:46655.3-46683.6" wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45859.3-45887.6" + attribute \src "libresoc.v:45861.3-45889.6" wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46235.3-46263.6" + attribute \src "libresoc.v:46237.3-46265.6" wire $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46350.3-46378.6" + attribute \src "libresoc.v:46352.3-46380.6" wire $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46521.3-46549.6" + attribute \src "libresoc.v:46523.3-46551.6" wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46568.3-46596.6" + attribute \src "libresoc.v:46570.3-46598.6" wire $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46148.3-46177.6" + attribute \src "libresoc.v:46150.3-46179.6" wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46148.3-46177.6" + attribute \src "libresoc.v:46150.3-46179.6" wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46483.3-46511.6" + attribute \src "libresoc.v:46485.3-46513.6" wire $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46061.3-46090.6" + attribute \src "libresoc.v:46063.3-46092.6" wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46061.3-46090.6" + attribute \src "libresoc.v:46063.3-46092.6" wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46398.3-46426.6" + attribute \src "libresoc.v:46400.3-46428.6" wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46283.3-46311.6" + attribute \src "libresoc.v:46285.3-46313.6" wire $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46984.3-47012.6" + attribute \src "libresoc.v:46986.3-47014.6" wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47069.3-47097.6" + attribute \src "libresoc.v:47071.3-47099.6" wire width 13 $1\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "libresoc.v:47154.3-47183.6" + attribute \src "libresoc.v:47156.3-47185.6" wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47154.3-47183.6" + attribute \src "libresoc.v:47156.3-47185.6" wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47107.3-47135.6" + attribute \src "libresoc.v:47109.3-47137.6" wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47022.3-47050.6" + attribute \src "libresoc.v:47024.3-47052.6" wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47249.3-47277.6" + attribute \src "libresoc.v:47251.3-47279.6" wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47211.3-47239.6" + attribute \src "libresoc.v:47213.3-47241.6" wire $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46814.3-46842.6" + attribute \src "libresoc.v:46816.3-46844.6" wire width 13 $1\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "libresoc.v:46861.3-46889.6" + attribute \src "libresoc.v:46863.3-46891.6" wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46767.3-46795.6" + attribute \src "libresoc.v:46769.3-46797.6" wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43921.3-43949.6" + attribute \src "libresoc.v:43923.3-43951.6" wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43570.3-43598.6" + attribute \src "libresoc.v:43572.3-43600.6" wire width 13 $1\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "libresoc.v:43599.3-43628.6" + attribute \src "libresoc.v:43601.3-43630.6" wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43599.3-43628.6" + attribute \src "libresoc.v:43601.3-43630.6" wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43747.3-43775.6" + attribute \src "libresoc.v:43749.3-43777.6" wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43950.3-43978.6" + attribute \src "libresoc.v:43952.3-43980.6" wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43541.3-43569.6" + attribute \src "libresoc.v:43543.3-43571.6" wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43689.3-43717.6" + attribute \src "libresoc.v:43691.3-43719.6" wire $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43776.3-43804.6" + attribute \src "libresoc.v:43778.3-43806.6" wire $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43863.3-43891.6" + attribute \src "libresoc.v:43865.3-43893.6" wire $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43892.3-43920.6" + attribute \src "libresoc.v:43894.3-43922.6" wire $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43659.3-43688.6" + attribute \src "libresoc.v:43661.3-43690.6" wire $1\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43659.3-43688.6" + attribute \src "libresoc.v:43661.3-43690.6" wire $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43834.3-43862.6" + attribute \src "libresoc.v:43836.3-43864.6" wire $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43629.3-43658.6" + attribute \src "libresoc.v:43631.3-43660.6" wire $1\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43629.3-43658.6" + attribute \src "libresoc.v:43631.3-43660.6" wire $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43805.3-43833.6" + attribute \src "libresoc.v:43807.3-43835.6" wire $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43718.3-43746.6" + attribute \src "libresoc.v:43720.3-43748.6" wire $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:48098.3-48126.6" + attribute \src "libresoc.v:48100.3-48128.6" wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47747.3-47775.6" + attribute \src "libresoc.v:47749.3-47777.6" wire width 13 $1\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "libresoc.v:47776.3-47805.6" + attribute \src "libresoc.v:47778.3-47807.6" wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47776.3-47805.6" + attribute \src "libresoc.v:47778.3-47807.6" wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47924.3-47952.6" + attribute \src "libresoc.v:47926.3-47954.6" wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48127.3-48155.6" + attribute \src "libresoc.v:48129.3-48157.6" wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47718.3-47746.6" + attribute \src "libresoc.v:47720.3-47748.6" wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47866.3-47894.6" + attribute \src "libresoc.v:47868.3-47896.6" wire $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47953.3-47981.6" + attribute \src "libresoc.v:47955.3-47983.6" wire $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48040.3-48068.6" + attribute \src "libresoc.v:48042.3-48070.6" wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:48069.3-48097.6" + attribute \src "libresoc.v:48071.3-48099.6" wire $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47836.3-47865.6" + attribute \src "libresoc.v:47838.3-47867.6" wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47836.3-47865.6" + attribute \src "libresoc.v:47838.3-47867.6" wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48011.3-48039.6" + attribute \src "libresoc.v:48013.3-48041.6" wire $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47806.3-47835.6" + attribute \src "libresoc.v:47808.3-47837.6" wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47806.3-47835.6" + attribute \src "libresoc.v:47808.3-47837.6" wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47982.3-48010.6" + attribute \src "libresoc.v:47984.3-48012.6" wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47895.3-47923.6" + attribute \src "libresoc.v:47897.3-47925.6" wire $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44066.3-44094.6" + attribute \src "libresoc.v:44068.3-44096.6" wire width 13 $1\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "libresoc.v:44095.3-44124.6" + attribute \src "libresoc.v:44097.3-44126.6" wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44095.3-44124.6" + attribute \src "libresoc.v:44097.3-44126.6" wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44272.3-44300.6" + attribute \src "libresoc.v:44274.3-44302.6" wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44037.3-44065.6" + attribute \src "libresoc.v:44039.3-44067.6" wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44214.3-44242.6" + attribute \src "libresoc.v:44216.3-44244.6" wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44243.3-44271.6" + attribute \src "libresoc.v:44245.3-44273.6" wire $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44155.3-44184.6" + attribute \src "libresoc.v:44157.3-44186.6" wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44155.3-44184.6" + attribute \src "libresoc.v:44157.3-44186.6" wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44125.3-44154.6" + attribute \src "libresoc.v:44127.3-44156.6" wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44125.3-44154.6" + attribute \src "libresoc.v:44127.3-44156.6" wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44185.3-44213.6" + attribute \src "libresoc.v:44187.3-44215.6" wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44388.3-44416.6" + attribute \src "libresoc.v:44390.3-44418.6" wire width 13 $1\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "libresoc.v:44417.3-44446.6" + attribute \src "libresoc.v:44419.3-44448.6" wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44417.3-44446.6" + attribute \src "libresoc.v:44419.3-44448.6" wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44565.3-44593.6" + attribute \src "libresoc.v:44567.3-44595.6" wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44623.3-44651.6" + attribute \src "libresoc.v:44625.3-44653.6" wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44739.3-44767.6" + attribute \src "libresoc.v:44741.3-44769.6" wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44359.3-44387.6" + attribute \src "libresoc.v:44361.3-44389.6" wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44536.3-44564.6" + attribute \src "libresoc.v:44538.3-44566.6" wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44681.3-44709.6" + attribute \src "libresoc.v:44683.3-44711.6" wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44710.3-44738.6" + attribute \src "libresoc.v:44712.3-44740.6" wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44477.3-44506.6" + attribute \src "libresoc.v:44479.3-44508.6" wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44477.3-44506.6" + attribute \src "libresoc.v:44479.3-44508.6" wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44594.3-44622.6" + attribute \src "libresoc.v:44596.3-44624.6" wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44652.3-44680.6" + attribute \src "libresoc.v:44654.3-44682.6" wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44447.3-44476.6" + attribute \src "libresoc.v:44449.3-44478.6" wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44447.3-44476.6" + attribute \src "libresoc.v:44449.3-44478.6" wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44507.3-44535.6" + attribute \src "libresoc.v:44509.3-44537.6" wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48243.3-48271.6" + attribute \src "libresoc.v:48245.3-48273.6" wire width 13 $1\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "libresoc.v:43425.3-43453.6" + attribute \src "libresoc.v:43427.3-43455.6" wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48214.3-48242.6" + attribute \src "libresoc.v:48216.3-48244.6" wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43454.3-43482.6" + attribute \src "libresoc.v:43456.3-43484.6" wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47515.3-47543.6" + attribute \src "libresoc.v:47517.3-47545.6" wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47419.3-47447.6" + attribute \src "libresoc.v:47421.3-47449.6" wire width 13 $1\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "libresoc.v:47457.3-47485.6" + attribute \src "libresoc.v:47459.3-47487.6" wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47372.3-47400.6" + attribute \src "libresoc.v:47374.3-47402.6" wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47544.3-47572.6" + attribute \src "libresoc.v:47546.3-47574.6" wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47631.3-47659.6" + attribute \src "libresoc.v:47633.3-47661.6" wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47486.3-47514.6" + attribute \src "libresoc.v:47488.3-47516.6" wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47602.3-47630.6" + attribute \src "libresoc.v:47604.3-47632.6" wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47573.3-47601.6" + attribute \src "libresoc.v:47575.3-47603.6" wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45090.3-45118.6" + attribute \src "libresoc.v:45092.3-45120.6" wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45061.3-45089.6" + attribute \src "libresoc.v:45063.3-45091.6" wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44855.3-44883.6" + attribute \src "libresoc.v:44857.3-44885.6" wire width 13 $1\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "libresoc.v:44884.3-44913.6" + attribute \src "libresoc.v:44886.3-44915.6" wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44884.3-44913.6" + attribute \src "libresoc.v:44886.3-44915.6" wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45177.3-45205.6" + attribute \src "libresoc.v:45179.3-45207.6" wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44826.3-44854.6" + attribute \src "libresoc.v:44828.3-44856.6" wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45003.3-45031.6" + attribute \src "libresoc.v:45005.3-45033.6" wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45032.3-45060.6" + attribute \src "libresoc.v:45034.3-45062.6" wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45148.3-45176.6" + attribute \src "libresoc.v:45150.3-45178.6" wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44973.3-45002.6" + attribute \src "libresoc.v:44975.3-45004.6" wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44973.3-45002.6" + attribute \src "libresoc.v:44975.3-45004.6" wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44943.3-44972.6" + attribute \src "libresoc.v:44945.3-44974.6" wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44943.3-44972.6" + attribute \src "libresoc.v:44945.3-44974.6" wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45119.3-45147.6" + attribute \src "libresoc.v:45121.3-45149.6" wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44914.3-44942.6" + attribute \src "libresoc.v:44916.3-44944.6" wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45292.3-45301.6" + attribute \src "libresoc.v:45294.3-45303.6" wire width 64 $1\fus_src1_i$42[63:0]$2465 - attribute \src "libresoc.v:45311.3-45320.6" + attribute \src "libresoc.v:45313.3-45322.6" wire width 64 $1\fus_src1_i$45[63:0]$2471 - attribute \src "libresoc.v:45330.3-45339.6" + attribute \src "libresoc.v:45332.3-45341.6" wire width 64 $1\fus_src1_i$48[63:0]$2477 - attribute \src "libresoc.v:45349.3-45358.6" + attribute \src "libresoc.v:45351.3-45360.6" wire width 64 $1\fus_src1_i$51[63:0]$2483 - attribute \src "libresoc.v:45368.3-45377.6" + attribute \src "libresoc.v:45370.3-45379.6" wire width 64 $1\fus_src1_i$54[63:0]$2489 - attribute \src "libresoc.v:45387.3-45396.6" + attribute \src "libresoc.v:45389.3-45398.6" wire width 64 $1\fus_src1_i$57[63:0]$2495 - attribute \src "libresoc.v:45406.3-45415.6" + attribute \src "libresoc.v:45408.3-45417.6" wire width 64 $1\fus_src1_i$60[63:0]$2501 - attribute \src "libresoc.v:45425.3-45434.6" + attribute \src "libresoc.v:45427.3-45436.6" wire width 64 $1\fus_src1_i$63[63:0]$2507 - attribute \src "libresoc.v:46206.3-46215.6" + attribute \src "libresoc.v:46208.3-46217.6" wire width 64 $1\fus_src1_i$86[63:0]$2670 - attribute \src "libresoc.v:45273.3-45282.6" + attribute \src "libresoc.v:45275.3-45284.6" wire width 64 $1\fus_src1_i[63:0] - attribute \src "libresoc.v:45463.3-45472.6" + attribute \src "libresoc.v:45465.3-45474.6" wire width 64 $1\fus_src2_i$64[63:0]$2517 - attribute \src "libresoc.v:45482.3-45491.6" + attribute \src "libresoc.v:45484.3-45493.6" wire width 64 $1\fus_src2_i$65[63:0]$2523 - attribute \src "libresoc.v:45501.3-45510.6" + attribute \src "libresoc.v:45503.3-45512.6" wire width 64 $1\fus_src2_i$66[63:0]$2529 - attribute \src "libresoc.v:45520.3-45529.6" + attribute \src "libresoc.v:45522.3-45531.6" wire width 64 $1\fus_src2_i$67[63:0]$2535 - attribute \src "libresoc.v:45539.3-45548.6" + attribute \src "libresoc.v:45541.3-45550.6" wire width 64 $1\fus_src2_i$68[63:0]$2541 - attribute \src "libresoc.v:45558.3-45567.6" + attribute \src "libresoc.v:45560.3-45569.6" wire width 64 $1\fus_src2_i$69[63:0]$2547 - attribute \src "libresoc.v:45577.3-45586.6" + attribute \src "libresoc.v:45579.3-45588.6" wire width 64 $1\fus_src2_i$70[63:0]$2553 - attribute \src "libresoc.v:46321.3-46330.6" + attribute \src "libresoc.v:46323.3-46332.6" wire width 64 $1\fus_src2_i$89[63:0]$2690 - attribute \src "libresoc.v:46388.3-46397.6" + attribute \src "libresoc.v:46390.3-46399.6" wire width 64 $1\fus_src2_i$91[63:0]$2703 - attribute \src "libresoc.v:45444.3-45453.6" + attribute \src "libresoc.v:45446.3-45455.6" wire width 64 $1\fus_src2_i[63:0] - attribute \src "libresoc.v:45615.3-45624.6" + attribute \src "libresoc.v:45617.3-45626.6" wire width 64 $1\fus_src3_i$71[63:0]$2563 - attribute \src "libresoc.v:45661.3-45670.6" + attribute \src "libresoc.v:45663.3-45672.6" wire $1\fus_src3_i$72[0:0]$2575 - attribute \src "libresoc.v:45771.3-45780.6" + attribute \src "libresoc.v:45773.3-45782.6" wire $1\fus_src3_i$73[0:0]$2582 - attribute \src "libresoc.v:45830.3-45839.6" + attribute \src "libresoc.v:45832.3-45841.6" wire $1\fus_src3_i$74[0:0]$2597 - attribute \src "libresoc.v:45849.3-45858.6" + attribute \src "libresoc.v:45851.3-45860.6" wire $1\fus_src3_i$75[0:0]$2603 - attribute \src "libresoc.v:46051.3-46060.6" + attribute \src "libresoc.v:46053.3-46062.6" wire width 32 $1\fus_src3_i$79[31:0]$2638 - attribute \src "libresoc.v:46119.3-46128.6" + attribute \src "libresoc.v:46121.3-46130.6" wire width 4 $1\fus_src3_i$83[3:0]$2651 - attribute \src "libresoc.v:46225.3-46234.6" + attribute \src "libresoc.v:46227.3-46236.6" wire width 64 $1\fus_src3_i$87[63:0]$2676 - attribute \src "libresoc.v:46273.3-46282.6" + attribute \src "libresoc.v:46275.3-46284.6" wire width 64 $1\fus_src3_i$88[63:0]$2683 - attribute \src "libresoc.v:45596.3-45605.6" + attribute \src "libresoc.v:45598.3-45607.6" wire width 64 $1\fus_src3_i[63:0] - attribute \src "libresoc.v:45897.3-45906.6" + attribute \src "libresoc.v:45899.3-45908.6" wire $1\fus_src4_i$76[0:0]$2610 - attribute \src "libresoc.v:45945.3-45954.6" + attribute \src "libresoc.v:45947.3-45956.6" wire width 2 $1\fus_src4_i$77[1:0]$2617 - attribute \src "libresoc.v:46100.3-46109.6" + attribute \src "libresoc.v:46102.3-46111.6" wire width 4 $1\fus_src4_i$80[3:0]$2645 - attribute \src "libresoc.v:46340.3-46349.6" + attribute \src "libresoc.v:46342.3-46351.6" wire width 64 $1\fus_src4_i$90[63:0]$2696 - attribute \src "libresoc.v:45790.3-45799.6" + attribute \src "libresoc.v:45792.3-45801.6" wire $1\fus_src4_i[0:0] - attribute \src "libresoc.v:46032.3-46041.6" + attribute \src "libresoc.v:46034.3-46043.6" wire width 2 $1\fus_src5_i$78[1:0]$2632 - attribute \src "libresoc.v:46138.3-46147.6" + attribute \src "libresoc.v:46140.3-46149.6" wire width 4 $1\fus_src5_i$84[3:0]$2657 - attribute \src "libresoc.v:46013.3-46022.6" + attribute \src "libresoc.v:46015.3-46024.6" wire width 2 $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46187.3-46196.6" + attribute \src "libresoc.v:46189.3-46198.6" wire width 4 $1\fus_src6_i$85[3:0]$2664 - attribute \src "libresoc.v:45964.3-45973.6" + attribute \src "libresoc.v:45966.3-45975.6" wire width 2 $1\fus_src6_i[1:0] - attribute \src "libresoc.v:46474.3-46482.6" + attribute \src "libresoc.v:46476.3-46484.6" wire $1\wr_pick_dly$1005$next[0:0]$2714 - attribute \src "libresoc.v:46512.3-46520.6" + attribute \src "libresoc.v:46514.3-46522.6" wire $1\wr_pick_dly$1026$next[0:0]$2718 - attribute \src "libresoc.v:46550.3-46558.6" + attribute \src "libresoc.v:46552.3-46560.6" wire $1\wr_pick_dly$1044$next[0:0]$2722 - attribute \src "libresoc.v:46559.3-46567.6" + attribute \src "libresoc.v:46561.3-46569.6" wire $1\wr_pick_dly$1066$next[0:0]$2725 - attribute \src "libresoc.v:46597.3-46605.6" + attribute \src "libresoc.v:46599.3-46607.6" wire $1\wr_pick_dly$1086$next[0:0]$2729 - attribute \src "libresoc.v:46635.3-46643.6" + attribute \src "libresoc.v:46637.3-46645.6" wire $1\wr_pick_dly$1106$next[0:0]$2733 - attribute \src "libresoc.v:46644.3-46652.6" + attribute \src "libresoc.v:46646.3-46654.6" wire $1\wr_pick_dly$1125$next[0:0]$2736 - attribute \src "libresoc.v:46682.3-46690.6" + attribute \src "libresoc.v:46684.3-46692.6" wire $1\wr_pick_dly$1143$next[0:0]$2740 - attribute \src "libresoc.v:46720.3-46728.6" + attribute \src "libresoc.v:46722.3-46730.6" wire $1\wr_pick_dly$1217$next[0:0]$2744 - attribute \src "libresoc.v:46758.3-46766.6" + attribute \src "libresoc.v:46760.3-46768.6" wire $1\wr_pick_dly$1245$next[0:0]$2748 - attribute \src "libresoc.v:46796.3-46804.6" + attribute \src "libresoc.v:46798.3-46806.6" wire $1\wr_pick_dly$1265$next[0:0]$2752 - attribute \src "libresoc.v:46805.3-46813.6" + attribute \src "libresoc.v:46807.3-46815.6" wire $1\wr_pick_dly$1285$next[0:0]$2755 - attribute \src "libresoc.v:46843.3-46851.6" + attribute \src "libresoc.v:46845.3-46853.6" wire $1\wr_pick_dly$1305$next[0:0]$2759 - attribute \src "libresoc.v:46852.3-46860.6" + attribute \src "libresoc.v:46854.3-46862.6" wire $1\wr_pick_dly$1325$next[0:0]$2762 - attribute \src "libresoc.v:46890.3-46898.6" + attribute \src "libresoc.v:46892.3-46900.6" wire $1\wr_pick_dly$1345$next[0:0]$2766 - attribute \src "libresoc.v:46928.3-46936.6" + attribute \src "libresoc.v:46930.3-46938.6" wire $1\wr_pick_dly$1392$next[0:0]$2774 - attribute \src "libresoc.v:46966.3-46974.6" + attribute \src "libresoc.v:46968.3-46976.6" wire $1\wr_pick_dly$1408$next[0:0]$2782 - attribute \src "libresoc.v:46975.3-46983.6" + attribute \src "libresoc.v:46977.3-46985.6" wire $1\wr_pick_dly$1424$next[0:0]$2785 - attribute \src "libresoc.v:47013.3-47021.6" + attribute \src "libresoc.v:47015.3-47023.6" wire $1\wr_pick_dly$1458$next[0:0]$2789 - attribute \src "libresoc.v:47051.3-47059.6" + attribute \src "libresoc.v:47053.3-47061.6" wire $1\wr_pick_dly$1474$next[0:0]$2793 - attribute \src "libresoc.v:47060.3-47068.6" + attribute \src "libresoc.v:47062.3-47070.6" wire $1\wr_pick_dly$1490$next[0:0]$2796 - attribute \src "libresoc.v:47098.3-47106.6" + attribute \src "libresoc.v:47100.3-47108.6" wire $1\wr_pick_dly$1506$next[0:0]$2800 - attribute \src "libresoc.v:47136.3-47144.6" + attribute \src "libresoc.v:47138.3-47146.6" wire $1\wr_pick_dly$1542$next[0:0]$2804 - attribute \src "libresoc.v:47145.3-47153.6" + attribute \src "libresoc.v:47147.3-47155.6" wire $1\wr_pick_dly$1558$next[0:0]$2807 - attribute \src "libresoc.v:47184.3-47192.6" + attribute \src "libresoc.v:47186.3-47194.6" wire $1\wr_pick_dly$1574$next[0:0]$2811 - attribute \src "libresoc.v:47193.3-47201.6" + attribute \src "libresoc.v:47195.3-47203.6" wire $1\wr_pick_dly$1590$next[0:0]$2814 - attribute \src "libresoc.v:47202.3-47210.6" + attribute \src "libresoc.v:47204.3-47212.6" wire $1\wr_pick_dly$1632$next[0:0]$2817 - attribute \src "libresoc.v:47240.3-47248.6" + attribute \src "libresoc.v:47242.3-47250.6" wire $1\wr_pick_dly$1651$next[0:0]$2821 - attribute \src "libresoc.v:47278.3-47286.6" + attribute \src "libresoc.v:47280.3-47288.6" wire $1\wr_pick_dly$1667$next[0:0]$2825 - attribute \src "libresoc.v:47287.3-47295.6" + attribute \src "libresoc.v:47289.3-47297.6" wire $1\wr_pick_dly$1683$next[0:0]$2828 - attribute \src "libresoc.v:47325.3-47333.6" + attribute \src "libresoc.v:47327.3-47335.6" wire $1\wr_pick_dly$1699$next[0:0]$2836 - attribute \src "libresoc.v:47363.3-47371.6" + attribute \src "libresoc.v:47365.3-47373.6" wire $1\wr_pick_dly$1743$next[0:0]$2844 - attribute \src "libresoc.v:47401.3-47409.6" + attribute \src "libresoc.v:47403.3-47411.6" wire $1\wr_pick_dly$1759$next[0:0]$2848 - attribute \src "libresoc.v:47410.3-47418.6" + attribute \src "libresoc.v:47412.3-47420.6" wire $1\wr_pick_dly$1783$next[0:0]$2851 - attribute \src "libresoc.v:47448.3-47456.6" + attribute \src "libresoc.v:47450.3-47458.6" wire $1\wr_pick_dly$1803$next[0:0]$2855 - attribute \src "libresoc.v:46465.3-46473.6" + attribute \src "libresoc.v:46467.3-46475.6" wire $1\wr_pick_dly$986$next[0:0]$2711 - attribute \src "libresoc.v:46427.3-46435.6" + attribute \src "libresoc.v:46429.3-46437.6" wire $1\wr_pick_dly$next[0:0]$2707 - attribute \src "libresoc.v:41430.7-41430.25" + attribute \src "libresoc.v:41432.7-41432.25" wire $1\wr_pick_dly[0:0] - attribute \src "libresoc.v:45800.3-45820.6" + attribute \src "libresoc.v:45802.3-45822.6" wire $2\core_terminate_o$next[0:0]$2590 - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $2\corebusy_o[0:0] - attribute \src "libresoc.v:45625.3-45651.6" + attribute \src "libresoc.v:45627.3-45653.6" wire width 2 $2\counter$next[1:0]$2567 - attribute \src "libresoc.v:46899.3-46927.6" + attribute \src "libresoc.v:46901.3-46929.6" wire $2\fus_cu_issue_i$13[0:0]$2770 - attribute \src "libresoc.v:47296.3-47324.6" + attribute \src "libresoc.v:47298.3-47326.6" wire $2\fus_cu_issue_i$16[0:0]$2832 - attribute \src "libresoc.v:47660.3-47688.6" + attribute \src "libresoc.v:47662.3-47690.6" wire $2\fus_cu_issue_i$19[0:0]$2866 - attribute \src "libresoc.v:48156.3-48184.6" + attribute \src "libresoc.v:48158.3-48186.6" wire $2\fus_cu_issue_i$22[0:0]$2891 - attribute \src "libresoc.v:43483.3-43511.6" + attribute \src "libresoc.v:43485.3-43513.6" wire $2\fus_cu_issue_i$25[0:0]$2358 - attribute \src "libresoc.v:43979.3-44007.6" + attribute \src "libresoc.v:43981.3-44009.6" wire $2\fus_cu_issue_i$28[0:0]$2383 - attribute \src "libresoc.v:44301.3-44329.6" + attribute \src "libresoc.v:44303.3-44331.6" wire $2\fus_cu_issue_i$31[0:0]$2402 - attribute \src "libresoc.v:44768.3-44796.6" + attribute \src "libresoc.v:44770.3-44798.6" wire $2\fus_cu_issue_i$34[0:0]$2426 - attribute \src "libresoc.v:45206.3-45234.6" + attribute \src "libresoc.v:45208.3-45236.6" wire $2\fus_cu_issue_i$37[0:0]$2449 - attribute \src "libresoc.v:46691.3-46719.6" + attribute \src "libresoc.v:46693.3-46721.6" wire $2\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46937.3-46965.6" + attribute \src "libresoc.v:46939.3-46967.6" wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2778 - attribute \src "libresoc.v:47334.3-47362.6" + attribute \src "libresoc.v:47336.3-47364.6" wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2840 - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47691.3-47719.6" wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2871 - attribute \src "libresoc.v:48185.3-48213.6" + attribute \src "libresoc.v:48187.3-48215.6" wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2896 - attribute \src "libresoc.v:43512.3-43540.6" + attribute \src "libresoc.v:43514.3-43542.6" wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2363 - attribute \src "libresoc.v:44008.3-44036.6" + attribute \src "libresoc.v:44010.3-44038.6" wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2388 - attribute \src "libresoc.v:44330.3-44358.6" + attribute \src "libresoc.v:44332.3-44360.6" wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2407 - attribute \src "libresoc.v:44797.3-44825.6" + attribute \src "libresoc.v:44799.3-44827.6" wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2431 - attribute \src "libresoc.v:45235.3-45263.6" + attribute \src "libresoc.v:45237.3-45265.6" wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2454 - attribute \src "libresoc.v:46729.3-46757.6" + attribute \src "libresoc.v:46731.3-46759.6" wire width 4 $2\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46606.3-46634.6" + attribute \src "libresoc.v:46608.3-46636.6" wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45916.3-45944.6" + attribute \src "libresoc.v:45918.3-45946.6" wire width 13 $2\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "libresoc.v:45983.3-46012.6" + attribute \src "libresoc.v:45985.3-46014.6" wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45983.3-46012.6" + attribute \src "libresoc.v:45985.3-46014.6" wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46436.3-46464.6" + attribute \src "libresoc.v:46438.3-46466.6" wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46653.3-46681.6" + attribute \src "libresoc.v:46655.3-46683.6" wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45859.3-45887.6" + attribute \src "libresoc.v:45861.3-45889.6" wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46235.3-46263.6" + attribute \src "libresoc.v:46237.3-46265.6" wire $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46350.3-46378.6" + attribute \src "libresoc.v:46352.3-46380.6" wire $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46521.3-46549.6" + attribute \src "libresoc.v:46523.3-46551.6" wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46568.3-46596.6" + attribute \src "libresoc.v:46570.3-46598.6" wire $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46148.3-46177.6" + attribute \src "libresoc.v:46150.3-46179.6" wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46148.3-46177.6" + attribute \src "libresoc.v:46150.3-46179.6" wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46483.3-46511.6" + attribute \src "libresoc.v:46485.3-46513.6" wire $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46061.3-46090.6" + attribute \src "libresoc.v:46063.3-46092.6" wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46061.3-46090.6" + attribute \src "libresoc.v:46063.3-46092.6" wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46398.3-46426.6" + attribute \src "libresoc.v:46400.3-46428.6" wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46283.3-46311.6" + attribute \src "libresoc.v:46285.3-46313.6" wire $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46984.3-47012.6" + attribute \src "libresoc.v:46986.3-47014.6" wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47069.3-47097.6" + attribute \src "libresoc.v:47071.3-47099.6" wire width 13 $2\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "libresoc.v:47154.3-47183.6" + attribute \src "libresoc.v:47156.3-47185.6" wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47154.3-47183.6" + attribute \src "libresoc.v:47156.3-47185.6" wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47107.3-47135.6" + attribute \src "libresoc.v:47109.3-47137.6" wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47022.3-47050.6" + attribute \src "libresoc.v:47024.3-47052.6" wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47249.3-47277.6" + attribute \src "libresoc.v:47251.3-47279.6" wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47211.3-47239.6" + attribute \src "libresoc.v:47213.3-47241.6" wire $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46814.3-46842.6" + attribute \src "libresoc.v:46816.3-46844.6" wire width 13 $2\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "libresoc.v:46861.3-46889.6" + attribute \src "libresoc.v:46863.3-46891.6" wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46767.3-46795.6" + attribute \src "libresoc.v:46769.3-46797.6" wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43921.3-43949.6" + attribute \src "libresoc.v:43923.3-43951.6" wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43570.3-43598.6" + attribute \src "libresoc.v:43572.3-43600.6" wire width 13 $2\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "libresoc.v:43599.3-43628.6" + attribute \src "libresoc.v:43601.3-43630.6" wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43599.3-43628.6" + attribute \src "libresoc.v:43601.3-43630.6" wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43747.3-43775.6" + attribute \src "libresoc.v:43749.3-43777.6" wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43950.3-43978.6" + attribute \src "libresoc.v:43952.3-43980.6" wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43541.3-43569.6" + attribute \src "libresoc.v:43543.3-43571.6" wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43689.3-43717.6" + attribute \src "libresoc.v:43691.3-43719.6" wire $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43776.3-43804.6" + attribute \src "libresoc.v:43778.3-43806.6" wire $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43863.3-43891.6" + attribute \src "libresoc.v:43865.3-43893.6" wire $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43892.3-43920.6" + attribute \src "libresoc.v:43894.3-43922.6" wire $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43659.3-43688.6" + attribute \src "libresoc.v:43661.3-43690.6" wire $2\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43659.3-43688.6" + attribute \src "libresoc.v:43661.3-43690.6" wire $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43834.3-43862.6" + attribute \src "libresoc.v:43836.3-43864.6" wire $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43629.3-43658.6" + attribute \src "libresoc.v:43631.3-43660.6" wire $2\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43629.3-43658.6" + attribute \src "libresoc.v:43631.3-43660.6" wire $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43805.3-43833.6" + attribute \src "libresoc.v:43807.3-43835.6" wire $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43718.3-43746.6" + attribute \src "libresoc.v:43720.3-43748.6" wire $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:48098.3-48126.6" + attribute \src "libresoc.v:48100.3-48128.6" wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47747.3-47775.6" + attribute \src "libresoc.v:47749.3-47777.6" wire width 13 $2\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "libresoc.v:47776.3-47805.6" + attribute \src "libresoc.v:47778.3-47807.6" wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47776.3-47805.6" + attribute \src "libresoc.v:47778.3-47807.6" wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47924.3-47952.6" + attribute \src "libresoc.v:47926.3-47954.6" wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48127.3-48155.6" + attribute \src "libresoc.v:48129.3-48157.6" wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47718.3-47746.6" + attribute \src "libresoc.v:47720.3-47748.6" wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47866.3-47894.6" + attribute \src "libresoc.v:47868.3-47896.6" wire $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47953.3-47981.6" + attribute \src "libresoc.v:47955.3-47983.6" wire $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48040.3-48068.6" + attribute \src "libresoc.v:48042.3-48070.6" wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:48069.3-48097.6" + attribute \src "libresoc.v:48071.3-48099.6" wire $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47836.3-47865.6" + attribute \src "libresoc.v:47838.3-47867.6" wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47836.3-47865.6" + attribute \src "libresoc.v:47838.3-47867.6" wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48011.3-48039.6" + attribute \src "libresoc.v:48013.3-48041.6" wire $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47806.3-47835.6" + attribute \src "libresoc.v:47808.3-47837.6" wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47806.3-47835.6" + attribute \src "libresoc.v:47808.3-47837.6" wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47982.3-48010.6" + attribute \src "libresoc.v:47984.3-48012.6" wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47895.3-47923.6" + attribute \src "libresoc.v:47897.3-47925.6" wire $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44066.3-44094.6" + attribute \src "libresoc.v:44068.3-44096.6" wire width 13 $2\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "libresoc.v:44095.3-44124.6" + attribute \src "libresoc.v:44097.3-44126.6" wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44095.3-44124.6" + attribute \src "libresoc.v:44097.3-44126.6" wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44272.3-44300.6" + attribute \src "libresoc.v:44274.3-44302.6" wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44037.3-44065.6" + attribute \src "libresoc.v:44039.3-44067.6" wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44214.3-44242.6" + attribute \src "libresoc.v:44216.3-44244.6" wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44243.3-44271.6" + attribute \src "libresoc.v:44245.3-44273.6" wire $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44155.3-44184.6" + attribute \src "libresoc.v:44157.3-44186.6" wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44155.3-44184.6" + attribute \src "libresoc.v:44157.3-44186.6" wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44125.3-44154.6" + attribute \src "libresoc.v:44127.3-44156.6" wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44125.3-44154.6" + attribute \src "libresoc.v:44127.3-44156.6" wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44185.3-44213.6" + attribute \src "libresoc.v:44187.3-44215.6" wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44388.3-44416.6" + attribute \src "libresoc.v:44390.3-44418.6" wire width 13 $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "libresoc.v:44417.3-44446.6" + attribute \src "libresoc.v:44419.3-44448.6" wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44417.3-44446.6" + attribute \src "libresoc.v:44419.3-44448.6" wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44565.3-44593.6" + attribute \src "libresoc.v:44567.3-44595.6" wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44623.3-44651.6" + attribute \src "libresoc.v:44625.3-44653.6" wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44739.3-44767.6" + attribute \src "libresoc.v:44741.3-44769.6" wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44359.3-44387.6" + attribute \src "libresoc.v:44361.3-44389.6" wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44536.3-44564.6" + attribute \src "libresoc.v:44538.3-44566.6" wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44681.3-44709.6" + attribute \src "libresoc.v:44683.3-44711.6" wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44710.3-44738.6" + attribute \src "libresoc.v:44712.3-44740.6" wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44477.3-44506.6" + attribute \src "libresoc.v:44479.3-44508.6" wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44477.3-44506.6" + attribute \src "libresoc.v:44479.3-44508.6" wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44594.3-44622.6" + attribute \src "libresoc.v:44596.3-44624.6" wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44652.3-44680.6" + attribute \src "libresoc.v:44654.3-44682.6" wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44447.3-44476.6" + attribute \src "libresoc.v:44449.3-44478.6" wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44447.3-44476.6" + attribute \src "libresoc.v:44449.3-44478.6" wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44507.3-44535.6" + attribute \src "libresoc.v:44509.3-44537.6" wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48243.3-48271.6" + attribute \src "libresoc.v:48245.3-48273.6" wire width 13 $2\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "libresoc.v:43425.3-43453.6" + attribute \src "libresoc.v:43427.3-43455.6" wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48214.3-48242.6" + attribute \src "libresoc.v:48216.3-48244.6" wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43454.3-43482.6" + attribute \src "libresoc.v:43456.3-43484.6" wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47515.3-47543.6" + attribute \src "libresoc.v:47517.3-47545.6" wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47419.3-47447.6" + attribute \src "libresoc.v:47421.3-47449.6" wire width 13 $2\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "libresoc.v:47457.3-47485.6" + attribute \src "libresoc.v:47459.3-47487.6" wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47372.3-47400.6" + attribute \src "libresoc.v:47374.3-47402.6" wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47544.3-47572.6" + attribute \src "libresoc.v:47546.3-47574.6" wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47631.3-47659.6" + attribute \src "libresoc.v:47633.3-47661.6" wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47486.3-47514.6" + attribute \src "libresoc.v:47488.3-47516.6" wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47602.3-47630.6" + attribute \src "libresoc.v:47604.3-47632.6" wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47573.3-47601.6" + attribute \src "libresoc.v:47575.3-47603.6" wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45090.3-45118.6" + attribute \src "libresoc.v:45092.3-45120.6" wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45061.3-45089.6" + attribute \src "libresoc.v:45063.3-45091.6" wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44855.3-44883.6" + attribute \src "libresoc.v:44857.3-44885.6" wire width 13 $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "libresoc.v:44884.3-44913.6" + attribute \src "libresoc.v:44886.3-44915.6" wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44884.3-44913.6" + attribute \src "libresoc.v:44886.3-44915.6" wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45177.3-45205.6" + attribute \src "libresoc.v:45179.3-45207.6" wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44826.3-44854.6" + attribute \src "libresoc.v:44828.3-44856.6" wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45003.3-45031.6" + attribute \src "libresoc.v:45005.3-45033.6" wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45032.3-45060.6" + attribute \src "libresoc.v:45034.3-45062.6" wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45148.3-45176.6" + attribute \src "libresoc.v:45150.3-45178.6" wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44973.3-45002.6" + attribute \src "libresoc.v:44975.3-45004.6" wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44973.3-45002.6" + attribute \src "libresoc.v:44975.3-45004.6" wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44943.3-44972.6" + attribute \src "libresoc.v:44945.3-44974.6" wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44943.3-44972.6" + attribute \src "libresoc.v:44945.3-44974.6" wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45119.3-45147.6" + attribute \src "libresoc.v:45121.3-45149.6" wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44914.3-44942.6" + attribute \src "libresoc.v:44916.3-44944.6" wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45800.3-45820.6" + attribute \src "libresoc.v:45802.3-45822.6" wire $3\core_terminate_o$next[0:0]$2591 - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $3\corebusy_o[0:0] - attribute \src "libresoc.v:45625.3-45651.6" + attribute \src "libresoc.v:45627.3-45653.6" wire width 2 $3\counter$next[1:0]$2568 - attribute \src "libresoc.v:46899.3-46927.6" + attribute \src "libresoc.v:46901.3-46929.6" wire $3\fus_cu_issue_i$13[0:0]$2771 - attribute \src "libresoc.v:47296.3-47324.6" + attribute \src "libresoc.v:47298.3-47326.6" wire $3\fus_cu_issue_i$16[0:0]$2833 - attribute \src "libresoc.v:47660.3-47688.6" + attribute \src "libresoc.v:47662.3-47690.6" wire $3\fus_cu_issue_i$19[0:0]$2867 - attribute \src "libresoc.v:48156.3-48184.6" + attribute \src "libresoc.v:48158.3-48186.6" wire $3\fus_cu_issue_i$22[0:0]$2892 - attribute \src "libresoc.v:43483.3-43511.6" + attribute \src "libresoc.v:43485.3-43513.6" wire $3\fus_cu_issue_i$25[0:0]$2359 - attribute \src "libresoc.v:43979.3-44007.6" + attribute \src "libresoc.v:43981.3-44009.6" wire $3\fus_cu_issue_i$28[0:0]$2384 - attribute \src "libresoc.v:44301.3-44329.6" + attribute \src "libresoc.v:44303.3-44331.6" wire $3\fus_cu_issue_i$31[0:0]$2403 - attribute \src "libresoc.v:44768.3-44796.6" + attribute \src "libresoc.v:44770.3-44798.6" wire $3\fus_cu_issue_i$34[0:0]$2427 - attribute \src "libresoc.v:45206.3-45234.6" + attribute \src "libresoc.v:45208.3-45236.6" wire $3\fus_cu_issue_i$37[0:0]$2450 - attribute \src "libresoc.v:46691.3-46719.6" + attribute \src "libresoc.v:46693.3-46721.6" wire $3\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46937.3-46965.6" + attribute \src "libresoc.v:46939.3-46967.6" wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2779 - attribute \src "libresoc.v:47334.3-47362.6" + attribute \src "libresoc.v:47336.3-47364.6" wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2841 - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47691.3-47719.6" wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2872 - attribute \src "libresoc.v:48185.3-48213.6" + attribute \src "libresoc.v:48187.3-48215.6" wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2897 - attribute \src "libresoc.v:43512.3-43540.6" + attribute \src "libresoc.v:43514.3-43542.6" wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2364 - attribute \src "libresoc.v:44008.3-44036.6" + attribute \src "libresoc.v:44010.3-44038.6" wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2389 - attribute \src "libresoc.v:44330.3-44358.6" + attribute \src "libresoc.v:44332.3-44360.6" wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2408 - attribute \src "libresoc.v:44797.3-44825.6" + attribute \src "libresoc.v:44799.3-44827.6" wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2432 - attribute \src "libresoc.v:45235.3-45263.6" + attribute \src "libresoc.v:45237.3-45265.6" wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2455 - attribute \src "libresoc.v:46729.3-46757.6" + attribute \src "libresoc.v:46731.3-46759.6" wire width 4 $3\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46606.3-46634.6" + attribute \src "libresoc.v:46608.3-46636.6" wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45916.3-45944.6" + attribute \src "libresoc.v:45918.3-45946.6" wire width 13 $3\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "libresoc.v:45983.3-46012.6" + attribute \src "libresoc.v:45985.3-46014.6" wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45983.3-46012.6" + attribute \src "libresoc.v:45985.3-46014.6" wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46436.3-46464.6" + attribute \src "libresoc.v:46438.3-46466.6" wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46653.3-46681.6" + attribute \src "libresoc.v:46655.3-46683.6" wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45859.3-45887.6" + attribute \src "libresoc.v:45861.3-45889.6" wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46235.3-46263.6" + attribute \src "libresoc.v:46237.3-46265.6" wire $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46350.3-46378.6" + attribute \src "libresoc.v:46352.3-46380.6" wire $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46521.3-46549.6" + attribute \src "libresoc.v:46523.3-46551.6" wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46568.3-46596.6" + attribute \src "libresoc.v:46570.3-46598.6" wire $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46148.3-46177.6" + attribute \src "libresoc.v:46150.3-46179.6" wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46148.3-46177.6" + attribute \src "libresoc.v:46150.3-46179.6" wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46483.3-46511.6" + attribute \src "libresoc.v:46485.3-46513.6" wire $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46061.3-46090.6" + attribute \src "libresoc.v:46063.3-46092.6" wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46061.3-46090.6" + attribute \src "libresoc.v:46063.3-46092.6" wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46398.3-46426.6" + attribute \src "libresoc.v:46400.3-46428.6" wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46283.3-46311.6" + attribute \src "libresoc.v:46285.3-46313.6" wire $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46984.3-47012.6" + attribute \src "libresoc.v:46986.3-47014.6" wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47069.3-47097.6" + attribute \src "libresoc.v:47071.3-47099.6" wire width 13 $3\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "libresoc.v:47154.3-47183.6" + attribute \src "libresoc.v:47156.3-47185.6" wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47154.3-47183.6" + attribute \src "libresoc.v:47156.3-47185.6" wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47107.3-47135.6" + attribute \src "libresoc.v:47109.3-47137.6" wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47022.3-47050.6" + attribute \src "libresoc.v:47024.3-47052.6" wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47249.3-47277.6" + attribute \src "libresoc.v:47251.3-47279.6" wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47211.3-47239.6" + attribute \src "libresoc.v:47213.3-47241.6" wire $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46814.3-46842.6" + attribute \src "libresoc.v:46816.3-46844.6" wire width 13 $3\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "libresoc.v:46861.3-46889.6" + attribute \src "libresoc.v:46863.3-46891.6" wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46767.3-46795.6" + attribute \src "libresoc.v:46769.3-46797.6" wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43921.3-43949.6" + attribute \src "libresoc.v:43923.3-43951.6" wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43570.3-43598.6" + attribute \src "libresoc.v:43572.3-43600.6" wire width 13 $3\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "libresoc.v:43599.3-43628.6" + attribute \src "libresoc.v:43601.3-43630.6" wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43599.3-43628.6" + attribute \src "libresoc.v:43601.3-43630.6" wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43747.3-43775.6" + attribute \src "libresoc.v:43749.3-43777.6" wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43950.3-43978.6" + attribute \src "libresoc.v:43952.3-43980.6" wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43541.3-43569.6" + attribute \src "libresoc.v:43543.3-43571.6" wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43689.3-43717.6" + attribute \src "libresoc.v:43691.3-43719.6" wire $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43776.3-43804.6" + attribute \src "libresoc.v:43778.3-43806.6" wire $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43863.3-43891.6" + attribute \src "libresoc.v:43865.3-43893.6" wire $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43892.3-43920.6" + attribute \src "libresoc.v:43894.3-43922.6" wire $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43659.3-43688.6" + attribute \src "libresoc.v:43661.3-43690.6" wire $3\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43659.3-43688.6" + attribute \src "libresoc.v:43661.3-43690.6" wire $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43834.3-43862.6" + attribute \src "libresoc.v:43836.3-43864.6" wire $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43629.3-43658.6" + attribute \src "libresoc.v:43631.3-43660.6" wire $3\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43629.3-43658.6" + attribute \src "libresoc.v:43631.3-43660.6" wire $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43805.3-43833.6" + attribute \src "libresoc.v:43807.3-43835.6" wire $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43718.3-43746.6" + attribute \src "libresoc.v:43720.3-43748.6" wire $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:48098.3-48126.6" + attribute \src "libresoc.v:48100.3-48128.6" wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47747.3-47775.6" + attribute \src "libresoc.v:47749.3-47777.6" wire width 13 $3\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "libresoc.v:47776.3-47805.6" + attribute \src "libresoc.v:47778.3-47807.6" wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47776.3-47805.6" + attribute \src "libresoc.v:47778.3-47807.6" wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47924.3-47952.6" + attribute \src "libresoc.v:47926.3-47954.6" wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48127.3-48155.6" + attribute \src "libresoc.v:48129.3-48157.6" wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47718.3-47746.6" + attribute \src "libresoc.v:47720.3-47748.6" wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47866.3-47894.6" + attribute \src "libresoc.v:47868.3-47896.6" wire $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47953.3-47981.6" + attribute \src "libresoc.v:47955.3-47983.6" wire $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48040.3-48068.6" + attribute \src "libresoc.v:48042.3-48070.6" wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:48069.3-48097.6" + attribute \src "libresoc.v:48071.3-48099.6" wire $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47836.3-47865.6" + attribute \src "libresoc.v:47838.3-47867.6" wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47836.3-47865.6" + attribute \src "libresoc.v:47838.3-47867.6" wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48011.3-48039.6" + attribute \src "libresoc.v:48013.3-48041.6" wire $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47806.3-47835.6" + attribute \src "libresoc.v:47808.3-47837.6" wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47806.3-47835.6" + attribute \src "libresoc.v:47808.3-47837.6" wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47982.3-48010.6" + attribute \src "libresoc.v:47984.3-48012.6" wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47895.3-47923.6" + attribute \src "libresoc.v:47897.3-47925.6" wire $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44066.3-44094.6" + attribute \src "libresoc.v:44068.3-44096.6" wire width 13 $3\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "libresoc.v:44095.3-44124.6" + attribute \src "libresoc.v:44097.3-44126.6" wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44095.3-44124.6" + attribute \src "libresoc.v:44097.3-44126.6" wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44272.3-44300.6" + attribute \src "libresoc.v:44274.3-44302.6" wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44037.3-44065.6" + attribute \src "libresoc.v:44039.3-44067.6" wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44214.3-44242.6" + attribute \src "libresoc.v:44216.3-44244.6" wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44243.3-44271.6" + attribute \src "libresoc.v:44245.3-44273.6" wire $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44155.3-44184.6" + attribute \src "libresoc.v:44157.3-44186.6" wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44155.3-44184.6" + attribute \src "libresoc.v:44157.3-44186.6" wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44125.3-44154.6" + attribute \src "libresoc.v:44127.3-44156.6" wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44125.3-44154.6" + attribute \src "libresoc.v:44127.3-44156.6" wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44185.3-44213.6" + attribute \src "libresoc.v:44187.3-44215.6" wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44388.3-44416.6" + attribute \src "libresoc.v:44390.3-44418.6" wire width 13 $3\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "libresoc.v:44417.3-44446.6" + attribute \src "libresoc.v:44419.3-44448.6" wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44417.3-44446.6" + attribute \src "libresoc.v:44419.3-44448.6" wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44565.3-44593.6" + attribute \src "libresoc.v:44567.3-44595.6" wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44623.3-44651.6" + attribute \src "libresoc.v:44625.3-44653.6" wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44739.3-44767.6" + attribute \src "libresoc.v:44741.3-44769.6" wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44359.3-44387.6" + attribute \src "libresoc.v:44361.3-44389.6" wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44536.3-44564.6" + attribute \src "libresoc.v:44538.3-44566.6" wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44681.3-44709.6" + attribute \src "libresoc.v:44683.3-44711.6" wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44710.3-44738.6" + attribute \src "libresoc.v:44712.3-44740.6" wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44477.3-44506.6" + attribute \src "libresoc.v:44479.3-44508.6" wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44477.3-44506.6" + attribute \src "libresoc.v:44479.3-44508.6" wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44594.3-44622.6" + attribute \src "libresoc.v:44596.3-44624.6" wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44652.3-44680.6" + attribute \src "libresoc.v:44654.3-44682.6" wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44447.3-44476.6" + attribute \src "libresoc.v:44449.3-44478.6" wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44447.3-44476.6" + attribute \src "libresoc.v:44449.3-44478.6" wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44507.3-44535.6" + attribute \src "libresoc.v:44509.3-44537.6" wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48243.3-48271.6" + attribute \src "libresoc.v:48245.3-48273.6" wire width 13 $3\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "libresoc.v:43425.3-43453.6" + attribute \src "libresoc.v:43427.3-43455.6" wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48214.3-48242.6" + attribute \src "libresoc.v:48216.3-48244.6" wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43454.3-43482.6" + attribute \src "libresoc.v:43456.3-43484.6" wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47515.3-47543.6" + attribute \src "libresoc.v:47517.3-47545.6" wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47419.3-47447.6" + attribute \src "libresoc.v:47421.3-47449.6" wire width 13 $3\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "libresoc.v:47457.3-47485.6" + attribute \src "libresoc.v:47459.3-47487.6" wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47372.3-47400.6" + attribute \src "libresoc.v:47374.3-47402.6" wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47544.3-47572.6" + attribute \src "libresoc.v:47546.3-47574.6" wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47631.3-47659.6" + attribute \src "libresoc.v:47633.3-47661.6" wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47486.3-47514.6" + attribute \src "libresoc.v:47488.3-47516.6" wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47602.3-47630.6" + attribute \src "libresoc.v:47604.3-47632.6" wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47573.3-47601.6" + attribute \src "libresoc.v:47575.3-47603.6" wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45090.3-45118.6" + attribute \src "libresoc.v:45092.3-45120.6" wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45061.3-45089.6" + attribute \src "libresoc.v:45063.3-45091.6" wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44855.3-44883.6" + attribute \src "libresoc.v:44857.3-44885.6" wire width 13 $3\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "libresoc.v:44884.3-44913.6" + attribute \src "libresoc.v:44886.3-44915.6" wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44884.3-44913.6" + attribute \src "libresoc.v:44886.3-44915.6" wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45177.3-45205.6" + attribute \src "libresoc.v:45179.3-45207.6" wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44826.3-44854.6" + attribute \src "libresoc.v:44828.3-44856.6" wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45003.3-45031.6" + attribute \src "libresoc.v:45005.3-45033.6" wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45032.3-45060.6" + attribute \src "libresoc.v:45034.3-45062.6" wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45148.3-45176.6" + attribute \src "libresoc.v:45150.3-45178.6" wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44973.3-45002.6" + attribute \src "libresoc.v:44975.3-45004.6" wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44973.3-45002.6" + attribute \src "libresoc.v:44975.3-45004.6" wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44943.3-44972.6" + attribute \src "libresoc.v:44945.3-44974.6" wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44943.3-44972.6" + attribute \src "libresoc.v:44945.3-44974.6" wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45119.3-45147.6" + attribute \src "libresoc.v:45121.3-45149.6" wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44914.3-44942.6" + attribute \src "libresoc.v:44916.3-44944.6" wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $4\corebusy_o[0:0] - attribute \src "libresoc.v:45625.3-45651.6" + attribute \src "libresoc.v:45627.3-45653.6" wire width 2 $4\counter$next[1:0]$2569 - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $5\corebusy_o[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $6\corebusy_o[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $7\corebusy_o[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $8\corebusy_o[0:0] - attribute \src "libresoc.v:45671.3-45761.6" + attribute \src "libresoc.v:45673.3-45763.6" wire $9\corebusy_o[0:0] - attribute \src "libresoc.v:41809.20-41809.122" - wire $and$libresoc.v:41809$1506_Y - attribute \src "libresoc.v:41810.20-41810.126" - wire $and$libresoc.v:41810$1507_Y - attribute \src "libresoc.v:41812.20-41812.110" - wire $and$libresoc.v:41812$1509_Y - attribute \src "libresoc.v:41813.20-41813.123" - wire $and$libresoc.v:41813$1510_Y - attribute \src "libresoc.v:41815.20-41815.122" - wire $and$libresoc.v:41815$1512_Y - attribute \src "libresoc.v:41816.20-41816.126" - wire $and$libresoc.v:41816$1513_Y - attribute \src "libresoc.v:41818.20-41818.110" - wire $and$libresoc.v:41818$1515_Y - attribute \src "libresoc.v:41819.20-41819.123" - wire $and$libresoc.v:41819$1516_Y + attribute \src "libresoc.v:41811.20-41811.122" + wire $and$libresoc.v:41811$1506_Y + attribute \src "libresoc.v:41812.20-41812.126" + wire $and$libresoc.v:41812$1507_Y + attribute \src "libresoc.v:41814.20-41814.110" + wire $and$libresoc.v:41814$1509_Y + attribute \src "libresoc.v:41815.20-41815.123" + wire $and$libresoc.v:41815$1510_Y + attribute \src "libresoc.v:41817.20-41817.122" + wire $and$libresoc.v:41817$1512_Y + attribute \src "libresoc.v:41818.20-41818.126" + wire $and$libresoc.v:41818$1513_Y + attribute \src "libresoc.v:41820.20-41820.110" + wire $and$libresoc.v:41820$1515_Y attribute \src "libresoc.v:41821.20-41821.123" - wire $and$libresoc.v:41821$1518_Y - attribute \src "libresoc.v:41822.20-41822.126" - wire $and$libresoc.v:41822$1519_Y - attribute \src "libresoc.v:41824.20-41824.110" - wire $and$libresoc.v:41824$1521_Y - attribute \src "libresoc.v:41825.20-41825.123" - wire $and$libresoc.v:41825$1522_Y + wire $and$libresoc.v:41821$1516_Y + attribute \src "libresoc.v:41823.20-41823.123" + wire $and$libresoc.v:41823$1518_Y + attribute \src "libresoc.v:41824.20-41824.126" + wire $and$libresoc.v:41824$1519_Y + attribute \src "libresoc.v:41826.20-41826.110" + wire $and$libresoc.v:41826$1521_Y attribute \src "libresoc.v:41827.20-41827.123" - wire $and$libresoc.v:41827$1524_Y - attribute \src "libresoc.v:41828.20-41828.126" - wire $and$libresoc.v:41828$1525_Y - attribute \src "libresoc.v:41830.20-41830.110" - wire $and$libresoc.v:41830$1527_Y - attribute \src "libresoc.v:41831.20-41831.123" - wire $and$libresoc.v:41831$1528_Y + wire $and$libresoc.v:41827$1522_Y + attribute \src "libresoc.v:41829.20-41829.123" + wire $and$libresoc.v:41829$1524_Y + attribute \src "libresoc.v:41830.20-41830.126" + wire $and$libresoc.v:41830$1525_Y + attribute \src "libresoc.v:41832.20-41832.110" + wire $and$libresoc.v:41832$1527_Y attribute \src "libresoc.v:41833.20-41833.123" - wire $and$libresoc.v:41833$1530_Y - attribute \src "libresoc.v:41834.20-41834.126" - wire $and$libresoc.v:41834$1531_Y - attribute \src "libresoc.v:41836.20-41836.110" - wire $and$libresoc.v:41836$1533_Y - attribute \src "libresoc.v:41837.20-41837.123" - wire $and$libresoc.v:41837$1534_Y + wire $and$libresoc.v:41833$1528_Y + attribute \src "libresoc.v:41835.20-41835.123" + wire $and$libresoc.v:41835$1530_Y + attribute \src "libresoc.v:41836.20-41836.126" + wire $and$libresoc.v:41836$1531_Y + attribute \src "libresoc.v:41838.20-41838.110" + wire $and$libresoc.v:41838$1533_Y attribute \src "libresoc.v:41839.20-41839.123" - wire $and$libresoc.v:41839$1536_Y - attribute \src "libresoc.v:41840.20-41840.126" - wire $and$libresoc.v:41840$1537_Y - attribute \src "libresoc.v:41842.20-41842.110" - wire $and$libresoc.v:41842$1539_Y - attribute \src "libresoc.v:41843.20-41843.123" - wire $and$libresoc.v:41843$1540_Y - attribute \src "libresoc.v:41845.20-41845.113" - wire $and$libresoc.v:41845$1542_Y - attribute \src "libresoc.v:41846.20-41846.126" - wire $and$libresoc.v:41846$1543_Y - attribute \src "libresoc.v:41848.20-41848.110" - wire $and$libresoc.v:41848$1545_Y - attribute \src "libresoc.v:41849.20-41849.123" - wire $and$libresoc.v:41849$1546_Y - attribute \src "libresoc.v:41851.20-41851.114" - wire $and$libresoc.v:41851$1548_Y - attribute \src "libresoc.v:41852.20-41852.126" - wire $and$libresoc.v:41852$1549_Y - attribute \src "libresoc.v:41854.20-41854.110" - wire $and$libresoc.v:41854$1551_Y - attribute \src "libresoc.v:41855.20-41855.123" - wire $and$libresoc.v:41855$1552_Y - attribute \src "libresoc.v:41884.20-41884.123" - wire $and$libresoc.v:41884$1581_Y - attribute \src "libresoc.v:41885.20-41885.128" - wire $and$libresoc.v:41885$1582_Y - attribute \src "libresoc.v:41886.20-41886.133" - wire $and$libresoc.v:41886$1583_Y - attribute \src "libresoc.v:41888.20-41888.110" - wire $and$libresoc.v:41888$1585_Y - attribute \src "libresoc.v:41889.20-41889.128" - wire $and$libresoc.v:41889$1586_Y - attribute \src "libresoc.v:41891.20-41891.116" - wire $and$libresoc.v:41891$1588_Y - attribute \src "libresoc.v:41892.20-41892.123" - wire $and$libresoc.v:41892$1589_Y - attribute \src "libresoc.v:41893.20-41893.128" - wire $and$libresoc.v:41893$1590_Y - attribute \src "libresoc.v:41894.20-41894.128" - wire $and$libresoc.v:41894$1591_Y - attribute \src "libresoc.v:41895.20-41895.129" - wire $and$libresoc.v:41895$1592_Y - attribute \src "libresoc.v:41896.20-41896.129" - wire $and$libresoc.v:41896$1593_Y + wire $and$libresoc.v:41839$1534_Y + attribute \src "libresoc.v:41841.20-41841.123" + wire $and$libresoc.v:41841$1536_Y + attribute \src "libresoc.v:41842.20-41842.126" + wire $and$libresoc.v:41842$1537_Y + attribute \src "libresoc.v:41844.20-41844.110" + wire $and$libresoc.v:41844$1539_Y + attribute \src "libresoc.v:41845.20-41845.123" + wire $and$libresoc.v:41845$1540_Y + attribute \src "libresoc.v:41847.20-41847.113" + wire $and$libresoc.v:41847$1542_Y + attribute \src "libresoc.v:41848.20-41848.126" + wire $and$libresoc.v:41848$1543_Y + attribute \src "libresoc.v:41850.20-41850.110" + wire $and$libresoc.v:41850$1545_Y + attribute \src "libresoc.v:41851.20-41851.123" + wire $and$libresoc.v:41851$1546_Y + attribute \src "libresoc.v:41853.20-41853.114" + wire $and$libresoc.v:41853$1548_Y + attribute \src "libresoc.v:41854.20-41854.126" + wire $and$libresoc.v:41854$1549_Y + attribute \src "libresoc.v:41856.20-41856.110" + wire $and$libresoc.v:41856$1551_Y + attribute \src "libresoc.v:41857.20-41857.123" + wire $and$libresoc.v:41857$1552_Y + attribute \src "libresoc.v:41886.20-41886.123" + wire $and$libresoc.v:41886$1581_Y + attribute \src "libresoc.v:41887.20-41887.128" + wire $and$libresoc.v:41887$1582_Y + attribute \src "libresoc.v:41888.20-41888.133" + wire $and$libresoc.v:41888$1583_Y + attribute \src "libresoc.v:41890.20-41890.110" + wire $and$libresoc.v:41890$1585_Y + attribute \src "libresoc.v:41891.20-41891.128" + wire $and$libresoc.v:41891$1586_Y + attribute \src "libresoc.v:41893.20-41893.116" + wire $and$libresoc.v:41893$1588_Y + attribute \src "libresoc.v:41894.20-41894.123" + wire $and$libresoc.v:41894$1589_Y + attribute \src "libresoc.v:41895.20-41895.128" + wire $and$libresoc.v:41895$1590_Y + attribute \src "libresoc.v:41896.20-41896.128" + wire $and$libresoc.v:41896$1591_Y attribute \src "libresoc.v:41897.20-41897.129" - wire $and$libresoc.v:41897$1594_Y - attribute \src "libresoc.v:41898.20-41898.130" - wire $and$libresoc.v:41898$1595_Y - attribute \src "libresoc.v:41900.20-41900.110" - wire $and$libresoc.v:41900$1597_Y - attribute \src "libresoc.v:41901.20-41901.125" - wire $and$libresoc.v:41901$1598_Y - attribute \src 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$and$libresoc.v:42248$1948_Y + attribute \src "libresoc.v:42250.19-42250.102" + wire $and$libresoc.v:42250$1950_Y attribute \src "libresoc.v:42251.19-42251.127" - wire $and$libresoc.v:42251$1953_Y - attribute \src "libresoc.v:42252.19-42252.112" - wire $and$libresoc.v:42252$1954_Y - attribute \src "libresoc.v:42254.19-42254.102" - wire $and$libresoc.v:42254$1956_Y - attribute \src "libresoc.v:42255.19-42255.127" - wire $and$libresoc.v:42255$1957_Y + wire $and$libresoc.v:42251$1951_Y + attribute \src "libresoc.v:42253.19-42253.127" + wire $and$libresoc.v:42253$1953_Y + attribute \src "libresoc.v:42254.19-42254.112" + wire $and$libresoc.v:42254$1954_Y + attribute \src "libresoc.v:42256.19-42256.102" + wire $and$libresoc.v:42256$1956_Y attribute \src "libresoc.v:42257.19-42257.127" - wire $and$libresoc.v:42257$1959_Y - attribute \src "libresoc.v:42258.19-42258.112" - wire $and$libresoc.v:42258$1960_Y - attribute \src "libresoc.v:42260.19-42260.102" - wire $and$libresoc.v:42260$1962_Y - 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"libresoc.v:42282.19-42282.127" - wire $and$libresoc.v:42282$1984_Y + wire $and$libresoc.v:42263$1963_Y + attribute \src "libresoc.v:42265.19-42265.127" + wire $and$libresoc.v:42265$1965_Y + attribute \src "libresoc.v:42266.19-42266.112" + wire $and$libresoc.v:42266$1966_Y + attribute \src "libresoc.v:42268.19-42268.102" + wire $and$libresoc.v:42268$1968_Y + attribute \src "libresoc.v:42269.19-42269.127" + wire $and$libresoc.v:42269$1969_Y + attribute \src "libresoc.v:42280.19-42280.122" + wire $and$libresoc.v:42280$1980_Y + attribute \src "libresoc.v:42281.19-42281.112" + wire $and$libresoc.v:42281$1981_Y + attribute \src "libresoc.v:42283.19-42283.102" + wire $and$libresoc.v:42283$1983_Y attribute \src "libresoc.v:42284.19-42284.127" - wire $and$libresoc.v:42284$1986_Y - attribute \src "libresoc.v:42285.19-42285.112" - wire $and$libresoc.v:42285$1987_Y - attribute \src "libresoc.v:42287.19-42287.102" - wire $and$libresoc.v:42287$1989_Y - attribute \src "libresoc.v:42288.19-42288.127" - wire $and$libresoc.v:42288$1990_Y + wire $and$libresoc.v:42284$1984_Y + attribute \src "libresoc.v:42286.19-42286.127" + wire $and$libresoc.v:42286$1986_Y + attribute \src "libresoc.v:42287.19-42287.112" + wire $and$libresoc.v:42287$1987_Y + attribute \src "libresoc.v:42289.19-42289.102" + wire $and$libresoc.v:42289$1989_Y attribute \src "libresoc.v:42290.19-42290.127" - wire $and$libresoc.v:42290$1992_Y - attribute \src "libresoc.v:42291.19-42291.112" - wire $and$libresoc.v:42291$1993_Y - attribute \src "libresoc.v:42293.19-42293.102" - wire $and$libresoc.v:42293$1995_Y - attribute \src "libresoc.v:42294.19-42294.127" - wire $and$libresoc.v:42294$1996_Y + wire $and$libresoc.v:42290$1990_Y + attribute \src "libresoc.v:42292.19-42292.127" + wire $and$libresoc.v:42292$1992_Y + attribute \src "libresoc.v:42293.19-42293.112" + wire $and$libresoc.v:42293$1993_Y + attribute \src "libresoc.v:42295.19-42295.102" + wire $and$libresoc.v:42295$1995_Y attribute \src "libresoc.v:42296.19-42296.127" - wire $and$libresoc.v:42296$1998_Y - attribute \src "libresoc.v:42297.19-42297.112" - wire $and$libresoc.v:42297$1999_Y - attribute \src "libresoc.v:42299.19-42299.102" - wire $and$libresoc.v:42299$2001_Y - attribute \src "libresoc.v:42300.19-42300.127" - wire $and$libresoc.v:42300$2002_Y + wire $and$libresoc.v:42296$1996_Y + attribute \src "libresoc.v:42298.19-42298.127" + wire $and$libresoc.v:42298$1998_Y + attribute \src "libresoc.v:42299.19-42299.112" + wire $and$libresoc.v:42299$1999_Y + attribute \src "libresoc.v:42301.19-42301.102" + wire $and$libresoc.v:42301$2001_Y attribute \src "libresoc.v:42302.19-42302.127" - wire $and$libresoc.v:42302$2004_Y - attribute \src "libresoc.v:42303.19-42303.112" - wire $and$libresoc.v:42303$2005_Y - attribute \src "libresoc.v:42305.19-42305.102" - wire $and$libresoc.v:42305$2007_Y - attribute \src "libresoc.v:42306.19-42306.127" - wire $and$libresoc.v:42306$2008_Y + wire $and$libresoc.v:42302$2002_Y + attribute \src "libresoc.v:42304.19-42304.127" + wire $and$libresoc.v:42304$2004_Y + attribute \src "libresoc.v:42305.19-42305.112" + wire $and$libresoc.v:42305$2005_Y + attribute \src "libresoc.v:42307.19-42307.102" + wire $and$libresoc.v:42307$2007_Y attribute \src "libresoc.v:42308.19-42308.127" - wire $and$libresoc.v:42308$2010_Y - attribute \src "libresoc.v:42309.19-42309.112" - wire $and$libresoc.v:42309$2011_Y - attribute \src "libresoc.v:42311.19-42311.102" - wire $and$libresoc.v:42311$2013_Y - attribute \src "libresoc.v:42312.19-42312.127" - wire $and$libresoc.v:42312$2014_Y + wire $and$libresoc.v:42308$2008_Y + attribute \src "libresoc.v:42310.19-42310.127" + wire $and$libresoc.v:42310$2010_Y + attribute \src "libresoc.v:42311.19-42311.112" + wire $and$libresoc.v:42311$2011_Y + attribute \src "libresoc.v:42313.19-42313.102" + wire $and$libresoc.v:42313$2013_Y attribute \src "libresoc.v:42314.19-42314.127" - wire $and$libresoc.v:42314$2016_Y - attribute \src "libresoc.v:42315.19-42315.112" - wire $and$libresoc.v:42315$2017_Y - attribute \src "libresoc.v:42317.19-42317.102" - wire $and$libresoc.v:42317$2019_Y - attribute \src "libresoc.v:42318.19-42318.127" - wire $and$libresoc.v:42318$2020_Y + wire $and$libresoc.v:42314$2014_Y + attribute \src "libresoc.v:42316.19-42316.127" + wire $and$libresoc.v:42316$2016_Y + attribute \src "libresoc.v:42317.19-42317.112" + wire $and$libresoc.v:42317$2017_Y + attribute \src "libresoc.v:42319.19-42319.102" + wire $and$libresoc.v:42319$2019_Y attribute \src "libresoc.v:42320.19-42320.127" - wire $and$libresoc.v:42320$2022_Y - attribute \src "libresoc.v:42321.19-42321.112" - wire $and$libresoc.v:42321$2023_Y - attribute \src "libresoc.v:42323.19-42323.102" - wire $and$libresoc.v:42323$2025_Y - attribute \src "libresoc.v:42324.19-42324.127" - wire $and$libresoc.v:42324$2026_Y - attribute \src "libresoc.v:42334.19-42334.127" - wire $and$libresoc.v:42334$2036_Y - attribute \src "libresoc.v:42335.19-42335.112" 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$ternary$libresoc.v:42087$1785_Y + attribute \src "libresoc.v:42107.20-42107.112" + wire $ternary$libresoc.v:42107$1805_Y + attribute \src "libresoc.v:42113.20-42113.112" + wire $ternary$libresoc.v:42113$1811_Y + attribute \src "libresoc.v:42125.20-42125.112" + wire width 2 $ternary$libresoc.v:42125$1824_Y + attribute \src "libresoc.v:42133.20-42133.120" + wire width 10 $ternary$libresoc.v:42133$1833_Y + attribute \src "libresoc.v:42222.19-42222.124" + wire width 7 $ternary$libresoc.v:42222$1922_Y + attribute \src "libresoc.v:42228.19-42228.123" + wire width 7 $ternary$libresoc.v:42228$1928_Y + attribute \src "libresoc.v:42234.19-42234.125" + wire width 7 $ternary$libresoc.v:42234$1934_Y + attribute \src "libresoc.v:42240.19-42240.128" + wire width 7 $ternary$libresoc.v:42240$1940_Y + attribute \src "libresoc.v:42246.19-42246.124" + wire width 7 $ternary$libresoc.v:42246$1946_Y + attribute \src "libresoc.v:42252.19-42252.124" + wire width 7 $ternary$libresoc.v:42252$1952_Y + attribute \src "libresoc.v:42258.19-42258.124" + wire width 7 $ternary$libresoc.v:42258$1958_Y + attribute \src "libresoc.v:42264.19-42264.129" + wire width 7 $ternary$libresoc.v:42264$1964_Y + attribute \src "libresoc.v:42270.19-42270.125" + wire width 7 $ternary$libresoc.v:42270$1970_Y + attribute \src "libresoc.v:42285.19-42285.124" + wire width 7 $ternary$libresoc.v:42285$1985_Y + attribute \src "libresoc.v:42291.19-42291.123" + wire width 7 $ternary$libresoc.v:42291$1991_Y + attribute \src "libresoc.v:42297.19-42297.125" + wire width 7 $ternary$libresoc.v:42297$1997_Y + attribute \src "libresoc.v:42303.19-42303.128" + wire width 7 $ternary$libresoc.v:42303$2003_Y + attribute \src "libresoc.v:42309.19-42309.124" + wire width 7 $ternary$libresoc.v:42309$2009_Y + attribute \src "libresoc.v:42315.19-42315.124" + wire width 7 $ternary$libresoc.v:42315$2015_Y + attribute \src "libresoc.v:42321.19-42321.129" + wire width 7 $ternary$libresoc.v:42321$2021_Y + attribute \src "libresoc.v:42327.19-42327.125" + wire width 7 $ternary$libresoc.v:42327$2027_Y + attribute \src "libresoc.v:42341.19-42341.129" + wire width 7 $ternary$libresoc.v:42341$2041_Y + attribute \src "libresoc.v:42347.19-42347.125" + wire width 7 $ternary$libresoc.v:42347$2047_Y + attribute \src "libresoc.v:42361.19-42361.122" + wire $ternary$libresoc.v:42361$2061_Y + attribute \src "libresoc.v:42367.19-42367.126" + wire $ternary$libresoc.v:42367$2067_Y + attribute \src "libresoc.v:42373.19-42373.122" + wire $ternary$libresoc.v:42373$2073_Y + attribute \src "libresoc.v:42379.19-42379.122" + wire $ternary$libresoc.v:42379$2079_Y + attribute \src "libresoc.v:42385.19-42385.122" + wire $ternary$libresoc.v:42385$2085_Y + attribute \src "libresoc.v:42391.19-42391.127" + wire $ternary$libresoc.v:42391$2091_Y + attribute \src "libresoc.v:42407.19-42407.122" + wire width 2 $ternary$libresoc.v:42407$2108_Y + attribute \src "libresoc.v:42413.19-42413.122" + wire width 2 $ternary$libresoc.v:42413$2114_Y + attribute \src "libresoc.v:42419.19-42419.127" + wire width 2 $ternary$libresoc.v:42419$2120_Y + attribute \src "libresoc.v:42432.19-42432.122" + wire width 3 $ternary$libresoc.v:42432$2134_Y + attribute \src "libresoc.v:42438.19-42438.133" + wire width 8 $ternary$libresoc.v:42438$2140_Y + attribute \src "libresoc.v:42446.19-42446.185" + wire width 256 $ternary$libresoc.v:42446$2148_Y + attribute \src "libresoc.v:42454.19-42454.189" + wire width 256 $ternary$libresoc.v:42454$2156_Y + attribute \src "libresoc.v:42463.19-42463.185" + wire width 256 $ternary$libresoc.v:42463$2165_Y + attribute \src "libresoc.v:42471.19-42471.185" + wire width 256 $ternary$libresoc.v:42471$2173_Y + attribute \src "libresoc.v:42477.19-42477.131" + wire width 3 $ternary$libresoc.v:42477$2179_Y + attribute \src "libresoc.v:42483.19-42483.129" + wire width 3 $ternary$libresoc.v:42483$2185_Y + attribute \src "libresoc.v:42489.19-42489.128" + wire width 3 $ternary$libresoc.v:42489$2191_Y + attribute \src "libresoc.v:42498.19-42498.131" + wire width 3 $ternary$libresoc.v:42498$2200_Y + attribute \src "libresoc.v:42504.19-42504.129" + wire width 3 $ternary$libresoc.v:42504$2206_Y + attribute \src "libresoc.v:42512.19-42512.128" + wire width 10 $ternary$libresoc.v:42512$2214_Y + attribute \src "libresoc.v:42529.19-42529.110" + wire width 7 $ternary$libresoc.v:42529$2231_Y + attribute \src "libresoc.v:42535.19-42535.116" + wire width 7 $ternary$libresoc.v:42535$2237_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" wire \$1000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" @@ -61924,7 +61924,7 @@ module \core wire width 3 input 32 \core_fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 input 33 \core_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 65 \core_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 input 18 \core_reg1 @@ -62006,7 +62006,8 @@ module \core attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -62123,7 +62124,8 @@ module \core attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -62173,16 +62175,16 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 10 input 24 \core_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" - wire output 13 \core_terminate_o + wire output 14 \core_terminate_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire \core_terminate_o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" wire width 3 input 27 \core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:95" wire output 2 \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 96 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" wire width 2 \counter @@ -62221,9 +62223,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire output 3 \cu_st__rel_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 10 \data_i + wire width 64 input 12 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 72 \data_i$11 + wire width 64 input 69 \data_i$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 88 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" @@ -65123,13 +65125,13 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 84 \issue__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" - wire input 69 \issue_i + wire input 71 \issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" - wire input 68 \ivalid_i + wire input 70 \ivalid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 14 \msr__data_o + wire width 64 output 15 \msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 12 \msr__ren + wire width 3 input 13 \msr__ren attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" @@ -65415,19 +65417,19 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \state_data_i$174 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 output 70 \state_nia_wen + wire width 3 output 72 \state_nia_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \state_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 15 \sv__data_o + wire width 64 output 10 \sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 11 \sv__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire width 3 input 9 \sv__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 86 \wb_dcache_en attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 9 \wen + wire width 3 input 11 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 71 \wen$10 + wire width 3 input 68 \wen$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" wire \wp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" @@ -65957,7 +65959,7 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_wen$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41809$1506 + cell $and $and$libresoc.v:41811$1506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65965,10 +65967,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$95 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:41809$1506_Y + connect \Y $and$libresoc.v:41811$1506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41810$1507 + cell $and $and$libresoc.v:41812$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65976,10 +65978,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41810$1507_Y + connect \Y $and$libresoc.v:41812$1507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41812$1509 + cell $and $and$libresoc.v:41814$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65987,10 +65989,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1002 connect \B \$1007 - connect \Y $and$libresoc.v:41812$1509_Y + connect \Y $and$libresoc.v:41814$1509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41813$1510 + cell $and $and$libresoc.v:41815$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -65998,10 +66000,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1002 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41813$1510_Y + connect \Y $and$libresoc.v:41815$1510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41815$1512 + cell $and $and$libresoc.v:41817$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66009,10 +66011,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$98 connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:41815$1512_Y + connect \Y $and$libresoc.v:41817$1512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41816$1513 + cell $and $and$libresoc.v:41818$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66020,10 +66022,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41816$1513_Y + connect \Y $and$libresoc.v:41818$1513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41818$1515 + cell $and $and$libresoc.v:41820$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66031,10 +66033,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1023 connect \B \$1028 - connect \Y $and$libresoc.v:41818$1515_Y + connect \Y $and$libresoc.v:41820$1515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41819$1516 + cell $and $and$libresoc.v:41821$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66042,10 +66044,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1023 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41819$1516_Y + connect \Y $and$libresoc.v:41821$1516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41821$1518 + cell $and $and$libresoc.v:41823$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66053,10 +66055,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$101 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:41821$1518_Y + connect \Y $and$libresoc.v:41823$1518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41822$1519 + cell $and $and$libresoc.v:41824$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66064,10 +66066,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41822$1519_Y + connect \Y $and$libresoc.v:41824$1519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41824$1521 + cell $and $and$libresoc.v:41826$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66075,10 +66077,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1041 connect \B \$1046 - connect \Y $and$libresoc.v:41824$1521_Y + connect \Y $and$libresoc.v:41826$1521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41825$1522 + cell $and $and$libresoc.v:41827$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66086,10 +66088,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1041 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41825$1522_Y + connect \Y $and$libresoc.v:41827$1522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41827$1524 + cell $and $and$libresoc.v:41829$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66097,10 +66099,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$104 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:41827$1524_Y + connect \Y $and$libresoc.v:41829$1524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41828$1525 + cell $and $and$libresoc.v:41830$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66108,10 +66110,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41828$1525_Y + connect \Y $and$libresoc.v:41830$1525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41830$1527 + cell $and $and$libresoc.v:41832$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66119,10 +66121,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1063 connect \B \$1068 - connect \Y $and$libresoc.v:41830$1527_Y + connect \Y $and$libresoc.v:41832$1527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41831$1528 + cell $and $and$libresoc.v:41833$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66130,10 +66132,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1063 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41831$1528_Y + connect \Y $and$libresoc.v:41833$1528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41833$1530 + cell $and $and$libresoc.v:41835$1530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66141,10 +66143,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$107 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:41833$1530_Y + connect \Y $and$libresoc.v:41835$1530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41834$1531 + cell $and $and$libresoc.v:41836$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66152,10 +66154,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41834$1531_Y + connect \Y $and$libresoc.v:41836$1531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41836$1533 + cell $and $and$libresoc.v:41838$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66163,10 +66165,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1083 connect \B \$1088 - connect \Y $and$libresoc.v:41836$1533_Y + connect \Y $and$libresoc.v:41838$1533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41837$1534 + cell $and $and$libresoc.v:41839$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66174,10 +66176,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1083 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41837$1534_Y + connect \Y $and$libresoc.v:41839$1534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41839$1536 + cell $and $and$libresoc.v:41841$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66185,10 +66187,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$110 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:41839$1536_Y + connect \Y $and$libresoc.v:41841$1536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41840$1537 + cell $and $and$libresoc.v:41842$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66196,10 +66198,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [7] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41840$1537_Y + connect \Y $and$libresoc.v:41842$1537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41842$1539 + cell $and $and$libresoc.v:41844$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66207,10 +66209,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1103 connect \B \$1108 - connect \Y $and$libresoc.v:41842$1539_Y + connect \Y $and$libresoc.v:41844$1539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41843$1540 + cell $and $and$libresoc.v:41845$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66218,10 +66220,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1103 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41843$1540_Y + connect \Y $and$libresoc.v:41845$1540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41845$1542 + cell $and $and$libresoc.v:41847$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66229,10 +66231,10 @@ module \core parameter \Y_WIDTH 1 connect \A \o_ok connect \B \fus_cu_busy_o$38 - connect \Y $and$libresoc.v:41845$1542_Y + connect \Y $and$libresoc.v:41847$1542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41846$1543 + cell $and $and$libresoc.v:41848$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66240,10 +66242,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [8] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41846$1543_Y + connect \Y $and$libresoc.v:41848$1543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41848$1545 + cell $and $and$libresoc.v:41850$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66251,10 +66253,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1122 connect \B \$1127 - connect \Y $and$libresoc.v:41848$1545_Y + connect \Y $and$libresoc.v:41850$1545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41849$1546 + cell $and $and$libresoc.v:41851$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66262,10 +66264,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1122 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41849$1546_Y + connect \Y $and$libresoc.v:41851$1546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41851$1548 + cell $and $and$libresoc.v:41853$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66273,10 +66275,10 @@ module \core parameter \Y_WIDTH 1 connect \A \ea_ok connect \B \fus_cu_busy_o$38 - connect \Y $and$libresoc.v:41851$1548_Y + connect \Y $and$libresoc.v:41853$1548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41852$1549 + cell $and $and$libresoc.v:41854$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66284,10 +66286,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [9] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41852$1549_Y + connect \Y $and$libresoc.v:41854$1549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41854$1551 + cell $and $and$libresoc.v:41856$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66295,10 +66297,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1140 connect \B \$1144 - connect \Y $and$libresoc.v:41854$1551_Y + connect \Y $and$libresoc.v:41856$1551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41855$1552 + cell $and $and$libresoc.v:41857$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66306,10 +66308,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1140 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41855$1552_Y + connect \Y $and$libresoc.v:41857$1552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41884$1581 + cell $and $and$libresoc.v:41886$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66317,10 +66319,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_full_cr_ok connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:41884$1581_Y + connect \Y $and$libresoc.v:41886$1581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41885$1582 + cell $and $and$libresoc.v:41887$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66328,10 +66330,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41885$1582_Y + connect \Y $and$libresoc.v:41887$1582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41886$1583 + cell $and $and$libresoc.v:41888$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66339,10 +66341,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:41886$1583_Y + connect \Y $and$libresoc.v:41888$1583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41888$1585 + cell $and $and$libresoc.v:41890$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66350,10 +66352,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1214 connect \B \$1218 - connect \Y $and$libresoc.v:41888$1585_Y + connect \Y $and$libresoc.v:41890$1585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41889$1586 + cell $and $and$libresoc.v:41891$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66361,10 +66363,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1214 connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:41889$1586_Y + connect \Y $and$libresoc.v:41891$1586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41891$1588 + cell $and $and$libresoc.v:41893$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66372,10 +66374,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41891$1588_Y + connect \Y $and$libresoc.v:41893$1588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41892$1589 + cell $and $and$libresoc.v:41894$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66383,10 +66385,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41892$1589_Y + connect \Y $and$libresoc.v:41894$1589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41893$1590 + cell $and $and$libresoc.v:41895$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66394,10 +66396,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:41893$1590_Y + connect \Y $and$libresoc.v:41895$1590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41894$1591 + cell $and $and$libresoc.v:41896$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66405,10 +66407,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:41894$1591_Y + connect \Y $and$libresoc.v:41896$1591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41895$1592 + cell $and $and$libresoc.v:41897$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66416,10 +66418,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41895$1592_Y + connect \Y $and$libresoc.v:41897$1592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41896$1593 + cell $and $and$libresoc.v:41898$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66427,10 +66429,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41896$1593_Y + connect \Y $and$libresoc.v:41898$1593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41897$1594 + cell $and $and$libresoc.v:41899$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66438,10 +66440,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41897$1594_Y + connect \Y $and$libresoc.v:41899$1594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41898$1595 + cell $and $and$libresoc.v:41900$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66449,10 +66451,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41898$1595_Y + connect \Y $and$libresoc.v:41900$1595_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41900$1597 + cell $and $and$libresoc.v:41902$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66460,10 +66462,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1242 connect \B \$1246 - connect \Y $and$libresoc.v:41900$1597_Y + connect \Y $and$libresoc.v:41902$1597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41901$1598 + cell $and $and$libresoc.v:41903$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66471,10 +66473,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1242 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41901$1598_Y + connect \Y $and$libresoc.v:41903$1598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41905$1602 + cell $and $and$libresoc.v:41907$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66482,10 +66484,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$122 connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:41905$1602_Y + connect \Y $and$libresoc.v:41907$1602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41906$1603 + cell $and $and$libresoc.v:41908$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66493,10 +66495,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41906$1603_Y + connect \Y $and$libresoc.v:41908$1603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41908$1605 + cell $and $and$libresoc.v:41910$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66504,10 +66506,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1262 connect \B \$1266 - connect \Y $and$libresoc.v:41908$1605_Y + connect \Y $and$libresoc.v:41910$1605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41909$1606 + cell $and $and$libresoc.v:41911$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66515,10 +66517,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1262 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41909$1606_Y + connect \Y $and$libresoc.v:41911$1606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41913$1610 + cell $and $and$libresoc.v:41915$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66526,10 +66528,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$123 connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:41913$1610_Y + connect \Y $and$libresoc.v:41915$1610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41914$1611 + cell $and $and$libresoc.v:41916$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66537,10 +66539,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41914$1611_Y + connect \Y $and$libresoc.v:41916$1611_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41916$1613 + cell $and $and$libresoc.v:41918$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66548,10 +66550,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1282 connect \B \$1286 - connect \Y $and$libresoc.v:41916$1613_Y + connect \Y $and$libresoc.v:41918$1613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41917$1614 + cell $and $and$libresoc.v:41919$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66559,10 +66561,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1282 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41917$1614_Y + connect \Y $and$libresoc.v:41919$1614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41921$1618 + cell $and $and$libresoc.v:41923$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66570,10 +66572,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$124 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:41921$1618_Y + connect \Y $and$libresoc.v:41923$1618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41922$1619 + cell $and $and$libresoc.v:41924$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66581,10 +66583,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41922$1619_Y + connect \Y $and$libresoc.v:41924$1619_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41924$1621 + cell $and $and$libresoc.v:41926$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66592,10 +66594,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1302 connect \B \$1306 - connect \Y $and$libresoc.v:41924$1621_Y + connect \Y $and$libresoc.v:41926$1621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41925$1622 + cell $and $and$libresoc.v:41927$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66603,10 +66605,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1302 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41925$1622_Y + connect \Y $and$libresoc.v:41927$1622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41929$1626 + cell $and $and$libresoc.v:41931$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66614,10 +66616,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$125 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:41929$1626_Y + connect \Y $and$libresoc.v:41931$1626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41930$1627 + cell $and $and$libresoc.v:41932$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66625,10 +66627,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [4] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41930$1627_Y + connect \Y $and$libresoc.v:41932$1627_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41932$1629 + cell $and $and$libresoc.v:41934$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66636,10 +66638,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1322 connect \B \$1326 - connect \Y $and$libresoc.v:41932$1629_Y + connect \Y $and$libresoc.v:41934$1629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41933$1630 + cell $and $and$libresoc.v:41935$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66647,10 +66649,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1322 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41933$1630_Y + connect \Y $and$libresoc.v:41935$1630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41937$1634 + cell $and $and$libresoc.v:41939$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66658,10 +66660,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$126 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:41937$1634_Y + connect \Y $and$libresoc.v:41939$1634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41938$1635 + cell $and $and$libresoc.v:41940$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66669,10 +66671,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [5] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41938$1635_Y + connect \Y $and$libresoc.v:41940$1635_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41940$1637 + cell $and $and$libresoc.v:41942$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66680,10 +66682,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1342 connect \B \$1346 - connect \Y $and$libresoc.v:41940$1637_Y + connect \Y $and$libresoc.v:41942$1637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41941$1638 + cell $and $and$libresoc.v:41943$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66691,10 +66693,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1342 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:41941$1638_Y + connect \Y $and$libresoc.v:41943$1638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41955$1652 + cell $and $and$libresoc.v:41957$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66702,10 +66704,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41955$1652_Y + connect \Y $and$libresoc.v:41957$1652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41956$1653 + cell $and $and$libresoc.v:41958$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66713,10 +66715,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41956$1653_Y + connect \Y $and$libresoc.v:41958$1653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41957$1654 + cell $and $and$libresoc.v:41959$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66724,10 +66726,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41957$1654_Y + connect \Y $and$libresoc.v:41959$1654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41958$1655 + cell $and $and$libresoc.v:41960$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66735,10 +66737,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:41958$1655_Y + connect \Y $and$libresoc.v:41960$1655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41959$1656 + cell $and $and$libresoc.v:41961$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66746,10 +66748,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41959$1656_Y + connect \Y $and$libresoc.v:41961$1656_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41961$1658 + cell $and $and$libresoc.v:41963$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66757,10 +66759,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1389 connect \B \$1393 - connect \Y $and$libresoc.v:41961$1658_Y + connect \Y $and$libresoc.v:41963$1658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41962$1659 + cell $and $and$libresoc.v:41964$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66768,10 +66770,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1389 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41962$1659_Y + connect \Y $and$libresoc.v:41964$1659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41964$1661 + cell $and $and$libresoc.v:41966$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66779,10 +66781,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$132 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:41964$1661_Y + connect \Y $and$libresoc.v:41966$1661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41965$1662 + cell $and $and$libresoc.v:41967$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66790,10 +66792,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41965$1662_Y + connect \Y $and$libresoc.v:41967$1662_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41967$1664 + cell $and $and$libresoc.v:41969$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66801,10 +66803,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1405 connect \B \$1409 - connect \Y $and$libresoc.v:41967$1664_Y + connect \Y $and$libresoc.v:41969$1664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41968$1665 + cell $and $and$libresoc.v:41970$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66812,10 +66814,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1405 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41968$1665_Y + connect \Y $and$libresoc.v:41970$1665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41970$1667 + cell $and $and$libresoc.v:41972$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66823,10 +66825,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$133 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:41970$1667_Y + connect \Y $and$libresoc.v:41972$1667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41971$1668 + cell $and $and$libresoc.v:41973$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66834,10 +66836,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41971$1668_Y + connect \Y $and$libresoc.v:41973$1668_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41973$1670 + cell $and $and$libresoc.v:41975$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66845,10 +66847,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1421 connect \B \$1425 - connect \Y $and$libresoc.v:41973$1670_Y + connect \Y $and$libresoc.v:41975$1670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41974$1671 + cell $and $and$libresoc.v:41976$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66856,10 +66858,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1421 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:41974$1671_Y + connect \Y $and$libresoc.v:41976$1671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41981$1679 + cell $and $and$libresoc.v:41983$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66867,10 +66869,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:41981$1679_Y + connect \Y $and$libresoc.v:41983$1679_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41982$1680 + cell $and $and$libresoc.v:41984$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66878,10 +66880,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:41982$1680_Y + connect \Y $and$libresoc.v:41984$1680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41983$1681 + cell $and $and$libresoc.v:41985$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66889,10 +66891,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:41983$1681_Y + connect \Y $and$libresoc.v:41985$1681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41984$1682 + cell $and $and$libresoc.v:41986$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66900,10 +66902,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:41984$1682_Y + connect \Y $and$libresoc.v:41986$1682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:41985$1683 + cell $and $and$libresoc.v:41987$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66911,10 +66913,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:41985$1683_Y + connect \Y $and$libresoc.v:41987$1683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41986$1684 + cell $and $and$libresoc.v:41988$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66922,10 +66924,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41986$1684_Y + connect \Y $and$libresoc.v:41988$1684_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41988$1686 + cell $and $and$libresoc.v:41990$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66933,10 +66935,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1455 connect \B \$1459 - connect \Y $and$libresoc.v:41988$1686_Y + connect \Y $and$libresoc.v:41990$1686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41989$1687 + cell $and $and$libresoc.v:41991$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66944,10 +66946,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1455 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41989$1687_Y + connect \Y $and$libresoc.v:41991$1687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41991$1689 + cell $and $and$libresoc.v:41993$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66955,10 +66957,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$136 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:41991$1689_Y + connect \Y $and$libresoc.v:41993$1689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41992$1690 + cell $and $and$libresoc.v:41994$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66966,10 +66968,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [1] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41992$1690_Y + connect \Y $and$libresoc.v:41994$1690_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:41994$1692 + cell $and $and$libresoc.v:41996$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66977,10 +66979,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1471 connect \B \$1475 - connect \Y $and$libresoc.v:41994$1692_Y + connect \Y $and$libresoc.v:41996$1692_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:41995$1693 + cell $and $and$libresoc.v:41997$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66988,10 +66990,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1471 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41995$1693_Y + connect \Y $and$libresoc.v:41997$1693_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:41997$1695 + cell $and $and$libresoc.v:41999$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66999,10 +67001,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$137 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:41997$1695_Y + connect \Y $and$libresoc.v:41999$1695_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:41998$1696 + cell $and $and$libresoc.v:42000$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67010,10 +67012,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [2] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:41998$1696_Y + connect \Y $and$libresoc.v:42000$1696_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42000$1698 + cell $and $and$libresoc.v:42002$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67021,10 +67023,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1487 connect \B \$1491 - connect \Y $and$libresoc.v:42000$1698_Y + connect \Y $and$libresoc.v:42002$1698_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42001$1699 + cell $and $and$libresoc.v:42003$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67032,10 +67034,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1487 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42001$1699_Y + connect \Y $and$libresoc.v:42003$1699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42003$1701 + cell $and $and$libresoc.v:42005$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67043,10 +67045,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$138 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42003$1701_Y + connect \Y $and$libresoc.v:42005$1701_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42004$1702 + cell $and $and$libresoc.v:42006$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67054,10 +67056,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [3] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42004$1702_Y + connect \Y $and$libresoc.v:42006$1702_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42006$1704 + cell $and $and$libresoc.v:42008$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67065,10 +67067,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1503 connect \B \$1507 - connect \Y $and$libresoc.v:42006$1704_Y + connect \Y $and$libresoc.v:42008$1704_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42007$1705 + cell $and $and$libresoc.v:42009$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67076,10 +67078,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1503 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42007$1705_Y + connect \Y $and$libresoc.v:42009$1705_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42015$1713 + cell $and $and$libresoc.v:42017$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67087,10 +67089,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42015$1713_Y + connect \Y $and$libresoc.v:42017$1713_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42016$1714 + cell $and $and$libresoc.v:42018$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67098,10 +67100,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [4] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42016$1714_Y + connect \Y $and$libresoc.v:42018$1714_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42017$1715 + cell $and $and$libresoc.v:42019$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67109,10 +67111,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42017$1715_Y + connect \Y $and$libresoc.v:42019$1715_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42018$1716 + cell $and $and$libresoc.v:42020$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67120,10 +67122,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [3] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42018$1716_Y + connect \Y $and$libresoc.v:42020$1716_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42019$1717 + cell $and $and$libresoc.v:42021$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67131,10 +67133,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [3] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42019$1717_Y + connect \Y $and$libresoc.v:42021$1717_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42020$1718 + cell $and $and$libresoc.v:42022$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67142,10 +67144,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42020$1718_Y + connect \Y $and$libresoc.v:42022$1718_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42022$1720 + cell $and $and$libresoc.v:42024$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67153,10 +67155,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1539 connect \B \$1543 - connect \Y $and$libresoc.v:42022$1720_Y + connect \Y $and$libresoc.v:42024$1720_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42023$1721 + cell $and $and$libresoc.v:42025$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67164,10 +67166,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1539 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42023$1721_Y + connect \Y $and$libresoc.v:42025$1721_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42025$1723 + cell $and $and$libresoc.v:42027$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67175,10 +67177,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$141 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42025$1723_Y + connect \Y $and$libresoc.v:42027$1723_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42026$1724 + cell $and $and$libresoc.v:42028$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67186,10 +67188,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [1] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42026$1724_Y + connect \Y $and$libresoc.v:42028$1724_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42028$1726 + cell $and $and$libresoc.v:42030$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67197,10 +67199,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1555 connect \B \$1559 - connect \Y $and$libresoc.v:42028$1726_Y + connect \Y $and$libresoc.v:42030$1726_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42029$1727 + cell $and $and$libresoc.v:42031$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67208,10 +67210,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1555 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42029$1727_Y + connect \Y $and$libresoc.v:42031$1727_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42031$1729 + cell $and $and$libresoc.v:42033$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67219,10 +67221,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$142 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42031$1729_Y + connect \Y $and$libresoc.v:42033$1729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42032$1730 + cell $and $and$libresoc.v:42034$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67230,10 +67232,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [2] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42032$1730_Y + connect \Y $and$libresoc.v:42034$1730_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42034$1732 + cell $and $and$libresoc.v:42036$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67241,10 +67243,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1571 connect \B \$1575 - connect \Y $and$libresoc.v:42034$1732_Y + connect \Y $and$libresoc.v:42036$1732_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42035$1733 + cell $and $and$libresoc.v:42037$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67252,10 +67254,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1571 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42035$1733_Y + connect \Y $and$libresoc.v:42037$1733_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42037$1735 + cell $and $and$libresoc.v:42039$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67263,10 +67265,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$143 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42037$1735_Y + connect \Y $and$libresoc.v:42039$1735_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42038$1736 + cell $and $and$libresoc.v:42040$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67274,10 +67276,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [3] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42038$1736_Y + connect \Y $and$libresoc.v:42040$1736_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42040$1738 + cell $and $and$libresoc.v:42042$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67285,10 +67287,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1587 connect \B \$1591 - connect \Y $and$libresoc.v:42040$1738_Y + connect \Y $and$libresoc.v:42042$1738_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42041$1739 + cell $and $and$libresoc.v:42043$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67296,10 +67298,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1587 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42041$1739_Y + connect \Y $and$libresoc.v:42043$1739_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42051$1751 + cell $and $and$libresoc.v:42053$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67307,10 +67309,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42051$1751_Y + connect \Y $and$libresoc.v:42053$1751_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42052$1752 + cell $and $and$libresoc.v:42054$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67318,10 +67320,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42052$1752_Y + connect \Y $and$libresoc.v:42054$1752_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42053$1753 + cell $and $and$libresoc.v:42055$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67329,10 +67331,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42053$1753_Y + connect \Y $and$libresoc.v:42055$1753_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42054$1754 + cell $and $and$libresoc.v:42056$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67340,10 +67342,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42054$1754_Y + connect \Y $and$libresoc.v:42056$1754_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42055$1755 + cell $and $and$libresoc.v:42057$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67351,10 +67353,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42055$1755_Y + connect \Y $and$libresoc.v:42057$1755_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42056$1756 + cell $and $and$libresoc.v:42058$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67362,10 +67364,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42056$1756_Y + connect \Y $and$libresoc.v:42058$1756_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42057$1757 + cell $and $and$libresoc.v:42059$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67373,10 +67375,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [0] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42057$1757_Y + connect \Y $and$libresoc.v:42059$1757_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42059$1759 + cell $and $and$libresoc.v:42061$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67384,10 +67386,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1629 connect \B \$1634 - connect \Y $and$libresoc.v:42059$1759_Y + connect \Y $and$libresoc.v:42061$1759_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42060$1760 + cell $and $and$libresoc.v:42062$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67395,10 +67397,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1629 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42060$1760_Y + connect \Y $and$libresoc.v:42062$1760_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42062$1762 + cell $and $and$libresoc.v:42064$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67406,10 +67408,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$150 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42062$1762_Y + connect \Y $and$libresoc.v:42064$1762_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42063$1763 + cell $and $and$libresoc.v:42065$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67417,10 +67419,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [1] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42063$1763_Y + connect \Y $and$libresoc.v:42065$1763_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42065$1765 + cell $and $and$libresoc.v:42067$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67428,10 +67430,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1648 connect \B \$1652 - connect \Y $and$libresoc.v:42065$1765_Y + connect \Y $and$libresoc.v:42067$1765_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42066$1766 + cell $and $and$libresoc.v:42068$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67439,10 +67441,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1648 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42066$1766_Y + connect \Y $and$libresoc.v:42068$1766_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42068$1768 + cell $and $and$libresoc.v:42070$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67450,10 +67452,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$151 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42068$1768_Y + connect \Y $and$libresoc.v:42070$1768_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42069$1769 + cell $and $and$libresoc.v:42071$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67461,10 +67463,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [2] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42069$1769_Y + connect \Y $and$libresoc.v:42071$1769_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42071$1771 + cell $and $and$libresoc.v:42073$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67472,10 +67474,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1664 connect \B \$1668 - connect \Y $and$libresoc.v:42071$1771_Y + connect \Y $and$libresoc.v:42073$1771_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42072$1772 + cell $and $and$libresoc.v:42074$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67483,10 +67485,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1664 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42072$1772_Y + connect \Y $and$libresoc.v:42074$1772_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42074$1774 + cell $and $and$libresoc.v:42076$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67494,10 +67496,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42074$1774_Y + connect \Y $and$libresoc.v:42076$1774_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42075$1775 + cell $and $and$libresoc.v:42077$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67505,10 +67507,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [3] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42075$1775_Y + connect \Y $and$libresoc.v:42077$1775_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42077$1777 + cell $and $and$libresoc.v:42079$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67516,10 +67518,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1680 connect \B \$1684 - connect \Y $and$libresoc.v:42077$1777_Y + connect \Y $and$libresoc.v:42079$1777_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42078$1778 + cell $and $and$libresoc.v:42080$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67527,10 +67529,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1680 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42078$1778_Y + connect \Y $and$libresoc.v:42080$1778_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42080$1780 + cell $and $and$libresoc.v:42082$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67538,10 +67540,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok$152 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42080$1780_Y + connect \Y $and$libresoc.v:42082$1780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42081$1781 + cell $and $and$libresoc.v:42083$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67549,10 +67551,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [4] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42081$1781_Y + connect \Y $and$libresoc.v:42083$1781_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42083$1783 + cell $and $and$libresoc.v:42085$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67560,10 +67562,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1696 connect \B \$1700 - connect \Y $and$libresoc.v:42083$1783_Y + connect \Y $and$libresoc.v:42085$1783_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42084$1784 + cell $and $and$libresoc.v:42086$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67571,10 +67573,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1696 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42084$1784_Y + connect \Y $and$libresoc.v:42086$1784_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42098$1798 + cell $and $and$libresoc.v:42100$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67582,10 +67584,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42098$1798_Y + connect \Y $and$libresoc.v:42100$1798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42099$1799 + cell $and $and$libresoc.v:42101$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67593,10 +67595,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42099$1799_Y + connect \Y $and$libresoc.v:42101$1799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42100$1800 + cell $and $and$libresoc.v:42102$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67604,10 +67606,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42100$1800_Y + connect \Y $and$libresoc.v:42102$1800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42101$1801 + cell $and $and$libresoc.v:42103$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67615,10 +67617,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [0] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42101$1801_Y + connect \Y $and$libresoc.v:42103$1801_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42103$1803 + cell $and $and$libresoc.v:42105$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67626,10 +67628,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1740 connect \B \$1744 - connect \Y $and$libresoc.v:42103$1803_Y + connect \Y $and$libresoc.v:42105$1803_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42104$1804 + cell $and $and$libresoc.v:42106$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67637,10 +67639,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1740 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42104$1804_Y + connect \Y $and$libresoc.v:42106$1804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42106$1806 + cell $and $and$libresoc.v:42108$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67648,10 +67650,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok$158 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42106$1806_Y + connect \Y $and$libresoc.v:42108$1806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42107$1807 + cell $and $and$libresoc.v:42109$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67659,10 +67661,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [1] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42107$1807_Y + connect \Y $and$libresoc.v:42109$1807_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42109$1809 + cell $and $and$libresoc.v:42111$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67670,10 +67672,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1756 connect \B \$1760 - connect \Y $and$libresoc.v:42109$1809_Y + connect \Y $and$libresoc.v:42111$1809_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42110$1810 + cell $and $and$libresoc.v:42112$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67681,10 +67683,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1756 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42110$1810_Y + connect \Y $and$libresoc.v:42112$1810_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42115$1816 + cell $and $and$libresoc.v:42117$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67692,10 +67694,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_msr_ok connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42115$1816_Y + connect \Y $and$libresoc.v:42117$1816_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42116$1817 + cell $and $and$libresoc.v:42118$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67703,10 +67705,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [4] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42116$1817_Y + connect \Y $and$libresoc.v:42118$1817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42117$1818 + cell $and $and$libresoc.v:42119$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -67714,10 +67716,10 @@ module \core parameter \Y_WIDTH 13 connect \A \core_core_fn_unit connect \B 2'10 - connect \Y $and$libresoc.v:42117$1818_Y + connect \Y $and$libresoc.v:42119$1818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42118$1819 + cell $and $and$libresoc.v:42120$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67725,10 +67727,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_msr_o connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:42118$1819_Y + connect \Y $and$libresoc.v:42120$1819_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42120$1821 + cell $and $and$libresoc.v:42122$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67736,10 +67738,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1780 connect \B \$1784 - connect \Y $and$libresoc.v:42120$1821_Y + connect \Y $and$libresoc.v:42122$1821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42122$1823 + cell $and $and$libresoc.v:42124$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67747,10 +67749,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1780 connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:42122$1823_Y + connect \Y $and$libresoc.v:42124$1823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42125$1827 + cell $and $and$libresoc.v:42127$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67758,10 +67760,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_spr1_ok connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42125$1827_Y + connect \Y $and$libresoc.v:42127$1827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42126$1828 + cell $and $and$libresoc.v:42128$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67769,10 +67771,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42126$1828_Y + connect \Y $and$libresoc.v:42128$1828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42127$1829 + cell $and $and$libresoc.v:42129$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67780,10 +67782,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_SPR_spr1_o connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42127$1829_Y + connect \Y $and$libresoc.v:42129$1829_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42129$1831 + cell $and $and$libresoc.v:42131$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67791,10 +67793,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1800 connect \B \$1804 - connect \Y $and$libresoc.v:42129$1831_Y + connect \Y $and$libresoc.v:42131$1831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42130$1832 + cell $and $and$libresoc.v:42132$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67802,10 +67804,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1800 connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42130$1832_Y + connect \Y $and$libresoc.v:42132$1832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42132$1834 + cell $and $and$libresoc.v:42134$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -67813,10 +67815,10 @@ module \core parameter \Y_WIDTH 13 connect \A \core_core_fn_unit connect \B 7'1000000 - connect \Y $and$libresoc.v:42132$1834_Y + connect \Y $and$libresoc.v:42134$1834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42134$1836 + cell $and $and$libresoc.v:42136$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -67824,10 +67826,10 @@ module \core parameter \Y_WIDTH 13 connect \A \core_core_fn_unit connect \B 6'100000 - connect \Y $and$libresoc.v:42134$1836_Y + connect \Y $and$libresoc.v:42136$1836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42136$1838 + cell $and $and$libresoc.v:42138$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -67835,10 +67837,10 @@ module \core parameter \Y_WIDTH 13 connect \A \core_core_fn_unit connect \B 8'10000000 - connect \Y $and$libresoc.v:42136$1838_Y + connect \Y $and$libresoc.v:42138$1838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42138$1840 + cell $and $and$libresoc.v:42140$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -67846,10 +67848,10 @@ module \core parameter \Y_WIDTH 13 connect \A \core_core_fn_unit connect \B 5'10000 - connect \Y $and$libresoc.v:42138$1840_Y + connect \Y $and$libresoc.v:42140$1840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42140$1842 + cell $and $and$libresoc.v:42142$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -67857,10 +67859,10 @@ module \core parameter \Y_WIDTH 13 connect \A \core_core_fn_unit connect \B 11'10000000000 - connect \Y $and$libresoc.v:42140$1842_Y + connect \Y $and$libresoc.v:42142$1842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42142$1844 + cell $and $and$libresoc.v:42144$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -67868,10 +67870,10 @@ module \core parameter \Y_WIDTH 13 connect \A \core_core_fn_unit connect \B 10'1000000000 - connect \Y $and$libresoc.v:42142$1844_Y + connect \Y $and$libresoc.v:42144$1844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42144$1846 + cell $and $and$libresoc.v:42146$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -67879,10 +67881,10 @@ module \core parameter \Y_WIDTH 13 connect \A \core_core_fn_unit connect \B 9'100000000 - connect \Y $and$libresoc.v:42144$1846_Y + connect \Y $and$libresoc.v:42146$1846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42146$1848 + cell $and $and$libresoc.v:42148$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -67890,10 +67892,10 @@ module \core parameter \Y_WIDTH 13 connect \A \core_core_fn_unit connect \B 4'1000 - connect \Y $and$libresoc.v:42146$1848_Y + connect \Y $and$libresoc.v:42148$1848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $and $and$libresoc.v:42148$1850 + cell $and $and$libresoc.v:42150$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -67901,10 +67903,10 @@ module \core parameter \Y_WIDTH 13 connect \A \core_core_fn_unit connect \B 3'100 - connect \Y $and$libresoc.v:42148$1850_Y + connect \Y $and$libresoc.v:42150$1850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42153$1855 + cell $and $and$libresoc.v:42155$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67912,10 +67914,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42153$1855_Y + connect \Y $and$libresoc.v:42155$1855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42154$1856 + cell $and $and$libresoc.v:42156$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67923,10 +67925,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42154$1856_Y + connect \Y $and$libresoc.v:42156$1856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42157$1859 + cell $and $and$libresoc.v:42159$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67934,10 +67936,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42157$1859_Y + connect \Y $and$libresoc.v:42159$1859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42160$1862 + cell $and $and$libresoc.v:42162$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67945,10 +67947,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42160$1862_Y + connect \Y $and$libresoc.v:42162$1862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42167$1869 + cell $and $and$libresoc.v:42169$1869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67956,10 +67958,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42167$1869_Y + connect \Y $and$libresoc.v:42169$1869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42168$1870 + cell $and $and$libresoc.v:42170$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -67967,10 +67969,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42168$1870_Y + connect \Y $and$libresoc.v:42170$1870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42171$1873 + cell $and $and$libresoc.v:42173$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67978,10 +67980,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42171$1873_Y + connect \Y $and$libresoc.v:42173$1873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42174$1876 + cell $and $and$libresoc.v:42176$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67989,10 +67991,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42174$1876_Y + connect \Y $and$libresoc.v:42176$1876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42175$1877 + cell $and $and$libresoc.v:42177$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68000,10 +68002,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42175$1877_Y + connect \Y $and$libresoc.v:42177$1877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42178$1880 + cell $and $and$libresoc.v:42180$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68011,10 +68013,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42178$1880_Y + connect \Y $and$libresoc.v:42180$1880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42180$1882 + cell $and $and$libresoc.v:42182$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68022,10 +68024,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42180$1882_Y + connect \Y $and$libresoc.v:42182$1882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42181$1883 + cell $and $and$libresoc.v:42183$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68033,10 +68035,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42181$1883_Y + connect \Y $and$libresoc.v:42183$1883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42185$1887 + cell $and $and$libresoc.v:42187$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68044,10 +68046,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42185$1887_Y + connect \Y $and$libresoc.v:42187$1887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42189$1891 + cell $and $and$libresoc.v:42191$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68055,10 +68057,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42189$1891_Y + connect \Y $and$libresoc.v:42191$1891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42190$1892 + cell $and $and$libresoc.v:42192$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68066,10 +68068,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42190$1892_Y + connect \Y $and$libresoc.v:42192$1892_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42193$1895 + cell $and $and$libresoc.v:42195$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68077,10 +68079,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42193$1895_Y + connect \Y $and$libresoc.v:42195$1895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42196$1898 + cell $and $and$libresoc.v:42198$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68088,10 +68090,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42196$1898_Y + connect \Y $and$libresoc.v:42198$1898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42197$1899 + cell $and $and$libresoc.v:42199$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68099,10 +68101,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42197$1899_Y + connect \Y $and$libresoc.v:42199$1899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42200$1902 + cell $and $and$libresoc.v:42202$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68110,10 +68112,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42200$1902_Y + connect \Y $and$libresoc.v:42202$1902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42203$1905 + cell $and $and$libresoc.v:42205$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68121,10 +68123,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42203$1905_Y + connect \Y $and$libresoc.v:42205$1905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42204$1906 + cell $and $and$libresoc.v:42206$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68132,10 +68134,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42204$1906_Y + connect \Y $and$libresoc.v:42206$1906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42207$1909 + cell $and $and$libresoc.v:42209$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68143,10 +68145,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42207$1909_Y + connect \Y $and$libresoc.v:42209$1909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42210$1912 + cell $and $and$libresoc.v:42212$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68154,10 +68156,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42210$1912_Y + connect \Y $and$libresoc.v:42212$1912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42215$1917 + cell $and $and$libresoc.v:42217$1917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68165,10 +68167,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42215$1917_Y + connect \Y $and$libresoc.v:42217$1917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42216$1918 + cell $and $and$libresoc.v:42218$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68176,10 +68178,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$347 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42216$1918_Y + connect \Y $and$libresoc.v:42218$1918_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42218$1920 + cell $and $and$libresoc.v:42220$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68187,10 +68189,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$349 connect \B \$351 - connect \Y $and$libresoc.v:42218$1920_Y + connect \Y $and$libresoc.v:42220$1920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42219$1921 + cell $and $and$libresoc.v:42221$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68198,10 +68200,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [0] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42219$1921_Y + connect \Y $and$libresoc.v:42221$1921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42221$1923 + cell $and $and$libresoc.v:42223$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68209,10 +68211,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42221$1923_Y + connect \Y $and$libresoc.v:42223$1923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42222$1924 + cell $and $and$libresoc.v:42224$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68220,10 +68222,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$359 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42222$1924_Y + connect \Y $and$libresoc.v:42224$1924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42224$1926 + cell $and $and$libresoc.v:42226$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68231,10 +68233,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$361 connect \B \$363 - connect \Y $and$libresoc.v:42224$1926_Y + connect \Y $and$libresoc.v:42226$1926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42225$1927 + cell $and $and$libresoc.v:42227$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68242,10 +68244,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [1] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42225$1927_Y + connect \Y $and$libresoc.v:42227$1927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42227$1929 + cell $and $and$libresoc.v:42229$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68253,10 +68255,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42227$1929_Y + connect \Y $and$libresoc.v:42229$1929_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42228$1930 + cell $and $and$libresoc.v:42230$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68264,10 +68266,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$371 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42228$1930_Y + connect \Y $and$libresoc.v:42230$1930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42230$1932 + cell $and $and$libresoc.v:42232$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68275,10 +68277,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$373 connect \B \$375 - connect \Y $and$libresoc.v:42230$1932_Y + connect \Y $and$libresoc.v:42232$1932_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42231$1933 + cell $and $and$libresoc.v:42233$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68286,10 +68288,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [2] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42231$1933_Y + connect \Y $and$libresoc.v:42233$1933_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42233$1935 + cell $and $and$libresoc.v:42235$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68297,10 +68299,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42233$1935_Y + connect \Y $and$libresoc.v:42235$1935_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42234$1936 + cell $and $and$libresoc.v:42236$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68308,10 +68310,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$383 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42234$1936_Y + connect \Y $and$libresoc.v:42236$1936_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42236$1938 + cell $and $and$libresoc.v:42238$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68319,10 +68321,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$385 connect \B \$387 - connect \Y $and$libresoc.v:42236$1938_Y + connect \Y $and$libresoc.v:42238$1938_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42237$1939 + cell $and $and$libresoc.v:42239$1939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68330,10 +68332,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [3] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42237$1939_Y + connect \Y $and$libresoc.v:42239$1939_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42239$1941 + cell $and $and$libresoc.v:42241$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68341,10 +68343,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42239$1941_Y + connect \Y $and$libresoc.v:42241$1941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42240$1942 + cell $and $and$libresoc.v:42242$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68352,10 +68354,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$395 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42240$1942_Y + connect \Y $and$libresoc.v:42242$1942_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42242$1944 + cell $and $and$libresoc.v:42244$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68363,10 +68365,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$397 connect \B \$399 - connect \Y $and$libresoc.v:42242$1944_Y + connect \Y $and$libresoc.v:42244$1944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42243$1945 + cell $and $and$libresoc.v:42245$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68374,10 +68376,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [4] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42243$1945_Y + connect \Y $and$libresoc.v:42245$1945_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42245$1947 + cell $and $and$libresoc.v:42247$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68385,10 +68387,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42245$1947_Y + connect \Y $and$libresoc.v:42247$1947_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42246$1948 + cell $and $and$libresoc.v:42248$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68396,10 +68398,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$407 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42246$1948_Y + connect \Y $and$libresoc.v:42248$1948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42248$1950 + cell $and $and$libresoc.v:42250$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68407,10 +68409,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$409 connect \B \$411 - connect \Y $and$libresoc.v:42248$1950_Y + connect \Y $and$libresoc.v:42250$1950_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42249$1951 + cell $and $and$libresoc.v:42251$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68418,10 +68420,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [5] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42249$1951_Y + connect \Y $and$libresoc.v:42251$1951_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42251$1953 + cell $and $and$libresoc.v:42253$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68429,10 +68431,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42251$1953_Y + connect \Y $and$libresoc.v:42253$1953_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42252$1954 + cell $and $and$libresoc.v:42254$1954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68440,10 +68442,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$419 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42252$1954_Y + connect \Y $and$libresoc.v:42254$1954_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42254$1956 + cell $and $and$libresoc.v:42256$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68451,10 +68453,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$421 connect \B \$423 - connect \Y $and$libresoc.v:42254$1956_Y + connect \Y $and$libresoc.v:42256$1956_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42255$1957 + cell $and $and$libresoc.v:42257$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68462,10 +68464,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [6] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42255$1957_Y + connect \Y $and$libresoc.v:42257$1957_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42257$1959 + cell $and $and$libresoc.v:42259$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68473,10 +68475,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42257$1959_Y + connect \Y $and$libresoc.v:42259$1959_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42258$1960 + cell $and $and$libresoc.v:42260$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68484,10 +68486,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$431 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42258$1960_Y + connect \Y $and$libresoc.v:42260$1960_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42260$1962 + cell $and $and$libresoc.v:42262$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68495,10 +68497,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$433 connect \B \$435 - connect \Y $and$libresoc.v:42260$1962_Y + connect \Y $and$libresoc.v:42262$1962_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42261$1963 + cell $and $and$libresoc.v:42263$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68506,10 +68508,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [7] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42261$1963_Y + connect \Y $and$libresoc.v:42263$1963_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42263$1965 + cell $and $and$libresoc.v:42265$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68517,10 +68519,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$61 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42263$1965_Y + connect \Y $and$libresoc.v:42265$1965_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42264$1966 + cell $and $and$libresoc.v:42266$1966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68528,10 +68530,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$443 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42264$1966_Y + connect \Y $and$libresoc.v:42266$1966_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42266$1968 + cell $and $and$libresoc.v:42268$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68539,10 +68541,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$445 connect \B \$447 - connect \Y $and$libresoc.v:42266$1968_Y + connect \Y $and$libresoc.v:42268$1968_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42267$1969 + cell $and $and$libresoc.v:42269$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68550,10 +68552,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [8] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42267$1969_Y + connect \Y $and$libresoc.v:42269$1969_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42278$1980 + cell $and $and$libresoc.v:42280$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68561,10 +68563,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42278$1980_Y + connect \Y $and$libresoc.v:42280$1980_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42279$1981 + cell $and $and$libresoc.v:42281$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68572,10 +68574,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$474 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42279$1981_Y + connect \Y $and$libresoc.v:42281$1981_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42281$1983 + cell $and $and$libresoc.v:42283$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68583,10 +68585,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$476 connect \B \$478 - connect \Y $and$libresoc.v:42281$1983_Y + connect \Y $and$libresoc.v:42283$1983_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42282$1984 + cell $and $and$libresoc.v:42284$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68594,10 +68596,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [0] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42282$1984_Y + connect \Y $and$libresoc.v:42284$1984_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42284$1986 + cell $and $and$libresoc.v:42286$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68605,10 +68607,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42284$1986_Y + connect \Y $and$libresoc.v:42286$1986_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42285$1987 + cell $and $and$libresoc.v:42287$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68616,10 +68618,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$486 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42285$1987_Y + connect \Y $and$libresoc.v:42287$1987_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42287$1989 + cell $and $and$libresoc.v:42289$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68627,10 +68629,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$488 connect \B \$490 - connect \Y $and$libresoc.v:42287$1989_Y + connect \Y $and$libresoc.v:42289$1989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42288$1990 + cell $and $and$libresoc.v:42290$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68638,10 +68640,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [1] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42288$1990_Y + connect \Y $and$libresoc.v:42290$1990_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42290$1992 + cell $and $and$libresoc.v:42292$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68649,10 +68651,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42290$1992_Y + connect \Y $and$libresoc.v:42292$1992_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42291$1993 + cell $and $and$libresoc.v:42293$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68660,10 +68662,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$498 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42291$1993_Y + connect \Y $and$libresoc.v:42293$1993_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42293$1995 + cell $and $and$libresoc.v:42295$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68671,10 +68673,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$500 connect \B \$502 - connect \Y $and$libresoc.v:42293$1995_Y + connect \Y $and$libresoc.v:42295$1995_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42294$1996 + cell $and $and$libresoc.v:42296$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68682,10 +68684,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [2] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42294$1996_Y + connect \Y $and$libresoc.v:42296$1996_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42296$1998 + cell $and $and$libresoc.v:42298$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68693,10 +68695,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42296$1998_Y + connect \Y $and$libresoc.v:42298$1998_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42297$1999 + cell $and $and$libresoc.v:42299$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68704,10 +68706,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$510 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42297$1999_Y + connect \Y $and$libresoc.v:42299$1999_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42299$2001 + cell $and $and$libresoc.v:42301$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68715,10 +68717,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$512 connect \B \$514 - connect \Y $and$libresoc.v:42299$2001_Y + connect \Y $and$libresoc.v:42301$2001_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42300$2002 + cell $and $and$libresoc.v:42302$2002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68726,10 +68728,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [3] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42300$2002_Y + connect \Y $and$libresoc.v:42302$2002_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42302$2004 + cell $and $and$libresoc.v:42304$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68737,10 +68739,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42302$2004_Y + connect \Y $and$libresoc.v:42304$2004_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42303$2005 + cell $and $and$libresoc.v:42305$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68748,10 +68750,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$522 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42303$2005_Y + connect \Y $and$libresoc.v:42305$2005_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42305$2007 + cell $and $and$libresoc.v:42307$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68759,10 +68761,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$524 connect \B \$526 - connect \Y $and$libresoc.v:42305$2007_Y + connect \Y $and$libresoc.v:42307$2007_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42306$2008 + cell $and $and$libresoc.v:42308$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68770,10 +68772,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [4] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42306$2008_Y + connect \Y $and$libresoc.v:42308$2008_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42308$2010 + cell $and $and$libresoc.v:42310$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68781,10 +68783,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42308$2010_Y + connect \Y $and$libresoc.v:42310$2010_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42309$2011 + cell $and $and$libresoc.v:42311$2011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68792,10 +68794,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$534 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42309$2011_Y + connect \Y $and$libresoc.v:42311$2011_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42311$2013 + cell $and $and$libresoc.v:42313$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68803,10 +68805,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$536 connect \B \$538 - connect \Y $and$libresoc.v:42311$2013_Y + connect \Y $and$libresoc.v:42313$2013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42312$2014 + cell $and $and$libresoc.v:42314$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68814,10 +68816,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [5] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42312$2014_Y + connect \Y $and$libresoc.v:42314$2014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42314$2016 + cell $and $and$libresoc.v:42316$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68825,10 +68827,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42314$2016_Y + connect \Y $and$libresoc.v:42316$2016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42315$2017 + cell $and $and$libresoc.v:42317$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68836,10 +68838,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$546 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42315$2017_Y + connect \Y $and$libresoc.v:42317$2017_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42317$2019 + cell $and $and$libresoc.v:42319$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68847,10 +68849,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$548 connect \B \$550 - connect \Y $and$libresoc.v:42317$2019_Y + connect \Y $and$libresoc.v:42319$2019_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42318$2020 + cell $and $and$libresoc.v:42320$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68858,10 +68860,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [6] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42318$2020_Y + connect \Y $and$libresoc.v:42320$2020_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42320$2022 + cell $and $and$libresoc.v:42322$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68869,10 +68871,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$61 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42320$2022_Y + connect \Y $and$libresoc.v:42322$2022_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42321$2023 + cell $and $and$libresoc.v:42323$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68880,10 +68882,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$558 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42321$2023_Y + connect \Y $and$libresoc.v:42323$2023_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42323$2025 + cell $and $and$libresoc.v:42325$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68891,10 +68893,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$560 connect \B \$562 - connect \Y $and$libresoc.v:42323$2025_Y + connect \Y $and$libresoc.v:42325$2025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42324$2026 + cell $and $and$libresoc.v:42326$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68902,10 +68904,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [7] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42324$2026_Y + connect \Y $and$libresoc.v:42326$2026_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42334$2036 + cell $and $and$libresoc.v:42336$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68913,10 +68915,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42334$2036_Y + connect \Y $and$libresoc.v:42336$2036_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42335$2037 + cell $and $and$libresoc.v:42337$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68924,10 +68926,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$587 connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:42335$2037_Y + connect \Y $and$libresoc.v:42337$2037_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42337$2039 + cell $and $and$libresoc.v:42339$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68935,10 +68937,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$589 connect \B \$591 - connect \Y $and$libresoc.v:42337$2039_Y + connect \Y $and$libresoc.v:42339$2039_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42338$2040 + cell $and $and$libresoc.v:42340$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68946,10 +68948,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [0] connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:42338$2040_Y + connect \Y $and$libresoc.v:42340$2040_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42340$2042 + cell $and $and$libresoc.v:42342$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68957,10 +68959,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$61 [2] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42340$2042_Y + connect \Y $and$libresoc.v:42342$2042_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42341$2043 + cell $and $and$libresoc.v:42343$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68968,10 +68970,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$599 connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:42341$2043_Y + connect \Y $and$libresoc.v:42343$2043_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42343$2045 + cell $and $and$libresoc.v:42345$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68979,10 +68981,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$601 connect \B \$603 - connect \Y $and$libresoc.v:42343$2045_Y + connect \Y $and$libresoc.v:42345$2045_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42344$2046 + cell $and $and$libresoc.v:42346$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68990,10 +68992,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [1] connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:42344$2046_Y + connect \Y $and$libresoc.v:42346$2046_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42348$2050 + cell $and $and$libresoc.v:42350$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69001,10 +69003,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42348$2050_Y + connect \Y $and$libresoc.v:42350$2050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42349$2051 + cell $and $and$libresoc.v:42351$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69012,10 +69014,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42349$2051_Y + connect \Y $and$libresoc.v:42351$2051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42352$2054 + cell $and $and$libresoc.v:42354$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69023,10 +69025,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42352$2054_Y + connect \Y $and$libresoc.v:42354$2054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42354$2056 + cell $and $and$libresoc.v:42356$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69034,10 +69036,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42354$2056_Y + connect \Y $and$libresoc.v:42356$2056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42355$2057 + cell $and $and$libresoc.v:42357$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69045,10 +69047,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$628 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42355$2057_Y + connect \Y $and$libresoc.v:42357$2057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42357$2059 + cell $and $and$libresoc.v:42359$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69056,10 +69058,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$630 connect \B \$632 - connect \Y $and$libresoc.v:42357$2059_Y + connect \Y $and$libresoc.v:42359$2059_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42358$2060 + cell $and $and$libresoc.v:42360$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69067,10 +69069,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42358$2060_Y + connect \Y $and$libresoc.v:42360$2060_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42360$2062 + cell $and $and$libresoc.v:42362$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69078,10 +69080,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [2] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42360$2062_Y + connect \Y $and$libresoc.v:42362$2062_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42361$2063 + cell $and $and$libresoc.v:42363$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69089,10 +69091,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$640 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42361$2063_Y + connect \Y $and$libresoc.v:42363$2063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42363$2065 + cell $and $and$libresoc.v:42365$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69100,10 +69102,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$642 connect \B \$644 - connect \Y $and$libresoc.v:42363$2065_Y + connect \Y $and$libresoc.v:42365$2065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42364$2066 + cell $and $and$libresoc.v:42366$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69111,10 +69113,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [1] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42364$2066_Y + connect \Y $and$libresoc.v:42366$2066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42366$2068 + cell $and $and$libresoc.v:42368$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69122,10 +69124,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42366$2068_Y + connect \Y $and$libresoc.v:42368$2068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42367$2069 + cell $and $and$libresoc.v:42369$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69133,10 +69135,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$652 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42367$2069_Y + connect \Y $and$libresoc.v:42369$2069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42369$2071 + cell $and $and$libresoc.v:42371$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69144,10 +69146,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$654 connect \B \$656 - connect \Y $and$libresoc.v:42369$2071_Y + connect \Y $and$libresoc.v:42371$2071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42370$2072 + cell $and $and$libresoc.v:42372$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69155,10 +69157,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [2] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42370$2072_Y + connect \Y $and$libresoc.v:42372$2072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42372$2074 + cell $and $and$libresoc.v:42374$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69166,10 +69168,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42372$2074_Y + connect \Y $and$libresoc.v:42374$2074_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42373$2075 + cell $and $and$libresoc.v:42375$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69177,10 +69179,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$664 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42373$2075_Y + connect \Y $and$libresoc.v:42375$2075_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42375$2077 + cell $and $and$libresoc.v:42377$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69188,10 +69190,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$666 connect \B \$668 - connect \Y $and$libresoc.v:42375$2077_Y + connect \Y $and$libresoc.v:42377$2077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42376$2078 + cell $and $and$libresoc.v:42378$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69199,10 +69201,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [3] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42376$2078_Y + connect \Y $and$libresoc.v:42378$2078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42378$2080 + cell $and $and$libresoc.v:42380$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69210,10 +69212,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42378$2080_Y + connect \Y $and$libresoc.v:42380$2080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42379$2081 + cell $and $and$libresoc.v:42381$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69221,10 +69223,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$676 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42379$2081_Y + connect \Y $and$libresoc.v:42381$2081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42381$2083 + cell $and $and$libresoc.v:42383$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69232,10 +69234,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$678 connect \B \$680 - connect \Y $and$libresoc.v:42381$2083_Y + connect \Y $and$libresoc.v:42383$2083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42382$2084 + cell $and $and$libresoc.v:42384$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69243,10 +69245,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [4] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42382$2084_Y + connect \Y $and$libresoc.v:42384$2084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42384$2086 + cell $and $and$libresoc.v:42386$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69254,10 +69256,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [3] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42384$2086_Y + connect \Y $and$libresoc.v:42386$2086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42385$2087 + cell $and $and$libresoc.v:42387$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69265,10 +69267,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$688 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42385$2087_Y + connect \Y $and$libresoc.v:42387$2087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42387$2089 + cell $and $and$libresoc.v:42389$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69276,10 +69278,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$690 connect \B \$692 - connect \Y $and$libresoc.v:42387$2089_Y + connect \Y $and$libresoc.v:42389$2089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42388$2090 + cell $and $and$libresoc.v:42390$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69287,10 +69289,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [5] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42388$2090_Y + connect \Y $and$libresoc.v:42390$2090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42397$2100 + cell $and $and$libresoc.v:42399$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69298,10 +69300,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42397$2100_Y + connect \Y $and$libresoc.v:42399$2100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42400$2103 + cell $and $and$libresoc.v:42402$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69309,10 +69311,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42400$2103_Y + connect \Y $and$libresoc.v:42402$2103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42401$2104 + cell $and $and$libresoc.v:42403$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69320,10 +69322,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$720 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42401$2104_Y + connect \Y $and$libresoc.v:42403$2104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42403$2106 + cell $and $and$libresoc.v:42405$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69331,10 +69333,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$722 connect \B \$724 - connect \Y $and$libresoc.v:42403$2106_Y + connect \Y $and$libresoc.v:42405$2106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42404$2107 + cell $and $and$libresoc.v:42406$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69342,10 +69344,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42404$2107_Y + connect \Y $and$libresoc.v:42406$2107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42406$2109 + cell $and $and$libresoc.v:42408$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69353,10 +69355,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42406$2109_Y + connect \Y $and$libresoc.v:42408$2109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42407$2110 + cell $and $and$libresoc.v:42409$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69364,10 +69366,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$732 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42407$2110_Y + connect \Y $and$libresoc.v:42409$2110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42409$2112 + cell $and $and$libresoc.v:42411$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69375,10 +69377,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$734 connect \B \$736 - connect \Y $and$libresoc.v:42409$2112_Y + connect \Y $and$libresoc.v:42411$2112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42410$2113 + cell $and $and$libresoc.v:42412$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69386,10 +69388,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [1] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42410$2113_Y + connect \Y $and$libresoc.v:42412$2113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42412$2115 + cell $and $and$libresoc.v:42414$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69397,10 +69399,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [4] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42412$2115_Y + connect \Y $and$libresoc.v:42414$2115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42413$2116 + cell $and $and$libresoc.v:42415$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69408,10 +69410,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$744 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42413$2116_Y + connect \Y $and$libresoc.v:42415$2116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42415$2118 + cell $and $and$libresoc.v:42417$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69419,10 +69421,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$746 connect \B \$748 - connect \Y $and$libresoc.v:42415$2118_Y + connect \Y $and$libresoc.v:42417$2118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42416$2119 + cell $and $and$libresoc.v:42418$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69430,10 +69432,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [2] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42416$2119_Y + connect \Y $and$libresoc.v:42418$2119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42421$2125 + cell $and $and$libresoc.v:42423$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69441,10 +69443,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42421$2125_Y + connect \Y $and$libresoc.v:42423$2125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42422$2126 + cell $and $and$libresoc.v:42424$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69452,10 +69454,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42422$2126_Y + connect \Y $and$libresoc.v:42424$2126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42425$2129 + cell $and $and$libresoc.v:42427$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69463,10 +69465,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42425$2129_Y + connect \Y $and$libresoc.v:42427$2129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42426$2130 + cell $and $and$libresoc.v:42428$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69474,10 +69476,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$770 connect \B \rdflag_XER_xer_ov_0 - connect \Y $and$libresoc.v:42426$2130_Y + connect \Y $and$libresoc.v:42428$2130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42428$2132 + cell $and $and$libresoc.v:42430$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69485,10 +69487,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$772 connect \B \$774 - connect \Y $and$libresoc.v:42428$2132_Y + connect \Y $and$libresoc.v:42430$2132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42429$2133 + cell $and $and$libresoc.v:42431$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69496,10 +69498,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42429$2133_Y + connect \Y $and$libresoc.v:42431$2133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42431$2135 + cell $and $and$libresoc.v:42433$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69507,10 +69509,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42431$2135_Y + connect \Y $and$libresoc.v:42433$2135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42432$2136 + cell $and $and$libresoc.v:42434$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69518,10 +69520,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$782 connect \B \rdflag_CR_full_cr_0 - connect \Y $and$libresoc.v:42432$2136_Y + connect \Y $and$libresoc.v:42434$2136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42434$2138 + cell $and $and$libresoc.v:42436$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69529,10 +69531,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$784 connect \B \$786 - connect \Y $and$libresoc.v:42434$2138_Y + connect \Y $and$libresoc.v:42436$2138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42435$2139 + cell $and $and$libresoc.v:42437$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69540,10 +69542,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42435$2139_Y + connect \Y $and$libresoc.v:42437$2139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42437$2141 + cell $and $and$libresoc.v:42439$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69551,10 +69553,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [3] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42437$2141_Y + connect \Y $and$libresoc.v:42439$2141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42438$2142 + cell $and $and$libresoc.v:42440$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69562,10 +69564,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$794 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42438$2142_Y + connect \Y $and$libresoc.v:42440$2142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42440$2144 + cell $and $and$libresoc.v:42442$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69573,10 +69575,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$796 connect \B \$798 - connect \Y $and$libresoc.v:42440$2144_Y + connect \Y $and$libresoc.v:42442$2144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42441$2145 + cell $and $and$libresoc.v:42443$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69584,10 +69586,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42441$2145_Y + connect \Y $and$libresoc.v:42443$2145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42445$2149 + cell $and $and$libresoc.v:42447$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69595,10 +69597,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42445$2149_Y + connect \Y $and$libresoc.v:42447$2149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42446$2150 + cell $and $and$libresoc.v:42448$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69606,10 +69608,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$810 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42446$2150_Y + connect \Y $and$libresoc.v:42448$2150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42448$2152 + cell $and $and$libresoc.v:42450$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69617,10 +69619,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$812 connect \B \$814 - connect \Y $and$libresoc.v:42448$2152_Y + connect \Y $and$libresoc.v:42450$2152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42449$2153 + cell $and $and$libresoc.v:42451$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69628,10 +69630,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [1] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42449$2153_Y + connect \Y $and$libresoc.v:42451$2153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42454$2158 + cell $and $and$libresoc.v:42456$2158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69639,10 +69641,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [4] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42454$2158_Y + connect \Y $and$libresoc.v:42456$2158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42455$2159 + cell $and $and$libresoc.v:42457$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69650,10 +69652,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$829 connect \B \rdflag_CR_cr_b_0 - connect \Y $and$libresoc.v:42455$2159_Y + connect \Y $and$libresoc.v:42457$2159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42457$2161 + cell $and $and$libresoc.v:42459$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69661,10 +69663,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$831 connect \B \$833 - connect \Y $and$libresoc.v:42457$2161_Y + connect \Y $and$libresoc.v:42459$2161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42458$2162 + cell $and $and$libresoc.v:42460$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69672,10 +69674,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_b_o connect \B \rdpick_CR_cr_b_en_o - connect \Y $and$libresoc.v:42458$2162_Y + connect \Y $and$libresoc.v:42460$2162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42462$2166 + cell $and $and$libresoc.v:42464$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69683,10 +69685,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [5] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42462$2166_Y + connect \Y $and$libresoc.v:42464$2166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42463$2167 + cell $and $and$libresoc.v:42465$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69694,10 +69696,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$845 connect \B \rdflag_CR_cr_c_0 - connect \Y $and$libresoc.v:42463$2167_Y + connect \Y $and$libresoc.v:42465$2167_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42465$2169 + cell $and $and$libresoc.v:42467$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69705,10 +69707,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$847 connect \B \$849 - connect \Y $and$libresoc.v:42465$2169_Y + connect \Y $and$libresoc.v:42467$2169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42466$2170 + cell $and $and$libresoc.v:42468$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69716,10 +69718,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_c_o connect \B \rdpick_CR_cr_c_en_o - connect \Y $and$libresoc.v:42466$2170_Y + connect \Y $and$libresoc.v:42468$2170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42470$2174 + cell $and $and$libresoc.v:42472$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69727,10 +69729,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42470$2174_Y + connect \Y $and$libresoc.v:42472$2174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42471$2175 + cell $and $and$libresoc.v:42473$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69738,10 +69740,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$861 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42471$2175_Y + connect \Y $and$libresoc.v:42473$2175_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42473$2177 + cell $and $and$libresoc.v:42475$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69749,10 +69751,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$863 connect \B \$865 - connect \Y $and$libresoc.v:42473$2177_Y + connect \Y $and$libresoc.v:42475$2177_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42474$2178 + cell $and $and$libresoc.v:42476$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69760,10 +69762,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42474$2178_Y + connect \Y $and$libresoc.v:42476$2178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42476$2180 + cell $and $and$libresoc.v:42478$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69771,10 +69773,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42476$2180_Y + connect \Y $and$libresoc.v:42478$2180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42477$2181 + cell $and $and$libresoc.v:42479$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69782,10 +69784,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$873 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42477$2181_Y + connect \Y $and$libresoc.v:42479$2181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42479$2183 + cell $and $and$libresoc.v:42481$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69793,10 +69795,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$875 connect \B \$877 - connect \Y $and$libresoc.v:42479$2183_Y + connect \Y $and$libresoc.v:42481$2183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42480$2184 + cell $and $and$libresoc.v:42482$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69804,10 +69806,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42480$2184_Y + connect \Y $and$libresoc.v:42482$2184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42482$2186 + cell $and $and$libresoc.v:42484$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69815,10 +69817,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42482$2186_Y + connect \Y $and$libresoc.v:42484$2186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42483$2187 + cell $and $and$libresoc.v:42485$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69826,10 +69828,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$885 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42483$2187_Y + connect \Y $and$libresoc.v:42485$2187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42485$2189 + cell $and $and$libresoc.v:42487$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69837,10 +69839,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$887 connect \B \$889 - connect \Y $and$libresoc.v:42485$2189_Y + connect \Y $and$libresoc.v:42487$2189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42486$2190 + cell $and $and$libresoc.v:42488$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69848,10 +69850,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [2] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42486$2190_Y + connect \Y $and$libresoc.v:42488$2190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42491$2195 + cell $and $and$libresoc.v:42493$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69859,10 +69861,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42491$2195_Y + connect \Y $and$libresoc.v:42493$2195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42492$2196 + cell $and $and$libresoc.v:42494$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69870,10 +69872,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$903 connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:42492$2196_Y + connect \Y $and$libresoc.v:42494$2196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42494$2198 + cell $and $and$libresoc.v:42496$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69881,10 +69883,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$905 connect \B \$907 - connect \Y $and$libresoc.v:42494$2198_Y + connect \Y $and$libresoc.v:42496$2198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42495$2199 + cell $and $and$libresoc.v:42497$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69892,10 +69894,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [0] connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:42495$2199_Y + connect \Y $and$libresoc.v:42497$2199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42497$2201 + cell $and $and$libresoc.v:42499$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69903,10 +69905,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42497$2201_Y + connect \Y $and$libresoc.v:42499$2201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42498$2202 + cell $and $and$libresoc.v:42500$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69914,10 +69916,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$915 connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:42498$2202_Y + connect \Y $and$libresoc.v:42500$2202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42500$2204 + cell $and $and$libresoc.v:42502$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69925,10 +69927,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$917 connect \B \$919 - connect \Y $and$libresoc.v:42500$2204_Y + connect \Y $and$libresoc.v:42502$2204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42501$2205 + cell $and $and$libresoc.v:42503$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69936,10 +69938,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [1] connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:42501$2205_Y + connect \Y $and$libresoc.v:42503$2205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42505$2209 + cell $and $and$libresoc.v:42507$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69947,10 +69949,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42505$2209_Y + connect \Y $and$libresoc.v:42507$2209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $and$libresoc.v:42506$2210 + cell $and $and$libresoc.v:42508$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69958,10 +69960,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$931 connect \B \rdflag_SPR_spr1_0 - connect \Y $and$libresoc.v:42506$2210_Y + connect \Y $and$libresoc.v:42508$2210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42508$2212 + cell $and $and$libresoc.v:42510$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69969,10 +69971,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$933 connect \B \$935 - connect \Y $and$libresoc.v:42508$2212_Y + connect \Y $and$libresoc.v:42510$2212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42509$2213 + cell $and $and$libresoc.v:42511$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69980,10 +69982,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42509$2213_Y + connect \Y $and$libresoc.v:42511$2213_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42512$2216 + cell $and $and$libresoc.v:42514$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69991,10 +69993,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42512$2216_Y + connect \Y $and$libresoc.v:42514$2216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42513$2217 + cell $and $and$libresoc.v:42515$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70002,10 +70004,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42513$2217_Y + connect \Y $and$libresoc.v:42515$2217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42514$2218 + cell $and $and$libresoc.v:42516$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70013,10 +70015,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42514$2218_Y + connect \Y $and$libresoc.v:42516$2218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42515$2219 + cell $and $and$libresoc.v:42517$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70024,10 +70026,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42515$2219_Y + connect \Y $and$libresoc.v:42517$2219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42516$2220 + cell $and $and$libresoc.v:42518$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70035,10 +70037,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42516$2220_Y + connect \Y $and$libresoc.v:42518$2220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42517$2221 + cell $and $and$libresoc.v:42519$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70046,10 +70048,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42517$2221_Y + connect \Y $and$libresoc.v:42519$2221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42518$2222 + cell $and $and$libresoc.v:42520$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70057,10 +70059,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42518$2222_Y + connect \Y $and$libresoc.v:42520$2222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42519$2223 + cell $and $and$libresoc.v:42521$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70068,10 +70070,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42519$2223_Y + connect \Y $and$libresoc.v:42521$2223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42520$2224 + cell $and $and$libresoc.v:42522$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70079,10 +70081,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42520$2224_Y + connect \Y $and$libresoc.v:42522$2224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42521$2225 + cell $and $and$libresoc.v:42523$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70090,10 +70092,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42521$2225_Y + connect \Y $and$libresoc.v:42523$2225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:401" - cell $and $and$libresoc.v:42522$2226 + cell $and $and$libresoc.v:42524$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70101,10 +70103,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42522$2226_Y + connect \Y $and$libresoc.v:42524$2226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42523$2227 + cell $and $and$libresoc.v:42525$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70112,10 +70114,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42523$2227_Y + connect \Y $and$libresoc.v:42525$2227_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42525$2229 + cell $and $and$libresoc.v:42527$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70123,10 +70125,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \$969 - connect \Y $and$libresoc.v:42525$2229_Y + connect \Y $and$libresoc.v:42527$2229_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42526$2230 + cell $and $and$libresoc.v:42528$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70134,10 +70136,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42526$2230_Y + connect \Y $and$libresoc.v:42528$2230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - cell $and $and$libresoc.v:42528$2232 + cell $and $and$libresoc.v:42530$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70145,10 +70147,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$92 connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42528$2232_Y + connect \Y $and$libresoc.v:42530$2232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $and $and$libresoc.v:42529$2233 + cell $and $and$libresoc.v:42531$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70156,10 +70158,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42529$2233_Y + connect \Y $and$libresoc.v:42531$2233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42531$2235 + cell $and $and$libresoc.v:42533$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70167,10 +70169,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$983 connect \B \$988 - connect \Y $and$libresoc.v:42531$2235_Y + connect \Y $and$libresoc.v:42533$2235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - cell $and $and$libresoc.v:42532$2236 + cell $and $and$libresoc.v:42534$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70178,10 +70180,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$983 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42532$2236_Y + connect \Y $and$libresoc.v:42534$2236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42155$1857 + cell $eq $eq$libresoc.v:42157$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70189,10 +70191,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$226 connect \B 1'1 - connect \Y $eq$libresoc.v:42155$1857_Y + connect \Y $eq$libresoc.v:42157$1857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42159$1861 + cell $eq $eq$libresoc.v:42161$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70200,10 +70202,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42159$1861_Y + connect \Y $eq$libresoc.v:42161$1861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42161$1863 + cell $eq $eq$libresoc.v:42163$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70211,10 +70213,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$238 connect \B 3'100 - connect \Y $eq$libresoc.v:42161$1863_Y + connect \Y $eq$libresoc.v:42163$1863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42169$1871 + cell $eq $eq$libresoc.v:42171$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70222,10 +70224,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$254 connect \B 1'1 - connect \Y $eq$libresoc.v:42169$1871_Y + connect \Y $eq$libresoc.v:42171$1871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42176$1878 + cell $eq $eq$libresoc.v:42178$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70233,10 +70235,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$268 connect \B 1'1 - connect \Y $eq$libresoc.v:42176$1878_Y + connect \Y $eq$libresoc.v:42178$1878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42182$1884 + cell $eq $eq$libresoc.v:42184$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70244,10 +70246,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$280 connect \B 2'10 - connect \Y $eq$libresoc.v:42182$1884_Y + connect \Y $eq$libresoc.v:42184$1884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42184$1886 + cell $eq $eq$libresoc.v:42186$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70255,10 +70257,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42184$1886_Y + connect \Y $eq$libresoc.v:42186$1886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42186$1888 + cell $eq $eq$libresoc.v:42188$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70266,10 +70268,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$288 connect \B 3'100 - connect \Y $eq$libresoc.v:42186$1888_Y + connect \Y $eq$libresoc.v:42188$1888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42191$1893 + cell $eq $eq$libresoc.v:42193$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70277,10 +70279,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$298 connect \B 1'1 - connect \Y $eq$libresoc.v:42191$1893_Y + connect \Y $eq$libresoc.v:42193$1893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42198$1900 + cell $eq $eq$libresoc.v:42200$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70288,10 +70290,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$312 connect \B 1'1 - connect \Y $eq$libresoc.v:42198$1900_Y + connect \Y $eq$libresoc.v:42200$1900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42205$1907 + cell $eq $eq$libresoc.v:42207$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70299,10 +70301,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$326 connect \B 1'1 - connect \Y $eq$libresoc.v:42205$1907_Y + connect \Y $eq$libresoc.v:42207$1907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42209$1911 + cell $eq $eq$libresoc.v:42211$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70310,10 +70312,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42209$1911_Y + connect \Y $eq$libresoc.v:42211$1911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42211$1913 + cell $eq $eq$libresoc.v:42213$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70321,10 +70323,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$338 connect \B 3'100 - connect \Y $eq$libresoc.v:42211$1913_Y + connect \Y $eq$libresoc.v:42213$1913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42350$2052 + cell $eq $eq$libresoc.v:42352$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70332,10 +70334,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$618 connect \B 1'1 - connect \Y $eq$libresoc.v:42350$2052_Y + connect \Y $eq$libresoc.v:42352$2052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42396$2099 + cell $eq $eq$libresoc.v:42398$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70343,10 +70345,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42396$2099_Y + connect \Y $eq$libresoc.v:42398$2099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42398$2101 + cell $eq $eq$libresoc.v:42400$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70354,10 +70356,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$714 connect \B 3'100 - connect \Y $eq$libresoc.v:42398$2101_Y + connect \Y $eq$libresoc.v:42400$2101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42423$2127 + cell $eq $eq$libresoc.v:42425$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70365,66 +70367,66 @@ module \core parameter \Y_WIDTH 1 connect \A \$764 connect \B 2'10 - connect \Y $eq$libresoc.v:42423$2127_Y + connect \Y $eq$libresoc.v:42425$2127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:41980$1677 + cell $pos $extend$libresoc.v:41982$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \$1442 - connect \Y $extend$libresoc.v:41980$1677_Y + connect \Y $extend$libresoc.v:41982$1677_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42046$1744 + cell $pos $extend$libresoc.v:42048$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \$1606 - connect \Y $extend$libresoc.v:42046$1744_Y + connect \Y $extend$libresoc.v:42048$1744_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42050$1749 + cell $pos $extend$libresoc.v:42052$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$1614 - connect \Y $extend$libresoc.v:42050$1749_Y + connect \Y $extend$libresoc.v:42052$1749_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $pos $extend$libresoc.v:42114$1814 + cell $pos $extend$libresoc.v:42116$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$1773 - connect \Y $extend$libresoc.v:42114$1814_Y + connect \Y $extend$libresoc.v:42116$1814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $pos $extend$libresoc.v:42124$1825 + cell $pos $extend$libresoc.v:42126$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \addr_en$1791 - connect \Y $extend$libresoc.v:42124$1825_Y + connect \Y $extend$libresoc.v:42126$1825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42395$2097 + cell $pos $extend$libresoc.v:42397$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$709 - connect \Y $extend$libresoc.v:42395$2097_Y + connect \Y $extend$libresoc.v:42397$2097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42420$2123 + cell $pos $extend$libresoc.v:42422$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \$759 - connect \Y $extend$libresoc.v:42420$2123_Y + connect \Y $extend$libresoc.v:42422$2123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" - cell $ne $ne$libresoc.v:42150$1852 + cell $ne $ne$libresoc.v:42152$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70432,10 +70434,10 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:42150$1852_Y + connect \Y $ne$libresoc.v:42152$1852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" - cell $ne $ne$libresoc.v:42152$1854 + cell $ne $ne$libresoc.v:42154$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70443,706 +70445,706 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:42152$1854_Y + connect \Y $ne$libresoc.v:42154$1854_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41811$1508 + cell $not $not$libresoc.v:41813$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1005 - connect \Y $not$libresoc.v:41811$1508_Y + connect \Y $not$libresoc.v:41813$1508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41817$1514 + cell $not $not$libresoc.v:41819$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1026 - connect \Y $not$libresoc.v:41817$1514_Y + connect \Y $not$libresoc.v:41819$1514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41823$1520 + cell $not $not$libresoc.v:41825$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1044 - connect \Y $not$libresoc.v:41823$1520_Y + connect \Y $not$libresoc.v:41825$1520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41829$1526 + cell $not $not$libresoc.v:41831$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1066 - connect \Y $not$libresoc.v:41829$1526_Y + connect \Y $not$libresoc.v:41831$1526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41835$1532 + cell $not $not$libresoc.v:41837$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1086 - connect \Y $not$libresoc.v:41835$1532_Y + connect \Y $not$libresoc.v:41837$1532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41841$1538 + cell $not $not$libresoc.v:41843$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1106 - connect \Y $not$libresoc.v:41841$1538_Y + connect \Y $not$libresoc.v:41843$1538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41847$1544 + cell $not $not$libresoc.v:41849$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1125 - connect \Y $not$libresoc.v:41847$1544_Y + connect \Y $not$libresoc.v:41849$1544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41853$1550 + cell $not $not$libresoc.v:41855$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1143 - connect \Y $not$libresoc.v:41853$1550_Y + connect \Y $not$libresoc.v:41855$1550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41887$1584 + cell $not $not$libresoc.v:41889$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1217 - connect \Y $not$libresoc.v:41887$1584_Y + connect \Y $not$libresoc.v:41889$1584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41899$1596 + cell $not $not$libresoc.v:41901$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1245 - connect \Y $not$libresoc.v:41899$1596_Y + connect \Y $not$libresoc.v:41901$1596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41907$1604 + cell $not $not$libresoc.v:41909$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1265 - connect \Y $not$libresoc.v:41907$1604_Y + connect \Y $not$libresoc.v:41909$1604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41915$1612 + cell $not $not$libresoc.v:41917$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1285 - connect \Y $not$libresoc.v:41915$1612_Y + connect \Y $not$libresoc.v:41917$1612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41923$1620 + cell $not $not$libresoc.v:41925$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1305 - connect \Y $not$libresoc.v:41923$1620_Y + connect \Y $not$libresoc.v:41925$1620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41931$1628 + cell $not $not$libresoc.v:41933$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1325 - connect \Y $not$libresoc.v:41931$1628_Y + connect \Y $not$libresoc.v:41933$1628_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41939$1636 + cell $not $not$libresoc.v:41941$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1345 - connect \Y $not$libresoc.v:41939$1636_Y + connect \Y $not$libresoc.v:41941$1636_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41960$1657 + cell $not $not$libresoc.v:41962$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1392 - connect \Y $not$libresoc.v:41960$1657_Y + connect \Y $not$libresoc.v:41962$1657_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41966$1663 + cell $not $not$libresoc.v:41968$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1408 - connect \Y $not$libresoc.v:41966$1663_Y + connect \Y $not$libresoc.v:41968$1663_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41972$1669 + cell $not $not$libresoc.v:41974$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1424 - connect \Y $not$libresoc.v:41972$1669_Y + connect \Y $not$libresoc.v:41974$1669_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41987$1685 + cell $not $not$libresoc.v:41989$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1458 - connect \Y $not$libresoc.v:41987$1685_Y + connect \Y $not$libresoc.v:41989$1685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41993$1691 + cell $not $not$libresoc.v:41995$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1474 - connect \Y $not$libresoc.v:41993$1691_Y + connect \Y $not$libresoc.v:41995$1691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:41999$1697 + cell $not $not$libresoc.v:42001$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1490 - connect \Y $not$libresoc.v:41999$1697_Y + connect \Y $not$libresoc.v:42001$1697_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42005$1703 + cell $not $not$libresoc.v:42007$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1506 - connect \Y $not$libresoc.v:42005$1703_Y + connect \Y $not$libresoc.v:42007$1703_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42021$1719 + cell $not $not$libresoc.v:42023$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1542 - connect \Y $not$libresoc.v:42021$1719_Y + connect \Y $not$libresoc.v:42023$1719_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42027$1725 + cell $not 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42427$2131 + cell $not $not$libresoc.v:42429$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_XER_xer_ov_spr0_0 - connect \Y $not$libresoc.v:42427$2131_Y + connect \Y $not$libresoc.v:42429$2131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42433$2137 + cell $not $not$libresoc.v:42435$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_full_cr_cr0_0 - connect \Y $not$libresoc.v:42433$2137_Y + connect \Y $not$libresoc.v:42435$2137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42439$2143 + cell $not $not$libresoc.v:42441$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_cr0_0 - connect \Y $not$libresoc.v:42439$2143_Y + connect \Y $not$libresoc.v:42441$2143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42447$2151 + cell $not $not$libresoc.v:42449$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_branch0_1 - connect \Y $not$libresoc.v:42447$2151_Y + connect \Y $not$libresoc.v:42449$2151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42456$2160 + cell $not $not$libresoc.v:42458$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_b_cr0_0 - connect \Y $not$libresoc.v:42456$2160_Y + connect \Y $not$libresoc.v:42458$2160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42464$2168 + cell $not $not$libresoc.v:42466$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_c_cr0_0 - connect \Y $not$libresoc.v:42464$2168_Y + connect \Y $not$libresoc.v:42466$2168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42472$2176 + cell $not $not$libresoc.v:42474$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_0 - connect \Y $not$libresoc.v:42472$2176_Y + connect \Y $not$libresoc.v:42474$2176_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42478$2182 + cell $not $not$libresoc.v:42480$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_trap0_1 - connect \Y $not$libresoc.v:42478$2182_Y + connect \Y $not$libresoc.v:42480$2182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42484$2188 + cell $not $not$libresoc.v:42486$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_spr0_2 - connect \Y $not$libresoc.v:42484$2188_Y + connect \Y $not$libresoc.v:42486$2188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42493$2197 + cell $not $not$libresoc.v:42495$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast2_branch0_0 - connect \Y $not$libresoc.v:42493$2197_Y + connect \Y $not$libresoc.v:42495$2197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42499$2203 + cell $not $not$libresoc.v:42501$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast2_trap0_1 - connect \Y $not$libresoc.v:42499$2203_Y + connect \Y $not$libresoc.v:42501$2203_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $not $not$libresoc.v:42507$2211 + cell $not $not$libresoc.v:42509$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_SPR_spr1_spr0_0 - connect \Y $not$libresoc.v:42507$2211_Y + connect \Y $not$libresoc.v:42509$2211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42524$2228 + cell $not $not$libresoc.v:42526$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly - connect \Y $not$libresoc.v:42524$2228_Y + connect \Y $not$libresoc.v:42526$2228_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42530$2234 + cell $not $not$libresoc.v:42532$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$986 - connect \Y $not$libresoc.v:42530$2234_Y + connect \Y $not$libresoc.v:42532$2234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41857$1554 + cell $or $or$libresoc.v:41859$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71150,10 +71152,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o connect \B \fus_dest1_o$115 - connect \Y $or$libresoc.v:41857$1554_Y + connect \Y $or$libresoc.v:41859$1554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41858$1555 + cell $or $or$libresoc.v:41860$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71161,10 +71163,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$117 connect \B \fus_dest1_o$118 - connect \Y $or$libresoc.v:41858$1555_Y + connect \Y $or$libresoc.v:41860$1555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41859$1556 + cell $or $or$libresoc.v:41861$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71172,10 +71174,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$116 connect \B \$1157 - connect \Y $or$libresoc.v:41859$1556_Y + connect \Y $or$libresoc.v:41861$1556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41860$1557 + cell $or $or$libresoc.v:41862$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71183,10 +71185,10 @@ module \core parameter \Y_WIDTH 64 connect \A \$1155 connect \B \$1159 - connect \Y $or$libresoc.v:41860$1557_Y + connect \Y $or$libresoc.v:41862$1557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41861$1558 + cell $or $or$libresoc.v:41863$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71194,10 +71196,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$119 connect \B \fus_dest1_o$120 - connect \Y $or$libresoc.v:41861$1558_Y + connect \Y $or$libresoc.v:41863$1558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41862$1559 + cell $or $or$libresoc.v:41864$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \B_SIGNED 0 @@ -71205,10 +71207,10 @@ module \core parameter \Y_WIDTH 65 connect \A { \o_ok \fus_o } connect \B { \ea_ok \fus_ea } - connect \Y $or$libresoc.v:41862$1559_Y + connect \Y $or$libresoc.v:41864$1559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41863$1560 + cell $or $or$libresoc.v:41865$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71216,10 +71218,10 @@ module \core parameter \Y_WIDTH 65 connect \A \fus_dest1_o$121 connect \B \$1165 - connect \Y $or$libresoc.v:41863$1560_Y + connect \Y $or$libresoc.v:41865$1560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41864$1561 + cell $or $or$libresoc.v:41866$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71227,10 +71229,10 @@ module \core parameter \Y_WIDTH 65 connect \A \$1163 connect \B \$1167 - connect \Y $or$libresoc.v:41864$1561_Y + connect \Y $or$libresoc.v:41866$1561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41865$1562 + cell $or $or$libresoc.v:41867$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71238,10 +71240,10 @@ module \core parameter \Y_WIDTH 65 connect \A \$1161 connect \B \$1169 - connect \Y $or$libresoc.v:41865$1562_Y + connect \Y $or$libresoc.v:41867$1562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41866$1563 + cell $or $or$libresoc.v:41868$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71249,10 +71251,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en connect \B \addr_en$997 - connect \Y $or$libresoc.v:41866$1563_Y + connect \Y $or$libresoc.v:41868$1563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41867$1564 + cell $or $or$libresoc.v:41869$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71260,10 +71262,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1036 connect \B \addr_en$1058 - connect \Y $or$libresoc.v:41867$1564_Y + connect \Y $or$libresoc.v:41869$1564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41868$1565 + cell $or $or$libresoc.v:41870$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71271,10 +71273,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1018 connect \B \$1176 - connect \Y $or$libresoc.v:41868$1565_Y + connect \Y $or$libresoc.v:41870$1565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41869$1566 + cell $or $or$libresoc.v:41871$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71282,10 +71284,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$1174 connect \B \$1178 - connect \Y $or$libresoc.v:41869$1566_Y + connect \Y $or$libresoc.v:41871$1566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41870$1567 + cell $or $or$libresoc.v:41872$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71293,10 +71295,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1078 connect \B \addr_en$1098 - connect \Y $or$libresoc.v:41870$1567_Y + connect \Y $or$libresoc.v:41872$1567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41871$1568 + cell $or $or$libresoc.v:41873$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71304,10 +71306,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1135 connect \B \addr_en$1151 - connect \Y $or$libresoc.v:41871$1568_Y + connect \Y $or$libresoc.v:41873$1568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41872$1569 + cell $or $or$libresoc.v:41874$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71315,10 +71317,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1117 connect \B \$1184 - connect \Y $or$libresoc.v:41872$1569_Y + connect \Y $or$libresoc.v:41874$1569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41873$1570 + cell $or $or$libresoc.v:41875$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71326,10 +71328,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$1182 connect \B \$1186 - connect \Y $or$libresoc.v:41873$1570_Y + connect \Y $or$libresoc.v:41875$1570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41874$1571 + cell $or $or$libresoc.v:41876$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71337,10 +71339,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$1180 connect \B \$1188 - connect \Y $or$libresoc.v:41874$1571_Y + connect \Y $or$libresoc.v:41876$1571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41875$1572 + cell $or $or$libresoc.v:41877$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71348,10 +71350,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp connect \B \wp$994 - connect \Y $or$libresoc.v:41875$1572_Y + connect \Y $or$libresoc.v:41877$1572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41876$1573 + cell $or $or$libresoc.v:41878$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71359,10 +71361,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1033 connect \B \wp$1055 - connect \Y $or$libresoc.v:41876$1573_Y + connect \Y $or$libresoc.v:41878$1573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41877$1574 + cell $or $or$libresoc.v:41879$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71370,10 +71372,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1015 connect \B \$1194 - connect \Y $or$libresoc.v:41877$1574_Y + connect \Y $or$libresoc.v:41879$1574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41878$1575 + cell $or $or$libresoc.v:41880$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71381,10 +71383,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1192 connect \B \$1196 - connect \Y $or$libresoc.v:41878$1575_Y + connect \Y $or$libresoc.v:41880$1575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41879$1576 + cell $or $or$libresoc.v:41881$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71392,10 +71394,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1075 connect \B \wp$1095 - connect \Y $or$libresoc.v:41879$1576_Y + connect \Y $or$libresoc.v:41881$1576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41880$1577 + cell $or $or$libresoc.v:41882$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71403,10 +71405,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1132 connect \B \wp$1148 - connect \Y $or$libresoc.v:41880$1577_Y + connect \Y $or$libresoc.v:41882$1577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41881$1578 + cell $or $or$libresoc.v:41883$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71414,10 +71416,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1114 connect \B \$1202 - connect \Y $or$libresoc.v:41881$1578_Y + connect \Y $or$libresoc.v:41883$1578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41882$1579 + cell $or $or$libresoc.v:41884$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71425,10 +71427,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1200 connect \B \$1204 - connect \Y $or$libresoc.v:41882$1579_Y + connect \Y $or$libresoc.v:41884$1579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41883$1580 + cell $or $or$libresoc.v:41885$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71436,10 +71438,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1198 connect \B \$1206 - connect \Y $or$libresoc.v:41883$1580_Y + connect \Y $or$libresoc.v:41885$1580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41945$1642 + cell $or $or$libresoc.v:41947$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71447,10 +71449,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest3_o connect \B \fus_dest2_o$128 - connect \Y $or$libresoc.v:41945$1642_Y + connect \Y $or$libresoc.v:41947$1642_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41946$1643 + cell $or $or$libresoc.v:41948$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71458,10 +71460,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$127 connect \B \$1360 - connect \Y $or$libresoc.v:41946$1643_Y + connect \Y $or$libresoc.v:41948$1643_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41947$1644 + cell $or $or$libresoc.v:41949$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71469,10 +71471,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$130 connect \B \fus_dest2_o$131 - connect \Y $or$libresoc.v:41947$1644_Y + connect \Y $or$libresoc.v:41949$1644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41948$1645 + cell $or $or$libresoc.v:41950$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71480,10 +71482,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$129 connect \B \$1364 - connect \Y $or$libresoc.v:41948$1645_Y + connect \Y $or$libresoc.v:41950$1645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41949$1646 + cell $or $or$libresoc.v:41951$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71491,10 +71493,10 @@ module \core parameter \Y_WIDTH 4 connect \A \$1362 connect \B \$1366 - connect \Y $or$libresoc.v:41949$1646_Y + connect \Y $or$libresoc.v:41951$1646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41950$1647 + cell $or $or$libresoc.v:41952$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71502,10 +71504,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1273 connect \B \addr_en$1293 - connect \Y $or$libresoc.v:41950$1647_Y + connect \Y $or$libresoc.v:41952$1647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41951$1648 + cell $or $or$libresoc.v:41953$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71513,10 +71515,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1253 connect \B \$1371 - connect \Y $or$libresoc.v:41951$1648_Y + connect \Y $or$libresoc.v:41953$1648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41952$1649 + cell $or $or$libresoc.v:41954$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71524,10 +71526,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1333 connect \B \addr_en$1353 - connect \Y $or$libresoc.v:41952$1649_Y + connect \Y $or$libresoc.v:41954$1649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41953$1650 + cell $or $or$libresoc.v:41955$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71535,10 +71537,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1313 connect \B \$1375 - connect \Y $or$libresoc.v:41953$1650_Y + connect \Y $or$libresoc.v:41955$1650_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41954$1651 + cell $or $or$libresoc.v:41956$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71546,10 +71548,10 @@ module \core parameter \Y_WIDTH 256 connect \A \$1373 connect \B \$1377 - connect \Y $or$libresoc.v:41954$1651_Y + connect \Y $or$libresoc.v:41956$1651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41976$1673 + cell $or $or$libresoc.v:41978$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71557,10 +71559,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest6_o connect \B \fus_dest3_o$135 - connect \Y $or$libresoc.v:41976$1673_Y + connect \Y $or$libresoc.v:41978$1673_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41977$1674 + cell $or $or$libresoc.v:41979$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71568,10 +71570,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest3_o$134 connect \B \$1435 - connect \Y $or$libresoc.v:41977$1674_Y + connect \Y $or$libresoc.v:41979$1674_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:41978$1675 + cell $or $or$libresoc.v:41980$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71579,10 +71581,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en$1416 connect \B \addr_en$1432 - connect \Y $or$libresoc.v:41978$1675_Y + connect \Y $or$libresoc.v:41980$1675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:41979$1676 + cell $or $or$libresoc.v:41981$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71590,10 +71592,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en$1400 connect \B \$1440 - connect \Y $or$libresoc.v:41979$1676_Y + connect \Y $or$libresoc.v:41981$1676_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42009$1707 + cell $or $or$libresoc.v:42011$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71601,10 +71603,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest4_o connect \B \fus_dest5_o - connect \Y $or$libresoc.v:42009$1707_Y + connect \Y $or$libresoc.v:42011$1707_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42010$1708 + cell $or $or$libresoc.v:42012$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71612,10 +71614,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest3_o$139 connect \B \fus_dest3_o$140 - connect \Y $or$libresoc.v:42010$1708_Y + connect \Y $or$libresoc.v:42012$1708_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42011$1709 + cell $or $or$libresoc.v:42013$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71623,10 +71625,10 @@ module \core parameter \Y_WIDTH 2 connect \A \$1517 connect \B \$1519 - connect \Y $or$libresoc.v:42011$1709_Y + connect \Y $or$libresoc.v:42013$1709_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42012$1710 + cell $or $or$libresoc.v:42014$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71634,10 +71636,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1466 connect \B \addr_en$1482 - connect \Y $or$libresoc.v:42012$1710_Y + connect \Y $or$libresoc.v:42014$1710_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42013$1711 + cell $or $or$libresoc.v:42015$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71645,10 +71647,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1498 connect \B \addr_en$1514 - connect \Y $or$libresoc.v:42013$1711_Y + connect \Y $or$libresoc.v:42015$1711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42014$1712 + cell $or $or$libresoc.v:42016$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71656,10 +71658,10 @@ module \core parameter \Y_WIDTH 3 connect \A \$1523 connect \B \$1525 - connect \Y $or$libresoc.v:42014$1712_Y + connect \Y $or$libresoc.v:42016$1712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42043$1741 + cell $or $or$libresoc.v:42045$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71667,10 +71669,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest5_o$144 connect \B \fus_dest4_o$145 - connect \Y $or$libresoc.v:42043$1741_Y + connect \Y $or$libresoc.v:42045$1741_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42044$1742 + cell $or $or$libresoc.v:42046$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71678,10 +71680,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest4_o$146 connect \B \fus_dest4_o$147 - connect \Y $or$libresoc.v:42044$1742_Y + connect \Y $or$libresoc.v:42046$1742_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42045$1743 + cell $or $or$libresoc.v:42047$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71689,10 +71691,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1602 connect \B \$1604 - connect \Y $or$libresoc.v:42045$1743_Y + connect \Y $or$libresoc.v:42047$1743_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42047$1746 + cell $or $or$libresoc.v:42049$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71700,10 +71702,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en$1550 connect \B \addr_en$1566 - connect \Y $or$libresoc.v:42047$1746_Y + connect \Y $or$libresoc.v:42049$1746_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42048$1747 + cell $or $or$libresoc.v:42050$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71711,10 +71713,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en$1582 connect \B \addr_en$1598 - connect \Y $or$libresoc.v:42048$1747_Y + connect \Y $or$libresoc.v:42050$1747_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42049$1748 + cell $or $or$libresoc.v:42051$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71722,10 +71724,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1610 connect \B \$1612 - connect \Y $or$libresoc.v:42049$1748_Y + connect \Y $or$libresoc.v:42051$1748_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42086$1786 + cell $or $or$libresoc.v:42088$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71733,10 +71735,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$153 connect \B \fus_dest2_o$154 - connect \Y $or$libresoc.v:42086$1786_Y + connect \Y $or$libresoc.v:42088$1786_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42087$1787 + cell $or $or$libresoc.v:42089$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71744,10 +71746,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest2_o$156 connect \B \fus_dest3_o$157 - connect \Y $or$libresoc.v:42087$1787_Y + connect \Y $or$libresoc.v:42089$1787_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42088$1788 + cell $or $or$libresoc.v:42090$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71755,10 +71757,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest3_o$155 connect \B \$1712 - connect \Y $or$libresoc.v:42088$1788_Y + connect \Y $or$libresoc.v:42090$1788_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42089$1789 + cell $or $or$libresoc.v:42091$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71766,10 +71768,10 @@ module \core parameter \Y_WIDTH 64 connect \A \$1710 connect \B \$1714 - connect \Y $or$libresoc.v:42089$1789_Y + connect \Y $or$libresoc.v:42091$1789_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42090$1790 + cell $or $or$libresoc.v:42092$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71777,10 +71779,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1643 connect \B \addr_en$1659 - connect \Y $or$libresoc.v:42090$1790_Y + connect \Y $or$libresoc.v:42092$1790_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42091$1791 + cell $or $or$libresoc.v:42093$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71788,10 +71790,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1691 connect \B \addr_en$1707 - connect \Y $or$libresoc.v:42091$1791_Y + connect \Y $or$libresoc.v:42093$1791_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42092$1792 + cell $or $or$libresoc.v:42094$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71799,10 +71801,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1675 connect \B \$1720 - connect \Y $or$libresoc.v:42092$1792_Y + connect \Y $or$libresoc.v:42094$1792_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42093$1793 + cell $or $or$libresoc.v:42095$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71810,10 +71812,10 @@ module \core parameter \Y_WIDTH 3 connect \A \$1718 connect \B \$1722 - connect \Y $or$libresoc.v:42093$1793_Y + connect \Y $or$libresoc.v:42095$1793_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42094$1794 + cell $or $or$libresoc.v:42096$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71821,10 +71823,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1640 connect \B \wp$1656 - connect \Y $or$libresoc.v:42094$1794_Y + connect \Y $or$libresoc.v:42096$1794_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42095$1795 + cell $or $or$libresoc.v:42097$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71832,10 +71834,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1688 connect \B \wp$1704 - connect \Y $or$libresoc.v:42095$1795_Y + connect \Y $or$libresoc.v:42097$1795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42096$1796 + cell $or $or$libresoc.v:42098$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71843,10 +71845,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1672 connect \B \$1728 - connect \Y $or$libresoc.v:42096$1796_Y + connect \Y $or$libresoc.v:42098$1796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42097$1797 + cell $or $or$libresoc.v:42099$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71854,10 +71856,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1726 connect \B \$1730 - connect \Y $or$libresoc.v:42097$1797_Y + connect \Y $or$libresoc.v:42099$1797_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42112$1812 + cell $or $or$libresoc.v:42114$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71865,10 +71867,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest3_o$159 connect \B \fus_dest4_o$160 - connect \Y $or$libresoc.v:42112$1812_Y + connect \Y $or$libresoc.v:42114$1812_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42113$1813 + cell $or $or$libresoc.v:42115$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71876,10 +71878,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en$1751 connect \B \addr_en$1767 - connect \Y $or$libresoc.v:42113$1813_Y + connect \Y $or$libresoc.v:42115$1813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42156$1858 + cell $or $or$libresoc.v:42158$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71887,10 +71889,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$224 connect \B \$228 - connect \Y $or$libresoc.v:42156$1858_Y + connect \Y $or$libresoc.v:42158$1858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42158$1860 + cell $or $or$libresoc.v:42160$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71898,10 +71900,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$230 connect \B \$232 - connect \Y $or$libresoc.v:42158$1860_Y + connect \Y $or$libresoc.v:42160$1860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42162$1864 + cell $or $or$libresoc.v:42164$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71909,10 +71911,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$236 connect \B \$240 - connect \Y $or$libresoc.v:42162$1864_Y + connect \Y $or$libresoc.v:42164$1864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42170$1872 + cell $or $or$libresoc.v:42172$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71920,10 +71922,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$252 connect \B \$256 - connect \Y $or$libresoc.v:42170$1872_Y + connect \Y $or$libresoc.v:42172$1872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42172$1874 + cell $or $or$libresoc.v:42174$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71931,10 +71933,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$258 connect \B \$260 - connect \Y $or$libresoc.v:42172$1874_Y + connect \Y $or$libresoc.v:42174$1874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42177$1879 + cell $or $or$libresoc.v:42179$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71942,10 +71944,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$266 connect \B \$270 - connect \Y $or$libresoc.v:42177$1879_Y + connect \Y $or$libresoc.v:42179$1879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42179$1881 + cell $or $or$libresoc.v:42181$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71953,10 +71955,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$272 connect \B \$274 - connect \Y $or$libresoc.v:42179$1881_Y + connect \Y $or$libresoc.v:42181$1881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42183$1885 + cell $or $or$libresoc.v:42185$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71964,10 +71966,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$278 connect \B \$282 - connect \Y $or$libresoc.v:42183$1885_Y + connect \Y $or$libresoc.v:42185$1885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42187$1889 + cell $or $or$libresoc.v:42189$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71975,10 +71977,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$286 connect \B \$290 - connect \Y $or$libresoc.v:42187$1889_Y + connect \Y $or$libresoc.v:42189$1889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42192$1894 + cell $or $or$libresoc.v:42194$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71986,10 +71988,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$296 connect \B \$300 - connect \Y $or$libresoc.v:42192$1894_Y + connect \Y $or$libresoc.v:42194$1894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42194$1896 + cell $or $or$libresoc.v:42196$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71997,10 +71999,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$302 connect \B \$304 - connect \Y $or$libresoc.v:42194$1896_Y + connect \Y $or$libresoc.v:42196$1896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42199$1901 + cell $or $or$libresoc.v:42201$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72008,10 +72010,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$310 connect \B \$314 - connect \Y $or$libresoc.v:42199$1901_Y + connect \Y $or$libresoc.v:42201$1901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42201$1903 + cell $or $or$libresoc.v:42203$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72019,10 +72021,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$316 connect \B \$318 - connect \Y $or$libresoc.v:42201$1903_Y + connect \Y $or$libresoc.v:42203$1903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42206$1908 + cell $or $or$libresoc.v:42208$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72030,10 +72032,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$324 connect \B \$328 - connect \Y $or$libresoc.v:42206$1908_Y + connect \Y $or$libresoc.v:42208$1908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42208$1910 + cell $or $or$libresoc.v:42210$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72041,10 +72043,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$330 connect \B \$332 - connect \Y $or$libresoc.v:42208$1910_Y + connect \Y $or$libresoc.v:42210$1910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42212$1914 + cell $or $or$libresoc.v:42214$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72052,10 +72054,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$336 connect \B \$340 - connect \Y $or$libresoc.v:42212$1914_Y + connect \Y $or$libresoc.v:42214$1914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42269$1971 + cell $or $or$libresoc.v:42271$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72063,10 +72065,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_alu0_0 connect \B \addr_en_INT_ra_cr0_1 - connect \Y $or$libresoc.v:42269$1971_Y + connect \Y $or$libresoc.v:42271$1971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42270$1972 + cell $or $or$libresoc.v:42272$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72074,10 +72076,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_trap0_2 connect \B \addr_en_INT_ra_logical0_3 - connect \Y $or$libresoc.v:42270$1972_Y + connect \Y $or$libresoc.v:42272$1972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42271$1973 + cell $or $or$libresoc.v:42273$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72085,10 +72087,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$456 connect \B \$458 - connect \Y $or$libresoc.v:42271$1973_Y + connect \Y $or$libresoc.v:42273$1973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42272$1974 + cell $or $or$libresoc.v:42274$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72096,10 +72098,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_spr0_4 connect \B \addr_en_INT_ra_div0_5 - connect \Y $or$libresoc.v:42272$1974_Y + connect \Y $or$libresoc.v:42274$1974_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42273$1975 + cell $or $or$libresoc.v:42275$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72107,10 +72109,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_shiftrot0_7 connect \B \addr_en_INT_ra_ldst0_8 - connect \Y $or$libresoc.v:42273$1975_Y + connect \Y $or$libresoc.v:42275$1975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42274$1976 + cell $or $or$libresoc.v:42276$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72118,10 +72120,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_mul0_6 connect \B \$464 - connect \Y $or$libresoc.v:42274$1976_Y + connect \Y $or$libresoc.v:42276$1976_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42275$1977 + cell $or $or$libresoc.v:42277$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72129,10 +72131,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$462 connect \B \$466 - connect \Y $or$libresoc.v:42275$1977_Y + connect \Y $or$libresoc.v:42277$1977_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42276$1978 + cell $or $or$libresoc.v:42278$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72140,10 +72142,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$460 connect \B \$468 - connect \Y $or$libresoc.v:42276$1978_Y + connect \Y $or$libresoc.v:42278$1978_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42326$2028 + cell $or $or$libresoc.v:42328$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72151,10 +72153,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_alu0_0 connect \B \addr_en_INT_rb_cr0_1 - connect \Y $or$libresoc.v:42326$2028_Y + connect \Y $or$libresoc.v:42328$2028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42327$2029 + cell $or $or$libresoc.v:42329$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72162,10 +72164,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_trap0_2 connect \B \addr_en_INT_rb_logical0_3 - connect \Y $or$libresoc.v:42327$2029_Y + connect \Y $or$libresoc.v:42329$2029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42328$2030 + cell $or $or$libresoc.v:42330$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72173,10 +72175,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$571 connect \B \$573 - connect \Y $or$libresoc.v:42328$2030_Y + connect \Y $or$libresoc.v:42330$2030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42329$2031 + cell $or $or$libresoc.v:42331$2031 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72184,10 +72186,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_div0_4 connect \B \addr_en_INT_rb_mul0_5 - connect \Y $or$libresoc.v:42329$2031_Y + connect \Y $or$libresoc.v:42331$2031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42330$2032 + cell $or $or$libresoc.v:42332$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72195,10 +72197,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_shiftrot0_6 connect \B \addr_en_INT_rb_ldst0_7 - connect \Y $or$libresoc.v:42330$2032_Y + connect \Y $or$libresoc.v:42332$2032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42331$2033 + cell $or $or$libresoc.v:42333$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72206,10 +72208,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$577 connect \B \$579 - connect \Y $or$libresoc.v:42331$2033_Y + connect \Y $or$libresoc.v:42333$2033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42332$2034 + cell $or $or$libresoc.v:42334$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72217,10 +72219,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$575 connect \B \$581 - connect \Y $or$libresoc.v:42332$2034_Y + connect \Y $or$libresoc.v:42334$2034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42346$2048 + cell $or $or$libresoc.v:42348$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72228,10 +72230,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rc_shiftrot0_0 connect \B \addr_en_INT_rc_ldst0_1 - connect \Y $or$libresoc.v:42346$2048_Y + connect \Y $or$libresoc.v:42348$2048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42351$2053 + cell $or $or$libresoc.v:42353$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72239,10 +72241,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$616 connect \B \$620 - connect \Y $or$libresoc.v:42351$2053_Y + connect \Y $or$libresoc.v:42353$2053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42353$2055 + cell $or $or$libresoc.v:42355$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72250,10 +72252,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$622 connect \B \$624 - connect \Y $or$libresoc.v:42353$2055_Y + connect \Y $or$libresoc.v:42355$2055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42390$2092 + cell $or $or$libresoc.v:42392$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72261,10 +72263,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_logical0_1 connect \B \addr_en_XER_xer_so_spr0_2 - connect \Y $or$libresoc.v:42390$2092_Y + connect \Y $or$libresoc.v:42392$2092_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42391$2093 + cell $or $or$libresoc.v:42393$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72272,10 +72274,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_alu0_0 connect \B \$701 - connect \Y $or$libresoc.v:42391$2093_Y + connect \Y $or$libresoc.v:42393$2093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42392$2094 + cell $or $or$libresoc.v:42394$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72283,10 +72285,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_mul0_4 connect \B \addr_en_XER_xer_so_shiftrot0_5 - connect \Y $or$libresoc.v:42392$2094_Y + connect \Y $or$libresoc.v:42394$2094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42393$2095 + cell $or $or$libresoc.v:42395$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72294,10 +72296,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_div0_3 connect \B \$705 - connect \Y $or$libresoc.v:42393$2095_Y + connect \Y $or$libresoc.v:42395$2095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42394$2096 + cell $or $or$libresoc.v:42396$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72305,10 +72307,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$703 connect \B \$707 - connect \Y $or$libresoc.v:42394$2096_Y + connect \Y $or$libresoc.v:42396$2096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42399$2102 + cell $or $or$libresoc.v:42401$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72316,10 +72318,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$712 connect \B \$716 - connect \Y $or$libresoc.v:42399$2102_Y + connect \Y $or$libresoc.v:42401$2102_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42418$2121 + cell $or $or$libresoc.v:42420$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72327,10 +72329,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_spr0_1 connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $or$libresoc.v:42418$2121_Y + connect \Y $or$libresoc.v:42420$2121_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42419$2122 + cell $or $or$libresoc.v:42421$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72338,10 +72340,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_alu0_0 connect \B \$757 - connect \Y $or$libresoc.v:42419$2122_Y + connect \Y $or$libresoc.v:42421$2122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42424$2128 + cell $or $or$libresoc.v:42426$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72349,10 +72351,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$762 connect \B \$766 - connect \Y $or$libresoc.v:42424$2128_Y + connect \Y $or$libresoc.v:42426$2128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42453$2157 + cell $or $or$libresoc.v:42455$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -72360,10 +72362,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en_CR_cr_a_cr0_0 connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $or$libresoc.v:42453$2157_Y + connect \Y $or$libresoc.v:42455$2157_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42488$2192 + cell $or $or$libresoc.v:42490$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72371,10 +72373,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_trap0_1 connect \B \addr_en_FAST_fast1_spr0_2 - connect \Y $or$libresoc.v:42488$2192_Y + connect \Y $or$libresoc.v:42490$2192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42489$2193 + cell $or $or$libresoc.v:42491$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72382,10 +72384,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_branch0_0 connect \B \$897 - connect \Y $or$libresoc.v:42489$2193_Y + connect \Y $or$libresoc.v:42491$2193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42503$2207 + cell $or $or$libresoc.v:42505$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72393,194 +72395,194 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast2_branch0_0 connect \B \addr_en_FAST_fast2_trap0_1 - connect \Y $or$libresoc.v:42503$2207_Y + connect \Y $or$libresoc.v:42505$2207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:41980$1678 + cell $pos $pos$libresoc.v:41982$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:41980$1677_Y - connect \Y $pos$libresoc.v:41980$1678_Y + connect \A $extend$libresoc.v:41982$1677_Y + connect \Y $pos$libresoc.v:41982$1678_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42046$1745 + cell $pos $pos$libresoc.v:42048$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:42046$1744_Y - connect \Y $pos$libresoc.v:42046$1745_Y + connect \A $extend$libresoc.v:42048$1744_Y + connect \Y $pos$libresoc.v:42048$1745_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42050$1750 + cell $pos $pos$libresoc.v:42052$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42050$1749_Y - connect \Y $pos$libresoc.v:42050$1750_Y + connect \A $extend$libresoc.v:42052$1749_Y + connect \Y $pos$libresoc.v:42052$1750_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $pos $pos$libresoc.v:42114$1815 + cell $pos $pos$libresoc.v:42116$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42114$1814_Y - connect \Y $pos$libresoc.v:42114$1815_Y + connect \A $extend$libresoc.v:42116$1814_Y + connect \Y $pos$libresoc.v:42116$1815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $pos $pos$libresoc.v:42124$1826 + cell $pos $pos$libresoc.v:42126$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42124$1825_Y - connect \Y $pos$libresoc.v:42124$1826_Y + connect \A $extend$libresoc.v:42126$1825_Y + connect \Y $pos$libresoc.v:42126$1826_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42395$2098 + cell $pos $pos$libresoc.v:42397$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42395$2097_Y - connect \Y $pos$libresoc.v:42395$2098_Y + connect \A $extend$libresoc.v:42397$2097_Y + connect \Y $pos$libresoc.v:42397$2098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42420$2124 + cell $pos $pos$libresoc.v:42422$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42420$2123_Y - connect \Y $pos$libresoc.v:42420$2124_Y + connect \A $extend$libresoc.v:42422$2123_Y + connect \Y $pos$libresoc.v:42422$2124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42121$1822 + cell $reduce_or $reduce_or$libresoc.v:42123$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A \$177 - connect \Y $reduce_or$libresoc.v:42121$1822_Y + connect \Y $reduce_or$libresoc.v:42123$1822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42133$1835 + cell $reduce_or $reduce_or$libresoc.v:42135$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A \$181 - connect \Y $reduce_or$libresoc.v:42133$1835_Y + connect \Y $reduce_or$libresoc.v:42135$1835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42135$1837 + cell $reduce_or $reduce_or$libresoc.v:42137$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A \$185 - connect \Y $reduce_or$libresoc.v:42135$1837_Y + connect \Y $reduce_or$libresoc.v:42137$1837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42137$1839 + cell $reduce_or $reduce_or$libresoc.v:42139$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A \$189 - connect \Y $reduce_or$libresoc.v:42137$1839_Y + connect \Y $reduce_or$libresoc.v:42139$1839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42139$1841 + cell $reduce_or $reduce_or$libresoc.v:42141$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A \$193 - connect \Y $reduce_or$libresoc.v:42139$1841_Y + connect \Y $reduce_or$libresoc.v:42141$1841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42141$1843 + cell $reduce_or $reduce_or$libresoc.v:42143$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A \$197 - connect \Y $reduce_or$libresoc.v:42141$1843_Y + connect \Y $reduce_or$libresoc.v:42143$1843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42143$1845 + cell $reduce_or $reduce_or$libresoc.v:42145$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A \$201 - connect \Y $reduce_or$libresoc.v:42143$1845_Y + connect \Y $reduce_or$libresoc.v:42145$1845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42145$1847 + cell $reduce_or $reduce_or$libresoc.v:42147$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A \$205 - connect \Y $reduce_or$libresoc.v:42145$1847_Y + connect \Y $reduce_or$libresoc.v:42147$1847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42147$1849 + cell $reduce_or $reduce_or$libresoc.v:42149$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A \$209 - connect \Y $reduce_or$libresoc.v:42147$1849_Y + connect \Y $reduce_or$libresoc.v:42149$1849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $reduce_or $reduce_or$libresoc.v:42149$1851 + cell $reduce_or $reduce_or$libresoc.v:42151$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \Y_WIDTH 1 connect \A \$213 - connect \Y $reduce_or$libresoc.v:42149$1851_Y + connect \Y $reduce_or$libresoc.v:42151$1851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42277$1979 + cell $reduce_or $reduce_or$libresoc.v:42279$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } - connect \Y $reduce_or$libresoc.v:42277$1979_Y + connect \Y $reduce_or$libresoc.v:42279$1979_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42333$2035 + cell $reduce_or $reduce_or$libresoc.v:42335$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } - connect \Y $reduce_or$libresoc.v:42333$2035_Y + connect \Y $reduce_or$libresoc.v:42335$2035_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42347$2049 + cell $reduce_or $reduce_or$libresoc.v:42349$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } - connect \Y $reduce_or$libresoc.v:42347$2049_Y + connect \Y $reduce_or$libresoc.v:42349$2049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42490$2194 + cell $reduce_or $reduce_or$libresoc.v:42492$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } - connect \Y $reduce_or$libresoc.v:42490$2194_Y + connect \Y $reduce_or$libresoc.v:42492$2194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42504$2208 + cell $reduce_or $reduce_or$libresoc.v:42506$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } - connect \Y $reduce_or$libresoc.v:42504$2208_Y + connect \Y $reduce_or$libresoc.v:42506$2208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" - cell $reduce_or $reduce_or$libresoc.v:42511$2215 + cell $reduce_or $reduce_or$libresoc.v:42513$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rp_SPR_spr1_spr0_0 - connect \Y $reduce_or$libresoc.v:42511$2215_Y + connect \Y $reduce_or$libresoc.v:42513$2215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41903$1600 + cell $sshl $sshl$libresoc.v:41905$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72588,10 +72590,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1254 - connect \Y $sshl$libresoc.v:41903$1600_Y + connect \Y $sshl$libresoc.v:41905$1600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41911$1608 + cell $sshl $sshl$libresoc.v:41913$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72599,10 +72601,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1274 - connect \Y $sshl$libresoc.v:41911$1608_Y + connect \Y $sshl$libresoc.v:41913$1608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41919$1616 + cell $sshl $sshl$libresoc.v:41921$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72610,10 +72612,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1294 - connect \Y $sshl$libresoc.v:41919$1616_Y + connect \Y $sshl$libresoc.v:41921$1616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41927$1624 + cell $sshl $sshl$libresoc.v:41929$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72621,10 +72623,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1314 - connect \Y $sshl$libresoc.v:41927$1624_Y + connect \Y $sshl$libresoc.v:41929$1624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41935$1632 + cell $sshl $sshl$libresoc.v:41937$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72632,10 +72634,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1334 - connect \Y $sshl$libresoc.v:41935$1632_Y + connect \Y $sshl$libresoc.v:41937$1632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:41943$1640 + cell $sshl $sshl$libresoc.v:41945$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72643,10 +72645,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1354 - connect \Y $sshl$libresoc.v:41943$1640_Y + connect \Y $sshl$libresoc.v:41945$1640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42443$2147 + cell $sshl $sshl$libresoc.v:42445$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72654,10 +72656,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$804 - connect \Y $sshl$libresoc.v:42443$2147_Y + connect \Y $sshl$libresoc.v:42445$2147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42451$2155 + cell $sshl $sshl$libresoc.v:42453$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72665,10 +72667,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$820 - connect \Y $sshl$libresoc.v:42451$2155_Y + connect \Y $sshl$libresoc.v:42453$2155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sshl $sshl$libresoc.v:42460$2164 + cell $sshl $sshl$libresoc.v:42462$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72676,10 +72678,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$839 - connect \Y $sshl$libresoc.v:42460$2164_Y + connect \Y $sshl$libresoc.v:42462$2164_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sshl $sshl$libresoc.v:42468$2172 + cell $sshl $sshl$libresoc.v:42470$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72687,10 +72689,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$855 - connect \Y $sshl$libresoc.v:42468$2172_Y + connect \Y $sshl$libresoc.v:42470$2172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41902$1599 + cell $sub $sub$libresoc.v:41904$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72698,10 +72700,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41902$1599_Y + connect \Y $sub$libresoc.v:41904$1599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41910$1607 + cell $sub $sub$libresoc.v:41912$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72709,10 +72711,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41910$1607_Y + connect \Y $sub$libresoc.v:41912$1607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41918$1615 + cell $sub $sub$libresoc.v:41920$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72720,10 +72722,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41918$1615_Y + connect \Y $sub$libresoc.v:41920$1615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41926$1623 + cell $sub $sub$libresoc.v:41928$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72731,10 +72733,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41926$1623_Y + connect \Y $sub$libresoc.v:41928$1623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41934$1631 + cell $sub $sub$libresoc.v:41936$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72742,10 +72744,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41934$1631_Y + connect \Y $sub$libresoc.v:41936$1631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:41942$1639 + cell $sub $sub$libresoc.v:41944$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72753,10 +72755,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:41942$1639_Y + connect \Y $sub$libresoc.v:41944$1639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $sub $sub$libresoc.v:42151$1853 + cell $sub $sub$libresoc.v:42153$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72764,10 +72766,10 @@ module \core parameter \Y_WIDTH 3 connect \A \counter connect \B 1'1 - connect \Y $sub$libresoc.v:42151$1853_Y + connect \Y $sub$libresoc.v:42153$1853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42442$2146 + cell $sub $sub$libresoc.v:42444$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72775,10 +72777,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42442$2146_Y + connect \Y $sub$libresoc.v:42444$2146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42450$2154 + cell $sub $sub$libresoc.v:42452$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72786,10 +72788,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42450$2154_Y + connect \Y $sub$libresoc.v:42452$2154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sub $sub$libresoc.v:42459$2163 + cell $sub $sub$libresoc.v:42461$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72797,10 +72799,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2 - connect \Y $sub$libresoc.v:42459$2163_Y + connect \Y $sub$libresoc.v:42461$2163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sub $sub$libresoc.v:42467$2171 + cell $sub $sub$libresoc.v:42469$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72808,626 +72810,626 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2$1 - connect \Y $sub$libresoc.v:42467$2171_Y + connect \Y $sub$libresoc.v:42469$2171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41814$1511 + cell $mux $ternary$libresoc.v:41816$1511 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1015 - connect \Y $ternary$libresoc.v:41814$1511_Y + connect \Y $ternary$libresoc.v:41816$1511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41820$1517 + cell $mux $ternary$libresoc.v:41822$1517 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1033 - connect \Y $ternary$libresoc.v:41820$1517_Y + connect \Y $ternary$libresoc.v:41822$1517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41826$1523 + cell $mux $ternary$libresoc.v:41828$1523 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1055 - connect \Y $ternary$libresoc.v:41826$1523_Y + connect \Y $ternary$libresoc.v:41828$1523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41832$1529 + cell $mux $ternary$libresoc.v:41834$1529 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1075 - connect \Y $ternary$libresoc.v:41832$1529_Y + connect \Y $ternary$libresoc.v:41834$1529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41838$1535 + cell $mux $ternary$libresoc.v:41840$1535 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1095 - connect \Y $ternary$libresoc.v:41838$1535_Y + connect \Y $ternary$libresoc.v:41840$1535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41844$1541 + cell $mux $ternary$libresoc.v:41846$1541 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1114 - connect \Y $ternary$libresoc.v:41844$1541_Y + connect \Y $ternary$libresoc.v:41846$1541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41850$1547 + cell $mux $ternary$libresoc.v:41852$1547 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1132 - connect \Y $ternary$libresoc.v:41850$1547_Y + connect \Y $ternary$libresoc.v:41852$1547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41856$1553 + cell $mux $ternary$libresoc.v:41858$1553 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_ea connect \S \wp$1148 - connect \Y $ternary$libresoc.v:41856$1553_Y + connect \Y $ternary$libresoc.v:41858$1553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41890$1587 + cell $mux $ternary$libresoc.v:41892$1587 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_wr connect \S \wp$1222 - connect \Y $ternary$libresoc.v:41890$1587_Y + connect \Y $ternary$libresoc.v:41892$1587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41904$1601 + cell $mux $ternary$libresoc.v:41906$1601 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1256 connect \S \wp$1250 - connect \Y $ternary$libresoc.v:41904$1601_Y + connect \Y $ternary$libresoc.v:41906$1601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41912$1609 + cell $mux $ternary$libresoc.v:41914$1609 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1276 connect \S \wp$1270 - connect \Y $ternary$libresoc.v:41912$1609_Y + connect \Y $ternary$libresoc.v:41914$1609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41920$1617 + cell $mux $ternary$libresoc.v:41922$1617 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1296 connect \S \wp$1290 - connect \Y $ternary$libresoc.v:41920$1617_Y + connect \Y $ternary$libresoc.v:41922$1617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41928$1625 + cell $mux $ternary$libresoc.v:41930$1625 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1316 connect \S \wp$1310 - connect \Y $ternary$libresoc.v:41928$1625_Y + connect \Y $ternary$libresoc.v:41930$1625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41936$1633 + cell $mux $ternary$libresoc.v:41938$1633 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1336 connect \S \wp$1330 - connect \Y $ternary$libresoc.v:41936$1633_Y + connect \Y $ternary$libresoc.v:41938$1633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41944$1641 + cell $mux $ternary$libresoc.v:41946$1641 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1356 connect \S \wp$1350 - connect \Y $ternary$libresoc.v:41944$1641_Y + connect \Y $ternary$libresoc.v:41946$1641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41963$1660 + cell $mux $ternary$libresoc.v:41965$1660 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1397 - connect \Y $ternary$libresoc.v:41963$1660_Y + connect \Y $ternary$libresoc.v:41965$1660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41969$1666 + cell $mux $ternary$libresoc.v:41971$1666 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1413 - connect \Y $ternary$libresoc.v:41969$1666_Y + connect \Y $ternary$libresoc.v:41971$1666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41975$1672 + cell $mux $ternary$libresoc.v:41977$1672 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1429 - connect \Y $ternary$libresoc.v:41975$1672_Y + connect \Y $ternary$libresoc.v:41977$1672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41990$1688 + cell $mux $ternary$libresoc.v:41992$1688 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1463 - connect \Y $ternary$libresoc.v:41990$1688_Y + connect \Y $ternary$libresoc.v:41992$1688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:41996$1694 + cell $mux $ternary$libresoc.v:41998$1694 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1479 - connect \Y $ternary$libresoc.v:41996$1694_Y + connect \Y $ternary$libresoc.v:41998$1694_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42002$1700 + cell $mux $ternary$libresoc.v:42004$1700 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1495 - connect \Y $ternary$libresoc.v:42002$1700_Y + connect \Y $ternary$libresoc.v:42004$1700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42008$1706 + cell $mux $ternary$libresoc.v:42010$1706 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1511 - connect \Y $ternary$libresoc.v:42008$1706_Y + connect \Y $ternary$libresoc.v:42010$1706_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42024$1722 + cell $mux $ternary$libresoc.v:42026$1722 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1547 - connect \Y $ternary$libresoc.v:42024$1722_Y + connect \Y $ternary$libresoc.v:42026$1722_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42030$1728 + cell $mux $ternary$libresoc.v:42032$1728 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1563 - connect \Y $ternary$libresoc.v:42030$1728_Y + connect \Y $ternary$libresoc.v:42032$1728_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42036$1734 + cell $mux $ternary$libresoc.v:42038$1734 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1579 - connect \Y $ternary$libresoc.v:42036$1734_Y + connect \Y $ternary$libresoc.v:42038$1734_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42042$1740 + cell $mux $ternary$libresoc.v:42044$1740 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1595 - connect \Y $ternary$libresoc.v:42042$1740_Y + connect \Y $ternary$libresoc.v:42044$1740_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42061$1761 + cell $mux $ternary$libresoc.v:42063$1761 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1640 - connect \Y $ternary$libresoc.v:42061$1761_Y + connect \Y $ternary$libresoc.v:42063$1761_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42067$1767 + cell $mux $ternary$libresoc.v:42069$1767 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1656 - connect \Y $ternary$libresoc.v:42067$1767_Y + connect \Y $ternary$libresoc.v:42069$1767_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42073$1773 + cell $mux $ternary$libresoc.v:42075$1773 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1672 - connect \Y $ternary$libresoc.v:42073$1773_Y + connect \Y $ternary$libresoc.v:42075$1773_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42079$1779 + cell $mux $ternary$libresoc.v:42081$1779 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 connect \S \wp$1688 - connect \Y $ternary$libresoc.v:42079$1779_Y + connect \Y $ternary$libresoc.v:42081$1779_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42085$1785 + cell $mux $ternary$libresoc.v:42087$1785 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 connect \S \wp$1704 - connect \Y $ternary$libresoc.v:42085$1785_Y + connect \Y $ternary$libresoc.v:42087$1785_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42105$1805 + cell $mux $ternary$libresoc.v:42107$1805 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1748 - connect \Y $ternary$libresoc.v:42105$1805_Y + connect \Y $ternary$libresoc.v:42107$1805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42111$1811 + cell $mux $ternary$libresoc.v:42113$1811 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1764 - connect \Y $ternary$libresoc.v:42111$1811_Y + connect \Y $ternary$libresoc.v:42113$1811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42123$1824 + cell $mux $ternary$libresoc.v:42125$1824 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1788 - connect \Y $ternary$libresoc.v:42123$1824_Y + connect \Y $ternary$libresoc.v:42125$1824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42131$1833 + cell $mux $ternary$libresoc.v:42133$1833 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spro connect \S \wp$1808 - connect \Y $ternary$libresoc.v:42131$1833_Y + connect \Y $ternary$libresoc.v:42133$1833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42220$1922 + cell $mux $ternary$libresoc.v:42222$1922 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_alu0_0 - connect \Y $ternary$libresoc.v:42220$1922_Y + connect \Y $ternary$libresoc.v:42222$1922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42226$1928 + cell $mux $ternary$libresoc.v:42228$1928 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_cr0_1 - connect \Y $ternary$libresoc.v:42226$1928_Y + connect \Y $ternary$libresoc.v:42228$1928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42232$1934 + cell $mux $ternary$libresoc.v:42234$1934 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_trap0_2 - connect \Y $ternary$libresoc.v:42232$1934_Y + connect \Y $ternary$libresoc.v:42234$1934_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42238$1940 + cell $mux $ternary$libresoc.v:42240$1940 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_logical0_3 - connect \Y $ternary$libresoc.v:42238$1940_Y + connect \Y $ternary$libresoc.v:42240$1940_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42244$1946 + cell $mux $ternary$libresoc.v:42246$1946 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_spr0_4 - connect \Y $ternary$libresoc.v:42244$1946_Y + connect \Y $ternary$libresoc.v:42246$1946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42250$1952 + cell $mux $ternary$libresoc.v:42252$1952 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_div0_5 - connect \Y $ternary$libresoc.v:42250$1952_Y + connect \Y $ternary$libresoc.v:42252$1952_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42256$1958 + cell $mux $ternary$libresoc.v:42258$1958 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_mul0_6 - connect \Y $ternary$libresoc.v:42256$1958_Y + connect \Y $ternary$libresoc.v:42258$1958_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42262$1964 + cell $mux $ternary$libresoc.v:42264$1964 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_shiftrot0_7 - connect \Y $ternary$libresoc.v:42262$1964_Y + connect \Y $ternary$libresoc.v:42264$1964_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42268$1970 + cell $mux $ternary$libresoc.v:42270$1970 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_ldst0_8 - connect \Y $ternary$libresoc.v:42268$1970_Y + connect \Y $ternary$libresoc.v:42270$1970_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42283$1985 + cell $mux $ternary$libresoc.v:42285$1985 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_alu0_0 - connect \Y $ternary$libresoc.v:42283$1985_Y + connect \Y $ternary$libresoc.v:42285$1985_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42289$1991 + cell $mux $ternary$libresoc.v:42291$1991 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_cr0_1 - connect \Y $ternary$libresoc.v:42289$1991_Y + connect \Y $ternary$libresoc.v:42291$1991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42295$1997 + cell $mux $ternary$libresoc.v:42297$1997 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_trap0_2 - connect \Y $ternary$libresoc.v:42295$1997_Y + connect \Y $ternary$libresoc.v:42297$1997_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42301$2003 + cell $mux $ternary$libresoc.v:42303$2003 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_logical0_3 - connect \Y $ternary$libresoc.v:42301$2003_Y + connect \Y $ternary$libresoc.v:42303$2003_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42307$2009 + cell $mux $ternary$libresoc.v:42309$2009 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_div0_4 - connect \Y $ternary$libresoc.v:42307$2009_Y + connect \Y $ternary$libresoc.v:42309$2009_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42313$2015 + cell $mux $ternary$libresoc.v:42315$2015 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_mul0_5 - connect \Y $ternary$libresoc.v:42313$2015_Y + connect \Y $ternary$libresoc.v:42315$2015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42319$2021 + cell $mux $ternary$libresoc.v:42321$2021 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_shiftrot0_6 - connect \Y $ternary$libresoc.v:42319$2021_Y + connect \Y $ternary$libresoc.v:42321$2021_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42325$2027 + cell $mux $ternary$libresoc.v:42327$2027 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_ldst0_7 - connect \Y $ternary$libresoc.v:42325$2027_Y + connect \Y $ternary$libresoc.v:42327$2027_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42339$2041 + cell $mux $ternary$libresoc.v:42341$2041 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rc_shiftrot0_0 - connect \Y $ternary$libresoc.v:42339$2041_Y + connect \Y $ternary$libresoc.v:42341$2041_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42345$2047 + cell $mux $ternary$libresoc.v:42347$2047 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rc_ldst0_1 - connect \Y $ternary$libresoc.v:42345$2047_Y + connect \Y $ternary$libresoc.v:42347$2047_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42359$2061 + cell $mux $ternary$libresoc.v:42361$2061 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_alu0_0 - connect \Y $ternary$libresoc.v:42359$2061_Y + connect \Y $ternary$libresoc.v:42361$2061_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42365$2067 + cell $mux $ternary$libresoc.v:42367$2067 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_logical0_1 - connect \Y $ternary$libresoc.v:42365$2067_Y + connect \Y $ternary$libresoc.v:42367$2067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42371$2073 + cell $mux $ternary$libresoc.v:42373$2073 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_spr0_2 - connect \Y $ternary$libresoc.v:42371$2073_Y + connect \Y $ternary$libresoc.v:42373$2073_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42377$2079 + cell $mux $ternary$libresoc.v:42379$2079 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_div0_3 - connect \Y $ternary$libresoc.v:42377$2079_Y + connect \Y $ternary$libresoc.v:42379$2079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42383$2085 + cell $mux $ternary$libresoc.v:42385$2085 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_mul0_4 - connect \Y $ternary$libresoc.v:42383$2085_Y + connect \Y $ternary$libresoc.v:42385$2085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42389$2091 + cell $mux $ternary$libresoc.v:42391$2091 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_shiftrot0_5 - connect \Y $ternary$libresoc.v:42389$2091_Y + connect \Y $ternary$libresoc.v:42391$2091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42405$2108 + cell $mux $ternary$libresoc.v:42407$2108 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $ternary$libresoc.v:42405$2108_Y + connect \Y $ternary$libresoc.v:42407$2108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42411$2114 + cell $mux $ternary$libresoc.v:42413$2114 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $ternary$libresoc.v:42411$2114_Y + connect \Y $ternary$libresoc.v:42413$2114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42417$2120 + cell $mux $ternary$libresoc.v:42419$2120 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $ternary$libresoc.v:42417$2120_Y + connect \Y $ternary$libresoc.v:42419$2120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42430$2134 + cell $mux $ternary$libresoc.v:42432$2134 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $ternary$libresoc.v:42430$2134_Y + connect \Y $ternary$libresoc.v:42432$2134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42436$2140 + cell $mux $ternary$libresoc.v:42438$2140 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_rd connect \S \rp_CR_full_cr_cr0_0 - connect \Y $ternary$libresoc.v:42436$2140_Y + connect \Y $ternary$libresoc.v:42438$2140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42444$2148 + cell $mux $ternary$libresoc.v:42446$2148 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$806 connect \S \rp_CR_cr_a_cr0_0 - connect \Y $ternary$libresoc.v:42444$2148_Y + connect \Y $ternary$libresoc.v:42446$2148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42452$2156 + cell $mux $ternary$libresoc.v:42454$2156 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$822 connect \S \rp_CR_cr_a_branch0_1 - connect \Y $ternary$libresoc.v:42452$2156_Y + connect \Y $ternary$libresoc.v:42454$2156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42461$2165 + cell $mux $ternary$libresoc.v:42463$2165 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$841 connect \S \rp_CR_cr_b_cr0_0 - connect \Y $ternary$libresoc.v:42461$2165_Y + connect \Y $ternary$libresoc.v:42463$2165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42469$2173 + cell $mux $ternary$libresoc.v:42471$2173 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$857 connect \S \rp_CR_cr_c_cr0_0 - connect \Y $ternary$libresoc.v:42469$2173_Y + connect \Y $ternary$libresoc.v:42471$2173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42475$2179 + cell $mux $ternary$libresoc.v:42477$2179 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_branch0_0 - connect \Y $ternary$libresoc.v:42475$2179_Y + connect \Y $ternary$libresoc.v:42477$2179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42481$2185 + cell $mux $ternary$libresoc.v:42483$2185 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_trap0_1 - connect \Y $ternary$libresoc.v:42481$2185_Y + connect \Y $ternary$libresoc.v:42483$2185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42487$2191 + cell $mux $ternary$libresoc.v:42489$2191 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_spr0_2 - connect \Y $ternary$libresoc.v:42487$2191_Y + connect \Y $ternary$libresoc.v:42489$2191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42496$2200 + cell $mux $ternary$libresoc.v:42498$2200 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast2_branch0_0 - connect \Y $ternary$libresoc.v:42496$2200_Y + connect \Y $ternary$libresoc.v:42498$2200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42502$2206 + cell $mux $ternary$libresoc.v:42504$2206 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast2_trap0_1 - connect \Y $ternary$libresoc.v:42502$2206_Y + connect \Y $ternary$libresoc.v:42504$2206_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" - cell $mux $ternary$libresoc.v:42510$2214 + cell $mux $ternary$libresoc.v:42512$2214 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spr1 connect \S \rp_SPR_spr1_spr0_0 - connect \Y $ternary$libresoc.v:42510$2214_Y + connect \Y $ternary$libresoc.v:42512$2214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42527$2231 + cell $mux $ternary$libresoc.v:42529$2231 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp - connect \Y $ternary$libresoc.v:42527$2231_Y + connect \Y $ternary$libresoc.v:42529$2231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $mux $ternary$libresoc.v:42533$2237 + cell $mux $ternary$libresoc.v:42535$2237 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$994 - connect \Y $ternary$libresoc.v:42533$2237_Y + connect \Y $ternary$libresoc.v:42535$2237_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:42692.6-42709.4" + attribute \src "libresoc.v:42694.6-42711.4" cell \cr \cr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73447,7 +73449,7 @@ module \core connect \wen \cr_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:42710.11-42731.4" + attribute \src "libresoc.v:42712.11-42733.4" cell \dec_ALU \dec_ALU connect \ALU__data_len \dec_ALU_ALU__data_len connect \ALU__fn_unit \dec_ALU_ALU__fn_unit @@ -73471,7 +73473,7 @@ module \core connect \raw_opcode_in \dec_ALU_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42732.14-42744.4" + attribute \src "libresoc.v:42734.14-42746.4" cell \dec_BRANCH \dec_BRANCH connect \BRANCH__cia \dec_BRANCH_BRANCH__cia connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit @@ -73486,7 +73488,7 @@ module \core connect \raw_opcode_in \dec_BRANCH_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42745.10-42751.4" + attribute \src "libresoc.v:42747.10-42753.4" cell \dec_CR \dec_CR connect \CR__fn_unit \dec_CR_CR__fn_unit connect \CR__insn \dec_CR_CR__insn @@ -73495,7 +73497,7 @@ module \core connect \raw_opcode_in \dec_CR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42752.11-42773.4" + attribute \src "libresoc.v:42754.11-42775.4" cell \dec_DIV \dec_DIV connect \DIV__data_len \dec_DIV_DIV__data_len connect \DIV__fn_unit \dec_DIV_DIV__fn_unit @@ -73519,7 +73521,7 @@ module \core connect \raw_opcode_in \dec_DIV_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42774.12-42793.4" + attribute \src "libresoc.v:42776.12-42795.4" cell \dec_LDST \dec_LDST connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse connect \LDST__data_len \dec_LDST_LDST__data_len @@ -73541,7 +73543,7 @@ module \core connect \raw_opcode_in \dec_LDST_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42794.15-42815.4" + attribute \src "libresoc.v:42796.15-42817.4" cell \dec_LOGICAL \dec_LOGICAL connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit @@ -73565,7 +73567,7 @@ module \core connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42816.11-42831.4" + attribute \src "libresoc.v:42818.11-42833.4" cell \dec_MUL \dec_MUL connect \MUL__fn_unit \dec_MUL_MUL__fn_unit connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data @@ -73583,7 +73585,7 @@ module \core connect \raw_opcode_in \dec_MUL_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42832.17-42852.4" + attribute \src "libresoc.v:42834.17-42854.4" cell \dec_SHIFT_ROT \dec_SHIFT_ROT connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data @@ -73606,7 +73608,7 @@ module \core connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42853.11-42860.4" + attribute \src "libresoc.v:42855.11-42862.4" cell \dec_SPR \dec_SPR connect \SPR__fn_unit \dec_SPR_SPR__fn_unit connect \SPR__insn \dec_SPR_SPR__insn @@ -73616,7 +73618,7 @@ module \core connect \raw_opcode_in \dec_SPR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:42861.8-42879.4" + attribute \src "libresoc.v:42863.8-42881.4" cell \fast \fast connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73637,7 +73639,7 @@ module \core connect \src2__ren \fast_src2__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:42880.7-43211.4" + attribute \src "libresoc.v:42882.7-43213.4" cell \fus \fus connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73971,7 +73973,7 @@ module \core connect \xer_so_ok$131 \fus_xer_so_ok$143 end attribute \module_not_derived 1 - attribute \src "libresoc.v:43212.9-43230.4" + attribute \src "libresoc.v:43214.9-43232.4" cell \int \int connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73992,7 +73994,7 @@ module \core connect \src3__ren \int_src3__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:43231.6-43263.4" + attribute \src "libresoc.v:43233.6-43265.4" cell \l0 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74027,98 +74029,98 @@ module \core connect \wb_dcache_en \wb_dcache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:43264.18-43268.4" + attribute \src "libresoc.v:43266.18-43270.4" cell \rdpick_CR_cr_a \rdpick_CR_cr_a connect \en_o \rdpick_CR_cr_a_en_o connect \i \rdpick_CR_cr_a_i connect \o \rdpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43269.18-43273.4" + attribute \src "libresoc.v:43271.18-43275.4" cell \rdpick_CR_cr_b \rdpick_CR_cr_b connect \en_o \rdpick_CR_cr_b_en_o connect \i \rdpick_CR_cr_b_i connect \o \rdpick_CR_cr_b_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43274.18-43278.4" + attribute \src "libresoc.v:43276.18-43280.4" cell \rdpick_CR_cr_c \rdpick_CR_cr_c connect \en_o \rdpick_CR_cr_c_en_o connect \i \rdpick_CR_cr_c_i connect \o \rdpick_CR_cr_c_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43279.21-43283.4" + attribute \src "libresoc.v:43281.21-43285.4" cell \rdpick_CR_full_cr \rdpick_CR_full_cr connect \en_o \rdpick_CR_full_cr_en_o connect \i \rdpick_CR_full_cr_i connect \o \rdpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43284.21-43288.4" + attribute \src "libresoc.v:43286.21-43290.4" cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 connect \en_o \rdpick_FAST_fast1_en_o connect \i \rdpick_FAST_fast1_i connect \o \rdpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43289.21-43293.4" + attribute \src "libresoc.v:43291.21-43295.4" cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 connect \en_o \rdpick_FAST_fast2_en_o connect \i \rdpick_FAST_fast2_i connect \o \rdpick_FAST_fast2_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43294.17-43298.4" + attribute \src "libresoc.v:43296.17-43300.4" cell \rdpick_INT_ra \rdpick_INT_ra connect \en_o \rdpick_INT_ra_en_o connect \i \rdpick_INT_ra_i connect \o \rdpick_INT_ra_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43299.17-43303.4" + attribute \src "libresoc.v:43301.17-43305.4" cell \rdpick_INT_rb \rdpick_INT_rb connect \en_o \rdpick_INT_rb_en_o connect \i \rdpick_INT_rb_i connect \o \rdpick_INT_rb_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43304.17-43308.4" + attribute \src "libresoc.v:43306.17-43310.4" cell \rdpick_INT_rc \rdpick_INT_rc connect \en_o \rdpick_INT_rc_en_o connect \i \rdpick_INT_rc_i connect \o \rdpick_INT_rc_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43309.19-43313.4" + attribute \src "libresoc.v:43311.19-43315.4" cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 connect \en_o \rdpick_SPR_spr1_en_o connect \i \rdpick_SPR_spr1_i connect \o \rdpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43314.21-43318.4" + attribute \src "libresoc.v:43316.21-43320.4" cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca connect \en_o \rdpick_XER_xer_ca_en_o connect \i \rdpick_XER_xer_ca_i connect \o \rdpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43319.21-43323.4" + attribute \src "libresoc.v:43321.21-43325.4" cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov connect \en_o \rdpick_XER_xer_ov_en_o connect \i \rdpick_XER_xer_ov_i connect \o \rdpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43324.21-43328.4" + attribute \src "libresoc.v:43326.21-43330.4" cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \en_o \rdpick_XER_xer_so_en_o connect \i \rdpick_XER_xer_so_i connect \o \rdpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43329.7-43338.4" + attribute \src "libresoc.v:43331.7-43340.4" cell \spr \spr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74130,7 +74132,7 @@ module \core connect \spr1__wen \spr_spr1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43339.9-43356.4" + attribute \src "libresoc.v:43341.9-43358.4" cell \state \state connect \cia__data_o \cia__data_o connect \cia__ren \cia__ren @@ -74150,77 +74152,77 @@ module \core connect \wen$5 \state_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43357.18-43361.4" + attribute \src "libresoc.v:43359.18-43363.4" cell \wrpick_CR_cr_a \wrpick_CR_cr_a connect \en_o \wrpick_CR_cr_a_en_o connect \i \wrpick_CR_cr_a_i connect \o \wrpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43362.21-43366.4" + attribute \src "libresoc.v:43364.21-43368.4" cell \wrpick_CR_full_cr \wrpick_CR_full_cr connect \en_o \wrpick_CR_full_cr_en_o connect \i \wrpick_CR_full_cr_i connect \o \wrpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43367.21-43371.4" + attribute \src "libresoc.v:43369.21-43373.4" cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 connect \en_o \wrpick_FAST_fast1_en_o connect \i \wrpick_FAST_fast1_i connect \o \wrpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43372.16-43376.4" + attribute \src "libresoc.v:43374.16-43378.4" cell \wrpick_INT_o \wrpick_INT_o connect \en_o \wrpick_INT_o_en_o connect \i \wrpick_INT_o_i connect \o \wrpick_INT_o_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43377.19-43381.4" + attribute \src "libresoc.v:43379.19-43383.4" cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 connect \en_o \wrpick_SPR_spr1_en_o connect \i \wrpick_SPR_spr1_i connect \o \wrpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43382.20-43386.4" + attribute \src "libresoc.v:43384.20-43388.4" cell \wrpick_STATE_msr \wrpick_STATE_msr connect \en_o \wrpick_STATE_msr_en_o connect \i \wrpick_STATE_msr_i connect \o \wrpick_STATE_msr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43387.20-43391.4" + attribute \src "libresoc.v:43389.20-43393.4" cell \wrpick_STATE_nia \wrpick_STATE_nia connect \en_o \wrpick_STATE_nia_en_o connect \i \wrpick_STATE_nia_i connect \o \wrpick_STATE_nia_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43392.21-43396.4" + attribute \src "libresoc.v:43394.21-43398.4" cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \en_o \wrpick_XER_xer_ca_en_o connect \i \wrpick_XER_xer_ca_i connect \o \wrpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43397.21-43401.4" + attribute \src "libresoc.v:43399.21-43403.4" cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \en_o \wrpick_XER_xer_ov_en_o connect \i \wrpick_XER_xer_ov_i connect \o \wrpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43402.21-43406.4" + attribute \src "libresoc.v:43404.21-43408.4" cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \en_o \wrpick_XER_xer_so_en_o connect \i \wrpick_XER_xer_so_i connect \o \wrpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43407.7-43424.4" + attribute \src "libresoc.v:43409.7-43426.4" cell \xer \xer connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74247,1199 +74249,1199 @@ module \core update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:38027.7-38027.30" - process $proc$libresoc.v:38027$2901 + attribute \src "libresoc.v:38029.7-38029.30" + process $proc$libresoc.v:38029$2901 assign { } { } assign $1\core_terminate_o[0:0] 1'0 sync always sync init update \core_terminate_o $1\core_terminate_o[0:0] end - attribute \src "libresoc.v:38040.13-38040.27" - process $proc$libresoc.v:38040$2902 + attribute \src "libresoc.v:38042.13-38042.27" + process $proc$libresoc.v:38042$2902 assign { } { } assign $1\counter[1:0] 2'00 sync always sync init update \counter $1\counter[1:0] end - attribute \src "libresoc.v:39181.7-39181.34" - process $proc$libresoc.v:39181$2903 + attribute \src "libresoc.v:39183.7-39183.34" + process $proc$libresoc.v:39183$2903 assign { } { } assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 sync always sync init update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:39185.7-39185.30" - process $proc$libresoc.v:39185$2904 + attribute \src "libresoc.v:39187.7-39187.30" + process $proc$libresoc.v:39187$2904 assign { } { } assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:39189.7-39189.30" - process $proc$libresoc.v:39189$2905 + attribute \src "libresoc.v:39191.7-39191.30" + process $proc$libresoc.v:39191$2905 assign { } { } assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:39193.7-39193.30" - process $proc$libresoc.v:39193$2906 + attribute \src "libresoc.v:39195.7-39195.30" + process $proc$libresoc.v:39195$2906 assign { } { } assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:39197.7-39197.33" - process $proc$libresoc.v:39197$2907 + attribute \src "libresoc.v:39199.7-39199.33" + process $proc$libresoc.v:39199$2907 assign { } { } assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:39201.7-39201.37" - process $proc$libresoc.v:39201$2908 + attribute \src "libresoc.v:39203.7-39203.37" + process $proc$libresoc.v:39203$2908 assign { } { } assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:39205.7-39205.34" - process $proc$libresoc.v:39205$2909 + attribute \src "libresoc.v:39207.7-39207.34" + process $proc$libresoc.v:39207$2909 assign { } { } assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 sync always sync init update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:39209.7-39209.35" - process $proc$libresoc.v:39209$2910 + attribute \src "libresoc.v:39211.7-39211.35" + process $proc$libresoc.v:39211$2910 assign { } { } assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:39213.7-39213.37" - process $proc$libresoc.v:39213$2911 + attribute \src "libresoc.v:39215.7-39215.37" + process $proc$libresoc.v:39215$2911 assign { } { } assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] end - attribute \src "libresoc.v:39217.7-39217.35" - process $proc$libresoc.v:39217$2912 + attribute \src "libresoc.v:39219.7-39219.35" + process $proc$libresoc.v:39219$2912 assign { } { } assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] end - attribute \src "libresoc.v:39221.7-39221.30" - process $proc$libresoc.v:39221$2913 + attribute \src "libresoc.v:39223.7-39223.30" + process $proc$libresoc.v:39223$2913 assign { } { } assign $1\dp_INT_ra_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] end - attribute \src "libresoc.v:39225.7-39225.29" - process $proc$libresoc.v:39225$2914 + attribute \src "libresoc.v:39227.7-39227.29" + process $proc$libresoc.v:39227$2914 assign { } { } assign $1\dp_INT_ra_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] end - attribute \src "libresoc.v:39229.7-39229.30" - process $proc$libresoc.v:39229$2915 + attribute \src "libresoc.v:39231.7-39231.30" + process $proc$libresoc.v:39231$2915 assign { } { } assign $1\dp_INT_ra_div0_5[0:0] 1'0 sync always sync init update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] end - attribute \src "libresoc.v:39233.7-39233.31" - process $proc$libresoc.v:39233$2916 + attribute \src "libresoc.v:39235.7-39235.31" + process $proc$libresoc.v:39235$2916 assign { } { } assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 sync always sync init update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] end - attribute \src "libresoc.v:39237.7-39237.34" - process $proc$libresoc.v:39237$2917 + attribute \src "libresoc.v:39239.7-39239.34" + process $proc$libresoc.v:39239$2917 assign { } { } assign $1\dp_INT_ra_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] end - attribute \src "libresoc.v:39241.7-39241.30" - process $proc$libresoc.v:39241$2918 + attribute \src "libresoc.v:39243.7-39243.30" + process $proc$libresoc.v:39243$2918 assign { } { } assign $1\dp_INT_ra_mul0_6[0:0] 1'0 sync always sync init update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] end - attribute \src "libresoc.v:39245.7-39245.35" - process $proc$libresoc.v:39245$2919 + attribute \src "libresoc.v:39247.7-39247.35" + process $proc$libresoc.v:39247$2919 assign { } { } assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 sync always sync init update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] end - attribute \src "libresoc.v:39249.7-39249.30" - process $proc$libresoc.v:39249$2920 + attribute \src "libresoc.v:39251.7-39251.30" + process $proc$libresoc.v:39251$2920 assign { } { } assign $1\dp_INT_ra_spr0_4[0:0] 1'0 sync always sync init update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] end - attribute \src "libresoc.v:39253.7-39253.31" - process $proc$libresoc.v:39253$2921 + attribute \src "libresoc.v:39255.7-39255.31" + process $proc$libresoc.v:39255$2921 assign { } { } assign $1\dp_INT_ra_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] end - attribute \src "libresoc.v:39257.7-39257.30" - process $proc$libresoc.v:39257$2922 + attribute \src "libresoc.v:39259.7-39259.30" + process $proc$libresoc.v:39259$2922 assign { } { } assign $1\dp_INT_rb_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] end - attribute \src "libresoc.v:39261.7-39261.29" - process $proc$libresoc.v:39261$2923 + attribute \src "libresoc.v:39263.7-39263.29" + process $proc$libresoc.v:39263$2923 assign { } { } assign $1\dp_INT_rb_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] end - attribute \src "libresoc.v:39265.7-39265.30" - process $proc$libresoc.v:39265$2924 + attribute \src "libresoc.v:39267.7-39267.30" + process $proc$libresoc.v:39267$2924 assign { } { } assign $1\dp_INT_rb_div0_4[0:0] 1'0 sync always sync init update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] end - attribute \src "libresoc.v:39269.7-39269.31" - process $proc$libresoc.v:39269$2925 + attribute \src "libresoc.v:39271.7-39271.31" + process $proc$libresoc.v:39271$2925 assign { } { } assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 sync always sync init update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] end - attribute \src "libresoc.v:39273.7-39273.34" - process $proc$libresoc.v:39273$2926 + attribute \src "libresoc.v:39275.7-39275.34" + process $proc$libresoc.v:39275$2926 assign { } { } assign $1\dp_INT_rb_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] end - attribute \src "libresoc.v:39277.7-39277.30" - process $proc$libresoc.v:39277$2927 + attribute \src "libresoc.v:39279.7-39279.30" + process $proc$libresoc.v:39279$2927 assign { } { } assign $1\dp_INT_rb_mul0_5[0:0] 1'0 sync always sync init update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] end - attribute \src "libresoc.v:39281.7-39281.35" - process $proc$libresoc.v:39281$2928 + attribute \src "libresoc.v:39283.7-39283.35" + process $proc$libresoc.v:39283$2928 assign { } { } assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 sync always sync init update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] end - attribute \src "libresoc.v:39285.7-39285.31" - process $proc$libresoc.v:39285$2929 + attribute \src "libresoc.v:39287.7-39287.31" + process $proc$libresoc.v:39287$2929 assign { } { } assign $1\dp_INT_rb_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] end - attribute \src "libresoc.v:39289.7-39289.31" - process $proc$libresoc.v:39289$2930 + attribute \src "libresoc.v:39291.7-39291.31" + process $proc$libresoc.v:39291$2930 assign { } { } assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 sync always sync init update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] end - attribute \src "libresoc.v:39293.7-39293.35" - process $proc$libresoc.v:39293$2931 + attribute \src "libresoc.v:39295.7-39295.35" + process $proc$libresoc.v:39295$2931 assign { } { } assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 sync always sync init update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] end - attribute \src "libresoc.v:39297.7-39297.32" - process $proc$libresoc.v:39297$2932 + attribute \src "libresoc.v:39299.7-39299.32" + process $proc$libresoc.v:39299$2932 assign { } { } assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 sync always sync init update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:39301.7-39301.34" - process $proc$libresoc.v:39301$2933 + attribute \src "libresoc.v:39303.7-39303.34" + process $proc$libresoc.v:39303$2933 assign { } { } assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:39305.7-39305.39" - process $proc$libresoc.v:39305$2934 + attribute \src "libresoc.v:39307.7-39307.39" + process $proc$libresoc.v:39307$2934 assign { } { } assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:39309.7-39309.34" - process $proc$libresoc.v:39309$2935 + attribute \src "libresoc.v:39311.7-39311.34" + process $proc$libresoc.v:39311$2935 assign { } { } assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:39313.7-39313.34" - process $proc$libresoc.v:39313$2936 + attribute \src "libresoc.v:39315.7-39315.34" + process $proc$libresoc.v:39315$2936 assign { } { } assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:39317.7-39317.34" - process $proc$libresoc.v:39317$2937 + attribute \src "libresoc.v:39319.7-39319.34" + process $proc$libresoc.v:39319$2937 assign { } { } assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:39321.7-39321.34" - process $proc$libresoc.v:39321$2938 + attribute \src "libresoc.v:39323.7-39323.34" + process $proc$libresoc.v:39323$2938 assign { } { } assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 sync always sync init update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:39325.7-39325.38" - process $proc$libresoc.v:39325$2939 + attribute \src "libresoc.v:39327.7-39327.38" + process $proc$libresoc.v:39327$2939 assign { } { } assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:39329.7-39329.34" - process $proc$libresoc.v:39329$2940 + attribute \src "libresoc.v:39331.7-39331.34" + process $proc$libresoc.v:39331$2940 assign { } { } assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 sync always sync init update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:39333.7-39333.39" - process $proc$libresoc.v:39333$2941 + attribute \src "libresoc.v:39335.7-39335.39" + process $proc$libresoc.v:39335$2941 assign { } { } assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 sync always sync init update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:39337.7-39337.34" - process $proc$libresoc.v:39337$2942 + attribute \src "libresoc.v:39339.7-39339.34" + process $proc$libresoc.v:39339$2942 assign { } { } assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:41430.7-41430.25" - process $proc$libresoc.v:41430$2943 + attribute \src "libresoc.v:41432.7-41432.25" + process $proc$libresoc.v:41432$2943 assign { } { } assign $1\wr_pick_dly[0:0] 1'0 sync always sync init update \wr_pick_dly $1\wr_pick_dly[0:0] end - attribute \src "libresoc.v:41432.7-41432.32" - process $proc$libresoc.v:41432$2944 + attribute \src "libresoc.v:41434.7-41434.32" + process $proc$libresoc.v:41434$2944 assign { } { } assign $0\wr_pick_dly$1005[0:0]$2945 1'0 sync always sync init update \wr_pick_dly$1005 $0\wr_pick_dly$1005[0:0]$2945 end - attribute \src "libresoc.v:41436.7-41436.32" - process $proc$libresoc.v:41436$2946 + attribute \src "libresoc.v:41438.7-41438.32" + process $proc$libresoc.v:41438$2946 assign { } { } assign $0\wr_pick_dly$1026[0:0]$2947 1'0 sync always sync init update \wr_pick_dly$1026 $0\wr_pick_dly$1026[0:0]$2947 end - attribute \src "libresoc.v:41440.7-41440.32" - process $proc$libresoc.v:41440$2948 + attribute \src "libresoc.v:41442.7-41442.32" + process $proc$libresoc.v:41442$2948 assign { } { } assign $0\wr_pick_dly$1044[0:0]$2949 1'0 sync always sync init update \wr_pick_dly$1044 $0\wr_pick_dly$1044[0:0]$2949 end - attribute \src "libresoc.v:41444.7-41444.32" - process $proc$libresoc.v:41444$2950 + attribute \src "libresoc.v:41446.7-41446.32" + process $proc$libresoc.v:41446$2950 assign { } { } assign $0\wr_pick_dly$1066[0:0]$2951 1'0 sync always sync init update \wr_pick_dly$1066 $0\wr_pick_dly$1066[0:0]$2951 end - attribute \src "libresoc.v:41448.7-41448.32" - process $proc$libresoc.v:41448$2952 + attribute \src "libresoc.v:41450.7-41450.32" + process $proc$libresoc.v:41450$2952 assign { } { } assign $0\wr_pick_dly$1086[0:0]$2953 1'0 sync always sync init update \wr_pick_dly$1086 $0\wr_pick_dly$1086[0:0]$2953 end - attribute \src "libresoc.v:41452.7-41452.32" - process $proc$libresoc.v:41452$2954 + attribute \src "libresoc.v:41454.7-41454.32" + process $proc$libresoc.v:41454$2954 assign { } { } assign $0\wr_pick_dly$1106[0:0]$2955 1'0 sync always sync init update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2955 end - attribute \src "libresoc.v:41456.7-41456.32" - process $proc$libresoc.v:41456$2956 + attribute \src "libresoc.v:41458.7-41458.32" + process $proc$libresoc.v:41458$2956 assign { } { } assign $0\wr_pick_dly$1125[0:0]$2957 1'0 sync always sync init update \wr_pick_dly$1125 $0\wr_pick_dly$1125[0:0]$2957 end - attribute \src "libresoc.v:41460.7-41460.32" - process $proc$libresoc.v:41460$2958 + attribute \src "libresoc.v:41462.7-41462.32" + process $proc$libresoc.v:41462$2958 assign { } { } assign $0\wr_pick_dly$1143[0:0]$2959 1'0 sync always sync init update \wr_pick_dly$1143 $0\wr_pick_dly$1143[0:0]$2959 end - attribute \src "libresoc.v:41464.7-41464.32" - process $proc$libresoc.v:41464$2960 + attribute \src "libresoc.v:41466.7-41466.32" + process $proc$libresoc.v:41466$2960 assign { } { } assign $0\wr_pick_dly$1217[0:0]$2961 1'0 sync always sync init update \wr_pick_dly$1217 $0\wr_pick_dly$1217[0:0]$2961 end - attribute \src "libresoc.v:41468.7-41468.32" - process $proc$libresoc.v:41468$2962 + attribute \src "libresoc.v:41470.7-41470.32" + process $proc$libresoc.v:41470$2962 assign { } { } assign $0\wr_pick_dly$1245[0:0]$2963 1'0 sync always sync init update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2963 end - attribute \src "libresoc.v:41472.7-41472.32" - process $proc$libresoc.v:41472$2964 + attribute \src "libresoc.v:41474.7-41474.32" + process $proc$libresoc.v:41474$2964 assign { } { } assign $0\wr_pick_dly$1265[0:0]$2965 1'0 sync always sync init update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2965 end - attribute \src "libresoc.v:41476.7-41476.32" - process $proc$libresoc.v:41476$2966 + attribute \src "libresoc.v:41478.7-41478.32" + process $proc$libresoc.v:41478$2966 assign { } { } assign $0\wr_pick_dly$1285[0:0]$2967 1'0 sync always sync init update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2967 end - attribute \src "libresoc.v:41480.7-41480.32" - process $proc$libresoc.v:41480$2968 + attribute \src "libresoc.v:41482.7-41482.32" + process $proc$libresoc.v:41482$2968 assign { } { } assign $0\wr_pick_dly$1305[0:0]$2969 1'0 sync always sync init update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2969 end - attribute \src "libresoc.v:41484.7-41484.32" - process $proc$libresoc.v:41484$2970 + attribute \src "libresoc.v:41486.7-41486.32" + process $proc$libresoc.v:41486$2970 assign { } { } assign $0\wr_pick_dly$1325[0:0]$2971 1'0 sync always sync init update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2971 end - attribute \src "libresoc.v:41488.7-41488.32" - process $proc$libresoc.v:41488$2972 + attribute \src "libresoc.v:41490.7-41490.32" + process $proc$libresoc.v:41490$2972 assign { } { } assign $0\wr_pick_dly$1345[0:0]$2973 1'0 sync always sync init update \wr_pick_dly$1345 $0\wr_pick_dly$1345[0:0]$2973 end - attribute \src "libresoc.v:41492.7-41492.32" - process $proc$libresoc.v:41492$2974 + attribute \src "libresoc.v:41494.7-41494.32" + process $proc$libresoc.v:41494$2974 assign { } { } assign $0\wr_pick_dly$1392[0:0]$2975 1'0 sync always sync init update \wr_pick_dly$1392 $0\wr_pick_dly$1392[0:0]$2975 end - attribute \src "libresoc.v:41496.7-41496.32" - process $proc$libresoc.v:41496$2976 + attribute \src "libresoc.v:41498.7-41498.32" + process $proc$libresoc.v:41498$2976 assign { } { } assign $0\wr_pick_dly$1408[0:0]$2977 1'0 sync always sync init update \wr_pick_dly$1408 $0\wr_pick_dly$1408[0:0]$2977 end - attribute \src "libresoc.v:41500.7-41500.32" - process $proc$libresoc.v:41500$2978 + attribute \src "libresoc.v:41502.7-41502.32" + process $proc$libresoc.v:41502$2978 assign { } { } assign $0\wr_pick_dly$1424[0:0]$2979 1'0 sync always sync init update \wr_pick_dly$1424 $0\wr_pick_dly$1424[0:0]$2979 end - attribute \src "libresoc.v:41504.7-41504.32" - process $proc$libresoc.v:41504$2980 + attribute \src "libresoc.v:41506.7-41506.32" + process $proc$libresoc.v:41506$2980 assign { } { } assign $0\wr_pick_dly$1458[0:0]$2981 1'0 sync always sync init update \wr_pick_dly$1458 $0\wr_pick_dly$1458[0:0]$2981 end - attribute \src "libresoc.v:41508.7-41508.32" - process $proc$libresoc.v:41508$2982 + attribute \src "libresoc.v:41510.7-41510.32" + process $proc$libresoc.v:41510$2982 assign { } { } assign $0\wr_pick_dly$1474[0:0]$2983 1'0 sync always sync init update \wr_pick_dly$1474 $0\wr_pick_dly$1474[0:0]$2983 end - attribute \src "libresoc.v:41512.7-41512.32" - process $proc$libresoc.v:41512$2984 + attribute \src "libresoc.v:41514.7-41514.32" + process $proc$libresoc.v:41514$2984 assign { } { } assign $0\wr_pick_dly$1490[0:0]$2985 1'0 sync always sync init update \wr_pick_dly$1490 $0\wr_pick_dly$1490[0:0]$2985 end - attribute \src "libresoc.v:41516.7-41516.32" - process $proc$libresoc.v:41516$2986 + attribute \src "libresoc.v:41518.7-41518.32" + process $proc$libresoc.v:41518$2986 assign { } { } assign $0\wr_pick_dly$1506[0:0]$2987 1'0 sync always sync init update \wr_pick_dly$1506 $0\wr_pick_dly$1506[0:0]$2987 end - attribute \src "libresoc.v:41520.7-41520.32" - process $proc$libresoc.v:41520$2988 + attribute \src "libresoc.v:41522.7-41522.32" + process $proc$libresoc.v:41522$2988 assign { } { } assign $0\wr_pick_dly$1542[0:0]$2989 1'0 sync always sync init update \wr_pick_dly$1542 $0\wr_pick_dly$1542[0:0]$2989 end - attribute \src "libresoc.v:41524.7-41524.32" - process $proc$libresoc.v:41524$2990 + attribute \src "libresoc.v:41526.7-41526.32" + process $proc$libresoc.v:41526$2990 assign { } { } assign $0\wr_pick_dly$1558[0:0]$2991 1'0 sync always sync init update \wr_pick_dly$1558 $0\wr_pick_dly$1558[0:0]$2991 end - attribute \src "libresoc.v:41528.7-41528.32" - process $proc$libresoc.v:41528$2992 + attribute \src "libresoc.v:41530.7-41530.32" + process $proc$libresoc.v:41530$2992 assign { } { } assign $0\wr_pick_dly$1574[0:0]$2993 1'0 sync always sync init update \wr_pick_dly$1574 $0\wr_pick_dly$1574[0:0]$2993 end - attribute \src "libresoc.v:41532.7-41532.32" - process $proc$libresoc.v:41532$2994 + attribute \src "libresoc.v:41534.7-41534.32" + process $proc$libresoc.v:41534$2994 assign { } { } assign $0\wr_pick_dly$1590[0:0]$2995 1'0 sync always sync init update \wr_pick_dly$1590 $0\wr_pick_dly$1590[0:0]$2995 end - attribute \src "libresoc.v:41536.7-41536.32" - process $proc$libresoc.v:41536$2996 + attribute \src "libresoc.v:41538.7-41538.32" + process $proc$libresoc.v:41538$2996 assign { } { } assign $0\wr_pick_dly$1632[0:0]$2997 1'0 sync always sync init update \wr_pick_dly$1632 $0\wr_pick_dly$1632[0:0]$2997 end - attribute \src "libresoc.v:41540.7-41540.32" - process $proc$libresoc.v:41540$2998 + attribute \src "libresoc.v:41542.7-41542.32" + process $proc$libresoc.v:41542$2998 assign { } { } assign $0\wr_pick_dly$1651[0:0]$2999 1'0 sync always sync init update \wr_pick_dly$1651 $0\wr_pick_dly$1651[0:0]$2999 end - attribute \src "libresoc.v:41544.7-41544.32" - process $proc$libresoc.v:41544$3000 + attribute \src "libresoc.v:41546.7-41546.32" + process $proc$libresoc.v:41546$3000 assign { } { } assign $0\wr_pick_dly$1667[0:0]$3001 1'0 sync always sync init update \wr_pick_dly$1667 $0\wr_pick_dly$1667[0:0]$3001 end - attribute \src "libresoc.v:41548.7-41548.32" - process $proc$libresoc.v:41548$3002 + attribute \src "libresoc.v:41550.7-41550.32" + process $proc$libresoc.v:41550$3002 assign { } { } assign $0\wr_pick_dly$1683[0:0]$3003 1'0 sync always sync init update \wr_pick_dly$1683 $0\wr_pick_dly$1683[0:0]$3003 end - attribute \src "libresoc.v:41552.7-41552.32" - process $proc$libresoc.v:41552$3004 + attribute \src "libresoc.v:41554.7-41554.32" + process $proc$libresoc.v:41554$3004 assign { } { } assign $0\wr_pick_dly$1699[0:0]$3005 1'0 sync always sync init update \wr_pick_dly$1699 $0\wr_pick_dly$1699[0:0]$3005 end - attribute \src "libresoc.v:41556.7-41556.32" - process $proc$libresoc.v:41556$3006 + attribute \src "libresoc.v:41558.7-41558.32" + process $proc$libresoc.v:41558$3006 assign { } { } assign $0\wr_pick_dly$1743[0:0]$3007 1'0 sync always sync init update \wr_pick_dly$1743 $0\wr_pick_dly$1743[0:0]$3007 end - attribute \src "libresoc.v:41560.7-41560.32" - process $proc$libresoc.v:41560$3008 + attribute \src "libresoc.v:41562.7-41562.32" + process $proc$libresoc.v:41562$3008 assign { } { } assign $0\wr_pick_dly$1759[0:0]$3009 1'0 sync always sync init update \wr_pick_dly$1759 $0\wr_pick_dly$1759[0:0]$3009 end - attribute \src "libresoc.v:41564.7-41564.32" - process $proc$libresoc.v:41564$3010 + attribute \src "libresoc.v:41566.7-41566.32" + process $proc$libresoc.v:41566$3010 assign { } { } assign $0\wr_pick_dly$1783[0:0]$3011 1'0 sync always sync init update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$3011 end - attribute \src "libresoc.v:41568.7-41568.32" - process $proc$libresoc.v:41568$3012 + attribute \src "libresoc.v:41570.7-41570.32" + process $proc$libresoc.v:41570$3012 assign { } { } assign $0\wr_pick_dly$1803[0:0]$3013 1'0 sync always sync init update \wr_pick_dly$1803 $0\wr_pick_dly$1803[0:0]$3013 end - attribute \src "libresoc.v:41572.7-41572.31" - process $proc$libresoc.v:41572$3014 + attribute \src "libresoc.v:41574.7-41574.31" + process $proc$libresoc.v:41574$3014 assign { } { } assign $0\wr_pick_dly$986[0:0]$3015 1'0 sync always sync init update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$3015 end - attribute \src "libresoc.v:42534.3-42535.51" - process $proc$libresoc.v:42534$2238 + attribute \src "libresoc.v:42536.3-42537.51" + process $proc$libresoc.v:42536$2238 assign { } { } assign $0\wr_pick_dly$1803[0:0]$2239 \wr_pick_dly$1803$next sync posedge \coresync_clk update \wr_pick_dly$1803 $0\wr_pick_dly$1803[0:0]$2239 end - attribute \src "libresoc.v:42536.3-42537.51" - process $proc$libresoc.v:42536$2240 + attribute \src "libresoc.v:42538.3-42539.51" + process $proc$libresoc.v:42538$2240 assign { } { } assign $0\wr_pick_dly$1783[0:0]$2241 \wr_pick_dly$1783$next sync posedge \coresync_clk update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$2241 end - attribute \src "libresoc.v:42538.3-42539.51" - process $proc$libresoc.v:42538$2242 + attribute \src "libresoc.v:42540.3-42541.51" + process $proc$libresoc.v:42540$2242 assign { } { } assign $0\wr_pick_dly$1759[0:0]$2243 \wr_pick_dly$1759$next sync posedge \coresync_clk update \wr_pick_dly$1759 $0\wr_pick_dly$1759[0:0]$2243 end - attribute \src "libresoc.v:42540.3-42541.51" - process $proc$libresoc.v:42540$2244 + attribute \src "libresoc.v:42542.3-42543.51" + process $proc$libresoc.v:42542$2244 assign { } { } assign $0\wr_pick_dly$1743[0:0]$2245 \wr_pick_dly$1743$next sync posedge \coresync_clk update \wr_pick_dly$1743 $0\wr_pick_dly$1743[0:0]$2245 end - attribute \src "libresoc.v:42542.3-42543.51" - process $proc$libresoc.v:42542$2246 + attribute \src "libresoc.v:42544.3-42545.51" + process $proc$libresoc.v:42544$2246 assign { } { } assign $0\wr_pick_dly$1699[0:0]$2247 \wr_pick_dly$1699$next sync posedge \coresync_clk update \wr_pick_dly$1699 $0\wr_pick_dly$1699[0:0]$2247 end - attribute \src "libresoc.v:42544.3-42545.51" - process $proc$libresoc.v:42544$2248 + attribute \src "libresoc.v:42546.3-42547.51" + process $proc$libresoc.v:42546$2248 assign { } { } assign $0\wr_pick_dly$1683[0:0]$2249 \wr_pick_dly$1683$next sync posedge \coresync_clk update \wr_pick_dly$1683 $0\wr_pick_dly$1683[0:0]$2249 end - attribute \src "libresoc.v:42546.3-42547.51" - process $proc$libresoc.v:42546$2250 + attribute \src "libresoc.v:42548.3-42549.51" + process $proc$libresoc.v:42548$2250 assign { } { } assign $0\wr_pick_dly$1667[0:0]$2251 \wr_pick_dly$1667$next sync posedge \coresync_clk update \wr_pick_dly$1667 $0\wr_pick_dly$1667[0:0]$2251 end - attribute \src "libresoc.v:42548.3-42549.51" - process $proc$libresoc.v:42548$2252 + attribute \src "libresoc.v:42550.3-42551.51" + process $proc$libresoc.v:42550$2252 assign { } { } assign $0\wr_pick_dly$1651[0:0]$2253 \wr_pick_dly$1651$next sync posedge \coresync_clk update \wr_pick_dly$1651 $0\wr_pick_dly$1651[0:0]$2253 end - attribute \src "libresoc.v:42550.3-42551.51" - process $proc$libresoc.v:42550$2254 + attribute \src "libresoc.v:42552.3-42553.51" + process $proc$libresoc.v:42552$2254 assign { } { } assign $0\wr_pick_dly$1632[0:0]$2255 \wr_pick_dly$1632$next sync posedge \coresync_clk update \wr_pick_dly$1632 $0\wr_pick_dly$1632[0:0]$2255 end - attribute \src "libresoc.v:42552.3-42553.51" - process $proc$libresoc.v:42552$2256 + attribute \src "libresoc.v:42554.3-42555.51" + process $proc$libresoc.v:42554$2256 assign { } { } assign $0\wr_pick_dly$1590[0:0]$2257 \wr_pick_dly$1590$next sync posedge \coresync_clk update \wr_pick_dly$1590 $0\wr_pick_dly$1590[0:0]$2257 end - attribute \src "libresoc.v:42554.3-42555.51" - process $proc$libresoc.v:42554$2258 + attribute \src "libresoc.v:42556.3-42557.51" + process $proc$libresoc.v:42556$2258 assign { } { } assign $0\wr_pick_dly$1574[0:0]$2259 \wr_pick_dly$1574$next sync posedge \coresync_clk update \wr_pick_dly$1574 $0\wr_pick_dly$1574[0:0]$2259 end - attribute \src "libresoc.v:42556.3-42557.51" - process $proc$libresoc.v:42556$2260 + attribute \src "libresoc.v:42558.3-42559.51" + process $proc$libresoc.v:42558$2260 assign { } { } assign $0\wr_pick_dly$1558[0:0]$2261 \wr_pick_dly$1558$next sync posedge \coresync_clk update \wr_pick_dly$1558 $0\wr_pick_dly$1558[0:0]$2261 end - attribute \src "libresoc.v:42558.3-42559.51" - process $proc$libresoc.v:42558$2262 + attribute \src "libresoc.v:42560.3-42561.51" + process $proc$libresoc.v:42560$2262 assign { } { } assign $0\wr_pick_dly$1542[0:0]$2263 \wr_pick_dly$1542$next sync posedge \coresync_clk update \wr_pick_dly$1542 $0\wr_pick_dly$1542[0:0]$2263 end - attribute \src "libresoc.v:42560.3-42561.51" - process $proc$libresoc.v:42560$2264 + attribute \src "libresoc.v:42562.3-42563.51" + process $proc$libresoc.v:42562$2264 assign { } { } assign $0\wr_pick_dly$1506[0:0]$2265 \wr_pick_dly$1506$next sync posedge \coresync_clk update \wr_pick_dly$1506 $0\wr_pick_dly$1506[0:0]$2265 end - attribute \src "libresoc.v:42562.3-42563.51" - process $proc$libresoc.v:42562$2266 + attribute \src "libresoc.v:42564.3-42565.51" + process $proc$libresoc.v:42564$2266 assign { } { } assign $0\wr_pick_dly$1490[0:0]$2267 \wr_pick_dly$1490$next sync posedge \coresync_clk update \wr_pick_dly$1490 $0\wr_pick_dly$1490[0:0]$2267 end - attribute \src "libresoc.v:42564.3-42565.51" - process $proc$libresoc.v:42564$2268 + attribute \src "libresoc.v:42566.3-42567.51" + process $proc$libresoc.v:42566$2268 assign { } { } assign $0\wr_pick_dly$1474[0:0]$2269 \wr_pick_dly$1474$next sync posedge \coresync_clk update \wr_pick_dly$1474 $0\wr_pick_dly$1474[0:0]$2269 end - attribute \src "libresoc.v:42566.3-42567.51" - process $proc$libresoc.v:42566$2270 + attribute \src "libresoc.v:42568.3-42569.51" + process $proc$libresoc.v:42568$2270 assign { } { } assign $0\wr_pick_dly$1458[0:0]$2271 \wr_pick_dly$1458$next sync posedge \coresync_clk update \wr_pick_dly$1458 $0\wr_pick_dly$1458[0:0]$2271 end - attribute \src "libresoc.v:42568.3-42569.51" - process $proc$libresoc.v:42568$2272 + attribute \src "libresoc.v:42570.3-42571.51" + process $proc$libresoc.v:42570$2272 assign { } { } assign $0\wr_pick_dly$1424[0:0]$2273 \wr_pick_dly$1424$next sync posedge \coresync_clk update \wr_pick_dly$1424 $0\wr_pick_dly$1424[0:0]$2273 end - attribute \src "libresoc.v:42570.3-42571.51" - process $proc$libresoc.v:42570$2274 + attribute \src "libresoc.v:42572.3-42573.51" + process $proc$libresoc.v:42572$2274 assign { } { } assign $0\wr_pick_dly$1408[0:0]$2275 \wr_pick_dly$1408$next sync posedge \coresync_clk update \wr_pick_dly$1408 $0\wr_pick_dly$1408[0:0]$2275 end - attribute \src "libresoc.v:42572.3-42573.51" - process $proc$libresoc.v:42572$2276 + attribute \src "libresoc.v:42574.3-42575.51" + process $proc$libresoc.v:42574$2276 assign { } { } assign $0\wr_pick_dly$1392[0:0]$2277 \wr_pick_dly$1392$next sync posedge \coresync_clk update \wr_pick_dly$1392 $0\wr_pick_dly$1392[0:0]$2277 end - attribute \src "libresoc.v:42574.3-42575.51" - process $proc$libresoc.v:42574$2278 + attribute \src "libresoc.v:42576.3-42577.51" + process $proc$libresoc.v:42576$2278 assign { } { } assign $0\wr_pick_dly$1345[0:0]$2279 \wr_pick_dly$1345$next sync posedge \coresync_clk update \wr_pick_dly$1345 $0\wr_pick_dly$1345[0:0]$2279 end - attribute \src "libresoc.v:42576.3-42577.51" - process $proc$libresoc.v:42576$2280 + attribute \src "libresoc.v:42578.3-42579.51" + process $proc$libresoc.v:42578$2280 assign { } { } assign $0\wr_pick_dly$1325[0:0]$2281 \wr_pick_dly$1325$next sync posedge \coresync_clk update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2281 end - attribute \src "libresoc.v:42578.3-42579.51" - process $proc$libresoc.v:42578$2282 + attribute \src "libresoc.v:42580.3-42581.51" + process $proc$libresoc.v:42580$2282 assign { } { } assign $0\wr_pick_dly$1305[0:0]$2283 \wr_pick_dly$1305$next sync posedge \coresync_clk update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2283 end - attribute \src "libresoc.v:42580.3-42581.51" - process $proc$libresoc.v:42580$2284 + attribute \src "libresoc.v:42582.3-42583.51" + process $proc$libresoc.v:42582$2284 assign { } { } assign $0\wr_pick_dly$1285[0:0]$2285 \wr_pick_dly$1285$next sync posedge \coresync_clk update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2285 end - attribute \src "libresoc.v:42582.3-42583.51" - process $proc$libresoc.v:42582$2286 + attribute \src "libresoc.v:42584.3-42585.51" + process $proc$libresoc.v:42584$2286 assign { } { } assign $0\wr_pick_dly$1265[0:0]$2287 \wr_pick_dly$1265$next sync posedge \coresync_clk update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2287 end - attribute \src "libresoc.v:42584.3-42585.51" - process $proc$libresoc.v:42584$2288 + attribute \src "libresoc.v:42586.3-42587.51" + process $proc$libresoc.v:42586$2288 assign { } { } assign $0\wr_pick_dly$1245[0:0]$2289 \wr_pick_dly$1245$next sync posedge \coresync_clk update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2289 end - attribute \src "libresoc.v:42586.3-42587.51" - process $proc$libresoc.v:42586$2290 + attribute \src "libresoc.v:42588.3-42589.51" + process $proc$libresoc.v:42588$2290 assign { } { } assign $0\wr_pick_dly$1217[0:0]$2291 \wr_pick_dly$1217$next sync posedge \coresync_clk update \wr_pick_dly$1217 $0\wr_pick_dly$1217[0:0]$2291 end - attribute \src "libresoc.v:42588.3-42589.51" - process $proc$libresoc.v:42588$2292 + attribute \src "libresoc.v:42590.3-42591.51" + process $proc$libresoc.v:42590$2292 assign { } { } assign $0\wr_pick_dly$1143[0:0]$2293 \wr_pick_dly$1143$next sync posedge \coresync_clk update \wr_pick_dly$1143 $0\wr_pick_dly$1143[0:0]$2293 end - attribute \src "libresoc.v:42590.3-42591.51" - process $proc$libresoc.v:42590$2294 + attribute \src "libresoc.v:42592.3-42593.51" + process $proc$libresoc.v:42592$2294 assign { } { } assign $0\wr_pick_dly$1125[0:0]$2295 \wr_pick_dly$1125$next sync posedge \coresync_clk update \wr_pick_dly$1125 $0\wr_pick_dly$1125[0:0]$2295 end - attribute \src "libresoc.v:42592.3-42593.51" - process $proc$libresoc.v:42592$2296 + attribute \src "libresoc.v:42594.3-42595.51" + process $proc$libresoc.v:42594$2296 assign { } { } assign $0\wr_pick_dly$1106[0:0]$2297 \wr_pick_dly$1106$next sync posedge \coresync_clk update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2297 end - attribute \src "libresoc.v:42594.3-42595.51" - process $proc$libresoc.v:42594$2298 + attribute \src "libresoc.v:42596.3-42597.51" + process $proc$libresoc.v:42596$2298 assign { } { } assign $0\wr_pick_dly$1086[0:0]$2299 \wr_pick_dly$1086$next sync posedge \coresync_clk update \wr_pick_dly$1086 $0\wr_pick_dly$1086[0:0]$2299 end - attribute \src "libresoc.v:42596.3-42597.51" - process $proc$libresoc.v:42596$2300 + attribute \src "libresoc.v:42598.3-42599.51" + process $proc$libresoc.v:42598$2300 assign { } { } assign $0\wr_pick_dly$1066[0:0]$2301 \wr_pick_dly$1066$next sync posedge \coresync_clk update \wr_pick_dly$1066 $0\wr_pick_dly$1066[0:0]$2301 end - attribute \src "libresoc.v:42598.3-42599.51" - process $proc$libresoc.v:42598$2302 + attribute \src "libresoc.v:42600.3-42601.51" + process $proc$libresoc.v:42600$2302 assign { } { } assign $0\wr_pick_dly$1044[0:0]$2303 \wr_pick_dly$1044$next sync posedge \coresync_clk update \wr_pick_dly$1044 $0\wr_pick_dly$1044[0:0]$2303 end - attribute \src "libresoc.v:42600.3-42601.51" - process $proc$libresoc.v:42600$2304 + attribute \src "libresoc.v:42602.3-42603.51" + process $proc$libresoc.v:42602$2304 assign { } { } assign $0\wr_pick_dly$1026[0:0]$2305 \wr_pick_dly$1026$next sync posedge \coresync_clk update \wr_pick_dly$1026 $0\wr_pick_dly$1026[0:0]$2305 end - attribute \src "libresoc.v:42602.3-42603.51" - process $proc$libresoc.v:42602$2306 + attribute \src "libresoc.v:42604.3-42605.51" + process $proc$libresoc.v:42604$2306 assign { } { } assign $0\wr_pick_dly$1005[0:0]$2307 \wr_pick_dly$1005$next sync posedge \coresync_clk update \wr_pick_dly$1005 $0\wr_pick_dly$1005[0:0]$2307 end - attribute \src "libresoc.v:42604.3-42605.49" - process $proc$libresoc.v:42604$2308 + attribute \src "libresoc.v:42606.3-42607.49" + process $proc$libresoc.v:42606$2308 assign { } { } assign $0\wr_pick_dly$986[0:0]$2309 \wr_pick_dly$986$next sync posedge \coresync_clk update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$2309 end - attribute \src "libresoc.v:42606.3-42607.39" - process $proc$libresoc.v:42606$2310 + attribute \src "libresoc.v:42608.3-42609.39" + process $proc$libresoc.v:42608$2310 assign { } { } assign $0\wr_pick_dly[0:0] \wr_pick_dly$next sync posedge \coresync_clk update \wr_pick_dly $0\wr_pick_dly[0:0] end - attribute \src "libresoc.v:42608.3-42609.53" - process $proc$libresoc.v:42608$2311 + attribute \src "libresoc.v:42610.3-42611.53" + process $proc$libresoc.v:42610$2311 assign { } { } assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next sync posedge \coresync_clk update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:42610.3-42611.59" - process $proc$libresoc.v:42610$2312 + attribute \src "libresoc.v:42612.3-42613.59" + process $proc$libresoc.v:42612$2312 assign { } { } assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] end - attribute \src "libresoc.v:42612.3-42613.63" - process $proc$libresoc.v:42612$2313 + attribute \src "libresoc.v:42614.3-42615.63" + process $proc$libresoc.v:42614$2313 assign { } { } assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] end - attribute \src "libresoc.v:42614.3-42615.57" - process $proc$libresoc.v:42614$2314 + attribute \src "libresoc.v:42616.3-42617.57" + process $proc$libresoc.v:42616$2314 assign { } { } assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next sync posedge \coresync_clk update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:42616.3-42617.59" - process $proc$libresoc.v:42616$2315 + attribute \src "libresoc.v:42618.3-42619.59" + process $proc$libresoc.v:42618$2315 assign { } { } assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:42618.3-42619.63" - process $proc$libresoc.v:42618$2316 + attribute \src "libresoc.v:42620.3-42621.63" + process $proc$libresoc.v:42620$2316 assign { } { } assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:42620.3-42621.49" - process $proc$libresoc.v:42620$2317 + attribute \src "libresoc.v:42622.3-42623.49" + process $proc$libresoc.v:42622$2317 assign { } { } assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:42622.3-42623.49" - process $proc$libresoc.v:42622$2318 + attribute \src "libresoc.v:42624.3-42625.49" + process $proc$libresoc.v:42624$2318 assign { } { } assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:42624.3-42625.57" - process $proc$libresoc.v:42624$2319 + attribute \src "libresoc.v:42626.3-42627.57" + process $proc$libresoc.v:42626$2319 assign { } { } assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next sync posedge \coresync_clk update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:42626.3-42627.49" - process $proc$libresoc.v:42626$2320 + attribute \src "libresoc.v:42628.3-42629.49" + process $proc$libresoc.v:42628$2320 assign { } { } assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:42628.3-42629.55" - process $proc$libresoc.v:42628$2321 + attribute \src "libresoc.v:42630.3-42631.55" + process $proc$libresoc.v:42630$2321 assign { } { } assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next sync posedge \coresync_clk update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:42630.3-42631.57" - process $proc$libresoc.v:42630$2322 + attribute \src "libresoc.v:42632.3-42633.57" + process $proc$libresoc.v:42632$2322 assign { } { } assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next sync posedge \coresync_clk update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:42632.3-42633.67" - process $proc$libresoc.v:42632$2323 + attribute \src "libresoc.v:42634.3-42635.67" + process $proc$libresoc.v:42634$2323 assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next sync posedge \coresync_clk update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:42634.3-42635.57" - process $proc$libresoc.v:42634$2324 + attribute \src "libresoc.v:42636.3-42637.57" + process $proc$libresoc.v:42636$2324 assign { } { } assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next sync posedge \coresync_clk update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:42636.3-42637.57" - process $proc$libresoc.v:42636$2325 + attribute \src "libresoc.v:42638.3-42639.57" + process $proc$libresoc.v:42638$2325 assign { } { } assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:42638.3-42639.67" - process $proc$libresoc.v:42638$2326 + attribute \src "libresoc.v:42640.3-42641.67" + process $proc$libresoc.v:42640$2326 assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next sync posedge \coresync_clk update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:42640.3-42641.57" - process $proc$libresoc.v:42640$2327 + attribute \src "libresoc.v:42642.3-42643.57" + process $proc$libresoc.v:42642$2327 assign { } { } assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next sync posedge \coresync_clk update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:42642.3-42643.57" - process $proc$libresoc.v:42642$2328 + attribute \src "libresoc.v:42644.3-42645.57" + process $proc$libresoc.v:42644$2328 assign { } { } assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next sync posedge \coresync_clk update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:42644.3-42645.57" - process $proc$libresoc.v:42644$2329 + attribute \src "libresoc.v:42646.3-42647.57" + process $proc$libresoc.v:42646$2329 assign { } { } assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next sync posedge \coresync_clk update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:42646.3-42647.65" - process $proc$libresoc.v:42646$2330 + attribute \src "libresoc.v:42648.3-42649.65" + process $proc$libresoc.v:42648$2330 assign { } { } assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next sync posedge \coresync_clk update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:42648.3-42649.57" - process $proc$libresoc.v:42648$2331 + attribute \src "libresoc.v:42650.3-42651.57" + process $proc$libresoc.v:42650$2331 assign { } { } assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:42650.3-42651.51" - process $proc$libresoc.v:42650$2332 + attribute \src "libresoc.v:42652.3-42653.51" + process $proc$libresoc.v:42652$2332 assign { } { } assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next sync posedge \coresync_clk update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] end - attribute \src "libresoc.v:42652.3-42653.59" - process $proc$libresoc.v:42652$2333 + attribute \src "libresoc.v:42654.3-42655.59" + process $proc$libresoc.v:42654$2333 assign { } { } assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next sync posedge \coresync_clk update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] end - attribute \src "libresoc.v:42654.3-42655.51" - process $proc$libresoc.v:42654$2334 + attribute \src "libresoc.v:42656.3-42657.51" + process $proc$libresoc.v:42656$2334 assign { } { } assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next sync posedge \coresync_clk update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] end - attribute \src "libresoc.v:42656.3-42657.59" - process $proc$libresoc.v:42656$2335 + attribute \src "libresoc.v:42658.3-42659.59" + process $proc$libresoc.v:42658$2335 assign { } { } assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next sync posedge \coresync_clk update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] end - attribute \src "libresoc.v:42658.3-42659.49" - process $proc$libresoc.v:42658$2336 + attribute \src "libresoc.v:42660.3-42661.49" + process $proc$libresoc.v:42660$2336 assign { } { } assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next sync posedge \coresync_clk update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] end - attribute \src "libresoc.v:42660.3-42661.49" - process $proc$libresoc.v:42660$2337 + attribute \src "libresoc.v:42662.3-42663.49" + process $proc$libresoc.v:42662$2337 assign { } { } assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next sync posedge \coresync_clk update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] end - attribute \src "libresoc.v:42662.3-42663.57" - process $proc$libresoc.v:42662$2338 + attribute \src "libresoc.v:42664.3-42665.57" + process $proc$libresoc.v:42664$2338 assign { } { } assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next sync posedge \coresync_clk update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] end - attribute \src "libresoc.v:42664.3-42665.51" - process $proc$libresoc.v:42664$2339 + attribute \src "libresoc.v:42666.3-42667.51" + process $proc$libresoc.v:42666$2339 assign { } { } assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next sync posedge \coresync_clk update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] end - attribute \src "libresoc.v:42666.3-42667.47" - process $proc$libresoc.v:42666$2340 + attribute \src "libresoc.v:42668.3-42669.47" + process $proc$libresoc.v:42668$2340 assign { } { } assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next sync posedge \coresync_clk update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] end - attribute \src "libresoc.v:42668.3-42669.49" - process $proc$libresoc.v:42668$2341 + attribute \src "libresoc.v:42670.3-42671.49" + process $proc$libresoc.v:42670$2341 assign { } { } assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next sync posedge \coresync_clk update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] end - attribute \src "libresoc.v:42670.3-42671.51" - process $proc$libresoc.v:42670$2342 + attribute \src "libresoc.v:42672.3-42673.51" + process $proc$libresoc.v:42672$2342 assign { } { } assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next sync posedge \coresync_clk update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] end - attribute \src "libresoc.v:42672.3-42673.59" - process $proc$libresoc.v:42672$2343 + attribute \src "libresoc.v:42674.3-42675.59" + process $proc$libresoc.v:42674$2343 assign { } { } assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next sync posedge \coresync_clk update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] end - attribute \src "libresoc.v:42674.3-42675.49" - process $proc$libresoc.v:42674$2344 + attribute \src "libresoc.v:42676.3-42677.49" + process $proc$libresoc.v:42676$2344 assign { } { } assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next sync posedge \coresync_clk update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] end - attribute \src "libresoc.v:42676.3-42677.49" - process $proc$libresoc.v:42676$2345 + attribute \src "libresoc.v:42678.3-42679.49" + process $proc$libresoc.v:42678$2345 assign { } { } assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next sync posedge \coresync_clk update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] end - attribute \src "libresoc.v:42678.3-42679.49" - process $proc$libresoc.v:42678$2346 + attribute \src "libresoc.v:42680.3-42681.49" + process $proc$libresoc.v:42680$2346 assign { } { } assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next sync posedge \coresync_clk update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] end - attribute \src "libresoc.v:42680.3-42681.57" - process $proc$libresoc.v:42680$2347 + attribute \src "libresoc.v:42682.3-42683.57" + process $proc$libresoc.v:42682$2347 assign { } { } assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next sync posedge \coresync_clk update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] end - attribute \src "libresoc.v:42682.3-42683.51" - process $proc$libresoc.v:42682$2348 + attribute \src "libresoc.v:42684.3-42685.51" + process $proc$libresoc.v:42684$2348 assign { } { } assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next sync posedge \coresync_clk update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] end - attribute \src "libresoc.v:42684.3-42685.47" - process $proc$libresoc.v:42684$2349 + attribute \src "libresoc.v:42686.3-42687.47" + process $proc$libresoc.v:42686$2349 assign { } { } assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next sync posedge \coresync_clk update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] end - attribute \src "libresoc.v:42686.3-42687.49" - process $proc$libresoc.v:42686$2350 + attribute \src "libresoc.v:42688.3-42689.49" + process $proc$libresoc.v:42688$2350 assign { } { } assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next sync posedge \coresync_clk update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] end - attribute \src "libresoc.v:42688.3-42689.49" - process $proc$libresoc.v:42688$2351 + attribute \src "libresoc.v:42690.3-42691.49" + process $proc$libresoc.v:42690$2351 assign { } { } assign $0\core_terminate_o[0:0] \core_terminate_o$next sync posedge \coresync_clk update \core_terminate_o $0\core_terminate_o[0:0] end - attribute \src "libresoc.v:42690.3-42691.31" - process $proc$libresoc.v:42690$2352 + attribute \src "libresoc.v:42692.3-42693.31" + process $proc$libresoc.v:42692$2352 assign { } { } assign $0\counter[1:0] \counter$next sync posedge \coresync_clk update \counter $0\counter[1:0] end - attribute \src "libresoc.v:43425.3-43453.6" - process $proc$libresoc.v:43425$2353 + attribute \src "libresoc.v:43427.3-43455.6" + process $proc$libresoc.v:43427$2353 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43426.5-43426.29" + attribute \src "libresoc.v:43428.5-43428.29" switch \initial - attribute \src "libresoc.v:43426.9-43426.17" + attribute \src "libresoc.v:43428.9-43428.17" case 1'1 case end @@ -75477,14 +75479,14 @@ module \core sync always update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] end - attribute \src "libresoc.v:43454.3-43482.6" - process $proc$libresoc.v:43454$2354 + attribute \src "libresoc.v:43456.3-43484.6" + process $proc$libresoc.v:43456$2354 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:43455.5-43455.29" + attribute \src "libresoc.v:43457.5-43457.29" switch \initial - attribute \src "libresoc.v:43455.9-43455.17" + attribute \src "libresoc.v:43457.9-43457.17" case 1'1 case end @@ -75522,14 +75524,14 @@ module \core sync always update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] end - attribute \src "libresoc.v:43483.3-43511.6" - process $proc$libresoc.v:43483$2355 + attribute \src "libresoc.v:43485.3-43513.6" + process $proc$libresoc.v:43485$2355 assign { } { } assign { } { } assign $0\fus_cu_issue_i$25[0:0]$2356 $1\fus_cu_issue_i$25[0:0]$2357 - attribute \src "libresoc.v:43484.5-43484.29" + attribute \src "libresoc.v:43486.5-43486.29" switch \initial - attribute \src "libresoc.v:43484.9-43484.17" + attribute \src "libresoc.v:43486.9-43486.17" case 1'1 case end @@ -75567,14 +75569,14 @@ module \core sync always update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2356 end - attribute \src "libresoc.v:43512.3-43540.6" - process $proc$libresoc.v:43512$2360 + attribute \src "libresoc.v:43514.3-43542.6" + process $proc$libresoc.v:43514$2360 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$27[5:0]$2361 $1\fus_cu_rdmaskn_i$27[5:0]$2362 - attribute \src "libresoc.v:43513.5-43513.29" + attribute \src "libresoc.v:43515.5-43515.29" switch \initial - attribute \src "libresoc.v:43513.9-43513.17" + attribute \src "libresoc.v:43515.9-43515.17" case 1'1 case end @@ -75612,14 +75614,14 @@ module \core sync always update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2361 end - attribute \src "libresoc.v:43541.3-43569.6" - process $proc$libresoc.v:43541$2365 + attribute \src "libresoc.v:43543.3-43571.6" + process $proc$libresoc.v:43543$2365 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43542.5-43542.29" + attribute \src "libresoc.v:43544.5-43544.29" switch \initial - attribute \src "libresoc.v:43542.9-43542.17" + attribute \src "libresoc.v:43544.9-43544.17" case 1'1 case end @@ -75657,14 +75659,14 @@ module \core sync always update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] end - attribute \src "libresoc.v:43570.3-43598.6" - process $proc$libresoc.v:43570$2366 + attribute \src "libresoc.v:43572.3-43600.6" + process $proc$libresoc.v:43572$2366 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__fn_unit[12:0] $1\fus_oper_i_alu_div0__fn_unit[12:0] - attribute \src "libresoc.v:43571.5-43571.29" + attribute \src "libresoc.v:43573.5-43573.29" switch \initial - attribute \src "libresoc.v:43571.9-43571.17" + attribute \src "libresoc.v:43573.9-43573.17" case 1'1 case end @@ -75702,17 +75704,17 @@ module \core sync always update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[12:0] end - attribute \src "libresoc.v:43599.3-43628.6" - process $proc$libresoc.v:43599$2367 + attribute \src "libresoc.v:43601.3-43630.6" + process $proc$libresoc.v:43601$2367 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43600.5-43600.29" + attribute \src "libresoc.v:43602.5-43602.29" switch \initial - attribute \src "libresoc.v:43600.9-43600.17" + attribute \src "libresoc.v:43602.9-43602.17" case 1'1 case end @@ -75760,17 +75762,17 @@ module \core update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] end - attribute \src "libresoc.v:43629.3-43658.6" - process $proc$libresoc.v:43629$2368 + attribute \src "libresoc.v:43631.3-43660.6" + process $proc$libresoc.v:43631$2368 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43630.5-43630.29" + attribute \src "libresoc.v:43632.5-43632.29" switch \initial - attribute \src "libresoc.v:43630.9-43630.17" + attribute \src "libresoc.v:43632.9-43632.17" case 1'1 case end @@ -75818,17 +75820,17 @@ module \core update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] end - attribute \src "libresoc.v:43659.3-43688.6" - process $proc$libresoc.v:43659$2369 + attribute \src "libresoc.v:43661.3-43690.6" + process $proc$libresoc.v:43661$2369 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43660.5-43660.29" + attribute \src "libresoc.v:43662.5-43662.29" switch \initial - attribute \src "libresoc.v:43660.9-43660.17" + attribute \src "libresoc.v:43662.9-43662.17" case 1'1 case end @@ -75876,14 +75878,14 @@ module \core update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] end - attribute \src "libresoc.v:43689.3-43717.6" - process $proc$libresoc.v:43689$2370 + attribute \src "libresoc.v:43691.3-43719.6" + process $proc$libresoc.v:43691$2370 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43690.5-43690.29" + attribute \src "libresoc.v:43692.5-43692.29" switch \initial - attribute \src "libresoc.v:43690.9-43690.17" + attribute \src "libresoc.v:43692.9-43692.17" case 1'1 case end @@ -75921,14 +75923,14 @@ module \core sync always update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] end - attribute \src "libresoc.v:43718.3-43746.6" - process $proc$libresoc.v:43718$2371 + attribute \src "libresoc.v:43720.3-43748.6" + process $proc$libresoc.v:43720$2371 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43719.5-43719.29" + attribute \src "libresoc.v:43721.5-43721.29" switch \initial - attribute \src "libresoc.v:43719.9-43719.17" + attribute \src "libresoc.v:43721.9-43721.17" case 1'1 case end @@ -75966,14 +75968,14 @@ module \core sync always update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] end - attribute \src "libresoc.v:43747.3-43775.6" - process $proc$libresoc.v:43747$2372 + attribute \src "libresoc.v:43749.3-43777.6" + process $proc$libresoc.v:43749$2372 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43748.5-43748.29" + attribute \src "libresoc.v:43750.5-43750.29" switch \initial - attribute \src "libresoc.v:43748.9-43748.17" + attribute \src "libresoc.v:43750.9-43750.17" case 1'1 case end @@ -76011,14 +76013,14 @@ module \core sync always update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] end - attribute \src "libresoc.v:43776.3-43804.6" - process $proc$libresoc.v:43776$2373 + attribute \src "libresoc.v:43778.3-43806.6" + process $proc$libresoc.v:43778$2373 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43777.5-43777.29" + attribute \src "libresoc.v:43779.5-43779.29" switch \initial - attribute \src "libresoc.v:43777.9-43777.17" + attribute \src "libresoc.v:43779.9-43779.17" case 1'1 case end @@ -76056,14 +76058,14 @@ module \core sync always update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] end - attribute \src "libresoc.v:43805.3-43833.6" - process $proc$libresoc.v:43805$2374 + attribute \src "libresoc.v:43807.3-43835.6" + process $proc$libresoc.v:43807$2374 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43806.5-43806.29" + attribute \src "libresoc.v:43808.5-43808.29" switch \initial - attribute \src "libresoc.v:43806.9-43806.17" + attribute \src "libresoc.v:43808.9-43808.17" case 1'1 case end @@ -76101,14 +76103,14 @@ module \core sync always update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] end - attribute \src "libresoc.v:43834.3-43862.6" - process $proc$libresoc.v:43834$2375 + attribute \src "libresoc.v:43836.3-43864.6" + process $proc$libresoc.v:43836$2375 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43835.5-43835.29" + attribute \src "libresoc.v:43837.5-43837.29" switch \initial - attribute \src "libresoc.v:43835.9-43835.17" + attribute \src "libresoc.v:43837.9-43837.17" case 1'1 case end @@ -76146,14 +76148,14 @@ module \core sync always update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] end - attribute \src "libresoc.v:43863.3-43891.6" - process $proc$libresoc.v:43863$2376 + attribute \src "libresoc.v:43865.3-43893.6" + process $proc$libresoc.v:43865$2376 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43864.5-43864.29" + attribute \src "libresoc.v:43866.5-43866.29" switch \initial - attribute \src "libresoc.v:43864.9-43864.17" + attribute \src "libresoc.v:43866.9-43866.17" case 1'1 case end @@ -76191,14 +76193,14 @@ module \core sync always update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] end - attribute \src "libresoc.v:43892.3-43920.6" - process $proc$libresoc.v:43892$2377 + attribute \src "libresoc.v:43894.3-43922.6" + process $proc$libresoc.v:43894$2377 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43893.5-43893.29" + attribute \src "libresoc.v:43895.5-43895.29" switch \initial - attribute \src "libresoc.v:43893.9-43893.17" + attribute \src "libresoc.v:43895.9-43895.17" case 1'1 case end @@ -76236,14 +76238,14 @@ module \core sync always update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] end - attribute \src "libresoc.v:43921.3-43949.6" - process $proc$libresoc.v:43921$2378 + attribute \src "libresoc.v:43923.3-43951.6" + process $proc$libresoc.v:43923$2378 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43922.5-43922.29" + attribute \src "libresoc.v:43924.5-43924.29" switch \initial - attribute \src "libresoc.v:43922.9-43922.17" + attribute \src "libresoc.v:43924.9-43924.17" case 1'1 case end @@ -76281,14 +76283,14 @@ module \core sync always update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] end - attribute \src "libresoc.v:43950.3-43978.6" - process $proc$libresoc.v:43950$2379 + attribute \src "libresoc.v:43952.3-43980.6" + process $proc$libresoc.v:43952$2379 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43951.5-43951.29" + attribute \src "libresoc.v:43953.5-43953.29" switch \initial - attribute \src "libresoc.v:43951.9-43951.17" + attribute \src "libresoc.v:43953.9-43953.17" case 1'1 case end @@ -76326,14 +76328,14 @@ module \core sync always update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] end - attribute \src "libresoc.v:43979.3-44007.6" - process $proc$libresoc.v:43979$2380 + attribute \src "libresoc.v:43981.3-44009.6" + process $proc$libresoc.v:43981$2380 assign { } { } assign { } { } assign $0\fus_cu_issue_i$28[0:0]$2381 $1\fus_cu_issue_i$28[0:0]$2382 - attribute \src "libresoc.v:43980.5-43980.29" + attribute \src "libresoc.v:43982.5-43982.29" switch \initial - attribute \src "libresoc.v:43980.9-43980.17" + attribute \src "libresoc.v:43982.9-43982.17" case 1'1 case end @@ -76371,14 +76373,14 @@ module \core sync always update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2381 end - attribute \src "libresoc.v:44008.3-44036.6" - process $proc$libresoc.v:44008$2385 + attribute \src "libresoc.v:44010.3-44038.6" + process $proc$libresoc.v:44010$2385 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$30[2:0]$2386 $1\fus_cu_rdmaskn_i$30[2:0]$2387 - attribute \src "libresoc.v:44009.5-44009.29" + attribute \src "libresoc.v:44011.5-44011.29" switch \initial - attribute \src "libresoc.v:44009.9-44009.17" + attribute \src "libresoc.v:44011.9-44011.17" case 1'1 case end @@ -76416,14 +76418,14 @@ module \core sync always update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2386 end - attribute \src "libresoc.v:44037.3-44065.6" - process $proc$libresoc.v:44037$2390 + attribute \src "libresoc.v:44039.3-44067.6" + process $proc$libresoc.v:44039$2390 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44038.5-44038.29" + attribute \src "libresoc.v:44040.5-44040.29" switch \initial - attribute \src "libresoc.v:44038.9-44038.17" + attribute \src "libresoc.v:44040.9-44040.17" case 1'1 case end @@ -76461,14 +76463,14 @@ module \core sync always update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] end - attribute \src "libresoc.v:44066.3-44094.6" - process $proc$libresoc.v:44066$2391 + attribute \src "libresoc.v:44068.3-44096.6" + process $proc$libresoc.v:44068$2391 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__fn_unit[12:0] $1\fus_oper_i_alu_mul0__fn_unit[12:0] - attribute \src "libresoc.v:44067.5-44067.29" + attribute \src "libresoc.v:44069.5-44069.29" switch \initial - attribute \src "libresoc.v:44067.9-44067.17" + attribute \src "libresoc.v:44069.9-44069.17" case 1'1 case end @@ -76506,17 +76508,17 @@ module \core sync always update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[12:0] end - attribute \src "libresoc.v:44095.3-44124.6" - process $proc$libresoc.v:44095$2392 + attribute \src "libresoc.v:44097.3-44126.6" + process $proc$libresoc.v:44097$2392 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44096.5-44096.29" + attribute \src "libresoc.v:44098.5-44098.29" switch \initial - attribute \src "libresoc.v:44096.9-44096.17" + attribute \src "libresoc.v:44098.9-44098.17" case 1'1 case end @@ -76564,17 +76566,17 @@ module \core update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44125.3-44154.6" - process $proc$libresoc.v:44125$2393 + attribute \src "libresoc.v:44127.3-44156.6" + process $proc$libresoc.v:44127$2393 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44126.5-44126.29" + attribute \src "libresoc.v:44128.5-44128.29" switch \initial - attribute \src "libresoc.v:44126.9-44126.17" + attribute \src "libresoc.v:44128.9-44128.17" case 1'1 case end @@ -76622,17 +76624,17 @@ module \core update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] end - attribute \src "libresoc.v:44155.3-44184.6" - process $proc$libresoc.v:44155$2394 + attribute \src "libresoc.v:44157.3-44186.6" + process $proc$libresoc.v:44157$2394 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44156.5-44156.29" + attribute \src "libresoc.v:44158.5-44158.29" switch \initial - attribute \src "libresoc.v:44156.9-44156.17" + attribute \src "libresoc.v:44158.9-44158.17" case 1'1 case end @@ -76680,14 +76682,14 @@ module \core update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] end - attribute \src "libresoc.v:44185.3-44213.6" - process $proc$libresoc.v:44185$2395 + attribute \src "libresoc.v:44187.3-44215.6" + process $proc$libresoc.v:44187$2395 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44186.5-44186.29" + attribute \src "libresoc.v:44188.5-44188.29" switch \initial - attribute \src "libresoc.v:44186.9-44186.17" + attribute \src "libresoc.v:44188.9-44188.17" case 1'1 case end @@ -76725,14 +76727,14 @@ module \core sync always update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] end - attribute \src "libresoc.v:44214.3-44242.6" - process $proc$libresoc.v:44214$2396 + attribute \src "libresoc.v:44216.3-44244.6" + process $proc$libresoc.v:44216$2396 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44215.5-44215.29" + attribute \src "libresoc.v:44217.5-44217.29" switch \initial - attribute \src "libresoc.v:44215.9-44215.17" + attribute \src "libresoc.v:44217.9-44217.17" case 1'1 case end @@ -76770,14 +76772,14 @@ module \core sync always update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] end - attribute \src "libresoc.v:44243.3-44271.6" - process $proc$libresoc.v:44243$2397 + attribute \src "libresoc.v:44245.3-44273.6" + process $proc$libresoc.v:44245$2397 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44244.5-44244.29" + attribute \src "libresoc.v:44246.5-44246.29" switch \initial - attribute \src "libresoc.v:44244.9-44244.17" + attribute \src "libresoc.v:44246.9-44246.17" case 1'1 case end @@ -76815,14 +76817,14 @@ module \core sync always update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] end - attribute \src "libresoc.v:44272.3-44300.6" - process $proc$libresoc.v:44272$2398 + attribute \src "libresoc.v:44274.3-44302.6" + process $proc$libresoc.v:44274$2398 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44273.5-44273.29" + attribute \src "libresoc.v:44275.5-44275.29" switch \initial - attribute \src "libresoc.v:44273.9-44273.17" + attribute \src "libresoc.v:44275.9-44275.17" case 1'1 case end @@ -76860,14 +76862,14 @@ module \core sync always update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] end - attribute \src "libresoc.v:44301.3-44329.6" - process $proc$libresoc.v:44301$2399 + attribute \src "libresoc.v:44303.3-44331.6" + process $proc$libresoc.v:44303$2399 assign { } { } assign { } { } assign $0\fus_cu_issue_i$31[0:0]$2400 $1\fus_cu_issue_i$31[0:0]$2401 - attribute \src "libresoc.v:44302.5-44302.29" + attribute \src "libresoc.v:44304.5-44304.29" switch \initial - attribute \src "libresoc.v:44302.9-44302.17" + attribute \src "libresoc.v:44304.9-44304.17" case 1'1 case end @@ -76905,14 +76907,14 @@ module \core sync always update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2400 end - attribute \src "libresoc.v:44330.3-44358.6" - process $proc$libresoc.v:44330$2404 + attribute \src "libresoc.v:44332.3-44360.6" + process $proc$libresoc.v:44332$2404 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$33[2:0]$2405 $1\fus_cu_rdmaskn_i$33[2:0]$2406 - attribute \src "libresoc.v:44331.5-44331.29" + attribute \src "libresoc.v:44333.5-44333.29" switch \initial - attribute \src "libresoc.v:44331.9-44331.17" + attribute \src "libresoc.v:44333.9-44333.17" case 1'1 case end @@ -76950,14 +76952,14 @@ module \core sync always update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2405 end - attribute \src "libresoc.v:44359.3-44387.6" - process $proc$libresoc.v:44359$2409 + attribute \src "libresoc.v:44361.3-44389.6" + process $proc$libresoc.v:44361$2409 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44360.5-44360.29" + attribute \src "libresoc.v:44362.5-44362.29" switch \initial - attribute \src "libresoc.v:44360.9-44360.17" + attribute \src "libresoc.v:44362.9-44362.17" case 1'1 case end @@ -76995,14 +76997,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] end - attribute \src "libresoc.v:44388.3-44416.6" - process $proc$libresoc.v:44388$2410 + attribute \src "libresoc.v:44390.3-44418.6" + process $proc$libresoc.v:44390$2410 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__fn_unit[12:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[12:0] - attribute \src "libresoc.v:44389.5-44389.29" + attribute \src "libresoc.v:44391.5-44391.29" switch \initial - attribute \src "libresoc.v:44389.9-44389.17" + attribute \src "libresoc.v:44391.9-44391.17" case 1'1 case end @@ -77040,17 +77042,17 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[12:0] end - attribute \src "libresoc.v:44417.3-44446.6" - process $proc$libresoc.v:44417$2411 + attribute \src "libresoc.v:44419.3-44448.6" + process $proc$libresoc.v:44419$2411 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44418.5-44418.29" + attribute \src "libresoc.v:44420.5-44420.29" switch \initial - attribute \src "libresoc.v:44418.9-44418.17" + attribute \src "libresoc.v:44420.9-44420.17" case 1'1 case end @@ -77098,17 +77100,17 @@ module \core update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44447.3-44476.6" - process $proc$libresoc.v:44447$2412 + attribute \src "libresoc.v:44449.3-44478.6" + process $proc$libresoc.v:44449$2412 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44448.5-44448.29" + attribute \src "libresoc.v:44450.5-44450.29" switch \initial - attribute \src "libresoc.v:44448.9-44448.17" + attribute \src "libresoc.v:44450.9-44450.17" case 1'1 case end @@ -77156,17 +77158,17 @@ module \core update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] end - attribute \src "libresoc.v:44477.3-44506.6" - process $proc$libresoc.v:44477$2413 + attribute \src "libresoc.v:44479.3-44508.6" + process $proc$libresoc.v:44479$2413 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44478.5-44478.29" + attribute \src "libresoc.v:44480.5-44480.29" switch \initial - attribute \src "libresoc.v:44478.9-44478.17" + attribute \src "libresoc.v:44480.9-44480.17" case 1'1 case end @@ -77214,14 +77216,14 @@ module \core update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] end - attribute \src "libresoc.v:44507.3-44535.6" - process $proc$libresoc.v:44507$2414 + attribute \src "libresoc.v:44509.3-44537.6" + process $proc$libresoc.v:44509$2414 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:44508.5-44508.29" + attribute \src "libresoc.v:44510.5-44510.29" switch \initial - attribute \src "libresoc.v:44508.9-44508.17" + attribute \src "libresoc.v:44510.9-44510.17" case 1'1 case end @@ -77259,14 +77261,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] end - attribute \src "libresoc.v:44536.3-44564.6" - process $proc$libresoc.v:44536$2415 + attribute \src "libresoc.v:44538.3-44566.6" + process $proc$libresoc.v:44538$2415 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44537.5-44537.29" + attribute \src "libresoc.v:44539.5-44539.29" switch \initial - attribute \src "libresoc.v:44537.9-44537.17" + attribute \src "libresoc.v:44539.9-44539.17" case 1'1 case end @@ -77304,14 +77306,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] end - attribute \src "libresoc.v:44565.3-44593.6" - process $proc$libresoc.v:44565$2416 + attribute \src "libresoc.v:44567.3-44595.6" + process $proc$libresoc.v:44567$2416 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44566.5-44566.29" + attribute \src "libresoc.v:44568.5-44568.29" switch \initial - attribute \src "libresoc.v:44566.9-44566.17" + attribute \src "libresoc.v:44568.9-44568.17" case 1'1 case end @@ -77349,14 +77351,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] end - attribute \src "libresoc.v:44594.3-44622.6" - process $proc$libresoc.v:44594$2417 + attribute \src "libresoc.v:44596.3-44624.6" + process $proc$libresoc.v:44596$2417 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44595.5-44595.29" + attribute \src "libresoc.v:44597.5-44597.29" switch \initial - attribute \src "libresoc.v:44595.9-44595.17" + attribute \src "libresoc.v:44597.9-44597.17" case 1'1 case end @@ -77394,14 +77396,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] end - attribute \src "libresoc.v:44623.3-44651.6" - process $proc$libresoc.v:44623$2418 + attribute \src "libresoc.v:44625.3-44653.6" + process $proc$libresoc.v:44625$2418 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44624.5-44624.29" + attribute \src "libresoc.v:44626.5-44626.29" switch \initial - attribute \src "libresoc.v:44624.9-44624.17" + attribute \src "libresoc.v:44626.9-44626.17" case 1'1 case end @@ -77439,14 +77441,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] end - attribute \src "libresoc.v:44652.3-44680.6" - process $proc$libresoc.v:44652$2419 + attribute \src "libresoc.v:44654.3-44682.6" + process $proc$libresoc.v:44654$2419 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44653.5-44653.29" + attribute \src "libresoc.v:44655.5-44655.29" switch \initial - attribute \src "libresoc.v:44653.9-44653.17" + attribute \src "libresoc.v:44655.9-44655.17" case 1'1 case end @@ -77484,14 +77486,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] end - attribute \src "libresoc.v:44681.3-44709.6" - process $proc$libresoc.v:44681$2420 + attribute \src "libresoc.v:44683.3-44711.6" + process $proc$libresoc.v:44683$2420 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44682.5-44682.29" + attribute \src "libresoc.v:44684.5-44684.29" switch \initial - attribute \src "libresoc.v:44682.9-44682.17" + attribute \src "libresoc.v:44684.9-44684.17" case 1'1 case end @@ -77529,14 +77531,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] end - attribute \src "libresoc.v:44710.3-44738.6" - process $proc$libresoc.v:44710$2421 + attribute \src "libresoc.v:44712.3-44740.6" + process $proc$libresoc.v:44712$2421 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44711.5-44711.29" + attribute \src "libresoc.v:44713.5-44713.29" switch \initial - attribute \src "libresoc.v:44711.9-44711.17" + attribute \src "libresoc.v:44713.9-44713.17" case 1'1 case end @@ -77574,14 +77576,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] end - attribute \src "libresoc.v:44739.3-44767.6" - process $proc$libresoc.v:44739$2422 + attribute \src "libresoc.v:44741.3-44769.6" + process $proc$libresoc.v:44741$2422 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44740.5-44740.29" + attribute \src "libresoc.v:44742.5-44742.29" switch \initial - attribute \src "libresoc.v:44740.9-44740.17" + attribute \src "libresoc.v:44742.9-44742.17" case 1'1 case end @@ -77619,14 +77621,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] end - attribute \src "libresoc.v:44768.3-44796.6" - process $proc$libresoc.v:44768$2423 + attribute \src "libresoc.v:44770.3-44798.6" + process $proc$libresoc.v:44770$2423 assign { } { } assign { } { } assign $0\fus_cu_issue_i$34[0:0]$2424 $1\fus_cu_issue_i$34[0:0]$2425 - attribute \src "libresoc.v:44769.5-44769.29" + attribute \src "libresoc.v:44771.5-44771.29" switch \initial - attribute \src "libresoc.v:44769.9-44769.17" + attribute \src "libresoc.v:44771.9-44771.17" case 1'1 case end @@ -77664,14 +77666,14 @@ module \core sync always update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2424 end - attribute \src "libresoc.v:44797.3-44825.6" - process $proc$libresoc.v:44797$2428 + attribute \src "libresoc.v:44799.3-44827.6" + process $proc$libresoc.v:44799$2428 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$36[4:0]$2429 $1\fus_cu_rdmaskn_i$36[4:0]$2430 - attribute \src "libresoc.v:44798.5-44798.29" + attribute \src "libresoc.v:44800.5-44800.29" switch \initial - attribute \src "libresoc.v:44798.9-44798.17" + attribute \src "libresoc.v:44800.9-44800.17" case 1'1 case end @@ -77709,14 +77711,14 @@ module \core sync always update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2429 end - attribute \src "libresoc.v:44826.3-44854.6" - process $proc$libresoc.v:44826$2433 + attribute \src "libresoc.v:44828.3-44856.6" + process $proc$libresoc.v:44828$2433 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44827.5-44827.29" + attribute \src "libresoc.v:44829.5-44829.29" switch \initial - attribute \src "libresoc.v:44827.9-44827.17" + attribute \src "libresoc.v:44829.9-44829.17" case 1'1 case end @@ -77754,14 +77756,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] end - attribute \src "libresoc.v:44855.3-44883.6" - process $proc$libresoc.v:44855$2434 + attribute \src "libresoc.v:44857.3-44885.6" + process $proc$libresoc.v:44857$2434 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__fn_unit[12:0] $1\fus_oper_i_ldst_ldst0__fn_unit[12:0] - attribute \src "libresoc.v:44856.5-44856.29" + attribute \src "libresoc.v:44858.5-44858.29" switch \initial - attribute \src "libresoc.v:44856.9-44856.17" + attribute \src "libresoc.v:44858.9-44858.17" case 1'1 case end @@ -77799,17 +77801,17 @@ module \core sync always update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[12:0] end - attribute \src "libresoc.v:44884.3-44913.6" - process $proc$libresoc.v:44884$2435 + attribute \src "libresoc.v:44886.3-44915.6" + process $proc$libresoc.v:44886$2435 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44885.5-44885.29" + attribute \src "libresoc.v:44887.5-44887.29" switch \initial - attribute \src "libresoc.v:44885.9-44885.17" + attribute \src "libresoc.v:44887.9-44887.17" case 1'1 case end @@ -77857,14 +77859,14 @@ module \core update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44914.3-44942.6" - process $proc$libresoc.v:44914$2436 + attribute \src "libresoc.v:44916.3-44944.6" + process $proc$libresoc.v:44916$2436 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:44915.5-44915.29" + attribute \src "libresoc.v:44917.5-44917.29" switch \initial - attribute \src "libresoc.v:44915.9-44915.17" + attribute \src "libresoc.v:44917.9-44917.17" case 1'1 case end @@ -77902,17 +77904,17 @@ module \core sync always update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] end - attribute \src "libresoc.v:44943.3-44972.6" - process $proc$libresoc.v:44943$2437 + attribute \src "libresoc.v:44945.3-44974.6" + process $proc$libresoc.v:44945$2437 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44944.5-44944.29" + attribute \src "libresoc.v:44946.5-44946.29" switch \initial - attribute \src "libresoc.v:44944.9-44944.17" + attribute \src "libresoc.v:44946.9-44946.17" case 1'1 case end @@ -77960,17 +77962,17 @@ module \core update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] end - attribute \src "libresoc.v:44973.3-45002.6" - process $proc$libresoc.v:44973$2438 + attribute \src "libresoc.v:44975.3-45004.6" + process $proc$libresoc.v:44975$2438 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44974.5-44974.29" + attribute \src "libresoc.v:44976.5-44976.29" switch \initial - attribute \src "libresoc.v:44974.9-44974.17" + attribute \src "libresoc.v:44976.9-44976.17" case 1'1 case end @@ -78018,14 +78020,14 @@ module \core update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] end - attribute \src "libresoc.v:45003.3-45031.6" - process $proc$libresoc.v:45003$2439 + attribute \src "libresoc.v:45005.3-45033.6" + process $proc$libresoc.v:45005$2439 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45004.5-45004.29" + attribute \src "libresoc.v:45006.5-45006.29" switch \initial - attribute \src "libresoc.v:45004.9-45004.17" + attribute \src "libresoc.v:45006.9-45006.17" case 1'1 case end @@ -78063,14 +78065,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] end - attribute \src "libresoc.v:45032.3-45060.6" - process $proc$libresoc.v:45032$2440 + attribute \src "libresoc.v:45034.3-45062.6" + process $proc$libresoc.v:45034$2440 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45033.5-45033.29" + attribute \src "libresoc.v:45035.5-45035.29" switch \initial - attribute \src "libresoc.v:45033.9-45033.17" + attribute \src "libresoc.v:45035.9-45035.17" case 1'1 case end @@ -78108,14 +78110,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] end - attribute \src "libresoc.v:45061.3-45089.6" - process $proc$libresoc.v:45061$2441 + attribute \src "libresoc.v:45063.3-45091.6" + process $proc$libresoc.v:45063$2441 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45062.5-45062.29" + attribute \src "libresoc.v:45064.5-45064.29" switch \initial - attribute \src "libresoc.v:45062.9-45062.17" + attribute \src "libresoc.v:45064.9-45064.17" case 1'1 case end @@ -78153,14 +78155,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] end - attribute \src "libresoc.v:45090.3-45118.6" - process $proc$libresoc.v:45090$2442 + attribute \src "libresoc.v:45092.3-45120.6" + process $proc$libresoc.v:45092$2442 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45091.5-45091.29" + attribute \src "libresoc.v:45093.5-45093.29" switch \initial - attribute \src "libresoc.v:45091.9-45091.17" + attribute \src "libresoc.v:45093.9-45093.17" case 1'1 case end @@ -78198,14 +78200,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] end - attribute \src "libresoc.v:45119.3-45147.6" - process $proc$libresoc.v:45119$2443 + attribute \src "libresoc.v:45121.3-45149.6" + process $proc$libresoc.v:45121$2443 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45120.5-45120.29" + attribute \src "libresoc.v:45122.5-45122.29" switch \initial - attribute \src "libresoc.v:45120.9-45120.17" + attribute \src "libresoc.v:45122.9-45122.17" case 1'1 case end @@ -78243,14 +78245,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] end - attribute \src "libresoc.v:45148.3-45176.6" - process $proc$libresoc.v:45148$2444 + attribute \src "libresoc.v:45150.3-45178.6" + process $proc$libresoc.v:45150$2444 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45149.5-45149.29" + attribute \src "libresoc.v:45151.5-45151.29" switch \initial - attribute \src "libresoc.v:45149.9-45149.17" + attribute \src "libresoc.v:45151.9-45151.17" case 1'1 case end @@ -78288,14 +78290,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] end - attribute \src "libresoc.v:45177.3-45205.6" - process $proc$libresoc.v:45177$2445 + attribute \src "libresoc.v:45179.3-45207.6" + process $proc$libresoc.v:45179$2445 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45178.5-45178.29" + attribute \src "libresoc.v:45180.5-45180.29" switch \initial - attribute \src "libresoc.v:45178.9-45178.17" + attribute \src "libresoc.v:45180.9-45180.17" case 1'1 case end @@ -78333,14 +78335,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] end - attribute \src "libresoc.v:45206.3-45234.6" - process $proc$libresoc.v:45206$2446 + attribute \src "libresoc.v:45208.3-45236.6" + process $proc$libresoc.v:45208$2446 assign { } { } assign { } { } assign $0\fus_cu_issue_i$37[0:0]$2447 $1\fus_cu_issue_i$37[0:0]$2448 - attribute \src "libresoc.v:45207.5-45207.29" + attribute \src "libresoc.v:45209.5-45209.29" switch \initial - attribute \src "libresoc.v:45207.9-45207.17" + attribute \src "libresoc.v:45209.9-45209.17" case 1'1 case end @@ -78378,14 +78380,14 @@ module \core sync always update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2447 end - attribute \src "libresoc.v:45235.3-45263.6" - process $proc$libresoc.v:45235$2451 + attribute \src "libresoc.v:45237.3-45265.6" + process $proc$libresoc.v:45237$2451 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$39[2:0]$2452 $1\fus_cu_rdmaskn_i$39[2:0]$2453 - attribute \src "libresoc.v:45236.5-45236.29" + attribute \src "libresoc.v:45238.5-45238.29" switch \initial - attribute \src "libresoc.v:45236.9-45236.17" + attribute \src "libresoc.v:45238.9-45238.17" case 1'1 case end @@ -78423,14 +78425,14 @@ module \core sync always update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2452 end - attribute \src "libresoc.v:45264.3-45272.6" - process $proc$libresoc.v:45264$2456 + attribute \src "libresoc.v:45266.3-45274.6" + process $proc$libresoc.v:45266$2456 assign { } { } assign { } { } assign $0\dp_INT_ra_alu0_0$next[0:0]$2457 $1\dp_INT_ra_alu0_0$next[0:0]$2458 - attribute \src "libresoc.v:45265.5-45265.29" + attribute \src "libresoc.v:45267.5-45267.29" switch \initial - attribute \src "libresoc.v:45265.9-45265.17" + attribute \src "libresoc.v:45267.9-45267.17" case 1'1 case end @@ -78446,14 +78448,14 @@ module \core sync always update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2457 end - attribute \src "libresoc.v:45273.3-45282.6" - process $proc$libresoc.v:45273$2459 + attribute \src "libresoc.v:45275.3-45284.6" + process $proc$libresoc.v:45275$2459 assign { } { } assign { } { } assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] - attribute \src "libresoc.v:45274.5-45274.29" + attribute \src "libresoc.v:45276.5-45276.29" switch \initial - attribute \src "libresoc.v:45274.9-45274.17" + attribute \src "libresoc.v:45276.9-45276.17" case 1'1 case end @@ -78469,14 +78471,14 @@ module \core sync always update \fus_src1_i $0\fus_src1_i[63:0] end - attribute \src "libresoc.v:45283.3-45291.6" - process $proc$libresoc.v:45283$2460 + attribute \src "libresoc.v:45285.3-45293.6" + process $proc$libresoc.v:45285$2460 assign { } { } assign { } { } assign $0\dp_INT_ra_cr0_1$next[0:0]$2461 $1\dp_INT_ra_cr0_1$next[0:0]$2462 - attribute \src "libresoc.v:45284.5-45284.29" + attribute \src "libresoc.v:45286.5-45286.29" switch \initial - attribute \src "libresoc.v:45284.9-45284.17" + attribute \src "libresoc.v:45286.9-45286.17" case 1'1 case end @@ -78492,14 +78494,14 @@ module \core sync always update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2461 end - attribute \src "libresoc.v:45292.3-45301.6" - process $proc$libresoc.v:45292$2463 + attribute \src "libresoc.v:45294.3-45303.6" + process $proc$libresoc.v:45294$2463 assign { } { } assign { } { } assign $0\fus_src1_i$42[63:0]$2464 $1\fus_src1_i$42[63:0]$2465 - attribute \src "libresoc.v:45293.5-45293.29" + attribute \src "libresoc.v:45295.5-45295.29" switch \initial - attribute \src "libresoc.v:45293.9-45293.17" + attribute \src "libresoc.v:45295.9-45295.17" case 1'1 case end @@ -78515,14 +78517,14 @@ module \core sync always update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2464 end - attribute \src "libresoc.v:45302.3-45310.6" - process $proc$libresoc.v:45302$2466 + attribute \src "libresoc.v:45304.3-45312.6" + process $proc$libresoc.v:45304$2466 assign { } { } assign { } { } assign $0\dp_INT_ra_trap0_2$next[0:0]$2467 $1\dp_INT_ra_trap0_2$next[0:0]$2468 - attribute \src "libresoc.v:45303.5-45303.29" + attribute \src "libresoc.v:45305.5-45305.29" switch \initial - attribute \src "libresoc.v:45303.9-45303.17" + attribute \src "libresoc.v:45305.9-45305.17" case 1'1 case end @@ -78538,14 +78540,14 @@ module \core sync always update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2467 end - attribute \src "libresoc.v:45311.3-45320.6" - process $proc$libresoc.v:45311$2469 + attribute \src "libresoc.v:45313.3-45322.6" + process $proc$libresoc.v:45313$2469 assign { } { } assign { } { } assign $0\fus_src1_i$45[63:0]$2470 $1\fus_src1_i$45[63:0]$2471 - attribute \src "libresoc.v:45312.5-45312.29" + attribute \src "libresoc.v:45314.5-45314.29" switch \initial - attribute \src "libresoc.v:45312.9-45312.17" + attribute \src "libresoc.v:45314.9-45314.17" case 1'1 case end @@ -78561,14 +78563,14 @@ module \core sync always update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2470 end - attribute \src "libresoc.v:45321.3-45329.6" - process $proc$libresoc.v:45321$2472 + attribute \src "libresoc.v:45323.3-45331.6" + process $proc$libresoc.v:45323$2472 assign { } { } assign { } { } assign $0\dp_INT_ra_logical0_3$next[0:0]$2473 $1\dp_INT_ra_logical0_3$next[0:0]$2474 - attribute \src "libresoc.v:45322.5-45322.29" + attribute \src "libresoc.v:45324.5-45324.29" switch \initial - attribute \src "libresoc.v:45322.9-45322.17" + attribute \src "libresoc.v:45324.9-45324.17" case 1'1 case end @@ -78584,14 +78586,14 @@ module \core sync always update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2473 end - attribute \src "libresoc.v:45330.3-45339.6" - process $proc$libresoc.v:45330$2475 + attribute \src "libresoc.v:45332.3-45341.6" + process $proc$libresoc.v:45332$2475 assign { } { } assign { } { } assign $0\fus_src1_i$48[63:0]$2476 $1\fus_src1_i$48[63:0]$2477 - attribute \src "libresoc.v:45331.5-45331.29" + attribute \src "libresoc.v:45333.5-45333.29" switch \initial - attribute \src "libresoc.v:45331.9-45331.17" + attribute \src "libresoc.v:45333.9-45333.17" case 1'1 case end @@ -78607,14 +78609,14 @@ module \core sync always update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2476 end - attribute \src "libresoc.v:45340.3-45348.6" - process $proc$libresoc.v:45340$2478 + attribute \src "libresoc.v:45342.3-45350.6" + process $proc$libresoc.v:45342$2478 assign { } { } assign { } { } assign $0\dp_INT_ra_spr0_4$next[0:0]$2479 $1\dp_INT_ra_spr0_4$next[0:0]$2480 - attribute \src "libresoc.v:45341.5-45341.29" + attribute \src "libresoc.v:45343.5-45343.29" switch \initial - attribute \src "libresoc.v:45341.9-45341.17" + attribute \src "libresoc.v:45343.9-45343.17" case 1'1 case end @@ -78630,14 +78632,14 @@ module \core sync always update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2479 end - attribute \src "libresoc.v:45349.3-45358.6" - process $proc$libresoc.v:45349$2481 + attribute \src "libresoc.v:45351.3-45360.6" + process $proc$libresoc.v:45351$2481 assign { } { } assign { } { } assign $0\fus_src1_i$51[63:0]$2482 $1\fus_src1_i$51[63:0]$2483 - attribute \src "libresoc.v:45350.5-45350.29" + attribute \src "libresoc.v:45352.5-45352.29" switch \initial - attribute \src "libresoc.v:45350.9-45350.17" + attribute \src "libresoc.v:45352.9-45352.17" case 1'1 case end @@ -78653,14 +78655,14 @@ module \core sync always update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2482 end - attribute \src "libresoc.v:45359.3-45367.6" - process $proc$libresoc.v:45359$2484 + attribute \src "libresoc.v:45361.3-45369.6" + process $proc$libresoc.v:45361$2484 assign { } { } assign { } { } assign $0\dp_INT_ra_div0_5$next[0:0]$2485 $1\dp_INT_ra_div0_5$next[0:0]$2486 - attribute \src "libresoc.v:45360.5-45360.29" + attribute \src "libresoc.v:45362.5-45362.29" switch \initial - attribute \src "libresoc.v:45360.9-45360.17" + attribute \src "libresoc.v:45362.9-45362.17" case 1'1 case end @@ -78676,14 +78678,14 @@ module \core sync always update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2485 end - attribute \src "libresoc.v:45368.3-45377.6" - process $proc$libresoc.v:45368$2487 + attribute \src "libresoc.v:45370.3-45379.6" + process $proc$libresoc.v:45370$2487 assign { } { } assign { } { } assign $0\fus_src1_i$54[63:0]$2488 $1\fus_src1_i$54[63:0]$2489 - attribute \src "libresoc.v:45369.5-45369.29" + attribute \src "libresoc.v:45371.5-45371.29" switch \initial - attribute \src "libresoc.v:45369.9-45369.17" + attribute \src "libresoc.v:45371.9-45371.17" case 1'1 case end @@ -78699,14 +78701,14 @@ module \core sync always update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2488 end - attribute \src "libresoc.v:45378.3-45386.6" - process $proc$libresoc.v:45378$2490 + attribute \src "libresoc.v:45380.3-45388.6" + process $proc$libresoc.v:45380$2490 assign { } { } assign { } { } assign $0\dp_INT_ra_mul0_6$next[0:0]$2491 $1\dp_INT_ra_mul0_6$next[0:0]$2492 - attribute \src "libresoc.v:45379.5-45379.29" + attribute \src "libresoc.v:45381.5-45381.29" switch \initial - attribute \src "libresoc.v:45379.9-45379.17" + attribute \src "libresoc.v:45381.9-45381.17" case 1'1 case end @@ -78722,14 +78724,14 @@ module \core sync always update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2491 end - attribute \src "libresoc.v:45387.3-45396.6" - process $proc$libresoc.v:45387$2493 + attribute \src "libresoc.v:45389.3-45398.6" + process $proc$libresoc.v:45389$2493 assign { } { } assign { } { } assign $0\fus_src1_i$57[63:0]$2494 $1\fus_src1_i$57[63:0]$2495 - attribute \src "libresoc.v:45388.5-45388.29" + attribute \src "libresoc.v:45390.5-45390.29" switch \initial - attribute \src "libresoc.v:45388.9-45388.17" + attribute \src "libresoc.v:45390.9-45390.17" case 1'1 case end @@ -78745,14 +78747,14 @@ module \core sync always update \fus_src1_i$57 $0\fus_src1_i$57[63:0]$2494 end - attribute \src "libresoc.v:45397.3-45405.6" - process $proc$libresoc.v:45397$2496 + attribute \src "libresoc.v:45399.3-45407.6" + process $proc$libresoc.v:45399$2496 assign { } { } assign { } { } assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 - attribute \src "libresoc.v:45398.5-45398.29" + attribute \src "libresoc.v:45400.5-45400.29" switch \initial - attribute \src "libresoc.v:45398.9-45398.17" + attribute \src "libresoc.v:45400.9-45400.17" case 1'1 case end @@ -78768,14 +78770,14 @@ module \core sync always update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 end - attribute \src "libresoc.v:45406.3-45415.6" - process $proc$libresoc.v:45406$2499 + attribute \src "libresoc.v:45408.3-45417.6" + process $proc$libresoc.v:45408$2499 assign { } { } assign { } { } assign $0\fus_src1_i$60[63:0]$2500 $1\fus_src1_i$60[63:0]$2501 - attribute \src "libresoc.v:45407.5-45407.29" + attribute \src "libresoc.v:45409.5-45409.29" switch \initial - attribute \src "libresoc.v:45407.9-45407.17" + attribute \src "libresoc.v:45409.9-45409.17" case 1'1 case end @@ -78791,14 +78793,14 @@ module \core sync always update \fus_src1_i$60 $0\fus_src1_i$60[63:0]$2500 end - attribute \src "libresoc.v:45416.3-45424.6" - process $proc$libresoc.v:45416$2502 + attribute \src "libresoc.v:45418.3-45426.6" + process $proc$libresoc.v:45418$2502 assign { } { } assign { } { } assign $0\dp_INT_ra_ldst0_8$next[0:0]$2503 $1\dp_INT_ra_ldst0_8$next[0:0]$2504 - attribute \src "libresoc.v:45417.5-45417.29" + attribute \src "libresoc.v:45419.5-45419.29" switch \initial - attribute \src "libresoc.v:45417.9-45417.17" + attribute \src "libresoc.v:45419.9-45419.17" case 1'1 case end @@ -78814,14 +78816,14 @@ module \core sync always update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2503 end - attribute \src "libresoc.v:45425.3-45434.6" - process $proc$libresoc.v:45425$2505 + attribute \src "libresoc.v:45427.3-45436.6" + process $proc$libresoc.v:45427$2505 assign { } { } assign { } { } assign $0\fus_src1_i$63[63:0]$2506 $1\fus_src1_i$63[63:0]$2507 - attribute \src "libresoc.v:45426.5-45426.29" + attribute \src "libresoc.v:45428.5-45428.29" switch \initial - attribute \src "libresoc.v:45426.9-45426.17" + attribute \src "libresoc.v:45428.9-45428.17" case 1'1 case end @@ -78837,14 +78839,14 @@ module \core sync always update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2506 end - attribute \src "libresoc.v:45435.3-45443.6" - process $proc$libresoc.v:45435$2508 + attribute \src "libresoc.v:45437.3-45445.6" + process $proc$libresoc.v:45437$2508 assign { } { } assign { } { } assign $0\dp_INT_rb_alu0_0$next[0:0]$2509 $1\dp_INT_rb_alu0_0$next[0:0]$2510 - attribute \src "libresoc.v:45436.5-45436.29" + attribute \src "libresoc.v:45438.5-45438.29" switch \initial - attribute \src "libresoc.v:45436.9-45436.17" + attribute \src "libresoc.v:45438.9-45438.17" case 1'1 case end @@ -78860,14 +78862,14 @@ module \core sync always update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2509 end - attribute \src "libresoc.v:45444.3-45453.6" - process $proc$libresoc.v:45444$2511 + attribute \src "libresoc.v:45446.3-45455.6" + process $proc$libresoc.v:45446$2511 assign { } { } assign { } { } assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] - attribute \src "libresoc.v:45445.5-45445.29" + attribute \src "libresoc.v:45447.5-45447.29" switch \initial - attribute \src "libresoc.v:45445.9-45445.17" + attribute \src "libresoc.v:45447.9-45447.17" case 1'1 case end @@ -78883,14 +78885,14 @@ module \core sync always update \fus_src2_i $0\fus_src2_i[63:0] end - attribute \src "libresoc.v:45454.3-45462.6" - process $proc$libresoc.v:45454$2512 + attribute \src "libresoc.v:45456.3-45464.6" + process $proc$libresoc.v:45456$2512 assign { } { } assign { } { } assign $0\dp_INT_rb_cr0_1$next[0:0]$2513 $1\dp_INT_rb_cr0_1$next[0:0]$2514 - attribute \src "libresoc.v:45455.5-45455.29" + attribute \src "libresoc.v:45457.5-45457.29" switch \initial - attribute \src "libresoc.v:45455.9-45455.17" + attribute \src "libresoc.v:45457.9-45457.17" case 1'1 case end @@ -78906,14 +78908,14 @@ module \core sync always update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2513 end - attribute \src "libresoc.v:45463.3-45472.6" - process $proc$libresoc.v:45463$2515 + attribute \src "libresoc.v:45465.3-45474.6" + process $proc$libresoc.v:45465$2515 assign { } { } assign { } { } assign $0\fus_src2_i$64[63:0]$2516 $1\fus_src2_i$64[63:0]$2517 - attribute \src "libresoc.v:45464.5-45464.29" + attribute \src "libresoc.v:45466.5-45466.29" switch \initial - attribute \src "libresoc.v:45464.9-45464.17" + attribute \src "libresoc.v:45466.9-45466.17" case 1'1 case end @@ -78929,14 +78931,14 @@ module \core sync always update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2516 end - attribute \src "libresoc.v:45473.3-45481.6" - process $proc$libresoc.v:45473$2518 + attribute \src "libresoc.v:45475.3-45483.6" + process $proc$libresoc.v:45475$2518 assign { } { } assign { } { } assign $0\dp_INT_rb_trap0_2$next[0:0]$2519 $1\dp_INT_rb_trap0_2$next[0:0]$2520 - attribute \src "libresoc.v:45474.5-45474.29" + attribute \src "libresoc.v:45476.5-45476.29" switch \initial - attribute \src "libresoc.v:45474.9-45474.17" + attribute \src "libresoc.v:45476.9-45476.17" case 1'1 case end @@ -78952,14 +78954,14 @@ module \core sync always update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2519 end - attribute \src "libresoc.v:45482.3-45491.6" - process $proc$libresoc.v:45482$2521 + attribute \src "libresoc.v:45484.3-45493.6" + process $proc$libresoc.v:45484$2521 assign { } { } assign { } { } assign $0\fus_src2_i$65[63:0]$2522 $1\fus_src2_i$65[63:0]$2523 - attribute \src "libresoc.v:45483.5-45483.29" + attribute \src "libresoc.v:45485.5-45485.29" switch \initial - attribute \src "libresoc.v:45483.9-45483.17" + attribute \src "libresoc.v:45485.9-45485.17" case 1'1 case end @@ -78975,14 +78977,14 @@ module \core sync always update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2522 end - attribute \src "libresoc.v:45492.3-45500.6" - process $proc$libresoc.v:45492$2524 + attribute \src "libresoc.v:45494.3-45502.6" + process $proc$libresoc.v:45494$2524 assign { } { } assign { } { } assign $0\dp_INT_rb_logical0_3$next[0:0]$2525 $1\dp_INT_rb_logical0_3$next[0:0]$2526 - attribute \src "libresoc.v:45493.5-45493.29" + attribute \src "libresoc.v:45495.5-45495.29" switch \initial - attribute \src "libresoc.v:45493.9-45493.17" + attribute \src "libresoc.v:45495.9-45495.17" case 1'1 case end @@ -78998,14 +79000,14 @@ module \core sync always update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2525 end - attribute \src "libresoc.v:45501.3-45510.6" - process $proc$libresoc.v:45501$2527 + attribute \src "libresoc.v:45503.3-45512.6" + process $proc$libresoc.v:45503$2527 assign { } { } assign { } { } assign $0\fus_src2_i$66[63:0]$2528 $1\fus_src2_i$66[63:0]$2529 - attribute \src "libresoc.v:45502.5-45502.29" + attribute \src "libresoc.v:45504.5-45504.29" switch \initial - attribute \src "libresoc.v:45502.9-45502.17" + attribute \src "libresoc.v:45504.9-45504.17" case 1'1 case end @@ -79021,14 +79023,14 @@ module \core sync always update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2528 end - attribute \src "libresoc.v:45511.3-45519.6" - process $proc$libresoc.v:45511$2530 + attribute \src "libresoc.v:45513.3-45521.6" + process $proc$libresoc.v:45513$2530 assign { } { } assign { } { } assign $0\dp_INT_rb_div0_4$next[0:0]$2531 $1\dp_INT_rb_div0_4$next[0:0]$2532 - attribute \src "libresoc.v:45512.5-45512.29" + attribute \src "libresoc.v:45514.5-45514.29" switch \initial - attribute \src "libresoc.v:45512.9-45512.17" + attribute \src "libresoc.v:45514.9-45514.17" case 1'1 case end @@ -79044,14 +79046,14 @@ module \core sync always update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2531 end - attribute \src "libresoc.v:45520.3-45529.6" - process $proc$libresoc.v:45520$2533 + attribute \src "libresoc.v:45522.3-45531.6" + process $proc$libresoc.v:45522$2533 assign { } { } assign { } { } assign $0\fus_src2_i$67[63:0]$2534 $1\fus_src2_i$67[63:0]$2535 - attribute \src "libresoc.v:45521.5-45521.29" + attribute \src "libresoc.v:45523.5-45523.29" switch \initial - attribute \src "libresoc.v:45521.9-45521.17" + attribute \src "libresoc.v:45523.9-45523.17" case 1'1 case end @@ -79067,14 +79069,14 @@ module \core sync always update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2534 end - attribute \src "libresoc.v:45530.3-45538.6" - process $proc$libresoc.v:45530$2536 + attribute \src "libresoc.v:45532.3-45540.6" + process $proc$libresoc.v:45532$2536 assign { } { } assign { } { } assign $0\dp_INT_rb_mul0_5$next[0:0]$2537 $1\dp_INT_rb_mul0_5$next[0:0]$2538 - attribute \src "libresoc.v:45531.5-45531.29" + attribute \src "libresoc.v:45533.5-45533.29" switch \initial - attribute \src "libresoc.v:45531.9-45531.17" + attribute \src "libresoc.v:45533.9-45533.17" case 1'1 case end @@ -79090,14 +79092,14 @@ module \core sync always update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2537 end - attribute \src "libresoc.v:45539.3-45548.6" - process $proc$libresoc.v:45539$2539 + attribute \src "libresoc.v:45541.3-45550.6" + process $proc$libresoc.v:45541$2539 assign { } { } assign { } { } assign $0\fus_src2_i$68[63:0]$2540 $1\fus_src2_i$68[63:0]$2541 - attribute \src "libresoc.v:45540.5-45540.29" + attribute \src "libresoc.v:45542.5-45542.29" switch \initial - attribute \src "libresoc.v:45540.9-45540.17" + attribute \src "libresoc.v:45542.9-45542.17" case 1'1 case end @@ -79113,14 +79115,14 @@ module \core sync always update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2540 end - attribute \src "libresoc.v:45549.3-45557.6" - process $proc$libresoc.v:45549$2542 + attribute \src "libresoc.v:45551.3-45559.6" + process $proc$libresoc.v:45551$2542 assign { } { } assign { } { } assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 - attribute \src "libresoc.v:45550.5-45550.29" + attribute \src "libresoc.v:45552.5-45552.29" switch \initial - attribute \src "libresoc.v:45550.9-45550.17" + attribute \src "libresoc.v:45552.9-45552.17" case 1'1 case end @@ -79136,14 +79138,14 @@ module \core sync always update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 end - attribute \src "libresoc.v:45558.3-45567.6" - process $proc$libresoc.v:45558$2545 + attribute \src "libresoc.v:45560.3-45569.6" + process $proc$libresoc.v:45560$2545 assign { } { } assign { } { } assign $0\fus_src2_i$69[63:0]$2546 $1\fus_src2_i$69[63:0]$2547 - attribute \src "libresoc.v:45559.5-45559.29" + attribute \src "libresoc.v:45561.5-45561.29" switch \initial - attribute \src "libresoc.v:45559.9-45559.17" + attribute \src "libresoc.v:45561.9-45561.17" case 1'1 case end @@ -79159,14 +79161,14 @@ module \core sync always update \fus_src2_i$69 $0\fus_src2_i$69[63:0]$2546 end - attribute \src "libresoc.v:45568.3-45576.6" - process $proc$libresoc.v:45568$2548 + attribute \src "libresoc.v:45570.3-45578.6" + process $proc$libresoc.v:45570$2548 assign { } { } assign { } { } assign $0\dp_INT_rb_ldst0_7$next[0:0]$2549 $1\dp_INT_rb_ldst0_7$next[0:0]$2550 - attribute \src "libresoc.v:45569.5-45569.29" + attribute \src "libresoc.v:45571.5-45571.29" switch \initial - attribute \src "libresoc.v:45569.9-45569.17" + attribute \src "libresoc.v:45571.9-45571.17" case 1'1 case end @@ -79182,14 +79184,14 @@ module \core sync always update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2549 end - attribute \src "libresoc.v:45577.3-45586.6" - process $proc$libresoc.v:45577$2551 + attribute \src "libresoc.v:45579.3-45588.6" + process $proc$libresoc.v:45579$2551 assign { } { } assign { } { } assign $0\fus_src2_i$70[63:0]$2552 $1\fus_src2_i$70[63:0]$2553 - attribute \src "libresoc.v:45578.5-45578.29" + attribute \src "libresoc.v:45580.5-45580.29" switch \initial - attribute \src "libresoc.v:45578.9-45578.17" + attribute \src "libresoc.v:45580.9-45580.17" case 1'1 case end @@ -79205,14 +79207,14 @@ module \core sync always update \fus_src2_i$70 $0\fus_src2_i$70[63:0]$2552 end - attribute \src "libresoc.v:45587.3-45595.6" - process $proc$libresoc.v:45587$2554 + attribute \src "libresoc.v:45589.3-45597.6" + process $proc$libresoc.v:45589$2554 assign { } { } assign { } { } assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 - attribute \src "libresoc.v:45588.5-45588.29" + attribute \src "libresoc.v:45590.5-45590.29" switch \initial - attribute \src "libresoc.v:45588.9-45588.17" + attribute \src "libresoc.v:45590.9-45590.17" case 1'1 case end @@ -79228,14 +79230,14 @@ module \core sync always update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 end - attribute \src "libresoc.v:45596.3-45605.6" - process $proc$libresoc.v:45596$2557 + attribute \src "libresoc.v:45598.3-45607.6" + process $proc$libresoc.v:45598$2557 assign { } { } assign { } { } assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] - attribute \src "libresoc.v:45597.5-45597.29" + attribute \src "libresoc.v:45599.5-45599.29" switch \initial - attribute \src "libresoc.v:45597.9-45597.17" + attribute \src "libresoc.v:45599.9-45599.17" case 1'1 case end @@ -79251,14 +79253,14 @@ module \core sync always update \fus_src3_i $0\fus_src3_i[63:0] end - attribute \src "libresoc.v:45606.3-45614.6" - process $proc$libresoc.v:45606$2558 + attribute \src "libresoc.v:45608.3-45616.6" + process $proc$libresoc.v:45608$2558 assign { } { } assign { } { } assign $0\dp_INT_rc_ldst0_1$next[0:0]$2559 $1\dp_INT_rc_ldst0_1$next[0:0]$2560 - attribute \src "libresoc.v:45607.5-45607.29" + attribute \src "libresoc.v:45609.5-45609.29" switch \initial - attribute \src "libresoc.v:45607.9-45607.17" + attribute \src "libresoc.v:45609.9-45609.17" case 1'1 case end @@ -79274,14 +79276,14 @@ module \core sync always update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2559 end - attribute \src "libresoc.v:45615.3-45624.6" - process $proc$libresoc.v:45615$2561 + attribute \src "libresoc.v:45617.3-45626.6" + process $proc$libresoc.v:45617$2561 assign { } { } assign { } { } assign $0\fus_src3_i$71[63:0]$2562 $1\fus_src3_i$71[63:0]$2563 - attribute \src "libresoc.v:45616.5-45616.29" + attribute \src "libresoc.v:45618.5-45618.29" switch \initial - attribute \src "libresoc.v:45616.9-45616.17" + attribute \src "libresoc.v:45618.9-45618.17" case 1'1 case end @@ -79297,16 +79299,16 @@ module \core sync always update \fus_src3_i$71 $0\fus_src3_i$71[63:0]$2562 end - attribute \src "libresoc.v:45625.3-45651.6" - process $proc$libresoc.v:45625$2564 + attribute \src "libresoc.v:45627.3-45653.6" + process $proc$libresoc.v:45627$2564 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\counter$next[1:0]$2565 $4\counter$next[1:0]$2569 - attribute \src "libresoc.v:45626.5-45626.29" + attribute \src "libresoc.v:45628.5-45628.29" switch \initial - attribute \src "libresoc.v:45626.9-45626.17" + attribute \src "libresoc.v:45628.9-45628.17" case 1'1 case end @@ -79349,14 +79351,14 @@ module \core sync always update \counter$next $0\counter$next[1:0]$2565 end - attribute \src "libresoc.v:45652.3-45660.6" - process $proc$libresoc.v:45652$2570 + attribute \src "libresoc.v:45654.3-45662.6" + process $proc$libresoc.v:45654$2570 assign { } { } assign { } { } assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 - attribute \src "libresoc.v:45653.5-45653.29" + attribute \src "libresoc.v:45655.5-45655.29" switch \initial - attribute \src "libresoc.v:45653.9-45653.17" + attribute \src "libresoc.v:45655.9-45655.17" case 1'1 case end @@ -79372,14 +79374,14 @@ module \core sync always update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 end - attribute \src "libresoc.v:45661.3-45670.6" - process $proc$libresoc.v:45661$2573 + attribute \src "libresoc.v:45663.3-45672.6" + process $proc$libresoc.v:45663$2573 assign { } { } assign { } { } assign $0\fus_src3_i$72[0:0]$2574 $1\fus_src3_i$72[0:0]$2575 - attribute \src "libresoc.v:45662.5-45662.29" + attribute \src "libresoc.v:45664.5-45664.29" switch \initial - attribute \src "libresoc.v:45662.9-45662.17" + attribute \src "libresoc.v:45664.9-45664.17" case 1'1 case end @@ -79395,15 +79397,15 @@ module \core sync always update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2574 end - attribute \src "libresoc.v:45671.3-45761.6" - process $proc$libresoc.v:45671$2576 + attribute \src "libresoc.v:45673.3-45763.6" + process $proc$libresoc.v:45673$2576 assign { } { } assign { } { } assign { } { } assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] - attribute \src "libresoc.v:45672.5-45672.29" + attribute \src "libresoc.v:45674.5-45674.29" switch \initial - attribute \src "libresoc.v:45672.9-45672.17" + attribute \src "libresoc.v:45674.9-45674.17" case 1'1 case end @@ -79541,14 +79543,14 @@ module \core sync always update \corebusy_o $0\corebusy_o[0:0] end - attribute \src "libresoc.v:45762.3-45770.6" - process $proc$libresoc.v:45762$2577 + attribute \src "libresoc.v:45764.3-45772.6" + process $proc$libresoc.v:45764$2577 assign { } { } assign { } { } assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 - attribute \src "libresoc.v:45763.5-45763.29" + attribute \src "libresoc.v:45765.5-45765.29" switch \initial - attribute \src "libresoc.v:45763.9-45763.17" + attribute \src "libresoc.v:45765.9-45765.17" case 1'1 case end @@ -79564,14 +79566,14 @@ module \core sync always update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 end - attribute \src "libresoc.v:45771.3-45780.6" - process $proc$libresoc.v:45771$2580 + attribute \src "libresoc.v:45773.3-45782.6" + process $proc$libresoc.v:45773$2580 assign { } { } assign { } { } assign $0\fus_src3_i$73[0:0]$2581 $1\fus_src3_i$73[0:0]$2582 - attribute \src "libresoc.v:45772.5-45772.29" + attribute \src "libresoc.v:45774.5-45774.29" switch \initial - attribute \src "libresoc.v:45772.9-45772.17" + attribute \src "libresoc.v:45774.9-45774.17" case 1'1 case end @@ -79587,14 +79589,14 @@ module \core sync always update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2581 end - attribute \src "libresoc.v:45781.3-45789.6" - process $proc$libresoc.v:45781$2583 + attribute \src "libresoc.v:45783.3-45791.6" + process $proc$libresoc.v:45783$2583 assign { } { } assign { } { } assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 - attribute \src "libresoc.v:45782.5-45782.29" + attribute \src "libresoc.v:45784.5-45784.29" switch \initial - attribute \src "libresoc.v:45782.9-45782.17" + attribute \src "libresoc.v:45784.9-45784.17" case 1'1 case end @@ -79610,14 +79612,14 @@ module \core sync always update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 end - attribute \src "libresoc.v:45790.3-45799.6" - process $proc$libresoc.v:45790$2586 + attribute \src "libresoc.v:45792.3-45801.6" + process $proc$libresoc.v:45792$2586 assign { } { } assign { } { } assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] - attribute \src "libresoc.v:45791.5-45791.29" + attribute \src "libresoc.v:45793.5-45793.29" switch \initial - attribute \src "libresoc.v:45791.9-45791.17" + attribute \src "libresoc.v:45793.9-45793.17" case 1'1 case end @@ -79633,15 +79635,15 @@ module \core sync always update \fus_src4_i $0\fus_src4_i[0:0] end - attribute \src "libresoc.v:45800.3-45820.6" - process $proc$libresoc.v:45800$2587 + attribute \src "libresoc.v:45802.3-45822.6" + process $proc$libresoc.v:45802$2587 assign { } { } assign { } { } assign { } { } assign $0\core_terminate_o$next[0:0]$2588 $3\core_terminate_o$next[0:0]$2591 - attribute \src "libresoc.v:45801.5-45801.29" + attribute \src "libresoc.v:45803.5-45803.29" switch \initial - attribute \src "libresoc.v:45801.9-45801.17" + attribute \src "libresoc.v:45803.9-45803.17" case 1'1 case end @@ -79675,14 +79677,14 @@ module \core sync always update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2588 end - attribute \src "libresoc.v:45821.3-45829.6" - process $proc$libresoc.v:45821$2592 + attribute \src "libresoc.v:45823.3-45831.6" + process $proc$libresoc.v:45823$2592 assign { } { } assign { } { } assign $0\dp_XER_xer_so_div0_3$next[0:0]$2593 $1\dp_XER_xer_so_div0_3$next[0:0]$2594 - attribute \src "libresoc.v:45822.5-45822.29" + attribute \src "libresoc.v:45824.5-45824.29" switch \initial - attribute \src "libresoc.v:45822.9-45822.17" + attribute \src "libresoc.v:45824.9-45824.17" case 1'1 case end @@ -79698,14 +79700,14 @@ module \core sync always update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2593 end - attribute \src "libresoc.v:45830.3-45839.6" - process $proc$libresoc.v:45830$2595 + attribute \src "libresoc.v:45832.3-45841.6" + process $proc$libresoc.v:45832$2595 assign { } { } assign { } { } assign $0\fus_src3_i$74[0:0]$2596 $1\fus_src3_i$74[0:0]$2597 - attribute \src "libresoc.v:45831.5-45831.29" + attribute \src "libresoc.v:45833.5-45833.29" switch \initial - attribute \src "libresoc.v:45831.9-45831.17" + attribute \src "libresoc.v:45833.9-45833.17" case 1'1 case end @@ -79721,14 +79723,14 @@ module \core sync always update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2596 end - attribute \src "libresoc.v:45840.3-45848.6" - process $proc$libresoc.v:45840$2598 + attribute \src "libresoc.v:45842.3-45850.6" + process $proc$libresoc.v:45842$2598 assign { } { } assign { } { } assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 - attribute \src "libresoc.v:45841.5-45841.29" + attribute \src "libresoc.v:45843.5-45843.29" switch \initial - attribute \src "libresoc.v:45841.9-45841.17" + attribute \src "libresoc.v:45843.9-45843.17" case 1'1 case end @@ -79744,14 +79746,14 @@ module \core sync always update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 end - attribute \src "libresoc.v:45849.3-45858.6" - process $proc$libresoc.v:45849$2601 + attribute \src "libresoc.v:45851.3-45860.6" + process $proc$libresoc.v:45851$2601 assign { } { } assign { } { } assign $0\fus_src3_i$75[0:0]$2602 $1\fus_src3_i$75[0:0]$2603 - attribute \src "libresoc.v:45850.5-45850.29" + attribute \src "libresoc.v:45852.5-45852.29" switch \initial - attribute \src "libresoc.v:45850.9-45850.17" + attribute \src "libresoc.v:45852.9-45852.17" case 1'1 case end @@ -79767,14 +79769,14 @@ module \core sync always update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2602 end - attribute \src "libresoc.v:45859.3-45887.6" - process $proc$libresoc.v:45859$2604 + attribute \src "libresoc.v:45861.3-45889.6" + process $proc$libresoc.v:45861$2604 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45860.5-45860.29" + attribute \src "libresoc.v:45862.5-45862.29" switch \initial - attribute \src "libresoc.v:45860.9-45860.17" + attribute \src "libresoc.v:45862.9-45862.17" case 1'1 case end @@ -79812,14 +79814,14 @@ module \core sync always update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] end - attribute \src "libresoc.v:45888.3-45896.6" - process $proc$libresoc.v:45888$2605 + attribute \src "libresoc.v:45890.3-45898.6" + process $proc$libresoc.v:45890$2605 assign { } { } assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 - attribute \src "libresoc.v:45889.5-45889.29" + attribute \src "libresoc.v:45891.5-45891.29" switch \initial - attribute \src "libresoc.v:45889.9-45889.17" + attribute \src "libresoc.v:45891.9-45891.17" case 1'1 case end @@ -79835,14 +79837,14 @@ module \core sync always update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 end - attribute \src "libresoc.v:45897.3-45906.6" - process $proc$libresoc.v:45897$2608 + attribute \src "libresoc.v:45899.3-45908.6" + process $proc$libresoc.v:45899$2608 assign { } { } assign { } { } assign $0\fus_src4_i$76[0:0]$2609 $1\fus_src4_i$76[0:0]$2610 - attribute \src "libresoc.v:45898.5-45898.29" + attribute \src "libresoc.v:45900.5-45900.29" switch \initial - attribute \src "libresoc.v:45898.9-45898.17" + attribute \src "libresoc.v:45900.9-45900.17" case 1'1 case end @@ -79858,14 +79860,14 @@ module \core sync always update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2609 end - attribute \src "libresoc.v:45907.3-45915.6" - process $proc$libresoc.v:45907$2611 + attribute \src "libresoc.v:45909.3-45917.6" + process $proc$libresoc.v:45909$2611 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 - attribute \src "libresoc.v:45908.5-45908.29" + attribute \src "libresoc.v:45910.5-45910.29" switch \initial - attribute \src "libresoc.v:45908.9-45908.17" + attribute \src "libresoc.v:45910.9-45910.17" case 1'1 case end @@ -79881,14 +79883,14 @@ module \core sync always update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 end - attribute \src "libresoc.v:45916.3-45944.6" - process $proc$libresoc.v:45916$2614 + attribute \src "libresoc.v:45918.3-45946.6" + process $proc$libresoc.v:45918$2614 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__fn_unit[12:0] $1\fus_oper_i_alu_alu0__fn_unit[12:0] - attribute \src "libresoc.v:45917.5-45917.29" + attribute \src "libresoc.v:45919.5-45919.29" switch \initial - attribute \src "libresoc.v:45917.9-45917.17" + attribute \src "libresoc.v:45919.9-45919.17" case 1'1 case end @@ -79926,14 +79928,14 @@ module \core sync always update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[12:0] end - attribute \src "libresoc.v:45945.3-45954.6" - process $proc$libresoc.v:45945$2615 + attribute \src "libresoc.v:45947.3-45956.6" + process $proc$libresoc.v:45947$2615 assign { } { } assign { } { } assign $0\fus_src4_i$77[1:0]$2616 $1\fus_src4_i$77[1:0]$2617 - attribute \src "libresoc.v:45946.5-45946.29" + attribute \src "libresoc.v:45948.5-45948.29" switch \initial - attribute \src "libresoc.v:45946.9-45946.17" + attribute \src "libresoc.v:45948.9-45948.17" case 1'1 case end @@ -79949,14 +79951,14 @@ module \core sync always update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2616 end - attribute \src "libresoc.v:45955.3-45963.6" - process $proc$libresoc.v:45955$2618 + attribute \src "libresoc.v:45957.3-45965.6" + process $proc$libresoc.v:45957$2618 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 - attribute \src "libresoc.v:45956.5-45956.29" + attribute \src "libresoc.v:45958.5-45958.29" switch \initial - attribute \src "libresoc.v:45956.9-45956.17" + attribute \src "libresoc.v:45958.9-45958.17" case 1'1 case end @@ -79972,14 +79974,14 @@ module \core sync always update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 end - attribute \src "libresoc.v:45964.3-45973.6" - process $proc$libresoc.v:45964$2621 + attribute \src "libresoc.v:45966.3-45975.6" + process $proc$libresoc.v:45966$2621 assign { } { } assign { } { } assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] - attribute \src "libresoc.v:45965.5-45965.29" + attribute \src "libresoc.v:45967.5-45967.29" switch \initial - attribute \src "libresoc.v:45965.9-45965.17" + attribute \src "libresoc.v:45967.9-45967.17" case 1'1 case end @@ -79995,14 +79997,14 @@ module \core sync always update \fus_src6_i $0\fus_src6_i[1:0] end - attribute \src "libresoc.v:45974.3-45982.6" - process $proc$libresoc.v:45974$2622 + attribute \src "libresoc.v:45976.3-45984.6" + process $proc$libresoc.v:45976$2622 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 - attribute \src "libresoc.v:45975.5-45975.29" + attribute \src "libresoc.v:45977.5-45977.29" switch \initial - attribute \src "libresoc.v:45975.9-45975.17" + attribute \src "libresoc.v:45977.9-45977.17" case 1'1 case end @@ -80018,17 +80020,17 @@ module \core sync always update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 end - attribute \src "libresoc.v:45983.3-46012.6" - process $proc$libresoc.v:45983$2625 + attribute \src "libresoc.v:45985.3-46014.6" + process $proc$libresoc.v:45985$2625 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:45984.5-45984.29" + attribute \src "libresoc.v:45986.5-45986.29" switch \initial - attribute \src "libresoc.v:45984.9-45984.17" + attribute \src "libresoc.v:45986.9-45986.17" case 1'1 case end @@ -80076,14 +80078,14 @@ module \core update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] end - attribute \src "libresoc.v:46013.3-46022.6" - process $proc$libresoc.v:46013$2626 + attribute \src "libresoc.v:46015.3-46024.6" + process $proc$libresoc.v:46015$2626 assign { } { } assign { } { } assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46014.5-46014.29" + attribute \src "libresoc.v:46016.5-46016.29" switch \initial - attribute \src "libresoc.v:46014.9-46014.17" + attribute \src "libresoc.v:46016.9-46016.17" case 1'1 case end @@ -80099,14 +80101,14 @@ module \core sync always update \fus_src5_i $0\fus_src5_i[1:0] end - attribute \src "libresoc.v:46023.3-46031.6" - process $proc$libresoc.v:46023$2627 + attribute \src "libresoc.v:46025.3-46033.6" + process $proc$libresoc.v:46025$2627 assign { } { } assign { } { } assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 - attribute \src "libresoc.v:46024.5-46024.29" + attribute \src "libresoc.v:46026.5-46026.29" switch \initial - attribute \src "libresoc.v:46024.9-46024.17" + attribute \src "libresoc.v:46026.9-46026.17" case 1'1 case end @@ -80122,14 +80124,14 @@ module \core sync always update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 end - attribute \src "libresoc.v:46032.3-46041.6" - process $proc$libresoc.v:46032$2630 + attribute \src "libresoc.v:46034.3-46043.6" + process $proc$libresoc.v:46034$2630 assign { } { } assign { } { } assign $0\fus_src5_i$78[1:0]$2631 $1\fus_src5_i$78[1:0]$2632 - attribute \src "libresoc.v:46033.5-46033.29" + attribute \src "libresoc.v:46035.5-46035.29" switch \initial - attribute \src "libresoc.v:46033.9-46033.17" + attribute \src "libresoc.v:46035.9-46035.17" case 1'1 case end @@ -80145,14 +80147,14 @@ module \core sync always update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2631 end - attribute \src "libresoc.v:46042.3-46050.6" - process $proc$libresoc.v:46042$2633 + attribute \src "libresoc.v:46044.3-46052.6" + process $proc$libresoc.v:46044$2633 assign { } { } assign { } { } assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 - attribute \src "libresoc.v:46043.5-46043.29" + attribute \src "libresoc.v:46045.5-46045.29" switch \initial - attribute \src "libresoc.v:46043.9-46043.17" + attribute \src "libresoc.v:46045.9-46045.17" case 1'1 case end @@ -80168,14 +80170,14 @@ module \core sync always update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 end - attribute \src "libresoc.v:46051.3-46060.6" - process $proc$libresoc.v:46051$2636 + attribute \src "libresoc.v:46053.3-46062.6" + process $proc$libresoc.v:46053$2636 assign { } { } assign { } { } assign $0\fus_src3_i$79[31:0]$2637 $1\fus_src3_i$79[31:0]$2638 - attribute \src "libresoc.v:46052.5-46052.29" + attribute \src "libresoc.v:46054.5-46054.29" switch \initial - attribute \src "libresoc.v:46052.9-46052.17" + attribute \src "libresoc.v:46054.9-46054.17" case 1'1 case end @@ -80191,17 +80193,17 @@ module \core sync always update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2637 end - attribute \src "libresoc.v:46061.3-46090.6" - process $proc$libresoc.v:46061$2639 + attribute \src "libresoc.v:46063.3-46092.6" + process $proc$libresoc.v:46063$2639 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46062.5-46062.29" + attribute \src "libresoc.v:46064.5-46064.29" switch \initial - attribute \src "libresoc.v:46062.9-46062.17" + attribute \src "libresoc.v:46064.9-46064.17" case 1'1 case end @@ -80249,14 +80251,14 @@ module \core update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] end - attribute \src "libresoc.v:46091.3-46099.6" - process $proc$libresoc.v:46091$2640 + attribute \src "libresoc.v:46093.3-46101.6" + process $proc$libresoc.v:46093$2640 assign { } { } assign { } { } assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 - attribute \src "libresoc.v:46092.5-46092.29" + attribute \src "libresoc.v:46094.5-46094.29" switch \initial - attribute \src "libresoc.v:46092.9-46092.17" + attribute \src "libresoc.v:46094.9-46094.17" case 1'1 case end @@ -80272,14 +80274,14 @@ module \core sync always update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 end - attribute \src "libresoc.v:46100.3-46109.6" - process $proc$libresoc.v:46100$2643 + attribute \src "libresoc.v:46102.3-46111.6" + process $proc$libresoc.v:46102$2643 assign { } { } assign { } { } assign $0\fus_src4_i$80[3:0]$2644 $1\fus_src4_i$80[3:0]$2645 - attribute \src "libresoc.v:46101.5-46101.29" + attribute \src "libresoc.v:46103.5-46103.29" switch \initial - attribute \src "libresoc.v:46101.9-46101.17" + attribute \src "libresoc.v:46103.9-46103.17" case 1'1 case end @@ -80295,14 +80297,14 @@ module \core sync always update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2644 end - attribute \src "libresoc.v:46110.3-46118.6" - process $proc$libresoc.v:46110$2646 + attribute \src "libresoc.v:46112.3-46120.6" + process $proc$libresoc.v:46112$2646 assign { } { } assign { } { } assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 - attribute \src "libresoc.v:46111.5-46111.29" + attribute \src "libresoc.v:46113.5-46113.29" switch \initial - attribute \src "libresoc.v:46111.9-46111.17" + attribute \src "libresoc.v:46113.9-46113.17" case 1'1 case end @@ -80318,14 +80320,14 @@ module \core sync always update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 end - attribute \src "libresoc.v:46119.3-46128.6" - process $proc$libresoc.v:46119$2649 + attribute \src "libresoc.v:46121.3-46130.6" + process $proc$libresoc.v:46121$2649 assign { } { } assign { } { } assign $0\fus_src3_i$83[3:0]$2650 $1\fus_src3_i$83[3:0]$2651 - attribute \src "libresoc.v:46120.5-46120.29" + attribute \src "libresoc.v:46122.5-46122.29" switch \initial - attribute \src "libresoc.v:46120.9-46120.17" + attribute \src "libresoc.v:46122.9-46122.17" case 1'1 case end @@ -80341,14 +80343,14 @@ module \core sync always update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2650 end - attribute \src "libresoc.v:46129.3-46137.6" - process $proc$libresoc.v:46129$2652 + attribute \src "libresoc.v:46131.3-46139.6" + process $proc$libresoc.v:46131$2652 assign { } { } assign { } { } assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 - attribute \src "libresoc.v:46130.5-46130.29" + attribute \src "libresoc.v:46132.5-46132.29" switch \initial - attribute \src "libresoc.v:46130.9-46130.17" + attribute \src "libresoc.v:46132.9-46132.17" case 1'1 case end @@ -80364,14 +80366,14 @@ module \core sync always update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 end - attribute \src "libresoc.v:46138.3-46147.6" - process $proc$libresoc.v:46138$2655 + attribute \src "libresoc.v:46140.3-46149.6" + process $proc$libresoc.v:46140$2655 assign { } { } assign { } { } assign $0\fus_src5_i$84[3:0]$2656 $1\fus_src5_i$84[3:0]$2657 - attribute \src "libresoc.v:46139.5-46139.29" + attribute \src "libresoc.v:46141.5-46141.29" switch \initial - attribute \src "libresoc.v:46139.9-46139.17" + attribute \src "libresoc.v:46141.9-46141.17" case 1'1 case end @@ -80387,17 +80389,17 @@ module \core sync always update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2656 end - attribute \src "libresoc.v:46148.3-46177.6" - process $proc$libresoc.v:46148$2658 + attribute \src "libresoc.v:46150.3-46179.6" + process $proc$libresoc.v:46150$2658 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46149.5-46149.29" + attribute \src "libresoc.v:46151.5-46151.29" switch \initial - attribute \src "libresoc.v:46149.9-46149.17" + attribute \src "libresoc.v:46151.9-46151.17" case 1'1 case end @@ -80445,14 +80447,14 @@ module \core update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] end - attribute \src "libresoc.v:46178.3-46186.6" - process $proc$libresoc.v:46178$2659 + attribute \src "libresoc.v:46180.3-46188.6" + process $proc$libresoc.v:46180$2659 assign { } { } assign { } { } assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 - attribute \src "libresoc.v:46179.5-46179.29" + attribute \src "libresoc.v:46181.5-46181.29" switch \initial - attribute \src "libresoc.v:46179.9-46179.17" + attribute \src "libresoc.v:46181.9-46181.17" case 1'1 case end @@ -80468,14 +80470,14 @@ module \core sync always update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 end - attribute \src "libresoc.v:46187.3-46196.6" - process $proc$libresoc.v:46187$2662 + attribute \src "libresoc.v:46189.3-46198.6" + process $proc$libresoc.v:46189$2662 assign { } { } assign { } { } assign $0\fus_src6_i$85[3:0]$2663 $1\fus_src6_i$85[3:0]$2664 - attribute \src "libresoc.v:46188.5-46188.29" + attribute \src "libresoc.v:46190.5-46190.29" switch \initial - attribute \src "libresoc.v:46188.9-46188.17" + attribute \src "libresoc.v:46190.9-46190.17" case 1'1 case end @@ -80491,14 +80493,14 @@ module \core sync always update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2663 end - attribute \src "libresoc.v:46197.3-46205.6" - process $proc$libresoc.v:46197$2665 + attribute \src "libresoc.v:46199.3-46207.6" + process $proc$libresoc.v:46199$2665 assign { } { } assign { } { } assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 - attribute \src "libresoc.v:46198.5-46198.29" + attribute \src "libresoc.v:46200.5-46200.29" switch \initial - attribute \src "libresoc.v:46198.9-46198.17" + attribute \src "libresoc.v:46200.9-46200.17" case 1'1 case end @@ -80514,14 +80516,14 @@ module \core sync always update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 end - attribute \src "libresoc.v:46206.3-46215.6" - process $proc$libresoc.v:46206$2668 + attribute \src "libresoc.v:46208.3-46217.6" + process $proc$libresoc.v:46208$2668 assign { } { } assign { } { } assign $0\fus_src1_i$86[63:0]$2669 $1\fus_src1_i$86[63:0]$2670 - attribute \src "libresoc.v:46207.5-46207.29" + attribute \src "libresoc.v:46209.5-46209.29" switch \initial - attribute \src "libresoc.v:46207.9-46207.17" + attribute \src "libresoc.v:46209.9-46209.17" case 1'1 case end @@ -80537,14 +80539,14 @@ module \core sync always update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2669 end - attribute \src "libresoc.v:46216.3-46224.6" - process $proc$libresoc.v:46216$2671 + attribute \src "libresoc.v:46218.3-46226.6" + process $proc$libresoc.v:46218$2671 assign { } { } assign { } { } assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 - attribute \src "libresoc.v:46217.5-46217.29" + attribute \src "libresoc.v:46219.5-46219.29" switch \initial - attribute \src "libresoc.v:46217.9-46217.17" + attribute \src "libresoc.v:46219.9-46219.17" case 1'1 case end @@ -80560,14 +80562,14 @@ module \core sync always update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 end - attribute \src "libresoc.v:46225.3-46234.6" - process $proc$libresoc.v:46225$2674 + attribute \src "libresoc.v:46227.3-46236.6" + process $proc$libresoc.v:46227$2674 assign { } { } assign { } { } assign $0\fus_src3_i$87[63:0]$2675 $1\fus_src3_i$87[63:0]$2676 - attribute \src "libresoc.v:46226.5-46226.29" + attribute \src "libresoc.v:46228.5-46228.29" switch \initial - attribute \src "libresoc.v:46226.9-46226.17" + attribute \src "libresoc.v:46228.9-46228.17" case 1'1 case end @@ -80583,14 +80585,14 @@ module \core sync always update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2675 end - attribute \src "libresoc.v:46235.3-46263.6" - process $proc$libresoc.v:46235$2677 + attribute \src "libresoc.v:46237.3-46265.6" + process $proc$libresoc.v:46237$2677 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46236.5-46236.29" + attribute \src "libresoc.v:46238.5-46238.29" switch \initial - attribute \src "libresoc.v:46236.9-46236.17" + attribute \src "libresoc.v:46238.9-46238.17" case 1'1 case end @@ -80628,14 +80630,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] end - attribute \src "libresoc.v:46264.3-46272.6" - process $proc$libresoc.v:46264$2678 + attribute \src "libresoc.v:46266.3-46274.6" + process $proc$libresoc.v:46266$2678 assign { } { } assign { } { } assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 - attribute \src "libresoc.v:46265.5-46265.29" + attribute \src "libresoc.v:46267.5-46267.29" switch \initial - attribute \src "libresoc.v:46265.9-46265.17" + attribute \src "libresoc.v:46267.9-46267.17" case 1'1 case end @@ -80651,14 +80653,14 @@ module \core sync always update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 end - attribute \src "libresoc.v:46273.3-46282.6" - process $proc$libresoc.v:46273$2681 + attribute \src "libresoc.v:46275.3-46284.6" + process $proc$libresoc.v:46275$2681 assign { } { } assign { } { } assign $0\fus_src3_i$88[63:0]$2682 $1\fus_src3_i$88[63:0]$2683 - attribute \src "libresoc.v:46274.5-46274.29" + attribute \src "libresoc.v:46276.5-46276.29" switch \initial - attribute \src "libresoc.v:46274.9-46274.17" + attribute \src "libresoc.v:46276.9-46276.17" case 1'1 case end @@ -80674,14 +80676,14 @@ module \core sync always update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2682 end - attribute \src "libresoc.v:46283.3-46311.6" - process $proc$libresoc.v:46283$2684 + attribute \src "libresoc.v:46285.3-46313.6" + process $proc$libresoc.v:46285$2684 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46284.5-46284.29" + attribute \src "libresoc.v:46286.5-46286.29" switch \initial - attribute \src "libresoc.v:46284.9-46284.17" + attribute \src "libresoc.v:46286.9-46286.17" case 1'1 case end @@ -80719,14 +80721,14 @@ module \core sync always update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] end - attribute \src "libresoc.v:46312.3-46320.6" - process $proc$libresoc.v:46312$2685 + attribute \src "libresoc.v:46314.3-46322.6" + process $proc$libresoc.v:46314$2685 assign { } { } assign { } { } assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 - attribute \src "libresoc.v:46313.5-46313.29" + attribute \src "libresoc.v:46315.5-46315.29" switch \initial - attribute \src "libresoc.v:46313.9-46313.17" + attribute \src "libresoc.v:46315.9-46315.17" case 1'1 case end @@ -80742,14 +80744,14 @@ module \core sync always update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 end - attribute \src "libresoc.v:46321.3-46330.6" - process $proc$libresoc.v:46321$2688 + attribute \src "libresoc.v:46323.3-46332.6" + process $proc$libresoc.v:46323$2688 assign { } { } assign { } { } assign $0\fus_src2_i$89[63:0]$2689 $1\fus_src2_i$89[63:0]$2690 - attribute \src "libresoc.v:46322.5-46322.29" + attribute \src "libresoc.v:46324.5-46324.29" switch \initial - attribute \src "libresoc.v:46322.9-46322.17" + attribute \src "libresoc.v:46324.9-46324.17" case 1'1 case end @@ -80765,14 +80767,14 @@ module \core sync always update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2689 end - attribute \src "libresoc.v:46331.3-46339.6" - process $proc$libresoc.v:46331$2691 + attribute \src "libresoc.v:46333.3-46341.6" + process $proc$libresoc.v:46333$2691 assign { } { } assign { } { } assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 - attribute \src "libresoc.v:46332.5-46332.29" + attribute \src "libresoc.v:46334.5-46334.29" switch \initial - attribute \src "libresoc.v:46332.9-46332.17" + attribute \src "libresoc.v:46334.9-46334.17" case 1'1 case end @@ -80788,14 +80790,14 @@ module \core sync always update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 end - attribute \src "libresoc.v:46340.3-46349.6" - process $proc$libresoc.v:46340$2694 + attribute \src "libresoc.v:46342.3-46351.6" + process $proc$libresoc.v:46342$2694 assign { } { } assign { } { } assign $0\fus_src4_i$90[63:0]$2695 $1\fus_src4_i$90[63:0]$2696 - attribute \src "libresoc.v:46341.5-46341.29" + attribute \src "libresoc.v:46343.5-46343.29" switch \initial - attribute \src "libresoc.v:46341.9-46341.17" + attribute \src "libresoc.v:46343.9-46343.17" case 1'1 case end @@ -80811,14 +80813,14 @@ module \core sync always update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2695 end - attribute \src "libresoc.v:46350.3-46378.6" - process $proc$libresoc.v:46350$2697 + attribute \src "libresoc.v:46352.3-46380.6" + process $proc$libresoc.v:46352$2697 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46351.5-46351.29" + attribute \src "libresoc.v:46353.5-46353.29" switch \initial - attribute \src "libresoc.v:46351.9-46351.17" + attribute \src "libresoc.v:46353.9-46353.17" case 1'1 case end @@ -80856,14 +80858,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] end - attribute \src "libresoc.v:46379.3-46387.6" - process $proc$libresoc.v:46379$2698 + attribute \src "libresoc.v:46381.3-46389.6" + process $proc$libresoc.v:46381$2698 assign { } { } assign { } { } assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 - attribute \src "libresoc.v:46380.5-46380.29" + attribute \src "libresoc.v:46382.5-46382.29" switch \initial - attribute \src "libresoc.v:46380.9-46380.17" + attribute \src "libresoc.v:46382.9-46382.17" case 1'1 case end @@ -80879,14 +80881,14 @@ module \core sync always update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 end - attribute \src "libresoc.v:46388.3-46397.6" - process $proc$libresoc.v:46388$2701 + attribute \src "libresoc.v:46390.3-46399.6" + process $proc$libresoc.v:46390$2701 assign { } { } assign { } { } assign $0\fus_src2_i$91[63:0]$2702 $1\fus_src2_i$91[63:0]$2703 - attribute \src "libresoc.v:46389.5-46389.29" + attribute \src "libresoc.v:46391.5-46391.29" switch \initial - attribute \src "libresoc.v:46389.9-46389.17" + attribute \src "libresoc.v:46391.9-46391.17" case 1'1 case end @@ -80902,14 +80904,14 @@ module \core sync always update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2702 end - attribute \src "libresoc.v:46398.3-46426.6" - process $proc$libresoc.v:46398$2704 + attribute \src "libresoc.v:46400.3-46428.6" + process $proc$libresoc.v:46400$2704 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46399.5-46399.29" + attribute \src "libresoc.v:46401.5-46401.29" switch \initial - attribute \src "libresoc.v:46399.9-46399.17" + attribute \src "libresoc.v:46401.9-46401.17" case 1'1 case end @@ -80947,14 +80949,14 @@ module \core sync always update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] end - attribute \src "libresoc.v:46427.3-46435.6" - process $proc$libresoc.v:46427$2705 + attribute \src "libresoc.v:46429.3-46437.6" + process $proc$libresoc.v:46429$2705 assign { } { } assign { } { } assign $0\wr_pick_dly$next[0:0]$2706 $1\wr_pick_dly$next[0:0]$2707 - attribute \src "libresoc.v:46428.5-46428.29" + attribute \src "libresoc.v:46430.5-46430.29" switch \initial - attribute \src "libresoc.v:46428.9-46428.17" + attribute \src "libresoc.v:46430.9-46430.17" case 1'1 case end @@ -80970,14 +80972,14 @@ module \core sync always update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2706 end - attribute \src "libresoc.v:46436.3-46464.6" - process $proc$libresoc.v:46436$2708 + attribute \src "libresoc.v:46438.3-46466.6" + process $proc$libresoc.v:46438$2708 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46437.5-46437.29" + attribute \src "libresoc.v:46439.5-46439.29" switch \initial - attribute \src "libresoc.v:46437.9-46437.17" + attribute \src "libresoc.v:46439.9-46439.17" case 1'1 case end @@ -81015,14 +81017,14 @@ module \core sync always update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] end - attribute \src "libresoc.v:46465.3-46473.6" - process $proc$libresoc.v:46465$2709 + attribute \src "libresoc.v:46467.3-46475.6" + process $proc$libresoc.v:46467$2709 assign { } { } assign { } { } assign $0\wr_pick_dly$986$next[0:0]$2710 $1\wr_pick_dly$986$next[0:0]$2711 - attribute \src "libresoc.v:46466.5-46466.29" + attribute \src "libresoc.v:46468.5-46468.29" switch \initial - attribute \src "libresoc.v:46466.9-46466.17" + attribute \src "libresoc.v:46468.9-46468.17" case 1'1 case end @@ -81038,14 +81040,14 @@ module \core sync always update \wr_pick_dly$986$next $0\wr_pick_dly$986$next[0:0]$2710 end - attribute \src "libresoc.v:46474.3-46482.6" - process $proc$libresoc.v:46474$2712 + attribute \src "libresoc.v:46476.3-46484.6" + process $proc$libresoc.v:46476$2712 assign { } { } assign { } { } assign $0\wr_pick_dly$1005$next[0:0]$2713 $1\wr_pick_dly$1005$next[0:0]$2714 - attribute \src "libresoc.v:46475.5-46475.29" + attribute \src "libresoc.v:46477.5-46477.29" switch \initial - attribute \src "libresoc.v:46475.9-46475.17" + attribute \src "libresoc.v:46477.9-46477.17" case 1'1 case end @@ -81061,14 +81063,14 @@ module \core sync always update \wr_pick_dly$1005$next $0\wr_pick_dly$1005$next[0:0]$2713 end - attribute \src "libresoc.v:46483.3-46511.6" - process $proc$libresoc.v:46483$2715 + attribute \src "libresoc.v:46485.3-46513.6" + process $proc$libresoc.v:46485$2715 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46484.5-46484.29" + attribute \src "libresoc.v:46486.5-46486.29" switch \initial - attribute \src "libresoc.v:46484.9-46484.17" + attribute \src "libresoc.v:46486.9-46486.17" case 1'1 case end @@ -81106,14 +81108,14 @@ module \core sync always update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] end - attribute \src "libresoc.v:46512.3-46520.6" - process $proc$libresoc.v:46512$2716 + attribute \src "libresoc.v:46514.3-46522.6" + process $proc$libresoc.v:46514$2716 assign { } { } assign { } { } assign $0\wr_pick_dly$1026$next[0:0]$2717 $1\wr_pick_dly$1026$next[0:0]$2718 - attribute \src "libresoc.v:46513.5-46513.29" + attribute \src "libresoc.v:46515.5-46515.29" switch \initial - attribute \src "libresoc.v:46513.9-46513.17" + attribute \src "libresoc.v:46515.9-46515.17" case 1'1 case end @@ -81129,14 +81131,14 @@ module \core sync always update \wr_pick_dly$1026$next $0\wr_pick_dly$1026$next[0:0]$2717 end - attribute \src "libresoc.v:46521.3-46549.6" - process $proc$libresoc.v:46521$2719 + attribute \src "libresoc.v:46523.3-46551.6" + process $proc$libresoc.v:46523$2719 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46522.5-46522.29" + attribute \src "libresoc.v:46524.5-46524.29" switch \initial - attribute \src "libresoc.v:46522.9-46522.17" + attribute \src "libresoc.v:46524.9-46524.17" case 1'1 case end @@ -81174,14 +81176,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] end - attribute \src "libresoc.v:46550.3-46558.6" - process $proc$libresoc.v:46550$2720 + attribute \src "libresoc.v:46552.3-46560.6" + process $proc$libresoc.v:46552$2720 assign { } { } assign { } { } assign $0\wr_pick_dly$1044$next[0:0]$2721 $1\wr_pick_dly$1044$next[0:0]$2722 - attribute \src "libresoc.v:46551.5-46551.29" + attribute \src "libresoc.v:46553.5-46553.29" switch \initial - attribute \src "libresoc.v:46551.9-46551.17" + attribute \src "libresoc.v:46553.9-46553.17" case 1'1 case end @@ -81197,14 +81199,14 @@ module \core sync always update \wr_pick_dly$1044$next $0\wr_pick_dly$1044$next[0:0]$2721 end - attribute \src "libresoc.v:46559.3-46567.6" - process $proc$libresoc.v:46559$2723 + attribute \src "libresoc.v:46561.3-46569.6" + process $proc$libresoc.v:46561$2723 assign { } { } assign { } { } assign $0\wr_pick_dly$1066$next[0:0]$2724 $1\wr_pick_dly$1066$next[0:0]$2725 - attribute \src "libresoc.v:46560.5-46560.29" + attribute \src "libresoc.v:46562.5-46562.29" switch \initial - attribute \src "libresoc.v:46560.9-46560.17" + attribute \src "libresoc.v:46562.9-46562.17" case 1'1 case end @@ -81220,14 +81222,14 @@ module \core sync always update \wr_pick_dly$1066$next $0\wr_pick_dly$1066$next[0:0]$2724 end - attribute \src "libresoc.v:46568.3-46596.6" - process $proc$libresoc.v:46568$2726 + attribute \src "libresoc.v:46570.3-46598.6" + process $proc$libresoc.v:46570$2726 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46569.5-46569.29" + attribute \src "libresoc.v:46571.5-46571.29" switch \initial - attribute \src "libresoc.v:46569.9-46569.17" + attribute \src "libresoc.v:46571.9-46571.17" case 1'1 case end @@ -81265,14 +81267,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] end - attribute \src "libresoc.v:46597.3-46605.6" - process $proc$libresoc.v:46597$2727 + attribute \src "libresoc.v:46599.3-46607.6" + process $proc$libresoc.v:46599$2727 assign { } { } assign { } { } assign $0\wr_pick_dly$1086$next[0:0]$2728 $1\wr_pick_dly$1086$next[0:0]$2729 - attribute \src "libresoc.v:46598.5-46598.29" + attribute \src "libresoc.v:46600.5-46600.29" switch \initial - attribute \src "libresoc.v:46598.9-46598.17" + attribute \src "libresoc.v:46600.9-46600.17" case 1'1 case end @@ -81288,14 +81290,14 @@ module \core sync always update \wr_pick_dly$1086$next $0\wr_pick_dly$1086$next[0:0]$2728 end - attribute \src "libresoc.v:46606.3-46634.6" - process $proc$libresoc.v:46606$2730 + attribute \src "libresoc.v:46608.3-46636.6" + process $proc$libresoc.v:46608$2730 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46607.5-46607.29" + attribute \src "libresoc.v:46609.5-46609.29" switch \initial - attribute \src "libresoc.v:46607.9-46607.17" + attribute \src "libresoc.v:46609.9-46609.17" case 1'1 case end @@ -81333,14 +81335,14 @@ module \core sync always update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] end - attribute \src "libresoc.v:46635.3-46643.6" - process $proc$libresoc.v:46635$2731 + attribute \src "libresoc.v:46637.3-46645.6" + process $proc$libresoc.v:46637$2731 assign { } { } assign { } { } assign $0\wr_pick_dly$1106$next[0:0]$2732 $1\wr_pick_dly$1106$next[0:0]$2733 - attribute \src "libresoc.v:46636.5-46636.29" + attribute \src "libresoc.v:46638.5-46638.29" switch \initial - attribute \src "libresoc.v:46636.9-46636.17" + attribute \src "libresoc.v:46638.9-46638.17" case 1'1 case end @@ -81356,14 +81358,14 @@ module \core sync always update \wr_pick_dly$1106$next $0\wr_pick_dly$1106$next[0:0]$2732 end - attribute \src "libresoc.v:46644.3-46652.6" - process $proc$libresoc.v:46644$2734 + attribute \src "libresoc.v:46646.3-46654.6" + process $proc$libresoc.v:46646$2734 assign { } { } assign { } { } assign $0\wr_pick_dly$1125$next[0:0]$2735 $1\wr_pick_dly$1125$next[0:0]$2736 - attribute \src "libresoc.v:46645.5-46645.29" + attribute \src "libresoc.v:46647.5-46647.29" switch \initial - attribute \src "libresoc.v:46645.9-46645.17" + attribute \src "libresoc.v:46647.9-46647.17" case 1'1 case end @@ -81379,14 +81381,14 @@ module \core sync always update \wr_pick_dly$1125$next $0\wr_pick_dly$1125$next[0:0]$2735 end - attribute \src "libresoc.v:46653.3-46681.6" - process $proc$libresoc.v:46653$2737 + attribute \src "libresoc.v:46655.3-46683.6" + process $proc$libresoc.v:46655$2737 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46654.5-46654.29" + attribute \src "libresoc.v:46656.5-46656.29" switch \initial - attribute \src "libresoc.v:46654.9-46654.17" + attribute \src "libresoc.v:46656.9-46656.17" case 1'1 case end @@ -81424,14 +81426,14 @@ module \core sync always update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] end - attribute \src "libresoc.v:46682.3-46690.6" - process $proc$libresoc.v:46682$2738 + attribute \src "libresoc.v:46684.3-46692.6" + process $proc$libresoc.v:46684$2738 assign { } { } assign { } { } assign $0\wr_pick_dly$1143$next[0:0]$2739 $1\wr_pick_dly$1143$next[0:0]$2740 - attribute \src "libresoc.v:46683.5-46683.29" + attribute \src "libresoc.v:46685.5-46685.29" switch \initial - attribute \src "libresoc.v:46683.9-46683.17" + attribute \src "libresoc.v:46685.9-46685.17" case 1'1 case end @@ -81447,14 +81449,14 @@ module \core sync always update \wr_pick_dly$1143$next $0\wr_pick_dly$1143$next[0:0]$2739 end - attribute \src "libresoc.v:46691.3-46719.6" - process $proc$libresoc.v:46691$2741 + attribute \src "libresoc.v:46693.3-46721.6" + process $proc$libresoc.v:46693$2741 assign { } { } assign { } { } assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46692.5-46692.29" + attribute \src "libresoc.v:46694.5-46694.29" switch \initial - attribute \src "libresoc.v:46692.9-46692.17" + attribute \src "libresoc.v:46694.9-46694.17" case 1'1 case end @@ -81492,14 +81494,14 @@ module \core sync always update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] end - attribute \src "libresoc.v:46720.3-46728.6" - process $proc$libresoc.v:46720$2742 + attribute \src "libresoc.v:46722.3-46730.6" + process $proc$libresoc.v:46722$2742 assign { } { } assign { } { } assign $0\wr_pick_dly$1217$next[0:0]$2743 $1\wr_pick_dly$1217$next[0:0]$2744 - attribute \src "libresoc.v:46721.5-46721.29" + attribute \src "libresoc.v:46723.5-46723.29" switch \initial - attribute \src "libresoc.v:46721.9-46721.17" + attribute \src "libresoc.v:46723.9-46723.17" case 1'1 case end @@ -81515,14 +81517,14 @@ module \core sync always update \wr_pick_dly$1217$next $0\wr_pick_dly$1217$next[0:0]$2743 end - attribute \src "libresoc.v:46729.3-46757.6" - process $proc$libresoc.v:46729$2745 + attribute \src "libresoc.v:46731.3-46759.6" + process $proc$libresoc.v:46731$2745 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46730.5-46730.29" + attribute \src "libresoc.v:46732.5-46732.29" switch \initial - attribute \src "libresoc.v:46730.9-46730.17" + attribute \src "libresoc.v:46732.9-46732.17" case 1'1 case end @@ -81560,14 +81562,14 @@ module \core sync always update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] end - attribute \src "libresoc.v:46758.3-46766.6" - process $proc$libresoc.v:46758$2746 + attribute \src "libresoc.v:46760.3-46768.6" + process $proc$libresoc.v:46760$2746 assign { } { } assign { } { } assign $0\wr_pick_dly$1245$next[0:0]$2747 $1\wr_pick_dly$1245$next[0:0]$2748 - attribute \src "libresoc.v:46759.5-46759.29" + attribute \src "libresoc.v:46761.5-46761.29" switch \initial - attribute \src "libresoc.v:46759.9-46759.17" + attribute \src "libresoc.v:46761.9-46761.17" case 1'1 case end @@ -81583,14 +81585,14 @@ module \core sync always update \wr_pick_dly$1245$next $0\wr_pick_dly$1245$next[0:0]$2747 end - attribute \src "libresoc.v:46767.3-46795.6" - process $proc$libresoc.v:46767$2749 + attribute \src "libresoc.v:46769.3-46797.6" + process $proc$libresoc.v:46769$2749 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:46768.5-46768.29" + attribute \src "libresoc.v:46770.5-46770.29" switch \initial - attribute \src "libresoc.v:46768.9-46768.17" + attribute \src "libresoc.v:46770.9-46770.17" case 1'1 case end @@ -81628,14 +81630,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] end - attribute \src "libresoc.v:46796.3-46804.6" - process $proc$libresoc.v:46796$2750 + attribute \src "libresoc.v:46798.3-46806.6" + process $proc$libresoc.v:46798$2750 assign { } { } assign { } { } assign $0\wr_pick_dly$1265$next[0:0]$2751 $1\wr_pick_dly$1265$next[0:0]$2752 - attribute \src "libresoc.v:46797.5-46797.29" + attribute \src "libresoc.v:46799.5-46799.29" switch \initial - attribute \src "libresoc.v:46797.9-46797.17" + attribute \src "libresoc.v:46799.9-46799.17" case 1'1 case end @@ -81651,14 +81653,14 @@ module \core sync always update \wr_pick_dly$1265$next $0\wr_pick_dly$1265$next[0:0]$2751 end - attribute \src "libresoc.v:46805.3-46813.6" - process $proc$libresoc.v:46805$2753 + attribute \src "libresoc.v:46807.3-46815.6" + process $proc$libresoc.v:46807$2753 assign { } { } assign { } { } assign $0\wr_pick_dly$1285$next[0:0]$2754 $1\wr_pick_dly$1285$next[0:0]$2755 - attribute \src "libresoc.v:46806.5-46806.29" + attribute \src "libresoc.v:46808.5-46808.29" switch \initial - attribute \src "libresoc.v:46806.9-46806.17" + attribute \src "libresoc.v:46808.9-46808.17" case 1'1 case end @@ -81674,14 +81676,14 @@ module \core sync always update \wr_pick_dly$1285$next $0\wr_pick_dly$1285$next[0:0]$2754 end - attribute \src "libresoc.v:46814.3-46842.6" - process $proc$libresoc.v:46814$2756 + attribute \src "libresoc.v:46816.3-46844.6" + process $proc$libresoc.v:46816$2756 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__fn_unit[12:0] $1\fus_oper_i_alu_cr0__fn_unit[12:0] - attribute \src "libresoc.v:46815.5-46815.29" + attribute \src "libresoc.v:46817.5-46817.29" switch \initial - attribute \src "libresoc.v:46815.9-46815.17" + attribute \src "libresoc.v:46817.9-46817.17" case 1'1 case end @@ -81719,14 +81721,14 @@ module \core sync always update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[12:0] end - attribute \src "libresoc.v:46843.3-46851.6" - process $proc$libresoc.v:46843$2757 + attribute \src "libresoc.v:46845.3-46853.6" + process $proc$libresoc.v:46845$2757 assign { } { } assign { } { } assign $0\wr_pick_dly$1305$next[0:0]$2758 $1\wr_pick_dly$1305$next[0:0]$2759 - attribute \src "libresoc.v:46844.5-46844.29" + attribute \src "libresoc.v:46846.5-46846.29" switch \initial - attribute \src "libresoc.v:46844.9-46844.17" + attribute \src "libresoc.v:46846.9-46846.17" case 1'1 case end @@ -81742,14 +81744,14 @@ module \core sync always update \wr_pick_dly$1305$next $0\wr_pick_dly$1305$next[0:0]$2758 end - attribute \src "libresoc.v:46852.3-46860.6" - process $proc$libresoc.v:46852$2760 + attribute \src "libresoc.v:46854.3-46862.6" + process $proc$libresoc.v:46854$2760 assign { } { } assign { } { } assign $0\wr_pick_dly$1325$next[0:0]$2761 $1\wr_pick_dly$1325$next[0:0]$2762 - attribute \src "libresoc.v:46853.5-46853.29" + attribute \src "libresoc.v:46855.5-46855.29" switch \initial - attribute \src "libresoc.v:46853.9-46853.17" + attribute \src "libresoc.v:46855.9-46855.17" case 1'1 case end @@ -81765,14 +81767,14 @@ module \core sync always update \wr_pick_dly$1325$next $0\wr_pick_dly$1325$next[0:0]$2761 end - attribute \src "libresoc.v:46861.3-46889.6" - process $proc$libresoc.v:46861$2763 + attribute \src "libresoc.v:46863.3-46891.6" + process $proc$libresoc.v:46863$2763 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46862.5-46862.29" + attribute \src "libresoc.v:46864.5-46864.29" switch \initial - attribute \src "libresoc.v:46862.9-46862.17" + attribute \src "libresoc.v:46864.9-46864.17" case 1'1 case end @@ -81810,14 +81812,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] end - attribute \src "libresoc.v:46890.3-46898.6" - process $proc$libresoc.v:46890$2764 + attribute \src "libresoc.v:46892.3-46900.6" + process $proc$libresoc.v:46892$2764 assign { } { } assign { } { } assign $0\wr_pick_dly$1345$next[0:0]$2765 $1\wr_pick_dly$1345$next[0:0]$2766 - attribute \src "libresoc.v:46891.5-46891.29" + attribute \src "libresoc.v:46893.5-46893.29" switch \initial - attribute \src "libresoc.v:46891.9-46891.17" + attribute \src "libresoc.v:46893.9-46893.17" case 1'1 case end @@ -81833,14 +81835,14 @@ module \core sync always update \wr_pick_dly$1345$next $0\wr_pick_dly$1345$next[0:0]$2765 end - attribute \src "libresoc.v:46899.3-46927.6" - process $proc$libresoc.v:46899$2767 + attribute \src "libresoc.v:46901.3-46929.6" + process $proc$libresoc.v:46901$2767 assign { } { } assign { } { } assign $0\fus_cu_issue_i$13[0:0]$2768 $1\fus_cu_issue_i$13[0:0]$2769 - attribute \src "libresoc.v:46900.5-46900.29" + attribute \src "libresoc.v:46902.5-46902.29" switch \initial - attribute \src "libresoc.v:46900.9-46900.17" + attribute \src "libresoc.v:46902.9-46902.17" case 1'1 case end @@ -81878,14 +81880,14 @@ module \core sync always update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2768 end - attribute \src "libresoc.v:46928.3-46936.6" - process $proc$libresoc.v:46928$2772 + attribute \src "libresoc.v:46930.3-46938.6" + process $proc$libresoc.v:46930$2772 assign { } { } assign { } { } assign $0\wr_pick_dly$1392$next[0:0]$2773 $1\wr_pick_dly$1392$next[0:0]$2774 - attribute \src "libresoc.v:46929.5-46929.29" + attribute \src "libresoc.v:46931.5-46931.29" switch \initial - attribute \src "libresoc.v:46929.9-46929.17" + attribute \src "libresoc.v:46931.9-46931.17" case 1'1 case end @@ -81901,14 +81903,14 @@ module \core sync always update \wr_pick_dly$1392$next $0\wr_pick_dly$1392$next[0:0]$2773 end - attribute \src "libresoc.v:46937.3-46965.6" - process $proc$libresoc.v:46937$2775 + attribute \src "libresoc.v:46939.3-46967.6" + process $proc$libresoc.v:46939$2775 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$15[5:0]$2776 $1\fus_cu_rdmaskn_i$15[5:0]$2777 - attribute \src "libresoc.v:46938.5-46938.29" + attribute \src "libresoc.v:46940.5-46940.29" switch \initial - attribute \src "libresoc.v:46938.9-46938.17" + attribute \src "libresoc.v:46940.9-46940.17" case 1'1 case end @@ -81946,14 +81948,14 @@ module \core sync always update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2776 end - attribute \src "libresoc.v:46966.3-46974.6" - process $proc$libresoc.v:46966$2780 + attribute \src "libresoc.v:46968.3-46976.6" + process $proc$libresoc.v:46968$2780 assign { } { } assign { } { } assign $0\wr_pick_dly$1408$next[0:0]$2781 $1\wr_pick_dly$1408$next[0:0]$2782 - attribute \src "libresoc.v:46967.5-46967.29" + attribute \src "libresoc.v:46969.5-46969.29" switch \initial - attribute \src "libresoc.v:46967.9-46967.17" + attribute \src "libresoc.v:46969.9-46969.17" case 1'1 case end @@ -81969,14 +81971,14 @@ module \core sync always update \wr_pick_dly$1408$next $0\wr_pick_dly$1408$next[0:0]$2781 end - attribute \src "libresoc.v:46975.3-46983.6" - process $proc$libresoc.v:46975$2783 + attribute \src "libresoc.v:46977.3-46985.6" + process $proc$libresoc.v:46977$2783 assign { } { } assign { } { } assign $0\wr_pick_dly$1424$next[0:0]$2784 $1\wr_pick_dly$1424$next[0:0]$2785 - attribute \src "libresoc.v:46976.5-46976.29" + attribute \src "libresoc.v:46978.5-46978.29" switch \initial - attribute \src "libresoc.v:46976.9-46976.17" + attribute \src "libresoc.v:46978.9-46978.17" case 1'1 case end @@ -81992,14 +81994,14 @@ module \core sync always update \wr_pick_dly$1424$next $0\wr_pick_dly$1424$next[0:0]$2784 end - attribute \src "libresoc.v:46984.3-47012.6" - process $proc$libresoc.v:46984$2786 + attribute \src "libresoc.v:46986.3-47014.6" + process $proc$libresoc.v:46986$2786 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46985.5-46985.29" + attribute \src "libresoc.v:46987.5-46987.29" switch \initial - attribute \src "libresoc.v:46985.9-46985.17" + attribute \src "libresoc.v:46987.9-46987.17" case 1'1 case end @@ -82037,14 +82039,14 @@ module \core sync always update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] end - attribute \src "libresoc.v:47013.3-47021.6" - process $proc$libresoc.v:47013$2787 + attribute \src "libresoc.v:47015.3-47023.6" + process $proc$libresoc.v:47015$2787 assign { } { } assign { } { } assign $0\wr_pick_dly$1458$next[0:0]$2788 $1\wr_pick_dly$1458$next[0:0]$2789 - attribute \src "libresoc.v:47014.5-47014.29" + attribute \src "libresoc.v:47016.5-47016.29" switch \initial - attribute \src "libresoc.v:47014.9-47014.17" + attribute \src "libresoc.v:47016.9-47016.17" case 1'1 case end @@ -82060,14 +82062,14 @@ module \core sync always update \wr_pick_dly$1458$next $0\wr_pick_dly$1458$next[0:0]$2788 end - attribute \src "libresoc.v:47022.3-47050.6" - process $proc$libresoc.v:47022$2790 + attribute \src "libresoc.v:47024.3-47052.6" + process $proc$libresoc.v:47024$2790 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47023.5-47023.29" + attribute \src "libresoc.v:47025.5-47025.29" switch \initial - attribute \src "libresoc.v:47023.9-47023.17" + attribute \src "libresoc.v:47025.9-47025.17" case 1'1 case end @@ -82105,14 +82107,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] end - attribute \src "libresoc.v:47051.3-47059.6" - process $proc$libresoc.v:47051$2791 + attribute \src "libresoc.v:47053.3-47061.6" + process $proc$libresoc.v:47053$2791 assign { } { } assign { } { } assign $0\wr_pick_dly$1474$next[0:0]$2792 $1\wr_pick_dly$1474$next[0:0]$2793 - attribute \src "libresoc.v:47052.5-47052.29" + attribute \src "libresoc.v:47054.5-47054.29" switch \initial - attribute \src "libresoc.v:47052.9-47052.17" + attribute \src "libresoc.v:47054.9-47054.17" case 1'1 case end @@ -82128,14 +82130,14 @@ module \core sync always update \wr_pick_dly$1474$next $0\wr_pick_dly$1474$next[0:0]$2792 end - attribute \src "libresoc.v:47060.3-47068.6" - process $proc$libresoc.v:47060$2794 + attribute \src "libresoc.v:47062.3-47070.6" + process $proc$libresoc.v:47062$2794 assign { } { } assign { } { } assign $0\wr_pick_dly$1490$next[0:0]$2795 $1\wr_pick_dly$1490$next[0:0]$2796 - attribute \src "libresoc.v:47061.5-47061.29" + attribute \src "libresoc.v:47063.5-47063.29" switch \initial - attribute \src "libresoc.v:47061.9-47061.17" + attribute \src "libresoc.v:47063.9-47063.17" case 1'1 case end @@ -82151,14 +82153,14 @@ module \core sync always update \wr_pick_dly$1490$next $0\wr_pick_dly$1490$next[0:0]$2795 end - attribute \src "libresoc.v:47069.3-47097.6" - process $proc$libresoc.v:47069$2797 + attribute \src "libresoc.v:47071.3-47099.6" + process $proc$libresoc.v:47071$2797 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__fn_unit[12:0] $1\fus_oper_i_alu_branch0__fn_unit[12:0] - attribute \src "libresoc.v:47070.5-47070.29" + attribute \src "libresoc.v:47072.5-47072.29" switch \initial - attribute \src "libresoc.v:47070.9-47070.17" + attribute \src "libresoc.v:47072.9-47072.17" case 1'1 case end @@ -82196,14 +82198,14 @@ module \core sync always update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[12:0] end - attribute \src "libresoc.v:47098.3-47106.6" - process $proc$libresoc.v:47098$2798 + attribute \src "libresoc.v:47100.3-47108.6" + process $proc$libresoc.v:47100$2798 assign { } { } assign { } { } assign $0\wr_pick_dly$1506$next[0:0]$2799 $1\wr_pick_dly$1506$next[0:0]$2800 - attribute \src "libresoc.v:47099.5-47099.29" + attribute \src "libresoc.v:47101.5-47101.29" switch \initial - attribute \src "libresoc.v:47099.9-47099.17" + attribute \src "libresoc.v:47101.9-47101.17" case 1'1 case end @@ -82219,14 +82221,14 @@ module \core sync always update \wr_pick_dly$1506$next $0\wr_pick_dly$1506$next[0:0]$2799 end - attribute \src "libresoc.v:47107.3-47135.6" - process $proc$libresoc.v:47107$2801 + attribute \src "libresoc.v:47109.3-47137.6" + process $proc$libresoc.v:47109$2801 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47108.5-47108.29" + attribute \src "libresoc.v:47110.5-47110.29" switch \initial - attribute \src "libresoc.v:47108.9-47108.17" + attribute \src "libresoc.v:47110.9-47110.17" case 1'1 case end @@ -82264,14 +82266,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] end - attribute \src "libresoc.v:47136.3-47144.6" - process $proc$libresoc.v:47136$2802 + attribute \src "libresoc.v:47138.3-47146.6" + process $proc$libresoc.v:47138$2802 assign { } { } assign { } { } assign $0\wr_pick_dly$1542$next[0:0]$2803 $1\wr_pick_dly$1542$next[0:0]$2804 - attribute \src "libresoc.v:47137.5-47137.29" + attribute \src "libresoc.v:47139.5-47139.29" switch \initial - attribute \src "libresoc.v:47137.9-47137.17" + attribute \src "libresoc.v:47139.9-47139.17" case 1'1 case end @@ -82287,14 +82289,14 @@ module \core sync always update \wr_pick_dly$1542$next $0\wr_pick_dly$1542$next[0:0]$2803 end - attribute \src "libresoc.v:47145.3-47153.6" - process $proc$libresoc.v:47145$2805 + attribute \src "libresoc.v:47147.3-47155.6" + process $proc$libresoc.v:47147$2805 assign { } { } assign { } { } assign $0\wr_pick_dly$1558$next[0:0]$2806 $1\wr_pick_dly$1558$next[0:0]$2807 - attribute \src "libresoc.v:47146.5-47146.29" + attribute \src "libresoc.v:47148.5-47148.29" switch \initial - attribute \src "libresoc.v:47146.9-47146.17" + attribute \src "libresoc.v:47148.9-47148.17" case 1'1 case end @@ -82310,17 +82312,17 @@ module \core sync always update \wr_pick_dly$1558$next $0\wr_pick_dly$1558$next[0:0]$2806 end - attribute \src "libresoc.v:47154.3-47183.6" - process $proc$libresoc.v:47154$2808 + attribute \src "libresoc.v:47156.3-47185.6" + process $proc$libresoc.v:47156$2808 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47155.5-47155.29" + attribute \src "libresoc.v:47157.5-47157.29" switch \initial - attribute \src "libresoc.v:47155.9-47155.17" + attribute \src "libresoc.v:47157.9-47157.17" case 1'1 case end @@ -82368,14 +82370,14 @@ module \core update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] end - attribute \src "libresoc.v:47184.3-47192.6" - process $proc$libresoc.v:47184$2809 + attribute \src "libresoc.v:47186.3-47194.6" + process $proc$libresoc.v:47186$2809 assign { } { } assign { } { } assign $0\wr_pick_dly$1574$next[0:0]$2810 $1\wr_pick_dly$1574$next[0:0]$2811 - attribute \src "libresoc.v:47185.5-47185.29" + attribute \src "libresoc.v:47187.5-47187.29" switch \initial - attribute \src "libresoc.v:47185.9-47185.17" + attribute \src "libresoc.v:47187.9-47187.17" case 1'1 case end @@ -82391,14 +82393,14 @@ module \core sync always update \wr_pick_dly$1574$next $0\wr_pick_dly$1574$next[0:0]$2810 end - attribute \src "libresoc.v:47193.3-47201.6" - process $proc$libresoc.v:47193$2812 + attribute \src "libresoc.v:47195.3-47203.6" + process $proc$libresoc.v:47195$2812 assign { } { } assign { } { } assign $0\wr_pick_dly$1590$next[0:0]$2813 $1\wr_pick_dly$1590$next[0:0]$2814 - attribute \src "libresoc.v:47194.5-47194.29" + attribute \src "libresoc.v:47196.5-47196.29" switch \initial - attribute \src "libresoc.v:47194.9-47194.17" + attribute \src "libresoc.v:47196.9-47196.17" case 1'1 case end @@ -82414,14 +82416,14 @@ module \core sync always update \wr_pick_dly$1590$next $0\wr_pick_dly$1590$next[0:0]$2813 end - attribute \src "libresoc.v:47202.3-47210.6" - process $proc$libresoc.v:47202$2815 + attribute \src "libresoc.v:47204.3-47212.6" + process $proc$libresoc.v:47204$2815 assign { } { } assign { } { } assign $0\wr_pick_dly$1632$next[0:0]$2816 $1\wr_pick_dly$1632$next[0:0]$2817 - attribute \src "libresoc.v:47203.5-47203.29" + attribute \src "libresoc.v:47205.5-47205.29" switch \initial - attribute \src "libresoc.v:47203.9-47203.17" + attribute \src "libresoc.v:47205.9-47205.17" case 1'1 case end @@ -82437,14 +82439,14 @@ module \core sync always update \wr_pick_dly$1632$next $0\wr_pick_dly$1632$next[0:0]$2816 end - attribute \src "libresoc.v:47211.3-47239.6" - process $proc$libresoc.v:47211$2818 + attribute \src "libresoc.v:47213.3-47241.6" + process $proc$libresoc.v:47213$2818 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47212.5-47212.29" + attribute \src "libresoc.v:47214.5-47214.29" switch \initial - attribute \src "libresoc.v:47212.9-47212.17" + attribute \src "libresoc.v:47214.9-47214.17" case 1'1 case end @@ -82482,14 +82484,14 @@ module \core sync always update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] end - attribute \src "libresoc.v:47240.3-47248.6" - process $proc$libresoc.v:47240$2819 + attribute \src "libresoc.v:47242.3-47250.6" + process $proc$libresoc.v:47242$2819 assign { } { } assign { } { } assign $0\wr_pick_dly$1651$next[0:0]$2820 $1\wr_pick_dly$1651$next[0:0]$2821 - attribute \src "libresoc.v:47241.5-47241.29" + attribute \src "libresoc.v:47243.5-47243.29" switch \initial - attribute \src "libresoc.v:47241.9-47241.17" + attribute \src "libresoc.v:47243.9-47243.17" case 1'1 case end @@ -82505,14 +82507,14 @@ module \core sync always update \wr_pick_dly$1651$next $0\wr_pick_dly$1651$next[0:0]$2820 end - attribute \src "libresoc.v:47249.3-47277.6" - process $proc$libresoc.v:47249$2822 + attribute \src "libresoc.v:47251.3-47279.6" + process $proc$libresoc.v:47251$2822 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47250.5-47250.29" + attribute \src "libresoc.v:47252.5-47252.29" switch \initial - attribute \src "libresoc.v:47250.9-47250.17" + attribute \src "libresoc.v:47252.9-47252.17" case 1'1 case end @@ -82550,14 +82552,14 @@ module \core sync always update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] end - attribute \src "libresoc.v:47278.3-47286.6" - process $proc$libresoc.v:47278$2823 + attribute \src "libresoc.v:47280.3-47288.6" + process $proc$libresoc.v:47280$2823 assign { } { } assign { } { } assign $0\wr_pick_dly$1667$next[0:0]$2824 $1\wr_pick_dly$1667$next[0:0]$2825 - attribute \src "libresoc.v:47279.5-47279.29" + attribute \src "libresoc.v:47281.5-47281.29" switch \initial - attribute \src "libresoc.v:47279.9-47279.17" + attribute \src "libresoc.v:47281.9-47281.17" case 1'1 case end @@ -82573,14 +82575,14 @@ module \core sync always update \wr_pick_dly$1667$next $0\wr_pick_dly$1667$next[0:0]$2824 end - attribute \src "libresoc.v:47287.3-47295.6" - process $proc$libresoc.v:47287$2826 + attribute \src "libresoc.v:47289.3-47297.6" + process $proc$libresoc.v:47289$2826 assign { } { } assign { } { } assign $0\wr_pick_dly$1683$next[0:0]$2827 $1\wr_pick_dly$1683$next[0:0]$2828 - attribute \src "libresoc.v:47288.5-47288.29" + attribute \src "libresoc.v:47290.5-47290.29" switch \initial - attribute \src "libresoc.v:47288.9-47288.17" + attribute \src "libresoc.v:47290.9-47290.17" case 1'1 case end @@ -82596,14 +82598,14 @@ module \core sync always update \wr_pick_dly$1683$next $0\wr_pick_dly$1683$next[0:0]$2827 end - attribute \src "libresoc.v:47296.3-47324.6" - process $proc$libresoc.v:47296$2829 + attribute \src "libresoc.v:47298.3-47326.6" + process $proc$libresoc.v:47298$2829 assign { } { } assign { } { } assign $0\fus_cu_issue_i$16[0:0]$2830 $1\fus_cu_issue_i$16[0:0]$2831 - attribute \src "libresoc.v:47297.5-47297.29" + attribute \src "libresoc.v:47299.5-47299.29" switch \initial - attribute \src "libresoc.v:47297.9-47297.17" + attribute \src "libresoc.v:47299.9-47299.17" case 1'1 case end @@ -82641,14 +82643,14 @@ module \core sync always update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2830 end - attribute \src "libresoc.v:47325.3-47333.6" - process $proc$libresoc.v:47325$2834 + attribute \src "libresoc.v:47327.3-47335.6" + process $proc$libresoc.v:47327$2834 assign { } { } assign { } { } assign $0\wr_pick_dly$1699$next[0:0]$2835 $1\wr_pick_dly$1699$next[0:0]$2836 - attribute \src "libresoc.v:47326.5-47326.29" + attribute \src "libresoc.v:47328.5-47328.29" switch \initial - attribute \src "libresoc.v:47326.9-47326.17" + attribute \src "libresoc.v:47328.9-47328.17" case 1'1 case end @@ -82664,14 +82666,14 @@ module \core sync always update \wr_pick_dly$1699$next $0\wr_pick_dly$1699$next[0:0]$2835 end - attribute \src "libresoc.v:47334.3-47362.6" - process $proc$libresoc.v:47334$2837 + attribute \src "libresoc.v:47336.3-47364.6" + process $proc$libresoc.v:47336$2837 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$18[2:0]$2838 $1\fus_cu_rdmaskn_i$18[2:0]$2839 - attribute \src "libresoc.v:47335.5-47335.29" + attribute \src "libresoc.v:47337.5-47337.29" switch \initial - attribute \src "libresoc.v:47335.9-47335.17" + attribute \src "libresoc.v:47337.9-47337.17" case 1'1 case end @@ -82709,14 +82711,14 @@ module \core sync always update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2838 end - attribute \src "libresoc.v:47363.3-47371.6" - process $proc$libresoc.v:47363$2842 + attribute \src "libresoc.v:47365.3-47373.6" + process $proc$libresoc.v:47365$2842 assign { } { } assign { } { } assign $0\wr_pick_dly$1743$next[0:0]$2843 $1\wr_pick_dly$1743$next[0:0]$2844 - attribute \src "libresoc.v:47364.5-47364.29" + attribute \src "libresoc.v:47366.5-47366.29" switch \initial - attribute \src "libresoc.v:47364.9-47364.17" + attribute \src "libresoc.v:47366.9-47366.17" case 1'1 case end @@ -82732,14 +82734,14 @@ module \core sync always update \wr_pick_dly$1743$next $0\wr_pick_dly$1743$next[0:0]$2843 end - attribute \src "libresoc.v:47372.3-47400.6" - process $proc$libresoc.v:47372$2845 + attribute \src "libresoc.v:47374.3-47402.6" + process $proc$libresoc.v:47374$2845 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47373.5-47373.29" + attribute \src "libresoc.v:47375.5-47375.29" switch \initial - attribute \src "libresoc.v:47373.9-47373.17" + attribute \src "libresoc.v:47375.9-47375.17" case 1'1 case end @@ -82777,14 +82779,14 @@ module \core sync always update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] end - attribute \src "libresoc.v:47401.3-47409.6" - process $proc$libresoc.v:47401$2846 + attribute \src "libresoc.v:47403.3-47411.6" + process $proc$libresoc.v:47403$2846 assign { } { } assign { } { } assign $0\wr_pick_dly$1759$next[0:0]$2847 $1\wr_pick_dly$1759$next[0:0]$2848 - attribute \src "libresoc.v:47402.5-47402.29" + attribute \src "libresoc.v:47404.5-47404.29" switch \initial - attribute \src "libresoc.v:47402.9-47402.17" + attribute \src "libresoc.v:47404.9-47404.17" case 1'1 case end @@ -82800,14 +82802,14 @@ module \core sync always update \wr_pick_dly$1759$next $0\wr_pick_dly$1759$next[0:0]$2847 end - attribute \src "libresoc.v:47410.3-47418.6" - process $proc$libresoc.v:47410$2849 + attribute \src "libresoc.v:47412.3-47420.6" + process $proc$libresoc.v:47412$2849 assign { } { } assign { } { } assign $0\wr_pick_dly$1783$next[0:0]$2850 $1\wr_pick_dly$1783$next[0:0]$2851 - attribute \src "libresoc.v:47411.5-47411.29" + attribute \src "libresoc.v:47413.5-47413.29" switch \initial - attribute \src "libresoc.v:47411.9-47411.17" + attribute \src "libresoc.v:47413.9-47413.17" case 1'1 case end @@ -82823,14 +82825,14 @@ module \core sync always update \wr_pick_dly$1783$next $0\wr_pick_dly$1783$next[0:0]$2850 end - attribute \src "libresoc.v:47419.3-47447.6" - process $proc$libresoc.v:47419$2852 + attribute \src "libresoc.v:47421.3-47449.6" + process $proc$libresoc.v:47421$2852 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__fn_unit[12:0] $1\fus_oper_i_alu_trap0__fn_unit[12:0] - attribute \src "libresoc.v:47420.5-47420.29" + attribute \src "libresoc.v:47422.5-47422.29" switch \initial - attribute \src "libresoc.v:47420.9-47420.17" + attribute \src "libresoc.v:47422.9-47422.17" case 1'1 case end @@ -82868,14 +82870,14 @@ module \core sync always update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[12:0] end - attribute \src "libresoc.v:47448.3-47456.6" - process $proc$libresoc.v:47448$2853 + attribute \src "libresoc.v:47450.3-47458.6" + process $proc$libresoc.v:47450$2853 assign { } { } assign { } { } assign $0\wr_pick_dly$1803$next[0:0]$2854 $1\wr_pick_dly$1803$next[0:0]$2855 - attribute \src "libresoc.v:47449.5-47449.29" + attribute \src "libresoc.v:47451.5-47451.29" switch \initial - attribute \src "libresoc.v:47449.9-47449.17" + attribute \src "libresoc.v:47451.9-47451.17" case 1'1 case end @@ -82891,14 +82893,14 @@ module \core sync always update \wr_pick_dly$1803$next $0\wr_pick_dly$1803$next[0:0]$2854 end - attribute \src "libresoc.v:47457.3-47485.6" - process $proc$libresoc.v:47457$2856 + attribute \src "libresoc.v:47459.3-47487.6" + process $proc$libresoc.v:47459$2856 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47458.5-47458.29" + attribute \src "libresoc.v:47460.5-47460.29" switch \initial - attribute \src "libresoc.v:47458.9-47458.17" + attribute \src "libresoc.v:47460.9-47460.17" case 1'1 case end @@ -82936,14 +82938,14 @@ module \core sync always update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] end - attribute \src "libresoc.v:47486.3-47514.6" - process $proc$libresoc.v:47486$2857 + attribute \src "libresoc.v:47488.3-47516.6" + process $proc$libresoc.v:47488$2857 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47487.5-47487.29" + attribute \src "libresoc.v:47489.5-47489.29" switch \initial - attribute \src "libresoc.v:47487.9-47487.17" + attribute \src "libresoc.v:47489.9-47489.17" case 1'1 case end @@ -82981,14 +82983,14 @@ module \core sync always update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] end - attribute \src "libresoc.v:47515.3-47543.6" - process $proc$libresoc.v:47515$2858 + attribute \src "libresoc.v:47517.3-47545.6" + process $proc$libresoc.v:47517$2858 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47516.5-47516.29" + attribute \src "libresoc.v:47518.5-47518.29" switch \initial - attribute \src "libresoc.v:47516.9-47516.17" + attribute \src "libresoc.v:47518.9-47518.17" case 1'1 case end @@ -83026,14 +83028,14 @@ module \core sync always update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] end - attribute \src "libresoc.v:47544.3-47572.6" - process $proc$libresoc.v:47544$2859 + attribute \src "libresoc.v:47546.3-47574.6" + process $proc$libresoc.v:47546$2859 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47545.5-47545.29" + attribute \src "libresoc.v:47547.5-47547.29" switch \initial - attribute \src "libresoc.v:47545.9-47545.17" + attribute \src "libresoc.v:47547.9-47547.17" case 1'1 case end @@ -83071,14 +83073,14 @@ module \core sync always update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] end - attribute \src "libresoc.v:47573.3-47601.6" - process $proc$libresoc.v:47573$2860 + attribute \src "libresoc.v:47575.3-47603.6" + process $proc$libresoc.v:47575$2860 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:47574.5-47574.29" + attribute \src "libresoc.v:47576.5-47576.29" switch \initial - attribute \src "libresoc.v:47574.9-47574.17" + attribute \src "libresoc.v:47576.9-47576.17" case 1'1 case end @@ -83116,14 +83118,14 @@ module \core sync always update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] end - attribute \src "libresoc.v:47602.3-47630.6" - process $proc$libresoc.v:47602$2861 + attribute \src "libresoc.v:47604.3-47632.6" + process $proc$libresoc.v:47604$2861 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47603.5-47603.29" + attribute \src "libresoc.v:47605.5-47605.29" switch \initial - attribute \src "libresoc.v:47603.9-47603.17" + attribute \src "libresoc.v:47605.9-47605.17" case 1'1 case end @@ -83161,14 +83163,14 @@ module \core sync always update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] end - attribute \src "libresoc.v:47631.3-47659.6" - process $proc$libresoc.v:47631$2862 + attribute \src "libresoc.v:47633.3-47661.6" + process $proc$libresoc.v:47633$2862 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47632.5-47632.29" + attribute \src "libresoc.v:47634.5-47634.29" switch \initial - attribute \src "libresoc.v:47632.9-47632.17" + attribute \src "libresoc.v:47634.9-47634.17" case 1'1 case end @@ -83206,14 +83208,14 @@ module \core sync always update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] end - attribute \src "libresoc.v:47660.3-47688.6" - process $proc$libresoc.v:47660$2863 + attribute \src "libresoc.v:47662.3-47690.6" + process $proc$libresoc.v:47662$2863 assign { } { } assign { } { } assign $0\fus_cu_issue_i$19[0:0]$2864 $1\fus_cu_issue_i$19[0:0]$2865 - attribute \src "libresoc.v:47661.5-47661.29" + attribute \src "libresoc.v:47663.5-47663.29" switch \initial - attribute \src "libresoc.v:47661.9-47661.17" + attribute \src "libresoc.v:47663.9-47663.17" case 1'1 case end @@ -83251,14 +83253,14 @@ module \core sync always update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2864 end - attribute \src "libresoc.v:47689.3-47717.6" - process $proc$libresoc.v:47689$2868 + attribute \src "libresoc.v:47691.3-47719.6" + process $proc$libresoc.v:47691$2868 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$21[3:0]$2869 $1\fus_cu_rdmaskn_i$21[3:0]$2870 - attribute \src "libresoc.v:47690.5-47690.29" + attribute \src "libresoc.v:47692.5-47692.29" switch \initial - attribute \src "libresoc.v:47690.9-47690.17" + attribute \src "libresoc.v:47692.9-47692.17" case 1'1 case end @@ -83296,14 +83298,14 @@ module \core sync always update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2869 end - attribute \src "libresoc.v:47718.3-47746.6" - process $proc$libresoc.v:47718$2873 + attribute \src "libresoc.v:47720.3-47748.6" + process $proc$libresoc.v:47720$2873 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47719.5-47719.29" + attribute \src "libresoc.v:47721.5-47721.29" switch \initial - attribute \src "libresoc.v:47719.9-47719.17" + attribute \src "libresoc.v:47721.9-47721.17" case 1'1 case end @@ -83341,14 +83343,14 @@ module \core sync always update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] end - attribute \src "libresoc.v:47747.3-47775.6" - process $proc$libresoc.v:47747$2874 + attribute \src "libresoc.v:47749.3-47777.6" + process $proc$libresoc.v:47749$2874 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__fn_unit[12:0] $1\fus_oper_i_alu_logical0__fn_unit[12:0] - attribute \src "libresoc.v:47748.5-47748.29" + attribute \src "libresoc.v:47750.5-47750.29" switch \initial - attribute \src "libresoc.v:47748.9-47748.17" + attribute \src "libresoc.v:47750.9-47750.17" case 1'1 case end @@ -83386,17 +83388,17 @@ module \core sync always update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[12:0] end - attribute \src "libresoc.v:47776.3-47805.6" - process $proc$libresoc.v:47776$2875 + attribute \src "libresoc.v:47778.3-47807.6" + process $proc$libresoc.v:47778$2875 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47777.5-47777.29" + attribute \src "libresoc.v:47779.5-47779.29" switch \initial - attribute \src "libresoc.v:47777.9-47777.17" + attribute \src "libresoc.v:47779.9-47779.17" case 1'1 case end @@ -83444,17 +83446,17 @@ module \core update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] end - attribute \src "libresoc.v:47806.3-47835.6" - process $proc$libresoc.v:47806$2876 + attribute \src "libresoc.v:47808.3-47837.6" + process $proc$libresoc.v:47808$2876 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47807.5-47807.29" + attribute \src "libresoc.v:47809.5-47809.29" switch \initial - attribute \src "libresoc.v:47807.9-47807.17" + attribute \src "libresoc.v:47809.9-47809.17" case 1'1 case end @@ -83502,17 +83504,17 @@ module \core update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] end - attribute \src "libresoc.v:47836.3-47865.6" - process $proc$libresoc.v:47836$2877 + attribute \src "libresoc.v:47838.3-47867.6" + process $proc$libresoc.v:47838$2877 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47837.5-47837.29" + attribute \src "libresoc.v:47839.5-47839.29" switch \initial - attribute \src "libresoc.v:47837.9-47837.17" + attribute \src "libresoc.v:47839.9-47839.17" case 1'1 case end @@ -83560,14 +83562,14 @@ module \core update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] end - attribute \src "libresoc.v:47866.3-47894.6" - process $proc$libresoc.v:47866$2878 + attribute \src "libresoc.v:47868.3-47896.6" + process $proc$libresoc.v:47868$2878 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47867.5-47867.29" + attribute \src "libresoc.v:47869.5-47869.29" switch \initial - attribute \src "libresoc.v:47867.9-47867.17" + attribute \src "libresoc.v:47869.9-47869.17" case 1'1 case end @@ -83605,14 +83607,14 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] end - attribute \src "libresoc.v:47895.3-47923.6" - process $proc$libresoc.v:47895$2879 + attribute \src "libresoc.v:47897.3-47925.6" + process $proc$libresoc.v:47897$2879 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:47896.5-47896.29" + attribute \src "libresoc.v:47898.5-47898.29" switch \initial - attribute \src "libresoc.v:47896.9-47896.17" + attribute \src "libresoc.v:47898.9-47898.17" case 1'1 case end @@ -83650,14 +83652,14 @@ module \core sync always update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] end - attribute \src "libresoc.v:47924.3-47952.6" - process $proc$libresoc.v:47924$2880 + attribute \src "libresoc.v:47926.3-47954.6" + process $proc$libresoc.v:47926$2880 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47925.5-47925.29" + attribute \src "libresoc.v:47927.5-47927.29" switch \initial - attribute \src "libresoc.v:47925.9-47925.17" + attribute \src "libresoc.v:47927.9-47927.17" case 1'1 case end @@ -83695,14 +83697,14 @@ module \core sync always update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] end - attribute \src "libresoc.v:47953.3-47981.6" - process $proc$libresoc.v:47953$2881 + attribute \src "libresoc.v:47955.3-47983.6" + process $proc$libresoc.v:47955$2881 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47954.5-47954.29" + attribute \src "libresoc.v:47956.5-47956.29" switch \initial - attribute \src "libresoc.v:47954.9-47954.17" + attribute \src "libresoc.v:47956.9-47956.17" case 1'1 case end @@ -83740,14 +83742,14 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] end - attribute \src "libresoc.v:47982.3-48010.6" - process $proc$libresoc.v:47982$2882 + attribute \src "libresoc.v:47984.3-48012.6" + process $proc$libresoc.v:47984$2882 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47983.5-47983.29" + attribute \src "libresoc.v:47985.5-47985.29" switch \initial - attribute \src "libresoc.v:47983.9-47983.17" + attribute \src "libresoc.v:47985.9-47985.17" case 1'1 case end @@ -83785,14 +83787,14 @@ module \core sync always update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] end - attribute \src "libresoc.v:48011.3-48039.6" - process $proc$libresoc.v:48011$2883 + attribute \src "libresoc.v:48013.3-48041.6" + process $proc$libresoc.v:48013$2883 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48012.5-48012.29" + attribute \src "libresoc.v:48014.5-48014.29" switch \initial - attribute \src "libresoc.v:48012.9-48012.17" + attribute \src "libresoc.v:48014.9-48014.17" case 1'1 case end @@ -83830,14 +83832,14 @@ module \core sync always update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] end - attribute \src "libresoc.v:48040.3-48068.6" - process $proc$libresoc.v:48040$2884 + attribute \src "libresoc.v:48042.3-48070.6" + process $proc$libresoc.v:48042$2884 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:48041.5-48041.29" + attribute \src "libresoc.v:48043.5-48043.29" switch \initial - attribute \src "libresoc.v:48041.9-48041.17" + attribute \src "libresoc.v:48043.9-48043.17" case 1'1 case end @@ -83875,14 +83877,14 @@ module \core sync always update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] end - attribute \src "libresoc.v:48069.3-48097.6" - process $proc$libresoc.v:48069$2885 + attribute \src "libresoc.v:48071.3-48099.6" + process $proc$libresoc.v:48071$2885 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48070.5-48070.29" + attribute \src "libresoc.v:48072.5-48072.29" switch \initial - attribute \src "libresoc.v:48070.9-48070.17" + attribute \src "libresoc.v:48072.9-48072.17" case 1'1 case end @@ -83920,14 +83922,14 @@ module \core sync always update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] end - attribute \src "libresoc.v:48098.3-48126.6" - process $proc$libresoc.v:48098$2886 + attribute \src "libresoc.v:48100.3-48128.6" + process $proc$libresoc.v:48100$2886 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48099.5-48099.29" + attribute \src "libresoc.v:48101.5-48101.29" switch \initial - attribute \src "libresoc.v:48099.9-48099.17" + attribute \src "libresoc.v:48101.9-48101.17" case 1'1 case end @@ -83965,14 +83967,14 @@ module \core sync always update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] end - attribute \src "libresoc.v:48127.3-48155.6" - process $proc$libresoc.v:48127$2887 + attribute \src "libresoc.v:48129.3-48157.6" + process $proc$libresoc.v:48129$2887 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48128.5-48128.29" + attribute \src "libresoc.v:48130.5-48130.29" switch \initial - attribute \src "libresoc.v:48128.9-48128.17" + attribute \src "libresoc.v:48130.9-48130.17" case 1'1 case end @@ -84010,14 +84012,14 @@ module \core sync always update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] end - attribute \src "libresoc.v:48156.3-48184.6" - process $proc$libresoc.v:48156$2888 + attribute \src "libresoc.v:48158.3-48186.6" + process $proc$libresoc.v:48158$2888 assign { } { } assign { } { } assign $0\fus_cu_issue_i$22[0:0]$2889 $1\fus_cu_issue_i$22[0:0]$2890 - attribute \src "libresoc.v:48157.5-48157.29" + attribute \src "libresoc.v:48159.5-48159.29" switch \initial - attribute \src "libresoc.v:48157.9-48157.17" + attribute \src "libresoc.v:48159.9-48159.17" case 1'1 case end @@ -84055,14 +84057,14 @@ module \core sync always update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2889 end - attribute \src "libresoc.v:48185.3-48213.6" - process $proc$libresoc.v:48185$2893 + attribute \src "libresoc.v:48187.3-48215.6" + process $proc$libresoc.v:48187$2893 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$24[2:0]$2894 $1\fus_cu_rdmaskn_i$24[2:0]$2895 - attribute \src "libresoc.v:48186.5-48186.29" + attribute \src "libresoc.v:48188.5-48188.29" switch \initial - attribute \src "libresoc.v:48186.9-48186.17" + attribute \src "libresoc.v:48188.9-48188.17" case 1'1 case end @@ -84100,14 +84102,14 @@ module \core sync always update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2894 end - attribute \src "libresoc.v:48214.3-48242.6" - process $proc$libresoc.v:48214$2898 + attribute \src "libresoc.v:48216.3-48244.6" + process $proc$libresoc.v:48216$2898 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:48215.5-48215.29" + attribute \src "libresoc.v:48217.5-48217.29" switch \initial - attribute \src "libresoc.v:48215.9-48215.17" + attribute \src "libresoc.v:48217.9-48217.17" case 1'1 case end @@ -84145,14 +84147,14 @@ module \core sync always update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] end - attribute \src "libresoc.v:48243.3-48271.6" - process $proc$libresoc.v:48243$2899 + attribute \src "libresoc.v:48245.3-48273.6" + process $proc$libresoc.v:48245$2899 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__fn_unit[12:0] $1\fus_oper_i_alu_spr0__fn_unit[12:0] - attribute \src "libresoc.v:48244.5-48244.29" + attribute \src "libresoc.v:48246.5-48246.29" switch \initial - attribute \src "libresoc.v:48244.9-48244.17" + attribute \src "libresoc.v:48246.9-48246.17" case 1'1 case end @@ -84190,731 +84192,731 @@ module \core sync always update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[12:0] end - connect \$1000 $and$libresoc.v:41809$1506_Y - connect \$1003 $and$libresoc.v:41810$1507_Y - connect \$1007 $not$libresoc.v:41811$1508_Y - connect \$1009 $and$libresoc.v:41812$1509_Y - connect \$1016 $and$libresoc.v:41813$1510_Y - connect \$1019 $ternary$libresoc.v:41814$1511_Y - connect \$1021 $and$libresoc.v:41815$1512_Y - connect \$1024 $and$libresoc.v:41816$1513_Y - connect \$1028 $not$libresoc.v:41817$1514_Y - connect \$1030 $and$libresoc.v:41818$1515_Y - connect \$1034 $and$libresoc.v:41819$1516_Y - connect \$1037 $ternary$libresoc.v:41820$1517_Y - connect \$1039 $and$libresoc.v:41821$1518_Y - connect \$1042 $and$libresoc.v:41822$1519_Y - connect \$1046 $not$libresoc.v:41823$1520_Y - connect \$1048 $and$libresoc.v:41824$1521_Y - connect \$1056 $and$libresoc.v:41825$1522_Y - connect \$1059 $ternary$libresoc.v:41826$1523_Y - connect \$1061 $and$libresoc.v:41827$1524_Y - connect \$1064 $and$libresoc.v:41828$1525_Y - connect \$1068 $not$libresoc.v:41829$1526_Y - connect \$1070 $and$libresoc.v:41830$1527_Y - connect \$1076 $and$libresoc.v:41831$1528_Y - connect \$1079 $ternary$libresoc.v:41832$1529_Y - connect \$1081 $and$libresoc.v:41833$1530_Y - connect \$1084 $and$libresoc.v:41834$1531_Y - connect \$1088 $not$libresoc.v:41835$1532_Y - connect \$1090 $and$libresoc.v:41836$1533_Y - connect \$1096 $and$libresoc.v:41837$1534_Y - connect \$1099 $ternary$libresoc.v:41838$1535_Y - connect \$1101 $and$libresoc.v:41839$1536_Y - connect \$1104 $and$libresoc.v:41840$1537_Y - connect \$1108 $not$libresoc.v:41841$1538_Y - connect \$1110 $and$libresoc.v:41842$1539_Y - connect \$1115 $and$libresoc.v:41843$1540_Y - connect \$1118 $ternary$libresoc.v:41844$1541_Y - connect \$1120 $and$libresoc.v:41845$1542_Y - connect \$1123 $and$libresoc.v:41846$1543_Y - connect \$1127 $not$libresoc.v:41847$1544_Y - connect \$1129 $and$libresoc.v:41848$1545_Y - connect \$1133 $and$libresoc.v:41849$1546_Y - connect \$1136 $ternary$libresoc.v:41850$1547_Y - connect \$1138 $and$libresoc.v:41851$1548_Y - connect \$1141 $and$libresoc.v:41852$1549_Y - connect \$1144 $not$libresoc.v:41853$1550_Y - connect \$1146 $and$libresoc.v:41854$1551_Y - connect \$1149 $and$libresoc.v:41855$1552_Y - connect \$1152 $ternary$libresoc.v:41856$1553_Y - connect \$1155 $or$libresoc.v:41857$1554_Y - connect \$1157 $or$libresoc.v:41858$1555_Y - connect \$1159 $or$libresoc.v:41859$1556_Y - connect \$1161 $or$libresoc.v:41860$1557_Y - connect \$1163 $or$libresoc.v:41861$1558_Y - connect \$1165 $or$libresoc.v:41862$1559_Y - connect \$1167 $or$libresoc.v:41863$1560_Y - connect \$1169 $or$libresoc.v:41864$1561_Y - connect \$1171 $or$libresoc.v:41865$1562_Y - connect \$1174 $or$libresoc.v:41866$1563_Y - connect \$1176 $or$libresoc.v:41867$1564_Y - connect \$1178 $or$libresoc.v:41868$1565_Y - connect \$1180 $or$libresoc.v:41869$1566_Y - connect \$1182 $or$libresoc.v:41870$1567_Y - connect \$1184 $or$libresoc.v:41871$1568_Y - connect \$1186 $or$libresoc.v:41872$1569_Y - connect \$1188 $or$libresoc.v:41873$1570_Y - connect \$1190 $or$libresoc.v:41874$1571_Y - connect \$1192 $or$libresoc.v:41875$1572_Y - connect \$1194 $or$libresoc.v:41876$1573_Y - connect \$1196 $or$libresoc.v:41877$1574_Y - connect \$1198 $or$libresoc.v:41878$1575_Y - connect \$1200 $or$libresoc.v:41879$1576_Y - connect \$1202 $or$libresoc.v:41880$1577_Y - connect \$1204 $or$libresoc.v:41881$1578_Y - connect \$1206 $or$libresoc.v:41882$1579_Y - connect \$1208 $or$libresoc.v:41883$1580_Y - connect \$1210 $and$libresoc.v:41884$1581_Y - connect \$1212 $and$libresoc.v:41885$1582_Y - connect \$1215 $and$libresoc.v:41886$1583_Y - connect \$1218 $not$libresoc.v:41887$1584_Y - connect \$1220 $and$libresoc.v:41888$1585_Y - connect \$1223 $and$libresoc.v:41889$1586_Y - connect \$1226 $ternary$libresoc.v:41890$1587_Y - connect \$1228 $and$libresoc.v:41891$1588_Y - connect \$1230 $and$libresoc.v:41892$1589_Y - connect \$1232 $and$libresoc.v:41893$1590_Y - connect \$1234 $and$libresoc.v:41894$1591_Y - connect \$1236 $and$libresoc.v:41895$1592_Y - connect \$1238 $and$libresoc.v:41896$1593_Y - connect \$1240 $and$libresoc.v:41897$1594_Y - connect \$1243 $and$libresoc.v:41898$1595_Y - connect \$1246 $not$libresoc.v:41899$1596_Y - connect \$1248 $and$libresoc.v:41900$1597_Y - connect \$1251 $and$libresoc.v:41901$1598_Y - connect \$1254 $sub$libresoc.v:41902$1599_Y - connect \$1256 $sshl$libresoc.v:41903$1600_Y - connect \$1258 $ternary$libresoc.v:41904$1601_Y - connect \$1260 $and$libresoc.v:41905$1602_Y - connect \$1263 $and$libresoc.v:41906$1603_Y - connect \$1266 $not$libresoc.v:41907$1604_Y - connect \$1268 $and$libresoc.v:41908$1605_Y - connect \$1271 $and$libresoc.v:41909$1606_Y - connect \$1274 $sub$libresoc.v:41910$1607_Y - connect \$1276 $sshl$libresoc.v:41911$1608_Y - connect \$1278 $ternary$libresoc.v:41912$1609_Y - connect \$1280 $and$libresoc.v:41913$1610_Y - connect \$1283 $and$libresoc.v:41914$1611_Y - connect \$1286 $not$libresoc.v:41915$1612_Y - connect \$1288 $and$libresoc.v:41916$1613_Y - connect \$1291 $and$libresoc.v:41917$1614_Y - connect \$1294 $sub$libresoc.v:41918$1615_Y - connect \$1296 $sshl$libresoc.v:41919$1616_Y - connect \$1298 $ternary$libresoc.v:41920$1617_Y - connect \$1300 $and$libresoc.v:41921$1618_Y - connect \$1303 $and$libresoc.v:41922$1619_Y - connect \$1306 $not$libresoc.v:41923$1620_Y - connect \$1308 $and$libresoc.v:41924$1621_Y - connect \$1311 $and$libresoc.v:41925$1622_Y - connect \$1314 $sub$libresoc.v:41926$1623_Y - connect \$1316 $sshl$libresoc.v:41927$1624_Y - connect \$1318 $ternary$libresoc.v:41928$1625_Y - connect \$1320 $and$libresoc.v:41929$1626_Y - connect \$1323 $and$libresoc.v:41930$1627_Y - connect \$1326 $not$libresoc.v:41931$1628_Y - connect \$1328 $and$libresoc.v:41932$1629_Y - connect \$1331 $and$libresoc.v:41933$1630_Y - connect \$1334 $sub$libresoc.v:41934$1631_Y - connect \$1336 $sshl$libresoc.v:41935$1632_Y - connect \$1338 $ternary$libresoc.v:41936$1633_Y - connect \$1340 $and$libresoc.v:41937$1634_Y - connect \$1343 $and$libresoc.v:41938$1635_Y - connect \$1346 $not$libresoc.v:41939$1636_Y - connect \$1348 $and$libresoc.v:41940$1637_Y - connect \$1351 $and$libresoc.v:41941$1638_Y - connect \$1354 $sub$libresoc.v:41942$1639_Y - connect \$1356 $sshl$libresoc.v:41943$1640_Y - connect \$1358 $ternary$libresoc.v:41944$1641_Y - connect \$1360 $or$libresoc.v:41945$1642_Y - connect \$1362 $or$libresoc.v:41946$1643_Y - connect \$1364 $or$libresoc.v:41947$1644_Y - connect \$1366 $or$libresoc.v:41948$1645_Y - connect \$1368 $or$libresoc.v:41949$1646_Y - connect \$1371 $or$libresoc.v:41950$1647_Y - connect \$1373 $or$libresoc.v:41951$1648_Y - connect \$1375 $or$libresoc.v:41952$1649_Y - connect \$1377 $or$libresoc.v:41953$1650_Y - connect \$1379 $or$libresoc.v:41954$1651_Y - connect \$1381 $and$libresoc.v:41955$1652_Y - connect \$1383 $and$libresoc.v:41956$1653_Y - connect \$1385 $and$libresoc.v:41957$1654_Y - connect \$1387 $and$libresoc.v:41958$1655_Y - connect \$1390 $and$libresoc.v:41959$1656_Y - connect \$1393 $not$libresoc.v:41960$1657_Y - connect \$1395 $and$libresoc.v:41961$1658_Y - connect \$1398 $and$libresoc.v:41962$1659_Y - connect \$1401 $ternary$libresoc.v:41963$1660_Y - connect \$1403 $and$libresoc.v:41964$1661_Y - connect \$1406 $and$libresoc.v:41965$1662_Y - connect \$1409 $not$libresoc.v:41966$1663_Y - connect \$1411 $and$libresoc.v:41967$1664_Y - connect \$1414 $and$libresoc.v:41968$1665_Y - connect \$1417 $ternary$libresoc.v:41969$1666_Y - connect \$1419 $and$libresoc.v:41970$1667_Y - connect \$1422 $and$libresoc.v:41971$1668_Y - connect \$1425 $not$libresoc.v:41972$1669_Y - connect \$1427 $and$libresoc.v:41973$1670_Y - connect \$1430 $and$libresoc.v:41974$1671_Y - connect \$1433 $ternary$libresoc.v:41975$1672_Y - connect \$1435 $or$libresoc.v:41976$1673_Y - connect \$1437 $or$libresoc.v:41977$1674_Y - connect \$1440 $or$libresoc.v:41978$1675_Y - connect \$1442 $or$libresoc.v:41979$1676_Y - connect \$1439 $pos$libresoc.v:41980$1678_Y - connect \$1445 $and$libresoc.v:41981$1679_Y - connect \$1447 $and$libresoc.v:41982$1680_Y - connect \$1449 $and$libresoc.v:41983$1681_Y - connect \$1451 $and$libresoc.v:41984$1682_Y - connect \$1453 $and$libresoc.v:41985$1683_Y - connect \$1456 $and$libresoc.v:41986$1684_Y - connect \$1459 $not$libresoc.v:41987$1685_Y - connect \$1461 $and$libresoc.v:41988$1686_Y - connect \$1464 $and$libresoc.v:41989$1687_Y - connect \$1467 $ternary$libresoc.v:41990$1688_Y - connect \$1469 $and$libresoc.v:41991$1689_Y - connect \$1472 $and$libresoc.v:41992$1690_Y - connect \$1475 $not$libresoc.v:41993$1691_Y - connect \$1477 $and$libresoc.v:41994$1692_Y - connect \$1480 $and$libresoc.v:41995$1693_Y - connect \$1483 $ternary$libresoc.v:41996$1694_Y - connect \$1485 $and$libresoc.v:41997$1695_Y - connect \$1488 $and$libresoc.v:41998$1696_Y - connect \$1491 $not$libresoc.v:41999$1697_Y - connect \$1493 $and$libresoc.v:42000$1698_Y - connect \$1496 $and$libresoc.v:42001$1699_Y - connect \$1499 $ternary$libresoc.v:42002$1700_Y - connect \$1501 $and$libresoc.v:42003$1701_Y - connect \$1504 $and$libresoc.v:42004$1702_Y - connect \$1507 $not$libresoc.v:42005$1703_Y - connect \$1509 $and$libresoc.v:42006$1704_Y - connect \$1512 $and$libresoc.v:42007$1705_Y - connect \$1515 $ternary$libresoc.v:42008$1706_Y - connect \$1517 $or$libresoc.v:42009$1707_Y - connect \$1519 $or$libresoc.v:42010$1708_Y - connect \$1521 $or$libresoc.v:42011$1709_Y - connect \$1523 $or$libresoc.v:42012$1710_Y - connect \$1525 $or$libresoc.v:42013$1711_Y - connect \$1527 $or$libresoc.v:42014$1712_Y - connect \$1529 $and$libresoc.v:42015$1713_Y - connect \$1531 $and$libresoc.v:42016$1714_Y - connect \$1533 $and$libresoc.v:42017$1715_Y - connect \$1535 $and$libresoc.v:42018$1716_Y - connect \$1537 $and$libresoc.v:42019$1717_Y - connect \$1540 $and$libresoc.v:42020$1718_Y - connect \$1543 $not$libresoc.v:42021$1719_Y - connect \$1545 $and$libresoc.v:42022$1720_Y - connect \$1548 $and$libresoc.v:42023$1721_Y - connect \$1551 $ternary$libresoc.v:42024$1722_Y - connect \$1553 $and$libresoc.v:42025$1723_Y - connect \$1556 $and$libresoc.v:42026$1724_Y - connect \$1559 $not$libresoc.v:42027$1725_Y - connect \$1561 $and$libresoc.v:42028$1726_Y - connect \$1564 $and$libresoc.v:42029$1727_Y - connect \$1567 $ternary$libresoc.v:42030$1728_Y - connect \$1569 $and$libresoc.v:42031$1729_Y - connect \$1572 $and$libresoc.v:42032$1730_Y - connect \$1575 $not$libresoc.v:42033$1731_Y - connect \$1577 $and$libresoc.v:42034$1732_Y - connect \$1580 $and$libresoc.v:42035$1733_Y - connect \$1583 $ternary$libresoc.v:42036$1734_Y - connect \$1585 $and$libresoc.v:42037$1735_Y - connect \$1588 $and$libresoc.v:42038$1736_Y - connect \$1591 $not$libresoc.v:42039$1737_Y - connect \$1593 $and$libresoc.v:42040$1738_Y - connect \$1596 $and$libresoc.v:42041$1739_Y - connect \$1599 $ternary$libresoc.v:42042$1740_Y - connect \$1602 $or$libresoc.v:42043$1741_Y - connect \$1604 $or$libresoc.v:42044$1742_Y - connect \$1606 $or$libresoc.v:42045$1743_Y - connect \$1601 $pos$libresoc.v:42046$1745_Y - connect \$1610 $or$libresoc.v:42047$1746_Y - connect \$1612 $or$libresoc.v:42048$1747_Y - connect \$1614 $or$libresoc.v:42049$1748_Y - connect \$1609 $pos$libresoc.v:42050$1750_Y - connect \$1617 $and$libresoc.v:42051$1751_Y - connect \$1619 $and$libresoc.v:42052$1752_Y - connect \$1621 $and$libresoc.v:42053$1753_Y - connect \$1623 $and$libresoc.v:42054$1754_Y - connect \$1625 $and$libresoc.v:42055$1755_Y - connect \$1627 $and$libresoc.v:42056$1756_Y - connect \$1630 $and$libresoc.v:42057$1757_Y - connect \$1634 $not$libresoc.v:42058$1758_Y - connect \$1636 $and$libresoc.v:42059$1759_Y - connect \$1641 $and$libresoc.v:42060$1760_Y - connect \$1644 $ternary$libresoc.v:42061$1761_Y - connect \$1646 $and$libresoc.v:42062$1762_Y - connect \$1649 $and$libresoc.v:42063$1763_Y - connect \$1652 $not$libresoc.v:42064$1764_Y - connect \$1654 $and$libresoc.v:42065$1765_Y - connect \$1657 $and$libresoc.v:42066$1766_Y - connect \$1660 $ternary$libresoc.v:42067$1767_Y - connect \$1662 $and$libresoc.v:42068$1768_Y - connect \$1665 $and$libresoc.v:42069$1769_Y - connect \$1668 $not$libresoc.v:42070$1770_Y - connect \$1670 $and$libresoc.v:42071$1771_Y - connect \$1673 $and$libresoc.v:42072$1772_Y - connect \$1676 $ternary$libresoc.v:42073$1773_Y - connect \$1678 $and$libresoc.v:42074$1774_Y - connect \$1681 $and$libresoc.v:42075$1775_Y - connect \$1684 $not$libresoc.v:42076$1776_Y - connect \$1686 $and$libresoc.v:42077$1777_Y - connect \$1689 $and$libresoc.v:42078$1778_Y - connect \$1692 $ternary$libresoc.v:42079$1779_Y - connect \$1694 $and$libresoc.v:42080$1780_Y - connect \$1697 $and$libresoc.v:42081$1781_Y - connect \$1700 $not$libresoc.v:42082$1782_Y - connect \$1702 $and$libresoc.v:42083$1783_Y - connect \$1705 $and$libresoc.v:42084$1784_Y - connect \$1708 $ternary$libresoc.v:42085$1785_Y - connect \$1710 $or$libresoc.v:42086$1786_Y - connect \$1712 $or$libresoc.v:42087$1787_Y - connect \$1714 $or$libresoc.v:42088$1788_Y - connect \$1716 $or$libresoc.v:42089$1789_Y - connect \$1718 $or$libresoc.v:42090$1790_Y - connect \$1720 $or$libresoc.v:42091$1791_Y - connect \$1722 $or$libresoc.v:42092$1792_Y - connect \$1724 $or$libresoc.v:42093$1793_Y - connect \$1726 $or$libresoc.v:42094$1794_Y - connect \$1728 $or$libresoc.v:42095$1795_Y - connect \$1730 $or$libresoc.v:42096$1796_Y - connect \$1732 $or$libresoc.v:42097$1797_Y - connect \$1734 $and$libresoc.v:42098$1798_Y - connect \$1736 $and$libresoc.v:42099$1799_Y - connect \$1738 $and$libresoc.v:42100$1800_Y - connect \$1741 $and$libresoc.v:42101$1801_Y - connect \$1744 $not$libresoc.v:42102$1802_Y - connect \$1746 $and$libresoc.v:42103$1803_Y - connect \$1749 $and$libresoc.v:42104$1804_Y - connect \$1752 $ternary$libresoc.v:42105$1805_Y - connect \$1754 $and$libresoc.v:42106$1806_Y - connect \$1757 $and$libresoc.v:42107$1807_Y - connect \$1760 $not$libresoc.v:42108$1808_Y - connect \$1762 $and$libresoc.v:42109$1809_Y - connect \$1765 $and$libresoc.v:42110$1810_Y - connect \$1768 $ternary$libresoc.v:42111$1811_Y - connect \$1770 $or$libresoc.v:42112$1812_Y - connect \$1773 $or$libresoc.v:42113$1813_Y - connect \$1772 $pos$libresoc.v:42114$1815_Y - connect \$1776 $and$libresoc.v:42115$1816_Y - connect \$1778 $and$libresoc.v:42116$1817_Y - connect \$177 $and$libresoc.v:42117$1818_Y - connect \$1781 $and$libresoc.v:42118$1819_Y - connect \$1784 $not$libresoc.v:42119$1820_Y - connect \$1786 $and$libresoc.v:42120$1821_Y - connect \$176 $reduce_or$libresoc.v:42121$1822_Y - connect \$1789 $and$libresoc.v:42122$1823_Y - connect \$1792 $ternary$libresoc.v:42123$1824_Y - connect \$1794 $pos$libresoc.v:42124$1826_Y - connect \$1796 $and$libresoc.v:42125$1827_Y - connect \$1798 $and$libresoc.v:42126$1828_Y - connect \$1801 $and$libresoc.v:42127$1829_Y - connect \$1804 $not$libresoc.v:42128$1830_Y - connect \$1806 $and$libresoc.v:42129$1831_Y - connect \$1809 $and$libresoc.v:42130$1832_Y - connect \$1812 $ternary$libresoc.v:42131$1833_Y - connect \$181 $and$libresoc.v:42132$1834_Y - connect \$180 $reduce_or$libresoc.v:42133$1835_Y - connect \$185 $and$libresoc.v:42134$1836_Y - connect \$184 $reduce_or$libresoc.v:42135$1837_Y - connect \$189 $and$libresoc.v:42136$1838_Y - connect \$188 $reduce_or$libresoc.v:42137$1839_Y - connect \$193 $and$libresoc.v:42138$1840_Y - connect \$192 $reduce_or$libresoc.v:42139$1841_Y - connect \$197 $and$libresoc.v:42140$1842_Y - connect \$196 $reduce_or$libresoc.v:42141$1843_Y - connect \$201 $and$libresoc.v:42142$1844_Y - connect \$200 $reduce_or$libresoc.v:42143$1845_Y - connect \$205 $and$libresoc.v:42144$1846_Y - connect \$204 $reduce_or$libresoc.v:42145$1847_Y - connect \$209 $and$libresoc.v:42146$1848_Y - connect \$208 $reduce_or$libresoc.v:42147$1849_Y - connect \$213 $and$libresoc.v:42148$1850_Y - connect \$212 $reduce_or$libresoc.v:42149$1851_Y - connect \$216 $ne$libresoc.v:42150$1852_Y - connect \$219 $sub$libresoc.v:42151$1853_Y - connect \$221 $ne$libresoc.v:42152$1854_Y - connect \$224 $and$libresoc.v:42153$1855_Y - connect \$226 $and$libresoc.v:42154$1856_Y - connect \$228 $eq$libresoc.v:42155$1857_Y - connect \$230 $or$libresoc.v:42156$1858_Y - connect \$232 $and$libresoc.v:42157$1859_Y - connect \$234 $or$libresoc.v:42158$1860_Y - connect \$236 $eq$libresoc.v:42159$1861_Y - connect \$238 $and$libresoc.v:42160$1862_Y - connect \$240 $eq$libresoc.v:42161$1863_Y - connect \$242 $or$libresoc.v:42162$1864_Y - connect \$223 $not$libresoc.v:42163$1865_Y - connect \$245 $not$libresoc.v:42164$1866_Y - connect \$247 $not$libresoc.v:42165$1867_Y - connect \$249 $not$libresoc.v:42166$1868_Y - connect \$252 $and$libresoc.v:42167$1869_Y - connect \$254 $and$libresoc.v:42168$1870_Y - connect \$256 $eq$libresoc.v:42169$1871_Y - connect \$258 $or$libresoc.v:42170$1872_Y - connect \$260 $and$libresoc.v:42171$1873_Y - connect \$262 $or$libresoc.v:42172$1874_Y - connect \$251 $not$libresoc.v:42173$1875_Y - connect \$266 $and$libresoc.v:42174$1876_Y - connect \$268 $and$libresoc.v:42175$1877_Y - connect \$270 $eq$libresoc.v:42176$1878_Y - connect \$272 $or$libresoc.v:42177$1879_Y - connect \$274 $and$libresoc.v:42178$1880_Y - connect \$276 $or$libresoc.v:42179$1881_Y - connect \$278 $and$libresoc.v:42180$1882_Y - connect \$280 $and$libresoc.v:42181$1883_Y - connect \$282 $eq$libresoc.v:42182$1884_Y - connect \$284 $or$libresoc.v:42183$1885_Y - connect \$286 $eq$libresoc.v:42184$1886_Y - connect \$288 $and$libresoc.v:42185$1887_Y - connect \$290 $eq$libresoc.v:42186$1888_Y - connect \$292 $or$libresoc.v:42187$1889_Y - connect \$265 $not$libresoc.v:42188$1890_Y - connect \$296 $and$libresoc.v:42189$1891_Y - connect \$298 $and$libresoc.v:42190$1892_Y - connect \$300 $eq$libresoc.v:42191$1893_Y - connect \$302 $or$libresoc.v:42192$1894_Y - connect \$304 $and$libresoc.v:42193$1895_Y - connect \$306 $or$libresoc.v:42194$1896_Y - connect \$295 $not$libresoc.v:42195$1897_Y - connect \$310 $and$libresoc.v:42196$1898_Y - connect \$312 $and$libresoc.v:42197$1899_Y - connect \$314 $eq$libresoc.v:42198$1900_Y - connect \$316 $or$libresoc.v:42199$1901_Y - connect \$318 $and$libresoc.v:42200$1902_Y - connect \$320 $or$libresoc.v:42201$1903_Y - connect \$309 $not$libresoc.v:42202$1904_Y - connect \$324 $and$libresoc.v:42203$1905_Y - connect \$326 $and$libresoc.v:42204$1906_Y - connect \$328 $eq$libresoc.v:42205$1907_Y - connect \$330 $or$libresoc.v:42206$1908_Y - connect \$332 $and$libresoc.v:42207$1909_Y - connect \$334 $or$libresoc.v:42208$1910_Y - connect \$336 $eq$libresoc.v:42209$1911_Y - connect \$338 $and$libresoc.v:42210$1912_Y - connect \$340 $eq$libresoc.v:42211$1913_Y - connect \$342 $or$libresoc.v:42212$1914_Y - connect \$323 $not$libresoc.v:42213$1915_Y - connect \$345 $not$libresoc.v:42214$1916_Y - connect \$347 $and$libresoc.v:42215$1917_Y - connect \$349 $and$libresoc.v:42216$1918_Y - connect \$351 $not$libresoc.v:42217$1919_Y - connect \$353 $and$libresoc.v:42218$1920_Y - connect \$355 $and$libresoc.v:42219$1921_Y - connect \$357 $ternary$libresoc.v:42220$1922_Y - connect \$359 $and$libresoc.v:42221$1923_Y - connect \$361 $and$libresoc.v:42222$1924_Y - connect \$363 $not$libresoc.v:42223$1925_Y - connect \$365 $and$libresoc.v:42224$1926_Y - connect \$367 $and$libresoc.v:42225$1927_Y - connect \$369 $ternary$libresoc.v:42226$1928_Y - connect \$371 $and$libresoc.v:42227$1929_Y - connect \$373 $and$libresoc.v:42228$1930_Y - connect \$375 $not$libresoc.v:42229$1931_Y - connect \$377 $and$libresoc.v:42230$1932_Y - connect \$379 $and$libresoc.v:42231$1933_Y - connect \$381 $ternary$libresoc.v:42232$1934_Y - connect \$383 $and$libresoc.v:42233$1935_Y - connect \$385 $and$libresoc.v:42234$1936_Y - connect \$387 $not$libresoc.v:42235$1937_Y - connect \$389 $and$libresoc.v:42236$1938_Y - connect \$391 $and$libresoc.v:42237$1939_Y - connect \$393 $ternary$libresoc.v:42238$1940_Y - connect \$395 $and$libresoc.v:42239$1941_Y - connect \$397 $and$libresoc.v:42240$1942_Y - connect \$399 $not$libresoc.v:42241$1943_Y - connect \$401 $and$libresoc.v:42242$1944_Y - connect \$403 $and$libresoc.v:42243$1945_Y - connect \$405 $ternary$libresoc.v:42244$1946_Y - connect \$407 $and$libresoc.v:42245$1947_Y - connect \$409 $and$libresoc.v:42246$1948_Y - connect \$411 $not$libresoc.v:42247$1949_Y - connect \$413 $and$libresoc.v:42248$1950_Y - connect \$415 $and$libresoc.v:42249$1951_Y - connect \$417 $ternary$libresoc.v:42250$1952_Y - connect \$419 $and$libresoc.v:42251$1953_Y - connect \$421 $and$libresoc.v:42252$1954_Y - connect \$423 $not$libresoc.v:42253$1955_Y - connect \$425 $and$libresoc.v:42254$1956_Y - connect \$427 $and$libresoc.v:42255$1957_Y - connect \$429 $ternary$libresoc.v:42256$1958_Y - connect \$431 $and$libresoc.v:42257$1959_Y - connect \$433 $and$libresoc.v:42258$1960_Y - connect \$435 $not$libresoc.v:42259$1961_Y - connect \$437 $and$libresoc.v:42260$1962_Y - connect \$439 $and$libresoc.v:42261$1963_Y - connect \$441 $ternary$libresoc.v:42262$1964_Y - connect \$443 $and$libresoc.v:42263$1965_Y - connect \$445 $and$libresoc.v:42264$1966_Y - connect \$447 $not$libresoc.v:42265$1967_Y - connect \$449 $and$libresoc.v:42266$1968_Y - connect \$451 $and$libresoc.v:42267$1969_Y - connect \$453 $ternary$libresoc.v:42268$1970_Y - connect \$456 $or$libresoc.v:42269$1971_Y - connect \$458 $or$libresoc.v:42270$1972_Y - connect \$460 $or$libresoc.v:42271$1973_Y - connect \$462 $or$libresoc.v:42272$1974_Y - connect \$464 $or$libresoc.v:42273$1975_Y - connect \$466 $or$libresoc.v:42274$1976_Y - connect \$468 $or$libresoc.v:42275$1977_Y - connect \$470 $or$libresoc.v:42276$1978_Y - connect \$472 $reduce_or$libresoc.v:42277$1979_Y - connect \$474 $and$libresoc.v:42278$1980_Y - connect \$476 $and$libresoc.v:42279$1981_Y - connect \$478 $not$libresoc.v:42280$1982_Y - connect \$480 $and$libresoc.v:42281$1983_Y - connect \$482 $and$libresoc.v:42282$1984_Y - connect \$484 $ternary$libresoc.v:42283$1985_Y - connect \$486 $and$libresoc.v:42284$1986_Y - connect \$488 $and$libresoc.v:42285$1987_Y - connect \$490 $not$libresoc.v:42286$1988_Y - connect \$492 $and$libresoc.v:42287$1989_Y - connect \$494 $and$libresoc.v:42288$1990_Y - connect \$496 $ternary$libresoc.v:42289$1991_Y - connect \$498 $and$libresoc.v:42290$1992_Y - connect \$500 $and$libresoc.v:42291$1993_Y - connect \$502 $not$libresoc.v:42292$1994_Y - connect \$504 $and$libresoc.v:42293$1995_Y - connect \$506 $and$libresoc.v:42294$1996_Y - connect \$508 $ternary$libresoc.v:42295$1997_Y - connect \$510 $and$libresoc.v:42296$1998_Y - connect \$512 $and$libresoc.v:42297$1999_Y - connect \$514 $not$libresoc.v:42298$2000_Y - connect \$516 $and$libresoc.v:42299$2001_Y - connect \$518 $and$libresoc.v:42300$2002_Y - connect \$520 $ternary$libresoc.v:42301$2003_Y - connect \$522 $and$libresoc.v:42302$2004_Y - connect \$524 $and$libresoc.v:42303$2005_Y - connect \$526 $not$libresoc.v:42304$2006_Y - connect \$528 $and$libresoc.v:42305$2007_Y - connect \$530 $and$libresoc.v:42306$2008_Y - connect \$532 $ternary$libresoc.v:42307$2009_Y - connect \$534 $and$libresoc.v:42308$2010_Y - connect \$536 $and$libresoc.v:42309$2011_Y - connect \$538 $not$libresoc.v:42310$2012_Y - connect \$540 $and$libresoc.v:42311$2013_Y - connect \$542 $and$libresoc.v:42312$2014_Y - connect \$544 $ternary$libresoc.v:42313$2015_Y - connect \$546 $and$libresoc.v:42314$2016_Y - connect \$548 $and$libresoc.v:42315$2017_Y - connect \$550 $not$libresoc.v:42316$2018_Y - connect \$552 $and$libresoc.v:42317$2019_Y - connect \$554 $and$libresoc.v:42318$2020_Y - connect \$556 $ternary$libresoc.v:42319$2021_Y - connect \$558 $and$libresoc.v:42320$2022_Y - connect \$560 $and$libresoc.v:42321$2023_Y - connect \$562 $not$libresoc.v:42322$2024_Y - connect \$564 $and$libresoc.v:42323$2025_Y - connect \$566 $and$libresoc.v:42324$2026_Y - connect \$568 $ternary$libresoc.v:42325$2027_Y - connect \$571 $or$libresoc.v:42326$2028_Y - connect \$573 $or$libresoc.v:42327$2029_Y - connect \$575 $or$libresoc.v:42328$2030_Y - connect \$577 $or$libresoc.v:42329$2031_Y - connect \$579 $or$libresoc.v:42330$2032_Y - connect \$581 $or$libresoc.v:42331$2033_Y - connect \$583 $or$libresoc.v:42332$2034_Y - connect \$585 $reduce_or$libresoc.v:42333$2035_Y - connect \$587 $and$libresoc.v:42334$2036_Y - connect \$589 $and$libresoc.v:42335$2037_Y - connect \$591 $not$libresoc.v:42336$2038_Y - connect \$593 $and$libresoc.v:42337$2039_Y - connect \$595 $and$libresoc.v:42338$2040_Y - connect \$597 $ternary$libresoc.v:42339$2041_Y - connect \$599 $and$libresoc.v:42340$2042_Y - connect \$601 $and$libresoc.v:42341$2043_Y - connect \$603 $not$libresoc.v:42342$2044_Y - connect \$605 $and$libresoc.v:42343$2045_Y - connect \$607 $and$libresoc.v:42344$2046_Y - connect \$609 $ternary$libresoc.v:42345$2047_Y - connect \$612 $or$libresoc.v:42346$2048_Y - connect \$614 $reduce_or$libresoc.v:42347$2049_Y - connect \$616 $and$libresoc.v:42348$2050_Y - connect \$618 $and$libresoc.v:42349$2051_Y - connect \$620 $eq$libresoc.v:42350$2052_Y - connect \$622 $or$libresoc.v:42351$2053_Y - connect \$624 $and$libresoc.v:42352$2054_Y - connect \$626 $or$libresoc.v:42353$2055_Y - connect \$628 $and$libresoc.v:42354$2056_Y - connect \$630 $and$libresoc.v:42355$2057_Y - connect \$632 $not$libresoc.v:42356$2058_Y - connect \$634 $and$libresoc.v:42357$2059_Y - connect \$636 $and$libresoc.v:42358$2060_Y - connect \$638 $ternary$libresoc.v:42359$2061_Y - connect \$640 $and$libresoc.v:42360$2062_Y - connect \$642 $and$libresoc.v:42361$2063_Y - connect \$644 $not$libresoc.v:42362$2064_Y - connect \$646 $and$libresoc.v:42363$2065_Y - connect \$648 $and$libresoc.v:42364$2066_Y - connect \$650 $ternary$libresoc.v:42365$2067_Y - connect \$652 $and$libresoc.v:42366$2068_Y - connect \$654 $and$libresoc.v:42367$2069_Y - connect \$656 $not$libresoc.v:42368$2070_Y - connect \$658 $and$libresoc.v:42369$2071_Y - connect \$660 $and$libresoc.v:42370$2072_Y - connect \$662 $ternary$libresoc.v:42371$2073_Y - connect \$664 $and$libresoc.v:42372$2074_Y - connect \$666 $and$libresoc.v:42373$2075_Y - connect \$668 $not$libresoc.v:42374$2076_Y - connect \$670 $and$libresoc.v:42375$2077_Y - connect \$672 $and$libresoc.v:42376$2078_Y - connect \$674 $ternary$libresoc.v:42377$2079_Y - connect \$676 $and$libresoc.v:42378$2080_Y - connect \$678 $and$libresoc.v:42379$2081_Y - connect \$680 $not$libresoc.v:42380$2082_Y - connect \$682 $and$libresoc.v:42381$2083_Y - connect \$684 $and$libresoc.v:42382$2084_Y - connect \$686 $ternary$libresoc.v:42383$2085_Y - connect \$688 $and$libresoc.v:42384$2086_Y - connect \$690 $and$libresoc.v:42385$2087_Y - connect \$692 $not$libresoc.v:42386$2088_Y - connect \$694 $and$libresoc.v:42387$2089_Y - connect \$696 $and$libresoc.v:42388$2090_Y - connect \$698 $ternary$libresoc.v:42389$2091_Y - connect \$701 $or$libresoc.v:42390$2092_Y - connect \$703 $or$libresoc.v:42391$2093_Y - connect \$705 $or$libresoc.v:42392$2094_Y - connect \$707 $or$libresoc.v:42393$2095_Y - connect \$709 $or$libresoc.v:42394$2096_Y - connect \$700 $pos$libresoc.v:42395$2098_Y - connect \$712 $eq$libresoc.v:42396$2099_Y - connect \$714 $and$libresoc.v:42397$2100_Y - connect \$716 $eq$libresoc.v:42398$2101_Y - connect \$718 $or$libresoc.v:42399$2102_Y - connect \$720 $and$libresoc.v:42400$2103_Y - connect \$722 $and$libresoc.v:42401$2104_Y - connect \$724 $not$libresoc.v:42402$2105_Y - connect \$726 $and$libresoc.v:42403$2106_Y - connect \$728 $and$libresoc.v:42404$2107_Y - connect \$730 $ternary$libresoc.v:42405$2108_Y - connect \$732 $and$libresoc.v:42406$2109_Y - connect \$734 $and$libresoc.v:42407$2110_Y - connect \$736 $not$libresoc.v:42408$2111_Y - connect \$738 $and$libresoc.v:42409$2112_Y - connect \$740 $and$libresoc.v:42410$2113_Y - connect \$742 $ternary$libresoc.v:42411$2114_Y - connect \$744 $and$libresoc.v:42412$2115_Y - connect \$746 $and$libresoc.v:42413$2116_Y - connect \$748 $not$libresoc.v:42414$2117_Y - connect \$750 $and$libresoc.v:42415$2118_Y - connect \$752 $and$libresoc.v:42416$2119_Y - connect \$754 $ternary$libresoc.v:42417$2120_Y - connect \$757 $or$libresoc.v:42418$2121_Y - connect \$759 $or$libresoc.v:42419$2122_Y - connect \$756 $pos$libresoc.v:42420$2124_Y - connect \$762 $and$libresoc.v:42421$2125_Y - connect \$764 $and$libresoc.v:42422$2126_Y - connect \$766 $eq$libresoc.v:42423$2127_Y - connect \$768 $or$libresoc.v:42424$2128_Y - connect \$770 $and$libresoc.v:42425$2129_Y - connect \$772 $and$libresoc.v:42426$2130_Y - connect \$774 $not$libresoc.v:42427$2131_Y - connect \$776 $and$libresoc.v:42428$2132_Y - connect \$778 $and$libresoc.v:42429$2133_Y - connect \$780 $ternary$libresoc.v:42430$2134_Y - connect \$782 $and$libresoc.v:42431$2135_Y - connect \$784 $and$libresoc.v:42432$2136_Y - connect \$786 $not$libresoc.v:42433$2137_Y - connect \$788 $and$libresoc.v:42434$2138_Y - connect \$790 $and$libresoc.v:42435$2139_Y - connect \$792 $ternary$libresoc.v:42436$2140_Y - connect \$794 $and$libresoc.v:42437$2141_Y - connect \$796 $and$libresoc.v:42438$2142_Y - connect \$798 $not$libresoc.v:42439$2143_Y - connect \$800 $and$libresoc.v:42440$2144_Y - connect \$802 $and$libresoc.v:42441$2145_Y - connect \$804 $sub$libresoc.v:42442$2146_Y - connect \$806 $sshl$libresoc.v:42443$2147_Y - connect \$808 $ternary$libresoc.v:42444$2148_Y - connect \$810 $and$libresoc.v:42445$2149_Y - connect \$812 $and$libresoc.v:42446$2150_Y - connect \$814 $not$libresoc.v:42447$2151_Y - connect \$816 $and$libresoc.v:42448$2152_Y - connect \$818 $and$libresoc.v:42449$2153_Y - connect \$820 $sub$libresoc.v:42450$2154_Y - connect \$822 $sshl$libresoc.v:42451$2155_Y - connect \$824 $ternary$libresoc.v:42452$2156_Y - connect \$827 $or$libresoc.v:42453$2157_Y - connect \$829 $and$libresoc.v:42454$2158_Y - connect \$831 $and$libresoc.v:42455$2159_Y - connect \$833 $not$libresoc.v:42456$2160_Y - connect \$835 $and$libresoc.v:42457$2161_Y - connect \$837 $and$libresoc.v:42458$2162_Y - connect \$839 $sub$libresoc.v:42459$2163_Y - connect \$841 $sshl$libresoc.v:42460$2164_Y - connect \$843 $ternary$libresoc.v:42461$2165_Y - connect \$845 $and$libresoc.v:42462$2166_Y - connect \$847 $and$libresoc.v:42463$2167_Y - connect \$849 $not$libresoc.v:42464$2168_Y - connect \$851 $and$libresoc.v:42465$2169_Y - connect \$853 $and$libresoc.v:42466$2170_Y - connect \$855 $sub$libresoc.v:42467$2171_Y - connect \$857 $sshl$libresoc.v:42468$2172_Y - connect \$859 $ternary$libresoc.v:42469$2173_Y - connect \$861 $and$libresoc.v:42470$2174_Y - connect \$863 $and$libresoc.v:42471$2175_Y - connect \$865 $not$libresoc.v:42472$2176_Y - connect \$867 $and$libresoc.v:42473$2177_Y - connect \$869 $and$libresoc.v:42474$2178_Y - connect \$871 $ternary$libresoc.v:42475$2179_Y - connect \$873 $and$libresoc.v:42476$2180_Y - connect \$875 $and$libresoc.v:42477$2181_Y - connect \$877 $not$libresoc.v:42478$2182_Y - connect \$879 $and$libresoc.v:42479$2183_Y - connect \$881 $and$libresoc.v:42480$2184_Y - connect \$883 $ternary$libresoc.v:42481$2185_Y - connect \$885 $and$libresoc.v:42482$2186_Y - connect \$887 $and$libresoc.v:42483$2187_Y - connect \$889 $not$libresoc.v:42484$2188_Y - connect \$891 $and$libresoc.v:42485$2189_Y - connect \$893 $and$libresoc.v:42486$2190_Y - connect \$895 $ternary$libresoc.v:42487$2191_Y - connect \$897 $or$libresoc.v:42488$2192_Y - connect \$899 $or$libresoc.v:42489$2193_Y - connect \$901 $reduce_or$libresoc.v:42490$2194_Y - connect \$903 $and$libresoc.v:42491$2195_Y - connect \$905 $and$libresoc.v:42492$2196_Y - connect \$907 $not$libresoc.v:42493$2197_Y - connect \$909 $and$libresoc.v:42494$2198_Y - connect \$911 $and$libresoc.v:42495$2199_Y - connect \$913 $ternary$libresoc.v:42496$2200_Y - connect \$915 $and$libresoc.v:42497$2201_Y - connect \$917 $and$libresoc.v:42498$2202_Y - connect \$919 $not$libresoc.v:42499$2203_Y - connect \$921 $and$libresoc.v:42500$2204_Y - connect \$923 $and$libresoc.v:42501$2205_Y - connect \$925 $ternary$libresoc.v:42502$2206_Y - connect \$927 $or$libresoc.v:42503$2207_Y - connect \$929 $reduce_or$libresoc.v:42504$2208_Y - connect \$931 $and$libresoc.v:42505$2209_Y - connect \$933 $and$libresoc.v:42506$2210_Y - connect \$935 $not$libresoc.v:42507$2211_Y - connect \$937 $and$libresoc.v:42508$2212_Y - connect \$939 $and$libresoc.v:42509$2213_Y - connect \$941 $ternary$libresoc.v:42510$2214_Y - connect \$943 $reduce_or$libresoc.v:42511$2215_Y - connect \$945 $and$libresoc.v:42512$2216_Y - connect \$947 $and$libresoc.v:42513$2217_Y - connect \$949 $and$libresoc.v:42514$2218_Y - connect \$951 $and$libresoc.v:42515$2219_Y - connect \$953 $and$libresoc.v:42516$2220_Y - connect \$955 $and$libresoc.v:42517$2221_Y - connect \$957 $and$libresoc.v:42518$2222_Y - connect \$959 $and$libresoc.v:42519$2223_Y - connect \$961 $and$libresoc.v:42520$2224_Y - connect \$963 $and$libresoc.v:42521$2225_Y - connect \$965 $and$libresoc.v:42522$2226_Y - connect \$967 $and$libresoc.v:42523$2227_Y - connect \$969 $not$libresoc.v:42524$2228_Y - connect \$971 $and$libresoc.v:42525$2229_Y - connect \$977 $and$libresoc.v:42526$2230_Y - connect \$979 $ternary$libresoc.v:42527$2231_Y - connect \$981 $and$libresoc.v:42528$2232_Y - connect \$984 $and$libresoc.v:42529$2233_Y - connect \$988 $not$libresoc.v:42530$2234_Y - connect \$990 $and$libresoc.v:42531$2235_Y - connect \$995 $and$libresoc.v:42532$2236_Y - connect \$998 $ternary$libresoc.v:42533$2237_Y + connect \$1000 $and$libresoc.v:41811$1506_Y + connect \$1003 $and$libresoc.v:41812$1507_Y + connect \$1007 $not$libresoc.v:41813$1508_Y + connect \$1009 $and$libresoc.v:41814$1509_Y + connect \$1016 $and$libresoc.v:41815$1510_Y + connect \$1019 $ternary$libresoc.v:41816$1511_Y + connect \$1021 $and$libresoc.v:41817$1512_Y + connect \$1024 $and$libresoc.v:41818$1513_Y + connect \$1028 $not$libresoc.v:41819$1514_Y + connect \$1030 $and$libresoc.v:41820$1515_Y + connect \$1034 $and$libresoc.v:41821$1516_Y + connect \$1037 $ternary$libresoc.v:41822$1517_Y + connect \$1039 $and$libresoc.v:41823$1518_Y + connect \$1042 $and$libresoc.v:41824$1519_Y + connect \$1046 $not$libresoc.v:41825$1520_Y + connect \$1048 $and$libresoc.v:41826$1521_Y + connect \$1056 $and$libresoc.v:41827$1522_Y + connect \$1059 $ternary$libresoc.v:41828$1523_Y + connect \$1061 $and$libresoc.v:41829$1524_Y + connect \$1064 $and$libresoc.v:41830$1525_Y + connect \$1068 $not$libresoc.v:41831$1526_Y + connect \$1070 $and$libresoc.v:41832$1527_Y + connect \$1076 $and$libresoc.v:41833$1528_Y + connect \$1079 $ternary$libresoc.v:41834$1529_Y + connect \$1081 $and$libresoc.v:41835$1530_Y + connect \$1084 $and$libresoc.v:41836$1531_Y + connect \$1088 $not$libresoc.v:41837$1532_Y + connect \$1090 $and$libresoc.v:41838$1533_Y + connect \$1096 $and$libresoc.v:41839$1534_Y + connect \$1099 $ternary$libresoc.v:41840$1535_Y + connect \$1101 $and$libresoc.v:41841$1536_Y + connect \$1104 $and$libresoc.v:41842$1537_Y + connect \$1108 $not$libresoc.v:41843$1538_Y + connect \$1110 $and$libresoc.v:41844$1539_Y + connect \$1115 $and$libresoc.v:41845$1540_Y + connect \$1118 $ternary$libresoc.v:41846$1541_Y + connect \$1120 $and$libresoc.v:41847$1542_Y + connect \$1123 $and$libresoc.v:41848$1543_Y + connect \$1127 $not$libresoc.v:41849$1544_Y + connect \$1129 $and$libresoc.v:41850$1545_Y + connect \$1133 $and$libresoc.v:41851$1546_Y + connect \$1136 $ternary$libresoc.v:41852$1547_Y + connect \$1138 $and$libresoc.v:41853$1548_Y + connect \$1141 $and$libresoc.v:41854$1549_Y + connect \$1144 $not$libresoc.v:41855$1550_Y + connect \$1146 $and$libresoc.v:41856$1551_Y + connect \$1149 $and$libresoc.v:41857$1552_Y + connect \$1152 $ternary$libresoc.v:41858$1553_Y + connect \$1155 $or$libresoc.v:41859$1554_Y + connect \$1157 $or$libresoc.v:41860$1555_Y + connect \$1159 $or$libresoc.v:41861$1556_Y + connect \$1161 $or$libresoc.v:41862$1557_Y + connect \$1163 $or$libresoc.v:41863$1558_Y + connect \$1165 $or$libresoc.v:41864$1559_Y + connect \$1167 $or$libresoc.v:41865$1560_Y + connect \$1169 $or$libresoc.v:41866$1561_Y + connect \$1171 $or$libresoc.v:41867$1562_Y + connect \$1174 $or$libresoc.v:41868$1563_Y + connect \$1176 $or$libresoc.v:41869$1564_Y + connect \$1178 $or$libresoc.v:41870$1565_Y + connect \$1180 $or$libresoc.v:41871$1566_Y + connect \$1182 $or$libresoc.v:41872$1567_Y + connect \$1184 $or$libresoc.v:41873$1568_Y + connect \$1186 $or$libresoc.v:41874$1569_Y + connect \$1188 $or$libresoc.v:41875$1570_Y + connect \$1190 $or$libresoc.v:41876$1571_Y + connect \$1192 $or$libresoc.v:41877$1572_Y + connect \$1194 $or$libresoc.v:41878$1573_Y + connect \$1196 $or$libresoc.v:41879$1574_Y + connect \$1198 $or$libresoc.v:41880$1575_Y + connect \$1200 $or$libresoc.v:41881$1576_Y + connect \$1202 $or$libresoc.v:41882$1577_Y + connect \$1204 $or$libresoc.v:41883$1578_Y + connect \$1206 $or$libresoc.v:41884$1579_Y + connect \$1208 $or$libresoc.v:41885$1580_Y + connect \$1210 $and$libresoc.v:41886$1581_Y + connect \$1212 $and$libresoc.v:41887$1582_Y + connect \$1215 $and$libresoc.v:41888$1583_Y + connect \$1218 $not$libresoc.v:41889$1584_Y + connect \$1220 $and$libresoc.v:41890$1585_Y + connect \$1223 $and$libresoc.v:41891$1586_Y + connect \$1226 $ternary$libresoc.v:41892$1587_Y + connect \$1228 $and$libresoc.v:41893$1588_Y + connect \$1230 $and$libresoc.v:41894$1589_Y + connect \$1232 $and$libresoc.v:41895$1590_Y + connect \$1234 $and$libresoc.v:41896$1591_Y + connect \$1236 $and$libresoc.v:41897$1592_Y + connect \$1238 $and$libresoc.v:41898$1593_Y + connect \$1240 $and$libresoc.v:41899$1594_Y + connect \$1243 $and$libresoc.v:41900$1595_Y + connect \$1246 $not$libresoc.v:41901$1596_Y + connect \$1248 $and$libresoc.v:41902$1597_Y + connect \$1251 $and$libresoc.v:41903$1598_Y + connect \$1254 $sub$libresoc.v:41904$1599_Y + connect \$1256 $sshl$libresoc.v:41905$1600_Y + connect \$1258 $ternary$libresoc.v:41906$1601_Y + connect \$1260 $and$libresoc.v:41907$1602_Y + connect \$1263 $and$libresoc.v:41908$1603_Y + connect \$1266 $not$libresoc.v:41909$1604_Y + connect \$1268 $and$libresoc.v:41910$1605_Y + connect \$1271 $and$libresoc.v:41911$1606_Y + connect \$1274 $sub$libresoc.v:41912$1607_Y + connect \$1276 $sshl$libresoc.v:41913$1608_Y + connect \$1278 $ternary$libresoc.v:41914$1609_Y + connect \$1280 $and$libresoc.v:41915$1610_Y + connect \$1283 $and$libresoc.v:41916$1611_Y + connect \$1286 $not$libresoc.v:41917$1612_Y + connect \$1288 $and$libresoc.v:41918$1613_Y + connect \$1291 $and$libresoc.v:41919$1614_Y + connect \$1294 $sub$libresoc.v:41920$1615_Y + connect \$1296 $sshl$libresoc.v:41921$1616_Y + connect \$1298 $ternary$libresoc.v:41922$1617_Y + connect \$1300 $and$libresoc.v:41923$1618_Y + connect \$1303 $and$libresoc.v:41924$1619_Y + connect \$1306 $not$libresoc.v:41925$1620_Y + connect \$1308 $and$libresoc.v:41926$1621_Y + connect \$1311 $and$libresoc.v:41927$1622_Y + connect \$1314 $sub$libresoc.v:41928$1623_Y + connect \$1316 $sshl$libresoc.v:41929$1624_Y + connect \$1318 $ternary$libresoc.v:41930$1625_Y + connect \$1320 $and$libresoc.v:41931$1626_Y + connect \$1323 $and$libresoc.v:41932$1627_Y + connect \$1326 $not$libresoc.v:41933$1628_Y + connect \$1328 $and$libresoc.v:41934$1629_Y + connect \$1331 $and$libresoc.v:41935$1630_Y + connect \$1334 $sub$libresoc.v:41936$1631_Y + connect \$1336 $sshl$libresoc.v:41937$1632_Y + connect \$1338 $ternary$libresoc.v:41938$1633_Y + connect \$1340 $and$libresoc.v:41939$1634_Y + connect \$1343 $and$libresoc.v:41940$1635_Y + connect \$1346 $not$libresoc.v:41941$1636_Y + connect \$1348 $and$libresoc.v:41942$1637_Y + connect \$1351 $and$libresoc.v:41943$1638_Y + connect \$1354 $sub$libresoc.v:41944$1639_Y + connect \$1356 $sshl$libresoc.v:41945$1640_Y + connect \$1358 $ternary$libresoc.v:41946$1641_Y + connect \$1360 $or$libresoc.v:41947$1642_Y + connect \$1362 $or$libresoc.v:41948$1643_Y + connect \$1364 $or$libresoc.v:41949$1644_Y + connect \$1366 $or$libresoc.v:41950$1645_Y + connect \$1368 $or$libresoc.v:41951$1646_Y + connect \$1371 $or$libresoc.v:41952$1647_Y + connect \$1373 $or$libresoc.v:41953$1648_Y + connect \$1375 $or$libresoc.v:41954$1649_Y + connect \$1377 $or$libresoc.v:41955$1650_Y + connect \$1379 $or$libresoc.v:41956$1651_Y + connect \$1381 $and$libresoc.v:41957$1652_Y + connect \$1383 $and$libresoc.v:41958$1653_Y + connect \$1385 $and$libresoc.v:41959$1654_Y + connect \$1387 $and$libresoc.v:41960$1655_Y + connect \$1390 $and$libresoc.v:41961$1656_Y + connect \$1393 $not$libresoc.v:41962$1657_Y + connect \$1395 $and$libresoc.v:41963$1658_Y + connect \$1398 $and$libresoc.v:41964$1659_Y + connect \$1401 $ternary$libresoc.v:41965$1660_Y + connect \$1403 $and$libresoc.v:41966$1661_Y + connect \$1406 $and$libresoc.v:41967$1662_Y + connect \$1409 $not$libresoc.v:41968$1663_Y + connect \$1411 $and$libresoc.v:41969$1664_Y + connect \$1414 $and$libresoc.v:41970$1665_Y + connect \$1417 $ternary$libresoc.v:41971$1666_Y + connect \$1419 $and$libresoc.v:41972$1667_Y + connect \$1422 $and$libresoc.v:41973$1668_Y + connect \$1425 $not$libresoc.v:41974$1669_Y + connect \$1427 $and$libresoc.v:41975$1670_Y + connect \$1430 $and$libresoc.v:41976$1671_Y + connect \$1433 $ternary$libresoc.v:41977$1672_Y + connect \$1435 $or$libresoc.v:41978$1673_Y + connect \$1437 $or$libresoc.v:41979$1674_Y + connect \$1440 $or$libresoc.v:41980$1675_Y + connect \$1442 $or$libresoc.v:41981$1676_Y + connect \$1439 $pos$libresoc.v:41982$1678_Y + connect \$1445 $and$libresoc.v:41983$1679_Y + connect \$1447 $and$libresoc.v:41984$1680_Y + connect \$1449 $and$libresoc.v:41985$1681_Y + connect \$1451 $and$libresoc.v:41986$1682_Y + connect \$1453 $and$libresoc.v:41987$1683_Y + connect \$1456 $and$libresoc.v:41988$1684_Y + connect \$1459 $not$libresoc.v:41989$1685_Y + connect \$1461 $and$libresoc.v:41990$1686_Y + connect \$1464 $and$libresoc.v:41991$1687_Y + connect \$1467 $ternary$libresoc.v:41992$1688_Y + connect \$1469 $and$libresoc.v:41993$1689_Y + connect \$1472 $and$libresoc.v:41994$1690_Y + connect \$1475 $not$libresoc.v:41995$1691_Y + connect \$1477 $and$libresoc.v:41996$1692_Y + connect \$1480 $and$libresoc.v:41997$1693_Y + connect \$1483 $ternary$libresoc.v:41998$1694_Y + connect \$1485 $and$libresoc.v:41999$1695_Y + connect \$1488 $and$libresoc.v:42000$1696_Y + connect \$1491 $not$libresoc.v:42001$1697_Y + connect \$1493 $and$libresoc.v:42002$1698_Y + connect \$1496 $and$libresoc.v:42003$1699_Y + connect \$1499 $ternary$libresoc.v:42004$1700_Y + connect \$1501 $and$libresoc.v:42005$1701_Y + connect \$1504 $and$libresoc.v:42006$1702_Y + connect \$1507 $not$libresoc.v:42007$1703_Y + connect \$1509 $and$libresoc.v:42008$1704_Y + connect \$1512 $and$libresoc.v:42009$1705_Y + connect \$1515 $ternary$libresoc.v:42010$1706_Y + connect \$1517 $or$libresoc.v:42011$1707_Y + connect \$1519 $or$libresoc.v:42012$1708_Y + connect \$1521 $or$libresoc.v:42013$1709_Y + connect \$1523 $or$libresoc.v:42014$1710_Y + connect \$1525 $or$libresoc.v:42015$1711_Y + connect \$1527 $or$libresoc.v:42016$1712_Y + connect \$1529 $and$libresoc.v:42017$1713_Y + connect \$1531 $and$libresoc.v:42018$1714_Y + connect \$1533 $and$libresoc.v:42019$1715_Y + connect \$1535 $and$libresoc.v:42020$1716_Y + connect \$1537 $and$libresoc.v:42021$1717_Y + connect \$1540 $and$libresoc.v:42022$1718_Y + connect \$1543 $not$libresoc.v:42023$1719_Y + connect \$1545 $and$libresoc.v:42024$1720_Y + connect \$1548 $and$libresoc.v:42025$1721_Y + connect \$1551 $ternary$libresoc.v:42026$1722_Y + connect \$1553 $and$libresoc.v:42027$1723_Y + connect \$1556 $and$libresoc.v:42028$1724_Y + connect \$1559 $not$libresoc.v:42029$1725_Y + connect \$1561 $and$libresoc.v:42030$1726_Y + connect \$1564 $and$libresoc.v:42031$1727_Y + connect \$1567 $ternary$libresoc.v:42032$1728_Y + connect \$1569 $and$libresoc.v:42033$1729_Y + connect \$1572 $and$libresoc.v:42034$1730_Y + connect \$1575 $not$libresoc.v:42035$1731_Y + connect \$1577 $and$libresoc.v:42036$1732_Y + connect \$1580 $and$libresoc.v:42037$1733_Y + connect \$1583 $ternary$libresoc.v:42038$1734_Y + connect \$1585 $and$libresoc.v:42039$1735_Y + connect \$1588 $and$libresoc.v:42040$1736_Y + connect \$1591 $not$libresoc.v:42041$1737_Y + connect \$1593 $and$libresoc.v:42042$1738_Y + connect \$1596 $and$libresoc.v:42043$1739_Y + connect \$1599 $ternary$libresoc.v:42044$1740_Y + connect \$1602 $or$libresoc.v:42045$1741_Y + connect \$1604 $or$libresoc.v:42046$1742_Y + connect \$1606 $or$libresoc.v:42047$1743_Y + connect \$1601 $pos$libresoc.v:42048$1745_Y + connect \$1610 $or$libresoc.v:42049$1746_Y + connect \$1612 $or$libresoc.v:42050$1747_Y + connect \$1614 $or$libresoc.v:42051$1748_Y + connect \$1609 $pos$libresoc.v:42052$1750_Y + connect \$1617 $and$libresoc.v:42053$1751_Y + connect \$1619 $and$libresoc.v:42054$1752_Y + connect \$1621 $and$libresoc.v:42055$1753_Y + connect \$1623 $and$libresoc.v:42056$1754_Y + connect \$1625 $and$libresoc.v:42057$1755_Y + connect \$1627 $and$libresoc.v:42058$1756_Y + connect \$1630 $and$libresoc.v:42059$1757_Y + connect \$1634 $not$libresoc.v:42060$1758_Y + connect \$1636 $and$libresoc.v:42061$1759_Y + connect \$1641 $and$libresoc.v:42062$1760_Y + connect \$1644 $ternary$libresoc.v:42063$1761_Y + connect \$1646 $and$libresoc.v:42064$1762_Y + connect \$1649 $and$libresoc.v:42065$1763_Y + connect \$1652 $not$libresoc.v:42066$1764_Y + connect \$1654 $and$libresoc.v:42067$1765_Y + connect \$1657 $and$libresoc.v:42068$1766_Y + connect \$1660 $ternary$libresoc.v:42069$1767_Y + connect \$1662 $and$libresoc.v:42070$1768_Y + connect \$1665 $and$libresoc.v:42071$1769_Y + connect \$1668 $not$libresoc.v:42072$1770_Y + connect \$1670 $and$libresoc.v:42073$1771_Y + connect \$1673 $and$libresoc.v:42074$1772_Y + connect \$1676 $ternary$libresoc.v:42075$1773_Y + connect \$1678 $and$libresoc.v:42076$1774_Y + connect \$1681 $and$libresoc.v:42077$1775_Y + connect \$1684 $not$libresoc.v:42078$1776_Y + connect \$1686 $and$libresoc.v:42079$1777_Y + connect \$1689 $and$libresoc.v:42080$1778_Y + connect \$1692 $ternary$libresoc.v:42081$1779_Y + connect \$1694 $and$libresoc.v:42082$1780_Y + connect \$1697 $and$libresoc.v:42083$1781_Y + connect \$1700 $not$libresoc.v:42084$1782_Y + connect \$1702 $and$libresoc.v:42085$1783_Y + connect \$1705 $and$libresoc.v:42086$1784_Y + connect \$1708 $ternary$libresoc.v:42087$1785_Y + connect \$1710 $or$libresoc.v:42088$1786_Y + connect \$1712 $or$libresoc.v:42089$1787_Y + connect \$1714 $or$libresoc.v:42090$1788_Y + connect \$1716 $or$libresoc.v:42091$1789_Y + connect \$1718 $or$libresoc.v:42092$1790_Y + connect \$1720 $or$libresoc.v:42093$1791_Y + connect \$1722 $or$libresoc.v:42094$1792_Y + connect \$1724 $or$libresoc.v:42095$1793_Y + connect \$1726 $or$libresoc.v:42096$1794_Y + connect \$1728 $or$libresoc.v:42097$1795_Y + connect \$1730 $or$libresoc.v:42098$1796_Y + connect \$1732 $or$libresoc.v:42099$1797_Y + connect \$1734 $and$libresoc.v:42100$1798_Y + connect \$1736 $and$libresoc.v:42101$1799_Y + connect \$1738 $and$libresoc.v:42102$1800_Y + connect \$1741 $and$libresoc.v:42103$1801_Y + connect \$1744 $not$libresoc.v:42104$1802_Y + connect \$1746 $and$libresoc.v:42105$1803_Y + connect \$1749 $and$libresoc.v:42106$1804_Y + connect \$1752 $ternary$libresoc.v:42107$1805_Y + connect \$1754 $and$libresoc.v:42108$1806_Y + connect \$1757 $and$libresoc.v:42109$1807_Y + connect \$1760 $not$libresoc.v:42110$1808_Y + connect \$1762 $and$libresoc.v:42111$1809_Y + connect \$1765 $and$libresoc.v:42112$1810_Y + connect \$1768 $ternary$libresoc.v:42113$1811_Y + connect \$1770 $or$libresoc.v:42114$1812_Y + connect \$1773 $or$libresoc.v:42115$1813_Y + connect \$1772 $pos$libresoc.v:42116$1815_Y + connect \$1776 $and$libresoc.v:42117$1816_Y + connect \$1778 $and$libresoc.v:42118$1817_Y + connect \$177 $and$libresoc.v:42119$1818_Y + connect \$1781 $and$libresoc.v:42120$1819_Y + connect \$1784 $not$libresoc.v:42121$1820_Y + connect \$1786 $and$libresoc.v:42122$1821_Y + connect \$176 $reduce_or$libresoc.v:42123$1822_Y + connect \$1789 $and$libresoc.v:42124$1823_Y + connect \$1792 $ternary$libresoc.v:42125$1824_Y + connect \$1794 $pos$libresoc.v:42126$1826_Y + connect \$1796 $and$libresoc.v:42127$1827_Y + connect \$1798 $and$libresoc.v:42128$1828_Y + connect \$1801 $and$libresoc.v:42129$1829_Y + connect \$1804 $not$libresoc.v:42130$1830_Y + connect \$1806 $and$libresoc.v:42131$1831_Y + connect \$1809 $and$libresoc.v:42132$1832_Y + connect \$1812 $ternary$libresoc.v:42133$1833_Y + connect \$181 $and$libresoc.v:42134$1834_Y + connect \$180 $reduce_or$libresoc.v:42135$1835_Y + connect \$185 $and$libresoc.v:42136$1836_Y + connect \$184 $reduce_or$libresoc.v:42137$1837_Y + connect \$189 $and$libresoc.v:42138$1838_Y + connect \$188 $reduce_or$libresoc.v:42139$1839_Y + connect \$193 $and$libresoc.v:42140$1840_Y + connect \$192 $reduce_or$libresoc.v:42141$1841_Y + connect \$197 $and$libresoc.v:42142$1842_Y + connect \$196 $reduce_or$libresoc.v:42143$1843_Y + connect \$201 $and$libresoc.v:42144$1844_Y + connect \$200 $reduce_or$libresoc.v:42145$1845_Y + connect \$205 $and$libresoc.v:42146$1846_Y + connect \$204 $reduce_or$libresoc.v:42147$1847_Y + connect \$209 $and$libresoc.v:42148$1848_Y + connect \$208 $reduce_or$libresoc.v:42149$1849_Y + connect \$213 $and$libresoc.v:42150$1850_Y + connect \$212 $reduce_or$libresoc.v:42151$1851_Y + connect \$216 $ne$libresoc.v:42152$1852_Y + connect \$219 $sub$libresoc.v:42153$1853_Y + connect \$221 $ne$libresoc.v:42154$1854_Y + connect \$224 $and$libresoc.v:42155$1855_Y + connect \$226 $and$libresoc.v:42156$1856_Y + connect \$228 $eq$libresoc.v:42157$1857_Y + connect \$230 $or$libresoc.v:42158$1858_Y + connect \$232 $and$libresoc.v:42159$1859_Y + connect \$234 $or$libresoc.v:42160$1860_Y + connect \$236 $eq$libresoc.v:42161$1861_Y + connect \$238 $and$libresoc.v:42162$1862_Y + connect \$240 $eq$libresoc.v:42163$1863_Y + connect \$242 $or$libresoc.v:42164$1864_Y + connect \$223 $not$libresoc.v:42165$1865_Y + connect \$245 $not$libresoc.v:42166$1866_Y + connect \$247 $not$libresoc.v:42167$1867_Y + connect \$249 $not$libresoc.v:42168$1868_Y + connect \$252 $and$libresoc.v:42169$1869_Y + connect \$254 $and$libresoc.v:42170$1870_Y + connect \$256 $eq$libresoc.v:42171$1871_Y + connect \$258 $or$libresoc.v:42172$1872_Y + connect \$260 $and$libresoc.v:42173$1873_Y + connect \$262 $or$libresoc.v:42174$1874_Y + connect \$251 $not$libresoc.v:42175$1875_Y + connect \$266 $and$libresoc.v:42176$1876_Y + connect \$268 $and$libresoc.v:42177$1877_Y + connect \$270 $eq$libresoc.v:42178$1878_Y + connect \$272 $or$libresoc.v:42179$1879_Y + connect \$274 $and$libresoc.v:42180$1880_Y + connect \$276 $or$libresoc.v:42181$1881_Y + connect \$278 $and$libresoc.v:42182$1882_Y + connect \$280 $and$libresoc.v:42183$1883_Y + connect \$282 $eq$libresoc.v:42184$1884_Y + connect \$284 $or$libresoc.v:42185$1885_Y + connect \$286 $eq$libresoc.v:42186$1886_Y + connect \$288 $and$libresoc.v:42187$1887_Y + connect \$290 $eq$libresoc.v:42188$1888_Y + connect \$292 $or$libresoc.v:42189$1889_Y + connect \$265 $not$libresoc.v:42190$1890_Y + connect \$296 $and$libresoc.v:42191$1891_Y + connect \$298 $and$libresoc.v:42192$1892_Y + connect \$300 $eq$libresoc.v:42193$1893_Y + connect \$302 $or$libresoc.v:42194$1894_Y + connect \$304 $and$libresoc.v:42195$1895_Y + connect \$306 $or$libresoc.v:42196$1896_Y + connect \$295 $not$libresoc.v:42197$1897_Y + connect \$310 $and$libresoc.v:42198$1898_Y + connect \$312 $and$libresoc.v:42199$1899_Y + connect \$314 $eq$libresoc.v:42200$1900_Y + connect \$316 $or$libresoc.v:42201$1901_Y + connect \$318 $and$libresoc.v:42202$1902_Y + connect \$320 $or$libresoc.v:42203$1903_Y + connect \$309 $not$libresoc.v:42204$1904_Y + connect \$324 $and$libresoc.v:42205$1905_Y + connect \$326 $and$libresoc.v:42206$1906_Y + connect \$328 $eq$libresoc.v:42207$1907_Y + connect \$330 $or$libresoc.v:42208$1908_Y + connect \$332 $and$libresoc.v:42209$1909_Y + connect \$334 $or$libresoc.v:42210$1910_Y + connect \$336 $eq$libresoc.v:42211$1911_Y + connect \$338 $and$libresoc.v:42212$1912_Y + connect \$340 $eq$libresoc.v:42213$1913_Y + connect \$342 $or$libresoc.v:42214$1914_Y + connect \$323 $not$libresoc.v:42215$1915_Y + connect \$345 $not$libresoc.v:42216$1916_Y + connect \$347 $and$libresoc.v:42217$1917_Y + connect \$349 $and$libresoc.v:42218$1918_Y + connect \$351 $not$libresoc.v:42219$1919_Y + connect \$353 $and$libresoc.v:42220$1920_Y + connect \$355 $and$libresoc.v:42221$1921_Y + connect \$357 $ternary$libresoc.v:42222$1922_Y + connect \$359 $and$libresoc.v:42223$1923_Y + connect \$361 $and$libresoc.v:42224$1924_Y + connect \$363 $not$libresoc.v:42225$1925_Y + connect \$365 $and$libresoc.v:42226$1926_Y + connect \$367 $and$libresoc.v:42227$1927_Y + connect \$369 $ternary$libresoc.v:42228$1928_Y + connect \$371 $and$libresoc.v:42229$1929_Y + connect \$373 $and$libresoc.v:42230$1930_Y + connect \$375 $not$libresoc.v:42231$1931_Y + connect \$377 $and$libresoc.v:42232$1932_Y + connect \$379 $and$libresoc.v:42233$1933_Y + connect \$381 $ternary$libresoc.v:42234$1934_Y + connect \$383 $and$libresoc.v:42235$1935_Y + connect \$385 $and$libresoc.v:42236$1936_Y + connect \$387 $not$libresoc.v:42237$1937_Y + connect \$389 $and$libresoc.v:42238$1938_Y + connect \$391 $and$libresoc.v:42239$1939_Y + connect \$393 $ternary$libresoc.v:42240$1940_Y + connect \$395 $and$libresoc.v:42241$1941_Y + connect \$397 $and$libresoc.v:42242$1942_Y + connect \$399 $not$libresoc.v:42243$1943_Y + connect \$401 $and$libresoc.v:42244$1944_Y + connect \$403 $and$libresoc.v:42245$1945_Y + connect \$405 $ternary$libresoc.v:42246$1946_Y + connect \$407 $and$libresoc.v:42247$1947_Y + connect \$409 $and$libresoc.v:42248$1948_Y + connect \$411 $not$libresoc.v:42249$1949_Y + connect \$413 $and$libresoc.v:42250$1950_Y + connect \$415 $and$libresoc.v:42251$1951_Y + connect \$417 $ternary$libresoc.v:42252$1952_Y + connect \$419 $and$libresoc.v:42253$1953_Y + connect \$421 $and$libresoc.v:42254$1954_Y + connect \$423 $not$libresoc.v:42255$1955_Y + connect \$425 $and$libresoc.v:42256$1956_Y + connect \$427 $and$libresoc.v:42257$1957_Y + connect \$429 $ternary$libresoc.v:42258$1958_Y + connect \$431 $and$libresoc.v:42259$1959_Y + connect \$433 $and$libresoc.v:42260$1960_Y + connect \$435 $not$libresoc.v:42261$1961_Y + connect \$437 $and$libresoc.v:42262$1962_Y + connect \$439 $and$libresoc.v:42263$1963_Y + connect \$441 $ternary$libresoc.v:42264$1964_Y + connect \$443 $and$libresoc.v:42265$1965_Y + connect \$445 $and$libresoc.v:42266$1966_Y + connect \$447 $not$libresoc.v:42267$1967_Y + connect \$449 $and$libresoc.v:42268$1968_Y + connect \$451 $and$libresoc.v:42269$1969_Y + connect \$453 $ternary$libresoc.v:42270$1970_Y + connect \$456 $or$libresoc.v:42271$1971_Y + connect \$458 $or$libresoc.v:42272$1972_Y + connect \$460 $or$libresoc.v:42273$1973_Y + connect \$462 $or$libresoc.v:42274$1974_Y + connect \$464 $or$libresoc.v:42275$1975_Y + connect \$466 $or$libresoc.v:42276$1976_Y + connect \$468 $or$libresoc.v:42277$1977_Y + connect \$470 $or$libresoc.v:42278$1978_Y + connect \$472 $reduce_or$libresoc.v:42279$1979_Y + connect \$474 $and$libresoc.v:42280$1980_Y + connect \$476 $and$libresoc.v:42281$1981_Y + connect \$478 $not$libresoc.v:42282$1982_Y + connect \$480 $and$libresoc.v:42283$1983_Y + connect \$482 $and$libresoc.v:42284$1984_Y + connect \$484 $ternary$libresoc.v:42285$1985_Y + connect \$486 $and$libresoc.v:42286$1986_Y + connect \$488 $and$libresoc.v:42287$1987_Y + connect \$490 $not$libresoc.v:42288$1988_Y + connect \$492 $and$libresoc.v:42289$1989_Y + connect \$494 $and$libresoc.v:42290$1990_Y + connect \$496 $ternary$libresoc.v:42291$1991_Y + connect \$498 $and$libresoc.v:42292$1992_Y + connect \$500 $and$libresoc.v:42293$1993_Y + connect \$502 $not$libresoc.v:42294$1994_Y + connect \$504 $and$libresoc.v:42295$1995_Y + connect \$506 $and$libresoc.v:42296$1996_Y + connect \$508 $ternary$libresoc.v:42297$1997_Y + connect \$510 $and$libresoc.v:42298$1998_Y + connect \$512 $and$libresoc.v:42299$1999_Y + connect \$514 $not$libresoc.v:42300$2000_Y + connect \$516 $and$libresoc.v:42301$2001_Y + connect \$518 $and$libresoc.v:42302$2002_Y + connect \$520 $ternary$libresoc.v:42303$2003_Y + connect \$522 $and$libresoc.v:42304$2004_Y + connect \$524 $and$libresoc.v:42305$2005_Y + connect \$526 $not$libresoc.v:42306$2006_Y + connect \$528 $and$libresoc.v:42307$2007_Y + connect \$530 $and$libresoc.v:42308$2008_Y + connect \$532 $ternary$libresoc.v:42309$2009_Y + connect \$534 $and$libresoc.v:42310$2010_Y + connect \$536 $and$libresoc.v:42311$2011_Y + connect \$538 $not$libresoc.v:42312$2012_Y + connect \$540 $and$libresoc.v:42313$2013_Y + connect \$542 $and$libresoc.v:42314$2014_Y + connect \$544 $ternary$libresoc.v:42315$2015_Y + connect \$546 $and$libresoc.v:42316$2016_Y + connect \$548 $and$libresoc.v:42317$2017_Y + connect \$550 $not$libresoc.v:42318$2018_Y + connect \$552 $and$libresoc.v:42319$2019_Y + connect \$554 $and$libresoc.v:42320$2020_Y + connect \$556 $ternary$libresoc.v:42321$2021_Y + connect \$558 $and$libresoc.v:42322$2022_Y + connect \$560 $and$libresoc.v:42323$2023_Y + connect \$562 $not$libresoc.v:42324$2024_Y + connect \$564 $and$libresoc.v:42325$2025_Y + connect \$566 $and$libresoc.v:42326$2026_Y + connect \$568 $ternary$libresoc.v:42327$2027_Y + connect \$571 $or$libresoc.v:42328$2028_Y + connect \$573 $or$libresoc.v:42329$2029_Y + connect \$575 $or$libresoc.v:42330$2030_Y + connect \$577 $or$libresoc.v:42331$2031_Y + connect \$579 $or$libresoc.v:42332$2032_Y + connect \$581 $or$libresoc.v:42333$2033_Y + connect \$583 $or$libresoc.v:42334$2034_Y + connect \$585 $reduce_or$libresoc.v:42335$2035_Y + connect \$587 $and$libresoc.v:42336$2036_Y + connect \$589 $and$libresoc.v:42337$2037_Y + connect \$591 $not$libresoc.v:42338$2038_Y + connect \$593 $and$libresoc.v:42339$2039_Y + connect \$595 $and$libresoc.v:42340$2040_Y + connect \$597 $ternary$libresoc.v:42341$2041_Y + connect \$599 $and$libresoc.v:42342$2042_Y + connect \$601 $and$libresoc.v:42343$2043_Y + connect \$603 $not$libresoc.v:42344$2044_Y + connect \$605 $and$libresoc.v:42345$2045_Y + connect \$607 $and$libresoc.v:42346$2046_Y + connect \$609 $ternary$libresoc.v:42347$2047_Y + connect \$612 $or$libresoc.v:42348$2048_Y + connect \$614 $reduce_or$libresoc.v:42349$2049_Y + connect \$616 $and$libresoc.v:42350$2050_Y + connect \$618 $and$libresoc.v:42351$2051_Y + connect \$620 $eq$libresoc.v:42352$2052_Y + connect \$622 $or$libresoc.v:42353$2053_Y + connect \$624 $and$libresoc.v:42354$2054_Y + connect \$626 $or$libresoc.v:42355$2055_Y + connect \$628 $and$libresoc.v:42356$2056_Y + connect \$630 $and$libresoc.v:42357$2057_Y + connect \$632 $not$libresoc.v:42358$2058_Y + connect \$634 $and$libresoc.v:42359$2059_Y + connect \$636 $and$libresoc.v:42360$2060_Y + connect \$638 $ternary$libresoc.v:42361$2061_Y + connect \$640 $and$libresoc.v:42362$2062_Y + connect \$642 $and$libresoc.v:42363$2063_Y + connect \$644 $not$libresoc.v:42364$2064_Y + connect \$646 $and$libresoc.v:42365$2065_Y + connect \$648 $and$libresoc.v:42366$2066_Y + connect \$650 $ternary$libresoc.v:42367$2067_Y + connect \$652 $and$libresoc.v:42368$2068_Y + connect \$654 $and$libresoc.v:42369$2069_Y + connect \$656 $not$libresoc.v:42370$2070_Y + connect \$658 $and$libresoc.v:42371$2071_Y + connect \$660 $and$libresoc.v:42372$2072_Y + connect \$662 $ternary$libresoc.v:42373$2073_Y + connect \$664 $and$libresoc.v:42374$2074_Y + connect \$666 $and$libresoc.v:42375$2075_Y + connect \$668 $not$libresoc.v:42376$2076_Y + connect \$670 $and$libresoc.v:42377$2077_Y + connect \$672 $and$libresoc.v:42378$2078_Y + connect \$674 $ternary$libresoc.v:42379$2079_Y + connect \$676 $and$libresoc.v:42380$2080_Y + connect \$678 $and$libresoc.v:42381$2081_Y + connect \$680 $not$libresoc.v:42382$2082_Y + connect \$682 $and$libresoc.v:42383$2083_Y + connect \$684 $and$libresoc.v:42384$2084_Y + connect \$686 $ternary$libresoc.v:42385$2085_Y + connect \$688 $and$libresoc.v:42386$2086_Y + connect \$690 $and$libresoc.v:42387$2087_Y + connect \$692 $not$libresoc.v:42388$2088_Y + connect \$694 $and$libresoc.v:42389$2089_Y + connect \$696 $and$libresoc.v:42390$2090_Y + connect \$698 $ternary$libresoc.v:42391$2091_Y + connect \$701 $or$libresoc.v:42392$2092_Y + connect \$703 $or$libresoc.v:42393$2093_Y + connect \$705 $or$libresoc.v:42394$2094_Y + connect \$707 $or$libresoc.v:42395$2095_Y + connect \$709 $or$libresoc.v:42396$2096_Y + connect \$700 $pos$libresoc.v:42397$2098_Y + connect \$712 $eq$libresoc.v:42398$2099_Y + connect \$714 $and$libresoc.v:42399$2100_Y + connect \$716 $eq$libresoc.v:42400$2101_Y + connect \$718 $or$libresoc.v:42401$2102_Y + connect \$720 $and$libresoc.v:42402$2103_Y + connect \$722 $and$libresoc.v:42403$2104_Y + connect \$724 $not$libresoc.v:42404$2105_Y + connect \$726 $and$libresoc.v:42405$2106_Y + connect \$728 $and$libresoc.v:42406$2107_Y + connect \$730 $ternary$libresoc.v:42407$2108_Y + connect \$732 $and$libresoc.v:42408$2109_Y + connect \$734 $and$libresoc.v:42409$2110_Y + connect \$736 $not$libresoc.v:42410$2111_Y + connect \$738 $and$libresoc.v:42411$2112_Y + connect \$740 $and$libresoc.v:42412$2113_Y + connect \$742 $ternary$libresoc.v:42413$2114_Y + connect \$744 $and$libresoc.v:42414$2115_Y + connect \$746 $and$libresoc.v:42415$2116_Y + connect \$748 $not$libresoc.v:42416$2117_Y + connect \$750 $and$libresoc.v:42417$2118_Y + connect \$752 $and$libresoc.v:42418$2119_Y + connect \$754 $ternary$libresoc.v:42419$2120_Y + connect \$757 $or$libresoc.v:42420$2121_Y + connect \$759 $or$libresoc.v:42421$2122_Y + connect \$756 $pos$libresoc.v:42422$2124_Y + connect \$762 $and$libresoc.v:42423$2125_Y + connect \$764 $and$libresoc.v:42424$2126_Y + connect \$766 $eq$libresoc.v:42425$2127_Y + connect \$768 $or$libresoc.v:42426$2128_Y + connect \$770 $and$libresoc.v:42427$2129_Y + connect \$772 $and$libresoc.v:42428$2130_Y + connect \$774 $not$libresoc.v:42429$2131_Y + connect \$776 $and$libresoc.v:42430$2132_Y + connect \$778 $and$libresoc.v:42431$2133_Y + connect \$780 $ternary$libresoc.v:42432$2134_Y + connect \$782 $and$libresoc.v:42433$2135_Y + connect \$784 $and$libresoc.v:42434$2136_Y + connect \$786 $not$libresoc.v:42435$2137_Y + connect \$788 $and$libresoc.v:42436$2138_Y + connect \$790 $and$libresoc.v:42437$2139_Y + connect \$792 $ternary$libresoc.v:42438$2140_Y + connect \$794 $and$libresoc.v:42439$2141_Y + connect \$796 $and$libresoc.v:42440$2142_Y + connect \$798 $not$libresoc.v:42441$2143_Y + connect \$800 $and$libresoc.v:42442$2144_Y + connect \$802 $and$libresoc.v:42443$2145_Y + connect \$804 $sub$libresoc.v:42444$2146_Y + connect \$806 $sshl$libresoc.v:42445$2147_Y + connect \$808 $ternary$libresoc.v:42446$2148_Y + connect \$810 $and$libresoc.v:42447$2149_Y + connect \$812 $and$libresoc.v:42448$2150_Y + connect \$814 $not$libresoc.v:42449$2151_Y + connect \$816 $and$libresoc.v:42450$2152_Y + connect \$818 $and$libresoc.v:42451$2153_Y + connect \$820 $sub$libresoc.v:42452$2154_Y + connect \$822 $sshl$libresoc.v:42453$2155_Y + connect \$824 $ternary$libresoc.v:42454$2156_Y + connect \$827 $or$libresoc.v:42455$2157_Y + connect \$829 $and$libresoc.v:42456$2158_Y + connect \$831 $and$libresoc.v:42457$2159_Y + connect \$833 $not$libresoc.v:42458$2160_Y + connect \$835 $and$libresoc.v:42459$2161_Y + connect \$837 $and$libresoc.v:42460$2162_Y + connect \$839 $sub$libresoc.v:42461$2163_Y + connect \$841 $sshl$libresoc.v:42462$2164_Y + connect \$843 $ternary$libresoc.v:42463$2165_Y + connect \$845 $and$libresoc.v:42464$2166_Y + connect \$847 $and$libresoc.v:42465$2167_Y + connect \$849 $not$libresoc.v:42466$2168_Y + connect \$851 $and$libresoc.v:42467$2169_Y + connect \$853 $and$libresoc.v:42468$2170_Y + connect \$855 $sub$libresoc.v:42469$2171_Y + connect \$857 $sshl$libresoc.v:42470$2172_Y + connect \$859 $ternary$libresoc.v:42471$2173_Y + connect \$861 $and$libresoc.v:42472$2174_Y + connect \$863 $and$libresoc.v:42473$2175_Y + connect \$865 $not$libresoc.v:42474$2176_Y + connect \$867 $and$libresoc.v:42475$2177_Y + connect \$869 $and$libresoc.v:42476$2178_Y + connect \$871 $ternary$libresoc.v:42477$2179_Y + connect \$873 $and$libresoc.v:42478$2180_Y + connect \$875 $and$libresoc.v:42479$2181_Y + connect \$877 $not$libresoc.v:42480$2182_Y + connect \$879 $and$libresoc.v:42481$2183_Y + connect \$881 $and$libresoc.v:42482$2184_Y + connect \$883 $ternary$libresoc.v:42483$2185_Y + connect \$885 $and$libresoc.v:42484$2186_Y + connect \$887 $and$libresoc.v:42485$2187_Y + connect \$889 $not$libresoc.v:42486$2188_Y + connect \$891 $and$libresoc.v:42487$2189_Y + connect \$893 $and$libresoc.v:42488$2190_Y + connect \$895 $ternary$libresoc.v:42489$2191_Y + connect \$897 $or$libresoc.v:42490$2192_Y + connect \$899 $or$libresoc.v:42491$2193_Y + connect \$901 $reduce_or$libresoc.v:42492$2194_Y + connect \$903 $and$libresoc.v:42493$2195_Y + connect \$905 $and$libresoc.v:42494$2196_Y + connect \$907 $not$libresoc.v:42495$2197_Y + connect \$909 $and$libresoc.v:42496$2198_Y + connect \$911 $and$libresoc.v:42497$2199_Y + connect \$913 $ternary$libresoc.v:42498$2200_Y + connect \$915 $and$libresoc.v:42499$2201_Y + connect \$917 $and$libresoc.v:42500$2202_Y + connect \$919 $not$libresoc.v:42501$2203_Y + connect \$921 $and$libresoc.v:42502$2204_Y + connect \$923 $and$libresoc.v:42503$2205_Y + connect \$925 $ternary$libresoc.v:42504$2206_Y + connect \$927 $or$libresoc.v:42505$2207_Y + connect \$929 $reduce_or$libresoc.v:42506$2208_Y + connect \$931 $and$libresoc.v:42507$2209_Y + connect \$933 $and$libresoc.v:42508$2210_Y + connect \$935 $not$libresoc.v:42509$2211_Y + connect \$937 $and$libresoc.v:42510$2212_Y + connect \$939 $and$libresoc.v:42511$2213_Y + connect \$941 $ternary$libresoc.v:42512$2214_Y + connect \$943 $reduce_or$libresoc.v:42513$2215_Y + connect \$945 $and$libresoc.v:42514$2216_Y + connect \$947 $and$libresoc.v:42515$2217_Y + connect \$949 $and$libresoc.v:42516$2218_Y + connect \$951 $and$libresoc.v:42517$2219_Y + connect \$953 $and$libresoc.v:42518$2220_Y + connect \$955 $and$libresoc.v:42519$2221_Y + connect \$957 $and$libresoc.v:42520$2222_Y + connect \$959 $and$libresoc.v:42521$2223_Y + connect \$961 $and$libresoc.v:42522$2224_Y + connect \$963 $and$libresoc.v:42523$2225_Y + connect \$965 $and$libresoc.v:42524$2226_Y + connect \$967 $and$libresoc.v:42525$2227_Y + connect \$969 $not$libresoc.v:42526$2228_Y + connect \$971 $and$libresoc.v:42527$2229_Y + connect \$977 $and$libresoc.v:42528$2230_Y + connect \$979 $ternary$libresoc.v:42529$2231_Y + connect \$981 $and$libresoc.v:42530$2232_Y + connect \$984 $and$libresoc.v:42531$2233_Y + connect \$988 $not$libresoc.v:42532$2234_Y + connect \$990 $and$libresoc.v:42533$2235_Y + connect \$995 $and$libresoc.v:42534$2236_Y + connect \$998 $ternary$libresoc.v:42535$2237_Y connect \$218 \$219 connect \$455 \$470 connect \$570 \$583 @@ -85478,97 +85480,97 @@ module \core connect \dec_ALU_bigendian \bigendian_i connect \dec_ALU_raw_opcode_in \raw_insn_i end -attribute \src "libresoc.v:48838.1-49471.10" +attribute \src "libresoc.v:48840.1-49473.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr" attribute \generator "nMigen" module \cr - attribute \src "libresoc.v:48839.7-48839.20" + attribute \src "libresoc.v:48841.7-48841.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49385.3-49393.6" + attribute \src "libresoc.v:49387.3-49395.6" wire width 8 $0\ren_delay$17$next[7:0]$3046 - attribute \src "libresoc.v:49221.3-49222.43" + attribute \src "libresoc.v:49223.3-49224.43" wire width 8 $0\ren_delay$17[7:0]$3043 - attribute \src "libresoc.v:49167.13-49167.35" + attribute \src "libresoc.v:49169.13-49169.35" wire width 8 $0\ren_delay$17[7:0]$3060 - attribute \src "libresoc.v:49404.3-49412.6" + attribute \src "libresoc.v:49406.3-49414.6" wire width 8 $0\ren_delay$34$next[7:0]$3050 - attribute \src "libresoc.v:49219.3-49220.43" + attribute \src "libresoc.v:49221.3-49222.43" wire width 8 $0\ren_delay$34[7:0]$3041 - attribute \src "libresoc.v:49171.13-49171.35" + attribute \src "libresoc.v:49173.13-49173.35" wire width 8 $0\ren_delay$34[7:0]$3062 - attribute \src "libresoc.v:49423.3-49431.6" + attribute \src "libresoc.v:49425.3-49433.6" wire width 8 $0\ren_delay$next[7:0]$3054 - attribute \src "libresoc.v:49223.3-49224.35" + attribute \src "libresoc.v:49225.3-49226.35" wire width 8 $0\ren_delay[7:0] - attribute \src "libresoc.v:49432.3-49441.6" + attribute \src "libresoc.v:49434.3-49443.6" wire width 4 $0\src1__data_o[3:0] - attribute \src "libresoc.v:49394.3-49403.6" + attribute \src "libresoc.v:49396.3-49405.6" wire width 4 $0\src2__data_o[3:0] - attribute \src "libresoc.v:49413.3-49422.6" + attribute \src "libresoc.v:49415.3-49424.6" wire width 4 $0\src3__data_o[3:0] - attribute \src "libresoc.v:49385.3-49393.6" + attribute \src "libresoc.v:49387.3-49395.6" wire width 8 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49404.3-49412.6" + attribute \src "libresoc.v:49406.3-49414.6" wire width 8 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49423.3-49431.6" + attribute \src "libresoc.v:49425.3-49433.6" wire width 8 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49165.13-49165.30" + attribute \src "libresoc.v:49167.13-49167.30" wire width 8 $1\ren_delay[7:0] - attribute \src "libresoc.v:49432.3-49441.6" + attribute \src "libresoc.v:49434.3-49443.6" wire width 4 $1\src1__data_o[3:0] - attribute \src "libresoc.v:49394.3-49403.6" + attribute \src "libresoc.v:49396.3-49405.6" wire width 4 $1\src2__data_o[3:0] - attribute \src "libresoc.v:49413.3-49422.6" + attribute \src "libresoc.v:49415.3-49424.6" wire width 4 $1\src3__data_o[3:0] - attribute \src "libresoc.v:49195.17-49195.125" - wire width 4 $or$libresoc.v:49195$3016_Y - attribute \src "libresoc.v:49196.18-49196.126" - wire width 4 $or$libresoc.v:49196$3017_Y - attribute \src "libresoc.v:49197.18-49197.96" - wire width 4 $or$libresoc.v:49197$3018_Y - attribute \src "libresoc.v:49198.18-49198.96" - wire width 4 $or$libresoc.v:49198$3019_Y - attribute \src "libresoc.v:49201.18-49201.126" - wire width 4 $or$libresoc.v:49201$3022_Y - attribute \src "libresoc.v:49202.18-49202.126" - wire width 4 $or$libresoc.v:49202$3023_Y - attribute \src "libresoc.v:49203.18-49203.97" - wire width 4 $or$libresoc.v:49203$3024_Y + attribute \src "libresoc.v:49197.17-49197.125" + wire width 4 $or$libresoc.v:49197$3016_Y + attribute \src "libresoc.v:49198.18-49198.126" + wire width 4 $or$libresoc.v:49198$3017_Y + attribute \src "libresoc.v:49199.18-49199.96" + wire width 4 $or$libresoc.v:49199$3018_Y + attribute \src "libresoc.v:49200.18-49200.96" + wire width 4 $or$libresoc.v:49200$3019_Y + attribute \src "libresoc.v:49203.18-49203.126" + wire width 4 $or$libresoc.v:49203$3022_Y attribute \src "libresoc.v:49204.18-49204.126" - wire width 4 $or$libresoc.v:49204$3025_Y - attribute \src "libresoc.v:49205.18-49205.126" - wire width 4 $or$libresoc.v:49205$3026_Y - attribute \src "libresoc.v:49206.18-49206.97" - wire width 4 $or$libresoc.v:49206$3027_Y - attribute \src "libresoc.v:49207.18-49207.97" - wire width 4 $or$libresoc.v:49207$3028_Y - attribute \src "libresoc.v:49209.18-49209.126" - wire width 4 $or$libresoc.v:49209$3030_Y - attribute \src "libresoc.v:49210.17-49210.125" - wire width 4 $or$libresoc.v:49210$3031_Y + wire width 4 $or$libresoc.v:49204$3023_Y + attribute \src "libresoc.v:49205.18-49205.97" + wire width 4 $or$libresoc.v:49205$3024_Y + attribute \src "libresoc.v:49206.18-49206.126" + wire width 4 $or$libresoc.v:49206$3025_Y + attribute \src "libresoc.v:49207.18-49207.126" + wire width 4 $or$libresoc.v:49207$3026_Y + attribute \src "libresoc.v:49208.18-49208.97" + wire width 4 $or$libresoc.v:49208$3027_Y + attribute \src "libresoc.v:49209.18-49209.97" + wire width 4 $or$libresoc.v:49209$3028_Y attribute \src "libresoc.v:49211.18-49211.126" - wire width 4 $or$libresoc.v:49211$3032_Y - attribute \src "libresoc.v:49212.18-49212.97" - wire width 4 $or$libresoc.v:49212$3033_Y + wire width 4 $or$libresoc.v:49211$3030_Y + attribute \src "libresoc.v:49212.17-49212.125" + wire width 4 $or$libresoc.v:49212$3031_Y attribute \src "libresoc.v:49213.18-49213.126" - wire width 4 $or$libresoc.v:49213$3034_Y - attribute \src "libresoc.v:49214.18-49214.126" - wire width 4 $or$libresoc.v:49214$3035_Y - attribute \src "libresoc.v:49215.18-49215.97" - wire width 4 $or$libresoc.v:49215$3036_Y - attribute \src "libresoc.v:49216.18-49216.97" - wire width 4 $or$libresoc.v:49216$3037_Y - attribute \src "libresoc.v:49217.17-49217.125" - wire width 4 $or$libresoc.v:49217$3038_Y - attribute \src "libresoc.v:49218.17-49218.94" - wire width 4 $or$libresoc.v:49218$3039_Y - attribute \src "libresoc.v:49199.18-49199.100" - wire $reduce_or$libresoc.v:49199$3020_Y - attribute \src "libresoc.v:49200.17-49200.95" - wire $reduce_or$libresoc.v:49200$3021_Y - attribute \src "libresoc.v:49208.18-49208.100" - wire $reduce_or$libresoc.v:49208$3029_Y + wire width 4 $or$libresoc.v:49213$3032_Y + attribute \src "libresoc.v:49214.18-49214.97" + wire width 4 $or$libresoc.v:49214$3033_Y + attribute \src "libresoc.v:49215.18-49215.126" + wire width 4 $or$libresoc.v:49215$3034_Y + attribute \src "libresoc.v:49216.18-49216.126" + wire width 4 $or$libresoc.v:49216$3035_Y + attribute \src "libresoc.v:49217.18-49217.97" + wire width 4 $or$libresoc.v:49217$3036_Y + attribute \src "libresoc.v:49218.18-49218.97" + wire width 4 $or$libresoc.v:49218$3037_Y + attribute \src "libresoc.v:49219.17-49219.125" + wire width 4 $or$libresoc.v:49219$3038_Y + attribute \src "libresoc.v:49220.17-49220.94" + wire width 4 $or$libresoc.v:49220$3039_Y + attribute \src "libresoc.v:49201.18-49201.100" + wire $reduce_or$libresoc.v:49201$3020_Y + attribute \src "libresoc.v:49202.17-49202.95" + wire $reduce_or$libresoc.v:49202$3021_Y + attribute \src "libresoc.v:49210.18-49210.100" + wire $reduce_or$libresoc.v:49210$3029_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -85617,9 +85619,9 @@ module \cr wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 14 \data_i @@ -85637,7 +85639,7 @@ module \cr wire width 32 input 12 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 13 \full_wr__wen - attribute \src "libresoc.v:48839.7-48839.15" + attribute \src "libresoc.v:48841.7-48841.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_dest10__data_i @@ -85924,7 +85926,7 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \wen$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49195$3016 + cell $or $or$libresoc.v:49197$3016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85932,10 +85934,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src14__data_o connect \B \reg_5_src15__data_o - connect \Y $or$libresoc.v:49195$3016_Y + connect \Y $or$libresoc.v:49197$3016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49196$3017 + cell $or $or$libresoc.v:49198$3017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85943,10 +85945,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src16__data_o connect \B \reg_7_src17__data_o - connect \Y $or$libresoc.v:49196$3017_Y + connect \Y $or$libresoc.v:49198$3017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49197$3018 + cell $or $or$libresoc.v:49199$3018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85954,10 +85956,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:49197$3018_Y + connect \Y $or$libresoc.v:49199$3018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49198$3019 + cell $or $or$libresoc.v:49200$3019 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85965,10 +85967,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$7 connect \B \$13 - connect \Y $or$libresoc.v:49198$3019_Y + connect \Y $or$libresoc.v:49200$3019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49201$3022 + cell $or $or$libresoc.v:49203$3022 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85976,10 +85978,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src20__data_o connect \B \reg_1_src21__data_o - connect \Y $or$libresoc.v:49201$3022_Y + connect \Y $or$libresoc.v:49203$3022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49202$3023 + cell $or $or$libresoc.v:49204$3023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85987,10 +85989,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src22__data_o connect \B \reg_3_src23__data_o - connect \Y $or$libresoc.v:49202$3023_Y + connect \Y $or$libresoc.v:49204$3023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49203$3024 + cell $or $or$libresoc.v:49205$3024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -85998,10 +86000,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$20 connect \B \$22 - connect \Y $or$libresoc.v:49203$3024_Y + connect \Y $or$libresoc.v:49205$3024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49204$3025 + cell $or $or$libresoc.v:49206$3025 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86009,10 +86011,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src24__data_o connect \B \reg_5_src25__data_o - connect \Y $or$libresoc.v:49204$3025_Y + connect \Y $or$libresoc.v:49206$3025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49205$3026 + cell $or $or$libresoc.v:49207$3026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86020,10 +86022,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src26__data_o connect \B \reg_7_src27__data_o - connect \Y $or$libresoc.v:49205$3026_Y + connect \Y $or$libresoc.v:49207$3026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49206$3027 + cell $or $or$libresoc.v:49208$3027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86031,10 +86033,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:49206$3027_Y + connect \Y $or$libresoc.v:49208$3027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49207$3028 + cell $or $or$libresoc.v:49209$3028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86042,10 +86044,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$24 connect \B \$30 - connect \Y $or$libresoc.v:49207$3028_Y + connect \Y $or$libresoc.v:49209$3028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49209$3030 + cell $or $or$libresoc.v:49211$3030 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86053,10 +86055,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src30__data_o connect \B \reg_1_src31__data_o - connect \Y $or$libresoc.v:49209$3030_Y + connect \Y $or$libresoc.v:49211$3030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49210$3031 + cell $or $or$libresoc.v:49212$3031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86064,10 +86066,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src10__data_o connect \B \reg_1_src11__data_o - connect \Y $or$libresoc.v:49210$3031_Y + connect \Y $or$libresoc.v:49212$3031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49211$3032 + cell $or $or$libresoc.v:49213$3032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86075,10 +86077,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src32__data_o connect \B \reg_3_src33__data_o - connect \Y $or$libresoc.v:49211$3032_Y + connect \Y $or$libresoc.v:49213$3032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49212$3033 + cell $or $or$libresoc.v:49214$3033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86086,10 +86088,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:49212$3033_Y + connect \Y $or$libresoc.v:49214$3033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49213$3034 + cell $or $or$libresoc.v:49215$3034 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86097,10 +86099,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src34__data_o connect \B \reg_5_src35__data_o - connect \Y $or$libresoc.v:49213$3034_Y + connect \Y $or$libresoc.v:49215$3034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49214$3035 + cell $or $or$libresoc.v:49216$3035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86108,10 +86110,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src36__data_o connect \B \reg_7_src37__data_o - connect \Y $or$libresoc.v:49214$3035_Y + connect \Y $or$libresoc.v:49216$3035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49215$3036 + cell $or $or$libresoc.v:49217$3036 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86119,10 +86121,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$43 connect \B \$45 - connect \Y $or$libresoc.v:49215$3036_Y + connect \Y $or$libresoc.v:49217$3036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49216$3037 + cell $or $or$libresoc.v:49218$3037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86130,10 +86132,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$41 connect \B \$47 - connect \Y $or$libresoc.v:49216$3037_Y + connect \Y $or$libresoc.v:49218$3037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49217$3038 + cell $or $or$libresoc.v:49219$3038 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86141,10 +86143,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src12__data_o connect \B \reg_3_src13__data_o - connect \Y $or$libresoc.v:49217$3038_Y + connect \Y $or$libresoc.v:49219$3038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49218$3039 + cell $or $or$libresoc.v:49220$3039 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86152,34 +86154,34 @@ module \cr parameter \Y_WIDTH 4 connect \A \$3 connect \B \$5 - connect \Y $or$libresoc.v:49218$3039_Y + connect \Y $or$libresoc.v:49220$3039_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49199$3020 + cell $reduce_or $reduce_or$libresoc.v:49201$3020 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$17 - connect \Y $reduce_or$libresoc.v:49199$3020_Y + connect \Y $reduce_or$libresoc.v:49201$3020_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49200$3021 + cell $reduce_or $reduce_or$libresoc.v:49202$3021 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:49200$3021_Y + connect \Y $reduce_or$libresoc.v:49202$3021_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49208$3029 + cell $reduce_or $reduce_or$libresoc.v:49210$3029 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$34 - connect \Y $reduce_or$libresoc.v:49208$3029_Y + connect \Y $reduce_or$libresoc.v:49210$3029_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:49225.9-49244.4" + attribute \src "libresoc.v:49227.9-49246.4" cell \reg_0 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86201,7 +86203,7 @@ module \cr connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49245.9-49264.4" + attribute \src "libresoc.v:49247.9-49266.4" cell \reg_1 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86223,7 +86225,7 @@ module \cr connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49265.9-49284.4" + attribute \src "libresoc.v:49267.9-49286.4" cell \reg_2 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86245,7 +86247,7 @@ module \cr connect \w2__wen \reg_2_w2__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49285.9-49304.4" + attribute \src "libresoc.v:49287.9-49306.4" cell \reg_3 \reg_3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86267,7 +86269,7 @@ module \cr connect \w3__wen \reg_3_w3__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49305.9-49324.4" + attribute \src "libresoc.v:49307.9-49326.4" cell \reg_4 \reg_4 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86289,7 +86291,7 @@ module \cr connect \w4__wen \reg_4_w4__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49325.9-49344.4" + attribute \src "libresoc.v:49327.9-49346.4" cell \reg_5 \reg_5 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86311,7 +86313,7 @@ module \cr connect \w5__wen \reg_5_w5__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49345.9-49364.4" + attribute \src "libresoc.v:49347.9-49366.4" cell \reg_6 \reg_6 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86333,7 +86335,7 @@ module \cr connect \w6__wen \reg_6_w6__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49365.9-49384.4" + attribute \src "libresoc.v:49367.9-49386.4" cell \reg_7 \reg_7 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86354,67 +86356,67 @@ module \cr connect \w7__data_i \reg_7_w7__data_i connect \w7__wen \reg_7_w7__wen end - attribute \src "libresoc.v:48839.7-48839.20" - process $proc$libresoc.v:48839$3057 + attribute \src "libresoc.v:48841.7-48841.20" + process $proc$libresoc.v:48841$3057 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49165.13-49165.30" - process $proc$libresoc.v:49165$3058 + attribute \src "libresoc.v:49167.13-49167.30" + process $proc$libresoc.v:49167$3058 assign { } { } assign $1\ren_delay[7:0] 8'00000000 sync always sync init update \ren_delay $1\ren_delay[7:0] end - attribute \src "libresoc.v:49167.13-49167.35" - process $proc$libresoc.v:49167$3059 + attribute \src "libresoc.v:49169.13-49169.35" + process $proc$libresoc.v:49169$3059 assign { } { } assign $0\ren_delay$17[7:0]$3060 8'00000000 sync always sync init update \ren_delay$17 $0\ren_delay$17[7:0]$3060 end - attribute \src "libresoc.v:49171.13-49171.35" - process $proc$libresoc.v:49171$3061 + attribute \src "libresoc.v:49173.13-49173.35" + process $proc$libresoc.v:49173$3061 assign { } { } assign $0\ren_delay$34[7:0]$3062 8'00000000 sync always sync init update \ren_delay$34 $0\ren_delay$34[7:0]$3062 end - attribute \src "libresoc.v:49219.3-49220.43" - process $proc$libresoc.v:49219$3040 + attribute \src "libresoc.v:49221.3-49222.43" + process $proc$libresoc.v:49221$3040 assign { } { } assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next sync posedge \coresync_clk update \ren_delay$34 $0\ren_delay$34[7:0]$3041 end - attribute \src "libresoc.v:49221.3-49222.43" - process $proc$libresoc.v:49221$3042 + attribute \src "libresoc.v:49223.3-49224.43" + process $proc$libresoc.v:49223$3042 assign { } { } assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next sync posedge \coresync_clk update \ren_delay$17 $0\ren_delay$17[7:0]$3043 end - attribute \src "libresoc.v:49223.3-49224.35" - process $proc$libresoc.v:49223$3044 + attribute \src "libresoc.v:49225.3-49226.35" + process $proc$libresoc.v:49225$3044 assign { } { } assign $0\ren_delay[7:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[7:0] end - attribute \src "libresoc.v:49385.3-49393.6" - process $proc$libresoc.v:49385$3045 + attribute \src "libresoc.v:49387.3-49395.6" + process $proc$libresoc.v:49387$3045 assign { } { } assign { } { } assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047 - attribute \src "libresoc.v:49386.5-49386.29" + attribute \src "libresoc.v:49388.5-49388.29" switch \initial - attribute \src "libresoc.v:49386.9-49386.17" + attribute \src "libresoc.v:49388.9-49388.17" case 1'1 case end @@ -86430,14 +86432,14 @@ module \cr sync always update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046 end - attribute \src "libresoc.v:49394.3-49403.6" - process $proc$libresoc.v:49394$3048 + attribute \src "libresoc.v:49396.3-49405.6" + process $proc$libresoc.v:49396$3048 assign { } { } assign { } { } assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "libresoc.v:49395.5-49395.29" + attribute \src "libresoc.v:49397.5-49397.29" switch \initial - attribute \src "libresoc.v:49395.9-49395.17" + attribute \src "libresoc.v:49397.9-49397.17" case 1'1 case end @@ -86453,14 +86455,14 @@ module \cr sync always update \src2__data_o $0\src2__data_o[3:0] end - attribute \src "libresoc.v:49404.3-49412.6" - process $proc$libresoc.v:49404$3049 + attribute \src "libresoc.v:49406.3-49414.6" + process $proc$libresoc.v:49406$3049 assign { } { } assign { } { } assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051 - attribute \src "libresoc.v:49405.5-49405.29" + attribute \src "libresoc.v:49407.5-49407.29" switch \initial - attribute \src "libresoc.v:49405.9-49405.17" + attribute \src "libresoc.v:49407.9-49407.17" case 1'1 case end @@ -86476,14 +86478,14 @@ module \cr sync always update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050 end - attribute \src "libresoc.v:49413.3-49422.6" - process $proc$libresoc.v:49413$3052 + attribute \src "libresoc.v:49415.3-49424.6" + process $proc$libresoc.v:49415$3052 assign { } { } assign { } { } assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "libresoc.v:49414.5-49414.29" + attribute \src "libresoc.v:49416.5-49416.29" switch \initial - attribute \src "libresoc.v:49414.9-49414.17" + attribute \src "libresoc.v:49416.9-49416.17" case 1'1 case end @@ -86499,14 +86501,14 @@ module \cr sync always update \src3__data_o $0\src3__data_o[3:0] end - attribute \src "libresoc.v:49423.3-49431.6" - process $proc$libresoc.v:49423$3053 + attribute \src "libresoc.v:49425.3-49433.6" + process $proc$libresoc.v:49425$3053 assign { } { } assign { } { } assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055 - attribute \src "libresoc.v:49424.5-49424.29" + attribute \src "libresoc.v:49426.5-49426.29" switch \initial - attribute \src "libresoc.v:49424.9-49424.17" + attribute \src "libresoc.v:49426.9-49426.17" case 1'1 case end @@ -86522,14 +86524,14 @@ module \cr sync always update \ren_delay$next $0\ren_delay$next[7:0]$3054 end - attribute \src "libresoc.v:49432.3-49441.6" - process $proc$libresoc.v:49432$3056 + attribute \src "libresoc.v:49434.3-49443.6" + process $proc$libresoc.v:49434$3056 assign { } { } assign { } { } assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "libresoc.v:49433.5-49433.29" + attribute \src "libresoc.v:49435.5-49435.29" switch \initial - attribute \src "libresoc.v:49433.9-49433.17" + attribute \src "libresoc.v:49435.9-49435.17" case 1'1 case end @@ -86545,30 +86547,30 @@ module \cr sync always update \src1__data_o $0\src1__data_o[3:0] end - connect \$9 $or$libresoc.v:49195$3016_Y - connect \$11 $or$libresoc.v:49196$3017_Y - connect \$13 $or$libresoc.v:49197$3018_Y - connect \$15 $or$libresoc.v:49198$3019_Y - connect \$18 $reduce_or$libresoc.v:49199$3020_Y - connect \$1 $reduce_or$libresoc.v:49200$3021_Y - connect \$20 $or$libresoc.v:49201$3022_Y - connect \$22 $or$libresoc.v:49202$3023_Y - connect \$24 $or$libresoc.v:49203$3024_Y - connect \$26 $or$libresoc.v:49204$3025_Y - connect \$28 $or$libresoc.v:49205$3026_Y - connect \$30 $or$libresoc.v:49206$3027_Y - connect \$32 $or$libresoc.v:49207$3028_Y - connect \$35 $reduce_or$libresoc.v:49208$3029_Y - connect \$37 $or$libresoc.v:49209$3030_Y - connect \$3 $or$libresoc.v:49210$3031_Y - connect \$39 $or$libresoc.v:49211$3032_Y - connect \$41 $or$libresoc.v:49212$3033_Y - connect \$43 $or$libresoc.v:49213$3034_Y - connect \$45 $or$libresoc.v:49214$3035_Y - connect \$47 $or$libresoc.v:49215$3036_Y - connect \$49 $or$libresoc.v:49216$3037_Y - connect \$5 $or$libresoc.v:49217$3038_Y - connect \$7 $or$libresoc.v:49218$3039_Y + connect \$9 $or$libresoc.v:49197$3016_Y + connect \$11 $or$libresoc.v:49198$3017_Y + connect \$13 $or$libresoc.v:49199$3018_Y + connect \$15 $or$libresoc.v:49200$3019_Y + connect \$18 $reduce_or$libresoc.v:49201$3020_Y + connect \$1 $reduce_or$libresoc.v:49202$3021_Y + connect \$20 $or$libresoc.v:49203$3022_Y + connect \$22 $or$libresoc.v:49204$3023_Y + connect \$24 $or$libresoc.v:49205$3024_Y + connect \$26 $or$libresoc.v:49206$3025_Y + connect \$28 $or$libresoc.v:49207$3026_Y + connect \$30 $or$libresoc.v:49208$3027_Y + connect \$32 $or$libresoc.v:49209$3028_Y + connect \$35 $reduce_or$libresoc.v:49210$3029_Y + connect \$37 $or$libresoc.v:49211$3030_Y + connect \$3 $or$libresoc.v:49212$3031_Y + connect \$39 $or$libresoc.v:49213$3032_Y + connect \$41 $or$libresoc.v:49214$3033_Y + connect \$43 $or$libresoc.v:49215$3034_Y + connect \$45 $or$libresoc.v:49216$3035_Y + connect \$47 $or$libresoc.v:49217$3036_Y + connect \$49 $or$libresoc.v:49218$3037_Y + connect \$5 $or$libresoc.v:49219$3038_Y + connect \$7 $or$libresoc.v:49220$3039_Y connect \wen$51 8'00000000 connect \data_i$52 4'0000 connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen @@ -86599,393 +86601,393 @@ module \cr connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:49475.1-50528.10" +attribute \src "libresoc.v:49477.1-50530.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" attribute \generator "nMigen" module \cr0 - attribute \src "libresoc.v:50129.3-50130.25" + attribute \src "libresoc.v:50131.3-50132.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:50302.3-50313.6" + attribute \src "libresoc.v:50304.3-50315.6" wire width 13 $0\alu_cr0_cr_op__fn_unit$next[12:0]$3182 - attribute \src "libresoc.v:50101.3-50102.61" + attribute \src "libresoc.v:50103.3-50104.61" wire width 13 $0\alu_cr0_cr_op__fn_unit[12:0] - attribute \src "libresoc.v:50302.3-50313.6" + attribute \src "libresoc.v:50304.3-50315.6" wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183 - attribute \src "libresoc.v:50103.3-50104.55" + attribute \src "libresoc.v:50105.3-50106.55" wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50302.3-50313.6" + attribute \src "libresoc.v:50304.3-50315.6" wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 - attribute \src "libresoc.v:50099.3-50100.65" + attribute \src "libresoc.v:50101.3-50102.65" wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50127.3-50128.39" + attribute \src "libresoc.v:50129.3-50130.39" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:50449.3-50457.6" + attribute \src "libresoc.v:50451.3-50459.6" wire $0\alu_l_r_alu$next[0:0]$3234 - attribute \src "libresoc.v:50071.3-50072.39" + attribute \src "libresoc.v:50073.3-50074.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50440.3-50448.6" + attribute \src "libresoc.v:50442.3-50450.6" wire $0\alui_l_r_alui$next[0:0]$3231 - attribute \src "libresoc.v:50073.3-50074.43" + attribute \src "libresoc.v:50075.3-50076.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50314.3-50335.6" + attribute \src "libresoc.v:50316.3-50337.6" wire width 64 $0\data_r0__o$next[63:0]$3189 - attribute \src "libresoc.v:50095.3-50096.37" + attribute \src "libresoc.v:50097.3-50098.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:50314.3-50335.6" + attribute \src "libresoc.v:50316.3-50337.6" wire $0\data_r0__o_ok$next[0:0]$3190 - attribute \src "libresoc.v:50097.3-50098.43" + attribute \src "libresoc.v:50099.3-50100.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50336.3-50357.6" + attribute \src "libresoc.v:50338.3-50359.6" wire width 32 $0\data_r1__full_cr$next[31:0]$3197 - attribute \src "libresoc.v:50091.3-50092.49" + attribute \src "libresoc.v:50093.3-50094.49" wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50336.3-50357.6" + attribute \src "libresoc.v:50338.3-50359.6" wire $0\data_r1__full_cr_ok$next[0:0]$3198 - attribute \src "libresoc.v:50093.3-50094.55" + attribute \src "libresoc.v:50095.3-50096.55" wire $0\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50358.3-50379.6" + attribute \src "libresoc.v:50360.3-50381.6" wire width 4 $0\data_r2__cr_a$next[3:0]$3205 - attribute \src "libresoc.v:50087.3-50088.43" + attribute \src "libresoc.v:50089.3-50090.43" wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50358.3-50379.6" + attribute \src "libresoc.v:50360.3-50381.6" wire $0\data_r2__cr_a_ok$next[0:0]$3206 - attribute \src "libresoc.v:50089.3-50090.49" + attribute \src "libresoc.v:50091.3-50092.49" wire $0\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50458.3-50467.6" + attribute \src "libresoc.v:50460.3-50469.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:50468.3-50477.6" + attribute \src "libresoc.v:50470.3-50479.6" wire width 32 $0\dest2_o[31:0] - attribute \src "libresoc.v:50478.3-50487.6" + attribute \src "libresoc.v:50480.3-50489.6" wire width 4 $0\dest3_o[3:0] - attribute \src "libresoc.v:49476.7-49476.20" + attribute \src "libresoc.v:49478.7-49478.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50257.3-50265.6" + attribute \src "libresoc.v:50259.3-50267.6" wire $0\opc_l_r_opc$next[0:0]$3167 - attribute \src "libresoc.v:50113.3-50114.39" + attribute \src "libresoc.v:50115.3-50116.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50248.3-50256.6" + attribute \src "libresoc.v:50250.3-50258.6" wire $0\opc_l_s_opc$next[0:0]$3164 - attribute \src "libresoc.v:50115.3-50116.39" + attribute \src "libresoc.v:50117.3-50118.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50488.3-50496.6" + attribute \src "libresoc.v:50490.3-50498.6" wire width 3 $0\prev_wr_go$next[2:0]$3240 - attribute \src "libresoc.v:50125.3-50126.37" + attribute \src "libresoc.v:50127.3-50128.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:50202.3-50211.6" + attribute \src "libresoc.v:50204.3-50213.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:50293.3-50301.6" + attribute \src "libresoc.v:50295.3-50303.6" wire width 3 $0\req_l_r_req$next[2:0]$3179 - attribute \src "libresoc.v:50105.3-50106.39" + attribute \src "libresoc.v:50107.3-50108.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:50284.3-50292.6" + attribute \src "libresoc.v:50286.3-50294.6" wire width 3 $0\req_l_s_req$next[2:0]$3176 - attribute \src "libresoc.v:50107.3-50108.39" + attribute \src "libresoc.v:50109.3-50110.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:50221.3-50229.6" + attribute \src "libresoc.v:50223.3-50231.6" wire $0\rok_l_r_rdok$next[0:0]$3155 - attribute \src "libresoc.v:50121.3-50122.41" + attribute \src "libresoc.v:50123.3-50124.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50212.3-50220.6" + attribute \src "libresoc.v:50214.3-50222.6" wire $0\rok_l_s_rdok$next[0:0]$3152 - attribute \src "libresoc.v:50123.3-50124.41" + attribute \src "libresoc.v:50125.3-50126.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50239.3-50247.6" + attribute \src "libresoc.v:50241.3-50249.6" wire $0\rst_l_r_rst$next[0:0]$3161 - attribute \src "libresoc.v:50117.3-50118.39" + attribute \src "libresoc.v:50119.3-50120.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50230.3-50238.6" + attribute \src "libresoc.v:50232.3-50240.6" wire $0\rst_l_s_rst$next[0:0]$3158 - attribute \src "libresoc.v:50119.3-50120.39" + attribute \src "libresoc.v:50121.3-50122.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50275.3-50283.6" + attribute \src "libresoc.v:50277.3-50285.6" wire width 6 $0\src_l_r_src$next[5:0]$3173 - attribute \src "libresoc.v:50109.3-50110.39" + attribute \src "libresoc.v:50111.3-50112.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:50266.3-50274.6" + attribute \src "libresoc.v:50268.3-50276.6" wire width 6 $0\src_l_s_src$next[5:0]$3170 - attribute \src "libresoc.v:50111.3-50112.39" + attribute \src "libresoc.v:50113.3-50114.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:50380.3-50389.6" + attribute \src "libresoc.v:50382.3-50391.6" wire width 64 $0\src_r0$next[63:0]$3213 - attribute \src "libresoc.v:50085.3-50086.29" + attribute \src "libresoc.v:50087.3-50088.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:50390.3-50399.6" + attribute \src "libresoc.v:50392.3-50401.6" wire width 64 $0\src_r1$next[63:0]$3216 - attribute \src "libresoc.v:50083.3-50084.29" + attribute \src "libresoc.v:50085.3-50086.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:50400.3-50409.6" + attribute \src "libresoc.v:50402.3-50411.6" wire width 32 $0\src_r2$next[31:0]$3219 - attribute \src "libresoc.v:50081.3-50082.29" + attribute \src "libresoc.v:50083.3-50084.29" wire width 32 $0\src_r2[31:0] - attribute \src "libresoc.v:50410.3-50419.6" + attribute \src "libresoc.v:50412.3-50421.6" wire width 4 $0\src_r3$next[3:0]$3222 - attribute \src "libresoc.v:50079.3-50080.29" + attribute \src "libresoc.v:50081.3-50082.29" wire width 4 $0\src_r3[3:0] - attribute \src "libresoc.v:50420.3-50429.6" + attribute \src "libresoc.v:50422.3-50431.6" wire width 4 $0\src_r4$next[3:0]$3225 - attribute \src "libresoc.v:50077.3-50078.29" + attribute \src "libresoc.v:50079.3-50080.29" wire width 4 $0\src_r4[3:0] - attribute \src "libresoc.v:50430.3-50439.6" + attribute \src "libresoc.v:50432.3-50441.6" wire width 4 $0\src_r5$next[3:0]$3228 - attribute \src "libresoc.v:50075.3-50076.29" + attribute \src "libresoc.v:50077.3-50078.29" wire width 4 $0\src_r5[3:0] - attribute \src "libresoc.v:49594.7-49594.24" + attribute \src "libresoc.v:49596.7-49596.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:50302.3-50313.6" + attribute \src "libresoc.v:50304.3-50315.6" wire width 13 $1\alu_cr0_cr_op__fn_unit$next[12:0]$3185 - attribute \src "libresoc.v:49624.14-49624.47" + attribute \src "libresoc.v:49626.14-49626.47" wire width 13 $1\alu_cr0_cr_op__fn_unit[12:0] - attribute \src "libresoc.v:50302.3-50313.6" + attribute \src "libresoc.v:50304.3-50315.6" wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3186 - attribute \src "libresoc.v:49628.14-49628.41" + attribute \src "libresoc.v:49630.14-49630.41" wire width 32 $1\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50302.3-50313.6" + attribute \src "libresoc.v:50304.3-50315.6" wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:49706.13-49706.45" + attribute \src "libresoc.v:49708.13-49708.45" wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:49730.7-49730.26" + attribute \src "libresoc.v:49732.7-49732.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:50449.3-50457.6" + attribute \src "libresoc.v:50451.3-50459.6" wire $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:49738.7-49738.25" + attribute \src "libresoc.v:49740.7-49740.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50440.3-50448.6" + attribute \src "libresoc.v:50442.3-50450.6" wire $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:49750.7-49750.27" + attribute \src "libresoc.v:49752.7-49752.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50314.3-50335.6" + attribute \src "libresoc.v:50316.3-50337.6" wire width 64 $1\data_r0__o$next[63:0]$3191 - attribute \src "libresoc.v:49784.14-49784.47" + attribute \src "libresoc.v:49786.14-49786.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:50314.3-50335.6" + attribute \src "libresoc.v:50316.3-50337.6" wire $1\data_r0__o_ok$next[0:0]$3192 - attribute \src "libresoc.v:49788.7-49788.27" + attribute \src "libresoc.v:49790.7-49790.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50336.3-50357.6" + attribute \src "libresoc.v:50338.3-50359.6" wire width 32 $1\data_r1__full_cr$next[31:0]$3199 - attribute \src "libresoc.v:49792.14-49792.38" + attribute \src "libresoc.v:49794.14-49794.38" wire width 32 $1\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50336.3-50357.6" + attribute \src "libresoc.v:50338.3-50359.6" wire $1\data_r1__full_cr_ok$next[0:0]$3200 - attribute \src "libresoc.v:49796.7-49796.33" + attribute \src "libresoc.v:49798.7-49798.33" wire $1\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50358.3-50379.6" + attribute \src "libresoc.v:50360.3-50381.6" wire width 4 $1\data_r2__cr_a$next[3:0]$3207 - attribute \src "libresoc.v:49800.13-49800.33" + attribute \src "libresoc.v:49802.13-49802.33" wire width 4 $1\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50358.3-50379.6" + attribute \src "libresoc.v:50360.3-50381.6" wire $1\data_r2__cr_a_ok$next[0:0]$3208 - attribute \src "libresoc.v:49804.7-49804.30" + attribute \src "libresoc.v:49806.7-49806.30" wire $1\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50458.3-50467.6" + attribute \src "libresoc.v:50460.3-50469.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:50468.3-50477.6" + attribute \src "libresoc.v:50470.3-50479.6" wire width 32 $1\dest2_o[31:0] - attribute \src "libresoc.v:50478.3-50487.6" + attribute \src "libresoc.v:50480.3-50489.6" wire width 4 $1\dest3_o[3:0] - attribute \src "libresoc.v:50257.3-50265.6" + attribute \src "libresoc.v:50259.3-50267.6" wire $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:49823.7-49823.25" + attribute \src "libresoc.v:49825.7-49825.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50248.3-50256.6" + attribute \src "libresoc.v:50250.3-50258.6" wire $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:49827.7-49827.25" + attribute \src "libresoc.v:49829.7-49829.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50488.3-50496.6" + attribute \src "libresoc.v:50490.3-50498.6" wire width 3 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:49925.13-49925.30" + attribute \src "libresoc.v:49927.13-49927.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:50202.3-50211.6" + attribute \src "libresoc.v:50204.3-50213.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:50293.3-50301.6" + attribute \src "libresoc.v:50295.3-50303.6" wire width 3 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:49933.13-49933.31" + attribute \src "libresoc.v:49935.13-49935.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:50284.3-50292.6" + attribute \src "libresoc.v:50286.3-50294.6" wire width 3 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:49937.13-49937.31" + attribute \src "libresoc.v:49939.13-49939.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:50221.3-50229.6" + attribute \src "libresoc.v:50223.3-50231.6" wire $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:49949.7-49949.26" + attribute \src "libresoc.v:49951.7-49951.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50212.3-50220.6" + attribute \src "libresoc.v:50214.3-50222.6" wire $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:49953.7-49953.26" + attribute \src "libresoc.v:49955.7-49955.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50239.3-50247.6" + attribute \src "libresoc.v:50241.3-50249.6" wire $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:49957.7-49957.25" + attribute \src "libresoc.v:49959.7-49959.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50230.3-50238.6" + attribute \src "libresoc.v:50232.3-50240.6" wire $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:49961.7-49961.25" + attribute \src "libresoc.v:49963.7-49963.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50275.3-50283.6" + attribute \src "libresoc.v:50277.3-50285.6" wire width 6 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:49981.13-49981.32" + attribute \src "libresoc.v:49983.13-49983.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:50266.3-50274.6" + attribute \src "libresoc.v:50268.3-50276.6" wire width 6 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:49985.13-49985.32" + attribute \src "libresoc.v:49987.13-49987.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:50380.3-50389.6" + attribute \src "libresoc.v:50382.3-50391.6" wire width 64 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:49989.14-49989.43" + attribute \src "libresoc.v:49991.14-49991.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:50390.3-50399.6" + attribute \src "libresoc.v:50392.3-50401.6" wire width 64 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:49993.14-49993.43" + attribute \src "libresoc.v:49995.14-49995.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:50400.3-50409.6" + attribute \src "libresoc.v:50402.3-50411.6" wire width 32 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:49997.14-49997.28" + attribute \src "libresoc.v:49999.14-49999.28" wire width 32 $1\src_r2[31:0] - attribute \src "libresoc.v:50410.3-50419.6" + attribute \src "libresoc.v:50412.3-50421.6" wire width 4 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50001.13-50001.26" + attribute \src "libresoc.v:50003.13-50003.26" wire width 4 $1\src_r3[3:0] - attribute \src "libresoc.v:50420.3-50429.6" + attribute \src "libresoc.v:50422.3-50431.6" wire width 4 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50005.13-50005.26" + attribute \src "libresoc.v:50007.13-50007.26" wire width 4 $1\src_r4[3:0] - attribute \src "libresoc.v:50430.3-50439.6" + attribute \src "libresoc.v:50432.3-50441.6" wire width 4 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:50009.13-50009.26" + attribute \src "libresoc.v:50011.13-50011.26" wire width 4 $1\src_r5[3:0] - attribute \src "libresoc.v:50314.3-50335.6" + attribute \src "libresoc.v:50316.3-50337.6" wire width 64 $2\data_r0__o$next[63:0]$3193 - attribute \src "libresoc.v:50314.3-50335.6" + attribute \src "libresoc.v:50316.3-50337.6" wire $2\data_r0__o_ok$next[0:0]$3194 - attribute \src "libresoc.v:50336.3-50357.6" + attribute \src "libresoc.v:50338.3-50359.6" wire width 32 $2\data_r1__full_cr$next[31:0]$3201 - attribute \src "libresoc.v:50336.3-50357.6" + attribute \src "libresoc.v:50338.3-50359.6" wire $2\data_r1__full_cr_ok$next[0:0]$3202 - attribute \src "libresoc.v:50358.3-50379.6" + attribute \src "libresoc.v:50360.3-50381.6" wire width 4 $2\data_r2__cr_a$next[3:0]$3209 - attribute \src "libresoc.v:50358.3-50379.6" + attribute \src "libresoc.v:50360.3-50381.6" wire $2\data_r2__cr_a_ok$next[0:0]$3210 - attribute \src "libresoc.v:50314.3-50335.6" + attribute \src "libresoc.v:50316.3-50337.6" wire $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50336.3-50357.6" + attribute \src "libresoc.v:50338.3-50359.6" wire $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50358.3-50379.6" + attribute \src "libresoc.v:50360.3-50381.6" wire $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:50015.18-50015.112" - wire width 6 $and$libresoc.v:50015$3064_Y - attribute \src "libresoc.v:50016.19-50016.125" - wire $and$libresoc.v:50016$3065_Y - attribute \src "libresoc.v:50017.19-50017.125" - wire $and$libresoc.v:50017$3066_Y + attribute \src "libresoc.v:50017.18-50017.112" + wire width 6 $and$libresoc.v:50017$3064_Y attribute \src "libresoc.v:50018.19-50018.125" - wire $and$libresoc.v:50018$3067_Y - attribute \src "libresoc.v:50019.19-50019.141" - wire width 3 $and$libresoc.v:50019$3068_Y - attribute \src "libresoc.v:50020.19-50020.121" - wire width 3 $and$libresoc.v:50020$3069_Y - attribute \src "libresoc.v:50021.19-50021.127" - wire $and$libresoc.v:50021$3070_Y - attribute \src "libresoc.v:50022.19-50022.127" - wire $and$libresoc.v:50022$3071_Y + wire $and$libresoc.v:50018$3065_Y + attribute \src "libresoc.v:50019.19-50019.125" + wire $and$libresoc.v:50019$3066_Y + attribute \src "libresoc.v:50020.19-50020.125" + wire $and$libresoc.v:50020$3067_Y + attribute \src "libresoc.v:50021.19-50021.141" + wire width 3 $and$libresoc.v:50021$3068_Y + attribute \src "libresoc.v:50022.19-50022.121" + wire width 3 $and$libresoc.v:50022$3069_Y attribute \src "libresoc.v:50023.19-50023.127" - wire $and$libresoc.v:50023$3072_Y - attribute \src "libresoc.v:50024.18-50024.110" - wire $and$libresoc.v:50024$3073_Y - attribute \src "libresoc.v:50026.18-50026.98" - wire $and$libresoc.v:50026$3075_Y - attribute \src "libresoc.v:50028.18-50028.100" - wire $and$libresoc.v:50028$3077_Y - attribute \src "libresoc.v:50029.18-50029.149" - wire width 3 $and$libresoc.v:50029$3078_Y - attribute \src "libresoc.v:50031.18-50031.119" - wire width 3 $and$libresoc.v:50031$3080_Y - attribute \src "libresoc.v:50034.18-50034.116" - wire $and$libresoc.v:50034$3083_Y - attribute \src "libresoc.v:50038.17-50038.123" - wire $and$libresoc.v:50038$3087_Y - attribute \src "libresoc.v:50040.18-50040.113" - wire $and$libresoc.v:50040$3089_Y - attribute \src "libresoc.v:50041.18-50041.125" - wire width 3 $and$libresoc.v:50041$3090_Y - attribute \src "libresoc.v:50043.18-50043.112" - wire $and$libresoc.v:50043$3092_Y - attribute \src "libresoc.v:50045.18-50045.125" - wire $and$libresoc.v:50045$3094_Y - attribute \src "libresoc.v:50046.18-50046.125" - wire $and$libresoc.v:50046$3095_Y - attribute \src "libresoc.v:50047.18-50047.117" - wire $and$libresoc.v:50047$3096_Y - attribute \src "libresoc.v:50052.18-50052.129" - wire $and$libresoc.v:50052$3101_Y - attribute \src "libresoc.v:50053.18-50053.124" - wire width 3 $and$libresoc.v:50053$3102_Y - attribute \src "libresoc.v:50056.18-50056.116" - wire $and$libresoc.v:50056$3105_Y - attribute \src "libresoc.v:50057.18-50057.122" - wire $and$libresoc.v:50057$3106_Y - attribute \src "libresoc.v:50058.18-50058.119" - wire $and$libresoc.v:50058$3107_Y - attribute \src "libresoc.v:50066.18-50066.133" - wire $and$libresoc.v:50066$3115_Y - attribute \src "libresoc.v:50067.18-50067.131" - wire $and$libresoc.v:50067$3116_Y - attribute \src "libresoc.v:50068.18-50068.182" - wire width 6 $and$libresoc.v:50068$3117_Y - attribute \src "libresoc.v:50069.18-50069.113" - wire width 6 $and$libresoc.v:50069$3118_Y + wire $and$libresoc.v:50023$3070_Y + attribute \src "libresoc.v:50024.19-50024.127" + wire $and$libresoc.v:50024$3071_Y + attribute \src "libresoc.v:50025.19-50025.127" + wire $and$libresoc.v:50025$3072_Y + attribute \src "libresoc.v:50026.18-50026.110" + wire $and$libresoc.v:50026$3073_Y + attribute \src "libresoc.v:50028.18-50028.98" + wire $and$libresoc.v:50028$3075_Y + attribute \src "libresoc.v:50030.18-50030.100" + wire $and$libresoc.v:50030$3077_Y + attribute \src "libresoc.v:50031.18-50031.149" + wire width 3 $and$libresoc.v:50031$3078_Y + attribute \src "libresoc.v:50033.18-50033.119" + wire width 3 $and$libresoc.v:50033$3080_Y + attribute \src "libresoc.v:50036.18-50036.116" + wire $and$libresoc.v:50036$3083_Y + attribute \src "libresoc.v:50040.17-50040.123" + wire $and$libresoc.v:50040$3087_Y attribute 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attribute \src "libresoc.v:50043.18-50043.125" + wire width 3 $and$libresoc.v:50043$3090_Y + attribute \src "libresoc.v:50045.18-50045.112" + wire $and$libresoc.v:50045$3092_Y + attribute \src "libresoc.v:50047.18-50047.125" + wire $and$libresoc.v:50047$3094_Y + attribute \src "libresoc.v:50048.18-50048.125" + wire $and$libresoc.v:50048$3095_Y + attribute \src "libresoc.v:50049.18-50049.117" + wire $and$libresoc.v:50049$3096_Y + attribute \src "libresoc.v:50054.18-50054.129" + wire $and$libresoc.v:50054$3101_Y + attribute \src "libresoc.v:50055.18-50055.124" + wire width 3 $and$libresoc.v:50055$3102_Y + attribute \src "libresoc.v:50058.18-50058.116" + wire $and$libresoc.v:50058$3105_Y + attribute \src "libresoc.v:50059.18-50059.122" + wire $and$libresoc.v:50059$3106_Y + attribute \src "libresoc.v:50060.18-50060.119" + wire $and$libresoc.v:50060$3107_Y + attribute \src "libresoc.v:50068.18-50068.133" + wire $and$libresoc.v:50068$3115_Y + attribute \src "libresoc.v:50069.18-50069.131" + wire $and$libresoc.v:50069$3116_Y + attribute \src "libresoc.v:50070.18-50070.182" + wire width 6 $and$libresoc.v:50070$3117_Y + attribute \src "libresoc.v:50071.18-50071.113" + wire width 6 $and$libresoc.v:50071$3118_Y + attribute \src "libresoc.v:50044.18-50044.113" + wire $eq$libresoc.v:50044$3091_Y + attribute \src "libresoc.v:50046.18-50046.119" + wire $eq$libresoc.v:50046$3093_Y + attribute \src "libresoc.v:50027.18-50027.97" + wire $not$libresoc.v:50027$3074_Y + attribute \src "libresoc.v:50029.18-50029.99" + wire $not$libresoc.v:50029$3076_Y + attribute \src "libresoc.v:50032.18-50032.113" + wire width 3 $not$libresoc.v:50032$3079_Y + attribute \src "libresoc.v:50035.18-50035.106" + wire $not$libresoc.v:50035$3082_Y + attribute \src "libresoc.v:50041.18-50041.119" + wire $not$libresoc.v:50041$3088_Y + attribute \src "libresoc.v:50056.17-50056.113" + wire width 6 $not$libresoc.v:50056$3103_Y + attribute \src "libresoc.v:50072.18-50072.114" + wire width 6 $not$libresoc.v:50072$3119_Y + attribute \src "libresoc.v:50039.18-50039.112" + wire $or$libresoc.v:50039$3086_Y + attribute \src "libresoc.v:50050.18-50050.122" + wire $or$libresoc.v:50050$3097_Y + attribute \src "libresoc.v:50051.18-50051.124" + wire $or$libresoc.v:50051$3098_Y + attribute \src "libresoc.v:50052.18-50052.155" + wire width 3 $or$libresoc.v:50052$3099_Y + attribute \src "libresoc.v:50053.18-50053.194" + wire width 6 $or$libresoc.v:50053$3100_Y + attribute \src "libresoc.v:50057.18-50057.120" + wire width 3 $or$libresoc.v:50057$3104_Y + attribute \src "libresoc.v:50067.17-50067.117" + wire width 6 $or$libresoc.v:50067$3114_Y + attribute \src "libresoc.v:50016.17-50016.104" + wire $reduce_and$libresoc.v:50016$3063_Y + attribute \src "libresoc.v:50034.18-50034.106" + wire $reduce_or$libresoc.v:50034$3081_Y + attribute \src "libresoc.v:50037.18-50037.113" + wire $reduce_or$libresoc.v:50037$3084_Y + attribute \src "libresoc.v:50038.18-50038.112" + wire $reduce_or$libresoc.v:50038$3085_Y attribute \src "libresoc.v:50061.18-50061.118" - wire width 32 $ternary$libresoc.v:50061$3110_Y + wire width 64 $ternary$libresoc.v:50061$3108_Y attribute \src "libresoc.v:50062.18-50062.118" - wire width 4 $ternary$libresoc.v:50062$3111_Y + wire width 64 $ternary$libresoc.v:50062$3109_Y attribute \src "libresoc.v:50063.18-50063.118" - wire width 4 $ternary$libresoc.v:50063$3112_Y + wire width 32 $ternary$libresoc.v:50063$3110_Y attribute \src "libresoc.v:50064.18-50064.118" - wire width 4 $ternary$libresoc.v:50064$3113_Y + wire width 4 $ternary$libresoc.v:50064$3111_Y + attribute \src "libresoc.v:50065.18-50065.118" + wire width 4 $ternary$libresoc.v:50065$3112_Y + attribute \src "libresoc.v:50066.18-50066.118" + wire width 4 $ternary$libresoc.v:50066$3113_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -87264,9 +87266,9 @@ module \cr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 24 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \cr_a_ok @@ -87324,7 +87326,7 @@ module \cr0 wire width 4 output 23 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 20 \full_cr_ok - attribute \src "libresoc.v:49476.7-49476.15" + attribute \src "libresoc.v:49478.7-49478.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 16 \o_ok @@ -87523,7 +87525,7 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50015$3064 + cell $and $and$libresoc.v:50017$3064 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87531,10 +87533,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:50015$3064_Y + connect \Y $and$libresoc.v:50017$3064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50016$3065 + cell $and $and$libresoc.v:50018$3065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87542,10 +87544,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50016$3065_Y + connect \Y $and$libresoc.v:50018$3065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50017$3066 + cell $and $and$libresoc.v:50019$3066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87553,10 +87555,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50017$3066_Y + connect \Y $and$libresoc.v:50019$3066_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50018$3067 + cell $and $and$libresoc.v:50020$3067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87564,10 +87566,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50018$3067_Y + connect \Y $and$libresoc.v:50020$3067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50019$3068 + cell $and $and$libresoc.v:50021$3068 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87575,10 +87577,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:50019$3068_Y + connect \Y $and$libresoc.v:50021$3068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50020$3069 + cell $and $and$libresoc.v:50022$3069 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87586,10 +87588,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50020$3069_Y + connect \Y $and$libresoc.v:50022$3069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50021$3070 + cell $and $and$libresoc.v:50023$3070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87597,10 +87599,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50021$3070_Y + connect \Y $and$libresoc.v:50023$3070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50022$3071 + cell $and $and$libresoc.v:50024$3071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87608,10 +87610,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50022$3071_Y + connect \Y $and$libresoc.v:50024$3071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50023$3072 + cell $and $and$libresoc.v:50025$3072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87619,10 +87621,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50023$3072_Y + connect \Y $and$libresoc.v:50025$3072_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:50024$3073 + cell $and $and$libresoc.v:50026$3073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87630,10 +87632,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:50024$3073_Y + connect \Y $and$libresoc.v:50026$3073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50026$3075 + cell $and $and$libresoc.v:50028$3075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87641,10 +87643,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:50026$3075_Y + connect \Y $and$libresoc.v:50028$3075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50028$3077 + cell $and $and$libresoc.v:50030$3077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87652,10 +87654,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:50028$3077_Y + connect \Y $and$libresoc.v:50030$3077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:50029$3078 + cell $and $and$libresoc.v:50031$3078 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87663,10 +87665,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50029$3078_Y + connect \Y $and$libresoc.v:50031$3078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50031$3080 + cell $and $and$libresoc.v:50033$3080 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87674,10 +87676,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:50031$3080_Y + connect \Y $and$libresoc.v:50033$3080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50034$3083 + cell $and $and$libresoc.v:50036$3083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87685,10 +87687,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:50034$3083_Y + connect \Y $and$libresoc.v:50036$3083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:50038$3087 + cell $and $and$libresoc.v:50040$3087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87696,10 +87698,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:50038$3087_Y + connect \Y $and$libresoc.v:50040$3087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:50040$3089 + cell $and $and$libresoc.v:50042$3089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87707,10 +87709,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:50040$3089_Y + connect \Y $and$libresoc.v:50042$3089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50041$3090 + cell $and $and$libresoc.v:50043$3090 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87718,10 +87720,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50041$3090_Y + connect \Y $and$libresoc.v:50043$3090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50043$3092 + cell $and $and$libresoc.v:50045$3092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87729,10 +87731,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:50043$3092_Y + connect \Y $and$libresoc.v:50045$3092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50045$3094 + cell $and $and$libresoc.v:50047$3094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87740,10 +87742,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_cr0_n_ready_i - connect \Y $and$libresoc.v:50045$3094_Y + connect \Y $and$libresoc.v:50047$3094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50046$3095 + cell $and $and$libresoc.v:50048$3095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87751,10 +87753,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_cr0_n_valid_o - connect \Y $and$libresoc.v:50046$3095_Y + connect \Y $and$libresoc.v:50048$3095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50047$3096 + cell $and $and$libresoc.v:50049$3096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87762,10 +87764,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:50047$3096_Y + connect \Y $and$libresoc.v:50049$3096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:50052$3101 + cell $and $and$libresoc.v:50054$3101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87773,10 +87775,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:50052$3101_Y + connect \Y $and$libresoc.v:50054$3101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:50053$3102 + cell $and $and$libresoc.v:50055$3102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87784,10 +87786,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50053$3102_Y + connect \Y $and$libresoc.v:50055$3102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50056$3105 + cell $and $and$libresoc.v:50058$3105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87795,10 +87797,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50056$3105_Y + connect \Y $and$libresoc.v:50058$3105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50057$3106 + cell $and $and$libresoc.v:50059$3106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87806,10 +87808,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \full_cr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50057$3106_Y + connect \Y $and$libresoc.v:50059$3106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50058$3107 + cell $and $and$libresoc.v:50060$3107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87817,10 +87819,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50058$3107_Y + connect \Y $and$libresoc.v:50060$3107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:50066$3115 + cell $and $and$libresoc.v:50068$3115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87828,10 +87830,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:50066$3115_Y + connect \Y $and$libresoc.v:50068$3115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:50067$3116 + cell $and $and$libresoc.v:50069$3116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87839,10 +87841,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:50067$3116_Y + connect \Y $and$libresoc.v:50069$3116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50068$3117 + cell $and $and$libresoc.v:50070$3117 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87850,10 +87852,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50068$3117_Y + connect \Y $and$libresoc.v:50070$3117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50069$3118 + cell $and $and$libresoc.v:50071$3118 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87861,10 +87863,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$93 connect \B 6'111111 - connect \Y $and$libresoc.v:50069$3118_Y + connect \Y $and$libresoc.v:50071$3118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:50042$3091 + cell $eq $eq$libresoc.v:50044$3091 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87872,10 +87874,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:50042$3091_Y + connect \Y $eq$libresoc.v:50044$3091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:50044$3093 + cell $eq $eq$libresoc.v:50046$3093 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87883,66 +87885,66 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:50044$3093_Y + connect \Y $eq$libresoc.v:50046$3093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50025$3074 + cell $not $not$libresoc.v:50027$3074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:50025$3074_Y + connect \Y $not$libresoc.v:50027$3074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50027$3076 + cell $not $not$libresoc.v:50029$3076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:50027$3076_Y + connect \Y $not$libresoc.v:50029$3076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50030$3079 + cell $not $not$libresoc.v:50032$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:50030$3079_Y + connect \Y $not$libresoc.v:50032$3079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50033$3082 + cell $not $not$libresoc.v:50035$3082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:50033$3082_Y + connect \Y $not$libresoc.v:50035$3082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:50039$3088 + cell $not $not$libresoc.v:50041$3088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_ready_i - connect \Y $not$libresoc.v:50039$3088_Y + connect \Y $not$libresoc.v:50041$3088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:50054$3103 + cell $not $not$libresoc.v:50056$3103 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:50054$3103_Y + connect \Y $not$libresoc.v:50056$3103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:50070$3119 + cell $not $not$libresoc.v:50072$3119 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:50070$3119_Y + connect \Y $not$libresoc.v:50072$3119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:50037$3086 + cell $or $or$libresoc.v:50039$3086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87950,10 +87952,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:50037$3086_Y + connect \Y $or$libresoc.v:50039$3086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:50048$3097 + cell $or $or$libresoc.v:50050$3097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87961,10 +87963,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50048$3097_Y + connect \Y $or$libresoc.v:50050$3097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:50049$3098 + cell $or $or$libresoc.v:50051$3098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -87972,10 +87974,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50049$3098_Y + connect \Y $or$libresoc.v:50051$3098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:50050$3099 + cell $or $or$libresoc.v:50052$3099 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -87983,10 +87985,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50050$3099_Y + connect \Y $or$libresoc.v:50052$3099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:50051$3100 + cell $or $or$libresoc.v:50053$3100 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -87994,10 +87996,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50051$3100_Y + connect \Y $or$libresoc.v:50053$3100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:50055$3104 + cell $or $or$libresoc.v:50057$3104 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88005,10 +88007,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:50055$3104_Y + connect \Y $or$libresoc.v:50057$3104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:50065$3114 + cell $or $or$libresoc.v:50067$3114 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88016,90 +88018,90 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:50065$3114_Y + connect \Y $or$libresoc.v:50067$3114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:50014$3063 + cell $reduce_and $reduce_and$libresoc.v:50016$3063 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:50014$3063_Y + connect \Y $reduce_and$libresoc.v:50016$3063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:50032$3081 + cell $reduce_or $reduce_or$libresoc.v:50034$3081 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:50032$3081_Y + connect \Y $reduce_or$libresoc.v:50034$3081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50035$3084 + cell $reduce_or $reduce_or$libresoc.v:50037$3084 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:50035$3084_Y + connect \Y $reduce_or$libresoc.v:50037$3084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50036$3085 + cell $reduce_or $reduce_or$libresoc.v:50038$3085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:50036$3085_Y + connect \Y $reduce_or$libresoc.v:50038$3085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50059$3108 + cell $mux $ternary$libresoc.v:50061$3108 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:50059$3108_Y + connect \Y $ternary$libresoc.v:50061$3108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50060$3109 + cell $mux $ternary$libresoc.v:50062$3109 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:50060$3109_Y + connect \Y $ternary$libresoc.v:50062$3109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50061$3110 + cell $mux $ternary$libresoc.v:50063$3110 parameter \WIDTH 32 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:50061$3110_Y + connect \Y $ternary$libresoc.v:50063$3110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50062$3111 + cell $mux $ternary$libresoc.v:50064$3111 parameter \WIDTH 4 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:50062$3111_Y + connect \Y $ternary$libresoc.v:50064$3111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50063$3112 + cell $mux $ternary$libresoc.v:50065$3112 parameter \WIDTH 4 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:50063$3112_Y + connect \Y $ternary$libresoc.v:50065$3112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50064$3113 + cell $mux $ternary$libresoc.v:50066$3113 parameter \WIDTH 4 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:50064$3113_Y + connect \Y $ternary$libresoc.v:50066$3113_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:50131.11-50153.4" + attribute \src "libresoc.v:50133.11-50155.4" cell \alu_cr0 \alu_cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88124,7 +88126,7 @@ module \cr0 connect \rb \alu_cr0_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:50154.14-50160.4" + attribute \src "libresoc.v:50156.14-50162.4" cell \alu_l$16 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88133,7 +88135,7 @@ module \cr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:50161.15-50167.4" + attribute \src "libresoc.v:50163.15-50169.4" cell \alui_l$15 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88142,7 +88144,7 @@ module \cr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:50168.14-50174.4" + attribute \src "libresoc.v:50170.14-50176.4" cell \opc_l$11 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88151,7 +88153,7 @@ module \cr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:50175.14-50181.4" + attribute \src "libresoc.v:50177.14-50183.4" cell \req_l$12 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88160,7 +88162,7 @@ module \cr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:50182.14-50188.4" + attribute \src "libresoc.v:50184.14-50190.4" cell \rok_l$14 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88169,7 +88171,7 @@ module \cr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:50189.14-50194.4" + attribute \src "libresoc.v:50191.14-50196.4" cell \rst_l$13 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88177,7 +88179,7 @@ module \cr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:50195.14-50201.4" + attribute \src "libresoc.v:50197.14-50203.4" cell \src_l$10 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88185,472 +88187,472 @@ module \cr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:49476.7-49476.20" - process $proc$libresoc.v:49476$3242 + attribute \src "libresoc.v:49478.7-49478.20" + process $proc$libresoc.v:49478$3242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49594.7-49594.24" - process $proc$libresoc.v:49594$3243 + attribute \src "libresoc.v:49596.7-49596.24" + process $proc$libresoc.v:49596$3243 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:49624.14-49624.47" - process $proc$libresoc.v:49624$3244 + attribute \src "libresoc.v:49626.14-49626.47" + process $proc$libresoc.v:49626$3244 assign { } { } assign $1\alu_cr0_cr_op__fn_unit[12:0] 13'0000000000000 sync always sync init update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[12:0] end - attribute \src "libresoc.v:49628.14-49628.41" - process $proc$libresoc.v:49628$3245 + attribute \src "libresoc.v:49630.14-49630.41" + process $proc$libresoc.v:49630$3245 assign { } { } assign $1\alu_cr0_cr_op__insn[31:0] 0 sync always sync init update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:49706.13-49706.45" - process $proc$libresoc.v:49706$3246 + attribute \src "libresoc.v:49708.13-49708.45" + process $proc$libresoc.v:49708$3246 assign { } { } assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:49730.7-49730.26" - process $proc$libresoc.v:49730$3247 + attribute \src "libresoc.v:49732.7-49732.26" + process $proc$libresoc.v:49732$3247 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:49738.7-49738.25" - process $proc$libresoc.v:49738$3248 + attribute \src "libresoc.v:49740.7-49740.25" + process $proc$libresoc.v:49740$3248 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:49750.7-49750.27" - process $proc$libresoc.v:49750$3249 + attribute \src "libresoc.v:49752.7-49752.27" + process $proc$libresoc.v:49752$3249 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:49784.14-49784.47" - process $proc$libresoc.v:49784$3250 + attribute \src "libresoc.v:49786.14-49786.47" + process $proc$libresoc.v:49786$3250 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:49788.7-49788.27" - process $proc$libresoc.v:49788$3251 + attribute \src "libresoc.v:49790.7-49790.27" + process $proc$libresoc.v:49790$3251 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:49792.14-49792.38" - process $proc$libresoc.v:49792$3252 + attribute \src "libresoc.v:49794.14-49794.38" + process $proc$libresoc.v:49794$3252 assign { } { } assign $1\data_r1__full_cr[31:0] 0 sync always sync init update \data_r1__full_cr $1\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:49796.7-49796.33" - process $proc$libresoc.v:49796$3253 + attribute \src "libresoc.v:49798.7-49798.33" + process $proc$libresoc.v:49798$3253 assign { } { } assign $1\data_r1__full_cr_ok[0:0] 1'0 sync always sync init update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:49800.13-49800.33" - process $proc$libresoc.v:49800$3254 + attribute \src "libresoc.v:49802.13-49802.33" + process $proc$libresoc.v:49802$3254 assign { } { } assign $1\data_r2__cr_a[3:0] 4'0000 sync always sync init update \data_r2__cr_a $1\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:49804.7-49804.30" - process $proc$libresoc.v:49804$3255 + attribute \src "libresoc.v:49806.7-49806.30" + process $proc$libresoc.v:49806$3255 assign { } { } assign $1\data_r2__cr_a_ok[0:0] 1'0 sync always sync init update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:49823.7-49823.25" - process $proc$libresoc.v:49823$3256 + attribute \src "libresoc.v:49825.7-49825.25" + process $proc$libresoc.v:49825$3256 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:49827.7-49827.25" - process $proc$libresoc.v:49827$3257 + attribute \src "libresoc.v:49829.7-49829.25" + process $proc$libresoc.v:49829$3257 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:49925.13-49925.30" - process $proc$libresoc.v:49925$3258 + attribute \src "libresoc.v:49927.13-49927.30" + process $proc$libresoc.v:49927$3258 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:49933.13-49933.31" - process $proc$libresoc.v:49933$3259 + attribute \src "libresoc.v:49935.13-49935.31" + process $proc$libresoc.v:49935$3259 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:49937.13-49937.31" - process $proc$libresoc.v:49937$3260 + attribute \src "libresoc.v:49939.13-49939.31" + process $proc$libresoc.v:49939$3260 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:49949.7-49949.26" - process $proc$libresoc.v:49949$3261 + attribute \src "libresoc.v:49951.7-49951.26" + process $proc$libresoc.v:49951$3261 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:49953.7-49953.26" - process $proc$libresoc.v:49953$3262 + attribute \src "libresoc.v:49955.7-49955.26" + process $proc$libresoc.v:49955$3262 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:49957.7-49957.25" - process $proc$libresoc.v:49957$3263 + attribute \src "libresoc.v:49959.7-49959.25" + process $proc$libresoc.v:49959$3263 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:49961.7-49961.25" - process $proc$libresoc.v:49961$3264 + attribute \src "libresoc.v:49963.7-49963.25" + process $proc$libresoc.v:49963$3264 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:49981.13-49981.32" - process $proc$libresoc.v:49981$3265 + attribute \src "libresoc.v:49983.13-49983.32" + process $proc$libresoc.v:49983$3265 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:49985.13-49985.32" - process $proc$libresoc.v:49985$3266 + attribute \src "libresoc.v:49987.13-49987.32" + process $proc$libresoc.v:49987$3266 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:49989.14-49989.43" - process $proc$libresoc.v:49989$3267 + attribute \src "libresoc.v:49991.14-49991.43" + process $proc$libresoc.v:49991$3267 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:49993.14-49993.43" - process $proc$libresoc.v:49993$3268 + attribute \src "libresoc.v:49995.14-49995.43" + process $proc$libresoc.v:49995$3268 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:49997.14-49997.28" - process $proc$libresoc.v:49997$3269 + attribute \src "libresoc.v:49999.14-49999.28" + process $proc$libresoc.v:49999$3269 assign { } { } assign $1\src_r2[31:0] 0 sync always sync init update \src_r2 $1\src_r2[31:0] end - attribute \src "libresoc.v:50001.13-50001.26" - process $proc$libresoc.v:50001$3270 + attribute \src "libresoc.v:50003.13-50003.26" + process $proc$libresoc.v:50003$3270 assign { } { } assign $1\src_r3[3:0] 4'0000 sync always sync init update \src_r3 $1\src_r3[3:0] end - attribute \src "libresoc.v:50005.13-50005.26" - process $proc$libresoc.v:50005$3271 + attribute \src "libresoc.v:50007.13-50007.26" + process $proc$libresoc.v:50007$3271 assign { } { } assign $1\src_r4[3:0] 4'0000 sync always sync init update \src_r4 $1\src_r4[3:0] end - attribute \src "libresoc.v:50009.13-50009.26" - process $proc$libresoc.v:50009$3272 + attribute \src "libresoc.v:50011.13-50011.26" + process $proc$libresoc.v:50011$3272 assign { } { } assign $1\src_r5[3:0] 4'0000 sync always sync init update \src_r5 $1\src_r5[3:0] end - attribute \src "libresoc.v:50071.3-50072.39" - process $proc$libresoc.v:50071$3120 + attribute \src "libresoc.v:50073.3-50074.39" + process $proc$libresoc.v:50073$3120 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50073.3-50074.43" - process $proc$libresoc.v:50073$3121 + attribute \src "libresoc.v:50075.3-50076.43" + process $proc$libresoc.v:50075$3121 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50075.3-50076.29" - process $proc$libresoc.v:50075$3122 + attribute \src "libresoc.v:50077.3-50078.29" + process $proc$libresoc.v:50077$3122 assign { } { } assign $0\src_r5[3:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[3:0] end - attribute \src "libresoc.v:50077.3-50078.29" - process $proc$libresoc.v:50077$3123 + attribute \src "libresoc.v:50079.3-50080.29" + process $proc$libresoc.v:50079$3123 assign { } { } assign $0\src_r4[3:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[3:0] end - attribute \src "libresoc.v:50079.3-50080.29" - process $proc$libresoc.v:50079$3124 + attribute \src "libresoc.v:50081.3-50082.29" + process $proc$libresoc.v:50081$3124 assign { } { } assign $0\src_r3[3:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[3:0] end - attribute \src "libresoc.v:50081.3-50082.29" - process $proc$libresoc.v:50081$3125 + attribute \src "libresoc.v:50083.3-50084.29" + process $proc$libresoc.v:50083$3125 assign { } { } assign $0\src_r2[31:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[31:0] end - attribute \src "libresoc.v:50083.3-50084.29" - process $proc$libresoc.v:50083$3126 + attribute \src "libresoc.v:50085.3-50086.29" + process $proc$libresoc.v:50085$3126 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:50085.3-50086.29" - process $proc$libresoc.v:50085$3127 + attribute \src "libresoc.v:50087.3-50088.29" + process $proc$libresoc.v:50087$3127 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:50087.3-50088.43" - process $proc$libresoc.v:50087$3128 + attribute \src "libresoc.v:50089.3-50090.43" + process $proc$libresoc.v:50089$3128 assign { } { } assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next sync posedge \coresync_clk update \data_r2__cr_a $0\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50089.3-50090.49" - process $proc$libresoc.v:50089$3129 + attribute \src "libresoc.v:50091.3-50092.49" + process $proc$libresoc.v:50091$3129 assign { } { } assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next sync posedge \coresync_clk update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50091.3-50092.49" - process $proc$libresoc.v:50091$3130 + attribute \src "libresoc.v:50093.3-50094.49" + process $proc$libresoc.v:50093$3130 assign { } { } assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next sync posedge \coresync_clk update \data_r1__full_cr $0\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50093.3-50094.55" - process $proc$libresoc.v:50093$3131 + attribute \src "libresoc.v:50095.3-50096.55" + process $proc$libresoc.v:50095$3131 assign { } { } assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next sync posedge \coresync_clk update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50095.3-50096.37" - process $proc$libresoc.v:50095$3132 + attribute \src "libresoc.v:50097.3-50098.37" + process $proc$libresoc.v:50097$3132 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:50097.3-50098.43" - process $proc$libresoc.v:50097$3133 + attribute \src "libresoc.v:50099.3-50100.43" + process $proc$libresoc.v:50099$3133 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50099.3-50100.65" - process $proc$libresoc.v:50099$3134 + attribute \src "libresoc.v:50101.3-50102.65" + process $proc$libresoc.v:50101$3134 assign { } { } assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50101.3-50102.61" - process $proc$libresoc.v:50101$3135 + attribute \src "libresoc.v:50103.3-50104.61" + process $proc$libresoc.v:50103$3135 assign { } { } assign $0\alu_cr0_cr_op__fn_unit[12:0] \alu_cr0_cr_op__fn_unit$next sync posedge \coresync_clk update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[12:0] end - attribute \src "libresoc.v:50103.3-50104.55" - process $proc$libresoc.v:50103$3136 + attribute \src "libresoc.v:50105.3-50106.55" + process $proc$libresoc.v:50105$3136 assign { } { } assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50105.3-50106.39" - process $proc$libresoc.v:50105$3137 + attribute \src "libresoc.v:50107.3-50108.39" + process $proc$libresoc.v:50107$3137 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:50107.3-50108.39" - process $proc$libresoc.v:50107$3138 + attribute \src "libresoc.v:50109.3-50110.39" + process $proc$libresoc.v:50109$3138 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:50109.3-50110.39" - process $proc$libresoc.v:50109$3139 + attribute \src "libresoc.v:50111.3-50112.39" + process $proc$libresoc.v:50111$3139 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:50111.3-50112.39" - process $proc$libresoc.v:50111$3140 + attribute \src "libresoc.v:50113.3-50114.39" + process $proc$libresoc.v:50113$3140 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:50113.3-50114.39" - process $proc$libresoc.v:50113$3141 + attribute \src "libresoc.v:50115.3-50116.39" + process $proc$libresoc.v:50115$3141 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50115.3-50116.39" - process $proc$libresoc.v:50115$3142 + attribute \src "libresoc.v:50117.3-50118.39" + process $proc$libresoc.v:50117$3142 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50117.3-50118.39" - process $proc$libresoc.v:50117$3143 + attribute \src "libresoc.v:50119.3-50120.39" + process $proc$libresoc.v:50119$3143 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50119.3-50120.39" - process $proc$libresoc.v:50119$3144 + attribute \src "libresoc.v:50121.3-50122.39" + process $proc$libresoc.v:50121$3144 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50121.3-50122.41" - process $proc$libresoc.v:50121$3145 + attribute \src "libresoc.v:50123.3-50124.41" + process $proc$libresoc.v:50123$3145 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50123.3-50124.41" - process $proc$libresoc.v:50123$3146 + attribute \src "libresoc.v:50125.3-50126.41" + process $proc$libresoc.v:50125$3146 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50125.3-50126.37" - process $proc$libresoc.v:50125$3147 + attribute \src "libresoc.v:50127.3-50128.37" + process $proc$libresoc.v:50127$3147 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:50127.3-50128.39" - process $proc$libresoc.v:50127$3148 + attribute \src "libresoc.v:50129.3-50130.39" + process $proc$libresoc.v:50129$3148 assign { } { } assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:50129.3-50130.25" - process $proc$libresoc.v:50129$3149 + attribute \src "libresoc.v:50131.3-50132.25" + process $proc$libresoc.v:50131$3149 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:50202.3-50211.6" - process $proc$libresoc.v:50202$3150 + attribute \src "libresoc.v:50204.3-50213.6" + process $proc$libresoc.v:50204$3150 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:50203.5-50203.29" + attribute \src "libresoc.v:50205.5-50205.29" switch \initial - attribute \src "libresoc.v:50203.9-50203.17" + attribute \src "libresoc.v:50205.9-50205.17" case 1'1 case end @@ -88666,14 +88668,14 @@ module \cr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:50212.3-50220.6" - process $proc$libresoc.v:50212$3151 + attribute \src "libresoc.v:50214.3-50222.6" + process $proc$libresoc.v:50214$3151 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153 - attribute \src "libresoc.v:50213.5-50213.29" + attribute \src "libresoc.v:50215.5-50215.29" switch \initial - attribute \src "libresoc.v:50213.9-50213.17" + attribute \src "libresoc.v:50215.9-50215.17" case 1'1 case end @@ -88689,14 +88691,14 @@ module \cr0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152 end - attribute \src "libresoc.v:50221.3-50229.6" - process $proc$libresoc.v:50221$3154 + attribute \src "libresoc.v:50223.3-50231.6" + process $proc$libresoc.v:50223$3154 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156 - attribute \src "libresoc.v:50222.5-50222.29" + attribute \src "libresoc.v:50224.5-50224.29" switch \initial - attribute \src "libresoc.v:50222.9-50222.17" + attribute \src "libresoc.v:50224.9-50224.17" case 1'1 case end @@ -88712,14 +88714,14 @@ module \cr0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155 end - attribute \src "libresoc.v:50230.3-50238.6" - process $proc$libresoc.v:50230$3157 + attribute \src "libresoc.v:50232.3-50240.6" + process $proc$libresoc.v:50232$3157 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159 - attribute \src "libresoc.v:50231.5-50231.29" + attribute \src "libresoc.v:50233.5-50233.29" switch \initial - attribute \src "libresoc.v:50231.9-50231.17" + attribute \src "libresoc.v:50233.9-50233.17" case 1'1 case end @@ -88735,14 +88737,14 @@ module \cr0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158 end - attribute \src "libresoc.v:50239.3-50247.6" - process $proc$libresoc.v:50239$3160 + attribute \src "libresoc.v:50241.3-50249.6" + process $proc$libresoc.v:50241$3160 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162 - attribute \src "libresoc.v:50240.5-50240.29" + attribute \src "libresoc.v:50242.5-50242.29" switch \initial - attribute \src "libresoc.v:50240.9-50240.17" + attribute \src "libresoc.v:50242.9-50242.17" case 1'1 case end @@ -88758,14 +88760,14 @@ module \cr0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161 end - attribute \src "libresoc.v:50248.3-50256.6" - process $proc$libresoc.v:50248$3163 + attribute \src "libresoc.v:50250.3-50258.6" + process $proc$libresoc.v:50250$3163 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165 - attribute \src "libresoc.v:50249.5-50249.29" + attribute \src "libresoc.v:50251.5-50251.29" switch \initial - attribute \src "libresoc.v:50249.9-50249.17" + attribute \src "libresoc.v:50251.9-50251.17" case 1'1 case end @@ -88781,14 +88783,14 @@ module \cr0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164 end - attribute \src "libresoc.v:50257.3-50265.6" - process $proc$libresoc.v:50257$3166 + attribute \src "libresoc.v:50259.3-50267.6" + process $proc$libresoc.v:50259$3166 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168 - attribute \src "libresoc.v:50258.5-50258.29" + attribute \src "libresoc.v:50260.5-50260.29" switch \initial - attribute \src "libresoc.v:50258.9-50258.17" + attribute \src "libresoc.v:50260.9-50260.17" case 1'1 case end @@ -88804,14 +88806,14 @@ module \cr0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167 end - attribute \src "libresoc.v:50266.3-50274.6" - process $proc$libresoc.v:50266$3169 + attribute \src "libresoc.v:50268.3-50276.6" + process $proc$libresoc.v:50268$3169 assign { } { } assign { } { } assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171 - attribute \src "libresoc.v:50267.5-50267.29" + attribute \src "libresoc.v:50269.5-50269.29" switch \initial - attribute \src "libresoc.v:50267.9-50267.17" + attribute \src "libresoc.v:50269.9-50269.17" case 1'1 case end @@ -88827,14 +88829,14 @@ module \cr0 sync always update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170 end - attribute \src "libresoc.v:50275.3-50283.6" - process $proc$libresoc.v:50275$3172 + attribute \src "libresoc.v:50277.3-50285.6" + process $proc$libresoc.v:50277$3172 assign { } { } assign { } { } assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174 - attribute \src "libresoc.v:50276.5-50276.29" + attribute \src "libresoc.v:50278.5-50278.29" switch \initial - attribute \src "libresoc.v:50276.9-50276.17" + attribute \src "libresoc.v:50278.9-50278.17" case 1'1 case end @@ -88850,14 +88852,14 @@ module \cr0 sync always update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173 end - attribute \src "libresoc.v:50284.3-50292.6" - process $proc$libresoc.v:50284$3175 + attribute \src "libresoc.v:50286.3-50294.6" + process $proc$libresoc.v:50286$3175 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177 - attribute \src "libresoc.v:50285.5-50285.29" + attribute \src "libresoc.v:50287.5-50287.29" switch \initial - attribute \src "libresoc.v:50285.9-50285.17" + attribute \src "libresoc.v:50287.9-50287.17" case 1'1 case end @@ -88873,14 +88875,14 @@ module \cr0 sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176 end - attribute \src "libresoc.v:50293.3-50301.6" - process $proc$libresoc.v:50293$3178 + attribute \src "libresoc.v:50295.3-50303.6" + process $proc$libresoc.v:50295$3178 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180 - attribute \src "libresoc.v:50294.5-50294.29" + attribute \src "libresoc.v:50296.5-50296.29" switch \initial - attribute \src "libresoc.v:50294.9-50294.17" + attribute \src "libresoc.v:50296.9-50296.17" case 1'1 case end @@ -88896,8 +88898,8 @@ module \cr0 sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179 end - attribute \src "libresoc.v:50302.3-50313.6" - process $proc$libresoc.v:50302$3181 + attribute \src "libresoc.v:50304.3-50315.6" + process $proc$libresoc.v:50304$3181 assign { } { } assign { } { } assign { } { } @@ -88907,9 +88909,9 @@ module \cr0 assign $0\alu_cr0_cr_op__fn_unit$next[12:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[12:0]$3185 assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186 assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 - attribute \src "libresoc.v:50303.5-50303.29" + attribute \src "libresoc.v:50305.5-50305.29" switch \initial - attribute \src "libresoc.v:50303.9-50303.17" + attribute \src "libresoc.v:50305.9-50305.17" case 1'1 case end @@ -88931,8 +88933,8 @@ module \cr0 update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183 update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 end - attribute \src "libresoc.v:50314.3-50335.6" - process $proc$libresoc.v:50314$3188 + attribute \src "libresoc.v:50316.3-50337.6" + process $proc$libresoc.v:50316$3188 assign { } { } assign { } { } assign { } { } @@ -88942,9 +88944,9 @@ module \cr0 assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193 assign { } { } assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195 - attribute \src "libresoc.v:50315.5-50315.29" + attribute \src "libresoc.v:50317.5-50317.29" switch \initial - attribute \src "libresoc.v:50315.9-50315.17" + attribute \src "libresoc.v:50317.9-50317.17" case 1'1 case end @@ -88983,8 +88985,8 @@ module \cr0 update \data_r0__o$next $0\data_r0__o$next[63:0]$3189 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190 end - attribute \src "libresoc.v:50336.3-50357.6" - process $proc$libresoc.v:50336$3196 + attribute \src "libresoc.v:50338.3-50359.6" + process $proc$libresoc.v:50338$3196 assign { } { } assign { } { } assign { } { } @@ -88994,9 +88996,9 @@ module \cr0 assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201 assign { } { } assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203 - attribute \src "libresoc.v:50337.5-50337.29" + attribute \src "libresoc.v:50339.5-50339.29" switch \initial - attribute \src "libresoc.v:50337.9-50337.17" + attribute \src "libresoc.v:50339.9-50339.17" case 1'1 case end @@ -89035,8 +89037,8 @@ module \cr0 update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197 update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198 end - attribute \src "libresoc.v:50358.3-50379.6" - process $proc$libresoc.v:50358$3204 + attribute \src "libresoc.v:50360.3-50381.6" + process $proc$libresoc.v:50360$3204 assign { } { } assign { } { } assign { } { } @@ -89046,9 +89048,9 @@ module \cr0 assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209 assign { } { } assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211 - attribute \src "libresoc.v:50359.5-50359.29" + attribute \src "libresoc.v:50361.5-50361.29" switch \initial - attribute \src "libresoc.v:50359.9-50359.17" + attribute \src "libresoc.v:50361.9-50361.17" case 1'1 case end @@ -89087,14 +89089,14 @@ module \cr0 update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205 update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206 end - attribute \src "libresoc.v:50380.3-50389.6" - process $proc$libresoc.v:50380$3212 + attribute \src "libresoc.v:50382.3-50391.6" + process $proc$libresoc.v:50382$3212 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214 - attribute \src "libresoc.v:50381.5-50381.29" + attribute \src "libresoc.v:50383.5-50383.29" switch \initial - attribute \src "libresoc.v:50381.9-50381.17" + attribute \src "libresoc.v:50383.9-50383.17" case 1'1 case end @@ -89110,14 +89112,14 @@ module \cr0 sync always update \src_r0$next $0\src_r0$next[63:0]$3213 end - attribute \src "libresoc.v:50390.3-50399.6" - process $proc$libresoc.v:50390$3215 + attribute \src "libresoc.v:50392.3-50401.6" + process $proc$libresoc.v:50392$3215 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217 - attribute \src "libresoc.v:50391.5-50391.29" + attribute \src "libresoc.v:50393.5-50393.29" switch \initial - attribute \src "libresoc.v:50391.9-50391.17" + attribute \src "libresoc.v:50393.9-50393.17" case 1'1 case end @@ -89133,14 +89135,14 @@ module \cr0 sync always update \src_r1$next $0\src_r1$next[63:0]$3216 end - attribute \src "libresoc.v:50400.3-50409.6" - process $proc$libresoc.v:50400$3218 + attribute \src "libresoc.v:50402.3-50411.6" + process $proc$libresoc.v:50402$3218 assign { } { } assign { } { } assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220 - attribute \src "libresoc.v:50401.5-50401.29" + attribute \src "libresoc.v:50403.5-50403.29" switch \initial - attribute \src "libresoc.v:50401.9-50401.17" + attribute \src "libresoc.v:50403.9-50403.17" case 1'1 case end @@ -89156,14 +89158,14 @@ module \cr0 sync always update \src_r2$next $0\src_r2$next[31:0]$3219 end - attribute \src "libresoc.v:50410.3-50419.6" - process $proc$libresoc.v:50410$3221 + attribute \src "libresoc.v:50412.3-50421.6" + process $proc$libresoc.v:50412$3221 assign { } { } assign { } { } assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223 - attribute \src "libresoc.v:50411.5-50411.29" + attribute \src "libresoc.v:50413.5-50413.29" switch \initial - attribute \src "libresoc.v:50411.9-50411.17" + attribute \src "libresoc.v:50413.9-50413.17" case 1'1 case end @@ -89179,14 +89181,14 @@ module \cr0 sync always update \src_r3$next $0\src_r3$next[3:0]$3222 end - attribute \src "libresoc.v:50420.3-50429.6" - process $proc$libresoc.v:50420$3224 + attribute \src "libresoc.v:50422.3-50431.6" + process $proc$libresoc.v:50422$3224 assign { } { } assign { } { } assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226 - attribute \src "libresoc.v:50421.5-50421.29" + attribute \src "libresoc.v:50423.5-50423.29" switch \initial - attribute \src "libresoc.v:50421.9-50421.17" + attribute \src "libresoc.v:50423.9-50423.17" case 1'1 case end @@ -89202,14 +89204,14 @@ module \cr0 sync always update \src_r4$next $0\src_r4$next[3:0]$3225 end - attribute \src "libresoc.v:50430.3-50439.6" - process $proc$libresoc.v:50430$3227 + attribute \src "libresoc.v:50432.3-50441.6" + process $proc$libresoc.v:50432$3227 assign { } { } assign { } { } assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229 - attribute \src "libresoc.v:50431.5-50431.29" + attribute \src "libresoc.v:50433.5-50433.29" switch \initial - attribute \src "libresoc.v:50431.9-50431.17" + attribute \src "libresoc.v:50433.9-50433.17" case 1'1 case end @@ -89225,14 +89227,14 @@ module \cr0 sync always update \src_r5$next $0\src_r5$next[3:0]$3228 end - attribute \src "libresoc.v:50440.3-50448.6" - process $proc$libresoc.v:50440$3230 + attribute \src "libresoc.v:50442.3-50450.6" + process $proc$libresoc.v:50442$3230 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232 - attribute \src "libresoc.v:50441.5-50441.29" + attribute \src "libresoc.v:50443.5-50443.29" switch \initial - attribute \src "libresoc.v:50441.9-50441.17" + attribute \src "libresoc.v:50443.9-50443.17" case 1'1 case end @@ -89248,14 +89250,14 @@ module \cr0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231 end - attribute \src "libresoc.v:50449.3-50457.6" - process $proc$libresoc.v:50449$3233 + attribute \src "libresoc.v:50451.3-50459.6" + process $proc$libresoc.v:50451$3233 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235 - attribute \src "libresoc.v:50450.5-50450.29" + attribute \src "libresoc.v:50452.5-50452.29" switch \initial - attribute \src "libresoc.v:50450.9-50450.17" + attribute \src "libresoc.v:50452.9-50452.17" case 1'1 case end @@ -89271,14 +89273,14 @@ module \cr0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234 end - attribute \src "libresoc.v:50458.3-50467.6" - process $proc$libresoc.v:50458$3236 + attribute \src "libresoc.v:50460.3-50469.6" + process $proc$libresoc.v:50460$3236 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:50459.5-50459.29" + attribute \src "libresoc.v:50461.5-50461.29" switch \initial - attribute \src "libresoc.v:50459.9-50459.17" + attribute \src "libresoc.v:50461.9-50461.17" case 1'1 case end @@ -89294,14 +89296,14 @@ module \cr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:50468.3-50477.6" - process $proc$libresoc.v:50468$3237 + attribute \src "libresoc.v:50470.3-50479.6" + process $proc$libresoc.v:50470$3237 assign { } { } assign { } { } assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "libresoc.v:50469.5-50469.29" + attribute \src "libresoc.v:50471.5-50471.29" switch \initial - attribute \src "libresoc.v:50469.9-50469.17" + attribute \src "libresoc.v:50471.9-50471.17" case 1'1 case end @@ -89317,14 +89319,14 @@ module \cr0 sync always update \dest2_o $0\dest2_o[31:0] end - attribute \src "libresoc.v:50478.3-50487.6" - process $proc$libresoc.v:50478$3238 + attribute \src "libresoc.v:50480.3-50489.6" + process $proc$libresoc.v:50480$3238 assign { } { } assign { } { } assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "libresoc.v:50479.5-50479.29" + attribute \src "libresoc.v:50481.5-50481.29" switch \initial - attribute \src "libresoc.v:50479.9-50479.17" + attribute \src "libresoc.v:50481.9-50481.17" case 1'1 case end @@ -89340,14 +89342,14 @@ module \cr0 sync always update \dest3_o $0\dest3_o[3:0] end - attribute \src "libresoc.v:50488.3-50496.6" - process $proc$libresoc.v:50488$3239 + attribute \src "libresoc.v:50490.3-50498.6" + process $proc$libresoc.v:50490$3239 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241 - attribute \src "libresoc.v:50489.5-50489.29" + attribute \src "libresoc.v:50491.5-50491.29" switch \initial - attribute \src "libresoc.v:50489.9-50489.17" + attribute \src "libresoc.v:50491.9-50491.17" case 1'1 case end @@ -89363,63 +89365,63 @@ module \cr0 sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240 end - connect \$5 $reduce_and$libresoc.v:50014$3063_Y - connect \$99 $and$libresoc.v:50015$3064_Y - connect \$101 $and$libresoc.v:50016$3065_Y - connect \$103 $and$libresoc.v:50017$3066_Y - connect \$105 $and$libresoc.v:50018$3067_Y - connect \$107 $and$libresoc.v:50019$3068_Y - connect \$109 $and$libresoc.v:50020$3069_Y - connect \$111 $and$libresoc.v:50021$3070_Y - connect \$113 $and$libresoc.v:50022$3071_Y - connect \$115 $and$libresoc.v:50023$3072_Y - connect \$11 $and$libresoc.v:50024$3073_Y - connect \$13 $not$libresoc.v:50025$3074_Y - connect \$15 $and$libresoc.v:50026$3075_Y - connect \$17 $not$libresoc.v:50027$3076_Y - connect \$19 $and$libresoc.v:50028$3077_Y - connect \$21 $and$libresoc.v:50029$3078_Y - connect \$25 $not$libresoc.v:50030$3079_Y - connect \$27 $and$libresoc.v:50031$3080_Y - connect \$24 $reduce_or$libresoc.v:50032$3081_Y - connect \$23 $not$libresoc.v:50033$3082_Y - connect \$31 $and$libresoc.v:50034$3083_Y - connect \$33 $reduce_or$libresoc.v:50035$3084_Y - connect \$35 $reduce_or$libresoc.v:50036$3085_Y - connect \$37 $or$libresoc.v:50037$3086_Y - connect \$3 $and$libresoc.v:50038$3087_Y - connect \$39 $not$libresoc.v:50039$3088_Y - connect \$41 $and$libresoc.v:50040$3089_Y - connect \$43 $and$libresoc.v:50041$3090_Y - connect \$45 $eq$libresoc.v:50042$3091_Y - connect \$47 $and$libresoc.v:50043$3092_Y - connect \$49 $eq$libresoc.v:50044$3093_Y - connect \$51 $and$libresoc.v:50045$3094_Y - connect \$53 $and$libresoc.v:50046$3095_Y - connect \$55 $and$libresoc.v:50047$3096_Y - connect \$57 $or$libresoc.v:50048$3097_Y - connect \$59 $or$libresoc.v:50049$3098_Y - connect \$61 $or$libresoc.v:50050$3099_Y - connect \$63 $or$libresoc.v:50051$3100_Y - connect \$65 $and$libresoc.v:50052$3101_Y - connect \$67 $and$libresoc.v:50053$3102_Y - connect \$6 $not$libresoc.v:50054$3103_Y - connect \$69 $or$libresoc.v:50055$3104_Y - connect \$71 $and$libresoc.v:50056$3105_Y - connect \$73 $and$libresoc.v:50057$3106_Y - connect \$75 $and$libresoc.v:50058$3107_Y - connect \$77 $ternary$libresoc.v:50059$3108_Y - connect \$79 $ternary$libresoc.v:50060$3109_Y - connect \$81 $ternary$libresoc.v:50061$3110_Y - connect \$83 $ternary$libresoc.v:50062$3111_Y - connect \$85 $ternary$libresoc.v:50063$3112_Y - connect \$87 $ternary$libresoc.v:50064$3113_Y - connect \$8 $or$libresoc.v:50065$3114_Y - connect \$89 $and$libresoc.v:50066$3115_Y - connect \$91 $and$libresoc.v:50067$3116_Y - connect \$93 $and$libresoc.v:50068$3117_Y - connect \$95 $and$libresoc.v:50069$3118_Y - connect \$97 $not$libresoc.v:50070$3119_Y + connect \$5 $reduce_and$libresoc.v:50016$3063_Y + connect \$99 $and$libresoc.v:50017$3064_Y + connect \$101 $and$libresoc.v:50018$3065_Y + connect \$103 $and$libresoc.v:50019$3066_Y + connect \$105 $and$libresoc.v:50020$3067_Y + connect \$107 $and$libresoc.v:50021$3068_Y + connect \$109 $and$libresoc.v:50022$3069_Y + connect \$111 $and$libresoc.v:50023$3070_Y + connect \$113 $and$libresoc.v:50024$3071_Y + connect \$115 $and$libresoc.v:50025$3072_Y + connect \$11 $and$libresoc.v:50026$3073_Y + connect \$13 $not$libresoc.v:50027$3074_Y + connect \$15 $and$libresoc.v:50028$3075_Y + connect \$17 $not$libresoc.v:50029$3076_Y + connect \$19 $and$libresoc.v:50030$3077_Y + connect \$21 $and$libresoc.v:50031$3078_Y + connect \$25 $not$libresoc.v:50032$3079_Y + connect \$27 $and$libresoc.v:50033$3080_Y + connect \$24 $reduce_or$libresoc.v:50034$3081_Y + connect \$23 $not$libresoc.v:50035$3082_Y + connect \$31 $and$libresoc.v:50036$3083_Y + connect \$33 $reduce_or$libresoc.v:50037$3084_Y + connect \$35 $reduce_or$libresoc.v:50038$3085_Y + connect \$37 $or$libresoc.v:50039$3086_Y + connect \$3 $and$libresoc.v:50040$3087_Y + connect \$39 $not$libresoc.v:50041$3088_Y + connect \$41 $and$libresoc.v:50042$3089_Y + connect \$43 $and$libresoc.v:50043$3090_Y + connect \$45 $eq$libresoc.v:50044$3091_Y + connect \$47 $and$libresoc.v:50045$3092_Y + connect \$49 $eq$libresoc.v:50046$3093_Y + connect \$51 $and$libresoc.v:50047$3094_Y + connect \$53 $and$libresoc.v:50048$3095_Y + connect \$55 $and$libresoc.v:50049$3096_Y + connect \$57 $or$libresoc.v:50050$3097_Y + connect \$59 $or$libresoc.v:50051$3098_Y + connect \$61 $or$libresoc.v:50052$3099_Y + connect \$63 $or$libresoc.v:50053$3100_Y + connect \$65 $and$libresoc.v:50054$3101_Y + connect \$67 $and$libresoc.v:50055$3102_Y + connect \$6 $not$libresoc.v:50056$3103_Y + connect \$69 $or$libresoc.v:50057$3104_Y + connect \$71 $and$libresoc.v:50058$3105_Y + connect \$73 $and$libresoc.v:50059$3106_Y + connect \$75 $and$libresoc.v:50060$3107_Y + connect \$77 $ternary$libresoc.v:50061$3108_Y + connect \$79 $ternary$libresoc.v:50062$3109_Y + connect \$81 $ternary$libresoc.v:50063$3110_Y + connect \$83 $ternary$libresoc.v:50064$3111_Y + connect \$85 $ternary$libresoc.v:50065$3112_Y + connect \$87 $ternary$libresoc.v:50066$3113_Y + connect \$8 $or$libresoc.v:50067$3114_Y + connect \$89 $and$libresoc.v:50068$3115_Y + connect \$91 $and$libresoc.v:50069$3116_Y + connect \$93 $and$libresoc.v:50070$3117_Y + connect \$95 $and$libresoc.v:50071$3118_Y + connect \$97 $not$libresoc.v:50072$3119_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -89452,41 +89454,65 @@ module \cr0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:50532.1-50635.10" +attribute \src "libresoc.v:50534.1-50697.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.crin_svdec" attribute \generator "nMigen" module \crin_svdec - attribute \src "libresoc.v:50622.3-50633.6" + attribute \src "libresoc.v:50683.3-50694.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:50533.7-50533.20" + attribute \src "libresoc.v:50632.3-50648.6" + wire width 3 $0\extra3_idx0[2:0] + attribute \src "libresoc.v:50649.3-50665.6" + wire width 3 $0\extra3_idx1[2:0] + attribute \src "libresoc.v:50666.3-50682.6" + wire width 3 $0\extra3_idx2[2:0] + attribute \src "libresoc.v:50535.7-50535.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50563.3-50621.6" + attribute \src "libresoc.v:50573.3-50631.6" wire width 3 $0\spec[2:0] - attribute \src "libresoc.v:50622.3-50633.6" + attribute \src "libresoc.v:50683.3-50694.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:50563.3-50621.6" + attribute \src "libresoc.v:50632.3-50648.6" + wire width 3 $1\extra3_idx0[2:0] + attribute \src "libresoc.v:50649.3-50665.6" + wire width 3 $1\extra3_idx1[2:0] + attribute \src "libresoc.v:50666.3-50682.6" + wire width 3 $1\extra3_idx2[2:0] + attribute \src "libresoc.v:50573.3-50631.6" wire width 3 $1\spec[2:0] - attribute \src "libresoc.v:50563.3-50621.6" + attribute \src "libresoc.v:50632.3-50648.6" + wire width 3 $2\extra3_idx0[2:0] + attribute \src "libresoc.v:50649.3-50665.6" + wire width 3 $2\extra3_idx1[2:0] + attribute \src "libresoc.v:50666.3-50682.6" + wire width 3 $2\extra3_idx2[2:0] + attribute \src "libresoc.v:50573.3-50631.6" wire width 2 $2\spec[2:1] - attribute \src "libresoc.v:50563.3-50621.6" + attribute \src "libresoc.v:50573.3-50631.6" wire width 3 $3\spec[2:0] - attribute \src "libresoc.v:50562.17-50562.119" - wire width 7 $pos$libresoc.v:50562$3273_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + attribute \src "libresoc.v:50572.17-50572.121" + wire width 7 $pos$libresoc.v:50572$3273_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157" wire width 7 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130" wire width 3 input 4 \cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131" wire width 7 output 5 \cr_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 input 3 \etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 input 2 \extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57" + wire width 3 \extra3_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60" + wire width 3 \extra3_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63" + wire width 3 \extra3_idx2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -89494,48 +89520,50 @@ module \crin_svdec attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 input 1 \idx - attribute \src "libresoc.v:50533.7-50533.15" + attribute \src "libresoc.v:50535.7-50535.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132" wire output 6 \isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25" wire width 3 \spec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" - cell $pos $pos$libresoc.v:50562$3273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:148" + wire width 2 \spec_aug + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157" + cell $pos $pos$libresoc.v:50572$3273 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A { 2'00 \spec [1:0] \cr_in } - connect \Y $pos$libresoc.v:50562$3273_Y + connect \A { 2'00 \spec_aug \cr_in } + connect \Y $pos$libresoc.v:50572$3273_Y end - attribute \src "libresoc.v:50533.7-50533.20" - process $proc$libresoc.v:50533$3276 + attribute \src "libresoc.v:50535.7-50535.20" + process $proc$libresoc.v:50535$3279 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50563.3-50621.6" - process $proc$libresoc.v:50563$3274 + attribute \src "libresoc.v:50573.3-50631.6" + process $proc$libresoc.v:50573$3274 assign { } { } assign { } { } assign $0\spec[2:0] $1\spec[2:0] - attribute \src "libresoc.v:50564.5-50564.29" + attribute \src "libresoc.v:50574.5-50574.29" switch \initial - attribute \src "libresoc.v:50564.9-50564.17" + attribute \src "libresoc.v:50574.9-50574.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" switch \etype attribute \src "libresoc.v:0.0-0.0" case 2'01 assign $1\spec[2:0] [0] 1'0 assign $1\spec[2:0] [2:1] $2\spec[2:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40" switch \idx attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -89564,20 +89592,20 @@ module \crin_svdec case 2'10 assign { } { } assign $1\spec[2:0] $3\spec[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" switch \idx attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $3\spec[2:0] \extra [8:6] + assign $3\spec[2:0] \extra3_idx0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $3\spec[2:0] \extra [5:3] + assign $3\spec[2:0] \extra3_idx1 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $3\spec[2:0] \extra [2:0] + assign $3\spec[2:0] \extra3_idx2 case assign $3\spec[2:0] 3'000 end @@ -89587,22 +89615,118 @@ module \crin_svdec sync always update \spec $0\spec[2:0] end - attribute \src "libresoc.v:50622.3-50633.6" - process $proc$libresoc.v:50622$3275 + attribute \src "libresoc.v:50632.3-50648.6" + process $proc$libresoc.v:50632$3275 + assign { } { } + assign { } { } + assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0] + attribute \src "libresoc.v:50633.5-50633.29" + switch \initial + attribute \src "libresoc.v:50633.9-50633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\extra3_idx0[2:0] \extra [8:6] + case + assign $2\extra3_idx0[2:0] 3'000 + end + case + assign $1\extra3_idx0[2:0] 3'000 + end + sync always + update \extra3_idx0 $0\extra3_idx0[2:0] + end + attribute \src "libresoc.v:50649.3-50665.6" + process $proc$libresoc.v:50649$3276 + assign { } { } + assign { } { } + assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0] + attribute \src "libresoc.v:50650.5-50650.29" + switch \initial + attribute \src "libresoc.v:50650.9-50650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\extra3_idx1[2:0] \extra [5:3] + case + assign $2\extra3_idx1[2:0] 3'000 + end + case + assign $1\extra3_idx1[2:0] 3'000 + end + sync always + update \extra3_idx1 $0\extra3_idx1[2:0] + end + attribute \src "libresoc.v:50666.3-50682.6" + process $proc$libresoc.v:50666$3277 + assign { } { } + assign { } { } + assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0] + attribute \src "libresoc.v:50667.5-50667.29" + switch \initial + attribute \src "libresoc.v:50667.9-50667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\extra3_idx2[2:0] \extra [2:0] + case + assign $2\extra3_idx2[2:0] 3'000 + end + case + assign $1\extra3_idx2[2:0] 3'000 + end + sync always + update \extra3_idx2 $0\extra3_idx2[2:0] + end + attribute \src "libresoc.v:50683.3-50694.6" + process $proc$libresoc.v:50683$3278 assign { } { } assign $0\cr_out[6:0] $1\cr_out[6:0] - attribute \src "libresoc.v:50623.5-50623.29" + attribute \src "libresoc.v:50684.5-50684.29" switch \initial - attribute \src "libresoc.v:50623.9-50623.17" + attribute \src "libresoc.v:50684.9-50684.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:152" switch \isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\cr_out[6:0] { \cr_in \spec [1:0] 2'00 } + assign $1\cr_out[6:0] { \cr_in \spec_aug 2'00 } attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -89611,44 +89735,69 @@ module \crin_svdec sync always update \cr_out $0\cr_out[6:0] end - connect \$1 $pos$libresoc.v:50562$3273_Y + connect \$1 $pos$libresoc.v:50572$3273_Y + connect \spec_aug \spec [1:0] connect \isvec \spec [2] end -attribute \src "libresoc.v:50639.1-50742.10" +attribute \src "libresoc.v:50701.1-50864.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.crin_svdec_b" attribute \generator "nMigen" module \crin_svdec_b - attribute \src "libresoc.v:50729.3-50740.6" + attribute \src "libresoc.v:50850.3-50861.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:50640.7-50640.20" + attribute \src "libresoc.v:50799.3-50815.6" + wire width 3 $0\extra3_idx0[2:0] + attribute \src "libresoc.v:50816.3-50832.6" + wire width 3 $0\extra3_idx1[2:0] + attribute \src "libresoc.v:50833.3-50849.6" + wire width 3 $0\extra3_idx2[2:0] + attribute \src "libresoc.v:50702.7-50702.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50670.3-50728.6" + attribute \src "libresoc.v:50740.3-50798.6" wire width 3 $0\spec[2:0] - attribute \src "libresoc.v:50729.3-50740.6" + attribute \src "libresoc.v:50850.3-50861.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:50670.3-50728.6" + attribute \src "libresoc.v:50799.3-50815.6" + wire width 3 $1\extra3_idx0[2:0] + attribute \src "libresoc.v:50816.3-50832.6" + wire width 3 $1\extra3_idx1[2:0] + attribute \src "libresoc.v:50833.3-50849.6" + wire width 3 $1\extra3_idx2[2:0] + attribute \src "libresoc.v:50740.3-50798.6" wire width 3 $1\spec[2:0] - attribute \src "libresoc.v:50670.3-50728.6" + attribute \src "libresoc.v:50799.3-50815.6" + wire width 3 $2\extra3_idx0[2:0] + attribute \src "libresoc.v:50816.3-50832.6" + wire width 3 $2\extra3_idx1[2:0] + attribute \src "libresoc.v:50833.3-50849.6" + wire width 3 $2\extra3_idx2[2:0] + attribute \src "libresoc.v:50740.3-50798.6" wire width 2 $2\spec[2:1] - attribute \src "libresoc.v:50670.3-50728.6" + attribute \src "libresoc.v:50740.3-50798.6" wire width 3 $3\spec[2:0] - attribute \src "libresoc.v:50669.17-50669.119" - wire width 7 $pos$libresoc.v:50669$3277_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + attribute \src "libresoc.v:50739.17-50739.121" + wire width 7 $pos$libresoc.v:50739$3280_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157" wire width 7 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130" wire width 3 input 4 \cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131" wire width 7 output 5 \cr_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 input 3 \etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 input 2 \extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57" + wire width 3 \extra3_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60" + wire width 3 \extra3_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63" + wire width 3 \extra3_idx2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -89656,48 +89805,50 @@ module \crin_svdec_b attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 input 1 \idx - attribute \src "libresoc.v:50640.7-50640.15" + attribute \src "libresoc.v:50702.7-50702.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132" wire output 6 \isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25" wire width 3 \spec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" - cell $pos $pos$libresoc.v:50669$3277 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:148" + wire width 2 \spec_aug + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157" + cell $pos $pos$libresoc.v:50739$3280 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A { 2'00 \spec [1:0] \cr_in } - connect \Y $pos$libresoc.v:50669$3277_Y + connect \A { 2'00 \spec_aug \cr_in } + connect \Y $pos$libresoc.v:50739$3280_Y end - attribute \src "libresoc.v:50640.7-50640.20" - process $proc$libresoc.v:50640$3280 + attribute \src "libresoc.v:50702.7-50702.20" + process $proc$libresoc.v:50702$3286 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50670.3-50728.6" - process $proc$libresoc.v:50670$3278 + attribute \src "libresoc.v:50740.3-50798.6" + process $proc$libresoc.v:50740$3281 assign { } { } assign { } { } assign $0\spec[2:0] $1\spec[2:0] - attribute \src "libresoc.v:50671.5-50671.29" + attribute \src "libresoc.v:50741.5-50741.29" switch \initial - attribute \src "libresoc.v:50671.9-50671.17" + attribute \src "libresoc.v:50741.9-50741.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" switch \etype attribute \src "libresoc.v:0.0-0.0" case 2'01 assign $1\spec[2:0] [0] 1'0 assign $1\spec[2:0] [2:1] $2\spec[2:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40" switch \idx attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -89726,20 +89877,20 @@ module \crin_svdec_b case 2'10 assign { } { } assign $1\spec[2:0] $3\spec[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" switch \idx attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $3\spec[2:0] \extra [8:6] + assign $3\spec[2:0] \extra3_idx0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $3\spec[2:0] \extra [5:3] + assign $3\spec[2:0] \extra3_idx1 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $3\spec[2:0] \extra [2:0] + assign $3\spec[2:0] \extra3_idx2 case assign $3\spec[2:0] 3'000 end @@ -89749,22 +89900,118 @@ module \crin_svdec_b sync always update \spec $0\spec[2:0] end - attribute \src "libresoc.v:50729.3-50740.6" - process $proc$libresoc.v:50729$3279 + attribute \src "libresoc.v:50799.3-50815.6" + process $proc$libresoc.v:50799$3282 + assign { } { } + assign { } { } + assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0] + attribute \src "libresoc.v:50800.5-50800.29" + switch \initial + attribute \src "libresoc.v:50800.9-50800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\extra3_idx0[2:0] \extra [8:6] + case + assign $2\extra3_idx0[2:0] 3'000 + end + case + assign $1\extra3_idx0[2:0] 3'000 + end + sync always + update \extra3_idx0 $0\extra3_idx0[2:0] + end + attribute \src "libresoc.v:50816.3-50832.6" + process $proc$libresoc.v:50816$3283 + assign { } { } + assign { } { } + assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0] + attribute \src "libresoc.v:50817.5-50817.29" + switch \initial + attribute \src "libresoc.v:50817.9-50817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\extra3_idx1[2:0] \extra [5:3] + case + assign $2\extra3_idx1[2:0] 3'000 + end + case + assign $1\extra3_idx1[2:0] 3'000 + end + sync always + update \extra3_idx1 $0\extra3_idx1[2:0] + end + attribute \src "libresoc.v:50833.3-50849.6" + process $proc$libresoc.v:50833$3284 + assign { } { } + assign { } { } + assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0] + attribute \src "libresoc.v:50834.5-50834.29" + switch \initial + attribute \src "libresoc.v:50834.9-50834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\extra3_idx2[2:0] \extra [2:0] + case + assign $2\extra3_idx2[2:0] 3'000 + end + case + assign $1\extra3_idx2[2:0] 3'000 + end + sync always + update \extra3_idx2 $0\extra3_idx2[2:0] + end + attribute \src "libresoc.v:50850.3-50861.6" + process $proc$libresoc.v:50850$3285 assign { } { } assign $0\cr_out[6:0] $1\cr_out[6:0] - attribute \src "libresoc.v:50730.5-50730.29" + attribute \src "libresoc.v:50851.5-50851.29" switch \initial - attribute \src "libresoc.v:50730.9-50730.17" + attribute \src "libresoc.v:50851.9-50851.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:152" switch \isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\cr_out[6:0] { \cr_in \spec [1:0] 2'00 } + assign $1\cr_out[6:0] { \cr_in \spec_aug 2'00 } attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -89773,44 +90020,69 @@ module \crin_svdec_b sync always update \cr_out $0\cr_out[6:0] end - connect \$1 $pos$libresoc.v:50669$3277_Y + connect \$1 $pos$libresoc.v:50739$3280_Y + connect \spec_aug \spec [1:0] connect \isvec \spec [2] end -attribute \src "libresoc.v:50746.1-50849.10" +attribute \src "libresoc.v:50868.1-51031.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.crin_svdec_o" attribute \generator "nMigen" module \crin_svdec_o - attribute \src "libresoc.v:50836.3-50847.6" + attribute \src "libresoc.v:51017.3-51028.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:50747.7-50747.20" + attribute \src "libresoc.v:50966.3-50982.6" + wire width 3 $0\extra3_idx0[2:0] + attribute \src "libresoc.v:50983.3-50999.6" + wire width 3 $0\extra3_idx1[2:0] + attribute \src "libresoc.v:51000.3-51016.6" + wire width 3 $0\extra3_idx2[2:0] + attribute \src "libresoc.v:50869.7-50869.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50777.3-50835.6" + attribute \src "libresoc.v:50907.3-50965.6" wire width 3 $0\spec[2:0] - attribute \src "libresoc.v:50836.3-50847.6" + attribute \src "libresoc.v:51017.3-51028.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:50777.3-50835.6" + attribute \src "libresoc.v:50966.3-50982.6" + wire width 3 $1\extra3_idx0[2:0] + attribute \src "libresoc.v:50983.3-50999.6" + wire width 3 $1\extra3_idx1[2:0] + attribute \src "libresoc.v:51000.3-51016.6" + wire width 3 $1\extra3_idx2[2:0] + attribute \src "libresoc.v:50907.3-50965.6" wire width 3 $1\spec[2:0] - attribute \src "libresoc.v:50777.3-50835.6" + attribute \src "libresoc.v:50966.3-50982.6" + wire width 3 $2\extra3_idx0[2:0] + attribute \src "libresoc.v:50983.3-50999.6" + wire width 3 $2\extra3_idx1[2:0] + attribute \src "libresoc.v:51000.3-51016.6" + wire width 3 $2\extra3_idx2[2:0] + attribute \src "libresoc.v:50907.3-50965.6" wire width 2 $2\spec[2:1] - attribute \src "libresoc.v:50777.3-50835.6" + attribute \src "libresoc.v:50907.3-50965.6" wire width 3 $3\spec[2:0] - attribute \src "libresoc.v:50776.17-50776.119" - wire width 7 $pos$libresoc.v:50776$3281_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + attribute \src "libresoc.v:50906.17-50906.121" + wire width 7 $pos$libresoc.v:50906$3287_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157" wire width 7 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130" wire width 3 input 4 \cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131" wire width 7 output 5 \cr_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 input 3 \etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 input 2 \extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57" + wire width 3 \extra3_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60" + wire width 3 \extra3_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63" + wire width 3 \extra3_idx2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -89818,48 +90090,50 @@ module \crin_svdec_o attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 input 1 \idx - attribute \src "libresoc.v:50747.7-50747.15" + attribute \src "libresoc.v:50869.7-50869.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132" wire output 6 \isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25" wire width 3 \spec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" - cell $pos $pos$libresoc.v:50776$3281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:148" + wire width 2 \spec_aug + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157" + cell $pos $pos$libresoc.v:50906$3287 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A { 2'00 \spec [1:0] \cr_in } - connect \Y $pos$libresoc.v:50776$3281_Y + connect \A { 2'00 \spec_aug \cr_in } + connect \Y $pos$libresoc.v:50906$3287_Y end - attribute \src "libresoc.v:50747.7-50747.20" - process $proc$libresoc.v:50747$3284 + attribute \src "libresoc.v:50869.7-50869.20" + process $proc$libresoc.v:50869$3293 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50777.3-50835.6" - process $proc$libresoc.v:50777$3282 + attribute \src "libresoc.v:50907.3-50965.6" + process $proc$libresoc.v:50907$3288 assign { } { } assign { } { } assign $0\spec[2:0] $1\spec[2:0] - attribute \src "libresoc.v:50778.5-50778.29" + attribute \src "libresoc.v:50908.5-50908.29" switch \initial - attribute \src "libresoc.v:50778.9-50778.17" + attribute \src "libresoc.v:50908.9-50908.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" switch \etype attribute \src "libresoc.v:0.0-0.0" case 2'01 assign $1\spec[2:0] [0] 1'0 assign $1\spec[2:0] [2:1] $2\spec[2:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40" switch \idx attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -89888,20 +90162,20 @@ module \crin_svdec_o case 2'10 assign { } { } assign $1\spec[2:0] $3\spec[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" switch \idx attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $3\spec[2:0] \extra [8:6] + assign $3\spec[2:0] \extra3_idx0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $3\spec[2:0] \extra [5:3] + assign $3\spec[2:0] \extra3_idx1 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $3\spec[2:0] \extra [2:0] + assign $3\spec[2:0] \extra3_idx2 case assign $3\spec[2:0] 3'000 end @@ -89911,22 +90185,118 @@ module \crin_svdec_o sync always update \spec $0\spec[2:0] end - attribute \src "libresoc.v:50836.3-50847.6" - process $proc$libresoc.v:50836$3283 + attribute \src "libresoc.v:50966.3-50982.6" + process $proc$libresoc.v:50966$3289 + assign { } { } + assign { } { } + assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0] + attribute \src "libresoc.v:50967.5-50967.29" + switch \initial + attribute \src "libresoc.v:50967.9-50967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\extra3_idx0[2:0] \extra [8:6] + case + assign $2\extra3_idx0[2:0] 3'000 + end + case + assign $1\extra3_idx0[2:0] 3'000 + end + sync always + update \extra3_idx0 $0\extra3_idx0[2:0] + end + attribute \src "libresoc.v:50983.3-50999.6" + process $proc$libresoc.v:50983$3290 + assign { } { } + assign { } { } + assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0] + attribute \src "libresoc.v:50984.5-50984.29" + switch \initial + attribute \src "libresoc.v:50984.9-50984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\extra3_idx1[2:0] \extra [5:3] + case + assign $2\extra3_idx1[2:0] 3'000 + end + case + assign $1\extra3_idx1[2:0] 3'000 + end + sync always + update \extra3_idx1 $0\extra3_idx1[2:0] + end + attribute \src "libresoc.v:51000.3-51016.6" + process $proc$libresoc.v:51000$3291 + assign { } { } + assign { } { } + assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0] + attribute \src "libresoc.v:51001.5-51001.29" + switch \initial + attribute \src "libresoc.v:51001.9-51001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\extra3_idx2[2:0] \extra [2:0] + case + assign $2\extra3_idx2[2:0] 3'000 + end + case + assign $1\extra3_idx2[2:0] 3'000 + end + sync always + update \extra3_idx2 $0\extra3_idx2[2:0] + end + attribute \src "libresoc.v:51017.3-51028.6" + process $proc$libresoc.v:51017$3292 assign { } { } assign $0\cr_out[6:0] $1\cr_out[6:0] - attribute \src "libresoc.v:50837.5-50837.29" + attribute \src "libresoc.v:51018.5-51018.29" switch \initial - attribute \src "libresoc.v:50837.9-50837.17" + attribute \src "libresoc.v:51018.9-51018.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:152" switch \isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\cr_out[6:0] { \cr_in \spec [1:0] 2'00 } + assign $1\cr_out[6:0] { \cr_in \spec_aug 2'00 } attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -89935,44 +90305,69 @@ module \crin_svdec_o sync always update \cr_out $0\cr_out[6:0] end - connect \$1 $pos$libresoc.v:50776$3281_Y + connect \$1 $pos$libresoc.v:50906$3287_Y + connect \spec_aug \spec [1:0] connect \isvec \spec [2] end -attribute \src "libresoc.v:50853.1-50956.10" +attribute \src "libresoc.v:51035.1-51198.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.crout_svdec" attribute \generator "nMigen" module \crout_svdec - attribute \src "libresoc.v:50943.3-50954.6" + attribute \src "libresoc.v:51184.3-51195.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:50854.7-50854.20" + attribute \src "libresoc.v:51133.3-51149.6" + wire width 3 $0\extra3_idx0[2:0] + attribute \src "libresoc.v:51150.3-51166.6" + wire width 3 $0\extra3_idx1[2:0] + attribute \src "libresoc.v:51167.3-51183.6" + wire width 3 $0\extra3_idx2[2:0] + attribute \src "libresoc.v:51036.7-51036.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50884.3-50942.6" + attribute \src "libresoc.v:51074.3-51132.6" wire width 3 $0\spec[2:0] - attribute \src "libresoc.v:50943.3-50954.6" + attribute \src "libresoc.v:51184.3-51195.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:50884.3-50942.6" + attribute \src "libresoc.v:51133.3-51149.6" + wire width 3 $1\extra3_idx0[2:0] + attribute \src "libresoc.v:51150.3-51166.6" + wire width 3 $1\extra3_idx1[2:0] + attribute \src "libresoc.v:51167.3-51183.6" + wire width 3 $1\extra3_idx2[2:0] + attribute \src "libresoc.v:51074.3-51132.6" wire width 3 $1\spec[2:0] - attribute \src "libresoc.v:50884.3-50942.6" + attribute \src "libresoc.v:51133.3-51149.6" + wire width 3 $2\extra3_idx0[2:0] + attribute \src "libresoc.v:51150.3-51166.6" + wire width 3 $2\extra3_idx1[2:0] + attribute \src "libresoc.v:51167.3-51183.6" + wire width 3 $2\extra3_idx2[2:0] + attribute \src "libresoc.v:51074.3-51132.6" wire width 2 $2\spec[2:1] - attribute \src "libresoc.v:50884.3-50942.6" + attribute \src "libresoc.v:51074.3-51132.6" wire width 3 $3\spec[2:0] - attribute \src "libresoc.v:50883.17-50883.119" - wire width 7 $pos$libresoc.v:50883$3285_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + attribute \src "libresoc.v:51073.17-51073.121" + wire width 7 $pos$libresoc.v:51073$3294_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157" wire width 7 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130" wire width 3 input 4 \cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131" wire width 7 output 5 \cr_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 input 3 \etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 input 2 \extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57" + wire width 3 \extra3_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60" + wire width 3 \extra3_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63" + wire width 3 \extra3_idx2 attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" attribute \enum_value_001 "Idx0" @@ -89980,48 +90375,50 @@ module \crout_svdec attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 input 6 \idx - attribute \src "libresoc.v:50854.7-50854.15" + attribute \src "libresoc.v:51036.7-51036.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132" wire output 1 \isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25" wire width 3 \spec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" - cell $pos $pos$libresoc.v:50883$3285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:148" + wire width 2 \spec_aug + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:157" + cell $pos $pos$libresoc.v:51073$3294 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A { 2'00 \spec [1:0] \cr_in } - connect \Y $pos$libresoc.v:50883$3285_Y + connect \A { 2'00 \spec_aug \cr_in } + connect \Y $pos$libresoc.v:51073$3294_Y end - attribute \src "libresoc.v:50854.7-50854.20" - process $proc$libresoc.v:50854$3288 + attribute \src "libresoc.v:51036.7-51036.20" + process $proc$libresoc.v:51036$3300 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50884.3-50942.6" - process $proc$libresoc.v:50884$3286 + attribute \src "libresoc.v:51074.3-51132.6" + process $proc$libresoc.v:51074$3295 assign { } { } assign { } { } assign $0\spec[2:0] $1\spec[2:0] - attribute \src "libresoc.v:50885.5-50885.29" + attribute \src "libresoc.v:51075.5-51075.29" switch \initial - attribute \src "libresoc.v:50885.9-50885.17" + attribute \src "libresoc.v:51075.9-51075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" switch \etype attribute \src "libresoc.v:0.0-0.0" case 2'01 assign $1\spec[2:0] [0] 1'0 assign $1\spec[2:0] [2:1] $2\spec[2:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40" switch \idx attribute \src "libresoc.v:0.0-0.0" case 3'001 @@ -90050,20 +90447,20 @@ module \crout_svdec case 2'10 assign { } { } assign $1\spec[2:0] $3\spec[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" switch \idx attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $3\spec[2:0] \extra [8:6] + assign $3\spec[2:0] \extra3_idx0 attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $3\spec[2:0] \extra [5:3] + assign $3\spec[2:0] \extra3_idx1 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $3\spec[2:0] \extra [2:0] + assign $3\spec[2:0] \extra3_idx2 case assign $3\spec[2:0] 3'000 end @@ -90073,22 +90470,118 @@ module \crout_svdec sync always update \spec $0\spec[2:0] end - attribute \src "libresoc.v:50943.3-50954.6" - process $proc$libresoc.v:50943$3287 + attribute \src "libresoc.v:51133.3-51149.6" + process $proc$libresoc.v:51133$3296 + assign { } { } + assign { } { } + assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0] + attribute \src "libresoc.v:51134.5-51134.29" + switch \initial + attribute \src "libresoc.v:51134.9-51134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\extra3_idx0[2:0] \extra [8:6] + case + assign $2\extra3_idx0[2:0] 3'000 + end + case + assign $1\extra3_idx0[2:0] 3'000 + end + sync always + update \extra3_idx0 $0\extra3_idx0[2:0] + end + attribute \src "libresoc.v:51150.3-51166.6" + process $proc$libresoc.v:51150$3297 + assign { } { } + assign { } { } + assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0] + attribute \src "libresoc.v:51151.5-51151.29" + switch \initial + attribute \src "libresoc.v:51151.9-51151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\extra3_idx1[2:0] \extra [5:3] + case + assign $2\extra3_idx1[2:0] 3'000 + end + case + assign $1\extra3_idx1[2:0] 3'000 + end + sync always + update \extra3_idx1 $0\extra3_idx1[2:0] + end + attribute \src "libresoc.v:51167.3-51183.6" + process $proc$libresoc.v:51167$3298 + assign { } { } + assign { } { } + assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0] + attribute \src "libresoc.v:51168.5-51168.29" + switch \initial + attribute \src "libresoc.v:51168.9-51168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\extra3_idx2[2:0] \extra [2:0] + case + assign $2\extra3_idx2[2:0] 3'000 + end + case + assign $1\extra3_idx2[2:0] 3'000 + end + sync always + update \extra3_idx2 $0\extra3_idx2[2:0] + end + attribute \src "libresoc.v:51184.3-51195.6" + process $proc$libresoc.v:51184$3299 assign { } { } assign $0\cr_out[6:0] $1\cr_out[6:0] - attribute \src "libresoc.v:50944.5-50944.29" + attribute \src "libresoc.v:51185.5-51185.29" switch \initial - attribute \src "libresoc.v:50944.9-50944.17" + attribute \src "libresoc.v:51185.9-51185.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:152" switch \isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\cr_out[6:0] { \cr_in \spec [1:0] 2'00 } + assign $1\cr_out[6:0] { \cr_in \spec_aug 2'00 } attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -90097,34 +90590,35 @@ module \crout_svdec sync always update \cr_out $0\cr_out[6:0] end - connect \$1 $pos$libresoc.v:50883$3285_Y + connect \$1 $pos$libresoc.v:51073$3294_Y + connect \spec_aug \spec [1:0] connect \isvec \spec [2] end -attribute \src "libresoc.v:50960.1-51009.10" +attribute \src "libresoc.v:51202.1-51251.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" attribute \generator "nMigen" module \cyc_l - attribute \src "libresoc.v:50961.7-50961.20" + attribute \src "libresoc.v:51203.7-51203.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50997.3-51005.6" - wire $0\q_int$next[0:0]$3296 - attribute \src "libresoc.v:50995.3-50996.27" + attribute \src "libresoc.v:51239.3-51247.6" + wire $0\q_int$next[0:0]$3308 + attribute \src "libresoc.v:51237.3-51238.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:50997.3-51005.6" - wire $1\q_int$next[0:0]$3297 - attribute \src "libresoc.v:50979.7-50979.19" + attribute \src "libresoc.v:51239.3-51247.6" + wire $1\q_int$next[0:0]$3309 + attribute \src "libresoc.v:51221.7-51221.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:50992.17-50992.96" - wire $and$libresoc.v:50992$3291_Y - attribute \src "libresoc.v:50991.17-50991.92" - wire $not$libresoc.v:50991$3290_Y - attribute \src "libresoc.v:50994.17-50994.92" - wire $not$libresoc.v:50994$3293_Y - attribute \src "libresoc.v:50990.17-50990.98" - wire $or$libresoc.v:50990$3289_Y - attribute \src "libresoc.v:50993.17-50993.97" - wire $or$libresoc.v:50993$3292_Y + attribute \src "libresoc.v:51234.17-51234.96" + wire $and$libresoc.v:51234$3303_Y + attribute \src "libresoc.v:51233.17-51233.92" + wire $not$libresoc.v:51233$3302_Y + attribute \src "libresoc.v:51236.17-51236.92" + wire $not$libresoc.v:51236$3305_Y + attribute \src "libresoc.v:51232.17-51232.98" + wire $or$libresoc.v:51232$3301_Y + attribute \src "libresoc.v:51235.17-51235.97" + wire $or$libresoc.v:51235$3304_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -90135,11 +90629,11 @@ module \cyc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:50961.7-50961.15" + attribute \src "libresoc.v:51203.7-51203.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_cyc @@ -90156,7 +90650,7 @@ module \cyc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:50992$3291 + cell $and $and$libresoc.v:51234$3303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90164,26 +90658,26 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:50992$3291_Y + connect \Y $and$libresoc.v:51234$3303_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:50991$3290 + cell $not $not$libresoc.v:51233$3302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_cyc - connect \Y $not$libresoc.v:50991$3290_Y + connect \Y $not$libresoc.v:51233$3302_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:50994$3293 + cell $not $not$libresoc.v:51236$3305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc - connect \Y $not$libresoc.v:50994$3293_Y + connect \Y $not$libresoc.v:51236$3305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:50990$3289 + cell $or $or$libresoc.v:51232$3301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90191,10 +90685,10 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_cyc connect \B \q_int - connect \Y $or$libresoc.v:50990$3289_Y + connect \Y $or$libresoc.v:51232$3301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:50993$3292 + cell $or $or$libresoc.v:51235$3304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90202,39 +90696,39 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_cyc - connect \Y $or$libresoc.v:50993$3292_Y + connect \Y $or$libresoc.v:51235$3304_Y end - attribute \src "libresoc.v:50961.7-50961.20" - process $proc$libresoc.v:50961$3298 + attribute \src "libresoc.v:51203.7-51203.20" + process $proc$libresoc.v:51203$3310 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50979.7-50979.19" - process $proc$libresoc.v:50979$3299 + attribute \src "libresoc.v:51221.7-51221.19" + process $proc$libresoc.v:51221$3311 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:50995.3-50996.27" - process $proc$libresoc.v:50995$3294 + attribute \src "libresoc.v:51237.3-51238.27" + process $proc$libresoc.v:51237$3306 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:50997.3-51005.6" - process $proc$libresoc.v:50997$3295 + attribute \src "libresoc.v:51239.3-51247.6" + process $proc$libresoc.v:51239$3307 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$3296 $1\q_int$next[0:0]$3297 - attribute \src "libresoc.v:50998.5-50998.29" + assign $0\q_int$next[0:0]$3308 $1\q_int$next[0:0]$3309 + attribute \src "libresoc.v:51240.5-51240.29" switch \initial - attribute \src "libresoc.v:50998.9-50998.17" + attribute \src "libresoc.v:51240.9-51240.17" case 1'1 case end @@ -90243,329 +90737,329 @@ module \cyc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$3297 1'0 + assign $1\q_int$next[0:0]$3309 1'0 case - assign $1\q_int$next[0:0]$3297 \$5 + assign $1\q_int$next[0:0]$3309 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$3296 + update \q_int$next $0\q_int$next[0:0]$3308 end - connect \$9 $or$libresoc.v:50990$3289_Y - connect \$1 $not$libresoc.v:50991$3290_Y - connect \$3 $and$libresoc.v:50992$3291_Y - connect \$5 $or$libresoc.v:50993$3292_Y - connect \$7 $not$libresoc.v:50994$3293_Y + connect \$9 $or$libresoc.v:51232$3301_Y + connect \$1 $not$libresoc.v:51233$3302_Y + connect \$3 $and$libresoc.v:51234$3303_Y + connect \$5 $or$libresoc.v:51235$3304_Y + connect \$7 $not$libresoc.v:51236$3305_Y connect \qlq_cyc \$9 connect \qn_cyc \$7 connect \q_cyc \q_int end -attribute \src "libresoc.v:51013.1-51727.10" +attribute \src "libresoc.v:51255.1-51969.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" module \dbg - attribute \src "libresoc.v:51543.3-51552.6" + attribute \src "libresoc.v:51785.3-51794.6" wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:51350.3-51359.6" + attribute \src "libresoc.v:51592.3-51601.6" wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:51553.3-51562.6" + attribute \src "libresoc.v:51795.3-51804.6" wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:51332.3-51349.6" + attribute \src "libresoc.v:51574.3-51591.6" wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:51563.3-51593.6" + attribute \src "libresoc.v:51805.3-51835.6" wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:51534.3-51542.6" - wire $0\dmi_read_log_data$next[0:0]$3413 - attribute \src "libresoc.v:51310.3-51311.51" + attribute \src "libresoc.v:51776.3-51784.6" + wire $0\dmi_read_log_data$next[0:0]$3425 + attribute \src "libresoc.v:51552.3-51553.51" wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51525.3-51533.6" - wire $0\dmi_read_log_data_1$next[0:0]$3410 - attribute \src "libresoc.v:51312.3-51313.55" + attribute \src "libresoc.v:51767.3-51775.6" + wire $0\dmi_read_log_data_1$next[0:0]$3422 + attribute \src "libresoc.v:51554.3-51555.55" wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51360.3-51368.6" - wire $0\dmi_req_i_1$next[0:0]$3376 - attribute \src "libresoc.v:51322.3-51323.39" + attribute \src "libresoc.v:51602.3-51610.6" + wire $0\dmi_req_i_1$next[0:0]$3388 + attribute \src "libresoc.v:51564.3-51565.39" wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51684.3-51717.6" - wire $0\do_dmi_log_rd$next[0:0]$3440 - attribute \src "libresoc.v:51324.3-51325.43" + attribute \src "libresoc.v:51926.3-51959.6" + wire $0\do_dmi_log_rd$next[0:0]$3452 + attribute \src "libresoc.v:51566.3-51567.43" wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51654.3-51683.6" - wire $0\do_icreset$next[0:0]$3433 - attribute \src "libresoc.v:51326.3-51327.37" + attribute \src "libresoc.v:51896.3-51925.6" + wire $0\do_icreset$next[0:0]$3445 + attribute \src "libresoc.v:51568.3-51569.37" wire $0\do_icreset[0:0] - attribute \src "libresoc.v:51624.3-51653.6" - wire $0\do_reset$next[0:0]$3426 - attribute \src "libresoc.v:51328.3-51329.33" + attribute \src "libresoc.v:51866.3-51895.6" + wire $0\do_reset$next[0:0]$3438 + attribute \src "libresoc.v:51570.3-51571.33" wire $0\do_reset[0:0] - attribute \src "libresoc.v:51594.3-51623.6" - wire $0\do_step$next[0:0]$3419 - attribute \src "libresoc.v:51330.3-51331.31" + attribute \src "libresoc.v:51836.3-51865.6" + wire $0\do_step$next[0:0]$3431 + attribute \src "libresoc.v:51572.3-51573.31" wire $0\do_step[0:0] - attribute \src "libresoc.v:51463.3-51490.6" - wire width 7 $0\gspr_index$next[6:0]$3398 - attribute \src "libresoc.v:51316.3-51317.37" + attribute \src "libresoc.v:51705.3-51732.6" + wire width 7 $0\gspr_index$next[6:0]$3410 + attribute \src "libresoc.v:51558.3-51559.37" wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:51014.7-51014.20" + attribute \src "libresoc.v:51256.7-51256.20" wire $0\initial[0:0] - attribute \src "libresoc.v:51491.3-51524.6" - wire width 32 $0\log_dmi_addr$next[31:0]$3404 - attribute \src "libresoc.v:51314.3-51315.41" + attribute \src "libresoc.v:51733.3-51766.6" + wire width 32 $0\log_dmi_addr$next[31:0]$3416 + attribute \src "libresoc.v:51556.3-51557.41" wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:51419.3-51462.6" - wire $0\stopping$next[0:0]$3389 - attribute \src "libresoc.v:51318.3-51319.33" + attribute \src "libresoc.v:51661.3-51704.6" + wire $0\stopping$next[0:0]$3401 + attribute \src "libresoc.v:51560.3-51561.33" wire $0\stopping[0:0] - attribute \src "libresoc.v:51369.3-51418.6" - wire $0\terminated$next[0:0]$3379 - attribute \src "libresoc.v:51320.3-51321.37" + attribute \src "libresoc.v:51611.3-51660.6" + wire $0\terminated$next[0:0]$3391 + attribute \src "libresoc.v:51562.3-51563.37" wire $0\terminated[0:0] - attribute \src "libresoc.v:51543.3-51552.6" + attribute \src "libresoc.v:51785.3-51794.6" wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:51350.3-51359.6" + attribute \src "libresoc.v:51592.3-51601.6" wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51553.3-51562.6" + attribute \src "libresoc.v:51795.3-51804.6" wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:51332.3-51349.6" + attribute \src "libresoc.v:51574.3-51591.6" wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51563.3-51593.6" + attribute \src "libresoc.v:51805.3-51835.6" wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:51534.3-51542.6" - wire $1\dmi_read_log_data$next[0:0]$3414 - attribute \src "libresoc.v:51187.7-51187.31" + attribute \src "libresoc.v:51776.3-51784.6" + wire $1\dmi_read_log_data$next[0:0]$3426 + attribute \src "libresoc.v:51429.7-51429.31" wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51525.3-51533.6" - wire $1\dmi_read_log_data_1$next[0:0]$3411 - attribute \src "libresoc.v:51191.7-51191.33" + attribute \src "libresoc.v:51767.3-51775.6" + wire $1\dmi_read_log_data_1$next[0:0]$3423 + attribute \src "libresoc.v:51433.7-51433.33" wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51360.3-51368.6" - wire $1\dmi_req_i_1$next[0:0]$3377 - attribute \src "libresoc.v:51197.7-51197.25" + attribute \src "libresoc.v:51602.3-51610.6" + wire $1\dmi_req_i_1$next[0:0]$3389 + attribute \src "libresoc.v:51439.7-51439.25" wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51684.3-51717.6" - wire $1\do_dmi_log_rd$next[0:0]$3441 - attribute \src "libresoc.v:51203.7-51203.27" + attribute \src "libresoc.v:51926.3-51959.6" + wire $1\do_dmi_log_rd$next[0:0]$3453 + attribute \src "libresoc.v:51445.7-51445.27" wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51654.3-51683.6" - wire $1\do_icreset$next[0:0]$3434 - attribute \src "libresoc.v:51207.7-51207.24" + attribute \src "libresoc.v:51896.3-51925.6" + wire $1\do_icreset$next[0:0]$3446 + attribute \src "libresoc.v:51449.7-51449.24" wire $1\do_icreset[0:0] - attribute \src "libresoc.v:51624.3-51653.6" - wire $1\do_reset$next[0:0]$3427 - attribute \src "libresoc.v:51211.7-51211.22" + attribute \src "libresoc.v:51866.3-51895.6" + wire $1\do_reset$next[0:0]$3439 + attribute \src "libresoc.v:51453.7-51453.22" wire $1\do_reset[0:0] - attribute \src "libresoc.v:51594.3-51623.6" - wire $1\do_step$next[0:0]$3420 - attribute \src "libresoc.v:51215.7-51215.21" + attribute \src "libresoc.v:51836.3-51865.6" + wire $1\do_step$next[0:0]$3432 + attribute \src "libresoc.v:51457.7-51457.21" wire $1\do_step[0:0] - attribute \src "libresoc.v:51463.3-51490.6" - wire width 7 $1\gspr_index$next[6:0]$3399 - attribute \src "libresoc.v:51219.13-51219.31" + attribute \src "libresoc.v:51705.3-51732.6" + wire width 7 $1\gspr_index$next[6:0]$3411 + attribute \src "libresoc.v:51461.13-51461.31" wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:51491.3-51524.6" - wire width 32 $1\log_dmi_addr$next[31:0]$3405 - attribute \src "libresoc.v:51225.14-51225.34" + attribute \src "libresoc.v:51733.3-51766.6" + wire width 32 $1\log_dmi_addr$next[31:0]$3417 + attribute \src "libresoc.v:51467.14-51467.34" wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:51419.3-51462.6" - wire $1\stopping$next[0:0]$3390 - attribute \src "libresoc.v:51237.7-51237.22" + attribute \src "libresoc.v:51661.3-51704.6" + wire $1\stopping$next[0:0]$3402 + attribute \src "libresoc.v:51479.7-51479.22" wire $1\stopping[0:0] - attribute \src "libresoc.v:51369.3-51418.6" - wire $1\terminated$next[0:0]$3380 - attribute \src "libresoc.v:51243.7-51243.24" + attribute \src "libresoc.v:51611.3-51660.6" + wire $1\terminated$next[0:0]$3392 + attribute \src "libresoc.v:51485.7-51485.24" wire $1\terminated[0:0] - attribute \src "libresoc.v:51684.3-51717.6" - wire $2\do_dmi_log_rd$next[0:0]$3442 - attribute \src "libresoc.v:51654.3-51683.6" - wire $2\do_icreset$next[0:0]$3435 - attribute \src "libresoc.v:51624.3-51653.6" - wire $2\do_reset$next[0:0]$3428 - attribute \src "libresoc.v:51594.3-51623.6" - wire $2\do_step$next[0:0]$3421 - attribute \src "libresoc.v:51463.3-51490.6" - wire width 7 $2\gspr_index$next[6:0]$3400 - attribute \src "libresoc.v:51491.3-51524.6" - wire width 32 $2\log_dmi_addr$next[31:0]$3406 - attribute \src "libresoc.v:51419.3-51462.6" - wire $2\stopping$next[0:0]$3391 - attribute \src "libresoc.v:51369.3-51418.6" - wire $2\terminated$next[0:0]$3381 - attribute \src "libresoc.v:51684.3-51717.6" - wire $3\do_dmi_log_rd$next[0:0]$3443 - attribute \src "libresoc.v:51654.3-51683.6" - wire $3\do_icreset$next[0:0]$3436 - attribute \src "libresoc.v:51624.3-51653.6" - wire $3\do_reset$next[0:0]$3429 - attribute \src "libresoc.v:51594.3-51623.6" - wire $3\do_step$next[0:0]$3422 - attribute \src "libresoc.v:51463.3-51490.6" - wire width 7 $3\gspr_index$next[6:0]$3401 - attribute \src "libresoc.v:51491.3-51524.6" - wire width 32 $3\log_dmi_addr$next[31:0]$3407 - attribute \src "libresoc.v:51419.3-51462.6" - wire $3\stopping$next[0:0]$3392 - attribute \src "libresoc.v:51369.3-51418.6" - wire $3\terminated$next[0:0]$3382 - attribute \src "libresoc.v:51684.3-51717.6" - wire $4\do_dmi_log_rd$next[0:0]$3444 - attribute \src "libresoc.v:51654.3-51683.6" - wire $4\do_icreset$next[0:0]$3437 - attribute \src "libresoc.v:51624.3-51653.6" - wire $4\do_reset$next[0:0]$3430 - attribute \src "libresoc.v:51594.3-51623.6" - wire $4\do_step$next[0:0]$3423 - attribute \src "libresoc.v:51463.3-51490.6" - wire width 7 $4\gspr_index$next[6:0]$3402 - attribute \src "libresoc.v:51491.3-51524.6" - wire width 32 $4\log_dmi_addr$next[31:0]$3408 - attribute \src "libresoc.v:51419.3-51462.6" - wire $4\stopping$next[0:0]$3393 - attribute \src "libresoc.v:51369.3-51418.6" - wire $4\terminated$next[0:0]$3383 - attribute \src "libresoc.v:51654.3-51683.6" - wire $5\do_icreset$next[0:0]$3438 - attribute \src "libresoc.v:51624.3-51653.6" - wire $5\do_reset$next[0:0]$3431 - attribute \src "libresoc.v:51594.3-51623.6" - wire $5\do_step$next[0:0]$3424 - attribute \src "libresoc.v:51419.3-51462.6" - wire $5\stopping$next[0:0]$3394 - attribute \src "libresoc.v:51369.3-51418.6" - wire $5\terminated$next[0:0]$3384 - attribute \src "libresoc.v:51419.3-51462.6" - wire $6\stopping$next[0:0]$3395 - attribute \src "libresoc.v:51369.3-51418.6" - wire $6\terminated$next[0:0]$3385 - attribute \src "libresoc.v:51419.3-51462.6" - wire $7\stopping$next[0:0]$3396 - attribute \src "libresoc.v:51369.3-51418.6" - wire $7\terminated$next[0:0]$3386 - attribute \src "libresoc.v:51369.3-51418.6" - wire $8\terminated$next[0:0]$3387 - attribute \src "libresoc.v:51257.19-51257.110" - wire width 3 $add$libresoc.v:51257$3309_Y - attribute \src "libresoc.v:51248.17-51248.109" - wire $and$libresoc.v:51248$3300_Y - attribute \src "libresoc.v:51251.19-51251.103" - wire $and$libresoc.v:51251$3303_Y - attribute \src "libresoc.v:51253.19-51253.113" - wire $and$libresoc.v:51253$3305_Y - attribute \src "libresoc.v:51260.19-51260.103" - wire $and$libresoc.v:51260$3312_Y - attribute \src "libresoc.v:51262.19-51262.102" - wire $and$libresoc.v:51262$3314_Y - attribute \src "libresoc.v:51267.18-51267.101" - wire $and$libresoc.v:51267$3319_Y - attribute \src "libresoc.v:51269.18-51269.111" - wire $and$libresoc.v:51269$3321_Y - attribute \src "libresoc.v:51274.18-51274.101" - wire $and$libresoc.v:51274$3326_Y - attribute \src "libresoc.v:51276.18-51276.111" - wire $and$libresoc.v:51276$3328_Y - attribute \src "libresoc.v:51282.18-51282.101" - wire $and$libresoc.v:51282$3334_Y - attribute \src "libresoc.v:51284.18-51284.111" - wire $and$libresoc.v:51284$3336_Y - attribute \src "libresoc.v:51288.17-51288.99" - wire $and$libresoc.v:51288$3340_Y - attribute \src "libresoc.v:51290.18-51290.101" - wire $and$libresoc.v:51290$3342_Y - attribute \src "libresoc.v:51292.18-51292.111" - wire $and$libresoc.v:51292$3344_Y - attribute \src "libresoc.v:51297.18-51297.101" - wire $and$libresoc.v:51297$3349_Y - attribute \src "libresoc.v:51300.18-51300.111" - wire $and$libresoc.v:51300$3352_Y - attribute \src "libresoc.v:51305.18-51305.101" - wire $and$libresoc.v:51305$3357_Y - attribute \src "libresoc.v:51307.18-51307.111" - wire $and$libresoc.v:51307$3359_Y - attribute \src "libresoc.v:51249.18-51249.103" - wire $eq$libresoc.v:51249$3301_Y - attribute \src "libresoc.v:51254.19-51254.104" - wire $eq$libresoc.v:51254$3306_Y - attribute \src "libresoc.v:51255.19-51255.104" - wire $eq$libresoc.v:51255$3307_Y - attribute \src "libresoc.v:51256.19-51256.104" - wire $eq$libresoc.v:51256$3308_Y - attribute \src "libresoc.v:51258.19-51258.104" - wire $eq$libresoc.v:51258$3310_Y - attribute \src "libresoc.v:51259.18-51259.103" - wire $eq$libresoc.v:51259$3311_Y - attribute \src "libresoc.v:51263.18-51263.103" - wire $eq$libresoc.v:51263$3315_Y - attribute \src "libresoc.v:51264.18-51264.103" - wire $eq$libresoc.v:51264$3316_Y - attribute \src "libresoc.v:51270.18-51270.103" - wire $eq$libresoc.v:51270$3322_Y - attribute \src "libresoc.v:51271.18-51271.103" - wire $eq$libresoc.v:51271$3323_Y - attribute \src "libresoc.v:51272.18-51272.103" - wire $eq$libresoc.v:51272$3324_Y - attribute \src "libresoc.v:51278.18-51278.103" - wire $eq$libresoc.v:51278$3330_Y - attribute \src "libresoc.v:51279.18-51279.103" - wire $eq$libresoc.v:51279$3331_Y - attribute \src "libresoc.v:51280.18-51280.103" - wire $eq$libresoc.v:51280$3332_Y - attribute \src "libresoc.v:51285.18-51285.103" - wire $eq$libresoc.v:51285$3337_Y - attribute \src "libresoc.v:51286.18-51286.103" - wire $eq$libresoc.v:51286$3338_Y - attribute \src "libresoc.v:51287.18-51287.103" - wire $eq$libresoc.v:51287$3339_Y - attribute \src "libresoc.v:51293.18-51293.103" - wire $eq$libresoc.v:51293$3345_Y - attribute \src "libresoc.v:51294.18-51294.103" - wire $eq$libresoc.v:51294$3346_Y - attribute \src "libresoc.v:51295.18-51295.103" - wire $eq$libresoc.v:51295$3347_Y - attribute \src "libresoc.v:51301.18-51301.103" - wire $eq$libresoc.v:51301$3353_Y - attribute \src "libresoc.v:51302.18-51302.103" - wire $eq$libresoc.v:51302$3354_Y - attribute \src "libresoc.v:51303.18-51303.103" - wire $eq$libresoc.v:51303$3355_Y - attribute \src "libresoc.v:51308.18-51308.103" - wire $eq$libresoc.v:51308$3360_Y - attribute \src "libresoc.v:51309.18-51309.103" - wire $eq$libresoc.v:51309$3361_Y - attribute \src "libresoc.v:51250.19-51250.99" - wire $not$libresoc.v:51250$3302_Y - attribute \src "libresoc.v:51252.19-51252.105" - wire $not$libresoc.v:51252$3304_Y - attribute \src "libresoc.v:51261.19-51261.95" - wire $not$libresoc.v:51261$3313_Y - attribute \src "libresoc.v:51265.18-51265.98" - wire $not$libresoc.v:51265$3317_Y - attribute \src "libresoc.v:51268.18-51268.104" - wire $not$libresoc.v:51268$3320_Y - attribute \src "libresoc.v:51273.18-51273.98" - wire $not$libresoc.v:51273$3325_Y - attribute \src "libresoc.v:51275.18-51275.104" - wire $not$libresoc.v:51275$3327_Y - attribute \src "libresoc.v:51277.17-51277.97" - wire $not$libresoc.v:51277$3329_Y - attribute \src "libresoc.v:51281.18-51281.98" - wire $not$libresoc.v:51281$3333_Y - attribute \src "libresoc.v:51283.18-51283.104" - wire $not$libresoc.v:51283$3335_Y - attribute \src "libresoc.v:51289.18-51289.98" - wire $not$libresoc.v:51289$3341_Y - attribute \src "libresoc.v:51291.18-51291.104" - wire $not$libresoc.v:51291$3343_Y - attribute \src "libresoc.v:51296.18-51296.98" - wire $not$libresoc.v:51296$3348_Y - attribute \src "libresoc.v:51298.18-51298.104" - wire $not$libresoc.v:51298$3350_Y - attribute \src "libresoc.v:51299.17-51299.103" - wire $not$libresoc.v:51299$3351_Y - attribute \src "libresoc.v:51304.18-51304.98" - wire $not$libresoc.v:51304$3356_Y - attribute \src "libresoc.v:51306.18-51306.104" - wire $not$libresoc.v:51306$3358_Y - attribute \src "libresoc.v:51266.17-51266.126" - wire width 64 $pos$libresoc.v:51266$3318_Y + attribute \src "libresoc.v:51926.3-51959.6" + wire $2\do_dmi_log_rd$next[0:0]$3454 + attribute \src "libresoc.v:51896.3-51925.6" + wire $2\do_icreset$next[0:0]$3447 + attribute \src "libresoc.v:51866.3-51895.6" + wire $2\do_reset$next[0:0]$3440 + attribute \src "libresoc.v:51836.3-51865.6" + wire $2\do_step$next[0:0]$3433 + attribute \src "libresoc.v:51705.3-51732.6" + wire width 7 $2\gspr_index$next[6:0]$3412 + attribute \src "libresoc.v:51733.3-51766.6" + wire width 32 $2\log_dmi_addr$next[31:0]$3418 + attribute \src "libresoc.v:51661.3-51704.6" + wire $2\stopping$next[0:0]$3403 + attribute \src "libresoc.v:51611.3-51660.6" + wire $2\terminated$next[0:0]$3393 + attribute \src "libresoc.v:51926.3-51959.6" + wire $3\do_dmi_log_rd$next[0:0]$3455 + attribute \src "libresoc.v:51896.3-51925.6" + wire $3\do_icreset$next[0:0]$3448 + attribute \src "libresoc.v:51866.3-51895.6" + wire $3\do_reset$next[0:0]$3441 + attribute \src "libresoc.v:51836.3-51865.6" + wire $3\do_step$next[0:0]$3434 + attribute \src "libresoc.v:51705.3-51732.6" + wire width 7 $3\gspr_index$next[6:0]$3413 + attribute \src "libresoc.v:51733.3-51766.6" + wire width 32 $3\log_dmi_addr$next[31:0]$3419 + attribute \src "libresoc.v:51661.3-51704.6" + wire $3\stopping$next[0:0]$3404 + attribute \src "libresoc.v:51611.3-51660.6" + wire $3\terminated$next[0:0]$3394 + attribute \src "libresoc.v:51926.3-51959.6" + wire $4\do_dmi_log_rd$next[0:0]$3456 + attribute \src "libresoc.v:51896.3-51925.6" + wire $4\do_icreset$next[0:0]$3449 + attribute \src "libresoc.v:51866.3-51895.6" + wire $4\do_reset$next[0:0]$3442 + attribute \src "libresoc.v:51836.3-51865.6" + wire $4\do_step$next[0:0]$3435 + attribute \src "libresoc.v:51705.3-51732.6" + wire width 7 $4\gspr_index$next[6:0]$3414 + attribute \src "libresoc.v:51733.3-51766.6" + wire width 32 $4\log_dmi_addr$next[31:0]$3420 + attribute \src "libresoc.v:51661.3-51704.6" + wire $4\stopping$next[0:0]$3405 + attribute \src "libresoc.v:51611.3-51660.6" + wire $4\terminated$next[0:0]$3395 + attribute \src "libresoc.v:51896.3-51925.6" + wire $5\do_icreset$next[0:0]$3450 + attribute \src "libresoc.v:51866.3-51895.6" + wire $5\do_reset$next[0:0]$3443 + attribute \src "libresoc.v:51836.3-51865.6" + wire $5\do_step$next[0:0]$3436 + attribute \src "libresoc.v:51661.3-51704.6" + wire $5\stopping$next[0:0]$3406 + attribute \src "libresoc.v:51611.3-51660.6" + wire $5\terminated$next[0:0]$3396 + attribute \src "libresoc.v:51661.3-51704.6" + wire $6\stopping$next[0:0]$3407 + attribute \src "libresoc.v:51611.3-51660.6" + wire $6\terminated$next[0:0]$3397 + attribute \src "libresoc.v:51661.3-51704.6" + wire $7\stopping$next[0:0]$3408 + attribute \src "libresoc.v:51611.3-51660.6" + wire $7\terminated$next[0:0]$3398 + attribute \src "libresoc.v:51611.3-51660.6" + wire $8\terminated$next[0:0]$3399 + attribute \src "libresoc.v:51499.19-51499.110" + wire width 3 $add$libresoc.v:51499$3321_Y + attribute \src "libresoc.v:51490.17-51490.109" + wire $and$libresoc.v:51490$3312_Y + attribute \src "libresoc.v:51493.19-51493.103" + wire $and$libresoc.v:51493$3315_Y + attribute \src "libresoc.v:51495.19-51495.113" + wire $and$libresoc.v:51495$3317_Y + attribute \src "libresoc.v:51502.19-51502.103" + wire $and$libresoc.v:51502$3324_Y + attribute \src "libresoc.v:51504.19-51504.102" + wire $and$libresoc.v:51504$3326_Y + attribute \src "libresoc.v:51509.18-51509.101" + wire $and$libresoc.v:51509$3331_Y + attribute \src "libresoc.v:51511.18-51511.111" + wire $and$libresoc.v:51511$3333_Y + attribute \src "libresoc.v:51516.18-51516.101" + wire $and$libresoc.v:51516$3338_Y + attribute \src "libresoc.v:51518.18-51518.111" + wire $and$libresoc.v:51518$3340_Y + attribute \src "libresoc.v:51524.18-51524.101" + wire $and$libresoc.v:51524$3346_Y + attribute \src "libresoc.v:51526.18-51526.111" + wire $and$libresoc.v:51526$3348_Y + attribute \src "libresoc.v:51530.17-51530.99" + wire $and$libresoc.v:51530$3352_Y + attribute \src "libresoc.v:51532.18-51532.101" + wire $and$libresoc.v:51532$3354_Y + attribute \src "libresoc.v:51534.18-51534.111" + wire $and$libresoc.v:51534$3356_Y + attribute \src "libresoc.v:51539.18-51539.101" + wire $and$libresoc.v:51539$3361_Y + attribute \src "libresoc.v:51542.18-51542.111" + wire $and$libresoc.v:51542$3364_Y + attribute \src "libresoc.v:51547.18-51547.101" + wire $and$libresoc.v:51547$3369_Y + attribute \src "libresoc.v:51549.18-51549.111" + wire $and$libresoc.v:51549$3371_Y + attribute \src "libresoc.v:51491.18-51491.103" + wire $eq$libresoc.v:51491$3313_Y + attribute \src "libresoc.v:51496.19-51496.104" + wire $eq$libresoc.v:51496$3318_Y + attribute \src "libresoc.v:51497.19-51497.104" + wire $eq$libresoc.v:51497$3319_Y + attribute \src "libresoc.v:51498.19-51498.104" + wire $eq$libresoc.v:51498$3320_Y + attribute \src "libresoc.v:51500.19-51500.104" + wire $eq$libresoc.v:51500$3322_Y + attribute \src "libresoc.v:51501.18-51501.103" + wire $eq$libresoc.v:51501$3323_Y + attribute \src "libresoc.v:51505.18-51505.103" + wire $eq$libresoc.v:51505$3327_Y + attribute \src "libresoc.v:51506.18-51506.103" + wire $eq$libresoc.v:51506$3328_Y + attribute \src "libresoc.v:51512.18-51512.103" + wire $eq$libresoc.v:51512$3334_Y + attribute \src "libresoc.v:51513.18-51513.103" + wire $eq$libresoc.v:51513$3335_Y + attribute \src "libresoc.v:51514.18-51514.103" + wire $eq$libresoc.v:51514$3336_Y + attribute \src "libresoc.v:51520.18-51520.103" + wire $eq$libresoc.v:51520$3342_Y + attribute \src "libresoc.v:51521.18-51521.103" + wire $eq$libresoc.v:51521$3343_Y + attribute \src "libresoc.v:51522.18-51522.103" + wire $eq$libresoc.v:51522$3344_Y + attribute \src "libresoc.v:51527.18-51527.103" + wire $eq$libresoc.v:51527$3349_Y + attribute \src "libresoc.v:51528.18-51528.103" + wire $eq$libresoc.v:51528$3350_Y + attribute \src "libresoc.v:51529.18-51529.103" + wire $eq$libresoc.v:51529$3351_Y + attribute \src "libresoc.v:51535.18-51535.103" + wire $eq$libresoc.v:51535$3357_Y + attribute \src "libresoc.v:51536.18-51536.103" + wire $eq$libresoc.v:51536$3358_Y + attribute \src "libresoc.v:51537.18-51537.103" + wire $eq$libresoc.v:51537$3359_Y + attribute \src "libresoc.v:51543.18-51543.103" + wire $eq$libresoc.v:51543$3365_Y + attribute \src "libresoc.v:51544.18-51544.103" + wire $eq$libresoc.v:51544$3366_Y + attribute \src "libresoc.v:51545.18-51545.103" + wire $eq$libresoc.v:51545$3367_Y + attribute \src "libresoc.v:51550.18-51550.103" + wire $eq$libresoc.v:51550$3372_Y + attribute \src "libresoc.v:51551.18-51551.103" + wire $eq$libresoc.v:51551$3373_Y + attribute \src "libresoc.v:51492.19-51492.99" + wire $not$libresoc.v:51492$3314_Y + attribute \src "libresoc.v:51494.19-51494.105" + wire $not$libresoc.v:51494$3316_Y + attribute \src "libresoc.v:51503.19-51503.95" + wire $not$libresoc.v:51503$3325_Y + attribute \src "libresoc.v:51507.18-51507.98" + wire $not$libresoc.v:51507$3329_Y + attribute \src "libresoc.v:51510.18-51510.104" + wire $not$libresoc.v:51510$3332_Y + attribute \src "libresoc.v:51515.18-51515.98" + wire $not$libresoc.v:51515$3337_Y + attribute \src "libresoc.v:51517.18-51517.104" + wire $not$libresoc.v:51517$3339_Y + attribute \src "libresoc.v:51519.17-51519.97" + wire $not$libresoc.v:51519$3341_Y + attribute \src "libresoc.v:51523.18-51523.98" + wire $not$libresoc.v:51523$3345_Y + attribute \src "libresoc.v:51525.18-51525.104" + wire $not$libresoc.v:51525$3347_Y + attribute \src "libresoc.v:51531.18-51531.98" + wire $not$libresoc.v:51531$3353_Y + attribute \src "libresoc.v:51533.18-51533.104" + wire $not$libresoc.v:51533$3355_Y + attribute \src "libresoc.v:51538.18-51538.98" + wire $not$libresoc.v:51538$3360_Y + attribute \src "libresoc.v:51540.18-51540.104" + wire $not$libresoc.v:51540$3362_Y + attribute \src "libresoc.v:51541.17-51541.103" + wire $not$libresoc.v:51541$3363_Y + attribute \src "libresoc.v:51546.18-51546.98" + wire $not$libresoc.v:51546$3368_Y + attribute \src "libresoc.v:51548.18-51548.104" + wire $not$libresoc.v:51548$3370_Y + attribute \src "libresoc.v:51508.17-51508.126" + wire width 64 $pos$libresoc.v:51508$3330_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" @@ -90692,11 +91186,11 @@ module \dbg wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 24 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 input 11 \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 10 \core_dbg_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" wire output 8 \core_rst_o @@ -90770,7 +91264,7 @@ module \dbg wire width 7 \gspr_index$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" wire \icache_rst_o - attribute \src "libresoc.v:51014.7-51014.15" + attribute \src "libresoc.v:51256.7-51256.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" wire width 32 \log_dmi_addr @@ -90780,7 +91274,7 @@ module \dbg wire width 64 \log_dmi_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119" wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134" wire width 64 \stat_reg @@ -90797,7 +91291,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" wire \terminated_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $add $add$libresoc.v:51257$3309 + cell $add $add$libresoc.v:51499$3321 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -90805,10 +91299,10 @@ module \dbg parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 - connect \Y $add$libresoc.v:51257$3309_Y + connect \Y $add$libresoc.v:51499$3321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:51248$3300 + cell $and $and$libresoc.v:51490$3312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90816,10 +91310,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$7 - connect \Y $and$libresoc.v:51248$3300_Y + connect \Y $and$libresoc.v:51490$3312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:51251$3303 + cell $and $and$libresoc.v:51493$3315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90827,10 +91321,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$101 - connect \Y $and$libresoc.v:51251$3303_Y + connect \Y $and$libresoc.v:51493$3315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:51253$3305 + cell $and $and$libresoc.v:51495$3317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90838,10 +91332,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$105 - connect \Y $and$libresoc.v:51253$3305_Y + connect \Y $and$libresoc.v:51495$3317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $and $and$libresoc.v:51260$3312 + cell $and $and$libresoc.v:51502$3324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90849,10 +91343,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$118 - connect \Y $and$libresoc.v:51260$3312_Y + connect \Y $and$libresoc.v:51502$3324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $and $and$libresoc.v:51262$3314 + cell $and $and$libresoc.v:51504$3326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90860,10 +91354,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \stopping connect \B \$122 - connect \Y $and$libresoc.v:51262$3314_Y + connect \Y $and$libresoc.v:51504$3326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:51267$3319 + cell $and $and$libresoc.v:51509$3331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90871,10 +91365,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$17 - connect \Y $and$libresoc.v:51267$3319_Y + connect \Y $and$libresoc.v:51509$3331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:51269$3321 + cell $and $and$libresoc.v:51511$3333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90882,10 +91376,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$21 - connect \Y $and$libresoc.v:51269$3321_Y + connect \Y $and$libresoc.v:51511$3333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:51274$3326 + cell $and $and$libresoc.v:51516$3338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90893,10 +91387,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$31 - connect \Y $and$libresoc.v:51274$3326_Y + connect \Y $and$libresoc.v:51516$3338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:51276$3328 + cell $and $and$libresoc.v:51518$3340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90904,10 +91398,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$35 - connect \Y $and$libresoc.v:51276$3328_Y + connect \Y $and$libresoc.v:51518$3340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:51282$3334 + cell $and $and$libresoc.v:51524$3346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90915,10 +91409,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$45 - connect \Y $and$libresoc.v:51282$3334_Y + connect \Y $and$libresoc.v:51524$3346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:51284$3336 + cell $and $and$libresoc.v:51526$3348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90926,10 +91420,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$49 - connect \Y $and$libresoc.v:51284$3336_Y + connect \Y $and$libresoc.v:51526$3348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:51288$3340 + cell $and $and$libresoc.v:51530$3352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90937,10 +91431,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$3 - connect \Y $and$libresoc.v:51288$3340_Y + connect \Y $and$libresoc.v:51530$3352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:51290$3342 + cell $and $and$libresoc.v:51532$3354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90948,10 +91442,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$59 - connect \Y $and$libresoc.v:51290$3342_Y + connect \Y $and$libresoc.v:51532$3354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:51292$3344 + cell $and $and$libresoc.v:51534$3356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90959,10 +91453,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$63 - connect \Y $and$libresoc.v:51292$3344_Y + connect \Y $and$libresoc.v:51534$3356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:51297$3349 + cell $and $and$libresoc.v:51539$3361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90970,10 +91464,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$73 - connect \Y $and$libresoc.v:51297$3349_Y + connect \Y $and$libresoc.v:51539$3361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:51300$3352 + cell $and $and$libresoc.v:51542$3364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90981,10 +91475,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$77 - connect \Y $and$libresoc.v:51300$3352_Y + connect \Y $and$libresoc.v:51542$3364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:51305$3357 + cell $and $and$libresoc.v:51547$3369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90992,10 +91486,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$87 - connect \Y $and$libresoc.v:51305$3357_Y + connect \Y $and$libresoc.v:51547$3369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:51307$3359 + cell $and $and$libresoc.v:51549$3371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -91003,10 +91497,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$91 - connect \Y $and$libresoc.v:51307$3359_Y + connect \Y $and$libresoc.v:51549$3371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:51249$3301 + cell $eq $eq$libresoc.v:51491$3313 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91014,10 +91508,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51249$3301_Y + connect \Y $eq$libresoc.v:51491$3313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:51254$3306 + cell $eq $eq$libresoc.v:51496$3318 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91025,10 +91519,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51254$3306_Y + connect \Y $eq$libresoc.v:51496$3318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:51255$3307 + cell $eq $eq$libresoc.v:51497$3319 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91036,10 +91530,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51255$3307_Y + connect \Y $eq$libresoc.v:51497$3319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:51256$3308 + cell $eq $eq$libresoc.v:51498$3320 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91047,10 +91541,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51256$3308_Y + connect \Y $eq$libresoc.v:51498$3320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $eq $eq$libresoc.v:51258$3310 + cell $eq $eq$libresoc.v:51500$3322 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91058,10 +91552,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 - connect \Y $eq$libresoc.v:51258$3310_Y + connect \Y $eq$libresoc.v:51500$3322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:51259$3311 + cell $eq $eq$libresoc.v:51501$3323 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91069,10 +91563,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51259$3311_Y + connect \Y $eq$libresoc.v:51501$3323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:51263$3315 + cell $eq $eq$libresoc.v:51505$3327 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91080,10 +91574,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51263$3315_Y + connect \Y $eq$libresoc.v:51505$3327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:51264$3316 + cell $eq $eq$libresoc.v:51506$3328 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91091,10 +91585,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51264$3316_Y + connect \Y $eq$libresoc.v:51506$3328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:51270$3322 + cell $eq $eq$libresoc.v:51512$3334 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91102,10 +91596,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51270$3322_Y + connect \Y $eq$libresoc.v:51512$3334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:51271$3323 + cell $eq $eq$libresoc.v:51513$3335 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91113,10 +91607,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51271$3323_Y + connect \Y $eq$libresoc.v:51513$3335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:51272$3324 + cell $eq $eq$libresoc.v:51514$3336 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91124,10 +91618,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51272$3324_Y + connect \Y $eq$libresoc.v:51514$3336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:51278$3330 + cell $eq $eq$libresoc.v:51520$3342 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91135,10 +91629,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51278$3330_Y + connect \Y $eq$libresoc.v:51520$3342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:51279$3331 + cell $eq $eq$libresoc.v:51521$3343 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91146,10 +91640,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51279$3331_Y + connect \Y $eq$libresoc.v:51521$3343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:51280$3332 + cell $eq $eq$libresoc.v:51522$3344 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91157,10 +91651,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51280$3332_Y + connect \Y $eq$libresoc.v:51522$3344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:51285$3337 + cell $eq $eq$libresoc.v:51527$3349 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91168,10 +91662,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51285$3337_Y + connect \Y $eq$libresoc.v:51527$3349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:51286$3338 + cell $eq $eq$libresoc.v:51528$3350 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91179,10 +91673,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51286$3338_Y + connect \Y $eq$libresoc.v:51528$3350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:51287$3339 + cell $eq $eq$libresoc.v:51529$3351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91190,10 +91684,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51287$3339_Y + connect \Y $eq$libresoc.v:51529$3351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:51293$3345 + cell $eq $eq$libresoc.v:51535$3357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91201,10 +91695,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51293$3345_Y + connect \Y $eq$libresoc.v:51535$3357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:51294$3346 + cell $eq $eq$libresoc.v:51536$3358 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91212,10 +91706,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51294$3346_Y + connect \Y $eq$libresoc.v:51536$3358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:51295$3347 + cell $eq $eq$libresoc.v:51537$3359 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91223,10 +91717,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51295$3347_Y + connect \Y $eq$libresoc.v:51537$3359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:51301$3353 + cell $eq $eq$libresoc.v:51543$3365 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91234,10 +91728,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51301$3353_Y + connect \Y $eq$libresoc.v:51543$3365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:51302$3354 + cell $eq $eq$libresoc.v:51544$3366 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91245,10 +91739,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51302$3354_Y + connect \Y $eq$libresoc.v:51544$3366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - cell $eq $eq$libresoc.v:51303$3355 + cell $eq $eq$libresoc.v:51545$3367 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91256,10 +91750,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51303$3355_Y + connect \Y $eq$libresoc.v:51545$3367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - cell $eq $eq$libresoc.v:51308$3360 + cell $eq $eq$libresoc.v:51550$3372 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91267,10 +91761,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51308$3360_Y + connect \Y $eq$libresoc.v:51550$3372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - cell $eq $eq$libresoc.v:51309$3361 + cell $eq $eq$libresoc.v:51551$3373 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91278,332 +91772,332 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51309$3361_Y + connect \Y $eq$libresoc.v:51551$3373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:51250$3302 + cell $not $not$libresoc.v:51492$3314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51250$3302_Y + connect \Y $not$libresoc.v:51492$3314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:51252$3304 + cell $not $not$libresoc.v:51494$3316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51252$3304_Y + connect \Y $not$libresoc.v:51494$3316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $not $not$libresoc.v:51261$3313 + cell $not $not$libresoc.v:51503$3325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step - connect \Y $not$libresoc.v:51261$3313_Y + connect \Y $not$libresoc.v:51503$3325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:51265$3317 + cell $not $not$libresoc.v:51507$3329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51265$3317_Y + connect \Y $not$libresoc.v:51507$3329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:51268$3320 + cell $not $not$libresoc.v:51510$3332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51268$3320_Y + connect \Y $not$libresoc.v:51510$3332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:51273$3325 + cell $not $not$libresoc.v:51515$3337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51273$3325_Y + connect \Y $not$libresoc.v:51515$3337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:51275$3327 + cell $not $not$libresoc.v:51517$3339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51275$3327_Y + connect \Y $not$libresoc.v:51517$3339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:51277$3329 + cell $not $not$libresoc.v:51519$3341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51277$3329_Y + connect \Y $not$libresoc.v:51519$3341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:51281$3333 + cell $not $not$libresoc.v:51523$3345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51281$3333_Y + connect \Y $not$libresoc.v:51523$3345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:51283$3335 + cell $not $not$libresoc.v:51525$3347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51283$3335_Y + connect \Y $not$libresoc.v:51525$3347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:51289$3341 + cell $not $not$libresoc.v:51531$3353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51289$3341_Y + connect \Y $not$libresoc.v:51531$3353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:51291$3343 + cell $not $not$libresoc.v:51533$3355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51291$3343_Y + connect \Y $not$libresoc.v:51533$3355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:51296$3348 + cell $not $not$libresoc.v:51538$3360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51296$3348_Y + connect \Y $not$libresoc.v:51538$3360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:51298$3350 + cell $not $not$libresoc.v:51540$3362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51298$3350_Y + connect \Y $not$libresoc.v:51540$3362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:51299$3351 + cell $not $not$libresoc.v:51541$3363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51299$3351_Y + connect \Y $not$libresoc.v:51541$3363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $not $not$libresoc.v:51304$3356 + cell $not $not$libresoc.v:51546$3368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51304$3356_Y + connect \Y $not$libresoc.v:51546$3368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $not $not$libresoc.v:51306$3358 + cell $not $not$libresoc.v:51548$3370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51306$3358_Y + connect \Y $not$libresoc.v:51548$3370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" - cell $pos $pos$libresoc.v:51266$3318 + cell $pos $pos$libresoc.v:51508$3330 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:51266$3318_Y + connect \Y $pos$libresoc.v:51508$3330_Y end - attribute \src "libresoc.v:51014.7-51014.20" - process $proc$libresoc.v:51014$3445 + attribute \src "libresoc.v:51256.7-51256.20" + process $proc$libresoc.v:51256$3457 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:51187.7-51187.31" - process $proc$libresoc.v:51187$3446 + attribute \src "libresoc.v:51429.7-51429.31" + process $proc$libresoc.v:51429$3458 assign { } { } assign $1\dmi_read_log_data[0:0] 1'0 sync always sync init update \dmi_read_log_data $1\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51191.7-51191.33" - process $proc$libresoc.v:51191$3447 + attribute \src "libresoc.v:51433.7-51433.33" + process $proc$libresoc.v:51433$3459 assign { } { } assign $1\dmi_read_log_data_1[0:0] 1'0 sync always sync init update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51197.7-51197.25" - process $proc$libresoc.v:51197$3448 + attribute \src "libresoc.v:51439.7-51439.25" + process $proc$libresoc.v:51439$3460 assign { } { } assign $1\dmi_req_i_1[0:0] 1'0 sync always sync init update \dmi_req_i_1 $1\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51203.7-51203.27" - process $proc$libresoc.v:51203$3449 + attribute \src "libresoc.v:51445.7-51445.27" + process $proc$libresoc.v:51445$3461 assign { } { } assign $1\do_dmi_log_rd[0:0] 1'0 sync always sync init update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51207.7-51207.24" - process $proc$libresoc.v:51207$3450 + attribute \src "libresoc.v:51449.7-51449.24" + process $proc$libresoc.v:51449$3462 assign { } { } assign $1\do_icreset[0:0] 1'0 sync always sync init update \do_icreset $1\do_icreset[0:0] end - attribute \src "libresoc.v:51211.7-51211.22" - process $proc$libresoc.v:51211$3451 + attribute \src "libresoc.v:51453.7-51453.22" + process $proc$libresoc.v:51453$3463 assign { } { } assign $1\do_reset[0:0] 1'0 sync always sync init update \do_reset $1\do_reset[0:0] end - attribute \src "libresoc.v:51215.7-51215.21" - process $proc$libresoc.v:51215$3452 + attribute \src "libresoc.v:51457.7-51457.21" + process $proc$libresoc.v:51457$3464 assign { } { } assign $1\do_step[0:0] 1'0 sync always sync init update \do_step $1\do_step[0:0] end - attribute \src "libresoc.v:51219.13-51219.31" - process $proc$libresoc.v:51219$3453 + attribute \src "libresoc.v:51461.13-51461.31" + process $proc$libresoc.v:51461$3465 assign { } { } assign $1\gspr_index[6:0] 7'0000000 sync always sync init update \gspr_index $1\gspr_index[6:0] end - attribute \src "libresoc.v:51225.14-51225.34" - process $proc$libresoc.v:51225$3454 + attribute \src "libresoc.v:51467.14-51467.34" + process $proc$libresoc.v:51467$3466 assign { } { } assign $1\log_dmi_addr[31:0] 0 sync always sync init update \log_dmi_addr $1\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51237.7-51237.22" - process $proc$libresoc.v:51237$3455 + attribute \src "libresoc.v:51479.7-51479.22" + process $proc$libresoc.v:51479$3467 assign { } { } assign $1\stopping[0:0] 1'0 sync always sync init update \stopping $1\stopping[0:0] end - attribute \src "libresoc.v:51243.7-51243.24" - process $proc$libresoc.v:51243$3456 + attribute \src "libresoc.v:51485.7-51485.24" + process $proc$libresoc.v:51485$3468 assign { } { } assign $1\terminated[0:0] 1'0 sync always sync init update \terminated $1\terminated[0:0] end - attribute \src "libresoc.v:51310.3-51311.51" - process $proc$libresoc.v:51310$3362 + attribute \src "libresoc.v:51552.3-51553.51" + process $proc$libresoc.v:51552$3374 assign { } { } assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next sync posedge \clk update \dmi_read_log_data $0\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51312.3-51313.55" - process $proc$libresoc.v:51312$3363 + attribute \src "libresoc.v:51554.3-51555.55" + process $proc$libresoc.v:51554$3375 assign { } { } assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next sync posedge \clk update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51314.3-51315.41" - process $proc$libresoc.v:51314$3364 + attribute \src "libresoc.v:51556.3-51557.41" + process $proc$libresoc.v:51556$3376 assign { } { } assign $0\log_dmi_addr[31:0] \log_dmi_addr$next sync posedge \clk update \log_dmi_addr $0\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51316.3-51317.37" - process $proc$libresoc.v:51316$3365 + attribute \src "libresoc.v:51558.3-51559.37" + process $proc$libresoc.v:51558$3377 assign { } { } assign $0\gspr_index[6:0] \gspr_index$next sync posedge \clk update \gspr_index $0\gspr_index[6:0] end - attribute \src "libresoc.v:51318.3-51319.33" - process $proc$libresoc.v:51318$3366 + attribute \src "libresoc.v:51560.3-51561.33" + process $proc$libresoc.v:51560$3378 assign { } { } assign $0\stopping[0:0] \stopping$next sync posedge \clk update \stopping $0\stopping[0:0] end - attribute \src "libresoc.v:51320.3-51321.37" - process $proc$libresoc.v:51320$3367 + attribute \src "libresoc.v:51562.3-51563.37" + process $proc$libresoc.v:51562$3379 assign { } { } assign $0\terminated[0:0] \terminated$next sync posedge \clk update \terminated $0\terminated[0:0] end - attribute \src "libresoc.v:51322.3-51323.39" - process $proc$libresoc.v:51322$3368 + attribute \src "libresoc.v:51564.3-51565.39" + process $proc$libresoc.v:51564$3380 assign { } { } assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next sync posedge \clk update \dmi_req_i_1 $0\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51324.3-51325.43" - process $proc$libresoc.v:51324$3369 + attribute \src "libresoc.v:51566.3-51567.43" + process $proc$libresoc.v:51566$3381 assign { } { } assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next sync posedge \clk update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51326.3-51327.37" - process $proc$libresoc.v:51326$3370 + attribute \src "libresoc.v:51568.3-51569.37" + process $proc$libresoc.v:51568$3382 assign { } { } assign $0\do_icreset[0:0] \do_icreset$next sync posedge \clk update \do_icreset $0\do_icreset[0:0] end - attribute \src "libresoc.v:51328.3-51329.33" - process $proc$libresoc.v:51328$3371 + attribute \src "libresoc.v:51570.3-51571.33" + process $proc$libresoc.v:51570$3383 assign { } { } assign $0\do_reset[0:0] \do_reset$next sync posedge \clk update \do_reset $0\do_reset[0:0] end - attribute \src "libresoc.v:51330.3-51331.31" - process $proc$libresoc.v:51330$3372 + attribute \src "libresoc.v:51572.3-51573.31" + process $proc$libresoc.v:51572$3384 assign { } { } assign $0\do_step[0:0] \do_step$next sync posedge \clk update \do_step $0\do_step[0:0] end - attribute \src "libresoc.v:51332.3-51349.6" - process $proc$libresoc.v:51332$3373 + attribute \src "libresoc.v:51574.3-51591.6" + process $proc$libresoc.v:51574$3385 assign { } { } assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51333.5-51333.29" + attribute \src "libresoc.v:51575.5-51575.29" switch \initial - attribute \src "libresoc.v:51333.9-51333.17" + attribute \src "libresoc.v:51575.9-51575.17" case 1'1 case end @@ -91629,14 +92123,14 @@ module \dbg sync always update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "libresoc.v:51350.3-51359.6" - process $proc$libresoc.v:51350$3374 + attribute \src "libresoc.v:51592.3-51601.6" + process $proc$libresoc.v:51592$3386 assign { } { } assign { } { } assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51351.5-51351.29" + attribute \src "libresoc.v:51593.5-51593.29" switch \initial - attribute \src "libresoc.v:51351.9-51351.17" + attribute \src "libresoc.v:51593.9-51593.17" case 1'1 case end @@ -91652,14 +92146,14 @@ module \dbg sync always update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "libresoc.v:51360.3-51368.6" - process $proc$libresoc.v:51360$3375 + attribute \src "libresoc.v:51602.3-51610.6" + process $proc$libresoc.v:51602$3387 assign { } { } assign { } { } - assign $0\dmi_req_i_1$next[0:0]$3376 $1\dmi_req_i_1$next[0:0]$3377 - attribute \src "libresoc.v:51361.5-51361.29" + assign $0\dmi_req_i_1$next[0:0]$3388 $1\dmi_req_i_1$next[0:0]$3389 + attribute \src "libresoc.v:51603.5-51603.29" switch \initial - attribute \src "libresoc.v:51361.9-51361.17" + attribute \src "libresoc.v:51603.9-51603.17" case 1'1 case end @@ -91668,23 +92162,23 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_req_i_1$next[0:0]$3377 1'0 + assign $1\dmi_req_i_1$next[0:0]$3389 1'0 case - assign $1\dmi_req_i_1$next[0:0]$3377 \dmi_req_i + assign $1\dmi_req_i_1$next[0:0]$3389 \dmi_req_i end sync always - update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3376 + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3388 end - attribute \src "libresoc.v:51369.3-51418.6" - process $proc$libresoc.v:51369$3378 + attribute \src "libresoc.v:51611.3-51660.6" + process $proc$libresoc.v:51611$3390 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\terminated$next[0:0]$3379 $8\terminated$next[0:0]$3387 - attribute \src "libresoc.v:51370.5-51370.29" + assign $0\terminated$next[0:0]$3391 $8\terminated$next[0:0]$3399 + attribute \src "libresoc.v:51612.5-51612.29" switch \initial - attribute \src "libresoc.v:51370.9-51370.17" + attribute \src "libresoc.v:51612.9-51612.17" case 1'1 case end @@ -91693,13 +92187,13 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\terminated$next[0:0]$3380 $2\terminated$next[0:0]$3381 + assign $1\terminated$next[0:0]$3392 $2\terminated$next[0:0]$3393 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\terminated$next[0:0]$3381 $3\terminated$next[0:0]$3382 + assign $2\terminated$next[0:0]$3393 $3\terminated$next[0:0]$3394 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$71 \$69 \$67 } attribute \src "libresoc.v:0.0-0.0" @@ -91707,74 +92201,74 @@ module \dbg assign { } { } assign { } { } assign { } { } - assign $3\terminated$next[0:0]$3382 $6\terminated$next[0:0]$3385 + assign $3\terminated$next[0:0]$3394 $6\terminated$next[0:0]$3397 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\terminated$next[0:0]$3383 1'0 + assign $4\terminated$next[0:0]$3395 1'0 case - assign $4\terminated$next[0:0]$3383 \terminated + assign $4\terminated$next[0:0]$3395 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\terminated$next[0:0]$3384 1'0 + assign $5\terminated$next[0:0]$3396 1'0 case - assign $5\terminated$next[0:0]$3384 $4\terminated$next[0:0]$3383 + assign $5\terminated$next[0:0]$3396 $4\terminated$next[0:0]$3395 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\terminated$next[0:0]$3385 1'0 + assign $6\terminated$next[0:0]$3397 1'0 case - assign $6\terminated$next[0:0]$3385 $5\terminated$next[0:0]$3384 + assign $6\terminated$next[0:0]$3397 $5\terminated$next[0:0]$3396 end case - assign $3\terminated$next[0:0]$3382 \terminated + assign $3\terminated$next[0:0]$3394 \terminated end case - assign $2\terminated$next[0:0]$3381 \terminated + assign $2\terminated$next[0:0]$3393 \terminated end case - assign $1\terminated$next[0:0]$3380 \terminated + assign $1\terminated$next[0:0]$3392 \terminated end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\terminated$next[0:0]$3386 1'1 + assign $7\terminated$next[0:0]$3398 1'1 case - assign $7\terminated$next[0:0]$3386 $1\terminated$next[0:0]$3380 + assign $7\terminated$next[0:0]$3398 $1\terminated$next[0:0]$3392 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\terminated$next[0:0]$3387 1'0 + assign $8\terminated$next[0:0]$3399 1'0 case - assign $8\terminated$next[0:0]$3387 $7\terminated$next[0:0]$3386 + assign $8\terminated$next[0:0]$3399 $7\terminated$next[0:0]$3398 end sync always - update \terminated$next $0\terminated$next[0:0]$3379 + update \terminated$next $0\terminated$next[0:0]$3391 end - attribute \src "libresoc.v:51419.3-51462.6" - process $proc$libresoc.v:51419$3388 + attribute \src "libresoc.v:51661.3-51704.6" + process $proc$libresoc.v:51661$3400 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\stopping$next[0:0]$3389 $7\stopping$next[0:0]$3396 - attribute \src "libresoc.v:51420.5-51420.29" + assign $0\stopping$next[0:0]$3401 $7\stopping$next[0:0]$3408 + attribute \src "libresoc.v:51662.5-51662.29" switch \initial - attribute \src "libresoc.v:51420.9-51420.17" + attribute \src "libresoc.v:51662.9-51662.17" case 1'1 case end @@ -91783,77 +92277,77 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\stopping$next[0:0]$3390 $2\stopping$next[0:0]$3391 + assign $1\stopping$next[0:0]$3402 $2\stopping$next[0:0]$3403 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\stopping$next[0:0]$3391 $3\stopping$next[0:0]$3392 + assign $2\stopping$next[0:0]$3403 $3\stopping$next[0:0]$3404 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$85 \$83 \$81 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } assign { } { } - assign $3\stopping$next[0:0]$3392 $5\stopping$next[0:0]$3394 + assign $3\stopping$next[0:0]$3404 $5\stopping$next[0:0]$3406 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" switch \dmi_din [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\stopping$next[0:0]$3393 1'1 + assign $4\stopping$next[0:0]$3405 1'1 case - assign $4\stopping$next[0:0]$3393 \stopping + assign $4\stopping$next[0:0]$3405 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" switch \dmi_din [4] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\stopping$next[0:0]$3394 1'0 + assign $5\stopping$next[0:0]$3406 1'0 case - assign $5\stopping$next[0:0]$3394 $4\stopping$next[0:0]$3393 + assign $5\stopping$next[0:0]$3406 $4\stopping$next[0:0]$3405 end case - assign $3\stopping$next[0:0]$3392 \stopping + assign $3\stopping$next[0:0]$3404 \stopping end case - assign $2\stopping$next[0:0]$3391 \stopping + assign $2\stopping$next[0:0]$3403 \stopping end case - assign $1\stopping$next[0:0]$3390 \stopping + assign $1\stopping$next[0:0]$3402 \stopping end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" switch \terminate_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\stopping$next[0:0]$3395 1'1 + assign $6\stopping$next[0:0]$3407 1'1 case - assign $6\stopping$next[0:0]$3395 $1\stopping$next[0:0]$3390 + assign $6\stopping$next[0:0]$3407 $1\stopping$next[0:0]$3402 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\stopping$next[0:0]$3396 1'0 + assign $7\stopping$next[0:0]$3408 1'0 case - assign $7\stopping$next[0:0]$3396 $6\stopping$next[0:0]$3395 + assign $7\stopping$next[0:0]$3408 $6\stopping$next[0:0]$3407 end sync always - update \stopping$next $0\stopping$next[0:0]$3389 + update \stopping$next $0\stopping$next[0:0]$3401 end - attribute \src "libresoc.v:51463.3-51490.6" - process $proc$libresoc.v:51463$3397 + attribute \src "libresoc.v:51705.3-51732.6" + process $proc$libresoc.v:51705$3409 assign { } { } assign { } { } assign { } { } - assign $0\gspr_index$next[6:0]$3398 $4\gspr_index$next[6:0]$3402 - attribute \src "libresoc.v:51464.5-51464.29" + assign $0\gspr_index$next[6:0]$3410 $4\gspr_index$next[6:0]$3414 + attribute \src "libresoc.v:51706.5-51706.29" switch \initial - attribute \src "libresoc.v:51464.9-51464.17" + attribute \src "libresoc.v:51706.9-51706.17" case 1'1 case end @@ -91862,52 +92356,52 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\gspr_index$next[6:0]$3399 $2\gspr_index$next[6:0]$3400 + assign $1\gspr_index$next[6:0]$3411 $2\gspr_index$next[6:0]$3412 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\gspr_index$next[6:0]$3400 $3\gspr_index$next[6:0]$3401 + assign $2\gspr_index$next[6:0]$3412 $3\gspr_index$next[6:0]$3413 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$99 \$97 \$95 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\gspr_index$next[6:0]$3401 \gspr_index + assign $3\gspr_index$next[6:0]$3413 \gspr_index attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $3\gspr_index$next[6:0]$3401 \dmi_din [6:0] + assign $3\gspr_index$next[6:0]$3413 \dmi_din [6:0] case - assign $3\gspr_index$next[6:0]$3401 \gspr_index + assign $3\gspr_index$next[6:0]$3413 \gspr_index end case - assign $2\gspr_index$next[6:0]$3400 \gspr_index + assign $2\gspr_index$next[6:0]$3412 \gspr_index end case - assign $1\gspr_index$next[6:0]$3399 \gspr_index + assign $1\gspr_index$next[6:0]$3411 \gspr_index end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\gspr_index$next[6:0]$3402 7'0000000 + assign $4\gspr_index$next[6:0]$3414 7'0000000 case - assign $4\gspr_index$next[6:0]$3402 $1\gspr_index$next[6:0]$3399 + assign $4\gspr_index$next[6:0]$3414 $1\gspr_index$next[6:0]$3411 end sync always - update \gspr_index$next $0\gspr_index$next[6:0]$3398 + update \gspr_index$next $0\gspr_index$next[6:0]$3410 end - attribute \src "libresoc.v:51491.3-51524.6" - process $proc$libresoc.v:51491$3403 + attribute \src "libresoc.v:51733.3-51766.6" + process $proc$libresoc.v:51733$3415 assign { } { } assign { } { } assign { } { } - assign $0\log_dmi_addr$next[31:0]$3404 $4\log_dmi_addr$next[31:0]$3408 - attribute \src "libresoc.v:51492.5-51492.29" + assign $0\log_dmi_addr$next[31:0]$3416 $4\log_dmi_addr$next[31:0]$3420 + attribute \src "libresoc.v:51734.5-51734.29" switch \initial - attribute \src "libresoc.v:51492.9-51492.17" + attribute \src "libresoc.v:51734.9-51734.17" case 1'1 case end @@ -91916,58 +92410,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\log_dmi_addr$next[31:0]$3405 $2\log_dmi_addr$next[31:0]$3406 + assign $1\log_dmi_addr$next[31:0]$3417 $2\log_dmi_addr$next[31:0]$3418 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\log_dmi_addr$next[31:0]$3406 $3\log_dmi_addr$next[31:0]$3407 + assign $2\log_dmi_addr$next[31:0]$3418 $3\log_dmi_addr$next[31:0]$3419 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$113 \$111 \$109 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\log_dmi_addr$next[31:0]$3407 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3419 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\log_dmi_addr$next[31:0]$3407 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3419 \log_dmi_addr attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\log_dmi_addr$next[31:0]$3407 \dmi_din [31:0] + assign $3\log_dmi_addr$next[31:0]$3419 \dmi_din [31:0] case - assign $3\log_dmi_addr$next[31:0]$3407 \log_dmi_addr + assign $3\log_dmi_addr$next[31:0]$3419 \log_dmi_addr end case - assign $2\log_dmi_addr$next[31:0]$3406 \log_dmi_addr + assign $2\log_dmi_addr$next[31:0]$3418 \log_dmi_addr end attribute \src "libresoc.v:0.0-0.0" case 2'1- - assign $1\log_dmi_addr$next[31:0]$3405 [31:2] \log_dmi_addr [31:2] - assign $1\log_dmi_addr$next[31:0]$3405 [1:0] \$115 [1:0] + assign $1\log_dmi_addr$next[31:0]$3417 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3417 [1:0] \$115 [1:0] case - assign $1\log_dmi_addr$next[31:0]$3405 \log_dmi_addr + assign $1\log_dmi_addr$next[31:0]$3417 \log_dmi_addr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\log_dmi_addr$next[31:0]$3408 0 + assign $4\log_dmi_addr$next[31:0]$3420 0 case - assign $4\log_dmi_addr$next[31:0]$3408 $1\log_dmi_addr$next[31:0]$3405 + assign $4\log_dmi_addr$next[31:0]$3420 $1\log_dmi_addr$next[31:0]$3417 end sync always - update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3404 + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3416 end - attribute \src "libresoc.v:51525.3-51533.6" - process $proc$libresoc.v:51525$3409 + attribute \src "libresoc.v:51767.3-51775.6" + process $proc$libresoc.v:51767$3421 assign { } { } assign { } { } - assign $0\dmi_read_log_data_1$next[0:0]$3410 $1\dmi_read_log_data_1$next[0:0]$3411 - attribute \src "libresoc.v:51526.5-51526.29" + assign $0\dmi_read_log_data_1$next[0:0]$3422 $1\dmi_read_log_data_1$next[0:0]$3423 + attribute \src "libresoc.v:51768.5-51768.29" switch \initial - attribute \src "libresoc.v:51526.9-51526.17" + attribute \src "libresoc.v:51768.9-51768.17" case 1'1 case end @@ -91976,21 +92470,21 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data_1$next[0:0]$3411 1'0 + assign $1\dmi_read_log_data_1$next[0:0]$3423 1'0 case - assign $1\dmi_read_log_data_1$next[0:0]$3411 \dmi_read_log_data + assign $1\dmi_read_log_data_1$next[0:0]$3423 \dmi_read_log_data end sync always - update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3410 + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3422 end - attribute \src "libresoc.v:51534.3-51542.6" - process $proc$libresoc.v:51534$3412 + attribute \src "libresoc.v:51776.3-51784.6" + process $proc$libresoc.v:51776$3424 assign { } { } assign { } { } - assign $0\dmi_read_log_data$next[0:0]$3413 $1\dmi_read_log_data$next[0:0]$3414 - attribute \src "libresoc.v:51535.5-51535.29" + assign $0\dmi_read_log_data$next[0:0]$3425 $1\dmi_read_log_data$next[0:0]$3426 + attribute \src "libresoc.v:51777.5-51777.29" switch \initial - attribute \src "libresoc.v:51535.9-51535.17" + attribute \src "libresoc.v:51777.9-51777.17" case 1'1 case end @@ -91999,21 +92493,21 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi_read_log_data$next[0:0]$3414 1'0 + assign $1\dmi_read_log_data$next[0:0]$3426 1'0 case - assign $1\dmi_read_log_data$next[0:0]$3414 \$120 + assign $1\dmi_read_log_data$next[0:0]$3426 \$120 end sync always - update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3413 + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3425 end - attribute \src "libresoc.v:51543.3-51552.6" - process $proc$libresoc.v:51543$3415 + attribute \src "libresoc.v:51785.3-51794.6" + process $proc$libresoc.v:51785$3427 assign { } { } assign { } { } assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:51544.5-51544.29" + attribute \src "libresoc.v:51786.5-51786.29" switch \initial - attribute \src "libresoc.v:51544.9-51544.17" + attribute \src "libresoc.v:51786.9-51786.17" case 1'1 case end @@ -92029,14 +92523,14 @@ module \dbg sync always update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "libresoc.v:51553.3-51562.6" - process $proc$libresoc.v:51553$3416 + attribute \src "libresoc.v:51795.3-51804.6" + process $proc$libresoc.v:51795$3428 assign { } { } assign { } { } assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:51554.5-51554.29" + attribute \src "libresoc.v:51796.5-51796.29" switch \initial - attribute \src "libresoc.v:51554.9-51554.17" + attribute \src "libresoc.v:51796.9-51796.17" case 1'1 case end @@ -92052,14 +92546,14 @@ module \dbg sync always update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "libresoc.v:51563.3-51593.6" - process $proc$libresoc.v:51563$3417 + attribute \src "libresoc.v:51805.3-51835.6" + process $proc$libresoc.v:51805$3429 assign { } { } assign { } { } assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:51564.5-51564.29" + attribute \src "libresoc.v:51806.5-51806.29" switch \initial - attribute \src "libresoc.v:51564.9-51564.17" + attribute \src "libresoc.v:51806.9-51806.17" case 1'1 case end @@ -92103,15 +92597,15 @@ module \dbg sync always update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "libresoc.v:51594.3-51623.6" - process $proc$libresoc.v:51594$3418 + attribute \src "libresoc.v:51836.3-51865.6" + process $proc$libresoc.v:51836$3430 assign { } { } assign { } { } assign { } { } - assign $0\do_step$next[0:0]$3419 $5\do_step$next[0:0]$3424 - attribute \src "libresoc.v:51595.5-51595.29" + assign $0\do_step$next[0:0]$3431 $5\do_step$next[0:0]$3436 + attribute \src "libresoc.v:51837.5-51837.29" switch \initial - attribute \src "libresoc.v:51595.9-51595.17" + attribute \src "libresoc.v:51837.9-51837.17" case 1'1 case end @@ -92120,58 +92614,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_step$next[0:0]$3420 $2\do_step$next[0:0]$3421 + assign $1\do_step$next[0:0]$3432 $2\do_step$next[0:0]$3433 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_step$next[0:0]$3421 $3\do_step$next[0:0]$3422 + assign $2\do_step$next[0:0]$3433 $3\do_step$next[0:0]$3434 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$15 \$13 \$11 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_step$next[0:0]$3422 $4\do_step$next[0:0]$3423 + assign $3\do_step$next[0:0]$3434 $4\do_step$next[0:0]$3435 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" switch \dmi_din [3] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_step$next[0:0]$3423 1'1 + assign $4\do_step$next[0:0]$3435 1'1 case - assign $4\do_step$next[0:0]$3423 1'0 + assign $4\do_step$next[0:0]$3435 1'0 end case - assign $3\do_step$next[0:0]$3422 1'0 + assign $3\do_step$next[0:0]$3434 1'0 end case - assign $2\do_step$next[0:0]$3421 1'0 + assign $2\do_step$next[0:0]$3433 1'0 end case - assign $1\do_step$next[0:0]$3420 1'0 + assign $1\do_step$next[0:0]$3432 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_step$next[0:0]$3424 1'0 + assign $5\do_step$next[0:0]$3436 1'0 case - assign $5\do_step$next[0:0]$3424 $1\do_step$next[0:0]$3420 + assign $5\do_step$next[0:0]$3436 $1\do_step$next[0:0]$3432 end sync always - update \do_step$next $0\do_step$next[0:0]$3419 + update \do_step$next $0\do_step$next[0:0]$3431 end - attribute \src "libresoc.v:51624.3-51653.6" - process $proc$libresoc.v:51624$3425 + attribute \src "libresoc.v:51866.3-51895.6" + process $proc$libresoc.v:51866$3437 assign { } { } assign { } { } assign { } { } - assign $0\do_reset$next[0:0]$3426 $5\do_reset$next[0:0]$3431 - attribute \src "libresoc.v:51625.5-51625.29" + assign $0\do_reset$next[0:0]$3438 $5\do_reset$next[0:0]$3443 + attribute \src "libresoc.v:51867.5-51867.29" switch \initial - attribute \src "libresoc.v:51625.9-51625.17" + attribute \src "libresoc.v:51867.9-51867.17" case 1'1 case end @@ -92180,58 +92674,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_reset$next[0:0]$3427 $2\do_reset$next[0:0]$3428 + assign $1\do_reset$next[0:0]$3439 $2\do_reset$next[0:0]$3440 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_reset$next[0:0]$3428 $3\do_reset$next[0:0]$3429 + assign $2\do_reset$next[0:0]$3440 $3\do_reset$next[0:0]$3441 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$29 \$27 \$25 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_reset$next[0:0]$3429 $4\do_reset$next[0:0]$3430 + assign $3\do_reset$next[0:0]$3441 $4\do_reset$next[0:0]$3442 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" switch \dmi_din [1] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_reset$next[0:0]$3430 1'1 + assign $4\do_reset$next[0:0]$3442 1'1 case - assign $4\do_reset$next[0:0]$3430 1'0 + assign $4\do_reset$next[0:0]$3442 1'0 end case - assign $3\do_reset$next[0:0]$3429 1'0 + assign $3\do_reset$next[0:0]$3441 1'0 end case - assign $2\do_reset$next[0:0]$3428 1'0 + assign $2\do_reset$next[0:0]$3440 1'0 end case - assign $1\do_reset$next[0:0]$3427 1'0 + assign $1\do_reset$next[0:0]$3439 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_reset$next[0:0]$3431 1'0 + assign $5\do_reset$next[0:0]$3443 1'0 case - assign $5\do_reset$next[0:0]$3431 $1\do_reset$next[0:0]$3427 + assign $5\do_reset$next[0:0]$3443 $1\do_reset$next[0:0]$3439 end sync always - update \do_reset$next $0\do_reset$next[0:0]$3426 + update \do_reset$next $0\do_reset$next[0:0]$3438 end - attribute \src "libresoc.v:51654.3-51683.6" - process $proc$libresoc.v:51654$3432 + attribute \src "libresoc.v:51896.3-51925.6" + process $proc$libresoc.v:51896$3444 assign { } { } assign { } { } assign { } { } - assign $0\do_icreset$next[0:0]$3433 $5\do_icreset$next[0:0]$3438 - attribute \src "libresoc.v:51655.5-51655.29" + assign $0\do_icreset$next[0:0]$3445 $5\do_icreset$next[0:0]$3450 + attribute \src "libresoc.v:51897.5-51897.29" switch \initial - attribute \src "libresoc.v:51655.9-51655.17" + attribute \src "libresoc.v:51897.9-51897.17" case 1'1 case end @@ -92240,58 +92734,58 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_icreset$next[0:0]$3434 $2\do_icreset$next[0:0]$3435 + assign $1\do_icreset$next[0:0]$3446 $2\do_icreset$next[0:0]$3447 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_icreset$next[0:0]$3435 $3\do_icreset$next[0:0]$3436 + assign $2\do_icreset$next[0:0]$3447 $3\do_icreset$next[0:0]$3448 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$43 \$41 \$39 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $3\do_icreset$next[0:0]$3436 $4\do_icreset$next[0:0]$3437 + assign $3\do_icreset$next[0:0]$3448 $4\do_icreset$next[0:0]$3449 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" switch \dmi_din [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_icreset$next[0:0]$3437 1'1 + assign $4\do_icreset$next[0:0]$3449 1'1 case - assign $4\do_icreset$next[0:0]$3437 1'0 + assign $4\do_icreset$next[0:0]$3449 1'0 end case - assign $3\do_icreset$next[0:0]$3436 1'0 + assign $3\do_icreset$next[0:0]$3448 1'0 end case - assign $2\do_icreset$next[0:0]$3435 1'0 + assign $2\do_icreset$next[0:0]$3447 1'0 end case - assign $1\do_icreset$next[0:0]$3434 1'0 + assign $1\do_icreset$next[0:0]$3446 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\do_icreset$next[0:0]$3438 1'0 + assign $5\do_icreset$next[0:0]$3450 1'0 case - assign $5\do_icreset$next[0:0]$3438 $1\do_icreset$next[0:0]$3434 + assign $5\do_icreset$next[0:0]$3450 $1\do_icreset$next[0:0]$3446 end sync always - update \do_icreset$next $0\do_icreset$next[0:0]$3433 + update \do_icreset$next $0\do_icreset$next[0:0]$3445 end - attribute \src "libresoc.v:51684.3-51717.6" - process $proc$libresoc.v:51684$3439 + attribute \src "libresoc.v:51926.3-51959.6" + process $proc$libresoc.v:51926$3451 assign { } { } assign { } { } assign { } { } - assign $0\do_dmi_log_rd$next[0:0]$3440 $4\do_dmi_log_rd$next[0:0]$3444 - attribute \src "libresoc.v:51685.5-51685.29" + assign $0\do_dmi_log_rd$next[0:0]$3452 $4\do_dmi_log_rd$next[0:0]$3456 + attribute \src "libresoc.v:51927.5-51927.29" switch \initial - attribute \src "libresoc.v:51685.9-51685.17" + attribute \src "libresoc.v:51927.9-51927.17" case 1'1 case end @@ -92300,112 +92794,112 @@ module \dbg attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3441 $2\do_dmi_log_rd$next[0:0]$3442 + assign $1\do_dmi_log_rd$next[0:0]$3453 $2\do_dmi_log_rd$next[0:0]$3454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\do_dmi_log_rd$next[0:0]$3442 $3\do_dmi_log_rd$next[0:0]$3443 + assign $2\do_dmi_log_rd$next[0:0]$3454 $3\do_dmi_log_rd$next[0:0]$3455 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" switch { \$57 \$55 \$53 } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $3\do_dmi_log_rd$next[0:0]$3443 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3455 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $3\do_dmi_log_rd$next[0:0]$3443 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3455 1'0 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $3\do_dmi_log_rd$next[0:0]$3443 1'1 + assign $3\do_dmi_log_rd$next[0:0]$3455 1'1 case - assign $3\do_dmi_log_rd$next[0:0]$3443 1'0 + assign $3\do_dmi_log_rd$next[0:0]$3455 1'0 end case - assign $2\do_dmi_log_rd$next[0:0]$3442 1'0 + assign $2\do_dmi_log_rd$next[0:0]$3454 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3441 1'1 + assign $1\do_dmi_log_rd$next[0:0]$3453 1'1 case - assign $1\do_dmi_log_rd$next[0:0]$3441 1'0 + assign $1\do_dmi_log_rd$next[0:0]$3453 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\do_dmi_log_rd$next[0:0]$3444 1'0 - case - assign $4\do_dmi_log_rd$next[0:0]$3444 $1\do_dmi_log_rd$next[0:0]$3441 - end - sync always - update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3440 - end - connect \$9 $and$libresoc.v:51248$3300_Y - connect \$99 $eq$libresoc.v:51249$3301_Y - connect \$101 $not$libresoc.v:51250$3302_Y - connect \$103 $and$libresoc.v:51251$3303_Y - connect \$105 $not$libresoc.v:51252$3304_Y - connect \$107 $and$libresoc.v:51253$3305_Y - connect \$109 $eq$libresoc.v:51254$3306_Y - connect \$111 $eq$libresoc.v:51255$3307_Y - connect \$113 $eq$libresoc.v:51256$3308_Y - connect \$116 $add$libresoc.v:51257$3309_Y - connect \$118 $eq$libresoc.v:51258$3310_Y - connect \$11 $eq$libresoc.v:51259$3311_Y - connect \$120 $and$libresoc.v:51260$3312_Y - connect \$122 $not$libresoc.v:51261$3313_Y - connect \$124 $and$libresoc.v:51262$3314_Y - connect \$13 $eq$libresoc.v:51263$3315_Y - connect \$15 $eq$libresoc.v:51264$3316_Y - connect \$17 $not$libresoc.v:51265$3317_Y - connect \$1 $pos$libresoc.v:51266$3318_Y - connect \$19 $and$libresoc.v:51267$3319_Y - connect \$21 $not$libresoc.v:51268$3320_Y - connect \$23 $and$libresoc.v:51269$3321_Y - connect \$25 $eq$libresoc.v:51270$3322_Y - connect \$27 $eq$libresoc.v:51271$3323_Y - connect \$29 $eq$libresoc.v:51272$3324_Y - connect \$31 $not$libresoc.v:51273$3325_Y - connect \$33 $and$libresoc.v:51274$3326_Y - connect \$35 $not$libresoc.v:51275$3327_Y - connect \$37 $and$libresoc.v:51276$3328_Y - connect \$3 $not$libresoc.v:51277$3329_Y - connect \$39 $eq$libresoc.v:51278$3330_Y - connect \$41 $eq$libresoc.v:51279$3331_Y - connect \$43 $eq$libresoc.v:51280$3332_Y - connect \$45 $not$libresoc.v:51281$3333_Y - connect \$47 $and$libresoc.v:51282$3334_Y - connect \$49 $not$libresoc.v:51283$3335_Y - connect \$51 $and$libresoc.v:51284$3336_Y - connect \$53 $eq$libresoc.v:51285$3337_Y - connect \$55 $eq$libresoc.v:51286$3338_Y - connect \$57 $eq$libresoc.v:51287$3339_Y - connect \$5 $and$libresoc.v:51288$3340_Y - connect \$59 $not$libresoc.v:51289$3341_Y - connect \$61 $and$libresoc.v:51290$3342_Y - connect \$63 $not$libresoc.v:51291$3343_Y - connect \$65 $and$libresoc.v:51292$3344_Y - connect \$67 $eq$libresoc.v:51293$3345_Y - connect \$69 $eq$libresoc.v:51294$3346_Y - connect \$71 $eq$libresoc.v:51295$3347_Y - connect \$73 $not$libresoc.v:51296$3348_Y - connect \$75 $and$libresoc.v:51297$3349_Y - connect \$77 $not$libresoc.v:51298$3350_Y - connect \$7 $not$libresoc.v:51299$3351_Y - connect \$79 $and$libresoc.v:51300$3352_Y - connect \$81 $eq$libresoc.v:51301$3353_Y - connect \$83 $eq$libresoc.v:51302$3354_Y - connect \$85 $eq$libresoc.v:51303$3355_Y - connect \$87 $not$libresoc.v:51304$3356_Y - connect \$89 $and$libresoc.v:51305$3357_Y - connect \$91 $not$libresoc.v:51306$3358_Y - connect \$93 $and$libresoc.v:51307$3359_Y - connect \$95 $eq$libresoc.v:51308$3360_Y - connect \$97 $eq$libresoc.v:51309$3361_Y + assign $4\do_dmi_log_rd$next[0:0]$3456 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$3456 $1\do_dmi_log_rd$next[0:0]$3453 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3452 + end + connect \$9 $and$libresoc.v:51490$3312_Y + connect \$99 $eq$libresoc.v:51491$3313_Y + connect \$101 $not$libresoc.v:51492$3314_Y + connect \$103 $and$libresoc.v:51493$3315_Y + connect \$105 $not$libresoc.v:51494$3316_Y + connect \$107 $and$libresoc.v:51495$3317_Y + connect \$109 $eq$libresoc.v:51496$3318_Y + connect \$111 $eq$libresoc.v:51497$3319_Y + connect \$113 $eq$libresoc.v:51498$3320_Y + connect \$116 $add$libresoc.v:51499$3321_Y + connect \$118 $eq$libresoc.v:51500$3322_Y + connect \$11 $eq$libresoc.v:51501$3323_Y + connect \$120 $and$libresoc.v:51502$3324_Y + connect \$122 $not$libresoc.v:51503$3325_Y + connect \$124 $and$libresoc.v:51504$3326_Y + connect \$13 $eq$libresoc.v:51505$3327_Y + connect \$15 $eq$libresoc.v:51506$3328_Y + connect \$17 $not$libresoc.v:51507$3329_Y + connect \$1 $pos$libresoc.v:51508$3330_Y + connect \$19 $and$libresoc.v:51509$3331_Y + connect \$21 $not$libresoc.v:51510$3332_Y + connect \$23 $and$libresoc.v:51511$3333_Y + connect \$25 $eq$libresoc.v:51512$3334_Y + connect \$27 $eq$libresoc.v:51513$3335_Y + connect \$29 $eq$libresoc.v:51514$3336_Y + connect \$31 $not$libresoc.v:51515$3337_Y + connect \$33 $and$libresoc.v:51516$3338_Y + connect \$35 $not$libresoc.v:51517$3339_Y + connect \$37 $and$libresoc.v:51518$3340_Y + connect \$3 $not$libresoc.v:51519$3341_Y + connect \$39 $eq$libresoc.v:51520$3342_Y + connect \$41 $eq$libresoc.v:51521$3343_Y + connect \$43 $eq$libresoc.v:51522$3344_Y + connect \$45 $not$libresoc.v:51523$3345_Y + connect \$47 $and$libresoc.v:51524$3346_Y + connect \$49 $not$libresoc.v:51525$3347_Y + connect \$51 $and$libresoc.v:51526$3348_Y + connect \$53 $eq$libresoc.v:51527$3349_Y + connect \$55 $eq$libresoc.v:51528$3350_Y + connect \$57 $eq$libresoc.v:51529$3351_Y + connect \$5 $and$libresoc.v:51530$3352_Y + connect \$59 $not$libresoc.v:51531$3353_Y + connect \$61 $and$libresoc.v:51532$3354_Y + connect \$63 $not$libresoc.v:51533$3355_Y + connect \$65 $and$libresoc.v:51534$3356_Y + connect \$67 $eq$libresoc.v:51535$3357_Y + connect \$69 $eq$libresoc.v:51536$3358_Y + connect \$71 $eq$libresoc.v:51537$3359_Y + connect \$73 $not$libresoc.v:51538$3360_Y + connect \$75 $and$libresoc.v:51539$3361_Y + connect \$77 $not$libresoc.v:51540$3362_Y + connect \$7 $not$libresoc.v:51541$3363_Y + connect \$79 $and$libresoc.v:51542$3364_Y + connect \$81 $eq$libresoc.v:51543$3365_Y + connect \$83 $eq$libresoc.v:51544$3366_Y + connect \$85 $eq$libresoc.v:51545$3367_Y + connect \$87 $not$libresoc.v:51546$3368_Y + connect \$89 $and$libresoc.v:51547$3369_Y + connect \$91 $not$libresoc.v:51548$3370_Y + connect \$93 $and$libresoc.v:51549$3371_Y + connect \$95 $eq$libresoc.v:51550$3372_Y + connect \$97 $eq$libresoc.v:51551$3373_Y connect \$115 \$116 connect \log_write_addr_o 0 connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -92416,105 +92910,105 @@ module \dbg connect \d_gpr_addr \gspr_index connect \stat_reg \$1 end -attribute \src "libresoc.v:51731.1-53776.10" +attribute \src "libresoc.v:51973.1-54017.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" attribute \generator "nMigen" module \dec - attribute \src "libresoc.v:53337.3-53370.6" + attribute \src "libresoc.v:53578.3-53611.6" wire width 3 $0\ALU_cr_in[2:0] - attribute \src "libresoc.v:53371.3-53404.6" + attribute \src "libresoc.v:53612.3-53645.6" wire width 3 $0\ALU_cr_out[2:0] - attribute \src "libresoc.v:52997.3-53030.6" + attribute \src "libresoc.v:53238.3-53271.6" wire width 2 $0\ALU_cry_in[1:0] - attribute \src "libresoc.v:53099.3-53132.6" + attribute \src "libresoc.v:53340.3-53373.6" wire $0\ALU_cry_out[0:0] - attribute \src "libresoc.v:53201.3-53234.6" + attribute \src "libresoc.v:53442.3-53475.6" wire width 13 $0\ALU_function_unit[12:0] - attribute \src "libresoc.v:53269.3-53302.6" + attribute \src "libresoc.v:53510.3-53543.6" wire width 3 $0\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53303.3-53336.6" + attribute \src "libresoc.v:53544.3-53577.6" wire width 4 $0\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53235.3-53268.6" + attribute \src "libresoc.v:53476.3-53509.6" wire width 7 $0\ALU_internal_op[6:0] - attribute \src "libresoc.v:53031.3-53064.6" + attribute \src "libresoc.v:53272.3-53305.6" wire $0\ALU_inv_a[0:0] - attribute \src "libresoc.v:53065.3-53098.6" + attribute \src "libresoc.v:53306.3-53339.6" wire $0\ALU_inv_out[0:0] - attribute \src "libresoc.v:53133.3-53166.6" + attribute \src "libresoc.v:53374.3-53407.6" wire $0\ALU_is_32b[0:0] - attribute \src "libresoc.v:53405.3-53438.6" + attribute \src "libresoc.v:53646.3-53679.6" wire width 4 $0\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52963.3-52996.6" + attribute \src "libresoc.v:53204.3-53237.6" wire width 2 $0\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53167.3-53200.6" + attribute \src "libresoc.v:53408.3-53441.6" wire $0\ALU_sgn[0:0] - attribute \src "libresoc.v:51732.7-51732.20" + attribute \src "libresoc.v:51974.7-51974.20" wire $0\initial[0:0] - attribute \src "libresoc.v:53337.3-53370.6" + attribute \src "libresoc.v:53578.3-53611.6" wire width 3 $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53371.3-53404.6" + attribute \src "libresoc.v:53612.3-53645.6" wire width 3 $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:52997.3-53030.6" + attribute \src "libresoc.v:53238.3-53271.6" wire width 2 $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:53099.3-53132.6" + attribute \src "libresoc.v:53340.3-53373.6" wire $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53201.3-53234.6" + attribute \src "libresoc.v:53442.3-53475.6" wire width 13 $1\ALU_function_unit[12:0] - attribute \src "libresoc.v:53269.3-53302.6" + attribute \src "libresoc.v:53510.3-53543.6" wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53303.3-53336.6" + attribute \src "libresoc.v:53544.3-53577.6" wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53235.3-53268.6" + attribute \src "libresoc.v:53476.3-53509.6" wire width 7 $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:53031.3-53064.6" + attribute \src "libresoc.v:53272.3-53305.6" wire $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:53065.3-53098.6" + attribute \src "libresoc.v:53306.3-53339.6" wire $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:53133.3-53166.6" + attribute \src "libresoc.v:53374.3-53407.6" wire $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53405.3-53438.6" + attribute \src "libresoc.v:53646.3-53679.6" wire width 4 $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52963.3-52996.6" + attribute \src "libresoc.v:53204.3-53237.6" wire width 2 $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53167.3-53200.6" + attribute \src "libresoc.v:53408.3-53441.6" wire $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52928.17-52928.211" - wire width 32 $ternary$libresoc.v:52928$3457_Y + attribute \src "libresoc.v:53169.17-53169.211" + wire width 32 $ternary$libresoc.v:53169$3469_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \ALU_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 28 \ALU_BA + wire width 5 \ALU_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 27 \ALU_BB + wire width 5 \ALU_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 33 \ALU_BC + wire width 5 \ALU_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 26 \ALU_BD + wire width 14 output 25 \ALU_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \ALU_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \ALU_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 31 \ALU_BI + wire width 5 \ALU_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 29 \ALU_BT + wire width 5 \ALU_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \ALU_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \ALU_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 32 \ALU_DS + wire width 14 output 26 \ALU_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 output 30 \ALU_FXM + wire width 8 \ALU_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \ALU_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 24 output 23 \ALU_LI + wire width 24 output 22 \ALU_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \ALU_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -92526,9 +93020,9 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 25 \ALU_OE + wire output 24 \ALU_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 18 \ALU_RA + wire width 5 output 17 \ALU_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -92536,19 +93030,19 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 24 \ALU_Rc + wire output 23 \ALU_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 21 \ALU_SH32 + wire width 5 output 20 \ALU_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 19 \ALU_SI + wire width 16 output 18 \ALU_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 10 output 7 \ALU_SPR + wire width 10 output 5 \ALU_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \ALU_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 20 \ALU_UI + wire width 16 output 19 \ALU_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -92559,7 +93053,7 @@ module \dec attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 4 \ALU_cr_in + wire width 3 \ALU_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -92568,15 +93062,15 @@ module \dec attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 5 \ALU_cr_out + wire width 3 output 9 \ALU_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 14 \ALU_cry_in + wire width 2 output 13 \ALU_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 15 \ALU_cry_out + wire output 14 \ALU_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -92930,7 +93424,7 @@ module \dec attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 8 \ALU_function_unit + wire width 13 output 6 \ALU_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -92938,7 +93432,7 @@ module \dec attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 9 \ALU_in1_sel + wire width 3 output 7 \ALU_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -92955,7 +93449,7 @@ module \dec attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 10 \ALU_in2_sel + wire width 4 output 8 \ALU_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -93031,13 +93525,13 @@ module \dec attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 output 6 \ALU_internal_op + wire width 7 output 4 \ALU_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 12 \ALU_inv_a + wire output 11 \ALU_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 13 \ALU_inv_out + wire output 12 \ALU_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 16 \ALU_is_32b + wire output 15 \ALU_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -93045,7 +93539,7 @@ module \dec attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 11 \ALU_ldst_len + wire width 4 output 10 \ALU_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -93053,9 +93547,9 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \ALU_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 17 \ALU_sgn + wire output 16 \ALU_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 6 output 22 \ALU_sh + wire width 6 output 21 \ALU_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \A_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -93357,7 +93851,7 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 output 36 \XL_BT + wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -93485,9 +93979,9 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 34 \X_BF + wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 35 \X_BFA + wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -93656,24 +94150,24 @@ module \dec wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:51732.7-51732.15" + attribute \src "libresoc.v:51974.7-51974.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 37 \raw_opcode_in + wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:52928$3457 + cell $mux $ternary$libresoc.v:53169$3469 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:52928$3457_Y + connect \Y $ternary$libresoc.v:53169$3469_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:52929.13-52945.4" + attribute \src "libresoc.v:53170.13-53186.4" cell \ALU_dec19 \ALU_dec19 connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out @@ -93692,7 +94186,7 @@ module \dec connect \opcode_in \ALU_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:52946.13-52962.4" + attribute \src "libresoc.v:53187.13-53203.4" cell \ALU_dec31 \ALU_dec31 connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out @@ -93710,22 +94204,22 @@ module \dec connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn connect \opcode_in \ALU_dec31_opcode_in end - attribute \src "libresoc.v:51732.7-51732.20" - process $proc$libresoc.v:51732$3472 + attribute \src "libresoc.v:51974.7-51974.20" + process $proc$libresoc.v:51974$3484 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:52963.3-52996.6" - process $proc$libresoc.v:52963$3458 + attribute \src "libresoc.v:53204.3-53237.6" + process $proc$libresoc.v:53204$3470 assign { } { } assign { } { } assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52964.5-52964.29" + attribute \src "libresoc.v:53205.5-53205.29" switch \initial - attribute \src "libresoc.v:52964.9-52964.17" + attribute \src "libresoc.v:53205.9-53205.17" case 1'1 case end @@ -93773,14 +94267,14 @@ module \dec sync always update \ALU_rc_sel $0\ALU_rc_sel[1:0] end - attribute \src "libresoc.v:52997.3-53030.6" - process $proc$libresoc.v:52997$3459 + attribute \src "libresoc.v:53238.3-53271.6" + process $proc$libresoc.v:53238$3471 assign { } { } assign { } { } assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:52998.5-52998.29" + attribute \src "libresoc.v:53239.5-53239.29" switch \initial - attribute \src "libresoc.v:52998.9-52998.17" + attribute \src "libresoc.v:53239.9-53239.17" case 1'1 case end @@ -93828,14 +94322,14 @@ module \dec sync always update \ALU_cry_in $0\ALU_cry_in[1:0] end - attribute \src "libresoc.v:53031.3-53064.6" - process $proc$libresoc.v:53031$3460 + attribute \src "libresoc.v:53272.3-53305.6" + process $proc$libresoc.v:53272$3472 assign { } { } assign { } { } assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:53032.5-53032.29" + attribute \src "libresoc.v:53273.5-53273.29" switch \initial - attribute \src "libresoc.v:53032.9-53032.17" + attribute \src "libresoc.v:53273.9-53273.17" case 1'1 case end @@ -93883,14 +94377,14 @@ module \dec sync always update \ALU_inv_a $0\ALU_inv_a[0:0] end - attribute \src "libresoc.v:53065.3-53098.6" - process $proc$libresoc.v:53065$3461 + attribute \src "libresoc.v:53306.3-53339.6" + process $proc$libresoc.v:53306$3473 assign { } { } assign { } { } assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:53066.5-53066.29" + attribute \src "libresoc.v:53307.5-53307.29" switch \initial - attribute \src "libresoc.v:53066.9-53066.17" + attribute \src "libresoc.v:53307.9-53307.17" case 1'1 case end @@ -93938,14 +94432,14 @@ module \dec sync always update \ALU_inv_out $0\ALU_inv_out[0:0] end - attribute \src "libresoc.v:53099.3-53132.6" - process $proc$libresoc.v:53099$3462 + attribute \src "libresoc.v:53340.3-53373.6" + process $proc$libresoc.v:53340$3474 assign { } { } assign { } { } assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53100.5-53100.29" + attribute \src "libresoc.v:53341.5-53341.29" switch \initial - attribute \src "libresoc.v:53100.9-53100.17" + attribute \src "libresoc.v:53341.9-53341.17" case 1'1 case end @@ -93993,14 +94487,14 @@ module \dec sync always update \ALU_cry_out $0\ALU_cry_out[0:0] end - attribute \src "libresoc.v:53133.3-53166.6" - process $proc$libresoc.v:53133$3463 + attribute \src "libresoc.v:53374.3-53407.6" + process $proc$libresoc.v:53374$3475 assign { } { } assign { } { } assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53134.5-53134.29" + attribute \src "libresoc.v:53375.5-53375.29" switch \initial - attribute \src "libresoc.v:53134.9-53134.17" + attribute \src "libresoc.v:53375.9-53375.17" case 1'1 case end @@ -94048,14 +94542,14 @@ module \dec sync always update \ALU_is_32b $0\ALU_is_32b[0:0] end - attribute \src "libresoc.v:53167.3-53200.6" - process $proc$libresoc.v:53167$3464 + attribute \src "libresoc.v:53408.3-53441.6" + process $proc$libresoc.v:53408$3476 assign { } { } assign { } { } assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "libresoc.v:53168.5-53168.29" + attribute \src "libresoc.v:53409.5-53409.29" switch \initial - attribute \src "libresoc.v:53168.9-53168.17" + attribute \src "libresoc.v:53409.9-53409.17" case 1'1 case end @@ -94103,14 +94597,14 @@ module \dec sync always update \ALU_sgn $0\ALU_sgn[0:0] end - attribute \src "libresoc.v:53201.3-53234.6" - process $proc$libresoc.v:53201$3465 + attribute \src "libresoc.v:53442.3-53475.6" + process $proc$libresoc.v:53442$3477 assign { } { } assign { } { } assign $0\ALU_function_unit[12:0] $1\ALU_function_unit[12:0] - attribute \src "libresoc.v:53202.5-53202.29" + attribute \src "libresoc.v:53443.5-53443.29" switch \initial - attribute \src "libresoc.v:53202.9-53202.17" + attribute \src "libresoc.v:53443.9-53443.17" case 1'1 case end @@ -94158,14 +94652,14 @@ module \dec sync always update \ALU_function_unit $0\ALU_function_unit[12:0] end - attribute \src "libresoc.v:53235.3-53268.6" - process $proc$libresoc.v:53235$3466 + attribute \src "libresoc.v:53476.3-53509.6" + process $proc$libresoc.v:53476$3478 assign { } { } assign { } { } assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:53236.5-53236.29" + attribute \src "libresoc.v:53477.5-53477.29" switch \initial - attribute \src "libresoc.v:53236.9-53236.17" + attribute \src "libresoc.v:53477.9-53477.17" case 1'1 case end @@ -94213,14 +94707,14 @@ module \dec sync always update \ALU_internal_op $0\ALU_internal_op[6:0] end - attribute \src "libresoc.v:53269.3-53302.6" - process $proc$libresoc.v:53269$3467 + attribute \src "libresoc.v:53510.3-53543.6" + process $proc$libresoc.v:53510$3479 assign { } { } assign { } { } assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53270.5-53270.29" + attribute \src "libresoc.v:53511.5-53511.29" switch \initial - attribute \src "libresoc.v:53270.9-53270.17" + attribute \src "libresoc.v:53511.9-53511.17" case 1'1 case end @@ -94268,14 +94762,14 @@ module \dec sync always update \ALU_in1_sel $0\ALU_in1_sel[2:0] end - attribute \src "libresoc.v:53303.3-53336.6" - process $proc$libresoc.v:53303$3468 + attribute \src "libresoc.v:53544.3-53577.6" + process $proc$libresoc.v:53544$3480 assign { } { } assign { } { } assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53304.5-53304.29" + attribute \src "libresoc.v:53545.5-53545.29" switch \initial - attribute \src "libresoc.v:53304.9-53304.17" + attribute \src "libresoc.v:53545.9-53545.17" case 1'1 case end @@ -94323,14 +94817,14 @@ module \dec sync always update \ALU_in2_sel $0\ALU_in2_sel[3:0] end - attribute \src "libresoc.v:53337.3-53370.6" - process $proc$libresoc.v:53337$3469 + attribute \src "libresoc.v:53578.3-53611.6" + process $proc$libresoc.v:53578$3481 assign { } { } assign { } { } assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53338.5-53338.29" + attribute \src "libresoc.v:53579.5-53579.29" switch \initial - attribute \src "libresoc.v:53338.9-53338.17" + attribute \src "libresoc.v:53579.9-53579.17" case 1'1 case end @@ -94378,14 +94872,14 @@ module \dec sync always update \ALU_cr_in $0\ALU_cr_in[2:0] end - attribute \src "libresoc.v:53371.3-53404.6" - process $proc$libresoc.v:53371$3470 + attribute \src "libresoc.v:53612.3-53645.6" + process $proc$libresoc.v:53612$3482 assign { } { } assign { } { } assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:53372.5-53372.29" + attribute \src "libresoc.v:53613.5-53613.29" switch \initial - attribute \src "libresoc.v:53372.9-53372.17" + attribute \src "libresoc.v:53613.9-53613.17" case 1'1 case end @@ -94433,14 +94927,14 @@ module \dec sync always update \ALU_cr_out $0\ALU_cr_out[2:0] end - attribute \src "libresoc.v:53405.3-53438.6" - process $proc$libresoc.v:53405$3471 + attribute \src "libresoc.v:53646.3-53679.6" + process $proc$libresoc.v:53646$3483 assign { } { } assign { } { } assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:53406.5-53406.29" + attribute \src "libresoc.v:53647.5-53647.29" switch \initial - attribute \src "libresoc.v:53406.9-53406.17" + attribute \src "libresoc.v:53647.9-53647.17" case 1'1 case end @@ -94488,7 +94982,7 @@ module \dec sync always update \ALU_ldst_len $0\ALU_ldst_len[3:0] end - connect \$1 $ternary$libresoc.v:52928$3457_Y + connect \$1 $ternary$libresoc.v:53169$3469_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -94827,35 +95321,35 @@ module \dec connect \ALU_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:53780.1-55240.10" +attribute \src "libresoc.v:54021.1-55480.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" attribute \generator "nMigen" -module \dec$139 - attribute \src "libresoc.v:54864.3-54876.6" +module \dec$138 + attribute \src "libresoc.v:55104.3-55116.6" wire width 3 $0\CR_cr_in[2:0] - attribute \src "libresoc.v:54877.3-54889.6" + attribute \src "libresoc.v:55117.3-55129.6" wire width 3 $0\CR_cr_out[2:0] - attribute \src "libresoc.v:54838.3-54850.6" + attribute \src "libresoc.v:55078.3-55090.6" wire width 13 $0\CR_function_unit[12:0] - attribute \src "libresoc.v:54851.3-54863.6" + attribute \src "libresoc.v:55091.3-55103.6" wire width 7 $0\CR_internal_op[6:0] - attribute \src "libresoc.v:54890.3-54902.6" + attribute \src "libresoc.v:55130.3-55142.6" wire width 2 $0\CR_rc_sel[1:0] - attribute \src "libresoc.v:53781.7-53781.20" + attribute \src "libresoc.v:54022.7-54022.20" wire $0\initial[0:0] - attribute \src "libresoc.v:54864.3-54876.6" + attribute \src "libresoc.v:55104.3-55116.6" wire width 3 $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54877.3-54889.6" + attribute \src "libresoc.v:55117.3-55129.6" wire width 3 $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54838.3-54850.6" + attribute \src "libresoc.v:55078.3-55090.6" wire width 13 $1\CR_function_unit[12:0] - attribute \src "libresoc.v:54851.3-54863.6" + attribute \src "libresoc.v:55091.3-55103.6" wire width 7 $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54890.3-54902.6" + attribute \src "libresoc.v:55130.3-55142.6" wire width 2 $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54821.17-54821.211" - wire width 32 $ternary$libresoc.v:54821$3473_Y + attribute \src "libresoc.v:55061.17-55061.211" + wire width 32 $ternary$libresoc.v:55061$3485_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -94891,11 +95385,11 @@ module \dec$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \CR_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 12 \CR_BA + wire width 5 \CR_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 11 \CR_BB + wire width 5 \CR_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 16 \CR_BC + wire width 5 \CR_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \CR_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -94903,11 +95397,11 @@ module \dec$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \CR_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 15 \CR_BI + wire width 5 \CR_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 13 \CR_BT + wire width 5 \CR_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \CR_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -94915,7 +95409,7 @@ module \dec$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \CR_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 output 14 \CR_FXM + wire width 8 \CR_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \CR_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -94931,7 +95425,7 @@ module \dec$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 10 \CR_OE + wire output 9 \CR_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -94941,7 +95435,7 @@ module \dec$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 9 \CR_Rc + wire output 8 \CR_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -94949,7 +95443,7 @@ module \dec$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \CR_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 10 output 7 \CR_SPR + wire width 10 output 5 \CR_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \CR_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -94964,7 +95458,7 @@ module \dec$139 attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 4 \CR_cr_in + wire width 3 \CR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -94973,7 +95467,7 @@ module \dec$139 attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 5 \CR_cr_out + wire width 3 output 7 \CR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -95229,7 +95723,7 @@ module \dec$139 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 8 \CR_function_unit + wire width 13 output 6 \CR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -95305,7 +95799,7 @@ module \dec$139 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 output 6 \CR_internal_op + wire width 7 output 4 \CR_internal_op attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -95585,7 +96079,7 @@ module \dec$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 output 19 \XL_BT + wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -95713,9 +96207,9 @@ module \dec$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 17 \X_BF + wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 18 \X_BFA + wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -95884,24 +96378,24 @@ module \dec$139 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:53781.7-53781.15" + attribute \src "libresoc.v:54022.7-54022.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 20 \raw_opcode_in + wire width 32 input 10 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:54821$3473 + cell $mux $ternary$libresoc.v:55061$3485 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:54821$3473_Y + connect \Y $ternary$libresoc.v:55061$3485_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:54822.12-54829.4" + attribute \src "libresoc.v:55062.12-55069.4" cell \CR_dec19 \CR_dec19 connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out @@ -95911,7 +96405,7 @@ module \dec$139 connect \opcode_in \CR_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:54830.12-54837.4" + attribute \src "libresoc.v:55070.12-55077.4" cell \CR_dec31 \CR_dec31 connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out @@ -95920,22 +96414,22 @@ module \dec$139 connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel connect \opcode_in \CR_dec31_opcode_in end - attribute \src "libresoc.v:53781.7-53781.20" - process $proc$libresoc.v:53781$3479 + attribute \src "libresoc.v:54022.7-54022.20" + process $proc$libresoc.v:54022$3491 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:54838.3-54850.6" - process $proc$libresoc.v:54838$3474 + attribute \src "libresoc.v:55078.3-55090.6" + process $proc$libresoc.v:55078$3486 assign { } { } assign { } { } assign $0\CR_function_unit[12:0] $1\CR_function_unit[12:0] - attribute \src "libresoc.v:54839.5-54839.29" + attribute \src "libresoc.v:55079.5-55079.29" switch \initial - attribute \src "libresoc.v:54839.9-54839.17" + attribute \src "libresoc.v:55079.9-55079.17" case 1'1 case end @@ -95955,14 +96449,14 @@ module \dec$139 sync always update \CR_function_unit $0\CR_function_unit[12:0] end - attribute \src "libresoc.v:54851.3-54863.6" - process $proc$libresoc.v:54851$3475 + attribute \src "libresoc.v:55091.3-55103.6" + process $proc$libresoc.v:55091$3487 assign { } { } assign { } { } assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54852.5-54852.29" + attribute \src "libresoc.v:55092.5-55092.29" switch \initial - attribute \src "libresoc.v:54852.9-54852.17" + attribute \src "libresoc.v:55092.9-55092.17" case 1'1 case end @@ -95982,14 +96476,14 @@ module \dec$139 sync always update \CR_internal_op $0\CR_internal_op[6:0] end - attribute \src "libresoc.v:54864.3-54876.6" - process $proc$libresoc.v:54864$3476 + attribute \src "libresoc.v:55104.3-55116.6" + process $proc$libresoc.v:55104$3488 assign { } { } assign { } { } assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54865.5-54865.29" + attribute \src "libresoc.v:55105.5-55105.29" switch \initial - attribute \src "libresoc.v:54865.9-54865.17" + attribute \src "libresoc.v:55105.9-55105.17" case 1'1 case end @@ -96009,14 +96503,14 @@ module \dec$139 sync always update \CR_cr_in $0\CR_cr_in[2:0] end - attribute \src "libresoc.v:54877.3-54889.6" - process $proc$libresoc.v:54877$3477 + attribute \src "libresoc.v:55117.3-55129.6" + process $proc$libresoc.v:55117$3489 assign { } { } assign { } { } assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54878.5-54878.29" + attribute \src "libresoc.v:55118.5-55118.29" switch \initial - attribute \src "libresoc.v:54878.9-54878.17" + attribute \src "libresoc.v:55118.9-55118.17" case 1'1 case end @@ -96036,14 +96530,14 @@ module \dec$139 sync always update \CR_cr_out $0\CR_cr_out[2:0] end - attribute \src "libresoc.v:54890.3-54902.6" - process $proc$libresoc.v:54890$3478 + attribute \src "libresoc.v:55130.3-55142.6" + process $proc$libresoc.v:55130$3490 assign { } { } assign { } { } assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54891.5-54891.29" + attribute \src "libresoc.v:55131.5-55131.29" switch \initial - attribute \src "libresoc.v:54891.9-54891.17" + attribute \src "libresoc.v:55131.9-55131.17" case 1'1 case end @@ -96063,7 +96557,7 @@ module \dec$139 sync always update \CR_rc_sel $0\CR_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:54821$3473_Y + connect \$1 $ternary$libresoc.v:55061$3485_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -96402,47 +96896,47 @@ module \dec$139 connect \CR_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:55244.1-56686.10" +attribute \src "libresoc.v:55484.1-56925.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" attribute \generator "nMigen" -module \dec$146 - attribute \src "libresoc.v:56270.3-56285.6" +module \dec$141 + attribute \src "libresoc.v:56509.3-56524.6" wire width 3 $0\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56286.3-56301.6" + attribute \src "libresoc.v:56525.3-56540.6" wire width 3 $0\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56222.3-56237.6" + attribute \src "libresoc.v:56461.3-56476.6" wire width 13 $0\BRANCH_function_unit[12:0] - attribute \src "libresoc.v:56254.3-56269.6" + attribute \src "libresoc.v:56493.3-56508.6" wire width 4 $0\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56238.3-56253.6" + attribute \src "libresoc.v:56477.3-56492.6" wire width 7 $0\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56318.3-56333.6" + attribute \src "libresoc.v:56557.3-56572.6" wire $0\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56334.3-56349.6" + attribute \src "libresoc.v:56573.3-56588.6" wire $0\BRANCH_lk[0:0] - attribute \src "libresoc.v:56302.3-56317.6" + attribute \src "libresoc.v:56541.3-56556.6" wire width 2 $0\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55245.7-55245.20" + attribute \src "libresoc.v:55485.7-55485.20" wire $0\initial[0:0] - attribute \src "libresoc.v:56270.3-56285.6" + attribute \src "libresoc.v:56509.3-56524.6" wire width 3 $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56286.3-56301.6" + attribute \src "libresoc.v:56525.3-56540.6" wire width 3 $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56222.3-56237.6" + attribute \src "libresoc.v:56461.3-56476.6" wire width 13 $1\BRANCH_function_unit[12:0] - attribute \src "libresoc.v:56254.3-56269.6" + attribute \src "libresoc.v:56493.3-56508.6" wire width 4 $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56238.3-56253.6" + attribute \src "libresoc.v:56477.3-56492.6" wire width 7 $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56318.3-56333.6" + attribute \src "libresoc.v:56557.3-56572.6" wire $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56334.3-56349.6" + attribute \src "libresoc.v:56573.3-56588.6" wire $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56302.3-56317.6" + attribute \src "libresoc.v:56541.3-56556.6" wire width 2 $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56210.17-56210.211" - wire width 32 $ternary$libresoc.v:56210$3480_Y + attribute \src "libresoc.v:56449.17-56449.211" + wire width 32 $ternary$libresoc.v:56449$3492_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -96468,37 +96962,37 @@ module \dec$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \BRANCH_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 22 \BRANCH_BA + wire width 5 \BRANCH_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 21 \BRANCH_BB + wire width 5 \BRANCH_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 27 \BRANCH_BC + wire width 5 \BRANCH_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 20 \BRANCH_BD + wire width 14 output 19 \BRANCH_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \BRANCH_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \BRANCH_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 25 \BRANCH_BI + wire width 5 \BRANCH_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 23 \BRANCH_BT + wire width 5 \BRANCH_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \BRANCH_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \BRANCH_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 26 \BRANCH_DS + wire width 14 output 20 \BRANCH_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 output 24 \BRANCH_FXM + wire width 8 \BRANCH_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \BRANCH_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 24 output 17 \BRANCH_LI + wire width 24 output 16 \BRANCH_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 12 \BRANCH_LK + wire output 11 \BRANCH_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -96508,7 +97002,7 @@ module \dec$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 19 \BRANCH_OE + wire output 18 \BRANCH_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -96518,19 +97012,19 @@ module \dec$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 18 \BRANCH_Rc + wire output 17 \BRANCH_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 15 \BRANCH_SH32 + wire width 5 output 14 \BRANCH_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 13 \BRANCH_SI + wire width 16 output 12 \BRANCH_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 10 output 7 \BRANCH_SPR + wire width 10 output 5 \BRANCH_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \BRANCH_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 14 \BRANCH_UI + wire width 16 output 13 \BRANCH_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -96541,7 +97035,7 @@ module \dec$146 attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 4 \BRANCH_cr_in + wire width 3 \BRANCH_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -96550,7 +97044,7 @@ module \dec$146 attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 5 \BRANCH_cr_out + wire width 3 output 8 \BRANCH_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -96707,7 +97201,7 @@ module \dec$146 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 8 \BRANCH_function_unit + wire width 13 output 6 \BRANCH_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -96724,7 +97218,7 @@ module \dec$146 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 9 \BRANCH_in2_sel + wire width 4 output 7 \BRANCH_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -96800,11 +97294,11 @@ module \dec$146 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 output 6 \BRANCH_internal_op + wire width 7 output 4 \BRANCH_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 10 \BRANCH_is_32b + wire output 9 \BRANCH_is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 11 \BRANCH_lk + wire output 10 \BRANCH_lk attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -96812,7 +97306,7 @@ module \dec$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \BRANCH_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 6 output 16 \BRANCH_sh + wire width 6 output 15 \BRANCH_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \B_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -97094,7 +97588,7 @@ module \dec$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 output 30 \XL_BT + wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -97222,9 +97716,9 @@ module \dec$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 28 \X_BF + wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 29 \X_BFA + wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -97393,24 +97887,24 @@ module \dec$146 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:55245.7-55245.15" + attribute \src "libresoc.v:55485.7-55485.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 31 \raw_opcode_in + wire width 32 input 21 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:56210$3480 + cell $mux $ternary$libresoc.v:56449$3492 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:56210$3480_Y + connect \Y $ternary$libresoc.v:56449$3492_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:56211.16-56221.4" + attribute \src "libresoc.v:56450.16-56460.4" cell \BRANCH_dec19 \BRANCH_dec19 connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out @@ -97422,22 +97916,22 @@ module \dec$146 connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel connect \opcode_in \BRANCH_dec19_opcode_in end - attribute \src "libresoc.v:55245.7-55245.20" - process $proc$libresoc.v:55245$3489 + attribute \src "libresoc.v:55485.7-55485.20" + process $proc$libresoc.v:55485$3501 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:56222.3-56237.6" - process $proc$libresoc.v:56222$3481 + attribute \src "libresoc.v:56461.3-56476.6" + process $proc$libresoc.v:56461$3493 assign { } { } assign { } { } assign $0\BRANCH_function_unit[12:0] $1\BRANCH_function_unit[12:0] - attribute \src "libresoc.v:56223.5-56223.29" + attribute \src "libresoc.v:56462.5-56462.29" switch \initial - attribute \src "libresoc.v:56223.9-56223.17" + attribute \src "libresoc.v:56462.9-56462.17" case 1'1 case end @@ -97461,14 +97955,14 @@ module \dec$146 sync always update \BRANCH_function_unit $0\BRANCH_function_unit[12:0] end - attribute \src "libresoc.v:56238.3-56253.6" - process $proc$libresoc.v:56238$3482 + attribute \src "libresoc.v:56477.3-56492.6" + process $proc$libresoc.v:56477$3494 assign { } { } assign { } { } assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56239.5-56239.29" + attribute \src "libresoc.v:56478.5-56478.29" switch \initial - attribute \src "libresoc.v:56239.9-56239.17" + attribute \src "libresoc.v:56478.9-56478.17" case 1'1 case end @@ -97492,14 +97986,14 @@ module \dec$146 sync always update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] end - attribute \src "libresoc.v:56254.3-56269.6" - process $proc$libresoc.v:56254$3483 + attribute \src "libresoc.v:56493.3-56508.6" + process $proc$libresoc.v:56493$3495 assign { } { } assign { } { } assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56255.5-56255.29" + attribute \src "libresoc.v:56494.5-56494.29" switch \initial - attribute \src "libresoc.v:56255.9-56255.17" + attribute \src "libresoc.v:56494.9-56494.17" case 1'1 case end @@ -97523,14 +98017,14 @@ module \dec$146 sync always update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] end - attribute \src "libresoc.v:56270.3-56285.6" - process $proc$libresoc.v:56270$3484 + attribute \src "libresoc.v:56509.3-56524.6" + process $proc$libresoc.v:56509$3496 assign { } { } assign { } { } assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56271.5-56271.29" + attribute \src "libresoc.v:56510.5-56510.29" switch \initial - attribute \src "libresoc.v:56271.9-56271.17" + attribute \src "libresoc.v:56510.9-56510.17" case 1'1 case end @@ -97554,14 +98048,14 @@ module \dec$146 sync always update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] end - attribute \src "libresoc.v:56286.3-56301.6" - process $proc$libresoc.v:56286$3485 + attribute \src "libresoc.v:56525.3-56540.6" + process $proc$libresoc.v:56525$3497 assign { } { } assign { } { } assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56287.5-56287.29" + attribute \src "libresoc.v:56526.5-56526.29" switch \initial - attribute \src "libresoc.v:56287.9-56287.17" + attribute \src "libresoc.v:56526.9-56526.17" case 1'1 case end @@ -97585,14 +98079,14 @@ module \dec$146 sync always update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] end - attribute \src "libresoc.v:56302.3-56317.6" - process $proc$libresoc.v:56302$3486 + attribute \src "libresoc.v:56541.3-56556.6" + process $proc$libresoc.v:56541$3498 assign { } { } assign { } { } assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56303.5-56303.29" + attribute \src "libresoc.v:56542.5-56542.29" switch \initial - attribute \src "libresoc.v:56303.9-56303.17" + attribute \src "libresoc.v:56542.9-56542.17" case 1'1 case end @@ -97616,14 +98110,14 @@ module \dec$146 sync always update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] end - attribute \src "libresoc.v:56318.3-56333.6" - process $proc$libresoc.v:56318$3487 + attribute \src "libresoc.v:56557.3-56572.6" + process $proc$libresoc.v:56557$3499 assign { } { } assign { } { } assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56319.5-56319.29" + attribute \src "libresoc.v:56558.5-56558.29" switch \initial - attribute \src "libresoc.v:56319.9-56319.17" + attribute \src "libresoc.v:56558.9-56558.17" case 1'1 case end @@ -97647,14 +98141,14 @@ module \dec$146 sync always update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] end - attribute \src "libresoc.v:56334.3-56349.6" - process $proc$libresoc.v:56334$3488 + attribute \src "libresoc.v:56573.3-56588.6" + process $proc$libresoc.v:56573$3500 assign { } { } assign { } { } assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56335.5-56335.29" + attribute \src "libresoc.v:56574.5-56574.29" switch \initial - attribute \src "libresoc.v:56335.9-56335.17" + attribute \src "libresoc.v:56574.9-56574.17" case 1'1 case end @@ -97678,7 +98172,7 @@ module \dec$146 sync always update \BRANCH_lk $0\BRANCH_lk[0:0] end - connect \$1 $ternary$libresoc.v:56210$3480_Y + connect \$1 $ternary$libresoc.v:56449$3492_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -98016,71 +98510,71 @@ module \dec$146 connect \BRANCH_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:56690.1-58464.10" +attribute \src "libresoc.v:56929.1-58702.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" attribute \generator "nMigen" -module \dec$154 - attribute \src "libresoc.v:58016.3-58043.6" +module \dec$145 + attribute \src "libresoc.v:58254.3-58281.6" wire width 3 $0\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:58044.3-58071.6" + attribute \src "libresoc.v:58282.3-58309.6" wire width 3 $0\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57736.3-57763.6" + attribute \src "libresoc.v:57974.3-58001.6" wire width 2 $0\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57820.3-57847.6" + attribute \src "libresoc.v:58058.3-58085.6" wire $0\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57904.3-57931.6" + attribute \src "libresoc.v:58142.3-58169.6" wire width 13 $0\LOGICAL_function_unit[12:0] - attribute \src "libresoc.v:57960.3-57987.6" + attribute \src "libresoc.v:58198.3-58225.6" wire width 3 $0\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57988.3-58015.6" + attribute \src "libresoc.v:58226.3-58253.6" wire width 4 $0\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57932.3-57959.6" + attribute \src "libresoc.v:58170.3-58197.6" wire width 7 $0\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57764.3-57791.6" + attribute \src "libresoc.v:58002.3-58029.6" wire $0\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57792.3-57819.6" + attribute \src "libresoc.v:58030.3-58057.6" wire $0\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57848.3-57875.6" + attribute \src "libresoc.v:58086.3-58113.6" wire $0\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:58072.3-58099.6" + attribute \src "libresoc.v:58310.3-58337.6" wire width 4 $0\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58100.3-58127.6" + attribute \src "libresoc.v:58338.3-58365.6" wire width 2 $0\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57876.3-57903.6" + attribute \src "libresoc.v:58114.3-58141.6" wire $0\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:56691.7-56691.20" + attribute \src "libresoc.v:56930.7-56930.20" wire $0\initial[0:0] - attribute \src "libresoc.v:58016.3-58043.6" + attribute \src "libresoc.v:58254.3-58281.6" wire width 3 $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:58044.3-58071.6" + attribute \src "libresoc.v:58282.3-58309.6" wire width 3 $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57736.3-57763.6" + attribute \src "libresoc.v:57974.3-58001.6" wire width 2 $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57820.3-57847.6" + attribute \src "libresoc.v:58058.3-58085.6" wire $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57904.3-57931.6" + attribute \src "libresoc.v:58142.3-58169.6" wire width 13 $1\LOGICAL_function_unit[12:0] - attribute \src "libresoc.v:57960.3-57987.6" + attribute \src "libresoc.v:58198.3-58225.6" wire width 3 $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57988.3-58015.6" + attribute \src "libresoc.v:58226.3-58253.6" wire width 4 $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57932.3-57959.6" + attribute \src "libresoc.v:58170.3-58197.6" wire width 7 $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57764.3-57791.6" + attribute \src "libresoc.v:58002.3-58029.6" wire $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57792.3-57819.6" + attribute \src "libresoc.v:58030.3-58057.6" wire $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57848.3-57875.6" + attribute \src "libresoc.v:58086.3-58113.6" wire $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:58072.3-58099.6" + attribute \src "libresoc.v:58310.3-58337.6" wire width 4 $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58100.3-58127.6" + attribute \src "libresoc.v:58338.3-58365.6" wire width 2 $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57876.3-57903.6" + attribute \src "libresoc.v:58114.3-58141.6" wire $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57718.17-57718.211" - wire width 32 $ternary$libresoc.v:57718$3490_Y + attribute \src "libresoc.v:57956.17-57956.211" + wire width 32 $ternary$libresoc.v:57956$3502_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -98206,35 +98700,35 @@ module \dec$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LOGICAL_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 28 \LOGICAL_BA + wire width 5 \LOGICAL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 27 \LOGICAL_BB + wire width 5 \LOGICAL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 33 \LOGICAL_BC + wire width 5 \LOGICAL_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 26 \LOGICAL_BD + wire width 14 output 25 \LOGICAL_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \LOGICAL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \LOGICAL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 31 \LOGICAL_BI + wire width 5 \LOGICAL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 29 \LOGICAL_BT + wire width 5 \LOGICAL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \LOGICAL_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \LOGICAL_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 32 \LOGICAL_DS + wire width 14 output 26 \LOGICAL_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 output 30 \LOGICAL_FXM + wire width 8 \LOGICAL_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LOGICAL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 24 output 23 \LOGICAL_LI + wire width 24 output 22 \LOGICAL_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LOGICAL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -98246,9 +98740,9 @@ module \dec$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 25 \LOGICAL_OE + wire output 24 \LOGICAL_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 18 \LOGICAL_RA + wire width 5 output 17 \LOGICAL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -98256,19 +98750,19 @@ module \dec$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 24 \LOGICAL_Rc + wire output 23 \LOGICAL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 21 \LOGICAL_SH32 + wire width 5 output 20 \LOGICAL_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 19 \LOGICAL_SI + wire width 16 output 18 \LOGICAL_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 10 output 7 \LOGICAL_SPR + wire width 10 output 5 \LOGICAL_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LOGICAL_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 20 \LOGICAL_UI + wire width 16 output 19 \LOGICAL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -98279,7 +98773,7 @@ module \dec$154 attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 4 \LOGICAL_cr_in + wire width 3 \LOGICAL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -98288,15 +98782,15 @@ module \dec$154 attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 5 \LOGICAL_cr_out + wire width 3 output 9 \LOGICAL_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 14 \LOGICAL_cry_in + wire width 2 output 13 \LOGICAL_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 15 \LOGICAL_cry_out + wire output 14 \LOGICAL_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -98481,7 +98975,7 @@ module \dec$154 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 8 \LOGICAL_function_unit + wire width 13 output 6 \LOGICAL_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -98489,7 +98983,7 @@ module \dec$154 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 9 \LOGICAL_in1_sel + wire width 3 output 7 \LOGICAL_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -98506,7 +99000,7 @@ module \dec$154 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 10 \LOGICAL_in2_sel + wire width 4 output 8 \LOGICAL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -98582,13 +99076,13 @@ module \dec$154 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 output 6 \LOGICAL_internal_op + wire width 7 output 4 \LOGICAL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 12 \LOGICAL_inv_a + wire output 11 \LOGICAL_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 13 \LOGICAL_inv_out + wire output 12 \LOGICAL_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 16 \LOGICAL_is_32b + wire output 15 \LOGICAL_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -98596,7 +99090,7 @@ module \dec$154 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 11 \LOGICAL_ldst_len + wire width 4 output 10 \LOGICAL_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -98604,9 +99098,9 @@ module \dec$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \LOGICAL_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 17 \LOGICAL_sgn + wire output 16 \LOGICAL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 6 output 22 \LOGICAL_sh + wire width 6 output 21 \LOGICAL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -98788,7 +99282,7 @@ module \dec$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 output 36 \XL_BT + wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -98916,9 +99410,9 @@ module \dec$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 34 \X_BF + wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 35 \X_BFA + wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -99087,24 +99581,24 @@ module \dec$154 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:56691.7-56691.15" + attribute \src "libresoc.v:56930.7-56930.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 37 \raw_opcode_in + wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:57718$3490 + cell $mux $ternary$libresoc.v:57956$3502 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:57718$3490_Y + connect \Y $ternary$libresoc.v:57956$3502_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:57719.17-57735.4" + attribute \src "libresoc.v:57957.17-57973.4" cell \LOGICAL_dec31 \LOGICAL_dec31 connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out @@ -99122,22 +99616,22 @@ module \dec$154 connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn connect \opcode_in \LOGICAL_dec31_opcode_in end - attribute \src "libresoc.v:56691.7-56691.20" - process $proc$libresoc.v:56691$3505 + attribute \src "libresoc.v:56930.7-56930.20" + process $proc$libresoc.v:56930$3517 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:57736.3-57763.6" - process $proc$libresoc.v:57736$3491 + attribute \src "libresoc.v:57974.3-58001.6" + process $proc$libresoc.v:57974$3503 assign { } { } assign { } { } assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57737.5-57737.29" + attribute \src "libresoc.v:57975.5-57975.29" switch \initial - attribute \src "libresoc.v:57737.9-57737.17" + attribute \src "libresoc.v:57975.9-57975.17" case 1'1 case end @@ -99177,14 +99671,14 @@ module \dec$154 sync always update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] end - attribute \src "libresoc.v:57764.3-57791.6" - process $proc$libresoc.v:57764$3492 + attribute \src "libresoc.v:58002.3-58029.6" + process $proc$libresoc.v:58002$3504 assign { } { } assign { } { } assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57765.5-57765.29" + attribute \src "libresoc.v:58003.5-58003.29" switch \initial - attribute \src "libresoc.v:57765.9-57765.17" + attribute \src "libresoc.v:58003.9-58003.17" case 1'1 case end @@ -99224,14 +99718,14 @@ module \dec$154 sync always update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] end - attribute \src "libresoc.v:57792.3-57819.6" - process $proc$libresoc.v:57792$3493 + attribute \src "libresoc.v:58030.3-58057.6" + process $proc$libresoc.v:58030$3505 assign { } { } assign { } { } assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57793.5-57793.29" + attribute \src "libresoc.v:58031.5-58031.29" switch \initial - attribute \src "libresoc.v:57793.9-57793.17" + attribute \src "libresoc.v:58031.9-58031.17" case 1'1 case end @@ -99271,14 +99765,14 @@ module \dec$154 sync always update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] end - attribute \src "libresoc.v:57820.3-57847.6" - process $proc$libresoc.v:57820$3494 + attribute \src "libresoc.v:58058.3-58085.6" + process $proc$libresoc.v:58058$3506 assign { } { } assign { } { } assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57821.5-57821.29" + attribute \src "libresoc.v:58059.5-58059.29" switch \initial - attribute \src "libresoc.v:57821.9-57821.17" + attribute \src "libresoc.v:58059.9-58059.17" case 1'1 case end @@ -99318,14 +99812,14 @@ module \dec$154 sync always update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] end - attribute \src "libresoc.v:57848.3-57875.6" - process $proc$libresoc.v:57848$3495 + attribute \src "libresoc.v:58086.3-58113.6" + process $proc$libresoc.v:58086$3507 assign { } { } assign { } { } assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57849.5-57849.29" + attribute \src "libresoc.v:58087.5-58087.29" switch \initial - attribute \src "libresoc.v:57849.9-57849.17" + attribute \src "libresoc.v:58087.9-58087.17" case 1'1 case end @@ -99365,14 +99859,14 @@ module \dec$154 sync always update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] end - attribute \src "libresoc.v:57876.3-57903.6" - process $proc$libresoc.v:57876$3496 + attribute \src "libresoc.v:58114.3-58141.6" + process $proc$libresoc.v:58114$3508 assign { } { } assign { } { } assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57877.5-57877.29" + attribute \src "libresoc.v:58115.5-58115.29" switch \initial - attribute \src "libresoc.v:57877.9-57877.17" + attribute \src "libresoc.v:58115.9-58115.17" case 1'1 case end @@ -99412,14 +99906,14 @@ module \dec$154 sync always update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] end - attribute \src "libresoc.v:57904.3-57931.6" - process $proc$libresoc.v:57904$3497 + attribute \src "libresoc.v:58142.3-58169.6" + process $proc$libresoc.v:58142$3509 assign { } { } assign { } { } assign $0\LOGICAL_function_unit[12:0] $1\LOGICAL_function_unit[12:0] - attribute \src "libresoc.v:57905.5-57905.29" + attribute \src "libresoc.v:58143.5-58143.29" switch \initial - attribute \src "libresoc.v:57905.9-57905.17" + attribute \src "libresoc.v:58143.9-58143.17" case 1'1 case end @@ -99459,14 +99953,14 @@ module \dec$154 sync always update \LOGICAL_function_unit $0\LOGICAL_function_unit[12:0] end - attribute \src "libresoc.v:57932.3-57959.6" - process $proc$libresoc.v:57932$3498 + attribute \src "libresoc.v:58170.3-58197.6" + process $proc$libresoc.v:58170$3510 assign { } { } assign { } { } assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57933.5-57933.29" + attribute \src "libresoc.v:58171.5-58171.29" switch \initial - attribute \src "libresoc.v:57933.9-57933.17" + attribute \src "libresoc.v:58171.9-58171.17" case 1'1 case end @@ -99506,14 +100000,14 @@ module \dec$154 sync always update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] end - attribute \src "libresoc.v:57960.3-57987.6" - process $proc$libresoc.v:57960$3499 + attribute \src "libresoc.v:58198.3-58225.6" + process $proc$libresoc.v:58198$3511 assign { } { } assign { } { } assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57961.5-57961.29" + attribute \src "libresoc.v:58199.5-58199.29" switch \initial - attribute \src "libresoc.v:57961.9-57961.17" + attribute \src "libresoc.v:58199.9-58199.17" case 1'1 case end @@ -99553,14 +100047,14 @@ module \dec$154 sync always update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] end - attribute \src "libresoc.v:57988.3-58015.6" - process $proc$libresoc.v:57988$3500 + attribute \src "libresoc.v:58226.3-58253.6" + process $proc$libresoc.v:58226$3512 assign { } { } assign { } { } assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57989.5-57989.29" + attribute \src "libresoc.v:58227.5-58227.29" switch \initial - attribute \src "libresoc.v:57989.9-57989.17" + attribute \src "libresoc.v:58227.9-58227.17" case 1'1 case end @@ -99600,14 +100094,14 @@ module \dec$154 sync always update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] end - attribute \src "libresoc.v:58016.3-58043.6" - process $proc$libresoc.v:58016$3501 + attribute \src "libresoc.v:58254.3-58281.6" + process $proc$libresoc.v:58254$3513 assign { } { } assign { } { } assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:58017.5-58017.29" + attribute \src "libresoc.v:58255.5-58255.29" switch \initial - attribute \src "libresoc.v:58017.9-58017.17" + attribute \src "libresoc.v:58255.9-58255.17" case 1'1 case end @@ -99647,14 +100141,14 @@ module \dec$154 sync always update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] end - attribute \src "libresoc.v:58044.3-58071.6" - process $proc$libresoc.v:58044$3502 + attribute \src "libresoc.v:58282.3-58309.6" + process $proc$libresoc.v:58282$3514 assign { } { } assign { } { } assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:58045.5-58045.29" + attribute \src "libresoc.v:58283.5-58283.29" switch \initial - attribute \src "libresoc.v:58045.9-58045.17" + attribute \src "libresoc.v:58283.9-58283.17" case 1'1 case end @@ -99694,14 +100188,14 @@ module \dec$154 sync always update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] end - attribute \src "libresoc.v:58072.3-58099.6" - process $proc$libresoc.v:58072$3503 + attribute \src "libresoc.v:58310.3-58337.6" + process $proc$libresoc.v:58310$3515 assign { } { } assign { } { } assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58073.5-58073.29" + attribute \src "libresoc.v:58311.5-58311.29" switch \initial - attribute \src "libresoc.v:58073.9-58073.17" + attribute \src "libresoc.v:58311.9-58311.17" case 1'1 case end @@ -99741,14 +100235,14 @@ module \dec$154 sync always update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] end - attribute \src "libresoc.v:58100.3-58127.6" - process $proc$libresoc.v:58100$3504 + attribute \src "libresoc.v:58338.3-58365.6" + process $proc$libresoc.v:58338$3516 assign { } { } assign { } { } assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:58101.5-58101.29" + attribute \src "libresoc.v:58339.5-58339.29" switch \initial - attribute \src "libresoc.v:58101.9-58101.17" + attribute \src "libresoc.v:58339.9-58339.17" case 1'1 case end @@ -99788,7 +100282,7 @@ module \dec$154 sync always update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:57718$3490_Y + connect \$1 $ternary$libresoc.v:57956$3502_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -100126,39 +100620,39 @@ module \dec$154 connect \LOGICAL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:58468.1-59800.10" +attribute \src "libresoc.v:58706.1-60037.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" attribute \generator "nMigen" -module \dec$163 - attribute \src "libresoc.v:59424.3-59433.6" +module \dec$150 + attribute \src "libresoc.v:59661.3-59670.6" wire width 3 $0\SPR_cr_in[2:0] - attribute \src "libresoc.v:59434.3-59443.6" + attribute \src "libresoc.v:59671.3-59680.6" wire width 3 $0\SPR_cr_out[2:0] - attribute \src "libresoc.v:59404.3-59413.6" + attribute \src "libresoc.v:59641.3-59650.6" wire width 13 $0\SPR_function_unit[12:0] - attribute \src "libresoc.v:59414.3-59423.6" + attribute \src "libresoc.v:59651.3-59660.6" wire width 7 $0\SPR_internal_op[6:0] - attribute \src "libresoc.v:59454.3-59463.6" + attribute \src "libresoc.v:59691.3-59700.6" wire $0\SPR_is_32b[0:0] - attribute \src "libresoc.v:59444.3-59453.6" + attribute \src "libresoc.v:59681.3-59690.6" wire width 2 $0\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58469.7-58469.20" + attribute \src "libresoc.v:58707.7-58707.20" wire $0\initial[0:0] - attribute \src "libresoc.v:59424.3-59433.6" + attribute \src "libresoc.v:59661.3-59670.6" wire width 3 $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59434.3-59443.6" + attribute \src "libresoc.v:59671.3-59680.6" wire width 3 $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59404.3-59413.6" + attribute \src "libresoc.v:59641.3-59650.6" wire width 13 $1\SPR_function_unit[12:0] - attribute \src "libresoc.v:59414.3-59423.6" + attribute \src "libresoc.v:59651.3-59660.6" wire width 7 $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59454.3-59463.6" + attribute \src "libresoc.v:59691.3-59700.6" wire $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59444.3-59453.6" + attribute \src "libresoc.v:59681.3-59690.6" wire width 2 $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59394.17-59394.211" - wire width 32 $ternary$libresoc.v:59394$3506_Y + attribute \src "libresoc.v:59631.17-59631.211" + wire width 32 $ternary$libresoc.v:59631$3518_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -100340,11 +100834,11 @@ module \dec$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \SPR_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 13 \SPR_BA + wire width 5 \SPR_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 12 \SPR_BB + wire width 5 \SPR_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 17 \SPR_BC + wire width 5 \SPR_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \SPR_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -100352,11 +100846,11 @@ module \dec$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \SPR_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 16 \SPR_BI + wire width 5 \SPR_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 14 \SPR_BT + wire width 5 \SPR_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \SPR_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -100364,7 +100858,7 @@ module \dec$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \SPR_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 output 15 \SPR_FXM + wire width 8 \SPR_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \SPR_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -100380,7 +100874,7 @@ module \dec$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 11 \SPR_OE + wire output 10 \SPR_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -100390,7 +100884,7 @@ module \dec$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 10 \SPR_Rc + wire output 9 \SPR_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -100398,7 +100892,7 @@ module \dec$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \SPR_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 10 output 7 \SPR_SPR + wire width 10 output 5 \SPR_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SPR_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -100413,7 +100907,7 @@ module \dec$163 attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 4 \SPR_cr_in + wire width 3 \SPR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -100422,7 +100916,7 @@ module \dec$163 attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 5 \SPR_cr_out + wire width 3 output 7 \SPR_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -100560,7 +101054,7 @@ module \dec$163 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 8 \SPR_function_unit + wire width 13 output 6 \SPR_function_unit attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100636,9 +101130,9 @@ module \dec$163 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 output 6 \SPR_internal_op + wire width 7 output 4 \SPR_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 9 \SPR_is_32b + wire output 8 \SPR_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -100772,7 +101266,7 @@ module \dec$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 output 20 \XL_BT + wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -100900,9 +101394,9 @@ module \dec$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 18 \X_BF + wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 19 \X_BFA + wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -101071,24 +101565,24 @@ module \dec$163 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:58469.7-58469.15" + attribute \src "libresoc.v:58707.7-58707.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 21 \raw_opcode_in + wire width 32 input 11 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:59394$3506 + cell $mux $ternary$libresoc.v:59631$3518 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:59394$3506_Y + connect \Y $ternary$libresoc.v:59631$3518_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:59395.13-59403.4" + attribute \src "libresoc.v:59632.13-59640.4" cell \SPR_dec31 \SPR_dec31 connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out @@ -101098,22 +101592,22 @@ module \dec$163 connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel connect \opcode_in \SPR_dec31_opcode_in end - attribute \src "libresoc.v:58469.7-58469.20" - process $proc$libresoc.v:58469$3513 + attribute \src "libresoc.v:58707.7-58707.20" + process $proc$libresoc.v:58707$3525 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:59404.3-59413.6" - process $proc$libresoc.v:59404$3507 + attribute \src "libresoc.v:59641.3-59650.6" + process $proc$libresoc.v:59641$3519 assign { } { } assign { } { } assign $0\SPR_function_unit[12:0] $1\SPR_function_unit[12:0] - attribute \src "libresoc.v:59405.5-59405.29" + attribute \src "libresoc.v:59642.5-59642.29" switch \initial - attribute \src "libresoc.v:59405.9-59405.17" + attribute \src "libresoc.v:59642.9-59642.17" case 1'1 case end @@ -101129,14 +101623,14 @@ module \dec$163 sync always update \SPR_function_unit $0\SPR_function_unit[12:0] end - attribute \src "libresoc.v:59414.3-59423.6" - process $proc$libresoc.v:59414$3508 + attribute \src "libresoc.v:59651.3-59660.6" + process $proc$libresoc.v:59651$3520 assign { } { } assign { } { } assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59415.5-59415.29" + attribute \src "libresoc.v:59652.5-59652.29" switch \initial - attribute \src "libresoc.v:59415.9-59415.17" + attribute \src "libresoc.v:59652.9-59652.17" case 1'1 case end @@ -101152,14 +101646,14 @@ module \dec$163 sync always update \SPR_internal_op $0\SPR_internal_op[6:0] end - attribute \src "libresoc.v:59424.3-59433.6" - process $proc$libresoc.v:59424$3509 + attribute \src "libresoc.v:59661.3-59670.6" + process $proc$libresoc.v:59661$3521 assign { } { } assign { } { } assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59425.5-59425.29" + attribute \src "libresoc.v:59662.5-59662.29" switch \initial - attribute \src "libresoc.v:59425.9-59425.17" + attribute \src "libresoc.v:59662.9-59662.17" case 1'1 case end @@ -101175,14 +101669,14 @@ module \dec$163 sync always update \SPR_cr_in $0\SPR_cr_in[2:0] end - attribute \src "libresoc.v:59434.3-59443.6" - process $proc$libresoc.v:59434$3510 + attribute \src "libresoc.v:59671.3-59680.6" + process $proc$libresoc.v:59671$3522 assign { } { } assign { } { } assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59435.5-59435.29" + attribute \src "libresoc.v:59672.5-59672.29" switch \initial - attribute \src "libresoc.v:59435.9-59435.17" + attribute \src "libresoc.v:59672.9-59672.17" case 1'1 case end @@ -101198,14 +101692,14 @@ module \dec$163 sync always update \SPR_cr_out $0\SPR_cr_out[2:0] end - attribute \src "libresoc.v:59444.3-59453.6" - process $proc$libresoc.v:59444$3511 + attribute \src "libresoc.v:59681.3-59690.6" + process $proc$libresoc.v:59681$3523 assign { } { } assign { } { } assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59445.5-59445.29" + attribute \src "libresoc.v:59682.5-59682.29" switch \initial - attribute \src "libresoc.v:59445.9-59445.17" + attribute \src "libresoc.v:59682.9-59682.17" case 1'1 case end @@ -101221,14 +101715,14 @@ module \dec$163 sync always update \SPR_rc_sel $0\SPR_rc_sel[1:0] end - attribute \src "libresoc.v:59454.3-59463.6" - process $proc$libresoc.v:59454$3512 + attribute \src "libresoc.v:59691.3-59700.6" + process $proc$libresoc.v:59691$3524 assign { } { } assign { } { } assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59455.5-59455.29" + attribute \src "libresoc.v:59692.5-59692.29" switch \initial - attribute \src "libresoc.v:59455.9-59455.17" + attribute \src "libresoc.v:59692.9-59692.17" case 1'1 case end @@ -101244,7 +101738,7 @@ module \dec$163 sync always update \SPR_is_32b $0\SPR_is_32b[0:0] end - connect \$1 $ternary$libresoc.v:59394$3506_Y + connect \$1 $ternary$libresoc.v:59631$3518_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -101582,71 +102076,71 @@ module \dec$163 connect \SPR_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:59804.1-61326.10" +attribute \src "libresoc.v:60041.1-61562.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" attribute \generator "nMigen" -module \dec$170 - attribute \src "libresoc.v:60950.3-60959.6" +module \dec$153 + attribute \src "libresoc.v:61186.3-61195.6" wire width 3 $0\DIV_cr_in[2:0] - attribute \src "libresoc.v:60960.3-60969.6" + attribute \src "libresoc.v:61196.3-61205.6" wire width 3 $0\DIV_cr_out[2:0] - attribute \src "libresoc.v:60850.3-60859.6" + attribute \src "libresoc.v:61086.3-61095.6" wire width 2 $0\DIV_cry_in[1:0] - attribute \src "libresoc.v:60880.3-60889.6" + attribute \src "libresoc.v:61116.3-61125.6" wire $0\DIV_cry_out[0:0] - attribute \src "libresoc.v:60910.3-60919.6" + attribute \src "libresoc.v:61146.3-61155.6" wire width 13 $0\DIV_function_unit[12:0] - attribute \src "libresoc.v:60930.3-60939.6" + attribute \src "libresoc.v:61166.3-61175.6" wire width 3 $0\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60940.3-60949.6" + attribute \src "libresoc.v:61176.3-61185.6" wire width 4 $0\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60920.3-60929.6" + attribute \src "libresoc.v:61156.3-61165.6" wire width 7 $0\DIV_internal_op[6:0] - attribute \src "libresoc.v:60860.3-60869.6" + attribute \src "libresoc.v:61096.3-61105.6" wire $0\DIV_inv_a[0:0] - attribute \src "libresoc.v:60870.3-60879.6" + attribute \src "libresoc.v:61106.3-61115.6" wire $0\DIV_inv_out[0:0] - attribute \src "libresoc.v:60890.3-60899.6" + attribute \src "libresoc.v:61126.3-61135.6" wire $0\DIV_is_32b[0:0] - attribute \src "libresoc.v:60970.3-60979.6" + attribute \src "libresoc.v:61206.3-61215.6" wire width 4 $0\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60980.3-60989.6" + attribute \src "libresoc.v:61216.3-61225.6" wire width 2 $0\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60900.3-60909.6" + attribute \src "libresoc.v:61136.3-61145.6" wire $0\DIV_sgn[0:0] - attribute \src "libresoc.v:59805.7-59805.20" + attribute \src "libresoc.v:60042.7-60042.20" wire $0\initial[0:0] - attribute \src "libresoc.v:60950.3-60959.6" + attribute \src "libresoc.v:61186.3-61195.6" wire width 3 $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60960.3-60969.6" + attribute \src "libresoc.v:61196.3-61205.6" wire width 3 $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60850.3-60859.6" + attribute \src "libresoc.v:61086.3-61095.6" wire width 2 $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60880.3-60889.6" + attribute \src "libresoc.v:61116.3-61125.6" wire $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60910.3-60919.6" + attribute \src "libresoc.v:61146.3-61155.6" wire width 13 $1\DIV_function_unit[12:0] - attribute \src "libresoc.v:60930.3-60939.6" + attribute \src "libresoc.v:61166.3-61175.6" wire width 3 $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60940.3-60949.6" + attribute \src "libresoc.v:61176.3-61185.6" wire width 4 $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60920.3-60929.6" + attribute \src "libresoc.v:61156.3-61165.6" wire width 7 $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60860.3-60869.6" + attribute \src "libresoc.v:61096.3-61105.6" wire $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60870.3-60879.6" + attribute \src "libresoc.v:61106.3-61115.6" wire $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60890.3-60899.6" + attribute \src "libresoc.v:61126.3-61135.6" wire $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60970.3-60979.6" + attribute \src "libresoc.v:61206.3-61215.6" wire width 4 $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60980.3-60989.6" + attribute \src "libresoc.v:61216.3-61225.6" wire width 2 $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60900.3-60909.6" + attribute \src "libresoc.v:61136.3-61145.6" wire $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60832.17-60832.211" - wire width 32 $ternary$libresoc.v:60832$3514_Y + attribute \src "libresoc.v:61068.17-61068.211" + wire width 32 $ternary$libresoc.v:61068$3526_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -101682,35 +102176,35 @@ module \dec$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \DIV_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 28 \DIV_BA + wire width 5 \DIV_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 27 \DIV_BB + wire width 5 \DIV_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 33 \DIV_BC + wire width 5 \DIV_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 26 \DIV_BD + wire width 14 output 25 \DIV_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \DIV_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \DIV_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 31 \DIV_BI + wire width 5 \DIV_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 29 \DIV_BT + wire width 5 \DIV_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \DIV_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \DIV_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 32 \DIV_DS + wire width 14 output 26 \DIV_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 output 30 \DIV_FXM + wire width 8 \DIV_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \DIV_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 24 output 23 \DIV_LI + wire width 24 output 22 \DIV_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \DIV_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -101722,9 +102216,9 @@ module \dec$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 25 \DIV_OE + wire output 24 \DIV_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 18 \DIV_RA + wire width 5 output 17 \DIV_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -101732,19 +102226,19 @@ module \dec$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 24 \DIV_Rc + wire output 23 \DIV_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 21 \DIV_SH32 + wire width 5 output 20 \DIV_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 19 \DIV_SI + wire width 16 output 18 \DIV_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 10 output 7 \DIV_SPR + wire width 10 output 5 \DIV_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \DIV_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 20 \DIV_UI + wire width 16 output 19 \DIV_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -101755,7 +102249,7 @@ module \dec$170 attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 4 \DIV_cr_in + wire width 3 \DIV_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -101764,15 +102258,15 @@ module \dec$170 attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 5 \DIV_cr_out + wire width 3 output 9 \DIV_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 14 \DIV_cry_in + wire width 2 output 13 \DIV_cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 15 \DIV_cry_out + wire output 14 \DIV_cry_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -101957,7 +102451,7 @@ module \dec$170 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 8 \DIV_function_unit + wire width 13 output 6 \DIV_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -101965,7 +102459,7 @@ module \dec$170 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 9 \DIV_in1_sel + wire width 3 output 7 \DIV_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -101982,7 +102476,7 @@ module \dec$170 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 10 \DIV_in2_sel + wire width 4 output 8 \DIV_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -102058,13 +102552,13 @@ module \dec$170 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 output 6 \DIV_internal_op + wire width 7 output 4 \DIV_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 12 \DIV_inv_a + wire output 11 \DIV_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 13 \DIV_inv_out + wire output 12 \DIV_inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 16 \DIV_is_32b + wire output 15 \DIV_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -102072,7 +102566,7 @@ module \dec$170 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 11 \DIV_ldst_len + wire width 4 output 10 \DIV_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -102080,9 +102574,9 @@ module \dec$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \DIV_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 17 \DIV_sgn + wire output 16 \DIV_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 6 output 22 \DIV_sh + wire width 6 output 21 \DIV_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \DQE_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -102354,7 +102848,7 @@ module \dec$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 output 36 \XL_BT + wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -102482,9 +102976,9 @@ module \dec$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 34 \X_BF + wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 35 \X_BFA + wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -102653,24 +103147,24 @@ module \dec$170 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:59805.7-59805.15" + attribute \src "libresoc.v:60042.7-60042.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 37 \raw_opcode_in + wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:60832$3514 + cell $mux $ternary$libresoc.v:61068$3526 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:60832$3514_Y + connect \Y $ternary$libresoc.v:61068$3526_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:60833.13-60849.4" + attribute \src "libresoc.v:61069.13-61085.4" cell \DIV_dec31 \DIV_dec31 connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out @@ -102688,22 +103182,22 @@ module \dec$170 connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn connect \opcode_in \DIV_dec31_opcode_in end - attribute \src "libresoc.v:59805.7-59805.20" - process $proc$libresoc.v:59805$3529 + attribute \src "libresoc.v:60042.7-60042.20" + process $proc$libresoc.v:60042$3541 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:60850.3-60859.6" - process $proc$libresoc.v:60850$3515 + attribute \src "libresoc.v:61086.3-61095.6" + process $proc$libresoc.v:61086$3527 assign { } { } assign { } { } assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60851.5-60851.29" + attribute \src "libresoc.v:61087.5-61087.29" switch \initial - attribute \src "libresoc.v:60851.9-60851.17" + attribute \src "libresoc.v:61087.9-61087.17" case 1'1 case end @@ -102719,14 +103213,14 @@ module \dec$170 sync always update \DIV_cry_in $0\DIV_cry_in[1:0] end - attribute \src "libresoc.v:60860.3-60869.6" - process $proc$libresoc.v:60860$3516 + attribute \src "libresoc.v:61096.3-61105.6" + process $proc$libresoc.v:61096$3528 assign { } { } assign { } { } assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60861.5-60861.29" + attribute \src "libresoc.v:61097.5-61097.29" switch \initial - attribute \src "libresoc.v:60861.9-60861.17" + attribute \src "libresoc.v:61097.9-61097.17" case 1'1 case end @@ -102742,14 +103236,14 @@ module \dec$170 sync always update \DIV_inv_a $0\DIV_inv_a[0:0] end - attribute \src "libresoc.v:60870.3-60879.6" - process $proc$libresoc.v:60870$3517 + attribute \src "libresoc.v:61106.3-61115.6" + process $proc$libresoc.v:61106$3529 assign { } { } assign { } { } assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60871.5-60871.29" + attribute \src "libresoc.v:61107.5-61107.29" switch \initial - attribute \src "libresoc.v:60871.9-60871.17" + attribute \src "libresoc.v:61107.9-61107.17" case 1'1 case end @@ -102765,14 +103259,14 @@ module \dec$170 sync always update \DIV_inv_out $0\DIV_inv_out[0:0] end - attribute \src "libresoc.v:60880.3-60889.6" - process $proc$libresoc.v:60880$3518 + attribute \src "libresoc.v:61116.3-61125.6" + process $proc$libresoc.v:61116$3530 assign { } { } assign { } { } assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60881.5-60881.29" + attribute \src "libresoc.v:61117.5-61117.29" switch \initial - attribute \src "libresoc.v:60881.9-60881.17" + attribute \src "libresoc.v:61117.9-61117.17" case 1'1 case end @@ -102788,14 +103282,14 @@ module \dec$170 sync always update \DIV_cry_out $0\DIV_cry_out[0:0] end - attribute \src "libresoc.v:60890.3-60899.6" - process $proc$libresoc.v:60890$3519 + attribute \src "libresoc.v:61126.3-61135.6" + process $proc$libresoc.v:61126$3531 assign { } { } assign { } { } assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60891.5-60891.29" + attribute \src "libresoc.v:61127.5-61127.29" switch \initial - attribute \src "libresoc.v:60891.9-60891.17" + attribute \src "libresoc.v:61127.9-61127.17" case 1'1 case end @@ -102811,14 +103305,14 @@ module \dec$170 sync always update \DIV_is_32b $0\DIV_is_32b[0:0] end - attribute \src "libresoc.v:60900.3-60909.6" - process $proc$libresoc.v:60900$3520 + attribute \src "libresoc.v:61136.3-61145.6" + process $proc$libresoc.v:61136$3532 assign { } { } assign { } { } assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60901.5-60901.29" + attribute \src "libresoc.v:61137.5-61137.29" switch \initial - attribute \src "libresoc.v:60901.9-60901.17" + attribute \src "libresoc.v:61137.9-61137.17" case 1'1 case end @@ -102834,14 +103328,14 @@ module \dec$170 sync always update \DIV_sgn $0\DIV_sgn[0:0] end - attribute \src "libresoc.v:60910.3-60919.6" - process $proc$libresoc.v:60910$3521 + attribute \src "libresoc.v:61146.3-61155.6" + process $proc$libresoc.v:61146$3533 assign { } { } assign { } { } assign $0\DIV_function_unit[12:0] $1\DIV_function_unit[12:0] - attribute \src "libresoc.v:60911.5-60911.29" + attribute \src "libresoc.v:61147.5-61147.29" switch \initial - attribute \src "libresoc.v:60911.9-60911.17" + attribute \src "libresoc.v:61147.9-61147.17" case 1'1 case end @@ -102857,14 +103351,14 @@ module \dec$170 sync always update \DIV_function_unit $0\DIV_function_unit[12:0] end - attribute \src "libresoc.v:60920.3-60929.6" - process $proc$libresoc.v:60920$3522 + attribute \src "libresoc.v:61156.3-61165.6" + process $proc$libresoc.v:61156$3534 assign { } { } assign { } { } assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60921.5-60921.29" + attribute \src "libresoc.v:61157.5-61157.29" switch \initial - attribute \src "libresoc.v:60921.9-60921.17" + attribute \src "libresoc.v:61157.9-61157.17" case 1'1 case end @@ -102880,14 +103374,14 @@ module \dec$170 sync always update \DIV_internal_op $0\DIV_internal_op[6:0] end - attribute \src "libresoc.v:60930.3-60939.6" - process $proc$libresoc.v:60930$3523 + attribute \src "libresoc.v:61166.3-61175.6" + process $proc$libresoc.v:61166$3535 assign { } { } assign { } { } assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60931.5-60931.29" + attribute \src "libresoc.v:61167.5-61167.29" switch \initial - attribute \src "libresoc.v:60931.9-60931.17" + attribute \src "libresoc.v:61167.9-61167.17" case 1'1 case end @@ -102903,14 +103397,14 @@ module \dec$170 sync always update \DIV_in1_sel $0\DIV_in1_sel[2:0] end - attribute \src "libresoc.v:60940.3-60949.6" - process $proc$libresoc.v:60940$3524 + attribute \src "libresoc.v:61176.3-61185.6" + process $proc$libresoc.v:61176$3536 assign { } { } assign { } { } assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60941.5-60941.29" + attribute \src "libresoc.v:61177.5-61177.29" switch \initial - attribute \src "libresoc.v:60941.9-60941.17" + attribute \src "libresoc.v:61177.9-61177.17" case 1'1 case end @@ -102926,14 +103420,14 @@ module \dec$170 sync always update \DIV_in2_sel $0\DIV_in2_sel[3:0] end - attribute \src "libresoc.v:60950.3-60959.6" - process $proc$libresoc.v:60950$3525 + attribute \src "libresoc.v:61186.3-61195.6" + process $proc$libresoc.v:61186$3537 assign { } { } assign { } { } assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60951.5-60951.29" + attribute \src "libresoc.v:61187.5-61187.29" switch \initial - attribute \src "libresoc.v:60951.9-60951.17" + attribute \src "libresoc.v:61187.9-61187.17" case 1'1 case end @@ -102949,14 +103443,14 @@ module \dec$170 sync always update \DIV_cr_in $0\DIV_cr_in[2:0] end - attribute \src "libresoc.v:60960.3-60969.6" - process $proc$libresoc.v:60960$3526 + attribute \src "libresoc.v:61196.3-61205.6" + process $proc$libresoc.v:61196$3538 assign { } { } assign { } { } assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60961.5-60961.29" + attribute \src "libresoc.v:61197.5-61197.29" switch \initial - attribute \src "libresoc.v:60961.9-60961.17" + attribute \src "libresoc.v:61197.9-61197.17" case 1'1 case end @@ -102972,14 +103466,14 @@ module \dec$170 sync always update \DIV_cr_out $0\DIV_cr_out[2:0] end - attribute \src "libresoc.v:60970.3-60979.6" - process $proc$libresoc.v:60970$3527 + attribute \src "libresoc.v:61206.3-61215.6" + process $proc$libresoc.v:61206$3539 assign { } { } assign { } { } assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60971.5-60971.29" + attribute \src "libresoc.v:61207.5-61207.29" switch \initial - attribute \src "libresoc.v:60971.9-60971.17" + attribute \src "libresoc.v:61207.9-61207.17" case 1'1 case end @@ -102995,14 +103489,14 @@ module \dec$170 sync always update \DIV_ldst_len $0\DIV_ldst_len[3:0] end - attribute \src "libresoc.v:60980.3-60989.6" - process $proc$libresoc.v:60980$3528 + attribute \src "libresoc.v:61216.3-61225.6" + process $proc$libresoc.v:61216$3540 assign { } { } assign { } { } assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60981.5-60981.29" + attribute \src "libresoc.v:61217.5-61217.29" switch \initial - attribute \src "libresoc.v:60981.9-60981.17" + attribute \src "libresoc.v:61217.9-61217.17" case 1'1 case end @@ -103018,7 +103512,7 @@ module \dec$170 sync always update \DIV_rc_sel $0\DIV_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:60832$3514_Y + connect \$1 $ternary$libresoc.v:61068$3526_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -103356,47 +103850,47 @@ module \dec$170 connect \DIV_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:61330.1-62748.10" +attribute \src "libresoc.v:61566.1-62983.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" attribute \generator "nMigen" -module \dec$179 - attribute \src "libresoc.v:62347.3-62359.6" +module \dec$158 + attribute \src "libresoc.v:62582.3-62594.6" wire width 3 $0\MUL_cr_in[2:0] - attribute \src "libresoc.v:62360.3-62372.6" + attribute \src "libresoc.v:62595.3-62607.6" wire width 3 $0\MUL_cr_out[2:0] - attribute \src "libresoc.v:62308.3-62320.6" + attribute \src "libresoc.v:62543.3-62555.6" wire width 13 $0\MUL_function_unit[12:0] - attribute \src "libresoc.v:62334.3-62346.6" + attribute \src "libresoc.v:62569.3-62581.6" wire width 4 $0\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62321.3-62333.6" + attribute \src "libresoc.v:62556.3-62568.6" wire width 7 $0\MUL_internal_op[6:0] - attribute \src "libresoc.v:62386.3-62398.6" + attribute \src "libresoc.v:62621.3-62633.6" wire $0\MUL_is_32b[0:0] - attribute \src "libresoc.v:62373.3-62385.6" + attribute \src "libresoc.v:62608.3-62620.6" wire width 2 $0\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62399.3-62411.6" + attribute \src "libresoc.v:62634.3-62646.6" wire $0\MUL_sgn[0:0] - attribute \src "libresoc.v:61331.7-61331.20" + attribute \src "libresoc.v:61567.7-61567.20" wire $0\initial[0:0] - attribute \src "libresoc.v:62347.3-62359.6" + attribute \src "libresoc.v:62582.3-62594.6" wire width 3 $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62360.3-62372.6" + attribute \src "libresoc.v:62595.3-62607.6" wire width 3 $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62308.3-62320.6" + attribute \src "libresoc.v:62543.3-62555.6" wire width 13 $1\MUL_function_unit[12:0] - attribute \src "libresoc.v:62334.3-62346.6" + attribute \src "libresoc.v:62569.3-62581.6" wire width 4 $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62321.3-62333.6" + attribute \src "libresoc.v:62556.3-62568.6" wire width 7 $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62386.3-62398.6" + attribute \src "libresoc.v:62621.3-62633.6" wire $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62373.3-62385.6" + attribute \src "libresoc.v:62608.3-62620.6" wire width 2 $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62399.3-62411.6" + attribute \src "libresoc.v:62634.3-62646.6" wire $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62296.17-62296.211" - wire width 32 $ternary$libresoc.v:62296$3530_Y + attribute \src "libresoc.v:62531.17-62531.211" + wire width 32 $ternary$libresoc.v:62531$3542_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -103558,35 +104052,35 @@ module \dec$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \MUL_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 21 \MUL_BA + wire width 5 \MUL_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 20 \MUL_BB + wire width 5 \MUL_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 26 \MUL_BC + wire width 5 \MUL_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 19 \MUL_BD + wire width 14 output 18 \MUL_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \MUL_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \MUL_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 24 \MUL_BI + wire width 5 \MUL_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 22 \MUL_BT + wire width 5 \MUL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \MUL_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \MUL_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 25 \MUL_DS + wire width 14 output 19 \MUL_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 output 23 \MUL_FXM + wire width 8 \MUL_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \MUL_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 24 output 16 \MUL_LI + wire width 24 output 15 \MUL_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \MUL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -103598,7 +104092,7 @@ module \dec$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 18 \MUL_OE + wire output 17 \MUL_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -103608,19 +104102,19 @@ module \dec$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 17 \MUL_Rc + wire output 16 \MUL_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 14 \MUL_SH32 + wire width 5 output 13 \MUL_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 12 \MUL_SI + wire width 16 output 11 \MUL_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 10 output 7 \MUL_SPR + wire width 10 output 5 \MUL_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MUL_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 13 \MUL_UI + wire width 16 output 12 \MUL_UI attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -103631,7 +104125,7 @@ module \dec$179 attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 4 \MUL_cr_in + wire width 3 \MUL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -103640,7 +104134,7 @@ module \dec$179 attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 5 \MUL_cr_out + wire width 3 output 8 \MUL_cr_out attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -103797,7 +104291,7 @@ module \dec$179 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 8 \MUL_function_unit + wire width 13 output 6 \MUL_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -103814,7 +104308,7 @@ module \dec$179 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 9 \MUL_in2_sel + wire width 4 output 7 \MUL_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -103890,9 +104384,9 @@ module \dec$179 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 output 6 \MUL_internal_op + wire width 7 output 4 \MUL_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 10 \MUL_is_32b + wire output 9 \MUL_is_32b attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -103900,9 +104394,9 @@ module \dec$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \MUL_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 11 \MUL_sgn + wire output 10 \MUL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 6 output 15 \MUL_sh + wire width 6 output 14 \MUL_sh attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \M_MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -104048,7 +104542,7 @@ module \dec$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 output 29 \XL_BT + wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -104176,9 +104670,9 @@ module \dec$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 27 \X_BF + wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 28 \X_BFA + wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -104347,24 +104841,24 @@ module \dec$179 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:61331.7-61331.15" + attribute \src "libresoc.v:61567.7-61567.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 30 \raw_opcode_in + wire width 32 input 20 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:62296$3530 + cell $mux $ternary$libresoc.v:62531$3542 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:62296$3530_Y + connect \Y $ternary$libresoc.v:62531$3542_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:62297.13-62307.4" + attribute \src "libresoc.v:62532.13-62542.4" cell \MUL_dec31 \MUL_dec31 connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out @@ -104376,22 +104870,22 @@ module \dec$179 connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn connect \opcode_in \MUL_dec31_opcode_in end - attribute \src "libresoc.v:61331.7-61331.20" - process $proc$libresoc.v:61331$3539 + attribute \src "libresoc.v:61567.7-61567.20" + process $proc$libresoc.v:61567$3551 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:62308.3-62320.6" - process $proc$libresoc.v:62308$3531 + attribute \src "libresoc.v:62543.3-62555.6" + process $proc$libresoc.v:62543$3543 assign { } { } assign { } { } assign $0\MUL_function_unit[12:0] $1\MUL_function_unit[12:0] - attribute \src "libresoc.v:62309.5-62309.29" + attribute \src "libresoc.v:62544.5-62544.29" switch \initial - attribute \src "libresoc.v:62309.9-62309.17" + attribute \src "libresoc.v:62544.9-62544.17" case 1'1 case end @@ -104411,14 +104905,14 @@ module \dec$179 sync always update \MUL_function_unit $0\MUL_function_unit[12:0] end - attribute \src "libresoc.v:62321.3-62333.6" - process $proc$libresoc.v:62321$3532 + attribute \src "libresoc.v:62556.3-62568.6" + process $proc$libresoc.v:62556$3544 assign { } { } assign { } { } assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62322.5-62322.29" + attribute \src "libresoc.v:62557.5-62557.29" switch \initial - attribute \src "libresoc.v:62322.9-62322.17" + attribute \src "libresoc.v:62557.9-62557.17" case 1'1 case end @@ -104438,14 +104932,14 @@ module \dec$179 sync always update \MUL_internal_op $0\MUL_internal_op[6:0] end - attribute \src "libresoc.v:62334.3-62346.6" - process $proc$libresoc.v:62334$3533 + attribute \src "libresoc.v:62569.3-62581.6" + process $proc$libresoc.v:62569$3545 assign { } { } assign { } { } assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62335.5-62335.29" + attribute \src "libresoc.v:62570.5-62570.29" switch \initial - attribute \src "libresoc.v:62335.9-62335.17" + attribute \src "libresoc.v:62570.9-62570.17" case 1'1 case end @@ -104465,14 +104959,14 @@ module \dec$179 sync always update \MUL_in2_sel $0\MUL_in2_sel[3:0] end - attribute \src "libresoc.v:62347.3-62359.6" - process $proc$libresoc.v:62347$3534 + attribute \src "libresoc.v:62582.3-62594.6" + process $proc$libresoc.v:62582$3546 assign { } { } assign { } { } assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62348.5-62348.29" + attribute \src "libresoc.v:62583.5-62583.29" switch \initial - attribute \src "libresoc.v:62348.9-62348.17" + attribute \src "libresoc.v:62583.9-62583.17" case 1'1 case end @@ -104492,14 +104986,14 @@ module \dec$179 sync always update \MUL_cr_in $0\MUL_cr_in[2:0] end - attribute \src "libresoc.v:62360.3-62372.6" - process $proc$libresoc.v:62360$3535 + attribute \src "libresoc.v:62595.3-62607.6" + process $proc$libresoc.v:62595$3547 assign { } { } assign { } { } assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62361.5-62361.29" + attribute \src "libresoc.v:62596.5-62596.29" switch \initial - attribute \src "libresoc.v:62361.9-62361.17" + attribute \src "libresoc.v:62596.9-62596.17" case 1'1 case end @@ -104519,14 +105013,14 @@ module \dec$179 sync always update \MUL_cr_out $0\MUL_cr_out[2:0] end - attribute \src "libresoc.v:62373.3-62385.6" - process $proc$libresoc.v:62373$3536 + attribute \src "libresoc.v:62608.3-62620.6" + process $proc$libresoc.v:62608$3548 assign { } { } assign { } { } assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62374.5-62374.29" + attribute \src "libresoc.v:62609.5-62609.29" switch \initial - attribute \src "libresoc.v:62374.9-62374.17" + attribute \src "libresoc.v:62609.9-62609.17" case 1'1 case end @@ -104546,14 +105040,14 @@ module \dec$179 sync always update \MUL_rc_sel $0\MUL_rc_sel[1:0] end - attribute \src "libresoc.v:62386.3-62398.6" - process $proc$libresoc.v:62386$3537 + attribute \src "libresoc.v:62621.3-62633.6" + process $proc$libresoc.v:62621$3549 assign { } { } assign { } { } assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62387.5-62387.29" + attribute \src "libresoc.v:62622.5-62622.29" switch \initial - attribute \src "libresoc.v:62387.9-62387.17" + attribute \src "libresoc.v:62622.9-62622.17" case 1'1 case end @@ -104573,14 +105067,14 @@ module \dec$179 sync always update \MUL_is_32b $0\MUL_is_32b[0:0] end - attribute \src "libresoc.v:62399.3-62411.6" - process $proc$libresoc.v:62399$3538 + attribute \src "libresoc.v:62634.3-62646.6" + process $proc$libresoc.v:62634$3550 assign { } { } assign { } { } assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62400.5-62400.29" + attribute \src "libresoc.v:62635.5-62635.29" switch \initial - attribute \src "libresoc.v:62400.9-62400.17" + attribute \src "libresoc.v:62635.9-62635.17" case 1'1 case end @@ -104600,7 +105094,7 @@ module \dec$179 sync always update \MUL_sgn $0\MUL_sgn[0:0] end - connect \$1 $ternary$libresoc.v:62296$3530_Y + connect \$1 $ternary$libresoc.v:62531$3542_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -104938,59 +105432,59 @@ module \dec$179 connect \MUL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:62752.1-64500.10" +attribute \src "libresoc.v:62987.1-64735.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" attribute \generator "nMigen" -module \dec$187 - attribute \src "libresoc.v:64075.3-64096.6" +module \dec$162 + attribute \src "libresoc.v:64310.3-64331.6" wire width 3 $0\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64097.3-64118.6" + attribute \src "libresoc.v:64332.3-64353.6" wire width 3 $0\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64141.3-64162.6" + attribute \src "libresoc.v:64376.3-64397.6" wire width 2 $0\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63943.3-63964.6" + attribute \src "libresoc.v:64178.3-64199.6" wire $0\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:64009.3-64030.6" + attribute \src "libresoc.v:64244.3-64265.6" wire width 13 $0\SHIFT_ROT_function_unit[12:0] - attribute \src "libresoc.v:64053.3-64074.6" + attribute \src "libresoc.v:64288.3-64309.6" wire width 4 $0\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:64031.3-64052.6" + attribute \src "libresoc.v:64266.3-64287.6" wire width 7 $0\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63921.3-63942.6" + attribute \src "libresoc.v:64156.3-64177.6" wire $0\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63965.3-63986.6" + attribute \src "libresoc.v:64200.3-64221.6" wire $0\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64119.3-64140.6" + attribute \src "libresoc.v:64354.3-64375.6" wire width 2 $0\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63987.3-64008.6" + attribute \src "libresoc.v:64222.3-64243.6" wire $0\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62753.7-62753.20" + attribute \src "libresoc.v:62988.7-62988.20" wire $0\initial[0:0] - attribute \src "libresoc.v:64075.3-64096.6" + attribute \src "libresoc.v:64310.3-64331.6" wire width 3 $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64097.3-64118.6" + attribute \src "libresoc.v:64332.3-64353.6" wire width 3 $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64141.3-64162.6" + attribute \src "libresoc.v:64376.3-64397.6" wire width 2 $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63943.3-63964.6" + attribute \src "libresoc.v:64178.3-64199.6" wire $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:64009.3-64030.6" + attribute \src "libresoc.v:64244.3-64265.6" wire width 13 $1\SHIFT_ROT_function_unit[12:0] - attribute \src "libresoc.v:64053.3-64074.6" + attribute \src "libresoc.v:64288.3-64309.6" wire width 4 $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:64031.3-64052.6" + attribute \src "libresoc.v:64266.3-64287.6" wire width 7 $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63921.3-63942.6" + attribute \src "libresoc.v:64156.3-64177.6" wire $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63965.3-63986.6" + attribute \src "libresoc.v:64200.3-64221.6" wire $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64119.3-64140.6" + attribute \src "libresoc.v:64354.3-64375.6" wire width 2 $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63987.3-64008.6" + attribute \src "libresoc.v:64222.3-64243.6" wire $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63892.17-63892.211" - wire width 32 $ternary$libresoc.v:63892$3540_Y + attribute \src "libresoc.v:64127.17-64127.211" + wire width 32 $ternary$libresoc.v:64127$3552_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -105172,11 +105666,11 @@ module \dec$187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \SHIFT_ROT_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 24 \SHIFT_ROT_BA + wire width 5 \SHIFT_ROT_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 23 \SHIFT_ROT_BB + wire width 5 \SHIFT_ROT_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 29 \SHIFT_ROT_BC + wire width 5 \SHIFT_ROT_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 output 22 \SHIFT_ROT_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -105184,19 +105678,19 @@ module \dec$187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \SHIFT_ROT_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 27 \SHIFT_ROT_BI + wire width 5 \SHIFT_ROT_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 25 \SHIFT_ROT_BT + wire width 5 \SHIFT_ROT_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \SHIFT_ROT_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \SHIFT_ROT_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 28 \SHIFT_ROT_DS + wire width 14 output 23 \SHIFT_ROT_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 output 26 \SHIFT_ROT_FXM + wire width 8 \SHIFT_ROT_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \SHIFT_ROT_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -105230,7 +105724,7 @@ module \dec$187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 output 15 \SHIFT_ROT_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 10 output 7 \SHIFT_ROT_SPR + wire width 10 output 5 \SHIFT_ROT_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \SHIFT_ROT_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -105245,7 +105739,7 @@ module \dec$187 attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 4 \SHIFT_ROT_cr_in + wire width 3 output 9 \SHIFT_ROT_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -105254,7 +105748,7 @@ module \dec$187 attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 5 \SHIFT_ROT_cr_out + wire width 3 output 8 \SHIFT_ROT_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -105580,7 +106074,7 @@ module \dec$187 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 8 \SHIFT_ROT_function_unit + wire width 13 output 6 \SHIFT_ROT_function_unit attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -105597,7 +106091,7 @@ module \dec$187 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 9 \SHIFT_ROT_in2_sel + wire width 4 output 7 \SHIFT_ROT_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -105673,7 +106167,7 @@ module \dec$187 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 output 6 \SHIFT_ROT_internal_op + wire width 7 output 4 \SHIFT_ROT_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire output 10 \SHIFT_ROT_inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" @@ -105813,7 +106307,7 @@ module \dec$187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 output 32 \XL_BT + wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -105941,9 +106435,9 @@ module \dec$187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 30 \X_BF + wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 31 \X_BFA + wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -106112,24 +106606,24 @@ module \dec$187 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:62753.7-62753.15" + attribute \src "libresoc.v:62988.7-62988.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 33 \raw_opcode_in + wire width 32 input 24 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:63892$3540 + cell $mux $ternary$libresoc.v:64127$3552 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:63892$3540_Y + connect \Y $ternary$libresoc.v:64127$3552_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:63893.19-63906.4" + attribute \src "libresoc.v:64128.19-64141.4" cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out @@ -106145,7 +106639,7 @@ module \dec$187 connect \opcode_in \SHIFT_ROT_dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:63907.19-63920.4" + attribute \src "libresoc.v:64142.19-64155.4" cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out @@ -106160,22 +106654,22 @@ module \dec$187 connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn connect \opcode_in \SHIFT_ROT_dec31_opcode_in end - attribute \src "libresoc.v:62753.7-62753.20" - process $proc$libresoc.v:62753$3552 + attribute \src "libresoc.v:62988.7-62988.20" + process $proc$libresoc.v:62988$3564 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:63921.3-63942.6" - process $proc$libresoc.v:63921$3541 + attribute \src "libresoc.v:64156.3-64177.6" + process $proc$libresoc.v:64156$3553 assign { } { } assign { } { } assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63922.5-63922.29" + attribute \src "libresoc.v:64157.5-64157.29" switch \initial - attribute \src "libresoc.v:63922.9-63922.17" + attribute \src "libresoc.v:64157.9-64157.17" case 1'1 case end @@ -106207,14 +106701,14 @@ module \dec$187 sync always update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] end - attribute \src "libresoc.v:63943.3-63964.6" - process $proc$libresoc.v:63943$3542 + attribute \src "libresoc.v:64178.3-64199.6" + process $proc$libresoc.v:64178$3554 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63944.5-63944.29" + attribute \src "libresoc.v:64179.5-64179.29" switch \initial - attribute \src "libresoc.v:63944.9-63944.17" + attribute \src "libresoc.v:64179.9-64179.17" case 1'1 case end @@ -106246,14 +106740,14 @@ module \dec$187 sync always update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] end - attribute \src "libresoc.v:63965.3-63986.6" - process $proc$libresoc.v:63965$3543 + attribute \src "libresoc.v:64200.3-64221.6" + process $proc$libresoc.v:64200$3555 assign { } { } assign { } { } assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63966.5-63966.29" + attribute \src "libresoc.v:64201.5-64201.29" switch \initial - attribute \src "libresoc.v:63966.9-63966.17" + attribute \src "libresoc.v:64201.9-64201.17" case 1'1 case end @@ -106285,14 +106779,14 @@ module \dec$187 sync always update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] end - attribute \src "libresoc.v:63987.3-64008.6" - process $proc$libresoc.v:63987$3544 + attribute \src "libresoc.v:64222.3-64243.6" + process $proc$libresoc.v:64222$3556 assign { } { } assign { } { } assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63988.5-63988.29" + attribute \src "libresoc.v:64223.5-64223.29" switch \initial - attribute \src "libresoc.v:63988.9-63988.17" + attribute \src "libresoc.v:64223.9-64223.17" case 1'1 case end @@ -106324,14 +106818,14 @@ module \dec$187 sync always update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] end - attribute \src "libresoc.v:64009.3-64030.6" - process $proc$libresoc.v:64009$3545 + attribute \src "libresoc.v:64244.3-64265.6" + process $proc$libresoc.v:64244$3557 assign { } { } assign { } { } assign $0\SHIFT_ROT_function_unit[12:0] $1\SHIFT_ROT_function_unit[12:0] - attribute \src "libresoc.v:64010.5-64010.29" + attribute \src "libresoc.v:64245.5-64245.29" switch \initial - attribute \src "libresoc.v:64010.9-64010.17" + attribute \src "libresoc.v:64245.9-64245.17" case 1'1 case end @@ -106363,14 +106857,14 @@ module \dec$187 sync always update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[12:0] end - attribute \src "libresoc.v:64031.3-64052.6" - process $proc$libresoc.v:64031$3546 + attribute \src "libresoc.v:64266.3-64287.6" + process $proc$libresoc.v:64266$3558 assign { } { } assign { } { } assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:64032.5-64032.29" + attribute \src "libresoc.v:64267.5-64267.29" switch \initial - attribute \src "libresoc.v:64032.9-64032.17" + attribute \src "libresoc.v:64267.9-64267.17" case 1'1 case end @@ -106402,14 +106896,14 @@ module \dec$187 sync always update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] end - attribute \src "libresoc.v:64053.3-64074.6" - process $proc$libresoc.v:64053$3547 + attribute \src "libresoc.v:64288.3-64309.6" + process $proc$libresoc.v:64288$3559 assign { } { } assign { } { } assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:64054.5-64054.29" + attribute \src "libresoc.v:64289.5-64289.29" switch \initial - attribute \src "libresoc.v:64054.9-64054.17" + attribute \src "libresoc.v:64289.9-64289.17" case 1'1 case end @@ -106441,14 +106935,14 @@ module \dec$187 sync always update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] end - attribute \src "libresoc.v:64075.3-64096.6" - process $proc$libresoc.v:64075$3548 + attribute \src "libresoc.v:64310.3-64331.6" + process $proc$libresoc.v:64310$3560 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64076.5-64076.29" + attribute \src "libresoc.v:64311.5-64311.29" switch \initial - attribute \src "libresoc.v:64076.9-64076.17" + attribute \src "libresoc.v:64311.9-64311.17" case 1'1 case end @@ -106480,14 +106974,14 @@ module \dec$187 sync always update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] end - attribute \src "libresoc.v:64097.3-64118.6" - process $proc$libresoc.v:64097$3549 + attribute \src "libresoc.v:64332.3-64353.6" + process $proc$libresoc.v:64332$3561 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64098.5-64098.29" + attribute \src "libresoc.v:64333.5-64333.29" switch \initial - attribute \src "libresoc.v:64098.9-64098.17" + attribute \src "libresoc.v:64333.9-64333.17" case 1'1 case end @@ -106519,14 +107013,14 @@ module \dec$187 sync always update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] end - attribute \src "libresoc.v:64119.3-64140.6" - process $proc$libresoc.v:64119$3550 + attribute \src "libresoc.v:64354.3-64375.6" + process $proc$libresoc.v:64354$3562 assign { } { } assign { } { } assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:64120.5-64120.29" + attribute \src "libresoc.v:64355.5-64355.29" switch \initial - attribute \src "libresoc.v:64120.9-64120.17" + attribute \src "libresoc.v:64355.9-64355.17" case 1'1 case end @@ -106558,14 +107052,14 @@ module \dec$187 sync always update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] end - attribute \src "libresoc.v:64141.3-64162.6" - process $proc$libresoc.v:64141$3551 + attribute \src "libresoc.v:64376.3-64397.6" + process $proc$libresoc.v:64376$3563 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:64142.5-64142.29" + attribute \src "libresoc.v:64377.5-64377.29" switch \initial - attribute \src "libresoc.v:64142.9-64142.17" + attribute \src "libresoc.v:64377.9-64377.17" case 1'1 case end @@ -106597,7 +107091,7 @@ module \dec$187 sync always update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] end - connect \$1 $ternary$libresoc.v:63892$3540_Y + connect \$1 $ternary$libresoc.v:64127$3552_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -106936,67 +107430,67 @@ module \dec$187 connect \SHIFT_ROT_dec30_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:64504.1-67006.10" +attribute \src "libresoc.v:64739.1-67240.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" attribute \generator "nMigen" -module \dec$195 - attribute \src "libresoc.v:66088.3-66145.6" +module \dec$166 + attribute \src "libresoc.v:66322.3-66379.6" wire $0\LDST_br[0:0] - attribute \src "libresoc.v:66552.3-66609.6" + attribute \src "libresoc.v:66786.3-66843.6" wire width 3 $0\LDST_cr_in[2:0] - attribute \src "libresoc.v:66610.3-66667.6" + attribute \src "libresoc.v:66844.3-66901.6" wire width 3 $0\LDST_cr_out[2:0] - attribute \src "libresoc.v:66320.3-66377.6" + attribute \src "libresoc.v:66554.3-66611.6" wire width 13 $0\LDST_function_unit[12:0] - attribute \src "libresoc.v:66436.3-66493.6" + attribute \src "libresoc.v:66670.3-66727.6" wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66494.3-66551.6" + attribute \src "libresoc.v:66728.3-66785.6" wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66378.3-66435.6" + attribute \src "libresoc.v:66612.3-66669.6" wire width 7 $0\LDST_internal_op[6:0] - attribute \src "libresoc.v:66204.3-66261.6" + attribute \src "libresoc.v:66438.3-66495.6" wire $0\LDST_is_32b[0:0] - attribute \src "libresoc.v:65914.3-65971.6" + attribute \src "libresoc.v:66148.3-66205.6" wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "libresoc.v:66030.3-66087.6" + attribute \src "libresoc.v:66264.3-66321.6" wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66262.3-66319.6" + attribute \src "libresoc.v:66496.3-66553.6" wire $0\LDST_sgn[0:0] - attribute \src "libresoc.v:66146.3-66203.6" + attribute \src "libresoc.v:66380.3-66437.6" wire $0\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65972.3-66029.6" + attribute \src "libresoc.v:66206.3-66263.6" wire width 2 $0\LDST_upd[1:0] - attribute \src "libresoc.v:64505.7-64505.20" + attribute \src "libresoc.v:64740.7-64740.20" wire $0\initial[0:0] - attribute \src "libresoc.v:66088.3-66145.6" + attribute \src "libresoc.v:66322.3-66379.6" wire $1\LDST_br[0:0] - attribute \src "libresoc.v:66552.3-66609.6" + attribute \src "libresoc.v:66786.3-66843.6" wire width 3 $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66610.3-66667.6" + attribute \src "libresoc.v:66844.3-66901.6" wire width 3 $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66320.3-66377.6" + attribute \src "libresoc.v:66554.3-66611.6" wire width 13 $1\LDST_function_unit[12:0] - attribute \src "libresoc.v:66436.3-66493.6" + attribute \src "libresoc.v:66670.3-66727.6" wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66494.3-66551.6" + attribute \src "libresoc.v:66728.3-66785.6" wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66378.3-66435.6" + attribute \src "libresoc.v:66612.3-66669.6" wire width 7 $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66204.3-66261.6" + attribute \src "libresoc.v:66438.3-66495.6" wire $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:65914.3-65971.6" + attribute \src "libresoc.v:66148.3-66205.6" wire width 4 $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:66030.3-66087.6" + attribute \src "libresoc.v:66264.3-66321.6" wire width 2 $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66262.3-66319.6" + attribute \src "libresoc.v:66496.3-66553.6" wire $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66146.3-66203.6" + attribute \src "libresoc.v:66380.3-66437.6" wire $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65972.3-66029.6" + attribute \src "libresoc.v:66206.3-66263.6" wire width 2 $1\LDST_upd[1:0] - attribute \src "libresoc.v:65865.17-65865.211" - wire width 32 $ternary$libresoc.v:65865$3553_Y + attribute \src "libresoc.v:66099.17-66099.211" + wire width 32 $ternary$libresoc.v:66099$3565_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -107122,35 +107616,35 @@ module \dec$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LDST_AA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 27 \LDST_BA + wire width 5 \LDST_BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 26 \LDST_BB + wire width 5 \LDST_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 32 \LDST_BC + wire width 5 \LDST_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 25 \LDST_BD + wire width 14 output 24 \LDST_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 3 \LDST_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 2 \LDST_BH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 30 \LDST_BI + wire width 5 \LDST_BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 28 \LDST_BT + wire width 5 \LDST_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \LDST_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \LDST_D attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 14 output 31 \LDST_DS + wire width 14 output 25 \LDST_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 output 29 \LDST_FXM + wire width 8 \LDST_FXM attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LDST_L attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 24 output 22 \LDST_LI + wire width 24 output 21 \LDST_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \LDST_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -107162,9 +107656,9 @@ module \dec$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_ME32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 24 \LDST_OE + wire output 23 \LDST_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 17 \LDST_RA + wire width 5 output 16 \LDST_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -107172,21 +107666,21 @@ module \dec$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 23 \LDST_Rc + wire output 22 \LDST_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_SH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 output 20 \LDST_SH32 + wire width 5 output 19 \LDST_SH32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 18 \LDST_SI + wire width 16 output 17 \LDST_SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 10 output 7 \LDST_SPR + wire width 10 output 5 \LDST_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \LDST_TO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 16 output 19 \LDST_UI + wire width 16 output 18 \LDST_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 14 \LDST_br + wire output 13 \LDST_br attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -107197,7 +107691,7 @@ module \dec$195 attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 4 \LDST_cr_in + wire width 3 \LDST_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -107206,7 +107700,7 @@ module \dec$195 attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 5 \LDST_cr_out + wire width 3 output 9 \LDST_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \LDST_dec31_LDST_dec31_br attribute \enum_base_type "CRInSel" @@ -107726,7 +108220,7 @@ module \dec$195 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 8 \LDST_function_unit + wire width 13 output 6 \LDST_function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -107734,7 +108228,7 @@ module \dec$195 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 9 \LDST_in1_sel + wire width 3 output 7 \LDST_in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -107751,7 +108245,7 @@ module \dec$195 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 10 \LDST_in2_sel + wire width 4 output 8 \LDST_in2_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -107827,9 +108321,9 @@ module \dec$195 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 output 6 \LDST_internal_op + wire width 7 output 4 \LDST_internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 12 \LDST_is_32b + wire output 11 \LDST_is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -107837,7 +108331,7 @@ module \dec$195 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 4 output 11 \LDST_ldst_len + wire width 4 output 10 \LDST_ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" @@ -107845,18 +108339,18 @@ module \dec$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 3 \LDST_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 13 \LDST_sgn + wire output 12 \LDST_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 15 \LDST_sgn_ext + wire output 14 \LDST_sgn_ext attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 6 output 21 \LDST_sh + wire width 6 output 20 \LDST_sh attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" attribute \enum_value_10 "cix" attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 16 \LDST_upd + wire width 2 output 15 \LDST_upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \MDS_IB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -108038,7 +108532,7 @@ module \dec$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \XL_BO_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 output 35 \XL_BT + wire width 5 \XL_BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \XL_LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -108166,9 +108660,9 @@ module \dec$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire \X_A attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 33 \X_BF + wire width 3 \X_BF attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 output 34 \X_BFA + wire width 3 \X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \X_BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -108337,24 +108831,24 @@ module \dec$195 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian - attribute \src "libresoc.v:64505.7-64505.15" + attribute \src "libresoc.v:64740.7-64740.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 6 \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 36 \raw_opcode_in + wire width 32 input 26 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:65865$3553 + cell $mux $ternary$libresoc.v:66099$3565 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:65865$3553_Y + connect \Y $ternary$libresoc.v:66099$3565_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:65866.14-65881.4" + attribute \src "libresoc.v:66100.14-66115.4" cell \LDST_dec31 \LDST_dec31 connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in @@ -108372,7 +108866,7 @@ module \dec$195 connect \opcode_in \LDST_dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65882.14-65897.4" + attribute \src "libresoc.v:66116.14-66131.4" cell \LDST_dec58 \LDST_dec58 connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in @@ -108390,7 +108884,7 @@ module \dec$195 connect \opcode_in \LDST_dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65898.14-65913.4" + attribute \src "libresoc.v:66132.14-66147.4" cell \LDST_dec62 \LDST_dec62 connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in @@ -108407,22 +108901,22 @@ module \dec$195 connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd connect \opcode_in \LDST_dec62_opcode_in end - attribute \src "libresoc.v:64505.7-64505.20" - process $proc$libresoc.v:64505$3567 + attribute \src "libresoc.v:64740.7-64740.20" + process $proc$libresoc.v:64740$3579 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:65914.3-65971.6" - process $proc$libresoc.v:65914$3554 + attribute \src "libresoc.v:66148.3-66205.6" + process $proc$libresoc.v:66148$3566 assign { } { } assign { } { } assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65915.5-65915.29" + attribute \src "libresoc.v:66149.5-66149.29" switch \initial - attribute \src "libresoc.v:65915.9-65915.17" + attribute \src "libresoc.v:66149.9-66149.17" case 1'1 case end @@ -108502,14 +108996,14 @@ module \dec$195 sync always update \LDST_ldst_len $0\LDST_ldst_len[3:0] end - attribute \src "libresoc.v:65972.3-66029.6" - process $proc$libresoc.v:65972$3555 + attribute \src "libresoc.v:66206.3-66263.6" + process $proc$libresoc.v:66206$3567 assign { } { } assign { } { } assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "libresoc.v:65973.5-65973.29" + attribute \src "libresoc.v:66207.5-66207.29" switch \initial - attribute \src "libresoc.v:65973.9-65973.17" + attribute \src "libresoc.v:66207.9-66207.17" case 1'1 case end @@ -108589,14 +109083,14 @@ module \dec$195 sync always update \LDST_upd $0\LDST_upd[1:0] end - attribute \src "libresoc.v:66030.3-66087.6" - process $proc$libresoc.v:66030$3556 + attribute \src "libresoc.v:66264.3-66321.6" + process $proc$libresoc.v:66264$3568 assign { } { } assign { } { } assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66031.5-66031.29" + attribute \src "libresoc.v:66265.5-66265.29" switch \initial - attribute \src "libresoc.v:66031.9-66031.17" + attribute \src "libresoc.v:66265.9-66265.17" case 1'1 case end @@ -108676,14 +109170,14 @@ module \dec$195 sync always update \LDST_rc_sel $0\LDST_rc_sel[1:0] end - attribute \src "libresoc.v:66088.3-66145.6" - process $proc$libresoc.v:66088$3557 + attribute \src "libresoc.v:66322.3-66379.6" + process $proc$libresoc.v:66322$3569 assign { } { } assign { } { } assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "libresoc.v:66089.5-66089.29" + attribute \src "libresoc.v:66323.5-66323.29" switch \initial - attribute \src "libresoc.v:66089.9-66089.17" + attribute \src "libresoc.v:66323.9-66323.17" case 1'1 case end @@ -108763,14 +109257,14 @@ module \dec$195 sync always update \LDST_br $0\LDST_br[0:0] end - attribute \src "libresoc.v:66146.3-66203.6" - process $proc$libresoc.v:66146$3558 + attribute \src "libresoc.v:66380.3-66437.6" + process $proc$libresoc.v:66380$3570 assign { } { } assign { } { } assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:66147.5-66147.29" + attribute \src "libresoc.v:66381.5-66381.29" switch \initial - attribute \src "libresoc.v:66147.9-66147.17" + attribute \src "libresoc.v:66381.9-66381.17" case 1'1 case end @@ -108850,14 +109344,14 @@ module \dec$195 sync always update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] end - attribute \src "libresoc.v:66204.3-66261.6" - process $proc$libresoc.v:66204$3559 + attribute \src "libresoc.v:66438.3-66495.6" + process $proc$libresoc.v:66438$3571 assign { } { } assign { } { } assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:66205.5-66205.29" + attribute \src "libresoc.v:66439.5-66439.29" switch \initial - attribute \src "libresoc.v:66205.9-66205.17" + attribute \src "libresoc.v:66439.9-66439.17" case 1'1 case end @@ -108937,14 +109431,14 @@ module \dec$195 sync always update \LDST_is_32b $0\LDST_is_32b[0:0] end - attribute \src "libresoc.v:66262.3-66319.6" - process $proc$libresoc.v:66262$3560 + attribute \src "libresoc.v:66496.3-66553.6" + process $proc$libresoc.v:66496$3572 assign { } { } assign { } { } assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66263.5-66263.29" + attribute \src "libresoc.v:66497.5-66497.29" switch \initial - attribute \src "libresoc.v:66263.9-66263.17" + attribute \src "libresoc.v:66497.9-66497.17" case 1'1 case end @@ -109024,14 +109518,14 @@ module \dec$195 sync always update \LDST_sgn $0\LDST_sgn[0:0] end - attribute \src "libresoc.v:66320.3-66377.6" - process $proc$libresoc.v:66320$3561 + attribute \src "libresoc.v:66554.3-66611.6" + process $proc$libresoc.v:66554$3573 assign { } { } assign { } { } assign $0\LDST_function_unit[12:0] $1\LDST_function_unit[12:0] - attribute \src "libresoc.v:66321.5-66321.29" + attribute \src "libresoc.v:66555.5-66555.29" switch \initial - attribute \src "libresoc.v:66321.9-66321.17" + attribute \src "libresoc.v:66555.9-66555.17" case 1'1 case end @@ -109111,14 +109605,14 @@ module \dec$195 sync always update \LDST_function_unit $0\LDST_function_unit[12:0] end - attribute \src "libresoc.v:66378.3-66435.6" - process $proc$libresoc.v:66378$3562 + attribute \src "libresoc.v:66612.3-66669.6" + process $proc$libresoc.v:66612$3574 assign { } { } assign { } { } assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66379.5-66379.29" + attribute \src "libresoc.v:66613.5-66613.29" switch \initial - attribute \src "libresoc.v:66379.9-66379.17" + attribute \src "libresoc.v:66613.9-66613.17" case 1'1 case end @@ -109198,14 +109692,14 @@ module \dec$195 sync always update \LDST_internal_op $0\LDST_internal_op[6:0] end - attribute \src "libresoc.v:66436.3-66493.6" - process $proc$libresoc.v:66436$3563 + attribute \src "libresoc.v:66670.3-66727.6" + process $proc$libresoc.v:66670$3575 assign { } { } assign { } { } assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66437.5-66437.29" + attribute \src "libresoc.v:66671.5-66671.29" switch \initial - attribute \src "libresoc.v:66437.9-66437.17" + attribute \src "libresoc.v:66671.9-66671.17" case 1'1 case end @@ -109285,14 +109779,14 @@ module \dec$195 sync always update \LDST_in1_sel $0\LDST_in1_sel[2:0] end - attribute \src "libresoc.v:66494.3-66551.6" - process $proc$libresoc.v:66494$3564 + attribute \src "libresoc.v:66728.3-66785.6" + process $proc$libresoc.v:66728$3576 assign { } { } assign { } { } assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66495.5-66495.29" + attribute \src "libresoc.v:66729.5-66729.29" switch \initial - attribute \src "libresoc.v:66495.9-66495.17" + attribute \src "libresoc.v:66729.9-66729.17" case 1'1 case end @@ -109372,14 +109866,14 @@ module \dec$195 sync always update \LDST_in2_sel $0\LDST_in2_sel[3:0] end - attribute \src "libresoc.v:66552.3-66609.6" - process $proc$libresoc.v:66552$3565 + attribute \src "libresoc.v:66786.3-66843.6" + process $proc$libresoc.v:66786$3577 assign { } { } assign { } { } assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66553.5-66553.29" + attribute \src "libresoc.v:66787.5-66787.29" switch \initial - attribute \src "libresoc.v:66553.9-66553.17" + attribute \src "libresoc.v:66787.9-66787.17" case 1'1 case end @@ -109459,14 +109953,14 @@ module \dec$195 sync always update \LDST_cr_in $0\LDST_cr_in[2:0] end - attribute \src "libresoc.v:66610.3-66667.6" - process $proc$libresoc.v:66610$3566 + attribute \src "libresoc.v:66844.3-66901.6" + process $proc$libresoc.v:66844$3578 assign { } { } assign { } { } assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66611.5-66611.29" + attribute \src "libresoc.v:66845.5-66845.29" switch \initial - attribute \src "libresoc.v:66611.9-66611.17" + attribute \src "libresoc.v:66845.9-66845.17" case 1'1 case end @@ -109546,7 +110040,7 @@ module \dec$195 sync always update \LDST_cr_out $0\LDST_cr_out[2:0] end - connect \$1 $ternary$libresoc.v:65865$3553_Y + connect \$1 $ternary$libresoc.v:66099$3565_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -109886,207 +110380,207 @@ module \dec$195 connect \LDST_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:67010.1-74561.10" +attribute \src "libresoc.v:67244.1-74801.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" -module \dec$204 - attribute \src "libresoc.v:69818.3-69959.6" +module \dec$171 + attribute \src "libresoc.v:70058.3-70199.6" wire width 2 $0\SV_Etype[1:0] - attribute \src "libresoc.v:69960.3-70101.6" + attribute \src "libresoc.v:70200.3-70341.6" wire width 2 $0\SV_Ptype[1:0] - attribute \src "libresoc.v:69679.3-69817.6" + attribute \src "libresoc.v:69919.3-70057.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:72800.3-72941.6" + attribute \src "libresoc.v:73040.3-73181.6" wire $0\br[0:0] - attribute \src "libresoc.v:70670.3-70811.6" + attribute \src "libresoc.v:70910.3-71051.6" wire width 3 $0\cr_in[2:0] - attribute \src "libresoc.v:70812.3-70953.6" + attribute \src "libresoc.v:71052.3-71193.6" wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:72232.3-72373.6" + attribute \src "libresoc.v:72472.3-72613.6" wire width 2 $0\cry_in[1:0] - attribute \src "libresoc.v:72658.3-72799.6" + attribute \src "libresoc.v:72898.3-73039.6" wire $0\cry_out[0:0] - attribute \src "libresoc.v:74078.3-74219.6" + attribute \src "libresoc.v:74318.3-74459.6" wire width 5 $0\form[4:0] - attribute \src "libresoc.v:73794.3-73935.6" + attribute \src "libresoc.v:74034.3-74175.6" wire width 13 $0\function_unit[12:0] - attribute \src "libresoc.v:70102.3-70243.6" + attribute \src "libresoc.v:70342.3-70483.6" wire width 3 $0\in1_sel[2:0] - attribute \src "libresoc.v:70244.3-70385.6" + attribute \src "libresoc.v:70484.3-70625.6" wire width 4 $0\in2_sel[3:0] - attribute \src "libresoc.v:70386.3-70527.6" + attribute \src "libresoc.v:70626.3-70767.6" wire width 2 $0\in3_sel[1:0] - attribute \src "libresoc.v:67011.7-67011.20" + attribute \src "libresoc.v:67245.7-67245.20" wire $0\initial[0:0] - attribute \src "libresoc.v:73936.3-74077.6" + attribute \src "libresoc.v:74176.3-74317.6" wire width 7 $0\internal_op[6:0] - attribute \src "libresoc.v:72374.3-72515.6" + attribute \src "libresoc.v:72614.3-72755.6" wire $0\inv_a[0:0] - attribute \src "libresoc.v:72516.3-72657.6" + attribute \src "libresoc.v:72756.3-72897.6" wire $0\inv_out[0:0] - attribute \src "libresoc.v:73226.3-73367.6" + attribute \src "libresoc.v:73466.3-73607.6" wire $0\is_32b[0:0] - attribute \src "libresoc.v:71806.3-71947.6" + attribute \src "libresoc.v:72046.3-72187.6" wire width 4 $0\ldst_len[3:0] - attribute \src "libresoc.v:73510.3-73651.6" + attribute \src "libresoc.v:73750.3-73891.6" wire $0\lk[0:0] - attribute \src "libresoc.v:70528.3-70669.6" + attribute \src "libresoc.v:70768.3-70909.6" wire width 2 $0\out_sel[1:0] - attribute \src "libresoc.v:72090.3-72231.6" + attribute \src "libresoc.v:72330.3-72471.6" wire width 2 $0\rc_sel[1:0] - attribute \src "libresoc.v:73084.3-73225.6" + attribute \src "libresoc.v:73324.3-73465.6" wire $0\rsrv[0:0] - attribute \src "libresoc.v:73652.3-73793.6" + attribute \src "libresoc.v:73892.3-74033.6" wire $0\sgl_pipe[0:0] - attribute \src "libresoc.v:73368.3-73509.6" + attribute \src "libresoc.v:73608.3-73749.6" wire $0\sgn[0:0] - attribute \src "libresoc.v:72942.3-73083.6" + attribute \src "libresoc.v:73182.3-73323.6" wire $0\sgn_ext[0:0] - attribute \src "libresoc.v:71522.3-71663.6" + attribute \src "libresoc.v:71762.3-71903.6" wire width 3 $0\sv_cr_in[2:0] - attribute \src "libresoc.v:71664.3-71805.6" + attribute \src "libresoc.v:71904.3-72045.6" wire width 3 $0\sv_cr_out[2:0] - attribute \src "libresoc.v:70954.3-71095.6" + attribute \src "libresoc.v:71194.3-71335.6" wire width 3 $0\sv_in1[2:0] - attribute \src "libresoc.v:71096.3-71237.6" + attribute \src "libresoc.v:71336.3-71477.6" wire width 3 $0\sv_in2[2:0] - attribute \src "libresoc.v:71238.3-71379.6" + attribute \src "libresoc.v:71478.3-71619.6" wire width 3 $0\sv_in3[2:0] - attribute \src "libresoc.v:71380.3-71521.6" + attribute \src "libresoc.v:71620.3-71761.6" wire width 3 $0\sv_out[2:0] - attribute \src "libresoc.v:71948.3-72089.6" + attribute \src "libresoc.v:72188.3-72329.6" wire width 2 $0\upd[1:0] - attribute \src "libresoc.v:69818.3-69959.6" + attribute \src "libresoc.v:70058.3-70199.6" wire width 2 $1\SV_Etype[1:0] - attribute \src "libresoc.v:69960.3-70101.6" + attribute \src "libresoc.v:70200.3-70341.6" wire width 2 $1\SV_Ptype[1:0] - attribute \src "libresoc.v:69679.3-69817.6" + attribute \src "libresoc.v:69919.3-70057.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:72800.3-72941.6" + attribute \src "libresoc.v:73040.3-73181.6" wire $1\br[0:0] - attribute \src "libresoc.v:70670.3-70811.6" + attribute \src "libresoc.v:70910.3-71051.6" wire width 3 $1\cr_in[2:0] - attribute \src "libresoc.v:70812.3-70953.6" + attribute \src "libresoc.v:71052.3-71193.6" wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:72232.3-72373.6" + attribute \src "libresoc.v:72472.3-72613.6" wire width 2 $1\cry_in[1:0] - attribute \src "libresoc.v:72658.3-72799.6" + attribute \src "libresoc.v:72898.3-73039.6" wire $1\cry_out[0:0] - attribute \src "libresoc.v:74078.3-74219.6" + attribute \src "libresoc.v:74318.3-74459.6" wire width 5 $1\form[4:0] - attribute \src "libresoc.v:73794.3-73935.6" + attribute \src "libresoc.v:74034.3-74175.6" wire width 13 $1\function_unit[12:0] - attribute \src "libresoc.v:70102.3-70243.6" + attribute \src "libresoc.v:70342.3-70483.6" wire width 3 $1\in1_sel[2:0] - attribute \src "libresoc.v:70244.3-70385.6" + attribute \src "libresoc.v:70484.3-70625.6" wire width 4 $1\in2_sel[3:0] - attribute \src "libresoc.v:70386.3-70527.6" + attribute \src "libresoc.v:70626.3-70767.6" wire width 2 $1\in3_sel[1:0] - attribute \src "libresoc.v:73936.3-74077.6" + attribute \src "libresoc.v:74176.3-74317.6" wire width 7 $1\internal_op[6:0] - attribute \src "libresoc.v:72374.3-72515.6" + attribute \src "libresoc.v:72614.3-72755.6" wire $1\inv_a[0:0] - attribute \src "libresoc.v:72516.3-72657.6" + attribute \src "libresoc.v:72756.3-72897.6" wire $1\inv_out[0:0] - attribute \src "libresoc.v:73226.3-73367.6" + attribute \src "libresoc.v:73466.3-73607.6" wire $1\is_32b[0:0] - attribute \src "libresoc.v:71806.3-71947.6" + attribute \src "libresoc.v:72046.3-72187.6" wire width 4 $1\ldst_len[3:0] - attribute \src "libresoc.v:73510.3-73651.6" + attribute \src "libresoc.v:73750.3-73891.6" wire $1\lk[0:0] - attribute \src "libresoc.v:70528.3-70669.6" + attribute \src "libresoc.v:70768.3-70909.6" wire width 2 $1\out_sel[1:0] - attribute \src "libresoc.v:72090.3-72231.6" + attribute \src "libresoc.v:72330.3-72471.6" wire width 2 $1\rc_sel[1:0] - attribute \src "libresoc.v:73084.3-73225.6" + attribute \src "libresoc.v:73324.3-73465.6" wire $1\rsrv[0:0] - attribute \src "libresoc.v:73652.3-73793.6" + attribute \src "libresoc.v:73892.3-74033.6" wire $1\sgl_pipe[0:0] - attribute \src "libresoc.v:73368.3-73509.6" + attribute \src "libresoc.v:73608.3-73749.6" wire $1\sgn[0:0] - attribute \src "libresoc.v:72942.3-73083.6" + attribute \src "libresoc.v:73182.3-73323.6" wire $1\sgn_ext[0:0] - attribute \src "libresoc.v:71522.3-71663.6" + attribute \src "libresoc.v:71762.3-71903.6" wire width 3 $1\sv_cr_in[2:0] - attribute \src "libresoc.v:71664.3-71805.6" + attribute \src "libresoc.v:71904.3-72045.6" wire width 3 $1\sv_cr_out[2:0] - attribute \src "libresoc.v:70954.3-71095.6" + attribute \src "libresoc.v:71194.3-71335.6" wire width 3 $1\sv_in1[2:0] - attribute \src "libresoc.v:71096.3-71237.6" + attribute \src "libresoc.v:71336.3-71477.6" wire width 3 $1\sv_in2[2:0] - attribute \src "libresoc.v:71238.3-71379.6" + attribute \src "libresoc.v:71478.3-71619.6" wire width 3 $1\sv_in3[2:0] - attribute \src "libresoc.v:71380.3-71521.6" + attribute \src "libresoc.v:71620.3-71761.6" wire width 3 $1\sv_out[2:0] - attribute \src "libresoc.v:71948.3-72089.6" + attribute \src "libresoc.v:72188.3-72329.6" wire width 2 $1\upd[1:0] - attribute \src "libresoc.v:69818.3-69959.6" + attribute \src "libresoc.v:70058.3-70199.6" wire width 2 $2\SV_Etype[1:0] - attribute \src "libresoc.v:69960.3-70101.6" + attribute \src "libresoc.v:70200.3-70341.6" wire width 2 $2\SV_Ptype[1:0] - attribute \src "libresoc.v:69679.3-69817.6" + attribute \src "libresoc.v:69919.3-70057.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:72800.3-72941.6" + attribute \src "libresoc.v:73040.3-73181.6" wire $2\br[0:0] - attribute \src "libresoc.v:70670.3-70811.6" + attribute \src "libresoc.v:70910.3-71051.6" wire width 3 $2\cr_in[2:0] - attribute \src "libresoc.v:70812.3-70953.6" + attribute \src "libresoc.v:71052.3-71193.6" wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:72232.3-72373.6" + attribute \src "libresoc.v:72472.3-72613.6" wire width 2 $2\cry_in[1:0] - attribute \src "libresoc.v:72658.3-72799.6" + attribute \src "libresoc.v:72898.3-73039.6" wire $2\cry_out[0:0] - attribute \src "libresoc.v:74078.3-74219.6" + attribute \src "libresoc.v:74318.3-74459.6" wire width 5 $2\form[4:0] - attribute \src "libresoc.v:73794.3-73935.6" + attribute \src "libresoc.v:74034.3-74175.6" wire width 13 $2\function_unit[12:0] - attribute \src "libresoc.v:70102.3-70243.6" + attribute \src "libresoc.v:70342.3-70483.6" wire width 3 $2\in1_sel[2:0] - attribute \src "libresoc.v:70244.3-70385.6" + attribute \src "libresoc.v:70484.3-70625.6" wire width 4 $2\in2_sel[3:0] - attribute \src "libresoc.v:70386.3-70527.6" + attribute \src "libresoc.v:70626.3-70767.6" wire width 2 $2\in3_sel[1:0] - attribute \src "libresoc.v:73936.3-74077.6" + attribute \src "libresoc.v:74176.3-74317.6" wire width 7 $2\internal_op[6:0] - attribute \src "libresoc.v:72374.3-72515.6" + attribute \src "libresoc.v:72614.3-72755.6" wire $2\inv_a[0:0] - attribute \src "libresoc.v:72516.3-72657.6" + attribute \src "libresoc.v:72756.3-72897.6" wire $2\inv_out[0:0] - attribute \src "libresoc.v:73226.3-73367.6" + attribute \src "libresoc.v:73466.3-73607.6" wire $2\is_32b[0:0] - attribute \src "libresoc.v:71806.3-71947.6" + attribute \src "libresoc.v:72046.3-72187.6" wire width 4 $2\ldst_len[3:0] - attribute \src "libresoc.v:73510.3-73651.6" + attribute \src "libresoc.v:73750.3-73891.6" wire $2\lk[0:0] - attribute \src "libresoc.v:70528.3-70669.6" + attribute \src "libresoc.v:70768.3-70909.6" wire width 2 $2\out_sel[1:0] - attribute \src "libresoc.v:72090.3-72231.6" + attribute \src "libresoc.v:72330.3-72471.6" wire width 2 $2\rc_sel[1:0] - attribute \src "libresoc.v:73084.3-73225.6" + attribute \src "libresoc.v:73324.3-73465.6" wire $2\rsrv[0:0] - attribute \src "libresoc.v:73652.3-73793.6" + attribute \src "libresoc.v:73892.3-74033.6" wire $2\sgl_pipe[0:0] - attribute \src "libresoc.v:73368.3-73509.6" + attribute \src "libresoc.v:73608.3-73749.6" wire $2\sgn[0:0] - attribute \src "libresoc.v:72942.3-73083.6" + attribute \src "libresoc.v:73182.3-73323.6" wire $2\sgn_ext[0:0] - attribute \src "libresoc.v:71522.3-71663.6" + attribute \src "libresoc.v:71762.3-71903.6" wire width 3 $2\sv_cr_in[2:0] - attribute \src "libresoc.v:71664.3-71805.6" + attribute \src "libresoc.v:71904.3-72045.6" wire width 3 $2\sv_cr_out[2:0] - attribute \src "libresoc.v:70954.3-71095.6" + attribute \src "libresoc.v:71194.3-71335.6" wire width 3 $2\sv_in1[2:0] - attribute \src "libresoc.v:71096.3-71237.6" + attribute \src "libresoc.v:71336.3-71477.6" wire width 3 $2\sv_in2[2:0] - attribute \src "libresoc.v:71238.3-71379.6" + attribute \src "libresoc.v:71478.3-71619.6" wire width 3 $2\sv_in3[2:0] - attribute \src "libresoc.v:71380.3-71521.6" + attribute \src "libresoc.v:71620.3-71761.6" wire width 3 $2\sv_out[2:0] - attribute \src "libresoc.v:71948.3-72089.6" + attribute \src "libresoc.v:72188.3-72329.6" wire width 2 $2\upd[1:0] - attribute \src "libresoc.v:69503.17-69503.211" - wire width 32 $ternary$libresoc.v:69503$3568_Y + attribute \src "libresoc.v:69743.17-69743.211" + wire width 32 $ternary$libresoc.v:69743$3580_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" wire width 32 \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -110242,7 +110736,7 @@ module \dec$204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire output 12 \LK + wire output 11 \LK attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 \MB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" @@ -110326,7 +110820,7 @@ module \dec$204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \SI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 10 output 7 \SPR + wire width 10 output 5 \SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" wire width 5 \SVL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" @@ -110781,7 +111275,7 @@ module \dec$204 attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 4 \cr_in + wire width 3 output 12 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -110790,13 +111284,13 @@ module \dec$204 attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 output 5 \cr_out + wire width 3 output 7 \cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 output 9 \cry_in + wire width 2 output 8 \cry_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \cry_out attribute \enum_base_type "SVEtype" @@ -110873,6 +111367,7 @@ module \dec$204 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec19_dec19_form attribute \enum_base_type "Function" @@ -111172,6 +111667,7 @@ module \dec$204 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec30_dec30_form attribute \enum_base_type "Function" @@ -111471,6 +111967,7 @@ module \dec$204 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec31_form attribute \enum_base_type "Function" @@ -111770,6 +112267,7 @@ module \dec$204 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec58_dec58_form attribute \enum_base_type "Function" @@ -112069,6 +112567,7 @@ module \dec$204 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec62_dec62_form attribute \enum_base_type "Function" @@ -112324,6 +112823,7 @@ module \dec$204 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \form attribute \enum_base_type "Function" @@ -112341,7 +112841,7 @@ module \dec$204 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 13 output 8 \function_unit + wire width 13 output 6 \function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -112373,7 +112873,7 @@ module \dec$204 attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 17 \in3_sel - attribute \src "libresoc.v:67011.7-67011.15" + attribute \src "libresoc.v:67245.7-67245.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -112450,13 +112950,13 @@ module \dec$204 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 output 6 \internal_op + wire width 7 output 4 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 10 \is_32b + wire output 9 \is_32b attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -112466,7 +112966,7 @@ module \dec$204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 4 \ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" - wire output 11 \lk + wire output 10 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 output 2 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" @@ -112560,15 +113060,15 @@ module \dec$204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 25 \upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" - cell $mux $ternary$libresoc.v:69503$3568 + cell $mux $ternary$libresoc.v:69743$3580 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:69503$3568_Y + connect \Y $ternary$libresoc.v:69743$3580_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:69504.9-69538.4" + attribute \src "libresoc.v:69744.9-69778.4" cell \dec19 \dec19 connect \dec19_SV_Etype \dec19_dec19_SV_Etype connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype @@ -112605,7 +113105,7 @@ module \dec$204 connect \opcode_in \dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69539.9-69573.4" + attribute \src "libresoc.v:69779.9-69813.4" cell \dec30 \dec30 connect \dec30_SV_Etype \dec30_dec30_SV_Etype connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype @@ -112642,7 +113142,7 @@ module \dec$204 connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69574.9-69608.4" + attribute \src "libresoc.v:69814.9-69848.4" cell \dec31 \dec31 connect \dec31_SV_Etype \dec31_dec31_SV_Etype connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype @@ -112679,7 +113179,7 @@ module \dec$204 connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69609.9-69643.4" + attribute \src "libresoc.v:69849.9-69883.4" cell \dec58 \dec58 connect \dec58_SV_Etype \dec58_dec58_SV_Etype connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype @@ -112716,7 +113216,7 @@ module \dec$204 connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69644.9-69678.4" + attribute \src "libresoc.v:69884.9-69918.4" cell \dec62 \dec62 connect \dec62_SV_Etype \dec62_dec62_SV_Etype connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype @@ -112752,23 +113252,23 @@ module \dec$204 connect \dec62_upd \dec62_dec62_upd connect \opcode_in \dec62_opcode_in end - attribute \src "libresoc.v:67011.7-67011.20" - process $proc$libresoc.v:67011$3601 + attribute \src "libresoc.v:67245.7-67245.20" + process $proc$libresoc.v:67245$3613 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:69679.3-69817.6" - process $proc$libresoc.v:69679$3569 + attribute \src "libresoc.v:69919.3-70057.6" + process $proc$libresoc.v:69919$3581 assign { } { } assign { } { } assign { } { } assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:69680.5-69680.29" + attribute \src "libresoc.v:69920.5-69920.29" switch \initial - attribute \src "libresoc.v:69680.9-69680.17" + attribute \src "libresoc.v:69920.9-69920.17" case 1'1 case end @@ -112957,15 +113457,15 @@ module \dec$204 sync always update \asmcode $0\asmcode[7:0] end - attribute \src "libresoc.v:69818.3-69959.6" - process $proc$libresoc.v:69818$3570 + attribute \src "libresoc.v:70058.3-70199.6" + process $proc$libresoc.v:70058$3582 assign { } { } assign { } { } assign { } { } assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] - attribute \src "libresoc.v:69819.5-69819.29" + attribute \src "libresoc.v:70059.5-70059.29" switch \initial - attribute \src "libresoc.v:69819.9-69819.17" + attribute \src "libresoc.v:70059.9-70059.17" case 1'1 case end @@ -113158,15 +113658,15 @@ module \dec$204 sync always update \SV_Etype $0\SV_Etype[1:0] end - attribute \src "libresoc.v:69960.3-70101.6" - process $proc$libresoc.v:69960$3571 + attribute \src "libresoc.v:70200.3-70341.6" + process $proc$libresoc.v:70200$3583 assign { } { } assign { } { } assign { } { } assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] - attribute \src "libresoc.v:69961.5-69961.29" + attribute \src "libresoc.v:70201.5-70201.29" switch \initial - attribute \src "libresoc.v:69961.9-69961.17" + attribute \src "libresoc.v:70201.9-70201.17" case 1'1 case end @@ -113359,15 +113859,15 @@ module \dec$204 sync always update \SV_Ptype $0\SV_Ptype[1:0] end - attribute \src "libresoc.v:70102.3-70243.6" - process $proc$libresoc.v:70102$3572 + attribute \src "libresoc.v:70342.3-70483.6" + process $proc$libresoc.v:70342$3584 assign { } { } assign { } { } assign { } { } assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:70103.5-70103.29" + attribute \src "libresoc.v:70343.5-70343.29" switch \initial - attribute \src "libresoc.v:70103.9-70103.17" + attribute \src "libresoc.v:70343.9-70343.17" case 1'1 case end @@ -113560,15 +114060,15 @@ module \dec$204 sync always update \in1_sel $0\in1_sel[2:0] end - attribute \src "libresoc.v:70244.3-70385.6" - process $proc$libresoc.v:70244$3573 + attribute \src "libresoc.v:70484.3-70625.6" + process $proc$libresoc.v:70484$3585 assign { } { } assign { } { } assign { } { } assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:70245.5-70245.29" + attribute \src "libresoc.v:70485.5-70485.29" switch \initial - attribute \src "libresoc.v:70245.9-70245.17" + attribute \src "libresoc.v:70485.9-70485.17" case 1'1 case end @@ -113761,15 +114261,15 @@ module \dec$204 sync always update \in2_sel $0\in2_sel[3:0] end - attribute \src "libresoc.v:70386.3-70527.6" - process $proc$libresoc.v:70386$3574 + attribute \src "libresoc.v:70626.3-70767.6" + process $proc$libresoc.v:70626$3586 assign { } { } assign { } { } assign { } { } assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:70387.5-70387.29" + attribute \src "libresoc.v:70627.5-70627.29" switch \initial - attribute \src "libresoc.v:70387.9-70387.17" + attribute \src "libresoc.v:70627.9-70627.17" case 1'1 case end @@ -113962,15 +114462,15 @@ module \dec$204 sync always update \in3_sel $0\in3_sel[1:0] end - attribute \src "libresoc.v:70528.3-70669.6" - process $proc$libresoc.v:70528$3575 + attribute \src "libresoc.v:70768.3-70909.6" + process $proc$libresoc.v:70768$3587 assign { } { } assign { } { } assign { } { } assign $0\out_sel[1:0] $2\out_sel[1:0] - attribute \src "libresoc.v:70529.5-70529.29" + attribute \src "libresoc.v:70769.5-70769.29" switch \initial - attribute \src "libresoc.v:70529.9-70529.17" + attribute \src "libresoc.v:70769.9-70769.17" case 1'1 case end @@ -114163,15 +114663,15 @@ module \dec$204 sync always update \out_sel $0\out_sel[1:0] end - attribute \src "libresoc.v:70670.3-70811.6" - process $proc$libresoc.v:70670$3576 + attribute \src "libresoc.v:70910.3-71051.6" + process $proc$libresoc.v:70910$3588 assign { } { } assign { } { } assign { } { } assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:70671.5-70671.29" + attribute \src "libresoc.v:70911.5-70911.29" switch \initial - attribute \src "libresoc.v:70671.9-70671.17" + attribute \src "libresoc.v:70911.9-70911.17" case 1'1 case end @@ -114364,15 +114864,15 @@ module \dec$204 sync always update \cr_in $0\cr_in[2:0] end - attribute \src "libresoc.v:70812.3-70953.6" - process $proc$libresoc.v:70812$3577 + attribute \src "libresoc.v:71052.3-71193.6" + process $proc$libresoc.v:71052$3589 assign { } { } assign { } { } assign { } { } assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:70813.5-70813.29" + attribute \src "libresoc.v:71053.5-71053.29" switch \initial - attribute \src "libresoc.v:70813.9-70813.17" + attribute \src "libresoc.v:71053.9-71053.17" case 1'1 case end @@ -114565,15 +115065,15 @@ module \dec$204 sync always update \cr_out $0\cr_out[2:0] end - attribute \src "libresoc.v:70954.3-71095.6" - process $proc$libresoc.v:70954$3578 + attribute \src "libresoc.v:71194.3-71335.6" + process $proc$libresoc.v:71194$3590 assign { } { } assign { } { } assign { } { } assign $0\sv_in1[2:0] $2\sv_in1[2:0] - attribute \src "libresoc.v:70955.5-70955.29" + attribute \src "libresoc.v:71195.5-71195.29" switch \initial - attribute \src "libresoc.v:70955.9-70955.17" + attribute \src "libresoc.v:71195.9-71195.17" case 1'1 case end @@ -114766,15 +115266,15 @@ module \dec$204 sync always update \sv_in1 $0\sv_in1[2:0] end - attribute \src "libresoc.v:71096.3-71237.6" - process $proc$libresoc.v:71096$3579 + attribute \src "libresoc.v:71336.3-71477.6" + process $proc$libresoc.v:71336$3591 assign { } { } assign { } { } assign { } { } assign $0\sv_in2[2:0] $2\sv_in2[2:0] - attribute \src "libresoc.v:71097.5-71097.29" + attribute \src "libresoc.v:71337.5-71337.29" switch \initial - attribute \src "libresoc.v:71097.9-71097.17" + attribute \src "libresoc.v:71337.9-71337.17" case 1'1 case end @@ -114967,15 +115467,15 @@ module \dec$204 sync always update \sv_in2 $0\sv_in2[2:0] end - attribute \src "libresoc.v:71238.3-71379.6" - process $proc$libresoc.v:71238$3580 + attribute \src "libresoc.v:71478.3-71619.6" + process $proc$libresoc.v:71478$3592 assign { } { } assign { } { } assign { } { } assign $0\sv_in3[2:0] $2\sv_in3[2:0] - attribute \src "libresoc.v:71239.5-71239.29" + attribute \src "libresoc.v:71479.5-71479.29" switch \initial - attribute \src "libresoc.v:71239.9-71239.17" + attribute \src "libresoc.v:71479.9-71479.17" case 1'1 case end @@ -115168,15 +115668,15 @@ module \dec$204 sync always update \sv_in3 $0\sv_in3[2:0] end - attribute \src "libresoc.v:71380.3-71521.6" - process $proc$libresoc.v:71380$3581 + attribute \src "libresoc.v:71620.3-71761.6" + process $proc$libresoc.v:71620$3593 assign { } { } assign { } { } assign { } { } assign $0\sv_out[2:0] $2\sv_out[2:0] - attribute \src "libresoc.v:71381.5-71381.29" + attribute \src "libresoc.v:71621.5-71621.29" switch \initial - attribute \src "libresoc.v:71381.9-71381.17" + attribute \src "libresoc.v:71621.9-71621.17" case 1'1 case end @@ -115369,15 +115869,15 @@ module \dec$204 sync always update \sv_out $0\sv_out[2:0] end - attribute \src "libresoc.v:71522.3-71663.6" - process $proc$libresoc.v:71522$3582 + attribute \src "libresoc.v:71762.3-71903.6" + process $proc$libresoc.v:71762$3594 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] - attribute \src "libresoc.v:71523.5-71523.29" + attribute \src "libresoc.v:71763.5-71763.29" switch \initial - attribute \src "libresoc.v:71523.9-71523.17" + attribute \src "libresoc.v:71763.9-71763.17" case 1'1 case end @@ -115570,15 +116070,15 @@ module \dec$204 sync always update \sv_cr_in $0\sv_cr_in[2:0] end - attribute \src "libresoc.v:71664.3-71805.6" - process $proc$libresoc.v:71664$3583 + attribute \src "libresoc.v:71904.3-72045.6" + process $proc$libresoc.v:71904$3595 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] - attribute \src "libresoc.v:71665.5-71665.29" + attribute \src "libresoc.v:71905.5-71905.29" switch \initial - attribute \src "libresoc.v:71665.9-71665.17" + attribute \src "libresoc.v:71905.9-71905.17" case 1'1 case end @@ -115771,15 +116271,15 @@ module \dec$204 sync always update \sv_cr_out $0\sv_cr_out[2:0] end - attribute \src "libresoc.v:71806.3-71947.6" - process $proc$libresoc.v:71806$3584 + attribute \src "libresoc.v:72046.3-72187.6" + process $proc$libresoc.v:72046$3596 assign { } { } assign { } { } assign { } { } assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:71807.5-71807.29" + attribute \src "libresoc.v:72047.5-72047.29" switch \initial - attribute \src "libresoc.v:71807.9-71807.17" + attribute \src "libresoc.v:72047.9-72047.17" case 1'1 case end @@ -115972,15 +116472,15 @@ module \dec$204 sync always update \ldst_len $0\ldst_len[3:0] end - attribute \src "libresoc.v:71948.3-72089.6" - process $proc$libresoc.v:71948$3585 + attribute \src "libresoc.v:72188.3-72329.6" + process $proc$libresoc.v:72188$3597 assign { } { } assign { } { } assign { } { } assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:71949.5-71949.29" + attribute \src "libresoc.v:72189.5-72189.29" switch \initial - attribute \src "libresoc.v:71949.9-71949.17" + attribute \src "libresoc.v:72189.9-72189.17" case 1'1 case end @@ -116173,15 +116673,15 @@ module \dec$204 sync always update \upd $0\upd[1:0] end - attribute \src "libresoc.v:72090.3-72231.6" - process $proc$libresoc.v:72090$3586 + attribute \src "libresoc.v:72330.3-72471.6" + process $proc$libresoc.v:72330$3598 assign { } { } assign { } { } assign { } { } assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:72091.5-72091.29" + attribute \src "libresoc.v:72331.5-72331.29" switch \initial - attribute \src "libresoc.v:72091.9-72091.17" + attribute \src "libresoc.v:72331.9-72331.17" case 1'1 case end @@ -116374,15 +116874,15 @@ module \dec$204 sync always update \rc_sel $0\rc_sel[1:0] end - attribute \src "libresoc.v:72232.3-72373.6" - process $proc$libresoc.v:72232$3587 + attribute \src "libresoc.v:72472.3-72613.6" + process $proc$libresoc.v:72472$3599 assign { } { } assign { } { } assign { } { } assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:72233.5-72233.29" + attribute \src "libresoc.v:72473.5-72473.29" switch \initial - attribute \src "libresoc.v:72233.9-72233.17" + attribute \src "libresoc.v:72473.9-72473.17" case 1'1 case end @@ -116575,15 +117075,15 @@ module \dec$204 sync always update \cry_in $0\cry_in[1:0] end - attribute \src "libresoc.v:72374.3-72515.6" - process $proc$libresoc.v:72374$3588 + attribute \src "libresoc.v:72614.3-72755.6" + process $proc$libresoc.v:72614$3600 assign { } { } assign { } { } assign { } { } assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:72375.5-72375.29" + attribute \src "libresoc.v:72615.5-72615.29" switch \initial - attribute \src "libresoc.v:72375.9-72375.17" + attribute \src "libresoc.v:72615.9-72615.17" case 1'1 case end @@ -116776,15 +117276,15 @@ module \dec$204 sync always update \inv_a $0\inv_a[0:0] end - attribute \src "libresoc.v:72516.3-72657.6" - process $proc$libresoc.v:72516$3589 + attribute \src "libresoc.v:72756.3-72897.6" + process $proc$libresoc.v:72756$3601 assign { } { } assign { } { } assign { } { } assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:72517.5-72517.29" + attribute \src "libresoc.v:72757.5-72757.29" switch \initial - attribute \src "libresoc.v:72517.9-72517.17" + attribute \src "libresoc.v:72757.9-72757.17" case 1'1 case end @@ -116977,15 +117477,15 @@ module \dec$204 sync always update \inv_out $0\inv_out[0:0] end - attribute \src "libresoc.v:72658.3-72799.6" - process $proc$libresoc.v:72658$3590 + attribute \src "libresoc.v:72898.3-73039.6" + process $proc$libresoc.v:72898$3602 assign { } { } assign { } { } assign { } { } assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:72659.5-72659.29" + attribute \src "libresoc.v:72899.5-72899.29" switch \initial - attribute \src "libresoc.v:72659.9-72659.17" + attribute \src "libresoc.v:72899.9-72899.17" case 1'1 case end @@ -117178,15 +117678,15 @@ module \dec$204 sync always update \cry_out $0\cry_out[0:0] end - attribute \src "libresoc.v:72800.3-72941.6" - process $proc$libresoc.v:72800$3591 + attribute \src "libresoc.v:73040.3-73181.6" + process $proc$libresoc.v:73040$3603 assign { } { } assign { } { } assign { } { } assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:72801.5-72801.29" + attribute \src "libresoc.v:73041.5-73041.29" switch \initial - attribute \src "libresoc.v:72801.9-72801.17" + attribute \src "libresoc.v:73041.9-73041.17" case 1'1 case end @@ -117379,15 +117879,15 @@ module \dec$204 sync always update \br $0\br[0:0] end - attribute \src "libresoc.v:72942.3-73083.6" - process $proc$libresoc.v:72942$3592 + attribute \src "libresoc.v:73182.3-73323.6" + process $proc$libresoc.v:73182$3604 assign { } { } assign { } { } assign { } { } assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:72943.5-72943.29" + attribute \src "libresoc.v:73183.5-73183.29" switch \initial - attribute \src "libresoc.v:72943.9-72943.17" + attribute \src "libresoc.v:73183.9-73183.17" case 1'1 case end @@ -117580,15 +118080,15 @@ module \dec$204 sync always update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "libresoc.v:73084.3-73225.6" - process $proc$libresoc.v:73084$3593 + attribute \src "libresoc.v:73324.3-73465.6" + process $proc$libresoc.v:73324$3605 assign { } { } assign { } { } assign { } { } assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:73085.5-73085.29" + attribute \src "libresoc.v:73325.5-73325.29" switch \initial - attribute \src "libresoc.v:73085.9-73085.17" + attribute \src "libresoc.v:73325.9-73325.17" case 1'1 case end @@ -117781,15 +118281,15 @@ module \dec$204 sync always update \rsrv $0\rsrv[0:0] end - attribute \src "libresoc.v:73226.3-73367.6" - process $proc$libresoc.v:73226$3594 + attribute \src "libresoc.v:73466.3-73607.6" + process $proc$libresoc.v:73466$3606 assign { } { } assign { } { } assign { } { } assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:73227.5-73227.29" + attribute \src "libresoc.v:73467.5-73467.29" switch \initial - attribute \src "libresoc.v:73227.9-73227.17" + attribute \src "libresoc.v:73467.9-73467.17" case 1'1 case end @@ -117982,15 +118482,15 @@ module \dec$204 sync always update \is_32b $0\is_32b[0:0] end - attribute \src "libresoc.v:73368.3-73509.6" - process $proc$libresoc.v:73368$3595 + attribute \src "libresoc.v:73608.3-73749.6" + process $proc$libresoc.v:73608$3607 assign { } { } assign { } { } assign { } { } assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:73369.5-73369.29" + attribute \src "libresoc.v:73609.5-73609.29" switch \initial - attribute \src "libresoc.v:73369.9-73369.17" + attribute \src "libresoc.v:73609.9-73609.17" case 1'1 case end @@ -118183,15 +118683,15 @@ module \dec$204 sync always update \sgn $0\sgn[0:0] end - attribute \src "libresoc.v:73510.3-73651.6" - process $proc$libresoc.v:73510$3596 + attribute \src "libresoc.v:73750.3-73891.6" + process $proc$libresoc.v:73750$3608 assign { } { } assign { } { } assign { } { } assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:73511.5-73511.29" + attribute \src "libresoc.v:73751.5-73751.29" switch \initial - attribute \src "libresoc.v:73511.9-73511.17" + attribute \src "libresoc.v:73751.9-73751.17" case 1'1 case end @@ -118384,15 +118884,15 @@ module \dec$204 sync always update \lk $0\lk[0:0] end - attribute \src "libresoc.v:73652.3-73793.6" - process $proc$libresoc.v:73652$3597 + attribute \src "libresoc.v:73892.3-74033.6" + process $proc$libresoc.v:73892$3609 assign { } { } assign { } { } assign { } { } assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:73653.5-73653.29" + attribute \src "libresoc.v:73893.5-73893.29" switch \initial - attribute \src "libresoc.v:73653.9-73653.17" + attribute \src "libresoc.v:73893.9-73893.17" case 1'1 case end @@ -118585,15 +119085,15 @@ module \dec$204 sync always update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "libresoc.v:73794.3-73935.6" - process $proc$libresoc.v:73794$3598 + attribute \src "libresoc.v:74034.3-74175.6" + process $proc$libresoc.v:74034$3610 assign { } { } assign { } { } assign { } { } assign $0\function_unit[12:0] $2\function_unit[12:0] - attribute \src "libresoc.v:73795.5-73795.29" + attribute \src "libresoc.v:74035.5-74035.29" switch \initial - attribute \src "libresoc.v:73795.9-73795.17" + attribute \src "libresoc.v:74035.9-74035.17" case 1'1 case end @@ -118786,15 +119286,15 @@ module \dec$204 sync always update \function_unit $0\function_unit[12:0] end - attribute \src "libresoc.v:73936.3-74077.6" - process $proc$libresoc.v:73936$3599 + attribute \src "libresoc.v:74176.3-74317.6" + process $proc$libresoc.v:74176$3611 assign { } { } assign { } { } assign { } { } assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:73937.5-73937.29" + attribute \src "libresoc.v:74177.5-74177.29" switch \initial - attribute \src "libresoc.v:73937.9-73937.17" + attribute \src "libresoc.v:74177.9-74177.17" case 1'1 case end @@ -118987,15 +119487,15 @@ module \dec$204 sync always update \internal_op $0\internal_op[6:0] end - attribute \src "libresoc.v:74078.3-74219.6" - process $proc$libresoc.v:74078$3600 + attribute \src "libresoc.v:74318.3-74459.6" + process $proc$libresoc.v:74318$3612 assign { } { } assign { } { } assign { } { } assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:74079.5-74079.29" + attribute \src "libresoc.v:74319.5-74319.29" switch \initial - attribute \src "libresoc.v:74079.9-74079.17" + attribute \src "libresoc.v:74319.9-74319.17" case 1'1 case end @@ -119188,7 +119688,7 @@ module \dec$204 sync always update \form $0\form[4:0] end - connect \$2 $ternary$libresoc.v:69503$3568_Y + connect \$2 $ternary$libresoc.v:69743$3580_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -119531,140 +120031,140 @@ module \dec$204 connect \dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:74565.1-76565.10" +attribute \src "libresoc.v:74805.1-76806.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" module \dec19 - attribute \src "libresoc.v:76252.3-76303.6" + attribute \src "libresoc.v:76493.3-76544.6" wire width 2 $0\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76304.3-76355.6" + attribute \src "libresoc.v:76545.3-76596.6" wire width 2 $0\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:75628.3-75679.6" + attribute \src "libresoc.v:75869.3-75920.6" wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:75836.3-75887.6" + attribute \src "libresoc.v:76077.3-76128.6" wire $0\dec19_br[0:0] - attribute \src "libresoc.v:74952.3-75003.6" + attribute \src "libresoc.v:75193.3-75244.6" wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:75004.3-75055.6" + attribute \src "libresoc.v:75245.3-75296.6" wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:75576.3-75627.6" + attribute \src "libresoc.v:75817.3-75868.6" wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:75784.3-75835.6" + attribute \src "libresoc.v:76025.3-76076.6" wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:76044.3-76095.6" + attribute \src "libresoc.v:76285.3-76336.6" wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:74900.3-74951.6" + attribute \src "libresoc.v:75141.3-75192.6" wire width 13 $0\dec19_function_unit[12:0] - attribute \src "libresoc.v:76356.3-76407.6" + attribute \src "libresoc.v:76597.3-76648.6" wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:76408.3-76459.6" + attribute \src "libresoc.v:76649.3-76700.6" wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76460.3-76511.6" + attribute \src "libresoc.v:76701.3-76752.6" wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:75472.3-75523.6" + attribute \src "libresoc.v:75713.3-75764.6" wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:75680.3-75731.6" + attribute \src "libresoc.v:75921.3-75972.6" wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:75732.3-75783.6" + attribute \src "libresoc.v:75973.3-76024.6" wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:75992.3-76043.6" + attribute \src "libresoc.v:76233.3-76284.6" wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:75368.3-75419.6" + attribute \src "libresoc.v:75609.3-75660.6" wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76148.3-76199.6" + attribute \src "libresoc.v:76389.3-76440.6" wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:76512.3-76563.6" + attribute \src "libresoc.v:76753.3-76804.6" wire width 2 $0\dec19_out_sel[1:0] - attribute \src "libresoc.v:75524.3-75575.6" + attribute \src "libresoc.v:75765.3-75816.6" wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:75940.3-75991.6" + attribute \src "libresoc.v:76181.3-76232.6" wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:76200.3-76251.6" + attribute \src "libresoc.v:76441.3-76492.6" wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76096.3-76147.6" + attribute \src "libresoc.v:76337.3-76388.6" wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:75888.3-75939.6" + attribute \src "libresoc.v:76129.3-76180.6" wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:75264.3-75315.6" + attribute \src "libresoc.v:75505.3-75556.6" wire width 3 $0\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75316.3-75367.6" + attribute \src "libresoc.v:75557.3-75608.6" wire width 3 $0\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75056.3-75107.6" + attribute \src "libresoc.v:75297.3-75348.6" wire width 3 $0\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75108.3-75159.6" + attribute \src "libresoc.v:75349.3-75400.6" wire width 3 $0\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75160.3-75211.6" + attribute \src "libresoc.v:75401.3-75452.6" wire width 3 $0\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75212.3-75263.6" + attribute \src "libresoc.v:75453.3-75504.6" wire width 3 $0\dec19_sv_out[2:0] - attribute \src "libresoc.v:75420.3-75471.6" + attribute \src "libresoc.v:75661.3-75712.6" wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:74566.7-74566.20" + attribute \src "libresoc.v:74806.7-74806.20" wire $0\initial[0:0] - attribute \src "libresoc.v:76252.3-76303.6" + attribute \src "libresoc.v:76493.3-76544.6" wire width 2 $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76304.3-76355.6" + attribute \src "libresoc.v:76545.3-76596.6" wire width 2 $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:75628.3-75679.6" + attribute \src "libresoc.v:75869.3-75920.6" wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:75836.3-75887.6" + attribute \src "libresoc.v:76077.3-76128.6" wire $1\dec19_br[0:0] - attribute \src "libresoc.v:74952.3-75003.6" + attribute \src "libresoc.v:75193.3-75244.6" wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75004.3-75055.6" + attribute \src "libresoc.v:75245.3-75296.6" wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:75576.3-75627.6" + attribute \src "libresoc.v:75817.3-75868.6" wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:75784.3-75835.6" + attribute \src "libresoc.v:76025.3-76076.6" wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76044.3-76095.6" + attribute \src "libresoc.v:76285.3-76336.6" wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:74900.3-74951.6" + attribute \src "libresoc.v:75141.3-75192.6" wire width 13 $1\dec19_function_unit[12:0] - attribute \src "libresoc.v:76356.3-76407.6" + attribute \src "libresoc.v:76597.3-76648.6" wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:76408.3-76459.6" + attribute \src "libresoc.v:76649.3-76700.6" wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76460.3-76511.6" + attribute \src "libresoc.v:76701.3-76752.6" wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:75472.3-75523.6" + attribute \src "libresoc.v:75713.3-75764.6" wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:75680.3-75731.6" + attribute \src "libresoc.v:75921.3-75972.6" wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:75732.3-75783.6" + attribute \src "libresoc.v:75973.3-76024.6" wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:75992.3-76043.6" + attribute \src "libresoc.v:76233.3-76284.6" wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:75368.3-75419.6" + attribute \src "libresoc.v:75609.3-75660.6" wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76148.3-76199.6" + attribute \src "libresoc.v:76389.3-76440.6" wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:76512.3-76563.6" + attribute \src "libresoc.v:76753.3-76804.6" wire width 2 $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:75524.3-75575.6" + attribute \src "libresoc.v:75765.3-75816.6" wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:75940.3-75991.6" + attribute \src "libresoc.v:76181.3-76232.6" wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76200.3-76251.6" + attribute \src "libresoc.v:76441.3-76492.6" wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76096.3-76147.6" + attribute \src "libresoc.v:76337.3-76388.6" wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:75888.3-75939.6" + attribute \src "libresoc.v:76129.3-76180.6" wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:75264.3-75315.6" + attribute \src "libresoc.v:75505.3-75556.6" wire width 3 $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75316.3-75367.6" + attribute \src "libresoc.v:75557.3-75608.6" wire width 3 $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75056.3-75107.6" + attribute \src "libresoc.v:75297.3-75348.6" wire width 3 $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75108.3-75159.6" + attribute \src "libresoc.v:75349.3-75400.6" wire width 3 $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75160.3-75211.6" + attribute \src "libresoc.v:75401.3-75452.6" wire width 3 $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75212.3-75263.6" + attribute \src "libresoc.v:75453.3-75504.6" wire width 3 $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:75420.3-75471.6" + attribute \src "libresoc.v:75661.3-75712.6" wire width 2 $1\dec19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -119740,6 +120240,7 @@ module \dec19 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec19_form attribute \enum_base_type "Function" @@ -119963,28 +120464,28 @@ module \dec19 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec19_upd - attribute \src "libresoc.v:74566.7-74566.15" + attribute \src "libresoc.v:74806.7-74806.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch - attribute \src "libresoc.v:74566.7-74566.20" - process $proc$libresoc.v:74566$3634 + attribute \src "libresoc.v:74806.7-74806.20" + process $proc$libresoc.v:74806$3646 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:74900.3-74951.6" - process $proc$libresoc.v:74900$3602 + attribute \src "libresoc.v:75141.3-75192.6" + process $proc$libresoc.v:75141$3614 assign { } { } assign { } { } assign $0\dec19_function_unit[12:0] $1\dec19_function_unit[12:0] - attribute \src "libresoc.v:74901.5-74901.29" + attribute \src "libresoc.v:75142.5-75142.29" switch \initial - attribute \src "libresoc.v:74901.9-74901.17" + attribute \src "libresoc.v:75142.9-75142.17" case 1'1 case end @@ -120056,14 +120557,14 @@ module \dec19 sync always update \dec19_function_unit $0\dec19_function_unit[12:0] end - attribute \src "libresoc.v:74952.3-75003.6" - process $proc$libresoc.v:74952$3603 + attribute \src "libresoc.v:75193.3-75244.6" + process $proc$libresoc.v:75193$3615 assign { } { } assign { } { } assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:74953.5-74953.29" + attribute \src "libresoc.v:75194.5-75194.29" switch \initial - attribute \src "libresoc.v:74953.9-74953.17" + attribute \src "libresoc.v:75194.9-75194.17" case 1'1 case end @@ -120135,14 +120636,14 @@ module \dec19 sync always update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "libresoc.v:75004.3-75055.6" - process $proc$libresoc.v:75004$3604 + attribute \src "libresoc.v:75245.3-75296.6" + process $proc$libresoc.v:75245$3616 assign { } { } assign { } { } assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:75005.5-75005.29" + attribute \src "libresoc.v:75246.5-75246.29" switch \initial - attribute \src "libresoc.v:75005.9-75005.17" + attribute \src "libresoc.v:75246.9-75246.17" case 1'1 case end @@ -120214,14 +120715,14 @@ module \dec19 sync always update \dec19_cr_out $0\dec19_cr_out[2:0] end - attribute \src "libresoc.v:75056.3-75107.6" - process $proc$libresoc.v:75056$3605 + attribute \src "libresoc.v:75297.3-75348.6" + process $proc$libresoc.v:75297$3617 assign { } { } assign { } { } assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75057.5-75057.29" + attribute \src "libresoc.v:75298.5-75298.29" switch \initial - attribute \src "libresoc.v:75057.9-75057.17" + attribute \src "libresoc.v:75298.9-75298.17" case 1'1 case end @@ -120293,14 +120794,14 @@ module \dec19 sync always update \dec19_sv_in1 $0\dec19_sv_in1[2:0] end - attribute \src "libresoc.v:75108.3-75159.6" - process $proc$libresoc.v:75108$3606 + attribute \src "libresoc.v:75349.3-75400.6" + process $proc$libresoc.v:75349$3618 assign { } { } assign { } { } assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75109.5-75109.29" + attribute \src "libresoc.v:75350.5-75350.29" switch \initial - attribute \src "libresoc.v:75109.9-75109.17" + attribute \src "libresoc.v:75350.9-75350.17" case 1'1 case end @@ -120372,14 +120873,14 @@ module \dec19 sync always update \dec19_sv_in2 $0\dec19_sv_in2[2:0] end - attribute \src "libresoc.v:75160.3-75211.6" - process $proc$libresoc.v:75160$3607 + attribute \src "libresoc.v:75401.3-75452.6" + process $proc$libresoc.v:75401$3619 assign { } { } assign { } { } assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75161.5-75161.29" + attribute \src "libresoc.v:75402.5-75402.29" switch \initial - attribute \src "libresoc.v:75161.9-75161.17" + attribute \src "libresoc.v:75402.9-75402.17" case 1'1 case end @@ -120451,14 +120952,14 @@ module \dec19 sync always update \dec19_sv_in3 $0\dec19_sv_in3[2:0] end - attribute \src "libresoc.v:75212.3-75263.6" - process $proc$libresoc.v:75212$3608 + attribute \src "libresoc.v:75453.3-75504.6" + process $proc$libresoc.v:75453$3620 assign { } { } assign { } { } assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:75213.5-75213.29" + attribute \src "libresoc.v:75454.5-75454.29" switch \initial - attribute \src "libresoc.v:75213.9-75213.17" + attribute \src "libresoc.v:75454.9-75454.17" case 1'1 case end @@ -120530,14 +121031,14 @@ module \dec19 sync always update \dec19_sv_out $0\dec19_sv_out[2:0] end - attribute \src "libresoc.v:75264.3-75315.6" - process $proc$libresoc.v:75264$3609 + attribute \src "libresoc.v:75505.3-75556.6" + process $proc$libresoc.v:75505$3621 assign { } { } assign { } { } assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:75265.5-75265.29" + attribute \src "libresoc.v:75506.5-75506.29" switch \initial - attribute \src "libresoc.v:75265.9-75265.17" + attribute \src "libresoc.v:75506.9-75506.17" case 1'1 case end @@ -120609,14 +121110,14 @@ module \dec19 sync always update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] end - attribute \src "libresoc.v:75316.3-75367.6" - process $proc$libresoc.v:75316$3610 + attribute \src "libresoc.v:75557.3-75608.6" + process $proc$libresoc.v:75557$3622 assign { } { } assign { } { } assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75317.5-75317.29" + attribute \src "libresoc.v:75558.5-75558.29" switch \initial - attribute \src "libresoc.v:75317.9-75317.17" + attribute \src "libresoc.v:75558.9-75558.17" case 1'1 case end @@ -120688,14 +121189,14 @@ module \dec19 sync always update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] end - attribute \src "libresoc.v:75368.3-75419.6" - process $proc$libresoc.v:75368$3611 + attribute \src "libresoc.v:75609.3-75660.6" + process $proc$libresoc.v:75609$3623 assign { } { } assign { } { } assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:75369.5-75369.29" + attribute \src "libresoc.v:75610.5-75610.29" switch \initial - attribute \src "libresoc.v:75369.9-75369.17" + attribute \src "libresoc.v:75610.9-75610.17" case 1'1 case end @@ -120767,14 +121268,14 @@ module \dec19 sync always update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "libresoc.v:75420.3-75471.6" - process $proc$libresoc.v:75420$3612 + attribute \src "libresoc.v:75661.3-75712.6" + process $proc$libresoc.v:75661$3624 assign { } { } assign { } { } assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:75421.5-75421.29" + attribute \src "libresoc.v:75662.5-75662.29" switch \initial - attribute \src "libresoc.v:75421.9-75421.17" + attribute \src "libresoc.v:75662.9-75662.17" case 1'1 case end @@ -120846,14 +121347,14 @@ module \dec19 sync always update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "libresoc.v:75472.3-75523.6" - process $proc$libresoc.v:75472$3613 + attribute \src "libresoc.v:75713.3-75764.6" + process $proc$libresoc.v:75713$3625 assign { } { } assign { } { } assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:75473.5-75473.29" + attribute \src "libresoc.v:75714.5-75714.29" switch \initial - attribute \src "libresoc.v:75473.9-75473.17" + attribute \src "libresoc.v:75714.9-75714.17" case 1'1 case end @@ -120925,14 +121426,14 @@ module \dec19 sync always update \dec19_internal_op $0\dec19_internal_op[6:0] end - attribute \src "libresoc.v:75524.3-75575.6" - process $proc$libresoc.v:75524$3614 + attribute \src "libresoc.v:75765.3-75816.6" + process $proc$libresoc.v:75765$3626 assign { } { } assign { } { } assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:75525.5-75525.29" + attribute \src "libresoc.v:75766.5-75766.29" switch \initial - attribute \src "libresoc.v:75525.9-75525.17" + attribute \src "libresoc.v:75766.9-75766.17" case 1'1 case end @@ -121004,14 +121505,14 @@ module \dec19 sync always update \dec19_rc_sel $0\dec19_rc_sel[1:0] end - attribute \src "libresoc.v:75576.3-75627.6" - process $proc$libresoc.v:75576$3615 + attribute \src "libresoc.v:75817.3-75868.6" + process $proc$libresoc.v:75817$3627 assign { } { } assign { } { } assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:75577.5-75577.29" + attribute \src "libresoc.v:75818.5-75818.29" switch \initial - attribute \src "libresoc.v:75577.9-75577.17" + attribute \src "libresoc.v:75818.9-75818.17" case 1'1 case end @@ -121083,14 +121584,14 @@ module \dec19 sync always update \dec19_cry_in $0\dec19_cry_in[1:0] end - attribute \src "libresoc.v:75628.3-75679.6" - process $proc$libresoc.v:75628$3616 + attribute \src "libresoc.v:75869.3-75920.6" + process $proc$libresoc.v:75869$3628 assign { } { } assign { } { } assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:75629.5-75629.29" + attribute \src "libresoc.v:75870.5-75870.29" switch \initial - attribute \src "libresoc.v:75629.9-75629.17" + attribute \src "libresoc.v:75870.9-75870.17" case 1'1 case end @@ -121162,14 +121663,14 @@ module \dec19 sync always update \dec19_asmcode $0\dec19_asmcode[7:0] end - attribute \src "libresoc.v:75680.3-75731.6" - process $proc$libresoc.v:75680$3617 + attribute \src "libresoc.v:75921.3-75972.6" + process $proc$libresoc.v:75921$3629 assign { } { } assign { } { } assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:75681.5-75681.29" + attribute \src "libresoc.v:75922.5-75922.29" switch \initial - attribute \src "libresoc.v:75681.9-75681.17" + attribute \src "libresoc.v:75922.9-75922.17" case 1'1 case end @@ -121241,14 +121742,14 @@ module \dec19 sync always update \dec19_inv_a $0\dec19_inv_a[0:0] end - attribute \src "libresoc.v:75732.3-75783.6" - process $proc$libresoc.v:75732$3618 + attribute \src "libresoc.v:75973.3-76024.6" + process $proc$libresoc.v:75973$3630 assign { } { } assign { } { } assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:75733.5-75733.29" + attribute \src "libresoc.v:75974.5-75974.29" switch \initial - attribute \src "libresoc.v:75733.9-75733.17" + attribute \src "libresoc.v:75974.9-75974.17" case 1'1 case end @@ -121320,14 +121821,14 @@ module \dec19 sync always update \dec19_inv_out $0\dec19_inv_out[0:0] end - attribute \src "libresoc.v:75784.3-75835.6" - process $proc$libresoc.v:75784$3619 + attribute \src "libresoc.v:76025.3-76076.6" + process $proc$libresoc.v:76025$3631 assign { } { } assign { } { } assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:75785.5-75785.29" + attribute \src "libresoc.v:76026.5-76026.29" switch \initial - attribute \src "libresoc.v:75785.9-75785.17" + attribute \src "libresoc.v:76026.9-76026.17" case 1'1 case end @@ -121399,14 +121900,14 @@ module \dec19 sync always update \dec19_cry_out $0\dec19_cry_out[0:0] end - attribute \src "libresoc.v:75836.3-75887.6" - process $proc$libresoc.v:75836$3620 + attribute \src "libresoc.v:76077.3-76128.6" + process $proc$libresoc.v:76077$3632 assign { } { } assign { } { } assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:75837.5-75837.29" + attribute \src "libresoc.v:76078.5-76078.29" switch \initial - attribute \src "libresoc.v:75837.9-75837.17" + attribute \src "libresoc.v:76078.9-76078.17" case 1'1 case end @@ -121478,14 +121979,14 @@ module \dec19 sync always update \dec19_br $0\dec19_br[0:0] end - attribute \src "libresoc.v:75888.3-75939.6" - process $proc$libresoc.v:75888$3621 + attribute \src "libresoc.v:76129.3-76180.6" + process $proc$libresoc.v:76129$3633 assign { } { } assign { } { } assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:75889.5-75889.29" + attribute \src "libresoc.v:76130.5-76130.29" switch \initial - attribute \src "libresoc.v:75889.9-75889.17" + attribute \src "libresoc.v:76130.9-76130.17" case 1'1 case end @@ -121557,14 +122058,14 @@ module \dec19 sync always update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] end - attribute \src "libresoc.v:75940.3-75991.6" - process $proc$libresoc.v:75940$3622 + attribute \src "libresoc.v:76181.3-76232.6" + process $proc$libresoc.v:76181$3634 assign { } { } assign { } { } assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:75941.5-75941.29" + attribute \src "libresoc.v:76182.5-76182.29" switch \initial - attribute \src "libresoc.v:75941.9-75941.17" + attribute \src "libresoc.v:76182.9-76182.17" case 1'1 case end @@ -121636,14 +122137,14 @@ module \dec19 sync always update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "libresoc.v:75992.3-76043.6" - process $proc$libresoc.v:75992$3623 + attribute \src "libresoc.v:76233.3-76284.6" + process $proc$libresoc.v:76233$3635 assign { } { } assign { } { } assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:75993.5-75993.29" + attribute \src "libresoc.v:76234.5-76234.29" switch \initial - attribute \src "libresoc.v:75993.9-75993.17" + attribute \src "libresoc.v:76234.9-76234.17" case 1'1 case end @@ -121715,14 +122216,14 @@ module \dec19 sync always update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "libresoc.v:76044.3-76095.6" - process $proc$libresoc.v:76044$3624 + attribute \src "libresoc.v:76285.3-76336.6" + process $proc$libresoc.v:76285$3636 assign { } { } assign { } { } assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:76045.5-76045.29" + attribute \src "libresoc.v:76286.5-76286.29" switch \initial - attribute \src "libresoc.v:76045.9-76045.17" + attribute \src "libresoc.v:76286.9-76286.17" case 1'1 case end @@ -121794,14 +122295,14 @@ module \dec19 sync always update \dec19_form $0\dec19_form[4:0] end - attribute \src "libresoc.v:76096.3-76147.6" - process $proc$libresoc.v:76096$3625 + attribute \src "libresoc.v:76337.3-76388.6" + process $proc$libresoc.v:76337$3637 assign { } { } assign { } { } assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76097.5-76097.29" + attribute \src "libresoc.v:76338.5-76338.29" switch \initial - attribute \src "libresoc.v:76097.9-76097.17" + attribute \src "libresoc.v:76338.9-76338.17" case 1'1 case end @@ -121873,14 +122374,14 @@ module \dec19 sync always update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "libresoc.v:76148.3-76199.6" - process $proc$libresoc.v:76148$3626 + attribute \src "libresoc.v:76389.3-76440.6" + process $proc$libresoc.v:76389$3638 assign { } { } assign { } { } assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:76149.5-76149.29" + attribute \src "libresoc.v:76390.5-76390.29" switch \initial - attribute \src "libresoc.v:76149.9-76149.17" + attribute \src "libresoc.v:76390.9-76390.17" case 1'1 case end @@ -121952,14 +122453,14 @@ module \dec19 sync always update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "libresoc.v:76200.3-76251.6" - process $proc$libresoc.v:76200$3627 + attribute \src "libresoc.v:76441.3-76492.6" + process $proc$libresoc.v:76441$3639 assign { } { } assign { } { } assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76201.5-76201.29" + attribute \src "libresoc.v:76442.5-76442.29" switch \initial - attribute \src "libresoc.v:76201.9-76201.17" + attribute \src "libresoc.v:76442.9-76442.17" case 1'1 case end @@ -122031,14 +122532,14 @@ module \dec19 sync always update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "libresoc.v:76252.3-76303.6" - process $proc$libresoc.v:76252$3628 + attribute \src "libresoc.v:76493.3-76544.6" + process $proc$libresoc.v:76493$3640 assign { } { } assign { } { } assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:76253.5-76253.29" + attribute \src "libresoc.v:76494.5-76494.29" switch \initial - attribute \src "libresoc.v:76253.9-76253.17" + attribute \src "libresoc.v:76494.9-76494.17" case 1'1 case end @@ -122110,14 +122611,14 @@ module \dec19 sync always update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] end - attribute \src "libresoc.v:76304.3-76355.6" - process $proc$libresoc.v:76304$3629 + attribute \src "libresoc.v:76545.3-76596.6" + process $proc$libresoc.v:76545$3641 assign { } { } assign { } { } assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76305.5-76305.29" + attribute \src "libresoc.v:76546.5-76546.29" switch \initial - attribute \src "libresoc.v:76305.9-76305.17" + attribute \src "libresoc.v:76546.9-76546.17" case 1'1 case end @@ -122189,14 +122690,14 @@ module \dec19 sync always update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] end - attribute \src "libresoc.v:76356.3-76407.6" - process $proc$libresoc.v:76356$3630 + attribute \src "libresoc.v:76597.3-76648.6" + process $proc$libresoc.v:76597$3642 assign { } { } assign { } { } assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:76357.5-76357.29" + attribute \src "libresoc.v:76598.5-76598.29" switch \initial - attribute \src "libresoc.v:76357.9-76357.17" + attribute \src "libresoc.v:76598.9-76598.17" case 1'1 case end @@ -122268,14 +122769,14 @@ module \dec19 sync always update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "libresoc.v:76408.3-76459.6" - process $proc$libresoc.v:76408$3631 + attribute \src "libresoc.v:76649.3-76700.6" + process $proc$libresoc.v:76649$3643 assign { } { } assign { } { } assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:76409.5-76409.29" + attribute \src "libresoc.v:76650.5-76650.29" switch \initial - attribute \src "libresoc.v:76409.9-76409.17" + attribute \src "libresoc.v:76650.9-76650.17" case 1'1 case end @@ -122347,14 +122848,14 @@ module \dec19 sync always update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "libresoc.v:76460.3-76511.6" - process $proc$libresoc.v:76460$3632 + attribute \src "libresoc.v:76701.3-76752.6" + process $proc$libresoc.v:76701$3644 assign { } { } assign { } { } assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:76461.5-76461.29" + attribute \src "libresoc.v:76702.5-76702.29" switch \initial - attribute \src "libresoc.v:76461.9-76461.17" + attribute \src "libresoc.v:76702.9-76702.17" case 1'1 case end @@ -122426,14 +122927,14 @@ module \dec19 sync always update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "libresoc.v:76512.3-76563.6" - process $proc$libresoc.v:76512$3633 + attribute \src "libresoc.v:76753.3-76804.6" + process $proc$libresoc.v:76753$3645 assign { } { } assign { } { } assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:76513.5-76513.29" + attribute \src "libresoc.v:76754.5-76754.29" switch \initial - attribute \src "libresoc.v:76513.9-76513.17" + attribute \src "libresoc.v:76754.9-76754.17" case 1'1 case end @@ -122507,817 +123008,1005 @@ module \dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:76569.1-79231.10" +attribute \src "libresoc.v:76810.1-79734.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" module \dec2 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:79028.3-79037.6" + attribute \src "libresoc.v:79508.3-79517.6" wire width 3 $0\cr_a_idx[2:0] - attribute \src "libresoc.v:79038.3-79047.6" + attribute \src "libresoc.v:79518.3-79527.6" wire width 3 $0\cr_b_idx[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $0\cr_in1[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire width 7 $0\cr_in2$1[6:0]$3673 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire width 7 $0\cr_in2$1[6:0]$3727 + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $0\cr_in2[6:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire $0\cr_in2_ok$2[0:0]$3674 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire $0\cr_in2_ok$2[0:0]$3728 + attribute \src "libresoc.v:79340.3-79497.6" wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $0\ea[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\ea_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire $0\exc_$signal$3[0:0]$3676 - attribute \src "libresoc.v:78848.3-79005.6" - wire $0\exc_$signal$4[0:0]$3677 - attribute \src "libresoc.v:78848.3-79005.6" - wire $0\exc_$signal$5[0:0]$3678 - attribute \src "libresoc.v:78848.3-79005.6" - wire $0\exc_$signal$6[0:0]$3679 - attribute \src "libresoc.v:78848.3-79005.6" - wire $0\exc_$signal$7[0:0]$3680 - attribute \src "libresoc.v:78848.3-79005.6" - wire $0\exc_$signal$8[0:0]$3681 - attribute \src "libresoc.v:78848.3-79005.6" - wire $0\exc_$signal$9[0:0]$3682 - attribute \src "libresoc.v:78848.3-79005.6" - wire $0\exc_$signal[0:0]$3675 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire $0\exc_$signal$3[0:0]$3730 + attribute \src "libresoc.v:79340.3-79497.6" + wire $0\exc_$signal$4[0:0]$3731 + attribute \src "libresoc.v:79340.3-79497.6" + wire $0\exc_$signal$5[0:0]$3732 + attribute \src "libresoc.v:79340.3-79497.6" + wire $0\exc_$signal$6[0:0]$3733 + attribute \src "libresoc.v:79340.3-79497.6" + wire $0\exc_$signal$7[0:0]$3734 + attribute \src "libresoc.v:79340.3-79497.6" + wire $0\exc_$signal$8[0:0]$3735 + attribute \src "libresoc.v:79340.3-79497.6" + wire $0\exc_$signal$9[0:0]$3736 + attribute \src "libresoc.v:79340.3-79497.6" + wire $0\exc_$signal[0:0]$3729 + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 13 $0\fn_unit[12:0] - attribute \src "libresoc.v:76570.7-76570.20" + attribute \src "libresoc.v:76811.7-76811.20" wire $0\initial[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:78824.3-78847.6" + attribute \src "libresoc.v:79316.3-79339.6" wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\lk[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\oe[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\rc[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $0\reg1[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $0\reg2[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $0\reg3[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $0\rego[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\rego_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\spro_ok[0:0] - attribute \src "libresoc.v:79096.3-79107.6" + attribute \src "libresoc.v:79173.3-79195.6" + wire width 7 $0\tmp_cr_in1[6:0] + attribute \src "libresoc.v:79234.3-79256.6" + wire width 7 $0\tmp_cr_in2$19[6:0]$3718 + attribute \src "libresoc.v:79196.3-79218.6" + wire width 7 $0\tmp_cr_in2[6:0] + attribute \src "libresoc.v:79257.3-79279.6" + wire width 7 $0\tmp_cr_out[6:0] + attribute \src "libresoc.v:79589.3-79600.6" wire width 7 $0\tmp_ea[6:0] - attribute \src "libresoc.v:79048.3-79059.6" + attribute \src "libresoc.v:79528.3-79539.6" wire width 7 $0\tmp_reg1[6:0] - attribute \src "libresoc.v:79060.3-79071.6" + attribute \src "libresoc.v:79540.3-79551.6" wire width 7 $0\tmp_reg2[6:0] - attribute \src "libresoc.v:79072.3-79083.6" + attribute \src "libresoc.v:79552.3-79563.6" wire width 7 $0\tmp_reg3[6:0] - attribute \src "libresoc.v:79084.3-79095.6" + attribute \src "libresoc.v:79577.3-79588.6" wire width 7 $0\tmp_rego[6:0] - attribute \src "libresoc.v:79006.3-79017.6" + attribute \src "libresoc.v:79219.3-79233.6" wire width 13 $0\tmp_tmp_fn_unit[12:0] - attribute \src "libresoc.v:79018.3-79027.6" + attribute \src "libresoc.v:79564.3-79576.6" + wire width 7 $0\tmp_tmp_insn_type[6:0] + attribute \src "libresoc.v:79498.3-79507.6" wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78814.3-78823.6" + attribute \src "libresoc.v:79306.3-79315.6" wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78788.3-78803.6" + attribute \src "libresoc.v:79280.3-79295.6" wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:78804.3-78813.6" + attribute \src "libresoc.v:79296.3-79305.6" wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $0\traptype[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $0\xer_out[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:79028.3-79037.6" + attribute \src "libresoc.v:79508.3-79517.6" wire width 3 $1\cr_a_idx[2:0] - attribute \src "libresoc.v:79038.3-79047.6" + attribute \src "libresoc.v:79518.3-79527.6" wire width 3 $1\cr_b_idx[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $1\cr_in1[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire width 7 $1\cr_in2$1[6:0]$3683 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire width 7 $1\cr_in2$1[6:0]$3737 + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $1\cr_in2[6:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire $1\cr_in2_ok$2[0:0]$3684 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire $1\cr_in2_ok$2[0:0]$3738 + attribute \src "libresoc.v:79340.3-79497.6" wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $1\ea[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\ea_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire $1\exc_$signal$3[0:0]$3686 - attribute \src "libresoc.v:78848.3-79005.6" - wire $1\exc_$signal$4[0:0]$3687 - attribute \src "libresoc.v:78848.3-79005.6" - wire $1\exc_$signal$5[0:0]$3688 - attribute \src "libresoc.v:78848.3-79005.6" - wire $1\exc_$signal$6[0:0]$3689 - attribute \src "libresoc.v:78848.3-79005.6" - wire $1\exc_$signal$7[0:0]$3690 - attribute \src "libresoc.v:78848.3-79005.6" - wire $1\exc_$signal$8[0:0]$3691 - attribute \src "libresoc.v:78848.3-79005.6" - wire $1\exc_$signal$9[0:0]$3692 - attribute \src "libresoc.v:78848.3-79005.6" - wire $1\exc_$signal[0:0]$3685 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire $1\exc_$signal$3[0:0]$3740 + attribute \src "libresoc.v:79340.3-79497.6" + wire $1\exc_$signal$4[0:0]$3741 + attribute \src "libresoc.v:79340.3-79497.6" + wire $1\exc_$signal$5[0:0]$3742 + attribute \src "libresoc.v:79340.3-79497.6" + wire $1\exc_$signal$6[0:0]$3743 + attribute \src "libresoc.v:79340.3-79497.6" + wire $1\exc_$signal$7[0:0]$3744 + attribute \src "libresoc.v:79340.3-79497.6" + wire $1\exc_$signal$8[0:0]$3745 + attribute \src "libresoc.v:79340.3-79497.6" + wire $1\exc_$signal$9[0:0]$3746 + attribute \src "libresoc.v:79340.3-79497.6" + wire $1\exc_$signal[0:0]$3739 + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 13 $1\fn_unit[12:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:78824.3-78847.6" + attribute \src "libresoc.v:79316.3-79339.6" wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\lk[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\oe[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\rc[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\rc_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $1\reg1[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $1\reg2[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $1\reg3[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $1\rego[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\rego_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\spro_ok[0:0] - attribute \src "libresoc.v:79096.3-79107.6" + attribute \src "libresoc.v:79173.3-79195.6" + wire width 7 $1\tmp_cr_in1[6:0] + attribute \src "libresoc.v:79234.3-79256.6" + wire width 7 $1\tmp_cr_in2$19[6:0]$3719 + attribute \src "libresoc.v:79196.3-79218.6" + wire width 7 $1\tmp_cr_in2[6:0] + attribute \src "libresoc.v:79257.3-79279.6" + wire width 7 $1\tmp_cr_out[6:0] + attribute \src "libresoc.v:79589.3-79600.6" wire width 7 $1\tmp_ea[6:0] - attribute \src "libresoc.v:79048.3-79059.6" + attribute \src "libresoc.v:79528.3-79539.6" wire width 7 $1\tmp_reg1[6:0] - attribute \src "libresoc.v:79060.3-79071.6" + attribute \src "libresoc.v:79540.3-79551.6" wire width 7 $1\tmp_reg2[6:0] - attribute \src "libresoc.v:79072.3-79083.6" + attribute \src "libresoc.v:79552.3-79563.6" wire width 7 $1\tmp_reg3[6:0] - attribute \src "libresoc.v:79084.3-79095.6" + attribute \src "libresoc.v:79577.3-79588.6" wire width 7 $1\tmp_rego[6:0] - attribute \src "libresoc.v:79006.3-79017.6" + attribute \src "libresoc.v:79219.3-79233.6" wire width 13 $1\tmp_tmp_fn_unit[12:0] - attribute \src "libresoc.v:79018.3-79027.6" + attribute \src "libresoc.v:79564.3-79576.6" + wire width 7 $1\tmp_tmp_insn_type[6:0] + attribute \src "libresoc.v:79498.3-79507.6" wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:78814.3-78823.6" + attribute \src "libresoc.v:79306.3-79315.6" wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78788.3-78803.6" + attribute \src "libresoc.v:79280.3-79295.6" wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:78804.3-78813.6" + attribute \src "libresoc.v:79296.3-79305.6" wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $1\traptype[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $1\xer_out[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 64 $2\cia[63:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $2\cr_in1[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\cr_in1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire width 7 $2\cr_in2$1[6:0]$3693 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire width 7 $2\cr_in2$1[6:0]$3747 + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $2\cr_in2[6:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire $2\cr_in2_ok$2[0:0]$3694 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire $2\cr_in2_ok$2[0:0]$3748 + attribute \src "libresoc.v:79340.3-79497.6" wire $2\cr_in2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $2\cr_out[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\cr_out_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $2\cr_rd[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\cr_rd_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $2\cr_wr[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\cr_wr_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $2\ea[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\ea_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire $2\exc_$signal$3[0:0]$3696 - attribute \src "libresoc.v:78848.3-79005.6" - wire $2\exc_$signal$4[0:0]$3697 - attribute \src "libresoc.v:78848.3-79005.6" - wire $2\exc_$signal$5[0:0]$3698 - attribute \src "libresoc.v:78848.3-79005.6" - wire $2\exc_$signal$6[0:0]$3699 - attribute \src "libresoc.v:78848.3-79005.6" - wire $2\exc_$signal$7[0:0]$3700 - attribute \src "libresoc.v:78848.3-79005.6" - wire $2\exc_$signal$8[0:0]$3701 - attribute \src "libresoc.v:78848.3-79005.6" - wire $2\exc_$signal$9[0:0]$3702 - attribute \src "libresoc.v:78848.3-79005.6" - wire $2\exc_$signal[0:0]$3695 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire $2\exc_$signal$3[0:0]$3750 + attribute \src "libresoc.v:79340.3-79497.6" + wire $2\exc_$signal$4[0:0]$3751 + attribute \src "libresoc.v:79340.3-79497.6" + wire $2\exc_$signal$5[0:0]$3752 + attribute \src "libresoc.v:79340.3-79497.6" + wire $2\exc_$signal$6[0:0]$3753 + attribute \src "libresoc.v:79340.3-79497.6" + wire $2\exc_$signal$7[0:0]$3754 + attribute \src "libresoc.v:79340.3-79497.6" + wire $2\exc_$signal$8[0:0]$3755 + attribute \src "libresoc.v:79340.3-79497.6" + wire $2\exc_$signal$9[0:0]$3756 + attribute \src "libresoc.v:79340.3-79497.6" + wire $2\exc_$signal[0:0]$3749 + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $2\fasto1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\fasto1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $2\fasto2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\fasto2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 13 $2\fn_unit[12:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 2 $2\input_carry[1:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 32 $2\insn[31:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $2\insn_type[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\is_32bit[0:0] - attribute \src "libresoc.v:78824.3-78847.6" + attribute \src "libresoc.v:79316.3-79339.6" wire $2\is_priv_insn[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\lk[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\oe[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\oe_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\rc[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\rc_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $2\reg1[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\reg1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $2\reg2[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\reg2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $2\reg3[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\reg3_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $2\rego[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\rego_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 10 $2\spr1[9:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 10 $2\spro[9:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\spro_ok[0:0] - attribute \src "libresoc.v:78788.3-78803.6" + attribute \src "libresoc.v:79173.3-79195.6" + wire width 7 $2\tmp_cr_in1[6:0] + attribute \src "libresoc.v:79234.3-79256.6" + wire width 7 $2\tmp_cr_in2$19[6:0]$3720 + attribute \src "libresoc.v:79196.3-79218.6" + wire width 7 $2\tmp_cr_in2[6:0] + attribute \src "libresoc.v:79257.3-79279.6" + wire width 7 $2\tmp_cr_out[6:0] + attribute \src "libresoc.v:79280.3-79295.6" wire width 3 $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 13 $2\trapaddr[12:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $2\traptype[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $2\xer_in[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $2\xer_out[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $3\asmcode[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 64 $3\cia[63:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $3\cr_in1[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\cr_in1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire width 7 $3\cr_in2$1[6:0]$3703 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire width 7 $3\cr_in2$1[6:0]$3757 + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $3\cr_in2[6:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire $3\cr_in2_ok$2[0:0]$3704 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire $3\cr_in2_ok$2[0:0]$3758 + attribute \src "libresoc.v:79340.3-79497.6" wire $3\cr_in2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $3\cr_out[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\cr_out_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $3\cr_rd[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\cr_rd_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $3\cr_wr[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\cr_wr_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $3\ea[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\ea_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire $3\exc_$signal$3[0:0]$3706 - attribute \src "libresoc.v:78848.3-79005.6" - wire $3\exc_$signal$4[0:0]$3707 - attribute \src "libresoc.v:78848.3-79005.6" - wire $3\exc_$signal$5[0:0]$3708 - attribute \src "libresoc.v:78848.3-79005.6" - wire $3\exc_$signal$6[0:0]$3709 - attribute \src "libresoc.v:78848.3-79005.6" - wire $3\exc_$signal$7[0:0]$3710 - attribute \src "libresoc.v:78848.3-79005.6" - wire $3\exc_$signal$8[0:0]$3711 - attribute \src "libresoc.v:78848.3-79005.6" - wire $3\exc_$signal$9[0:0]$3712 - attribute \src "libresoc.v:78848.3-79005.6" - wire $3\exc_$signal[0:0]$3705 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire $3\exc_$signal$3[0:0]$3760 + attribute \src "libresoc.v:79340.3-79497.6" + wire $3\exc_$signal$4[0:0]$3761 + attribute \src "libresoc.v:79340.3-79497.6" + wire $3\exc_$signal$5[0:0]$3762 + attribute \src "libresoc.v:79340.3-79497.6" + wire $3\exc_$signal$6[0:0]$3763 + attribute \src "libresoc.v:79340.3-79497.6" + wire $3\exc_$signal$7[0:0]$3764 + attribute \src "libresoc.v:79340.3-79497.6" + wire $3\exc_$signal$8[0:0]$3765 + attribute \src "libresoc.v:79340.3-79497.6" + wire $3\exc_$signal$9[0:0]$3766 + attribute \src "libresoc.v:79340.3-79497.6" + wire $3\exc_$signal[0:0]$3759 + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $3\fast1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\fast1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $3\fast2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\fast2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $3\fasto1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\fasto1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $3\fasto2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\fasto2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 13 $3\fn_unit[12:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 2 $3\input_carry[1:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 32 $3\insn[31:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $3\insn_type[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\is_32bit[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\lk[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 64 $3\msr[63:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\oe[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\oe_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\rc[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\rc_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $3\reg1[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\reg1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $3\reg2[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\reg2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $3\reg3[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\reg3_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $3\rego[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\rego_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 10 $3\spr1[9:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\spr1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 10 $3\spro[9:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\spro_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 13 $3\trapaddr[12:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $3\traptype[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $3\xer_in[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $3\xer_out[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $4\asmcode[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 64 $4\cia[63:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $4\cr_in1[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\cr_in1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire width 7 $4\cr_in2$1[6:0]$3713 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire width 7 $4\cr_in2$1[6:0]$3767 + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $4\cr_in2[6:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire $4\cr_in2_ok$2[0:0]$3714 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire $4\cr_in2_ok$2[0:0]$3768 + attribute \src "libresoc.v:79340.3-79497.6" wire $4\cr_in2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $4\cr_out[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\cr_out_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $4\cr_rd[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\cr_rd_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $4\cr_wr[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\cr_wr_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $4\ea[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\ea_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" - wire $4\exc_$signal$3[0:0]$3716 - attribute \src "libresoc.v:78848.3-79005.6" - wire $4\exc_$signal$4[0:0]$3717 - attribute \src "libresoc.v:78848.3-79005.6" - wire $4\exc_$signal$5[0:0]$3718 - attribute \src "libresoc.v:78848.3-79005.6" - wire $4\exc_$signal$6[0:0]$3719 - attribute \src "libresoc.v:78848.3-79005.6" - wire $4\exc_$signal$7[0:0]$3720 - attribute \src "libresoc.v:78848.3-79005.6" - wire $4\exc_$signal$8[0:0]$3721 - attribute \src "libresoc.v:78848.3-79005.6" - wire $4\exc_$signal$9[0:0]$3722 - attribute \src "libresoc.v:78848.3-79005.6" - wire $4\exc_$signal[0:0]$3715 - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" + wire $4\exc_$signal$3[0:0]$3770 + attribute \src "libresoc.v:79340.3-79497.6" + wire $4\exc_$signal$4[0:0]$3771 + attribute \src "libresoc.v:79340.3-79497.6" + wire $4\exc_$signal$5[0:0]$3772 + attribute \src "libresoc.v:79340.3-79497.6" + wire $4\exc_$signal$6[0:0]$3773 + attribute \src "libresoc.v:79340.3-79497.6" + wire $4\exc_$signal$7[0:0]$3774 + attribute \src "libresoc.v:79340.3-79497.6" + wire $4\exc_$signal$8[0:0]$3775 + attribute \src "libresoc.v:79340.3-79497.6" + wire $4\exc_$signal$9[0:0]$3776 + attribute \src "libresoc.v:79340.3-79497.6" + wire $4\exc_$signal[0:0]$3769 + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $4\fast1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\fast1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $4\fast2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\fast2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $4\fasto1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\fasto1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $4\fasto2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\fasto2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 13 $4\fn_unit[12:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 2 $4\input_carry[1:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 32 $4\insn[31:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $4\insn_type[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\is_32bit[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\lk[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 64 $4\msr[63:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\oe[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\oe_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\rc[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\rc_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $4\reg1[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\reg1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $4\reg2[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\reg2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $4\reg3[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\reg3_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 7 $4\rego[6:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\rego_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 10 $4\spr1[9:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\spr1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 10 $4\spro[9:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\spro_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 13 $4\trapaddr[12:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 8 $4\traptype[7:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $4\xer_in[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $4\xer_out[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $5\fast1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $5\fast1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $5\fast2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $5\fast2_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $5\fasto1[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $5\fasto1_ok[0:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire width 3 $5\fasto2[2:0] - attribute \src "libresoc.v:78848.3-79005.6" + attribute \src "libresoc.v:79340.3-79497.6" wire $5\fasto2_ok[0:0] - attribute \src "libresoc.v:78556.18-78556.126" - wire width 8 $add$libresoc.v:78556$3655_Y - attribute \src "libresoc.v:78557.18-78557.126" - wire width 8 $add$libresoc.v:78557$3656_Y - attribute \src "libresoc.v:78558.18-78558.126" - wire width 8 $add$libresoc.v:78558$3657_Y - attribute \src "libresoc.v:78559.18-78559.124" - wire width 8 $add$libresoc.v:78559$3658_Y - attribute \src "libresoc.v:78560.18-78560.125" - wire width 8 $add$libresoc.v:78560$3659_Y - attribute \src "libresoc.v:78536.18-78536.124" - wire $and$libresoc.v:78536$3635_Y - attribute \src "libresoc.v:78537.19-78537.126" - wire $and$libresoc.v:78537$3636_Y - attribute \src "libresoc.v:78553.18-78553.110" - wire $and$libresoc.v:78553$3652_Y - attribute \src "libresoc.v:78563.18-78563.111" - wire $and$libresoc.v:78563$3662_Y - attribute \src "libresoc.v:78568.18-78568.121" - wire $and$libresoc.v:78568$3667_Y - attribute \src "libresoc.v:78538.19-78538.124" - wire $eq$libresoc.v:78538$3637_Y - attribute \src "libresoc.v:78539.18-78539.117" - wire $eq$libresoc.v:78539$3638_Y - attribute \src "libresoc.v:78540.18-78540.117" - wire $eq$libresoc.v:78540$3639_Y - attribute \src "libresoc.v:78542.18-78542.117" - wire $eq$libresoc.v:78542$3641_Y - attribute \src "libresoc.v:78543.18-78543.122" - wire $eq$libresoc.v:78543$3642_Y - attribute \src "libresoc.v:78544.18-78544.122" - wire $eq$libresoc.v:78544$3643_Y - attribute \src "libresoc.v:78546.18-78546.112" - wire $eq$libresoc.v:78546$3645_Y - attribute \src "libresoc.v:78547.18-78547.112" - wire $eq$libresoc.v:78547$3646_Y - attribute \src "libresoc.v:78549.18-78549.112" - wire $eq$libresoc.v:78549$3648_Y - attribute \src "libresoc.v:78551.18-78551.110" - wire $eq$libresoc.v:78551$3650_Y - attribute \src "libresoc.v:78554.18-78554.119" - wire $eq$libresoc.v:78554$3653_Y - attribute \src "libresoc.v:78555.18-78555.119" - wire $eq$libresoc.v:78555$3654_Y - attribute \src "libresoc.v:78564.18-78564.123" - wire $eq$libresoc.v:78564$3663_Y - attribute \src "libresoc.v:78565.18-78565.123" - wire $eq$libresoc.v:78565$3664_Y - attribute \src "libresoc.v:78566.18-78566.123" - wire $eq$libresoc.v:78566$3665_Y - attribute \src "libresoc.v:78567.18-78567.123" - wire $eq$libresoc.v:78567$3666_Y - attribute \src "libresoc.v:78561.18-78561.115" - wire $not$libresoc.v:78561$3660_Y - attribute \src "libresoc.v:78562.18-78562.114" - wire $not$libresoc.v:78562$3661_Y - attribute \src "libresoc.v:78541.18-78541.111" - wire $or$libresoc.v:78541$3640_Y - attribute \src "libresoc.v:78545.18-78545.110" - wire $or$libresoc.v:78545$3644_Y - attribute \src "libresoc.v:78548.18-78548.110" - wire $or$libresoc.v:78548$3647_Y - attribute \src "libresoc.v:78550.18-78550.110" - wire $or$libresoc.v:78550$3649_Y - attribute \src "libresoc.v:78552.18-78552.110" - wire $or$libresoc.v:78552$3651_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1210" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1211" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1259" + attribute \src "libresoc.v:78885.19-78885.127" + wire width 8 $add$libresoc.v:78885$3647_Y + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 output 7 \asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" @@ -123331,7 +124020,7 @@ module \dec2 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1083" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1000" wire width 3 \cr_a_idx attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -123340,7 +124029,7 @@ module \dec2 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1084" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1001" wire width 3 \cr_b_idx attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 output 32 \cr_in1 @@ -123354,15 +124043,15 @@ module \dec2 wire output 35 \cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 37 \cr_in2_ok$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1004" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:904" wire \cr_in_b_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1003" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:903" wire \cr_in_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1005" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:905" wire \cr_in_o_isvec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 output 38 \cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1002" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:902" wire \cr_out_isvec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 39 \cr_out_ok @@ -123374,17 +124063,17 @@ module \dec2 wire width 8 output 63 \cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 64 \cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130" wire width 3 \crin_svdec_b_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131" wire width 7 \crin_svdec_b_cr_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 \crin_svdec_b_etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 \crin_svdec_b_extra attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -123393,21 +124082,21 @@ module \dec2 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 \crin_svdec_b_idx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132" wire \crin_svdec_b_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130" wire width 3 \crin_svdec_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131" wire width 7 \crin_svdec_cr_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 \crin_svdec_etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 \crin_svdec_extra attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -123416,21 +124105,21 @@ module \dec2 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 \crin_svdec_idx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132" wire \crin_svdec_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130" wire width 3 \crin_svdec_o_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131" wire width 7 \crin_svdec_o_cr_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 \crin_svdec_o_etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 \crin_svdec_o_extra attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -123439,21 +124128,21 @@ module \dec2 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 \crin_svdec_o_idx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132" wire \crin_svdec_o_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:130" wire width 3 \crout_svdec_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:131" wire width 7 \crout_svdec_cr_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 \crout_svdec_etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 \crout_svdec_extra attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -123462,19 +124151,19 @@ module \dec2 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 \crout_svdec_idx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:132" wire \crout_svdec_isvec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" - wire width 7 input 4 \cur_cur_srcstep - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:12" + wire width 7 input 5 \cur_cur_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 input 66 \cur_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire input 67 \cur_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 input 3 \cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 2 \cur_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \dec2_exc_$signal @@ -123550,7 +124239,7 @@ module \dec2 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" wire width 3 \dec_a_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -123618,7 +124307,8 @@ module \dec2 attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -123694,7 +124384,7 @@ module \dec2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 4 \dec_b_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_c_reg_c @@ -123704,7 +124394,7 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:428" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" wire width 2 \dec_c_sel_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123733,7 +124423,7 @@ module \dec2 wire width 8 \dec_cr_in_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_in_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:517" wire width 32 \dec_cr_in_insn_in attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" @@ -123744,8 +124434,10 @@ module \dec2 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:516" wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" + wire width 2 \dec_cr_in_sv_override attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -123763,9 +124455,9 @@ module \dec2 wire width 8 \dec_cr_out_cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_cr_out_cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590" wire \dec_cr_out_rc_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" @@ -123774,8 +124466,10 @@ module \dec2 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:591" wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + wire width 2 \dec_cr_out_sv_override attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -123905,7 +124599,7 @@ module \dec2 attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1203" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1138" wire \dec_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec_is_32b @@ -123915,7 +124609,7 @@ module \dec2 wire width 3 \dec_o2_fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_o2_fast_o2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" wire \dec_o2_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 \dec_o2_reg_o2 @@ -123934,7 +124628,7 @@ module \dec2 attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" wire width 2 \dec_o_sel_in attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -124002,7 +124696,8 @@ module \dec2 attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -124061,7 +124756,7 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -124086,7 +124781,7 @@ module \dec2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" wire width 2 \dec_rc_sel_in attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -124142,8 +124837,8 @@ module \dec2 attribute \enum_value_101 "Idx_1_2" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 3 \dec_sv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" - wire width 9 input 5 \dec_svp64__extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" + wire width 9 input 6 \dec_svp64__extra attribute \enum_base_type "LDSTMode" attribute \enum_value_00 "NONE" attribute \enum_value_01 "update" @@ -124171,7 +124866,7 @@ module \dec2 wire output 58 \exc_$signal$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire output 59 \exc_$signal$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1202" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1137" wire \ext_irq_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 24 \fast1 @@ -124205,15 +124900,15 @@ module \dec2 attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" wire width 13 output 44 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1205" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1140" wire \illeg_ok attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 \in1_svdec_etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 \in1_svdec_extra attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -124222,21 +124917,21 @@ module \dec2 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 \in1_svdec_idx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85" wire \in1_svdec_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83" wire width 5 \in1_svdec_reg_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84" wire width 7 \in1_svdec_reg_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 \in2_svdec_etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 \in2_svdec_extra attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -124245,21 +124940,21 @@ module \dec2 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 \in2_svdec_idx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85" wire \in2_svdec_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83" wire width 5 \in2_svdec_reg_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84" wire width 7 \in2_svdec_reg_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 \in3_svdec_etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 \in3_svdec_extra attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -124268,15 +124963,15 @@ module \dec2 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 \in3_svdec_idx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85" wire \in3_svdec_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83" wire width 5 \in3_svdec_reg_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84" wire width 7 \in3_svdec_reg_out - attribute \src "libresoc.v:76570.7-76570.15" + attribute \src "libresoc.v:76811.7-76811.15" wire \initial attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" @@ -124286,20 +124981,20 @@ module \dec2 wire width 2 output 50 \input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" wire width 32 output 42 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" wire width 32 \insn_in$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 32 \insn_in$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:323" - wire width 32 \insn_in$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:429" - wire width 32 \insn_in$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:460" - wire width 32 \insn_in$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" - wire width 32 \insn_in$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" + wire width 32 \insn_in$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + wire width 32 \insn_in$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + wire width 32 \insn_in$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" + wire width 32 \insn_in$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:391" + wire width 32 \insn_in$89 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -124378,35 +125073,41 @@ module \dec2 wire width 7 output 43 \insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire output 65 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:46" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:51" wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" wire output 45 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" wire width 64 output 40 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1011" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911" + wire \no_in_vec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912" wire \no_out_vec attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 \o2_svdec_etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 \o2_svdec_extra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85" wire \o2_svdec_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83" wire width 5 \o2_svdec_reg_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84" wire width 7 \o2_svdec_reg_out attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" attribute \enum_value_01 "EXTRA2" attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" wire width 2 \o_svdec_etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" wire width 9 \o_svdec_extra attribute \enum_base_type "SVEXTRA" attribute \enum_value_000 "NONE" @@ -124415,22 +125116,22 @@ module \dec2 attribute \enum_value_011 "Idx2" attribute \enum_value_100 "Idx3" attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" wire width 3 \o_svdec_idx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85" wire \o_svdec_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83" wire width 5 \o_svdec_reg_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84" wire width 7 \o_svdec_reg_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 48 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 49 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1139" wire \priv_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 32 input 6 \raw_opcode_in + wire width 32 input 4 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 46 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -124447,15 +125148,15 @@ module \dec2 wire width 7 output 16 \reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1006" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:906" wire \reg_a_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1007" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:907" wire \reg_b_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1008" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:908" wire \reg_c_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1010" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" wire \reg_o2_isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1009" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909" wire \reg_o_isvec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 output 8 \rego @@ -124466,9 +125167,9 @@ module \dec2 attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389" wire width 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -124536,7 +125237,8 @@ module \dec2 attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -124653,7 +125355,8 @@ module \dec2 attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -124704,7 +125407,7 @@ module \dec2 wire width 10 output 18 \spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 19 \spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1113" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1030" wire width 7 \srcstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \tmp_asmcode @@ -124826,7 +125529,8 @@ module \dec2 attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -124943,7 +125647,8 @@ module \dec2 attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -125150,63 +125855,206 @@ module \dec2 wire width 3 output 22 \xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire output 23 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1130" - cell $add $add$libresoc.v:78556$3655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047" + cell $add $add$libresoc.v:78885$3647 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A \srcstep - connect \B \in1_svdec_reg_out - connect \Y $add$libresoc.v:78556$3655_Y + connect \B \in3_svdec_reg_out + connect \Y $add$libresoc.v:78885$3647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1130" - cell $add $add$libresoc.v:78557$3656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047" + cell $add $add$libresoc.v:78886$3648 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A \srcstep - connect \B \in2_svdec_reg_out - connect \Y $add$libresoc.v:78557$3656_Y + connect \B \o_svdec_reg_out + connect \Y $add$libresoc.v:78886$3648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1130" - cell $add $add$libresoc.v:78558$3657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047" + cell $add $add$libresoc.v:78887$3649 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A \srcstep - connect \B \in3_svdec_reg_out - connect \Y $add$libresoc.v:78558$3657_Y + connect \B \o2_svdec_reg_out + connect \Y $add$libresoc.v:78887$3649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1130" - cell $add $add$libresoc.v:78559$3658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1099" + cell $add $add$libresoc.v:78894$3656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B 1'0 + connect \Y $add$libresoc.v:78894$3656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1102" + cell $add $add$libresoc.v:78895$3657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B 1'1 + connect \Y $add$libresoc.v:78895$3657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1104" + cell $add $add$libresoc.v:78896$3658 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A \srcstep - connect \B \o_svdec_reg_out - connect \Y $add$libresoc.v:78559$3658_Y + connect \B \crin_svdec_cr_out + connect \Y $add$libresoc.v:78896$3658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1099" + cell $add $add$libresoc.v:78899$3661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B 1'0 + connect \Y $add$libresoc.v:78899$3661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1130" - cell $add $add$libresoc.v:78560$3659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1102" + cell $add $add$libresoc.v:78900$3662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B 1'1 + connect \Y $add$libresoc.v:78900$3662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1104" + cell $add $add$libresoc.v:78901$3663 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 8 connect \A \srcstep - connect \B \o2_svdec_reg_out - connect \Y $add$libresoc.v:78560$3659_Y + connect \B \crin_svdec_b_cr_out + connect \Y $add$libresoc.v:78901$3663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1099" + cell $add $add$libresoc.v:78904$3666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B 1'0 + connect \Y $add$libresoc.v:78904$3666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1102" + cell $add $add$libresoc.v:78905$3667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B 1'1 + connect \Y $add$libresoc.v:78905$3667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1104" + cell $add $add$libresoc.v:78906$3668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B \crin_svdec_o_cr_out + connect \Y $add$libresoc.v:78906$3668_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1099" + cell $add $add$libresoc.v:78909$3671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B 1'0 + connect \Y $add$libresoc.v:78909$3671_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1102" + cell $add $add$libresoc.v:78910$3672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B 1'1 + connect \Y $add$libresoc.v:78910$3672_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1104" + cell $add $add$libresoc.v:78911$3673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B \crout_svdec_cr_out + connect \Y $add$libresoc.v:78911$3673_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047" + cell $add $add$libresoc.v:78950$3712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B \in1_svdec_reg_out + connect \Y $add$libresoc.v:78950$3712_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1209" - cell $and $and$libresoc.v:78536$3635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1047" + cell $add $add$libresoc.v:78951$3713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B \in2_svdec_reg_out + connect \Y $add$libresoc.v:78951$3713_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1143" + cell $and $and$libresoc.v:78916$3678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_eint + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:78916$3678_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1144" + cell $and $and$libresoc.v:78917$3679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125214,10 +126062,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_dec [63] connect \B \cur_msr [15] - connect \Y $and$libresoc.v:78536$3635_Y + connect \Y $and$libresoc.v:78917$3679_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1210" - cell $and $and$libresoc.v:78537$3636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1145" + cell $and $and$libresoc.v:78918$3680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125225,175 +126073,186 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_priv_insn connect \B \cur_msr [14] - connect \Y $and$libresoc.v:78537$3636_Y + connect \Y $and$libresoc.v:78918$3680_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $and $and$libresoc.v:78553$3652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:78925$3687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$41 - connect \B \$55 - connect \Y $and$libresoc.v:78553$3652_Y + connect \A \is_spr_mv + connect \B \$37 + connect \Y $and$libresoc.v:78925$3687_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150" - cell $and $and$libresoc.v:78563$3662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:78926$3688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$83 - connect \B \$85 - connect \Y $and$libresoc.v:78563$3662_Y + connect \A \$39 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:78926$3688_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1208" - cell $and $and$libresoc.v:78568$3667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:78928$3690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cur_eint - connect \B \cur_msr [15] - connect \Y $and$libresoc.v:78568$3667_Y + connect \A \is_spr_mv + connect \B \$43 + connect \Y $and$libresoc.v:78928$3690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1211" - cell $eq $eq$libresoc.v:78538$3637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:78930$3692 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0000000 - connect \Y $eq$libresoc.v:78538$3637_Y + connect \A \$45 + connect \B \$47 + connect \Y $and$libresoc.v:78930$3692_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1259" - cell $eq $eq$libresoc.v:78539$3638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:78942$3704 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'0111111 - connect \Y $eq$libresoc.v:78539$3638_Y + connect \A \is_spr_mv + connect \B \$71 + connect \Y $and$libresoc.v:78942$3704_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" - cell $eq $eq$libresoc.v:78540$3639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:78943$3705 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1001001 - connect \Y $eq$libresoc.v:78540$3639_Y + connect \A \$73 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:78943$3705_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1269" - cell $eq $eq$libresoc.v:78542$3641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:78945$3707 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1000110 - connect \Y $eq$libresoc.v:78542$3641_Y + connect \A \is_spr_mv + connect \B \$77 + connect \Y $and$libresoc.v:78945$3707_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - cell $eq $eq$libresoc.v:78543$3642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:78947$3709 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:78543$3642_Y + connect \A \$79 + connect \B \$81 + connect \Y $and$libresoc.v:78947$3709_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $eq $eq$libresoc.v:78544$3643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097" + cell $eq $eq$libresoc.v:78892$3654 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0101110 - connect \Y $eq$libresoc.v:78544$3643_Y + connect \A \dec_cr_in_sv_override + connect \B 1'1 + connect \Y $eq$libresoc.v:78892$3654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:78546$3645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1100" + cell $eq $eq$libresoc.v:78893$3655 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010010 - connect \Y $eq$libresoc.v:78546$3645_Y + connect \A \dec_cr_in_sv_override + connect \B 2'10 + connect \Y $eq$libresoc.v:78893$3655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:78547$3646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097" + cell $eq $eq$libresoc.v:78897$3659 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010011 - connect \Y $eq$libresoc.v:78547$3646_Y + connect \A \dec_cr_in_sv_override + connect \B 1'1 + connect \Y $eq$libresoc.v:78897$3659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:78549$3648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1100" + cell $eq $eq$libresoc.v:78898$3660 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'1011010000 - connect \Y $eq$libresoc.v:78549$3648_Y + connect \A \dec_cr_in_sv_override + connect \B 2'10 + connect \Y $eq$libresoc.v:78898$3660_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:78551$3650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097" + cell $eq $eq$libresoc.v:78902$3664 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 6'110000 - connect \Y $eq$libresoc.v:78551$3650_Y + connect \A \dec_cr_in_sv_override + connect \B 1'1 + connect \Y $eq$libresoc.v:78902$3664_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1090" - cell $eq $eq$libresoc.v:78554$3653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1100" + cell $eq $eq$libresoc.v:78903$3665 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \dec_sv_cr_in - connect \B 3'101 - connect \Y $eq$libresoc.v:78554$3653_Y + connect \A \dec_cr_in_sv_override + connect \B 2'10 + connect \Y $eq$libresoc.v:78903$3665_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1090" - cell $eq $eq$libresoc.v:78555$3654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097" + cell $eq $eq$libresoc.v:78907$3669 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dec_sv_cr_in - connect \B 3'101 - connect \Y $eq$libresoc.v:78555$3654_Y + connect \A \dec_cr_out_sv_override + connect \B 1'1 + connect \Y $eq$libresoc.v:78907$3669_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1100" + cell $eq $eq$libresoc.v:78908$3670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \dec_cr_out_sv_override + connect \B 2'10 + connect \Y $eq$libresoc.v:78908$3670_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1177" - cell $eq $eq$libresoc.v:78564$3663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1112" + cell $eq $eq$libresoc.v:78912$3674 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125401,10 +126260,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:78564$3663_Y + connect \Y $eq$libresoc.v:78912$3674_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" - cell $eq $eq$libresoc.v:78565$3664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1114" + cell $eq $eq$libresoc.v:78913$3675 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125412,10 +126271,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0001010 - connect \Y $eq$libresoc.v:78565$3664_Y + connect \Y $eq$libresoc.v:78913$3675_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1181" - cell $eq $eq$libresoc.v:78566$3665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1116" + cell $eq $eq$libresoc.v:78914$3676 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125423,10 +126282,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:78566$3665_Y + connect \Y $eq$libresoc.v:78914$3676_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1185" - cell $eq $eq$libresoc.v:78567$3666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1120" + cell $eq $eq$libresoc.v:78915$3677 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125434,26 +126293,218 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0111111 - connect \Y $eq$libresoc.v:78567$3666_Y + connect \Y $eq$libresoc.v:78915$3677_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150" - cell $not $not$libresoc.v:78561$3660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1146" + cell $eq $eq$libresoc.v:78919$3681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$libresoc.v:78919$3681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1194" + cell $eq $eq$libresoc.v:78920$3682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:78920$3682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1195" + cell $eq $eq$libresoc.v:78921$3683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:78921$3683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" + cell $eq $eq$libresoc.v:78923$3685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:78923$3685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:78924$3686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:78924$3686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:78927$3689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:78927$3689_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" + cell $eq $eq$libresoc.v:78931$3693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:78931$3693_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $eq $eq$libresoc.v:78932$3694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:78932$3694_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:78934$3696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:78934$3696_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:78935$3697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:78935$3697_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:78937$3699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:78937$3699_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $eq $eq$libresoc.v:78939$3701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:78939$3701_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:78941$3703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:78941$3703_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:78944$3706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:78944$3706_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1007" + cell $eq $eq$libresoc.v:78948$3710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dec_sv_cr_in + connect \B 3'101 + connect \Y $eq$libresoc.v:78948$3710_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1007" + cell $eq $eq$libresoc.v:78949$3711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dec_sv_cr_in + connect \B 3'101 + connect \Y $eq$libresoc.v:78949$3711_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1069" + cell $not $not$libresoc.v:78889$3651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \o2_svdec_isvec - connect \Y $not$libresoc.v:78561$3660_Y + connect \A \$110 + connect \Y $not$libresoc.v:78889$3651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150" - cell $not $not$libresoc.v:78562$3661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1071" + cell $not $not$libresoc.v:78891$3653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \o_svdec_isvec - connect \Y $not$libresoc.v:78562$3661_Y + connect \A \$114 + connect \Y $not$libresoc.v:78891$3653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" - cell $or $or$libresoc.v:78541$3640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:78929$3691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:78929$3691_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:78946$3708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:78946$3708_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1195" + cell $or $or$libresoc.v:78922$3684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125461,54 +126512,70 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$28 connect \B \$30 - connect \Y $or$libresoc.v:78541$3640_Y + connect \Y $or$libresoc.v:78922$3684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $or $or$libresoc.v:78545$3644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $or $or$libresoc.v:78933$3695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$37 - connect \B \$39 - connect \Y $or$libresoc.v:78545$3644_Y + connect \A \$51 + connect \B \$53 + connect \Y $or$libresoc.v:78933$3695_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:78548$3647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:78936$3698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$43 - connect \B \$45 - connect \Y $or$libresoc.v:78548$3647_Y + connect \A \$57 + connect \B \$59 + connect \Y $or$libresoc.v:78936$3698_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:78550$3649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:78938$3700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$47 - connect \B \$49 - connect \Y $or$libresoc.v:78550$3649_Y + connect \A \$61 + connect \B \$63 + connect \Y $or$libresoc.v:78938$3700_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:78552$3651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $or $or$libresoc.v:78940$3702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$51 - connect \B \$53 - connect \Y $or$libresoc.v:78552$3651_Y + connect \A \$65 + connect \B \$67 + connect \Y $or$libresoc.v:78940$3702_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1069" + cell $reduce_or $reduce_or$libresoc.v:78888$3650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \crin_svdec_o_isvec \crin_svdec_b_isvec \crin_svdec_isvec \in3_svdec_isvec \in2_svdec_isvec \in1_svdec_isvec } + connect \Y $reduce_or$libresoc.v:78888$3650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1071" + cell $reduce_or $reduce_or$libresoc.v:78890$3652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \crout_svdec_isvec \o_svdec_isvec \o2_svdec_isvec } + connect \Y $reduce_or$libresoc.v:78890$3652_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:78569.14-78576.4" + attribute \src "libresoc.v:78952.14-78959.4" cell \crin_svdec \crin_svdec connect \cr_in \crin_svdec_cr_in connect \cr_out \crin_svdec_cr_out @@ -125518,7 +126585,7 @@ module \dec2 connect \isvec \crin_svdec_isvec end attribute \module_not_derived 1 - attribute \src "libresoc.v:78577.16-78584.4" + attribute \src "libresoc.v:78960.16-78967.4" cell \crin_svdec_b \crin_svdec_b connect \cr_in \crin_svdec_b_cr_in connect \cr_out \crin_svdec_b_cr_out @@ -125528,7 +126595,7 @@ module \dec2 connect \isvec \crin_svdec_b_isvec end attribute \module_not_derived 1 - attribute \src "libresoc.v:78585.16-78592.4" + attribute \src "libresoc.v:78968.16-78975.4" cell \crin_svdec_o \crin_svdec_o connect \cr_in \crin_svdec_o_cr_in connect \cr_out \crin_svdec_o_cr_out @@ -125538,7 +126605,7 @@ module \dec2 connect \isvec \crin_svdec_o_isvec end attribute \module_not_derived 1 - attribute \src "libresoc.v:78593.15-78600.4" + attribute \src "libresoc.v:78976.15-78983.4" cell \crout_svdec \crout_svdec connect \cr_in \crout_svdec_cr_in connect \cr_out \crout_svdec_cr_out @@ -125548,8 +126615,8 @@ module \dec2 connect \isvec \crout_svdec_isvec end attribute \module_not_derived 1 - attribute \src "libresoc.v:78601.13-78645.4" - cell \dec$204 \dec + attribute \src "libresoc.v:78984.13-79028.4" + cell \dec$171 \dec connect \BA \dec_BA connect \BB \dec_BB connect \BC \dec_BC @@ -125595,7 +126662,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:78646.9-78660.4" + attribute \src "libresoc.v:79029.9-79043.4" cell \dec_a \dec_a connect \BO \dec_BO connect \RA \dec_RA @@ -125612,7 +126679,7 @@ module \dec2 connect \spr_a_ok \dec_a_spr_a_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:78661.9-78671.4" + attribute \src "libresoc.v:79044.9-79054.4" cell \dec_b \dec_b connect \RB \dec_RB connect \RS \dec_RS @@ -125625,7 +126692,7 @@ module \dec2 connect \sel_in \dec_b_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78672.9-78678.4" + attribute \src "libresoc.v:79055.9-79061.4" cell \dec_c \dec_c connect \RB \dec_RB connect \RS \dec_RS @@ -125634,8 +126701,8 @@ module \dec2 connect \sel_in \dec_c_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78679.19-78698.4" - cell \dec_cr_in$207 \dec_cr_in$10 + attribute \src "libresoc.v:79062.13-79082.4" + cell \dec_cr_in \dec_cr_in$10 connect \BA \dec_BA connect \BB \dec_BB connect \BC \dec_BC @@ -125654,10 +126721,11 @@ module \dec2 connect \insn_in \dec_cr_in_insn_in connect \internal_op \dec_internal_op connect \sel_in \dec_cr_in_sel_in + connect \sv_override \dec_cr_in_sv_override end attribute \module_not_derived 1 - attribute \src "libresoc.v:78699.20-78711.4" - cell \dec_cr_out$209 \dec_cr_out$11 + attribute \src "libresoc.v:79083.14-79096.4" + cell \dec_cr_out \dec_cr_out$11 connect \FXM \dec_FXM connect \XL_BT \dec_XL_BT connect \X_BF \dec_X_BF @@ -125669,9 +126737,10 @@ module \dec2 connect \internal_op \dec_internal_op connect \rc_in \dec_cr_out_rc_in connect \sel_in \dec_cr_out_sel_in + connect \sv_override \dec_cr_out_sv_override end attribute \module_not_derived 1 - attribute \src "libresoc.v:78712.9-78725.4" + attribute \src "libresoc.v:79097.9-79110.4" cell \dec_o \dec_o connect \BO \dec_BO connect \RA \dec_RA @@ -125687,7 +126756,7 @@ module \dec2 connect \spr_o_ok \dec_o_spr_o_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:78726.10-78735.4" + attribute \src "libresoc.v:79111.10-79120.4" cell \dec_o2 \dec_o2 connect \RA \dec_RA connect \fast_o2 \dec_o2_fast_o2 @@ -125699,8 +126768,8 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:78736.16-78742.4" - cell \dec_oe$206 \dec_oe + attribute \src "libresoc.v:79121.16-79127.4" + cell \dec_oe$173 \dec_oe connect \OE \dec_OE connect \internal_op \dec_internal_op connect \oe \dec_oe_oe @@ -125708,15 +126777,15 @@ module \dec2 connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78743.16-78748.4" - cell \dec_rc$205 \dec_rc + attribute \src "libresoc.v:79128.16-79133.4" + cell \dec_rc$172 \dec_rc connect \Rc \dec_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:78749.13-78756.4" + attribute \src "libresoc.v:79134.13-79141.4" cell \in1_svdec \in1_svdec connect \etype \in1_svdec_etype connect \extra \in1_svdec_extra @@ -125726,7 +126795,7 @@ module \dec2 connect \reg_out \in1_svdec_reg_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:78757.13-78764.4" + attribute \src "libresoc.v:79142.13-79149.4" cell \in2_svdec \in2_svdec connect \etype \in2_svdec_etype connect \extra \in2_svdec_extra @@ -125736,7 +126805,7 @@ module \dec2 connect \reg_out \in2_svdec_reg_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:78765.13-78772.4" + attribute \src "libresoc.v:79150.13-79157.4" cell \in3_svdec \in3_svdec connect \etype \in3_svdec_etype connect \extra \in3_svdec_extra @@ -125746,7 +126815,7 @@ module \dec2 connect \reg_out \in3_svdec_reg_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:78773.12-78779.4" + attribute \src "libresoc.v:79158.12-79164.4" cell \o2_svdec \o2_svdec connect \etype \o2_svdec_etype connect \extra \o2_svdec_extra @@ -125755,7 +126824,7 @@ module \dec2 connect \reg_out \o2_svdec_reg_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:78780.11-78787.4" + attribute \src "libresoc.v:79165.11-79172.4" cell \o_svdec \o_svdec connect \etype \o_svdec_etype connect \extra \o_svdec_extra @@ -125764,28 +126833,212 @@ module \dec2 connect \reg_in \o_svdec_reg_in connect \reg_out \o_svdec_reg_out end - attribute \src "libresoc.v:76570.7-76570.20" - process $proc$libresoc.v:76570$3732 + attribute \src "libresoc.v:76811.7-76811.20" + process $proc$libresoc.v:76811$3786 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:78788.3-78803.6" - process $proc$libresoc.v:78788$3668 + attribute \src "libresoc.v:79173.3-79195.6" + process $proc$libresoc.v:79173$3714 + assign { } { } + assign $0\tmp_cr_in1[6:0] $1\tmp_cr_in1[6:0] + attribute \src "libresoc.v:79174.5-79174.29" + switch \initial + attribute \src "libresoc.v:79174.9-79174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1093" + switch \crin_svdec_isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_cr_in1[6:0] $2\tmp_cr_in1[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097" + switch { \$119 \$117 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\tmp_cr_in1[6:0] \$121 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\tmp_cr_in1[6:0] \$124 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\tmp_cr_in1[6:0] \$127 [6:0] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_cr_in1[6:0] \crin_svdec_cr_out + end + sync always + update \tmp_cr_in1 $0\tmp_cr_in1[6:0] + end + attribute \src "libresoc.v:79196.3-79218.6" + process $proc$libresoc.v:79196$3715 + assign { } { } + assign $0\tmp_cr_in2[6:0] $1\tmp_cr_in2[6:0] + attribute \src "libresoc.v:79197.5-79197.29" + switch \initial + attribute \src "libresoc.v:79197.9-79197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1093" + switch \crin_svdec_b_isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_cr_in2[6:0] $2\tmp_cr_in2[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097" + switch { \$132 \$130 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\tmp_cr_in2[6:0] \$134 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\tmp_cr_in2[6:0] \$137 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\tmp_cr_in2[6:0] \$140 [6:0] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_cr_in2[6:0] \crin_svdec_b_cr_out + end + sync always + update \tmp_cr_in2 $0\tmp_cr_in2[6:0] + end + attribute \src "libresoc.v:79219.3-79233.6" + process $proc$libresoc.v:79219$3716 + assign { } { } + assign $0\tmp_tmp_fn_unit[12:0] $1\tmp_tmp_fn_unit[12:0] + attribute \src "libresoc.v:79220.5-79220.29" + switch \initial + attribute \src "libresoc.v:79220.9-79220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$83 \$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\tmp_tmp_fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\tmp_tmp_fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_tmp_fn_unit[12:0] \dec_function_unit + end + sync always + update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[12:0] + end + attribute \src "libresoc.v:79234.3-79256.6" + process $proc$libresoc.v:79234$3717 + assign { } { } + assign $0\tmp_cr_in2$19[6:0]$3718 $1\tmp_cr_in2$19[6:0]$3719 + attribute \src "libresoc.v:79235.5-79235.29" + switch \initial + attribute \src "libresoc.v:79235.9-79235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1093" + switch \crin_svdec_o_isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_cr_in2$19[6:0]$3719 $2\tmp_cr_in2$19[6:0]$3720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097" + switch { \$145 \$143 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\tmp_cr_in2$19[6:0]$3720 \$147 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\tmp_cr_in2$19[6:0]$3720 \$150 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\tmp_cr_in2$19[6:0]$3720 \$153 [6:0] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_cr_in2$19[6:0]$3719 \crin_svdec_o_cr_out + end + sync always + update \tmp_cr_in2$19 $0\tmp_cr_in2$19[6:0]$3718 + end + attribute \src "libresoc.v:79257.3-79279.6" + process $proc$libresoc.v:79257$3721 + assign { } { } + assign $0\tmp_cr_out[6:0] $1\tmp_cr_out[6:0] + attribute \src "libresoc.v:79258.5-79258.29" + switch \initial + attribute \src "libresoc.v:79258.9-79258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1093" + switch \crout_svdec_isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_cr_out[6:0] $2\tmp_cr_out[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1097" + switch { \$158 \$156 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\tmp_cr_out[6:0] \$160 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\tmp_cr_out[6:0] \$163 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\tmp_cr_out[6:0] \$166 [6:0] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_cr_out[6:0] \crout_svdec_cr_out + end + sync always + update \tmp_cr_out $0\tmp_cr_out[6:0] + end + attribute \src "libresoc.v:79280.3-79295.6" + process $proc$libresoc.v:79280$3722 assign { } { } assign { } { } assign { } { } assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:78789.5-78789.29" + attribute \src "libresoc.v:79281.5-79281.29" switch \initial - attribute \src "libresoc.v:78789.9-78789.17" + attribute \src "libresoc.v:79281.9-79281.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1177" - switch \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1112" + switch \$169 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -125793,8 +127046,8 @@ module \dec2 case assign $1\tmp_xer_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" - switch \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1114" + switch \$171 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -125805,19 +127058,19 @@ module \dec2 sync always update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "libresoc.v:78804.3-78813.6" - process $proc$libresoc.v:78804$3669 + attribute \src "libresoc.v:79296.3-79305.6" + process $proc$libresoc.v:79296$3723 assign { } { } assign { } { } assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:78805.5-78805.29" + attribute \src "libresoc.v:79297.5-79297.29" switch \initial - attribute \src "libresoc.v:78805.9-78805.17" + attribute \src "libresoc.v:79297.9-79297.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1181" - switch \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1116" + switch \$173 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -125828,19 +127081,19 @@ module \dec2 sync always update \tmp_xer_out $0\tmp_xer_out[0:0] end - attribute \src "libresoc.v:78814.3-78823.6" - process $proc$libresoc.v:78814$3670 + attribute \src "libresoc.v:79306.3-79315.6" + process $proc$libresoc.v:79306$3724 assign { } { } assign { } { } assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:78815.5-78815.29" + attribute \src "libresoc.v:79307.5-79307.29" switch \initial - attribute \src "libresoc.v:78815.9-78815.17" + attribute \src "libresoc.v:79307.9-79307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1185" - switch \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1120" + switch \$175 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -125851,18 +127104,18 @@ module \dec2 sync always update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end - attribute \src "libresoc.v:78824.3-78847.6" - process $proc$libresoc.v:78824$3671 + attribute \src "libresoc.v:79316.3-79339.6" + process $proc$libresoc.v:79316$3725 assign { } { } assign { } { } assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:78825.5-78825.29" + attribute \src "libresoc.v:79317.5-79317.29" switch \initial - attribute \src "libresoc.v:78825.9-78825.17" + attribute \src "libresoc.v:79317.9-79317.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:47" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" switch \dec_internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 @@ -125876,7 +127129,7 @@ module \dec2 case 7'0101110 , 7'0110001 assign { } { } assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:58" switch \tmp_tmp_insn [20] attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -125891,8 +127144,8 @@ module \dec2 sync always update \is_priv_insn $0\is_priv_insn[0:0] end - attribute \src "libresoc.v:78848.3-79005.6" - process $proc$libresoc.v:78848$3672 + attribute \src "libresoc.v:79340.3-79497.6" + process $proc$libresoc.v:79340$3726 assign { } { } assign { } { } assign { } { } @@ -125969,22 +127222,22 @@ module \dec2 assign $0\cr_in1[6:0] $1\cr_in1[6:0] assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] assign $0\cr_in2[6:0] $1\cr_in2[6:0] - assign $0\cr_in2$1[6:0]$3673 $1\cr_in2$1[6:0]$3683 + assign $0\cr_in2$1[6:0]$3727 $1\cr_in2$1[6:0]$3737 assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] - assign $0\cr_in2_ok$2[0:0]$3674 $1\cr_in2_ok$2[0:0]$3684 + assign $0\cr_in2_ok$2[0:0]$3728 $1\cr_in2_ok$2[0:0]$3738 assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] assign $0\cr_rd[7:0] $1\cr_rd[7:0] assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] assign $0\cr_wr[7:0] $1\cr_wr[7:0] assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] - assign $0\exc_$signal[0:0]$3675 $1\exc_$signal[0:0]$3685 - assign $0\exc_$signal$3[0:0]$3676 $1\exc_$signal$3[0:0]$3686 - assign $0\exc_$signal$4[0:0]$3677 $1\exc_$signal$4[0:0]$3687 - assign $0\exc_$signal$5[0:0]$3678 $1\exc_$signal$5[0:0]$3688 - assign $0\exc_$signal$6[0:0]$3679 $1\exc_$signal$6[0:0]$3689 - assign $0\exc_$signal$7[0:0]$3680 $1\exc_$signal$7[0:0]$3690 - assign $0\exc_$signal$8[0:0]$3681 $1\exc_$signal$8[0:0]$3691 - assign $0\exc_$signal$9[0:0]$3682 $1\exc_$signal$9[0:0]$3692 + assign $0\exc_$signal[0:0]$3729 $1\exc_$signal[0:0]$3739 + assign $0\exc_$signal$3[0:0]$3730 $1\exc_$signal$3[0:0]$3740 + assign $0\exc_$signal$4[0:0]$3731 $1\exc_$signal$4[0:0]$3741 + assign $0\exc_$signal$5[0:0]$3732 $1\exc_$signal$5[0:0]$3742 + assign $0\exc_$signal$6[0:0]$3733 $1\exc_$signal$6[0:0]$3743 + assign $0\exc_$signal$7[0:0]$3734 $1\exc_$signal$7[0:0]$3744 + assign $0\exc_$signal$8[0:0]$3735 $1\exc_$signal$8[0:0]$3745 + assign $0\exc_$signal$9[0:0]$3736 $1\exc_$signal$9[0:0]$3746 assign { } { } assign { } { } assign { } { } @@ -126020,13 +127273,13 @@ module \dec2 assign $0\fast2[2:0] $5\fast2[2:0] assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:78849.5-78849.29" + attribute \src "libresoc.v:79341.5-79341.29" switch \initial - attribute \src "libresoc.v:78849.9-78849.17" + attribute \src "libresoc.v:79341.9-79341.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150" switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } attribute \src "libresoc.v:0.0-0.0" case 5'----1 @@ -126106,22 +127359,22 @@ module \dec2 assign $1\cr_in1[6:0] $2\cr_in1[6:0] assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] assign $1\cr_in2[6:0] $2\cr_in2[6:0] - assign $1\cr_in2$1[6:0]$3683 $2\cr_in2$1[6:0]$3693 + assign $1\cr_in2$1[6:0]$3737 $2\cr_in2$1[6:0]$3747 assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] - assign $1\cr_in2_ok$2[0:0]$3684 $2\cr_in2_ok$2[0:0]$3694 + assign $1\cr_in2_ok$2[0:0]$3738 $2\cr_in2_ok$2[0:0]$3748 assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] assign $1\cr_rd[7:0] $2\cr_rd[7:0] assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] assign $1\cr_wr[7:0] $2\cr_wr[7:0] assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] - assign $1\exc_$signal[0:0]$3685 $2\exc_$signal[0:0]$3695 - assign $1\exc_$signal$3[0:0]$3686 $2\exc_$signal$3[0:0]$3696 - assign $1\exc_$signal$4[0:0]$3687 $2\exc_$signal$4[0:0]$3697 - assign $1\exc_$signal$5[0:0]$3688 $2\exc_$signal$5[0:0]$3698 - assign $1\exc_$signal$6[0:0]$3689 $2\exc_$signal$6[0:0]$3699 - assign $1\exc_$signal$7[0:0]$3690 $2\exc_$signal$7[0:0]$3700 - assign $1\exc_$signal$8[0:0]$3691 $2\exc_$signal$8[0:0]$3701 - assign $1\exc_$signal$9[0:0]$3692 $2\exc_$signal$9[0:0]$3702 + assign $1\exc_$signal[0:0]$3739 $2\exc_$signal[0:0]$3749 + assign $1\exc_$signal$3[0:0]$3740 $2\exc_$signal$3[0:0]$3750 + assign $1\exc_$signal$4[0:0]$3741 $2\exc_$signal$4[0:0]$3751 + assign $1\exc_$signal$5[0:0]$3742 $2\exc_$signal$5[0:0]$3752 + assign $1\exc_$signal$6[0:0]$3743 $2\exc_$signal$6[0:0]$3753 + assign $1\exc_$signal$7[0:0]$3744 $2\exc_$signal$7[0:0]$3754 + assign $1\exc_$signal$8[0:0]$3745 $2\exc_$signal$8[0:0]$3755 + assign $1\exc_$signal$9[0:0]$3746 $2\exc_$signal$9[0:0]$3756 assign $1\fasto1[2:0] $2\fasto1[2:0] assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] assign $1\fasto2[2:0] $2\fasto2[2:0] @@ -126148,7 +127401,7 @@ module \dec2 assign $1\traptype[7:0] $2\traptype[7:0] assign $1\xer_in[2:0] $2\xer_in[2:0] assign $1\xer_out[0:0] $2\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1216" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1151" switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -126211,7 +127464,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3702 $2\exc_$signal$8[0:0]$3701 $2\exc_$signal$7[0:0]$3700 $2\exc_$signal$6[0:0]$3699 $2\exc_$signal$5[0:0]$3698 $2\exc_$signal$4[0:0]$3697 $2\exc_$signal$3[0:0]$3696 $2\exc_$signal[0:0]$3695 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3694 $2\cr_in2$1[6:0]$3693 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3756 $2\exc_$signal$8[0:0]$3755 $2\exc_$signal$7[0:0]$3754 $2\exc_$signal$6[0:0]$3753 $2\exc_$signal$5[0:0]$3752 $2\exc_$signal$4[0:0]$3751 $2\exc_$signal$3[0:0]$3750 $2\exc_$signal[0:0]$3749 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3748 $2\cr_in2$1[6:0]$3747 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $2\insn[31:0] \dec_opcode_in assign $2\insn_type[6:0] 7'0111111 assign $2\fn_unit[12:0] 13'0000010000000 @@ -126297,22 +127550,22 @@ module \dec2 assign $2\cr_in1[6:0] $3\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] assign $2\cr_in2[6:0] $3\cr_in2[6:0] - assign $2\cr_in2$1[6:0]$3693 $3\cr_in2$1[6:0]$3703 + assign $2\cr_in2$1[6:0]$3747 $3\cr_in2$1[6:0]$3757 assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3694 $3\cr_in2_ok$2[0:0]$3704 + assign $2\cr_in2_ok$2[0:0]$3748 $3\cr_in2_ok$2[0:0]$3758 assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] assign $2\cr_rd[7:0] $3\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $3\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3695 $3\exc_$signal[0:0]$3705 - assign $2\exc_$signal$3[0:0]$3696 $3\exc_$signal$3[0:0]$3706 - assign $2\exc_$signal$4[0:0]$3697 $3\exc_$signal$4[0:0]$3707 - assign $2\exc_$signal$5[0:0]$3698 $3\exc_$signal$5[0:0]$3708 - assign $2\exc_$signal$6[0:0]$3699 $3\exc_$signal$6[0:0]$3709 - assign $2\exc_$signal$7[0:0]$3700 $3\exc_$signal$7[0:0]$3710 - assign $2\exc_$signal$8[0:0]$3701 $3\exc_$signal$8[0:0]$3711 - assign $2\exc_$signal$9[0:0]$3702 $3\exc_$signal$9[0:0]$3712 + assign $2\exc_$signal[0:0]$3749 $3\exc_$signal[0:0]$3759 + assign $2\exc_$signal$3[0:0]$3750 $3\exc_$signal$3[0:0]$3760 + assign $2\exc_$signal$4[0:0]$3751 $3\exc_$signal$4[0:0]$3761 + assign $2\exc_$signal$5[0:0]$3752 $3\exc_$signal$5[0:0]$3762 + assign $2\exc_$signal$6[0:0]$3753 $3\exc_$signal$6[0:0]$3763 + assign $2\exc_$signal$7[0:0]$3754 $3\exc_$signal$7[0:0]$3764 + assign $2\exc_$signal$8[0:0]$3755 $3\exc_$signal$8[0:0]$3765 + assign $2\exc_$signal$9[0:0]$3756 $3\exc_$signal$9[0:0]$3766 assign $2\fasto1[2:0] $3\fasto1[2:0] assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] assign $2\fasto2[2:0] $3\fasto2[2:0] @@ -126339,7 +127592,7 @@ module \dec2 assign $2\traptype[7:0] $3\traptype[7:0] assign $2\xer_in[2:0] $3\xer_in[2:0] assign $2\xer_out[0:0] $3\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1219" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1154" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126402,7 +127655,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3712 $3\exc_$signal$8[0:0]$3711 $3\exc_$signal$7[0:0]$3710 $3\exc_$signal$6[0:0]$3709 $3\exc_$signal$5[0:0]$3708 $3\exc_$signal$4[0:0]$3707 $3\exc_$signal$3[0:0]$3706 $3\exc_$signal[0:0]$3705 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3704 $3\cr_in2$1[6:0]$3703 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3766 $3\exc_$signal$8[0:0]$3765 $3\exc_$signal$7[0:0]$3764 $3\exc_$signal$6[0:0]$3763 $3\exc_$signal$5[0:0]$3762 $3\exc_$signal$4[0:0]$3761 $3\exc_$signal$3[0:0]$3760 $3\exc_$signal[0:0]$3759 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3758 $3\cr_in2$1[6:0]$3757 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 assign $3\fn_unit[12:0] 13'0000010000000 @@ -126471,13 +127724,13 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3704 $3\cr_in2$1[6:0]$3703 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3758 $3\cr_in2$1[6:0]$3757 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $3\insn[31:0] \dec_opcode_in assign $3\insn_type[6:0] 7'0111111 assign $3\fn_unit[12:0] 13'0000010000000 assign $3\trapaddr[12:0] 13'0000001000000 assign $3\traptype[7:0] 8'01000000 - assign { $3\exc_$signal$9[0:0]$3712 $3\exc_$signal$8[0:0]$3711 $3\exc_$signal$7[0:0]$3710 $3\exc_$signal$6[0:0]$3709 $3\exc_$signal$5[0:0]$3708 $3\exc_$signal$4[0:0]$3707 $3\exc_$signal$3[0:0]$3706 $3\exc_$signal[0:0]$3705 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign { $3\exc_$signal$9[0:0]$3766 $3\exc_$signal$8[0:0]$3765 $3\exc_$signal$7[0:0]$3764 $3\exc_$signal$6[0:0]$3763 $3\exc_$signal$5[0:0]$3762 $3\exc_$signal$4[0:0]$3761 $3\exc_$signal$3[0:0]$3760 $3\exc_$signal[0:0]$3759 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } assign $3\msr[63:0] \cur_msr assign $3\cia[63:0] \cur_pc end @@ -126559,22 +127812,22 @@ module \dec2 assign $2\cr_in1[6:0] $4\cr_in1[6:0] assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] assign $2\cr_in2[6:0] $4\cr_in2[6:0] - assign $2\cr_in2$1[6:0]$3693 $4\cr_in2$1[6:0]$3713 + assign $2\cr_in2$1[6:0]$3747 $4\cr_in2$1[6:0]$3767 assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3694 $4\cr_in2_ok$2[0:0]$3714 + assign $2\cr_in2_ok$2[0:0]$3748 $4\cr_in2_ok$2[0:0]$3768 assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] assign $2\cr_rd[7:0] $4\cr_rd[7:0] assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] assign $2\cr_wr[7:0] $4\cr_wr[7:0] assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3695 $4\exc_$signal[0:0]$3715 - assign $2\exc_$signal$3[0:0]$3696 $4\exc_$signal$3[0:0]$3716 - assign $2\exc_$signal$4[0:0]$3697 $4\exc_$signal$4[0:0]$3717 - assign $2\exc_$signal$5[0:0]$3698 $4\exc_$signal$5[0:0]$3718 - assign $2\exc_$signal$6[0:0]$3699 $4\exc_$signal$6[0:0]$3719 - assign $2\exc_$signal$7[0:0]$3700 $4\exc_$signal$7[0:0]$3720 - assign $2\exc_$signal$8[0:0]$3701 $4\exc_$signal$8[0:0]$3721 - assign $2\exc_$signal$9[0:0]$3702 $4\exc_$signal$9[0:0]$3722 + assign $2\exc_$signal[0:0]$3749 $4\exc_$signal[0:0]$3769 + assign $2\exc_$signal$3[0:0]$3750 $4\exc_$signal$3[0:0]$3770 + assign $2\exc_$signal$4[0:0]$3751 $4\exc_$signal$4[0:0]$3771 + assign $2\exc_$signal$5[0:0]$3752 $4\exc_$signal$5[0:0]$3772 + assign $2\exc_$signal$6[0:0]$3753 $4\exc_$signal$6[0:0]$3773 + assign $2\exc_$signal$7[0:0]$3754 $4\exc_$signal$7[0:0]$3774 + assign $2\exc_$signal$8[0:0]$3755 $4\exc_$signal$8[0:0]$3775 + assign $2\exc_$signal$9[0:0]$3756 $4\exc_$signal$9[0:0]$3776 assign $2\fasto1[2:0] $4\fasto1[2:0] assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] assign $2\fasto2[2:0] $4\fasto2[2:0] @@ -126601,7 +127854,7 @@ module \dec2 assign $2\traptype[7:0] $4\traptype[7:0] assign $2\xer_in[2:0] $4\xer_in[2:0] assign $2\xer_out[0:0] $4\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1160" switch \dec2_exc_$signal$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -126664,7 +127917,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3722 $4\exc_$signal$8[0:0]$3721 $4\exc_$signal$7[0:0]$3720 $4\exc_$signal$6[0:0]$3719 $4\exc_$signal$5[0:0]$3718 $4\exc_$signal$4[0:0]$3717 $4\exc_$signal$3[0:0]$3716 $4\exc_$signal[0:0]$3715 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3714 $4\cr_in2$1[6:0]$3713 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3776 $4\exc_$signal$8[0:0]$3775 $4\exc_$signal$7[0:0]$3774 $4\exc_$signal$6[0:0]$3773 $4\exc_$signal$5[0:0]$3772 $4\exc_$signal$4[0:0]$3771 $4\exc_$signal$3[0:0]$3770 $4\exc_$signal[0:0]$3769 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3768 $4\cr_in2$1[6:0]$3767 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 assign $4\fn_unit[12:0] 13'0000010000000 @@ -126733,7 +127986,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3722 $4\exc_$signal$8[0:0]$3721 $4\exc_$signal$7[0:0]$3720 $4\exc_$signal$6[0:0]$3719 $4\exc_$signal$5[0:0]$3718 $4\exc_$signal$4[0:0]$3717 $4\exc_$signal$3[0:0]$3716 $4\exc_$signal[0:0]$3715 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3714 $4\cr_in2$1[6:0]$3713 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3776 $4\exc_$signal$8[0:0]$3775 $4\exc_$signal$7[0:0]$3774 $4\exc_$signal$6[0:0]$3773 $4\exc_$signal$5[0:0]$3772 $4\exc_$signal$4[0:0]$3771 $4\exc_$signal$3[0:0]$3770 $4\exc_$signal[0:0]$3769 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3768 $4\cr_in2$1[6:0]$3767 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $4\insn[31:0] \dec_opcode_in assign $4\insn_type[6:0] 7'0111111 assign $4\fn_unit[12:0] 13'0000010000000 @@ -126804,7 +128057,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3692 $1\exc_$signal$8[0:0]$3691 $1\exc_$signal$7[0:0]$3690 $1\exc_$signal$6[0:0]$3689 $1\exc_$signal$5[0:0]$3688 $1\exc_$signal$4[0:0]$3687 $1\exc_$signal$3[0:0]$3686 $1\exc_$signal[0:0]$3685 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3684 $1\cr_in2$1[6:0]$3683 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3746 $1\exc_$signal$8[0:0]$3745 $1\exc_$signal$7[0:0]$3744 $1\exc_$signal$6[0:0]$3743 $1\exc_$signal$5[0:0]$3742 $1\exc_$signal$4[0:0]$3741 $1\exc_$signal$3[0:0]$3740 $1\exc_$signal[0:0]$3739 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3738 $1\cr_in2$1[6:0]$3737 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[12:0] 13'0000010000000 @@ -126873,7 +128126,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3692 $1\exc_$signal$8[0:0]$3691 $1\exc_$signal$7[0:0]$3690 $1\exc_$signal$6[0:0]$3689 $1\exc_$signal$5[0:0]$3688 $1\exc_$signal$4[0:0]$3687 $1\exc_$signal$3[0:0]$3686 $1\exc_$signal[0:0]$3685 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3684 $1\cr_in2$1[6:0]$3683 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3746 $1\exc_$signal$8[0:0]$3745 $1\exc_$signal$7[0:0]$3744 $1\exc_$signal$6[0:0]$3743 $1\exc_$signal$5[0:0]$3742 $1\exc_$signal$4[0:0]$3741 $1\exc_$signal$3[0:0]$3740 $1\exc_$signal[0:0]$3739 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3738 $1\cr_in2$1[6:0]$3737 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[12:0] 13'0000010000000 @@ -126942,7 +128195,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3692 $1\exc_$signal$8[0:0]$3691 $1\exc_$signal$7[0:0]$3690 $1\exc_$signal$6[0:0]$3689 $1\exc_$signal$5[0:0]$3688 $1\exc_$signal$4[0:0]$3687 $1\exc_$signal$3[0:0]$3686 $1\exc_$signal[0:0]$3685 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3684 $1\cr_in2$1[6:0]$3683 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3746 $1\exc_$signal$8[0:0]$3745 $1\exc_$signal$7[0:0]$3744 $1\exc_$signal$6[0:0]$3743 $1\exc_$signal$5[0:0]$3742 $1\exc_$signal$4[0:0]$3741 $1\exc_$signal$3[0:0]$3740 $1\exc_$signal[0:0]$3739 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3738 $1\cr_in2$1[6:0]$3737 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[12:0] 13'0000010000000 @@ -127011,7 +128264,7 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3692 $1\exc_$signal$8[0:0]$3691 $1\exc_$signal$7[0:0]$3690 $1\exc_$signal$6[0:0]$3689 $1\exc_$signal$5[0:0]$3688 $1\exc_$signal$4[0:0]$3687 $1\exc_$signal$3[0:0]$3686 $1\exc_$signal[0:0]$3685 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3684 $1\cr_in2$1[6:0]$3683 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3746 $1\exc_$signal$8[0:0]$3745 $1\exc_$signal$7[0:0]$3744 $1\exc_$signal$6[0:0]$3743 $1\exc_$signal$5[0:0]$3742 $1\exc_$signal$4[0:0]$3741 $1\exc_$signal$3[0:0]$3740 $1\exc_$signal[0:0]$3739 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3738 $1\cr_in2$1[6:0]$3737 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 assign $1\insn[31:0] \dec_opcode_in assign $1\insn_type[6:0] 7'0111111 assign $1\fn_unit[12:0] 13'0000010000000 @@ -127080,9 +128333,9 @@ module \dec2 assign { } { } assign { } { } assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3692 $1\exc_$signal$8[0:0]$3691 $1\exc_$signal$7[0:0]$3690 $1\exc_$signal$6[0:0]$3689 $1\exc_$signal$5[0:0]$3688 $1\exc_$signal$4[0:0]$3687 $1\exc_$signal$3[0:0]$3686 $1\exc_$signal[0:0]$3685 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[12:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3684 $1\cr_in2$1[6:0]$3683 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3746 $1\exc_$signal$8[0:0]$3745 $1\exc_$signal$7[0:0]$3744 $1\exc_$signal$6[0:0]$3743 $1\exc_$signal$5[0:0]$3742 $1\exc_$signal$4[0:0]$3741 $1\exc_$signal$3[0:0]$3740 $1\exc_$signal[0:0]$3739 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[12:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3738 $1\cr_in2$1[6:0]$3737 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1195" switch \$32 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127100,7 +128353,7 @@ module \dec2 assign $5\fasto2[2:0] $1\fasto2[2:0] assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127136,22 +128389,22 @@ module \dec2 update \cr_in1 $0\cr_in1[6:0] update \cr_in1_ok $0\cr_in1_ok[0:0] update \cr_in2 $0\cr_in2[6:0] - update \cr_in2$1 $0\cr_in2$1[6:0]$3673 + update \cr_in2$1 $0\cr_in2$1[6:0]$3727 update \cr_in2_ok $0\cr_in2_ok[0:0] - update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3674 + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3728 update \cr_out_ok $0\cr_out_ok[0:0] update \cr_rd $0\cr_rd[7:0] update \cr_rd_ok $0\cr_rd_ok[0:0] update \cr_wr $0\cr_wr[7:0] update \cr_wr_ok $0\cr_wr_ok[0:0] - update \exc_$signal $0\exc_$signal[0:0]$3675 - update \exc_$signal$3 $0\exc_$signal$3[0:0]$3676 - update \exc_$signal$4 $0\exc_$signal$4[0:0]$3677 - update \exc_$signal$5 $0\exc_$signal$5[0:0]$3678 - update \exc_$signal$6 $0\exc_$signal$6[0:0]$3679 - update \exc_$signal$7 $0\exc_$signal$7[0:0]$3680 - update \exc_$signal$8 $0\exc_$signal$8[0:0]$3681 - update \exc_$signal$9 $0\exc_$signal$9[0:0]$3682 + update \exc_$signal $0\exc_$signal[0:0]$3729 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$3730 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$3731 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$3732 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$3733 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$3734 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$3735 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$3736 update \fasto1 $0\fasto1[2:0] update \fasto1_ok $0\fasto1_ok[0:0] update \fasto2 $0\fasto2[2:0] @@ -127179,42 +128432,18 @@ module \dec2 update \xer_in $0\xer_in[2:0] update \xer_out $0\xer_out[0:0] end - attribute \src "libresoc.v:79006.3-79017.6" - process $proc$libresoc.v:79006$3723 - assign { } { } - assign $0\tmp_tmp_fn_unit[12:0] $1\tmp_tmp_fn_unit[12:0] - attribute \src "libresoc.v:79007.5-79007.29" - switch \initial - attribute \src "libresoc.v:79007.9-79007.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \$57 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_tmp_fn_unit[12:0] 13'0100000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\tmp_tmp_fn_unit[12:0] \dec_function_unit - end - sync always - update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[12:0] - end - attribute \src "libresoc.v:79018.3-79027.6" - process $proc$libresoc.v:79018$3724 + attribute \src "libresoc.v:79498.3-79507.6" + process $proc$libresoc.v:79498$3777 assign { } { } assign { } { } assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:79019.5-79019.29" + attribute \src "libresoc.v:79499.5-79499.29" switch \initial - attribute \src "libresoc.v:79019.9-79019.17" + attribute \src "libresoc.v:79499.9-79499.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:957" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:857" switch \dec_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -127226,19 +128455,19 @@ module \dec2 sync always update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "libresoc.v:79028.3-79037.6" - process $proc$libresoc.v:79028$3725 + attribute \src "libresoc.v:79508.3-79517.6" + process $proc$libresoc.v:79508$3778 assign { } { } assign { } { } assign $0\cr_a_idx[2:0] $1\cr_a_idx[2:0] - attribute \src "libresoc.v:79029.5-79029.29" + attribute \src "libresoc.v:79509.5-79509.29" switch \initial - attribute \src "libresoc.v:79029.9-79029.17" + attribute \src "libresoc.v:79509.9-79509.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1090" - switch \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1007" + switch \$90 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -127249,19 +128478,19 @@ module \dec2 sync always update \cr_a_idx $0\cr_a_idx[2:0] end - attribute \src "libresoc.v:79038.3-79047.6" - process $proc$libresoc.v:79038$3726 + attribute \src "libresoc.v:79518.3-79527.6" + process $proc$libresoc.v:79518$3779 assign { } { } assign { } { } assign $0\cr_b_idx[2:0] $1\cr_b_idx[2:0] - attribute \src "libresoc.v:79039.5-79039.29" + attribute \src "libresoc.v:79519.5-79519.29" switch \initial - attribute \src "libresoc.v:79039.9-79039.17" + attribute \src "libresoc.v:79519.9-79519.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1090" - switch \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1007" + switch \$92 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -127272,22 +128501,22 @@ module \dec2 sync always update \cr_b_idx $0\cr_b_idx[2:0] end - attribute \src "libresoc.v:79048.3-79059.6" - process $proc$libresoc.v:79048$3727 + attribute \src "libresoc.v:79528.3-79539.6" + process $proc$libresoc.v:79528$3780 assign { } { } assign $0\tmp_reg1[6:0] $1\tmp_reg1[6:0] - attribute \src "libresoc.v:79049.5-79049.29" + attribute \src "libresoc.v:79529.5-79529.29" switch \initial - attribute \src "libresoc.v:79049.9-79049.17" + attribute \src "libresoc.v:79529.9-79529.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1046" switch \in1_svdec_isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\tmp_reg1[6:0] \$68 [6:0] + assign $1\tmp_reg1[6:0] \$94 [6:0] attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -127296,22 +128525,22 @@ module \dec2 sync always update \tmp_reg1 $0\tmp_reg1[6:0] end - attribute \src "libresoc.v:79060.3-79071.6" - process $proc$libresoc.v:79060$3728 + attribute \src "libresoc.v:79540.3-79551.6" + process $proc$libresoc.v:79540$3781 assign { } { } assign $0\tmp_reg2[6:0] $1\tmp_reg2[6:0] - attribute \src "libresoc.v:79061.5-79061.29" + attribute \src "libresoc.v:79541.5-79541.29" switch \initial - attribute \src "libresoc.v:79061.9-79061.17" + attribute \src "libresoc.v:79541.9-79541.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1046" switch \in2_svdec_isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\tmp_reg2[6:0] \$71 [6:0] + assign $1\tmp_reg2[6:0] \$97 [6:0] attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -127320,22 +128549,22 @@ module \dec2 sync always update \tmp_reg2 $0\tmp_reg2[6:0] end - attribute \src "libresoc.v:79072.3-79083.6" - process $proc$libresoc.v:79072$3729 + attribute \src "libresoc.v:79552.3-79563.6" + process $proc$libresoc.v:79552$3782 assign { } { } assign $0\tmp_reg3[6:0] $1\tmp_reg3[6:0] - attribute \src "libresoc.v:79073.5-79073.29" + attribute \src "libresoc.v:79553.5-79553.29" switch \initial - attribute \src "libresoc.v:79073.9-79073.17" + attribute \src "libresoc.v:79553.9-79553.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1046" switch \in3_svdec_isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\tmp_reg3[6:0] \$74 [6:0] + assign $1\tmp_reg3[6:0] \$100 [6:0] attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -127344,22 +128573,49 @@ module \dec2 sync always update \tmp_reg3 $0\tmp_reg3[6:0] end - attribute \src "libresoc.v:79084.3-79095.6" - process $proc$libresoc.v:79084$3730 + attribute \src "libresoc.v:79564.3-79576.6" + process $proc$libresoc.v:79564$3783 + assign { } { } + assign { } { } + assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0] + attribute \src "libresoc.v:79565.5-79565.29" + switch \initial + attribute \src "libresoc.v:79565.9-79565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$49 \$41 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\tmp_tmp_insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\tmp_tmp_insn_type[6:0] 7'0000000 + case + assign $1\tmp_tmp_insn_type[6:0] \dec_internal_op + end + sync always + update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0] + end + attribute \src "libresoc.v:79577.3-79588.6" + process $proc$libresoc.v:79577$3784 assign { } { } assign $0\tmp_rego[6:0] $1\tmp_rego[6:0] - attribute \src "libresoc.v:79085.5-79085.29" + attribute \src "libresoc.v:79578.5-79578.29" switch \initial - attribute \src "libresoc.v:79085.9-79085.17" + attribute \src "libresoc.v:79578.9-79578.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1046" switch \o_svdec_isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\tmp_rego[6:0] \$77 [6:0] + assign $1\tmp_rego[6:0] \$103 [6:0] attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -127368,22 +128624,22 @@ module \dec2 sync always update \tmp_rego $0\tmp_rego[6:0] end - attribute \src "libresoc.v:79096.3-79107.6" - process $proc$libresoc.v:79096$3731 + attribute \src "libresoc.v:79589.3-79600.6" + process $proc$libresoc.v:79589$3785 assign { } { } assign $0\tmp_ea[6:0] $1\tmp_ea[6:0] - attribute \src "libresoc.v:79097.5-79097.29" + attribute \src "libresoc.v:79590.5-79590.29" switch \initial - attribute \src "libresoc.v:79097.9-79097.17" + attribute \src "libresoc.v:79590.9-79590.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1046" switch \o2_svdec_isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\tmp_ea[6:0] \$80 [6:0] + assign $1\tmp_ea[6:0] \$106 [6:0] attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -127392,44 +128648,90 @@ module \dec2 sync always update \tmp_ea $0\tmp_ea[6:0] end - connect \$99 $and$libresoc.v:78536$3635_Y - connect \$101 $and$libresoc.v:78537$3636_Y - connect \$103 $eq$libresoc.v:78538$3637_Y - connect \$28 $eq$libresoc.v:78539$3638_Y - connect \$30 $eq$libresoc.v:78540$3639_Y - connect \$32 $or$libresoc.v:78541$3640_Y - connect \$34 $eq$libresoc.v:78542$3641_Y - connect \$37 $eq$libresoc.v:78543$3642_Y - connect \$39 $eq$libresoc.v:78544$3643_Y - connect \$41 $or$libresoc.v:78545$3644_Y - connect \$43 $eq$libresoc.v:78546$3645_Y - connect \$45 $eq$libresoc.v:78547$3646_Y - connect \$47 $or$libresoc.v:78548$3647_Y - connect \$49 $eq$libresoc.v:78549$3648_Y - connect \$51 $or$libresoc.v:78550$3649_Y - connect \$53 $eq$libresoc.v:78551$3650_Y - connect \$55 $or$libresoc.v:78552$3651_Y - connect \$57 $and$libresoc.v:78553$3652_Y - connect \$64 $eq$libresoc.v:78554$3653_Y - connect \$66 $eq$libresoc.v:78555$3654_Y - connect \$69 $add$libresoc.v:78556$3655_Y - connect \$72 $add$libresoc.v:78557$3656_Y - connect \$75 $add$libresoc.v:78558$3657_Y - connect \$78 $add$libresoc.v:78559$3658_Y - connect \$81 $add$libresoc.v:78560$3659_Y - connect \$83 $not$libresoc.v:78561$3660_Y - connect \$85 $not$libresoc.v:78562$3661_Y - connect \$87 $and$libresoc.v:78563$3662_Y - connect \$89 $eq$libresoc.v:78564$3663_Y - connect \$91 $eq$libresoc.v:78565$3664_Y - connect \$93 $eq$libresoc.v:78566$3665_Y - connect \$95 $eq$libresoc.v:78567$3666_Y - connect \$97 $and$libresoc.v:78568$3667_Y - connect \$68 \$69 - connect \$71 \$72 - connect \$74 \$75 - connect \$77 \$78 - connect \$80 \$81 + connect \$101 $add$libresoc.v:78885$3647_Y + connect \$104 $add$libresoc.v:78886$3648_Y + connect \$107 $add$libresoc.v:78887$3649_Y + connect \$110 $reduce_or$libresoc.v:78888$3650_Y + connect \$109 $not$libresoc.v:78889$3651_Y + connect \$114 $reduce_or$libresoc.v:78890$3652_Y + connect \$113 $not$libresoc.v:78891$3653_Y + connect \$117 $eq$libresoc.v:78892$3654_Y + connect \$119 $eq$libresoc.v:78893$3655_Y + connect \$122 $add$libresoc.v:78894$3656_Y + connect \$125 $add$libresoc.v:78895$3657_Y + connect \$128 $add$libresoc.v:78896$3658_Y + connect \$130 $eq$libresoc.v:78897$3659_Y + connect \$132 $eq$libresoc.v:78898$3660_Y + connect \$135 $add$libresoc.v:78899$3661_Y + connect \$138 $add$libresoc.v:78900$3662_Y + connect \$141 $add$libresoc.v:78901$3663_Y + connect \$143 $eq$libresoc.v:78902$3664_Y + connect \$145 $eq$libresoc.v:78903$3665_Y + connect \$148 $add$libresoc.v:78904$3666_Y + connect \$151 $add$libresoc.v:78905$3667_Y + connect \$154 $add$libresoc.v:78906$3668_Y + connect \$156 $eq$libresoc.v:78907$3669_Y + connect \$158 $eq$libresoc.v:78908$3670_Y + connect \$161 $add$libresoc.v:78909$3671_Y + connect \$164 $add$libresoc.v:78910$3672_Y + connect \$167 $add$libresoc.v:78911$3673_Y + connect \$169 $eq$libresoc.v:78912$3674_Y + connect \$171 $eq$libresoc.v:78913$3675_Y + connect \$173 $eq$libresoc.v:78914$3676_Y + connect \$175 $eq$libresoc.v:78915$3677_Y + connect \$177 $and$libresoc.v:78916$3678_Y + connect \$179 $and$libresoc.v:78917$3679_Y + connect \$181 $and$libresoc.v:78918$3680_Y + connect \$183 $eq$libresoc.v:78919$3681_Y + connect \$28 $eq$libresoc.v:78920$3682_Y + connect \$30 $eq$libresoc.v:78921$3683_Y + connect \$32 $or$libresoc.v:78922$3684_Y + connect \$34 $eq$libresoc.v:78923$3685_Y + connect \$37 $eq$libresoc.v:78924$3686_Y + connect \$39 $and$libresoc.v:78925$3687_Y + connect \$41 $and$libresoc.v:78926$3688_Y + connect \$43 $eq$libresoc.v:78927$3689_Y + connect \$45 $and$libresoc.v:78928$3690_Y + connect \$47 $not$libresoc.v:78929$3691_Y + connect \$49 $and$libresoc.v:78930$3692_Y + connect \$51 $eq$libresoc.v:78931$3693_Y + connect \$53 $eq$libresoc.v:78932$3694_Y + connect \$55 $or$libresoc.v:78933$3695_Y + connect \$57 $eq$libresoc.v:78934$3696_Y + connect \$59 $eq$libresoc.v:78935$3697_Y + connect \$61 $or$libresoc.v:78936$3698_Y + connect \$63 $eq$libresoc.v:78937$3699_Y + connect \$65 $or$libresoc.v:78938$3700_Y + connect \$67 $eq$libresoc.v:78939$3701_Y + connect \$69 $or$libresoc.v:78940$3702_Y + connect \$71 $eq$libresoc.v:78941$3703_Y + connect \$73 $and$libresoc.v:78942$3704_Y + connect \$75 $and$libresoc.v:78943$3705_Y + connect \$77 $eq$libresoc.v:78944$3706_Y + connect \$79 $and$libresoc.v:78945$3707_Y + connect \$81 $not$libresoc.v:78946$3708_Y + connect \$83 $and$libresoc.v:78947$3709_Y + connect \$90 $eq$libresoc.v:78948$3710_Y + connect \$92 $eq$libresoc.v:78949$3711_Y + connect \$95 $add$libresoc.v:78950$3712_Y + connect \$98 $add$libresoc.v:78951$3713_Y + connect \$94 \$95 + connect \$97 \$98 + connect \$100 \$101 + connect \$103 \$104 + connect \$106 \$107 + connect \$121 \$122 + connect \$124 \$125 + connect \$127 \$128 + connect \$134 \$135 + connect \$137 \$138 + connect \$140 \$141 + connect \$147 \$148 + connect \$150 \$151 + connect \$153 \$154 + connect \$160 \$161 + connect \$163 \$164 + connect \$166 \$167 connect \dec2_exc_$signal 1'0 connect \dec2_exc_$signal$12 1'0 connect \dec2_exc_$signal$13 1'0 @@ -127448,27 +128750,23 @@ module \dec2 connect \tmp_tmp_exc_$signal$25 1'0 connect \tmp_tmp_exc_$signal$26 1'0 connect \tmp_tmp_exc_$signal$27 1'0 - connect \illeg_ok \$103 - connect \priv_ok \$101 - connect \dec_irq_ok \$99 - connect \ext_irq_ok \$97 + connect \illeg_ok \$183 + connect \priv_ok \$181 + connect \dec_irq_ok \$179 + connect \ext_irq_ok \$177 connect \tmp_cr_out_ok \dec_cr_out_cr_bitfield_ok - connect \tmp_cr_out \crout_svdec_cr_out connect \crout_svdec_cr_in \dec_cr_out_cr_bitfield connect \crout_svdec_etype \dec_SV_Etype connect \crout_svdec_extra \dec_svp64__extra connect \tmp_cr_in2_ok$20 \dec_cr_in_cr_bitfield_o_ok - connect \tmp_cr_in2$19 \crin_svdec_o_cr_out connect \crin_svdec_o_cr_in \dec_cr_in_cr_bitfield_o connect \crin_svdec_o_etype \dec_SV_Etype connect \crin_svdec_o_extra \dec_svp64__extra connect \tmp_cr_in2_ok \dec_cr_in_cr_bitfield_b_ok - connect \tmp_cr_in2 \crin_svdec_b_cr_out connect \crin_svdec_b_cr_in \dec_cr_in_cr_bitfield_b connect \crin_svdec_b_etype \dec_SV_Etype connect \crin_svdec_b_extra \dec_svp64__extra connect \tmp_cr_in1_ok \dec_cr_in_cr_bitfield_ok - connect \tmp_cr_in1 \crin_svdec_cr_out connect \crin_svdec_cr_in \dec_cr_in_cr_bitfield connect \crin_svdec_etype \dec_SV_Etype connect \crin_svdec_extra \dec_svp64__extra @@ -127478,7 +128776,8 @@ module \dec2 connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } - connect \no_out_vec \$87 + connect \no_out_vec \$113 + connect \no_in_vec \$109 connect \reg_o2_isvec \o2_svdec_isvec connect \reg_o_isvec \o_svdec_isvec connect \reg_c_isvec \in3_svdec_isvec @@ -127523,166 +128822,167 @@ module \dec2 connect \cr_in_isvec \crin_svdec_isvec connect \cr_out_isvec \crout_svdec_isvec connect \crout_svdec_idx \dec_sv_cr_out - connect \insn_in$63 \dec_opcode_in - connect \insn_in$62 \dec_opcode_in - connect \insn_in$61 \dec_opcode_in - connect \insn_in$60 \dec_opcode_in - connect \insn_in$59 \dec_opcode_in + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \insn_in$89 \dec_opcode_in + connect \insn_in$88 \dec_opcode_in + connect \insn_in$87 \dec_opcode_in + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$86 \dec_opcode_in + connect \insn_in$85 \dec_opcode_in connect \tmp_tmp_insn \dec_opcode_in connect \tmp_tmp_is_32bit \dec_is_32b connect \tmp_tmp_input_carry \dec_cry_in - connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } - connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } + connect \is_mmu_spr \$69 + connect \is_spr_mv \$55 connect \spr { \dec_SPR [4:0] \dec_SPR [9:5] } - connect \tmp_tmp_insn_type \dec_internal_op connect \tmp_tmp_cia \cur_pc connect \tmp_tmp_msr \cur_msr - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_cr_out - connect \dec_cr_in_sel_in \dec_cr_in connect \dec_oe_sel_in \dec_rc_sel connect \dec_rc_sel_in \dec_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$36 \dec_opcode_in connect \insn_in \dec_opcode_in end -attribute \src "libresoc.v:79235.1-80755.10" +attribute \src "libresoc.v:79738.1-81259.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" module \dec30 - attribute \src "libresoc.v:80532.3-80568.6" + attribute \src "libresoc.v:81036.3-81072.6" wire width 2 $0\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:80569.3-80605.6" + attribute \src "libresoc.v:81073.3-81109.6" wire width 2 $0\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:80088.3-80124.6" + attribute \src "libresoc.v:80592.3-80628.6" wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:80236.3-80272.6" + attribute \src "libresoc.v:80740.3-80776.6" wire $0\dec30_br[0:0] - attribute \src "libresoc.v:79607.3-79643.6" + attribute \src "libresoc.v:80111.3-80147.6" wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:79644.3-79680.6" + attribute \src "libresoc.v:80148.3-80184.6" wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:80051.3-80087.6" + attribute \src "libresoc.v:80555.3-80591.6" wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:80199.3-80235.6" + attribute \src "libresoc.v:80703.3-80739.6" wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:80384.3-80420.6" + attribute \src "libresoc.v:80888.3-80924.6" wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:79570.3-79606.6" + attribute \src "libresoc.v:80074.3-80110.6" wire width 13 $0\dec30_function_unit[12:0] - attribute \src "libresoc.v:80606.3-80642.6" + attribute \src "libresoc.v:81110.3-81146.6" wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:80643.3-80679.6" + attribute \src "libresoc.v:81147.3-81183.6" wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:80680.3-80716.6" + attribute \src "libresoc.v:81184.3-81220.6" wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:79977.3-80013.6" + attribute \src "libresoc.v:80481.3-80517.6" wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:80125.3-80161.6" + attribute \src "libresoc.v:80629.3-80665.6" wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:80162.3-80198.6" + attribute \src "libresoc.v:80666.3-80702.6" wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:80347.3-80383.6" + attribute \src "libresoc.v:80851.3-80887.6" wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:79903.3-79939.6" + attribute \src "libresoc.v:80407.3-80443.6" wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:80458.3-80494.6" + attribute \src "libresoc.v:80962.3-80998.6" wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:80717.3-80753.6" + attribute \src "libresoc.v:81221.3-81257.6" wire width 2 $0\dec30_out_sel[1:0] - attribute \src "libresoc.v:80014.3-80050.6" + attribute \src "libresoc.v:80518.3-80554.6" wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:80310.3-80346.6" + attribute \src "libresoc.v:80814.3-80850.6" wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:80495.3-80531.6" + attribute \src "libresoc.v:80999.3-81035.6" wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:80421.3-80457.6" + attribute \src "libresoc.v:80925.3-80961.6" wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:80273.3-80309.6" + attribute \src "libresoc.v:80777.3-80813.6" wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:79829.3-79865.6" + attribute \src "libresoc.v:80333.3-80369.6" wire width 3 $0\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:79866.3-79902.6" + attribute \src "libresoc.v:80370.3-80406.6" wire width 3 $0\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:79681.3-79717.6" + attribute \src "libresoc.v:80185.3-80221.6" wire width 3 $0\dec30_sv_in1[2:0] - attribute \src "libresoc.v:79718.3-79754.6" + attribute \src "libresoc.v:80222.3-80258.6" wire width 3 $0\dec30_sv_in2[2:0] - attribute \src "libresoc.v:79755.3-79791.6" + attribute \src "libresoc.v:80259.3-80295.6" wire width 3 $0\dec30_sv_in3[2:0] - attribute \src "libresoc.v:79792.3-79828.6" + attribute \src "libresoc.v:80296.3-80332.6" wire width 3 $0\dec30_sv_out[2:0] - attribute \src "libresoc.v:79940.3-79976.6" + attribute \src "libresoc.v:80444.3-80480.6" wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:79236.7-79236.20" + attribute \src "libresoc.v:79739.7-79739.20" wire $0\initial[0:0] - attribute \src "libresoc.v:80532.3-80568.6" + attribute \src "libresoc.v:81036.3-81072.6" wire width 2 $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:80569.3-80605.6" + attribute \src "libresoc.v:81073.3-81109.6" wire width 2 $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:80088.3-80124.6" + attribute \src "libresoc.v:80592.3-80628.6" wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:80236.3-80272.6" + attribute \src "libresoc.v:80740.3-80776.6" wire $1\dec30_br[0:0] - attribute \src "libresoc.v:79607.3-79643.6" + attribute \src "libresoc.v:80111.3-80147.6" wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:79644.3-79680.6" + attribute \src "libresoc.v:80148.3-80184.6" wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:80051.3-80087.6" + attribute \src "libresoc.v:80555.3-80591.6" wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:80199.3-80235.6" + attribute \src "libresoc.v:80703.3-80739.6" wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:80384.3-80420.6" + attribute \src "libresoc.v:80888.3-80924.6" wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:79570.3-79606.6" + attribute \src "libresoc.v:80074.3-80110.6" wire width 13 $1\dec30_function_unit[12:0] - attribute \src "libresoc.v:80606.3-80642.6" + attribute \src "libresoc.v:81110.3-81146.6" wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:80643.3-80679.6" + attribute \src "libresoc.v:81147.3-81183.6" wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:80680.3-80716.6" + attribute \src "libresoc.v:81184.3-81220.6" wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:79977.3-80013.6" + attribute \src "libresoc.v:80481.3-80517.6" wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:80125.3-80161.6" + attribute \src "libresoc.v:80629.3-80665.6" wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:80162.3-80198.6" + attribute \src "libresoc.v:80666.3-80702.6" wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:80347.3-80383.6" + attribute \src "libresoc.v:80851.3-80887.6" wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:79903.3-79939.6" + attribute \src "libresoc.v:80407.3-80443.6" wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:80458.3-80494.6" + attribute \src "libresoc.v:80962.3-80998.6" wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:80717.3-80753.6" + attribute \src "libresoc.v:81221.3-81257.6" wire width 2 $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:80014.3-80050.6" + attribute \src "libresoc.v:80518.3-80554.6" wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:80310.3-80346.6" + attribute \src "libresoc.v:80814.3-80850.6" wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:80495.3-80531.6" + attribute \src "libresoc.v:80999.3-81035.6" wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:80421.3-80457.6" + attribute \src "libresoc.v:80925.3-80961.6" wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:80273.3-80309.6" + attribute \src "libresoc.v:80777.3-80813.6" wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:79829.3-79865.6" + attribute \src "libresoc.v:80333.3-80369.6" wire width 3 $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:79866.3-79902.6" + attribute \src "libresoc.v:80370.3-80406.6" wire width 3 $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:79681.3-79717.6" + attribute \src "libresoc.v:80185.3-80221.6" wire width 3 $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:79718.3-79754.6" + attribute \src "libresoc.v:80222.3-80258.6" wire width 3 $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:79755.3-79791.6" + attribute \src "libresoc.v:80259.3-80295.6" wire width 3 $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:79792.3-79828.6" + attribute \src "libresoc.v:80296.3-80332.6" wire width 3 $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:79940.3-79976.6" + attribute \src "libresoc.v:80444.3-80480.6" wire width 2 $1\dec30_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -127758,6 +129058,7 @@ module \dec30 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec30_form attribute \enum_base_type "Function" @@ -127981,28 +129282,28 @@ module \dec30 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec30_upd - attribute \src "libresoc.v:79236.7-79236.15" + attribute \src "libresoc.v:79739.7-79739.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 4 \opcode_switch - attribute \src "libresoc.v:79236.7-79236.20" - process $proc$libresoc.v:79236$3765 + attribute \src "libresoc.v:79739.7-79739.20" + process $proc$libresoc.v:79739$3819 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:79570.3-79606.6" - process $proc$libresoc.v:79570$3733 + attribute \src "libresoc.v:80074.3-80110.6" + process $proc$libresoc.v:80074$3787 assign { } { } assign { } { } assign $0\dec30_function_unit[12:0] $1\dec30_function_unit[12:0] - attribute \src "libresoc.v:79571.5-79571.29" + attribute \src "libresoc.v:80075.5-80075.29" switch \initial - attribute \src "libresoc.v:79571.9-79571.17" + attribute \src "libresoc.v:80075.9-80075.17" case 1'1 case end @@ -128054,14 +129355,14 @@ module \dec30 sync always update \dec30_function_unit $0\dec30_function_unit[12:0] end - attribute \src "libresoc.v:79607.3-79643.6" - process $proc$libresoc.v:79607$3734 + attribute \src "libresoc.v:80111.3-80147.6" + process $proc$libresoc.v:80111$3788 assign { } { } assign { } { } assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:79608.5-79608.29" + attribute \src "libresoc.v:80112.5-80112.29" switch \initial - attribute \src "libresoc.v:79608.9-79608.17" + attribute \src "libresoc.v:80112.9-80112.17" case 1'1 case end @@ -128113,14 +129414,14 @@ module \dec30 sync always update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "libresoc.v:79644.3-79680.6" - process $proc$libresoc.v:79644$3735 + attribute \src "libresoc.v:80148.3-80184.6" + process $proc$libresoc.v:80148$3789 assign { } { } assign { } { } assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:79645.5-79645.29" + attribute \src "libresoc.v:80149.5-80149.29" switch \initial - attribute \src "libresoc.v:79645.9-79645.17" + attribute \src "libresoc.v:80149.9-80149.17" case 1'1 case end @@ -128172,14 +129473,14 @@ module \dec30 sync always update \dec30_cr_out $0\dec30_cr_out[2:0] end - attribute \src "libresoc.v:79681.3-79717.6" - process $proc$libresoc.v:79681$3736 + attribute \src "libresoc.v:80185.3-80221.6" + process $proc$libresoc.v:80185$3790 assign { } { } assign { } { } assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:79682.5-79682.29" + attribute \src "libresoc.v:80186.5-80186.29" switch \initial - attribute \src "libresoc.v:79682.9-79682.17" + attribute \src "libresoc.v:80186.9-80186.17" case 1'1 case end @@ -128231,14 +129532,14 @@ module \dec30 sync always update \dec30_sv_in1 $0\dec30_sv_in1[2:0] end - attribute \src "libresoc.v:79718.3-79754.6" - process $proc$libresoc.v:79718$3737 + attribute \src "libresoc.v:80222.3-80258.6" + process $proc$libresoc.v:80222$3791 assign { } { } assign { } { } assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:79719.5-79719.29" + attribute \src "libresoc.v:80223.5-80223.29" switch \initial - attribute \src "libresoc.v:79719.9-79719.17" + attribute \src "libresoc.v:80223.9-80223.17" case 1'1 case end @@ -128290,14 +129591,14 @@ module \dec30 sync always update \dec30_sv_in2 $0\dec30_sv_in2[2:0] end - attribute \src "libresoc.v:79755.3-79791.6" - process $proc$libresoc.v:79755$3738 + attribute \src "libresoc.v:80259.3-80295.6" + process $proc$libresoc.v:80259$3792 assign { } { } assign { } { } assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:79756.5-79756.29" + attribute \src "libresoc.v:80260.5-80260.29" switch \initial - attribute \src "libresoc.v:79756.9-79756.17" + attribute \src "libresoc.v:80260.9-80260.17" case 1'1 case end @@ -128349,14 +129650,14 @@ module \dec30 sync always update \dec30_sv_in3 $0\dec30_sv_in3[2:0] end - attribute \src "libresoc.v:79792.3-79828.6" - process $proc$libresoc.v:79792$3739 + attribute \src "libresoc.v:80296.3-80332.6" + process $proc$libresoc.v:80296$3793 assign { } { } assign { } { } assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:79793.5-79793.29" + attribute \src "libresoc.v:80297.5-80297.29" switch \initial - attribute \src "libresoc.v:79793.9-79793.17" + attribute \src "libresoc.v:80297.9-80297.17" case 1'1 case end @@ -128408,14 +129709,14 @@ module \dec30 sync always update \dec30_sv_out $0\dec30_sv_out[2:0] end - attribute \src "libresoc.v:79829.3-79865.6" - process $proc$libresoc.v:79829$3740 + attribute \src "libresoc.v:80333.3-80369.6" + process $proc$libresoc.v:80333$3794 assign { } { } assign { } { } assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:79830.5-79830.29" + attribute \src "libresoc.v:80334.5-80334.29" switch \initial - attribute \src "libresoc.v:79830.9-79830.17" + attribute \src "libresoc.v:80334.9-80334.17" case 1'1 case end @@ -128467,14 +129768,14 @@ module \dec30 sync always update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] end - attribute \src "libresoc.v:79866.3-79902.6" - process $proc$libresoc.v:79866$3741 + attribute \src "libresoc.v:80370.3-80406.6" + process $proc$libresoc.v:80370$3795 assign { } { } assign { } { } assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:79867.5-79867.29" + attribute \src "libresoc.v:80371.5-80371.29" switch \initial - attribute \src "libresoc.v:79867.9-79867.17" + attribute \src "libresoc.v:80371.9-80371.17" case 1'1 case end @@ -128526,14 +129827,14 @@ module \dec30 sync always update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] end - attribute \src "libresoc.v:79903.3-79939.6" - process $proc$libresoc.v:79903$3742 + attribute \src "libresoc.v:80407.3-80443.6" + process $proc$libresoc.v:80407$3796 assign { } { } assign { } { } assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:79904.5-79904.29" + attribute \src "libresoc.v:80408.5-80408.29" switch \initial - attribute \src "libresoc.v:79904.9-79904.17" + attribute \src "libresoc.v:80408.9-80408.17" case 1'1 case end @@ -128585,14 +129886,14 @@ module \dec30 sync always update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "libresoc.v:79940.3-79976.6" - process $proc$libresoc.v:79940$3743 + attribute \src "libresoc.v:80444.3-80480.6" + process $proc$libresoc.v:80444$3797 assign { } { } assign { } { } assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:79941.5-79941.29" + attribute \src "libresoc.v:80445.5-80445.29" switch \initial - attribute \src "libresoc.v:79941.9-79941.17" + attribute \src "libresoc.v:80445.9-80445.17" case 1'1 case end @@ -128644,14 +129945,14 @@ module \dec30 sync always update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "libresoc.v:79977.3-80013.6" - process $proc$libresoc.v:79977$3744 + attribute \src "libresoc.v:80481.3-80517.6" + process $proc$libresoc.v:80481$3798 assign { } { } assign { } { } assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:79978.5-79978.29" + attribute \src "libresoc.v:80482.5-80482.29" switch \initial - attribute \src "libresoc.v:79978.9-79978.17" + attribute \src "libresoc.v:80482.9-80482.17" case 1'1 case end @@ -128703,14 +130004,14 @@ module \dec30 sync always update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "libresoc.v:80014.3-80050.6" - process $proc$libresoc.v:80014$3745 + attribute \src "libresoc.v:80518.3-80554.6" + process $proc$libresoc.v:80518$3799 assign { } { } assign { } { } assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:80015.5-80015.29" + attribute \src "libresoc.v:80519.5-80519.29" switch \initial - attribute \src "libresoc.v:80015.9-80015.17" + attribute \src "libresoc.v:80519.9-80519.17" case 1'1 case end @@ -128762,14 +130063,14 @@ module \dec30 sync always update \dec30_rc_sel $0\dec30_rc_sel[1:0] end - attribute \src "libresoc.v:80051.3-80087.6" - process $proc$libresoc.v:80051$3746 + attribute \src "libresoc.v:80555.3-80591.6" + process $proc$libresoc.v:80555$3800 assign { } { } assign { } { } assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:80052.5-80052.29" + attribute \src "libresoc.v:80556.5-80556.29" switch \initial - attribute \src "libresoc.v:80052.9-80052.17" + attribute \src "libresoc.v:80556.9-80556.17" case 1'1 case end @@ -128821,14 +130122,14 @@ module \dec30 sync always update \dec30_cry_in $0\dec30_cry_in[1:0] end - attribute \src "libresoc.v:80088.3-80124.6" - process $proc$libresoc.v:80088$3747 + attribute \src "libresoc.v:80592.3-80628.6" + process $proc$libresoc.v:80592$3801 assign { } { } assign { } { } assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:80089.5-80089.29" + attribute \src "libresoc.v:80593.5-80593.29" switch \initial - attribute \src "libresoc.v:80089.9-80089.17" + attribute \src "libresoc.v:80593.9-80593.17" case 1'1 case end @@ -128880,14 +130181,14 @@ module \dec30 sync always update \dec30_asmcode $0\dec30_asmcode[7:0] end - attribute \src "libresoc.v:80125.3-80161.6" - process $proc$libresoc.v:80125$3748 + attribute \src "libresoc.v:80629.3-80665.6" + process $proc$libresoc.v:80629$3802 assign { } { } assign { } { } assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:80126.5-80126.29" + attribute \src "libresoc.v:80630.5-80630.29" switch \initial - attribute \src "libresoc.v:80126.9-80126.17" + attribute \src "libresoc.v:80630.9-80630.17" case 1'1 case end @@ -128939,14 +130240,14 @@ module \dec30 sync always update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "libresoc.v:80162.3-80198.6" - process $proc$libresoc.v:80162$3749 + attribute \src "libresoc.v:80666.3-80702.6" + process $proc$libresoc.v:80666$3803 assign { } { } assign { } { } assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:80163.5-80163.29" + attribute \src "libresoc.v:80667.5-80667.29" switch \initial - attribute \src "libresoc.v:80163.9-80163.17" + attribute \src "libresoc.v:80667.9-80667.17" case 1'1 case end @@ -128998,14 +130299,14 @@ module \dec30 sync always update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "libresoc.v:80199.3-80235.6" - process $proc$libresoc.v:80199$3750 + attribute \src "libresoc.v:80703.3-80739.6" + process $proc$libresoc.v:80703$3804 assign { } { } assign { } { } assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:80200.5-80200.29" + attribute \src "libresoc.v:80704.5-80704.29" switch \initial - attribute \src "libresoc.v:80200.9-80200.17" + attribute \src "libresoc.v:80704.9-80704.17" case 1'1 case end @@ -129057,14 +130358,14 @@ module \dec30 sync always update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "libresoc.v:80236.3-80272.6" - process $proc$libresoc.v:80236$3751 + attribute \src "libresoc.v:80740.3-80776.6" + process $proc$libresoc.v:80740$3805 assign { } { } assign { } { } assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:80237.5-80237.29" + attribute \src "libresoc.v:80741.5-80741.29" switch \initial - attribute \src "libresoc.v:80237.9-80237.17" + attribute \src "libresoc.v:80741.9-80741.17" case 1'1 case end @@ -129116,14 +130417,14 @@ module \dec30 sync always update \dec30_br $0\dec30_br[0:0] end - attribute \src "libresoc.v:80273.3-80309.6" - process $proc$libresoc.v:80273$3752 + attribute \src "libresoc.v:80777.3-80813.6" + process $proc$libresoc.v:80777$3806 assign { } { } assign { } { } assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80274.5-80274.29" + attribute \src "libresoc.v:80778.5-80778.29" switch \initial - attribute \src "libresoc.v:80274.9-80274.17" + attribute \src "libresoc.v:80778.9-80778.17" case 1'1 case end @@ -129175,14 +130476,14 @@ module \dec30 sync always update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "libresoc.v:80310.3-80346.6" - process $proc$libresoc.v:80310$3753 + attribute \src "libresoc.v:80814.3-80850.6" + process $proc$libresoc.v:80814$3807 assign { } { } assign { } { } assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:80311.5-80311.29" + attribute \src "libresoc.v:80815.5-80815.29" switch \initial - attribute \src "libresoc.v:80311.9-80311.17" + attribute \src "libresoc.v:80815.9-80815.17" case 1'1 case end @@ -129234,14 +130535,14 @@ module \dec30 sync always update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "libresoc.v:80347.3-80383.6" - process $proc$libresoc.v:80347$3754 + attribute \src "libresoc.v:80851.3-80887.6" + process $proc$libresoc.v:80851$3808 assign { } { } assign { } { } assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:80348.5-80348.29" + attribute \src "libresoc.v:80852.5-80852.29" switch \initial - attribute \src "libresoc.v:80348.9-80348.17" + attribute \src "libresoc.v:80852.9-80852.17" case 1'1 case end @@ -129293,14 +130594,14 @@ module \dec30 sync always update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "libresoc.v:80384.3-80420.6" - process $proc$libresoc.v:80384$3755 + attribute \src "libresoc.v:80888.3-80924.6" + process $proc$libresoc.v:80888$3809 assign { } { } assign { } { } assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:80385.5-80385.29" + attribute \src "libresoc.v:80889.5-80889.29" switch \initial - attribute \src "libresoc.v:80385.9-80385.17" + attribute \src "libresoc.v:80889.9-80889.17" case 1'1 case end @@ -129352,14 +130653,14 @@ module \dec30 sync always update \dec30_form $0\dec30_form[4:0] end - attribute \src "libresoc.v:80421.3-80457.6" - process $proc$libresoc.v:80421$3756 + attribute \src "libresoc.v:80925.3-80961.6" + process $proc$libresoc.v:80925$3810 assign { } { } assign { } { } assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:80422.5-80422.29" + attribute \src "libresoc.v:80926.5-80926.29" switch \initial - attribute \src "libresoc.v:80422.9-80422.17" + attribute \src "libresoc.v:80926.9-80926.17" case 1'1 case end @@ -129411,14 +130712,14 @@ module \dec30 sync always update \dec30_sgn $0\dec30_sgn[0:0] end - attribute \src "libresoc.v:80458.3-80494.6" - process $proc$libresoc.v:80458$3757 + attribute \src "libresoc.v:80962.3-80998.6" + process $proc$libresoc.v:80962$3811 assign { } { } assign { } { } assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:80459.5-80459.29" + attribute \src "libresoc.v:80963.5-80963.29" switch \initial - attribute \src "libresoc.v:80459.9-80459.17" + attribute \src "libresoc.v:80963.9-80963.17" case 1'1 case end @@ -129470,14 +130771,14 @@ module \dec30 sync always update \dec30_lk $0\dec30_lk[0:0] end - attribute \src "libresoc.v:80495.3-80531.6" - process $proc$libresoc.v:80495$3758 + attribute \src "libresoc.v:80999.3-81035.6" + process $proc$libresoc.v:80999$3812 assign { } { } assign { } { } assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:80496.5-80496.29" + attribute \src "libresoc.v:81000.5-81000.29" switch \initial - attribute \src "libresoc.v:80496.9-80496.17" + attribute \src "libresoc.v:81000.9-81000.17" case 1'1 case end @@ -129529,14 +130830,14 @@ module \dec30 sync always update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end - attribute \src "libresoc.v:80532.3-80568.6" - process $proc$libresoc.v:80532$3759 + attribute \src "libresoc.v:81036.3-81072.6" + process $proc$libresoc.v:81036$3813 assign { } { } assign { } { } assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:80533.5-80533.29" + attribute \src "libresoc.v:81037.5-81037.29" switch \initial - attribute \src "libresoc.v:80533.9-80533.17" + attribute \src "libresoc.v:81037.9-81037.17" case 1'1 case end @@ -129588,14 +130889,14 @@ module \dec30 sync always update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] end - attribute \src "libresoc.v:80569.3-80605.6" - process $proc$libresoc.v:80569$3760 + attribute \src "libresoc.v:81073.3-81109.6" + process $proc$libresoc.v:81073$3814 assign { } { } assign { } { } assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:80570.5-80570.29" + attribute \src "libresoc.v:81074.5-81074.29" switch \initial - attribute \src "libresoc.v:80570.9-80570.17" + attribute \src "libresoc.v:81074.9-81074.17" case 1'1 case end @@ -129647,14 +130948,14 @@ module \dec30 sync always update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] end - attribute \src "libresoc.v:80606.3-80642.6" - process $proc$libresoc.v:80606$3761 + attribute \src "libresoc.v:81110.3-81146.6" + process $proc$libresoc.v:81110$3815 assign { } { } assign { } { } assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:80607.5-80607.29" + attribute \src "libresoc.v:81111.5-81111.29" switch \initial - attribute \src "libresoc.v:80607.9-80607.17" + attribute \src "libresoc.v:81111.9-81111.17" case 1'1 case end @@ -129706,14 +131007,14 @@ module \dec30 sync always update \dec30_in1_sel $0\dec30_in1_sel[2:0] end - attribute \src "libresoc.v:80643.3-80679.6" - process $proc$libresoc.v:80643$3762 + attribute \src "libresoc.v:81147.3-81183.6" + process $proc$libresoc.v:81147$3816 assign { } { } assign { } { } assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:80644.5-80644.29" + attribute \src "libresoc.v:81148.5-81148.29" switch \initial - attribute \src "libresoc.v:80644.9-80644.17" + attribute \src "libresoc.v:81148.9-81148.17" case 1'1 case end @@ -129765,14 +131066,14 @@ module \dec30 sync always update \dec30_in2_sel $0\dec30_in2_sel[3:0] end - attribute \src "libresoc.v:80680.3-80716.6" - process $proc$libresoc.v:80680$3763 + attribute \src "libresoc.v:81184.3-81220.6" + process $proc$libresoc.v:81184$3817 assign { } { } assign { } { } assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:80681.5-80681.29" + attribute \src "libresoc.v:81185.5-81185.29" switch \initial - attribute \src "libresoc.v:80681.9-80681.17" + attribute \src "libresoc.v:81185.9-81185.17" case 1'1 case end @@ -129824,14 +131125,14 @@ module \dec30 sync always update \dec30_in3_sel $0\dec30_in3_sel[1:0] end - attribute \src "libresoc.v:80717.3-80753.6" - process $proc$libresoc.v:80717$3764 + attribute \src "libresoc.v:81221.3-81257.6" + process $proc$libresoc.v:81221$3818 assign { } { } assign { } { } assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:80718.5-80718.29" + attribute \src "libresoc.v:81222.5-81222.29" switch \initial - attribute \src "libresoc.v:80718.9-80718.17" + attribute \src "libresoc.v:81222.9-81222.17" case 1'1 case end @@ -129885,140 +131186,140 @@ module \dec30 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:80759.1-89080.10" +attribute \src "libresoc.v:81263.1-89603.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator "nMigen" module \dec31 - attribute \src "libresoc.v:87352.3-87412.6" + attribute \src "libresoc.v:87875.3-87935.6" wire width 2 $0\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:87413.3-87473.6" + attribute \src "libresoc.v:87936.3-87996.6" wire width 2 $0\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:87291.3-87351.6" + attribute \src "libresoc.v:87814.3-87874.6" wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:88633.3-88693.6" + attribute \src "libresoc.v:89156.3-89216.6" wire $0\dec31_br[0:0] - attribute \src "libresoc.v:87718.3-87778.6" + attribute \src "libresoc.v:88241.3-88301.6" wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:87779.3-87839.6" + attribute \src "libresoc.v:88302.3-88362.6" wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:88389.3-88449.6" + attribute \src "libresoc.v:88912.3-88972.6" wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:88572.3-88632.6" + attribute \src "libresoc.v:89095.3-89155.6" wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:87230.3-87290.6" + attribute \src "libresoc.v:87753.3-87813.6" wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:87108.3-87168.6" + attribute \src "libresoc.v:87631.3-87691.6" wire width 13 $0\dec31_function_unit[12:0] - attribute \src "libresoc.v:87474.3-87534.6" + attribute \src "libresoc.v:87997.3-88057.6" wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:87535.3-87595.6" + attribute \src "libresoc.v:88058.3-88118.6" wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:87596.3-87656.6" + attribute \src "libresoc.v:88119.3-88179.6" wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:87169.3-87229.6" + attribute \src "libresoc.v:87692.3-87752.6" wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:88450.3-88510.6" + attribute \src "libresoc.v:88973.3-89033.6" wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:88511.3-88571.6" + attribute \src "libresoc.v:89034.3-89094.6" wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:88816.3-88876.6" + attribute \src "libresoc.v:89339.3-89399.6" wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:88206.3-88266.6" + attribute \src "libresoc.v:88729.3-88789.6" wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:88938.3-88998.6" + attribute \src "libresoc.v:89461.3-89521.6" wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:87657.3-87717.6" + attribute \src "libresoc.v:88180.3-88240.6" wire width 2 $0\dec31_out_sel[1:0] - attribute \src "libresoc.v:88328.3-88388.6" + attribute \src "libresoc.v:88851.3-88911.6" wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:88755.3-88815.6" + attribute \src "libresoc.v:89278.3-89338.6" wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:88999.3-89059.6" + attribute \src "libresoc.v:89522.3-89582.6" wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:88877.3-88937.6" + attribute \src "libresoc.v:89400.3-89460.6" wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:88694.3-88754.6" + attribute \src "libresoc.v:89217.3-89277.6" wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:88084.3-88144.6" + attribute \src "libresoc.v:88607.3-88667.6" wire width 3 $0\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:88145.3-88205.6" + attribute \src "libresoc.v:88668.3-88728.6" wire width 3 $0\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:87840.3-87900.6" + attribute \src "libresoc.v:88363.3-88423.6" wire width 3 $0\dec31_sv_in1[2:0] - attribute \src "libresoc.v:87901.3-87961.6" + attribute \src "libresoc.v:88424.3-88484.6" wire width 3 $0\dec31_sv_in2[2:0] - attribute \src "libresoc.v:87962.3-88022.6" + attribute \src "libresoc.v:88485.3-88545.6" wire width 3 $0\dec31_sv_in3[2:0] - attribute \src "libresoc.v:88023.3-88083.6" + attribute \src "libresoc.v:88546.3-88606.6" wire width 3 $0\dec31_sv_out[2:0] - attribute \src "libresoc.v:88267.3-88327.6" + attribute \src "libresoc.v:88790.3-88850.6" wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:80760.7-80760.20" + attribute \src "libresoc.v:81264.7-81264.20" wire $0\initial[0:0] - attribute \src "libresoc.v:87352.3-87412.6" + attribute \src "libresoc.v:87875.3-87935.6" wire width 2 $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:87413.3-87473.6" + attribute \src "libresoc.v:87936.3-87996.6" wire width 2 $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:87291.3-87351.6" + attribute \src "libresoc.v:87814.3-87874.6" wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:88633.3-88693.6" + attribute \src "libresoc.v:89156.3-89216.6" wire $1\dec31_br[0:0] - attribute \src "libresoc.v:87718.3-87778.6" + attribute \src "libresoc.v:88241.3-88301.6" wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:87779.3-87839.6" + attribute \src "libresoc.v:88302.3-88362.6" wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:88389.3-88449.6" + attribute \src "libresoc.v:88912.3-88972.6" wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:88572.3-88632.6" + attribute \src "libresoc.v:89095.3-89155.6" wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:87230.3-87290.6" + attribute \src "libresoc.v:87753.3-87813.6" wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:87108.3-87168.6" + attribute \src "libresoc.v:87631.3-87691.6" wire width 13 $1\dec31_function_unit[12:0] - attribute \src "libresoc.v:87474.3-87534.6" + attribute \src "libresoc.v:87997.3-88057.6" wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:87535.3-87595.6" + attribute \src "libresoc.v:88058.3-88118.6" wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:87596.3-87656.6" + attribute \src "libresoc.v:88119.3-88179.6" wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:87169.3-87229.6" + attribute \src "libresoc.v:87692.3-87752.6" wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:88450.3-88510.6" + attribute \src "libresoc.v:88973.3-89033.6" wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:88511.3-88571.6" + attribute \src "libresoc.v:89034.3-89094.6" wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:88816.3-88876.6" + attribute \src "libresoc.v:89339.3-89399.6" wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:88206.3-88266.6" + attribute \src "libresoc.v:88729.3-88789.6" wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:88938.3-88998.6" + attribute \src "libresoc.v:89461.3-89521.6" wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:87657.3-87717.6" + attribute \src "libresoc.v:88180.3-88240.6" wire width 2 $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:88328.3-88388.6" + attribute \src "libresoc.v:88851.3-88911.6" wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:88755.3-88815.6" + attribute \src "libresoc.v:89278.3-89338.6" wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:88999.3-89059.6" + attribute \src "libresoc.v:89522.3-89582.6" wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:88877.3-88937.6" + attribute \src "libresoc.v:89400.3-89460.6" wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:88694.3-88754.6" + attribute \src "libresoc.v:89217.3-89277.6" wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:88084.3-88144.6" + attribute \src "libresoc.v:88607.3-88667.6" wire width 3 $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:88145.3-88205.6" + attribute \src "libresoc.v:88668.3-88728.6" wire width 3 $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:87840.3-87900.6" + attribute \src "libresoc.v:88363.3-88423.6" wire width 3 $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:87901.3-87961.6" + attribute \src "libresoc.v:88424.3-88484.6" wire width 3 $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:87962.3-88022.6" + attribute \src "libresoc.v:88485.3-88545.6" wire width 3 $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:88023.3-88083.6" + attribute \src "libresoc.v:88546.3-88606.6" wire width 3 $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:88267.3-88327.6" + attribute \src "libresoc.v:88790.3-88850.6" wire width 2 $1\dec31_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -130138,6 +131439,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form attribute \enum_base_type "Function" @@ -130437,6 +131739,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form attribute \enum_base_type "Function" @@ -130736,6 +132039,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub11_dec31_dec_sub11_form attribute \enum_base_type "Function" @@ -131035,6 +132339,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub15_dec31_dec_sub15_form attribute \enum_base_type "Function" @@ -131334,6 +132639,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub16_dec31_dec_sub16_form attribute \enum_base_type "Function" @@ -131633,6 +132939,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub18_dec31_dec_sub18_form attribute \enum_base_type "Function" @@ -131932,6 +133239,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub19_dec31_dec_sub19_form attribute \enum_base_type "Function" @@ -132231,6 +133539,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub20_dec31_dec_sub20_form attribute \enum_base_type "Function" @@ -132530,6 +133839,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub21_dec31_dec_sub21_form attribute \enum_base_type "Function" @@ -132829,6 +134139,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub22_dec31_dec_sub22_form attribute \enum_base_type "Function" @@ -133128,6 +134439,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub23_dec31_dec_sub23_form attribute \enum_base_type "Function" @@ -133427,6 +134739,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub24_dec31_dec_sub24_form attribute \enum_base_type "Function" @@ -133726,6 +135039,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub26_dec31_dec_sub26_form attribute \enum_base_type "Function" @@ -134025,6 +135339,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub27_dec31_dec_sub27_form attribute \enum_base_type "Function" @@ -134324,6 +135639,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub28_dec31_dec_sub28_form attribute \enum_base_type "Function" @@ -134623,6 +135939,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub4_dec31_dec_sub4_form attribute \enum_base_type "Function" @@ -134922,6 +136239,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub8_dec31_dec_sub8_form attribute \enum_base_type "Function" @@ -135221,6 +136539,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 \dec31_dec_sub9_dec31_dec_sub9_form attribute \enum_base_type "Function" @@ -135476,6 +136795,7 @@ module \dec31 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_form attribute \enum_base_type "Function" @@ -135699,7 +137019,7 @@ module \dec31 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_upd - attribute \src "libresoc.v:80760.7-80760.15" + attribute \src "libresoc.v:81264.7-81264.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" wire width 5 \opc_in @@ -135708,7 +137028,7 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:86478.18-86512.4" + attribute \src "libresoc.v:87001.18-87035.4" cell \dec31_dec_sub0 \dec31_dec_sub0 connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype @@ -135745,7 +137065,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86513.19-86547.4" + attribute \src "libresoc.v:87036.19-87070.4" cell \dec31_dec_sub10 \dec31_dec_sub10 connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype @@ -135782,7 +137102,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86548.19-86582.4" + attribute \src "libresoc.v:87071.19-87105.4" cell \dec31_dec_sub11 \dec31_dec_sub11 connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype @@ -135819,7 +137139,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86583.19-86617.4" + attribute \src "libresoc.v:87106.19-87140.4" cell \dec31_dec_sub15 \dec31_dec_sub15 connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype @@ -135856,7 +137176,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86618.19-86652.4" + attribute \src "libresoc.v:87141.19-87175.4" cell \dec31_dec_sub16 \dec31_dec_sub16 connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype @@ -135893,7 +137213,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86653.19-86687.4" + attribute \src "libresoc.v:87176.19-87210.4" cell \dec31_dec_sub18 \dec31_dec_sub18 connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype @@ -135930,7 +137250,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub18_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86688.19-86722.4" + attribute \src "libresoc.v:87211.19-87245.4" cell \dec31_dec_sub19 \dec31_dec_sub19 connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype @@ -135967,7 +137287,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86723.19-86757.4" + attribute \src "libresoc.v:87246.19-87280.4" cell \dec31_dec_sub20 \dec31_dec_sub20 connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype @@ -136004,7 +137324,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86758.19-86792.4" + attribute \src "libresoc.v:87281.19-87315.4" cell \dec31_dec_sub21 \dec31_dec_sub21 connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype @@ -136041,7 +137361,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86793.19-86827.4" + attribute \src "libresoc.v:87316.19-87350.4" cell \dec31_dec_sub22 \dec31_dec_sub22 connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype @@ -136078,7 +137398,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86828.19-86862.4" + attribute \src "libresoc.v:87351.19-87385.4" cell \dec31_dec_sub23 \dec31_dec_sub23 connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype @@ -136115,7 +137435,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub23_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86863.19-86897.4" + attribute \src "libresoc.v:87386.19-87420.4" cell \dec31_dec_sub24 \dec31_dec_sub24 connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype @@ -136152,7 +137472,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86898.19-86932.4" + attribute \src "libresoc.v:87421.19-87455.4" cell \dec31_dec_sub26 \dec31_dec_sub26 connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype @@ -136189,7 +137509,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86933.19-86967.4" + attribute \src "libresoc.v:87456.19-87490.4" cell \dec31_dec_sub27 \dec31_dec_sub27 connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype @@ -136226,7 +137546,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub27_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:86968.19-87002.4" + attribute \src "libresoc.v:87491.19-87525.4" cell \dec31_dec_sub28 \dec31_dec_sub28 connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype @@ -136263,7 +137583,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub28_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87003.18-87037.4" + attribute \src "libresoc.v:87526.18-87560.4" cell \dec31_dec_sub4 \dec31_dec_sub4 connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype @@ -136300,7 +137620,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub4_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87038.18-87072.4" + attribute \src "libresoc.v:87561.18-87595.4" cell \dec31_dec_sub8 \dec31_dec_sub8 connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype @@ -136337,7 +137657,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub8_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87073.18-87107.4" + attribute \src "libresoc.v:87596.18-87630.4" cell \dec31_dec_sub9 \dec31_dec_sub9 connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype @@ -136373,22 +137693,22 @@ module \dec31 connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd connect \opcode_in \dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:80760.7-80760.20" - process $proc$libresoc.v:80760$3798 + attribute \src "libresoc.v:81264.7-81264.20" + process $proc$libresoc.v:81264$3852 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:87108.3-87168.6" - process $proc$libresoc.v:87108$3766 + attribute \src "libresoc.v:87631.3-87691.6" + process $proc$libresoc.v:87631$3820 assign { } { } assign { } { } assign $0\dec31_function_unit[12:0] $1\dec31_function_unit[12:0] - attribute \src "libresoc.v:87109.5-87109.29" + attribute \src "libresoc.v:87632.5-87632.29" switch \initial - attribute \src "libresoc.v:87109.9-87109.17" + attribute \src "libresoc.v:87632.9-87632.17" case 1'1 case end @@ -136472,14 +137792,14 @@ module \dec31 sync always update \dec31_function_unit $0\dec31_function_unit[12:0] end - attribute \src "libresoc.v:87169.3-87229.6" - process $proc$libresoc.v:87169$3767 + attribute \src "libresoc.v:87692.3-87752.6" + process $proc$libresoc.v:87692$3821 assign { } { } assign { } { } assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:87170.5-87170.29" + attribute \src "libresoc.v:87693.5-87693.29" switch \initial - attribute \src "libresoc.v:87170.9-87170.17" + attribute \src "libresoc.v:87693.9-87693.17" case 1'1 case end @@ -136563,14 +137883,14 @@ module \dec31 sync always update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "libresoc.v:87230.3-87290.6" - process $proc$libresoc.v:87230$3768 + attribute \src "libresoc.v:87753.3-87813.6" + process $proc$libresoc.v:87753$3822 assign { } { } assign { } { } assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:87231.5-87231.29" + attribute \src "libresoc.v:87754.5-87754.29" switch \initial - attribute \src "libresoc.v:87231.9-87231.17" + attribute \src "libresoc.v:87754.9-87754.17" case 1'1 case end @@ -136654,14 +137974,14 @@ module \dec31 sync always update \dec31_form $0\dec31_form[4:0] end - attribute \src "libresoc.v:87291.3-87351.6" - process $proc$libresoc.v:87291$3769 + attribute \src "libresoc.v:87814.3-87874.6" + process $proc$libresoc.v:87814$3823 assign { } { } assign { } { } assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:87292.5-87292.29" + attribute \src "libresoc.v:87815.5-87815.29" switch \initial - attribute \src "libresoc.v:87292.9-87292.17" + attribute \src "libresoc.v:87815.9-87815.17" case 1'1 case end @@ -136745,14 +138065,14 @@ module \dec31 sync always update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "libresoc.v:87352.3-87412.6" - process $proc$libresoc.v:87352$3770 + attribute \src "libresoc.v:87875.3-87935.6" + process $proc$libresoc.v:87875$3824 assign { } { } assign { } { } assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:87353.5-87353.29" + attribute \src "libresoc.v:87876.5-87876.29" switch \initial - attribute \src "libresoc.v:87353.9-87353.17" + attribute \src "libresoc.v:87876.9-87876.17" case 1'1 case end @@ -136836,14 +138156,14 @@ module \dec31 sync always update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] end - attribute \src "libresoc.v:87413.3-87473.6" - process $proc$libresoc.v:87413$3771 + attribute \src "libresoc.v:87936.3-87996.6" + process $proc$libresoc.v:87936$3825 assign { } { } assign { } { } assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:87414.5-87414.29" + attribute \src "libresoc.v:87937.5-87937.29" switch \initial - attribute \src "libresoc.v:87414.9-87414.17" + attribute \src "libresoc.v:87937.9-87937.17" case 1'1 case end @@ -136927,14 +138247,14 @@ module \dec31 sync always update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] end - attribute \src "libresoc.v:87474.3-87534.6" - process $proc$libresoc.v:87474$3772 + attribute \src "libresoc.v:87997.3-88057.6" + process $proc$libresoc.v:87997$3826 assign { } { } assign { } { } assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:87475.5-87475.29" + attribute \src "libresoc.v:87998.5-87998.29" switch \initial - attribute \src "libresoc.v:87475.9-87475.17" + attribute \src "libresoc.v:87998.9-87998.17" case 1'1 case end @@ -137018,14 +138338,14 @@ module \dec31 sync always update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "libresoc.v:87535.3-87595.6" - process $proc$libresoc.v:87535$3773 + attribute \src "libresoc.v:88058.3-88118.6" + process $proc$libresoc.v:88058$3827 assign { } { } assign { } { } assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:87536.5-87536.29" + attribute \src "libresoc.v:88059.5-88059.29" switch \initial - attribute \src "libresoc.v:87536.9-87536.17" + attribute \src "libresoc.v:88059.9-88059.17" case 1'1 case end @@ -137109,14 +138429,14 @@ module \dec31 sync always update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "libresoc.v:87596.3-87656.6" - process $proc$libresoc.v:87596$3774 + attribute \src "libresoc.v:88119.3-88179.6" + process $proc$libresoc.v:88119$3828 assign { } { } assign { } { } assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:87597.5-87597.29" + attribute \src "libresoc.v:88120.5-88120.29" switch \initial - attribute \src "libresoc.v:87597.9-87597.17" + attribute \src "libresoc.v:88120.9-88120.17" case 1'1 case end @@ -137200,14 +138520,14 @@ module \dec31 sync always update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "libresoc.v:87657.3-87717.6" - process $proc$libresoc.v:87657$3775 + attribute \src "libresoc.v:88180.3-88240.6" + process $proc$libresoc.v:88180$3829 assign { } { } assign { } { } assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:87658.5-87658.29" + attribute \src "libresoc.v:88181.5-88181.29" switch \initial - attribute \src "libresoc.v:87658.9-87658.17" + attribute \src "libresoc.v:88181.9-88181.17" case 1'1 case end @@ -137291,14 +138611,14 @@ module \dec31 sync always update \dec31_out_sel $0\dec31_out_sel[1:0] end - attribute \src "libresoc.v:87718.3-87778.6" - process $proc$libresoc.v:87718$3776 + attribute \src "libresoc.v:88241.3-88301.6" + process $proc$libresoc.v:88241$3830 assign { } { } assign { } { } assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:87719.5-87719.29" + attribute \src "libresoc.v:88242.5-88242.29" switch \initial - attribute \src "libresoc.v:87719.9-87719.17" + attribute \src "libresoc.v:88242.9-88242.17" case 1'1 case end @@ -137382,14 +138702,14 @@ module \dec31 sync always update \dec31_cr_in $0\dec31_cr_in[2:0] end - attribute \src "libresoc.v:87779.3-87839.6" - process $proc$libresoc.v:87779$3777 + attribute \src "libresoc.v:88302.3-88362.6" + process $proc$libresoc.v:88302$3831 assign { } { } assign { } { } assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:87780.5-87780.29" + attribute \src "libresoc.v:88303.5-88303.29" switch \initial - attribute \src "libresoc.v:87780.9-87780.17" + attribute \src "libresoc.v:88303.9-88303.17" case 1'1 case end @@ -137473,14 +138793,14 @@ module \dec31 sync always update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "libresoc.v:87840.3-87900.6" - process $proc$libresoc.v:87840$3778 + attribute \src "libresoc.v:88363.3-88423.6" + process $proc$libresoc.v:88363$3832 assign { } { } assign { } { } assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:87841.5-87841.29" + attribute \src "libresoc.v:88364.5-88364.29" switch \initial - attribute \src "libresoc.v:87841.9-87841.17" + attribute \src "libresoc.v:88364.9-88364.17" case 1'1 case end @@ -137564,14 +138884,14 @@ module \dec31 sync always update \dec31_sv_in1 $0\dec31_sv_in1[2:0] end - attribute \src "libresoc.v:87901.3-87961.6" - process $proc$libresoc.v:87901$3779 + attribute \src "libresoc.v:88424.3-88484.6" + process $proc$libresoc.v:88424$3833 assign { } { } assign { } { } assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:87902.5-87902.29" + attribute \src "libresoc.v:88425.5-88425.29" switch \initial - attribute \src "libresoc.v:87902.9-87902.17" + attribute \src "libresoc.v:88425.9-88425.17" case 1'1 case end @@ -137655,14 +138975,14 @@ module \dec31 sync always update \dec31_sv_in2 $0\dec31_sv_in2[2:0] end - attribute \src "libresoc.v:87962.3-88022.6" - process $proc$libresoc.v:87962$3780 + attribute \src "libresoc.v:88485.3-88545.6" + process $proc$libresoc.v:88485$3834 assign { } { } assign { } { } assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:87963.5-87963.29" + attribute \src "libresoc.v:88486.5-88486.29" switch \initial - attribute \src "libresoc.v:87963.9-87963.17" + attribute \src "libresoc.v:88486.9-88486.17" case 1'1 case end @@ -137746,14 +139066,14 @@ module \dec31 sync always update \dec31_sv_in3 $0\dec31_sv_in3[2:0] end - attribute \src "libresoc.v:88023.3-88083.6" - process $proc$libresoc.v:88023$3781 + attribute \src "libresoc.v:88546.3-88606.6" + process $proc$libresoc.v:88546$3835 assign { } { } assign { } { } assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:88024.5-88024.29" + attribute \src "libresoc.v:88547.5-88547.29" switch \initial - attribute \src "libresoc.v:88024.9-88024.17" + attribute \src "libresoc.v:88547.9-88547.17" case 1'1 case end @@ -137837,14 +139157,14 @@ module \dec31 sync always update \dec31_sv_out $0\dec31_sv_out[2:0] end - attribute \src "libresoc.v:88084.3-88144.6" - process $proc$libresoc.v:88084$3782 + attribute \src "libresoc.v:88607.3-88667.6" + process $proc$libresoc.v:88607$3836 assign { } { } assign { } { } assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:88085.5-88085.29" + attribute \src "libresoc.v:88608.5-88608.29" switch \initial - attribute \src "libresoc.v:88085.9-88085.17" + attribute \src "libresoc.v:88608.9-88608.17" case 1'1 case end @@ -137928,14 +139248,14 @@ module \dec31 sync always update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] end - attribute \src "libresoc.v:88145.3-88205.6" - process $proc$libresoc.v:88145$3783 + attribute \src "libresoc.v:88668.3-88728.6" + process $proc$libresoc.v:88668$3837 assign { } { } assign { } { } assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:88146.5-88146.29" + attribute \src "libresoc.v:88669.5-88669.29" switch \initial - attribute \src "libresoc.v:88146.9-88146.17" + attribute \src "libresoc.v:88669.9-88669.17" case 1'1 case end @@ -138019,14 +139339,14 @@ module \dec31 sync always update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] end - attribute \src "libresoc.v:88206.3-88266.6" - process $proc$libresoc.v:88206$3784 + attribute \src "libresoc.v:88729.3-88789.6" + process $proc$libresoc.v:88729$3838 assign { } { } assign { } { } assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:88207.5-88207.29" + attribute \src "libresoc.v:88730.5-88730.29" switch \initial - attribute \src "libresoc.v:88207.9-88207.17" + attribute \src "libresoc.v:88730.9-88730.17" case 1'1 case end @@ -138110,14 +139430,14 @@ module \dec31 sync always update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "libresoc.v:88267.3-88327.6" - process $proc$libresoc.v:88267$3785 + attribute \src "libresoc.v:88790.3-88850.6" + process $proc$libresoc.v:88790$3839 assign { } { } assign { } { } assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:88268.5-88268.29" + attribute \src "libresoc.v:88791.5-88791.29" switch \initial - attribute \src "libresoc.v:88268.9-88268.17" + attribute \src "libresoc.v:88791.9-88791.17" case 1'1 case end @@ -138201,14 +139521,14 @@ module \dec31 sync always update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "libresoc.v:88328.3-88388.6" - process $proc$libresoc.v:88328$3786 + attribute \src "libresoc.v:88851.3-88911.6" + process $proc$libresoc.v:88851$3840 assign { } { } assign { } { } assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:88329.5-88329.29" + attribute \src "libresoc.v:88852.5-88852.29" switch \initial - attribute \src "libresoc.v:88329.9-88329.17" + attribute \src "libresoc.v:88852.9-88852.17" case 1'1 case end @@ -138292,14 +139612,14 @@ module \dec31 sync always update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "libresoc.v:88389.3-88449.6" - process $proc$libresoc.v:88389$3787 + attribute \src "libresoc.v:88912.3-88972.6" + process $proc$libresoc.v:88912$3841 assign { } { } assign { } { } assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:88390.5-88390.29" + attribute \src "libresoc.v:88913.5-88913.29" switch \initial - attribute \src "libresoc.v:88390.9-88390.17" + attribute \src "libresoc.v:88913.9-88913.17" case 1'1 case end @@ -138383,14 +139703,14 @@ module \dec31 sync always update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "libresoc.v:88450.3-88510.6" - process $proc$libresoc.v:88450$3788 + attribute \src "libresoc.v:88973.3-89033.6" + process $proc$libresoc.v:88973$3842 assign { } { } assign { } { } assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:88451.5-88451.29" + attribute \src "libresoc.v:88974.5-88974.29" switch \initial - attribute \src "libresoc.v:88451.9-88451.17" + attribute \src "libresoc.v:88974.9-88974.17" case 1'1 case end @@ -138474,14 +139794,14 @@ module \dec31 sync always update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "libresoc.v:88511.3-88571.6" - process $proc$libresoc.v:88511$3789 + attribute \src "libresoc.v:89034.3-89094.6" + process $proc$libresoc.v:89034$3843 assign { } { } assign { } { } assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:88512.5-88512.29" + attribute \src "libresoc.v:89035.5-89035.29" switch \initial - attribute \src "libresoc.v:88512.9-88512.17" + attribute \src "libresoc.v:89035.9-89035.17" case 1'1 case end @@ -138565,14 +139885,14 @@ module \dec31 sync always update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "libresoc.v:88572.3-88632.6" - process $proc$libresoc.v:88572$3790 + attribute \src "libresoc.v:89095.3-89155.6" + process $proc$libresoc.v:89095$3844 assign { } { } assign { } { } assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:88573.5-88573.29" + attribute \src "libresoc.v:89096.5-89096.29" switch \initial - attribute \src "libresoc.v:88573.9-88573.17" + attribute \src "libresoc.v:89096.9-89096.17" case 1'1 case end @@ -138656,14 +139976,14 @@ module \dec31 sync always update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "libresoc.v:88633.3-88693.6" - process $proc$libresoc.v:88633$3791 + attribute \src "libresoc.v:89156.3-89216.6" + process $proc$libresoc.v:89156$3845 assign { } { } assign { } { } assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:88634.5-88634.29" + attribute \src "libresoc.v:89157.5-89157.29" switch \initial - attribute \src "libresoc.v:88634.9-88634.17" + attribute \src "libresoc.v:89157.9-89157.17" case 1'1 case end @@ -138747,14 +140067,14 @@ module \dec31 sync always update \dec31_br $0\dec31_br[0:0] end - attribute \src "libresoc.v:88694.3-88754.6" - process $proc$libresoc.v:88694$3792 + attribute \src "libresoc.v:89217.3-89277.6" + process $proc$libresoc.v:89217$3846 assign { } { } assign { } { } assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:88695.5-88695.29" + attribute \src "libresoc.v:89218.5-89218.29" switch \initial - attribute \src "libresoc.v:88695.9-88695.17" + attribute \src "libresoc.v:89218.9-89218.17" case 1'1 case end @@ -138838,14 +140158,14 @@ module \dec31 sync always update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:88755.3-88815.6" - process $proc$libresoc.v:88755$3793 + attribute \src "libresoc.v:89278.3-89338.6" + process $proc$libresoc.v:89278$3847 assign { } { } assign { } { } assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:88756.5-88756.29" + attribute \src "libresoc.v:89279.5-89279.29" switch \initial - attribute \src "libresoc.v:88756.9-88756.17" + attribute \src "libresoc.v:89279.9-89279.17" case 1'1 case end @@ -138929,14 +140249,14 @@ module \dec31 sync always update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "libresoc.v:88816.3-88876.6" - process $proc$libresoc.v:88816$3794 + attribute \src "libresoc.v:89339.3-89399.6" + process $proc$libresoc.v:89339$3848 assign { } { } assign { } { } assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:88817.5-88817.29" + attribute \src "libresoc.v:89340.5-89340.29" switch \initial - attribute \src "libresoc.v:88817.9-88817.17" + attribute \src "libresoc.v:89340.9-89340.17" case 1'1 case end @@ -139020,14 +140340,14 @@ module \dec31 sync always update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "libresoc.v:88877.3-88937.6" - process $proc$libresoc.v:88877$3795 + attribute \src "libresoc.v:89400.3-89460.6" + process $proc$libresoc.v:89400$3849 assign { } { } assign { } { } assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:88878.5-88878.29" + attribute \src "libresoc.v:89401.5-89401.29" switch \initial - attribute \src "libresoc.v:88878.9-88878.17" + attribute \src "libresoc.v:89401.9-89401.17" case 1'1 case end @@ -139111,14 +140431,14 @@ module \dec31 sync always update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "libresoc.v:88938.3-88998.6" - process $proc$libresoc.v:88938$3796 + attribute \src "libresoc.v:89461.3-89521.6" + process $proc$libresoc.v:89461$3850 assign { } { } assign { } { } assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:88939.5-88939.29" + attribute \src "libresoc.v:89462.5-89462.29" switch \initial - attribute \src "libresoc.v:88939.9-88939.17" + attribute \src "libresoc.v:89462.9-89462.17" case 1'1 case end @@ -139202,14 +140522,14 @@ module \dec31 sync always update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "libresoc.v:88999.3-89059.6" - process $proc$libresoc.v:88999$3797 + attribute \src "libresoc.v:89522.3-89582.6" + process $proc$libresoc.v:89522$3851 assign { } { } assign { } { } assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:89000.5-89000.29" + attribute \src "libresoc.v:89523.5-89523.29" switch \initial - attribute \src "libresoc.v:89000.9-89000.17" + attribute \src "libresoc.v:89523.9-89523.17" case 1'1 case end @@ -139314,140 +140634,140 @@ module \dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:89084.1-90028.10" +attribute \src "libresoc.v:89607.1-90552.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" module \dec31_dec_sub0 - attribute \src "libresoc.v:89913.3-89931.6" + attribute \src "libresoc.v:90437.3-90455.6" wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:89932.3-89950.6" + attribute \src "libresoc.v:90456.3-90474.6" wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:89685.3-89703.6" + attribute \src "libresoc.v:90209.3-90227.6" wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:89761.3-89779.6" + attribute \src "libresoc.v:90285.3-90303.6" wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:89438.3-89456.6" + attribute \src "libresoc.v:89962.3-89980.6" wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:89457.3-89475.6" + attribute \src "libresoc.v:89981.3-89999.6" wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:89666.3-89684.6" + attribute \src "libresoc.v:90190.3-90208.6" wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:89742.3-89760.6" + attribute \src "libresoc.v:90266.3-90284.6" wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:89837.3-89855.6" + attribute \src "libresoc.v:90361.3-90379.6" wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:89419.3-89437.6" + attribute \src "libresoc.v:89943.3-89961.6" wire width 13 $0\dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:89951.3-89969.6" + attribute \src "libresoc.v:90475.3-90493.6" wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:89970.3-89988.6" + attribute \src "libresoc.v:90494.3-90512.6" wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:89989.3-90007.6" + attribute \src "libresoc.v:90513.3-90531.6" wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:89628.3-89646.6" + attribute \src "libresoc.v:90152.3-90170.6" wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:89704.3-89722.6" + attribute \src "libresoc.v:90228.3-90246.6" wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:89723.3-89741.6" + attribute \src "libresoc.v:90247.3-90265.6" wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:89818.3-89836.6" + attribute \src "libresoc.v:90342.3-90360.6" wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:89590.3-89608.6" + attribute \src "libresoc.v:90114.3-90132.6" wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:89875.3-89893.6" + attribute \src "libresoc.v:90399.3-90417.6" wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:90008.3-90026.6" + attribute \src "libresoc.v:90532.3-90550.6" wire width 2 $0\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:89647.3-89665.6" + attribute \src "libresoc.v:90171.3-90189.6" wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:89799.3-89817.6" + attribute \src "libresoc.v:90323.3-90341.6" wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:89894.3-89912.6" + attribute \src "libresoc.v:90418.3-90436.6" wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:89856.3-89874.6" + attribute \src "libresoc.v:90380.3-90398.6" wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:89780.3-89798.6" + attribute \src "libresoc.v:90304.3-90322.6" wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:89552.3-89570.6" + attribute \src "libresoc.v:90076.3-90094.6" wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:89571.3-89589.6" + attribute \src "libresoc.v:90095.3-90113.6" wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:89476.3-89494.6" + attribute \src "libresoc.v:90000.3-90018.6" wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:89495.3-89513.6" + attribute \src "libresoc.v:90019.3-90037.6" wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:89514.3-89532.6" + attribute \src "libresoc.v:90038.3-90056.6" wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:89533.3-89551.6" + attribute \src "libresoc.v:90057.3-90075.6" wire width 3 $0\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:89609.3-89627.6" + attribute \src "libresoc.v:90133.3-90151.6" wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:89085.7-89085.20" + attribute \src "libresoc.v:89608.7-89608.20" wire $0\initial[0:0] - attribute \src "libresoc.v:89913.3-89931.6" + attribute \src "libresoc.v:90437.3-90455.6" wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:89932.3-89950.6" + attribute \src "libresoc.v:90456.3-90474.6" wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:89685.3-89703.6" + attribute \src "libresoc.v:90209.3-90227.6" wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:89761.3-89779.6" + attribute \src "libresoc.v:90285.3-90303.6" wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:89438.3-89456.6" + attribute \src "libresoc.v:89962.3-89980.6" wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:89457.3-89475.6" + attribute \src "libresoc.v:89981.3-89999.6" wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:89666.3-89684.6" + attribute \src "libresoc.v:90190.3-90208.6" wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:89742.3-89760.6" + attribute \src "libresoc.v:90266.3-90284.6" wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:89837.3-89855.6" + attribute \src "libresoc.v:90361.3-90379.6" wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:89419.3-89437.6" + attribute \src "libresoc.v:89943.3-89961.6" wire width 13 $1\dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:89951.3-89969.6" + attribute \src "libresoc.v:90475.3-90493.6" wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:89970.3-89988.6" + attribute \src "libresoc.v:90494.3-90512.6" wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:89989.3-90007.6" + attribute \src "libresoc.v:90513.3-90531.6" wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:89628.3-89646.6" + attribute \src "libresoc.v:90152.3-90170.6" wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:89704.3-89722.6" + attribute \src "libresoc.v:90228.3-90246.6" wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:89723.3-89741.6" + attribute \src "libresoc.v:90247.3-90265.6" wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:89818.3-89836.6" + attribute \src "libresoc.v:90342.3-90360.6" wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:89590.3-89608.6" + attribute \src "libresoc.v:90114.3-90132.6" wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:89875.3-89893.6" + attribute \src "libresoc.v:90399.3-90417.6" wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:90008.3-90026.6" + attribute \src "libresoc.v:90532.3-90550.6" wire width 2 $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:89647.3-89665.6" + attribute \src "libresoc.v:90171.3-90189.6" wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:89799.3-89817.6" + attribute \src "libresoc.v:90323.3-90341.6" wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:89894.3-89912.6" + attribute \src "libresoc.v:90418.3-90436.6" wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:89856.3-89874.6" + attribute \src "libresoc.v:90380.3-90398.6" wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:89780.3-89798.6" + attribute \src "libresoc.v:90304.3-90322.6" wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:89552.3-89570.6" + attribute \src "libresoc.v:90076.3-90094.6" wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:89571.3-89589.6" + attribute \src "libresoc.v:90095.3-90113.6" wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:89476.3-89494.6" + attribute \src "libresoc.v:90000.3-90018.6" wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:89495.3-89513.6" + attribute \src "libresoc.v:90019.3-90037.6" wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:89514.3-89532.6" + attribute \src "libresoc.v:90038.3-90056.6" wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:89533.3-89551.6" + attribute \src "libresoc.v:90057.3-90075.6" wire width 3 $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:89609.3-89627.6" + attribute \src "libresoc.v:90133.3-90151.6" wire width 2 $1\dec31_dec_sub0_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -139523,6 +140843,7 @@ module \dec31_dec_sub0 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub0_form attribute \enum_base_type "Function" @@ -139746,28 +141067,28 @@ module \dec31_dec_sub0 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub0_upd - attribute \src "libresoc.v:89085.7-89085.15" + attribute \src "libresoc.v:89608.7-89608.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:89085.7-89085.20" - process $proc$libresoc.v:89085$3831 + attribute \src "libresoc.v:89608.7-89608.20" + process $proc$libresoc.v:89608$3885 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:89419.3-89437.6" - process $proc$libresoc.v:89419$3799 + attribute \src "libresoc.v:89943.3-89961.6" + process $proc$libresoc.v:89943$3853 assign { } { } assign { } { } assign $0\dec31_dec_sub0_function_unit[12:0] $1\dec31_dec_sub0_function_unit[12:0] - attribute \src "libresoc.v:89420.5-89420.29" + attribute \src "libresoc.v:89944.5-89944.29" switch \initial - attribute \src "libresoc.v:89420.9-89420.17" + attribute \src "libresoc.v:89944.9-89944.17" case 1'1 case end @@ -139795,14 +141116,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[12:0] end - attribute \src "libresoc.v:89438.3-89456.6" - process $proc$libresoc.v:89438$3800 + attribute \src "libresoc.v:89962.3-89980.6" + process $proc$libresoc.v:89962$3854 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:89439.5-89439.29" + attribute \src "libresoc.v:89963.5-89963.29" switch \initial - attribute \src "libresoc.v:89439.9-89439.17" + attribute \src "libresoc.v:89963.9-89963.17" case 1'1 case end @@ -139830,14 +141151,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:89457.3-89475.6" - process $proc$libresoc.v:89457$3801 + attribute \src "libresoc.v:89981.3-89999.6" + process $proc$libresoc.v:89981$3855 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:89458.5-89458.29" + attribute \src "libresoc.v:89982.5-89982.29" switch \initial - attribute \src "libresoc.v:89458.9-89458.17" + attribute \src "libresoc.v:89982.9-89982.17" case 1'1 case end @@ -139865,14 +141186,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:89476.3-89494.6" - process $proc$libresoc.v:89476$3802 + attribute \src "libresoc.v:90000.3-90018.6" + process $proc$libresoc.v:90000$3856 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:89477.5-89477.29" + attribute \src "libresoc.v:90001.5-90001.29" switch \initial - attribute \src "libresoc.v:89477.9-89477.17" + attribute \src "libresoc.v:90001.9-90001.17" case 1'1 case end @@ -139900,14 +141221,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] end - attribute \src "libresoc.v:89495.3-89513.6" - process $proc$libresoc.v:89495$3803 + attribute \src "libresoc.v:90019.3-90037.6" + process $proc$libresoc.v:90019$3857 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:89496.5-89496.29" + attribute \src "libresoc.v:90020.5-90020.29" switch \initial - attribute \src "libresoc.v:89496.9-89496.17" + attribute \src "libresoc.v:90020.9-90020.17" case 1'1 case end @@ -139935,14 +141256,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] end - attribute \src "libresoc.v:89514.3-89532.6" - process $proc$libresoc.v:89514$3804 + attribute \src "libresoc.v:90038.3-90056.6" + process $proc$libresoc.v:90038$3858 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:89515.5-89515.29" + attribute \src "libresoc.v:90039.5-90039.29" switch \initial - attribute \src "libresoc.v:89515.9-89515.17" + attribute \src "libresoc.v:90039.9-90039.17" case 1'1 case end @@ -139970,14 +141291,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] end - attribute \src "libresoc.v:89533.3-89551.6" - process $proc$libresoc.v:89533$3805 + attribute \src "libresoc.v:90057.3-90075.6" + process $proc$libresoc.v:90057$3859 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:89534.5-89534.29" + attribute \src "libresoc.v:90058.5-90058.29" switch \initial - attribute \src "libresoc.v:89534.9-89534.17" + attribute \src "libresoc.v:90058.9-90058.17" case 1'1 case end @@ -140005,14 +141326,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] end - attribute \src "libresoc.v:89552.3-89570.6" - process $proc$libresoc.v:89552$3806 + attribute \src "libresoc.v:90076.3-90094.6" + process $proc$libresoc.v:90076$3860 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:89553.5-89553.29" + attribute \src "libresoc.v:90077.5-90077.29" switch \initial - attribute \src "libresoc.v:89553.9-89553.17" + attribute \src "libresoc.v:90077.9-90077.17" case 1'1 case end @@ -140040,14 +141361,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] end - attribute \src "libresoc.v:89571.3-89589.6" - process $proc$libresoc.v:89571$3807 + attribute \src "libresoc.v:90095.3-90113.6" + process $proc$libresoc.v:90095$3861 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:89572.5-89572.29" + attribute \src "libresoc.v:90096.5-90096.29" switch \initial - attribute \src "libresoc.v:89572.9-89572.17" + attribute \src "libresoc.v:90096.9-90096.17" case 1'1 case end @@ -140075,14 +141396,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] end - attribute \src "libresoc.v:89590.3-89608.6" - process $proc$libresoc.v:89590$3808 + attribute \src "libresoc.v:90114.3-90132.6" + process $proc$libresoc.v:90114$3862 assign { } { } assign { } { } assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:89591.5-89591.29" + attribute \src "libresoc.v:90115.5-90115.29" switch \initial - attribute \src "libresoc.v:89591.9-89591.17" + attribute \src "libresoc.v:90115.9-90115.17" case 1'1 case end @@ -140110,14 +141431,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:89609.3-89627.6" - process $proc$libresoc.v:89609$3809 + attribute \src "libresoc.v:90133.3-90151.6" + process $proc$libresoc.v:90133$3863 assign { } { } assign { } { } assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:89610.5-89610.29" + attribute \src "libresoc.v:90134.5-90134.29" switch \initial - attribute \src "libresoc.v:89610.9-89610.17" + attribute \src "libresoc.v:90134.9-90134.17" case 1'1 case end @@ -140145,14 +141466,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \src "libresoc.v:89628.3-89646.6" - process $proc$libresoc.v:89628$3810 + attribute \src "libresoc.v:90152.3-90170.6" + process $proc$libresoc.v:90152$3864 assign { } { } assign { } { } assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:89629.5-89629.29" + attribute \src "libresoc.v:90153.5-90153.29" switch \initial - attribute \src "libresoc.v:89629.9-89629.17" + attribute \src "libresoc.v:90153.9-90153.17" case 1'1 case end @@ -140180,14 +141501,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:89647.3-89665.6" - process $proc$libresoc.v:89647$3811 + attribute \src "libresoc.v:90171.3-90189.6" + process $proc$libresoc.v:90171$3865 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:89648.5-89648.29" + attribute \src "libresoc.v:90172.5-90172.29" switch \initial - attribute \src "libresoc.v:89648.9-89648.17" + attribute \src "libresoc.v:90172.9-90172.17" case 1'1 case end @@ -140215,14 +141536,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:89666.3-89684.6" - process $proc$libresoc.v:89666$3812 + attribute \src "libresoc.v:90190.3-90208.6" + process $proc$libresoc.v:90190$3866 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:89667.5-89667.29" + attribute \src "libresoc.v:90191.5-90191.29" switch \initial - attribute \src "libresoc.v:89667.9-89667.17" + attribute \src "libresoc.v:90191.9-90191.17" case 1'1 case end @@ -140250,14 +141571,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end - attribute \src "libresoc.v:89685.3-89703.6" - process $proc$libresoc.v:89685$3813 + attribute \src "libresoc.v:90209.3-90227.6" + process $proc$libresoc.v:90209$3867 assign { } { } assign { } { } assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:89686.5-89686.29" + attribute \src "libresoc.v:90210.5-90210.29" switch \initial - attribute \src "libresoc.v:89686.9-89686.17" + attribute \src "libresoc.v:90210.9-90210.17" case 1'1 case end @@ -140285,14 +141606,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end - attribute \src "libresoc.v:89704.3-89722.6" - process $proc$libresoc.v:89704$3814 + attribute \src "libresoc.v:90228.3-90246.6" + process $proc$libresoc.v:90228$3868 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:89705.5-89705.29" + attribute \src "libresoc.v:90229.5-90229.29" switch \initial - attribute \src "libresoc.v:89705.9-89705.17" + attribute \src "libresoc.v:90229.9-90229.17" case 1'1 case end @@ -140320,14 +141641,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:89723.3-89741.6" - process $proc$libresoc.v:89723$3815 + attribute \src "libresoc.v:90247.3-90265.6" + process $proc$libresoc.v:90247$3869 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:89724.5-89724.29" + attribute \src "libresoc.v:90248.5-90248.29" switch \initial - attribute \src "libresoc.v:89724.9-89724.17" + attribute \src "libresoc.v:90248.9-90248.17" case 1'1 case end @@ -140355,14 +141676,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:89742.3-89760.6" - process $proc$libresoc.v:89742$3816 + attribute \src "libresoc.v:90266.3-90284.6" + process $proc$libresoc.v:90266$3870 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:89743.5-89743.29" + attribute \src "libresoc.v:90267.5-90267.29" switch \initial - attribute \src "libresoc.v:89743.9-89743.17" + attribute \src "libresoc.v:90267.9-90267.17" case 1'1 case end @@ -140390,14 +141711,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:89761.3-89779.6" - process $proc$libresoc.v:89761$3817 + attribute \src "libresoc.v:90285.3-90303.6" + process $proc$libresoc.v:90285$3871 assign { } { } assign { } { } assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:89762.5-89762.29" + attribute \src "libresoc.v:90286.5-90286.29" switch \initial - attribute \src "libresoc.v:89762.9-89762.17" + attribute \src "libresoc.v:90286.9-90286.17" case 1'1 case end @@ -140425,14 +141746,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end - attribute \src "libresoc.v:89780.3-89798.6" - process $proc$libresoc.v:89780$3818 + attribute \src "libresoc.v:90304.3-90322.6" + process $proc$libresoc.v:90304$3872 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:89781.5-89781.29" + attribute \src "libresoc.v:90305.5-90305.29" switch \initial - attribute \src "libresoc.v:89781.9-89781.17" + attribute \src "libresoc.v:90305.9-90305.17" case 1'1 case end @@ -140460,14 +141781,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end - attribute \src "libresoc.v:89799.3-89817.6" - process $proc$libresoc.v:89799$3819 + attribute \src "libresoc.v:90323.3-90341.6" + process $proc$libresoc.v:90323$3873 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:89800.5-89800.29" + attribute \src "libresoc.v:90324.5-90324.29" switch \initial - attribute \src "libresoc.v:89800.9-89800.17" + attribute \src "libresoc.v:90324.9-90324.17" case 1'1 case end @@ -140495,14 +141816,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end - attribute \src "libresoc.v:89818.3-89836.6" - process $proc$libresoc.v:89818$3820 + attribute \src "libresoc.v:90342.3-90360.6" + process $proc$libresoc.v:90342$3874 assign { } { } assign { } { } assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:89819.5-89819.29" + attribute \src "libresoc.v:90343.5-90343.29" switch \initial - attribute \src "libresoc.v:89819.9-89819.17" + attribute \src "libresoc.v:90343.9-90343.17" case 1'1 case end @@ -140530,14 +141851,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:89837.3-89855.6" - process $proc$libresoc.v:89837$3821 + attribute \src "libresoc.v:90361.3-90379.6" + process $proc$libresoc.v:90361$3875 assign { } { } assign { } { } assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:89838.5-89838.29" + attribute \src "libresoc.v:90362.5-90362.29" switch \initial - attribute \src "libresoc.v:89838.9-89838.17" + attribute \src "libresoc.v:90362.9-90362.17" case 1'1 case end @@ -140565,14 +141886,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end - attribute \src "libresoc.v:89856.3-89874.6" - process $proc$libresoc.v:89856$3822 + attribute \src "libresoc.v:90380.3-90398.6" + process $proc$libresoc.v:90380$3876 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:89857.5-89857.29" + attribute \src "libresoc.v:90381.5-90381.29" switch \initial - attribute \src "libresoc.v:89857.9-89857.17" + attribute \src "libresoc.v:90381.9-90381.17" case 1'1 case end @@ -140600,14 +141921,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:89875.3-89893.6" - process $proc$libresoc.v:89875$3823 + attribute \src "libresoc.v:90399.3-90417.6" + process $proc$libresoc.v:90399$3877 assign { } { } assign { } { } assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:89876.5-89876.29" + attribute \src "libresoc.v:90400.5-90400.29" switch \initial - attribute \src "libresoc.v:89876.9-89876.17" + attribute \src "libresoc.v:90400.9-90400.17" case 1'1 case end @@ -140635,14 +141956,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end - attribute \src "libresoc.v:89894.3-89912.6" - process $proc$libresoc.v:89894$3824 + attribute \src "libresoc.v:90418.3-90436.6" + process $proc$libresoc.v:90418$3878 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:89895.5-89895.29" + attribute \src "libresoc.v:90419.5-90419.29" switch \initial - attribute \src "libresoc.v:89895.9-89895.17" + attribute \src "libresoc.v:90419.9-90419.17" case 1'1 case end @@ -140670,14 +141991,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end - attribute \src "libresoc.v:89913.3-89931.6" - process $proc$libresoc.v:89913$3825 + attribute \src "libresoc.v:90437.3-90455.6" + process $proc$libresoc.v:90437$3879 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:89914.5-89914.29" + attribute \src "libresoc.v:90438.5-90438.29" switch \initial - attribute \src "libresoc.v:89914.9-89914.17" + attribute \src "libresoc.v:90438.9-90438.17" case 1'1 case end @@ -140705,14 +142026,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] end - attribute \src "libresoc.v:89932.3-89950.6" - process $proc$libresoc.v:89932$3826 + attribute \src "libresoc.v:90456.3-90474.6" + process $proc$libresoc.v:90456$3880 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:89933.5-89933.29" + attribute \src "libresoc.v:90457.5-90457.29" switch \initial - attribute \src "libresoc.v:89933.9-89933.17" + attribute \src "libresoc.v:90457.9-90457.17" case 1'1 case end @@ -140740,14 +142061,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] end - attribute \src "libresoc.v:89951.3-89969.6" - process $proc$libresoc.v:89951$3827 + attribute \src "libresoc.v:90475.3-90493.6" + process $proc$libresoc.v:90475$3881 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:89952.5-89952.29" + attribute \src "libresoc.v:90476.5-90476.29" switch \initial - attribute \src "libresoc.v:89952.9-89952.17" + attribute \src "libresoc.v:90476.9-90476.17" case 1'1 case end @@ -140775,14 +142096,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:89970.3-89988.6" - process $proc$libresoc.v:89970$3828 + attribute \src "libresoc.v:90494.3-90512.6" + process $proc$libresoc.v:90494$3882 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:89971.5-89971.29" + attribute \src "libresoc.v:90495.5-90495.29" switch \initial - attribute \src "libresoc.v:89971.9-89971.17" + attribute \src "libresoc.v:90495.9-90495.17" case 1'1 case end @@ -140810,14 +142131,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:89989.3-90007.6" - process $proc$libresoc.v:89989$3829 + attribute \src "libresoc.v:90513.3-90531.6" + process $proc$libresoc.v:90513$3883 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:89990.5-89990.29" + attribute \src "libresoc.v:90514.5-90514.29" switch \initial - attribute \src "libresoc.v:89990.9-89990.17" + attribute \src "libresoc.v:90514.9-90514.17" case 1'1 case end @@ -140845,14 +142166,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end - attribute \src "libresoc.v:90008.3-90026.6" - process $proc$libresoc.v:90008$3830 + attribute \src "libresoc.v:90532.3-90550.6" + process $proc$libresoc.v:90532$3884 assign { } { } assign { } { } assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:90009.5-90009.29" + attribute \src "libresoc.v:90533.5-90533.29" switch \initial - attribute \src "libresoc.v:90009.9-90009.17" + attribute \src "libresoc.v:90533.9-90533.17" case 1'1 case end @@ -140882,140 +142203,140 @@ module \dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:90032.1-91552.10" +attribute \src "libresoc.v:90556.1-92077.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" module \dec31_dec_sub10 - attribute \src "libresoc.v:91329.3-91365.6" + attribute \src "libresoc.v:91854.3-91890.6" wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:91366.3-91402.6" + attribute \src "libresoc.v:91891.3-91927.6" wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:90885.3-90921.6" + attribute \src "libresoc.v:91410.3-91446.6" wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:91033.3-91069.6" + attribute \src "libresoc.v:91558.3-91594.6" wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:90404.3-90440.6" + attribute \src "libresoc.v:90929.3-90965.6" wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:90441.3-90477.6" + attribute \src "libresoc.v:90966.3-91002.6" wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:90848.3-90884.6" + attribute \src "libresoc.v:91373.3-91409.6" wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:90996.3-91032.6" + attribute \src "libresoc.v:91521.3-91557.6" wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:91181.3-91217.6" + attribute \src "libresoc.v:91706.3-91742.6" wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:90367.3-90403.6" + attribute \src "libresoc.v:90892.3-90928.6" wire width 13 $0\dec31_dec_sub10_function_unit[12:0] - attribute \src "libresoc.v:91403.3-91439.6" + attribute \src "libresoc.v:91928.3-91964.6" wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:91440.3-91476.6" + attribute \src "libresoc.v:91965.3-92001.6" wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:91477.3-91513.6" + attribute \src "libresoc.v:92002.3-92038.6" wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:90774.3-90810.6" + attribute \src "libresoc.v:91299.3-91335.6" wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:90922.3-90958.6" + attribute \src "libresoc.v:91447.3-91483.6" wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:90959.3-90995.6" + attribute \src "libresoc.v:91484.3-91520.6" wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:91144.3-91180.6" + attribute \src "libresoc.v:91669.3-91705.6" wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:90700.3-90736.6" + attribute \src "libresoc.v:91225.3-91261.6" wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:91255.3-91291.6" + attribute \src "libresoc.v:91780.3-91816.6" wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:91514.3-91550.6" + attribute \src "libresoc.v:92039.3-92075.6" wire width 2 $0\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:90811.3-90847.6" + attribute \src "libresoc.v:91336.3-91372.6" wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:91107.3-91143.6" + attribute \src "libresoc.v:91632.3-91668.6" wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:91292.3-91328.6" + attribute \src "libresoc.v:91817.3-91853.6" wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:91218.3-91254.6" + attribute \src "libresoc.v:91743.3-91779.6" wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:91070.3-91106.6" + attribute \src "libresoc.v:91595.3-91631.6" wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:90626.3-90662.6" + attribute \src "libresoc.v:91151.3-91187.6" wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:90663.3-90699.6" + attribute \src "libresoc.v:91188.3-91224.6" wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:90478.3-90514.6" + attribute \src "libresoc.v:91003.3-91039.6" wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:90515.3-90551.6" + attribute \src "libresoc.v:91040.3-91076.6" wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:90552.3-90588.6" + attribute \src "libresoc.v:91077.3-91113.6" wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:90589.3-90625.6" + attribute \src "libresoc.v:91114.3-91150.6" wire width 3 $0\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:90737.3-90773.6" + attribute \src "libresoc.v:91262.3-91298.6" wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:90033.7-90033.20" + attribute \src "libresoc.v:90557.7-90557.20" wire $0\initial[0:0] - attribute \src "libresoc.v:91329.3-91365.6" + attribute \src "libresoc.v:91854.3-91890.6" wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:91366.3-91402.6" + attribute \src "libresoc.v:91891.3-91927.6" wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:90885.3-90921.6" + attribute \src "libresoc.v:91410.3-91446.6" wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:91033.3-91069.6" + attribute \src "libresoc.v:91558.3-91594.6" wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:90404.3-90440.6" + attribute \src "libresoc.v:90929.3-90965.6" wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:90441.3-90477.6" + attribute \src "libresoc.v:90966.3-91002.6" wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:90848.3-90884.6" + attribute \src "libresoc.v:91373.3-91409.6" wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:90996.3-91032.6" + attribute \src "libresoc.v:91521.3-91557.6" wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:91181.3-91217.6" + attribute \src "libresoc.v:91706.3-91742.6" wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:90367.3-90403.6" + attribute \src "libresoc.v:90892.3-90928.6" wire width 13 $1\dec31_dec_sub10_function_unit[12:0] - attribute \src "libresoc.v:91403.3-91439.6" + attribute \src "libresoc.v:91928.3-91964.6" wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:91440.3-91476.6" + attribute \src "libresoc.v:91965.3-92001.6" wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:91477.3-91513.6" + attribute \src "libresoc.v:92002.3-92038.6" wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:90774.3-90810.6" + attribute \src "libresoc.v:91299.3-91335.6" wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:90922.3-90958.6" + attribute \src "libresoc.v:91447.3-91483.6" wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:90959.3-90995.6" + attribute \src "libresoc.v:91484.3-91520.6" wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:91144.3-91180.6" + attribute \src "libresoc.v:91669.3-91705.6" wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:90700.3-90736.6" + attribute \src "libresoc.v:91225.3-91261.6" wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:91255.3-91291.6" + attribute \src "libresoc.v:91780.3-91816.6" wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:91514.3-91550.6" + attribute \src "libresoc.v:92039.3-92075.6" wire width 2 $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:90811.3-90847.6" + attribute \src "libresoc.v:91336.3-91372.6" wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:91107.3-91143.6" + attribute \src "libresoc.v:91632.3-91668.6" wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:91292.3-91328.6" + attribute \src "libresoc.v:91817.3-91853.6" wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:91218.3-91254.6" + attribute \src "libresoc.v:91743.3-91779.6" wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:91070.3-91106.6" + attribute \src "libresoc.v:91595.3-91631.6" wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:90626.3-90662.6" + attribute \src "libresoc.v:91151.3-91187.6" wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:90663.3-90699.6" + attribute \src "libresoc.v:91188.3-91224.6" wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:90478.3-90514.6" + attribute \src "libresoc.v:91003.3-91039.6" wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:90515.3-90551.6" + attribute \src "libresoc.v:91040.3-91076.6" wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:90552.3-90588.6" + attribute \src "libresoc.v:91077.3-91113.6" wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:90589.3-90625.6" + attribute \src "libresoc.v:91114.3-91150.6" wire width 3 $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:90737.3-90773.6" + attribute \src "libresoc.v:91262.3-91298.6" wire width 2 $1\dec31_dec_sub10_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -141091,6 +142412,7 @@ module \dec31_dec_sub10 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub10_form attribute \enum_base_type "Function" @@ -141314,28 +142636,28 @@ module \dec31_dec_sub10 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub10_upd - attribute \src "libresoc.v:90033.7-90033.15" + attribute \src "libresoc.v:90557.7-90557.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:90033.7-90033.20" - process $proc$libresoc.v:90033$3864 + attribute \src "libresoc.v:90557.7-90557.20" + process $proc$libresoc.v:90557$3918 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:90367.3-90403.6" - process $proc$libresoc.v:90367$3832 + attribute \src "libresoc.v:90892.3-90928.6" + process $proc$libresoc.v:90892$3886 assign { } { } assign { } { } assign $0\dec31_dec_sub10_function_unit[12:0] $1\dec31_dec_sub10_function_unit[12:0] - attribute \src "libresoc.v:90368.5-90368.29" + attribute \src "libresoc.v:90893.5-90893.29" switch \initial - attribute \src "libresoc.v:90368.9-90368.17" + attribute \src "libresoc.v:90893.9-90893.17" case 1'1 case end @@ -141387,14 +142709,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[12:0] end - attribute \src "libresoc.v:90404.3-90440.6" - process $proc$libresoc.v:90404$3833 + attribute \src "libresoc.v:90929.3-90965.6" + process $proc$libresoc.v:90929$3887 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:90405.5-90405.29" + attribute \src "libresoc.v:90930.5-90930.29" switch \initial - attribute \src "libresoc.v:90405.9-90405.17" + attribute \src "libresoc.v:90930.9-90930.17" case 1'1 case end @@ -141446,14 +142768,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:90441.3-90477.6" - process $proc$libresoc.v:90441$3834 + attribute \src "libresoc.v:90966.3-91002.6" + process $proc$libresoc.v:90966$3888 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:90442.5-90442.29" + attribute \src "libresoc.v:90967.5-90967.29" switch \initial - attribute \src "libresoc.v:90442.9-90442.17" + attribute \src "libresoc.v:90967.9-90967.17" case 1'1 case end @@ -141505,14 +142827,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end - attribute \src "libresoc.v:90478.3-90514.6" - process $proc$libresoc.v:90478$3835 + attribute \src "libresoc.v:91003.3-91039.6" + process $proc$libresoc.v:91003$3889 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:90479.5-90479.29" + attribute \src "libresoc.v:91004.5-91004.29" switch \initial - attribute \src "libresoc.v:90479.9-90479.17" + attribute \src "libresoc.v:91004.9-91004.17" case 1'1 case end @@ -141564,14 +142886,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] end - attribute \src "libresoc.v:90515.3-90551.6" - process $proc$libresoc.v:90515$3836 + attribute \src "libresoc.v:91040.3-91076.6" + process $proc$libresoc.v:91040$3890 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:90516.5-90516.29" + attribute \src "libresoc.v:91041.5-91041.29" switch \initial - attribute \src "libresoc.v:90516.9-90516.17" + attribute \src "libresoc.v:91041.9-91041.17" case 1'1 case end @@ -141623,14 +142945,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] end - attribute \src "libresoc.v:90552.3-90588.6" - process $proc$libresoc.v:90552$3837 + attribute \src "libresoc.v:91077.3-91113.6" + process $proc$libresoc.v:91077$3891 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:90553.5-90553.29" + attribute \src "libresoc.v:91078.5-91078.29" switch \initial - attribute \src "libresoc.v:90553.9-90553.17" + attribute \src "libresoc.v:91078.9-91078.17" case 1'1 case end @@ -141682,14 +143004,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] end - attribute \src "libresoc.v:90589.3-90625.6" - process $proc$libresoc.v:90589$3838 + attribute \src "libresoc.v:91114.3-91150.6" + process $proc$libresoc.v:91114$3892 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:90590.5-90590.29" + attribute \src "libresoc.v:91115.5-91115.29" switch \initial - attribute \src "libresoc.v:90590.9-90590.17" + attribute \src "libresoc.v:91115.9-91115.17" case 1'1 case end @@ -141741,14 +143063,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] end - attribute \src "libresoc.v:90626.3-90662.6" - process $proc$libresoc.v:90626$3839 + attribute \src "libresoc.v:91151.3-91187.6" + process $proc$libresoc.v:91151$3893 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:90627.5-90627.29" + attribute \src "libresoc.v:91152.5-91152.29" switch \initial - attribute \src "libresoc.v:90627.9-90627.17" + attribute \src "libresoc.v:91152.9-91152.17" case 1'1 case end @@ -141800,14 +143122,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] end - attribute \src "libresoc.v:90663.3-90699.6" - process $proc$libresoc.v:90663$3840 + attribute \src "libresoc.v:91188.3-91224.6" + process $proc$libresoc.v:91188$3894 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:90664.5-90664.29" + attribute \src "libresoc.v:91189.5-91189.29" switch \initial - attribute \src "libresoc.v:90664.9-90664.17" + attribute \src "libresoc.v:91189.9-91189.17" case 1'1 case end @@ -141859,14 +143181,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] end - attribute \src "libresoc.v:90700.3-90736.6" - process $proc$libresoc.v:90700$3841 + attribute \src "libresoc.v:91225.3-91261.6" + process $proc$libresoc.v:91225$3895 assign { } { } assign { } { } assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:90701.5-90701.29" + attribute \src "libresoc.v:91226.5-91226.29" switch \initial - attribute \src "libresoc.v:90701.9-90701.17" + attribute \src "libresoc.v:91226.9-91226.17" case 1'1 case end @@ -141918,14 +143240,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:90737.3-90773.6" - process $proc$libresoc.v:90737$3842 + attribute \src "libresoc.v:91262.3-91298.6" + process $proc$libresoc.v:91262$3896 assign { } { } assign { } { } assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:90738.5-90738.29" + attribute \src "libresoc.v:91263.5-91263.29" switch \initial - attribute \src "libresoc.v:90738.9-90738.17" + attribute \src "libresoc.v:91263.9-91263.17" case 1'1 case end @@ -141977,14 +143299,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "libresoc.v:90774.3-90810.6" - process $proc$libresoc.v:90774$3843 + attribute \src "libresoc.v:91299.3-91335.6" + process $proc$libresoc.v:91299$3897 assign { } { } assign { } { } assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:90775.5-90775.29" + attribute \src "libresoc.v:91300.5-91300.29" switch \initial - attribute \src "libresoc.v:90775.9-90775.17" + attribute \src "libresoc.v:91300.9-91300.17" case 1'1 case end @@ -142036,14 +143358,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:90811.3-90847.6" - process $proc$libresoc.v:90811$3844 + attribute \src "libresoc.v:91336.3-91372.6" + process $proc$libresoc.v:91336$3898 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:90812.5-90812.29" + attribute \src "libresoc.v:91337.5-91337.29" switch \initial - attribute \src "libresoc.v:90812.9-90812.17" + attribute \src "libresoc.v:91337.9-91337.17" case 1'1 case end @@ -142095,14 +143417,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "libresoc.v:90848.3-90884.6" - process $proc$libresoc.v:90848$3845 + attribute \src "libresoc.v:91373.3-91409.6" + process $proc$libresoc.v:91373$3899 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:90849.5-90849.29" + attribute \src "libresoc.v:91374.5-91374.29" switch \initial - attribute \src "libresoc.v:90849.9-90849.17" + attribute \src "libresoc.v:91374.9-91374.17" case 1'1 case end @@ -142154,14 +143476,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "libresoc.v:90885.3-90921.6" - process $proc$libresoc.v:90885$3846 + attribute \src "libresoc.v:91410.3-91446.6" + process $proc$libresoc.v:91410$3900 assign { } { } assign { } { } assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:90886.5-90886.29" + attribute \src "libresoc.v:91411.5-91411.29" switch \initial - attribute \src "libresoc.v:90886.9-90886.17" + attribute \src "libresoc.v:91411.9-91411.17" case 1'1 case end @@ -142213,14 +143535,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "libresoc.v:90922.3-90958.6" - process $proc$libresoc.v:90922$3847 + attribute \src "libresoc.v:91447.3-91483.6" + process $proc$libresoc.v:91447$3901 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:90923.5-90923.29" + attribute \src "libresoc.v:91448.5-91448.29" switch \initial - attribute \src "libresoc.v:90923.9-90923.17" + attribute \src "libresoc.v:91448.9-91448.17" case 1'1 case end @@ -142272,14 +143594,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end - attribute \src "libresoc.v:90959.3-90995.6" - process $proc$libresoc.v:90959$3848 + attribute \src "libresoc.v:91484.3-91520.6" + process $proc$libresoc.v:91484$3902 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:90960.5-90960.29" + attribute \src "libresoc.v:91485.5-91485.29" switch \initial - attribute \src "libresoc.v:90960.9-90960.17" + attribute \src "libresoc.v:91485.9-91485.17" case 1'1 case end @@ -142331,14 +143653,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end - attribute \src "libresoc.v:90996.3-91032.6" - process $proc$libresoc.v:90996$3849 + attribute \src "libresoc.v:91521.3-91557.6" + process $proc$libresoc.v:91521$3903 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:90997.5-90997.29" + attribute \src "libresoc.v:91522.5-91522.29" switch \initial - attribute \src "libresoc.v:90997.9-90997.17" + attribute \src "libresoc.v:91522.9-91522.17" case 1'1 case end @@ -142390,14 +143712,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end - attribute \src "libresoc.v:91033.3-91069.6" - process $proc$libresoc.v:91033$3850 + attribute \src "libresoc.v:91558.3-91594.6" + process $proc$libresoc.v:91558$3904 assign { } { } assign { } { } assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91034.5-91034.29" + attribute \src "libresoc.v:91559.5-91559.29" switch \initial - attribute \src "libresoc.v:91034.9-91034.17" + attribute \src "libresoc.v:91559.9-91559.17" case 1'1 case end @@ -142449,14 +143771,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end - attribute \src "libresoc.v:91070.3-91106.6" - process $proc$libresoc.v:91070$3851 + attribute \src "libresoc.v:91595.3-91631.6" + process $proc$libresoc.v:91595$3905 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:91071.5-91071.29" + attribute \src "libresoc.v:91596.5-91596.29" switch \initial - attribute \src "libresoc.v:91071.9-91071.17" + attribute \src "libresoc.v:91596.9-91596.17" case 1'1 case end @@ -142508,14 +143830,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end - attribute \src "libresoc.v:91107.3-91143.6" - process $proc$libresoc.v:91107$3852 + attribute \src "libresoc.v:91632.3-91668.6" + process $proc$libresoc.v:91632$3906 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:91108.5-91108.29" + attribute \src "libresoc.v:91633.5-91633.29" switch \initial - attribute \src "libresoc.v:91108.9-91108.17" + attribute \src "libresoc.v:91633.9-91633.17" case 1'1 case end @@ -142567,14 +143889,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "libresoc.v:91144.3-91180.6" - process $proc$libresoc.v:91144$3853 + attribute \src "libresoc.v:91669.3-91705.6" + process $proc$libresoc.v:91669$3907 assign { } { } assign { } { } assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:91145.5-91145.29" + attribute \src "libresoc.v:91670.5-91670.29" switch \initial - attribute \src "libresoc.v:91145.9-91145.17" + attribute \src "libresoc.v:91670.9-91670.17" case 1'1 case end @@ -142626,14 +143948,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:91181.3-91217.6" - process $proc$libresoc.v:91181$3854 + attribute \src "libresoc.v:91706.3-91742.6" + process $proc$libresoc.v:91706$3908 assign { } { } assign { } { } assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91182.5-91182.29" + attribute \src "libresoc.v:91707.5-91707.29" switch \initial - attribute \src "libresoc.v:91182.9-91182.17" + attribute \src "libresoc.v:91707.9-91707.17" case 1'1 case end @@ -142685,14 +144007,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "libresoc.v:91218.3-91254.6" - process $proc$libresoc.v:91218$3855 + attribute \src "libresoc.v:91743.3-91779.6" + process $proc$libresoc.v:91743$3909 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:91219.5-91219.29" + attribute \src "libresoc.v:91744.5-91744.29" switch \initial - attribute \src "libresoc.v:91219.9-91219.17" + attribute \src "libresoc.v:91744.9-91744.17" case 1'1 case end @@ -142744,14 +144066,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:91255.3-91291.6" - process $proc$libresoc.v:91255$3856 + attribute \src "libresoc.v:91780.3-91816.6" + process $proc$libresoc.v:91780$3910 assign { } { } assign { } { } assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:91256.5-91256.29" + attribute \src "libresoc.v:91781.5-91781.29" switch \initial - attribute \src "libresoc.v:91256.9-91256.17" + attribute \src "libresoc.v:91781.9-91781.17" case 1'1 case end @@ -142803,14 +144125,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "libresoc.v:91292.3-91328.6" - process $proc$libresoc.v:91292$3857 + attribute \src "libresoc.v:91817.3-91853.6" + process $proc$libresoc.v:91817$3911 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:91293.5-91293.29" + attribute \src "libresoc.v:91818.5-91818.29" switch \initial - attribute \src "libresoc.v:91293.9-91293.17" + attribute \src "libresoc.v:91818.9-91818.17" case 1'1 case end @@ -142862,14 +144184,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "libresoc.v:91329.3-91365.6" - process $proc$libresoc.v:91329$3858 + attribute \src "libresoc.v:91854.3-91890.6" + process $proc$libresoc.v:91854$3912 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:91330.5-91330.29" + attribute \src "libresoc.v:91855.5-91855.29" switch \initial - attribute \src "libresoc.v:91330.9-91330.17" + attribute \src "libresoc.v:91855.9-91855.17" case 1'1 case end @@ -142921,14 +144243,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] end - attribute \src "libresoc.v:91366.3-91402.6" - process $proc$libresoc.v:91366$3859 + attribute \src "libresoc.v:91891.3-91927.6" + process $proc$libresoc.v:91891$3913 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:91367.5-91367.29" + attribute \src "libresoc.v:91892.5-91892.29" switch \initial - attribute \src "libresoc.v:91367.9-91367.17" + attribute \src "libresoc.v:91892.9-91892.17" case 1'1 case end @@ -142980,14 +144302,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] end - attribute \src "libresoc.v:91403.3-91439.6" - process $proc$libresoc.v:91403$3860 + attribute \src "libresoc.v:91928.3-91964.6" + process $proc$libresoc.v:91928$3914 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:91404.5-91404.29" + attribute \src "libresoc.v:91929.5-91929.29" switch \initial - attribute \src "libresoc.v:91404.9-91404.17" + attribute \src "libresoc.v:91929.9-91929.17" case 1'1 case end @@ -143039,14 +144361,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:91440.3-91476.6" - process $proc$libresoc.v:91440$3861 + attribute \src "libresoc.v:91965.3-92001.6" + process $proc$libresoc.v:91965$3915 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:91441.5-91441.29" + attribute \src "libresoc.v:91966.5-91966.29" switch \initial - attribute \src "libresoc.v:91441.9-91441.17" + attribute \src "libresoc.v:91966.9-91966.17" case 1'1 case end @@ -143098,14 +144420,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:91477.3-91513.6" - process $proc$libresoc.v:91477$3862 + attribute \src "libresoc.v:92002.3-92038.6" + process $proc$libresoc.v:92002$3916 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:91478.5-91478.29" + attribute \src "libresoc.v:92003.5-92003.29" switch \initial - attribute \src "libresoc.v:91478.9-91478.17" + attribute \src "libresoc.v:92003.9-92003.17" case 1'1 case end @@ -143157,14 +144479,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "libresoc.v:91514.3-91550.6" - process $proc$libresoc.v:91514$3863 + attribute \src "libresoc.v:92039.3-92075.6" + process $proc$libresoc.v:92039$3917 assign { } { } assign { } { } assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:91515.5-91515.29" + attribute \src "libresoc.v:92040.5-92040.29" switch \initial - attribute \src "libresoc.v:91515.9-91515.17" + attribute \src "libresoc.v:92040.9-92040.17" case 1'1 case end @@ -143218,140 +144540,140 @@ module \dec31_dec_sub10 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:91556.1-93652.10" +attribute \src "libresoc.v:92081.1-94178.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" module \dec31_dec_sub11 - attribute \src "libresoc.v:93321.3-93375.6" + attribute \src "libresoc.v:93847.3-93901.6" wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:93376.3-93430.6" + attribute \src "libresoc.v:93902.3-93956.6" wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:92661.3-92715.6" + attribute \src "libresoc.v:93187.3-93241.6" wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:92881.3-92935.6" + attribute \src "libresoc.v:93407.3-93461.6" wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:91946.3-92000.6" + attribute \src "libresoc.v:92472.3-92526.6" wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:92001.3-92055.6" + attribute \src "libresoc.v:92527.3-92581.6" wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:92606.3-92660.6" + attribute \src "libresoc.v:93132.3-93186.6" wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:92826.3-92880.6" + attribute \src "libresoc.v:93352.3-93406.6" wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:93101.3-93155.6" + attribute \src "libresoc.v:93627.3-93681.6" wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:91891.3-91945.6" + attribute \src "libresoc.v:92417.3-92471.6" wire width 13 $0\dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:93431.3-93485.6" + attribute \src "libresoc.v:93957.3-94011.6" wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:93486.3-93540.6" + attribute \src "libresoc.v:94012.3-94066.6" wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:93541.3-93595.6" + attribute \src "libresoc.v:94067.3-94121.6" wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:92496.3-92550.6" + attribute \src "libresoc.v:93022.3-93076.6" wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:92716.3-92770.6" + attribute \src "libresoc.v:93242.3-93296.6" wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:92771.3-92825.6" + attribute \src "libresoc.v:93297.3-93351.6" wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:93046.3-93100.6" + attribute \src "libresoc.v:93572.3-93626.6" wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:92386.3-92440.6" + attribute \src "libresoc.v:92912.3-92966.6" wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93211.3-93265.6" + attribute \src "libresoc.v:93737.3-93791.6" wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:93596.3-93650.6" + attribute \src "libresoc.v:94122.3-94176.6" wire width 2 $0\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:92551.3-92605.6" + attribute \src "libresoc.v:93077.3-93131.6" wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:92991.3-93045.6" + attribute \src "libresoc.v:93517.3-93571.6" wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:93266.3-93320.6" + attribute \src "libresoc.v:93792.3-93846.6" wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:93156.3-93210.6" + attribute \src "libresoc.v:93682.3-93736.6" wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:92936.3-92990.6" + attribute \src "libresoc.v:93462.3-93516.6" wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:92276.3-92330.6" + attribute \src "libresoc.v:92802.3-92856.6" wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:92331.3-92385.6" + attribute \src "libresoc.v:92857.3-92911.6" wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:92056.3-92110.6" + attribute \src "libresoc.v:92582.3-92636.6" wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:92111.3-92165.6" + attribute \src "libresoc.v:92637.3-92691.6" wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:92166.3-92220.6" + attribute \src "libresoc.v:92692.3-92746.6" wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:92221.3-92275.6" + attribute \src "libresoc.v:92747.3-92801.6" wire width 3 $0\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:92441.3-92495.6" + attribute \src "libresoc.v:92967.3-93021.6" wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:91557.7-91557.20" + attribute \src "libresoc.v:92082.7-92082.20" wire $0\initial[0:0] - attribute \src "libresoc.v:93321.3-93375.6" + attribute \src "libresoc.v:93847.3-93901.6" wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:93376.3-93430.6" + attribute \src "libresoc.v:93902.3-93956.6" wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:92661.3-92715.6" + attribute \src "libresoc.v:93187.3-93241.6" wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:92881.3-92935.6" + attribute \src "libresoc.v:93407.3-93461.6" wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:91946.3-92000.6" + attribute \src "libresoc.v:92472.3-92526.6" wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:92001.3-92055.6" + attribute \src "libresoc.v:92527.3-92581.6" wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:92606.3-92660.6" + attribute \src "libresoc.v:93132.3-93186.6" wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:92826.3-92880.6" + attribute \src "libresoc.v:93352.3-93406.6" wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:93101.3-93155.6" + attribute \src "libresoc.v:93627.3-93681.6" wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:91891.3-91945.6" + attribute \src "libresoc.v:92417.3-92471.6" wire width 13 $1\dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:93431.3-93485.6" + attribute \src "libresoc.v:93957.3-94011.6" wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:93486.3-93540.6" + attribute \src "libresoc.v:94012.3-94066.6" wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:93541.3-93595.6" + attribute \src "libresoc.v:94067.3-94121.6" wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:92496.3-92550.6" + attribute \src "libresoc.v:93022.3-93076.6" wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:92716.3-92770.6" + attribute \src "libresoc.v:93242.3-93296.6" wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:92771.3-92825.6" + attribute \src "libresoc.v:93297.3-93351.6" wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:93046.3-93100.6" + attribute \src "libresoc.v:93572.3-93626.6" wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:92386.3-92440.6" + attribute \src "libresoc.v:92912.3-92966.6" wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93211.3-93265.6" + attribute \src "libresoc.v:93737.3-93791.6" wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:93596.3-93650.6" + attribute \src "libresoc.v:94122.3-94176.6" wire width 2 $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:92551.3-92605.6" + attribute \src "libresoc.v:93077.3-93131.6" wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:92991.3-93045.6" + attribute \src "libresoc.v:93517.3-93571.6" wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:93266.3-93320.6" + attribute \src "libresoc.v:93792.3-93846.6" wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:93156.3-93210.6" + attribute \src "libresoc.v:93682.3-93736.6" wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:92936.3-92990.6" + attribute \src "libresoc.v:93462.3-93516.6" wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:92276.3-92330.6" + attribute \src "libresoc.v:92802.3-92856.6" wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:92331.3-92385.6" + attribute \src "libresoc.v:92857.3-92911.6" wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:92056.3-92110.6" + attribute \src "libresoc.v:92582.3-92636.6" wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:92111.3-92165.6" + attribute \src "libresoc.v:92637.3-92691.6" wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:92166.3-92220.6" + attribute \src "libresoc.v:92692.3-92746.6" wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:92221.3-92275.6" + attribute \src "libresoc.v:92747.3-92801.6" wire width 3 $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:92441.3-92495.6" + attribute \src "libresoc.v:92967.3-93021.6" wire width 2 $1\dec31_dec_sub11_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -143427,6 +144749,7 @@ module \dec31_dec_sub11 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub11_form attribute \enum_base_type "Function" @@ -143650,28 +144973,28 @@ module \dec31_dec_sub11 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub11_upd - attribute \src "libresoc.v:91557.7-91557.15" + attribute \src "libresoc.v:92082.7-92082.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:91557.7-91557.20" - process $proc$libresoc.v:91557$3897 + attribute \src "libresoc.v:92082.7-92082.20" + process $proc$libresoc.v:92082$3951 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:91891.3-91945.6" - process $proc$libresoc.v:91891$3865 + attribute \src "libresoc.v:92417.3-92471.6" + process $proc$libresoc.v:92417$3919 assign { } { } assign { } { } assign $0\dec31_dec_sub11_function_unit[12:0] $1\dec31_dec_sub11_function_unit[12:0] - attribute \src "libresoc.v:91892.5-91892.29" + attribute \src "libresoc.v:92418.5-92418.29" switch \initial - attribute \src "libresoc.v:91892.9-91892.17" + attribute \src "libresoc.v:92418.9-92418.17" case 1'1 case end @@ -143747,14 +145070,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[12:0] end - attribute \src "libresoc.v:91946.3-92000.6" - process $proc$libresoc.v:91946$3866 + attribute \src "libresoc.v:92472.3-92526.6" + process $proc$libresoc.v:92472$3920 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:91947.5-91947.29" + attribute \src "libresoc.v:92473.5-92473.29" switch \initial - attribute \src "libresoc.v:91947.9-91947.17" + attribute \src "libresoc.v:92473.9-92473.17" case 1'1 case end @@ -143830,14 +145153,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:92001.3-92055.6" - process $proc$libresoc.v:92001$3867 + attribute \src "libresoc.v:92527.3-92581.6" + process $proc$libresoc.v:92527$3921 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:92002.5-92002.29" + attribute \src "libresoc.v:92528.5-92528.29" switch \initial - attribute \src "libresoc.v:92002.9-92002.17" + attribute \src "libresoc.v:92528.9-92528.17" case 1'1 case end @@ -143913,14 +145236,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:92056.3-92110.6" - process $proc$libresoc.v:92056$3868 + attribute \src "libresoc.v:92582.3-92636.6" + process $proc$libresoc.v:92582$3922 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:92057.5-92057.29" + attribute \src "libresoc.v:92583.5-92583.29" switch \initial - attribute \src "libresoc.v:92057.9-92057.17" + attribute \src "libresoc.v:92583.9-92583.17" case 1'1 case end @@ -143996,14 +145319,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] end - attribute \src "libresoc.v:92111.3-92165.6" - process $proc$libresoc.v:92111$3869 + attribute \src "libresoc.v:92637.3-92691.6" + process $proc$libresoc.v:92637$3923 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:92112.5-92112.29" + attribute \src "libresoc.v:92638.5-92638.29" switch \initial - attribute \src "libresoc.v:92112.9-92112.17" + attribute \src "libresoc.v:92638.9-92638.17" case 1'1 case end @@ -144079,14 +145402,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] end - attribute \src "libresoc.v:92166.3-92220.6" - process $proc$libresoc.v:92166$3870 + attribute \src "libresoc.v:92692.3-92746.6" + process $proc$libresoc.v:92692$3924 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:92167.5-92167.29" + attribute \src "libresoc.v:92693.5-92693.29" switch \initial - attribute \src "libresoc.v:92167.9-92167.17" + attribute \src "libresoc.v:92693.9-92693.17" case 1'1 case end @@ -144162,14 +145485,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] end - attribute \src "libresoc.v:92221.3-92275.6" - process $proc$libresoc.v:92221$3871 + attribute \src "libresoc.v:92747.3-92801.6" + process $proc$libresoc.v:92747$3925 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:92222.5-92222.29" + attribute \src "libresoc.v:92748.5-92748.29" switch \initial - attribute \src "libresoc.v:92222.9-92222.17" + attribute \src "libresoc.v:92748.9-92748.17" case 1'1 case end @@ -144245,14 +145568,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] end - attribute \src "libresoc.v:92276.3-92330.6" - process $proc$libresoc.v:92276$3872 + attribute \src "libresoc.v:92802.3-92856.6" + process $proc$libresoc.v:92802$3926 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:92277.5-92277.29" + attribute \src "libresoc.v:92803.5-92803.29" switch \initial - attribute \src "libresoc.v:92277.9-92277.17" + attribute \src "libresoc.v:92803.9-92803.17" case 1'1 case end @@ -144328,14 +145651,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] end - attribute \src "libresoc.v:92331.3-92385.6" - process $proc$libresoc.v:92331$3873 + attribute \src "libresoc.v:92857.3-92911.6" + process $proc$libresoc.v:92857$3927 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:92332.5-92332.29" + attribute \src "libresoc.v:92858.5-92858.29" switch \initial - attribute \src "libresoc.v:92332.9-92332.17" + attribute \src "libresoc.v:92858.9-92858.17" case 1'1 case end @@ -144411,14 +145734,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] end - attribute \src "libresoc.v:92386.3-92440.6" - process $proc$libresoc.v:92386$3874 + attribute \src "libresoc.v:92912.3-92966.6" + process $proc$libresoc.v:92912$3928 assign { } { } assign { } { } assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:92387.5-92387.29" + attribute \src "libresoc.v:92913.5-92913.29" switch \initial - attribute \src "libresoc.v:92387.9-92387.17" + attribute \src "libresoc.v:92913.9-92913.17" case 1'1 case end @@ -144494,14 +145817,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:92441.3-92495.6" - process $proc$libresoc.v:92441$3875 + attribute \src "libresoc.v:92967.3-93021.6" + process $proc$libresoc.v:92967$3929 assign { } { } assign { } { } assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:92442.5-92442.29" + attribute \src "libresoc.v:92968.5-92968.29" switch \initial - attribute \src "libresoc.v:92442.9-92442.17" + attribute \src "libresoc.v:92968.9-92968.17" case 1'1 case end @@ -144577,14 +145900,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "libresoc.v:92496.3-92550.6" - process $proc$libresoc.v:92496$3876 + attribute \src "libresoc.v:93022.3-93076.6" + process $proc$libresoc.v:93022$3930 assign { } { } assign { } { } assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:92497.5-92497.29" + attribute \src "libresoc.v:93023.5-93023.29" switch \initial - attribute \src "libresoc.v:92497.9-92497.17" + attribute \src "libresoc.v:93023.9-93023.17" case 1'1 case end @@ -144660,14 +145983,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:92551.3-92605.6" - process $proc$libresoc.v:92551$3877 + attribute \src "libresoc.v:93077.3-93131.6" + process $proc$libresoc.v:93077$3931 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:92552.5-92552.29" + attribute \src "libresoc.v:93078.5-93078.29" switch \initial - attribute \src "libresoc.v:92552.9-92552.17" + attribute \src "libresoc.v:93078.9-93078.17" case 1'1 case end @@ -144743,14 +146066,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:92606.3-92660.6" - process $proc$libresoc.v:92606$3878 + attribute \src "libresoc.v:93132.3-93186.6" + process $proc$libresoc.v:93132$3932 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:92607.5-92607.29" + attribute \src "libresoc.v:93133.5-93133.29" switch \initial - attribute \src "libresoc.v:92607.9-92607.17" + attribute \src "libresoc.v:93133.9-93133.17" case 1'1 case end @@ -144826,14 +146149,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "libresoc.v:92661.3-92715.6" - process $proc$libresoc.v:92661$3879 + attribute \src "libresoc.v:93187.3-93241.6" + process $proc$libresoc.v:93187$3933 assign { } { } assign { } { } assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:92662.5-92662.29" + attribute \src "libresoc.v:93188.5-93188.29" switch \initial - attribute \src "libresoc.v:92662.9-92662.17" + attribute \src "libresoc.v:93188.9-93188.17" case 1'1 case end @@ -144909,14 +146232,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "libresoc.v:92716.3-92770.6" - process $proc$libresoc.v:92716$3880 + attribute \src "libresoc.v:93242.3-93296.6" + process $proc$libresoc.v:93242$3934 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:92717.5-92717.29" + attribute \src "libresoc.v:93243.5-93243.29" switch \initial - attribute \src "libresoc.v:92717.9-92717.17" + attribute \src "libresoc.v:93243.9-93243.17" case 1'1 case end @@ -144992,14 +146315,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:92771.3-92825.6" - process $proc$libresoc.v:92771$3881 + attribute \src "libresoc.v:93297.3-93351.6" + process $proc$libresoc.v:93297$3935 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:92772.5-92772.29" + attribute \src "libresoc.v:93298.5-93298.29" switch \initial - attribute \src "libresoc.v:92772.9-92772.17" + attribute \src "libresoc.v:93298.9-93298.17" case 1'1 case end @@ -145075,14 +146398,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "libresoc.v:92826.3-92880.6" - process $proc$libresoc.v:92826$3882 + attribute \src "libresoc.v:93352.3-93406.6" + process $proc$libresoc.v:93352$3936 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:92827.5-92827.29" + attribute \src "libresoc.v:93353.5-93353.29" switch \initial - attribute \src "libresoc.v:92827.9-92827.17" + attribute \src "libresoc.v:93353.9-93353.17" case 1'1 case end @@ -145158,14 +146481,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "libresoc.v:92881.3-92935.6" - process $proc$libresoc.v:92881$3883 + attribute \src "libresoc.v:93407.3-93461.6" + process $proc$libresoc.v:93407$3937 assign { } { } assign { } { } assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:92882.5-92882.29" + attribute \src "libresoc.v:93408.5-93408.29" switch \initial - attribute \src "libresoc.v:92882.9-92882.17" + attribute \src "libresoc.v:93408.9-93408.17" case 1'1 case end @@ -145241,14 +146564,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "libresoc.v:92936.3-92990.6" - process $proc$libresoc.v:92936$3884 + attribute \src "libresoc.v:93462.3-93516.6" + process $proc$libresoc.v:93462$3938 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:92937.5-92937.29" + attribute \src "libresoc.v:93463.5-93463.29" switch \initial - attribute \src "libresoc.v:92937.9-92937.17" + attribute \src "libresoc.v:93463.9-93463.17" case 1'1 case end @@ -145324,14 +146647,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - attribute \src "libresoc.v:92991.3-93045.6" - process $proc$libresoc.v:92991$3885 + attribute \src "libresoc.v:93517.3-93571.6" + process $proc$libresoc.v:93517$3939 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:92992.5-92992.29" + attribute \src "libresoc.v:93518.5-93518.29" switch \initial - attribute \src "libresoc.v:92992.9-92992.17" + attribute \src "libresoc.v:93518.9-93518.17" case 1'1 case end @@ -145407,14 +146730,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "libresoc.v:93046.3-93100.6" - process $proc$libresoc.v:93046$3886 + attribute \src "libresoc.v:93572.3-93626.6" + process $proc$libresoc.v:93572$3940 assign { } { } assign { } { } assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93047.5-93047.29" + attribute \src "libresoc.v:93573.5-93573.29" switch \initial - attribute \src "libresoc.v:93047.9-93047.17" + attribute \src "libresoc.v:93573.9-93573.17" case 1'1 case end @@ -145490,14 +146813,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:93101.3-93155.6" - process $proc$libresoc.v:93101$3887 + attribute \src "libresoc.v:93627.3-93681.6" + process $proc$libresoc.v:93627$3941 assign { } { } assign { } { } assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:93102.5-93102.29" + attribute \src "libresoc.v:93628.5-93628.29" switch \initial - attribute \src "libresoc.v:93102.9-93102.17" + attribute \src "libresoc.v:93628.9-93628.17" case 1'1 case end @@ -145573,14 +146896,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "libresoc.v:93156.3-93210.6" - process $proc$libresoc.v:93156$3888 + attribute \src "libresoc.v:93682.3-93736.6" + process $proc$libresoc.v:93682$3942 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:93157.5-93157.29" + attribute \src "libresoc.v:93683.5-93683.29" switch \initial - attribute \src "libresoc.v:93157.9-93157.17" + attribute \src "libresoc.v:93683.9-93683.17" case 1'1 case end @@ -145656,14 +146979,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:93211.3-93265.6" - process $proc$libresoc.v:93211$3889 + attribute \src "libresoc.v:93737.3-93791.6" + process $proc$libresoc.v:93737$3943 assign { } { } assign { } { } assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:93212.5-93212.29" + attribute \src "libresoc.v:93738.5-93738.29" switch \initial - attribute \src "libresoc.v:93212.9-93212.17" + attribute \src "libresoc.v:93738.9-93738.17" case 1'1 case end @@ -145739,14 +147062,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "libresoc.v:93266.3-93320.6" - process $proc$libresoc.v:93266$3890 + attribute \src "libresoc.v:93792.3-93846.6" + process $proc$libresoc.v:93792$3944 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:93267.5-93267.29" + attribute \src "libresoc.v:93793.5-93793.29" switch \initial - attribute \src "libresoc.v:93267.9-93267.17" + attribute \src "libresoc.v:93793.9-93793.17" case 1'1 case end @@ -145822,14 +147145,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "libresoc.v:93321.3-93375.6" - process $proc$libresoc.v:93321$3891 + attribute \src "libresoc.v:93847.3-93901.6" + process $proc$libresoc.v:93847$3945 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:93322.5-93322.29" + attribute \src "libresoc.v:93848.5-93848.29" switch \initial - attribute \src "libresoc.v:93322.9-93322.17" + attribute \src "libresoc.v:93848.9-93848.17" case 1'1 case end @@ -145905,14 +147228,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] end - attribute \src "libresoc.v:93376.3-93430.6" - process $proc$libresoc.v:93376$3892 + attribute \src "libresoc.v:93902.3-93956.6" + process $proc$libresoc.v:93902$3946 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:93377.5-93377.29" + attribute \src "libresoc.v:93903.5-93903.29" switch \initial - attribute \src "libresoc.v:93377.9-93377.17" + attribute \src "libresoc.v:93903.9-93903.17" case 1'1 case end @@ -145988,14 +147311,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] end - attribute \src "libresoc.v:93431.3-93485.6" - process $proc$libresoc.v:93431$3893 + attribute \src "libresoc.v:93957.3-94011.6" + process $proc$libresoc.v:93957$3947 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:93432.5-93432.29" + attribute \src "libresoc.v:93958.5-93958.29" switch \initial - attribute \src "libresoc.v:93432.9-93432.17" + attribute \src "libresoc.v:93958.9-93958.17" case 1'1 case end @@ -146071,14 +147394,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "libresoc.v:93486.3-93540.6" - process $proc$libresoc.v:93486$3894 + attribute \src "libresoc.v:94012.3-94066.6" + process $proc$libresoc.v:94012$3948 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:93487.5-93487.29" + attribute \src "libresoc.v:94013.5-94013.29" switch \initial - attribute \src "libresoc.v:93487.9-93487.17" + attribute \src "libresoc.v:94013.9-94013.17" case 1'1 case end @@ -146154,14 +147477,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:93541.3-93595.6" - process $proc$libresoc.v:93541$3895 + attribute \src "libresoc.v:94067.3-94121.6" + process $proc$libresoc.v:94067$3949 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93542.5-93542.29" + attribute \src "libresoc.v:94068.5-94068.29" switch \initial - attribute \src "libresoc.v:93542.9-93542.17" + attribute \src "libresoc.v:94068.9-94068.17" case 1'1 case end @@ -146237,14 +147560,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "libresoc.v:93596.3-93650.6" - process $proc$libresoc.v:93596$3896 + attribute \src "libresoc.v:94122.3-94176.6" + process $proc$libresoc.v:94122$3950 assign { } { } assign { } { } assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:93597.5-93597.29" + attribute \src "libresoc.v:94123.5-94123.29" switch \initial - attribute \src "libresoc.v:93597.9-93597.17" + attribute \src "libresoc.v:94123.9-94123.17" case 1'1 case end @@ -146322,140 +147645,140 @@ module \dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:93656.1-97288.10" +attribute \src "libresoc.v:94182.1-97815.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" module \dec31_dec_sub15 - attribute \src "libresoc.v:96669.3-96771.6" + attribute \src "libresoc.v:97196.3-97298.6" wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:96772.3-96874.6" + attribute \src "libresoc.v:97299.3-97401.6" wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:95433.3-95535.6" + attribute \src "libresoc.v:95960.3-96062.6" wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:95845.3-95947.6" + attribute \src "libresoc.v:96372.3-96474.6" wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:94094.3-94196.6" + attribute \src "libresoc.v:94621.3-94723.6" wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:94197.3-94299.6" + attribute \src "libresoc.v:94724.3-94826.6" wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:95330.3-95432.6" + attribute \src "libresoc.v:95857.3-95959.6" wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:95742.3-95844.6" + attribute \src "libresoc.v:96269.3-96371.6" wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:96257.3-96359.6" + attribute \src "libresoc.v:96784.3-96886.6" wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:93991.3-94093.6" + attribute \src "libresoc.v:94518.3-94620.6" wire width 13 $0\dec31_dec_sub15_function_unit[12:0] - attribute \src "libresoc.v:96875.3-96977.6" + attribute \src "libresoc.v:97402.3-97504.6" wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:96978.3-97080.6" + attribute \src "libresoc.v:97505.3-97607.6" wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:97081.3-97183.6" + attribute \src "libresoc.v:97608.3-97710.6" wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:95124.3-95226.6" + attribute \src "libresoc.v:95651.3-95753.6" wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:95536.3-95638.6" + attribute \src "libresoc.v:96063.3-96165.6" wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:95639.3-95741.6" + attribute \src "libresoc.v:96166.3-96268.6" wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:96154.3-96256.6" + attribute \src "libresoc.v:96681.3-96783.6" wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:94918.3-95020.6" + attribute \src "libresoc.v:95445.3-95547.6" wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:96463.3-96565.6" + attribute \src "libresoc.v:96990.3-97092.6" wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:97184.3-97286.6" + attribute \src "libresoc.v:97711.3-97813.6" wire width 2 $0\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:95227.3-95329.6" + attribute \src "libresoc.v:95754.3-95856.6" wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:96051.3-96153.6" + attribute \src "libresoc.v:96578.3-96680.6" wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:96566.3-96668.6" + attribute \src "libresoc.v:97093.3-97195.6" wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:96360.3-96462.6" + attribute \src "libresoc.v:96887.3-96989.6" wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:95948.3-96050.6" + attribute \src "libresoc.v:96475.3-96577.6" wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:94712.3-94814.6" + attribute \src "libresoc.v:95239.3-95341.6" wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:94815.3-94917.6" + attribute \src "libresoc.v:95342.3-95444.6" wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:94300.3-94402.6" + attribute \src "libresoc.v:94827.3-94929.6" wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:94403.3-94505.6" + attribute \src "libresoc.v:94930.3-95032.6" wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:94506.3-94608.6" + attribute \src "libresoc.v:95033.3-95135.6" wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:94609.3-94711.6" + attribute \src "libresoc.v:95136.3-95238.6" wire width 3 $0\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:95021.3-95123.6" + attribute \src "libresoc.v:95548.3-95650.6" wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:93657.7-93657.20" + attribute \src "libresoc.v:94183.7-94183.20" wire $0\initial[0:0] - attribute \src "libresoc.v:96669.3-96771.6" + attribute \src "libresoc.v:97196.3-97298.6" wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:96772.3-96874.6" + attribute \src "libresoc.v:97299.3-97401.6" wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:95433.3-95535.6" + attribute \src "libresoc.v:95960.3-96062.6" wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:95845.3-95947.6" + attribute \src "libresoc.v:96372.3-96474.6" wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:94094.3-94196.6" + attribute \src "libresoc.v:94621.3-94723.6" wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:94197.3-94299.6" + attribute \src "libresoc.v:94724.3-94826.6" wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:95330.3-95432.6" + attribute \src "libresoc.v:95857.3-95959.6" wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:95742.3-95844.6" + attribute \src "libresoc.v:96269.3-96371.6" wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:96257.3-96359.6" + attribute \src "libresoc.v:96784.3-96886.6" wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:93991.3-94093.6" + attribute \src "libresoc.v:94518.3-94620.6" wire width 13 $1\dec31_dec_sub15_function_unit[12:0] - attribute \src "libresoc.v:96875.3-96977.6" + attribute \src "libresoc.v:97402.3-97504.6" wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:96978.3-97080.6" + attribute \src "libresoc.v:97505.3-97607.6" wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:97081.3-97183.6" + attribute \src "libresoc.v:97608.3-97710.6" wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:95124.3-95226.6" + attribute \src "libresoc.v:95651.3-95753.6" wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:95536.3-95638.6" + attribute \src "libresoc.v:96063.3-96165.6" wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:95639.3-95741.6" + attribute \src "libresoc.v:96166.3-96268.6" wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:96154.3-96256.6" + attribute \src "libresoc.v:96681.3-96783.6" wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:94918.3-95020.6" + attribute \src "libresoc.v:95445.3-95547.6" wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:96463.3-96565.6" + attribute \src "libresoc.v:96990.3-97092.6" wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:97184.3-97286.6" + attribute \src "libresoc.v:97711.3-97813.6" wire width 2 $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:95227.3-95329.6" + attribute \src "libresoc.v:95754.3-95856.6" wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:96051.3-96153.6" + attribute \src "libresoc.v:96578.3-96680.6" wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:96566.3-96668.6" + attribute \src "libresoc.v:97093.3-97195.6" wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:96360.3-96462.6" + attribute \src "libresoc.v:96887.3-96989.6" wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:95948.3-96050.6" + attribute \src "libresoc.v:96475.3-96577.6" wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:94712.3-94814.6" + attribute \src "libresoc.v:95239.3-95341.6" wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:94815.3-94917.6" + attribute \src "libresoc.v:95342.3-95444.6" wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:94300.3-94402.6" + attribute \src "libresoc.v:94827.3-94929.6" wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:94403.3-94505.6" + attribute \src "libresoc.v:94930.3-95032.6" wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:94506.3-94608.6" + attribute \src "libresoc.v:95033.3-95135.6" wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:94609.3-94711.6" + attribute \src "libresoc.v:95136.3-95238.6" wire width 3 $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:95021.3-95123.6" + attribute \src "libresoc.v:95548.3-95650.6" wire width 2 $1\dec31_dec_sub15_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -146531,6 +147854,7 @@ module \dec31_dec_sub15 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub15_form attribute \enum_base_type "Function" @@ -146754,28 +148078,28 @@ module \dec31_dec_sub15 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub15_upd - attribute \src "libresoc.v:93657.7-93657.15" + attribute \src "libresoc.v:94183.7-94183.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:93657.7-93657.20" - process $proc$libresoc.v:93657$3930 + attribute \src "libresoc.v:94183.7-94183.20" + process $proc$libresoc.v:94183$3984 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:93991.3-94093.6" - process $proc$libresoc.v:93991$3898 + attribute \src "libresoc.v:94518.3-94620.6" + process $proc$libresoc.v:94518$3952 assign { } { } assign { } { } assign $0\dec31_dec_sub15_function_unit[12:0] $1\dec31_dec_sub15_function_unit[12:0] - attribute \src "libresoc.v:93992.5-93992.29" + attribute \src "libresoc.v:94519.5-94519.29" switch \initial - attribute \src "libresoc.v:93992.9-93992.17" + attribute \src "libresoc.v:94519.9-94519.17" case 1'1 case end @@ -146915,14 +148239,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[12:0] end - attribute \src "libresoc.v:94094.3-94196.6" - process $proc$libresoc.v:94094$3899 + attribute \src "libresoc.v:94621.3-94723.6" + process $proc$libresoc.v:94621$3953 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:94095.5-94095.29" + attribute \src "libresoc.v:94622.5-94622.29" switch \initial - attribute \src "libresoc.v:94095.9-94095.17" + attribute \src "libresoc.v:94622.9-94622.17" case 1'1 case end @@ -147062,14 +148386,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:94197.3-94299.6" - process $proc$libresoc.v:94197$3900 + attribute \src "libresoc.v:94724.3-94826.6" + process $proc$libresoc.v:94724$3954 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:94198.5-94198.29" + attribute \src "libresoc.v:94725.5-94725.29" switch \initial - attribute \src "libresoc.v:94198.9-94198.17" + attribute \src "libresoc.v:94725.9-94725.17" case 1'1 case end @@ -147209,14 +148533,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:94300.3-94402.6" - process $proc$libresoc.v:94300$3901 + attribute \src "libresoc.v:94827.3-94929.6" + process $proc$libresoc.v:94827$3955 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:94301.5-94301.29" + attribute \src "libresoc.v:94828.5-94828.29" switch \initial - attribute \src "libresoc.v:94301.9-94301.17" + attribute \src "libresoc.v:94828.9-94828.17" case 1'1 case end @@ -147356,14 +148680,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] end - attribute \src "libresoc.v:94403.3-94505.6" - process $proc$libresoc.v:94403$3902 + attribute \src "libresoc.v:94930.3-95032.6" + process $proc$libresoc.v:94930$3956 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:94404.5-94404.29" + attribute \src "libresoc.v:94931.5-94931.29" switch \initial - attribute \src "libresoc.v:94404.9-94404.17" + attribute \src "libresoc.v:94931.9-94931.17" case 1'1 case end @@ -147503,14 +148827,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] end - attribute \src "libresoc.v:94506.3-94608.6" - process $proc$libresoc.v:94506$3903 + attribute \src "libresoc.v:95033.3-95135.6" + process $proc$libresoc.v:95033$3957 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:94507.5-94507.29" + attribute \src "libresoc.v:95034.5-95034.29" switch \initial - attribute \src "libresoc.v:94507.9-94507.17" + attribute \src "libresoc.v:95034.9-95034.17" case 1'1 case end @@ -147650,14 +148974,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] end - attribute \src "libresoc.v:94609.3-94711.6" - process $proc$libresoc.v:94609$3904 + attribute \src "libresoc.v:95136.3-95238.6" + process $proc$libresoc.v:95136$3958 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:94610.5-94610.29" + attribute \src "libresoc.v:95137.5-95137.29" switch \initial - attribute \src "libresoc.v:94610.9-94610.17" + attribute \src "libresoc.v:95137.9-95137.17" case 1'1 case end @@ -147797,14 +149121,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] end - attribute \src "libresoc.v:94712.3-94814.6" - process $proc$libresoc.v:94712$3905 + attribute \src "libresoc.v:95239.3-95341.6" + process $proc$libresoc.v:95239$3959 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:94713.5-94713.29" + attribute \src "libresoc.v:95240.5-95240.29" switch \initial - attribute \src "libresoc.v:94713.9-94713.17" + attribute \src "libresoc.v:95240.9-95240.17" case 1'1 case end @@ -147944,14 +149268,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] end - attribute \src "libresoc.v:94815.3-94917.6" - process $proc$libresoc.v:94815$3906 + attribute \src "libresoc.v:95342.3-95444.6" + process $proc$libresoc.v:95342$3960 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:94816.5-94816.29" + attribute \src "libresoc.v:95343.5-95343.29" switch \initial - attribute \src "libresoc.v:94816.9-94816.17" + attribute \src "libresoc.v:95343.9-95343.17" case 1'1 case end @@ -148091,14 +149415,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] end - attribute \src "libresoc.v:94918.3-95020.6" - process $proc$libresoc.v:94918$3907 + attribute \src "libresoc.v:95445.3-95547.6" + process $proc$libresoc.v:95445$3961 assign { } { } assign { } { } assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:94919.5-94919.29" + attribute \src "libresoc.v:95446.5-95446.29" switch \initial - attribute \src "libresoc.v:94919.9-94919.17" + attribute \src "libresoc.v:95446.9-95446.17" case 1'1 case end @@ -148238,14 +149562,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "libresoc.v:95021.3-95123.6" - process $proc$libresoc.v:95021$3908 + attribute \src "libresoc.v:95548.3-95650.6" + process $proc$libresoc.v:95548$3962 assign { } { } assign { } { } assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:95022.5-95022.29" + attribute \src "libresoc.v:95549.5-95549.29" switch \initial - attribute \src "libresoc.v:95022.9-95022.17" + attribute \src "libresoc.v:95549.9-95549.17" case 1'1 case end @@ -148385,14 +149709,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "libresoc.v:95124.3-95226.6" - process $proc$libresoc.v:95124$3909 + attribute \src "libresoc.v:95651.3-95753.6" + process $proc$libresoc.v:95651$3963 assign { } { } assign { } { } assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:95125.5-95125.29" + attribute \src "libresoc.v:95652.5-95652.29" switch \initial - attribute \src "libresoc.v:95125.9-95125.17" + attribute \src "libresoc.v:95652.9-95652.17" case 1'1 case end @@ -148532,14 +149856,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:95227.3-95329.6" - process $proc$libresoc.v:95227$3910 + attribute \src "libresoc.v:95754.3-95856.6" + process $proc$libresoc.v:95754$3964 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:95228.5-95228.29" + attribute \src "libresoc.v:95755.5-95755.29" switch \initial - attribute \src "libresoc.v:95228.9-95228.17" + attribute \src "libresoc.v:95755.9-95755.17" case 1'1 case end @@ -148679,14 +150003,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "libresoc.v:95330.3-95432.6" - process $proc$libresoc.v:95330$3911 + attribute \src "libresoc.v:95857.3-95959.6" + process $proc$libresoc.v:95857$3965 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:95331.5-95331.29" + attribute \src "libresoc.v:95858.5-95858.29" switch \initial - attribute \src "libresoc.v:95331.9-95331.17" + attribute \src "libresoc.v:95858.9-95858.17" case 1'1 case end @@ -148826,14 +150150,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "libresoc.v:95433.3-95535.6" - process $proc$libresoc.v:95433$3912 + attribute \src "libresoc.v:95960.3-96062.6" + process $proc$libresoc.v:95960$3966 assign { } { } assign { } { } assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:95434.5-95434.29" + attribute \src "libresoc.v:95961.5-95961.29" switch \initial - attribute \src "libresoc.v:95434.9-95434.17" + attribute \src "libresoc.v:95961.9-95961.17" case 1'1 case end @@ -148973,14 +150297,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "libresoc.v:95536.3-95638.6" - process $proc$libresoc.v:95536$3913 + attribute \src "libresoc.v:96063.3-96165.6" + process $proc$libresoc.v:96063$3967 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:95537.5-95537.29" + attribute \src "libresoc.v:96064.5-96064.29" switch \initial - attribute \src "libresoc.v:95537.9-95537.17" + attribute \src "libresoc.v:96064.9-96064.17" case 1'1 case end @@ -149120,14 +150444,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "libresoc.v:95639.3-95741.6" - process $proc$libresoc.v:95639$3914 + attribute \src "libresoc.v:96166.3-96268.6" + process $proc$libresoc.v:96166$3968 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:95640.5-95640.29" + attribute \src "libresoc.v:96167.5-96167.29" switch \initial - attribute \src "libresoc.v:95640.9-95640.17" + attribute \src "libresoc.v:96167.9-96167.17" case 1'1 case end @@ -149267,14 +150591,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "libresoc.v:95742.3-95844.6" - process $proc$libresoc.v:95742$3915 + attribute \src "libresoc.v:96269.3-96371.6" + process $proc$libresoc.v:96269$3969 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:95743.5-95743.29" + attribute \src "libresoc.v:96270.5-96270.29" switch \initial - attribute \src "libresoc.v:95743.9-95743.17" + attribute \src "libresoc.v:96270.9-96270.17" case 1'1 case end @@ -149414,14 +150738,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "libresoc.v:95845.3-95947.6" - process $proc$libresoc.v:95845$3916 + attribute \src "libresoc.v:96372.3-96474.6" + process $proc$libresoc.v:96372$3970 assign { } { } assign { } { } assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:95846.5-95846.29" + attribute \src "libresoc.v:96373.5-96373.29" switch \initial - attribute \src "libresoc.v:95846.9-95846.17" + attribute \src "libresoc.v:96373.9-96373.17" case 1'1 case end @@ -149561,14 +150885,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "libresoc.v:95948.3-96050.6" - process $proc$libresoc.v:95948$3917 + attribute \src "libresoc.v:96475.3-96577.6" + process $proc$libresoc.v:96475$3971 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:95949.5-95949.29" + attribute \src "libresoc.v:96476.5-96476.29" switch \initial - attribute \src "libresoc.v:95949.9-95949.17" + attribute \src "libresoc.v:96476.9-96476.17" case 1'1 case end @@ -149708,14 +151032,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "libresoc.v:96051.3-96153.6" - process $proc$libresoc.v:96051$3918 + attribute \src "libresoc.v:96578.3-96680.6" + process $proc$libresoc.v:96578$3972 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:96052.5-96052.29" + attribute \src "libresoc.v:96579.5-96579.29" switch \initial - attribute \src "libresoc.v:96052.9-96052.17" + attribute \src "libresoc.v:96579.9-96579.17" case 1'1 case end @@ -149855,14 +151179,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "libresoc.v:96154.3-96256.6" - process $proc$libresoc.v:96154$3919 + attribute \src "libresoc.v:96681.3-96783.6" + process $proc$libresoc.v:96681$3973 assign { } { } assign { } { } assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:96155.5-96155.29" + attribute \src "libresoc.v:96682.5-96682.29" switch \initial - attribute \src "libresoc.v:96155.9-96155.17" + attribute \src "libresoc.v:96682.9-96682.17" case 1'1 case end @@ -150002,14 +151326,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "libresoc.v:96257.3-96359.6" - process $proc$libresoc.v:96257$3920 + attribute \src "libresoc.v:96784.3-96886.6" + process $proc$libresoc.v:96784$3974 assign { } { } assign { } { } assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:96258.5-96258.29" + attribute \src "libresoc.v:96785.5-96785.29" switch \initial - attribute \src "libresoc.v:96258.9-96258.17" + attribute \src "libresoc.v:96785.9-96785.17" case 1'1 case end @@ -150149,14 +151473,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "libresoc.v:96360.3-96462.6" - process $proc$libresoc.v:96360$3921 + attribute \src "libresoc.v:96887.3-96989.6" + process $proc$libresoc.v:96887$3975 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:96361.5-96361.29" + attribute \src "libresoc.v:96888.5-96888.29" switch \initial - attribute \src "libresoc.v:96361.9-96361.17" + attribute \src "libresoc.v:96888.9-96888.17" case 1'1 case end @@ -150296,14 +151620,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "libresoc.v:96463.3-96565.6" - process $proc$libresoc.v:96463$3922 + attribute \src "libresoc.v:96990.3-97092.6" + process $proc$libresoc.v:96990$3976 assign { } { } assign { } { } assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:96464.5-96464.29" + attribute \src "libresoc.v:96991.5-96991.29" switch \initial - attribute \src "libresoc.v:96464.9-96464.17" + attribute \src "libresoc.v:96991.9-96991.17" case 1'1 case end @@ -150443,14 +151767,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "libresoc.v:96566.3-96668.6" - process $proc$libresoc.v:96566$3923 + attribute \src "libresoc.v:97093.3-97195.6" + process $proc$libresoc.v:97093$3977 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:96567.5-96567.29" + attribute \src "libresoc.v:97094.5-97094.29" switch \initial - attribute \src "libresoc.v:96567.9-96567.17" + attribute \src "libresoc.v:97094.9-97094.17" case 1'1 case end @@ -150590,14 +151914,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "libresoc.v:96669.3-96771.6" - process $proc$libresoc.v:96669$3924 + attribute \src "libresoc.v:97196.3-97298.6" + process $proc$libresoc.v:97196$3978 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:96670.5-96670.29" + attribute \src "libresoc.v:97197.5-97197.29" switch \initial - attribute \src "libresoc.v:96670.9-96670.17" + attribute \src "libresoc.v:97197.9-97197.17" case 1'1 case end @@ -150737,14 +152061,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] end - attribute \src "libresoc.v:96772.3-96874.6" - process $proc$libresoc.v:96772$3925 + attribute \src "libresoc.v:97299.3-97401.6" + process $proc$libresoc.v:97299$3979 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:96773.5-96773.29" + attribute \src "libresoc.v:97300.5-97300.29" switch \initial - attribute \src "libresoc.v:96773.9-96773.17" + attribute \src "libresoc.v:97300.9-97300.17" case 1'1 case end @@ -150884,14 +152208,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] end - attribute \src "libresoc.v:96875.3-96977.6" - process $proc$libresoc.v:96875$3926 + attribute \src "libresoc.v:97402.3-97504.6" + process $proc$libresoc.v:97402$3980 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:96876.5-96876.29" + attribute \src "libresoc.v:97403.5-97403.29" switch \initial - attribute \src "libresoc.v:96876.9-96876.17" + attribute \src "libresoc.v:97403.9-97403.17" case 1'1 case end @@ -151031,14 +152355,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "libresoc.v:96978.3-97080.6" - process $proc$libresoc.v:96978$3927 + attribute \src "libresoc.v:97505.3-97607.6" + process $proc$libresoc.v:97505$3981 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:96979.5-96979.29" + attribute \src "libresoc.v:97506.5-97506.29" switch \initial - attribute \src "libresoc.v:96979.9-96979.17" + attribute \src "libresoc.v:97506.9-97506.17" case 1'1 case end @@ -151178,14 +152502,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "libresoc.v:97081.3-97183.6" - process $proc$libresoc.v:97081$3928 + attribute \src "libresoc.v:97608.3-97710.6" + process $proc$libresoc.v:97608$3982 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:97082.5-97082.29" + attribute \src "libresoc.v:97609.5-97609.29" switch \initial - attribute \src "libresoc.v:97082.9-97082.17" + attribute \src "libresoc.v:97609.9-97609.17" case 1'1 case end @@ -151325,14 +152649,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "libresoc.v:97184.3-97286.6" - process $proc$libresoc.v:97184$3929 + attribute \src "libresoc.v:97711.3-97813.6" + process $proc$libresoc.v:97711$3983 assign { } { } assign { } { } assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:97185.5-97185.29" + attribute \src "libresoc.v:97712.5-97712.29" switch \initial - attribute \src "libresoc.v:97185.9-97185.17" + attribute \src "libresoc.v:97712.9-97712.17" case 1'1 case end @@ -151474,140 +152798,140 @@ module \dec31_dec_sub15 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:97292.1-97948.10" +attribute \src "libresoc.v:97819.1-98476.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" module \dec31_dec_sub16 - attribute \src "libresoc.v:97887.3-97896.6" + attribute \src "libresoc.v:98415.3-98424.6" wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:97897.3-97906.6" + attribute \src "libresoc.v:98425.3-98434.6" wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:97767.3-97776.6" + attribute \src "libresoc.v:98295.3-98304.6" wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:97807.3-97816.6" + attribute \src "libresoc.v:98335.3-98344.6" wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:97637.3-97646.6" + attribute \src "libresoc.v:98165.3-98174.6" wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:97647.3-97656.6" + attribute \src "libresoc.v:98175.3-98184.6" wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:97757.3-97766.6" + attribute \src "libresoc.v:98285.3-98294.6" wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:97797.3-97806.6" + attribute \src "libresoc.v:98325.3-98334.6" wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:97847.3-97856.6" + attribute \src "libresoc.v:98375.3-98384.6" wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:97627.3-97636.6" + attribute \src "libresoc.v:98155.3-98164.6" wire width 13 $0\dec31_dec_sub16_function_unit[12:0] - attribute \src "libresoc.v:97907.3-97916.6" + attribute \src "libresoc.v:98435.3-98444.6" wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:97917.3-97926.6" + attribute \src "libresoc.v:98445.3-98454.6" wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:97927.3-97936.6" + attribute \src "libresoc.v:98455.3-98464.6" wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:97737.3-97746.6" + attribute \src "libresoc.v:98265.3-98274.6" wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:97777.3-97786.6" + attribute \src "libresoc.v:98305.3-98314.6" wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:97787.3-97796.6" + attribute \src "libresoc.v:98315.3-98324.6" wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:97837.3-97846.6" + attribute \src "libresoc.v:98365.3-98374.6" wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:97717.3-97726.6" + attribute \src "libresoc.v:98245.3-98254.6" wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:97867.3-97876.6" + attribute \src "libresoc.v:98395.3-98404.6" wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:97937.3-97946.6" + attribute \src "libresoc.v:98465.3-98474.6" wire width 2 $0\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:97747.3-97756.6" + attribute \src "libresoc.v:98275.3-98284.6" wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:97827.3-97836.6" + attribute \src "libresoc.v:98355.3-98364.6" wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:97877.3-97886.6" + attribute \src "libresoc.v:98405.3-98414.6" wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:97857.3-97866.6" + attribute \src "libresoc.v:98385.3-98394.6" wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:97817.3-97826.6" + attribute \src "libresoc.v:98345.3-98354.6" wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:97697.3-97706.6" + attribute \src "libresoc.v:98225.3-98234.6" wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:97707.3-97716.6" + attribute \src "libresoc.v:98235.3-98244.6" wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:97657.3-97666.6" + attribute \src "libresoc.v:98185.3-98194.6" wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:97667.3-97676.6" + attribute \src "libresoc.v:98195.3-98204.6" wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:97677.3-97686.6" + attribute \src "libresoc.v:98205.3-98214.6" wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:97687.3-97696.6" + attribute \src "libresoc.v:98215.3-98224.6" wire width 3 $0\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:97727.3-97736.6" + attribute \src "libresoc.v:98255.3-98264.6" wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:97293.7-97293.20" + attribute \src "libresoc.v:97820.7-97820.20" wire $0\initial[0:0] - attribute \src "libresoc.v:97887.3-97896.6" + attribute \src "libresoc.v:98415.3-98424.6" wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:97897.3-97906.6" + attribute \src "libresoc.v:98425.3-98434.6" wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:97767.3-97776.6" + attribute \src "libresoc.v:98295.3-98304.6" wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:97807.3-97816.6" + attribute \src "libresoc.v:98335.3-98344.6" wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:97637.3-97646.6" + attribute \src "libresoc.v:98165.3-98174.6" wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:97647.3-97656.6" + attribute \src "libresoc.v:98175.3-98184.6" wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:97757.3-97766.6" + attribute \src "libresoc.v:98285.3-98294.6" wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:97797.3-97806.6" + attribute \src "libresoc.v:98325.3-98334.6" wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:97847.3-97856.6" + attribute \src "libresoc.v:98375.3-98384.6" wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:97627.3-97636.6" + attribute \src "libresoc.v:98155.3-98164.6" wire width 13 $1\dec31_dec_sub16_function_unit[12:0] - attribute \src "libresoc.v:97907.3-97916.6" + attribute \src "libresoc.v:98435.3-98444.6" wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:97917.3-97926.6" + attribute \src "libresoc.v:98445.3-98454.6" wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:97927.3-97936.6" + attribute \src "libresoc.v:98455.3-98464.6" wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:97737.3-97746.6" + attribute \src "libresoc.v:98265.3-98274.6" wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:97777.3-97786.6" + attribute \src "libresoc.v:98305.3-98314.6" wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:97787.3-97796.6" + attribute \src "libresoc.v:98315.3-98324.6" wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:97837.3-97846.6" + attribute \src "libresoc.v:98365.3-98374.6" wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:97717.3-97726.6" + attribute \src "libresoc.v:98245.3-98254.6" wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:97867.3-97876.6" + attribute \src "libresoc.v:98395.3-98404.6" wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:97937.3-97946.6" + attribute \src "libresoc.v:98465.3-98474.6" wire width 2 $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:97747.3-97756.6" + attribute \src "libresoc.v:98275.3-98284.6" wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:97827.3-97836.6" + attribute \src "libresoc.v:98355.3-98364.6" wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:97877.3-97886.6" + attribute \src "libresoc.v:98405.3-98414.6" wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:97857.3-97866.6" + attribute \src "libresoc.v:98385.3-98394.6" wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:97817.3-97826.6" + attribute \src "libresoc.v:98345.3-98354.6" wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:97697.3-97706.6" + attribute \src "libresoc.v:98225.3-98234.6" wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:97707.3-97716.6" + attribute \src "libresoc.v:98235.3-98244.6" wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:97657.3-97666.6" + attribute \src "libresoc.v:98185.3-98194.6" wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:97667.3-97676.6" + attribute \src "libresoc.v:98195.3-98204.6" wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:97677.3-97686.6" + attribute \src "libresoc.v:98205.3-98214.6" wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:97687.3-97696.6" + attribute \src "libresoc.v:98215.3-98224.6" wire width 3 $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:97727.3-97736.6" + attribute \src "libresoc.v:98255.3-98264.6" wire width 2 $1\dec31_dec_sub16_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -151683,6 +153007,7 @@ module \dec31_dec_sub16 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub16_form attribute \enum_base_type "Function" @@ -151906,28 +153231,28 @@ module \dec31_dec_sub16 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub16_upd - attribute \src "libresoc.v:97293.7-97293.15" + attribute \src "libresoc.v:97820.7-97820.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:97293.7-97293.20" - process $proc$libresoc.v:97293$3963 + attribute \src "libresoc.v:97820.7-97820.20" + process $proc$libresoc.v:97820$4017 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:97627.3-97636.6" - process $proc$libresoc.v:97627$3931 + attribute \src "libresoc.v:98155.3-98164.6" + process $proc$libresoc.v:98155$3985 assign { } { } assign { } { } assign $0\dec31_dec_sub16_function_unit[12:0] $1\dec31_dec_sub16_function_unit[12:0] - attribute \src "libresoc.v:97628.5-97628.29" + attribute \src "libresoc.v:98156.5-98156.29" switch \initial - attribute \src "libresoc.v:97628.9-97628.17" + attribute \src "libresoc.v:98156.9-98156.17" case 1'1 case end @@ -151943,14 +153268,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[12:0] end - attribute \src "libresoc.v:97637.3-97646.6" - process $proc$libresoc.v:97637$3932 + attribute \src "libresoc.v:98165.3-98174.6" + process $proc$libresoc.v:98165$3986 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:97638.5-97638.29" + attribute \src "libresoc.v:98166.5-98166.29" switch \initial - attribute \src "libresoc.v:97638.9-97638.17" + attribute \src "libresoc.v:98166.9-98166.17" case 1'1 case end @@ -151966,14 +153291,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:97647.3-97656.6" - process $proc$libresoc.v:97647$3933 + attribute \src "libresoc.v:98175.3-98184.6" + process $proc$libresoc.v:98175$3987 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:97648.5-97648.29" + attribute \src "libresoc.v:98176.5-98176.29" switch \initial - attribute \src "libresoc.v:97648.9-97648.17" + attribute \src "libresoc.v:98176.9-98176.17" case 1'1 case end @@ -151989,14 +153314,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] end - attribute \src "libresoc.v:97657.3-97666.6" - process $proc$libresoc.v:97657$3934 + attribute \src "libresoc.v:98185.3-98194.6" + process $proc$libresoc.v:98185$3988 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:97658.5-97658.29" + attribute \src "libresoc.v:98186.5-98186.29" switch \initial - attribute \src "libresoc.v:97658.9-97658.17" + attribute \src "libresoc.v:98186.9-98186.17" case 1'1 case end @@ -152012,14 +153337,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] end - attribute \src "libresoc.v:97667.3-97676.6" - process $proc$libresoc.v:97667$3935 + attribute \src "libresoc.v:98195.3-98204.6" + process $proc$libresoc.v:98195$3989 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:97668.5-97668.29" + attribute \src "libresoc.v:98196.5-98196.29" switch \initial - attribute \src "libresoc.v:97668.9-97668.17" + attribute \src "libresoc.v:98196.9-98196.17" case 1'1 case end @@ -152035,14 +153360,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] end - attribute \src "libresoc.v:97677.3-97686.6" - process $proc$libresoc.v:97677$3936 + attribute \src "libresoc.v:98205.3-98214.6" + process $proc$libresoc.v:98205$3990 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:97678.5-97678.29" + attribute \src "libresoc.v:98206.5-98206.29" switch \initial - attribute \src "libresoc.v:97678.9-97678.17" + attribute \src "libresoc.v:98206.9-98206.17" case 1'1 case end @@ -152058,14 +153383,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] end - attribute \src "libresoc.v:97687.3-97696.6" - process $proc$libresoc.v:97687$3937 + attribute \src "libresoc.v:98215.3-98224.6" + process $proc$libresoc.v:98215$3991 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:97688.5-97688.29" + attribute \src "libresoc.v:98216.5-98216.29" switch \initial - attribute \src "libresoc.v:97688.9-97688.17" + attribute \src "libresoc.v:98216.9-98216.17" case 1'1 case end @@ -152081,14 +153406,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] end - attribute \src "libresoc.v:97697.3-97706.6" - process $proc$libresoc.v:97697$3938 + attribute \src "libresoc.v:98225.3-98234.6" + process $proc$libresoc.v:98225$3992 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:97698.5-97698.29" + attribute \src "libresoc.v:98226.5-98226.29" switch \initial - attribute \src "libresoc.v:97698.9-97698.17" + attribute \src "libresoc.v:98226.9-98226.17" case 1'1 case end @@ -152104,14 +153429,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] end - attribute \src "libresoc.v:97707.3-97716.6" - process $proc$libresoc.v:97707$3939 + attribute \src "libresoc.v:98235.3-98244.6" + process $proc$libresoc.v:98235$3993 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:97708.5-97708.29" + attribute \src "libresoc.v:98236.5-98236.29" switch \initial - attribute \src "libresoc.v:97708.9-97708.17" + attribute \src "libresoc.v:98236.9-98236.17" case 1'1 case end @@ -152127,14 +153452,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] end - attribute \src "libresoc.v:97717.3-97726.6" - process $proc$libresoc.v:97717$3940 + attribute \src "libresoc.v:98245.3-98254.6" + process $proc$libresoc.v:98245$3994 assign { } { } assign { } { } assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:97718.5-97718.29" + attribute \src "libresoc.v:98246.5-98246.29" switch \initial - attribute \src "libresoc.v:97718.9-97718.17" + attribute \src "libresoc.v:98246.9-98246.17" case 1'1 case end @@ -152150,14 +153475,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end - attribute \src "libresoc.v:97727.3-97736.6" - process $proc$libresoc.v:97727$3941 + attribute \src "libresoc.v:98255.3-98264.6" + process $proc$libresoc.v:98255$3995 assign { } { } assign { } { } assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:97728.5-97728.29" + attribute \src "libresoc.v:98256.5-98256.29" switch \initial - attribute \src "libresoc.v:97728.9-97728.17" + attribute \src "libresoc.v:98256.9-98256.17" case 1'1 case end @@ -152173,14 +153498,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end - attribute \src "libresoc.v:97737.3-97746.6" - process $proc$libresoc.v:97737$3942 + attribute \src "libresoc.v:98265.3-98274.6" + process $proc$libresoc.v:98265$3996 assign { } { } assign { } { } assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:97738.5-97738.29" + attribute \src "libresoc.v:98266.5-98266.29" switch \initial - attribute \src "libresoc.v:97738.9-97738.17" + attribute \src "libresoc.v:98266.9-98266.17" case 1'1 case end @@ -152196,14 +153521,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:97747.3-97756.6" - process $proc$libresoc.v:97747$3943 + attribute \src "libresoc.v:98275.3-98284.6" + process $proc$libresoc.v:98275$3997 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:97748.5-97748.29" + attribute \src "libresoc.v:98276.5-98276.29" switch \initial - attribute \src "libresoc.v:97748.9-97748.17" + attribute \src "libresoc.v:98276.9-98276.17" case 1'1 case end @@ -152219,14 +153544,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end - attribute \src "libresoc.v:97757.3-97766.6" - process $proc$libresoc.v:97757$3944 + attribute \src "libresoc.v:98285.3-98294.6" + process $proc$libresoc.v:98285$3998 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:97758.5-97758.29" + attribute \src "libresoc.v:98286.5-98286.29" switch \initial - attribute \src "libresoc.v:97758.9-97758.17" + attribute \src "libresoc.v:98286.9-98286.17" case 1'1 case end @@ -152242,14 +153567,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end - attribute \src "libresoc.v:97767.3-97776.6" - process $proc$libresoc.v:97767$3945 + attribute \src "libresoc.v:98295.3-98304.6" + process $proc$libresoc.v:98295$3999 assign { } { } assign { } { } assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:97768.5-97768.29" + attribute \src "libresoc.v:98296.5-98296.29" switch \initial - attribute \src "libresoc.v:97768.9-97768.17" + attribute \src "libresoc.v:98296.9-98296.17" case 1'1 case end @@ -152265,14 +153590,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end - attribute \src "libresoc.v:97777.3-97786.6" - process $proc$libresoc.v:97777$3946 + attribute \src "libresoc.v:98305.3-98314.6" + process $proc$libresoc.v:98305$4000 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:97778.5-97778.29" + attribute \src "libresoc.v:98306.5-98306.29" switch \initial - attribute \src "libresoc.v:97778.9-97778.17" + attribute \src "libresoc.v:98306.9-98306.17" case 1'1 case end @@ -152288,14 +153613,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end - attribute \src "libresoc.v:97787.3-97796.6" - process $proc$libresoc.v:97787$3947 + attribute \src "libresoc.v:98315.3-98324.6" + process $proc$libresoc.v:98315$4001 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:97788.5-97788.29" + attribute \src "libresoc.v:98316.5-98316.29" switch \initial - attribute \src "libresoc.v:97788.9-97788.17" + attribute \src "libresoc.v:98316.9-98316.17" case 1'1 case end @@ -152311,14 +153636,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end - attribute \src "libresoc.v:97797.3-97806.6" - process $proc$libresoc.v:97797$3948 + attribute \src "libresoc.v:98325.3-98334.6" + process $proc$libresoc.v:98325$4002 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:97798.5-97798.29" + attribute \src "libresoc.v:98326.5-98326.29" switch \initial - attribute \src "libresoc.v:97798.9-97798.17" + attribute \src "libresoc.v:98326.9-98326.17" case 1'1 case end @@ -152334,14 +153659,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end - attribute \src "libresoc.v:97807.3-97816.6" - process $proc$libresoc.v:97807$3949 + attribute \src "libresoc.v:98335.3-98344.6" + process $proc$libresoc.v:98335$4003 assign { } { } assign { } { } assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:97808.5-97808.29" + attribute \src "libresoc.v:98336.5-98336.29" switch \initial - attribute \src "libresoc.v:97808.9-97808.17" + attribute \src "libresoc.v:98336.9-98336.17" case 1'1 case end @@ -152357,14 +153682,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end - attribute \src "libresoc.v:97817.3-97826.6" - process $proc$libresoc.v:97817$3950 + attribute \src "libresoc.v:98345.3-98354.6" + process $proc$libresoc.v:98345$4004 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:97818.5-97818.29" + attribute \src "libresoc.v:98346.5-98346.29" switch \initial - attribute \src "libresoc.v:97818.9-97818.17" + attribute \src "libresoc.v:98346.9-98346.17" case 1'1 case end @@ -152380,14 +153705,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end - attribute \src "libresoc.v:97827.3-97836.6" - process $proc$libresoc.v:97827$3951 + attribute \src "libresoc.v:98355.3-98364.6" + process $proc$libresoc.v:98355$4005 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:97828.5-97828.29" + attribute \src "libresoc.v:98356.5-98356.29" switch \initial - attribute \src "libresoc.v:97828.9-97828.17" + attribute \src "libresoc.v:98356.9-98356.17" case 1'1 case end @@ -152403,14 +153728,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end - attribute \src "libresoc.v:97837.3-97846.6" - process $proc$libresoc.v:97837$3952 + attribute \src "libresoc.v:98365.3-98374.6" + process $proc$libresoc.v:98365$4006 assign { } { } assign { } { } assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:97838.5-97838.29" + attribute \src "libresoc.v:98366.5-98366.29" switch \initial - attribute \src "libresoc.v:97838.9-97838.17" + attribute \src "libresoc.v:98366.9-98366.17" case 1'1 case end @@ -152426,14 +153751,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] end - attribute \src "libresoc.v:97847.3-97856.6" - process $proc$libresoc.v:97847$3953 + attribute \src "libresoc.v:98375.3-98384.6" + process $proc$libresoc.v:98375$4007 assign { } { } assign { } { } assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:97848.5-97848.29" + attribute \src "libresoc.v:98376.5-98376.29" switch \initial - attribute \src "libresoc.v:97848.9-97848.17" + attribute \src "libresoc.v:98376.9-98376.17" case 1'1 case end @@ -152449,14 +153774,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] end - attribute \src "libresoc.v:97857.3-97866.6" - process $proc$libresoc.v:97857$3954 + attribute \src "libresoc.v:98385.3-98394.6" + process $proc$libresoc.v:98385$4008 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:97858.5-97858.29" + attribute \src "libresoc.v:98386.5-98386.29" switch \initial - attribute \src "libresoc.v:97858.9-97858.17" + attribute \src "libresoc.v:98386.9-98386.17" case 1'1 case end @@ -152472,14 +153797,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end - attribute \src "libresoc.v:97867.3-97876.6" - process $proc$libresoc.v:97867$3955 + attribute \src "libresoc.v:98395.3-98404.6" + process $proc$libresoc.v:98395$4009 assign { } { } assign { } { } assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:97868.5-97868.29" + attribute \src "libresoc.v:98396.5-98396.29" switch \initial - attribute \src "libresoc.v:97868.9-97868.17" + attribute \src "libresoc.v:98396.9-98396.17" case 1'1 case end @@ -152495,14 +153820,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] end - attribute \src "libresoc.v:97877.3-97886.6" - process $proc$libresoc.v:97877$3956 + attribute \src "libresoc.v:98405.3-98414.6" + process $proc$libresoc.v:98405$4010 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:97878.5-97878.29" + attribute \src "libresoc.v:98406.5-98406.29" switch \initial - attribute \src "libresoc.v:97878.9-97878.17" + attribute \src "libresoc.v:98406.9-98406.17" case 1'1 case end @@ -152518,14 +153843,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] end - attribute \src "libresoc.v:97887.3-97896.6" - process $proc$libresoc.v:97887$3957 + attribute \src "libresoc.v:98415.3-98424.6" + process $proc$libresoc.v:98415$4011 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:97888.5-97888.29" + attribute \src "libresoc.v:98416.5-98416.29" switch \initial - attribute \src "libresoc.v:97888.9-97888.17" + attribute \src "libresoc.v:98416.9-98416.17" case 1'1 case end @@ -152541,14 +153866,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] end - attribute \src "libresoc.v:97897.3-97906.6" - process $proc$libresoc.v:97897$3958 + attribute \src "libresoc.v:98425.3-98434.6" + process $proc$libresoc.v:98425$4012 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:97898.5-97898.29" + attribute \src "libresoc.v:98426.5-98426.29" switch \initial - attribute \src "libresoc.v:97898.9-97898.17" + attribute \src "libresoc.v:98426.9-98426.17" case 1'1 case end @@ -152564,14 +153889,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] end - attribute \src "libresoc.v:97907.3-97916.6" - process $proc$libresoc.v:97907$3959 + attribute \src "libresoc.v:98435.3-98444.6" + process $proc$libresoc.v:98435$4013 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:97908.5-97908.29" + attribute \src "libresoc.v:98436.5-98436.29" switch \initial - attribute \src "libresoc.v:97908.9-97908.17" + attribute \src "libresoc.v:98436.9-98436.17" case 1'1 case end @@ -152587,14 +153912,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] end - attribute \src "libresoc.v:97917.3-97926.6" - process $proc$libresoc.v:97917$3960 + attribute \src "libresoc.v:98445.3-98454.6" + process $proc$libresoc.v:98445$4014 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:97918.5-97918.29" + attribute \src "libresoc.v:98446.5-98446.29" switch \initial - attribute \src "libresoc.v:97918.9-97918.17" + attribute \src "libresoc.v:98446.9-98446.17" case 1'1 case end @@ -152610,14 +153935,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] end - attribute \src "libresoc.v:97927.3-97936.6" - process $proc$libresoc.v:97927$3961 + attribute \src "libresoc.v:98455.3-98464.6" + process $proc$libresoc.v:98455$4015 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:97928.5-97928.29" + attribute \src "libresoc.v:98456.5-98456.29" switch \initial - attribute \src "libresoc.v:97928.9-97928.17" + attribute \src "libresoc.v:98456.9-98456.17" case 1'1 case end @@ -152633,14 +153958,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] end - attribute \src "libresoc.v:97937.3-97946.6" - process $proc$libresoc.v:97937$3962 + attribute \src "libresoc.v:98465.3-98474.6" + process $proc$libresoc.v:98465$4016 assign { } { } assign { } { } assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:97938.5-97938.29" + attribute \src "libresoc.v:98466.5-98466.29" switch \initial - attribute \src "libresoc.v:97938.9-97938.17" + attribute \src "libresoc.v:98466.9-98466.17" case 1'1 case end @@ -152658,140 +153983,140 @@ module \dec31_dec_sub16 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:97952.1-98992.10" +attribute \src "libresoc.v:98480.1-99521.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" attribute \generator "nMigen" module \dec31_dec_sub18 - attribute \src "libresoc.v:98859.3-98880.6" + attribute \src "libresoc.v:99388.3-99409.6" wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:98881.3-98902.6" + attribute \src "libresoc.v:99410.3-99431.6" wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:98595.3-98616.6" + attribute \src "libresoc.v:99124.3-99145.6" wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:98683.3-98704.6" + attribute \src "libresoc.v:99212.3-99233.6" wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:98309.3-98330.6" + attribute \src "libresoc.v:98838.3-98859.6" wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:98331.3-98352.6" + attribute \src "libresoc.v:98860.3-98881.6" wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:98573.3-98594.6" + attribute \src "libresoc.v:99102.3-99123.6" wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:98661.3-98682.6" + attribute \src "libresoc.v:99190.3-99211.6" wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:98771.3-98792.6" + attribute \src "libresoc.v:99300.3-99321.6" wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:98287.3-98308.6" + attribute \src "libresoc.v:98816.3-98837.6" wire width 13 $0\dec31_dec_sub18_function_unit[12:0] - attribute \src "libresoc.v:98903.3-98924.6" + attribute \src "libresoc.v:99432.3-99453.6" wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:98925.3-98946.6" + attribute \src "libresoc.v:99454.3-99475.6" wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:98947.3-98968.6" + attribute \src "libresoc.v:99476.3-99497.6" wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:98529.3-98550.6" + attribute \src "libresoc.v:99058.3-99079.6" wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:98617.3-98638.6" + attribute \src "libresoc.v:99146.3-99167.6" wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:98639.3-98660.6" + attribute \src "libresoc.v:99168.3-99189.6" wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:98749.3-98770.6" + attribute \src "libresoc.v:99278.3-99299.6" wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:98485.3-98506.6" + attribute \src "libresoc.v:99014.3-99035.6" wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:98815.3-98836.6" + attribute \src "libresoc.v:99344.3-99365.6" wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:98969.3-98990.6" + attribute \src "libresoc.v:99498.3-99519.6" wire width 2 $0\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:98551.3-98572.6" + attribute \src "libresoc.v:99080.3-99101.6" wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:98727.3-98748.6" + attribute \src "libresoc.v:99256.3-99277.6" wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:98837.3-98858.6" + attribute \src "libresoc.v:99366.3-99387.6" wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:98793.3-98814.6" + attribute \src "libresoc.v:99322.3-99343.6" wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:98705.3-98726.6" + attribute \src "libresoc.v:99234.3-99255.6" wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:98441.3-98462.6" + attribute \src "libresoc.v:98970.3-98991.6" wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:98463.3-98484.6" + attribute \src "libresoc.v:98992.3-99013.6" wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:98353.3-98374.6" + attribute \src "libresoc.v:98882.3-98903.6" wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:98375.3-98396.6" + attribute \src "libresoc.v:98904.3-98925.6" wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:98397.3-98418.6" + attribute \src "libresoc.v:98926.3-98947.6" wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:98419.3-98440.6" + attribute \src "libresoc.v:98948.3-98969.6" wire width 3 $0\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:98507.3-98528.6" + attribute \src "libresoc.v:99036.3-99057.6" wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:97953.7-97953.20" + attribute \src "libresoc.v:98481.7-98481.20" wire $0\initial[0:0] - attribute \src "libresoc.v:98859.3-98880.6" + attribute \src "libresoc.v:99388.3-99409.6" wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:98881.3-98902.6" + attribute \src "libresoc.v:99410.3-99431.6" wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:98595.3-98616.6" + attribute \src "libresoc.v:99124.3-99145.6" wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:98683.3-98704.6" + attribute \src "libresoc.v:99212.3-99233.6" wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:98309.3-98330.6" + attribute \src "libresoc.v:98838.3-98859.6" wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:98331.3-98352.6" + attribute \src "libresoc.v:98860.3-98881.6" wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:98573.3-98594.6" + attribute \src "libresoc.v:99102.3-99123.6" wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:98661.3-98682.6" + attribute \src "libresoc.v:99190.3-99211.6" wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:98771.3-98792.6" + attribute \src "libresoc.v:99300.3-99321.6" wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:98287.3-98308.6" + attribute \src "libresoc.v:98816.3-98837.6" wire width 13 $1\dec31_dec_sub18_function_unit[12:0] - attribute \src "libresoc.v:98903.3-98924.6" + attribute \src "libresoc.v:99432.3-99453.6" wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:98925.3-98946.6" + attribute \src "libresoc.v:99454.3-99475.6" wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:98947.3-98968.6" + attribute \src "libresoc.v:99476.3-99497.6" wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:98529.3-98550.6" + attribute \src "libresoc.v:99058.3-99079.6" wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:98617.3-98638.6" + attribute \src "libresoc.v:99146.3-99167.6" wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:98639.3-98660.6" + attribute \src "libresoc.v:99168.3-99189.6" wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:98749.3-98770.6" + attribute \src "libresoc.v:99278.3-99299.6" wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:98485.3-98506.6" + attribute \src "libresoc.v:99014.3-99035.6" wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:98815.3-98836.6" + attribute \src "libresoc.v:99344.3-99365.6" wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:98969.3-98990.6" + attribute \src "libresoc.v:99498.3-99519.6" wire width 2 $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:98551.3-98572.6" + attribute \src "libresoc.v:99080.3-99101.6" wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:98727.3-98748.6" + attribute \src "libresoc.v:99256.3-99277.6" wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:98837.3-98858.6" + attribute \src "libresoc.v:99366.3-99387.6" wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:98793.3-98814.6" + attribute \src "libresoc.v:99322.3-99343.6" wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:98705.3-98726.6" + attribute \src "libresoc.v:99234.3-99255.6" wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:98441.3-98462.6" + attribute \src "libresoc.v:98970.3-98991.6" wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:98463.3-98484.6" + attribute \src "libresoc.v:98992.3-99013.6" wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:98353.3-98374.6" + attribute \src "libresoc.v:98882.3-98903.6" wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:98375.3-98396.6" + attribute \src "libresoc.v:98904.3-98925.6" wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:98397.3-98418.6" + attribute \src "libresoc.v:98926.3-98947.6" wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:98419.3-98440.6" + attribute \src "libresoc.v:98948.3-98969.6" wire width 3 $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:98507.3-98528.6" + attribute \src "libresoc.v:99036.3-99057.6" wire width 2 $1\dec31_dec_sub18_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -152867,6 +154192,7 @@ module \dec31_dec_sub18 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub18_form attribute \enum_base_type "Function" @@ -153090,28 +154416,28 @@ module \dec31_dec_sub18 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub18_upd - attribute \src "libresoc.v:97953.7-97953.15" + attribute \src "libresoc.v:98481.7-98481.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:97953.7-97953.20" - process $proc$libresoc.v:97953$3996 + attribute \src "libresoc.v:98481.7-98481.20" + process $proc$libresoc.v:98481$4050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:98287.3-98308.6" - process $proc$libresoc.v:98287$3964 + attribute \src "libresoc.v:98816.3-98837.6" + process $proc$libresoc.v:98816$4018 assign { } { } assign { } { } assign $0\dec31_dec_sub18_function_unit[12:0] $1\dec31_dec_sub18_function_unit[12:0] - attribute \src "libresoc.v:98288.5-98288.29" + attribute \src "libresoc.v:98817.5-98817.29" switch \initial - attribute \src "libresoc.v:98288.9-98288.17" + attribute \src "libresoc.v:98817.9-98817.17" case 1'1 case end @@ -153143,14 +154469,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[12:0] end - attribute \src "libresoc.v:98309.3-98330.6" - process $proc$libresoc.v:98309$3965 + attribute \src "libresoc.v:98838.3-98859.6" + process $proc$libresoc.v:98838$4019 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:98310.5-98310.29" + attribute \src "libresoc.v:98839.5-98839.29" switch \initial - attribute \src "libresoc.v:98310.9-98310.17" + attribute \src "libresoc.v:98839.9-98839.17" case 1'1 case end @@ -153182,14 +154508,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] end - attribute \src "libresoc.v:98331.3-98352.6" - process $proc$libresoc.v:98331$3966 + attribute \src "libresoc.v:98860.3-98881.6" + process $proc$libresoc.v:98860$4020 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:98332.5-98332.29" + attribute \src "libresoc.v:98861.5-98861.29" switch \initial - attribute \src "libresoc.v:98332.9-98332.17" + attribute \src "libresoc.v:98861.9-98861.17" case 1'1 case end @@ -153221,14 +154547,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] end - attribute \src "libresoc.v:98353.3-98374.6" - process $proc$libresoc.v:98353$3967 + attribute \src "libresoc.v:98882.3-98903.6" + process $proc$libresoc.v:98882$4021 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:98354.5-98354.29" + attribute \src "libresoc.v:98883.5-98883.29" switch \initial - attribute \src "libresoc.v:98354.9-98354.17" + attribute \src "libresoc.v:98883.9-98883.17" case 1'1 case end @@ -153260,14 +154586,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] end - attribute \src "libresoc.v:98375.3-98396.6" - process $proc$libresoc.v:98375$3968 + attribute \src "libresoc.v:98904.3-98925.6" + process $proc$libresoc.v:98904$4022 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:98376.5-98376.29" + attribute \src "libresoc.v:98905.5-98905.29" switch \initial - attribute \src "libresoc.v:98376.9-98376.17" + attribute \src "libresoc.v:98905.9-98905.17" case 1'1 case end @@ -153299,14 +154625,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] end - attribute \src "libresoc.v:98397.3-98418.6" - process $proc$libresoc.v:98397$3969 + attribute \src "libresoc.v:98926.3-98947.6" + process $proc$libresoc.v:98926$4023 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:98398.5-98398.29" + attribute \src "libresoc.v:98927.5-98927.29" switch \initial - attribute \src "libresoc.v:98398.9-98398.17" + attribute \src "libresoc.v:98927.9-98927.17" case 1'1 case end @@ -153338,14 +154664,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] end - attribute \src "libresoc.v:98419.3-98440.6" - process $proc$libresoc.v:98419$3970 + attribute \src "libresoc.v:98948.3-98969.6" + process $proc$libresoc.v:98948$4024 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:98420.5-98420.29" + attribute \src "libresoc.v:98949.5-98949.29" switch \initial - attribute \src "libresoc.v:98420.9-98420.17" + attribute \src "libresoc.v:98949.9-98949.17" case 1'1 case end @@ -153377,14 +154703,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] end - attribute \src "libresoc.v:98441.3-98462.6" - process $proc$libresoc.v:98441$3971 + attribute \src "libresoc.v:98970.3-98991.6" + process $proc$libresoc.v:98970$4025 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:98442.5-98442.29" + attribute \src "libresoc.v:98971.5-98971.29" switch \initial - attribute \src "libresoc.v:98442.9-98442.17" + attribute \src "libresoc.v:98971.9-98971.17" case 1'1 case end @@ -153416,14 +154742,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] end - attribute \src "libresoc.v:98463.3-98484.6" - process $proc$libresoc.v:98463$3972 + attribute \src "libresoc.v:98992.3-99013.6" + process $proc$libresoc.v:98992$4026 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:98464.5-98464.29" + attribute \src "libresoc.v:98993.5-98993.29" switch \initial - attribute \src "libresoc.v:98464.9-98464.17" + attribute \src "libresoc.v:98993.9-98993.17" case 1'1 case end @@ -153455,14 +154781,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] end - attribute \src "libresoc.v:98485.3-98506.6" - process $proc$libresoc.v:98485$3973 + attribute \src "libresoc.v:99014.3-99035.6" + process $proc$libresoc.v:99014$4027 assign { } { } assign { } { } assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:98486.5-98486.29" + attribute \src "libresoc.v:99015.5-99015.29" switch \initial - attribute \src "libresoc.v:98486.9-98486.17" + attribute \src "libresoc.v:99015.9-99015.17" case 1'1 case end @@ -153494,14 +154820,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] end - attribute \src "libresoc.v:98507.3-98528.6" - process $proc$libresoc.v:98507$3974 + attribute \src "libresoc.v:99036.3-99057.6" + process $proc$libresoc.v:99036$4028 assign { } { } assign { } { } assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:98508.5-98508.29" + attribute \src "libresoc.v:99037.5-99037.29" switch \initial - attribute \src "libresoc.v:98508.9-98508.17" + attribute \src "libresoc.v:99037.9-99037.17" case 1'1 case end @@ -153533,14 +154859,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] end - attribute \src "libresoc.v:98529.3-98550.6" - process $proc$libresoc.v:98529$3975 + attribute \src "libresoc.v:99058.3-99079.6" + process $proc$libresoc.v:99058$4029 assign { } { } assign { } { } assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:98530.5-98530.29" + attribute \src "libresoc.v:99059.5-99059.29" switch \initial - attribute \src "libresoc.v:98530.9-98530.17" + attribute \src "libresoc.v:99059.9-99059.17" case 1'1 case end @@ -153572,14 +154898,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] end - attribute \src "libresoc.v:98551.3-98572.6" - process $proc$libresoc.v:98551$3976 + attribute \src "libresoc.v:99080.3-99101.6" + process $proc$libresoc.v:99080$4030 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:98552.5-98552.29" + attribute \src "libresoc.v:99081.5-99081.29" switch \initial - attribute \src "libresoc.v:98552.9-98552.17" + attribute \src "libresoc.v:99081.9-99081.17" case 1'1 case end @@ -153611,14 +154937,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] end - attribute \src "libresoc.v:98573.3-98594.6" - process $proc$libresoc.v:98573$3977 + attribute \src "libresoc.v:99102.3-99123.6" + process $proc$libresoc.v:99102$4031 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:98574.5-98574.29" + attribute \src "libresoc.v:99103.5-99103.29" switch \initial - attribute \src "libresoc.v:98574.9-98574.17" + attribute \src "libresoc.v:99103.9-99103.17" case 1'1 case end @@ -153650,14 +154976,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] end - attribute \src "libresoc.v:98595.3-98616.6" - process $proc$libresoc.v:98595$3978 + attribute \src "libresoc.v:99124.3-99145.6" + process $proc$libresoc.v:99124$4032 assign { } { } assign { } { } assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:98596.5-98596.29" + attribute \src "libresoc.v:99125.5-99125.29" switch \initial - attribute \src "libresoc.v:98596.9-98596.17" + attribute \src "libresoc.v:99125.9-99125.17" case 1'1 case end @@ -153689,14 +155015,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end - attribute \src "libresoc.v:98617.3-98638.6" - process $proc$libresoc.v:98617$3979 + attribute \src "libresoc.v:99146.3-99167.6" + process $proc$libresoc.v:99146$4033 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:98618.5-98618.29" + attribute \src "libresoc.v:99147.5-99147.29" switch \initial - attribute \src "libresoc.v:98618.9-98618.17" + attribute \src "libresoc.v:99147.9-99147.17" case 1'1 case end @@ -153728,14 +155054,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end - attribute \src "libresoc.v:98639.3-98660.6" - process $proc$libresoc.v:98639$3980 + attribute \src "libresoc.v:99168.3-99189.6" + process $proc$libresoc.v:99168$4034 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:98640.5-98640.29" + attribute \src "libresoc.v:99169.5-99169.29" switch \initial - attribute \src "libresoc.v:98640.9-98640.17" + attribute \src "libresoc.v:99169.9-99169.17" case 1'1 case end @@ -153767,14 +155093,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end - attribute \src "libresoc.v:98661.3-98682.6" - process $proc$libresoc.v:98661$3981 + attribute \src "libresoc.v:99190.3-99211.6" + process $proc$libresoc.v:99190$4035 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:98662.5-98662.29" + attribute \src "libresoc.v:99191.5-99191.29" switch \initial - attribute \src "libresoc.v:98662.9-98662.17" + attribute \src "libresoc.v:99191.9-99191.17" case 1'1 case end @@ -153806,14 +155132,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end - attribute \src "libresoc.v:98683.3-98704.6" - process $proc$libresoc.v:98683$3982 + attribute \src "libresoc.v:99212.3-99233.6" + process $proc$libresoc.v:99212$4036 assign { } { } assign { } { } assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:98684.5-98684.29" + attribute \src "libresoc.v:99213.5-99213.29" switch \initial - attribute \src "libresoc.v:98684.9-98684.17" + attribute \src "libresoc.v:99213.9-99213.17" case 1'1 case end @@ -153845,14 +155171,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end - attribute \src "libresoc.v:98705.3-98726.6" - process $proc$libresoc.v:98705$3983 + attribute \src "libresoc.v:99234.3-99255.6" + process $proc$libresoc.v:99234$4037 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:98706.5-98706.29" + attribute \src "libresoc.v:99235.5-99235.29" switch \initial - attribute \src "libresoc.v:98706.9-98706.17" + attribute \src "libresoc.v:99235.9-99235.17" case 1'1 case end @@ -153884,14 +155210,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end - attribute \src "libresoc.v:98727.3-98748.6" - process $proc$libresoc.v:98727$3984 + attribute \src "libresoc.v:99256.3-99277.6" + process $proc$libresoc.v:99256$4038 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:98728.5-98728.29" + attribute \src "libresoc.v:99257.5-99257.29" switch \initial - attribute \src "libresoc.v:98728.9-98728.17" + attribute \src "libresoc.v:99257.9-99257.17" case 1'1 case end @@ -153923,14 +155249,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end - attribute \src "libresoc.v:98749.3-98770.6" - process $proc$libresoc.v:98749$3985 + attribute \src "libresoc.v:99278.3-99299.6" + process $proc$libresoc.v:99278$4039 assign { } { } assign { } { } assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:98750.5-98750.29" + attribute \src "libresoc.v:99279.5-99279.29" switch \initial - attribute \src "libresoc.v:98750.9-98750.17" + attribute \src "libresoc.v:99279.9-99279.17" case 1'1 case end @@ -153962,14 +155288,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] end - attribute \src "libresoc.v:98771.3-98792.6" - process $proc$libresoc.v:98771$3986 + attribute \src "libresoc.v:99300.3-99321.6" + process $proc$libresoc.v:99300$4040 assign { } { } assign { } { } assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:98772.5-98772.29" + attribute \src "libresoc.v:99301.5-99301.29" switch \initial - attribute \src "libresoc.v:98772.9-98772.17" + attribute \src "libresoc.v:99301.9-99301.17" case 1'1 case end @@ -154001,14 +155327,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end - attribute \src "libresoc.v:98793.3-98814.6" - process $proc$libresoc.v:98793$3987 + attribute \src "libresoc.v:99322.3-99343.6" + process $proc$libresoc.v:99322$4041 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:98794.5-98794.29" + attribute \src "libresoc.v:99323.5-99323.29" switch \initial - attribute \src "libresoc.v:98794.9-98794.17" + attribute \src "libresoc.v:99323.9-99323.17" case 1'1 case end @@ -154040,14 +155366,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] end - attribute \src "libresoc.v:98815.3-98836.6" - process $proc$libresoc.v:98815$3988 + attribute \src "libresoc.v:99344.3-99365.6" + process $proc$libresoc.v:99344$4042 assign { } { } assign { } { } assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:98816.5-98816.29" + attribute \src "libresoc.v:99345.5-99345.29" switch \initial - attribute \src "libresoc.v:98816.9-98816.17" + attribute \src "libresoc.v:99345.9-99345.17" case 1'1 case end @@ -154079,14 +155405,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end - attribute \src "libresoc.v:98837.3-98858.6" - process $proc$libresoc.v:98837$3989 + attribute \src "libresoc.v:99366.3-99387.6" + process $proc$libresoc.v:99366$4043 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:98838.5-98838.29" + attribute \src "libresoc.v:99367.5-99367.29" switch \initial - attribute \src "libresoc.v:98838.9-98838.17" + attribute \src "libresoc.v:99367.9-99367.17" case 1'1 case end @@ -154118,14 +155444,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] end - attribute \src "libresoc.v:98859.3-98880.6" - process $proc$libresoc.v:98859$3990 + attribute \src "libresoc.v:99388.3-99409.6" + process $proc$libresoc.v:99388$4044 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:98860.5-98860.29" + attribute \src "libresoc.v:99389.5-99389.29" switch \initial - attribute \src "libresoc.v:98860.9-98860.17" + attribute \src "libresoc.v:99389.9-99389.17" case 1'1 case end @@ -154157,14 +155483,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] end - attribute \src "libresoc.v:98881.3-98902.6" - process $proc$libresoc.v:98881$3991 + attribute \src "libresoc.v:99410.3-99431.6" + process $proc$libresoc.v:99410$4045 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:98882.5-98882.29" + attribute \src "libresoc.v:99411.5-99411.29" switch \initial - attribute \src "libresoc.v:98882.9-98882.17" + attribute \src "libresoc.v:99411.9-99411.17" case 1'1 case end @@ -154196,14 +155522,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] end - attribute \src "libresoc.v:98903.3-98924.6" - process $proc$libresoc.v:98903$3992 + attribute \src "libresoc.v:99432.3-99453.6" + process $proc$libresoc.v:99432$4046 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:98904.5-98904.29" + attribute \src "libresoc.v:99433.5-99433.29" switch \initial - attribute \src "libresoc.v:98904.9-98904.17" + attribute \src "libresoc.v:99433.9-99433.17" case 1'1 case end @@ -154235,14 +155561,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] end - attribute \src "libresoc.v:98925.3-98946.6" - process $proc$libresoc.v:98925$3993 + attribute \src "libresoc.v:99454.3-99475.6" + process $proc$libresoc.v:99454$4047 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:98926.5-98926.29" + attribute \src "libresoc.v:99455.5-99455.29" switch \initial - attribute \src "libresoc.v:98926.9-98926.17" + attribute \src "libresoc.v:99455.9-99455.17" case 1'1 case end @@ -154274,14 +155600,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] end - attribute \src "libresoc.v:98947.3-98968.6" - process $proc$libresoc.v:98947$3994 + attribute \src "libresoc.v:99476.3-99497.6" + process $proc$libresoc.v:99476$4048 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:98948.5-98948.29" + attribute \src "libresoc.v:99477.5-99477.29" switch \initial - attribute \src "libresoc.v:98948.9-98948.17" + attribute \src "libresoc.v:99477.9-99477.17" case 1'1 case end @@ -154313,14 +155639,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] end - attribute \src "libresoc.v:98969.3-98990.6" - process $proc$libresoc.v:98969$3995 + attribute \src "libresoc.v:99498.3-99519.6" + process $proc$libresoc.v:99498$4049 assign { } { } assign { } { } assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:98970.5-98970.29" + attribute \src "libresoc.v:99499.5-99499.29" switch \initial - attribute \src "libresoc.v:98970.9-98970.17" + attribute \src "libresoc.v:99499.9-99499.17" case 1'1 case end @@ -154354,140 +155680,140 @@ module \dec31_dec_sub18 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98996.1-99940.10" +attribute \src "libresoc.v:99525.1-100470.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" module \dec31_dec_sub19 - attribute \src "libresoc.v:99825.3-99843.6" + attribute \src "libresoc.v:100355.3-100373.6" wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:99844.3-99862.6" + attribute \src "libresoc.v:100374.3-100392.6" wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:99597.3-99615.6" + attribute \src "libresoc.v:100127.3-100145.6" wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:99673.3-99691.6" + attribute \src "libresoc.v:100203.3-100221.6" wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:99350.3-99368.6" + attribute \src "libresoc.v:99880.3-99898.6" wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:99369.3-99387.6" + attribute \src "libresoc.v:99899.3-99917.6" wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:99578.3-99596.6" + attribute \src "libresoc.v:100108.3-100126.6" wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:99654.3-99672.6" + attribute \src "libresoc.v:100184.3-100202.6" wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:99749.3-99767.6" + attribute \src "libresoc.v:100279.3-100297.6" wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:99331.3-99349.6" + attribute \src "libresoc.v:99861.3-99879.6" wire width 13 $0\dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:99863.3-99881.6" + attribute \src "libresoc.v:100393.3-100411.6" wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:99882.3-99900.6" + attribute \src "libresoc.v:100412.3-100430.6" wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:99901.3-99919.6" + attribute \src "libresoc.v:100431.3-100449.6" wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:99540.3-99558.6" + attribute \src "libresoc.v:100070.3-100088.6" wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:99616.3-99634.6" + attribute \src "libresoc.v:100146.3-100164.6" wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:99635.3-99653.6" + attribute \src "libresoc.v:100165.3-100183.6" wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:99730.3-99748.6" + attribute \src "libresoc.v:100260.3-100278.6" wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:99502.3-99520.6" + attribute \src "libresoc.v:100032.3-100050.6" wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:99787.3-99805.6" + attribute \src "libresoc.v:100317.3-100335.6" wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:99920.3-99938.6" + attribute \src "libresoc.v:100450.3-100468.6" wire width 2 $0\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:99559.3-99577.6" + attribute \src "libresoc.v:100089.3-100107.6" wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:99711.3-99729.6" + attribute \src "libresoc.v:100241.3-100259.6" wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:99806.3-99824.6" + attribute \src "libresoc.v:100336.3-100354.6" wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:99768.3-99786.6" + attribute \src "libresoc.v:100298.3-100316.6" wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:99692.3-99710.6" + attribute \src "libresoc.v:100222.3-100240.6" wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:99464.3-99482.6" + attribute \src "libresoc.v:99994.3-100012.6" wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:99483.3-99501.6" + attribute \src "libresoc.v:100013.3-100031.6" wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:99388.3-99406.6" + attribute \src "libresoc.v:99918.3-99936.6" wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:99407.3-99425.6" + attribute \src "libresoc.v:99937.3-99955.6" wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:99426.3-99444.6" + attribute \src "libresoc.v:99956.3-99974.6" wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:99445.3-99463.6" + attribute \src "libresoc.v:99975.3-99993.6" wire width 3 $0\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:99521.3-99539.6" + attribute \src "libresoc.v:100051.3-100069.6" wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:98997.7-98997.20" + attribute \src "libresoc.v:99526.7-99526.20" wire $0\initial[0:0] - attribute \src "libresoc.v:99825.3-99843.6" + attribute \src "libresoc.v:100355.3-100373.6" wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:99844.3-99862.6" + attribute \src "libresoc.v:100374.3-100392.6" wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:99597.3-99615.6" + attribute \src "libresoc.v:100127.3-100145.6" wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:99673.3-99691.6" + attribute \src "libresoc.v:100203.3-100221.6" wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:99350.3-99368.6" + attribute \src "libresoc.v:99880.3-99898.6" wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:99369.3-99387.6" + attribute \src "libresoc.v:99899.3-99917.6" wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:99578.3-99596.6" + attribute \src "libresoc.v:100108.3-100126.6" wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:99654.3-99672.6" + attribute \src "libresoc.v:100184.3-100202.6" wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:99749.3-99767.6" + attribute \src "libresoc.v:100279.3-100297.6" wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:99331.3-99349.6" + attribute \src "libresoc.v:99861.3-99879.6" wire width 13 $1\dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:99863.3-99881.6" + attribute \src "libresoc.v:100393.3-100411.6" wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:99882.3-99900.6" + attribute \src "libresoc.v:100412.3-100430.6" wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:99901.3-99919.6" + attribute \src "libresoc.v:100431.3-100449.6" wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:99540.3-99558.6" + attribute \src "libresoc.v:100070.3-100088.6" wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:99616.3-99634.6" + attribute \src "libresoc.v:100146.3-100164.6" wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:99635.3-99653.6" + attribute \src "libresoc.v:100165.3-100183.6" wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:99730.3-99748.6" + attribute \src "libresoc.v:100260.3-100278.6" wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:99502.3-99520.6" + attribute \src "libresoc.v:100032.3-100050.6" wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:99787.3-99805.6" + attribute \src "libresoc.v:100317.3-100335.6" wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:99920.3-99938.6" + attribute \src "libresoc.v:100450.3-100468.6" wire width 2 $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:99559.3-99577.6" + attribute \src "libresoc.v:100089.3-100107.6" wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:99711.3-99729.6" + attribute \src "libresoc.v:100241.3-100259.6" wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:99806.3-99824.6" + attribute \src "libresoc.v:100336.3-100354.6" wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:99768.3-99786.6" + attribute \src "libresoc.v:100298.3-100316.6" wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:99692.3-99710.6" + attribute \src "libresoc.v:100222.3-100240.6" wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:99464.3-99482.6" + attribute \src "libresoc.v:99994.3-100012.6" wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:99483.3-99501.6" + attribute \src "libresoc.v:100013.3-100031.6" wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:99388.3-99406.6" + attribute \src "libresoc.v:99918.3-99936.6" wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:99407.3-99425.6" + attribute \src "libresoc.v:99937.3-99955.6" wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:99426.3-99444.6" + attribute \src "libresoc.v:99956.3-99974.6" wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:99445.3-99463.6" + attribute \src "libresoc.v:99975.3-99993.6" wire width 3 $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:99521.3-99539.6" + attribute \src "libresoc.v:100051.3-100069.6" wire width 2 $1\dec31_dec_sub19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -154563,6 +155889,7 @@ module \dec31_dec_sub19 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub19_form attribute \enum_base_type "Function" @@ -154786,308 +156113,20 @@ module \dec31_dec_sub19 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub19_upd - attribute \src "libresoc.v:98997.7-98997.15" + attribute \src "libresoc.v:99526.7-99526.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:98997.7-98997.20" - process $proc$libresoc.v:98997$4029 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:99331.3-99349.6" - process $proc$libresoc.v:99331$3997 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_function_unit[12:0] $1\dec31_dec_sub19_function_unit[12:0] - attribute \src "libresoc.v:99332.5-99332.29" - switch \initial - attribute \src "libresoc.v:99332.9-99332.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000 - case - assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000000000000 - end - sync always - update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[12:0] - end - attribute \src "libresoc.v:99350.3-99368.6" - process $proc$libresoc.v:99350$3998 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:99351.5-99351.29" - switch \initial - attribute \src "libresoc.v:99351.9-99351.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] - end - attribute \src "libresoc.v:99369.3-99387.6" - process $proc$libresoc.v:99369$3999 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:99370.5-99370.29" - switch \initial - attribute \src "libresoc.v:99370.9-99370.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] - end - attribute \src "libresoc.v:99388.3-99406.6" - process $proc$libresoc.v:99388$4000 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:99389.5-99389.29" - switch \initial - attribute \src "libresoc.v:99389.9-99389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 - case - assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] - end - attribute \src "libresoc.v:99407.3-99425.6" - process $proc$libresoc.v:99407$4001 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:99408.5-99408.29" - switch \initial - attribute \src "libresoc.v:99408.9-99408.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 - case - assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] - end - attribute \src "libresoc.v:99426.3-99444.6" - process $proc$libresoc.v:99426$4002 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:99427.5-99427.29" - switch \initial - attribute \src "libresoc.v:99427.9-99427.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 - case - assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] - end - attribute \src "libresoc.v:99445.3-99463.6" - process $proc$libresoc.v:99445$4003 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:99446.5-99446.29" - switch \initial - attribute \src "libresoc.v:99446.9-99446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 - case - assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] - end - attribute \src "libresoc.v:99464.3-99482.6" - process $proc$libresoc.v:99464$4004 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:99465.5-99465.29" - switch \initial - attribute \src "libresoc.v:99465.9-99465.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] - end - attribute \src "libresoc.v:99483.3-99501.6" - process $proc$libresoc.v:99483$4005 + attribute \src "libresoc.v:100013.3-100031.6" + process $proc$libresoc.v:100013$4059 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:99484.5-99484.29" + attribute \src "libresoc.v:100014.5-100014.29" switch \initial - attribute \src "libresoc.v:99484.9-99484.17" + attribute \src "libresoc.v:100014.9-100014.17" case 1'1 case end @@ -155115,14 +156154,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] end - attribute \src "libresoc.v:99502.3-99520.6" - process $proc$libresoc.v:99502$4006 + attribute \src "libresoc.v:100032.3-100050.6" + process $proc$libresoc.v:100032$4060 assign { } { } assign { } { } assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:99503.5-99503.29" + attribute \src "libresoc.v:100033.5-100033.29" switch \initial - attribute \src "libresoc.v:99503.9-99503.17" + attribute \src "libresoc.v:100033.9-100033.17" case 1'1 case end @@ -155150,14 +156189,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] end - attribute \src "libresoc.v:99521.3-99539.6" - process $proc$libresoc.v:99521$4007 + attribute \src "libresoc.v:100051.3-100069.6" + process $proc$libresoc.v:100051$4061 assign { } { } assign { } { } assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:99522.5-99522.29" + attribute \src "libresoc.v:100052.5-100052.29" switch \initial - attribute \src "libresoc.v:99522.9-99522.17" + attribute \src "libresoc.v:100052.9-100052.17" case 1'1 case end @@ -155185,14 +156224,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] end - attribute \src "libresoc.v:99540.3-99558.6" - process $proc$libresoc.v:99540$4008 + attribute \src "libresoc.v:100070.3-100088.6" + process $proc$libresoc.v:100070$4062 assign { } { } assign { } { } assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:99541.5-99541.29" + attribute \src "libresoc.v:100071.5-100071.29" switch \initial - attribute \src "libresoc.v:99541.9-99541.17" + attribute \src "libresoc.v:100071.9-100071.17" case 1'1 case end @@ -155220,14 +156259,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:99559.3-99577.6" - process $proc$libresoc.v:99559$4009 + attribute \src "libresoc.v:100089.3-100107.6" + process $proc$libresoc.v:100089$4063 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:99560.5-99560.29" + attribute \src "libresoc.v:100090.5-100090.29" switch \initial - attribute \src "libresoc.v:99560.9-99560.17" + attribute \src "libresoc.v:100090.9-100090.17" case 1'1 case end @@ -155255,14 +156294,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:99578.3-99596.6" - process $proc$libresoc.v:99578$4010 + attribute \src "libresoc.v:100108.3-100126.6" + process $proc$libresoc.v:100108$4064 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:99579.5-99579.29" + attribute \src "libresoc.v:100109.5-100109.29" switch \initial - attribute \src "libresoc.v:99579.9-99579.17" + attribute \src "libresoc.v:100109.9-100109.17" case 1'1 case end @@ -155290,14 +156329,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] end - attribute \src "libresoc.v:99597.3-99615.6" - process $proc$libresoc.v:99597$4011 + attribute \src "libresoc.v:100127.3-100145.6" + process $proc$libresoc.v:100127$4065 assign { } { } assign { } { } assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:99598.5-99598.29" + attribute \src "libresoc.v:100128.5-100128.29" switch \initial - attribute \src "libresoc.v:99598.9-99598.17" + attribute \src "libresoc.v:100128.9-100128.17" case 1'1 case end @@ -155325,14 +156364,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end - attribute \src "libresoc.v:99616.3-99634.6" - process $proc$libresoc.v:99616$4012 + attribute \src "libresoc.v:100146.3-100164.6" + process $proc$libresoc.v:100146$4066 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:99617.5-99617.29" + attribute \src "libresoc.v:100147.5-100147.29" switch \initial - attribute \src "libresoc.v:99617.9-99617.17" + attribute \src "libresoc.v:100147.9-100147.17" case 1'1 case end @@ -155360,14 +156399,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] end - attribute \src "libresoc.v:99635.3-99653.6" - process $proc$libresoc.v:99635$4013 + attribute \src "libresoc.v:100165.3-100183.6" + process $proc$libresoc.v:100165$4067 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:99636.5-99636.29" + attribute \src "libresoc.v:100166.5-100166.29" switch \initial - attribute \src "libresoc.v:99636.9-99636.17" + attribute \src "libresoc.v:100166.9-100166.17" case 1'1 case end @@ -155395,14 +156434,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] end - attribute \src "libresoc.v:99654.3-99672.6" - process $proc$libresoc.v:99654$4014 + attribute \src "libresoc.v:100184.3-100202.6" + process $proc$libresoc.v:100184$4068 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:99655.5-99655.29" + attribute \src "libresoc.v:100185.5-100185.29" switch \initial - attribute \src "libresoc.v:99655.9-99655.17" + attribute \src "libresoc.v:100185.9-100185.17" case 1'1 case end @@ -155430,14 +156469,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end - attribute \src "libresoc.v:99673.3-99691.6" - process $proc$libresoc.v:99673$4015 + attribute \src "libresoc.v:100203.3-100221.6" + process $proc$libresoc.v:100203$4069 assign { } { } assign { } { } assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:99674.5-99674.29" + attribute \src "libresoc.v:100204.5-100204.29" switch \initial - attribute \src "libresoc.v:99674.9-99674.17" + attribute \src "libresoc.v:100204.9-100204.17" case 1'1 case end @@ -155465,14 +156504,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] end - attribute \src "libresoc.v:99692.3-99710.6" - process $proc$libresoc.v:99692$4016 + attribute \src "libresoc.v:100222.3-100240.6" + process $proc$libresoc.v:100222$4070 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:99693.5-99693.29" + attribute \src "libresoc.v:100223.5-100223.29" switch \initial - attribute \src "libresoc.v:99693.9-99693.17" + attribute \src "libresoc.v:100223.9-100223.17" case 1'1 case end @@ -155500,14 +156539,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] end - attribute \src "libresoc.v:99711.3-99729.6" - process $proc$libresoc.v:99711$4017 + attribute \src "libresoc.v:100241.3-100259.6" + process $proc$libresoc.v:100241$4071 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:99712.5-99712.29" + attribute \src "libresoc.v:100242.5-100242.29" switch \initial - attribute \src "libresoc.v:99712.9-99712.17" + attribute \src "libresoc.v:100242.9-100242.17" case 1'1 case end @@ -155535,14 +156574,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end - attribute \src "libresoc.v:99730.3-99748.6" - process $proc$libresoc.v:99730$4018 + attribute \src "libresoc.v:100260.3-100278.6" + process $proc$libresoc.v:100260$4072 assign { } { } assign { } { } assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:99731.5-99731.29" + attribute \src "libresoc.v:100261.5-100261.29" switch \initial - attribute \src "libresoc.v:99731.9-99731.17" + attribute \src "libresoc.v:100261.9-100261.17" case 1'1 case end @@ -155570,14 +156609,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] end - attribute \src "libresoc.v:99749.3-99767.6" - process $proc$libresoc.v:99749$4019 + attribute \src "libresoc.v:100279.3-100297.6" + process $proc$libresoc.v:100279$4073 assign { } { } assign { } { } assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:99750.5-99750.29" + attribute \src "libresoc.v:100280.5-100280.29" switch \initial - attribute \src "libresoc.v:99750.9-99750.17" + attribute \src "libresoc.v:100280.9-100280.17" case 1'1 case end @@ -155605,14 +156644,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] end - attribute \src "libresoc.v:99768.3-99786.6" - process $proc$libresoc.v:99768$4020 + attribute \src "libresoc.v:100298.3-100316.6" + process $proc$libresoc.v:100298$4074 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:99769.5-99769.29" + attribute \src "libresoc.v:100299.5-100299.29" switch \initial - attribute \src "libresoc.v:99769.9-99769.17" + attribute \src "libresoc.v:100299.9-100299.17" case 1'1 case end @@ -155640,14 +156679,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end - attribute \src "libresoc.v:99787.3-99805.6" - process $proc$libresoc.v:99787$4021 + attribute \src "libresoc.v:100317.3-100335.6" + process $proc$libresoc.v:100317$4075 assign { } { } assign { } { } assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:99788.5-99788.29" + attribute \src "libresoc.v:100318.5-100318.29" switch \initial - attribute \src "libresoc.v:99788.9-99788.17" + attribute \src "libresoc.v:100318.9-100318.17" case 1'1 case end @@ -155675,14 +156714,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] end - attribute \src "libresoc.v:99806.3-99824.6" - process $proc$libresoc.v:99806$4022 + attribute \src "libresoc.v:100336.3-100354.6" + process $proc$libresoc.v:100336$4076 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:99807.5-99807.29" + attribute \src "libresoc.v:100337.5-100337.29" switch \initial - attribute \src "libresoc.v:99807.9-99807.17" + attribute \src "libresoc.v:100337.9-100337.17" case 1'1 case end @@ -155710,14 +156749,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] end - attribute \src "libresoc.v:99825.3-99843.6" - process $proc$libresoc.v:99825$4023 + attribute \src "libresoc.v:100355.3-100373.6" + process $proc$libresoc.v:100355$4077 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:99826.5-99826.29" + attribute \src "libresoc.v:100356.5-100356.29" switch \initial - attribute \src "libresoc.v:99826.9-99826.17" + attribute \src "libresoc.v:100356.9-100356.17" case 1'1 case end @@ -155745,14 +156784,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] end - attribute \src "libresoc.v:99844.3-99862.6" - process $proc$libresoc.v:99844$4024 + attribute \src "libresoc.v:100374.3-100392.6" + process $proc$libresoc.v:100374$4078 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:99845.5-99845.29" + attribute \src "libresoc.v:100375.5-100375.29" switch \initial - attribute \src "libresoc.v:99845.9-99845.17" + attribute \src "libresoc.v:100375.9-100375.17" case 1'1 case end @@ -155780,14 +156819,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] end - attribute \src "libresoc.v:99863.3-99881.6" - process $proc$libresoc.v:99863$4025 + attribute \src "libresoc.v:100393.3-100411.6" + process $proc$libresoc.v:100393$4079 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:99864.5-99864.29" + attribute \src "libresoc.v:100394.5-100394.29" switch \initial - attribute \src "libresoc.v:99864.9-99864.17" + attribute \src "libresoc.v:100394.9-100394.17" case 1'1 case end @@ -155815,14 +156854,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] end - attribute \src "libresoc.v:99882.3-99900.6" - process $proc$libresoc.v:99882$4026 + attribute \src "libresoc.v:100412.3-100430.6" + process $proc$libresoc.v:100412$4080 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:99883.5-99883.29" + attribute \src "libresoc.v:100413.5-100413.29" switch \initial - attribute \src "libresoc.v:99883.9-99883.17" + attribute \src "libresoc.v:100413.9-100413.17" case 1'1 case end @@ -155850,14 +156889,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end - attribute \src "libresoc.v:99901.3-99919.6" - process $proc$libresoc.v:99901$4027 + attribute \src "libresoc.v:100431.3-100449.6" + process $proc$libresoc.v:100431$4081 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:99902.5-99902.29" + attribute \src "libresoc.v:100432.5-100432.29" switch \initial - attribute \src "libresoc.v:99902.9-99902.17" + attribute \src "libresoc.v:100432.9-100432.17" case 1'1 case end @@ -155885,14 +156924,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] end - attribute \src "libresoc.v:99920.3-99938.6" - process $proc$libresoc.v:99920$4028 + attribute \src "libresoc.v:100450.3-100468.6" + process $proc$libresoc.v:100450$4082 assign { } { } assign { } { } assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:99921.5-99921.29" + attribute \src "libresoc.v:100451.5-100451.29" switch \initial - attribute \src "libresoc.v:99921.9-99921.17" + attribute \src "libresoc.v:100451.9-100451.17" case 1'1 case end @@ -155920,142 +156959,430 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] end + attribute \src "libresoc.v:99526.7-99526.20" + process $proc$libresoc.v:99526$4083 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:99861.3-99879.6" + process $proc$libresoc.v:99861$4051 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_function_unit[12:0] $1\dec31_dec_sub19_function_unit[12:0] + attribute \src "libresoc.v:99862.5-99862.29" + switch \initial + attribute \src "libresoc.v:99862.9-99862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000 + case + assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[12:0] + end + attribute \src "libresoc.v:99880.3-99898.6" + process $proc$libresoc.v:99880$4052 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:99881.5-99881.29" + switch \initial + attribute \src "libresoc.v:99881.9-99881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:99899.3-99917.6" + process $proc$libresoc.v:99899$4053 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:99900.5-99900.29" + switch \initial + attribute \src "libresoc.v:99900.9-99900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:99918.3-99936.6" + process $proc$libresoc.v:99918$4054 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] + attribute \src "libresoc.v:99919.5-99919.29" + switch \initial + attribute \src "libresoc.v:99919.9-99919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] + end + attribute \src "libresoc.v:99937.3-99955.6" + process $proc$libresoc.v:99937$4055 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] + attribute \src "libresoc.v:99938.5-99938.29" + switch \initial + attribute \src "libresoc.v:99938.9-99938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] + end + attribute \src "libresoc.v:99956.3-99974.6" + process $proc$libresoc.v:99956$4056 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] + attribute \src "libresoc.v:99957.5-99957.29" + switch \initial + attribute \src "libresoc.v:99957.9-99957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] + end + attribute \src "libresoc.v:99975.3-99993.6" + process $proc$libresoc.v:99975$4057 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] + attribute \src "libresoc.v:99976.5-99976.29" + switch \initial + attribute \src "libresoc.v:99976.9-99976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] + end + attribute \src "libresoc.v:99994.3-100012.6" + process $proc$libresoc.v:99994$4058 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] + attribute \src "libresoc.v:99995.5-99995.29" + switch \initial + attribute \src "libresoc.v:99995.9-99995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] + end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:99944.1-101080.10" +attribute \src "libresoc.v:100474.1-101611.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" attribute \generator "nMigen" module \dec31_dec_sub20 - attribute \src "libresoc.v:100929.3-100953.6" + attribute \src "libresoc.v:101460.3-101484.6" wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:100954.3-100978.6" + attribute \src "libresoc.v:101485.3-101509.6" wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:100629.3-100653.6" + attribute \src "libresoc.v:101160.3-101184.6" wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:100729.3-100753.6" + attribute \src "libresoc.v:101260.3-101284.6" wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:100304.3-100328.6" + attribute \src "libresoc.v:100835.3-100859.6" wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:100329.3-100353.6" + attribute \src "libresoc.v:100860.3-100884.6" wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:100604.3-100628.6" + attribute \src "libresoc.v:101135.3-101159.6" wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:100704.3-100728.6" + attribute \src "libresoc.v:101235.3-101259.6" wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:100829.3-100853.6" + attribute \src "libresoc.v:101360.3-101384.6" wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:100279.3-100303.6" + attribute \src "libresoc.v:100810.3-100834.6" wire width 13 $0\dec31_dec_sub20_function_unit[12:0] - attribute \src "libresoc.v:100979.3-101003.6" + attribute \src "libresoc.v:101510.3-101534.6" wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:101004.3-101028.6" + attribute \src "libresoc.v:101535.3-101559.6" wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:101029.3-101053.6" + attribute \src "libresoc.v:101560.3-101584.6" wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:100554.3-100578.6" + attribute \src "libresoc.v:101085.3-101109.6" wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:100654.3-100678.6" + attribute \src "libresoc.v:101185.3-101209.6" wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:100679.3-100703.6" + attribute \src "libresoc.v:101210.3-101234.6" wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:100804.3-100828.6" + attribute \src "libresoc.v:101335.3-101359.6" wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:100504.3-100528.6" + attribute \src "libresoc.v:101035.3-101059.6" wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:100879.3-100903.6" + attribute \src "libresoc.v:101410.3-101434.6" wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:101054.3-101078.6" + attribute \src "libresoc.v:101585.3-101609.6" wire width 2 $0\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:100579.3-100603.6" + attribute \src "libresoc.v:101110.3-101134.6" wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:100779.3-100803.6" + attribute \src "libresoc.v:101310.3-101334.6" wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:100904.3-100928.6" + attribute \src "libresoc.v:101435.3-101459.6" wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:100854.3-100878.6" + attribute \src "libresoc.v:101385.3-101409.6" wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:100754.3-100778.6" + attribute \src "libresoc.v:101285.3-101309.6" wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:100454.3-100478.6" + attribute \src "libresoc.v:100985.3-101009.6" wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:100479.3-100503.6" + attribute \src "libresoc.v:101010.3-101034.6" wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:100354.3-100378.6" + attribute \src "libresoc.v:100885.3-100909.6" wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:100379.3-100403.6" + attribute \src "libresoc.v:100910.3-100934.6" wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:100404.3-100428.6" + attribute \src "libresoc.v:100935.3-100959.6" wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:100429.3-100453.6" + attribute \src "libresoc.v:100960.3-100984.6" wire width 3 $0\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:100529.3-100553.6" + attribute \src "libresoc.v:101060.3-101084.6" wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:99945.7-99945.20" + attribute \src "libresoc.v:100475.7-100475.20" wire $0\initial[0:0] - attribute \src "libresoc.v:100929.3-100953.6" + attribute \src "libresoc.v:101460.3-101484.6" wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:100954.3-100978.6" + attribute \src "libresoc.v:101485.3-101509.6" wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:100629.3-100653.6" + attribute \src "libresoc.v:101160.3-101184.6" wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:100729.3-100753.6" + attribute \src "libresoc.v:101260.3-101284.6" wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:100304.3-100328.6" + attribute \src "libresoc.v:100835.3-100859.6" wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:100329.3-100353.6" + attribute \src "libresoc.v:100860.3-100884.6" wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:100604.3-100628.6" + attribute \src "libresoc.v:101135.3-101159.6" wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:100704.3-100728.6" + attribute \src "libresoc.v:101235.3-101259.6" wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:100829.3-100853.6" + attribute \src "libresoc.v:101360.3-101384.6" wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:100279.3-100303.6" + attribute \src "libresoc.v:100810.3-100834.6" wire width 13 $1\dec31_dec_sub20_function_unit[12:0] - attribute \src "libresoc.v:100979.3-101003.6" + attribute \src "libresoc.v:101510.3-101534.6" wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:101004.3-101028.6" + attribute \src "libresoc.v:101535.3-101559.6" wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:101029.3-101053.6" + attribute \src "libresoc.v:101560.3-101584.6" wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:100554.3-100578.6" + attribute \src "libresoc.v:101085.3-101109.6" wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:100654.3-100678.6" + attribute \src "libresoc.v:101185.3-101209.6" wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:100679.3-100703.6" + attribute \src "libresoc.v:101210.3-101234.6" wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:100804.3-100828.6" + attribute \src "libresoc.v:101335.3-101359.6" wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:100504.3-100528.6" + attribute \src "libresoc.v:101035.3-101059.6" wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:100879.3-100903.6" + attribute \src "libresoc.v:101410.3-101434.6" wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:101054.3-101078.6" + attribute \src "libresoc.v:101585.3-101609.6" wire width 2 $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:100579.3-100603.6" + attribute \src "libresoc.v:101110.3-101134.6" wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:100779.3-100803.6" + attribute \src "libresoc.v:101310.3-101334.6" wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:100904.3-100928.6" + attribute \src "libresoc.v:101435.3-101459.6" wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:100854.3-100878.6" + attribute \src "libresoc.v:101385.3-101409.6" wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:100754.3-100778.6" + attribute \src "libresoc.v:101285.3-101309.6" wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:100454.3-100478.6" + attribute \src "libresoc.v:100985.3-101009.6" wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:100479.3-100503.6" + attribute \src "libresoc.v:101010.3-101034.6" wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:100354.3-100378.6" + attribute \src "libresoc.v:100885.3-100909.6" wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:100379.3-100403.6" + attribute \src "libresoc.v:100910.3-100934.6" wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:100404.3-100428.6" + attribute \src "libresoc.v:100935.3-100959.6" wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:100429.3-100453.6" + attribute \src "libresoc.v:100960.3-100984.6" wire width 3 $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:100529.3-100553.6" + attribute \src "libresoc.v:101060.3-101084.6" wire width 2 $1\dec31_dec_sub20_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -156131,6 +157458,7 @@ module \dec31_dec_sub20 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub20_form attribute \enum_base_type "Function" @@ -156354,20 +157682,28 @@ module \dec31_dec_sub20 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub20_upd - attribute \src "libresoc.v:99945.7-99945.15" + attribute \src "libresoc.v:100475.7-100475.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:100279.3-100303.6" - process $proc$libresoc.v:100279$4030 + attribute \src "libresoc.v:100475.7-100475.20" + process $proc$libresoc.v:100475$4116 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:100810.3-100834.6" + process $proc$libresoc.v:100810$4084 assign { } { } assign { } { } assign $0\dec31_dec_sub20_function_unit[12:0] $1\dec31_dec_sub20_function_unit[12:0] - attribute \src "libresoc.v:100280.5-100280.29" + attribute \src "libresoc.v:100811.5-100811.29" switch \initial - attribute \src "libresoc.v:100280.9-100280.17" + attribute \src "libresoc.v:100811.9-100811.17" case 1'1 case end @@ -156403,14 +157739,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[12:0] end - attribute \src "libresoc.v:100304.3-100328.6" - process $proc$libresoc.v:100304$4031 + attribute \src "libresoc.v:100835.3-100859.6" + process $proc$libresoc.v:100835$4085 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:100305.5-100305.29" + attribute \src "libresoc.v:100836.5-100836.29" switch \initial - attribute \src "libresoc.v:100305.9-100305.17" + attribute \src "libresoc.v:100836.9-100836.17" case 1'1 case end @@ -156446,14 +157782,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] end - attribute \src "libresoc.v:100329.3-100353.6" - process $proc$libresoc.v:100329$4032 + attribute \src "libresoc.v:100860.3-100884.6" + process $proc$libresoc.v:100860$4086 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:100330.5-100330.29" + attribute \src "libresoc.v:100861.5-100861.29" switch \initial - attribute \src "libresoc.v:100330.9-100330.17" + attribute \src "libresoc.v:100861.9-100861.17" case 1'1 case end @@ -156489,14 +157825,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] end - attribute \src "libresoc.v:100354.3-100378.6" - process $proc$libresoc.v:100354$4033 + attribute \src "libresoc.v:100885.3-100909.6" + process $proc$libresoc.v:100885$4087 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:100355.5-100355.29" + attribute \src "libresoc.v:100886.5-100886.29" switch \initial - attribute \src "libresoc.v:100355.9-100355.17" + attribute \src "libresoc.v:100886.9-100886.17" case 1'1 case end @@ -156532,14 +157868,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] end - attribute \src "libresoc.v:100379.3-100403.6" - process $proc$libresoc.v:100379$4034 + attribute \src "libresoc.v:100910.3-100934.6" + process $proc$libresoc.v:100910$4088 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:100380.5-100380.29" + attribute \src "libresoc.v:100911.5-100911.29" switch \initial - attribute \src "libresoc.v:100380.9-100380.17" + attribute \src "libresoc.v:100911.9-100911.17" case 1'1 case end @@ -156575,14 +157911,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] end - attribute \src "libresoc.v:100404.3-100428.6" - process $proc$libresoc.v:100404$4035 + attribute \src "libresoc.v:100935.3-100959.6" + process $proc$libresoc.v:100935$4089 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:100405.5-100405.29" + attribute \src "libresoc.v:100936.5-100936.29" switch \initial - attribute \src "libresoc.v:100405.9-100405.17" + attribute \src "libresoc.v:100936.9-100936.17" case 1'1 case end @@ -156618,14 +157954,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] end - attribute \src "libresoc.v:100429.3-100453.6" - process $proc$libresoc.v:100429$4036 + attribute \src "libresoc.v:100960.3-100984.6" + process $proc$libresoc.v:100960$4090 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:100430.5-100430.29" + attribute \src "libresoc.v:100961.5-100961.29" switch \initial - attribute \src "libresoc.v:100430.9-100430.17" + attribute \src "libresoc.v:100961.9-100961.17" case 1'1 case end @@ -156661,14 +157997,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] end - attribute \src "libresoc.v:100454.3-100478.6" - process $proc$libresoc.v:100454$4037 + attribute \src "libresoc.v:100985.3-101009.6" + process $proc$libresoc.v:100985$4091 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:100455.5-100455.29" + attribute \src "libresoc.v:100986.5-100986.29" switch \initial - attribute \src "libresoc.v:100455.9-100455.17" + attribute \src "libresoc.v:100986.9-100986.17" case 1'1 case end @@ -156704,14 +158040,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] end - attribute \src "libresoc.v:100479.3-100503.6" - process $proc$libresoc.v:100479$4038 + attribute \src "libresoc.v:101010.3-101034.6" + process $proc$libresoc.v:101010$4092 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:100480.5-100480.29" + attribute \src "libresoc.v:101011.5-101011.29" switch \initial - attribute \src "libresoc.v:100480.9-100480.17" + attribute \src "libresoc.v:101011.9-101011.17" case 1'1 case end @@ -156747,14 +158083,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] end - attribute \src "libresoc.v:100504.3-100528.6" - process $proc$libresoc.v:100504$4039 + attribute \src "libresoc.v:101035.3-101059.6" + process $proc$libresoc.v:101035$4093 assign { } { } assign { } { } assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:100505.5-100505.29" + attribute \src "libresoc.v:101036.5-101036.29" switch \initial - attribute \src "libresoc.v:100505.9-100505.17" + attribute \src "libresoc.v:101036.9-101036.17" case 1'1 case end @@ -156790,14 +158126,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] end - attribute \src "libresoc.v:100529.3-100553.6" - process $proc$libresoc.v:100529$4040 + attribute \src "libresoc.v:101060.3-101084.6" + process $proc$libresoc.v:101060$4094 assign { } { } assign { } { } assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:100530.5-100530.29" + attribute \src "libresoc.v:101061.5-101061.29" switch \initial - attribute \src "libresoc.v:100530.9-100530.17" + attribute \src "libresoc.v:101061.9-101061.17" case 1'1 case end @@ -156833,14 +158169,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:100554.3-100578.6" - process $proc$libresoc.v:100554$4041 + attribute \src "libresoc.v:101085.3-101109.6" + process $proc$libresoc.v:101085$4095 assign { } { } assign { } { } assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:100555.5-100555.29" + attribute \src "libresoc.v:101086.5-101086.29" switch \initial - attribute \src "libresoc.v:100555.9-100555.17" + attribute \src "libresoc.v:101086.9-101086.17" case 1'1 case end @@ -156876,14 +158212,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:100579.3-100603.6" - process $proc$libresoc.v:100579$4042 + attribute \src "libresoc.v:101110.3-101134.6" + process $proc$libresoc.v:101110$4096 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:100580.5-100580.29" + attribute \src "libresoc.v:101111.5-101111.29" switch \initial - attribute \src "libresoc.v:100580.9-100580.17" + attribute \src "libresoc.v:101111.9-101111.17" case 1'1 case end @@ -156919,14 +158255,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] end - attribute \src "libresoc.v:100604.3-100628.6" - process $proc$libresoc.v:100604$4043 + attribute \src "libresoc.v:101135.3-101159.6" + process $proc$libresoc.v:101135$4097 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:100605.5-100605.29" + attribute \src "libresoc.v:101136.5-101136.29" switch \initial - attribute \src "libresoc.v:100605.9-100605.17" + attribute \src "libresoc.v:101136.9-101136.17" case 1'1 case end @@ -156962,14 +158298,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end - attribute \src "libresoc.v:100629.3-100653.6" - process $proc$libresoc.v:100629$4044 + attribute \src "libresoc.v:101160.3-101184.6" + process $proc$libresoc.v:101160$4098 assign { } { } assign { } { } assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:100630.5-100630.29" + attribute \src "libresoc.v:101161.5-101161.29" switch \initial - attribute \src "libresoc.v:100630.9-100630.17" + attribute \src "libresoc.v:101161.9-101161.17" case 1'1 case end @@ -157005,14 +158341,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] end - attribute \src "libresoc.v:100654.3-100678.6" - process $proc$libresoc.v:100654$4045 + attribute \src "libresoc.v:101185.3-101209.6" + process $proc$libresoc.v:101185$4099 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:100655.5-100655.29" + attribute \src "libresoc.v:101186.5-101186.29" switch \initial - attribute \src "libresoc.v:100655.9-100655.17" + attribute \src "libresoc.v:101186.9-101186.17" case 1'1 case end @@ -157048,14 +158384,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end - attribute \src "libresoc.v:100679.3-100703.6" - process $proc$libresoc.v:100679$4046 + attribute \src "libresoc.v:101210.3-101234.6" + process $proc$libresoc.v:101210$4100 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:100680.5-100680.29" + attribute \src "libresoc.v:101211.5-101211.29" switch \initial - attribute \src "libresoc.v:100680.9-100680.17" + attribute \src "libresoc.v:101211.9-101211.17" case 1'1 case end @@ -157091,14 +158427,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] end - attribute \src "libresoc.v:100704.3-100728.6" - process $proc$libresoc.v:100704$4047 + attribute \src "libresoc.v:101235.3-101259.6" + process $proc$libresoc.v:101235$4101 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:100705.5-100705.29" + attribute \src "libresoc.v:101236.5-101236.29" switch \initial - attribute \src "libresoc.v:100705.9-100705.17" + attribute \src "libresoc.v:101236.9-101236.17" case 1'1 case end @@ -157134,14 +158470,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] end - attribute \src "libresoc.v:100729.3-100753.6" - process $proc$libresoc.v:100729$4048 + attribute \src "libresoc.v:101260.3-101284.6" + process $proc$libresoc.v:101260$4102 assign { } { } assign { } { } assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:100730.5-100730.29" + attribute \src "libresoc.v:101261.5-101261.29" switch \initial - attribute \src "libresoc.v:100730.9-100730.17" + attribute \src "libresoc.v:101261.9-101261.17" case 1'1 case end @@ -157177,14 +158513,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:100754.3-100778.6" - process $proc$libresoc.v:100754$4049 + attribute \src "libresoc.v:101285.3-101309.6" + process $proc$libresoc.v:101285$4103 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:100755.5-100755.29" + attribute \src "libresoc.v:101286.5-101286.29" switch \initial - attribute \src "libresoc.v:100755.9-100755.17" + attribute \src "libresoc.v:101286.9-101286.17" case 1'1 case end @@ -157220,14 +158556,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] end - attribute \src "libresoc.v:100779.3-100803.6" - process $proc$libresoc.v:100779$4050 + attribute \src "libresoc.v:101310.3-101334.6" + process $proc$libresoc.v:101310$4104 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:100780.5-100780.29" + attribute \src "libresoc.v:101311.5-101311.29" switch \initial - attribute \src "libresoc.v:100780.9-100780.17" + attribute \src "libresoc.v:101311.9-101311.17" case 1'1 case end @@ -157263,14 +158599,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] end - attribute \src "libresoc.v:100804.3-100828.6" - process $proc$libresoc.v:100804$4051 + attribute \src "libresoc.v:101335.3-101359.6" + process $proc$libresoc.v:101335$4105 assign { } { } assign { } { } assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:100805.5-100805.29" + attribute \src "libresoc.v:101336.5-101336.29" switch \initial - attribute \src "libresoc.v:100805.9-100805.17" + attribute \src "libresoc.v:101336.9-101336.17" case 1'1 case end @@ -157306,14 +158642,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:100829.3-100853.6" - process $proc$libresoc.v:100829$4052 + attribute \src "libresoc.v:101360.3-101384.6" + process $proc$libresoc.v:101360$4106 assign { } { } assign { } { } assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:100830.5-100830.29" + attribute \src "libresoc.v:101361.5-101361.29" switch \initial - attribute \src "libresoc.v:100830.9-100830.17" + attribute \src "libresoc.v:101361.9-101361.17" case 1'1 case end @@ -157349,14 +158685,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] end - attribute \src "libresoc.v:100854.3-100878.6" - process $proc$libresoc.v:100854$4053 + attribute \src "libresoc.v:101385.3-101409.6" + process $proc$libresoc.v:101385$4107 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:100855.5-100855.29" + attribute \src "libresoc.v:101386.5-101386.29" switch \initial - attribute \src "libresoc.v:100855.9-100855.17" + attribute \src "libresoc.v:101386.9-101386.17" case 1'1 case end @@ -157392,14 +158728,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] end - attribute \src "libresoc.v:100879.3-100903.6" - process $proc$libresoc.v:100879$4054 + attribute \src "libresoc.v:101410.3-101434.6" + process $proc$libresoc.v:101410$4108 assign { } { } assign { } { } assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:100880.5-100880.29" + attribute \src "libresoc.v:101411.5-101411.29" switch \initial - attribute \src "libresoc.v:100880.9-100880.17" + attribute \src "libresoc.v:101411.9-101411.17" case 1'1 case end @@ -157435,14 +158771,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] end - attribute \src "libresoc.v:100904.3-100928.6" - process $proc$libresoc.v:100904$4055 + attribute \src "libresoc.v:101435.3-101459.6" + process $proc$libresoc.v:101435$4109 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:100905.5-100905.29" + attribute \src "libresoc.v:101436.5-101436.29" switch \initial - attribute \src "libresoc.v:100905.9-100905.17" + attribute \src "libresoc.v:101436.9-101436.17" case 1'1 case end @@ -157478,14 +158814,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] end - attribute \src "libresoc.v:100929.3-100953.6" - process $proc$libresoc.v:100929$4056 + attribute \src "libresoc.v:101460.3-101484.6" + process $proc$libresoc.v:101460$4110 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:100930.5-100930.29" + attribute \src "libresoc.v:101461.5-101461.29" switch \initial - attribute \src "libresoc.v:100930.9-100930.17" + attribute \src "libresoc.v:101461.9-101461.17" case 1'1 case end @@ -157521,14 +158857,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] end - attribute \src "libresoc.v:100954.3-100978.6" - process $proc$libresoc.v:100954$4057 + attribute \src "libresoc.v:101485.3-101509.6" + process $proc$libresoc.v:101485$4111 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:100955.5-100955.29" + attribute \src "libresoc.v:101486.5-101486.29" switch \initial - attribute \src "libresoc.v:100955.9-100955.17" + attribute \src "libresoc.v:101486.9-101486.17" case 1'1 case end @@ -157564,14 +158900,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] end - attribute \src "libresoc.v:100979.3-101003.6" - process $proc$libresoc.v:100979$4058 + attribute \src "libresoc.v:101510.3-101534.6" + process $proc$libresoc.v:101510$4112 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:100980.5-100980.29" + attribute \src "libresoc.v:101511.5-101511.29" switch \initial - attribute \src "libresoc.v:100980.9-100980.17" + attribute \src "libresoc.v:101511.9-101511.17" case 1'1 case end @@ -157607,14 +158943,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] end - attribute \src "libresoc.v:101004.3-101028.6" - process $proc$libresoc.v:101004$4059 + attribute \src "libresoc.v:101535.3-101559.6" + process $proc$libresoc.v:101535$4113 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:101005.5-101005.29" + attribute \src "libresoc.v:101536.5-101536.29" switch \initial - attribute \src "libresoc.v:101005.9-101005.17" + attribute \src "libresoc.v:101536.9-101536.17" case 1'1 case end @@ -157650,14 +158986,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] end - attribute \src "libresoc.v:101029.3-101053.6" - process $proc$libresoc.v:101029$4060 + attribute \src "libresoc.v:101560.3-101584.6" + process $proc$libresoc.v:101560$4114 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:101030.5-101030.29" + attribute \src "libresoc.v:101561.5-101561.29" switch \initial - attribute \src "libresoc.v:101030.9-101030.17" + attribute \src "libresoc.v:101561.9-101561.17" case 1'1 case end @@ -157693,14 +159029,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] end - attribute \src "libresoc.v:101054.3-101078.6" - process $proc$libresoc.v:101054$4061 + attribute \src "libresoc.v:101585.3-101609.6" + process $proc$libresoc.v:101585$4115 assign { } { } assign { } { } assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:101055.5-101055.29" + attribute \src "libresoc.v:101586.5-101586.29" switch \initial - attribute \src "libresoc.v:101055.9-101055.17" + attribute \src "libresoc.v:101586.9-101586.17" case 1'1 case end @@ -157736,150 +159072,142 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] end - attribute \src "libresoc.v:99945.7-99945.20" - process $proc$libresoc.v:99945$4062 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:101084.1-102970.10" +attribute \src "libresoc.v:101615.1-103502.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" module \dec31_dec_sub21 - attribute \src "libresoc.v:102675.3-102723.6" + attribute \src "libresoc.v:103207.3-103255.6" wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:102724.3-102772.6" + attribute \src "libresoc.v:103256.3-103304.6" wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:102644.3-102674.6" + attribute \src "libresoc.v:103176.3-103206.6" wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:102252.3-102300.6" + attribute \src "libresoc.v:102784.3-102832.6" wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:101468.3-101516.6" + attribute \src "libresoc.v:102000.3-102048.6" wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:101517.3-101565.6" + attribute \src "libresoc.v:102049.3-102097.6" wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:102056.3-102104.6" + attribute \src "libresoc.v:102588.3-102636.6" wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:102203.3-102251.6" + attribute \src "libresoc.v:102735.3-102783.6" wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:102497.3-102545.6" + attribute \src "libresoc.v:103029.3-103077.6" wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:101419.3-101467.6" + attribute \src "libresoc.v:101951.3-101999.6" wire width 13 $0\dec31_dec_sub21_function_unit[12:0] - attribute \src "libresoc.v:102773.3-102821.6" + attribute \src "libresoc.v:103305.3-103353.6" wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:102822.3-102870.6" + attribute \src "libresoc.v:103354.3-103402.6" wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:102871.3-102919.6" + attribute \src "libresoc.v:103403.3-103451.6" wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:101958.3-102006.6" + attribute \src "libresoc.v:102490.3-102538.6" wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:102105.3-102153.6" + attribute \src "libresoc.v:102637.3-102685.6" wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:102154.3-102202.6" + attribute \src "libresoc.v:102686.3-102734.6" wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:102399.3-102447.6" + attribute \src "libresoc.v:102931.3-102979.6" wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:101860.3-101908.6" + attribute \src "libresoc.v:102392.3-102440.6" wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:102546.3-102594.6" + attribute \src "libresoc.v:103078.3-103126.6" wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:102920.3-102968.6" + attribute \src "libresoc.v:103452.3-103500.6" wire width 2 $0\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:102007.3-102055.6" + attribute \src "libresoc.v:102539.3-102587.6" wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:102350.3-102398.6" + attribute \src "libresoc.v:102882.3-102930.6" wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:102595.3-102643.6" + attribute \src "libresoc.v:103127.3-103175.6" wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:102448.3-102496.6" + attribute \src "libresoc.v:102980.3-103028.6" wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:102301.3-102349.6" + attribute \src "libresoc.v:102833.3-102881.6" wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:101762.3-101810.6" + attribute \src "libresoc.v:102294.3-102342.6" wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:101811.3-101859.6" + attribute \src "libresoc.v:102343.3-102391.6" wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:101566.3-101614.6" + attribute \src "libresoc.v:102098.3-102146.6" wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:101615.3-101663.6" + attribute \src "libresoc.v:102147.3-102195.6" wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:101664.3-101712.6" + attribute \src "libresoc.v:102196.3-102244.6" wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:101713.3-101761.6" + attribute \src "libresoc.v:102245.3-102293.6" wire width 3 $0\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:101909.3-101957.6" + attribute \src "libresoc.v:102441.3-102489.6" wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:101085.7-101085.20" + attribute \src "libresoc.v:101616.7-101616.20" wire $0\initial[0:0] - attribute \src "libresoc.v:102675.3-102723.6" + attribute \src "libresoc.v:103207.3-103255.6" wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:102724.3-102772.6" + attribute \src "libresoc.v:103256.3-103304.6" wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:102644.3-102674.6" + attribute \src "libresoc.v:103176.3-103206.6" wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:102252.3-102300.6" + attribute \src "libresoc.v:102784.3-102832.6" wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:101468.3-101516.6" + attribute \src "libresoc.v:102000.3-102048.6" wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:101517.3-101565.6" + attribute \src "libresoc.v:102049.3-102097.6" wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:102056.3-102104.6" + attribute \src "libresoc.v:102588.3-102636.6" wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:102203.3-102251.6" + attribute \src "libresoc.v:102735.3-102783.6" wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:102497.3-102545.6" + attribute \src "libresoc.v:103029.3-103077.6" wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:101419.3-101467.6" + attribute \src "libresoc.v:101951.3-101999.6" wire width 13 $1\dec31_dec_sub21_function_unit[12:0] - attribute \src "libresoc.v:102773.3-102821.6" + attribute \src "libresoc.v:103305.3-103353.6" wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:102822.3-102870.6" + attribute \src "libresoc.v:103354.3-103402.6" wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:102871.3-102919.6" + attribute \src "libresoc.v:103403.3-103451.6" wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:101958.3-102006.6" + attribute \src "libresoc.v:102490.3-102538.6" wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:102105.3-102153.6" + attribute \src "libresoc.v:102637.3-102685.6" wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:102154.3-102202.6" + attribute \src "libresoc.v:102686.3-102734.6" wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:102399.3-102447.6" + attribute \src "libresoc.v:102931.3-102979.6" wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:101860.3-101908.6" + attribute \src "libresoc.v:102392.3-102440.6" wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:102546.3-102594.6" + attribute \src "libresoc.v:103078.3-103126.6" wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:102920.3-102968.6" + attribute \src "libresoc.v:103452.3-103500.6" wire width 2 $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:102007.3-102055.6" + attribute \src "libresoc.v:102539.3-102587.6" wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:102350.3-102398.6" + attribute \src "libresoc.v:102882.3-102930.6" wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:102595.3-102643.6" + attribute \src "libresoc.v:103127.3-103175.6" wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:102448.3-102496.6" + attribute \src "libresoc.v:102980.3-103028.6" wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:102301.3-102349.6" + attribute \src "libresoc.v:102833.3-102881.6" wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:101762.3-101810.6" + attribute \src "libresoc.v:102294.3-102342.6" wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:101811.3-101859.6" + attribute \src "libresoc.v:102343.3-102391.6" wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:101566.3-101614.6" + attribute \src "libresoc.v:102098.3-102146.6" wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:101615.3-101663.6" + attribute \src "libresoc.v:102147.3-102195.6" wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:101664.3-101712.6" + attribute \src "libresoc.v:102196.3-102244.6" wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:101713.3-101761.6" + attribute \src "libresoc.v:102245.3-102293.6" wire width 3 $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:101909.3-101957.6" + attribute \src "libresoc.v:102441.3-102489.6" wire width 2 $1\dec31_dec_sub21_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -157955,6 +159283,7 @@ module \dec31_dec_sub21 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub21_form attribute \enum_base_type "Function" @@ -158178,28 +159507,28 @@ module \dec31_dec_sub21 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub21_upd - attribute \src "libresoc.v:101085.7-101085.15" + attribute \src "libresoc.v:101616.7-101616.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:101085.7-101085.20" - process $proc$libresoc.v:101085$4095 + attribute \src "libresoc.v:101616.7-101616.20" + process $proc$libresoc.v:101616$4149 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:101419.3-101467.6" - process $proc$libresoc.v:101419$4063 + attribute \src "libresoc.v:101951.3-101999.6" + process $proc$libresoc.v:101951$4117 assign { } { } assign { } { } assign $0\dec31_dec_sub21_function_unit[12:0] $1\dec31_dec_sub21_function_unit[12:0] - attribute \src "libresoc.v:101420.5-101420.29" + attribute \src "libresoc.v:101952.5-101952.29" switch \initial - attribute \src "libresoc.v:101420.9-101420.17" + attribute \src "libresoc.v:101952.9-101952.17" case 1'1 case end @@ -158267,14 +159596,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[12:0] end - attribute \src "libresoc.v:101468.3-101516.6" - process $proc$libresoc.v:101468$4064 + attribute \src "libresoc.v:102000.3-102048.6" + process $proc$libresoc.v:102000$4118 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:101469.5-101469.29" + attribute \src "libresoc.v:102001.5-102001.29" switch \initial - attribute \src "libresoc.v:101469.9-101469.17" + attribute \src "libresoc.v:102001.9-102001.17" case 1'1 case end @@ -158342,14 +159671,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:101517.3-101565.6" - process $proc$libresoc.v:101517$4065 + attribute \src "libresoc.v:102049.3-102097.6" + process $proc$libresoc.v:102049$4119 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:101518.5-101518.29" + attribute \src "libresoc.v:102050.5-102050.29" switch \initial - attribute \src "libresoc.v:101518.9-101518.17" + attribute \src "libresoc.v:102050.9-102050.17" case 1'1 case end @@ -158417,14 +159746,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end - attribute \src "libresoc.v:101566.3-101614.6" - process $proc$libresoc.v:101566$4066 + attribute \src "libresoc.v:102098.3-102146.6" + process $proc$libresoc.v:102098$4120 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:101567.5-101567.29" + attribute \src "libresoc.v:102099.5-102099.29" switch \initial - attribute \src "libresoc.v:101567.9-101567.17" + attribute \src "libresoc.v:102099.9-102099.17" case 1'1 case end @@ -158492,14 +159821,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] end - attribute \src "libresoc.v:101615.3-101663.6" - process $proc$libresoc.v:101615$4067 + attribute \src "libresoc.v:102147.3-102195.6" + process $proc$libresoc.v:102147$4121 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:101616.5-101616.29" + attribute \src "libresoc.v:102148.5-102148.29" switch \initial - attribute \src "libresoc.v:101616.9-101616.17" + attribute \src "libresoc.v:102148.9-102148.17" case 1'1 case end @@ -158567,14 +159896,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] end - attribute \src "libresoc.v:101664.3-101712.6" - process $proc$libresoc.v:101664$4068 + attribute \src "libresoc.v:102196.3-102244.6" + process $proc$libresoc.v:102196$4122 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:101665.5-101665.29" + attribute \src "libresoc.v:102197.5-102197.29" switch \initial - attribute \src "libresoc.v:101665.9-101665.17" + attribute \src "libresoc.v:102197.9-102197.17" case 1'1 case end @@ -158642,14 +159971,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] end - attribute \src "libresoc.v:101713.3-101761.6" - process $proc$libresoc.v:101713$4069 + attribute \src "libresoc.v:102245.3-102293.6" + process $proc$libresoc.v:102245$4123 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:101714.5-101714.29" + attribute \src "libresoc.v:102246.5-102246.29" switch \initial - attribute \src "libresoc.v:101714.9-101714.17" + attribute \src "libresoc.v:102246.9-102246.17" case 1'1 case end @@ -158717,14 +160046,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] end - attribute \src "libresoc.v:101762.3-101810.6" - process $proc$libresoc.v:101762$4070 + attribute \src "libresoc.v:102294.3-102342.6" + process $proc$libresoc.v:102294$4124 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:101763.5-101763.29" + attribute \src "libresoc.v:102295.5-102295.29" switch \initial - attribute \src "libresoc.v:101763.9-101763.17" + attribute \src "libresoc.v:102295.9-102295.17" case 1'1 case end @@ -158792,14 +160121,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] end - attribute \src "libresoc.v:101811.3-101859.6" - process $proc$libresoc.v:101811$4071 + attribute \src "libresoc.v:102343.3-102391.6" + process $proc$libresoc.v:102343$4125 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:101812.5-101812.29" + attribute \src "libresoc.v:102344.5-102344.29" switch \initial - attribute \src "libresoc.v:101812.9-101812.17" + attribute \src "libresoc.v:102344.9-102344.17" case 1'1 case end @@ -158867,14 +160196,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] end - attribute \src "libresoc.v:101860.3-101908.6" - process $proc$libresoc.v:101860$4072 + attribute \src "libresoc.v:102392.3-102440.6" + process $proc$libresoc.v:102392$4126 assign { } { } assign { } { } assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:101861.5-101861.29" + attribute \src "libresoc.v:102393.5-102393.29" switch \initial - attribute \src "libresoc.v:101861.9-101861.17" + attribute \src "libresoc.v:102393.9-102393.17" case 1'1 case end @@ -158942,14 +160271,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:101909.3-101957.6" - process $proc$libresoc.v:101909$4073 + attribute \src "libresoc.v:102441.3-102489.6" + process $proc$libresoc.v:102441$4127 assign { } { } assign { } { } assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:101910.5-101910.29" + attribute \src "libresoc.v:102442.5-102442.29" switch \initial - attribute \src "libresoc.v:101910.9-101910.17" + attribute \src "libresoc.v:102442.9-102442.17" case 1'1 case end @@ -159017,14 +160346,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:101958.3-102006.6" - process $proc$libresoc.v:101958$4074 + attribute \src "libresoc.v:102490.3-102538.6" + process $proc$libresoc.v:102490$4128 assign { } { } assign { } { } assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:101959.5-101959.29" + attribute \src "libresoc.v:102491.5-102491.29" switch \initial - attribute \src "libresoc.v:101959.9-101959.17" + attribute \src "libresoc.v:102491.9-102491.17" case 1'1 case end @@ -159092,14 +160421,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:102007.3-102055.6" - process $proc$libresoc.v:102007$4075 + attribute \src "libresoc.v:102539.3-102587.6" + process $proc$libresoc.v:102539$4129 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:102008.5-102008.29" + attribute \src "libresoc.v:102540.5-102540.29" switch \initial - attribute \src "libresoc.v:102008.9-102008.17" + attribute \src "libresoc.v:102540.9-102540.17" case 1'1 case end @@ -159167,14 +160496,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "libresoc.v:102056.3-102104.6" - process $proc$libresoc.v:102056$4076 + attribute \src "libresoc.v:102588.3-102636.6" + process $proc$libresoc.v:102588$4130 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:102057.5-102057.29" + attribute \src "libresoc.v:102589.5-102589.29" switch \initial - attribute \src "libresoc.v:102057.9-102057.17" + attribute \src "libresoc.v:102589.9-102589.17" case 1'1 case end @@ -159242,14 +160571,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "libresoc.v:102105.3-102153.6" - process $proc$libresoc.v:102105$4077 + attribute \src "libresoc.v:102637.3-102685.6" + process $proc$libresoc.v:102637$4131 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:102106.5-102106.29" + attribute \src "libresoc.v:102638.5-102638.29" switch \initial - attribute \src "libresoc.v:102106.9-102106.17" + attribute \src "libresoc.v:102638.9-102638.17" case 1'1 case end @@ -159317,14 +160646,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "libresoc.v:102154.3-102202.6" - process $proc$libresoc.v:102154$4078 + attribute \src "libresoc.v:102686.3-102734.6" + process $proc$libresoc.v:102686$4132 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:102155.5-102155.29" + attribute \src "libresoc.v:102687.5-102687.29" switch \initial - attribute \src "libresoc.v:102155.9-102155.17" + attribute \src "libresoc.v:102687.9-102687.17" case 1'1 case end @@ -159392,14 +160721,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "libresoc.v:102203.3-102251.6" - process $proc$libresoc.v:102203$4079 + attribute \src "libresoc.v:102735.3-102783.6" + process $proc$libresoc.v:102735$4133 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:102204.5-102204.29" + attribute \src "libresoc.v:102736.5-102736.29" switch \initial - attribute \src "libresoc.v:102204.9-102204.17" + attribute \src "libresoc.v:102736.9-102736.17" case 1'1 case end @@ -159467,14 +160796,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "libresoc.v:102252.3-102300.6" - process $proc$libresoc.v:102252$4080 + attribute \src "libresoc.v:102784.3-102832.6" + process $proc$libresoc.v:102784$4134 assign { } { } assign { } { } assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:102253.5-102253.29" + attribute \src "libresoc.v:102785.5-102785.29" switch \initial - attribute \src "libresoc.v:102253.9-102253.17" + attribute \src "libresoc.v:102785.9-102785.17" case 1'1 case end @@ -159542,14 +160871,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:102301.3-102349.6" - process $proc$libresoc.v:102301$4081 + attribute \src "libresoc.v:102833.3-102881.6" + process $proc$libresoc.v:102833$4135 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:102302.5-102302.29" + attribute \src "libresoc.v:102834.5-102834.29" switch \initial - attribute \src "libresoc.v:102302.9-102302.17" + attribute \src "libresoc.v:102834.9-102834.17" case 1'1 case end @@ -159617,14 +160946,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:102350.3-102398.6" - process $proc$libresoc.v:102350$4082 + attribute \src "libresoc.v:102882.3-102930.6" + process $proc$libresoc.v:102882$4136 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:102351.5-102351.29" + attribute \src "libresoc.v:102883.5-102883.29" switch \initial - attribute \src "libresoc.v:102351.9-102351.17" + attribute \src "libresoc.v:102883.9-102883.17" case 1'1 case end @@ -159692,14 +161021,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "libresoc.v:102399.3-102447.6" - process $proc$libresoc.v:102399$4083 + attribute \src "libresoc.v:102931.3-102979.6" + process $proc$libresoc.v:102931$4137 assign { } { } assign { } { } assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:102400.5-102400.29" + attribute \src "libresoc.v:102932.5-102932.29" switch \initial - attribute \src "libresoc.v:102400.9-102400.17" + attribute \src "libresoc.v:102932.9-102932.17" case 1'1 case end @@ -159767,14 +161096,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:102448.3-102496.6" - process $proc$libresoc.v:102448$4084 + attribute \src "libresoc.v:102980.3-103028.6" + process $proc$libresoc.v:102980$4138 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:102449.5-102449.29" + attribute \src "libresoc.v:102981.5-102981.29" switch \initial - attribute \src "libresoc.v:102449.9-102449.17" + attribute \src "libresoc.v:102981.9-102981.17" case 1'1 case end @@ -159842,14 +161171,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:102497.3-102545.6" - process $proc$libresoc.v:102497$4085 + attribute \src "libresoc.v:103029.3-103077.6" + process $proc$libresoc.v:103029$4139 assign { } { } assign { } { } assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:102498.5-102498.29" + attribute \src "libresoc.v:103030.5-103030.29" switch \initial - attribute \src "libresoc.v:102498.9-102498.17" + attribute \src "libresoc.v:103030.9-103030.17" case 1'1 case end @@ -159917,14 +161246,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "libresoc.v:102546.3-102594.6" - process $proc$libresoc.v:102546$4086 + attribute \src "libresoc.v:103078.3-103126.6" + process $proc$libresoc.v:103078$4140 assign { } { } assign { } { } assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:102547.5-102547.29" + attribute \src "libresoc.v:103079.5-103079.29" switch \initial - attribute \src "libresoc.v:102547.9-102547.17" + attribute \src "libresoc.v:103079.9-103079.17" case 1'1 case end @@ -159992,14 +161321,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] end - attribute \src "libresoc.v:102595.3-102643.6" - process $proc$libresoc.v:102595$4087 + attribute \src "libresoc.v:103127.3-103175.6" + process $proc$libresoc.v:103127$4141 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:102596.5-102596.29" + attribute \src "libresoc.v:103128.5-103128.29" switch \initial - attribute \src "libresoc.v:102596.9-102596.17" + attribute \src "libresoc.v:103128.9-103128.17" case 1'1 case end @@ -160067,14 +161396,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] end - attribute \src "libresoc.v:102644.3-102674.6" - process $proc$libresoc.v:102644$4088 + attribute \src "libresoc.v:103176.3-103206.6" + process $proc$libresoc.v:103176$4142 assign { } { } assign { } { } assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:102645.5-102645.29" + attribute \src "libresoc.v:103177.5-103177.29" switch \initial - attribute \src "libresoc.v:102645.9-102645.17" + attribute \src "libresoc.v:103177.9-103177.17" case 1'1 case end @@ -160118,14 +161447,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end - attribute \src "libresoc.v:102675.3-102723.6" - process $proc$libresoc.v:102675$4089 + attribute \src "libresoc.v:103207.3-103255.6" + process $proc$libresoc.v:103207$4143 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:102676.5-102676.29" + attribute \src "libresoc.v:103208.5-103208.29" switch \initial - attribute \src "libresoc.v:102676.9-102676.17" + attribute \src "libresoc.v:103208.9-103208.17" case 1'1 case end @@ -160193,14 +161522,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] end - attribute \src "libresoc.v:102724.3-102772.6" - process $proc$libresoc.v:102724$4090 + attribute \src "libresoc.v:103256.3-103304.6" + process $proc$libresoc.v:103256$4144 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:102725.5-102725.29" + attribute \src "libresoc.v:103257.5-103257.29" switch \initial - attribute \src "libresoc.v:102725.9-102725.17" + attribute \src "libresoc.v:103257.9-103257.17" case 1'1 case end @@ -160268,14 +161597,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] end - attribute \src "libresoc.v:102773.3-102821.6" - process $proc$libresoc.v:102773$4091 + attribute \src "libresoc.v:103305.3-103353.6" + process $proc$libresoc.v:103305$4145 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:102774.5-102774.29" + attribute \src "libresoc.v:103306.5-103306.29" switch \initial - attribute \src "libresoc.v:102774.9-102774.17" + attribute \src "libresoc.v:103306.9-103306.17" case 1'1 case end @@ -160343,14 +161672,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:102822.3-102870.6" - process $proc$libresoc.v:102822$4092 + attribute \src "libresoc.v:103354.3-103402.6" + process $proc$libresoc.v:103354$4146 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:102823.5-102823.29" + attribute \src "libresoc.v:103355.5-103355.29" switch \initial - attribute \src "libresoc.v:102823.9-102823.17" + attribute \src "libresoc.v:103355.9-103355.17" case 1'1 case end @@ -160418,14 +161747,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:102871.3-102919.6" - process $proc$libresoc.v:102871$4093 + attribute \src "libresoc.v:103403.3-103451.6" + process $proc$libresoc.v:103403$4147 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:102872.5-102872.29" + attribute \src "libresoc.v:103404.5-103404.29" switch \initial - attribute \src "libresoc.v:102872.9-102872.17" + attribute \src "libresoc.v:103404.9-103404.17" case 1'1 case end @@ -160493,14 +161822,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end - attribute \src "libresoc.v:102920.3-102968.6" - process $proc$libresoc.v:102920$4094 + attribute \src "libresoc.v:103452.3-103500.6" + process $proc$libresoc.v:103452$4148 assign { } { } assign { } { } assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:102921.5-102921.29" + attribute \src "libresoc.v:103453.5-103453.29" switch \initial - attribute \src "libresoc.v:102921.9-102921.17" + attribute \src "libresoc.v:103453.9-103453.17" case 1'1 case end @@ -160570,140 +161899,140 @@ module \dec31_dec_sub21 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:102974.1-105070.10" +attribute \src "libresoc.v:103506.1-105603.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" module \dec31_dec_sub22 - attribute \src "libresoc.v:104739.3-104793.6" + attribute \src "libresoc.v:105272.3-105326.6" wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:104794.3-104848.6" + attribute \src "libresoc.v:105327.3-105381.6" wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:104079.3-104133.6" + attribute \src "libresoc.v:104612.3-104666.6" wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:104299.3-104353.6" + attribute \src "libresoc.v:104832.3-104886.6" wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:103364.3-103418.6" + attribute \src "libresoc.v:103897.3-103951.6" wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:103419.3-103473.6" + attribute \src "libresoc.v:103952.3-104006.6" wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:104024.3-104078.6" + attribute \src "libresoc.v:104557.3-104611.6" wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:104244.3-104298.6" + attribute \src "libresoc.v:104777.3-104831.6" wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:104519.3-104573.6" + attribute \src "libresoc.v:105052.3-105106.6" wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:103309.3-103363.6" + attribute \src "libresoc.v:103842.3-103896.6" wire width 13 $0\dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:104849.3-104903.6" + attribute \src "libresoc.v:105382.3-105436.6" wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:104904.3-104958.6" + attribute \src "libresoc.v:105437.3-105491.6" wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:104959.3-105013.6" + attribute \src "libresoc.v:105492.3-105546.6" wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:103914.3-103968.6" + attribute \src "libresoc.v:104447.3-104501.6" wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:104134.3-104188.6" + attribute \src "libresoc.v:104667.3-104721.6" wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:104189.3-104243.6" + attribute \src "libresoc.v:104722.3-104776.6" wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:104464.3-104518.6" + attribute \src "libresoc.v:104997.3-105051.6" wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:103804.3-103858.6" + attribute \src "libresoc.v:104337.3-104391.6" wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:104629.3-104683.6" + attribute \src "libresoc.v:105162.3-105216.6" wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:105014.3-105068.6" + attribute \src "libresoc.v:105547.3-105601.6" wire width 2 $0\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:103969.3-104023.6" + attribute \src "libresoc.v:104502.3-104556.6" wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:104409.3-104463.6" + attribute \src "libresoc.v:104942.3-104996.6" wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:104684.3-104738.6" + attribute \src "libresoc.v:105217.3-105271.6" wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:104574.3-104628.6" + attribute \src "libresoc.v:105107.3-105161.6" wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:104354.3-104408.6" + attribute \src "libresoc.v:104887.3-104941.6" wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:103694.3-103748.6" + attribute \src "libresoc.v:104227.3-104281.6" wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:103749.3-103803.6" + attribute \src "libresoc.v:104282.3-104336.6" wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:103474.3-103528.6" + attribute \src "libresoc.v:104007.3-104061.6" wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:103529.3-103583.6" + attribute \src "libresoc.v:104062.3-104116.6" wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:103584.3-103638.6" + attribute \src "libresoc.v:104117.3-104171.6" wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:103639.3-103693.6" + attribute \src "libresoc.v:104172.3-104226.6" wire width 3 $0\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:103859.3-103913.6" + attribute \src "libresoc.v:104392.3-104446.6" wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:102975.7-102975.20" + attribute \src "libresoc.v:103507.7-103507.20" wire $0\initial[0:0] - attribute \src "libresoc.v:104739.3-104793.6" + attribute \src "libresoc.v:105272.3-105326.6" wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:104794.3-104848.6" + attribute \src "libresoc.v:105327.3-105381.6" wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:104079.3-104133.6" + attribute \src "libresoc.v:104612.3-104666.6" wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:104299.3-104353.6" + attribute \src "libresoc.v:104832.3-104886.6" wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:103364.3-103418.6" + attribute \src "libresoc.v:103897.3-103951.6" wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:103419.3-103473.6" + attribute \src "libresoc.v:103952.3-104006.6" wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:104024.3-104078.6" + attribute \src "libresoc.v:104557.3-104611.6" wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:104244.3-104298.6" + attribute \src "libresoc.v:104777.3-104831.6" wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:104519.3-104573.6" + attribute \src "libresoc.v:105052.3-105106.6" wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:103309.3-103363.6" + attribute \src "libresoc.v:103842.3-103896.6" wire width 13 $1\dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:104849.3-104903.6" + attribute \src "libresoc.v:105382.3-105436.6" wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:104904.3-104958.6" + attribute \src "libresoc.v:105437.3-105491.6" wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:104959.3-105013.6" + attribute \src "libresoc.v:105492.3-105546.6" wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:103914.3-103968.6" + attribute \src "libresoc.v:104447.3-104501.6" wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:104134.3-104188.6" + attribute \src "libresoc.v:104667.3-104721.6" wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:104189.3-104243.6" + attribute \src "libresoc.v:104722.3-104776.6" wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:104464.3-104518.6" + attribute \src "libresoc.v:104997.3-105051.6" wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:103804.3-103858.6" + attribute \src "libresoc.v:104337.3-104391.6" wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:104629.3-104683.6" + attribute \src "libresoc.v:105162.3-105216.6" wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:105014.3-105068.6" + attribute \src "libresoc.v:105547.3-105601.6" wire width 2 $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:103969.3-104023.6" + attribute \src "libresoc.v:104502.3-104556.6" wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:104409.3-104463.6" + attribute \src "libresoc.v:104942.3-104996.6" wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:104684.3-104738.6" + attribute \src "libresoc.v:105217.3-105271.6" wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:104574.3-104628.6" + attribute \src "libresoc.v:105107.3-105161.6" wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:104354.3-104408.6" + attribute \src "libresoc.v:104887.3-104941.6" wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:103694.3-103748.6" + attribute \src "libresoc.v:104227.3-104281.6" wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:103749.3-103803.6" + attribute \src "libresoc.v:104282.3-104336.6" wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:103474.3-103528.6" + attribute \src "libresoc.v:104007.3-104061.6" wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:103529.3-103583.6" + attribute \src "libresoc.v:104062.3-104116.6" wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:103584.3-103638.6" + attribute \src "libresoc.v:104117.3-104171.6" wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:103639.3-103693.6" + attribute \src "libresoc.v:104172.3-104226.6" wire width 3 $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:103859.3-103913.6" + attribute \src "libresoc.v:104392.3-104446.6" wire width 2 $1\dec31_dec_sub22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -160779,6 +162108,7 @@ module \dec31_dec_sub22 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub22_form attribute \enum_base_type "Function" @@ -161002,28 +162332,28 @@ module \dec31_dec_sub22 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub22_upd - attribute \src "libresoc.v:102975.7-102975.15" + attribute \src "libresoc.v:103507.7-103507.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:102975.7-102975.20" - process $proc$libresoc.v:102975$4128 + attribute \src "libresoc.v:103507.7-103507.20" + process $proc$libresoc.v:103507$4182 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:103309.3-103363.6" - process $proc$libresoc.v:103309$4096 + attribute \src "libresoc.v:103842.3-103896.6" + process $proc$libresoc.v:103842$4150 assign { } { } assign { } { } assign $0\dec31_dec_sub22_function_unit[12:0] $1\dec31_dec_sub22_function_unit[12:0] - attribute \src "libresoc.v:103310.5-103310.29" + attribute \src "libresoc.v:103843.5-103843.29" switch \initial - attribute \src "libresoc.v:103310.9-103310.17" + attribute \src "libresoc.v:103843.9-103843.17" case 1'1 case end @@ -161099,14 +162429,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[12:0] end - attribute \src "libresoc.v:103364.3-103418.6" - process $proc$libresoc.v:103364$4097 + attribute \src "libresoc.v:103897.3-103951.6" + process $proc$libresoc.v:103897$4151 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:103365.5-103365.29" + attribute \src "libresoc.v:103898.5-103898.29" switch \initial - attribute \src "libresoc.v:103365.9-103365.17" + attribute \src "libresoc.v:103898.9-103898.17" case 1'1 case end @@ -161182,14 +162512,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:103419.3-103473.6" - process $proc$libresoc.v:103419$4098 + attribute \src "libresoc.v:103952.3-104006.6" + process $proc$libresoc.v:103952$4152 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:103420.5-103420.29" + attribute \src "libresoc.v:103953.5-103953.29" switch \initial - attribute \src "libresoc.v:103420.9-103420.17" + attribute \src "libresoc.v:103953.9-103953.17" case 1'1 case end @@ -161265,14 +162595,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:103474.3-103528.6" - process $proc$libresoc.v:103474$4099 + attribute \src "libresoc.v:104007.3-104061.6" + process $proc$libresoc.v:104007$4153 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:103475.5-103475.29" + attribute \src "libresoc.v:104008.5-104008.29" switch \initial - attribute \src "libresoc.v:103475.9-103475.17" + attribute \src "libresoc.v:104008.9-104008.17" case 1'1 case end @@ -161348,14 +162678,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] end - attribute \src "libresoc.v:103529.3-103583.6" - process $proc$libresoc.v:103529$4100 + attribute \src "libresoc.v:104062.3-104116.6" + process $proc$libresoc.v:104062$4154 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:103530.5-103530.29" + attribute \src "libresoc.v:104063.5-104063.29" switch \initial - attribute \src "libresoc.v:103530.9-103530.17" + attribute \src "libresoc.v:104063.9-104063.17" case 1'1 case end @@ -161431,14 +162761,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] end - attribute \src "libresoc.v:103584.3-103638.6" - process $proc$libresoc.v:103584$4101 + attribute \src "libresoc.v:104117.3-104171.6" + process $proc$libresoc.v:104117$4155 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:103585.5-103585.29" + attribute \src "libresoc.v:104118.5-104118.29" switch \initial - attribute \src "libresoc.v:103585.9-103585.17" + attribute \src "libresoc.v:104118.9-104118.17" case 1'1 case end @@ -161514,14 +162844,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] end - attribute \src "libresoc.v:103639.3-103693.6" - process $proc$libresoc.v:103639$4102 + attribute \src "libresoc.v:104172.3-104226.6" + process $proc$libresoc.v:104172$4156 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:103640.5-103640.29" + attribute \src "libresoc.v:104173.5-104173.29" switch \initial - attribute \src "libresoc.v:103640.9-103640.17" + attribute \src "libresoc.v:104173.9-104173.17" case 1'1 case end @@ -161597,14 +162927,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] end - attribute \src "libresoc.v:103694.3-103748.6" - process $proc$libresoc.v:103694$4103 + attribute \src "libresoc.v:104227.3-104281.6" + process $proc$libresoc.v:104227$4157 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:103695.5-103695.29" + attribute \src "libresoc.v:104228.5-104228.29" switch \initial - attribute \src "libresoc.v:103695.9-103695.17" + attribute \src "libresoc.v:104228.9-104228.17" case 1'1 case end @@ -161680,14 +163010,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] end - attribute \src "libresoc.v:103749.3-103803.6" - process $proc$libresoc.v:103749$4104 + attribute \src "libresoc.v:104282.3-104336.6" + process $proc$libresoc.v:104282$4158 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:103750.5-103750.29" + attribute \src "libresoc.v:104283.5-104283.29" switch \initial - attribute \src "libresoc.v:103750.9-103750.17" + attribute \src "libresoc.v:104283.9-104283.17" case 1'1 case end @@ -161763,14 +163093,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] end - attribute \src "libresoc.v:103804.3-103858.6" - process $proc$libresoc.v:103804$4105 + attribute \src "libresoc.v:104337.3-104391.6" + process $proc$libresoc.v:104337$4159 assign { } { } assign { } { } assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:103805.5-103805.29" + attribute \src "libresoc.v:104338.5-104338.29" switch \initial - attribute \src "libresoc.v:103805.9-103805.17" + attribute \src "libresoc.v:104338.9-104338.17" case 1'1 case end @@ -161846,14 +163176,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:103859.3-103913.6" - process $proc$libresoc.v:103859$4106 + attribute \src "libresoc.v:104392.3-104446.6" + process $proc$libresoc.v:104392$4160 assign { } { } assign { } { } assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:103860.5-103860.29" + attribute \src "libresoc.v:104393.5-104393.29" switch \initial - attribute \src "libresoc.v:103860.9-103860.17" + attribute \src "libresoc.v:104393.9-104393.17" case 1'1 case end @@ -161929,14 +163259,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:103914.3-103968.6" - process $proc$libresoc.v:103914$4107 + attribute \src "libresoc.v:104447.3-104501.6" + process $proc$libresoc.v:104447$4161 assign { } { } assign { } { } assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:103915.5-103915.29" + attribute \src "libresoc.v:104448.5-104448.29" switch \initial - attribute \src "libresoc.v:103915.9-103915.17" + attribute \src "libresoc.v:104448.9-104448.17" case 1'1 case end @@ -162012,14 +163342,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:103969.3-104023.6" - process $proc$libresoc.v:103969$4108 + attribute \src "libresoc.v:104502.3-104556.6" + process $proc$libresoc.v:104502$4162 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:103970.5-103970.29" + attribute \src "libresoc.v:104503.5-104503.29" switch \initial - attribute \src "libresoc.v:103970.9-103970.17" + attribute \src "libresoc.v:104503.9-104503.17" case 1'1 case end @@ -162095,14 +163425,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:104024.3-104078.6" - process $proc$libresoc.v:104024$4109 + attribute \src "libresoc.v:104557.3-104611.6" + process $proc$libresoc.v:104557$4163 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:104025.5-104025.29" + attribute \src "libresoc.v:104558.5-104558.29" switch \initial - attribute \src "libresoc.v:104025.9-104025.17" + attribute \src "libresoc.v:104558.9-104558.17" case 1'1 case end @@ -162178,14 +163508,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "libresoc.v:104079.3-104133.6" - process $proc$libresoc.v:104079$4110 + attribute \src "libresoc.v:104612.3-104666.6" + process $proc$libresoc.v:104612$4164 assign { } { } assign { } { } assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:104080.5-104080.29" + attribute \src "libresoc.v:104613.5-104613.29" switch \initial - attribute \src "libresoc.v:104080.9-104080.17" + attribute \src "libresoc.v:104613.9-104613.17" case 1'1 case end @@ -162261,14 +163591,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "libresoc.v:104134.3-104188.6" - process $proc$libresoc.v:104134$4111 + attribute \src "libresoc.v:104667.3-104721.6" + process $proc$libresoc.v:104667$4165 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:104135.5-104135.29" + attribute \src "libresoc.v:104668.5-104668.29" switch \initial - attribute \src "libresoc.v:104135.9-104135.17" + attribute \src "libresoc.v:104668.9-104668.17" case 1'1 case end @@ -162344,14 +163674,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:104189.3-104243.6" - process $proc$libresoc.v:104189$4112 + attribute \src "libresoc.v:104722.3-104776.6" + process $proc$libresoc.v:104722$4166 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:104190.5-104190.29" + attribute \src "libresoc.v:104723.5-104723.29" switch \initial - attribute \src "libresoc.v:104190.9-104190.17" + attribute \src "libresoc.v:104723.9-104723.17" case 1'1 case end @@ -162427,14 +163757,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:104244.3-104298.6" - process $proc$libresoc.v:104244$4113 + attribute \src "libresoc.v:104777.3-104831.6" + process $proc$libresoc.v:104777$4167 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:104245.5-104245.29" + attribute \src "libresoc.v:104778.5-104778.29" switch \initial - attribute \src "libresoc.v:104245.9-104245.17" + attribute \src "libresoc.v:104778.9-104778.17" case 1'1 case end @@ -162510,14 +163840,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:104299.3-104353.6" - process $proc$libresoc.v:104299$4114 + attribute \src "libresoc.v:104832.3-104886.6" + process $proc$libresoc.v:104832$4168 assign { } { } assign { } { } assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:104300.5-104300.29" + attribute \src "libresoc.v:104833.5-104833.29" switch \initial - attribute \src "libresoc.v:104300.9-104300.17" + attribute \src "libresoc.v:104833.9-104833.17" case 1'1 case end @@ -162593,14 +163923,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:104354.3-104408.6" - process $proc$libresoc.v:104354$4115 + attribute \src "libresoc.v:104887.3-104941.6" + process $proc$libresoc.v:104887$4169 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:104355.5-104355.29" + attribute \src "libresoc.v:104888.5-104888.29" switch \initial - attribute \src "libresoc.v:104355.9-104355.17" + attribute \src "libresoc.v:104888.9-104888.17" case 1'1 case end @@ -162676,14 +164006,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:104409.3-104463.6" - process $proc$libresoc.v:104409$4116 + attribute \src "libresoc.v:104942.3-104996.6" + process $proc$libresoc.v:104942$4170 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:104410.5-104410.29" + attribute \src "libresoc.v:104943.5-104943.29" switch \initial - attribute \src "libresoc.v:104410.9-104410.17" + attribute \src "libresoc.v:104943.9-104943.17" case 1'1 case end @@ -162759,14 +164089,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "libresoc.v:104464.3-104518.6" - process $proc$libresoc.v:104464$4117 + attribute \src "libresoc.v:104997.3-105051.6" + process $proc$libresoc.v:104997$4171 assign { } { } assign { } { } assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:104465.5-104465.29" + attribute \src "libresoc.v:104998.5-104998.29" switch \initial - attribute \src "libresoc.v:104465.9-104465.17" + attribute \src "libresoc.v:104998.9-104998.17" case 1'1 case end @@ -162842,14 +164172,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:104519.3-104573.6" - process $proc$libresoc.v:104519$4118 + attribute \src "libresoc.v:105052.3-105106.6" + process $proc$libresoc.v:105052$4172 assign { } { } assign { } { } assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:104520.5-104520.29" + attribute \src "libresoc.v:105053.5-105053.29" switch \initial - attribute \src "libresoc.v:104520.9-104520.17" + attribute \src "libresoc.v:105053.9-105053.17" case 1'1 case end @@ -162925,14 +164255,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "libresoc.v:104574.3-104628.6" - process $proc$libresoc.v:104574$4119 + attribute \src "libresoc.v:105107.3-105161.6" + process $proc$libresoc.v:105107$4173 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:104575.5-104575.29" + attribute \src "libresoc.v:105108.5-105108.29" switch \initial - attribute \src "libresoc.v:104575.9-104575.17" + attribute \src "libresoc.v:105108.9-105108.17" case 1'1 case end @@ -163008,14 +164338,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:104629.3-104683.6" - process $proc$libresoc.v:104629$4120 + attribute \src "libresoc.v:105162.3-105216.6" + process $proc$libresoc.v:105162$4174 assign { } { } assign { } { } assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:104630.5-104630.29" + attribute \src "libresoc.v:105163.5-105163.29" switch \initial - attribute \src "libresoc.v:104630.9-104630.17" + attribute \src "libresoc.v:105163.9-105163.17" case 1'1 case end @@ -163091,14 +164421,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "libresoc.v:104684.3-104738.6" - process $proc$libresoc.v:104684$4121 + attribute \src "libresoc.v:105217.3-105271.6" + process $proc$libresoc.v:105217$4175 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:104685.5-104685.29" + attribute \src "libresoc.v:105218.5-105218.29" switch \initial - attribute \src "libresoc.v:104685.9-104685.17" + attribute \src "libresoc.v:105218.9-105218.17" case 1'1 case end @@ -163174,14 +164504,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "libresoc.v:104739.3-104793.6" - process $proc$libresoc.v:104739$4122 + attribute \src "libresoc.v:105272.3-105326.6" + process $proc$libresoc.v:105272$4176 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:104740.5-104740.29" + attribute \src "libresoc.v:105273.5-105273.29" switch \initial - attribute \src "libresoc.v:104740.9-104740.17" + attribute \src "libresoc.v:105273.9-105273.17" case 1'1 case end @@ -163257,14 +164587,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] end - attribute \src "libresoc.v:104794.3-104848.6" - process $proc$libresoc.v:104794$4123 + attribute \src "libresoc.v:105327.3-105381.6" + process $proc$libresoc.v:105327$4177 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:104795.5-104795.29" + attribute \src "libresoc.v:105328.5-105328.29" switch \initial - attribute \src "libresoc.v:104795.9-104795.17" + attribute \src "libresoc.v:105328.9-105328.17" case 1'1 case end @@ -163340,14 +164670,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] end - attribute \src "libresoc.v:104849.3-104903.6" - process $proc$libresoc.v:104849$4124 + attribute \src "libresoc.v:105382.3-105436.6" + process $proc$libresoc.v:105382$4178 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:104850.5-104850.29" + attribute \src "libresoc.v:105383.5-105383.29" switch \initial - attribute \src "libresoc.v:104850.9-104850.17" + attribute \src "libresoc.v:105383.9-105383.17" case 1'1 case end @@ -163423,14 +164753,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:104904.3-104958.6" - process $proc$libresoc.v:104904$4125 + attribute \src "libresoc.v:105437.3-105491.6" + process $proc$libresoc.v:105437$4179 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:104905.5-104905.29" + attribute \src "libresoc.v:105438.5-105438.29" switch \initial - attribute \src "libresoc.v:104905.9-104905.17" + attribute \src "libresoc.v:105438.9-105438.17" case 1'1 case end @@ -163506,14 +164836,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:104959.3-105013.6" - process $proc$libresoc.v:104959$4126 + attribute \src "libresoc.v:105492.3-105546.6" + process $proc$libresoc.v:105492$4180 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:104960.5-104960.29" + attribute \src "libresoc.v:105493.5-105493.29" switch \initial - attribute \src "libresoc.v:104960.9-104960.17" + attribute \src "libresoc.v:105493.9-105493.17" case 1'1 case end @@ -163589,14 +164919,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "libresoc.v:105014.3-105068.6" - process $proc$libresoc.v:105014$4127 + attribute \src "libresoc.v:105547.3-105601.6" + process $proc$libresoc.v:105547$4181 assign { } { } assign { } { } assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:105015.5-105015.29" + attribute \src "libresoc.v:105548.5-105548.29" switch \initial - attribute \src "libresoc.v:105015.9-105015.17" + attribute \src "libresoc.v:105548.9-105548.17" case 1'1 case end @@ -163674,140 +165004,140 @@ module \dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:105074.1-106978.10" +attribute \src "libresoc.v:105607.1-107512.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" module \dec31_dec_sub23 - attribute \src "libresoc.v:106683.3-106731.6" + attribute \src "libresoc.v:107217.3-107265.6" wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:106732.3-106780.6" + attribute \src "libresoc.v:107266.3-107314.6" wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:106095.3-106143.6" + attribute \src "libresoc.v:106629.3-106677.6" wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:106291.3-106339.6" + attribute \src "libresoc.v:106825.3-106873.6" wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:105458.3-105506.6" + attribute \src "libresoc.v:105992.3-106040.6" wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:105507.3-105555.6" + attribute \src "libresoc.v:106041.3-106089.6" wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:106046.3-106094.6" + attribute \src "libresoc.v:106580.3-106628.6" wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:106242.3-106290.6" + attribute \src "libresoc.v:106776.3-106824.6" wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:106487.3-106535.6" + attribute \src "libresoc.v:107021.3-107069.6" wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:105409.3-105457.6" + attribute \src "libresoc.v:105943.3-105991.6" wire width 13 $0\dec31_dec_sub23_function_unit[12:0] - attribute \src "libresoc.v:106781.3-106829.6" + attribute \src "libresoc.v:107315.3-107363.6" wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:106830.3-106878.6" + attribute \src "libresoc.v:107364.3-107412.6" wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:106879.3-106927.6" + attribute \src "libresoc.v:107413.3-107461.6" wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:105948.3-105996.6" + attribute \src "libresoc.v:106482.3-106530.6" wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:106144.3-106192.6" + attribute \src "libresoc.v:106678.3-106726.6" wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:106193.3-106241.6" + attribute \src "libresoc.v:106727.3-106775.6" wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:106438.3-106486.6" + attribute \src "libresoc.v:106972.3-107020.6" wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:105850.3-105898.6" + attribute \src "libresoc.v:106384.3-106432.6" wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:106585.3-106633.6" + attribute \src "libresoc.v:107119.3-107167.6" wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:106928.3-106976.6" + attribute \src "libresoc.v:107462.3-107510.6" wire width 2 $0\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:105997.3-106045.6" + attribute \src "libresoc.v:106531.3-106579.6" wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:106389.3-106437.6" + attribute \src "libresoc.v:106923.3-106971.6" wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:106634.3-106682.6" + attribute \src "libresoc.v:107168.3-107216.6" wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:106536.3-106584.6" + attribute \src "libresoc.v:107070.3-107118.6" wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:106340.3-106388.6" + attribute \src "libresoc.v:106874.3-106922.6" wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:105752.3-105800.6" + attribute \src "libresoc.v:106286.3-106334.6" wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:105801.3-105849.6" + attribute \src "libresoc.v:106335.3-106383.6" wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:105556.3-105604.6" + attribute \src "libresoc.v:106090.3-106138.6" wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:105605.3-105653.6" + attribute \src "libresoc.v:106139.3-106187.6" wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:105654.3-105702.6" + attribute \src "libresoc.v:106188.3-106236.6" wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:105703.3-105751.6" + attribute \src "libresoc.v:106237.3-106285.6" wire width 3 $0\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:105899.3-105947.6" + attribute \src "libresoc.v:106433.3-106481.6" wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:105075.7-105075.20" + attribute \src "libresoc.v:105608.7-105608.20" wire $0\initial[0:0] - attribute \src "libresoc.v:106683.3-106731.6" + attribute \src "libresoc.v:107217.3-107265.6" wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:106732.3-106780.6" + attribute \src "libresoc.v:107266.3-107314.6" wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:106095.3-106143.6" + attribute \src "libresoc.v:106629.3-106677.6" wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:106291.3-106339.6" + attribute \src "libresoc.v:106825.3-106873.6" wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:105458.3-105506.6" + attribute \src "libresoc.v:105992.3-106040.6" wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:105507.3-105555.6" + attribute \src "libresoc.v:106041.3-106089.6" wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:106046.3-106094.6" + attribute \src "libresoc.v:106580.3-106628.6" wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:106242.3-106290.6" + attribute \src "libresoc.v:106776.3-106824.6" wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:106487.3-106535.6" + attribute \src "libresoc.v:107021.3-107069.6" wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:105409.3-105457.6" + attribute \src "libresoc.v:105943.3-105991.6" wire width 13 $1\dec31_dec_sub23_function_unit[12:0] - attribute \src "libresoc.v:106781.3-106829.6" + attribute \src "libresoc.v:107315.3-107363.6" wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:106830.3-106878.6" + attribute \src "libresoc.v:107364.3-107412.6" wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:106879.3-106927.6" + attribute \src "libresoc.v:107413.3-107461.6" wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:105948.3-105996.6" + attribute \src "libresoc.v:106482.3-106530.6" wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:106144.3-106192.6" + attribute \src "libresoc.v:106678.3-106726.6" wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:106193.3-106241.6" + attribute \src "libresoc.v:106727.3-106775.6" wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:106438.3-106486.6" + attribute \src "libresoc.v:106972.3-107020.6" wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:105850.3-105898.6" + attribute \src "libresoc.v:106384.3-106432.6" wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:106585.3-106633.6" + attribute \src "libresoc.v:107119.3-107167.6" wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:106928.3-106976.6" + attribute \src "libresoc.v:107462.3-107510.6" wire width 2 $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:105997.3-106045.6" + attribute \src "libresoc.v:106531.3-106579.6" wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:106389.3-106437.6" + attribute \src "libresoc.v:106923.3-106971.6" wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:106634.3-106682.6" + attribute \src "libresoc.v:107168.3-107216.6" wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:106536.3-106584.6" + attribute \src "libresoc.v:107070.3-107118.6" wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:106340.3-106388.6" + attribute \src "libresoc.v:106874.3-106922.6" wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:105752.3-105800.6" + attribute \src "libresoc.v:106286.3-106334.6" wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:105801.3-105849.6" + attribute \src "libresoc.v:106335.3-106383.6" wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:105556.3-105604.6" + attribute \src "libresoc.v:106090.3-106138.6" wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:105605.3-105653.6" + attribute \src "libresoc.v:106139.3-106187.6" wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:105654.3-105702.6" + attribute \src "libresoc.v:106188.3-106236.6" wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:105703.3-105751.6" + attribute \src "libresoc.v:106237.3-106285.6" wire width 3 $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:105899.3-105947.6" + attribute \src "libresoc.v:106433.3-106481.6" wire width 2 $1\dec31_dec_sub23_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -163883,6 +165213,7 @@ module \dec31_dec_sub23 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub23_form attribute \enum_base_type "Function" @@ -164106,28 +165437,28 @@ module \dec31_dec_sub23 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub23_upd - attribute \src "libresoc.v:105075.7-105075.15" + attribute \src "libresoc.v:105608.7-105608.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:105075.7-105075.20" - process $proc$libresoc.v:105075$4161 + attribute \src "libresoc.v:105608.7-105608.20" + process $proc$libresoc.v:105608$4215 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:105409.3-105457.6" - process $proc$libresoc.v:105409$4129 + attribute \src "libresoc.v:105943.3-105991.6" + process $proc$libresoc.v:105943$4183 assign { } { } assign { } { } assign $0\dec31_dec_sub23_function_unit[12:0] $1\dec31_dec_sub23_function_unit[12:0] - attribute \src "libresoc.v:105410.5-105410.29" + attribute \src "libresoc.v:105944.5-105944.29" switch \initial - attribute \src "libresoc.v:105410.9-105410.17" + attribute \src "libresoc.v:105944.9-105944.17" case 1'1 case end @@ -164195,14 +165526,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[12:0] end - attribute \src "libresoc.v:105458.3-105506.6" - process $proc$libresoc.v:105458$4130 + attribute \src "libresoc.v:105992.3-106040.6" + process $proc$libresoc.v:105992$4184 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:105459.5-105459.29" + attribute \src "libresoc.v:105993.5-105993.29" switch \initial - attribute \src "libresoc.v:105459.9-105459.17" + attribute \src "libresoc.v:105993.9-105993.17" case 1'1 case end @@ -164270,14 +165601,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:105507.3-105555.6" - process $proc$libresoc.v:105507$4131 + attribute \src "libresoc.v:106041.3-106089.6" + process $proc$libresoc.v:106041$4185 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:105508.5-105508.29" + attribute \src "libresoc.v:106042.5-106042.29" switch \initial - attribute \src "libresoc.v:105508.9-105508.17" + attribute \src "libresoc.v:106042.9-106042.17" case 1'1 case end @@ -164345,14 +165676,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] end - attribute \src "libresoc.v:105556.3-105604.6" - process $proc$libresoc.v:105556$4132 + attribute \src "libresoc.v:106090.3-106138.6" + process $proc$libresoc.v:106090$4186 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:105557.5-105557.29" + attribute \src "libresoc.v:106091.5-106091.29" switch \initial - attribute \src "libresoc.v:105557.9-105557.17" + attribute \src "libresoc.v:106091.9-106091.17" case 1'1 case end @@ -164420,14 +165751,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] end - attribute \src "libresoc.v:105605.3-105653.6" - process $proc$libresoc.v:105605$4133 + attribute \src "libresoc.v:106139.3-106187.6" + process $proc$libresoc.v:106139$4187 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:105606.5-105606.29" + attribute \src "libresoc.v:106140.5-106140.29" switch \initial - attribute \src "libresoc.v:105606.9-105606.17" + attribute \src "libresoc.v:106140.9-106140.17" case 1'1 case end @@ -164495,14 +165826,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] end - attribute \src "libresoc.v:105654.3-105702.6" - process $proc$libresoc.v:105654$4134 + attribute \src "libresoc.v:106188.3-106236.6" + process $proc$libresoc.v:106188$4188 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:105655.5-105655.29" + attribute \src "libresoc.v:106189.5-106189.29" switch \initial - attribute \src "libresoc.v:105655.9-105655.17" + attribute \src "libresoc.v:106189.9-106189.17" case 1'1 case end @@ -164570,14 +165901,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] end - attribute \src "libresoc.v:105703.3-105751.6" - process $proc$libresoc.v:105703$4135 + attribute \src "libresoc.v:106237.3-106285.6" + process $proc$libresoc.v:106237$4189 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:105704.5-105704.29" + attribute \src "libresoc.v:106238.5-106238.29" switch \initial - attribute \src "libresoc.v:105704.9-105704.17" + attribute \src "libresoc.v:106238.9-106238.17" case 1'1 case end @@ -164645,14 +165976,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] end - attribute \src "libresoc.v:105752.3-105800.6" - process $proc$libresoc.v:105752$4136 + attribute \src "libresoc.v:106286.3-106334.6" + process $proc$libresoc.v:106286$4190 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:105753.5-105753.29" + attribute \src "libresoc.v:106287.5-106287.29" switch \initial - attribute \src "libresoc.v:105753.9-105753.17" + attribute \src "libresoc.v:106287.9-106287.17" case 1'1 case end @@ -164720,14 +166051,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] end - attribute \src "libresoc.v:105801.3-105849.6" - process $proc$libresoc.v:105801$4137 + attribute \src "libresoc.v:106335.3-106383.6" + process $proc$libresoc.v:106335$4191 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:105802.5-105802.29" + attribute \src "libresoc.v:106336.5-106336.29" switch \initial - attribute \src "libresoc.v:105802.9-105802.17" + attribute \src "libresoc.v:106336.9-106336.17" case 1'1 case end @@ -164795,14 +166126,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] end - attribute \src "libresoc.v:105850.3-105898.6" - process $proc$libresoc.v:105850$4138 + attribute \src "libresoc.v:106384.3-106432.6" + process $proc$libresoc.v:106384$4192 assign { } { } assign { } { } assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:105851.5-105851.29" + attribute \src "libresoc.v:106385.5-106385.29" switch \initial - attribute \src "libresoc.v:105851.9-105851.17" + attribute \src "libresoc.v:106385.9-106385.17" case 1'1 case end @@ -164870,14 +166201,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:105899.3-105947.6" - process $proc$libresoc.v:105899$4139 + attribute \src "libresoc.v:106433.3-106481.6" + process $proc$libresoc.v:106433$4193 assign { } { } assign { } { } assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:105900.5-105900.29" + attribute \src "libresoc.v:106434.5-106434.29" switch \initial - attribute \src "libresoc.v:105900.9-105900.17" + attribute \src "libresoc.v:106434.9-106434.17" case 1'1 case end @@ -164945,14 +166276,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:105948.3-105996.6" - process $proc$libresoc.v:105948$4140 + attribute \src "libresoc.v:106482.3-106530.6" + process $proc$libresoc.v:106482$4194 assign { } { } assign { } { } assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:105949.5-105949.29" + attribute \src "libresoc.v:106483.5-106483.29" switch \initial - attribute \src "libresoc.v:105949.9-105949.17" + attribute \src "libresoc.v:106483.9-106483.17" case 1'1 case end @@ -165020,14 +166351,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:105997.3-106045.6" - process $proc$libresoc.v:105997$4141 + attribute \src "libresoc.v:106531.3-106579.6" + process $proc$libresoc.v:106531$4195 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:105998.5-105998.29" + attribute \src "libresoc.v:106532.5-106532.29" switch \initial - attribute \src "libresoc.v:105998.9-105998.17" + attribute \src "libresoc.v:106532.9-106532.17" case 1'1 case end @@ -165095,14 +166426,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "libresoc.v:106046.3-106094.6" - process $proc$libresoc.v:106046$4142 + attribute \src "libresoc.v:106580.3-106628.6" + process $proc$libresoc.v:106580$4196 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:106047.5-106047.29" + attribute \src "libresoc.v:106581.5-106581.29" switch \initial - attribute \src "libresoc.v:106047.9-106047.17" + attribute \src "libresoc.v:106581.9-106581.17" case 1'1 case end @@ -165170,14 +166501,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:106095.3-106143.6" - process $proc$libresoc.v:106095$4143 + attribute \src "libresoc.v:106629.3-106677.6" + process $proc$libresoc.v:106629$4197 assign { } { } assign { } { } assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:106096.5-106096.29" + attribute \src "libresoc.v:106630.5-106630.29" switch \initial - attribute \src "libresoc.v:106096.9-106096.17" + attribute \src "libresoc.v:106630.9-106630.17" case 1'1 case end @@ -165245,14 +166576,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "libresoc.v:106144.3-106192.6" - process $proc$libresoc.v:106144$4144 + attribute \src "libresoc.v:106678.3-106726.6" + process $proc$libresoc.v:106678$4198 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:106145.5-106145.29" + attribute \src "libresoc.v:106679.5-106679.29" switch \initial - attribute \src "libresoc.v:106145.9-106145.17" + attribute \src "libresoc.v:106679.9-106679.17" case 1'1 case end @@ -165320,14 +166651,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "libresoc.v:106193.3-106241.6" - process $proc$libresoc.v:106193$4145 + attribute \src "libresoc.v:106727.3-106775.6" + process $proc$libresoc.v:106727$4199 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:106194.5-106194.29" + attribute \src "libresoc.v:106728.5-106728.29" switch \initial - attribute \src "libresoc.v:106194.9-106194.17" + attribute \src "libresoc.v:106728.9-106728.17" case 1'1 case end @@ -165395,14 +166726,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:106242.3-106290.6" - process $proc$libresoc.v:106242$4146 + attribute \src "libresoc.v:106776.3-106824.6" + process $proc$libresoc.v:106776$4200 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:106243.5-106243.29" + attribute \src "libresoc.v:106777.5-106777.29" switch \initial - attribute \src "libresoc.v:106243.9-106243.17" + attribute \src "libresoc.v:106777.9-106777.17" case 1'1 case end @@ -165470,14 +166801,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "libresoc.v:106291.3-106339.6" - process $proc$libresoc.v:106291$4147 + attribute \src "libresoc.v:106825.3-106873.6" + process $proc$libresoc.v:106825$4201 assign { } { } assign { } { } assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:106292.5-106292.29" + attribute \src "libresoc.v:106826.5-106826.29" switch \initial - attribute \src "libresoc.v:106292.9-106292.17" + attribute \src "libresoc.v:106826.9-106826.17" case 1'1 case end @@ -165545,14 +166876,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:106340.3-106388.6" - process $proc$libresoc.v:106340$4148 + attribute \src "libresoc.v:106874.3-106922.6" + process $proc$libresoc.v:106874$4202 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:106341.5-106341.29" + attribute \src "libresoc.v:106875.5-106875.29" switch \initial - attribute \src "libresoc.v:106341.9-106341.17" + attribute \src "libresoc.v:106875.9-106875.17" case 1'1 case end @@ -165620,14 +166951,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:106389.3-106437.6" - process $proc$libresoc.v:106389$4149 + attribute \src "libresoc.v:106923.3-106971.6" + process $proc$libresoc.v:106923$4203 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:106390.5-106390.29" + attribute \src "libresoc.v:106924.5-106924.29" switch \initial - attribute \src "libresoc.v:106390.9-106390.17" + attribute \src "libresoc.v:106924.9-106924.17" case 1'1 case end @@ -165695,14 +167026,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end - attribute \src "libresoc.v:106438.3-106486.6" - process $proc$libresoc.v:106438$4150 + attribute \src "libresoc.v:106972.3-107020.6" + process $proc$libresoc.v:106972$4204 assign { } { } assign { } { } assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:106439.5-106439.29" + attribute \src "libresoc.v:106973.5-106973.29" switch \initial - attribute \src "libresoc.v:106439.9-106439.17" + attribute \src "libresoc.v:106973.9-106973.17" case 1'1 case end @@ -165770,14 +167101,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:106487.3-106535.6" - process $proc$libresoc.v:106487$4151 + attribute \src "libresoc.v:107021.3-107069.6" + process $proc$libresoc.v:107021$4205 assign { } { } assign { } { } assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:106488.5-106488.29" + attribute \src "libresoc.v:107022.5-107022.29" switch \initial - attribute \src "libresoc.v:106488.9-106488.17" + attribute \src "libresoc.v:107022.9-107022.17" case 1'1 case end @@ -165845,14 +167176,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end - attribute \src "libresoc.v:106536.3-106584.6" - process $proc$libresoc.v:106536$4152 + attribute \src "libresoc.v:107070.3-107118.6" + process $proc$libresoc.v:107070$4206 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:106537.5-106537.29" + attribute \src "libresoc.v:107071.5-107071.29" switch \initial - attribute \src "libresoc.v:106537.9-106537.17" + attribute \src "libresoc.v:107071.9-107071.17" case 1'1 case end @@ -165920,14 +167251,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:106585.3-106633.6" - process $proc$libresoc.v:106585$4153 + attribute \src "libresoc.v:107119.3-107167.6" + process $proc$libresoc.v:107119$4207 assign { } { } assign { } { } assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:106586.5-106586.29" + attribute \src "libresoc.v:107120.5-107120.29" switch \initial - attribute \src "libresoc.v:106586.9-106586.17" + attribute \src "libresoc.v:107120.9-107120.17" case 1'1 case end @@ -165995,14 +167326,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end - attribute \src "libresoc.v:106634.3-106682.6" - process $proc$libresoc.v:106634$4154 + attribute \src "libresoc.v:107168.3-107216.6" + process $proc$libresoc.v:107168$4208 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:106635.5-106635.29" + attribute \src "libresoc.v:107169.5-107169.29" switch \initial - attribute \src "libresoc.v:106635.9-106635.17" + attribute \src "libresoc.v:107169.9-107169.17" case 1'1 case end @@ -166070,14 +167401,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:106683.3-106731.6" - process $proc$libresoc.v:106683$4155 + attribute \src "libresoc.v:107217.3-107265.6" + process $proc$libresoc.v:107217$4209 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:106684.5-106684.29" + attribute \src "libresoc.v:107218.5-107218.29" switch \initial - attribute \src "libresoc.v:106684.9-106684.17" + attribute \src "libresoc.v:107218.9-107218.17" case 1'1 case end @@ -166145,14 +167476,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] end - attribute \src "libresoc.v:106732.3-106780.6" - process $proc$libresoc.v:106732$4156 + attribute \src "libresoc.v:107266.3-107314.6" + process $proc$libresoc.v:107266$4210 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:106733.5-106733.29" + attribute \src "libresoc.v:107267.5-107267.29" switch \initial - attribute \src "libresoc.v:106733.9-106733.17" + attribute \src "libresoc.v:107267.9-107267.17" case 1'1 case end @@ -166220,14 +167551,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] end - attribute \src "libresoc.v:106781.3-106829.6" - process $proc$libresoc.v:106781$4157 + attribute \src "libresoc.v:107315.3-107363.6" + process $proc$libresoc.v:107315$4211 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:106782.5-106782.29" + attribute \src "libresoc.v:107316.5-107316.29" switch \initial - attribute \src "libresoc.v:106782.9-106782.17" + attribute \src "libresoc.v:107316.9-107316.17" case 1'1 case end @@ -166295,14 +167626,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:106830.3-106878.6" - process $proc$libresoc.v:106830$4158 + attribute \src "libresoc.v:107364.3-107412.6" + process $proc$libresoc.v:107364$4212 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:106831.5-106831.29" + attribute \src "libresoc.v:107365.5-107365.29" switch \initial - attribute \src "libresoc.v:106831.9-106831.17" + attribute \src "libresoc.v:107365.9-107365.17" case 1'1 case end @@ -166370,14 +167701,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:106879.3-106927.6" - process $proc$libresoc.v:106879$4159 + attribute \src "libresoc.v:107413.3-107461.6" + process $proc$libresoc.v:107413$4213 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:106880.5-106880.29" + attribute \src "libresoc.v:107414.5-107414.29" switch \initial - attribute \src "libresoc.v:106880.9-106880.17" + attribute \src "libresoc.v:107414.9-107414.17" case 1'1 case end @@ -166445,14 +167776,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end - attribute \src "libresoc.v:106928.3-106976.6" - process $proc$libresoc.v:106928$4160 + attribute \src "libresoc.v:107462.3-107510.6" + process $proc$libresoc.v:107462$4214 assign { } { } assign { } { } assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:106929.5-106929.29" + attribute \src "libresoc.v:107463.5-107463.29" switch \initial - attribute \src "libresoc.v:106929.9-106929.17" + attribute \src "libresoc.v:107463.9-107463.17" case 1'1 case end @@ -166522,140 +167853,140 @@ module \dec31_dec_sub23 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:106982.1-107926.10" +attribute \src "libresoc.v:107516.1-108461.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" attribute \generator "nMigen" module \dec31_dec_sub24 - attribute \src "libresoc.v:107811.3-107829.6" + attribute \src "libresoc.v:108346.3-108364.6" wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:107830.3-107848.6" + attribute \src "libresoc.v:108365.3-108383.6" wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:107583.3-107601.6" + attribute \src "libresoc.v:108118.3-108136.6" wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:107659.3-107677.6" + attribute \src "libresoc.v:108194.3-108212.6" wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:107336.3-107354.6" + attribute \src "libresoc.v:107871.3-107889.6" wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:107355.3-107373.6" + attribute \src "libresoc.v:107890.3-107908.6" wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:107564.3-107582.6" + attribute \src "libresoc.v:108099.3-108117.6" wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:107640.3-107658.6" + attribute \src "libresoc.v:108175.3-108193.6" wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:107735.3-107753.6" + attribute \src "libresoc.v:108270.3-108288.6" wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:107317.3-107335.6" + attribute \src "libresoc.v:107852.3-107870.6" wire width 13 $0\dec31_dec_sub24_function_unit[12:0] - attribute \src "libresoc.v:107849.3-107867.6" + attribute \src "libresoc.v:108384.3-108402.6" wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:107868.3-107886.6" + attribute \src "libresoc.v:108403.3-108421.6" wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:107887.3-107905.6" + attribute \src "libresoc.v:108422.3-108440.6" wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:107526.3-107544.6" + attribute \src "libresoc.v:108061.3-108079.6" wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:107602.3-107620.6" + attribute \src "libresoc.v:108137.3-108155.6" wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:107621.3-107639.6" + attribute \src "libresoc.v:108156.3-108174.6" wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:107716.3-107734.6" + attribute \src "libresoc.v:108251.3-108269.6" wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:107488.3-107506.6" + attribute \src "libresoc.v:108023.3-108041.6" wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:107773.3-107791.6" + attribute \src "libresoc.v:108308.3-108326.6" wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:107906.3-107924.6" + attribute \src "libresoc.v:108441.3-108459.6" wire width 2 $0\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:107545.3-107563.6" + attribute \src "libresoc.v:108080.3-108098.6" wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:107697.3-107715.6" + attribute \src "libresoc.v:108232.3-108250.6" wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:107792.3-107810.6" + attribute \src "libresoc.v:108327.3-108345.6" wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:107754.3-107772.6" + attribute \src "libresoc.v:108289.3-108307.6" wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:107678.3-107696.6" + attribute \src "libresoc.v:108213.3-108231.6" wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:107450.3-107468.6" + attribute \src "libresoc.v:107985.3-108003.6" wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:107469.3-107487.6" + attribute \src "libresoc.v:108004.3-108022.6" wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:107374.3-107392.6" + attribute \src "libresoc.v:107909.3-107927.6" wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:107393.3-107411.6" + attribute \src "libresoc.v:107928.3-107946.6" wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:107412.3-107430.6" + attribute \src "libresoc.v:107947.3-107965.6" wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:107431.3-107449.6" + attribute \src "libresoc.v:107966.3-107984.6" wire width 3 $0\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:107507.3-107525.6" + attribute \src "libresoc.v:108042.3-108060.6" wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:106983.7-106983.20" + attribute \src "libresoc.v:107517.7-107517.20" wire $0\initial[0:0] - attribute \src "libresoc.v:107811.3-107829.6" + attribute \src "libresoc.v:108346.3-108364.6" wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:107830.3-107848.6" + attribute \src "libresoc.v:108365.3-108383.6" wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:107583.3-107601.6" + attribute \src "libresoc.v:108118.3-108136.6" wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:107659.3-107677.6" + attribute \src "libresoc.v:108194.3-108212.6" wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:107336.3-107354.6" + attribute \src "libresoc.v:107871.3-107889.6" wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:107355.3-107373.6" + attribute \src "libresoc.v:107890.3-107908.6" wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:107564.3-107582.6" + attribute \src "libresoc.v:108099.3-108117.6" wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:107640.3-107658.6" + attribute \src "libresoc.v:108175.3-108193.6" wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:107735.3-107753.6" + attribute \src "libresoc.v:108270.3-108288.6" wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:107317.3-107335.6" + attribute \src "libresoc.v:107852.3-107870.6" wire width 13 $1\dec31_dec_sub24_function_unit[12:0] - attribute \src "libresoc.v:107849.3-107867.6" + attribute \src "libresoc.v:108384.3-108402.6" wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:107868.3-107886.6" + attribute \src "libresoc.v:108403.3-108421.6" wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:107887.3-107905.6" + attribute \src "libresoc.v:108422.3-108440.6" wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:107526.3-107544.6" + attribute \src "libresoc.v:108061.3-108079.6" wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:107602.3-107620.6" + attribute \src "libresoc.v:108137.3-108155.6" wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:107621.3-107639.6" + attribute \src "libresoc.v:108156.3-108174.6" wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:107716.3-107734.6" + attribute \src "libresoc.v:108251.3-108269.6" wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:107488.3-107506.6" + attribute \src "libresoc.v:108023.3-108041.6" wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:107773.3-107791.6" + attribute \src "libresoc.v:108308.3-108326.6" wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:107906.3-107924.6" + attribute \src "libresoc.v:108441.3-108459.6" wire width 2 $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:107545.3-107563.6" + attribute \src "libresoc.v:108080.3-108098.6" wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:107697.3-107715.6" + attribute \src "libresoc.v:108232.3-108250.6" wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:107792.3-107810.6" + attribute \src "libresoc.v:108327.3-108345.6" wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:107754.3-107772.6" + attribute \src "libresoc.v:108289.3-108307.6" wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:107678.3-107696.6" + attribute \src "libresoc.v:108213.3-108231.6" wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:107450.3-107468.6" + attribute \src "libresoc.v:107985.3-108003.6" wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:107469.3-107487.6" + attribute \src "libresoc.v:108004.3-108022.6" wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:107374.3-107392.6" + attribute \src "libresoc.v:107909.3-107927.6" wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:107393.3-107411.6" + attribute \src "libresoc.v:107928.3-107946.6" wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:107412.3-107430.6" + attribute \src "libresoc.v:107947.3-107965.6" wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:107431.3-107449.6" + attribute \src "libresoc.v:107966.3-107984.6" wire width 3 $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:107507.3-107525.6" + attribute \src "libresoc.v:108042.3-108060.6" wire width 2 $1\dec31_dec_sub24_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -166731,6 +168062,7 @@ module \dec31_dec_sub24 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub24_form attribute \enum_base_type "Function" @@ -166954,28 +168286,28 @@ module \dec31_dec_sub24 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub24_upd - attribute \src "libresoc.v:106983.7-106983.15" + attribute \src "libresoc.v:107517.7-107517.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:106983.7-106983.20" - process $proc$libresoc.v:106983$4194 + attribute \src "libresoc.v:107517.7-107517.20" + process $proc$libresoc.v:107517$4248 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:107317.3-107335.6" - process $proc$libresoc.v:107317$4162 + attribute \src "libresoc.v:107852.3-107870.6" + process $proc$libresoc.v:107852$4216 assign { } { } assign { } { } assign $0\dec31_dec_sub24_function_unit[12:0] $1\dec31_dec_sub24_function_unit[12:0] - attribute \src "libresoc.v:107318.5-107318.29" + attribute \src "libresoc.v:107853.5-107853.29" switch \initial - attribute \src "libresoc.v:107318.9-107318.17" + attribute \src "libresoc.v:107853.9-107853.17" case 1'1 case end @@ -167003,14 +168335,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[12:0] end - attribute \src "libresoc.v:107336.3-107354.6" - process $proc$libresoc.v:107336$4163 + attribute \src "libresoc.v:107871.3-107889.6" + process $proc$libresoc.v:107871$4217 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:107337.5-107337.29" + attribute \src "libresoc.v:107872.5-107872.29" switch \initial - attribute \src "libresoc.v:107337.9-107337.17" + attribute \src "libresoc.v:107872.9-107872.17" case 1'1 case end @@ -167038,14 +168370,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:107355.3-107373.6" - process $proc$libresoc.v:107355$4164 + attribute \src "libresoc.v:107890.3-107908.6" + process $proc$libresoc.v:107890$4218 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:107356.5-107356.29" + attribute \src "libresoc.v:107891.5-107891.29" switch \initial - attribute \src "libresoc.v:107356.9-107356.17" + attribute \src "libresoc.v:107891.9-107891.17" case 1'1 case end @@ -167073,14 +168405,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:107374.3-107392.6" - process $proc$libresoc.v:107374$4165 + attribute \src "libresoc.v:107909.3-107927.6" + process $proc$libresoc.v:107909$4219 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:107375.5-107375.29" + attribute \src "libresoc.v:107910.5-107910.29" switch \initial - attribute \src "libresoc.v:107375.9-107375.17" + attribute \src "libresoc.v:107910.9-107910.17" case 1'1 case end @@ -167108,14 +168440,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] end - attribute \src "libresoc.v:107393.3-107411.6" - process $proc$libresoc.v:107393$4166 + attribute \src "libresoc.v:107928.3-107946.6" + process $proc$libresoc.v:107928$4220 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:107394.5-107394.29" + attribute \src "libresoc.v:107929.5-107929.29" switch \initial - attribute \src "libresoc.v:107394.9-107394.17" + attribute \src "libresoc.v:107929.9-107929.17" case 1'1 case end @@ -167143,14 +168475,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] end - attribute \src "libresoc.v:107412.3-107430.6" - process $proc$libresoc.v:107412$4167 + attribute \src "libresoc.v:107947.3-107965.6" + process $proc$libresoc.v:107947$4221 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:107413.5-107413.29" + attribute \src "libresoc.v:107948.5-107948.29" switch \initial - attribute \src "libresoc.v:107413.9-107413.17" + attribute \src "libresoc.v:107948.9-107948.17" case 1'1 case end @@ -167178,14 +168510,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] end - attribute \src "libresoc.v:107431.3-107449.6" - process $proc$libresoc.v:107431$4168 + attribute \src "libresoc.v:107966.3-107984.6" + process $proc$libresoc.v:107966$4222 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:107432.5-107432.29" + attribute \src "libresoc.v:107967.5-107967.29" switch \initial - attribute \src "libresoc.v:107432.9-107432.17" + attribute \src "libresoc.v:107967.9-107967.17" case 1'1 case end @@ -167213,14 +168545,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] end - attribute \src "libresoc.v:107450.3-107468.6" - process $proc$libresoc.v:107450$4169 + attribute \src "libresoc.v:107985.3-108003.6" + process $proc$libresoc.v:107985$4223 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:107451.5-107451.29" + attribute \src "libresoc.v:107986.5-107986.29" switch \initial - attribute \src "libresoc.v:107451.9-107451.17" + attribute \src "libresoc.v:107986.9-107986.17" case 1'1 case end @@ -167248,14 +168580,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] end - attribute \src "libresoc.v:107469.3-107487.6" - process $proc$libresoc.v:107469$4170 + attribute \src "libresoc.v:108004.3-108022.6" + process $proc$libresoc.v:108004$4224 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:107470.5-107470.29" + attribute \src "libresoc.v:108005.5-108005.29" switch \initial - attribute \src "libresoc.v:107470.9-107470.17" + attribute \src "libresoc.v:108005.9-108005.17" case 1'1 case end @@ -167283,14 +168615,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] end - attribute \src "libresoc.v:107488.3-107506.6" - process $proc$libresoc.v:107488$4171 + attribute \src "libresoc.v:108023.3-108041.6" + process $proc$libresoc.v:108023$4225 assign { } { } assign { } { } assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:107489.5-107489.29" + attribute \src "libresoc.v:108024.5-108024.29" switch \initial - attribute \src "libresoc.v:107489.9-107489.17" + attribute \src "libresoc.v:108024.9-108024.17" case 1'1 case end @@ -167318,14 +168650,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "libresoc.v:107507.3-107525.6" - process $proc$libresoc.v:107507$4172 + attribute \src "libresoc.v:108042.3-108060.6" + process $proc$libresoc.v:108042$4226 assign { } { } assign { } { } assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:107508.5-107508.29" + attribute \src "libresoc.v:108043.5-108043.29" switch \initial - attribute \src "libresoc.v:107508.9-107508.17" + attribute \src "libresoc.v:108043.9-108043.17" case 1'1 case end @@ -167353,14 +168685,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "libresoc.v:107526.3-107544.6" - process $proc$libresoc.v:107526$4173 + attribute \src "libresoc.v:108061.3-108079.6" + process $proc$libresoc.v:108061$4227 assign { } { } assign { } { } assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:107527.5-107527.29" + attribute \src "libresoc.v:108062.5-108062.29" switch \initial - attribute \src "libresoc.v:107527.9-107527.17" + attribute \src "libresoc.v:108062.9-108062.17" case 1'1 case end @@ -167388,14 +168720,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:107545.3-107563.6" - process $proc$libresoc.v:107545$4174 + attribute \src "libresoc.v:108080.3-108098.6" + process $proc$libresoc.v:108080$4228 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:107546.5-107546.29" + attribute \src "libresoc.v:108081.5-108081.29" switch \initial - attribute \src "libresoc.v:107546.9-107546.17" + attribute \src "libresoc.v:108081.9-108081.17" case 1'1 case end @@ -167423,14 +168755,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:107564.3-107582.6" - process $proc$libresoc.v:107564$4175 + attribute \src "libresoc.v:108099.3-108117.6" + process $proc$libresoc.v:108099$4229 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:107565.5-107565.29" + attribute \src "libresoc.v:108100.5-108100.29" switch \initial - attribute \src "libresoc.v:107565.9-107565.17" + attribute \src "libresoc.v:108100.9-108100.17" case 1'1 case end @@ -167458,14 +168790,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:107583.3-107601.6" - process $proc$libresoc.v:107583$4176 + attribute \src "libresoc.v:108118.3-108136.6" + process $proc$libresoc.v:108118$4230 assign { } { } assign { } { } assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:107584.5-107584.29" + attribute \src "libresoc.v:108119.5-108119.29" switch \initial - attribute \src "libresoc.v:107584.9-107584.17" + attribute \src "libresoc.v:108119.9-108119.17" case 1'1 case end @@ -167493,14 +168825,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:107602.3-107620.6" - process $proc$libresoc.v:107602$4177 + attribute \src "libresoc.v:108137.3-108155.6" + process $proc$libresoc.v:108137$4231 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:107603.5-107603.29" + attribute \src "libresoc.v:108138.5-108138.29" switch \initial - attribute \src "libresoc.v:107603.9-107603.17" + attribute \src "libresoc.v:108138.9-108138.17" case 1'1 case end @@ -167528,14 +168860,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:107621.3-107639.6" - process $proc$libresoc.v:107621$4178 + attribute \src "libresoc.v:108156.3-108174.6" + process $proc$libresoc.v:108156$4232 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:107622.5-107622.29" + attribute \src "libresoc.v:108157.5-108157.29" switch \initial - attribute \src "libresoc.v:107622.9-107622.17" + attribute \src "libresoc.v:108157.9-108157.17" case 1'1 case end @@ -167563,14 +168895,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end - attribute \src "libresoc.v:107640.3-107658.6" - process $proc$libresoc.v:107640$4179 + attribute \src "libresoc.v:108175.3-108193.6" + process $proc$libresoc.v:108175$4233 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:107641.5-107641.29" + attribute \src "libresoc.v:108176.5-108176.29" switch \initial - attribute \src "libresoc.v:107641.9-107641.17" + attribute \src "libresoc.v:108176.9-108176.17" case 1'1 case end @@ -167598,14 +168930,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "libresoc.v:107659.3-107677.6" - process $proc$libresoc.v:107659$4180 + attribute \src "libresoc.v:108194.3-108212.6" + process $proc$libresoc.v:108194$4234 assign { } { } assign { } { } assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:107660.5-107660.29" + attribute \src "libresoc.v:108195.5-108195.29" switch \initial - attribute \src "libresoc.v:107660.9-107660.17" + attribute \src "libresoc.v:108195.9-108195.17" case 1'1 case end @@ -167633,14 +168965,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end - attribute \src "libresoc.v:107678.3-107696.6" - process $proc$libresoc.v:107678$4181 + attribute \src "libresoc.v:108213.3-108231.6" + process $proc$libresoc.v:108213$4235 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:107679.5-107679.29" + attribute \src "libresoc.v:108214.5-108214.29" switch \initial - attribute \src "libresoc.v:107679.9-107679.17" + attribute \src "libresoc.v:108214.9-108214.17" case 1'1 case end @@ -167668,14 +169000,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "libresoc.v:107697.3-107715.6" - process $proc$libresoc.v:107697$4182 + attribute \src "libresoc.v:108232.3-108250.6" + process $proc$libresoc.v:108232$4236 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:107698.5-107698.29" + attribute \src "libresoc.v:108233.5-108233.29" switch \initial - attribute \src "libresoc.v:107698.9-107698.17" + attribute \src "libresoc.v:108233.9-108233.17" case 1'1 case end @@ -167703,14 +169035,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end - attribute \src "libresoc.v:107716.3-107734.6" - process $proc$libresoc.v:107716$4183 + attribute \src "libresoc.v:108251.3-108269.6" + process $proc$libresoc.v:108251$4237 assign { } { } assign { } { } assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:107717.5-107717.29" + attribute \src "libresoc.v:108252.5-108252.29" switch \initial - attribute \src "libresoc.v:107717.9-107717.17" + attribute \src "libresoc.v:108252.9-108252.17" case 1'1 case end @@ -167738,14 +169070,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:107735.3-107753.6" - process $proc$libresoc.v:107735$4184 + attribute \src "libresoc.v:108270.3-108288.6" + process $proc$libresoc.v:108270$4238 assign { } { } assign { } { } assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:107736.5-107736.29" + attribute \src "libresoc.v:108271.5-108271.29" switch \initial - attribute \src "libresoc.v:107736.9-107736.17" + attribute \src "libresoc.v:108271.9-108271.17" case 1'1 case end @@ -167773,14 +169105,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end - attribute \src "libresoc.v:107754.3-107772.6" - process $proc$libresoc.v:107754$4185 + attribute \src "libresoc.v:108289.3-108307.6" + process $proc$libresoc.v:108289$4239 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:107755.5-107755.29" + attribute \src "libresoc.v:108290.5-108290.29" switch \initial - attribute \src "libresoc.v:107755.9-107755.17" + attribute \src "libresoc.v:108290.9-108290.17" case 1'1 case end @@ -167808,14 +169140,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:107773.3-107791.6" - process $proc$libresoc.v:107773$4186 + attribute \src "libresoc.v:108308.3-108326.6" + process $proc$libresoc.v:108308$4240 assign { } { } assign { } { } assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:107774.5-107774.29" + attribute \src "libresoc.v:108309.5-108309.29" switch \initial - attribute \src "libresoc.v:107774.9-107774.17" + attribute \src "libresoc.v:108309.9-108309.17" case 1'1 case end @@ -167843,14 +169175,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] end - attribute \src "libresoc.v:107792.3-107810.6" - process $proc$libresoc.v:107792$4187 + attribute \src "libresoc.v:108327.3-108345.6" + process $proc$libresoc.v:108327$4241 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:107793.5-107793.29" + attribute \src "libresoc.v:108328.5-108328.29" switch \initial - attribute \src "libresoc.v:107793.9-107793.17" + attribute \src "libresoc.v:108328.9-108328.17" case 1'1 case end @@ -167878,14 +169210,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:107811.3-107829.6" - process $proc$libresoc.v:107811$4188 + attribute \src "libresoc.v:108346.3-108364.6" + process $proc$libresoc.v:108346$4242 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:107812.5-107812.29" + attribute \src "libresoc.v:108347.5-108347.29" switch \initial - attribute \src "libresoc.v:107812.9-107812.17" + attribute \src "libresoc.v:108347.9-108347.17" case 1'1 case end @@ -167913,14 +169245,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] end - attribute \src "libresoc.v:107830.3-107848.6" - process $proc$libresoc.v:107830$4189 + attribute \src "libresoc.v:108365.3-108383.6" + process $proc$libresoc.v:108365$4243 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:107831.5-107831.29" + attribute \src "libresoc.v:108366.5-108366.29" switch \initial - attribute \src "libresoc.v:107831.9-107831.17" + attribute \src "libresoc.v:108366.9-108366.17" case 1'1 case end @@ -167948,14 +169280,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] end - attribute \src "libresoc.v:107849.3-107867.6" - process $proc$libresoc.v:107849$4190 + attribute \src "libresoc.v:108384.3-108402.6" + process $proc$libresoc.v:108384$4244 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:107850.5-107850.29" + attribute \src "libresoc.v:108385.5-108385.29" switch \initial - attribute \src "libresoc.v:107850.9-107850.17" + attribute \src "libresoc.v:108385.9-108385.17" case 1'1 case end @@ -167983,14 +169315,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] end - attribute \src "libresoc.v:107868.3-107886.6" - process $proc$libresoc.v:107868$4191 + attribute \src "libresoc.v:108403.3-108421.6" + process $proc$libresoc.v:108403$4245 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:107869.5-107869.29" + attribute \src "libresoc.v:108404.5-108404.29" switch \initial - attribute \src "libresoc.v:107869.9-107869.17" + attribute \src "libresoc.v:108404.9-108404.17" case 1'1 case end @@ -168018,14 +169350,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:107887.3-107905.6" - process $proc$libresoc.v:107887$4192 + attribute \src "libresoc.v:108422.3-108440.6" + process $proc$libresoc.v:108422$4246 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:107888.5-107888.29" + attribute \src "libresoc.v:108423.5-108423.29" switch \initial - attribute \src "libresoc.v:107888.9-107888.17" + attribute \src "libresoc.v:108423.9-108423.17" case 1'1 case end @@ -168053,14 +169385,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end - attribute \src "libresoc.v:107906.3-107924.6" - process $proc$libresoc.v:107906$4193 + attribute \src "libresoc.v:108441.3-108459.6" + process $proc$libresoc.v:108441$4247 assign { } { } assign { } { } assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:107907.5-107907.29" + attribute \src "libresoc.v:108442.5-108442.29" switch \initial - attribute \src "libresoc.v:107907.9-107907.17" + attribute \src "libresoc.v:108442.9-108442.17" case 1'1 case end @@ -168090,140 +169422,140 @@ module \dec31_dec_sub24 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:107930.1-109930.10" +attribute \src "libresoc.v:108465.1-110466.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" module \dec31_dec_sub26 - attribute \src "libresoc.v:109617.3-109668.6" + attribute \src "libresoc.v:110153.3-110204.6" wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:109669.3-109720.6" + attribute \src "libresoc.v:110205.3-110256.6" wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:108993.3-109044.6" + attribute \src "libresoc.v:109529.3-109580.6" wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:109201.3-109252.6" + attribute \src "libresoc.v:109737.3-109788.6" wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:108317.3-108368.6" + attribute \src "libresoc.v:108853.3-108904.6" wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:108369.3-108420.6" + attribute \src "libresoc.v:108905.3-108956.6" wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:108941.3-108992.6" + attribute \src "libresoc.v:109477.3-109528.6" wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:109149.3-109200.6" + attribute \src "libresoc.v:109685.3-109736.6" wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:109409.3-109460.6" + attribute \src "libresoc.v:109945.3-109996.6" wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:108265.3-108316.6" + attribute \src "libresoc.v:108801.3-108852.6" wire width 13 $0\dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:109721.3-109772.6" + attribute \src "libresoc.v:110257.3-110308.6" wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:109773.3-109824.6" + attribute \src "libresoc.v:110309.3-110360.6" wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:109825.3-109876.6" + attribute \src "libresoc.v:110361.3-110412.6" wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:108837.3-108888.6" + attribute \src "libresoc.v:109373.3-109424.6" wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:109045.3-109096.6" + attribute \src "libresoc.v:109581.3-109632.6" wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:109097.3-109148.6" + attribute \src "libresoc.v:109633.3-109684.6" wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:109357.3-109408.6" + attribute \src "libresoc.v:109893.3-109944.6" wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:108733.3-108784.6" + attribute \src "libresoc.v:109269.3-109320.6" wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:109513.3-109564.6" + attribute \src "libresoc.v:110049.3-110100.6" wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:109877.3-109928.6" + attribute \src "libresoc.v:110413.3-110464.6" wire width 2 $0\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:108889.3-108940.6" + attribute \src "libresoc.v:109425.3-109476.6" wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:109305.3-109356.6" + attribute \src "libresoc.v:109841.3-109892.6" wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:109565.3-109616.6" + attribute \src "libresoc.v:110101.3-110152.6" wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:109461.3-109512.6" + attribute \src "libresoc.v:109997.3-110048.6" wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:109253.3-109304.6" + attribute \src "libresoc.v:109789.3-109840.6" wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:108629.3-108680.6" + attribute \src "libresoc.v:109165.3-109216.6" wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:108681.3-108732.6" + attribute \src "libresoc.v:109217.3-109268.6" wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:108421.3-108472.6" + attribute \src "libresoc.v:108957.3-109008.6" wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:108473.3-108524.6" + attribute \src "libresoc.v:109009.3-109060.6" wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:108525.3-108576.6" + attribute \src "libresoc.v:109061.3-109112.6" wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:108577.3-108628.6" + attribute \src "libresoc.v:109113.3-109164.6" wire width 3 $0\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:108785.3-108836.6" + attribute \src "libresoc.v:109321.3-109372.6" wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:107931.7-107931.20" + attribute \src "libresoc.v:108466.7-108466.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109617.3-109668.6" + attribute \src "libresoc.v:110153.3-110204.6" wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:109669.3-109720.6" + attribute \src "libresoc.v:110205.3-110256.6" wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:108993.3-109044.6" + attribute \src "libresoc.v:109529.3-109580.6" wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:109201.3-109252.6" + attribute \src "libresoc.v:109737.3-109788.6" wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:108317.3-108368.6" + attribute \src "libresoc.v:108853.3-108904.6" wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:108369.3-108420.6" + attribute \src "libresoc.v:108905.3-108956.6" wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:108941.3-108992.6" + attribute \src "libresoc.v:109477.3-109528.6" wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:109149.3-109200.6" + attribute \src "libresoc.v:109685.3-109736.6" wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:109409.3-109460.6" + attribute \src "libresoc.v:109945.3-109996.6" wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:108265.3-108316.6" + attribute \src "libresoc.v:108801.3-108852.6" wire width 13 $1\dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:109721.3-109772.6" + attribute \src "libresoc.v:110257.3-110308.6" wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:109773.3-109824.6" + attribute \src "libresoc.v:110309.3-110360.6" wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:109825.3-109876.6" + attribute \src "libresoc.v:110361.3-110412.6" wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:108837.3-108888.6" + attribute \src "libresoc.v:109373.3-109424.6" wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:109045.3-109096.6" + attribute \src "libresoc.v:109581.3-109632.6" wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:109097.3-109148.6" + attribute \src "libresoc.v:109633.3-109684.6" wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:109357.3-109408.6" + attribute \src "libresoc.v:109893.3-109944.6" wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:108733.3-108784.6" + attribute \src "libresoc.v:109269.3-109320.6" wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:109513.3-109564.6" + attribute \src "libresoc.v:110049.3-110100.6" wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:109877.3-109928.6" + attribute \src "libresoc.v:110413.3-110464.6" wire width 2 $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:108889.3-108940.6" + attribute \src "libresoc.v:109425.3-109476.6" wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:109305.3-109356.6" + attribute \src "libresoc.v:109841.3-109892.6" wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:109565.3-109616.6" + attribute \src "libresoc.v:110101.3-110152.6" wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:109461.3-109512.6" + attribute \src "libresoc.v:109997.3-110048.6" wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:109253.3-109304.6" + attribute \src "libresoc.v:109789.3-109840.6" wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:108629.3-108680.6" + attribute \src "libresoc.v:109165.3-109216.6" wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:108681.3-108732.6" + attribute \src "libresoc.v:109217.3-109268.6" wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:108421.3-108472.6" + attribute \src "libresoc.v:108957.3-109008.6" wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:108473.3-108524.6" + attribute \src "libresoc.v:109009.3-109060.6" wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:108525.3-108576.6" + attribute \src "libresoc.v:109061.3-109112.6" wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:108577.3-108628.6" + attribute \src "libresoc.v:109113.3-109164.6" wire width 3 $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:108785.3-108836.6" + attribute \src "libresoc.v:109321.3-109372.6" wire width 2 $1\dec31_dec_sub26_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -168299,6 +169631,7 @@ module \dec31_dec_sub26 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub26_form attribute \enum_base_type "Function" @@ -168522,28 +169855,28 @@ module \dec31_dec_sub26 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub26_upd - attribute \src "libresoc.v:107931.7-107931.15" + attribute \src "libresoc.v:108466.7-108466.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:107931.7-107931.20" - process $proc$libresoc.v:107931$4227 + attribute \src "libresoc.v:108466.7-108466.20" + process $proc$libresoc.v:108466$4281 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:108265.3-108316.6" - process $proc$libresoc.v:108265$4195 + attribute \src "libresoc.v:108801.3-108852.6" + process $proc$libresoc.v:108801$4249 assign { } { } assign { } { } assign $0\dec31_dec_sub26_function_unit[12:0] $1\dec31_dec_sub26_function_unit[12:0] - attribute \src "libresoc.v:108266.5-108266.29" + attribute \src "libresoc.v:108802.5-108802.29" switch \initial - attribute \src "libresoc.v:108266.9-108266.17" + attribute \src "libresoc.v:108802.9-108802.17" case 1'1 case end @@ -168615,14 +169948,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[12:0] end - attribute \src "libresoc.v:108317.3-108368.6" - process $proc$libresoc.v:108317$4196 + attribute \src "libresoc.v:108853.3-108904.6" + process $proc$libresoc.v:108853$4250 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:108318.5-108318.29" + attribute \src "libresoc.v:108854.5-108854.29" switch \initial - attribute \src "libresoc.v:108318.9-108318.17" + attribute \src "libresoc.v:108854.9-108854.17" case 1'1 case end @@ -168694,14 +170027,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:108369.3-108420.6" - process $proc$libresoc.v:108369$4197 + attribute \src "libresoc.v:108905.3-108956.6" + process $proc$libresoc.v:108905$4251 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:108370.5-108370.29" + attribute \src "libresoc.v:108906.5-108906.29" switch \initial - attribute \src "libresoc.v:108370.9-108370.17" + attribute \src "libresoc.v:108906.9-108906.17" case 1'1 case end @@ -168773,14 +170106,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:108421.3-108472.6" - process $proc$libresoc.v:108421$4198 + attribute \src "libresoc.v:108957.3-109008.6" + process $proc$libresoc.v:108957$4252 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:108422.5-108422.29" + attribute \src "libresoc.v:108958.5-108958.29" switch \initial - attribute \src "libresoc.v:108422.9-108422.17" + attribute \src "libresoc.v:108958.9-108958.17" case 1'1 case end @@ -168852,14 +170185,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] end - attribute \src "libresoc.v:108473.3-108524.6" - process $proc$libresoc.v:108473$4199 + attribute \src "libresoc.v:109009.3-109060.6" + process $proc$libresoc.v:109009$4253 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:108474.5-108474.29" + attribute \src "libresoc.v:109010.5-109010.29" switch \initial - attribute \src "libresoc.v:108474.9-108474.17" + attribute \src "libresoc.v:109010.9-109010.17" case 1'1 case end @@ -168931,14 +170264,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] end - attribute \src "libresoc.v:108525.3-108576.6" - process $proc$libresoc.v:108525$4200 + attribute \src "libresoc.v:109061.3-109112.6" + process $proc$libresoc.v:109061$4254 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:108526.5-108526.29" + attribute \src "libresoc.v:109062.5-109062.29" switch \initial - attribute \src "libresoc.v:108526.9-108526.17" + attribute \src "libresoc.v:109062.9-109062.17" case 1'1 case end @@ -169010,14 +170343,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] end - attribute \src "libresoc.v:108577.3-108628.6" - process $proc$libresoc.v:108577$4201 + attribute \src "libresoc.v:109113.3-109164.6" + process $proc$libresoc.v:109113$4255 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:108578.5-108578.29" + attribute \src "libresoc.v:109114.5-109114.29" switch \initial - attribute \src "libresoc.v:108578.9-108578.17" + attribute \src "libresoc.v:109114.9-109114.17" case 1'1 case end @@ -169089,14 +170422,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] end - attribute \src "libresoc.v:108629.3-108680.6" - process $proc$libresoc.v:108629$4202 + attribute \src "libresoc.v:109165.3-109216.6" + process $proc$libresoc.v:109165$4256 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:108630.5-108630.29" + attribute \src "libresoc.v:109166.5-109166.29" switch \initial - attribute \src "libresoc.v:108630.9-108630.17" + attribute \src "libresoc.v:109166.9-109166.17" case 1'1 case end @@ -169168,14 +170501,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] end - attribute \src "libresoc.v:108681.3-108732.6" - process $proc$libresoc.v:108681$4203 + attribute \src "libresoc.v:109217.3-109268.6" + process $proc$libresoc.v:109217$4257 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:108682.5-108682.29" + attribute \src "libresoc.v:109218.5-109218.29" switch \initial - attribute \src "libresoc.v:108682.9-108682.17" + attribute \src "libresoc.v:109218.9-109218.17" case 1'1 case end @@ -169247,14 +170580,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] end - attribute \src "libresoc.v:108733.3-108784.6" - process $proc$libresoc.v:108733$4204 + attribute \src "libresoc.v:109269.3-109320.6" + process $proc$libresoc.v:109269$4258 assign { } { } assign { } { } assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:108734.5-108734.29" + attribute \src "libresoc.v:109270.5-109270.29" switch \initial - attribute \src "libresoc.v:108734.9-108734.17" + attribute \src "libresoc.v:109270.9-109270.17" case 1'1 case end @@ -169326,14 +170659,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:108785.3-108836.6" - process $proc$libresoc.v:108785$4205 + attribute \src "libresoc.v:109321.3-109372.6" + process $proc$libresoc.v:109321$4259 assign { } { } assign { } { } assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:108786.5-108786.29" + attribute \src "libresoc.v:109322.5-109322.29" switch \initial - attribute \src "libresoc.v:108786.9-108786.17" + attribute \src "libresoc.v:109322.9-109322.17" case 1'1 case end @@ -169405,14 +170738,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "libresoc.v:108837.3-108888.6" - process $proc$libresoc.v:108837$4206 + attribute \src "libresoc.v:109373.3-109424.6" + process $proc$libresoc.v:109373$4260 assign { } { } assign { } { } assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:108838.5-108838.29" + attribute \src "libresoc.v:109374.5-109374.29" switch \initial - attribute \src "libresoc.v:108838.9-108838.17" + attribute \src "libresoc.v:109374.9-109374.17" case 1'1 case end @@ -169484,14 +170817,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:108889.3-108940.6" - process $proc$libresoc.v:108889$4207 + attribute \src "libresoc.v:109425.3-109476.6" + process $proc$libresoc.v:109425$4261 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:108890.5-108890.29" + attribute \src "libresoc.v:109426.5-109426.29" switch \initial - attribute \src "libresoc.v:108890.9-108890.17" + attribute \src "libresoc.v:109426.9-109426.17" case 1'1 case end @@ -169563,14 +170896,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:108941.3-108992.6" - process $proc$libresoc.v:108941$4208 + attribute \src "libresoc.v:109477.3-109528.6" + process $proc$libresoc.v:109477$4262 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:108942.5-108942.29" + attribute \src "libresoc.v:109478.5-109478.29" switch \initial - attribute \src "libresoc.v:108942.9-108942.17" + attribute \src "libresoc.v:109478.9-109478.17" case 1'1 case end @@ -169642,14 +170975,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:108993.3-109044.6" - process $proc$libresoc.v:108993$4209 + attribute \src "libresoc.v:109529.3-109580.6" + process $proc$libresoc.v:109529$4263 assign { } { } assign { } { } assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:108994.5-108994.29" + attribute \src "libresoc.v:109530.5-109530.29" switch \initial - attribute \src "libresoc.v:108994.9-108994.17" + attribute \src "libresoc.v:109530.9-109530.17" case 1'1 case end @@ -169721,14 +171054,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "libresoc.v:109045.3-109096.6" - process $proc$libresoc.v:109045$4210 + attribute \src "libresoc.v:109581.3-109632.6" + process $proc$libresoc.v:109581$4264 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:109046.5-109046.29" + attribute \src "libresoc.v:109582.5-109582.29" switch \initial - attribute \src "libresoc.v:109046.9-109046.17" + attribute \src "libresoc.v:109582.9-109582.17" case 1'1 case end @@ -169800,14 +171133,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:109097.3-109148.6" - process $proc$libresoc.v:109097$4211 + attribute \src "libresoc.v:109633.3-109684.6" + process $proc$libresoc.v:109633$4265 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:109098.5-109098.29" + attribute \src "libresoc.v:109634.5-109634.29" switch \initial - attribute \src "libresoc.v:109098.9-109098.17" + attribute \src "libresoc.v:109634.9-109634.17" case 1'1 case end @@ -169879,14 +171212,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:109149.3-109200.6" - process $proc$libresoc.v:109149$4212 + attribute \src "libresoc.v:109685.3-109736.6" + process $proc$libresoc.v:109685$4266 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:109150.5-109150.29" + attribute \src "libresoc.v:109686.5-109686.29" switch \initial - attribute \src "libresoc.v:109150.9-109150.17" + attribute \src "libresoc.v:109686.9-109686.17" case 1'1 case end @@ -169958,14 +171291,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:109201.3-109252.6" - process $proc$libresoc.v:109201$4213 + attribute \src "libresoc.v:109737.3-109788.6" + process $proc$libresoc.v:109737$4267 assign { } { } assign { } { } assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:109202.5-109202.29" + attribute \src "libresoc.v:109738.5-109738.29" switch \initial - attribute \src "libresoc.v:109202.9-109202.17" + attribute \src "libresoc.v:109738.9-109738.17" case 1'1 case end @@ -170037,14 +171370,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:109253.3-109304.6" - process $proc$libresoc.v:109253$4214 + attribute \src "libresoc.v:109789.3-109840.6" + process $proc$libresoc.v:109789$4268 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:109254.5-109254.29" + attribute \src "libresoc.v:109790.5-109790.29" switch \initial - attribute \src "libresoc.v:109254.9-109254.17" + attribute \src "libresoc.v:109790.9-109790.17" case 1'1 case end @@ -170116,14 +171449,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "libresoc.v:109305.3-109356.6" - process $proc$libresoc.v:109305$4215 + attribute \src "libresoc.v:109841.3-109892.6" + process $proc$libresoc.v:109841$4269 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:109306.5-109306.29" + attribute \src "libresoc.v:109842.5-109842.29" switch \initial - attribute \src "libresoc.v:109306.9-109306.17" + attribute \src "libresoc.v:109842.9-109842.17" case 1'1 case end @@ -170195,14 +171528,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:109357.3-109408.6" - process $proc$libresoc.v:109357$4216 + attribute \src "libresoc.v:109893.3-109944.6" + process $proc$libresoc.v:109893$4270 assign { } { } assign { } { } assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:109358.5-109358.29" + attribute \src "libresoc.v:109894.5-109894.29" switch \initial - attribute \src "libresoc.v:109358.9-109358.17" + attribute \src "libresoc.v:109894.9-109894.17" case 1'1 case end @@ -170274,14 +171607,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:109409.3-109460.6" - process $proc$libresoc.v:109409$4217 + attribute \src "libresoc.v:109945.3-109996.6" + process $proc$libresoc.v:109945$4271 assign { } { } assign { } { } assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:109410.5-109410.29" + attribute \src "libresoc.v:109946.5-109946.29" switch \initial - attribute \src "libresoc.v:109410.9-109410.17" + attribute \src "libresoc.v:109946.9-109946.17" case 1'1 case end @@ -170353,14 +171686,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "libresoc.v:109461.3-109512.6" - process $proc$libresoc.v:109461$4218 + attribute \src "libresoc.v:109997.3-110048.6" + process $proc$libresoc.v:109997$4272 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:109462.5-109462.29" + attribute \src "libresoc.v:109998.5-109998.29" switch \initial - attribute \src "libresoc.v:109462.9-109462.17" + attribute \src "libresoc.v:109998.9-109998.17" case 1'1 case end @@ -170432,14 +171765,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:109513.3-109564.6" - process $proc$libresoc.v:109513$4219 + attribute \src "libresoc.v:110049.3-110100.6" + process $proc$libresoc.v:110049$4273 assign { } { } assign { } { } assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:109514.5-109514.29" + attribute \src "libresoc.v:110050.5-110050.29" switch \initial - attribute \src "libresoc.v:109514.9-109514.17" + attribute \src "libresoc.v:110050.9-110050.17" case 1'1 case end @@ -170511,14 +171844,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "libresoc.v:109565.3-109616.6" - process $proc$libresoc.v:109565$4220 + attribute \src "libresoc.v:110101.3-110152.6" + process $proc$libresoc.v:110101$4274 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:109566.5-109566.29" + attribute \src "libresoc.v:110102.5-110102.29" switch \initial - attribute \src "libresoc.v:109566.9-109566.17" + attribute \src "libresoc.v:110102.9-110102.17" case 1'1 case end @@ -170590,14 +171923,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end - attribute \src "libresoc.v:109617.3-109668.6" - process $proc$libresoc.v:109617$4221 + attribute \src "libresoc.v:110153.3-110204.6" + process $proc$libresoc.v:110153$4275 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:109618.5-109618.29" + attribute \src "libresoc.v:110154.5-110154.29" switch \initial - attribute \src "libresoc.v:109618.9-109618.17" + attribute \src "libresoc.v:110154.9-110154.17" case 1'1 case end @@ -170669,14 +172002,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] end - attribute \src "libresoc.v:109669.3-109720.6" - process $proc$libresoc.v:109669$4222 + attribute \src "libresoc.v:110205.3-110256.6" + process $proc$libresoc.v:110205$4276 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:109670.5-109670.29" + attribute \src "libresoc.v:110206.5-110206.29" switch \initial - attribute \src "libresoc.v:109670.9-109670.17" + attribute \src "libresoc.v:110206.9-110206.17" case 1'1 case end @@ -170748,14 +172081,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] end - attribute \src "libresoc.v:109721.3-109772.6" - process $proc$libresoc.v:109721$4223 + attribute \src "libresoc.v:110257.3-110308.6" + process $proc$libresoc.v:110257$4277 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:109722.5-109722.29" + attribute \src "libresoc.v:110258.5-110258.29" switch \initial - attribute \src "libresoc.v:109722.9-109722.17" + attribute \src "libresoc.v:110258.9-110258.17" case 1'1 case end @@ -170827,14 +172160,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:109773.3-109824.6" - process $proc$libresoc.v:109773$4224 + attribute \src "libresoc.v:110309.3-110360.6" + process $proc$libresoc.v:110309$4278 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:109774.5-109774.29" + attribute \src "libresoc.v:110310.5-110310.29" switch \initial - attribute \src "libresoc.v:109774.9-109774.17" + attribute \src "libresoc.v:110310.9-110310.17" case 1'1 case end @@ -170906,14 +172239,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:109825.3-109876.6" - process $proc$libresoc.v:109825$4225 + attribute \src "libresoc.v:110361.3-110412.6" + process $proc$libresoc.v:110361$4279 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:109826.5-109826.29" + attribute \src "libresoc.v:110362.5-110362.29" switch \initial - attribute \src "libresoc.v:109826.9-109826.17" + attribute \src "libresoc.v:110362.9-110362.17" case 1'1 case end @@ -170985,14 +172318,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end - attribute \src "libresoc.v:109877.3-109928.6" - process $proc$libresoc.v:109877$4226 + attribute \src "libresoc.v:110413.3-110464.6" + process $proc$libresoc.v:110413$4280 assign { } { } assign { } { } assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:109878.5-109878.29" + attribute \src "libresoc.v:110414.5-110414.29" switch \initial - attribute \src "libresoc.v:109878.9-109878.17" + attribute \src "libresoc.v:110414.9-110414.17" case 1'1 case end @@ -171066,140 +172399,140 @@ module \dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:109934.1-110878.10" +attribute \src "libresoc.v:110470.1-111415.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" attribute \generator "nMigen" module \dec31_dec_sub27 - attribute \src "libresoc.v:110763.3-110781.6" + attribute \src "libresoc.v:111300.3-111318.6" wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:110782.3-110800.6" + attribute \src "libresoc.v:111319.3-111337.6" wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:110535.3-110553.6" + attribute \src "libresoc.v:111072.3-111090.6" wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:110611.3-110629.6" + attribute \src "libresoc.v:111148.3-111166.6" wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:110288.3-110306.6" + attribute \src "libresoc.v:110825.3-110843.6" wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:110307.3-110325.6" + attribute \src "libresoc.v:110844.3-110862.6" wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:110516.3-110534.6" + attribute \src "libresoc.v:111053.3-111071.6" wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:110592.3-110610.6" + attribute \src "libresoc.v:111129.3-111147.6" wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:110687.3-110705.6" + attribute \src "libresoc.v:111224.3-111242.6" wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:110269.3-110287.6" + attribute \src "libresoc.v:110806.3-110824.6" wire width 13 $0\dec31_dec_sub27_function_unit[12:0] - attribute \src "libresoc.v:110801.3-110819.6" + attribute \src "libresoc.v:111338.3-111356.6" wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:110820.3-110838.6" + attribute \src "libresoc.v:111357.3-111375.6" wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:110839.3-110857.6" + attribute \src "libresoc.v:111376.3-111394.6" wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:110478.3-110496.6" + attribute \src "libresoc.v:111015.3-111033.6" wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:110554.3-110572.6" + attribute \src "libresoc.v:111091.3-111109.6" wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:110573.3-110591.6" + attribute \src "libresoc.v:111110.3-111128.6" wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:110668.3-110686.6" + attribute \src "libresoc.v:111205.3-111223.6" wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:110440.3-110458.6" + attribute \src "libresoc.v:110977.3-110995.6" wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:110725.3-110743.6" + attribute \src "libresoc.v:111262.3-111280.6" wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:110858.3-110876.6" + attribute \src "libresoc.v:111395.3-111413.6" wire width 2 $0\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:110497.3-110515.6" + attribute \src "libresoc.v:111034.3-111052.6" wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:110649.3-110667.6" + attribute \src "libresoc.v:111186.3-111204.6" wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:110744.3-110762.6" + attribute \src "libresoc.v:111281.3-111299.6" wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:110706.3-110724.6" + attribute \src "libresoc.v:111243.3-111261.6" wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:110630.3-110648.6" + attribute \src "libresoc.v:111167.3-111185.6" wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:110402.3-110420.6" + attribute \src "libresoc.v:110939.3-110957.6" wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:110421.3-110439.6" + attribute \src "libresoc.v:110958.3-110976.6" wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:110326.3-110344.6" + attribute \src "libresoc.v:110863.3-110881.6" wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:110345.3-110363.6" + attribute \src "libresoc.v:110882.3-110900.6" wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:110364.3-110382.6" + attribute \src "libresoc.v:110901.3-110919.6" wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:110383.3-110401.6" + attribute \src "libresoc.v:110920.3-110938.6" wire width 3 $0\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:110459.3-110477.6" + attribute \src "libresoc.v:110996.3-111014.6" wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:109935.7-109935.20" + attribute \src "libresoc.v:110471.7-110471.20" wire $0\initial[0:0] - attribute \src "libresoc.v:110763.3-110781.6" + attribute \src "libresoc.v:111300.3-111318.6" wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:110782.3-110800.6" + attribute \src "libresoc.v:111319.3-111337.6" wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:110535.3-110553.6" + attribute \src "libresoc.v:111072.3-111090.6" wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:110611.3-110629.6" + attribute \src "libresoc.v:111148.3-111166.6" wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:110288.3-110306.6" + attribute \src "libresoc.v:110825.3-110843.6" wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:110307.3-110325.6" + attribute \src "libresoc.v:110844.3-110862.6" wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:110516.3-110534.6" + attribute \src "libresoc.v:111053.3-111071.6" wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:110592.3-110610.6" + attribute \src "libresoc.v:111129.3-111147.6" wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:110687.3-110705.6" + attribute \src "libresoc.v:111224.3-111242.6" wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:110269.3-110287.6" + attribute \src "libresoc.v:110806.3-110824.6" wire width 13 $1\dec31_dec_sub27_function_unit[12:0] - attribute \src "libresoc.v:110801.3-110819.6" + attribute \src "libresoc.v:111338.3-111356.6" wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:110820.3-110838.6" + attribute \src "libresoc.v:111357.3-111375.6" wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:110839.3-110857.6" + attribute \src "libresoc.v:111376.3-111394.6" wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:110478.3-110496.6" + attribute \src "libresoc.v:111015.3-111033.6" wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:110554.3-110572.6" + attribute \src "libresoc.v:111091.3-111109.6" wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:110573.3-110591.6" + attribute \src "libresoc.v:111110.3-111128.6" wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:110668.3-110686.6" + attribute \src "libresoc.v:111205.3-111223.6" wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:110440.3-110458.6" + attribute \src "libresoc.v:110977.3-110995.6" wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:110725.3-110743.6" + attribute \src "libresoc.v:111262.3-111280.6" wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:110858.3-110876.6" + attribute \src "libresoc.v:111395.3-111413.6" wire width 2 $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:110497.3-110515.6" + attribute \src "libresoc.v:111034.3-111052.6" wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:110649.3-110667.6" + attribute \src "libresoc.v:111186.3-111204.6" wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:110744.3-110762.6" + attribute \src "libresoc.v:111281.3-111299.6" wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:110706.3-110724.6" + attribute \src "libresoc.v:111243.3-111261.6" wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:110630.3-110648.6" + attribute \src "libresoc.v:111167.3-111185.6" wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:110402.3-110420.6" + attribute \src "libresoc.v:110939.3-110957.6" wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:110421.3-110439.6" + attribute \src "libresoc.v:110958.3-110976.6" wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:110326.3-110344.6" + attribute \src "libresoc.v:110863.3-110881.6" wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:110345.3-110363.6" + attribute \src "libresoc.v:110882.3-110900.6" wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:110364.3-110382.6" + attribute \src "libresoc.v:110901.3-110919.6" wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:110383.3-110401.6" + attribute \src "libresoc.v:110920.3-110938.6" wire width 3 $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:110459.3-110477.6" + attribute \src "libresoc.v:110996.3-111014.6" wire width 2 $1\dec31_dec_sub27_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -171275,6 +172608,7 @@ module \dec31_dec_sub27 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub27_form attribute \enum_base_type "Function" @@ -171498,28 +172832,28 @@ module \dec31_dec_sub27 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub27_upd - attribute \src "libresoc.v:109935.7-109935.15" + attribute \src "libresoc.v:110471.7-110471.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:109935.7-109935.20" - process $proc$libresoc.v:109935$4260 + attribute \src "libresoc.v:110471.7-110471.20" + process $proc$libresoc.v:110471$4314 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:110269.3-110287.6" - process $proc$libresoc.v:110269$4228 + attribute \src "libresoc.v:110806.3-110824.6" + process $proc$libresoc.v:110806$4282 assign { } { } assign { } { } assign $0\dec31_dec_sub27_function_unit[12:0] $1\dec31_dec_sub27_function_unit[12:0] - attribute \src "libresoc.v:110270.5-110270.29" + attribute \src "libresoc.v:110807.5-110807.29" switch \initial - attribute \src "libresoc.v:110270.9-110270.17" + attribute \src "libresoc.v:110807.9-110807.17" case 1'1 case end @@ -171547,14 +172881,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[12:0] end - attribute \src "libresoc.v:110288.3-110306.6" - process $proc$libresoc.v:110288$4229 + attribute \src "libresoc.v:110825.3-110843.6" + process $proc$libresoc.v:110825$4283 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:110289.5-110289.29" + attribute \src "libresoc.v:110826.5-110826.29" switch \initial - attribute \src "libresoc.v:110289.9-110289.17" + attribute \src "libresoc.v:110826.9-110826.17" case 1'1 case end @@ -171582,14 +172916,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:110307.3-110325.6" - process $proc$libresoc.v:110307$4230 + attribute \src "libresoc.v:110844.3-110862.6" + process $proc$libresoc.v:110844$4284 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:110308.5-110308.29" + attribute \src "libresoc.v:110845.5-110845.29" switch \initial - attribute \src "libresoc.v:110308.9-110308.17" + attribute \src "libresoc.v:110845.9-110845.17" case 1'1 case end @@ -171617,14 +172951,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:110326.3-110344.6" - process $proc$libresoc.v:110326$4231 + attribute \src "libresoc.v:110863.3-110881.6" + process $proc$libresoc.v:110863$4285 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:110327.5-110327.29" + attribute \src "libresoc.v:110864.5-110864.29" switch \initial - attribute \src "libresoc.v:110327.9-110327.17" + attribute \src "libresoc.v:110864.9-110864.17" case 1'1 case end @@ -171652,14 +172986,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] end - attribute \src "libresoc.v:110345.3-110363.6" - process $proc$libresoc.v:110345$4232 + attribute \src "libresoc.v:110882.3-110900.6" + process $proc$libresoc.v:110882$4286 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:110346.5-110346.29" + attribute \src "libresoc.v:110883.5-110883.29" switch \initial - attribute \src "libresoc.v:110346.9-110346.17" + attribute \src "libresoc.v:110883.9-110883.17" case 1'1 case end @@ -171687,14 +173021,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] end - attribute \src "libresoc.v:110364.3-110382.6" - process $proc$libresoc.v:110364$4233 + attribute \src "libresoc.v:110901.3-110919.6" + process $proc$libresoc.v:110901$4287 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:110365.5-110365.29" + attribute \src "libresoc.v:110902.5-110902.29" switch \initial - attribute \src "libresoc.v:110365.9-110365.17" + attribute \src "libresoc.v:110902.9-110902.17" case 1'1 case end @@ -171722,14 +173056,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] end - attribute \src "libresoc.v:110383.3-110401.6" - process $proc$libresoc.v:110383$4234 + attribute \src "libresoc.v:110920.3-110938.6" + process $proc$libresoc.v:110920$4288 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:110384.5-110384.29" + attribute \src "libresoc.v:110921.5-110921.29" switch \initial - attribute \src "libresoc.v:110384.9-110384.17" + attribute \src "libresoc.v:110921.9-110921.17" case 1'1 case end @@ -171757,14 +173091,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] end - attribute \src "libresoc.v:110402.3-110420.6" - process $proc$libresoc.v:110402$4235 + attribute \src "libresoc.v:110939.3-110957.6" + process $proc$libresoc.v:110939$4289 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:110403.5-110403.29" + attribute \src "libresoc.v:110940.5-110940.29" switch \initial - attribute \src "libresoc.v:110403.9-110403.17" + attribute \src "libresoc.v:110940.9-110940.17" case 1'1 case end @@ -171792,14 +173126,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] end - attribute \src "libresoc.v:110421.3-110439.6" - process $proc$libresoc.v:110421$4236 + attribute \src "libresoc.v:110958.3-110976.6" + process $proc$libresoc.v:110958$4290 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:110422.5-110422.29" + attribute \src "libresoc.v:110959.5-110959.29" switch \initial - attribute \src "libresoc.v:110422.9-110422.17" + attribute \src "libresoc.v:110959.9-110959.17" case 1'1 case end @@ -171827,14 +173161,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] end - attribute \src "libresoc.v:110440.3-110458.6" - process $proc$libresoc.v:110440$4237 + attribute \src "libresoc.v:110977.3-110995.6" + process $proc$libresoc.v:110977$4291 assign { } { } assign { } { } assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:110441.5-110441.29" + attribute \src "libresoc.v:110978.5-110978.29" switch \initial - attribute \src "libresoc.v:110441.9-110441.17" + attribute \src "libresoc.v:110978.9-110978.17" case 1'1 case end @@ -171862,14 +173196,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:110459.3-110477.6" - process $proc$libresoc.v:110459$4238 + attribute \src "libresoc.v:110996.3-111014.6" + process $proc$libresoc.v:110996$4292 assign { } { } assign { } { } assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:110460.5-110460.29" + attribute \src "libresoc.v:110997.5-110997.29" switch \initial - attribute \src "libresoc.v:110460.9-110460.17" + attribute \src "libresoc.v:110997.9-110997.17" case 1'1 case end @@ -171897,14 +173231,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "libresoc.v:110478.3-110496.6" - process $proc$libresoc.v:110478$4239 + attribute \src "libresoc.v:111015.3-111033.6" + process $proc$libresoc.v:111015$4293 assign { } { } assign { } { } assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:110479.5-110479.29" + attribute \src "libresoc.v:111016.5-111016.29" switch \initial - attribute \src "libresoc.v:110479.9-110479.17" + attribute \src "libresoc.v:111016.9-111016.17" case 1'1 case end @@ -171932,14 +173266,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:110497.3-110515.6" - process $proc$libresoc.v:110497$4240 + attribute \src "libresoc.v:111034.3-111052.6" + process $proc$libresoc.v:111034$4294 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:110498.5-110498.29" + attribute \src "libresoc.v:111035.5-111035.29" switch \initial - attribute \src "libresoc.v:110498.9-110498.17" + attribute \src "libresoc.v:111035.9-111035.17" case 1'1 case end @@ -171967,14 +173301,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:110516.3-110534.6" - process $proc$libresoc.v:110516$4241 + attribute \src "libresoc.v:111053.3-111071.6" + process $proc$libresoc.v:111053$4295 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:110517.5-110517.29" + attribute \src "libresoc.v:111054.5-111054.29" switch \initial - attribute \src "libresoc.v:110517.9-110517.17" + attribute \src "libresoc.v:111054.9-111054.17" case 1'1 case end @@ -172002,14 +173336,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:110535.3-110553.6" - process $proc$libresoc.v:110535$4242 + attribute \src "libresoc.v:111072.3-111090.6" + process $proc$libresoc.v:111072$4296 assign { } { } assign { } { } assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:110536.5-110536.29" + attribute \src "libresoc.v:111073.5-111073.29" switch \initial - attribute \src "libresoc.v:110536.9-110536.17" + attribute \src "libresoc.v:111073.9-111073.17" case 1'1 case end @@ -172037,14 +173371,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "libresoc.v:110554.3-110572.6" - process $proc$libresoc.v:110554$4243 + attribute \src "libresoc.v:111091.3-111109.6" + process $proc$libresoc.v:111091$4297 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:110555.5-110555.29" + attribute \src "libresoc.v:111092.5-111092.29" switch \initial - attribute \src "libresoc.v:110555.9-110555.17" + attribute \src "libresoc.v:111092.9-111092.17" case 1'1 case end @@ -172072,14 +173406,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:110573.3-110591.6" - process $proc$libresoc.v:110573$4244 + attribute \src "libresoc.v:111110.3-111128.6" + process $proc$libresoc.v:111110$4298 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:110574.5-110574.29" + attribute \src "libresoc.v:111111.5-111111.29" switch \initial - attribute \src "libresoc.v:110574.9-110574.17" + attribute \src "libresoc.v:111111.9-111111.17" case 1'1 case end @@ -172107,14 +173441,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "libresoc.v:110592.3-110610.6" - process $proc$libresoc.v:110592$4245 + attribute \src "libresoc.v:111129.3-111147.6" + process $proc$libresoc.v:111129$4299 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:110593.5-110593.29" + attribute \src "libresoc.v:111130.5-111130.29" switch \initial - attribute \src "libresoc.v:110593.9-110593.17" + attribute \src "libresoc.v:111130.9-111130.17" case 1'1 case end @@ -172142,14 +173476,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "libresoc.v:110611.3-110629.6" - process $proc$libresoc.v:110611$4246 + attribute \src "libresoc.v:111148.3-111166.6" + process $proc$libresoc.v:111148$4300 assign { } { } assign { } { } assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:110612.5-110612.29" + attribute \src "libresoc.v:111149.5-111149.29" switch \initial - attribute \src "libresoc.v:110612.9-110612.17" + attribute \src "libresoc.v:111149.9-111149.17" case 1'1 case end @@ -172177,14 +173511,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "libresoc.v:110630.3-110648.6" - process $proc$libresoc.v:110630$4247 + attribute \src "libresoc.v:111167.3-111185.6" + process $proc$libresoc.v:111167$4301 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:110631.5-110631.29" + attribute \src "libresoc.v:111168.5-111168.29" switch \initial - attribute \src "libresoc.v:110631.9-110631.17" + attribute \src "libresoc.v:111168.9-111168.17" case 1'1 case end @@ -172212,14 +173546,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end - attribute \src "libresoc.v:110649.3-110667.6" - process $proc$libresoc.v:110649$4248 + attribute \src "libresoc.v:111186.3-111204.6" + process $proc$libresoc.v:111186$4302 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:110650.5-110650.29" + attribute \src "libresoc.v:111187.5-111187.29" switch \initial - attribute \src "libresoc.v:110650.9-110650.17" + attribute \src "libresoc.v:111187.9-111187.17" case 1'1 case end @@ -172247,14 +173581,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:110668.3-110686.6" - process $proc$libresoc.v:110668$4249 + attribute \src "libresoc.v:111205.3-111223.6" + process $proc$libresoc.v:111205$4303 assign { } { } assign { } { } assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:110669.5-110669.29" + attribute \src "libresoc.v:111206.5-111206.29" switch \initial - attribute \src "libresoc.v:110669.9-110669.17" + attribute \src "libresoc.v:111206.9-111206.17" case 1'1 case end @@ -172282,14 +173616,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:110687.3-110705.6" - process $proc$libresoc.v:110687$4250 + attribute \src "libresoc.v:111224.3-111242.6" + process $proc$libresoc.v:111224$4304 assign { } { } assign { } { } assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:110688.5-110688.29" + attribute \src "libresoc.v:111225.5-111225.29" switch \initial - attribute \src "libresoc.v:110688.9-110688.17" + attribute \src "libresoc.v:111225.9-111225.17" case 1'1 case end @@ -172317,14 +173651,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "libresoc.v:110706.3-110724.6" - process $proc$libresoc.v:110706$4251 + attribute \src "libresoc.v:111243.3-111261.6" + process $proc$libresoc.v:111243$4305 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:110707.5-110707.29" + attribute \src "libresoc.v:111244.5-111244.29" switch \initial - attribute \src "libresoc.v:110707.9-110707.17" + attribute \src "libresoc.v:111244.9-111244.17" case 1'1 case end @@ -172352,14 +173686,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:110725.3-110743.6" - process $proc$libresoc.v:110725$4252 + attribute \src "libresoc.v:111262.3-111280.6" + process $proc$libresoc.v:111262$4306 assign { } { } assign { } { } assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:110726.5-110726.29" + attribute \src "libresoc.v:111263.5-111263.29" switch \initial - attribute \src "libresoc.v:110726.9-110726.17" + attribute \src "libresoc.v:111263.9-111263.17" case 1'1 case end @@ -172387,14 +173721,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end - attribute \src "libresoc.v:110744.3-110762.6" - process $proc$libresoc.v:110744$4253 + attribute \src "libresoc.v:111281.3-111299.6" + process $proc$libresoc.v:111281$4307 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:110745.5-110745.29" + attribute \src "libresoc.v:111282.5-111282.29" switch \initial - attribute \src "libresoc.v:110745.9-110745.17" + attribute \src "libresoc.v:111282.9-111282.17" case 1'1 case end @@ -172422,14 +173756,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end - attribute \src "libresoc.v:110763.3-110781.6" - process $proc$libresoc.v:110763$4254 + attribute \src "libresoc.v:111300.3-111318.6" + process $proc$libresoc.v:111300$4308 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:110764.5-110764.29" + attribute \src "libresoc.v:111301.5-111301.29" switch \initial - attribute \src "libresoc.v:110764.9-110764.17" + attribute \src "libresoc.v:111301.9-111301.17" case 1'1 case end @@ -172457,14 +173791,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] end - attribute \src "libresoc.v:110782.3-110800.6" - process $proc$libresoc.v:110782$4255 + attribute \src "libresoc.v:111319.3-111337.6" + process $proc$libresoc.v:111319$4309 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:110783.5-110783.29" + attribute \src "libresoc.v:111320.5-111320.29" switch \initial - attribute \src "libresoc.v:110783.9-110783.17" + attribute \src "libresoc.v:111320.9-111320.17" case 1'1 case end @@ -172492,14 +173826,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] end - attribute \src "libresoc.v:110801.3-110819.6" - process $proc$libresoc.v:110801$4256 + attribute \src "libresoc.v:111338.3-111356.6" + process $proc$libresoc.v:111338$4310 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:110802.5-110802.29" + attribute \src "libresoc.v:111339.5-111339.29" switch \initial - attribute \src "libresoc.v:110802.9-110802.17" + attribute \src "libresoc.v:111339.9-111339.17" case 1'1 case end @@ -172527,14 +173861,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end - attribute \src "libresoc.v:110820.3-110838.6" - process $proc$libresoc.v:110820$4257 + attribute \src "libresoc.v:111357.3-111375.6" + process $proc$libresoc.v:111357$4311 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:110821.5-110821.29" + attribute \src "libresoc.v:111358.5-111358.29" switch \initial - attribute \src "libresoc.v:110821.9-110821.17" + attribute \src "libresoc.v:111358.9-111358.17" case 1'1 case end @@ -172562,14 +173896,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:110839.3-110857.6" - process $proc$libresoc.v:110839$4258 + attribute \src "libresoc.v:111376.3-111394.6" + process $proc$libresoc.v:111376$4312 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:110840.5-110840.29" + attribute \src "libresoc.v:111377.5-111377.29" switch \initial - attribute \src "libresoc.v:110840.9-110840.17" + attribute \src "libresoc.v:111377.9-111377.17" case 1'1 case end @@ -172597,14 +173931,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end - attribute \src "libresoc.v:110858.3-110876.6" - process $proc$libresoc.v:110858$4259 + attribute \src "libresoc.v:111395.3-111413.6" + process $proc$libresoc.v:111395$4313 assign { } { } assign { } { } assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:110859.5-110859.29" + attribute \src "libresoc.v:111396.5-111396.29" switch \initial - attribute \src "libresoc.v:110859.9-110859.17" + attribute \src "libresoc.v:111396.9-111396.17" case 1'1 case end @@ -172634,140 +173968,140 @@ module \dec31_dec_sub27 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:110882.1-112402.10" +attribute \src "libresoc.v:111419.1-112940.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" attribute \generator "nMigen" module \dec31_dec_sub28 - attribute \src "libresoc.v:112179.3-112215.6" + attribute \src "libresoc.v:112717.3-112753.6" wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:112216.3-112252.6" + attribute \src "libresoc.v:112754.3-112790.6" wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:111735.3-111771.6" + attribute \src "libresoc.v:112273.3-112309.6" wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:111883.3-111919.6" + attribute \src "libresoc.v:112421.3-112457.6" wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:111254.3-111290.6" + attribute \src "libresoc.v:111792.3-111828.6" wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:111291.3-111327.6" + attribute \src "libresoc.v:111829.3-111865.6" wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:111698.3-111734.6" + attribute \src "libresoc.v:112236.3-112272.6" wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:111846.3-111882.6" + attribute \src "libresoc.v:112384.3-112420.6" wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:112031.3-112067.6" + attribute \src "libresoc.v:112569.3-112605.6" wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:111217.3-111253.6" + attribute \src "libresoc.v:111755.3-111791.6" wire width 13 $0\dec31_dec_sub28_function_unit[12:0] - attribute \src "libresoc.v:112253.3-112289.6" + attribute \src "libresoc.v:112791.3-112827.6" wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:112290.3-112326.6" + attribute \src "libresoc.v:112828.3-112864.6" wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:112327.3-112363.6" + attribute \src "libresoc.v:112865.3-112901.6" wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:111624.3-111660.6" + attribute \src "libresoc.v:112162.3-112198.6" wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:111772.3-111808.6" + attribute \src "libresoc.v:112310.3-112346.6" wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:111809.3-111845.6" + attribute \src "libresoc.v:112347.3-112383.6" wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:111994.3-112030.6" + attribute \src "libresoc.v:112532.3-112568.6" wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:111550.3-111586.6" + attribute \src "libresoc.v:112088.3-112124.6" wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:112105.3-112141.6" + attribute \src "libresoc.v:112643.3-112679.6" wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:112364.3-112400.6" + attribute \src "libresoc.v:112902.3-112938.6" wire width 2 $0\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:111661.3-111697.6" + attribute \src "libresoc.v:112199.3-112235.6" wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:111957.3-111993.6" + attribute \src "libresoc.v:112495.3-112531.6" wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:112142.3-112178.6" + attribute \src "libresoc.v:112680.3-112716.6" wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:112068.3-112104.6" + attribute \src "libresoc.v:112606.3-112642.6" wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:111920.3-111956.6" + attribute \src "libresoc.v:112458.3-112494.6" wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:111476.3-111512.6" + attribute \src "libresoc.v:112014.3-112050.6" wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:111513.3-111549.6" + attribute \src "libresoc.v:112051.3-112087.6" wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:111328.3-111364.6" + attribute \src "libresoc.v:111866.3-111902.6" wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:111365.3-111401.6" + attribute \src "libresoc.v:111903.3-111939.6" wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:111402.3-111438.6" + attribute \src "libresoc.v:111940.3-111976.6" wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:111439.3-111475.6" + attribute \src "libresoc.v:111977.3-112013.6" wire width 3 $0\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:111587.3-111623.6" + attribute \src "libresoc.v:112125.3-112161.6" wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:110883.7-110883.20" + attribute \src "libresoc.v:111420.7-111420.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112179.3-112215.6" + attribute \src "libresoc.v:112717.3-112753.6" wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:112216.3-112252.6" + attribute \src "libresoc.v:112754.3-112790.6" wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:111735.3-111771.6" + attribute \src "libresoc.v:112273.3-112309.6" wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:111883.3-111919.6" + attribute \src "libresoc.v:112421.3-112457.6" wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:111254.3-111290.6" + attribute \src "libresoc.v:111792.3-111828.6" wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:111291.3-111327.6" + attribute \src "libresoc.v:111829.3-111865.6" wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:111698.3-111734.6" + attribute \src "libresoc.v:112236.3-112272.6" wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:111846.3-111882.6" + attribute \src "libresoc.v:112384.3-112420.6" wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:112031.3-112067.6" + attribute \src "libresoc.v:112569.3-112605.6" wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:111217.3-111253.6" + attribute \src "libresoc.v:111755.3-111791.6" wire width 13 $1\dec31_dec_sub28_function_unit[12:0] - attribute \src "libresoc.v:112253.3-112289.6" + attribute \src "libresoc.v:112791.3-112827.6" wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:112290.3-112326.6" + attribute \src "libresoc.v:112828.3-112864.6" wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:112327.3-112363.6" + attribute \src "libresoc.v:112865.3-112901.6" wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:111624.3-111660.6" + attribute \src "libresoc.v:112162.3-112198.6" wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:111772.3-111808.6" + attribute \src "libresoc.v:112310.3-112346.6" wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:111809.3-111845.6" + attribute \src "libresoc.v:112347.3-112383.6" wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:111994.3-112030.6" + attribute \src "libresoc.v:112532.3-112568.6" wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:111550.3-111586.6" + attribute \src "libresoc.v:112088.3-112124.6" wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:112105.3-112141.6" + attribute \src "libresoc.v:112643.3-112679.6" wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:112364.3-112400.6" + attribute \src "libresoc.v:112902.3-112938.6" wire width 2 $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:111661.3-111697.6" + attribute \src "libresoc.v:112199.3-112235.6" wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:111957.3-111993.6" + attribute \src "libresoc.v:112495.3-112531.6" wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:112142.3-112178.6" + attribute \src "libresoc.v:112680.3-112716.6" wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:112068.3-112104.6" + attribute \src "libresoc.v:112606.3-112642.6" wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:111920.3-111956.6" + attribute \src "libresoc.v:112458.3-112494.6" wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:111476.3-111512.6" + attribute \src "libresoc.v:112014.3-112050.6" wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:111513.3-111549.6" + attribute \src "libresoc.v:112051.3-112087.6" wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:111328.3-111364.6" + attribute \src "libresoc.v:111866.3-111902.6" wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:111365.3-111401.6" + attribute \src "libresoc.v:111903.3-111939.6" wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:111402.3-111438.6" + attribute \src "libresoc.v:111940.3-111976.6" wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:111439.3-111475.6" + attribute \src "libresoc.v:111977.3-112013.6" wire width 3 $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:111587.3-111623.6" + attribute \src "libresoc.v:112125.3-112161.6" wire width 2 $1\dec31_dec_sub28_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -172843,6 +174177,7 @@ module \dec31_dec_sub28 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub28_form attribute \enum_base_type "Function" @@ -173066,28 +174401,28 @@ module \dec31_dec_sub28 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub28_upd - attribute \src "libresoc.v:110883.7-110883.15" + attribute \src "libresoc.v:111420.7-111420.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:110883.7-110883.20" - process $proc$libresoc.v:110883$4293 + attribute \src "libresoc.v:111420.7-111420.20" + process $proc$libresoc.v:111420$4347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:111217.3-111253.6" - process $proc$libresoc.v:111217$4261 + attribute \src "libresoc.v:111755.3-111791.6" + process $proc$libresoc.v:111755$4315 assign { } { } assign { } { } assign $0\dec31_dec_sub28_function_unit[12:0] $1\dec31_dec_sub28_function_unit[12:0] - attribute \src "libresoc.v:111218.5-111218.29" + attribute \src "libresoc.v:111756.5-111756.29" switch \initial - attribute \src "libresoc.v:111218.9-111218.17" + attribute \src "libresoc.v:111756.9-111756.17" case 1'1 case end @@ -173139,14 +174474,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[12:0] end - attribute \src "libresoc.v:111254.3-111290.6" - process $proc$libresoc.v:111254$4262 + attribute \src "libresoc.v:111792.3-111828.6" + process $proc$libresoc.v:111792$4316 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:111255.5-111255.29" + attribute \src "libresoc.v:111793.5-111793.29" switch \initial - attribute \src "libresoc.v:111255.9-111255.17" + attribute \src "libresoc.v:111793.9-111793.17" case 1'1 case end @@ -173198,14 +174533,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:111291.3-111327.6" - process $proc$libresoc.v:111291$4263 + attribute \src "libresoc.v:111829.3-111865.6" + process $proc$libresoc.v:111829$4317 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:111292.5-111292.29" + attribute \src "libresoc.v:111830.5-111830.29" switch \initial - attribute \src "libresoc.v:111292.9-111292.17" + attribute \src "libresoc.v:111830.9-111830.17" case 1'1 case end @@ -173257,14 +174592,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end - attribute \src "libresoc.v:111328.3-111364.6" - process $proc$libresoc.v:111328$4264 + attribute \src "libresoc.v:111866.3-111902.6" + process $proc$libresoc.v:111866$4318 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:111329.5-111329.29" + attribute \src "libresoc.v:111867.5-111867.29" switch \initial - attribute \src "libresoc.v:111329.9-111329.17" + attribute \src "libresoc.v:111867.9-111867.17" case 1'1 case end @@ -173316,14 +174651,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] end - attribute \src "libresoc.v:111365.3-111401.6" - process $proc$libresoc.v:111365$4265 + attribute \src "libresoc.v:111903.3-111939.6" + process $proc$libresoc.v:111903$4319 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:111366.5-111366.29" + attribute \src "libresoc.v:111904.5-111904.29" switch \initial - attribute \src "libresoc.v:111366.9-111366.17" + attribute \src "libresoc.v:111904.9-111904.17" case 1'1 case end @@ -173375,14 +174710,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] end - attribute \src "libresoc.v:111402.3-111438.6" - process $proc$libresoc.v:111402$4266 + attribute \src "libresoc.v:111940.3-111976.6" + process $proc$libresoc.v:111940$4320 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:111403.5-111403.29" + attribute \src "libresoc.v:111941.5-111941.29" switch \initial - attribute \src "libresoc.v:111403.9-111403.17" + attribute \src "libresoc.v:111941.9-111941.17" case 1'1 case end @@ -173434,14 +174769,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] end - attribute \src "libresoc.v:111439.3-111475.6" - process $proc$libresoc.v:111439$4267 + attribute \src "libresoc.v:111977.3-112013.6" + process $proc$libresoc.v:111977$4321 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:111440.5-111440.29" + attribute \src "libresoc.v:111978.5-111978.29" switch \initial - attribute \src "libresoc.v:111440.9-111440.17" + attribute \src "libresoc.v:111978.9-111978.17" case 1'1 case end @@ -173493,14 +174828,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] end - attribute \src "libresoc.v:111476.3-111512.6" - process $proc$libresoc.v:111476$4268 + attribute \src "libresoc.v:112014.3-112050.6" + process $proc$libresoc.v:112014$4322 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:111477.5-111477.29" + attribute \src "libresoc.v:112015.5-112015.29" switch \initial - attribute \src "libresoc.v:111477.9-111477.17" + attribute \src "libresoc.v:112015.9-112015.17" case 1'1 case end @@ -173552,14 +174887,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] end - attribute \src "libresoc.v:111513.3-111549.6" - process $proc$libresoc.v:111513$4269 + attribute \src "libresoc.v:112051.3-112087.6" + process $proc$libresoc.v:112051$4323 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:111514.5-111514.29" + attribute \src "libresoc.v:112052.5-112052.29" switch \initial - attribute \src "libresoc.v:111514.9-111514.17" + attribute \src "libresoc.v:112052.9-112052.17" case 1'1 case end @@ -173611,14 +174946,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] end - attribute \src "libresoc.v:111550.3-111586.6" - process $proc$libresoc.v:111550$4270 + attribute \src "libresoc.v:112088.3-112124.6" + process $proc$libresoc.v:112088$4324 assign { } { } assign { } { } assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:111551.5-111551.29" + attribute \src "libresoc.v:112089.5-112089.29" switch \initial - attribute \src "libresoc.v:111551.9-111551.17" + attribute \src "libresoc.v:112089.9-112089.17" case 1'1 case end @@ -173670,14 +175005,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:111587.3-111623.6" - process $proc$libresoc.v:111587$4271 + attribute \src "libresoc.v:112125.3-112161.6" + process $proc$libresoc.v:112125$4325 assign { } { } assign { } { } assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:111588.5-111588.29" + attribute \src "libresoc.v:112126.5-112126.29" switch \initial - attribute \src "libresoc.v:111588.9-111588.17" + attribute \src "libresoc.v:112126.9-112126.17" case 1'1 case end @@ -173729,14 +175064,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "libresoc.v:111624.3-111660.6" - process $proc$libresoc.v:111624$4272 + attribute \src "libresoc.v:112162.3-112198.6" + process $proc$libresoc.v:112162$4326 assign { } { } assign { } { } assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:111625.5-111625.29" + attribute \src "libresoc.v:112163.5-112163.29" switch \initial - attribute \src "libresoc.v:111625.9-111625.17" + attribute \src "libresoc.v:112163.9-112163.17" case 1'1 case end @@ -173788,14 +175123,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:111661.3-111697.6" - process $proc$libresoc.v:111661$4273 + attribute \src "libresoc.v:112199.3-112235.6" + process $proc$libresoc.v:112199$4327 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:111662.5-111662.29" + attribute \src "libresoc.v:112200.5-112200.29" switch \initial - attribute \src "libresoc.v:111662.9-111662.17" + attribute \src "libresoc.v:112200.9-112200.17" case 1'1 case end @@ -173847,14 +175182,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:111698.3-111734.6" - process $proc$libresoc.v:111698$4274 + attribute \src "libresoc.v:112236.3-112272.6" + process $proc$libresoc.v:112236$4328 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:111699.5-111699.29" + attribute \src "libresoc.v:112237.5-112237.29" switch \initial - attribute \src "libresoc.v:111699.9-111699.17" + attribute \src "libresoc.v:112237.9-112237.17" case 1'1 case end @@ -173906,14 +175241,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:111735.3-111771.6" - process $proc$libresoc.v:111735$4275 + attribute \src "libresoc.v:112273.3-112309.6" + process $proc$libresoc.v:112273$4329 assign { } { } assign { } { } assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:111736.5-111736.29" + attribute \src "libresoc.v:112274.5-112274.29" switch \initial - attribute \src "libresoc.v:111736.9-111736.17" + attribute \src "libresoc.v:112274.9-112274.17" case 1'1 case end @@ -173965,14 +175300,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:111772.3-111808.6" - process $proc$libresoc.v:111772$4276 + attribute \src "libresoc.v:112310.3-112346.6" + process $proc$libresoc.v:112310$4330 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:111773.5-111773.29" + attribute \src "libresoc.v:112311.5-112311.29" switch \initial - attribute \src "libresoc.v:111773.9-111773.17" + attribute \src "libresoc.v:112311.9-112311.17" case 1'1 case end @@ -174024,14 +175359,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:111809.3-111845.6" - process $proc$libresoc.v:111809$4277 + attribute \src "libresoc.v:112347.3-112383.6" + process $proc$libresoc.v:112347$4331 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:111810.5-111810.29" + attribute \src "libresoc.v:112348.5-112348.29" switch \initial - attribute \src "libresoc.v:111810.9-111810.17" + attribute \src "libresoc.v:112348.9-112348.17" case 1'1 case end @@ -174083,14 +175418,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:111846.3-111882.6" - process $proc$libresoc.v:111846$4278 + attribute \src "libresoc.v:112384.3-112420.6" + process $proc$libresoc.v:112384$4332 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:111847.5-111847.29" + attribute \src "libresoc.v:112385.5-112385.29" switch \initial - attribute \src "libresoc.v:111847.9-111847.17" + attribute \src "libresoc.v:112385.9-112385.17" case 1'1 case end @@ -174142,14 +175477,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:111883.3-111919.6" - process $proc$libresoc.v:111883$4279 + attribute \src "libresoc.v:112421.3-112457.6" + process $proc$libresoc.v:112421$4333 assign { } { } assign { } { } assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:111884.5-111884.29" + attribute \src "libresoc.v:112422.5-112422.29" switch \initial - attribute \src "libresoc.v:111884.9-111884.17" + attribute \src "libresoc.v:112422.9-112422.17" case 1'1 case end @@ -174201,14 +175536,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "libresoc.v:111920.3-111956.6" - process $proc$libresoc.v:111920$4280 + attribute \src "libresoc.v:112458.3-112494.6" + process $proc$libresoc.v:112458$4334 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:111921.5-111921.29" + attribute \src "libresoc.v:112459.5-112459.29" switch \initial - attribute \src "libresoc.v:111921.9-111921.17" + attribute \src "libresoc.v:112459.9-112459.17" case 1'1 case end @@ -174260,14 +175595,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:111957.3-111993.6" - process $proc$libresoc.v:111957$4281 + attribute \src "libresoc.v:112495.3-112531.6" + process $proc$libresoc.v:112495$4335 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:111958.5-111958.29" + attribute \src "libresoc.v:112496.5-112496.29" switch \initial - attribute \src "libresoc.v:111958.9-111958.17" + attribute \src "libresoc.v:112496.9-112496.17" case 1'1 case end @@ -174319,14 +175654,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "libresoc.v:111994.3-112030.6" - process $proc$libresoc.v:111994$4282 + attribute \src "libresoc.v:112532.3-112568.6" + process $proc$libresoc.v:112532$4336 assign { } { } assign { } { } assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:111995.5-111995.29" + attribute \src "libresoc.v:112533.5-112533.29" switch \initial - attribute \src "libresoc.v:111995.9-111995.17" + attribute \src "libresoc.v:112533.9-112533.17" case 1'1 case end @@ -174378,14 +175713,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:112031.3-112067.6" - process $proc$libresoc.v:112031$4283 + attribute \src "libresoc.v:112569.3-112605.6" + process $proc$libresoc.v:112569$4337 assign { } { } assign { } { } assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:112032.5-112032.29" + attribute \src "libresoc.v:112570.5-112570.29" switch \initial - attribute \src "libresoc.v:112032.9-112032.17" + attribute \src "libresoc.v:112570.9-112570.17" case 1'1 case end @@ -174437,14 +175772,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "libresoc.v:112068.3-112104.6" - process $proc$libresoc.v:112068$4284 + attribute \src "libresoc.v:112606.3-112642.6" + process $proc$libresoc.v:112606$4338 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:112069.5-112069.29" + attribute \src "libresoc.v:112607.5-112607.29" switch \initial - attribute \src "libresoc.v:112069.9-112069.17" + attribute \src "libresoc.v:112607.9-112607.17" case 1'1 case end @@ -174496,14 +175831,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:112105.3-112141.6" - process $proc$libresoc.v:112105$4285 + attribute \src "libresoc.v:112643.3-112679.6" + process $proc$libresoc.v:112643$4339 assign { } { } assign { } { } assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:112106.5-112106.29" + attribute \src "libresoc.v:112644.5-112644.29" switch \initial - attribute \src "libresoc.v:112106.9-112106.17" + attribute \src "libresoc.v:112644.9-112644.17" case 1'1 case end @@ -174555,14 +175890,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "libresoc.v:112142.3-112178.6" - process $proc$libresoc.v:112142$4286 + attribute \src "libresoc.v:112680.3-112716.6" + process $proc$libresoc.v:112680$4340 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:112143.5-112143.29" + attribute \src "libresoc.v:112681.5-112681.29" switch \initial - attribute \src "libresoc.v:112143.9-112143.17" + attribute \src "libresoc.v:112681.9-112681.17" case 1'1 case end @@ -174614,14 +175949,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:112179.3-112215.6" - process $proc$libresoc.v:112179$4287 + attribute \src "libresoc.v:112717.3-112753.6" + process $proc$libresoc.v:112717$4341 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:112180.5-112180.29" + attribute \src "libresoc.v:112718.5-112718.29" switch \initial - attribute \src "libresoc.v:112180.9-112180.17" + attribute \src "libresoc.v:112718.9-112718.17" case 1'1 case end @@ -174673,14 +176008,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] end - attribute \src "libresoc.v:112216.3-112252.6" - process $proc$libresoc.v:112216$4288 + attribute \src "libresoc.v:112754.3-112790.6" + process $proc$libresoc.v:112754$4342 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:112217.5-112217.29" + attribute \src "libresoc.v:112755.5-112755.29" switch \initial - attribute \src "libresoc.v:112217.9-112217.17" + attribute \src "libresoc.v:112755.9-112755.17" case 1'1 case end @@ -174732,14 +176067,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] end - attribute \src "libresoc.v:112253.3-112289.6" - process $proc$libresoc.v:112253$4289 + attribute \src "libresoc.v:112791.3-112827.6" + process $proc$libresoc.v:112791$4343 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:112254.5-112254.29" + attribute \src "libresoc.v:112792.5-112792.29" switch \initial - attribute \src "libresoc.v:112254.9-112254.17" + attribute \src "libresoc.v:112792.9-112792.17" case 1'1 case end @@ -174791,14 +176126,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:112290.3-112326.6" - process $proc$libresoc.v:112290$4290 + attribute \src "libresoc.v:112828.3-112864.6" + process $proc$libresoc.v:112828$4344 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:112291.5-112291.29" + attribute \src "libresoc.v:112829.5-112829.29" switch \initial - attribute \src "libresoc.v:112291.9-112291.17" + attribute \src "libresoc.v:112829.9-112829.17" case 1'1 case end @@ -174850,14 +176185,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:112327.3-112363.6" - process $proc$libresoc.v:112327$4291 + attribute \src "libresoc.v:112865.3-112901.6" + process $proc$libresoc.v:112865$4345 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:112328.5-112328.29" + attribute \src "libresoc.v:112866.5-112866.29" switch \initial - attribute \src "libresoc.v:112328.9-112328.17" + attribute \src "libresoc.v:112866.9-112866.17" case 1'1 case end @@ -174909,14 +176244,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "libresoc.v:112364.3-112400.6" - process $proc$libresoc.v:112364$4292 + attribute \src "libresoc.v:112902.3-112938.6" + process $proc$libresoc.v:112902$4346 assign { } { } assign { } { } assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:112365.5-112365.29" + attribute \src "libresoc.v:112903.5-112903.29" switch \initial - attribute \src "libresoc.v:112365.9-112365.17" + attribute \src "libresoc.v:112903.9-112903.17" case 1'1 case end @@ -174970,140 +176305,140 @@ module \dec31_dec_sub28 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:112406.1-113158.10" +attribute \src "libresoc.v:112944.1-113697.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" module \dec31_dec_sub4 - attribute \src "libresoc.v:113079.3-113091.6" + attribute \src "libresoc.v:113618.3-113630.6" wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:113092.3-113104.6" + attribute \src "libresoc.v:113631.3-113643.6" wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:112923.3-112935.6" + attribute \src "libresoc.v:113462.3-113474.6" wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:112975.3-112987.6" + attribute \src "libresoc.v:113514.3-113526.6" wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:112754.3-112766.6" + attribute \src "libresoc.v:113293.3-113305.6" wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:112767.3-112779.6" + attribute \src "libresoc.v:113306.3-113318.6" wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:112910.3-112922.6" + attribute \src "libresoc.v:113449.3-113461.6" wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:112962.3-112974.6" + attribute \src "libresoc.v:113501.3-113513.6" wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:113027.3-113039.6" + attribute \src "libresoc.v:113566.3-113578.6" wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:112741.3-112753.6" + attribute \src "libresoc.v:113280.3-113292.6" wire width 13 $0\dec31_dec_sub4_function_unit[12:0] - attribute \src "libresoc.v:113105.3-113117.6" + attribute \src "libresoc.v:113644.3-113656.6" wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:113118.3-113130.6" + attribute \src "libresoc.v:113657.3-113669.6" wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:113131.3-113143.6" + attribute \src "libresoc.v:113670.3-113682.6" wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:112884.3-112896.6" + attribute \src "libresoc.v:113423.3-113435.6" wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:112936.3-112948.6" + attribute \src "libresoc.v:113475.3-113487.6" wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:112949.3-112961.6" + attribute \src "libresoc.v:113488.3-113500.6" wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:113014.3-113026.6" + attribute \src "libresoc.v:113553.3-113565.6" wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:112858.3-112870.6" + attribute \src "libresoc.v:113397.3-113409.6" wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:113053.3-113065.6" + attribute \src "libresoc.v:113592.3-113604.6" wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:113144.3-113156.6" + attribute \src "libresoc.v:113683.3-113695.6" wire width 2 $0\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:112897.3-112909.6" + attribute \src "libresoc.v:113436.3-113448.6" wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:113001.3-113013.6" + attribute \src "libresoc.v:113540.3-113552.6" wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:113066.3-113078.6" + attribute \src "libresoc.v:113605.3-113617.6" wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:113040.3-113052.6" + attribute \src "libresoc.v:113579.3-113591.6" wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:112988.3-113000.6" + attribute \src "libresoc.v:113527.3-113539.6" wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:112832.3-112844.6" + attribute \src "libresoc.v:113371.3-113383.6" wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:112845.3-112857.6" + attribute \src "libresoc.v:113384.3-113396.6" wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:112780.3-112792.6" + attribute \src "libresoc.v:113319.3-113331.6" wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:112793.3-112805.6" + attribute \src "libresoc.v:113332.3-113344.6" wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:112806.3-112818.6" + attribute \src "libresoc.v:113345.3-113357.6" wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:112819.3-112831.6" + attribute \src "libresoc.v:113358.3-113370.6" wire width 3 $0\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:112871.3-112883.6" + attribute \src "libresoc.v:113410.3-113422.6" wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:112407.7-112407.20" + attribute \src "libresoc.v:112945.7-112945.20" wire $0\initial[0:0] - attribute \src "libresoc.v:113079.3-113091.6" + attribute \src "libresoc.v:113618.3-113630.6" wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:113092.3-113104.6" + attribute \src "libresoc.v:113631.3-113643.6" wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:112923.3-112935.6" + attribute \src "libresoc.v:113462.3-113474.6" wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:112975.3-112987.6" + attribute \src "libresoc.v:113514.3-113526.6" wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:112754.3-112766.6" + attribute \src "libresoc.v:113293.3-113305.6" wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:112767.3-112779.6" + attribute \src "libresoc.v:113306.3-113318.6" wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:112910.3-112922.6" + attribute \src "libresoc.v:113449.3-113461.6" wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:112962.3-112974.6" + attribute \src "libresoc.v:113501.3-113513.6" wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:113027.3-113039.6" + attribute \src "libresoc.v:113566.3-113578.6" wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:112741.3-112753.6" + attribute \src "libresoc.v:113280.3-113292.6" wire width 13 $1\dec31_dec_sub4_function_unit[12:0] - attribute \src "libresoc.v:113105.3-113117.6" + attribute \src "libresoc.v:113644.3-113656.6" wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:113118.3-113130.6" + attribute \src "libresoc.v:113657.3-113669.6" wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:113131.3-113143.6" + attribute \src "libresoc.v:113670.3-113682.6" wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:112884.3-112896.6" + attribute \src "libresoc.v:113423.3-113435.6" wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:112936.3-112948.6" + attribute \src "libresoc.v:113475.3-113487.6" wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:112949.3-112961.6" + attribute \src "libresoc.v:113488.3-113500.6" wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:113014.3-113026.6" + attribute \src "libresoc.v:113553.3-113565.6" wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:112858.3-112870.6" + attribute \src "libresoc.v:113397.3-113409.6" wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:113053.3-113065.6" + attribute \src "libresoc.v:113592.3-113604.6" wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:113144.3-113156.6" + attribute \src "libresoc.v:113683.3-113695.6" wire width 2 $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:112897.3-112909.6" + attribute \src "libresoc.v:113436.3-113448.6" wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:113001.3-113013.6" + attribute \src "libresoc.v:113540.3-113552.6" wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:113066.3-113078.6" + attribute \src "libresoc.v:113605.3-113617.6" wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:113040.3-113052.6" + attribute \src "libresoc.v:113579.3-113591.6" wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:112988.3-113000.6" + attribute \src "libresoc.v:113527.3-113539.6" wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:112832.3-112844.6" + attribute \src "libresoc.v:113371.3-113383.6" wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:112845.3-112857.6" + attribute \src "libresoc.v:113384.3-113396.6" wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:112780.3-112792.6" + attribute \src "libresoc.v:113319.3-113331.6" wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:112793.3-112805.6" + attribute \src "libresoc.v:113332.3-113344.6" wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:112806.3-112818.6" + attribute \src "libresoc.v:113345.3-113357.6" wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:112819.3-112831.6" + attribute \src "libresoc.v:113358.3-113370.6" wire width 3 $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:112871.3-112883.6" + attribute \src "libresoc.v:113410.3-113422.6" wire width 2 $1\dec31_dec_sub4_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -175179,6 +176514,7 @@ module \dec31_dec_sub4 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub4_form attribute \enum_base_type "Function" @@ -175402,28 +176738,28 @@ module \dec31_dec_sub4 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub4_upd - attribute \src "libresoc.v:112407.7-112407.15" + attribute \src "libresoc.v:112945.7-112945.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:112407.7-112407.20" - process $proc$libresoc.v:112407$4326 + attribute \src "libresoc.v:112945.7-112945.20" + process $proc$libresoc.v:112945$4380 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:112741.3-112753.6" - process $proc$libresoc.v:112741$4294 + attribute \src "libresoc.v:113280.3-113292.6" + process $proc$libresoc.v:113280$4348 assign { } { } assign { } { } assign $0\dec31_dec_sub4_function_unit[12:0] $1\dec31_dec_sub4_function_unit[12:0] - attribute \src "libresoc.v:112742.5-112742.29" + attribute \src "libresoc.v:113281.5-113281.29" switch \initial - attribute \src "libresoc.v:112742.9-112742.17" + attribute \src "libresoc.v:113281.9-113281.17" case 1'1 case end @@ -175443,14 +176779,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[12:0] end - attribute \src "libresoc.v:112754.3-112766.6" - process $proc$libresoc.v:112754$4295 + attribute \src "libresoc.v:113293.3-113305.6" + process $proc$libresoc.v:113293$4349 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:112755.5-112755.29" + attribute \src "libresoc.v:113294.5-113294.29" switch \initial - attribute \src "libresoc.v:112755.9-112755.17" + attribute \src "libresoc.v:113294.9-113294.17" case 1'1 case end @@ -175470,14 +176806,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "libresoc.v:112767.3-112779.6" - process $proc$libresoc.v:112767$4296 + attribute \src "libresoc.v:113306.3-113318.6" + process $proc$libresoc.v:113306$4350 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:112768.5-112768.29" + attribute \src "libresoc.v:113307.5-113307.29" switch \initial - attribute \src "libresoc.v:112768.9-112768.17" + attribute \src "libresoc.v:113307.9-113307.17" case 1'1 case end @@ -175497,14 +176833,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] end - attribute \src "libresoc.v:112780.3-112792.6" - process $proc$libresoc.v:112780$4297 + attribute \src "libresoc.v:113319.3-113331.6" + process $proc$libresoc.v:113319$4351 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:112781.5-112781.29" + attribute \src "libresoc.v:113320.5-113320.29" switch \initial - attribute \src "libresoc.v:112781.9-112781.17" + attribute \src "libresoc.v:113320.9-113320.17" case 1'1 case end @@ -175524,14 +176860,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] end - attribute \src "libresoc.v:112793.3-112805.6" - process $proc$libresoc.v:112793$4298 + attribute \src "libresoc.v:113332.3-113344.6" + process $proc$libresoc.v:113332$4352 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:112794.5-112794.29" + attribute \src "libresoc.v:113333.5-113333.29" switch \initial - attribute \src "libresoc.v:112794.9-112794.17" + attribute \src "libresoc.v:113333.9-113333.17" case 1'1 case end @@ -175551,14 +176887,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] end - attribute \src "libresoc.v:112806.3-112818.6" - process $proc$libresoc.v:112806$4299 + attribute \src "libresoc.v:113345.3-113357.6" + process $proc$libresoc.v:113345$4353 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:112807.5-112807.29" + attribute \src "libresoc.v:113346.5-113346.29" switch \initial - attribute \src "libresoc.v:112807.9-112807.17" + attribute \src "libresoc.v:113346.9-113346.17" case 1'1 case end @@ -175578,14 +176914,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] end - attribute \src "libresoc.v:112819.3-112831.6" - process $proc$libresoc.v:112819$4300 + attribute \src "libresoc.v:113358.3-113370.6" + process $proc$libresoc.v:113358$4354 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:112820.5-112820.29" + attribute \src "libresoc.v:113359.5-113359.29" switch \initial - attribute \src "libresoc.v:112820.9-112820.17" + attribute \src "libresoc.v:113359.9-113359.17" case 1'1 case end @@ -175605,14 +176941,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] end - attribute \src "libresoc.v:112832.3-112844.6" - process $proc$libresoc.v:112832$4301 + attribute \src "libresoc.v:113371.3-113383.6" + process $proc$libresoc.v:113371$4355 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:112833.5-112833.29" + attribute \src "libresoc.v:113372.5-113372.29" switch \initial - attribute \src "libresoc.v:112833.9-112833.17" + attribute \src "libresoc.v:113372.9-113372.17" case 1'1 case end @@ -175632,14 +176968,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] end - attribute \src "libresoc.v:112845.3-112857.6" - process $proc$libresoc.v:112845$4302 + attribute \src "libresoc.v:113384.3-113396.6" + process $proc$libresoc.v:113384$4356 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:112846.5-112846.29" + attribute \src "libresoc.v:113385.5-113385.29" switch \initial - attribute \src "libresoc.v:112846.9-112846.17" + attribute \src "libresoc.v:113385.9-113385.17" case 1'1 case end @@ -175659,14 +176995,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] end - attribute \src "libresoc.v:112858.3-112870.6" - process $proc$libresoc.v:112858$4303 + attribute \src "libresoc.v:113397.3-113409.6" + process $proc$libresoc.v:113397$4357 assign { } { } assign { } { } assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:112859.5-112859.29" + attribute \src "libresoc.v:113398.5-113398.29" switch \initial - attribute \src "libresoc.v:112859.9-112859.17" + attribute \src "libresoc.v:113398.9-113398.17" case 1'1 case end @@ -175686,14 +177022,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "libresoc.v:112871.3-112883.6" - process $proc$libresoc.v:112871$4304 + attribute \src "libresoc.v:113410.3-113422.6" + process $proc$libresoc.v:113410$4358 assign { } { } assign { } { } assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:112872.5-112872.29" + attribute \src "libresoc.v:113411.5-113411.29" switch \initial - attribute \src "libresoc.v:112872.9-112872.17" + attribute \src "libresoc.v:113411.9-113411.17" case 1'1 case end @@ -175713,14 +177049,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end - attribute \src "libresoc.v:112884.3-112896.6" - process $proc$libresoc.v:112884$4305 + attribute \src "libresoc.v:113423.3-113435.6" + process $proc$libresoc.v:113423$4359 assign { } { } assign { } { } assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:112885.5-112885.29" + attribute \src "libresoc.v:113424.5-113424.29" switch \initial - attribute \src "libresoc.v:112885.9-112885.17" + attribute \src "libresoc.v:113424.9-113424.17" case 1'1 case end @@ -175740,14 +177076,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end - attribute \src "libresoc.v:112897.3-112909.6" - process $proc$libresoc.v:112897$4306 + attribute \src "libresoc.v:113436.3-113448.6" + process $proc$libresoc.v:113436$4360 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:112898.5-112898.29" + attribute \src "libresoc.v:113437.5-113437.29" switch \initial - attribute \src "libresoc.v:112898.9-112898.17" + attribute \src "libresoc.v:113437.9-113437.17" case 1'1 case end @@ -175767,14 +177103,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end - attribute \src "libresoc.v:112910.3-112922.6" - process $proc$libresoc.v:112910$4307 + attribute \src "libresoc.v:113449.3-113461.6" + process $proc$libresoc.v:113449$4361 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:112911.5-112911.29" + attribute \src "libresoc.v:113450.5-113450.29" switch \initial - attribute \src "libresoc.v:112911.9-112911.17" + attribute \src "libresoc.v:113450.9-113450.17" case 1'1 case end @@ -175794,14 +177130,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "libresoc.v:112923.3-112935.6" - process $proc$libresoc.v:112923$4308 + attribute \src "libresoc.v:113462.3-113474.6" + process $proc$libresoc.v:113462$4362 assign { } { } assign { } { } assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:112924.5-112924.29" + attribute \src "libresoc.v:113463.5-113463.29" switch \initial - attribute \src "libresoc.v:112924.9-112924.17" + attribute \src "libresoc.v:113463.9-113463.17" case 1'1 case end @@ -175821,14 +177157,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end - attribute \src "libresoc.v:112936.3-112948.6" - process $proc$libresoc.v:112936$4309 + attribute \src "libresoc.v:113475.3-113487.6" + process $proc$libresoc.v:113475$4363 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:112937.5-112937.29" + attribute \src "libresoc.v:113476.5-113476.29" switch \initial - attribute \src "libresoc.v:112937.9-112937.17" + attribute \src "libresoc.v:113476.9-113476.17" case 1'1 case end @@ -175848,14 +177184,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end - attribute \src "libresoc.v:112949.3-112961.6" - process $proc$libresoc.v:112949$4310 + attribute \src "libresoc.v:113488.3-113500.6" + process $proc$libresoc.v:113488$4364 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:112950.5-112950.29" + attribute \src "libresoc.v:113489.5-113489.29" switch \initial - attribute \src "libresoc.v:112950.9-112950.17" + attribute \src "libresoc.v:113489.9-113489.17" case 1'1 case end @@ -175875,14 +177211,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end - attribute \src "libresoc.v:112962.3-112974.6" - process $proc$libresoc.v:112962$4311 + attribute \src "libresoc.v:113501.3-113513.6" + process $proc$libresoc.v:113501$4365 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:112963.5-112963.29" + attribute \src "libresoc.v:113502.5-113502.29" switch \initial - attribute \src "libresoc.v:112963.9-112963.17" + attribute \src "libresoc.v:113502.9-113502.17" case 1'1 case end @@ -175902,14 +177238,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end - attribute \src "libresoc.v:112975.3-112987.6" - process $proc$libresoc.v:112975$4312 + attribute \src "libresoc.v:113514.3-113526.6" + process $proc$libresoc.v:113514$4366 assign { } { } assign { } { } assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:112976.5-112976.29" + attribute \src "libresoc.v:113515.5-113515.29" switch \initial - attribute \src "libresoc.v:112976.9-112976.17" + attribute \src "libresoc.v:113515.9-113515.17" case 1'1 case end @@ -175929,14 +177265,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end - attribute \src "libresoc.v:112988.3-113000.6" - process $proc$libresoc.v:112988$4313 + attribute \src "libresoc.v:113527.3-113539.6" + process $proc$libresoc.v:113527$4367 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:112989.5-112989.29" + attribute \src "libresoc.v:113528.5-113528.29" switch \initial - attribute \src "libresoc.v:112989.9-112989.17" + attribute \src "libresoc.v:113528.9-113528.17" case 1'1 case end @@ -175956,14 +177292,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end - attribute \src "libresoc.v:113001.3-113013.6" - process $proc$libresoc.v:113001$4314 + attribute \src "libresoc.v:113540.3-113552.6" + process $proc$libresoc.v:113540$4368 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:113002.5-113002.29" + attribute \src "libresoc.v:113541.5-113541.29" switch \initial - attribute \src "libresoc.v:113002.9-113002.17" + attribute \src "libresoc.v:113541.9-113541.17" case 1'1 case end @@ -175983,14 +177319,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end - attribute \src "libresoc.v:113014.3-113026.6" - process $proc$libresoc.v:113014$4315 + attribute \src "libresoc.v:113553.3-113565.6" + process $proc$libresoc.v:113553$4369 assign { } { } assign { } { } assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:113015.5-113015.29" + attribute \src "libresoc.v:113554.5-113554.29" switch \initial - attribute \src "libresoc.v:113015.9-113015.17" + attribute \src "libresoc.v:113554.9-113554.17" case 1'1 case end @@ -176010,14 +177346,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "libresoc.v:113027.3-113039.6" - process $proc$libresoc.v:113027$4316 + attribute \src "libresoc.v:113566.3-113578.6" + process $proc$libresoc.v:113566$4370 assign { } { } assign { } { } assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:113028.5-113028.29" + attribute \src "libresoc.v:113567.5-113567.29" switch \initial - attribute \src "libresoc.v:113028.9-113028.17" + attribute \src "libresoc.v:113567.9-113567.17" case 1'1 case end @@ -176037,14 +177373,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end - attribute \src "libresoc.v:113040.3-113052.6" - process $proc$libresoc.v:113040$4317 + attribute \src "libresoc.v:113579.3-113591.6" + process $proc$libresoc.v:113579$4371 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:113041.5-113041.29" + attribute \src "libresoc.v:113580.5-113580.29" switch \initial - attribute \src "libresoc.v:113041.9-113041.17" + attribute \src "libresoc.v:113580.9-113580.17" case 1'1 case end @@ -176064,14 +177400,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end - attribute \src "libresoc.v:113053.3-113065.6" - process $proc$libresoc.v:113053$4318 + attribute \src "libresoc.v:113592.3-113604.6" + process $proc$libresoc.v:113592$4372 assign { } { } assign { } { } assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:113054.5-113054.29" + attribute \src "libresoc.v:113593.5-113593.29" switch \initial - attribute \src "libresoc.v:113054.9-113054.17" + attribute \src "libresoc.v:113593.9-113593.17" case 1'1 case end @@ -176091,14 +177427,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end - attribute \src "libresoc.v:113066.3-113078.6" - process $proc$libresoc.v:113066$4319 + attribute \src "libresoc.v:113605.3-113617.6" + process $proc$libresoc.v:113605$4373 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:113067.5-113067.29" + attribute \src "libresoc.v:113606.5-113606.29" switch \initial - attribute \src "libresoc.v:113067.9-113067.17" + attribute \src "libresoc.v:113606.9-113606.17" case 1'1 case end @@ -176118,14 +177454,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end - attribute \src "libresoc.v:113079.3-113091.6" - process $proc$libresoc.v:113079$4320 + attribute \src "libresoc.v:113618.3-113630.6" + process $proc$libresoc.v:113618$4374 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:113080.5-113080.29" + attribute \src "libresoc.v:113619.5-113619.29" switch \initial - attribute \src "libresoc.v:113080.9-113080.17" + attribute \src "libresoc.v:113619.9-113619.17" case 1'1 case end @@ -176145,14 +177481,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] end - attribute \src "libresoc.v:113092.3-113104.6" - process $proc$libresoc.v:113092$4321 + attribute \src "libresoc.v:113631.3-113643.6" + process $proc$libresoc.v:113631$4375 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:113093.5-113093.29" + attribute \src "libresoc.v:113632.5-113632.29" switch \initial - attribute \src "libresoc.v:113093.9-113093.17" + attribute \src "libresoc.v:113632.9-113632.17" case 1'1 case end @@ -176172,14 +177508,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] end - attribute \src "libresoc.v:113105.3-113117.6" - process $proc$libresoc.v:113105$4322 + attribute \src "libresoc.v:113644.3-113656.6" + process $proc$libresoc.v:113644$4376 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:113106.5-113106.29" + attribute \src "libresoc.v:113645.5-113645.29" switch \initial - attribute \src "libresoc.v:113106.9-113106.17" + attribute \src "libresoc.v:113645.9-113645.17" case 1'1 case end @@ -176199,14 +177535,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end - attribute \src "libresoc.v:113118.3-113130.6" - process $proc$libresoc.v:113118$4323 + attribute \src "libresoc.v:113657.3-113669.6" + process $proc$libresoc.v:113657$4377 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:113119.5-113119.29" + attribute \src "libresoc.v:113658.5-113658.29" switch \initial - attribute \src "libresoc.v:113119.9-113119.17" + attribute \src "libresoc.v:113658.9-113658.17" case 1'1 case end @@ -176226,14 +177562,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "libresoc.v:113131.3-113143.6" - process $proc$libresoc.v:113131$4324 + attribute \src "libresoc.v:113670.3-113682.6" + process $proc$libresoc.v:113670$4378 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:113132.5-113132.29" + attribute \src "libresoc.v:113671.5-113671.29" switch \initial - attribute \src "libresoc.v:113132.9-113132.17" + attribute \src "libresoc.v:113671.9-113671.17" case 1'1 case end @@ -176253,14 +177589,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end - attribute \src "libresoc.v:113144.3-113156.6" - process $proc$libresoc.v:113144$4325 + attribute \src "libresoc.v:113683.3-113695.6" + process $proc$libresoc.v:113683$4379 assign { } { } assign { } { } assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:113145.5-113145.29" + attribute \src "libresoc.v:113684.5-113684.29" switch \initial - attribute \src "libresoc.v:113145.9-113145.17" + attribute \src "libresoc.v:113684.9-113684.17" case 1'1 case end @@ -176282,140 +177618,140 @@ module \dec31_dec_sub4 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:113162.1-114874.10" +attribute \src "libresoc.v:113701.1-115414.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" attribute \generator "nMigen" module \dec31_dec_sub8 - attribute \src "libresoc.v:114615.3-114657.6" + attribute \src "libresoc.v:115155.3-115197.6" wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:114658.3-114700.6" + attribute \src "libresoc.v:115198.3-115240.6" wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:114099.3-114141.6" + attribute \src "libresoc.v:114639.3-114681.6" wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:114271.3-114313.6" + attribute \src "libresoc.v:114811.3-114853.6" wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:113540.3-113582.6" + attribute \src "libresoc.v:114080.3-114122.6" wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:113583.3-113625.6" + attribute \src "libresoc.v:114123.3-114165.6" wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:114056.3-114098.6" + attribute \src "libresoc.v:114596.3-114638.6" wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:114228.3-114270.6" + attribute \src "libresoc.v:114768.3-114810.6" wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:114443.3-114485.6" + attribute \src "libresoc.v:114983.3-115025.6" wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:113497.3-113539.6" + attribute \src "libresoc.v:114037.3-114079.6" wire width 13 $0\dec31_dec_sub8_function_unit[12:0] - attribute \src "libresoc.v:114701.3-114743.6" + attribute \src "libresoc.v:115241.3-115283.6" wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:114744.3-114786.6" + attribute \src "libresoc.v:115284.3-115326.6" wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:114787.3-114829.6" + attribute \src "libresoc.v:115327.3-115369.6" wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:113970.3-114012.6" + attribute \src "libresoc.v:114510.3-114552.6" wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:114142.3-114184.6" + attribute \src "libresoc.v:114682.3-114724.6" wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:114185.3-114227.6" + attribute \src "libresoc.v:114725.3-114767.6" wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:114400.3-114442.6" + attribute \src "libresoc.v:114940.3-114982.6" wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:113884.3-113926.6" + attribute \src "libresoc.v:114424.3-114466.6" wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:114529.3-114571.6" + attribute \src "libresoc.v:115069.3-115111.6" wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:114830.3-114872.6" + attribute \src "libresoc.v:115370.3-115412.6" wire width 2 $0\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:114013.3-114055.6" + attribute \src "libresoc.v:114553.3-114595.6" wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:114357.3-114399.6" + attribute \src "libresoc.v:114897.3-114939.6" wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:114572.3-114614.6" + attribute \src "libresoc.v:115112.3-115154.6" wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:114486.3-114528.6" + attribute \src "libresoc.v:115026.3-115068.6" wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:114314.3-114356.6" + attribute \src "libresoc.v:114854.3-114896.6" wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:113798.3-113840.6" + attribute \src "libresoc.v:114338.3-114380.6" wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:113841.3-113883.6" + attribute \src "libresoc.v:114381.3-114423.6" wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:113626.3-113668.6" + attribute \src "libresoc.v:114166.3-114208.6" wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:113669.3-113711.6" + attribute \src "libresoc.v:114209.3-114251.6" wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:113712.3-113754.6" + attribute \src "libresoc.v:114252.3-114294.6" wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:113755.3-113797.6" + attribute \src "libresoc.v:114295.3-114337.6" wire width 3 $0\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:113927.3-113969.6" + attribute \src "libresoc.v:114467.3-114509.6" wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:113163.7-113163.20" + attribute \src "libresoc.v:113702.7-113702.20" wire $0\initial[0:0] - attribute \src "libresoc.v:114615.3-114657.6" + attribute \src "libresoc.v:115155.3-115197.6" wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:114658.3-114700.6" + attribute \src "libresoc.v:115198.3-115240.6" wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:114099.3-114141.6" + attribute \src "libresoc.v:114639.3-114681.6" wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:114271.3-114313.6" + attribute \src "libresoc.v:114811.3-114853.6" wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:113540.3-113582.6" + attribute \src "libresoc.v:114080.3-114122.6" wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:113583.3-113625.6" + attribute \src "libresoc.v:114123.3-114165.6" wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:114056.3-114098.6" + attribute \src "libresoc.v:114596.3-114638.6" wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:114228.3-114270.6" + attribute \src "libresoc.v:114768.3-114810.6" wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:114443.3-114485.6" + attribute \src "libresoc.v:114983.3-115025.6" wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:113497.3-113539.6" + attribute \src "libresoc.v:114037.3-114079.6" wire width 13 $1\dec31_dec_sub8_function_unit[12:0] - attribute \src "libresoc.v:114701.3-114743.6" + attribute \src "libresoc.v:115241.3-115283.6" wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:114744.3-114786.6" + attribute \src "libresoc.v:115284.3-115326.6" wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:114787.3-114829.6" + attribute \src "libresoc.v:115327.3-115369.6" wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:113970.3-114012.6" + attribute \src "libresoc.v:114510.3-114552.6" wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:114142.3-114184.6" + attribute \src "libresoc.v:114682.3-114724.6" wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:114185.3-114227.6" + attribute \src "libresoc.v:114725.3-114767.6" wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:114400.3-114442.6" + attribute \src "libresoc.v:114940.3-114982.6" wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:113884.3-113926.6" + attribute \src "libresoc.v:114424.3-114466.6" wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:114529.3-114571.6" + attribute \src "libresoc.v:115069.3-115111.6" wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:114830.3-114872.6" + attribute \src "libresoc.v:115370.3-115412.6" wire width 2 $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:114013.3-114055.6" + attribute \src "libresoc.v:114553.3-114595.6" wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:114357.3-114399.6" + attribute \src "libresoc.v:114897.3-114939.6" wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:114572.3-114614.6" + attribute \src "libresoc.v:115112.3-115154.6" wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:114486.3-114528.6" + attribute \src "libresoc.v:115026.3-115068.6" wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:114314.3-114356.6" + attribute \src "libresoc.v:114854.3-114896.6" wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:113798.3-113840.6" + attribute \src "libresoc.v:114338.3-114380.6" wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:113841.3-113883.6" + attribute \src "libresoc.v:114381.3-114423.6" wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:113626.3-113668.6" + attribute \src "libresoc.v:114166.3-114208.6" wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:113669.3-113711.6" + attribute \src "libresoc.v:114209.3-114251.6" wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:113712.3-113754.6" + attribute \src "libresoc.v:114252.3-114294.6" wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:113755.3-113797.6" + attribute \src "libresoc.v:114295.3-114337.6" wire width 3 $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:113927.3-113969.6" + attribute \src "libresoc.v:114467.3-114509.6" wire width 2 $1\dec31_dec_sub8_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -176491,6 +177827,7 @@ module \dec31_dec_sub8 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub8_form attribute \enum_base_type "Function" @@ -176714,28 +178051,28 @@ module \dec31_dec_sub8 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub8_upd - attribute \src "libresoc.v:113163.7-113163.15" + attribute \src "libresoc.v:113702.7-113702.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:113163.7-113163.20" - process $proc$libresoc.v:113163$4359 + attribute \src "libresoc.v:113702.7-113702.20" + process $proc$libresoc.v:113702$4413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:113497.3-113539.6" - process $proc$libresoc.v:113497$4327 + attribute \src "libresoc.v:114037.3-114079.6" + process $proc$libresoc.v:114037$4381 assign { } { } assign { } { } assign $0\dec31_dec_sub8_function_unit[12:0] $1\dec31_dec_sub8_function_unit[12:0] - attribute \src "libresoc.v:113498.5-113498.29" + attribute \src "libresoc.v:114038.5-114038.29" switch \initial - attribute \src "libresoc.v:113498.9-113498.17" + attribute \src "libresoc.v:114038.9-114038.17" case 1'1 case end @@ -176795,14 +178132,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[12:0] end - attribute \src "libresoc.v:113540.3-113582.6" - process $proc$libresoc.v:113540$4328 + attribute \src "libresoc.v:114080.3-114122.6" + process $proc$libresoc.v:114080$4382 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:113541.5-113541.29" + attribute \src "libresoc.v:114081.5-114081.29" switch \initial - attribute \src "libresoc.v:113541.9-113541.17" + attribute \src "libresoc.v:114081.9-114081.17" case 1'1 case end @@ -176862,14 +178199,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:113583.3-113625.6" - process $proc$libresoc.v:113583$4329 + attribute \src "libresoc.v:114123.3-114165.6" + process $proc$libresoc.v:114123$4383 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:113584.5-113584.29" + attribute \src "libresoc.v:114124.5-114124.29" switch \initial - attribute \src "libresoc.v:113584.9-113584.17" + attribute \src "libresoc.v:114124.9-114124.17" case 1'1 case end @@ -176929,14 +178266,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:113626.3-113668.6" - process $proc$libresoc.v:113626$4330 + attribute \src "libresoc.v:114166.3-114208.6" + process $proc$libresoc.v:114166$4384 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:113627.5-113627.29" + attribute \src "libresoc.v:114167.5-114167.29" switch \initial - attribute \src "libresoc.v:113627.9-113627.17" + attribute \src "libresoc.v:114167.9-114167.17" case 1'1 case end @@ -176996,14 +178333,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] end - attribute \src "libresoc.v:113669.3-113711.6" - process $proc$libresoc.v:113669$4331 + attribute \src "libresoc.v:114209.3-114251.6" + process $proc$libresoc.v:114209$4385 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:113670.5-113670.29" + attribute \src "libresoc.v:114210.5-114210.29" switch \initial - attribute \src "libresoc.v:113670.9-113670.17" + attribute \src "libresoc.v:114210.9-114210.17" case 1'1 case end @@ -177063,14 +178400,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] end - attribute \src "libresoc.v:113712.3-113754.6" - process $proc$libresoc.v:113712$4332 + attribute \src "libresoc.v:114252.3-114294.6" + process $proc$libresoc.v:114252$4386 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:113713.5-113713.29" + attribute \src "libresoc.v:114253.5-114253.29" switch \initial - attribute \src "libresoc.v:113713.9-113713.17" + attribute \src "libresoc.v:114253.9-114253.17" case 1'1 case end @@ -177130,14 +178467,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] end - attribute \src "libresoc.v:113755.3-113797.6" - process $proc$libresoc.v:113755$4333 + attribute \src "libresoc.v:114295.3-114337.6" + process $proc$libresoc.v:114295$4387 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:113756.5-113756.29" + attribute \src "libresoc.v:114296.5-114296.29" switch \initial - attribute \src "libresoc.v:113756.9-113756.17" + attribute \src "libresoc.v:114296.9-114296.17" case 1'1 case end @@ -177197,14 +178534,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] end - attribute \src "libresoc.v:113798.3-113840.6" - process $proc$libresoc.v:113798$4334 + attribute \src "libresoc.v:114338.3-114380.6" + process $proc$libresoc.v:114338$4388 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:113799.5-113799.29" + attribute \src "libresoc.v:114339.5-114339.29" switch \initial - attribute \src "libresoc.v:113799.9-113799.17" + attribute \src "libresoc.v:114339.9-114339.17" case 1'1 case end @@ -177264,14 +178601,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] end - attribute \src "libresoc.v:113841.3-113883.6" - process $proc$libresoc.v:113841$4335 + attribute \src "libresoc.v:114381.3-114423.6" + process $proc$libresoc.v:114381$4389 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:113842.5-113842.29" + attribute \src "libresoc.v:114382.5-114382.29" switch \initial - attribute \src "libresoc.v:113842.9-113842.17" + attribute \src "libresoc.v:114382.9-114382.17" case 1'1 case end @@ -177331,14 +178668,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] end - attribute \src "libresoc.v:113884.3-113926.6" - process $proc$libresoc.v:113884$4336 + attribute \src "libresoc.v:114424.3-114466.6" + process $proc$libresoc.v:114424$4390 assign { } { } assign { } { } assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:113885.5-113885.29" + attribute \src "libresoc.v:114425.5-114425.29" switch \initial - attribute \src "libresoc.v:113885.9-113885.17" + attribute \src "libresoc.v:114425.9-114425.17" case 1'1 case end @@ -177398,14 +178735,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:113927.3-113969.6" - process $proc$libresoc.v:113927$4337 + attribute \src "libresoc.v:114467.3-114509.6" + process $proc$libresoc.v:114467$4391 assign { } { } assign { } { } assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:113928.5-113928.29" + attribute \src "libresoc.v:114468.5-114468.29" switch \initial - attribute \src "libresoc.v:113928.9-113928.17" + attribute \src "libresoc.v:114468.9-114468.17" case 1'1 case end @@ -177465,14 +178802,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "libresoc.v:113970.3-114012.6" - process $proc$libresoc.v:113970$4338 + attribute \src "libresoc.v:114510.3-114552.6" + process $proc$libresoc.v:114510$4392 assign { } { } assign { } { } assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:113971.5-113971.29" + attribute \src "libresoc.v:114511.5-114511.29" switch \initial - attribute \src "libresoc.v:113971.9-113971.17" + attribute \src "libresoc.v:114511.9-114511.17" case 1'1 case end @@ -177532,14 +178869,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:114013.3-114055.6" - process $proc$libresoc.v:114013$4339 + attribute \src "libresoc.v:114553.3-114595.6" + process $proc$libresoc.v:114553$4393 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:114014.5-114014.29" + attribute \src "libresoc.v:114554.5-114554.29" switch \initial - attribute \src "libresoc.v:114014.9-114014.17" + attribute \src "libresoc.v:114554.9-114554.17" case 1'1 case end @@ -177599,14 +178936,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:114056.3-114098.6" - process $proc$libresoc.v:114056$4340 + attribute \src "libresoc.v:114596.3-114638.6" + process $proc$libresoc.v:114596$4394 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:114057.5-114057.29" + attribute \src "libresoc.v:114597.5-114597.29" switch \initial - attribute \src "libresoc.v:114057.9-114057.17" + attribute \src "libresoc.v:114597.9-114597.17" case 1'1 case end @@ -177666,14 +179003,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "libresoc.v:114099.3-114141.6" - process $proc$libresoc.v:114099$4341 + attribute \src "libresoc.v:114639.3-114681.6" + process $proc$libresoc.v:114639$4395 assign { } { } assign { } { } assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:114100.5-114100.29" + attribute \src "libresoc.v:114640.5-114640.29" switch \initial - attribute \src "libresoc.v:114100.9-114100.17" + attribute \src "libresoc.v:114640.9-114640.17" case 1'1 case end @@ -177733,14 +179070,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "libresoc.v:114142.3-114184.6" - process $proc$libresoc.v:114142$4342 + attribute \src "libresoc.v:114682.3-114724.6" + process $proc$libresoc.v:114682$4396 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:114143.5-114143.29" + attribute \src "libresoc.v:114683.5-114683.29" switch \initial - attribute \src "libresoc.v:114143.9-114143.17" + attribute \src "libresoc.v:114683.9-114683.17" case 1'1 case end @@ -177800,14 +179137,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:114185.3-114227.6" - process $proc$libresoc.v:114185$4343 + attribute \src "libresoc.v:114725.3-114767.6" + process $proc$libresoc.v:114725$4397 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:114186.5-114186.29" + attribute \src "libresoc.v:114726.5-114726.29" switch \initial - attribute \src "libresoc.v:114186.9-114186.17" + attribute \src "libresoc.v:114726.9-114726.17" case 1'1 case end @@ -177867,14 +179204,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:114228.3-114270.6" - process $proc$libresoc.v:114228$4344 + attribute \src "libresoc.v:114768.3-114810.6" + process $proc$libresoc.v:114768$4398 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:114229.5-114229.29" + attribute \src "libresoc.v:114769.5-114769.29" switch \initial - attribute \src "libresoc.v:114229.9-114229.17" + attribute \src "libresoc.v:114769.9-114769.17" case 1'1 case end @@ -177934,14 +179271,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:114271.3-114313.6" - process $proc$libresoc.v:114271$4345 + attribute \src "libresoc.v:114811.3-114853.6" + process $proc$libresoc.v:114811$4399 assign { } { } assign { } { } assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:114272.5-114272.29" + attribute \src "libresoc.v:114812.5-114812.29" switch \initial - attribute \src "libresoc.v:114272.9-114272.17" + attribute \src "libresoc.v:114812.9-114812.17" case 1'1 case end @@ -178001,14 +179338,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "libresoc.v:114314.3-114356.6" - process $proc$libresoc.v:114314$4346 + attribute \src "libresoc.v:114854.3-114896.6" + process $proc$libresoc.v:114854$4400 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:114315.5-114315.29" + attribute \src "libresoc.v:114855.5-114855.29" switch \initial - attribute \src "libresoc.v:114315.9-114315.17" + attribute \src "libresoc.v:114855.9-114855.17" case 1'1 case end @@ -178068,14 +179405,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end - attribute \src "libresoc.v:114357.3-114399.6" - process $proc$libresoc.v:114357$4347 + attribute \src "libresoc.v:114897.3-114939.6" + process $proc$libresoc.v:114897$4401 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:114358.5-114358.29" + attribute \src "libresoc.v:114898.5-114898.29" switch \initial - attribute \src "libresoc.v:114358.9-114358.17" + attribute \src "libresoc.v:114898.9-114898.17" case 1'1 case end @@ -178135,14 +179472,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "libresoc.v:114400.3-114442.6" - process $proc$libresoc.v:114400$4348 + attribute \src "libresoc.v:114940.3-114982.6" + process $proc$libresoc.v:114940$4402 assign { } { } assign { } { } assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:114401.5-114401.29" + attribute \src "libresoc.v:114941.5-114941.29" switch \initial - attribute \src "libresoc.v:114401.9-114401.17" + attribute \src "libresoc.v:114941.9-114941.17" case 1'1 case end @@ -178202,14 +179539,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:114443.3-114485.6" - process $proc$libresoc.v:114443$4349 + attribute \src "libresoc.v:114983.3-115025.6" + process $proc$libresoc.v:114983$4403 assign { } { } assign { } { } assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:114444.5-114444.29" + attribute \src "libresoc.v:114984.5-114984.29" switch \initial - attribute \src "libresoc.v:114444.9-114444.17" + attribute \src "libresoc.v:114984.9-114984.17" case 1'1 case end @@ -178269,14 +179606,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "libresoc.v:114486.3-114528.6" - process $proc$libresoc.v:114486$4350 + attribute \src "libresoc.v:115026.3-115068.6" + process $proc$libresoc.v:115026$4404 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:114487.5-114487.29" + attribute \src "libresoc.v:115027.5-115027.29" switch \initial - attribute \src "libresoc.v:114487.9-114487.17" + attribute \src "libresoc.v:115027.9-115027.17" case 1'1 case end @@ -178336,14 +179673,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:114529.3-114571.6" - process $proc$libresoc.v:114529$4351 + attribute \src "libresoc.v:115069.3-115111.6" + process $proc$libresoc.v:115069$4405 assign { } { } assign { } { } assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:114530.5-114530.29" + attribute \src "libresoc.v:115070.5-115070.29" switch \initial - attribute \src "libresoc.v:114530.9-114530.17" + attribute \src "libresoc.v:115070.9-115070.17" case 1'1 case end @@ -178403,14 +179740,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end - attribute \src "libresoc.v:114572.3-114614.6" - process $proc$libresoc.v:114572$4352 + attribute \src "libresoc.v:115112.3-115154.6" + process $proc$libresoc.v:115112$4406 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:114573.5-114573.29" + attribute \src "libresoc.v:115113.5-115113.29" switch \initial - attribute \src "libresoc.v:114573.9-114573.17" + attribute \src "libresoc.v:115113.9-115113.17" case 1'1 case end @@ -178470,14 +179807,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "libresoc.v:114615.3-114657.6" - process $proc$libresoc.v:114615$4353 + attribute \src "libresoc.v:115155.3-115197.6" + process $proc$libresoc.v:115155$4407 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:114616.5-114616.29" + attribute \src "libresoc.v:115156.5-115156.29" switch \initial - attribute \src "libresoc.v:114616.9-114616.17" + attribute \src "libresoc.v:115156.9-115156.17" case 1'1 case end @@ -178537,14 +179874,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] end - attribute \src "libresoc.v:114658.3-114700.6" - process $proc$libresoc.v:114658$4354 + attribute \src "libresoc.v:115198.3-115240.6" + process $proc$libresoc.v:115198$4408 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:114659.5-114659.29" + attribute \src "libresoc.v:115199.5-115199.29" switch \initial - attribute \src "libresoc.v:114659.9-114659.17" + attribute \src "libresoc.v:115199.9-115199.17" case 1'1 case end @@ -178604,14 +179941,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] end - attribute \src "libresoc.v:114701.3-114743.6" - process $proc$libresoc.v:114701$4355 + attribute \src "libresoc.v:115241.3-115283.6" + process $proc$libresoc.v:115241$4409 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:114702.5-114702.29" + attribute \src "libresoc.v:115242.5-115242.29" switch \initial - attribute \src "libresoc.v:114702.9-114702.17" + attribute \src "libresoc.v:115242.9-115242.17" case 1'1 case end @@ -178671,14 +180008,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:114744.3-114786.6" - process $proc$libresoc.v:114744$4356 + attribute \src "libresoc.v:115284.3-115326.6" + process $proc$libresoc.v:115284$4410 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:114745.5-114745.29" + attribute \src "libresoc.v:115285.5-115285.29" switch \initial - attribute \src "libresoc.v:114745.9-114745.17" + attribute \src "libresoc.v:115285.9-115285.17" case 1'1 case end @@ -178738,14 +180075,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:114787.3-114829.6" - process $proc$libresoc.v:114787$4357 + attribute \src "libresoc.v:115327.3-115369.6" + process $proc$libresoc.v:115327$4411 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:114788.5-114788.29" + attribute \src "libresoc.v:115328.5-115328.29" switch \initial - attribute \src "libresoc.v:114788.9-114788.17" + attribute \src "libresoc.v:115328.9-115328.17" case 1'1 case end @@ -178805,14 +180142,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "libresoc.v:114830.3-114872.6" - process $proc$libresoc.v:114830$4358 + attribute \src "libresoc.v:115370.3-115412.6" + process $proc$libresoc.v:115370$4412 assign { } { } assign { } { } assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:114831.5-114831.29" + attribute \src "libresoc.v:115371.5-115371.29" switch \initial - attribute \src "libresoc.v:114831.9-114831.17" + attribute \src "libresoc.v:115371.9-115371.17" case 1'1 case end @@ -178874,140 +180211,140 @@ module \dec31_dec_sub8 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:114878.1-116974.10" +attribute \src "libresoc.v:115418.1-117515.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" module \dec31_dec_sub9 - attribute \src "libresoc.v:116643.3-116697.6" + attribute \src "libresoc.v:117184.3-117238.6" wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:116698.3-116752.6" + attribute \src "libresoc.v:117239.3-117293.6" wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:115983.3-116037.6" + attribute \src "libresoc.v:116524.3-116578.6" wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:116203.3-116257.6" + attribute \src "libresoc.v:116744.3-116798.6" wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:115268.3-115322.6" + attribute \src "libresoc.v:115809.3-115863.6" wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:115323.3-115377.6" + attribute \src "libresoc.v:115864.3-115918.6" wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:115928.3-115982.6" + attribute \src "libresoc.v:116469.3-116523.6" wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:116148.3-116202.6" + attribute \src "libresoc.v:116689.3-116743.6" wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:116423.3-116477.6" + attribute \src "libresoc.v:116964.3-117018.6" wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:115213.3-115267.6" + attribute \src "libresoc.v:115754.3-115808.6" wire width 13 $0\dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:116753.3-116807.6" + attribute \src "libresoc.v:117294.3-117348.6" wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:116808.3-116862.6" + attribute \src "libresoc.v:117349.3-117403.6" wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:116863.3-116917.6" + attribute \src "libresoc.v:117404.3-117458.6" wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:115818.3-115872.6" + attribute \src "libresoc.v:116359.3-116413.6" wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:116038.3-116092.6" + attribute \src "libresoc.v:116579.3-116633.6" wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:116093.3-116147.6" + attribute \src "libresoc.v:116634.3-116688.6" wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:116368.3-116422.6" + attribute \src "libresoc.v:116909.3-116963.6" wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:115708.3-115762.6" + attribute \src "libresoc.v:116249.3-116303.6" wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:116533.3-116587.6" + attribute \src "libresoc.v:117074.3-117128.6" wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:116918.3-116972.6" + attribute \src "libresoc.v:117459.3-117513.6" wire width 2 $0\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:115873.3-115927.6" + attribute \src "libresoc.v:116414.3-116468.6" wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:116313.3-116367.6" + attribute \src "libresoc.v:116854.3-116908.6" wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:116588.3-116642.6" + attribute \src "libresoc.v:117129.3-117183.6" wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:116478.3-116532.6" + attribute \src "libresoc.v:117019.3-117073.6" wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:116258.3-116312.6" + attribute \src "libresoc.v:116799.3-116853.6" wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:115598.3-115652.6" + attribute \src "libresoc.v:116139.3-116193.6" wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:115653.3-115707.6" + attribute \src "libresoc.v:116194.3-116248.6" wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:115378.3-115432.6" + attribute \src "libresoc.v:115919.3-115973.6" wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:115433.3-115487.6" + attribute \src "libresoc.v:115974.3-116028.6" wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:115488.3-115542.6" + attribute \src "libresoc.v:116029.3-116083.6" wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:115543.3-115597.6" + attribute \src "libresoc.v:116084.3-116138.6" wire width 3 $0\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:115763.3-115817.6" + attribute \src "libresoc.v:116304.3-116358.6" wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:114879.7-114879.20" + attribute \src "libresoc.v:115419.7-115419.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116643.3-116697.6" + attribute \src "libresoc.v:117184.3-117238.6" wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:116698.3-116752.6" + attribute \src "libresoc.v:117239.3-117293.6" wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:115983.3-116037.6" + attribute \src "libresoc.v:116524.3-116578.6" wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:116203.3-116257.6" + attribute \src "libresoc.v:116744.3-116798.6" wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:115268.3-115322.6" + attribute \src "libresoc.v:115809.3-115863.6" wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:115323.3-115377.6" + attribute \src "libresoc.v:115864.3-115918.6" wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:115928.3-115982.6" + attribute \src "libresoc.v:116469.3-116523.6" wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:116148.3-116202.6" + attribute \src "libresoc.v:116689.3-116743.6" wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:116423.3-116477.6" + attribute \src "libresoc.v:116964.3-117018.6" wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:115213.3-115267.6" + attribute \src "libresoc.v:115754.3-115808.6" wire width 13 $1\dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:116753.3-116807.6" + attribute \src "libresoc.v:117294.3-117348.6" wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:116808.3-116862.6" + attribute \src "libresoc.v:117349.3-117403.6" wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:116863.3-116917.6" + attribute \src "libresoc.v:117404.3-117458.6" wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:115818.3-115872.6" + attribute \src "libresoc.v:116359.3-116413.6" wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:116038.3-116092.6" + attribute \src "libresoc.v:116579.3-116633.6" wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:116093.3-116147.6" + attribute \src "libresoc.v:116634.3-116688.6" wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:116368.3-116422.6" + attribute \src "libresoc.v:116909.3-116963.6" wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:115708.3-115762.6" + attribute \src "libresoc.v:116249.3-116303.6" wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:116533.3-116587.6" + attribute \src "libresoc.v:117074.3-117128.6" wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:116918.3-116972.6" + attribute \src "libresoc.v:117459.3-117513.6" wire width 2 $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:115873.3-115927.6" + attribute \src "libresoc.v:116414.3-116468.6" wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:116313.3-116367.6" + attribute \src "libresoc.v:116854.3-116908.6" wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:116588.3-116642.6" + attribute \src "libresoc.v:117129.3-117183.6" wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:116478.3-116532.6" + attribute \src "libresoc.v:117019.3-117073.6" wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:116258.3-116312.6" + attribute \src "libresoc.v:116799.3-116853.6" wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:115598.3-115652.6" + attribute \src "libresoc.v:116139.3-116193.6" wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:115653.3-115707.6" + attribute \src "libresoc.v:116194.3-116248.6" wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:115378.3-115432.6" + attribute \src "libresoc.v:115919.3-115973.6" wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:115433.3-115487.6" + attribute \src "libresoc.v:115974.3-116028.6" wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:115488.3-115542.6" + attribute \src "libresoc.v:116029.3-116083.6" wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:115543.3-115597.6" + attribute \src "libresoc.v:116084.3-116138.6" wire width 3 $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:115763.3-115817.6" + attribute \src "libresoc.v:116304.3-116358.6" wire width 2 $1\dec31_dec_sub9_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -179083,6 +180420,7 @@ module \dec31_dec_sub9 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec31_dec_sub9_form attribute \enum_base_type "Function" @@ -179306,28 +180644,28 @@ module \dec31_dec_sub9 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec31_dec_sub9_upd - attribute \src "libresoc.v:114879.7-114879.15" + attribute \src "libresoc.v:115419.7-115419.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 5 \opcode_switch - attribute \src "libresoc.v:114879.7-114879.20" - process $proc$libresoc.v:114879$4392 + attribute \src "libresoc.v:115419.7-115419.20" + process $proc$libresoc.v:115419$4446 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115213.3-115267.6" - process $proc$libresoc.v:115213$4360 + attribute \src "libresoc.v:115754.3-115808.6" + process $proc$libresoc.v:115754$4414 assign { } { } assign { } { } assign $0\dec31_dec_sub9_function_unit[12:0] $1\dec31_dec_sub9_function_unit[12:0] - attribute \src "libresoc.v:115214.5-115214.29" + attribute \src "libresoc.v:115755.5-115755.29" switch \initial - attribute \src "libresoc.v:115214.9-115214.17" + attribute \src "libresoc.v:115755.9-115755.17" case 1'1 case end @@ -179403,14 +180741,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[12:0] end - attribute \src "libresoc.v:115268.3-115322.6" - process $proc$libresoc.v:115268$4361 + attribute \src "libresoc.v:115809.3-115863.6" + process $proc$libresoc.v:115809$4415 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:115269.5-115269.29" + attribute \src "libresoc.v:115810.5-115810.29" switch \initial - attribute \src "libresoc.v:115269.9-115269.17" + attribute \src "libresoc.v:115810.9-115810.17" case 1'1 case end @@ -179486,14 +180824,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:115323.3-115377.6" - process $proc$libresoc.v:115323$4362 + attribute \src "libresoc.v:115864.3-115918.6" + process $proc$libresoc.v:115864$4416 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:115324.5-115324.29" + attribute \src "libresoc.v:115865.5-115865.29" switch \initial - attribute \src "libresoc.v:115324.9-115324.17" + attribute \src "libresoc.v:115865.9-115865.17" case 1'1 case end @@ -179569,14 +180907,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:115378.3-115432.6" - process $proc$libresoc.v:115378$4363 + attribute \src "libresoc.v:115919.3-115973.6" + process $proc$libresoc.v:115919$4417 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:115379.5-115379.29" + attribute \src "libresoc.v:115920.5-115920.29" switch \initial - attribute \src "libresoc.v:115379.9-115379.17" + attribute \src "libresoc.v:115920.9-115920.17" case 1'1 case end @@ -179652,14 +180990,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] end - attribute \src "libresoc.v:115433.3-115487.6" - process $proc$libresoc.v:115433$4364 + attribute \src "libresoc.v:115974.3-116028.6" + process $proc$libresoc.v:115974$4418 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:115434.5-115434.29" + attribute \src "libresoc.v:115975.5-115975.29" switch \initial - attribute \src "libresoc.v:115434.9-115434.17" + attribute \src "libresoc.v:115975.9-115975.17" case 1'1 case end @@ -179735,14 +181073,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] end - attribute \src "libresoc.v:115488.3-115542.6" - process $proc$libresoc.v:115488$4365 + attribute \src "libresoc.v:116029.3-116083.6" + process $proc$libresoc.v:116029$4419 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:115489.5-115489.29" + attribute \src "libresoc.v:116030.5-116030.29" switch \initial - attribute \src "libresoc.v:115489.9-115489.17" + attribute \src "libresoc.v:116030.9-116030.17" case 1'1 case end @@ -179818,14 +181156,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] end - attribute \src "libresoc.v:115543.3-115597.6" - process $proc$libresoc.v:115543$4366 + attribute \src "libresoc.v:116084.3-116138.6" + process $proc$libresoc.v:116084$4420 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:115544.5-115544.29" + attribute \src "libresoc.v:116085.5-116085.29" switch \initial - attribute \src "libresoc.v:115544.9-115544.17" + attribute \src "libresoc.v:116085.9-116085.17" case 1'1 case end @@ -179901,14 +181239,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] end - attribute \src "libresoc.v:115598.3-115652.6" - process $proc$libresoc.v:115598$4367 + attribute \src "libresoc.v:116139.3-116193.6" + process $proc$libresoc.v:116139$4421 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:115599.5-115599.29" + attribute \src "libresoc.v:116140.5-116140.29" switch \initial - attribute \src "libresoc.v:115599.9-115599.17" + attribute \src "libresoc.v:116140.9-116140.17" case 1'1 case end @@ -179984,14 +181322,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] end - attribute \src "libresoc.v:115653.3-115707.6" - process $proc$libresoc.v:115653$4368 + attribute \src "libresoc.v:116194.3-116248.6" + process $proc$libresoc.v:116194$4422 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:115654.5-115654.29" + attribute \src "libresoc.v:116195.5-116195.29" switch \initial - attribute \src "libresoc.v:115654.9-115654.17" + attribute \src "libresoc.v:116195.9-116195.17" case 1'1 case end @@ -180067,14 +181405,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] end - attribute \src "libresoc.v:115708.3-115762.6" - process $proc$libresoc.v:115708$4369 + attribute \src "libresoc.v:116249.3-116303.6" + process $proc$libresoc.v:116249$4423 assign { } { } assign { } { } assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:115709.5-115709.29" + attribute \src "libresoc.v:116250.5-116250.29" switch \initial - attribute \src "libresoc.v:115709.9-115709.17" + attribute \src "libresoc.v:116250.9-116250.17" case 1'1 case end @@ -180150,14 +181488,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:115763.3-115817.6" - process $proc$libresoc.v:115763$4370 + attribute \src "libresoc.v:116304.3-116358.6" + process $proc$libresoc.v:116304$4424 assign { } { } assign { } { } assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:115764.5-115764.29" + attribute \src "libresoc.v:116305.5-116305.29" switch \initial - attribute \src "libresoc.v:115764.9-115764.17" + attribute \src "libresoc.v:116305.9-116305.17" case 1'1 case end @@ -180233,14 +181571,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:115818.3-115872.6" - process $proc$libresoc.v:115818$4371 + attribute \src "libresoc.v:116359.3-116413.6" + process $proc$libresoc.v:116359$4425 assign { } { } assign { } { } assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:115819.5-115819.29" + attribute \src "libresoc.v:116360.5-116360.29" switch \initial - attribute \src "libresoc.v:115819.9-115819.17" + attribute \src "libresoc.v:116360.9-116360.17" case 1'1 case end @@ -180316,14 +181654,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:115873.3-115927.6" - process $proc$libresoc.v:115873$4372 + attribute \src "libresoc.v:116414.3-116468.6" + process $proc$libresoc.v:116414$4426 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:115874.5-115874.29" + attribute \src "libresoc.v:116415.5-116415.29" switch \initial - attribute \src "libresoc.v:115874.9-115874.17" + attribute \src "libresoc.v:116415.9-116415.17" case 1'1 case end @@ -180399,14 +181737,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:115928.3-115982.6" - process $proc$libresoc.v:115928$4373 + attribute \src "libresoc.v:116469.3-116523.6" + process $proc$libresoc.v:116469$4427 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:115929.5-115929.29" + attribute \src "libresoc.v:116470.5-116470.29" switch \initial - attribute \src "libresoc.v:115929.9-115929.17" + attribute \src "libresoc.v:116470.9-116470.17" case 1'1 case end @@ -180482,14 +181820,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:115983.3-116037.6" - process $proc$libresoc.v:115983$4374 + attribute \src "libresoc.v:116524.3-116578.6" + process $proc$libresoc.v:116524$4428 assign { } { } assign { } { } assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:115984.5-115984.29" + attribute \src "libresoc.v:116525.5-116525.29" switch \initial - attribute \src "libresoc.v:115984.9-115984.17" + attribute \src "libresoc.v:116525.9-116525.17" case 1'1 case end @@ -180565,14 +181903,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:116038.3-116092.6" - process $proc$libresoc.v:116038$4375 + attribute \src "libresoc.v:116579.3-116633.6" + process $proc$libresoc.v:116579$4429 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:116039.5-116039.29" + attribute \src "libresoc.v:116580.5-116580.29" switch \initial - attribute \src "libresoc.v:116039.9-116039.17" + attribute \src "libresoc.v:116580.9-116580.17" case 1'1 case end @@ -180648,14 +181986,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:116093.3-116147.6" - process $proc$libresoc.v:116093$4376 + attribute \src "libresoc.v:116634.3-116688.6" + process $proc$libresoc.v:116634$4430 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:116094.5-116094.29" + attribute \src "libresoc.v:116635.5-116635.29" switch \initial - attribute \src "libresoc.v:116094.9-116094.17" + attribute \src "libresoc.v:116635.9-116635.17" case 1'1 case end @@ -180731,14 +182069,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:116148.3-116202.6" - process $proc$libresoc.v:116148$4377 + attribute \src "libresoc.v:116689.3-116743.6" + process $proc$libresoc.v:116689$4431 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:116149.5-116149.29" + attribute \src "libresoc.v:116690.5-116690.29" switch \initial - attribute \src "libresoc.v:116149.9-116149.17" + attribute \src "libresoc.v:116690.9-116690.17" case 1'1 case end @@ -180814,14 +182152,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:116203.3-116257.6" - process $proc$libresoc.v:116203$4378 + attribute \src "libresoc.v:116744.3-116798.6" + process $proc$libresoc.v:116744$4432 assign { } { } assign { } { } assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:116204.5-116204.29" + attribute \src "libresoc.v:116745.5-116745.29" switch \initial - attribute \src "libresoc.v:116204.9-116204.17" + attribute \src "libresoc.v:116745.9-116745.17" case 1'1 case end @@ -180897,14 +182235,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "libresoc.v:116258.3-116312.6" - process $proc$libresoc.v:116258$4379 + attribute \src "libresoc.v:116799.3-116853.6" + process $proc$libresoc.v:116799$4433 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:116259.5-116259.29" + attribute \src "libresoc.v:116800.5-116800.29" switch \initial - attribute \src "libresoc.v:116259.9-116259.17" + attribute \src "libresoc.v:116800.9-116800.17" case 1'1 case end @@ -180980,14 +182318,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "libresoc.v:116313.3-116367.6" - process $proc$libresoc.v:116313$4380 + attribute \src "libresoc.v:116854.3-116908.6" + process $proc$libresoc.v:116854$4434 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:116314.5-116314.29" + attribute \src "libresoc.v:116855.5-116855.29" switch \initial - attribute \src "libresoc.v:116314.9-116314.17" + attribute \src "libresoc.v:116855.9-116855.17" case 1'1 case end @@ -181063,14 +182401,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "libresoc.v:116368.3-116422.6" - process $proc$libresoc.v:116368$4381 + attribute \src "libresoc.v:116909.3-116963.6" + process $proc$libresoc.v:116909$4435 assign { } { } assign { } { } assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:116369.5-116369.29" + attribute \src "libresoc.v:116910.5-116910.29" switch \initial - attribute \src "libresoc.v:116369.9-116369.17" + attribute \src "libresoc.v:116910.9-116910.17" case 1'1 case end @@ -181146,14 +182484,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:116423.3-116477.6" - process $proc$libresoc.v:116423$4382 + attribute \src "libresoc.v:116964.3-117018.6" + process $proc$libresoc.v:116964$4436 assign { } { } assign { } { } assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:116424.5-116424.29" + attribute \src "libresoc.v:116965.5-116965.29" switch \initial - attribute \src "libresoc.v:116424.9-116424.17" + attribute \src "libresoc.v:116965.9-116965.17" case 1'1 case end @@ -181229,14 +182567,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "libresoc.v:116478.3-116532.6" - process $proc$libresoc.v:116478$4383 + attribute \src "libresoc.v:117019.3-117073.6" + process $proc$libresoc.v:117019$4437 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:116479.5-116479.29" + attribute \src "libresoc.v:117020.5-117020.29" switch \initial - attribute \src "libresoc.v:116479.9-116479.17" + attribute \src "libresoc.v:117020.9-117020.17" case 1'1 case end @@ -181312,14 +182650,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:116533.3-116587.6" - process $proc$libresoc.v:116533$4384 + attribute \src "libresoc.v:117074.3-117128.6" + process $proc$libresoc.v:117074$4438 assign { } { } assign { } { } assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:116534.5-116534.29" + attribute \src "libresoc.v:117075.5-117075.29" switch \initial - attribute \src "libresoc.v:116534.9-116534.17" + attribute \src "libresoc.v:117075.9-117075.17" case 1'1 case end @@ -181395,14 +182733,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "libresoc.v:116588.3-116642.6" - process $proc$libresoc.v:116588$4385 + attribute \src "libresoc.v:117129.3-117183.6" + process $proc$libresoc.v:117129$4439 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:116589.5-116589.29" + attribute \src "libresoc.v:117130.5-117130.29" switch \initial - attribute \src "libresoc.v:116589.9-116589.17" + attribute \src "libresoc.v:117130.9-117130.17" case 1'1 case end @@ -181478,14 +182816,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "libresoc.v:116643.3-116697.6" - process $proc$libresoc.v:116643$4386 + attribute \src "libresoc.v:117184.3-117238.6" + process $proc$libresoc.v:117184$4440 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:116644.5-116644.29" + attribute \src "libresoc.v:117185.5-117185.29" switch \initial - attribute \src "libresoc.v:116644.9-116644.17" + attribute \src "libresoc.v:117185.9-117185.17" case 1'1 case end @@ -181561,14 +182899,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] end - attribute \src "libresoc.v:116698.3-116752.6" - process $proc$libresoc.v:116698$4387 + attribute \src "libresoc.v:117239.3-117293.6" + process $proc$libresoc.v:117239$4441 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:116699.5-116699.29" + attribute \src "libresoc.v:117240.5-117240.29" switch \initial - attribute \src "libresoc.v:116699.9-116699.17" + attribute \src "libresoc.v:117240.9-117240.17" case 1'1 case end @@ -181644,14 +182982,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] end - attribute \src "libresoc.v:116753.3-116807.6" - process $proc$libresoc.v:116753$4388 + attribute \src "libresoc.v:117294.3-117348.6" + process $proc$libresoc.v:117294$4442 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:116754.5-116754.29" + attribute \src "libresoc.v:117295.5-117295.29" switch \initial - attribute \src "libresoc.v:116754.9-116754.17" + attribute \src "libresoc.v:117295.9-117295.17" case 1'1 case end @@ -181727,14 +183065,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:116808.3-116862.6" - process $proc$libresoc.v:116808$4389 + attribute \src "libresoc.v:117349.3-117403.6" + process $proc$libresoc.v:117349$4443 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:116809.5-116809.29" + attribute \src "libresoc.v:117350.5-117350.29" switch \initial - attribute \src "libresoc.v:116809.9-116809.17" + attribute \src "libresoc.v:117350.9-117350.17" case 1'1 case end @@ -181810,14 +183148,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:116863.3-116917.6" - process $proc$libresoc.v:116863$4390 + attribute \src "libresoc.v:117404.3-117458.6" + process $proc$libresoc.v:117404$4444 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:116864.5-116864.29" + attribute \src "libresoc.v:117405.5-117405.29" switch \initial - attribute \src "libresoc.v:116864.9-116864.17" + attribute \src "libresoc.v:117405.9-117405.17" case 1'1 case end @@ -181893,14 +183231,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \src "libresoc.v:116918.3-116972.6" - process $proc$libresoc.v:116918$4391 + attribute \src "libresoc.v:117459.3-117513.6" + process $proc$libresoc.v:117459$4445 assign { } { } assign { } { } assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:116919.5-116919.29" + attribute \src "libresoc.v:117460.5-117460.29" switch \initial - attribute \src "libresoc.v:116919.9-116919.17" + attribute \src "libresoc.v:117460.9-117460.17" case 1'1 case end @@ -181978,140 +183316,140 @@ module \dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:116978.1-117826.10" +attribute \src "libresoc.v:117519.1-118368.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" module \dec58 - attribute \src "libresoc.v:117729.3-117744.6" + attribute \src "libresoc.v:118271.3-118286.6" wire width 2 $0\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:117745.3-117760.6" + attribute \src "libresoc.v:118287.3-118302.6" wire width 2 $0\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:117537.3-117552.6" + attribute \src "libresoc.v:118079.3-118094.6" wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:117601.3-117616.6" + attribute \src "libresoc.v:118143.3-118158.6" wire $0\dec58_br[0:0] - attribute \src "libresoc.v:117329.3-117344.6" + attribute \src "libresoc.v:117871.3-117886.6" wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:117345.3-117360.6" + attribute \src "libresoc.v:117887.3-117902.6" wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:117521.3-117536.6" + attribute \src "libresoc.v:118063.3-118078.6" wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:117585.3-117600.6" + attribute \src "libresoc.v:118127.3-118142.6" wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:117665.3-117680.6" + attribute \src "libresoc.v:118207.3-118222.6" wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:117313.3-117328.6" + attribute \src "libresoc.v:117855.3-117870.6" wire width 13 $0\dec58_function_unit[12:0] - attribute \src "libresoc.v:117761.3-117776.6" + attribute \src "libresoc.v:118303.3-118318.6" wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:117777.3-117792.6" + attribute \src "libresoc.v:118319.3-118334.6" wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:117793.3-117808.6" + attribute \src "libresoc.v:118335.3-118350.6" wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:117489.3-117504.6" + attribute \src "libresoc.v:118031.3-118046.6" wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:117553.3-117568.6" + attribute \src "libresoc.v:118095.3-118110.6" wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:117569.3-117584.6" + attribute \src "libresoc.v:118111.3-118126.6" wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:117649.3-117664.6" + attribute \src "libresoc.v:118191.3-118206.6" wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:117457.3-117472.6" + attribute \src "libresoc.v:117999.3-118014.6" wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:117697.3-117712.6" + attribute \src "libresoc.v:118239.3-118254.6" wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:117809.3-117824.6" + attribute \src "libresoc.v:118351.3-118366.6" wire width 2 $0\dec58_out_sel[1:0] - attribute \src "libresoc.v:117505.3-117520.6" + attribute \src "libresoc.v:118047.3-118062.6" wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:117633.3-117648.6" + attribute \src "libresoc.v:118175.3-118190.6" wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:117713.3-117728.6" + attribute \src "libresoc.v:118255.3-118270.6" wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:117681.3-117696.6" + attribute \src "libresoc.v:118223.3-118238.6" wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:117617.3-117632.6" + attribute \src "libresoc.v:118159.3-118174.6" wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:117425.3-117440.6" + attribute \src "libresoc.v:117967.3-117982.6" wire width 3 $0\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:117441.3-117456.6" + attribute \src "libresoc.v:117983.3-117998.6" wire width 3 $0\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:117361.3-117376.6" + attribute \src "libresoc.v:117903.3-117918.6" wire width 3 $0\dec58_sv_in1[2:0] - attribute \src "libresoc.v:117377.3-117392.6" + attribute \src "libresoc.v:117919.3-117934.6" wire width 3 $0\dec58_sv_in2[2:0] - attribute \src "libresoc.v:117393.3-117408.6" + attribute \src "libresoc.v:117935.3-117950.6" wire width 3 $0\dec58_sv_in3[2:0] - attribute \src "libresoc.v:117409.3-117424.6" + attribute \src "libresoc.v:117951.3-117966.6" wire width 3 $0\dec58_sv_out[2:0] - attribute \src "libresoc.v:117473.3-117488.6" + attribute \src "libresoc.v:118015.3-118030.6" wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:116979.7-116979.20" + attribute \src "libresoc.v:117520.7-117520.20" wire $0\initial[0:0] - attribute \src "libresoc.v:117729.3-117744.6" + attribute \src "libresoc.v:118271.3-118286.6" wire width 2 $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:117745.3-117760.6" + attribute \src "libresoc.v:118287.3-118302.6" wire width 2 $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:117537.3-117552.6" + attribute \src "libresoc.v:118079.3-118094.6" wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:117601.3-117616.6" + attribute \src "libresoc.v:118143.3-118158.6" wire $1\dec58_br[0:0] - attribute \src "libresoc.v:117329.3-117344.6" + attribute \src "libresoc.v:117871.3-117886.6" wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:117345.3-117360.6" + attribute \src "libresoc.v:117887.3-117902.6" wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:117521.3-117536.6" + attribute \src "libresoc.v:118063.3-118078.6" wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:117585.3-117600.6" + attribute \src "libresoc.v:118127.3-118142.6" wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:117665.3-117680.6" + attribute \src "libresoc.v:118207.3-118222.6" wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:117313.3-117328.6" + attribute \src "libresoc.v:117855.3-117870.6" wire width 13 $1\dec58_function_unit[12:0] - attribute \src "libresoc.v:117761.3-117776.6" + attribute \src "libresoc.v:118303.3-118318.6" wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:117777.3-117792.6" + attribute \src "libresoc.v:118319.3-118334.6" wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:117793.3-117808.6" + attribute \src "libresoc.v:118335.3-118350.6" wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:117489.3-117504.6" + attribute \src "libresoc.v:118031.3-118046.6" wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:117553.3-117568.6" + attribute \src "libresoc.v:118095.3-118110.6" wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:117569.3-117584.6" + attribute \src "libresoc.v:118111.3-118126.6" wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:117649.3-117664.6" + attribute \src "libresoc.v:118191.3-118206.6" wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:117457.3-117472.6" + attribute \src "libresoc.v:117999.3-118014.6" wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:117697.3-117712.6" + attribute \src "libresoc.v:118239.3-118254.6" wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:117809.3-117824.6" + attribute \src "libresoc.v:118351.3-118366.6" wire width 2 $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:117505.3-117520.6" + attribute \src "libresoc.v:118047.3-118062.6" wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:117633.3-117648.6" + attribute \src "libresoc.v:118175.3-118190.6" wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:117713.3-117728.6" + attribute \src "libresoc.v:118255.3-118270.6" wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:117681.3-117696.6" + attribute \src "libresoc.v:118223.3-118238.6" wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:117617.3-117632.6" + attribute \src "libresoc.v:118159.3-118174.6" wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:117425.3-117440.6" + attribute \src "libresoc.v:117967.3-117982.6" wire width 3 $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:117441.3-117456.6" + attribute \src "libresoc.v:117983.3-117998.6" wire width 3 $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:117361.3-117376.6" + attribute \src "libresoc.v:117903.3-117918.6" wire width 3 $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:117377.3-117392.6" + attribute \src "libresoc.v:117919.3-117934.6" wire width 3 $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:117393.3-117408.6" + attribute \src "libresoc.v:117935.3-117950.6" wire width 3 $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:117409.3-117424.6" + attribute \src "libresoc.v:117951.3-117966.6" wire width 3 $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:117473.3-117488.6" + attribute \src "libresoc.v:118015.3-118030.6" wire width 2 $1\dec58_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -182187,6 +183525,7 @@ module \dec58 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec58_form attribute \enum_base_type "Function" @@ -182410,28 +183749,28 @@ module \dec58 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec58_upd - attribute \src "libresoc.v:116979.7-116979.15" + attribute \src "libresoc.v:117520.7-117520.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 2 \opcode_switch - attribute \src "libresoc.v:116979.7-116979.20" - process $proc$libresoc.v:116979$4425 + attribute \src "libresoc.v:117520.7-117520.20" + process $proc$libresoc.v:117520$4479 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117313.3-117328.6" - process $proc$libresoc.v:117313$4393 + attribute \src "libresoc.v:117855.3-117870.6" + process $proc$libresoc.v:117855$4447 assign { } { } assign { } { } assign $0\dec58_function_unit[12:0] $1\dec58_function_unit[12:0] - attribute \src "libresoc.v:117314.5-117314.29" + attribute \src "libresoc.v:117856.5-117856.29" switch \initial - attribute \src "libresoc.v:117314.9-117314.17" + attribute \src "libresoc.v:117856.9-117856.17" case 1'1 case end @@ -182455,14 +183794,14 @@ module \dec58 sync always update \dec58_function_unit $0\dec58_function_unit[12:0] end - attribute \src "libresoc.v:117329.3-117344.6" - process $proc$libresoc.v:117329$4394 + attribute \src "libresoc.v:117871.3-117886.6" + process $proc$libresoc.v:117871$4448 assign { } { } assign { } { } assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:117330.5-117330.29" + attribute \src "libresoc.v:117872.5-117872.29" switch \initial - attribute \src "libresoc.v:117330.9-117330.17" + attribute \src "libresoc.v:117872.9-117872.17" case 1'1 case end @@ -182486,14 +183825,14 @@ module \dec58 sync always update \dec58_cr_in $0\dec58_cr_in[2:0] end - attribute \src "libresoc.v:117345.3-117360.6" - process $proc$libresoc.v:117345$4395 + attribute \src "libresoc.v:117887.3-117902.6" + process $proc$libresoc.v:117887$4449 assign { } { } assign { } { } assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:117346.5-117346.29" + attribute \src "libresoc.v:117888.5-117888.29" switch \initial - attribute \src "libresoc.v:117346.9-117346.17" + attribute \src "libresoc.v:117888.9-117888.17" case 1'1 case end @@ -182517,14 +183856,14 @@ module \dec58 sync always update \dec58_cr_out $0\dec58_cr_out[2:0] end - attribute \src "libresoc.v:117361.3-117376.6" - process $proc$libresoc.v:117361$4396 + attribute \src "libresoc.v:117903.3-117918.6" + process $proc$libresoc.v:117903$4450 assign { } { } assign { } { } assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:117362.5-117362.29" + attribute \src "libresoc.v:117904.5-117904.29" switch \initial - attribute \src "libresoc.v:117362.9-117362.17" + attribute \src "libresoc.v:117904.9-117904.17" case 1'1 case end @@ -182548,14 +183887,14 @@ module \dec58 sync always update \dec58_sv_in1 $0\dec58_sv_in1[2:0] end - attribute \src "libresoc.v:117377.3-117392.6" - process $proc$libresoc.v:117377$4397 + attribute \src "libresoc.v:117919.3-117934.6" + process $proc$libresoc.v:117919$4451 assign { } { } assign { } { } assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:117378.5-117378.29" + attribute \src "libresoc.v:117920.5-117920.29" switch \initial - attribute \src "libresoc.v:117378.9-117378.17" + attribute \src "libresoc.v:117920.9-117920.17" case 1'1 case end @@ -182579,14 +183918,14 @@ module \dec58 sync always update \dec58_sv_in2 $0\dec58_sv_in2[2:0] end - attribute \src "libresoc.v:117393.3-117408.6" - process $proc$libresoc.v:117393$4398 + attribute \src "libresoc.v:117935.3-117950.6" + process $proc$libresoc.v:117935$4452 assign { } { } assign { } { } assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:117394.5-117394.29" + attribute \src "libresoc.v:117936.5-117936.29" switch \initial - attribute \src "libresoc.v:117394.9-117394.17" + attribute \src "libresoc.v:117936.9-117936.17" case 1'1 case end @@ -182610,14 +183949,14 @@ module \dec58 sync always update \dec58_sv_in3 $0\dec58_sv_in3[2:0] end - attribute \src "libresoc.v:117409.3-117424.6" - process $proc$libresoc.v:117409$4399 + attribute \src "libresoc.v:117951.3-117966.6" + process $proc$libresoc.v:117951$4453 assign { } { } assign { } { } assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:117410.5-117410.29" + attribute \src "libresoc.v:117952.5-117952.29" switch \initial - attribute \src "libresoc.v:117410.9-117410.17" + attribute \src "libresoc.v:117952.9-117952.17" case 1'1 case end @@ -182641,14 +183980,14 @@ module \dec58 sync always update \dec58_sv_out $0\dec58_sv_out[2:0] end - attribute \src "libresoc.v:117425.3-117440.6" - process $proc$libresoc.v:117425$4400 + attribute \src "libresoc.v:117967.3-117982.6" + process $proc$libresoc.v:117967$4454 assign { } { } assign { } { } assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:117426.5-117426.29" + attribute \src "libresoc.v:117968.5-117968.29" switch \initial - attribute \src "libresoc.v:117426.9-117426.17" + attribute \src "libresoc.v:117968.9-117968.17" case 1'1 case end @@ -182672,14 +184011,14 @@ module \dec58 sync always update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] end - attribute \src "libresoc.v:117441.3-117456.6" - process $proc$libresoc.v:117441$4401 + attribute \src "libresoc.v:117983.3-117998.6" + process $proc$libresoc.v:117983$4455 assign { } { } assign { } { } assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:117442.5-117442.29" + attribute \src "libresoc.v:117984.5-117984.29" switch \initial - attribute \src "libresoc.v:117442.9-117442.17" + attribute \src "libresoc.v:117984.9-117984.17" case 1'1 case end @@ -182703,14 +184042,14 @@ module \dec58 sync always update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] end - attribute \src "libresoc.v:117457.3-117472.6" - process $proc$libresoc.v:117457$4402 + attribute \src "libresoc.v:117999.3-118014.6" + process $proc$libresoc.v:117999$4456 assign { } { } assign { } { } assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:117458.5-117458.29" + attribute \src "libresoc.v:118000.5-118000.29" switch \initial - attribute \src "libresoc.v:117458.9-117458.17" + attribute \src "libresoc.v:118000.9-118000.17" case 1'1 case end @@ -182734,14 +184073,14 @@ module \dec58 sync always update \dec58_ldst_len $0\dec58_ldst_len[3:0] end - attribute \src "libresoc.v:117473.3-117488.6" - process $proc$libresoc.v:117473$4403 + attribute \src "libresoc.v:118015.3-118030.6" + process $proc$libresoc.v:118015$4457 assign { } { } assign { } { } assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:117474.5-117474.29" + attribute \src "libresoc.v:118016.5-118016.29" switch \initial - attribute \src "libresoc.v:117474.9-117474.17" + attribute \src "libresoc.v:118016.9-118016.17" case 1'1 case end @@ -182765,14 +184104,14 @@ module \dec58 sync always update \dec58_upd $0\dec58_upd[1:0] end - attribute \src "libresoc.v:117489.3-117504.6" - process $proc$libresoc.v:117489$4404 + attribute \src "libresoc.v:118031.3-118046.6" + process $proc$libresoc.v:118031$4458 assign { } { } assign { } { } assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:117490.5-117490.29" + attribute \src "libresoc.v:118032.5-118032.29" switch \initial - attribute \src "libresoc.v:117490.9-117490.17" + attribute \src "libresoc.v:118032.9-118032.17" case 1'1 case end @@ -182796,14 +184135,14 @@ module \dec58 sync always update \dec58_internal_op $0\dec58_internal_op[6:0] end - attribute \src "libresoc.v:117505.3-117520.6" - process $proc$libresoc.v:117505$4405 + attribute \src "libresoc.v:118047.3-118062.6" + process $proc$libresoc.v:118047$4459 assign { } { } assign { } { } assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:117506.5-117506.29" + attribute \src "libresoc.v:118048.5-118048.29" switch \initial - attribute \src "libresoc.v:117506.9-117506.17" + attribute \src "libresoc.v:118048.9-118048.17" case 1'1 case end @@ -182827,14 +184166,14 @@ module \dec58 sync always update \dec58_rc_sel $0\dec58_rc_sel[1:0] end - attribute \src "libresoc.v:117521.3-117536.6" - process $proc$libresoc.v:117521$4406 + attribute \src "libresoc.v:118063.3-118078.6" + process $proc$libresoc.v:118063$4460 assign { } { } assign { } { } assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:117522.5-117522.29" + attribute \src "libresoc.v:118064.5-118064.29" switch \initial - attribute \src "libresoc.v:117522.9-117522.17" + attribute \src "libresoc.v:118064.9-118064.17" case 1'1 case end @@ -182858,14 +184197,14 @@ module \dec58 sync always update \dec58_cry_in $0\dec58_cry_in[1:0] end - attribute \src "libresoc.v:117537.3-117552.6" - process $proc$libresoc.v:117537$4407 + attribute \src "libresoc.v:118079.3-118094.6" + process $proc$libresoc.v:118079$4461 assign { } { } assign { } { } assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:117538.5-117538.29" + attribute \src "libresoc.v:118080.5-118080.29" switch \initial - attribute \src "libresoc.v:117538.9-117538.17" + attribute \src "libresoc.v:118080.9-118080.17" case 1'1 case end @@ -182889,14 +184228,14 @@ module \dec58 sync always update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "libresoc.v:117553.3-117568.6" - process $proc$libresoc.v:117553$4408 + attribute \src "libresoc.v:118095.3-118110.6" + process $proc$libresoc.v:118095$4462 assign { } { } assign { } { } assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:117554.5-117554.29" + attribute \src "libresoc.v:118096.5-118096.29" switch \initial - attribute \src "libresoc.v:117554.9-117554.17" + attribute \src "libresoc.v:118096.9-118096.17" case 1'1 case end @@ -182920,14 +184259,14 @@ module \dec58 sync always update \dec58_inv_a $0\dec58_inv_a[0:0] end - attribute \src "libresoc.v:117569.3-117584.6" - process $proc$libresoc.v:117569$4409 + attribute \src "libresoc.v:118111.3-118126.6" + process $proc$libresoc.v:118111$4463 assign { } { } assign { } { } assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:117570.5-117570.29" + attribute \src "libresoc.v:118112.5-118112.29" switch \initial - attribute \src "libresoc.v:117570.9-117570.17" + attribute \src "libresoc.v:118112.9-118112.17" case 1'1 case end @@ -182951,14 +184290,14 @@ module \dec58 sync always update \dec58_inv_out $0\dec58_inv_out[0:0] end - attribute \src "libresoc.v:117585.3-117600.6" - process $proc$libresoc.v:117585$4410 + attribute \src "libresoc.v:118127.3-118142.6" + process $proc$libresoc.v:118127$4464 assign { } { } assign { } { } assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:117586.5-117586.29" + attribute \src "libresoc.v:118128.5-118128.29" switch \initial - attribute \src "libresoc.v:117586.9-117586.17" + attribute \src "libresoc.v:118128.9-118128.17" case 1'1 case end @@ -182982,14 +184321,14 @@ module \dec58 sync always update \dec58_cry_out $0\dec58_cry_out[0:0] end - attribute \src "libresoc.v:117601.3-117616.6" - process $proc$libresoc.v:117601$4411 + attribute \src "libresoc.v:118143.3-118158.6" + process $proc$libresoc.v:118143$4465 assign { } { } assign { } { } assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:117602.5-117602.29" + attribute \src "libresoc.v:118144.5-118144.29" switch \initial - attribute \src "libresoc.v:117602.9-117602.17" + attribute \src "libresoc.v:118144.9-118144.17" case 1'1 case end @@ -183013,14 +184352,14 @@ module \dec58 sync always update \dec58_br $0\dec58_br[0:0] end - attribute \src "libresoc.v:117617.3-117632.6" - process $proc$libresoc.v:117617$4412 + attribute \src "libresoc.v:118159.3-118174.6" + process $proc$libresoc.v:118159$4466 assign { } { } assign { } { } assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:117618.5-117618.29" + attribute \src "libresoc.v:118160.5-118160.29" switch \initial - attribute \src "libresoc.v:117618.9-117618.17" + attribute \src "libresoc.v:118160.9-118160.17" case 1'1 case end @@ -183044,14 +184383,14 @@ module \dec58 sync always update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end - attribute \src "libresoc.v:117633.3-117648.6" - process $proc$libresoc.v:117633$4413 + attribute \src "libresoc.v:118175.3-118190.6" + process $proc$libresoc.v:118175$4467 assign { } { } assign { } { } assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:117634.5-117634.29" + attribute \src "libresoc.v:118176.5-118176.29" switch \initial - attribute \src "libresoc.v:117634.9-117634.17" + attribute \src "libresoc.v:118176.9-118176.17" case 1'1 case end @@ -183075,14 +184414,14 @@ module \dec58 sync always update \dec58_rsrv $0\dec58_rsrv[0:0] end - attribute \src "libresoc.v:117649.3-117664.6" - process $proc$libresoc.v:117649$4414 + attribute \src "libresoc.v:118191.3-118206.6" + process $proc$libresoc.v:118191$4468 assign { } { } assign { } { } assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:117650.5-117650.29" + attribute \src "libresoc.v:118192.5-118192.29" switch \initial - attribute \src "libresoc.v:117650.9-117650.17" + attribute \src "libresoc.v:118192.9-118192.17" case 1'1 case end @@ -183106,14 +184445,14 @@ module \dec58 sync always update \dec58_is_32b $0\dec58_is_32b[0:0] end - attribute \src "libresoc.v:117665.3-117680.6" - process $proc$libresoc.v:117665$4415 + attribute \src "libresoc.v:118207.3-118222.6" + process $proc$libresoc.v:118207$4469 assign { } { } assign { } { } assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:117666.5-117666.29" + attribute \src "libresoc.v:118208.5-118208.29" switch \initial - attribute \src "libresoc.v:117666.9-117666.17" + attribute \src "libresoc.v:118208.9-118208.17" case 1'1 case end @@ -183137,14 +184476,14 @@ module \dec58 sync always update \dec58_form $0\dec58_form[4:0] end - attribute \src "libresoc.v:117681.3-117696.6" - process $proc$libresoc.v:117681$4416 + attribute \src "libresoc.v:118223.3-118238.6" + process $proc$libresoc.v:118223$4470 assign { } { } assign { } { } assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:117682.5-117682.29" + attribute \src "libresoc.v:118224.5-118224.29" switch \initial - attribute \src "libresoc.v:117682.9-117682.17" + attribute \src "libresoc.v:118224.9-118224.17" case 1'1 case end @@ -183168,14 +184507,14 @@ module \dec58 sync always update \dec58_sgn $0\dec58_sgn[0:0] end - attribute \src "libresoc.v:117697.3-117712.6" - process $proc$libresoc.v:117697$4417 + attribute \src "libresoc.v:118239.3-118254.6" + process $proc$libresoc.v:118239$4471 assign { } { } assign { } { } assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:117698.5-117698.29" + attribute \src "libresoc.v:118240.5-118240.29" switch \initial - attribute \src "libresoc.v:117698.9-117698.17" + attribute \src "libresoc.v:118240.9-118240.17" case 1'1 case end @@ -183199,14 +184538,14 @@ module \dec58 sync always update \dec58_lk $0\dec58_lk[0:0] end - attribute \src "libresoc.v:117713.3-117728.6" - process $proc$libresoc.v:117713$4418 + attribute \src "libresoc.v:118255.3-118270.6" + process $proc$libresoc.v:118255$4472 assign { } { } assign { } { } assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:117714.5-117714.29" + attribute \src "libresoc.v:118256.5-118256.29" switch \initial - attribute \src "libresoc.v:117714.9-117714.17" + attribute \src "libresoc.v:118256.9-118256.17" case 1'1 case end @@ -183230,14 +184569,14 @@ module \dec58 sync always update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end - attribute \src "libresoc.v:117729.3-117744.6" - process $proc$libresoc.v:117729$4419 + attribute \src "libresoc.v:118271.3-118286.6" + process $proc$libresoc.v:118271$4473 assign { } { } assign { } { } assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:117730.5-117730.29" + attribute \src "libresoc.v:118272.5-118272.29" switch \initial - attribute \src "libresoc.v:117730.9-117730.17" + attribute \src "libresoc.v:118272.9-118272.17" case 1'1 case end @@ -183261,14 +184600,14 @@ module \dec58 sync always update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] end - attribute \src "libresoc.v:117745.3-117760.6" - process $proc$libresoc.v:117745$4420 + attribute \src "libresoc.v:118287.3-118302.6" + process $proc$libresoc.v:118287$4474 assign { } { } assign { } { } assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:117746.5-117746.29" + attribute \src "libresoc.v:118288.5-118288.29" switch \initial - attribute \src "libresoc.v:117746.9-117746.17" + attribute \src "libresoc.v:118288.9-118288.17" case 1'1 case end @@ -183292,14 +184631,14 @@ module \dec58 sync always update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] end - attribute \src "libresoc.v:117761.3-117776.6" - process $proc$libresoc.v:117761$4421 + attribute \src "libresoc.v:118303.3-118318.6" + process $proc$libresoc.v:118303$4475 assign { } { } assign { } { } assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:117762.5-117762.29" + attribute \src "libresoc.v:118304.5-118304.29" switch \initial - attribute \src "libresoc.v:117762.9-117762.17" + attribute \src "libresoc.v:118304.9-118304.17" case 1'1 case end @@ -183323,14 +184662,14 @@ module \dec58 sync always update \dec58_in1_sel $0\dec58_in1_sel[2:0] end - attribute \src "libresoc.v:117777.3-117792.6" - process $proc$libresoc.v:117777$4422 + attribute \src "libresoc.v:118319.3-118334.6" + process $proc$libresoc.v:118319$4476 assign { } { } assign { } { } assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:117778.5-117778.29" + attribute \src "libresoc.v:118320.5-118320.29" switch \initial - attribute \src "libresoc.v:117778.9-117778.17" + attribute \src "libresoc.v:118320.9-118320.17" case 1'1 case end @@ -183354,14 +184693,14 @@ module \dec58 sync always update \dec58_in2_sel $0\dec58_in2_sel[3:0] end - attribute \src "libresoc.v:117793.3-117808.6" - process $proc$libresoc.v:117793$4423 + attribute \src "libresoc.v:118335.3-118350.6" + process $proc$libresoc.v:118335$4477 assign { } { } assign { } { } assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:117794.5-117794.29" + attribute \src "libresoc.v:118336.5-118336.29" switch \initial - attribute \src "libresoc.v:117794.9-117794.17" + attribute \src "libresoc.v:118336.9-118336.17" case 1'1 case end @@ -183385,14 +184724,14 @@ module \dec58 sync always update \dec58_in3_sel $0\dec58_in3_sel[1:0] end - attribute \src "libresoc.v:117809.3-117824.6" - process $proc$libresoc.v:117809$4424 + attribute \src "libresoc.v:118351.3-118366.6" + process $proc$libresoc.v:118351$4478 assign { } { } assign { } { } assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:117810.5-117810.29" + attribute \src "libresoc.v:118352.5-118352.29" switch \initial - attribute \src "libresoc.v:117810.9-117810.17" + attribute \src "libresoc.v:118352.9-118352.17" case 1'1 case end @@ -183418,140 +184757,140 @@ module \dec58 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:117830.1-118582.10" +attribute \src "libresoc.v:118372.1-119125.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" attribute \generator "nMigen" module \dec62 - attribute \src "libresoc.v:118503.3-118515.6" + attribute \src "libresoc.v:119046.3-119058.6" wire width 2 $0\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:118516.3-118528.6" + attribute \src "libresoc.v:119059.3-119071.6" wire width 2 $0\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:118347.3-118359.6" + attribute \src "libresoc.v:118890.3-118902.6" wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:118399.3-118411.6" + attribute \src "libresoc.v:118942.3-118954.6" wire $0\dec62_br[0:0] - attribute \src "libresoc.v:118178.3-118190.6" + attribute \src "libresoc.v:118721.3-118733.6" wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:118191.3-118203.6" + attribute \src "libresoc.v:118734.3-118746.6" wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:118334.3-118346.6" + attribute \src "libresoc.v:118877.3-118889.6" wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:118386.3-118398.6" + attribute \src "libresoc.v:118929.3-118941.6" wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:118451.3-118463.6" + attribute \src "libresoc.v:118994.3-119006.6" wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:118165.3-118177.6" + attribute \src "libresoc.v:118708.3-118720.6" wire width 13 $0\dec62_function_unit[12:0] - attribute \src "libresoc.v:118529.3-118541.6" + attribute \src "libresoc.v:119072.3-119084.6" wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:118542.3-118554.6" + attribute \src "libresoc.v:119085.3-119097.6" wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:118555.3-118567.6" + attribute \src "libresoc.v:119098.3-119110.6" wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:118308.3-118320.6" + attribute \src "libresoc.v:118851.3-118863.6" wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:118360.3-118372.6" + attribute \src "libresoc.v:118903.3-118915.6" wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:118373.3-118385.6" + attribute \src "libresoc.v:118916.3-118928.6" wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:118438.3-118450.6" + attribute \src "libresoc.v:118981.3-118993.6" wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:118282.3-118294.6" + attribute \src "libresoc.v:118825.3-118837.6" wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:118477.3-118489.6" + attribute \src "libresoc.v:119020.3-119032.6" wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:118568.3-118580.6" + attribute \src "libresoc.v:119111.3-119123.6" wire width 2 $0\dec62_out_sel[1:0] - attribute \src "libresoc.v:118321.3-118333.6" + attribute \src "libresoc.v:118864.3-118876.6" wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:118425.3-118437.6" + attribute \src "libresoc.v:118968.3-118980.6" wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:118490.3-118502.6" + attribute \src "libresoc.v:119033.3-119045.6" wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:118464.3-118476.6" + attribute \src "libresoc.v:119007.3-119019.6" wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:118412.3-118424.6" + attribute \src "libresoc.v:118955.3-118967.6" wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:118256.3-118268.6" + attribute \src "libresoc.v:118799.3-118811.6" wire width 3 $0\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:118269.3-118281.6" + attribute \src "libresoc.v:118812.3-118824.6" wire width 3 $0\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:118204.3-118216.6" + attribute \src "libresoc.v:118747.3-118759.6" wire width 3 $0\dec62_sv_in1[2:0] - attribute \src "libresoc.v:118217.3-118229.6" + attribute \src "libresoc.v:118760.3-118772.6" wire width 3 $0\dec62_sv_in2[2:0] - attribute \src "libresoc.v:118230.3-118242.6" + attribute \src "libresoc.v:118773.3-118785.6" wire width 3 $0\dec62_sv_in3[2:0] - attribute \src "libresoc.v:118243.3-118255.6" + attribute \src "libresoc.v:118786.3-118798.6" wire width 3 $0\dec62_sv_out[2:0] - attribute \src "libresoc.v:118295.3-118307.6" + attribute \src "libresoc.v:118838.3-118850.6" wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:117831.7-117831.20" + attribute \src "libresoc.v:118373.7-118373.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118503.3-118515.6" + attribute \src "libresoc.v:119046.3-119058.6" wire width 2 $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:118516.3-118528.6" + attribute \src "libresoc.v:119059.3-119071.6" wire width 2 $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:118347.3-118359.6" + attribute \src "libresoc.v:118890.3-118902.6" wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:118399.3-118411.6" + attribute \src "libresoc.v:118942.3-118954.6" wire $1\dec62_br[0:0] - attribute \src "libresoc.v:118178.3-118190.6" + attribute \src "libresoc.v:118721.3-118733.6" wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:118191.3-118203.6" + attribute \src "libresoc.v:118734.3-118746.6" wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:118334.3-118346.6" + attribute \src "libresoc.v:118877.3-118889.6" wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:118386.3-118398.6" + attribute \src "libresoc.v:118929.3-118941.6" wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:118451.3-118463.6" + attribute \src "libresoc.v:118994.3-119006.6" wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:118165.3-118177.6" + attribute \src "libresoc.v:118708.3-118720.6" wire width 13 $1\dec62_function_unit[12:0] - attribute \src "libresoc.v:118529.3-118541.6" + attribute \src "libresoc.v:119072.3-119084.6" wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:118542.3-118554.6" + attribute \src "libresoc.v:119085.3-119097.6" wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:118555.3-118567.6" + attribute \src "libresoc.v:119098.3-119110.6" wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:118308.3-118320.6" + attribute \src "libresoc.v:118851.3-118863.6" wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:118360.3-118372.6" + attribute \src "libresoc.v:118903.3-118915.6" wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:118373.3-118385.6" + attribute \src "libresoc.v:118916.3-118928.6" wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:118438.3-118450.6" + attribute \src "libresoc.v:118981.3-118993.6" wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:118282.3-118294.6" + attribute \src "libresoc.v:118825.3-118837.6" wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:118477.3-118489.6" + attribute \src "libresoc.v:119020.3-119032.6" wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:118568.3-118580.6" + attribute \src "libresoc.v:119111.3-119123.6" wire width 2 $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:118321.3-118333.6" + attribute \src "libresoc.v:118864.3-118876.6" wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:118425.3-118437.6" + attribute \src "libresoc.v:118968.3-118980.6" wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:118490.3-118502.6" + attribute \src "libresoc.v:119033.3-119045.6" wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:118464.3-118476.6" + attribute \src "libresoc.v:119007.3-119019.6" wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:118412.3-118424.6" + attribute \src "libresoc.v:118955.3-118967.6" wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:118256.3-118268.6" + attribute \src "libresoc.v:118799.3-118811.6" wire width 3 $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:118269.3-118281.6" + attribute \src "libresoc.v:118812.3-118824.6" wire width 3 $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:118204.3-118216.6" + attribute \src "libresoc.v:118747.3-118759.6" wire width 3 $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:118217.3-118229.6" + attribute \src "libresoc.v:118760.3-118772.6" wire width 3 $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:118230.3-118242.6" + attribute \src "libresoc.v:118773.3-118785.6" wire width 3 $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:118243.3-118255.6" + attribute \src "libresoc.v:118786.3-118798.6" wire width 3 $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:118295.3-118307.6" + attribute \src "libresoc.v:118838.3-118850.6" wire width 2 $1\dec62_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -183627,6 +184966,7 @@ module \dec62 attribute \enum_value_11010 "EVS" attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" + attribute \enum_value_11101 "SVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 5 output 3 \dec62_form attribute \enum_base_type "Function" @@ -183850,28 +185190,28 @@ module \dec62 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 output 20 \dec62_upd - attribute \src "libresoc.v:117831.7-117831.15" + attribute \src "libresoc.v:118373.7-118373.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 input 33 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" wire width 2 \opcode_switch - attribute \src "libresoc.v:117831.7-117831.20" - process $proc$libresoc.v:117831$4458 + attribute \src "libresoc.v:118373.7-118373.20" + process $proc$libresoc.v:118373$4512 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:118165.3-118177.6" - process $proc$libresoc.v:118165$4426 + attribute \src "libresoc.v:118708.3-118720.6" + process $proc$libresoc.v:118708$4480 assign { } { } assign { } { } assign $0\dec62_function_unit[12:0] $1\dec62_function_unit[12:0] - attribute \src "libresoc.v:118166.5-118166.29" + attribute \src "libresoc.v:118709.5-118709.29" switch \initial - attribute \src "libresoc.v:118166.9-118166.17" + attribute \src "libresoc.v:118709.9-118709.17" case 1'1 case end @@ -183891,14 +185231,14 @@ module \dec62 sync always update \dec62_function_unit $0\dec62_function_unit[12:0] end - attribute \src "libresoc.v:118178.3-118190.6" - process $proc$libresoc.v:118178$4427 + attribute \src "libresoc.v:118721.3-118733.6" + process $proc$libresoc.v:118721$4481 assign { } { } assign { } { } assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:118179.5-118179.29" + attribute \src "libresoc.v:118722.5-118722.29" switch \initial - attribute \src "libresoc.v:118179.9-118179.17" + attribute \src "libresoc.v:118722.9-118722.17" case 1'1 case end @@ -183918,14 +185258,14 @@ module \dec62 sync always update \dec62_cr_in $0\dec62_cr_in[2:0] end - attribute \src "libresoc.v:118191.3-118203.6" - process $proc$libresoc.v:118191$4428 + attribute \src "libresoc.v:118734.3-118746.6" + process $proc$libresoc.v:118734$4482 assign { } { } assign { } { } assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:118192.5-118192.29" + attribute \src "libresoc.v:118735.5-118735.29" switch \initial - attribute \src "libresoc.v:118192.9-118192.17" + attribute \src "libresoc.v:118735.9-118735.17" case 1'1 case end @@ -183945,14 +185285,14 @@ module \dec62 sync always update \dec62_cr_out $0\dec62_cr_out[2:0] end - attribute \src "libresoc.v:118204.3-118216.6" - process $proc$libresoc.v:118204$4429 + attribute \src "libresoc.v:118747.3-118759.6" + process $proc$libresoc.v:118747$4483 assign { } { } assign { } { } assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:118205.5-118205.29" + attribute \src "libresoc.v:118748.5-118748.29" switch \initial - attribute \src "libresoc.v:118205.9-118205.17" + attribute \src "libresoc.v:118748.9-118748.17" case 1'1 case end @@ -183972,14 +185312,14 @@ module \dec62 sync always update \dec62_sv_in1 $0\dec62_sv_in1[2:0] end - attribute \src "libresoc.v:118217.3-118229.6" - process $proc$libresoc.v:118217$4430 + attribute \src "libresoc.v:118760.3-118772.6" + process $proc$libresoc.v:118760$4484 assign { } { } assign { } { } assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:118218.5-118218.29" + attribute \src "libresoc.v:118761.5-118761.29" switch \initial - attribute \src "libresoc.v:118218.9-118218.17" + attribute \src "libresoc.v:118761.9-118761.17" case 1'1 case end @@ -183999,14 +185339,14 @@ module \dec62 sync always update \dec62_sv_in2 $0\dec62_sv_in2[2:0] end - attribute \src "libresoc.v:118230.3-118242.6" - process $proc$libresoc.v:118230$4431 + attribute \src "libresoc.v:118773.3-118785.6" + process $proc$libresoc.v:118773$4485 assign { } { } assign { } { } assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:118231.5-118231.29" + attribute \src "libresoc.v:118774.5-118774.29" switch \initial - attribute \src "libresoc.v:118231.9-118231.17" + attribute \src "libresoc.v:118774.9-118774.17" case 1'1 case end @@ -184026,14 +185366,14 @@ module \dec62 sync always update \dec62_sv_in3 $0\dec62_sv_in3[2:0] end - attribute \src "libresoc.v:118243.3-118255.6" - process $proc$libresoc.v:118243$4432 + attribute \src "libresoc.v:118786.3-118798.6" + process $proc$libresoc.v:118786$4486 assign { } { } assign { } { } assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:118244.5-118244.29" + attribute \src "libresoc.v:118787.5-118787.29" switch \initial - attribute \src "libresoc.v:118244.9-118244.17" + attribute \src "libresoc.v:118787.9-118787.17" case 1'1 case end @@ -184053,14 +185393,14 @@ module \dec62 sync always update \dec62_sv_out $0\dec62_sv_out[2:0] end - attribute \src "libresoc.v:118256.3-118268.6" - process $proc$libresoc.v:118256$4433 + attribute \src "libresoc.v:118799.3-118811.6" + process $proc$libresoc.v:118799$4487 assign { } { } assign { } { } assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:118257.5-118257.29" + attribute \src "libresoc.v:118800.5-118800.29" switch \initial - attribute \src "libresoc.v:118257.9-118257.17" + attribute \src "libresoc.v:118800.9-118800.17" case 1'1 case end @@ -184080,14 +185420,14 @@ module \dec62 sync always update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] end - attribute \src "libresoc.v:118269.3-118281.6" - process $proc$libresoc.v:118269$4434 + attribute \src "libresoc.v:118812.3-118824.6" + process $proc$libresoc.v:118812$4488 assign { } { } assign { } { } assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:118270.5-118270.29" + attribute \src "libresoc.v:118813.5-118813.29" switch \initial - attribute \src "libresoc.v:118270.9-118270.17" + attribute \src "libresoc.v:118813.9-118813.17" case 1'1 case end @@ -184107,14 +185447,14 @@ module \dec62 sync always update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] end - attribute \src "libresoc.v:118282.3-118294.6" - process $proc$libresoc.v:118282$4435 + attribute \src "libresoc.v:118825.3-118837.6" + process $proc$libresoc.v:118825$4489 assign { } { } assign { } { } assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:118283.5-118283.29" + attribute \src "libresoc.v:118826.5-118826.29" switch \initial - attribute \src "libresoc.v:118283.9-118283.17" + attribute \src "libresoc.v:118826.9-118826.17" case 1'1 case end @@ -184134,14 +185474,14 @@ module \dec62 sync always update \dec62_ldst_len $0\dec62_ldst_len[3:0] end - attribute \src "libresoc.v:118295.3-118307.6" - process $proc$libresoc.v:118295$4436 + attribute \src "libresoc.v:118838.3-118850.6" + process $proc$libresoc.v:118838$4490 assign { } { } assign { } { } assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:118296.5-118296.29" + attribute \src "libresoc.v:118839.5-118839.29" switch \initial - attribute \src "libresoc.v:118296.9-118296.17" + attribute \src "libresoc.v:118839.9-118839.17" case 1'1 case end @@ -184161,14 +185501,14 @@ module \dec62 sync always update \dec62_upd $0\dec62_upd[1:0] end - attribute \src "libresoc.v:118308.3-118320.6" - process $proc$libresoc.v:118308$4437 + attribute \src "libresoc.v:118851.3-118863.6" + process $proc$libresoc.v:118851$4491 assign { } { } assign { } { } assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:118309.5-118309.29" + attribute \src "libresoc.v:118852.5-118852.29" switch \initial - attribute \src "libresoc.v:118309.9-118309.17" + attribute \src "libresoc.v:118852.9-118852.17" case 1'1 case end @@ -184188,14 +185528,14 @@ module \dec62 sync always update \dec62_internal_op $0\dec62_internal_op[6:0] end - attribute \src "libresoc.v:118321.3-118333.6" - process $proc$libresoc.v:118321$4438 + attribute \src "libresoc.v:118864.3-118876.6" + process $proc$libresoc.v:118864$4492 assign { } { } assign { } { } assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:118322.5-118322.29" + attribute \src "libresoc.v:118865.5-118865.29" switch \initial - attribute \src "libresoc.v:118322.9-118322.17" + attribute \src "libresoc.v:118865.9-118865.17" case 1'1 case end @@ -184215,14 +185555,14 @@ module \dec62 sync always update \dec62_rc_sel $0\dec62_rc_sel[1:0] end - attribute \src "libresoc.v:118334.3-118346.6" - process $proc$libresoc.v:118334$4439 + attribute \src "libresoc.v:118877.3-118889.6" + process $proc$libresoc.v:118877$4493 assign { } { } assign { } { } assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:118335.5-118335.29" + attribute \src "libresoc.v:118878.5-118878.29" switch \initial - attribute \src "libresoc.v:118335.9-118335.17" + attribute \src "libresoc.v:118878.9-118878.17" case 1'1 case end @@ -184242,14 +185582,14 @@ module \dec62 sync always update \dec62_cry_in $0\dec62_cry_in[1:0] end - attribute \src "libresoc.v:118347.3-118359.6" - process $proc$libresoc.v:118347$4440 + attribute \src "libresoc.v:118890.3-118902.6" + process $proc$libresoc.v:118890$4494 assign { } { } assign { } { } assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:118348.5-118348.29" + attribute \src "libresoc.v:118891.5-118891.29" switch \initial - attribute \src "libresoc.v:118348.9-118348.17" + attribute \src "libresoc.v:118891.9-118891.17" case 1'1 case end @@ -184269,14 +185609,14 @@ module \dec62 sync always update \dec62_asmcode $0\dec62_asmcode[7:0] end - attribute \src "libresoc.v:118360.3-118372.6" - process $proc$libresoc.v:118360$4441 + attribute \src "libresoc.v:118903.3-118915.6" + process $proc$libresoc.v:118903$4495 assign { } { } assign { } { } assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:118361.5-118361.29" + attribute \src "libresoc.v:118904.5-118904.29" switch \initial - attribute \src "libresoc.v:118361.9-118361.17" + attribute \src "libresoc.v:118904.9-118904.17" case 1'1 case end @@ -184296,14 +185636,14 @@ module \dec62 sync always update \dec62_inv_a $0\dec62_inv_a[0:0] end - attribute \src "libresoc.v:118373.3-118385.6" - process $proc$libresoc.v:118373$4442 + attribute \src "libresoc.v:118916.3-118928.6" + process $proc$libresoc.v:118916$4496 assign { } { } assign { } { } assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:118374.5-118374.29" + attribute \src "libresoc.v:118917.5-118917.29" switch \initial - attribute \src "libresoc.v:118374.9-118374.17" + attribute \src "libresoc.v:118917.9-118917.17" case 1'1 case end @@ -184323,14 +185663,14 @@ module \dec62 sync always update \dec62_inv_out $0\dec62_inv_out[0:0] end - attribute \src "libresoc.v:118386.3-118398.6" - process $proc$libresoc.v:118386$4443 + attribute \src "libresoc.v:118929.3-118941.6" + process $proc$libresoc.v:118929$4497 assign { } { } assign { } { } assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:118387.5-118387.29" + attribute \src "libresoc.v:118930.5-118930.29" switch \initial - attribute \src "libresoc.v:118387.9-118387.17" + attribute \src "libresoc.v:118930.9-118930.17" case 1'1 case end @@ -184350,14 +185690,14 @@ module \dec62 sync always update \dec62_cry_out $0\dec62_cry_out[0:0] end - attribute \src "libresoc.v:118399.3-118411.6" - process $proc$libresoc.v:118399$4444 + attribute \src "libresoc.v:118942.3-118954.6" + process $proc$libresoc.v:118942$4498 assign { } { } assign { } { } assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:118400.5-118400.29" + attribute \src "libresoc.v:118943.5-118943.29" switch \initial - attribute \src "libresoc.v:118400.9-118400.17" + attribute \src "libresoc.v:118943.9-118943.17" case 1'1 case end @@ -184377,14 +185717,14 @@ module \dec62 sync always update \dec62_br $0\dec62_br[0:0] end - attribute \src "libresoc.v:118412.3-118424.6" - process $proc$libresoc.v:118412$4445 + attribute \src "libresoc.v:118955.3-118967.6" + process $proc$libresoc.v:118955$4499 assign { } { } assign { } { } assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:118413.5-118413.29" + attribute \src "libresoc.v:118956.5-118956.29" switch \initial - attribute \src "libresoc.v:118413.9-118413.17" + attribute \src "libresoc.v:118956.9-118956.17" case 1'1 case end @@ -184404,14 +185744,14 @@ module \dec62 sync always update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] end - attribute \src "libresoc.v:118425.3-118437.6" - process $proc$libresoc.v:118425$4446 + attribute \src "libresoc.v:118968.3-118980.6" + process $proc$libresoc.v:118968$4500 assign { } { } assign { } { } assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:118426.5-118426.29" + attribute \src "libresoc.v:118969.5-118969.29" switch \initial - attribute \src "libresoc.v:118426.9-118426.17" + attribute \src "libresoc.v:118969.9-118969.17" case 1'1 case end @@ -184431,14 +185771,14 @@ module \dec62 sync always update \dec62_rsrv $0\dec62_rsrv[0:0] end - attribute \src "libresoc.v:118438.3-118450.6" - process $proc$libresoc.v:118438$4447 + attribute \src "libresoc.v:118981.3-118993.6" + process $proc$libresoc.v:118981$4501 assign { } { } assign { } { } assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:118439.5-118439.29" + attribute \src "libresoc.v:118982.5-118982.29" switch \initial - attribute \src "libresoc.v:118439.9-118439.17" + attribute \src "libresoc.v:118982.9-118982.17" case 1'1 case end @@ -184458,14 +185798,14 @@ module \dec62 sync always update \dec62_is_32b $0\dec62_is_32b[0:0] end - attribute \src "libresoc.v:118451.3-118463.6" - process $proc$libresoc.v:118451$4448 + attribute \src "libresoc.v:118994.3-119006.6" + process $proc$libresoc.v:118994$4502 assign { } { } assign { } { } assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:118452.5-118452.29" + attribute \src "libresoc.v:118995.5-118995.29" switch \initial - attribute \src "libresoc.v:118452.9-118452.17" + attribute \src "libresoc.v:118995.9-118995.17" case 1'1 case end @@ -184485,14 +185825,14 @@ module \dec62 sync always update \dec62_form $0\dec62_form[4:0] end - attribute \src "libresoc.v:118464.3-118476.6" - process $proc$libresoc.v:118464$4449 + attribute \src "libresoc.v:119007.3-119019.6" + process $proc$libresoc.v:119007$4503 assign { } { } assign { } { } assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:118465.5-118465.29" + attribute \src "libresoc.v:119008.5-119008.29" switch \initial - attribute \src "libresoc.v:118465.9-118465.17" + attribute \src "libresoc.v:119008.9-119008.17" case 1'1 case end @@ -184512,14 +185852,14 @@ module \dec62 sync always update \dec62_sgn $0\dec62_sgn[0:0] end - attribute \src "libresoc.v:118477.3-118489.6" - process $proc$libresoc.v:118477$4450 + attribute \src "libresoc.v:119020.3-119032.6" + process $proc$libresoc.v:119020$4504 assign { } { } assign { } { } assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:118478.5-118478.29" + attribute \src "libresoc.v:119021.5-119021.29" switch \initial - attribute \src "libresoc.v:118478.9-118478.17" + attribute \src "libresoc.v:119021.9-119021.17" case 1'1 case end @@ -184539,14 +185879,14 @@ module \dec62 sync always update \dec62_lk $0\dec62_lk[0:0] end - attribute \src "libresoc.v:118490.3-118502.6" - process $proc$libresoc.v:118490$4451 + attribute \src "libresoc.v:119033.3-119045.6" + process $proc$libresoc.v:119033$4505 assign { } { } assign { } { } assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:118491.5-118491.29" + attribute \src "libresoc.v:119034.5-119034.29" switch \initial - attribute \src "libresoc.v:118491.9-118491.17" + attribute \src "libresoc.v:119034.9-119034.17" case 1'1 case end @@ -184566,14 +185906,14 @@ module \dec62 sync always update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end - attribute \src "libresoc.v:118503.3-118515.6" - process $proc$libresoc.v:118503$4452 + attribute \src "libresoc.v:119046.3-119058.6" + process $proc$libresoc.v:119046$4506 assign { } { } assign { } { } assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:118504.5-118504.29" + attribute \src "libresoc.v:119047.5-119047.29" switch \initial - attribute \src "libresoc.v:118504.9-118504.17" + attribute \src "libresoc.v:119047.9-119047.17" case 1'1 case end @@ -184593,14 +185933,14 @@ module \dec62 sync always update \dec62_SV_Etype $0\dec62_SV_Etype[1:0] end - attribute \src "libresoc.v:118516.3-118528.6" - process $proc$libresoc.v:118516$4453 + attribute \src "libresoc.v:119059.3-119071.6" + process $proc$libresoc.v:119059$4507 assign { } { } assign { } { } assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:118517.5-118517.29" + attribute \src "libresoc.v:119060.5-119060.29" switch \initial - attribute \src "libresoc.v:118517.9-118517.17" + attribute \src "libresoc.v:119060.9-119060.17" case 1'1 case end @@ -184620,14 +185960,14 @@ module \dec62 sync always update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] end - attribute \src "libresoc.v:118529.3-118541.6" - process $proc$libresoc.v:118529$4454 + attribute \src "libresoc.v:119072.3-119084.6" + process $proc$libresoc.v:119072$4508 assign { } { } assign { } { } assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:118530.5-118530.29" + attribute \src "libresoc.v:119073.5-119073.29" switch \initial - attribute \src "libresoc.v:118530.9-118530.17" + attribute \src "libresoc.v:119073.9-119073.17" case 1'1 case end @@ -184647,14 +185987,14 @@ module \dec62 sync always update \dec62_in1_sel $0\dec62_in1_sel[2:0] end - attribute \src "libresoc.v:118542.3-118554.6" - process $proc$libresoc.v:118542$4455 + attribute \src "libresoc.v:119085.3-119097.6" + process $proc$libresoc.v:119085$4509 assign { } { } assign { } { } assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:118543.5-118543.29" + attribute \src "libresoc.v:119086.5-119086.29" switch \initial - attribute \src "libresoc.v:118543.9-118543.17" + attribute \src "libresoc.v:119086.9-119086.17" case 1'1 case end @@ -184674,14 +186014,14 @@ module \dec62 sync always update \dec62_in2_sel $0\dec62_in2_sel[3:0] end - attribute \src "libresoc.v:118555.3-118567.6" - process $proc$libresoc.v:118555$4456 + attribute \src "libresoc.v:119098.3-119110.6" + process $proc$libresoc.v:119098$4510 assign { } { } assign { } { } assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:118556.5-118556.29" + attribute \src "libresoc.v:119099.5-119099.29" switch \initial - attribute \src "libresoc.v:118556.9-118556.17" + attribute \src "libresoc.v:119099.9-119099.17" case 1'1 case end @@ -184701,14 +186041,14 @@ module \dec62 sync always update \dec62_in3_sel $0\dec62_in3_sel[1:0] end - attribute \src "libresoc.v:118568.3-118580.6" - process $proc$libresoc.v:118568$4457 + attribute \src "libresoc.v:119111.3-119123.6" + process $proc$libresoc.v:119111$4511 assign { } { } assign { } { } assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:118569.5-118569.29" + attribute \src "libresoc.v:119112.5-119112.29" switch \initial - attribute \src "libresoc.v:118569.9-118569.17" + attribute \src "libresoc.v:119112.9-119112.17" case 1'1 case end @@ -184730,60 +186070,120 @@ module \dec62 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:118586.1-119177.10" +attribute \src "libresoc.v:119129.1-119702.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" attribute \generator "nMigen" module \dec_ALU - attribute \src "libresoc.v:119139.3-119150.6" + attribute \src "libresoc.v:119666.3-119680.6" wire width 13 $0\ALU__fn_unit[12:0] - attribute \src "libresoc.v:118587.7-118587.20" + attribute \src "libresoc.v:119653.3-119665.6" + wire width 7 $0\ALU__insn_type[6:0] + attribute \src "libresoc.v:119638.3-119652.6" + wire $0\ALU__write_cr0[0:0] + attribute \src "libresoc.v:119130.7-119130.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119139.3-119150.6" + attribute \src "libresoc.v:119666.3-119680.6" wire width 13 $1\ALU__fn_unit[12:0] - attribute \src "libresoc.v:119043.18-119043.109" - wire $and$libresoc.v:119043$4465_Y - attribute \src "libresoc.v:119037.18-119037.112" - wire $eq$libresoc.v:119037$4459_Y - attribute \src "libresoc.v:119039.18-119039.112" - wire $eq$libresoc.v:119039$4461_Y - attribute \src "libresoc.v:119041.18-119041.110" - wire $eq$libresoc.v:119041$4463_Y - attribute \src "libresoc.v:119044.17-119044.125" - wire $eq$libresoc.v:119044$4466_Y - attribute \src "libresoc.v:119045.17-119045.125" - wire $eq$libresoc.v:119045$4467_Y - attribute \src "libresoc.v:119047.17-119047.111" - wire $eq$libresoc.v:119047$4469_Y - attribute \src "libresoc.v:119038.18-119038.109" - wire $or$libresoc.v:119038$4460_Y - attribute \src "libresoc.v:119040.18-119040.110" - wire $or$libresoc.v:119040$4462_Y - attribute \src "libresoc.v:119042.18-119042.110" - wire $or$libresoc.v:119042$4464_Y - attribute \src "libresoc.v:119046.17-119046.107" - wire $or$libresoc.v:119046$4468_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "libresoc.v:119653.3-119665.6" + wire width 7 $1\ALU__insn_type[6:0] + attribute \src "libresoc.v:119638.3-119652.6" + wire $1\ALU__write_cr0[0:0] + attribute \src "libresoc.v:119555.18-119555.113" + wire $and$libresoc.v:119555$4513_Y + attribute \src "libresoc.v:119557.18-119557.110" + wire $and$libresoc.v:119557$4515_Y + attribute \src "libresoc.v:119570.18-119570.114" + wire $and$libresoc.v:119570$4528_Y + attribute \src "libresoc.v:119571.18-119571.116" + wire $and$libresoc.v:119571$4529_Y + attribute \src "libresoc.v:119573.18-119573.114" + wire $and$libresoc.v:119573$4531_Y + attribute \src "libresoc.v:119575.18-119575.110" + wire $and$libresoc.v:119575$4533_Y + attribute \src "libresoc.v:119576.17-119576.112" + wire $and$libresoc.v:119576$4534_Y + attribute \src "libresoc.v:119577.17-119577.114" + wire $and$libresoc.v:119577$4535_Y + attribute \src "libresoc.v:119558.18-119558.126" + wire $eq$libresoc.v:119558$4516_Y + attribute \src "libresoc.v:119559.18-119559.126" + wire $eq$libresoc.v:119559$4517_Y + attribute \src "libresoc.v:119561.18-119561.110" + wire $eq$libresoc.v:119561$4519_Y + attribute \src "libresoc.v:119562.18-119562.110" + wire $eq$libresoc.v:119562$4520_Y + attribute \src "libresoc.v:119564.18-119564.112" + wire $eq$libresoc.v:119564$4522_Y + attribute \src "libresoc.v:119565.17-119565.130" + wire $eq$libresoc.v:119565$4523_Y + attribute \src "libresoc.v:119567.18-119567.110" + wire $eq$libresoc.v:119567$4525_Y + attribute \src "libresoc.v:119569.18-119569.131" + wire $eq$libresoc.v:119569$4527_Y + attribute \src "libresoc.v:119572.18-119572.131" + wire $eq$libresoc.v:119572$4530_Y + attribute \src "libresoc.v:119578.17-119578.130" + wire $eq$libresoc.v:119578$4536_Y + attribute \src "libresoc.v:119556.18-119556.110" + wire $not$libresoc.v:119556$4514_Y + attribute \src "libresoc.v:119574.18-119574.110" + wire $not$libresoc.v:119574$4532_Y + attribute \src "libresoc.v:119560.18-119560.110" + wire $or$libresoc.v:119560$4518_Y + attribute \src "libresoc.v:119563.18-119563.110" + wire $or$libresoc.v:119563$4521_Y + attribute \src "libresoc.v:119566.18-119566.110" + wire $or$libresoc.v:119566$4524_Y + attribute \src "libresoc.v:119568.18-119568.110" + wire $or$libresoc.v:119568$4526_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 18 \ALU__data_len @@ -184916,22 +186316,10 @@ module \dec_ALU attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_ALU_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_ALU_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 \dec_ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \dec_ALU_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_ALU_OE @@ -184947,17 +186335,6 @@ module \dec_ALU wire width 10 \dec_ALU_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \dec_ALU_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 \dec_ALU_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -185116,13 +186493,7 @@ module \dec_ALU wire \dec_ALU_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \dec_ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -185130,7 +186501,7 @@ module \dec_ALU attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire width 3 \dec_ai_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -185151,36 +186522,8 @@ module \dec_ALU attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 \dec_cr_out_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -185189,7 +186532,7 @@ module \dec_ALU attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -185201,64 +186544,112 @@ module \dec_ALU attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:118587.7-118587.15" + attribute \src "libresoc.v:119130.7-119130.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $and $and$libresoc.v:119043$4465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:119555$4513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$6 - connect \B \$20 - connect \Y $and$libresoc.v:119043$4465_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:119555$4513_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:119037$4459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:119557$4515 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010011 - connect \Y $eq$libresoc.v:119037$4459_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:119557$4515_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:119039$4461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:119570$4528 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'1011010000 - connect \Y $eq$libresoc.v:119039$4461_Y + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:119570$4528_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:119041$4463 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:119571$4529 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 6'110000 - connect \Y $eq$libresoc.v:119041$4463_Y + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:119571$4529_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - cell $eq $eq$libresoc.v:119044$4466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:119573$4531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:119573$4531_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:119575$4533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:119575$4533_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:119576$4534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:119576$4534_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:119577$4535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:119577$4535_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" + cell $eq $eq$libresoc.v:119558$4516 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -185266,10 +186657,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:119044$4466_Y + connect \Y $eq$libresoc.v:119558$4516_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $eq $eq$libresoc.v:119045$4467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $eq $eq$libresoc.v:119559$4517 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -185277,74 +186668,161 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:119045$4467_Y + connect \Y $eq$libresoc.v:119559$4517_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:119047$4469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:119561$4519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:119561$4519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:119562$4520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:119562$4520_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:119564$4522 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr - connect \B 10'0000010010 - connect \Y $eq$libresoc.v:119047$4469_Y + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:119564$4522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:119565$4523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:119565$4523_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:119038$4460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $eq $eq$libresoc.v:119567$4525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:119567$4525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:119569$4527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:119569$4527_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:119572$4530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:119572$4530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:119578$4536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:119578$4536_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:119556$4514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:119556$4514_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:119574$4532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:119574$4532_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $or $or$libresoc.v:119560$4518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$8 - connect \B \$10 - connect \Y $or$libresoc.v:119038$4460_Y + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:119560$4518_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:119040$4462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:119563$4521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$12 - connect \B \$14 - connect \Y $or$libresoc.v:119040$4462_Y + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:119563$4521_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:119042$4464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:119566$4524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$16 - connect \B \$18 - connect \Y $or$libresoc.v:119042$4464_Y + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:119566$4524_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $or $or$libresoc.v:119046$4468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $or $or$libresoc.v:119568$4526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$2 - connect \B \$4 - connect \Y $or$libresoc.v:119046$4468_Y + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:119568$4526_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:119048.7-119086.4" + attribute \src "libresoc.v:119579.7-119607.4" cell \dec \dec - connect \ALU_BA \dec_ALU_BA - connect \ALU_BB \dec_ALU_BB - connect \ALU_BC \dec_ALU_BC connect \ALU_BD \dec_ALU_BD - connect \ALU_BI \dec_ALU_BI - connect \ALU_BT \dec_ALU_BT connect \ALU_DS \dec_ALU_DS - connect \ALU_FXM \dec_ALU_FXM connect \ALU_LI \dec_ALU_LI connect \ALU_OE \dec_ALU_OE connect \ALU_RA \dec_ALU_RA @@ -185353,7 +186831,6 @@ module \dec_ALU connect \ALU_SI \dec_ALU_SI connect \ALU_SPR \dec_ALU_SPR connect \ALU_UI \dec_ALU_UI - connect \ALU_cr_in \dec_ALU_cr_in connect \ALU_cr_out \dec_ALU_cr_out connect \ALU_cry_in \dec_ALU_cry_in connect \ALU_cry_out \dec_ALU_cry_out @@ -185368,22 +186845,19 @@ module \dec_ALU connect \ALU_rc_sel \dec_ALU_rc_sel connect \ALU_sgn \dec_ALU_sgn connect \ALU_sh \dec_ALU_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119087.10-119091.4" + attribute \src "libresoc.v:119608.10-119612.4" cell \dec_ai \dec_ai connect \ALU_RA \dec_ALU_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119092.10-119103.4" + attribute \src "libresoc.v:119613.10-119624.4" cell \dec_bi \dec_bi connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -185397,33 +186871,7 @@ module \dec_ALU connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119104.13-119115.4" - cell \dec_cr_in \dec_cr_in - connect \ALU_BA \dec_ALU_BA - connect \ALU_BB \dec_ALU_BB - connect \ALU_BC \dec_ALU_BC - connect \ALU_BI \dec_ALU_BI - connect \ALU_BT \dec_ALU_BT - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_internal_op \dec_ALU_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:119116.14-119125.4" - cell \dec_cr_out \dec_cr_out - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_internal_op \dec_ALU_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:119126.10-119132.4" + attribute \src "libresoc.v:119625.10-119631.4" cell \dec_oe \dec_oe connect \ALU_OE \dec_ALU_OE connect \ALU_internal_op \dec_ALU_internal_op @@ -185432,37 +186880,95 @@ module \dec_ALU connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119133.10-119138.4" + attribute \src "libresoc.v:119632.10-119637.4" cell \dec_rc \dec_rc connect \ALU_Rc \dec_ALU_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:118587.7-118587.20" - process $proc$libresoc.v:118587$4471 + attribute \src "libresoc.v:119130.7-119130.20" + process $proc$libresoc.v:119130$4540 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119139.3-119150.6" - process $proc$libresoc.v:119139$4470 + attribute \src "libresoc.v:119638.3-119652.6" + process $proc$libresoc.v:119638$4537 assign { } { } - assign $0\ALU__fn_unit[12:0] $1\ALU__fn_unit[12:0] - attribute \src "libresoc.v:119140.5-119140.29" + assign { } { } + assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0] + attribute \src "libresoc.v:119639.5-119639.29" switch \initial - attribute \src "libresoc.v:119140.9-119140.17" + attribute \src "libresoc.v:119639.9-119639.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:838" + switch \dec_ALU_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 3'001 , 3'101 + assign { } { } + assign $1\ALU__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" + case 3'010 , 3'011 + assign { } { } + assign $1\ALU__write_cr0[0:0] 1'1 + case + assign $1\ALU__write_cr0[0:0] 1'0 + end + sync always + update \ALU__write_cr0 $0\ALU__write_cr0[0:0] + end + attribute \src "libresoc.v:119653.3-119665.6" + process $proc$libresoc.v:119653$4538 + assign { } { } + assign { } { } + assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0] + attribute \src "libresoc.v:119654.5-119654.29" + switch \initial + attribute \src "libresoc.v:119654.9-119654.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\ALU__fn_unit[12:0] 13'0100000000000 + assign $1\ALU__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ALU__insn_type[6:0] 7'0000000 + case + assign $1\ALU__insn_type[6:0] \dec_ALU_internal_op + end + sync always + update \ALU__insn_type $0\ALU__insn_type[6:0] + end + attribute \src "libresoc.v:119666.3-119680.6" + process $proc$libresoc.v:119666$4539 + assign { } { } + assign $0\ALU__fn_unit[12:0] $1\ALU__fn_unit[12:0] + attribute \src "libresoc.v:119667.5-119667.29" + switch \initial + attribute \src "libresoc.v:119667.9-119667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ALU__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ALU__fn_unit[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -185471,17 +186977,30 @@ module \dec_ALU sync always update \ALU__fn_unit $0\ALU__fn_unit[12:0] end - connect \$10 $eq$libresoc.v:119037$4459_Y - connect \$12 $or$libresoc.v:119038$4460_Y - connect \$14 $eq$libresoc.v:119039$4461_Y - connect \$16 $or$libresoc.v:119040$4462_Y - connect \$18 $eq$libresoc.v:119041$4463_Y - connect \$20 $or$libresoc.v:119042$4464_Y - connect \$22 $and$libresoc.v:119043$4465_Y - connect \$2 $eq$libresoc.v:119044$4466_Y - connect \$4 $eq$libresoc.v:119045$4467_Y - connect \$6 $or$libresoc.v:119046$4468_Y - connect \$8 $eq$libresoc.v:119047$4469_Y + connect \$10 $and$libresoc.v:119555$4513_Y + connect \$12 $not$libresoc.v:119556$4514_Y + connect \$14 $and$libresoc.v:119557$4515_Y + connect \$16 $eq$libresoc.v:119558$4516_Y + connect \$18 $eq$libresoc.v:119559$4517_Y + connect \$20 $or$libresoc.v:119560$4518_Y + connect \$22 $eq$libresoc.v:119561$4519_Y + connect \$24 $eq$libresoc.v:119562$4520_Y + connect \$26 $or$libresoc.v:119563$4521_Y + connect \$28 $eq$libresoc.v:119564$4522_Y + connect \$2 $eq$libresoc.v:119565$4523_Y + connect \$30 $or$libresoc.v:119566$4524_Y + connect \$32 $eq$libresoc.v:119567$4525_Y + connect \$34 $or$libresoc.v:119568$4526_Y + connect \$36 $eq$libresoc.v:119569$4527_Y + connect \$38 $and$libresoc.v:119570$4528_Y + connect \$40 $and$libresoc.v:119571$4529_Y + connect \$42 $eq$libresoc.v:119572$4530_Y + connect \$44 $and$libresoc.v:119573$4531_Y + connect \$46 $not$libresoc.v:119574$4532_Y + connect \$48 $and$libresoc.v:119575$4533_Y + connect \$4 $and$libresoc.v:119576$4534_Y + connect \$6 $and$libresoc.v:119577$4535_Y + connect \$8 $eq$libresoc.v:119578$4536_Y connect \ALU__is_signed \dec_ALU_sgn connect \ALU__is_32bit \dec_ALU_is_32b connect \ALU__output_carry \dec_ALU_cry_out @@ -185489,84 +187008,135 @@ module \dec_ALU connect \ALU__invert_out \dec_ALU_inv_out connect \ALU__invert_in \dec_ALU_inv_a connect \ALU__data_len \dec_ALU_ldst_len - connect \ALU__write_cr0 \dec_cr_out_cr_bitfield_ok connect { \ALU__oe__ok \ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \ALU__rc__ok \ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \ALU__imm_data__ok \ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_ALU_in2_sel connect \ALU__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_ALU_in1_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 connect \spr { \dec_ALU_SPR [4:0] \dec_ALU_SPR [9:5] } - connect \ALU__insn_type \dec_ALU_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_ALU_cr_out - connect \dec_cr_in_sel_in \dec_ALU_cr_in connect \dec_oe_sel_in \dec_ALU_rc_sel connect \dec_rc_sel_in \dec_ALU_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \ALU__insn \dec_opcode_in end -attribute \src "libresoc.v:119181.1-119690.10" +attribute \src "libresoc.v:119706.1-120182.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" attribute \generator "nMigen" module \dec_BRANCH - attribute \src "libresoc.v:119652.3-119663.6" + attribute \src "libresoc.v:120132.3-120146.6" wire width 13 $0\BRANCH__fn_unit[12:0] - attribute \src "libresoc.v:119664.3-119673.6" + attribute \src "libresoc.v:120157.3-120169.6" + wire width 7 $0\BRANCH__insn_type[6:0] + attribute \src "libresoc.v:120147.3-120156.6" wire $0\BRANCH__lk[0:0] - attribute \src "libresoc.v:119182.7-119182.20" + attribute \src "libresoc.v:119707.7-119707.20" wire $0\initial[0:0] - attribute \src "libresoc.v:119652.3-119663.6" + attribute \src "libresoc.v:120132.3-120146.6" wire width 13 $1\BRANCH__fn_unit[12:0] - attribute \src "libresoc.v:119664.3-119673.6" + attribute \src "libresoc.v:120157.3-120169.6" + wire width 7 $1\BRANCH__insn_type[6:0] + attribute \src "libresoc.v:120147.3-120156.6" wire $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:119571.18-119571.109" - wire $and$libresoc.v:119571$4478_Y - attribute \src "libresoc.v:119565.18-119565.112" - wire $eq$libresoc.v:119565$4472_Y - attribute \src "libresoc.v:119567.18-119567.112" - wire $eq$libresoc.v:119567$4474_Y - attribute \src "libresoc.v:119569.18-119569.110" - wire $eq$libresoc.v:119569$4476_Y - attribute \src "libresoc.v:119572.17-119572.128" - wire $eq$libresoc.v:119572$4479_Y - attribute \src "libresoc.v:119573.17-119573.128" - wire $eq$libresoc.v:119573$4480_Y - attribute \src "libresoc.v:119575.17-119575.111" - wire $eq$libresoc.v:119575$4482_Y - attribute \src "libresoc.v:119566.18-119566.109" - wire $or$libresoc.v:119566$4473_Y - attribute \src "libresoc.v:119568.18-119568.110" - wire $or$libresoc.v:119568$4475_Y - attribute \src "libresoc.v:119570.18-119570.110" - wire $or$libresoc.v:119570$4477_Y - attribute \src "libresoc.v:119574.17-119574.107" - wire $or$libresoc.v:119574$4481_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "libresoc.v:120064.18-120064.113" + wire $and$libresoc.v:120064$4541_Y + attribute \src "libresoc.v:120066.18-120066.110" + wire $and$libresoc.v:120066$4543_Y + attribute \src "libresoc.v:120079.18-120079.114" + wire $and$libresoc.v:120079$4556_Y + attribute \src "libresoc.v:120080.18-120080.116" + wire $and$libresoc.v:120080$4557_Y + attribute \src "libresoc.v:120082.18-120082.114" + wire $and$libresoc.v:120082$4559_Y + attribute \src "libresoc.v:120084.18-120084.110" + wire $and$libresoc.v:120084$4561_Y + attribute \src "libresoc.v:120085.17-120085.112" + wire $and$libresoc.v:120085$4562_Y + attribute \src "libresoc.v:120086.17-120086.114" + wire $and$libresoc.v:120086$4563_Y + attribute \src "libresoc.v:120067.18-120067.129" + wire $eq$libresoc.v:120067$4544_Y + attribute \src "libresoc.v:120068.18-120068.129" + wire $eq$libresoc.v:120068$4545_Y + attribute \src "libresoc.v:120070.18-120070.110" + wire $eq$libresoc.v:120070$4547_Y + attribute \src "libresoc.v:120071.18-120071.110" + wire $eq$libresoc.v:120071$4548_Y + attribute \src "libresoc.v:120073.18-120073.112" + wire $eq$libresoc.v:120073$4550_Y + attribute \src "libresoc.v:120074.17-120074.133" + wire $eq$libresoc.v:120074$4551_Y + attribute \src "libresoc.v:120076.18-120076.110" + wire $eq$libresoc.v:120076$4553_Y + attribute \src "libresoc.v:120078.18-120078.134" + wire $eq$libresoc.v:120078$4555_Y + attribute \src "libresoc.v:120081.18-120081.134" + wire $eq$libresoc.v:120081$4558_Y + attribute \src "libresoc.v:120087.17-120087.133" + wire $eq$libresoc.v:120087$4564_Y + attribute \src "libresoc.v:120065.18-120065.110" + wire $not$libresoc.v:120065$4542_Y + attribute \src "libresoc.v:120083.18-120083.110" + wire $not$libresoc.v:120083$4560_Y + attribute \src "libresoc.v:120069.18-120069.110" + wire $or$libresoc.v:120069$4546_Y + attribute \src "libresoc.v:120072.18-120072.110" + wire $or$libresoc.v:120072$4549_Y + attribute \src "libresoc.v:120075.18-120075.110" + wire $or$libresoc.v:120075$4552_Y + attribute \src "libresoc.v:120077.18-120077.110" + wire $or$libresoc.v:120077$4554_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 output 3 \BRANCH__cia @@ -185674,25 +187244,13 @@ module \dec_BRANCH wire output 9 \BRANCH__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 2 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 input 11 \core_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_BRANCH_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_BRANCH_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 \dec_BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \dec_BRANCH_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_BRANCH_LK @@ -185708,17 +187266,6 @@ module \dec_BRANCH wire width 10 \dec_BRANCH_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \dec_BRANCH_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 \dec_BRANCH_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -185849,12 +187396,6 @@ module \dec_BRANCH wire width 2 \dec_BRANCH_rc_sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \dec_BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -185874,106 +187415,126 @@ module \dec_BRANCH attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:119182.7-119182.15" + attribute \src "libresoc.v:119707.7-119707.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 1 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $and $and$libresoc.v:119571$4478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:120064$4541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$6 - connect \B \$20 - connect \Y $and$libresoc.v:119571$4478_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:120064$4541_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:119565$4472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:120066$4543 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010011 - connect \Y $eq$libresoc.v:119565$4472_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:120066$4543_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:119567$4474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:120079$4556 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'1011010000 - connect \Y $eq$libresoc.v:119567$4474_Y + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:120079$4556_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:119569$4476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:120080$4557 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 6'110000 - connect \Y $eq$libresoc.v:119569$4476_Y + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:120080$4557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:120082$4559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:120082$4559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:120084$4561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:120084$4561_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - cell $eq $eq$libresoc.v:119572$4479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:120085$4562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:120085$4562_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:120086$4563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:120086$4563_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" + cell $eq $eq$libresoc.v:120067$4544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -185981,10 +187542,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:119572$4479_Y + connect \Y $eq$libresoc.v:120067$4544_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $eq $eq$libresoc.v:119573$4480 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $eq $eq$libresoc.v:120068$4545 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -185992,74 +187553,161 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:119573$4480_Y + connect \Y $eq$libresoc.v:120068$4545_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:119575$4482 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:120070$4547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:120070$4547_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:120071$4548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:120071$4548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:120073$4550 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr - connect \B 10'0000010010 - connect \Y $eq$libresoc.v:119575$4482_Y + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:120073$4550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:120074$4551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:120074$4551_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $eq $eq$libresoc.v:120076$4553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:120076$4553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:120078$4555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:120078$4555_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:120081$4558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:120081$4558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:120087$4564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:120087$4564_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:120065$4542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:120065$4542_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:120083$4560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:120083$4560_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:119566$4473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $or $or$libresoc.v:120069$4546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$8 - connect \B \$10 - connect \Y $or$libresoc.v:119566$4473_Y + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:120069$4546_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:119568$4475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:120072$4549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$12 - connect \B \$14 - connect \Y $or$libresoc.v:119568$4475_Y + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:120072$4549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:119570$4477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:120075$4552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$16 - connect \B \$18 - connect \Y $or$libresoc.v:119570$4477_Y + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:120075$4552_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $or $or$libresoc.v:119574$4481 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $or $or$libresoc.v:120077$4554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$2 - connect \B \$4 - connect \Y $or$libresoc.v:119574$4481_Y + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:120077$4554_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:119576.13-119608.4" - cell \dec$146 \dec - connect \BRANCH_BA \dec_BRANCH_BA - connect \BRANCH_BB \dec_BRANCH_BB - connect \BRANCH_BC \dec_BRANCH_BC + attribute \src "libresoc.v:120088.13-120110.4" + cell \dec$141 \dec connect \BRANCH_BD \dec_BRANCH_BD - connect \BRANCH_BI \dec_BRANCH_BI - connect \BRANCH_BT \dec_BRANCH_BT connect \BRANCH_DS \dec_BRANCH_DS - connect \BRANCH_FXM \dec_BRANCH_FXM connect \BRANCH_LI \dec_BRANCH_LI connect \BRANCH_LK \dec_BRANCH_LK connect \BRANCH_OE \dec_BRANCH_OE @@ -186068,7 +187716,6 @@ module \dec_BRANCH connect \BRANCH_SI \dec_BRANCH_SI connect \BRANCH_SPR \dec_BRANCH_SPR connect \BRANCH_UI \dec_BRANCH_UI - connect \BRANCH_cr_in \dec_BRANCH_cr_in connect \BRANCH_cr_out \dec_BRANCH_cr_out connect \BRANCH_function_unit \dec_BRANCH_function_unit connect \BRANCH_in2_sel \dec_BRANCH_in2_sel @@ -186077,16 +187724,13 @@ module \dec_BRANCH connect \BRANCH_lk \dec_BRANCH_lk connect \BRANCH_rc_sel \dec_BRANCH_rc_sel connect \BRANCH_sh \dec_BRANCH_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119609.16-119620.4" - cell \dec_bi$153 \dec_bi + attribute \src "libresoc.v:120111.16-120122.4" + cell \dec_bi$144 \dec_bi connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS connect \BRANCH_LI \dec_BRANCH_LI @@ -186099,68 +187743,46 @@ module \dec_BRANCH connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119621.19-119632.4" - cell \dec_cr_in$149 \dec_cr_in - connect \BRANCH_BA \dec_BRANCH_BA - connect \BRANCH_BB \dec_BRANCH_BB - connect \BRANCH_BC \dec_BRANCH_BC - connect \BRANCH_BI \dec_BRANCH_BI - connect \BRANCH_BT \dec_BRANCH_BT - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:119633.20-119641.4" - cell \dec_cr_out$151 \dec_cr_out - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:119642.16-119646.4" - cell \dec_oe$148 \dec_oe + attribute \src "libresoc.v:120123.16-120127.4" + cell \dec_oe$143 \dec_oe connect \BRANCH_OE \dec_BRANCH_OE connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:119647.16-119651.4" - cell \dec_rc$147 \dec_rc + attribute \src "libresoc.v:120128.16-120131.4" + cell \dec_rc$142 \dec_rc connect \BRANCH_Rc \dec_BRANCH_Rc - connect \rc \dec_rc_rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:119182.7-119182.20" - process $proc$libresoc.v:119182$4485 + attribute \src "libresoc.v:119707.7-119707.20" + process $proc$libresoc.v:119707$4568 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119652.3-119663.6" - process $proc$libresoc.v:119652$4483 + attribute \src "libresoc.v:120132.3-120146.6" + process $proc$libresoc.v:120132$4565 assign { } { } assign $0\BRANCH__fn_unit[12:0] $1\BRANCH__fn_unit[12:0] - attribute \src "libresoc.v:119653.5-119653.29" + attribute \src "libresoc.v:120133.5-120133.29" switch \initial - attribute \src "libresoc.v:119653.9-119653.17" + attribute \src "libresoc.v:120133.9-120133.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$48 \$40 } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\BRANCH__fn_unit[12:0] 13'0100000000000 + assign $1\BRANCH__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\BRANCH__fn_unit[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -186169,18 +187791,18 @@ module \dec_BRANCH sync always update \BRANCH__fn_unit $0\BRANCH__fn_unit[12:0] end - attribute \src "libresoc.v:119664.3-119673.6" - process $proc$libresoc.v:119664$4484 + attribute \src "libresoc.v:120147.3-120156.6" + process $proc$libresoc.v:120147$4566 assign { } { } assign { } { } assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:119665.5-119665.29" + attribute \src "libresoc.v:120148.5-120148.29" switch \initial - attribute \src "libresoc.v:119665.9-119665.17" + attribute \src "libresoc.v:120148.9-120148.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:957" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:857" switch \dec_BRANCH_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -186192,88 +187814,180 @@ module \dec_BRANCH sync always update \BRANCH__lk $0\BRANCH__lk[0:0] end - connect \$10 $eq$libresoc.v:119565$4472_Y - connect \$12 $or$libresoc.v:119566$4473_Y - connect \$14 $eq$libresoc.v:119567$4474_Y - connect \$16 $or$libresoc.v:119568$4475_Y - connect \$18 $eq$libresoc.v:119569$4476_Y - connect \$20 $or$libresoc.v:119570$4477_Y - connect \$22 $and$libresoc.v:119571$4478_Y - connect \$2 $eq$libresoc.v:119572$4479_Y - connect \$4 $eq$libresoc.v:119573$4480_Y - connect \$6 $or$libresoc.v:119574$4481_Y - connect \$8 $eq$libresoc.v:119575$4482_Y + attribute \src "libresoc.v:120157.3-120169.6" + process $proc$libresoc.v:120157$4567 + assign { } { } + assign { } { } + assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0] + attribute \src "libresoc.v:120158.5-120158.29" + switch \initial + attribute \src "libresoc.v:120158.9-120158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\BRANCH__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\BRANCH__insn_type[6:0] 7'0000000 + case + assign $1\BRANCH__insn_type[6:0] \dec_BRANCH_internal_op + end + sync always + update \BRANCH__insn_type $0\BRANCH__insn_type[6:0] + end + connect \$10 $and$libresoc.v:120064$4541_Y + connect \$12 $not$libresoc.v:120065$4542_Y + connect \$14 $and$libresoc.v:120066$4543_Y + connect \$16 $eq$libresoc.v:120067$4544_Y + connect \$18 $eq$libresoc.v:120068$4545_Y + connect \$20 $or$libresoc.v:120069$4546_Y + connect \$22 $eq$libresoc.v:120070$4547_Y + connect \$24 $eq$libresoc.v:120071$4548_Y + connect \$26 $or$libresoc.v:120072$4549_Y + connect \$28 $eq$libresoc.v:120073$4550_Y + connect \$2 $eq$libresoc.v:120074$4551_Y + connect \$30 $or$libresoc.v:120075$4552_Y + connect \$32 $eq$libresoc.v:120076$4553_Y + connect \$34 $or$libresoc.v:120077$4554_Y + connect \$36 $eq$libresoc.v:120078$4555_Y + connect \$38 $and$libresoc.v:120079$4556_Y + connect \$40 $and$libresoc.v:120080$4557_Y + connect \$42 $eq$libresoc.v:120081$4558_Y + connect \$44 $and$libresoc.v:120082$4559_Y + connect \$46 $not$libresoc.v:120083$4560_Y + connect \$48 $and$libresoc.v:120084$4561_Y + connect \$4 $and$libresoc.v:120085$4562_Y + connect \$6 $and$libresoc.v:120086$4563_Y + connect \$8 $eq$libresoc.v:120087$4564_Y connect \BRANCH__is_32bit \dec_BRANCH_is_32b connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_BRANCH_in2_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 connect \spr { \dec_BRANCH_SPR [4:0] \dec_BRANCH_SPR [9:5] } - connect \BRANCH__insn_type \dec_BRANCH_internal_op connect \BRANCH__cia \core_pc - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_BRANCH_cr_out - connect \dec_cr_in_sel_in \dec_BRANCH_cr_in connect \dec_oe_sel_in \dec_BRANCH_rc_sel connect \dec_rc_sel_in \dec_BRANCH_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \BRANCH__insn \dec_opcode_in end -attribute \src "libresoc.v:119694.1-120095.10" +attribute \src "libresoc.v:120186.1-120554.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" attribute \generator "nMigen" module \dec_CR - attribute \src "libresoc.v:120071.3-120082.6" + attribute \src "libresoc.v:120531.3-120545.6" wire width 13 $0\CR__fn_unit[12:0] - attribute \src "libresoc.v:119695.7-119695.20" + attribute \src "libresoc.v:120518.3-120530.6" + wire width 7 $0\CR__insn_type[6:0] + attribute \src "libresoc.v:120187.7-120187.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120071.3-120082.6" + attribute \src "libresoc.v:120531.3-120545.6" wire width 13 $1\CR__fn_unit[12:0] - attribute \src "libresoc.v:120013.18-120013.109" - wire $and$libresoc.v:120013$4492_Y - attribute \src "libresoc.v:120007.18-120007.112" - wire $eq$libresoc.v:120007$4486_Y - attribute \src "libresoc.v:120009.18-120009.112" - wire $eq$libresoc.v:120009$4488_Y - attribute \src "libresoc.v:120011.18-120011.110" - wire $eq$libresoc.v:120011$4490_Y - attribute \src "libresoc.v:120014.17-120014.124" - wire $eq$libresoc.v:120014$4493_Y - attribute \src "libresoc.v:120015.17-120015.124" - wire $eq$libresoc.v:120015$4494_Y - attribute \src "libresoc.v:120017.17-120017.111" - wire $eq$libresoc.v:120017$4496_Y - attribute \src "libresoc.v:120008.18-120008.109" - wire $or$libresoc.v:120008$4487_Y - attribute \src "libresoc.v:120010.18-120010.110" - wire $or$libresoc.v:120010$4489_Y - attribute \src "libresoc.v:120012.18-120012.110" - wire $or$libresoc.v:120012$4491_Y - attribute \src "libresoc.v:120016.17-120016.107" - wire $or$libresoc.v:120016$4495_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "libresoc.v:120518.3-120530.6" + wire width 7 $1\CR__insn_type[6:0] + attribute \src "libresoc.v:120473.18-120473.113" + wire $and$libresoc.v:120473$4569_Y + attribute \src "libresoc.v:120475.18-120475.110" + wire $and$libresoc.v:120475$4571_Y + attribute \src "libresoc.v:120488.18-120488.114" + wire $and$libresoc.v:120488$4584_Y + attribute \src "libresoc.v:120489.18-120489.116" + wire $and$libresoc.v:120489$4585_Y + attribute \src "libresoc.v:120491.18-120491.114" + wire $and$libresoc.v:120491$4587_Y + attribute \src "libresoc.v:120493.18-120493.110" + wire $and$libresoc.v:120493$4589_Y + attribute \src "libresoc.v:120494.17-120494.112" + wire $and$libresoc.v:120494$4590_Y + attribute \src "libresoc.v:120495.17-120495.114" + wire $and$libresoc.v:120495$4591_Y + attribute \src "libresoc.v:120476.18-120476.125" + wire $eq$libresoc.v:120476$4572_Y + attribute \src "libresoc.v:120477.18-120477.125" + wire $eq$libresoc.v:120477$4573_Y + attribute \src "libresoc.v:120479.18-120479.110" + wire $eq$libresoc.v:120479$4575_Y + attribute \src "libresoc.v:120480.18-120480.110" + wire $eq$libresoc.v:120480$4576_Y + attribute \src "libresoc.v:120482.18-120482.112" + wire $eq$libresoc.v:120482$4578_Y + attribute \src "libresoc.v:120483.17-120483.129" + wire $eq$libresoc.v:120483$4579_Y + attribute \src "libresoc.v:120485.18-120485.110" + wire $eq$libresoc.v:120485$4581_Y + attribute \src "libresoc.v:120487.18-120487.130" + wire $eq$libresoc.v:120487$4583_Y + attribute \src "libresoc.v:120490.18-120490.130" + wire $eq$libresoc.v:120490$4586_Y + attribute \src "libresoc.v:120496.17-120496.129" + wire $eq$libresoc.v:120496$4592_Y + attribute \src "libresoc.v:120474.18-120474.110" + wire $not$libresoc.v:120474$4570_Y + attribute \src "libresoc.v:120492.18-120492.110" + wire $not$libresoc.v:120492$4588_Y + attribute \src "libresoc.v:120478.18-120478.110" + wire $or$libresoc.v:120478$4574_Y + attribute \src "libresoc.v:120481.18-120481.110" + wire $or$libresoc.v:120481$4577_Y + attribute \src "libresoc.v:120484.18-120484.110" + wire $or$libresoc.v:120484$4580_Y + attribute \src "libresoc.v:120486.18-120486.110" + wire $or$libresoc.v:120486$4582_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" @@ -186372,34 +188086,11 @@ module \dec_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 \dec_CR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_CR_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_CR_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \dec_CR_SPR - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 \dec_CR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -186507,110 +188198,124 @@ module \dec_CR attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec_CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:119695.7-119695.15" + attribute \src "libresoc.v:120187.7-120187.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 5 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $and $and$libresoc.v:120013$4492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:120473$4569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$6 - connect \B \$20 - connect \Y $and$libresoc.v:120013$4492_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:120473$4569_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:120007$4486 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:120475$4571 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010011 - connect \Y $eq$libresoc.v:120007$4486_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:120475$4571_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:120009$4488 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:120488$4584 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'1011010000 - connect \Y $eq$libresoc.v:120009$4488_Y + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:120488$4584_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:120011$4490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:120489$4585 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 6'110000 - connect \Y $eq$libresoc.v:120011$4490_Y + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:120489$4585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:120491$4587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:120491$4587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:120493$4589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:120493$4589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:120494$4590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:120494$4590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:120495$4591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:120495$4591_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - cell $eq $eq$libresoc.v:120014$4493 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" + cell $eq $eq$libresoc.v:120476$4572 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -186618,10 +188323,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:120014$4493_Y + connect \Y $eq$libresoc.v:120476$4572_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $eq $eq$libresoc.v:120015$4494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $eq $eq$libresoc.v:120477$4573 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -186629,150 +188334,238 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:120015$4494_Y + connect \Y $eq$libresoc.v:120477$4573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:120479$4575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:120479$4575_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:120480$4576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:120480$4576_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:120017$4496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:120482$4578 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr - connect \B 10'0000010010 - connect \Y $eq$libresoc.v:120017$4496_Y + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:120482$4578_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:120483$4579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_CR_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:120483$4579_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $eq $eq$libresoc.v:120485$4581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:120485$4581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:120487$4583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_CR_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:120487$4583_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:120490$4586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_CR_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:120490$4586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:120496$4592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_CR_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:120496$4592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:120474$4570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:120474$4570_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:120008$4487 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:120492$4588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:120492$4588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $or $or$libresoc.v:120478$4574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$8 - connect \B \$10 - connect \Y $or$libresoc.v:120008$4487_Y + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:120478$4574_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:120010$4489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:120481$4577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$12 - connect \B \$14 - connect \Y $or$libresoc.v:120010$4489_Y + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:120481$4577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:120012$4491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:120484$4580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$16 - connect \B \$18 - connect \Y $or$libresoc.v:120012$4491_Y + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:120484$4580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $or $or$libresoc.v:120016$4495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $or $or$libresoc.v:120486$4582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$2 - connect \B \$4 - connect \Y $or$libresoc.v:120016$4495_Y + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:120486$4582_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:120018.13-120039.4" - cell \dec$139 \dec - connect \CR_BA \dec_CR_BA - connect \CR_BB \dec_CR_BB - connect \CR_BC \dec_CR_BC - connect \CR_BI \dec_CR_BI - connect \CR_BT \dec_CR_BT - connect \CR_FXM \dec_CR_FXM + attribute \src "libresoc.v:120497.13-120508.4" + cell \dec$138 \dec connect \CR_OE \dec_CR_OE connect \CR_Rc \dec_CR_Rc connect \CR_SPR \dec_CR_SPR - connect \CR_cr_in \dec_CR_cr_in connect \CR_cr_out \dec_CR_cr_out connect \CR_function_unit \dec_CR_function_unit connect \CR_internal_op \dec_CR_internal_op connect \CR_rc_sel \dec_CR_rc_sel - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120040.19-120051.4" - cell \dec_cr_in$142 \dec_cr_in - connect \CR_BA \dec_CR_BA - connect \CR_BB \dec_CR_BB - connect \CR_BC \dec_CR_BC - connect \CR_BI \dec_CR_BI - connect \CR_BT \dec_CR_BT - connect \CR_FXM \dec_CR_FXM - connect \CR_internal_op \dec_CR_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:120052.20-120060.4" - cell \dec_cr_out$144 \dec_cr_out - connect \CR_FXM \dec_CR_FXM - connect \CR_internal_op \dec_CR_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:120061.16-120065.4" - cell \dec_oe$141 \dec_oe + attribute \src "libresoc.v:120509.16-120513.4" + cell \dec_oe$140 \dec_oe connect \CR_OE \dec_CR_OE connect \CR_internal_op \dec_CR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120066.16-120070.4" - cell \dec_rc$140 \dec_rc + attribute \src "libresoc.v:120514.16-120517.4" + cell \dec_rc$139 \dec_rc connect \CR_Rc \dec_CR_Rc - connect \rc \dec_rc_rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:119695.7-119695.20" - process $proc$libresoc.v:119695$4498 + attribute \src "libresoc.v:120187.7-120187.20" + process $proc$libresoc.v:120187$4595 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120071.3-120082.6" - process $proc$libresoc.v:120071$4497 + attribute \src "libresoc.v:120518.3-120530.6" + process $proc$libresoc.v:120518$4593 assign { } { } - assign $0\CR__fn_unit[12:0] $1\CR__fn_unit[12:0] - attribute \src "libresoc.v:120072.5-120072.29" + assign { } { } + assign $0\CR__insn_type[6:0] $1\CR__insn_type[6:0] + attribute \src "libresoc.v:120519.5-120519.29" switch \initial - attribute \src "libresoc.v:120072.9-120072.17" + attribute \src "libresoc.v:120519.9-120519.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\CR__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\CR__insn_type[6:0] 7'0000000 + case + assign $1\CR__insn_type[6:0] \dec_CR_internal_op + end + sync always + update \CR__insn_type $0\CR__insn_type[6:0] + end + attribute \src "libresoc.v:120531.3-120545.6" + process $proc$libresoc.v:120531$4594 + assign { } { } + assign $0\CR__fn_unit[12:0] $1\CR__fn_unit[12:0] + attribute \src "libresoc.v:120532.5-120532.29" + switch \initial + attribute \src "libresoc.v:120532.9-120532.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\CR__fn_unit[12:0] 13'0100000000000 + assign $1\CR__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\CR__fn_unit[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -186781,84 +188574,153 @@ module \dec_CR sync always update \CR__fn_unit $0\CR__fn_unit[12:0] end - connect \$10 $eq$libresoc.v:120007$4486_Y - connect \$12 $or$libresoc.v:120008$4487_Y - connect \$14 $eq$libresoc.v:120009$4488_Y - connect \$16 $or$libresoc.v:120010$4489_Y - connect \$18 $eq$libresoc.v:120011$4490_Y - connect \$20 $or$libresoc.v:120012$4491_Y - connect \$22 $and$libresoc.v:120013$4492_Y - connect \$2 $eq$libresoc.v:120014$4493_Y - connect \$4 $eq$libresoc.v:120015$4494_Y - connect \$6 $or$libresoc.v:120016$4495_Y - connect \$8 $eq$libresoc.v:120017$4496_Y + connect \$10 $and$libresoc.v:120473$4569_Y + connect \$12 $not$libresoc.v:120474$4570_Y + connect \$14 $and$libresoc.v:120475$4571_Y + connect \$16 $eq$libresoc.v:120476$4572_Y + connect \$18 $eq$libresoc.v:120477$4573_Y + connect \$20 $or$libresoc.v:120478$4574_Y + connect \$22 $eq$libresoc.v:120479$4575_Y + connect \$24 $eq$libresoc.v:120480$4576_Y + connect \$26 $or$libresoc.v:120481$4577_Y + connect \$28 $eq$libresoc.v:120482$4578_Y + connect \$2 $eq$libresoc.v:120483$4579_Y + connect \$30 $or$libresoc.v:120484$4580_Y + connect \$32 $eq$libresoc.v:120485$4581_Y + connect \$34 $or$libresoc.v:120486$4582_Y + connect \$36 $eq$libresoc.v:120487$4583_Y + connect \$38 $and$libresoc.v:120488$4584_Y + connect \$40 $and$libresoc.v:120489$4585_Y + connect \$42 $eq$libresoc.v:120490$4586_Y + connect \$44 $and$libresoc.v:120491$4587_Y + connect \$46 $not$libresoc.v:120492$4588_Y + connect \$48 $and$libresoc.v:120493$4589_Y + connect \$4 $and$libresoc.v:120494$4590_Y + connect \$6 $and$libresoc.v:120495$4591_Y + connect \$8 $eq$libresoc.v:120496$4592_Y + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 connect \spr { \dec_CR_SPR [4:0] \dec_CR_SPR [9:5] } - connect \CR__insn_type \dec_CR_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_CR_cr_out - connect \dec_cr_in_sel_in \dec_CR_cr_in connect \dec_oe_sel_in \dec_CR_rc_sel connect \dec_rc_sel_in \dec_CR_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \CR__insn \dec_opcode_in end -attribute \src "libresoc.v:120099.1-120690.10" +attribute \src "libresoc.v:120558.1-121131.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV" attribute \generator "nMigen" module \dec_DIV - attribute \src "libresoc.v:120652.3-120663.6" + attribute \src "libresoc.v:121095.3-121109.6" wire width 13 $0\DIV__fn_unit[12:0] - attribute \src "libresoc.v:120100.7-120100.20" + attribute \src "libresoc.v:121082.3-121094.6" + wire width 7 $0\DIV__insn_type[6:0] + attribute \src "libresoc.v:121067.3-121081.6" + wire $0\DIV__write_cr0[0:0] + attribute \src "libresoc.v:120559.7-120559.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120652.3-120663.6" + attribute \src "libresoc.v:121095.3-121109.6" wire width 13 $1\DIV__fn_unit[12:0] - attribute \src "libresoc.v:120556.18-120556.109" - wire $and$libresoc.v:120556$4505_Y - attribute \src "libresoc.v:120550.18-120550.112" - wire $eq$libresoc.v:120550$4499_Y - attribute \src "libresoc.v:120552.18-120552.112" - wire $eq$libresoc.v:120552$4501_Y - attribute \src "libresoc.v:120554.18-120554.110" - wire $eq$libresoc.v:120554$4503_Y - attribute \src "libresoc.v:120557.17-120557.125" - wire $eq$libresoc.v:120557$4506_Y - attribute \src "libresoc.v:120558.17-120558.125" - wire $eq$libresoc.v:120558$4507_Y - attribute \src "libresoc.v:120560.17-120560.111" - wire $eq$libresoc.v:120560$4509_Y - attribute \src "libresoc.v:120551.18-120551.109" - wire $or$libresoc.v:120551$4500_Y - attribute \src "libresoc.v:120553.18-120553.110" - wire $or$libresoc.v:120553$4502_Y - attribute \src "libresoc.v:120555.18-120555.110" - wire $or$libresoc.v:120555$4504_Y - attribute \src "libresoc.v:120559.17-120559.107" - wire $or$libresoc.v:120559$4508_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "libresoc.v:121082.3-121094.6" + wire width 7 $1\DIV__insn_type[6:0] + attribute \src "libresoc.v:121067.3-121081.6" + wire $1\DIV__write_cr0[0:0] + attribute \src "libresoc.v:120984.18-120984.113" + wire $and$libresoc.v:120984$4596_Y + attribute \src "libresoc.v:120986.18-120986.110" + wire $and$libresoc.v:120986$4598_Y + attribute \src "libresoc.v:120999.18-120999.114" + wire $and$libresoc.v:120999$4611_Y + attribute \src "libresoc.v:121000.18-121000.116" + wire $and$libresoc.v:121000$4612_Y + attribute \src "libresoc.v:121002.18-121002.114" + wire $and$libresoc.v:121002$4614_Y + attribute \src "libresoc.v:121004.18-121004.110" + wire $and$libresoc.v:121004$4616_Y + attribute \src "libresoc.v:121005.17-121005.112" + wire $and$libresoc.v:121005$4617_Y + attribute \src "libresoc.v:121006.17-121006.114" + wire $and$libresoc.v:121006$4618_Y + attribute \src "libresoc.v:120987.18-120987.126" + wire $eq$libresoc.v:120987$4599_Y + attribute \src "libresoc.v:120988.18-120988.126" + wire $eq$libresoc.v:120988$4600_Y + attribute \src "libresoc.v:120990.18-120990.110" + wire $eq$libresoc.v:120990$4602_Y + attribute \src "libresoc.v:120991.18-120991.110" + wire $eq$libresoc.v:120991$4603_Y + attribute \src "libresoc.v:120993.18-120993.112" + wire $eq$libresoc.v:120993$4605_Y + attribute \src "libresoc.v:120994.17-120994.130" + wire $eq$libresoc.v:120994$4606_Y + attribute \src "libresoc.v:120996.18-120996.110" + wire $eq$libresoc.v:120996$4608_Y + attribute \src "libresoc.v:120998.18-120998.131" + wire $eq$libresoc.v:120998$4610_Y + attribute \src "libresoc.v:121001.18-121001.131" + wire $eq$libresoc.v:121001$4613_Y + attribute \src "libresoc.v:121007.17-121007.130" + wire $eq$libresoc.v:121007$4619_Y + attribute \src "libresoc.v:120985.18-120985.110" + wire $not$libresoc.v:120985$4597_Y + attribute \src "libresoc.v:121003.18-121003.110" + wire $not$libresoc.v:121003$4615_Y + attribute \src "libresoc.v:120989.18-120989.110" + wire $or$libresoc.v:120989$4601_Y + attribute \src "libresoc.v:120992.18-120992.110" + wire $or$libresoc.v:120992$4604_Y + attribute \src "libresoc.v:120995.18-120995.110" + wire $or$libresoc.v:120995$4607_Y + attribute \src "libresoc.v:120997.18-120997.110" + wire $or$libresoc.v:120997$4609_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 18 \DIV__data_len @@ -186991,22 +188853,10 @@ module \dec_DIV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_DIV_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_DIV_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 \dec_DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \dec_DIV_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_DIV_OE @@ -187022,17 +188872,6 @@ module \dec_DIV wire width 10 \dec_DIV_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \dec_DIV_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 \dec_DIV_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -187191,13 +189030,7 @@ module \dec_DIV wire \dec_DIV_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \dec_DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -187205,7 +189038,7 @@ module \dec_DIV attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire width 3 \dec_ai_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -187226,36 +189059,8 @@ module \dec_DIV attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 \dec_cr_out_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -187264,7 +189069,7 @@ module \dec_DIV attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -187276,64 +189081,112 @@ module \dec_DIV attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120100.7-120100.15" + attribute \src "libresoc.v:120559.7-120559.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $and $and$libresoc.v:120556$4505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:120984$4596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$6 - connect \B \$20 - connect \Y $and$libresoc.v:120556$4505_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:120984$4596_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:120550$4499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:120986$4598 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010011 - connect \Y $eq$libresoc.v:120550$4499_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:120986$4598_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:120552$4501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:120999$4611 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'1011010000 - connect \Y $eq$libresoc.v:120552$4501_Y + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:120999$4611_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:120554$4503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:121000$4612 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 6'110000 - connect \Y $eq$libresoc.v:120554$4503_Y + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:121000$4612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:121002$4614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:121002$4614_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:121004$4616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:121004$4616_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:121005$4617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:121005$4617_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:121006$4618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:121006$4618_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - cell $eq $eq$libresoc.v:120557$4506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" + cell $eq $eq$libresoc.v:120987$4599 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -187341,10 +189194,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:120557$4506_Y + connect \Y $eq$libresoc.v:120987$4599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $eq $eq$libresoc.v:120558$4507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $eq $eq$libresoc.v:120988$4600 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -187352,74 +189205,161 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:120558$4507_Y + connect \Y $eq$libresoc.v:120988$4600_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:120990$4602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:120990$4602_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:120991$4603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:120991$4603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:120560$4509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:120993$4605 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr - connect \B 10'0000010010 - connect \Y $eq$libresoc.v:120560$4509_Y + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:120993$4605_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:120994$4606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:120994$4606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $eq $eq$libresoc.v:120996$4608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:120996$4608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:120551$4500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:120998$4610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:120998$4610_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:121001$4613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:121001$4613_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:121007$4619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:121007$4619_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:120985$4597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:120985$4597_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:121003$4615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:121003$4615_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $or $or$libresoc.v:120989$4601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$8 - connect \B \$10 - connect \Y $or$libresoc.v:120551$4500_Y + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:120989$4601_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:120553$4502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:120992$4604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$12 - connect \B \$14 - connect \Y $or$libresoc.v:120553$4502_Y + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:120992$4604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:120555$4504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:120995$4607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$16 - connect \B \$18 - connect \Y $or$libresoc.v:120555$4504_Y + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:120995$4607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $or $or$libresoc.v:120559$4508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $or $or$libresoc.v:120997$4609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$2 - connect \B \$4 - connect \Y $or$libresoc.v:120559$4508_Y + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:120997$4609_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:120561.13-120599.4" - cell \dec$170 \dec - connect \DIV_BA \dec_DIV_BA - connect \DIV_BB \dec_DIV_BB - connect \DIV_BC \dec_DIV_BC + attribute \src "libresoc.v:121008.13-121036.4" + cell \dec$153 \dec connect \DIV_BD \dec_DIV_BD - connect \DIV_BI \dec_DIV_BI - connect \DIV_BT \dec_DIV_BT connect \DIV_DS \dec_DIV_DS - connect \DIV_FXM \dec_DIV_FXM connect \DIV_LI \dec_DIV_LI connect \DIV_OE \dec_DIV_OE connect \DIV_RA \dec_DIV_RA @@ -187428,7 +189368,6 @@ module \dec_DIV connect \DIV_SI \dec_DIV_SI connect \DIV_SPR \dec_DIV_SPR connect \DIV_UI \dec_DIV_UI - connect \DIV_cr_in \dec_DIV_cr_in connect \DIV_cr_out \dec_DIV_cr_out connect \DIV_cry_in \dec_DIV_cry_in connect \DIV_cry_out \dec_DIV_cry_out @@ -187443,23 +189382,20 @@ module \dec_DIV connect \DIV_rc_sel \dec_DIV_rc_sel connect \DIV_sgn \dec_DIV_sgn connect \DIV_sh \dec_DIV_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120600.16-120604.4" - cell \dec_ai$177 \dec_ai + attribute \src "libresoc.v:121037.16-121041.4" + cell \dec_ai$156 \dec_ai connect \DIV_RA \dec_DIV_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120605.16-120616.4" - cell \dec_bi$178 \dec_bi + attribute \src "libresoc.v:121042.16-121053.4" + cell \dec_bi$157 \dec_bi connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS connect \DIV_LI \dec_DIV_LI @@ -187472,34 +189408,8 @@ module \dec_DIV connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120617.19-120628.4" - cell \dec_cr_in$173 \dec_cr_in - connect \DIV_BA \dec_DIV_BA - connect \DIV_BB \dec_DIV_BB - connect \DIV_BC \dec_DIV_BC - connect \DIV_BI \dec_DIV_BI - connect \DIV_BT \dec_DIV_BT - connect \DIV_FXM \dec_DIV_FXM - connect \DIV_internal_op \dec_DIV_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:120629.20-120638.4" - cell \dec_cr_out$175 \dec_cr_out - connect \DIV_FXM \dec_DIV_FXM - connect \DIV_internal_op \dec_DIV_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:120639.16-120645.4" - cell \dec_oe$172 \dec_oe + attribute \src "libresoc.v:121054.16-121060.4" + cell \dec_oe$155 \dec_oe connect \DIV_OE \dec_DIV_OE connect \DIV_internal_op \dec_DIV_internal_op connect \oe \dec_oe_oe @@ -187507,37 +189417,95 @@ module \dec_DIV connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:120646.16-120651.4" - cell \dec_rc$171 \dec_rc + attribute \src "libresoc.v:121061.16-121066.4" + cell \dec_rc$154 \dec_rc connect \DIV_Rc \dec_DIV_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120100.7-120100.20" - process $proc$libresoc.v:120100$4511 + attribute \src "libresoc.v:120559.7-120559.20" + process $proc$libresoc.v:120559$4623 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120652.3-120663.6" - process $proc$libresoc.v:120652$4510 + attribute \src "libresoc.v:121067.3-121081.6" + process $proc$libresoc.v:121067$4620 assign { } { } - assign $0\DIV__fn_unit[12:0] $1\DIV__fn_unit[12:0] - attribute \src "libresoc.v:120653.5-120653.29" + assign { } { } + assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0] + attribute \src "libresoc.v:121068.5-121068.29" switch \initial - attribute \src "libresoc.v:120653.9-120653.17" + attribute \src "libresoc.v:121068.9-121068.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:838" + switch \dec_DIV_cr_out attribute \src "libresoc.v:0.0-0.0" + case 3'001 , 3'101 + assign { } { } + assign $1\DIV__write_cr0[0:0] \dec_rc_rc + attribute \src "libresoc.v:0.0-0.0" + case 3'010 , 3'011 + assign { } { } + assign $1\DIV__write_cr0[0:0] 1'1 + case + assign $1\DIV__write_cr0[0:0] 1'0 + end + sync always + update \DIV__write_cr0 $0\DIV__write_cr0[0:0] + end + attribute \src "libresoc.v:121082.3-121094.6" + process $proc$libresoc.v:121082$4621 + assign { } { } + assign { } { } + assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0] + attribute \src "libresoc.v:121083.5-121083.29" + switch \initial + attribute \src "libresoc.v:121083.9-121083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\DIV__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\DIV__insn_type[6:0] 7'0000000 + case + assign $1\DIV__insn_type[6:0] \dec_DIV_internal_op + end + sync always + update \DIV__insn_type $0\DIV__insn_type[6:0] + end + attribute \src "libresoc.v:121095.3-121109.6" + process $proc$libresoc.v:121095$4622 + assign { } { } + assign $0\DIV__fn_unit[12:0] $1\DIV__fn_unit[12:0] + attribute \src "libresoc.v:121096.5-121096.29" + switch \initial + attribute \src "libresoc.v:121096.9-121096.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\DIV__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $1\DIV__fn_unit[12:0] 13'0100000000000 + assign $1\DIV__fn_unit[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -187546,17 +189514,30 @@ module \dec_DIV sync always update \DIV__fn_unit $0\DIV__fn_unit[12:0] end - connect \$10 $eq$libresoc.v:120550$4499_Y - connect \$12 $or$libresoc.v:120551$4500_Y - connect \$14 $eq$libresoc.v:120552$4501_Y - connect \$16 $or$libresoc.v:120553$4502_Y - connect \$18 $eq$libresoc.v:120554$4503_Y - connect \$20 $or$libresoc.v:120555$4504_Y - connect \$22 $and$libresoc.v:120556$4505_Y - connect \$2 $eq$libresoc.v:120557$4506_Y - connect \$4 $eq$libresoc.v:120558$4507_Y - connect \$6 $or$libresoc.v:120559$4508_Y - connect \$8 $eq$libresoc.v:120560$4509_Y + connect \$10 $and$libresoc.v:120984$4596_Y + connect \$12 $not$libresoc.v:120985$4597_Y + connect \$14 $and$libresoc.v:120986$4598_Y + connect \$16 $eq$libresoc.v:120987$4599_Y + connect \$18 $eq$libresoc.v:120988$4600_Y + connect \$20 $or$libresoc.v:120989$4601_Y + connect \$22 $eq$libresoc.v:120990$4602_Y + connect \$24 $eq$libresoc.v:120991$4603_Y + connect \$26 $or$libresoc.v:120992$4604_Y + connect \$28 $eq$libresoc.v:120993$4605_Y + connect \$2 $eq$libresoc.v:120994$4606_Y + connect \$30 $or$libresoc.v:120995$4607_Y + connect \$32 $eq$libresoc.v:120996$4608_Y + connect \$34 $or$libresoc.v:120997$4609_Y + connect \$36 $eq$libresoc.v:120998$4610_Y + connect \$38 $and$libresoc.v:120999$4611_Y + connect \$40 $and$libresoc.v:121000$4612_Y + connect \$42 $eq$libresoc.v:121001$4613_Y + connect \$44 $and$libresoc.v:121002$4614_Y + connect \$46 $not$libresoc.v:121003$4615_Y + connect \$48 $and$libresoc.v:121004$4616_Y + connect \$4 $and$libresoc.v:121005$4617_Y + connect \$6 $and$libresoc.v:121006$4618_Y + connect \$8 $eq$libresoc.v:121007$4619_Y connect \DIV__is_signed \dec_DIV_sgn connect \DIV__is_32bit \dec_DIV_is_32b connect \DIV__output_carry \dec_DIV_cry_out @@ -187564,80 +189545,131 @@ module \dec_DIV connect \DIV__invert_out \dec_DIV_inv_out connect \DIV__invert_in \dec_DIV_inv_a connect \DIV__data_len \dec_DIV_ldst_len - connect \DIV__write_cr0 \dec_cr_out_cr_bitfield_ok connect { \DIV__oe__ok \DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \DIV__rc__ok \DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \DIV__imm_data__ok \DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_DIV_in2_sel connect \DIV__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_DIV_in1_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 connect \spr { \dec_DIV_SPR [4:0] \dec_DIV_SPR [9:5] } - connect \DIV__insn_type \dec_DIV_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_DIV_cr_out - connect \dec_cr_in_sel_in \dec_DIV_cr_in connect \dec_oe_sel_in \dec_DIV_rc_sel connect \dec_rc_sel_in \dec_DIV_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \DIV__insn \dec_opcode_in end -attribute \src "libresoc.v:120694.1-121275.10" +attribute \src "libresoc.v:121135.1-121686.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" attribute \generator "nMigen" module \dec_LDST - attribute \src "libresoc.v:121239.3-121250.6" + attribute \src "libresoc.v:121651.3-121665.6" wire width 13 $0\LDST__fn_unit[12:0] - attribute \src "libresoc.v:120695.7-120695.20" + attribute \src "libresoc.v:121638.3-121650.6" + wire width 7 $0\LDST__insn_type[6:0] + attribute \src "libresoc.v:121136.7-121136.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121239.3-121250.6" + attribute \src "libresoc.v:121651.3-121665.6" wire width 13 $1\LDST__fn_unit[12:0] - attribute \src "libresoc.v:121145.18-121145.109" - wire $and$libresoc.v:121145$4518_Y - attribute \src "libresoc.v:121139.18-121139.112" - wire $eq$libresoc.v:121139$4512_Y - attribute \src "libresoc.v:121141.18-121141.112" - wire $eq$libresoc.v:121141$4514_Y - attribute \src "libresoc.v:121143.18-121143.110" - wire $eq$libresoc.v:121143$4516_Y - attribute \src "libresoc.v:121146.17-121146.126" - wire $eq$libresoc.v:121146$4519_Y - attribute \src "libresoc.v:121147.17-121147.126" - wire $eq$libresoc.v:121147$4520_Y - attribute \src "libresoc.v:121149.17-121149.111" - wire $eq$libresoc.v:121149$4522_Y - attribute \src "libresoc.v:121140.18-121140.109" - wire $or$libresoc.v:121140$4513_Y - attribute \src "libresoc.v:121142.18-121142.110" - wire $or$libresoc.v:121142$4515_Y - attribute \src "libresoc.v:121144.18-121144.110" - wire $or$libresoc.v:121144$4517_Y - attribute \src "libresoc.v:121148.17-121148.107" - wire $or$libresoc.v:121148$4521_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "libresoc.v:121638.3-121650.6" + wire width 7 $1\LDST__insn_type[6:0] + attribute \src "libresoc.v:121556.18-121556.113" + wire $and$libresoc.v:121556$4624_Y + attribute \src "libresoc.v:121558.18-121558.110" + wire $and$libresoc.v:121558$4626_Y + attribute \src "libresoc.v:121571.18-121571.114" + wire $and$libresoc.v:121571$4639_Y + attribute \src "libresoc.v:121572.18-121572.116" + wire $and$libresoc.v:121572$4640_Y + attribute \src "libresoc.v:121574.18-121574.114" + wire $and$libresoc.v:121574$4642_Y + attribute \src "libresoc.v:121576.18-121576.110" + wire $and$libresoc.v:121576$4644_Y + attribute \src "libresoc.v:121577.17-121577.112" + wire $and$libresoc.v:121577$4645_Y + attribute \src "libresoc.v:121578.17-121578.114" + wire $and$libresoc.v:121578$4646_Y + attribute \src "libresoc.v:121559.18-121559.127" + wire $eq$libresoc.v:121559$4627_Y + attribute \src "libresoc.v:121560.18-121560.127" + wire $eq$libresoc.v:121560$4628_Y + attribute \src "libresoc.v:121562.18-121562.110" + wire $eq$libresoc.v:121562$4630_Y + attribute \src "libresoc.v:121563.18-121563.110" + wire $eq$libresoc.v:121563$4631_Y + attribute \src "libresoc.v:121565.18-121565.112" + wire $eq$libresoc.v:121565$4633_Y + attribute \src "libresoc.v:121566.17-121566.131" + wire $eq$libresoc.v:121566$4634_Y + attribute \src "libresoc.v:121568.18-121568.110" + wire $eq$libresoc.v:121568$4636_Y + attribute \src "libresoc.v:121570.18-121570.132" + wire $eq$libresoc.v:121570$4638_Y + attribute \src "libresoc.v:121573.18-121573.132" + wire $eq$libresoc.v:121573$4641_Y + attribute \src "libresoc.v:121579.17-121579.131" + wire $eq$libresoc.v:121579$4647_Y + attribute \src "libresoc.v:121557.18-121557.110" + wire $not$libresoc.v:121557$4625_Y + attribute \src "libresoc.v:121575.18-121575.110" + wire $not$libresoc.v:121575$4643_Y + attribute \src "libresoc.v:121561.18-121561.110" + wire $or$libresoc.v:121561$4629_Y + attribute \src "libresoc.v:121564.18-121564.110" + wire $or$libresoc.v:121564$4632_Y + attribute \src "libresoc.v:121567.18-121567.110" + wire $or$libresoc.v:121567$4635_Y + attribute \src "libresoc.v:121569.18-121569.110" + wire $or$libresoc.v:121569$4637_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire output 14 \LDST__byte_reverse @@ -187767,22 +189799,10 @@ module \dec_LDST attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_LDST_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_LDST_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 \dec_LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \dec_LDST_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_LDST_OE @@ -187800,17 +189820,6 @@ module \dec_LDST wire width 16 \dec_LDST_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" wire \dec_LDST_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 \dec_LDST_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -187966,13 +189975,7 @@ module \dec_LDST attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -187980,7 +189983,7 @@ module \dec_LDST attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire width 3 \dec_ai_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -188001,34 +190004,8 @@ module \dec_LDST attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 \dec_cr_out_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -188037,7 +190014,7 @@ module \dec_LDST attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -188049,64 +190026,112 @@ module \dec_LDST attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120695.7-120695.15" + attribute \src "libresoc.v:121136.7-121136.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 18 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $and $and$libresoc.v:121145$4518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:121556$4624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$6 - connect \B \$20 - connect \Y $and$libresoc.v:121145$4518_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:121556$4624_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:121139$4512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:121558$4626 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010011 - connect \Y $eq$libresoc.v:121139$4512_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:121558$4626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:121141$4514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:121571$4639 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121141$4514_Y + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:121571$4639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:121143$4516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:121572$4640 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 6'110000 - connect \Y $eq$libresoc.v:121143$4516_Y + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:121572$4640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:121574$4642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:121574$4642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:121576$4644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:121576$4644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:121577$4645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:121577$4645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:121578$4646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:121578$4646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - cell $eq $eq$libresoc.v:121146$4519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" + cell $eq $eq$libresoc.v:121559$4627 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188114,10 +190139,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121146$4519_Y + connect \Y $eq$libresoc.v:121559$4627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $eq $eq$libresoc.v:121147$4520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $eq $eq$libresoc.v:121560$4628 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188125,74 +190150,161 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121147$4520_Y + connect \Y $eq$libresoc.v:121560$4628_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:121562$4630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:121562$4630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:121149$4522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:121563$4631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:121563$4631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:121565$4633 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr - connect \B 10'0000010010 - connect \Y $eq$libresoc.v:121149$4522_Y + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:121565$4633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:121566$4634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:121566$4634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $eq $eq$libresoc.v:121568$4636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:121568$4636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:121570$4638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:121570$4638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:121573$4641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:121573$4641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:121579$4647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:121579$4647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:121557$4625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:121557$4625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:121575$4643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:121575$4643_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:121140$4513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $or $or$libresoc.v:121561$4629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$8 - connect \B \$10 - connect \Y $or$libresoc.v:121140$4513_Y + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:121561$4629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:121142$4515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:121564$4632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$12 - connect \B \$14 - connect \Y $or$libresoc.v:121142$4515_Y + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:121564$4632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:121144$4517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:121567$4635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$16 - connect \B \$18 - connect \Y $or$libresoc.v:121144$4517_Y + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:121567$4635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $or $or$libresoc.v:121148$4521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $or $or$libresoc.v:121569$4637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$2 - connect \B \$4 - connect \Y $or$libresoc.v:121148$4521_Y + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:121569$4637_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121150.13-121187.4" - cell \dec$195 \dec - connect \LDST_BA \dec_LDST_BA - connect \LDST_BB \dec_LDST_BB - connect \LDST_BC \dec_LDST_BC + attribute \src "libresoc.v:121580.13-121607.4" + cell \dec$166 \dec connect \LDST_BD \dec_LDST_BD - connect \LDST_BI \dec_LDST_BI - connect \LDST_BT \dec_LDST_BT connect \LDST_DS \dec_LDST_DS - connect \LDST_FXM \dec_LDST_FXM connect \LDST_LI \dec_LDST_LI connect \LDST_OE \dec_LDST_OE connect \LDST_RA \dec_LDST_RA @@ -188202,7 +190314,6 @@ module \dec_LDST connect \LDST_SPR \dec_LDST_SPR connect \LDST_UI \dec_LDST_UI connect \LDST_br \dec_LDST_br - connect \LDST_cr_in \dec_LDST_cr_in connect \LDST_cr_out \dec_LDST_cr_out connect \LDST_function_unit \dec_LDST_function_unit connect \LDST_in1_sel \dec_LDST_in1_sel @@ -188215,23 +190326,20 @@ module \dec_LDST connect \LDST_sgn_ext \dec_LDST_sgn_ext connect \LDST_sh \dec_LDST_sh connect \LDST_upd \dec_LDST_upd - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121188.16-121192.4" - cell \dec_ai$202 \dec_ai + attribute \src "libresoc.v:121608.16-121612.4" + cell \dec_ai$169 \dec_ai connect \LDST_RA \dec_LDST_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121193.16-121204.4" - cell \dec_bi$203 \dec_bi + attribute \src "libresoc.v:121613.16-121624.4" + cell \dec_bi$170 \dec_bi connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS connect \LDST_LI \dec_LDST_LI @@ -188244,33 +190352,8 @@ module \dec_LDST connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121205.19-121216.4" - cell \dec_cr_in$198 \dec_cr_in - connect \LDST_BA \dec_LDST_BA - connect \LDST_BB \dec_LDST_BB - connect \LDST_BC \dec_LDST_BC - connect \LDST_BI \dec_LDST_BI - connect \LDST_BT \dec_LDST_BT - connect \LDST_FXM \dec_LDST_FXM - connect \LDST_internal_op \dec_LDST_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121217.20-121225.4" - cell \dec_cr_out$200 \dec_cr_out - connect \LDST_FXM \dec_LDST_FXM - connect \LDST_internal_op \dec_LDST_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121226.16-121232.4" - cell \dec_oe$197 \dec_oe + attribute \src "libresoc.v:121625.16-121631.4" + cell \dec_oe$168 \dec_oe connect \LDST_OE \dec_LDST_OE connect \LDST_internal_op \dec_LDST_internal_op connect \oe \dec_oe_oe @@ -188278,37 +190361,68 @@ module \dec_LDST connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121233.16-121238.4" - cell \dec_rc$196 \dec_rc + attribute \src "libresoc.v:121632.16-121637.4" + cell \dec_rc$167 \dec_rc connect \LDST_Rc \dec_LDST_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120695.7-120695.20" - process $proc$libresoc.v:120695$4524 + attribute \src "libresoc.v:121136.7-121136.20" + process $proc$libresoc.v:121136$4650 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121239.3-121250.6" - process $proc$libresoc.v:121239$4523 + attribute \src "libresoc.v:121638.3-121650.6" + process $proc$libresoc.v:121638$4648 assign { } { } - assign $0\LDST__fn_unit[12:0] $1\LDST__fn_unit[12:0] - attribute \src "libresoc.v:121240.5-121240.29" + assign { } { } + assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0] + attribute \src "libresoc.v:121639.5-121639.29" switch \initial - attribute \src "libresoc.v:121240.9-121240.17" + attribute \src "libresoc.v:121639.9-121639.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$14 \$6 } attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\LDST__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\LDST__insn_type[6:0] 7'0000000 + case + assign $1\LDST__insn_type[6:0] \dec_LDST_internal_op + end + sync always + update \LDST__insn_type $0\LDST__insn_type[6:0] + end + attribute \src "libresoc.v:121651.3-121665.6" + process $proc$libresoc.v:121651$4649 + assign { } { } + assign $0\LDST__fn_unit[12:0] $1\LDST__fn_unit[12:0] + attribute \src "libresoc.v:121652.5-121652.29" + switch \initial + attribute \src "libresoc.v:121652.9-121652.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\LDST__fn_unit[12:0] 13'0100000000000 + assign $1\LDST__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\LDST__fn_unit[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -188317,17 +190431,30 @@ module \dec_LDST sync always update \LDST__fn_unit $0\LDST__fn_unit[12:0] end - connect \$10 $eq$libresoc.v:121139$4512_Y - connect \$12 $or$libresoc.v:121140$4513_Y - connect \$14 $eq$libresoc.v:121141$4514_Y - connect \$16 $or$libresoc.v:121142$4515_Y - connect \$18 $eq$libresoc.v:121143$4516_Y - connect \$20 $or$libresoc.v:121144$4517_Y - connect \$22 $and$libresoc.v:121145$4518_Y - connect \$2 $eq$libresoc.v:121146$4519_Y - connect \$4 $eq$libresoc.v:121147$4520_Y - connect \$6 $or$libresoc.v:121148$4521_Y - connect \$8 $eq$libresoc.v:121149$4522_Y + connect \$10 $and$libresoc.v:121556$4624_Y + connect \$12 $not$libresoc.v:121557$4625_Y + connect \$14 $and$libresoc.v:121558$4626_Y + connect \$16 $eq$libresoc.v:121559$4627_Y + connect \$18 $eq$libresoc.v:121560$4628_Y + connect \$20 $or$libresoc.v:121561$4629_Y + connect \$22 $eq$libresoc.v:121562$4630_Y + connect \$24 $eq$libresoc.v:121563$4631_Y + connect \$26 $or$libresoc.v:121564$4632_Y + connect \$28 $eq$libresoc.v:121565$4633_Y + connect \$2 $eq$libresoc.v:121566$4634_Y + connect \$30 $or$libresoc.v:121567$4635_Y + connect \$32 $eq$libresoc.v:121568$4636_Y + connect \$34 $or$libresoc.v:121569$4637_Y + connect \$36 $eq$libresoc.v:121570$4638_Y + connect \$38 $and$libresoc.v:121571$4639_Y + connect \$40 $and$libresoc.v:121572$4640_Y + connect \$42 $eq$libresoc.v:121573$4641_Y + connect \$44 $and$libresoc.v:121574$4642_Y + connect \$46 $not$libresoc.v:121575$4643_Y + connect \$48 $and$libresoc.v:121576$4644_Y + connect \$4 $and$libresoc.v:121577$4645_Y + connect \$6 $and$libresoc.v:121578$4646_Y + connect \$8 $eq$libresoc.v:121579$4647_Y connect \LDST__ldst_mode \dec_LDST_upd connect \LDST__sign_extend \dec_LDST_sgn_ext connect \LDST__byte_reverse \dec_LDST_br @@ -188340,73 +190467,129 @@ module \dec_LDST connect \dec_bi_sel_in \dec_LDST_in2_sel connect \LDST__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_LDST_in1_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 connect \spr { \dec_LDST_SPR [4:0] \dec_LDST_SPR [9:5] } - connect \LDST__insn_type \dec_LDST_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_LDST_cr_out - connect \dec_cr_in_sel_in \dec_LDST_cr_in connect \dec_oe_sel_in \dec_LDST_rc_sel connect \dec_rc_sel_in \dec_LDST_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \LDST__insn \dec_opcode_in end -attribute \src "libresoc.v:121279.1-121870.10" +attribute \src "libresoc.v:121690.1-122263.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" attribute \generator "nMigen" module \dec_LOGICAL - attribute \src "libresoc.v:121832.3-121843.6" + attribute \src "libresoc.v:122227.3-122241.6" wire width 13 $0\LOGICAL__fn_unit[12:0] - attribute \src "libresoc.v:121280.7-121280.20" + attribute \src "libresoc.v:122214.3-122226.6" + wire width 7 $0\LOGICAL__insn_type[6:0] + attribute \src "libresoc.v:122199.3-122213.6" + wire $0\LOGICAL__write_cr0[0:0] + attribute \src "libresoc.v:121691.7-121691.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121832.3-121843.6" + attribute \src "libresoc.v:122227.3-122241.6" wire width 13 $1\LOGICAL__fn_unit[12:0] - attribute \src "libresoc.v:121736.18-121736.109" - wire $and$libresoc.v:121736$4531_Y - attribute \src "libresoc.v:121730.18-121730.112" - wire $eq$libresoc.v:121730$4525_Y - attribute \src "libresoc.v:121732.18-121732.112" - wire $eq$libresoc.v:121732$4527_Y - attribute \src "libresoc.v:121734.18-121734.110" - wire $eq$libresoc.v:121734$4529_Y - attribute \src "libresoc.v:121737.17-121737.129" - wire $eq$libresoc.v:121737$4532_Y - attribute \src "libresoc.v:121738.17-121738.129" - wire $eq$libresoc.v:121738$4533_Y - attribute \src "libresoc.v:121740.17-121740.111" - wire $eq$libresoc.v:121740$4535_Y - attribute \src "libresoc.v:121731.18-121731.109" - wire $or$libresoc.v:121731$4526_Y - attribute \src "libresoc.v:121733.18-121733.110" - wire $or$libresoc.v:121733$4528_Y - attribute \src "libresoc.v:121735.18-121735.110" - wire $or$libresoc.v:121735$4530_Y - attribute \src "libresoc.v:121739.17-121739.107" - wire $or$libresoc.v:121739$4534_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "libresoc.v:122214.3-122226.6" + wire width 7 $1\LOGICAL__insn_type[6:0] + attribute \src "libresoc.v:122199.3-122213.6" + wire $1\LOGICAL__write_cr0[0:0] + attribute \src "libresoc.v:122116.18-122116.113" + wire $and$libresoc.v:122116$4651_Y + attribute \src "libresoc.v:122118.18-122118.110" + wire $and$libresoc.v:122118$4653_Y + attribute \src "libresoc.v:122131.18-122131.114" + wire $and$libresoc.v:122131$4666_Y + attribute \src "libresoc.v:122132.18-122132.116" + wire $and$libresoc.v:122132$4667_Y + attribute \src "libresoc.v:122134.18-122134.114" + wire $and$libresoc.v:122134$4669_Y + attribute \src "libresoc.v:122136.18-122136.110" + wire $and$libresoc.v:122136$4671_Y + attribute \src "libresoc.v:122137.17-122137.112" + wire $and$libresoc.v:122137$4672_Y + attribute \src "libresoc.v:122138.17-122138.114" + wire $and$libresoc.v:122138$4673_Y + attribute \src "libresoc.v:122119.18-122119.130" + wire $eq$libresoc.v:122119$4654_Y + attribute \src "libresoc.v:122120.18-122120.130" + wire $eq$libresoc.v:122120$4655_Y + attribute \src "libresoc.v:122122.18-122122.110" + wire $eq$libresoc.v:122122$4657_Y + attribute \src "libresoc.v:122123.18-122123.110" + wire $eq$libresoc.v:122123$4658_Y + attribute \src "libresoc.v:122125.18-122125.112" + wire $eq$libresoc.v:122125$4660_Y + attribute \src "libresoc.v:122126.17-122126.134" + wire $eq$libresoc.v:122126$4661_Y + attribute \src "libresoc.v:122128.18-122128.110" + wire $eq$libresoc.v:122128$4663_Y + attribute \src "libresoc.v:122130.18-122130.135" + wire $eq$libresoc.v:122130$4665_Y + attribute \src "libresoc.v:122133.18-122133.135" + wire $eq$libresoc.v:122133$4668_Y + attribute \src "libresoc.v:122139.17-122139.134" + wire $eq$libresoc.v:122139$4674_Y + attribute \src "libresoc.v:122117.18-122117.110" + wire $not$libresoc.v:122117$4652_Y + attribute \src "libresoc.v:122135.18-122135.110" + wire $not$libresoc.v:122135$4670_Y + attribute \src "libresoc.v:122121.18-122121.110" + wire $or$libresoc.v:122121$4656_Y + attribute \src "libresoc.v:122124.18-122124.110" + wire $or$libresoc.v:122124$4659_Y + attribute \src "libresoc.v:122127.18-122127.110" + wire $or$libresoc.v:122127$4662_Y + attribute \src "libresoc.v:122129.18-122129.110" + wire $or$libresoc.v:122129$4664_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 output 18 \LOGICAL__data_len @@ -188539,22 +190722,10 @@ module \dec_LOGICAL attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_LOGICAL_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_LOGICAL_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 \dec_LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \dec_LOGICAL_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_LOGICAL_OE @@ -188570,17 +190741,6 @@ module \dec_LOGICAL wire width 10 \dec_LOGICAL_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \dec_LOGICAL_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 \dec_LOGICAL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -188739,13 +190899,7 @@ module \dec_LOGICAL wire \dec_LOGICAL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \dec_LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire \dec_ai_immz_out attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -188753,7 +190907,7 @@ module \dec_LOGICAL attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire width 3 \dec_ai_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b @@ -188774,36 +190928,8 @@ module \dec_LOGICAL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 \dec_cr_out_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -188812,7 +190938,7 @@ module \dec_LOGICAL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -188824,64 +190950,112 @@ module \dec_LOGICAL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121280.7-121280.15" + attribute \src "libresoc.v:121691.7-121691.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $and $and$libresoc.v:121736$4531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:122116$4651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$6 - connect \B \$20 - connect \Y $and$libresoc.v:121736$4531_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:122116$4651_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:121730$4525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:122118$4653 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010011 - connect \Y $eq$libresoc.v:121730$4525_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:122118$4653_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:121732$4527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:122131$4666 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121732$4527_Y + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:122131$4666_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:121734$4529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:122132$4667 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 6'110000 - connect \Y $eq$libresoc.v:121734$4529_Y + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:122132$4667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:122134$4669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:122134$4669_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:122136$4671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:122136$4671_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:122137$4672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:122137$4672_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:122138$4673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:122138$4673_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - cell $eq $eq$libresoc.v:121737$4532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" + cell $eq $eq$libresoc.v:122119$4654 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188889,10 +191063,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121737$4532_Y + connect \Y $eq$libresoc.v:122119$4654_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $eq $eq$libresoc.v:121738$4533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $eq $eq$libresoc.v:122120$4655 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188900,74 +191074,161 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121738$4533_Y + connect \Y $eq$libresoc.v:122120$4655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:122122$4657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:122122$4657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:122123$4658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:122123$4658_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:121740$4535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:122125$4660 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr - connect \B 10'0000010010 - connect \Y $eq$libresoc.v:121740$4535_Y + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:122125$4660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:122126$4661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:122126$4661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:121731$4526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $eq $eq$libresoc.v:122128$4663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:122128$4663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:122130$4665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:122130$4665_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:122133$4668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:122133$4668_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:122139$4674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:122139$4674_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:122117$4652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:122117$4652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:122135$4670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:122135$4670_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $or $or$libresoc.v:122121$4656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$8 - connect \B \$10 - connect \Y $or$libresoc.v:121731$4526_Y + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:122121$4656_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:121733$4528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:122124$4659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$12 - connect \B \$14 - connect \Y $or$libresoc.v:121733$4528_Y + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:122124$4659_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:121735$4530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:122127$4662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$16 - connect \B \$18 - connect \Y $or$libresoc.v:121735$4530_Y + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:122127$4662_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $or $or$libresoc.v:121739$4534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $or $or$libresoc.v:122129$4664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$2 - connect \B \$4 - connect \Y $or$libresoc.v:121739$4534_Y + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:122129$4664_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121741.13-121779.4" - cell \dec$154 \dec - connect \LOGICAL_BA \dec_LOGICAL_BA - connect \LOGICAL_BB \dec_LOGICAL_BB - connect \LOGICAL_BC \dec_LOGICAL_BC + attribute \src "libresoc.v:122140.13-122168.4" + cell \dec$145 \dec connect \LOGICAL_BD \dec_LOGICAL_BD - connect \LOGICAL_BI \dec_LOGICAL_BI - connect \LOGICAL_BT \dec_LOGICAL_BT connect \LOGICAL_DS \dec_LOGICAL_DS - connect \LOGICAL_FXM \dec_LOGICAL_FXM connect \LOGICAL_LI \dec_LOGICAL_LI connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_RA \dec_LOGICAL_RA @@ -188976,7 +191237,6 @@ module \dec_LOGICAL connect \LOGICAL_SI \dec_LOGICAL_SI connect \LOGICAL_SPR \dec_LOGICAL_SPR connect \LOGICAL_UI \dec_LOGICAL_UI - connect \LOGICAL_cr_in \dec_LOGICAL_cr_in connect \LOGICAL_cr_out \dec_LOGICAL_cr_out connect \LOGICAL_cry_in \dec_LOGICAL_cry_in connect \LOGICAL_cry_out \dec_LOGICAL_cry_out @@ -188991,23 +191251,20 @@ module \dec_LOGICAL connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel connect \LOGICAL_sgn \dec_LOGICAL_sgn connect \LOGICAL_sh \dec_LOGICAL_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121780.16-121784.4" - cell \dec_ai$161 \dec_ai + attribute \src "libresoc.v:122169.16-122173.4" + cell \dec_ai$148 \dec_ai connect \LOGICAL_RA \dec_LOGICAL_RA connect \immz_out \dec_ai_immz_out connect \sel_in \dec_ai_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121785.16-121796.4" - cell \dec_bi$162 \dec_bi + attribute \src "libresoc.v:122174.16-122185.4" + cell \dec_bi$149 \dec_bi connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS connect \LOGICAL_LI \dec_LOGICAL_LI @@ -189020,34 +191277,8 @@ module \dec_LOGICAL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121797.19-121808.4" - cell \dec_cr_in$157 \dec_cr_in - connect \LOGICAL_BA \dec_LOGICAL_BA - connect \LOGICAL_BB \dec_LOGICAL_BB - connect \LOGICAL_BC \dec_LOGICAL_BC - connect \LOGICAL_BI \dec_LOGICAL_BI - connect \LOGICAL_BT \dec_LOGICAL_BT - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121809.20-121818.4" - cell \dec_cr_out$159 \dec_cr_out - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121819.16-121825.4" - cell \dec_oe$156 \dec_oe + attribute \src "libresoc.v:122186.16-122192.4" + cell \dec_oe$147 \dec_oe connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_internal_op \dec_LOGICAL_internal_op connect \oe \dec_oe_oe @@ -189055,37 +191286,95 @@ module \dec_LOGICAL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121826.16-121831.4" - cell \dec_rc$155 \dec_rc + attribute \src "libresoc.v:122193.16-122198.4" + cell \dec_rc$146 \dec_rc connect \LOGICAL_Rc \dec_LOGICAL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121280.7-121280.20" - process $proc$libresoc.v:121280$4537 + attribute \src "libresoc.v:121691.7-121691.20" + process $proc$libresoc.v:121691$4678 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121832.3-121843.6" - process $proc$libresoc.v:121832$4536 + attribute \src "libresoc.v:122199.3-122213.6" + process $proc$libresoc.v:122199$4675 assign { } { } - assign $0\LOGICAL__fn_unit[12:0] $1\LOGICAL__fn_unit[12:0] - attribute \src "libresoc.v:121833.5-121833.29" + assign { } { } + assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0] + attribute \src "libresoc.v:122200.5-122200.29" switch \initial - attribute \src "libresoc.v:121833.9-121833.17" + attribute \src "libresoc.v:122200.9-122200.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:838" + switch \dec_LOGICAL_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 3'001 , 3'101 + assign { } { } + assign $1\LOGICAL__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" + case 3'010 , 3'011 + assign { } { } + assign $1\LOGICAL__write_cr0[0:0] 1'1 + case + assign $1\LOGICAL__write_cr0[0:0] 1'0 + end + sync always + update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0] + end + attribute \src "libresoc.v:122214.3-122226.6" + process $proc$libresoc.v:122214$4676 + assign { } { } + assign { } { } + assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0] + attribute \src "libresoc.v:122215.5-122215.29" + switch \initial + attribute \src "libresoc.v:122215.9-122215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\LOGICAL__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\LOGICAL__insn_type[6:0] 7'0000000 + case + assign $1\LOGICAL__insn_type[6:0] \dec_LOGICAL_internal_op + end + sync always + update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0] + end + attribute \src "libresoc.v:122227.3-122241.6" + process $proc$libresoc.v:122227$4677 + assign { } { } + assign $0\LOGICAL__fn_unit[12:0] $1\LOGICAL__fn_unit[12:0] + attribute \src "libresoc.v:122228.5-122228.29" + switch \initial + attribute \src "libresoc.v:122228.9-122228.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\LOGICAL__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $1\LOGICAL__fn_unit[12:0] 13'0100000000000 + assign $1\LOGICAL__fn_unit[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -189094,17 +191383,30 @@ module \dec_LOGICAL sync always update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[12:0] end - connect \$10 $eq$libresoc.v:121730$4525_Y - connect \$12 $or$libresoc.v:121731$4526_Y - connect \$14 $eq$libresoc.v:121732$4527_Y - connect \$16 $or$libresoc.v:121733$4528_Y - connect \$18 $eq$libresoc.v:121734$4529_Y - connect \$20 $or$libresoc.v:121735$4530_Y - connect \$22 $and$libresoc.v:121736$4531_Y - connect \$2 $eq$libresoc.v:121737$4532_Y - connect \$4 $eq$libresoc.v:121738$4533_Y - connect \$6 $or$libresoc.v:121739$4534_Y - connect \$8 $eq$libresoc.v:121740$4535_Y + connect \$10 $and$libresoc.v:122116$4651_Y + connect \$12 $not$libresoc.v:122117$4652_Y + connect \$14 $and$libresoc.v:122118$4653_Y + connect \$16 $eq$libresoc.v:122119$4654_Y + connect \$18 $eq$libresoc.v:122120$4655_Y + connect \$20 $or$libresoc.v:122121$4656_Y + connect \$22 $eq$libresoc.v:122122$4657_Y + connect \$24 $eq$libresoc.v:122123$4658_Y + connect \$26 $or$libresoc.v:122124$4659_Y + connect \$28 $eq$libresoc.v:122125$4660_Y + connect \$2 $eq$libresoc.v:122126$4661_Y + connect \$30 $or$libresoc.v:122127$4662_Y + connect \$32 $eq$libresoc.v:122128$4663_Y + connect \$34 $or$libresoc.v:122129$4664_Y + connect \$36 $eq$libresoc.v:122130$4665_Y + connect \$38 $and$libresoc.v:122131$4666_Y + connect \$40 $and$libresoc.v:122132$4667_Y + connect \$42 $eq$libresoc.v:122133$4668_Y + connect \$44 $and$libresoc.v:122134$4669_Y + connect \$46 $not$libresoc.v:122135$4670_Y + connect \$48 $and$libresoc.v:122136$4671_Y + connect \$4 $and$libresoc.v:122137$4672_Y + connect \$6 $and$libresoc.v:122138$4673_Y + connect \$8 $eq$libresoc.v:122139$4674_Y connect \LOGICAL__is_signed \dec_LOGICAL_sgn connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b connect \LOGICAL__output_carry \dec_LOGICAL_cry_out @@ -189112,80 +191414,135 @@ module \dec_LOGICAL connect \LOGICAL__invert_out \dec_LOGICAL_inv_out connect \LOGICAL__invert_in \dec_LOGICAL_inv_a connect \LOGICAL__data_len \dec_LOGICAL_ldst_len - connect \LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok connect { \LOGICAL__oe__ok \LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \LOGICAL__rc__ok \LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \LOGICAL__imm_data__ok \LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_LOGICAL_in2_sel connect \LOGICAL__zero_a \dec_ai_immz_out connect \dec_ai_sel_in \dec_LOGICAL_in1_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 connect \spr { \dec_LOGICAL_SPR [4:0] \dec_LOGICAL_SPR [9:5] } - connect \LOGICAL__insn_type \dec_LOGICAL_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_LOGICAL_cr_out - connect \dec_cr_in_sel_in \dec_LOGICAL_cr_in connect \dec_oe_sel_in \dec_LOGICAL_rc_sel connect \dec_rc_sel_in \dec_LOGICAL_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \LOGICAL__insn \dec_opcode_in end -attribute \src "libresoc.v:121874.1-122390.10" +attribute \src "libresoc.v:122267.1-122765.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" attribute \generator "nMigen" module \dec_MUL - attribute \src "libresoc.v:122359.3-122370.6" + attribute \src "libresoc.v:122736.3-122750.6" wire width 13 $0\MUL__fn_unit[12:0] - attribute \src "libresoc.v:121875.7-121875.20" + attribute \src "libresoc.v:122723.3-122735.6" + wire width 7 $0\MUL__insn_type[6:0] + attribute \src "libresoc.v:122708.3-122722.6" + wire $0\MUL__write_cr0[0:0] + attribute \src "libresoc.v:122268.7-122268.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122359.3-122370.6" + attribute \src "libresoc.v:122736.3-122750.6" wire width 13 $1\MUL__fn_unit[12:0] - attribute \src "libresoc.v:122275.18-122275.109" - wire $and$libresoc.v:122275$4544_Y - attribute \src "libresoc.v:122269.18-122269.112" - wire $eq$libresoc.v:122269$4538_Y - attribute \src "libresoc.v:122271.18-122271.112" - wire $eq$libresoc.v:122271$4540_Y - attribute \src "libresoc.v:122273.18-122273.110" - wire $eq$libresoc.v:122273$4542_Y - attribute \src "libresoc.v:122276.17-122276.125" - wire $eq$libresoc.v:122276$4545_Y - attribute \src "libresoc.v:122277.17-122277.125" - wire $eq$libresoc.v:122277$4546_Y - attribute \src "libresoc.v:122279.17-122279.111" - wire $eq$libresoc.v:122279$4548_Y - attribute \src "libresoc.v:122270.18-122270.109" - wire $or$libresoc.v:122270$4539_Y - attribute \src "libresoc.v:122272.18-122272.110" - wire $or$libresoc.v:122272$4541_Y - attribute \src "libresoc.v:122274.18-122274.110" - wire $or$libresoc.v:122274$4543_Y - attribute \src "libresoc.v:122278.17-122278.107" - wire $or$libresoc.v:122278$4547_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "libresoc.v:122723.3-122735.6" + wire width 7 $1\MUL__insn_type[6:0] + attribute \src "libresoc.v:122708.3-122722.6" + wire $1\MUL__write_cr0[0:0] + attribute \src "libresoc.v:122637.18-122637.113" + wire $and$libresoc.v:122637$4679_Y + attribute \src "libresoc.v:122639.18-122639.110" + wire $and$libresoc.v:122639$4681_Y + attribute \src "libresoc.v:122652.18-122652.114" + wire $and$libresoc.v:122652$4694_Y + attribute \src "libresoc.v:122653.18-122653.116" + wire $and$libresoc.v:122653$4695_Y + attribute \src "libresoc.v:122655.18-122655.114" + wire $and$libresoc.v:122655$4697_Y + attribute \src "libresoc.v:122657.18-122657.110" + wire $and$libresoc.v:122657$4699_Y + attribute \src "libresoc.v:122658.17-122658.112" + wire $and$libresoc.v:122658$4700_Y + attribute \src "libresoc.v:122659.17-122659.114" + wire $and$libresoc.v:122659$4701_Y + attribute \src "libresoc.v:122640.18-122640.126" + wire $eq$libresoc.v:122640$4682_Y + attribute \src "libresoc.v:122641.18-122641.126" + wire $eq$libresoc.v:122641$4683_Y + attribute \src "libresoc.v:122643.18-122643.110" + wire $eq$libresoc.v:122643$4685_Y + attribute \src "libresoc.v:122644.18-122644.110" + wire $eq$libresoc.v:122644$4686_Y + attribute \src "libresoc.v:122646.18-122646.112" + wire $eq$libresoc.v:122646$4688_Y + attribute \src "libresoc.v:122647.17-122647.130" + wire $eq$libresoc.v:122647$4689_Y + attribute \src "libresoc.v:122649.18-122649.110" + wire $eq$libresoc.v:122649$4691_Y + attribute \src "libresoc.v:122651.18-122651.131" + wire $eq$libresoc.v:122651$4693_Y + attribute \src "libresoc.v:122654.18-122654.131" + wire $eq$libresoc.v:122654$4696_Y + attribute \src "libresoc.v:122660.17-122660.130" + wire $eq$libresoc.v:122660$4702_Y + attribute \src "libresoc.v:122638.18-122638.110" + wire $not$libresoc.v:122638$4680_Y + attribute \src "libresoc.v:122656.18-122656.110" + wire $not$libresoc.v:122656$4698_Y + attribute \src "libresoc.v:122642.18-122642.110" + wire $or$libresoc.v:122642$4684_Y + attribute \src "libresoc.v:122645.18-122645.110" + wire $or$libresoc.v:122645$4687_Y + attribute \src "libresoc.v:122648.18-122648.110" + wire $or$libresoc.v:122648$4690_Y + attribute \src "libresoc.v:122650.18-122650.110" + wire $or$libresoc.v:122650$4692_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" @@ -189302,22 +191659,10 @@ module \dec_MUL attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_MUL_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_MUL_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 \dec_MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \dec_MUL_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_MUL_OE @@ -189331,17 +191676,6 @@ module \dec_MUL wire width 10 \dec_MUL_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 16 \dec_MUL_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 \dec_MUL_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -189472,12 +191806,6 @@ module \dec_MUL wire \dec_MUL_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \dec_MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -189497,36 +191825,8 @@ module \dec_MUL attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 \dec_cr_out_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -189535,7 +191835,7 @@ module \dec_MUL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -189547,64 +191847,112 @@ module \dec_MUL attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121875.7-121875.15" + attribute \src "libresoc.v:122268.7-122268.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 14 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $and $and$libresoc.v:122275$4544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:122637$4679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$6 - connect \B \$20 - connect \Y $and$libresoc.v:122275$4544_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:122637$4679_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:122269$4538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:122639$4681 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010011 - connect \Y $eq$libresoc.v:122269$4538_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:122639$4681_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:122271$4540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:122652$4694 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122271$4540_Y + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:122652$4694_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:122273$4542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:122653$4695 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 6'110000 - connect \Y $eq$libresoc.v:122273$4542_Y + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:122653$4695_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:122655$4697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:122655$4697_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - cell $eq $eq$libresoc.v:122276$4545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:122657$4699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:122657$4699_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:122658$4700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:122658$4700_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:122659$4701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:122659$4701_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" + cell $eq $eq$libresoc.v:122640$4682 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189612,10 +191960,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122276$4545_Y + connect \Y $eq$libresoc.v:122640$4682_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $eq $eq$libresoc.v:122277$4546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $eq $eq$libresoc.v:122641$4683 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189623,74 +191971,161 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122277$4546_Y + connect \Y $eq$libresoc.v:122641$4683_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:122279$4548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:122643$4685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:122643$4685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:122644$4686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:122644$4686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:122646$4688 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr - connect \B 10'0000010010 - connect \Y $eq$libresoc.v:122279$4548_Y + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:122646$4688_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:122647$4689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:122647$4689_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $eq $eq$libresoc.v:122649$4691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:122649$4691_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:122651$4693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:122651$4693_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:122654$4696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:122654$4696_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:122270$4539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:122660$4702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:122660$4702_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:122638$4680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:122638$4680_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:122656$4698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:122656$4698_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $or $or$libresoc.v:122642$4684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$8 - connect \B \$10 - connect \Y $or$libresoc.v:122270$4539_Y + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:122642$4684_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:122272$4541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:122645$4687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$12 - connect \B \$14 - connect \Y $or$libresoc.v:122272$4541_Y + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:122645$4687_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:122274$4543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:122648$4690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$16 - connect \B \$18 - connect \Y $or$libresoc.v:122274$4543_Y + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:122648$4690_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $or $or$libresoc.v:122278$4547 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $or $or$libresoc.v:122650$4692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$2 - connect \B \$4 - connect \Y $or$libresoc.v:122278$4547_Y + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:122650$4692_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122280.13-122311.4" - cell \dec$179 \dec - connect \MUL_BA \dec_MUL_BA - connect \MUL_BB \dec_MUL_BB - connect \MUL_BC \dec_MUL_BC + attribute \src "libresoc.v:122661.13-122682.4" + cell \dec$158 \dec connect \MUL_BD \dec_MUL_BD - connect \MUL_BI \dec_MUL_BI - connect \MUL_BT \dec_MUL_BT connect \MUL_DS \dec_MUL_DS - connect \MUL_FXM \dec_MUL_FXM connect \MUL_LI \dec_MUL_LI connect \MUL_OE \dec_MUL_OE connect \MUL_Rc \dec_MUL_Rc @@ -189698,7 +192133,6 @@ module \dec_MUL connect \MUL_SI \dec_MUL_SI connect \MUL_SPR \dec_MUL_SPR connect \MUL_UI \dec_MUL_UI - connect \MUL_cr_in \dec_MUL_cr_in connect \MUL_cr_out \dec_MUL_cr_out connect \MUL_function_unit \dec_MUL_function_unit connect \MUL_in2_sel \dec_MUL_in2_sel @@ -189707,16 +192141,13 @@ module \dec_MUL connect \MUL_rc_sel \dec_MUL_rc_sel connect \MUL_sgn \dec_MUL_sgn connect \MUL_sh \dec_MUL_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122312.16-122323.4" - cell \dec_bi$186 \dec_bi + attribute \src "libresoc.v:122683.16-122694.4" + cell \dec_bi$161 \dec_bi connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS connect \MUL_LI \dec_MUL_LI @@ -189729,34 +192160,8 @@ module \dec_MUL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122324.19-122335.4" - cell \dec_cr_in$182 \dec_cr_in - connect \MUL_BA \dec_MUL_BA - connect \MUL_BB \dec_MUL_BB - connect \MUL_BC \dec_MUL_BC - connect \MUL_BI \dec_MUL_BI - connect \MUL_BT \dec_MUL_BT - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_internal_op \dec_MUL_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:122336.20-122345.4" - cell \dec_cr_out$184 \dec_cr_out - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_internal_op \dec_MUL_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:122346.16-122352.4" - cell \dec_oe$181 \dec_oe + attribute \src "libresoc.v:122695.16-122701.4" + cell \dec_oe$160 \dec_oe connect \MUL_OE \dec_MUL_OE connect \MUL_internal_op \dec_MUL_internal_op connect \oe \dec_oe_oe @@ -189764,37 +192169,95 @@ module \dec_MUL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122353.16-122358.4" - cell \dec_rc$180 \dec_rc + attribute \src "libresoc.v:122702.16-122707.4" + cell \dec_rc$159 \dec_rc connect \MUL_Rc \dec_MUL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121875.7-121875.20" - process $proc$libresoc.v:121875$4550 + attribute \src "libresoc.v:122268.7-122268.20" + process $proc$libresoc.v:122268$4706 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122359.3-122370.6" - process $proc$libresoc.v:122359$4549 + attribute \src "libresoc.v:122708.3-122722.6" + process $proc$libresoc.v:122708$4703 assign { } { } - assign $0\MUL__fn_unit[12:0] $1\MUL__fn_unit[12:0] - attribute \src "libresoc.v:122360.5-122360.29" + assign { } { } + assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0] + attribute \src "libresoc.v:122709.5-122709.29" switch \initial - attribute \src "libresoc.v:122360.9-122360.17" + attribute \src "libresoc.v:122709.9-122709.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:838" + switch \dec_MUL_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 3'001 , 3'101 + assign { } { } + assign $1\MUL__write_cr0[0:0] \dec_rc_rc attribute \src "libresoc.v:0.0-0.0" + case 3'010 , 3'011 + assign { } { } + assign $1\MUL__write_cr0[0:0] 1'1 + case + assign $1\MUL__write_cr0[0:0] 1'0 + end + sync always + update \MUL__write_cr0 $0\MUL__write_cr0[0:0] + end + attribute \src "libresoc.v:122723.3-122735.6" + process $proc$libresoc.v:122723$4704 + assign { } { } + assign { } { } + assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0] + attribute \src "libresoc.v:122724.5-122724.29" + switch \initial + attribute \src "libresoc.v:122724.9-122724.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\MUL__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\MUL__insn_type[6:0] 7'0000000 + case + assign $1\MUL__insn_type[6:0] \dec_MUL_internal_op + end + sync always + update \MUL__insn_type $0\MUL__insn_type[6:0] + end + attribute \src "libresoc.v:122736.3-122750.6" + process $proc$libresoc.v:122736$4705 + assign { } { } + assign $0\MUL__fn_unit[12:0] $1\MUL__fn_unit[12:0] + attribute \src "libresoc.v:122737.5-122737.29" + switch \initial + attribute \src "libresoc.v:122737.9-122737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\MUL__fn_unit[12:0] 13'0100000000000 + assign $1\MUL__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\MUL__fn_unit[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -189803,91 +192266,159 @@ module \dec_MUL sync always update \MUL__fn_unit $0\MUL__fn_unit[12:0] end - connect \$10 $eq$libresoc.v:122269$4538_Y - connect \$12 $or$libresoc.v:122270$4539_Y - connect \$14 $eq$libresoc.v:122271$4540_Y - connect \$16 $or$libresoc.v:122272$4541_Y - connect \$18 $eq$libresoc.v:122273$4542_Y - connect \$20 $or$libresoc.v:122274$4543_Y - connect \$22 $and$libresoc.v:122275$4544_Y - connect \$2 $eq$libresoc.v:122276$4545_Y - connect \$4 $eq$libresoc.v:122277$4546_Y - connect \$6 $or$libresoc.v:122278$4547_Y - connect \$8 $eq$libresoc.v:122279$4548_Y + connect \$10 $and$libresoc.v:122637$4679_Y + connect \$12 $not$libresoc.v:122638$4680_Y + connect \$14 $and$libresoc.v:122639$4681_Y + connect \$16 $eq$libresoc.v:122640$4682_Y + connect \$18 $eq$libresoc.v:122641$4683_Y + connect \$20 $or$libresoc.v:122642$4684_Y + connect \$22 $eq$libresoc.v:122643$4685_Y + connect \$24 $eq$libresoc.v:122644$4686_Y + connect \$26 $or$libresoc.v:122645$4687_Y + connect \$28 $eq$libresoc.v:122646$4688_Y + connect \$2 $eq$libresoc.v:122647$4689_Y + connect \$30 $or$libresoc.v:122648$4690_Y + connect \$32 $eq$libresoc.v:122649$4691_Y + connect \$34 $or$libresoc.v:122650$4692_Y + connect \$36 $eq$libresoc.v:122651$4693_Y + connect \$38 $and$libresoc.v:122652$4694_Y + connect \$40 $and$libresoc.v:122653$4695_Y + connect \$42 $eq$libresoc.v:122654$4696_Y + connect \$44 $and$libresoc.v:122655$4697_Y + connect \$46 $not$libresoc.v:122656$4698_Y + connect \$48 $and$libresoc.v:122657$4699_Y + connect \$4 $and$libresoc.v:122658$4700_Y + connect \$6 $and$libresoc.v:122659$4701_Y + connect \$8 $eq$libresoc.v:122660$4702_Y connect \MUL__is_signed \dec_MUL_sgn connect \MUL__is_32bit \dec_MUL_is_32b - connect \MUL__write_cr0 \dec_cr_out_cr_bitfield_ok connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \MUL__rc__ok \MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \MUL__imm_data__ok \MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_MUL_in2_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 connect \spr { \dec_MUL_SPR [4:0] \dec_MUL_SPR [9:5] } - connect \MUL__insn_type \dec_MUL_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_MUL_cr_out - connect \dec_cr_in_sel_in \dec_MUL_cr_in connect \dec_oe_sel_in \dec_MUL_rc_sel connect \dec_rc_sel_in \dec_MUL_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \MUL__insn \dec_opcode_in end -attribute \src "libresoc.v:122394.1-122942.10" +attribute \src "libresoc.v:122769.1-123311.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" attribute \generator "nMigen" module \dec_SHIFT_ROT - attribute \src "libresoc.v:122906.3-122917.6" + attribute \src "libresoc.v:123277.3-123291.6" wire width 13 $0\SHIFT_ROT__fn_unit[12:0] - attribute \src "libresoc.v:122395.7-122395.20" + attribute \src "libresoc.v:123264.3-123276.6" + wire width 7 $0\SHIFT_ROT__insn_type[6:0] + attribute \src "libresoc.v:123249.3-123263.6" + wire $0\SHIFT_ROT__write_cr0[0:0] + attribute \src "libresoc.v:122770.7-122770.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122906.3-122917.6" + attribute \src "libresoc.v:123277.3-123291.6" wire width 13 $1\SHIFT_ROT__fn_unit[12:0] - attribute \src "libresoc.v:122819.18-122819.109" - wire $and$libresoc.v:122819$4557_Y - attribute \src "libresoc.v:122813.18-122813.112" - wire $eq$libresoc.v:122813$4551_Y - attribute \src "libresoc.v:122815.18-122815.112" - wire $eq$libresoc.v:122815$4553_Y - attribute \src "libresoc.v:122817.18-122817.110" - wire $eq$libresoc.v:122817$4555_Y - attribute \src "libresoc.v:122820.17-122820.131" - wire $eq$libresoc.v:122820$4558_Y - attribute \src "libresoc.v:122821.17-122821.131" - wire $eq$libresoc.v:122821$4559_Y - attribute \src "libresoc.v:122823.17-122823.111" - wire $eq$libresoc.v:122823$4561_Y - attribute \src "libresoc.v:122814.18-122814.109" - wire $or$libresoc.v:122814$4552_Y - attribute \src "libresoc.v:122816.18-122816.110" - wire $or$libresoc.v:122816$4554_Y - attribute \src "libresoc.v:122818.18-122818.110" - wire $or$libresoc.v:122818$4556_Y - attribute \src "libresoc.v:122822.17-122822.107" - wire $or$libresoc.v:122822$4560_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "libresoc.v:123264.3-123276.6" + wire width 7 $1\SHIFT_ROT__insn_type[6:0] + attribute \src "libresoc.v:123249.3-123263.6" + wire $1\SHIFT_ROT__write_cr0[0:0] + attribute \src "libresoc.v:123174.18-123174.113" + wire $and$libresoc.v:123174$4707_Y + attribute \src "libresoc.v:123176.18-123176.110" + wire $and$libresoc.v:123176$4709_Y + attribute \src "libresoc.v:123189.18-123189.114" + wire $and$libresoc.v:123189$4722_Y + attribute \src "libresoc.v:123190.18-123190.116" + wire $and$libresoc.v:123190$4723_Y + attribute \src "libresoc.v:123192.18-123192.114" + wire $and$libresoc.v:123192$4725_Y + attribute \src "libresoc.v:123194.18-123194.110" + wire $and$libresoc.v:123194$4727_Y + attribute \src "libresoc.v:123195.17-123195.112" + wire $and$libresoc.v:123195$4728_Y + attribute \src "libresoc.v:123196.17-123196.114" + wire $and$libresoc.v:123196$4729_Y + attribute \src "libresoc.v:123177.18-123177.132" + wire $eq$libresoc.v:123177$4710_Y + attribute \src "libresoc.v:123178.18-123178.132" + wire $eq$libresoc.v:123178$4711_Y + attribute \src "libresoc.v:123180.18-123180.110" + wire $eq$libresoc.v:123180$4713_Y + attribute \src "libresoc.v:123181.18-123181.110" + wire $eq$libresoc.v:123181$4714_Y + attribute \src "libresoc.v:123183.18-123183.112" + wire $eq$libresoc.v:123183$4716_Y + attribute \src "libresoc.v:123184.17-123184.136" + wire $eq$libresoc.v:123184$4717_Y + attribute \src "libresoc.v:123186.18-123186.110" + wire $eq$libresoc.v:123186$4719_Y + attribute \src "libresoc.v:123188.18-123188.137" + wire $eq$libresoc.v:123188$4721_Y + attribute \src "libresoc.v:123191.18-123191.137" + wire $eq$libresoc.v:123191$4724_Y + attribute \src "libresoc.v:123197.17-123197.136" + wire $eq$libresoc.v:123197$4730_Y + attribute \src "libresoc.v:123175.18-123175.110" + wire $not$libresoc.v:123175$4708_Y + attribute \src "libresoc.v:123193.18-123193.110" + wire $not$libresoc.v:123193$4726_Y + attribute \src "libresoc.v:123179.18-123179.110" + wire $or$libresoc.v:123179$4712_Y + attribute \src "libresoc.v:123182.18-123182.110" + wire $or$libresoc.v:123182$4715_Y + attribute \src "libresoc.v:123185.18-123185.110" + wire $or$libresoc.v:123185$4718_Y + attribute \src "libresoc.v:123187.18-123187.110" + wire $or$libresoc.v:123187$4720_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" @@ -190018,22 +192549,10 @@ module \dec_SHIFT_ROT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_SHIFT_ROT_BD attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 14 \dec_SHIFT_ROT_DS attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 \dec_SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 24 \dec_SHIFT_ROT_LI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_SHIFT_ROT_OE @@ -190198,12 +192717,6 @@ module \dec_SHIFT_ROT wire \dec_SHIFT_ROT_sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 \dec_SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BFA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 \dec_bi_imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -190223,36 +192736,8 @@ module \dec_SHIFT_ROT attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 \dec_cr_out_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec_oe_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -190261,7 +192746,7 @@ module \dec_SHIFT_ROT attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in @@ -190273,64 +192758,112 @@ module \dec_SHIFT_ROT attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:122395.7-122395.15" + attribute \src "libresoc.v:122770.7-122770.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $and $and$libresoc.v:122819$4557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:123174$4707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$6 - connect \B \$20 - connect \Y $and$libresoc.v:122819$4557_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:123174$4707_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:122813$4551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:123176$4709 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010011 - connect \Y $eq$libresoc.v:122813$4551_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:123176$4709_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:122815$4553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:123189$4722 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122815$4553_Y + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:123189$4722_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:122817$4555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:123190$4723 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 6'110000 - connect \Y $eq$libresoc.v:122817$4555_Y + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:123190$4723_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:123192$4725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:123192$4725_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:123194$4727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:123194$4727_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:123195$4728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:123195$4728_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:123196$4729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:123196$4729_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - cell $eq $eq$libresoc.v:122820$4558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" + cell $eq $eq$libresoc.v:123177$4710 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190338,10 +192871,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122820$4558_Y + connect \Y $eq$libresoc.v:123177$4710_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $eq $eq$libresoc.v:122821$4559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $eq $eq$libresoc.v:123178$4711 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190349,74 +192882,161 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122821$4559_Y + connect \Y $eq$libresoc.v:123178$4711_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:123180$4713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:123180$4713_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:123181$4714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:123181$4714_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:122823$4561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:123183$4716 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr - connect \B 10'0000010010 - connect \Y $eq$libresoc.v:122823$4561_Y + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:123183$4716_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:123184$4717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:123184$4717_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:122814$4552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $eq $eq$libresoc.v:123186$4719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:123186$4719_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:123188$4721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:123188$4721_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:123191$4724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:123191$4724_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:123197$4730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:123197$4730_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:123175$4708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:123175$4708_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:123193$4726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:123193$4726_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $or $or$libresoc.v:123179$4712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$8 - connect \B \$10 - connect \Y $or$libresoc.v:122814$4552_Y + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:123179$4712_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:122816$4554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:123182$4715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$12 - connect \B \$14 - connect \Y $or$libresoc.v:122816$4554_Y + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:123182$4715_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:122818$4556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:123185$4718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$16 - connect \B \$18 - connect \Y $or$libresoc.v:122818$4556_Y + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:123185$4718_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $or $or$libresoc.v:122822$4560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $or $or$libresoc.v:123187$4720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$2 - connect \B \$4 - connect \Y $or$libresoc.v:122822$4560_Y + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:123187$4720_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122824.13-122858.4" - cell \dec$187 \dec - connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA - connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB - connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + attribute \src "libresoc.v:123198.13-123223.4" + cell \dec$162 \dec connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD - connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI - connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc @@ -190436,16 +193056,13 @@ module \dec_SHIFT_ROT connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122859.16-122870.4" - cell \dec_bi$194 \dec_bi + attribute \src "libresoc.v:123224.16-123235.4" + cell \dec_bi$165 \dec_bi connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI @@ -190458,34 +193075,8 @@ module \dec_SHIFT_ROT connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122871.19-122882.4" - cell \dec_cr_in$190 \dec_cr_in - connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA - connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB - connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC - connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI - connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:122883.20-122892.4" - cell \dec_cr_out$192 \dec_cr_out - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:122893.16-122899.4" - cell \dec_oe$189 \dec_oe + attribute \src "libresoc.v:123236.16-123242.4" + cell \dec_oe$164 \dec_oe connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op connect \oe \dec_oe_oe @@ -190493,37 +193084,95 @@ module \dec_SHIFT_ROT connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122900.16-122905.4" - cell \dec_rc$188 \dec_rc + attribute \src "libresoc.v:123243.16-123248.4" + cell \dec_rc$163 \dec_rc connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:122395.7-122395.20" - process $proc$libresoc.v:122395$4563 + attribute \src "libresoc.v:122770.7-122770.20" + process $proc$libresoc.v:122770$4734 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122906.3-122917.6" - process $proc$libresoc.v:122906$4562 + attribute \src "libresoc.v:123249.3-123263.6" + process $proc$libresoc.v:123249$4731 assign { } { } - assign $0\SHIFT_ROT__fn_unit[12:0] $1\SHIFT_ROT__fn_unit[12:0] - attribute \src "libresoc.v:122907.5-122907.29" + assign { } { } + assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0] + attribute \src "libresoc.v:123250.5-123250.29" switch \initial - attribute \src "libresoc.v:122907.9-122907.17" + attribute \src "libresoc.v:123250.9-123250.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:838" + switch \dec_SHIFT_ROT_cr_out attribute \src "libresoc.v:0.0-0.0" + case 3'001 , 3'101 + assign { } { } + assign $1\SHIFT_ROT__write_cr0[0:0] \dec_rc_rc + attribute \src "libresoc.v:0.0-0.0" + case 3'010 , 3'011 + assign { } { } + assign $1\SHIFT_ROT__write_cr0[0:0] 1'1 + case + assign $1\SHIFT_ROT__write_cr0[0:0] 1'0 + end + sync always + update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0] + end + attribute \src "libresoc.v:123264.3-123276.6" + process $proc$libresoc.v:123264$4732 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0] + attribute \src "libresoc.v:123265.5-123265.29" + switch \initial + attribute \src "libresoc.v:123265.9-123265.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\SHIFT_ROT__fn_unit[12:0] 13'0100000000000 + assign $1\SHIFT_ROT__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\SHIFT_ROT__insn_type[6:0] 7'0000000 + case + assign $1\SHIFT_ROT__insn_type[6:0] \dec_SHIFT_ROT_internal_op + end + sync always + update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0] + end + attribute \src "libresoc.v:123277.3-123291.6" + process $proc$libresoc.v:123277$4733 + assign { } { } + assign $0\SHIFT_ROT__fn_unit[12:0] $1\SHIFT_ROT__fn_unit[12:0] + attribute \src "libresoc.v:123278.5-123278.29" + switch \initial + attribute \src "libresoc.v:123278.9-123278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\SHIFT_ROT__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\SHIFT_ROT__fn_unit[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -190532,17 +193181,30 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[12:0] end - connect \$10 $eq$libresoc.v:122813$4551_Y - connect \$12 $or$libresoc.v:122814$4552_Y - connect \$14 $eq$libresoc.v:122815$4553_Y - connect \$16 $or$libresoc.v:122816$4554_Y - connect \$18 $eq$libresoc.v:122817$4555_Y - connect \$20 $or$libresoc.v:122818$4556_Y - connect \$22 $and$libresoc.v:122819$4557_Y - connect \$2 $eq$libresoc.v:122820$4558_Y - connect \$4 $eq$libresoc.v:122821$4559_Y - connect \$6 $or$libresoc.v:122822$4560_Y - connect \$8 $eq$libresoc.v:122823$4561_Y + connect \$10 $and$libresoc.v:123174$4707_Y + connect \$12 $not$libresoc.v:123175$4708_Y + connect \$14 $and$libresoc.v:123176$4709_Y + connect \$16 $eq$libresoc.v:123177$4710_Y + connect \$18 $eq$libresoc.v:123178$4711_Y + connect \$20 $or$libresoc.v:123179$4712_Y + connect \$22 $eq$libresoc.v:123180$4713_Y + connect \$24 $eq$libresoc.v:123181$4714_Y + connect \$26 $or$libresoc.v:123182$4715_Y + connect \$28 $eq$libresoc.v:123183$4716_Y + connect \$2 $eq$libresoc.v:123184$4717_Y + connect \$30 $or$libresoc.v:123185$4718_Y + connect \$32 $eq$libresoc.v:123186$4719_Y + connect \$34 $or$libresoc.v:123187$4720_Y + connect \$36 $eq$libresoc.v:123188$4721_Y + connect \$38 $and$libresoc.v:123189$4722_Y + connect \$40 $and$libresoc.v:123190$4723_Y + connect \$42 $eq$libresoc.v:123191$4724_Y + connect \$44 $and$libresoc.v:123192$4725_Y + connect \$46 $not$libresoc.v:123193$4726_Y + connect \$48 $and$libresoc.v:123194$4727_Y + connect \$4 $and$libresoc.v:123195$4728_Y + connect \$6 $and$libresoc.v:123196$4729_Y + connect \$8 $eq$libresoc.v:123197$4730_Y connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out @@ -190550,78 +193212,129 @@ module \dec_SHIFT_ROT connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_inv_a connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] - connect \SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok connect { \SHIFT_ROT__oe__ok \SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } connect { \SHIFT_ROT__rc__ok \SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } connect { \SHIFT_ROT__imm_data__ok \SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 connect \spr { \dec_SHIFT_ROT_SPR [4:0] \dec_SHIFT_ROT_SPR [9:5] } - connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out - connect \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \SHIFT_ROT__insn \dec_opcode_in end -attribute \src "libresoc.v:122946.1-123353.10" +attribute \src "libresoc.v:123315.1-123689.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" attribute \generator "nMigen" module \dec_SPR - attribute \src "libresoc.v:123328.3-123339.6" + attribute \src "libresoc.v:123665.3-123679.6" wire width 13 $0\SPR__fn_unit[12:0] - attribute \src "libresoc.v:122947.7-122947.20" + attribute \src "libresoc.v:123652.3-123664.6" + wire width 7 $0\SPR__insn_type[6:0] + attribute \src "libresoc.v:123316.7-123316.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123328.3-123339.6" + attribute \src "libresoc.v:123665.3-123679.6" wire width 13 $1\SPR__fn_unit[12:0] - attribute \src "libresoc.v:123269.18-123269.109" - wire $and$libresoc.v:123269$4570_Y - attribute \src "libresoc.v:123263.18-123263.112" - wire $eq$libresoc.v:123263$4564_Y - attribute \src "libresoc.v:123265.18-123265.112" - wire $eq$libresoc.v:123265$4566_Y - attribute \src "libresoc.v:123267.18-123267.110" - wire $eq$libresoc.v:123267$4568_Y - attribute \src "libresoc.v:123270.17-123270.125" - wire $eq$libresoc.v:123270$4571_Y - attribute \src "libresoc.v:123271.17-123271.125" - wire $eq$libresoc.v:123271$4572_Y - attribute \src "libresoc.v:123273.17-123273.111" - wire $eq$libresoc.v:123273$4574_Y - attribute \src "libresoc.v:123264.18-123264.109" - wire $or$libresoc.v:123264$4565_Y - attribute \src "libresoc.v:123266.18-123266.110" - wire $or$libresoc.v:123266$4567_Y - attribute \src "libresoc.v:123268.18-123268.110" - wire $or$libresoc.v:123268$4569_Y - attribute \src "libresoc.v:123272.17-123272.107" - wire $or$libresoc.v:123272$4573_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "libresoc.v:123652.3-123664.6" + wire width 7 $1\SPR__insn_type[6:0] + attribute \src "libresoc.v:123606.18-123606.113" + wire $and$libresoc.v:123606$4735_Y + attribute \src "libresoc.v:123608.18-123608.110" + wire $and$libresoc.v:123608$4737_Y + attribute \src "libresoc.v:123621.18-123621.114" + wire $and$libresoc.v:123621$4750_Y + attribute \src "libresoc.v:123622.18-123622.116" + wire $and$libresoc.v:123622$4751_Y + attribute \src "libresoc.v:123624.18-123624.114" + wire $and$libresoc.v:123624$4753_Y + attribute \src "libresoc.v:123626.18-123626.110" + wire $and$libresoc.v:123626$4755_Y + attribute \src "libresoc.v:123627.17-123627.112" + wire $and$libresoc.v:123627$4756_Y + attribute \src "libresoc.v:123628.17-123628.114" + wire $and$libresoc.v:123628$4757_Y + attribute \src "libresoc.v:123609.18-123609.126" + wire $eq$libresoc.v:123609$4738_Y + attribute \src "libresoc.v:123610.18-123610.126" + wire $eq$libresoc.v:123610$4739_Y + attribute \src "libresoc.v:123612.18-123612.110" + wire $eq$libresoc.v:123612$4741_Y + attribute \src "libresoc.v:123613.18-123613.110" + wire $eq$libresoc.v:123613$4742_Y + attribute \src "libresoc.v:123615.18-123615.112" + wire $eq$libresoc.v:123615$4744_Y + attribute \src "libresoc.v:123616.17-123616.130" + wire $eq$libresoc.v:123616$4745_Y + attribute \src "libresoc.v:123618.18-123618.110" + wire $eq$libresoc.v:123618$4747_Y + attribute \src "libresoc.v:123620.18-123620.131" + wire $eq$libresoc.v:123620$4749_Y + attribute \src "libresoc.v:123623.18-123623.131" + wire $eq$libresoc.v:123623$4752_Y + attribute \src "libresoc.v:123629.17-123629.130" + wire $eq$libresoc.v:123629$4758_Y + attribute \src "libresoc.v:123607.18-123607.110" + wire $not$libresoc.v:123607$4736_Y + attribute \src "libresoc.v:123625.18-123625.110" + wire $not$libresoc.v:123625$4754_Y + attribute \src "libresoc.v:123611.18-123611.110" + wire $or$libresoc.v:123611$4740_Y + attribute \src "libresoc.v:123614.18-123614.110" + wire $or$libresoc.v:123614$4743_Y + attribute \src "libresoc.v:123617.18-123617.110" + wire $or$libresoc.v:123617$4746_Y + attribute \src "libresoc.v:123619.18-123619.110" + wire $or$libresoc.v:123619$4748_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + wire \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" wire \$8 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" @@ -190722,34 +193435,11 @@ module \dec_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" wire input 1 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 \dec_SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 \dec_SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_SPR_OE attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire \dec_SPR_Rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 10 \dec_SPR_SPR - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 3 \dec_SPR_cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -190859,110 +193549,124 @@ module \dec_SPR attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 2 \dec_SPR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 \dec_cr_out_sel_in attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:122947.7-122947.15" + attribute \src "libresoc.v:123316.7-123316.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:437" wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474" wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:802" + wire \is_mmu_spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:801" + wire \is_spr_mv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 input 6 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:796" wire width 10 \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $and $and$libresoc.v:123269$4570 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:123606$4735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$6 - connect \B \$20 - connect \Y $and$libresoc.v:123269$4570_Y + connect \A \is_spr_mv + connect \B \$8 + connect \Y $and$libresoc.v:123606$4735_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:123263$4564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:123608$4737 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000010011 - connect \Y $eq$libresoc.v:123263$4564_Y + connect \A \$10 + connect \B \$12 + connect \Y $and$libresoc.v:123608$4737_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:123265$4566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:123621$4750 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 10 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'1011010000 - connect \Y $eq$libresoc.v:123265$4566_Y + connect \A \is_spr_mv + connect \B \$36 + connect \Y $and$libresoc.v:123621$4750_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:123267$4568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:123622$4751 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr - connect \B 6'110000 - connect \Y $eq$libresoc.v:123267$4568_Y + connect \A \$38 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:123622$4751_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - cell $eq $eq$libresoc.v:123270$4571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:123624$4753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$42 + connect \Y $and$libresoc.v:123624$4753_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $and $and$libresoc.v:123626$4755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:123626$4755_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:123627$4756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_spr_mv + connect \B \$2 + connect \Y $and$libresoc.v:123627$4756_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $and $and$libresoc.v:123628$4757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \B \is_mmu_spr + connect \Y $and$libresoc.v:123628$4757_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:803" + cell $eq $eq$libresoc.v:123609$4738 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190970,10 +193674,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:123270$4571_Y + connect \Y $eq$libresoc.v:123609$4738_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $eq $eq$libresoc.v:123271$4572 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $eq $eq$libresoc.v:123610$4739 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190981,151 +193685,239 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:123271$4572_Y + connect \Y $eq$libresoc.v:123610$4739_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:123612$4741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10010 + connect \Y $eq$libresoc.v:123612$4741_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:123613$4742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 5'10011 + connect \Y $eq$libresoc.v:123613$4742_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $eq$libresoc.v:123273$4574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $eq $eq$libresoc.v:123615$4744 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \spr - connect \B 10'0000010010 - connect \Y $eq$libresoc.v:123273$4574_Y + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:123615$4744_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:123616$4745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:123616$4745_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $eq $eq$libresoc.v:123618$4747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:123618$4747_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + cell $eq $eq$libresoc.v:123620$4749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_function_unit + connect \B 13'0010000000000 + connect \Y $eq$libresoc.v:123620$4749_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:123623$4752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:123623$4752_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $eq $eq$libresoc.v:123629$4758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_function_unit + connect \B 13'0100000000000 + connect \Y $eq$libresoc.v:123629$4758_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:123607$4736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:123607$4736_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:123264$4565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:814" + cell $not $not$libresoc.v:123625$4754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_mmu_spr + connect \Y $not$libresoc.v:123625$4754_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:804" + cell $or $or$libresoc.v:123611$4740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$8 - connect \B \$10 - connect \Y $or$libresoc.v:123264$4565_Y + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:123611$4740_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:123266$4567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:123614$4743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$12 - connect \B \$14 - connect \Y $or$libresoc.v:123266$4567_Y + connect \A \$22 + connect \B \$24 + connect \Y $or$libresoc.v:123614$4743_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $or $or$libresoc.v:123268$4569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:807" + cell $or $or$libresoc.v:123617$4746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$16 - connect \B \$18 - connect \Y $or$libresoc.v:123268$4569_Y + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:123617$4746_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" - cell $or $or$libresoc.v:123272$4573 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" + cell $or $or$libresoc.v:123619$4748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$2 - connect \B \$4 - connect \Y $or$libresoc.v:123272$4573_Y + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:123619$4748_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:123274.13-123296.4" - cell \dec$163 \dec - connect \SPR_BA \dec_SPR_BA - connect \SPR_BB \dec_SPR_BB - connect \SPR_BC \dec_SPR_BC - connect \SPR_BI \dec_SPR_BI - connect \SPR_BT \dec_SPR_BT - connect \SPR_FXM \dec_SPR_FXM + attribute \src "libresoc.v:123630.13-123642.4" + cell \dec$150 \dec connect \SPR_OE \dec_SPR_OE connect \SPR_Rc \dec_SPR_Rc connect \SPR_SPR \dec_SPR_SPR - connect \SPR_cr_in \dec_SPR_cr_in connect \SPR_cr_out \dec_SPR_cr_out connect \SPR_function_unit \dec_SPR_function_unit connect \SPR_internal_op \dec_SPR_internal_op connect \SPR_is_32b \dec_SPR_is_32b connect \SPR_rc_sel \dec_SPR_rc_sel - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA connect \bigendian \bigendian connect \opcode_in \dec_opcode_in connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123297.19-123308.4" - cell \dec_cr_in$166 \dec_cr_in - connect \SPR_BA \dec_SPR_BA - connect \SPR_BB \dec_SPR_BB - connect \SPR_BC \dec_SPR_BC - connect \SPR_BI \dec_SPR_BI - connect \SPR_BT \dec_SPR_BT - connect \SPR_FXM \dec_SPR_FXM - connect \SPR_internal_op \dec_SPR_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:123309.20-123317.4" - cell \dec_cr_out$168 \dec_cr_out - connect \SPR_FXM \dec_SPR_FXM - connect \SPR_internal_op \dec_SPR_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:123318.16-123322.4" - cell \dec_oe$165 \dec_oe + attribute \src "libresoc.v:123643.16-123647.4" + cell \dec_oe$152 \dec_oe connect \SPR_OE \dec_SPR_OE connect \SPR_internal_op \dec_SPR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123323.16-123327.4" - cell \dec_rc$164 \dec_rc + attribute \src "libresoc.v:123648.16-123651.4" + cell \dec_rc$151 \dec_rc connect \SPR_Rc \dec_SPR_Rc - connect \rc \dec_rc_rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:122947.7-122947.20" - process $proc$libresoc.v:122947$4576 + attribute \src "libresoc.v:123316.7-123316.20" + process $proc$libresoc.v:123316$4761 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123328.3-123339.6" - process $proc$libresoc.v:123328$4575 + attribute \src "libresoc.v:123652.3-123664.6" + process $proc$libresoc.v:123652$4759 assign { } { } - assign $0\SPR__fn_unit[12:0] $1\SPR__fn_unit[12:0] - attribute \src "libresoc.v:123329.5-123329.29" + assign { } { } + assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0] + attribute \src "libresoc.v:123653.5-123653.29" switch \initial - attribute \src "libresoc.v:123329.9-123329.17" + attribute \src "libresoc.v:123653.9-123653.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$14 \$6 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\SPR__insn_type[6:0] 7'0000000 attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\SPR__insn_type[6:0] 7'0000000 + case + assign $1\SPR__insn_type[6:0] \dec_SPR_internal_op + end + sync always + update \SPR__insn_type $0\SPR__insn_type[6:0] + end + attribute \src "libresoc.v:123665.3-123679.6" + process $proc$libresoc.v:123665$4760 + assign { } { } + assign $0\SPR__fn_unit[12:0] $1\SPR__fn_unit[12:0] + attribute \src "libresoc.v:123666.5-123666.29" + switch \initial + attribute \src "libresoc.v:123666.9-123666.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:810" + switch { \$48 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } - assign $1\SPR__fn_unit[12:0] 13'0100000000000 + assign $1\SPR__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\SPR__fn_unit[12:0] 13'0000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -191134,141 +193926,150 @@ module \dec_SPR sync always update \SPR__fn_unit $0\SPR__fn_unit[12:0] end - connect \$10 $eq$libresoc.v:123263$4564_Y - connect \$12 $or$libresoc.v:123264$4565_Y - connect \$14 $eq$libresoc.v:123265$4566_Y - connect \$16 $or$libresoc.v:123266$4567_Y - connect \$18 $eq$libresoc.v:123267$4568_Y - connect \$20 $or$libresoc.v:123268$4569_Y - connect \$22 $and$libresoc.v:123269$4570_Y - connect \$2 $eq$libresoc.v:123270$4571_Y - connect \$4 $eq$libresoc.v:123271$4572_Y - connect \$6 $or$libresoc.v:123272$4573_Y - connect \$8 $eq$libresoc.v:123273$4574_Y + connect \$10 $and$libresoc.v:123606$4735_Y + connect \$12 $not$libresoc.v:123607$4736_Y + connect \$14 $and$libresoc.v:123608$4737_Y + connect \$16 $eq$libresoc.v:123609$4738_Y + connect \$18 $eq$libresoc.v:123610$4739_Y + connect \$20 $or$libresoc.v:123611$4740_Y + connect \$22 $eq$libresoc.v:123612$4741_Y + connect \$24 $eq$libresoc.v:123613$4742_Y + connect \$26 $or$libresoc.v:123614$4743_Y + connect \$28 $eq$libresoc.v:123615$4744_Y + connect \$2 $eq$libresoc.v:123616$4745_Y + connect \$30 $or$libresoc.v:123617$4746_Y + connect \$32 $eq$libresoc.v:123618$4747_Y + connect \$34 $or$libresoc.v:123619$4748_Y + connect \$36 $eq$libresoc.v:123620$4749_Y + connect \$38 $and$libresoc.v:123621$4750_Y + connect \$40 $and$libresoc.v:123622$4751_Y + connect \$42 $eq$libresoc.v:123623$4752_Y + connect \$44 $and$libresoc.v:123624$4753_Y + connect \$46 $not$libresoc.v:123625$4754_Y + connect \$48 $and$libresoc.v:123626$4755_Y + connect \$4 $and$libresoc.v:123627$4756_Y + connect \$6 $and$libresoc.v:123628$4757_Y + connect \$8 $eq$libresoc.v:123629$4758_Y connect \SPR__is_32bit \dec_SPR_is_32b + connect \is_mmu_spr \$34 + connect \is_spr_mv \$20 connect \spr { \dec_SPR_SPR [4:0] \dec_SPR_SPR [9:5] } - connect \SPR__insn_type \dec_SPR_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_SPR_cr_out - connect \dec_cr_in_sel_in \dec_SPR_cr_in connect \dec_oe_sel_in \dec_SPR_rc_sel connect \dec_rc_sel_in \dec_SPR_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in connect \insn_in$1 \dec_opcode_in connect \insn_in \dec_opcode_in connect \SPR__insn \dec_opcode_in end -attribute \src "libresoc.v:123357.1-123869.10" +attribute \src "libresoc.v:123693.1-124207.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" attribute \generator "nMigen" module \dec_a - attribute \src "libresoc.v:123797.3-123832.6" + attribute \src "libresoc.v:124135.3-124170.6" wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:123797.3-123832.6" + attribute \src "libresoc.v:124135.3-124170.6" wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:123358.7-123358.20" + attribute \src "libresoc.v:123694.7-123694.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123765.3-123780.6" + attribute \src "libresoc.v:124103.3-124118.6" wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:123781.3-123796.6" + attribute \src "libresoc.v:124119.3-124134.6" wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:123833.3-123843.6" + attribute \src "libresoc.v:124171.3-124181.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:123855.3-123866.6" + attribute \src "libresoc.v:124193.3-124204.6" wire width 10 $0\spr_a[9:0] - attribute \src "libresoc.v:123855.3-123866.6" + attribute \src "libresoc.v:124193.3-124204.6" wire $0\spr_a_ok[0:0] - attribute \src "libresoc.v:123844.3-123854.6" + attribute \src "libresoc.v:124182.3-124192.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:123797.3-123832.6" + attribute \src "libresoc.v:124135.3-124170.6" wire width 3 $1\fast_a[2:0] - attribute \src "libresoc.v:123797.3-123832.6" + attribute \src "libresoc.v:124135.3-124170.6" wire $1\fast_a_ok[0:0] - attribute \src "libresoc.v:123765.3-123780.6" + attribute \src "libresoc.v:124103.3-124118.6" wire width 5 $1\reg_a[4:0] - attribute \src "libresoc.v:123781.3-123796.6" + attribute \src "libresoc.v:124119.3-124134.6" wire $1\reg_a_ok[0:0] - attribute \src "libresoc.v:123833.3-123843.6" + attribute \src "libresoc.v:124171.3-124181.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:123855.3-123866.6" + attribute \src "libresoc.v:124193.3-124204.6" wire width 10 $1\spr_a[9:0] - attribute \src "libresoc.v:123855.3-123866.6" + attribute \src "libresoc.v:124193.3-124204.6" wire $1\spr_a_ok[0:0] - attribute \src "libresoc.v:123844.3-123854.6" + attribute \src "libresoc.v:124182.3-124192.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:123797.3-123832.6" + attribute \src "libresoc.v:124135.3-124170.6" wire width 3 $2\fast_a[2:0] - attribute \src "libresoc.v:123797.3-123832.6" + attribute \src "libresoc.v:124135.3-124170.6" wire $2\fast_a_ok[0:0] - attribute \src "libresoc.v:123765.3-123780.6" + attribute \src "libresoc.v:124103.3-124118.6" wire width 5 $2\reg_a[4:0] - attribute \src "libresoc.v:123781.3-123796.6" + attribute \src "libresoc.v:124119.3-124134.6" wire $2\reg_a_ok[0:0] - attribute \src "libresoc.v:123797.3-123832.6" + attribute \src "libresoc.v:124135.3-124170.6" wire width 3 $3\fast_a[2:0] - attribute \src "libresoc.v:123797.3-123832.6" + attribute \src "libresoc.v:124135.3-124170.6" wire $3\fast_a_ok[0:0] - attribute \src "libresoc.v:123749.18-123749.110" - wire $and$libresoc.v:123749$4583_Y - attribute \src "libresoc.v:123754.18-123754.113" - wire $and$libresoc.v:123754$4588_Y - attribute \src "libresoc.v:123757.17-123757.107" - wire $and$libresoc.v:123757$4591_Y - attribute \src "libresoc.v:123744.18-123744.112" - wire $eq$libresoc.v:123744$4578_Y - attribute \src "libresoc.v:123745.18-123745.112" - wire $eq$libresoc.v:123745$4579_Y - attribute \src "libresoc.v:123746.18-123746.112" - wire $eq$libresoc.v:123746$4580_Y - attribute \src "libresoc.v:123748.17-123748.111" - wire $eq$libresoc.v:123748$4582_Y - attribute \src "libresoc.v:123751.18-123751.112" - wire $eq$libresoc.v:123751$4585_Y - attribute \src "libresoc.v:123755.17-123755.111" - wire $eq$libresoc.v:123755$4589_Y - attribute \src "libresoc.v:123747.18-123747.109" - wire $ne$libresoc.v:123747$4581_Y - attribute \src "libresoc.v:123756.17-123756.108" - wire $ne$libresoc.v:123756$4590_Y - attribute \src "libresoc.v:123752.18-123752.105" - wire $not$libresoc.v:123752$4586_Y - attribute \src "libresoc.v:123753.18-123753.108" - wire $not$libresoc.v:123753$4587_Y - attribute \src "libresoc.v:123743.17-123743.107" - wire $or$libresoc.v:123743$4577_Y - attribute \src "libresoc.v:123750.18-123750.110" - wire $or$libresoc.v:123750$4584_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "libresoc.v:124087.18-124087.110" + wire $and$libresoc.v:124087$4768_Y + attribute \src "libresoc.v:124092.18-124092.113" + wire $and$libresoc.v:124092$4773_Y + attribute \src "libresoc.v:124095.17-124095.107" + wire $and$libresoc.v:124095$4776_Y + attribute \src "libresoc.v:124082.18-124082.112" + wire $eq$libresoc.v:124082$4763_Y + attribute \src "libresoc.v:124083.18-124083.112" + wire $eq$libresoc.v:124083$4764_Y + attribute \src "libresoc.v:124084.18-124084.112" + wire $eq$libresoc.v:124084$4765_Y + attribute \src "libresoc.v:124086.17-124086.111" + wire $eq$libresoc.v:124086$4767_Y + attribute \src "libresoc.v:124089.18-124089.112" + wire $eq$libresoc.v:124089$4770_Y + attribute \src "libresoc.v:124093.17-124093.111" + wire $eq$libresoc.v:124093$4774_Y + attribute \src "libresoc.v:124085.18-124085.109" + wire $ne$libresoc.v:124085$4766_Y + attribute \src "libresoc.v:124094.17-124094.108" + wire $ne$libresoc.v:124094$4775_Y + attribute \src "libresoc.v:124090.18-124090.105" + wire $not$libresoc.v:124090$4771_Y + attribute \src "libresoc.v:124091.18-124091.108" + wire $not$libresoc.v:124091$4772_Y + attribute \src "libresoc.v:124081.17-124081.107" + wire $or$libresoc.v:124081$4762_Y + attribute \src "libresoc.v:124088.18-124088.110" + wire $or$libresoc.v:124088$4769_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 11 \BO @@ -191284,7 +194085,7 @@ module \dec_a wire width 3 output 7 \fast_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 8 \fast_a_ok - attribute \src "libresoc.v:123358.7-123358.15" + attribute \src "libresoc.v:123694.7-123694.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -191362,13 +194163,13 @@ module \dec_a attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" wire width 7 input 13 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108" wire width 5 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 3 \reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \reg_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" wire width 5 \rs attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -191376,9 +194177,9 @@ module \dec_a attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" wire width 3 input 2 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -191446,7 +194247,8 @@ module \dec_a attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -191501,7 +194303,7 @@ module \dec_a wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" wire width 10 \sprmap_spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -191569,7 +194371,8 @@ module \dec_a attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -191620,8 +194423,8 @@ module \dec_a wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" - cell $and $and$libresoc.v:123749$4583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $and $and$libresoc.v:124087$4768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191629,10 +194432,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 - connect \Y $and$libresoc.v:123749$4583_Y + connect \Y $and$libresoc.v:124087$4768_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $and $and$libresoc.v:123754$4588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" + cell $and $and$libresoc.v:124092$4773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191640,10 +194443,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \XL_XO [9] connect \B \$27 - connect \Y $and$libresoc.v:123754$4588_Y + connect \Y $and$libresoc.v:124092$4773_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" - cell $and $and$libresoc.v:123757$4591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $and $and$libresoc.v:124095$4776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191651,10 +194454,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:123757$4591_Y + connect \Y $and$libresoc.v:124095$4776_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $eq $eq$libresoc.v:123744$4578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" + cell $eq $eq$libresoc.v:124082$4763 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -191662,10 +194465,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:123744$4578_Y + connect \Y $eq$libresoc.v:124082$4763_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $eq $eq$libresoc.v:123745$4579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + cell $eq $eq$libresoc.v:124083$4764 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -191673,10 +194476,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:123745$4579_Y + connect \Y $eq$libresoc.v:124083$4764_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $eq $eq$libresoc.v:123746$4580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" + cell $eq $eq$libresoc.v:124084$4765 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -191684,10 +194487,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:123746$4580_Y + connect \Y $eq$libresoc.v:124084$4765_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $eq $eq$libresoc.v:123748$4582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + cell $eq $eq$libresoc.v:124086$4767 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -191695,10 +194498,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:123748$4582_Y + connect \Y $eq$libresoc.v:124086$4767_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - cell $eq $eq$libresoc.v:123751$4585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" + cell $eq $eq$libresoc.v:124089$4770 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -191706,10 +194509,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:123751$4585_Y + connect \Y $eq$libresoc.v:124089$4770_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $eq $eq$libresoc.v:123755$4589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" + cell $eq $eq$libresoc.v:124093$4774 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -191717,10 +194520,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:123755$4589_Y + connect \Y $eq$libresoc.v:124093$4774_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" - cell $ne $ne$libresoc.v:123747$4581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $ne $ne$libresoc.v:124085$4766 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -191728,10 +194531,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:123747$4581_Y + connect \Y $ne$libresoc.v:124085$4766_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" - cell $ne $ne$libresoc.v:123756$4590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $ne $ne$libresoc.v:124094$4775 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -191739,26 +194542,26 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:123756$4590_Y + connect \Y $ne$libresoc.v:124094$4775_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" - cell $not $not$libresoc.v:123752$4586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" + cell $not $not$libresoc.v:124090$4771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:123752$4586_Y + connect \Y $not$libresoc.v:124090$4771_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $not $not$libresoc.v:123753$4587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" + cell $not $not$libresoc.v:124091$4772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [5] - connect \Y $not$libresoc.v:123753$4587_Y + connect \Y $not$libresoc.v:124091$4772_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" - cell $or $or$libresoc.v:123743$4577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $or $or$libresoc.v:124081$4762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191766,10 +194569,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$1 connect \B \$7 - connect \Y $or$libresoc.v:123743$4577_Y + connect \Y $or$libresoc.v:124081$4762_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" - cell $or $or$libresoc.v:123750$4584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + cell $or $or$libresoc.v:124088$4769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191777,10 +194580,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$13 connect \B \$19 - connect \Y $or$libresoc.v:123750$4584_Y + connect \Y $or$libresoc.v:124088$4769_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:123758.10-123764.4" + attribute \src "libresoc.v:124096.10-124102.4" cell \sprmap \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -191788,27 +194591,27 @@ module \dec_a connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:123358.7-123358.20" - process $proc$libresoc.v:123358$4598 + attribute \src "libresoc.v:123694.7-123694.20" + process $proc$libresoc.v:123694$4783 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123765.3-123780.6" - process $proc$libresoc.v:123765$4592 + attribute \src "libresoc.v:124103.3-124118.6" + process $proc$libresoc.v:124103$4777 assign { } { } assign { } { } assign { } { } assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:123766.5-123766.29" + attribute \src "libresoc.v:124104.5-124104.29" switch \initial - attribute \src "libresoc.v:123766.9-123766.17" + attribute \src "libresoc.v:124104.9-124104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -191817,7 +194620,7 @@ module \dec_a case assign $1\reg_a[4:0] 5'00000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -191829,19 +194632,19 @@ module \dec_a sync always update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:123781.3-123796.6" - process $proc$libresoc.v:123781$4593 + attribute \src "libresoc.v:124119.3-124134.6" + process $proc$libresoc.v:124119$4778 assign { } { } assign { } { } assign { } { } assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:123782.5-123782.29" + attribute \src "libresoc.v:124120.5-124120.29" switch \initial - attribute \src "libresoc.v:123782.9-123782.17" + attribute \src "libresoc.v:124120.9-124120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -191850,7 +194653,7 @@ module \dec_a case assign $1\reg_a_ok[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -191862,21 +194665,21 @@ module \dec_a sync always update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "libresoc.v:123797.3-123832.6" - process $proc$libresoc.v:123797$4594 + attribute \src "libresoc.v:124135.3-124170.6" + process $proc$libresoc.v:124135$4779 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast_a[2:0] $1\fast_a[2:0] assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:123798.5-123798.29" + attribute \src "libresoc.v:124136.5-124136.29" switch \initial - attribute \src "libresoc.v:123798.9-123798.17" + attribute \src "libresoc.v:124136.9-124136.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:125" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0000111 @@ -191884,7 +194687,7 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $2\fast_a[2:0] assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -191902,7 +194705,7 @@ module \dec_a assign { } { } assign $1\fast_a[2:0] $3\fast_a[2:0] assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -191927,18 +194730,18 @@ module \dec_a update \fast_a $0\fast_a[2:0] update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:123833.3-123843.6" - process $proc$libresoc.v:123833$4595 + attribute \src "libresoc.v:124171.3-124181.6" + process $proc$libresoc.v:124171$4780 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:123834.5-123834.29" + attribute \src "libresoc.v:124172.5-124172.29" switch \initial - attribute \src "libresoc.v:123834.9-123834.17" + attribute \src "libresoc.v:124172.9-124172.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:125" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -191950,18 +194753,18 @@ module \dec_a sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:123844.3-123854.6" - process $proc$libresoc.v:123844$4596 + attribute \src "libresoc.v:124182.3-124192.6" + process $proc$libresoc.v:124182$4781 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:123845.5-123845.29" + attribute \src "libresoc.v:124183.5-124183.29" switch \initial - attribute \src "libresoc.v:123845.9-123845.17" + attribute \src "libresoc.v:124183.9-124183.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:125" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -191973,21 +194776,21 @@ module \dec_a sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:123855.3-123866.6" - process $proc$libresoc.v:123855$4597 + attribute \src "libresoc.v:124193.3-124204.6" + process $proc$libresoc.v:124193$4782 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_a[9:0] $1\spr_a[9:0] assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:123856.5-123856.29" + attribute \src "libresoc.v:124194.5-124194.29" switch \initial - attribute \src "libresoc.v:123856.9-123856.17" + attribute \src "libresoc.v:124194.9-124194.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:125" switch \internal_op attribute \src "libresoc.v:0.0-0.0" case 7'0101110 @@ -192002,54 +194805,54 @@ module \dec_a update \spr_a $0\spr_a[9:0] update \spr_a_ok $0\spr_a_ok[0:0] end - connect \$9 $or$libresoc.v:123743$4577_Y - connect \$11 $eq$libresoc.v:123744$4578_Y - connect \$13 $eq$libresoc.v:123745$4579_Y - connect \$15 $eq$libresoc.v:123746$4580_Y - connect \$17 $ne$libresoc.v:123747$4581_Y - connect \$1 $eq$libresoc.v:123748$4582_Y - connect \$19 $and$libresoc.v:123749$4583_Y - connect \$21 $or$libresoc.v:123750$4584_Y - connect \$23 $eq$libresoc.v:123751$4585_Y - connect \$25 $not$libresoc.v:123752$4586_Y - connect \$27 $not$libresoc.v:123753$4587_Y - connect \$29 $and$libresoc.v:123754$4588_Y - connect \$3 $eq$libresoc.v:123755$4589_Y - connect \$5 $ne$libresoc.v:123756$4590_Y - connect \$7 $and$libresoc.v:123757$4591_Y + connect \$9 $or$libresoc.v:124081$4762_Y + connect \$11 $eq$libresoc.v:124082$4763_Y + connect \$13 $eq$libresoc.v:124083$4764_Y + connect \$15 $eq$libresoc.v:124084$4765_Y + connect \$17 $ne$libresoc.v:124085$4766_Y + connect \$1 $eq$libresoc.v:124086$4767_Y + connect \$19 $and$libresoc.v:124087$4768_Y + connect \$21 $or$libresoc.v:124088$4769_Y + connect \$23 $eq$libresoc.v:124089$4770_Y + connect \$25 $not$libresoc.v:124090$4771_Y + connect \$27 $not$libresoc.v:124091$4772_Y + connect \$29 $and$libresoc.v:124092$4773_Y + connect \$3 $eq$libresoc.v:124093$4774_Y + connect \$5 $ne$libresoc.v:124094$4775_Y + connect \$7 $and$libresoc.v:124095$4776_Y connect \rs \RS connect \ra \RA end -attribute \src "libresoc.v:123873.1-123910.10" +attribute \src "libresoc.v:124211.1-124248.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" attribute \generator "nMigen" module \dec_ai - attribute \src "libresoc.v:123899.3-123908.6" + attribute \src "libresoc.v:124237.3-124246.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:123874.7-123874.20" + attribute \src "libresoc.v:124212.7-124212.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123899.3-123908.6" + attribute \src "libresoc.v:124237.3-124246.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:123898.17-123898.107" - wire $and$libresoc.v:123898$4601_Y - attribute \src "libresoc.v:123896.17-123896.111" - wire $eq$libresoc.v:123896$4599_Y - attribute \src "libresoc.v:123897.17-123897.108" - wire $eq$libresoc.v:123897$4600_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "libresoc.v:124236.17-124236.107" + wire $and$libresoc.v:124236$4786_Y + attribute \src "libresoc.v:124234.17-124234.111" + wire $eq$libresoc.v:124234$4784_Y + attribute \src "libresoc.v:124235.17-124235.108" + wire $eq$libresoc.v:124235$4785_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 2 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire output 1 \immz_out - attribute \src "libresoc.v:123874.7-123874.15" + attribute \src "libresoc.v:124212.7-124212.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -192057,10 +194860,10 @@ module \dec_ai attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $and $and$libresoc.v:123898$4601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $and $and$libresoc.v:124236$4786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192068,10 +194871,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:123898$4601_Y + connect \Y $and$libresoc.v:124236$4786_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $eq $eq$libresoc.v:123896$4599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $eq $eq$libresoc.v:124234$4784 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192079,10 +194882,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:123896$4599_Y + connect \Y $eq$libresoc.v:124234$4784_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $eq $eq$libresoc.v:123897$4600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $eq $eq$libresoc.v:124235$4785 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -192090,28 +194893,28 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:123897$4600_Y + connect \Y $eq$libresoc.v:124235$4785_Y end - attribute \src "libresoc.v:123874.7-123874.20" - process $proc$libresoc.v:123874$4603 + attribute \src "libresoc.v:124212.7-124212.20" + process $proc$libresoc.v:124212$4788 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123899.3-123908.6" - process $proc$libresoc.v:123899$4602 + attribute \src "libresoc.v:124237.3-124246.6" + process $proc$libresoc.v:124237$4787 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:123900.5-123900.29" + attribute \src "libresoc.v:124238.5-124238.29" switch \initial - attribute \src "libresoc.v:123900.9-123900.17" + attribute \src "libresoc.v:124238.9-124238.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -192123,41 +194926,41 @@ module \dec_ai sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:123896$4599_Y - connect \$3 $eq$libresoc.v:123897$4600_Y - connect \$5 $and$libresoc.v:123898$4601_Y + connect \$1 $eq$libresoc.v:124234$4784_Y + connect \$3 $eq$libresoc.v:124235$4785_Y + connect \$5 $and$libresoc.v:124236$4786_Y connect \ra \ALU_RA end -attribute \src "libresoc.v:123914.1-123951.10" +attribute \src "libresoc.v:124252.1-124289.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" attribute \generator "nMigen" -module \dec_ai$161 - attribute \src "libresoc.v:123940.3-123949.6" +module \dec_ai$148 + attribute \src "libresoc.v:124278.3-124287.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:123915.7-123915.20" + attribute \src "libresoc.v:124253.7-124253.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123940.3-123949.6" + attribute \src "libresoc.v:124278.3-124287.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:123939.17-123939.107" - wire $and$libresoc.v:123939$4606_Y - attribute \src "libresoc.v:123937.17-123937.111" - wire $eq$libresoc.v:123937$4604_Y - attribute \src "libresoc.v:123938.17-123938.108" - wire $eq$libresoc.v:123938$4605_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "libresoc.v:124277.17-124277.107" + wire $and$libresoc.v:124277$4791_Y + attribute \src "libresoc.v:124275.17-124275.111" + wire $eq$libresoc.v:124275$4789_Y + attribute \src "libresoc.v:124276.17-124276.108" + wire $eq$libresoc.v:124276$4790_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 2 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire output 1 \immz_out - attribute \src "libresoc.v:123915.7-123915.15" + attribute \src "libresoc.v:124253.7-124253.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -192165,10 +194968,10 @@ module \dec_ai$161 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $and $and$libresoc.v:123939$4606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $and $and$libresoc.v:124277$4791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192176,10 +194979,10 @@ module \dec_ai$161 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:123939$4606_Y + connect \Y $and$libresoc.v:124277$4791_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $eq $eq$libresoc.v:123937$4604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $eq $eq$libresoc.v:124275$4789 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192187,10 +194990,10 @@ module \dec_ai$161 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:123937$4604_Y + connect \Y $eq$libresoc.v:124275$4789_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $eq $eq$libresoc.v:123938$4605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $eq $eq$libresoc.v:124276$4790 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -192198,28 +195001,28 @@ module \dec_ai$161 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:123938$4605_Y + connect \Y $eq$libresoc.v:124276$4790_Y end - attribute \src "libresoc.v:123915.7-123915.20" - process $proc$libresoc.v:123915$4608 + attribute \src "libresoc.v:124253.7-124253.20" + process $proc$libresoc.v:124253$4793 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123940.3-123949.6" - process $proc$libresoc.v:123940$4607 + attribute \src "libresoc.v:124278.3-124287.6" + process $proc$libresoc.v:124278$4792 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:123941.5-123941.29" + attribute \src "libresoc.v:124279.5-124279.29" switch \initial - attribute \src "libresoc.v:123941.9-123941.17" + attribute \src "libresoc.v:124279.9-124279.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -192231,41 +195034,41 @@ module \dec_ai$161 sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:123937$4604_Y - connect \$3 $eq$libresoc.v:123938$4605_Y - connect \$5 $and$libresoc.v:123939$4606_Y + connect \$1 $eq$libresoc.v:124275$4789_Y + connect \$3 $eq$libresoc.v:124276$4790_Y + connect \$5 $and$libresoc.v:124277$4791_Y connect \ra \LOGICAL_RA end -attribute \src "libresoc.v:123955.1-123992.10" +attribute \src "libresoc.v:124293.1-124330.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" attribute \generator "nMigen" -module \dec_ai$177 - attribute \src "libresoc.v:123981.3-123990.6" +module \dec_ai$156 + attribute \src "libresoc.v:124319.3-124328.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:123956.7-123956.20" + attribute \src "libresoc.v:124294.7-124294.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123981.3-123990.6" + attribute \src "libresoc.v:124319.3-124328.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:123980.17-123980.107" - wire $and$libresoc.v:123980$4611_Y - attribute \src "libresoc.v:123978.17-123978.111" - wire $eq$libresoc.v:123978$4609_Y - attribute \src "libresoc.v:123979.17-123979.108" - wire $eq$libresoc.v:123979$4610_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "libresoc.v:124318.17-124318.107" + wire $and$libresoc.v:124318$4796_Y + attribute \src "libresoc.v:124316.17-124316.111" + wire $eq$libresoc.v:124316$4794_Y + attribute \src "libresoc.v:124317.17-124317.108" + wire $eq$libresoc.v:124317$4795_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 2 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire output 1 \immz_out - attribute \src "libresoc.v:123956.7-123956.15" + attribute \src "libresoc.v:124294.7-124294.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -192273,10 +195076,10 @@ module \dec_ai$177 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $and $and$libresoc.v:123980$4611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $and $and$libresoc.v:124318$4796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192284,10 +195087,10 @@ module \dec_ai$177 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:123980$4611_Y + connect \Y $and$libresoc.v:124318$4796_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $eq $eq$libresoc.v:123978$4609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $eq $eq$libresoc.v:124316$4794 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192295,10 +195098,10 @@ module \dec_ai$177 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:123978$4609_Y + connect \Y $eq$libresoc.v:124316$4794_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $eq $eq$libresoc.v:123979$4610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $eq $eq$libresoc.v:124317$4795 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -192306,28 +195109,28 @@ module \dec_ai$177 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:123979$4610_Y + connect \Y $eq$libresoc.v:124317$4795_Y end - attribute \src "libresoc.v:123956.7-123956.20" - process $proc$libresoc.v:123956$4613 + attribute \src "libresoc.v:124294.7-124294.20" + process $proc$libresoc.v:124294$4798 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123981.3-123990.6" - process $proc$libresoc.v:123981$4612 + attribute \src "libresoc.v:124319.3-124328.6" + process $proc$libresoc.v:124319$4797 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:123982.5-123982.29" + attribute \src "libresoc.v:124320.5-124320.29" switch \initial - attribute \src "libresoc.v:123982.9-123982.17" + attribute \src "libresoc.v:124320.9-124320.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -192339,41 +195142,41 @@ module \dec_ai$177 sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:123978$4609_Y - connect \$3 $eq$libresoc.v:123979$4610_Y - connect \$5 $and$libresoc.v:123980$4611_Y + connect \$1 $eq$libresoc.v:124316$4794_Y + connect \$3 $eq$libresoc.v:124317$4795_Y + connect \$5 $and$libresoc.v:124318$4796_Y connect \ra \DIV_RA end -attribute \src "libresoc.v:123996.1-124033.10" +attribute \src "libresoc.v:124334.1-124371.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai" attribute \generator "nMigen" -module \dec_ai$202 - attribute \src "libresoc.v:124022.3-124031.6" +module \dec_ai$169 + attribute \src "libresoc.v:124360.3-124369.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:123997.7-123997.20" + attribute \src "libresoc.v:124335.7-124335.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124022.3-124031.6" + attribute \src "libresoc.v:124360.3-124369.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:124021.17-124021.107" - wire $and$libresoc.v:124021$4616_Y - attribute \src "libresoc.v:124019.17-124019.111" - wire $eq$libresoc.v:124019$4614_Y - attribute \src "libresoc.v:124020.17-124020.108" - wire $eq$libresoc.v:124020$4615_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "libresoc.v:124359.17-124359.107" + wire $and$libresoc.v:124359$4801_Y + attribute \src "libresoc.v:124357.17-124357.111" + wire $eq$libresoc.v:124357$4799_Y + attribute \src "libresoc.v:124358.17-124358.108" + wire $eq$libresoc.v:124358$4800_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" wire \$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 2 \LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:162" wire output 1 \immz_out - attribute \src "libresoc.v:123997.7-123997.15" + attribute \src "libresoc.v:124335.7-124335.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" wire width 5 \ra attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" @@ -192381,10 +195184,10 @@ module \dec_ai$202 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" wire width 3 input 3 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $and $and$libresoc.v:124021$4616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $and $and$libresoc.v:124359$4801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192392,10 +195195,10 @@ module \dec_ai$202 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:124021$4616_Y + connect \Y $and$libresoc.v:124359$4801_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $eq $eq$libresoc.v:124019$4614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $eq $eq$libresoc.v:124357$4799 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -192403,10 +195206,10 @@ module \dec_ai$202 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:124019$4614_Y + connect \Y $eq$libresoc.v:124357$4799_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" - cell $eq $eq$libresoc.v:124020$4615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + cell $eq $eq$libresoc.v:124358$4800 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -192414,28 +195217,28 @@ module \dec_ai$202 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:124020$4615_Y + connect \Y $eq$libresoc.v:124358$4800_Y end - attribute \src "libresoc.v:123997.7-123997.20" - process $proc$libresoc.v:123997$4618 + attribute \src "libresoc.v:124335.7-124335.20" + process $proc$libresoc.v:124335$4803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124022.3-124031.6" - process $proc$libresoc.v:124022$4617 + attribute \src "libresoc.v:124360.3-124369.6" + process $proc$libresoc.v:124360$4802 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:124023.5-124023.29" + attribute \src "libresoc.v:124361.5-124361.29" switch \initial - attribute \src "libresoc.v:124023.9-124023.17" + attribute \src "libresoc.v:124361.9-124361.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -192447,65 +195250,65 @@ module \dec_ai$202 sync always update \immz_out $0\immz_out[0:0] end - connect \$1 $eq$libresoc.v:124019$4614_Y - connect \$3 $eq$libresoc.v:124020$4615_Y - connect \$5 $and$libresoc.v:124021$4616_Y + connect \$1 $eq$libresoc.v:124357$4799_Y + connect \$3 $eq$libresoc.v:124358$4800_Y + connect \$5 $and$libresoc.v:124359$4801_Y connect \ra \LDST_RA end -attribute \src "libresoc.v:124037.1-124234.10" +attribute \src "libresoc.v:124375.1-124572.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" attribute \generator "nMigen" module \dec_b - attribute \src "libresoc.v:124198.3-124215.6" + attribute \src "libresoc.v:124536.3-124553.6" wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:124216.3-124233.6" + attribute \src "libresoc.v:124554.3-124571.6" wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:124038.7-124038.20" + attribute \src "libresoc.v:124376.7-124376.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124168.3-124182.6" + attribute \src "libresoc.v:124506.3-124520.6" wire width 7 $0\reg_b[6:0] - attribute \src "libresoc.v:124183.3-124197.6" + attribute \src "libresoc.v:124521.3-124535.6" wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:124198.3-124215.6" + attribute \src "libresoc.v:124536.3-124553.6" wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:124216.3-124233.6" + attribute \src "libresoc.v:124554.3-124571.6" wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:124168.3-124182.6" + attribute \src "libresoc.v:124506.3-124520.6" wire width 7 $1\reg_b[6:0] - attribute \src "libresoc.v:124183.3-124197.6" + attribute \src "libresoc.v:124521.3-124535.6" wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:124198.3-124215.6" + attribute \src "libresoc.v:124536.3-124553.6" wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:124216.3-124233.6" + attribute \src "libresoc.v:124554.3-124571.6" wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:124162.17-124162.117" - wire $eq$libresoc.v:124162$4619_Y - attribute \src "libresoc.v:124166.17-124166.117" - wire $eq$libresoc.v:124166$4625_Y - attribute \src "libresoc.v:124164.17-124164.100" - wire width 7 $extend$libresoc.v:124164$4621_Y - attribute \src "libresoc.v:124165.17-124165.100" - wire width 7 $extend$libresoc.v:124165$4623_Y - attribute \src "libresoc.v:124163.18-124163.108" - wire $not$libresoc.v:124163$4620_Y - attribute \src "libresoc.v:124167.17-124167.107" - wire $not$libresoc.v:124167$4626_Y - attribute \src "libresoc.v:124164.17-124164.100" - wire width 7 $pos$libresoc.v:124164$4622_Y - attribute \src "libresoc.v:124165.17-124165.100" - wire width 7 $pos$libresoc.v:124165$4624_Y + attribute \src "libresoc.v:124500.17-124500.117" + wire $eq$libresoc.v:124500$4804_Y + attribute \src "libresoc.v:124504.17-124504.117" + wire $eq$libresoc.v:124504$4810_Y + attribute \src "libresoc.v:124502.17-124502.100" + wire width 7 $extend$libresoc.v:124502$4806_Y + attribute \src "libresoc.v:124503.17-124503.100" + wire width 7 $extend$libresoc.v:124503$4808_Y + attribute \src "libresoc.v:124501.18-124501.108" + wire $not$libresoc.v:124501$4805_Y + attribute \src "libresoc.v:124505.17-124505.107" + wire $not$libresoc.v:124505$4811_Y + attribute \src "libresoc.v:124502.17-124502.100" + wire width 7 $pos$libresoc.v:124502$4807_Y + attribute \src "libresoc.v:124503.17-124503.100" + wire width 7 $pos$libresoc.v:124503$4809_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 7 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 7 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" wire \$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 7 \RB @@ -192517,7 +195320,7 @@ module \dec_b wire width 3 output 4 \fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_b_ok - attribute \src "libresoc.v:124038.7-124038.15" + attribute \src "libresoc.v:124376.7-124376.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -192614,10 +195417,10 @@ module \dec_b attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" wire width 4 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" - cell $eq $eq$libresoc.v:124162$4619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" + cell $eq $eq$libresoc.v:124500$4804 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192625,10 +195428,10 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:124162$4619_Y + connect \Y $eq$libresoc.v:124500$4804_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" - cell $eq $eq$libresoc.v:124166$4625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" + cell $eq $eq$libresoc.v:124504$4810 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192636,76 +195439,76 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:124166$4625_Y + connect \Y $eq$libresoc.v:124504$4810_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124164$4621 + cell $pos $extend$libresoc.v:124502$4806 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RB - connect \Y $extend$libresoc.v:124164$4621_Y + connect \Y $extend$libresoc.v:124502$4806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124165$4623 + cell $pos $extend$libresoc.v:124503$4808 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RS - connect \Y $extend$libresoc.v:124165$4623_Y + connect \Y $extend$libresoc.v:124503$4808_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" - cell $not $not$libresoc.v:124163$4620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + cell $not $not$libresoc.v:124501$4805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:124163$4620_Y + connect \Y $not$libresoc.v:124501$4805_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" - cell $not $not$libresoc.v:124167$4626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + cell $not $not$libresoc.v:124505$4811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:124167$4626_Y + connect \Y $not$libresoc.v:124505$4811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124164$4622 + cell $pos $pos$libresoc.v:124502$4807 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:124164$4621_Y - connect \Y $pos$libresoc.v:124164$4622_Y + connect \A $extend$libresoc.v:124502$4806_Y + connect \Y $pos$libresoc.v:124502$4807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124165$4624 + cell $pos $pos$libresoc.v:124503$4809 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:124165$4623_Y - connect \Y $pos$libresoc.v:124165$4624_Y + connect \A $extend$libresoc.v:124503$4808_Y + connect \Y $pos$libresoc.v:124503$4809_Y end - attribute \src "libresoc.v:124038.7-124038.20" - process $proc$libresoc.v:124038$4631 + attribute \src "libresoc.v:124376.7-124376.20" + process $proc$libresoc.v:124376$4816 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124168.3-124182.6" - process $proc$libresoc.v:124168$4627 + attribute \src "libresoc.v:124506.3-124520.6" + process $proc$libresoc.v:124506$4812 assign { } { } assign { } { } assign $0\reg_b[6:0] $1\reg_b[6:0] - attribute \src "libresoc.v:124169.5-124169.29" + attribute \src "libresoc.v:124507.5-124507.29" switch \initial - attribute \src "libresoc.v:124169.9-124169.17" + attribute \src "libresoc.v:124507.9-124507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -192721,18 +195524,18 @@ module \dec_b sync always update \reg_b $0\reg_b[6:0] end - attribute \src "libresoc.v:124183.3-124197.6" - process $proc$libresoc.v:124183$4628 + attribute \src "libresoc.v:124521.3-124535.6" + process $proc$libresoc.v:124521$4813 assign { } { } assign { } { } assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:124184.5-124184.29" + attribute \src "libresoc.v:124522.5-124522.29" switch \initial - attribute \src "libresoc.v:124184.9-124184.17" + attribute \src "libresoc.v:124522.9-124522.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0001 @@ -192748,24 +195551,24 @@ module \dec_b sync always update \reg_b_ok $0\reg_b_ok[0:0] end - attribute \src "libresoc.v:124198.3-124215.6" - process $proc$libresoc.v:124198$4629 + attribute \src "libresoc.v:124536.3-124553.6" + process $proc$libresoc.v:124536$4814 assign { } { } assign { } { } assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:124199.5-124199.29" + attribute \src "libresoc.v:124537.5-124537.29" switch \initial - attribute \src "libresoc.v:124199.9-124199.17" + attribute \src "libresoc.v:124537.9-124537.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b[2:0] $2\fast_b[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" switch { \XL_XO [5] \$7 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -192784,24 +195587,24 @@ module \dec_b sync always update \fast_b $0\fast_b[2:0] end - attribute \src "libresoc.v:124216.3-124233.6" - process $proc$libresoc.v:124216$4630 + attribute \src "libresoc.v:124554.3-124571.6" + process $proc$libresoc.v:124554$4815 assign { } { } assign { } { } assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:124217.5-124217.29" + attribute \src "libresoc.v:124555.5-124555.29" switch \initial - attribute \src "libresoc.v:124217.9-124217.17" + attribute \src "libresoc.v:124555.9-124555.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" switch { \XL_XO [5] \$11 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -192820,103 +195623,103 @@ module \dec_b sync always update \fast_b_ok $0\fast_b_ok[0:0] end - connect \$9 $eq$libresoc.v:124162$4619_Y - connect \$11 $not$libresoc.v:124163$4620_Y - connect \$1 $pos$libresoc.v:124164$4622_Y - connect \$3 $pos$libresoc.v:124165$4624_Y - connect \$5 $eq$libresoc.v:124166$4625_Y - connect \$7 $not$libresoc.v:124167$4626_Y + connect \$9 $eq$libresoc.v:124500$4804_Y + connect \$11 $not$libresoc.v:124501$4805_Y + connect \$1 $pos$libresoc.v:124502$4807_Y + connect \$3 $pos$libresoc.v:124503$4809_Y + connect \$5 $eq$libresoc.v:124504$4810_Y + connect \$7 $not$libresoc.v:124505$4811_Y end -attribute \src "libresoc.v:124238.1-124491.10" +attribute \src "libresoc.v:124576.1-124829.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" attribute \generator "nMigen" module \dec_bi - attribute \src "libresoc.v:124465.3-124475.6" + attribute \src "libresoc.v:124803.3-124813.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:124476.3-124486.6" + attribute \src "libresoc.v:124814.3-124824.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:124327.3-124373.6" + attribute \src "libresoc.v:124665.3-124711.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:124374.3-124420.6" + attribute \src "libresoc.v:124712.3-124758.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:124239.7-124239.20" + attribute \src "libresoc.v:124577.7-124577.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124454.3-124464.6" + attribute \src "libresoc.v:124792.3-124802.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:124421.3-124431.6" + attribute \src "libresoc.v:124759.3-124769.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:124432.3-124442.6" + attribute \src "libresoc.v:124770.3-124780.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:124443.3-124453.6" + attribute \src "libresoc.v:124781.3-124791.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:124465.3-124475.6" + attribute \src "libresoc.v:124803.3-124813.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:124476.3-124486.6" + attribute \src "libresoc.v:124814.3-124824.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:124327.3-124373.6" + attribute \src "libresoc.v:124665.3-124711.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:124374.3-124420.6" + attribute \src "libresoc.v:124712.3-124758.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124454.3-124464.6" + attribute \src "libresoc.v:124792.3-124802.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:124421.3-124431.6" + attribute \src "libresoc.v:124759.3-124769.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:124432.3-124442.6" + attribute \src "libresoc.v:124770.3-124780.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:124443.3-124453.6" + attribute \src "libresoc.v:124781.3-124791.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:124317.17-124317.104" - wire width 64 $extend$libresoc.v:124317$4632_Y - attribute \src "libresoc.v:124318.18-124318.107" - wire width 64 $extend$libresoc.v:124318$4634_Y - attribute \src "libresoc.v:124321.17-124321.104" - wire width 64 $extend$libresoc.v:124321$4638_Y - attribute \src "libresoc.v:124325.17-124325.102" - wire width 64 $extend$libresoc.v:124325$4643_Y - attribute \src "libresoc.v:124317.17-124317.104" - wire width 64 $pos$libresoc.v:124317$4633_Y - attribute \src "libresoc.v:124318.18-124318.107" - wire width 64 $pos$libresoc.v:124318$4635_Y - attribute \src "libresoc.v:124321.17-124321.104" - wire width 64 $pos$libresoc.v:124321$4639_Y - attribute \src "libresoc.v:124325.17-124325.102" - wire width 64 $pos$libresoc.v:124325$4644_Y - attribute \src "libresoc.v:124319.18-124319.114" - wire width 47 $sshl$libresoc.v:124319$4636_Y - attribute \src "libresoc.v:124320.18-124320.113" - wire width 27 $sshl$libresoc.v:124320$4637_Y - attribute \src "libresoc.v:124322.18-124322.113" - wire width 17 $sshl$libresoc.v:124322$4640_Y - attribute \src "libresoc.v:124323.18-124323.113" - wire width 17 $sshl$libresoc.v:124323$4641_Y - attribute \src "libresoc.v:124324.17-124324.109" - wire width 47 $sshl$libresoc.v:124324$4642_Y + attribute \src "libresoc.v:124655.17-124655.104" + wire width 64 $extend$libresoc.v:124655$4817_Y + attribute \src "libresoc.v:124656.18-124656.107" + wire width 64 $extend$libresoc.v:124656$4819_Y + attribute \src "libresoc.v:124659.17-124659.104" + wire width 64 $extend$libresoc.v:124659$4823_Y + attribute \src "libresoc.v:124663.17-124663.102" + wire width 64 $extend$libresoc.v:124663$4828_Y + attribute \src "libresoc.v:124655.17-124655.104" + wire width 64 $pos$libresoc.v:124655$4818_Y + attribute \src "libresoc.v:124656.18-124656.107" + wire width 64 $pos$libresoc.v:124656$4820_Y + attribute \src "libresoc.v:124659.17-124659.104" + wire width 64 $pos$libresoc.v:124659$4824_Y + attribute \src "libresoc.v:124663.17-124663.102" + wire width 64 $pos$libresoc.v:124663$4829_Y + attribute \src "libresoc.v:124657.18-124657.114" + wire width 47 $sshl$libresoc.v:124657$4821_Y + attribute \src "libresoc.v:124658.18-124658.113" + wire width 27 $sshl$libresoc.v:124658$4822_Y + attribute \src "libresoc.v:124660.18-124660.113" + wire width 17 $sshl$libresoc.v:124660$4825_Y + attribute \src "libresoc.v:124661.18-124661.113" + wire width 17 $sshl$libresoc.v:124661$4826_Y + attribute \src "libresoc.v:124662.17-124662.109" + wire width 47 $sshl$libresoc.v:124662$4827_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -192934,17 +195737,17 @@ module \dec_bi wire width 16 input 4 \ALU_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:124239.7-124239.15" + attribute \src "libresoc.v:124577.7-124577.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -192961,80 +195764,80 @@ module \dec_bi attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124317$4632 + cell $pos $extend$libresoc.v:124655$4817 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \ALU_sh - connect \Y $extend$libresoc.v:124317$4632_Y + connect \Y $extend$libresoc.v:124655$4817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124318$4634 + cell $pos $extend$libresoc.v:124656$4819 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \ALU_SH32 - connect \Y $extend$libresoc.v:124318$4634_Y + connect \Y $extend$libresoc.v:124656$4819_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124321$4638 + cell $pos $extend$libresoc.v:124659$4823 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \ALU_UI - connect \Y $extend$libresoc.v:124321$4638_Y + connect \Y $extend$libresoc.v:124659$4823_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $extend$libresoc.v:124325$4643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $extend$libresoc.v:124663$4828 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:124325$4643_Y + connect \Y $extend$libresoc.v:124663$4828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124317$4633 + cell $pos $pos$libresoc.v:124655$4818 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124317$4632_Y - connect \Y $pos$libresoc.v:124317$4633_Y + connect \A $extend$libresoc.v:124655$4817_Y + connect \Y $pos$libresoc.v:124655$4818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124318$4635 + cell $pos $pos$libresoc.v:124656$4820 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124318$4634_Y - connect \Y $pos$libresoc.v:124318$4635_Y + connect \A $extend$libresoc.v:124656$4819_Y + connect \Y $pos$libresoc.v:124656$4820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124321$4639 + cell $pos $pos$libresoc.v:124659$4824 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124321$4638_Y - connect \Y $pos$libresoc.v:124321$4639_Y + connect \A $extend$libresoc.v:124659$4823_Y + connect \Y $pos$libresoc.v:124659$4824_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $pos$libresoc.v:124325$4644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $pos$libresoc.v:124663$4829 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124325$4643_Y - connect \Y $pos$libresoc.v:124325$4644_Y + connect \A $extend$libresoc.v:124663$4828_Y + connect \Y $pos$libresoc.v:124663$4829_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - cell $sshl $sshl$libresoc.v:124319$4636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:124657$4821 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -193042,10 +195845,10 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ALU_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:124319$4636_Y + connect \Y $sshl$libresoc.v:124657$4821_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" - cell $sshl $sshl$libresoc.v:124320$4637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:124658$4822 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -193053,10 +195856,10 @@ module \dec_bi parameter \Y_WIDTH 27 connect \A \ALU_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:124320$4637_Y + connect \Y $sshl$libresoc.v:124658$4822_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" - cell $sshl $sshl$libresoc.v:124322$4640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:124660$4825 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193064,10 +195867,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:124322$4640_Y + connect \Y $sshl$libresoc.v:124660$4825_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - cell $sshl $sshl$libresoc.v:124323$4641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:124661$4826 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193075,10 +195878,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:124323$4641_Y + connect \Y $sshl$libresoc.v:124661$4826_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $sshl $sshl$libresoc.v:124324$4642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $sshl $sshl$libresoc.v:124662$4827 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -193086,28 +195889,28 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:124324$4642_Y + connect \Y $sshl$libresoc.v:124662$4827_Y end - attribute \src "libresoc.v:124239.7-124239.20" - process $proc$libresoc.v:124239$4653 + attribute \src "libresoc.v:124577.7-124577.20" + process $proc$libresoc.v:124577$4838 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124327.3-124373.6" - process $proc$libresoc.v:124327$4645 + attribute \src "libresoc.v:124665.3-124711.6" + process $proc$libresoc.v:124665$4830 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:124328.5-124328.29" + attribute \src "libresoc.v:124666.5-124666.29" switch \initial - attribute \src "libresoc.v:124328.9-124328.17" + attribute \src "libresoc.v:124666.9-124666.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -193155,18 +195958,18 @@ module \dec_bi sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:124374.3-124420.6" - process $proc$libresoc.v:124374$4646 + attribute \src "libresoc.v:124712.3-124758.6" + process $proc$libresoc.v:124712$4831 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124375.5-124375.29" + attribute \src "libresoc.v:124713.5-124713.29" switch \initial - attribute \src "libresoc.v:124375.9-124375.17" + attribute \src "libresoc.v:124713.9-124713.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -193214,18 +196017,18 @@ module \dec_bi sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:124421.3-124431.6" - process $proc$libresoc.v:124421$4647 + attribute \src "libresoc.v:124759.3-124769.6" + process $proc$libresoc.v:124759$4832 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:124422.5-124422.29" + attribute \src "libresoc.v:124760.5-124760.29" switch \initial - attribute \src "libresoc.v:124422.9-124422.17" + attribute \src "libresoc.v:124760.9-124760.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -193237,18 +196040,18 @@ module \dec_bi sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:124432.3-124442.6" - process $proc$libresoc.v:124432$4648 + attribute \src "libresoc.v:124770.3-124780.6" + process $proc$libresoc.v:124770$4833 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:124433.5-124433.29" + attribute \src "libresoc.v:124771.5-124771.29" switch \initial - attribute \src "libresoc.v:124433.9-124433.17" + attribute \src "libresoc.v:124771.9-124771.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -193260,18 +196063,18 @@ module \dec_bi sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:124443.3-124453.6" - process $proc$libresoc.v:124443$4649 + attribute \src "libresoc.v:124781.3-124791.6" + process $proc$libresoc.v:124781$4834 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:124444.5-124444.29" + attribute \src "libresoc.v:124782.5-124782.29" switch \initial - attribute \src "libresoc.v:124444.9-124444.17" + attribute \src "libresoc.v:124782.9-124782.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -193283,18 +196086,18 @@ module \dec_bi sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:124454.3-124464.6" - process $proc$libresoc.v:124454$4650 + attribute \src "libresoc.v:124792.3-124802.6" + process $proc$libresoc.v:124792$4835 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:124455.5-124455.29" + attribute \src "libresoc.v:124793.5-124793.29" switch \initial - attribute \src "libresoc.v:124455.9-124455.17" + attribute \src "libresoc.v:124793.9-124793.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -193306,18 +196109,18 @@ module \dec_bi sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:124465.3-124475.6" - process $proc$libresoc.v:124465$4651 + attribute \src "libresoc.v:124803.3-124813.6" + process $proc$libresoc.v:124803$4836 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:124466.5-124466.29" + attribute \src "libresoc.v:124804.5-124804.29" switch \initial - attribute \src "libresoc.v:124466.9-124466.17" + attribute \src "libresoc.v:124804.9-124804.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -193329,18 +196132,18 @@ module \dec_bi sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:124476.3-124486.6" - process $proc$libresoc.v:124476$4652 + attribute \src "libresoc.v:124814.3-124824.6" + process $proc$libresoc.v:124814$4837 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:124477.5-124477.29" + attribute \src "libresoc.v:124815.5-124815.29" switch \initial - attribute \src "libresoc.v:124477.9-124477.17" + attribute \src "libresoc.v:124815.9-124815.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -193352,111 +196155,111 @@ module \dec_bi sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:124317$4633_Y - connect \$11 $pos$libresoc.v:124318$4635_Y - connect \$14 $sshl$libresoc.v:124319$4636_Y - connect \$17 $sshl$libresoc.v:124320$4637_Y - connect \$1 $pos$libresoc.v:124321$4639_Y - connect \$20 $sshl$libresoc.v:124322$4640_Y - connect \$23 $sshl$libresoc.v:124323$4641_Y - connect \$4 $sshl$libresoc.v:124324$4642_Y - connect \$3 $pos$libresoc.v:124325$4644_Y + connect \$9 $pos$libresoc.v:124655$4818_Y + connect \$11 $pos$libresoc.v:124656$4820_Y + connect \$14 $sshl$libresoc.v:124657$4821_Y + connect \$17 $sshl$libresoc.v:124658$4822_Y + connect \$1 $pos$libresoc.v:124659$4824_Y + connect \$20 $sshl$libresoc.v:124660$4825_Y + connect \$23 $sshl$libresoc.v:124661$4826_Y + connect \$4 $sshl$libresoc.v:124662$4827_Y + connect \$3 $pos$libresoc.v:124663$4829_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:124495.1-124748.10" +attribute \src "libresoc.v:124833.1-125086.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" attribute \generator "nMigen" -module \dec_bi$153 - attribute \src "libresoc.v:124722.3-124732.6" +module \dec_bi$144 + attribute \src "libresoc.v:125060.3-125070.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:124733.3-124743.6" + attribute \src "libresoc.v:125071.3-125081.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:124584.3-124630.6" + attribute \src "libresoc.v:124922.3-124968.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:124631.3-124677.6" + attribute \src "libresoc.v:124969.3-125015.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:124496.7-124496.20" + attribute \src "libresoc.v:124834.7-124834.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124711.3-124721.6" + attribute \src "libresoc.v:125049.3-125059.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:124678.3-124688.6" + attribute \src "libresoc.v:125016.3-125026.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:124689.3-124699.6" + attribute \src "libresoc.v:125027.3-125037.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:124700.3-124710.6" + attribute \src "libresoc.v:125038.3-125048.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:124722.3-124732.6" + attribute \src "libresoc.v:125060.3-125070.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:124733.3-124743.6" + attribute \src "libresoc.v:125071.3-125081.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:124584.3-124630.6" + attribute \src "libresoc.v:124922.3-124968.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:124631.3-124677.6" + attribute \src "libresoc.v:124969.3-125015.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124711.3-124721.6" + attribute \src "libresoc.v:125049.3-125059.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:124678.3-124688.6" + attribute \src "libresoc.v:125016.3-125026.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:124689.3-124699.6" + attribute \src "libresoc.v:125027.3-125037.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:124700.3-124710.6" + attribute \src "libresoc.v:125038.3-125048.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:124574.17-124574.107" - wire width 64 $extend$libresoc.v:124574$4654_Y - attribute \src "libresoc.v:124575.18-124575.110" - wire width 64 $extend$libresoc.v:124575$4656_Y - attribute \src "libresoc.v:124578.17-124578.107" - wire width 64 $extend$libresoc.v:124578$4660_Y - attribute \src "libresoc.v:124582.17-124582.102" - wire width 64 $extend$libresoc.v:124582$4665_Y - attribute \src "libresoc.v:124574.17-124574.107" - wire width 64 $pos$libresoc.v:124574$4655_Y - attribute \src "libresoc.v:124575.18-124575.110" - wire width 64 $pos$libresoc.v:124575$4657_Y - attribute \src "libresoc.v:124578.17-124578.107" - wire width 64 $pos$libresoc.v:124578$4661_Y - attribute \src "libresoc.v:124582.17-124582.102" - wire width 64 $pos$libresoc.v:124582$4666_Y - attribute \src "libresoc.v:124576.18-124576.117" - wire width 47 $sshl$libresoc.v:124576$4658_Y - attribute \src "libresoc.v:124577.18-124577.116" - wire width 27 $sshl$libresoc.v:124577$4659_Y - attribute \src "libresoc.v:124579.18-124579.116" - wire width 17 $sshl$libresoc.v:124579$4662_Y - attribute \src "libresoc.v:124580.18-124580.116" - wire width 17 $sshl$libresoc.v:124580$4663_Y - attribute \src "libresoc.v:124581.17-124581.109" - wire width 47 $sshl$libresoc.v:124581$4664_Y + attribute \src "libresoc.v:124912.17-124912.107" + wire width 64 $extend$libresoc.v:124912$4839_Y + attribute \src "libresoc.v:124913.18-124913.110" + wire width 64 $extend$libresoc.v:124913$4841_Y + attribute \src "libresoc.v:124916.17-124916.107" + wire width 64 $extend$libresoc.v:124916$4845_Y + attribute \src "libresoc.v:124920.17-124920.102" + wire width 64 $extend$libresoc.v:124920$4850_Y + attribute \src "libresoc.v:124912.17-124912.107" + wire width 64 $pos$libresoc.v:124912$4840_Y + attribute \src "libresoc.v:124913.18-124913.110" + wire width 64 $pos$libresoc.v:124913$4842_Y + attribute \src "libresoc.v:124916.17-124916.107" + wire width 64 $pos$libresoc.v:124916$4846_Y + attribute \src "libresoc.v:124920.17-124920.102" + wire width 64 $pos$libresoc.v:124920$4851_Y + attribute \src "libresoc.v:124914.18-124914.117" + wire width 47 $sshl$libresoc.v:124914$4843_Y + attribute \src "libresoc.v:124915.18-124915.116" + wire width 27 $sshl$libresoc.v:124915$4844_Y + attribute \src "libresoc.v:124917.18-124917.116" + wire width 17 $sshl$libresoc.v:124917$4847_Y + attribute \src "libresoc.v:124918.18-124918.116" + wire width 17 $sshl$libresoc.v:124918$4848_Y + attribute \src "libresoc.v:124919.17-124919.109" + wire width 47 $sshl$libresoc.v:124919$4849_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -193474,17 +196277,17 @@ module \dec_bi$153 wire width 16 input 4 \BRANCH_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:124496.7-124496.15" + attribute \src "libresoc.v:124834.7-124834.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -193501,80 +196304,80 @@ module \dec_bi$153 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124574$4654 + cell $pos $extend$libresoc.v:124912$4839 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \BRANCH_sh - connect \Y $extend$libresoc.v:124574$4654_Y + connect \Y $extend$libresoc.v:124912$4839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124575$4656 + cell $pos $extend$libresoc.v:124913$4841 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \BRANCH_SH32 - connect \Y $extend$libresoc.v:124575$4656_Y + connect \Y $extend$libresoc.v:124913$4841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124578$4660 + cell $pos $extend$libresoc.v:124916$4845 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \BRANCH_UI - connect \Y $extend$libresoc.v:124578$4660_Y + connect \Y $extend$libresoc.v:124916$4845_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $extend$libresoc.v:124582$4665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $extend$libresoc.v:124920$4850 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:124582$4665_Y + connect \Y $extend$libresoc.v:124920$4850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124574$4655 + cell $pos $pos$libresoc.v:124912$4840 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124574$4654_Y - connect \Y $pos$libresoc.v:124574$4655_Y + connect \A $extend$libresoc.v:124912$4839_Y + connect \Y $pos$libresoc.v:124912$4840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124575$4657 + cell $pos $pos$libresoc.v:124913$4842 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124575$4656_Y - connect \Y $pos$libresoc.v:124575$4657_Y + connect \A $extend$libresoc.v:124913$4841_Y + connect \Y $pos$libresoc.v:124913$4842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124578$4661 + cell $pos $pos$libresoc.v:124916$4846 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124578$4660_Y - connect \Y $pos$libresoc.v:124578$4661_Y + connect \A $extend$libresoc.v:124916$4845_Y + connect \Y $pos$libresoc.v:124916$4846_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $pos$libresoc.v:124582$4666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $pos$libresoc.v:124920$4851 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124582$4665_Y - connect \Y $pos$libresoc.v:124582$4666_Y + connect \A $extend$libresoc.v:124920$4850_Y + connect \Y $pos$libresoc.v:124920$4851_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - cell $sshl $sshl$libresoc.v:124576$4658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:124914$4843 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -193582,10 +196385,10 @@ module \dec_bi$153 parameter \Y_WIDTH 47 connect \A \BRANCH_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:124576$4658_Y + connect \Y $sshl$libresoc.v:124914$4843_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" - cell $sshl $sshl$libresoc.v:124577$4659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:124915$4844 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -193593,10 +196396,10 @@ module \dec_bi$153 parameter \Y_WIDTH 27 connect \A \BRANCH_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:124577$4659_Y + connect \Y $sshl$libresoc.v:124915$4844_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" - cell $sshl $sshl$libresoc.v:124579$4662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:124917$4847 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193604,10 +196407,10 @@ module \dec_bi$153 parameter \Y_WIDTH 17 connect \A \BRANCH_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:124579$4662_Y + connect \Y $sshl$libresoc.v:124917$4847_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - cell $sshl $sshl$libresoc.v:124580$4663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:124918$4848 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193615,10 +196418,10 @@ module \dec_bi$153 parameter \Y_WIDTH 17 connect \A \BRANCH_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:124580$4663_Y + connect \Y $sshl$libresoc.v:124918$4848_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $sshl $sshl$libresoc.v:124581$4664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $sshl $sshl$libresoc.v:124919$4849 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -193626,28 +196429,28 @@ module \dec_bi$153 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:124581$4664_Y + connect \Y $sshl$libresoc.v:124919$4849_Y end - attribute \src "libresoc.v:124496.7-124496.20" - process $proc$libresoc.v:124496$4675 + attribute \src "libresoc.v:124834.7-124834.20" + process $proc$libresoc.v:124834$4860 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124584.3-124630.6" - process $proc$libresoc.v:124584$4667 + attribute \src "libresoc.v:124922.3-124968.6" + process $proc$libresoc.v:124922$4852 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:124585.5-124585.29" + attribute \src "libresoc.v:124923.5-124923.29" switch \initial - attribute \src "libresoc.v:124585.9-124585.17" + attribute \src "libresoc.v:124923.9-124923.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -193695,18 +196498,18 @@ module \dec_bi$153 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:124631.3-124677.6" - process $proc$libresoc.v:124631$4668 + attribute \src "libresoc.v:124969.3-125015.6" + process $proc$libresoc.v:124969$4853 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124632.5-124632.29" + attribute \src "libresoc.v:124970.5-124970.29" switch \initial - attribute \src "libresoc.v:124632.9-124632.17" + attribute \src "libresoc.v:124970.9-124970.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -193754,18 +196557,18 @@ module \dec_bi$153 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:124678.3-124688.6" - process $proc$libresoc.v:124678$4669 + attribute \src "libresoc.v:125016.3-125026.6" + process $proc$libresoc.v:125016$4854 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:124679.5-124679.29" + attribute \src "libresoc.v:125017.5-125017.29" switch \initial - attribute \src "libresoc.v:124679.9-124679.17" + attribute \src "libresoc.v:125017.9-125017.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -193777,18 +196580,18 @@ module \dec_bi$153 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:124689.3-124699.6" - process $proc$libresoc.v:124689$4670 + attribute \src "libresoc.v:125027.3-125037.6" + process $proc$libresoc.v:125027$4855 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:124690.5-124690.29" + attribute \src "libresoc.v:125028.5-125028.29" switch \initial - attribute \src "libresoc.v:124690.9-124690.17" + attribute \src "libresoc.v:125028.9-125028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -193800,18 +196603,18 @@ module \dec_bi$153 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:124700.3-124710.6" - process $proc$libresoc.v:124700$4671 + attribute \src "libresoc.v:125038.3-125048.6" + process $proc$libresoc.v:125038$4856 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:124701.5-124701.29" + attribute \src "libresoc.v:125039.5-125039.29" switch \initial - attribute \src "libresoc.v:124701.9-124701.17" + attribute \src "libresoc.v:125039.9-125039.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -193823,18 +196626,18 @@ module \dec_bi$153 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:124711.3-124721.6" - process $proc$libresoc.v:124711$4672 + attribute \src "libresoc.v:125049.3-125059.6" + process $proc$libresoc.v:125049$4857 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:124712.5-124712.29" + attribute \src "libresoc.v:125050.5-125050.29" switch \initial - attribute \src "libresoc.v:124712.9-124712.17" + attribute \src "libresoc.v:125050.9-125050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -193846,18 +196649,18 @@ module \dec_bi$153 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:124722.3-124732.6" - process $proc$libresoc.v:124722$4673 + attribute \src "libresoc.v:125060.3-125070.6" + process $proc$libresoc.v:125060$4858 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:124723.5-124723.29" + attribute \src "libresoc.v:125061.5-125061.29" switch \initial - attribute \src "libresoc.v:124723.9-124723.17" + attribute \src "libresoc.v:125061.9-125061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -193869,18 +196672,18 @@ module \dec_bi$153 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:124733.3-124743.6" - process $proc$libresoc.v:124733$4674 + attribute \src "libresoc.v:125071.3-125081.6" + process $proc$libresoc.v:125071$4859 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:124734.5-124734.29" + attribute \src "libresoc.v:125072.5-125072.29" switch \initial - attribute \src "libresoc.v:124734.9-124734.17" + attribute \src "libresoc.v:125072.9-125072.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -193892,111 +196695,111 @@ module \dec_bi$153 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:124574$4655_Y - connect \$11 $pos$libresoc.v:124575$4657_Y - connect \$14 $sshl$libresoc.v:124576$4658_Y - connect \$17 $sshl$libresoc.v:124577$4659_Y - connect \$1 $pos$libresoc.v:124578$4661_Y - connect \$20 $sshl$libresoc.v:124579$4662_Y - connect \$23 $sshl$libresoc.v:124580$4663_Y - connect \$4 $sshl$libresoc.v:124581$4664_Y - connect \$3 $pos$libresoc.v:124582$4666_Y + connect \$9 $pos$libresoc.v:124912$4840_Y + connect \$11 $pos$libresoc.v:124913$4842_Y + connect \$14 $sshl$libresoc.v:124914$4843_Y + connect \$17 $sshl$libresoc.v:124915$4844_Y + connect \$1 $pos$libresoc.v:124916$4846_Y + connect \$20 $sshl$libresoc.v:124917$4847_Y + connect \$23 $sshl$libresoc.v:124918$4848_Y + connect \$4 $sshl$libresoc.v:124919$4849_Y + connect \$3 $pos$libresoc.v:124920$4851_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:124752.1-125005.10" +attribute \src "libresoc.v:125090.1-125343.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" attribute \generator "nMigen" -module \dec_bi$162 - attribute \src "libresoc.v:124979.3-124989.6" +module \dec_bi$149 + attribute \src "libresoc.v:125317.3-125327.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:124990.3-125000.6" + attribute \src "libresoc.v:125328.3-125338.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:124841.3-124887.6" + attribute \src "libresoc.v:125179.3-125225.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:124888.3-124934.6" + attribute \src "libresoc.v:125226.3-125272.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:124753.7-124753.20" + attribute \src "libresoc.v:125091.7-125091.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124968.3-124978.6" + attribute \src "libresoc.v:125306.3-125316.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:124935.3-124945.6" + attribute \src "libresoc.v:125273.3-125283.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:124946.3-124956.6" + attribute \src "libresoc.v:125284.3-125294.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:124957.3-124967.6" + attribute \src "libresoc.v:125295.3-125305.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:124979.3-124989.6" + attribute \src "libresoc.v:125317.3-125327.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:124990.3-125000.6" + attribute \src "libresoc.v:125328.3-125338.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:124841.3-124887.6" + attribute \src "libresoc.v:125179.3-125225.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:124888.3-124934.6" + attribute \src "libresoc.v:125226.3-125272.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124968.3-124978.6" + attribute \src "libresoc.v:125306.3-125316.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:124935.3-124945.6" + attribute \src "libresoc.v:125273.3-125283.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:124946.3-124956.6" + attribute \src "libresoc.v:125284.3-125294.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:124957.3-124967.6" + attribute \src "libresoc.v:125295.3-125305.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:124831.17-124831.108" - wire width 64 $extend$libresoc.v:124831$4676_Y - attribute \src "libresoc.v:124832.18-124832.111" - wire width 64 $extend$libresoc.v:124832$4678_Y - attribute \src "libresoc.v:124835.17-124835.108" - wire width 64 $extend$libresoc.v:124835$4682_Y - attribute \src "libresoc.v:124839.17-124839.102" - wire width 64 $extend$libresoc.v:124839$4687_Y - attribute \src "libresoc.v:124831.17-124831.108" - wire width 64 $pos$libresoc.v:124831$4677_Y - attribute \src "libresoc.v:124832.18-124832.111" - wire width 64 $pos$libresoc.v:124832$4679_Y - attribute \src "libresoc.v:124835.17-124835.108" - wire width 64 $pos$libresoc.v:124835$4683_Y - attribute \src "libresoc.v:124839.17-124839.102" - wire width 64 $pos$libresoc.v:124839$4688_Y - attribute \src "libresoc.v:124833.18-124833.118" - wire width 47 $sshl$libresoc.v:124833$4680_Y - attribute \src "libresoc.v:124834.18-124834.117" - wire width 27 $sshl$libresoc.v:124834$4681_Y - attribute \src "libresoc.v:124836.18-124836.117" - wire width 17 $sshl$libresoc.v:124836$4684_Y - attribute \src "libresoc.v:124837.18-124837.117" - wire width 17 $sshl$libresoc.v:124837$4685_Y - attribute \src "libresoc.v:124838.17-124838.109" - wire width 47 $sshl$libresoc.v:124838$4686_Y + attribute \src "libresoc.v:125169.17-125169.108" + wire width 64 $extend$libresoc.v:125169$4861_Y + attribute \src "libresoc.v:125170.18-125170.111" + wire width 64 $extend$libresoc.v:125170$4863_Y + attribute \src "libresoc.v:125173.17-125173.108" + wire width 64 $extend$libresoc.v:125173$4867_Y + attribute \src "libresoc.v:125177.17-125177.102" + wire width 64 $extend$libresoc.v:125177$4872_Y + attribute \src "libresoc.v:125169.17-125169.108" + wire width 64 $pos$libresoc.v:125169$4862_Y + attribute \src "libresoc.v:125170.18-125170.111" + wire width 64 $pos$libresoc.v:125170$4864_Y + attribute \src "libresoc.v:125173.17-125173.108" + wire width 64 $pos$libresoc.v:125173$4868_Y + attribute \src "libresoc.v:125177.17-125177.102" + wire width 64 $pos$libresoc.v:125177$4873_Y + attribute \src "libresoc.v:125171.18-125171.118" + wire width 47 $sshl$libresoc.v:125171$4865_Y + attribute \src "libresoc.v:125172.18-125172.117" + wire width 27 $sshl$libresoc.v:125172$4866_Y + attribute \src "libresoc.v:125174.18-125174.117" + wire width 17 $sshl$libresoc.v:125174$4869_Y + attribute \src "libresoc.v:125175.18-125175.117" + wire width 17 $sshl$libresoc.v:125175$4870_Y + attribute \src "libresoc.v:125176.17-125176.109" + wire width 47 $sshl$libresoc.v:125176$4871_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -194014,17 +196817,17 @@ module \dec_bi$162 wire width 16 input 4 \LOGICAL_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:124753.7-124753.15" + attribute \src "libresoc.v:125091.7-125091.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -194041,80 +196844,80 @@ module \dec_bi$162 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124831$4676 + cell $pos $extend$libresoc.v:125169$4861 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LOGICAL_sh - connect \Y $extend$libresoc.v:124831$4676_Y + connect \Y $extend$libresoc.v:125169$4861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124832$4678 + cell $pos $extend$libresoc.v:125170$4863 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LOGICAL_SH32 - connect \Y $extend$libresoc.v:124832$4678_Y + connect \Y $extend$libresoc.v:125170$4863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:124835$4682 + cell $pos $extend$libresoc.v:125173$4867 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LOGICAL_UI - connect \Y $extend$libresoc.v:124835$4682_Y + connect \Y $extend$libresoc.v:125173$4867_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $extend$libresoc.v:124839$4687 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $extend$libresoc.v:125177$4872 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:124839$4687_Y + connect \Y $extend$libresoc.v:125177$4872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124831$4677 + cell $pos $pos$libresoc.v:125169$4862 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124831$4676_Y - connect \Y $pos$libresoc.v:124831$4677_Y + connect \A $extend$libresoc.v:125169$4861_Y + connect \Y $pos$libresoc.v:125169$4862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124832$4679 + cell $pos $pos$libresoc.v:125170$4864 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124832$4678_Y - connect \Y $pos$libresoc.v:124832$4679_Y + connect \A $extend$libresoc.v:125170$4863_Y + connect \Y $pos$libresoc.v:125170$4864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:124835$4683 + cell $pos $pos$libresoc.v:125173$4868 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124835$4682_Y - connect \Y $pos$libresoc.v:124835$4683_Y + connect \A $extend$libresoc.v:125173$4867_Y + connect \Y $pos$libresoc.v:125173$4868_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $pos$libresoc.v:124839$4688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $pos$libresoc.v:125177$4873 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:124839$4687_Y - connect \Y $pos$libresoc.v:124839$4688_Y + connect \A $extend$libresoc.v:125177$4872_Y + connect \Y $pos$libresoc.v:125177$4873_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - cell $sshl $sshl$libresoc.v:124833$4680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:125171$4865 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -194122,10 +196925,10 @@ module \dec_bi$162 parameter \Y_WIDTH 47 connect \A \LOGICAL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:124833$4680_Y + connect \Y $sshl$libresoc.v:125171$4865_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" - cell $sshl $sshl$libresoc.v:124834$4681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125172$4866 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -194133,10 +196936,10 @@ module \dec_bi$162 parameter \Y_WIDTH 27 connect \A \LOGICAL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:124834$4681_Y + connect \Y $sshl$libresoc.v:125172$4866_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" - cell $sshl $sshl$libresoc.v:124836$4684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:125174$4869 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194144,10 +196947,10 @@ module \dec_bi$162 parameter \Y_WIDTH 17 connect \A \LOGICAL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:124836$4684_Y + connect \Y $sshl$libresoc.v:125174$4869_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - cell $sshl $sshl$libresoc.v:124837$4685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:125175$4870 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194155,10 +196958,10 @@ module \dec_bi$162 parameter \Y_WIDTH 17 connect \A \LOGICAL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:124837$4685_Y + connect \Y $sshl$libresoc.v:125175$4870_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $sshl $sshl$libresoc.v:124838$4686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $sshl $sshl$libresoc.v:125176$4871 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -194166,28 +196969,28 @@ module \dec_bi$162 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:124838$4686_Y + connect \Y $sshl$libresoc.v:125176$4871_Y end - attribute \src "libresoc.v:124753.7-124753.20" - process $proc$libresoc.v:124753$4697 + attribute \src "libresoc.v:125091.7-125091.20" + process $proc$libresoc.v:125091$4882 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124841.3-124887.6" - process $proc$libresoc.v:124841$4689 + attribute \src "libresoc.v:125179.3-125225.6" + process $proc$libresoc.v:125179$4874 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:124842.5-124842.29" + attribute \src "libresoc.v:125180.5-125180.29" switch \initial - attribute \src "libresoc.v:124842.9-124842.17" + attribute \src "libresoc.v:125180.9-125180.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -194235,18 +197038,18 @@ module \dec_bi$162 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:124888.3-124934.6" - process $proc$libresoc.v:124888$4690 + attribute \src "libresoc.v:125226.3-125272.6" + process $proc$libresoc.v:125226$4875 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:124889.5-124889.29" + attribute \src "libresoc.v:125227.5-125227.29" switch \initial - attribute \src "libresoc.v:124889.9-124889.17" + attribute \src "libresoc.v:125227.9-125227.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -194294,18 +197097,18 @@ module \dec_bi$162 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:124935.3-124945.6" - process $proc$libresoc.v:124935$4691 + attribute \src "libresoc.v:125273.3-125283.6" + process $proc$libresoc.v:125273$4876 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:124936.5-124936.29" + attribute \src "libresoc.v:125274.5-125274.29" switch \initial - attribute \src "libresoc.v:124936.9-124936.17" + attribute \src "libresoc.v:125274.9-125274.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -194317,18 +197120,18 @@ module \dec_bi$162 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:124946.3-124956.6" - process $proc$libresoc.v:124946$4692 + attribute \src "libresoc.v:125284.3-125294.6" + process $proc$libresoc.v:125284$4877 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:124947.5-124947.29" + attribute \src "libresoc.v:125285.5-125285.29" switch \initial - attribute \src "libresoc.v:124947.9-124947.17" + attribute \src "libresoc.v:125285.9-125285.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -194340,18 +197143,18 @@ module \dec_bi$162 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:124957.3-124967.6" - process $proc$libresoc.v:124957$4693 + attribute \src "libresoc.v:125295.3-125305.6" + process $proc$libresoc.v:125295$4878 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:124958.5-124958.29" + attribute \src "libresoc.v:125296.5-125296.29" switch \initial - attribute \src "libresoc.v:124958.9-124958.17" + attribute \src "libresoc.v:125296.9-125296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -194363,18 +197166,18 @@ module \dec_bi$162 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:124968.3-124978.6" - process $proc$libresoc.v:124968$4694 + attribute \src "libresoc.v:125306.3-125316.6" + process $proc$libresoc.v:125306$4879 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:124969.5-124969.29" + attribute \src "libresoc.v:125307.5-125307.29" switch \initial - attribute \src "libresoc.v:124969.9-124969.17" + attribute \src "libresoc.v:125307.9-125307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -194386,18 +197189,18 @@ module \dec_bi$162 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:124979.3-124989.6" - process $proc$libresoc.v:124979$4695 + attribute \src "libresoc.v:125317.3-125327.6" + process $proc$libresoc.v:125317$4880 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:124980.5-124980.29" + attribute \src "libresoc.v:125318.5-125318.29" switch \initial - attribute \src "libresoc.v:124980.9-124980.17" + attribute \src "libresoc.v:125318.9-125318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -194409,18 +197212,18 @@ module \dec_bi$162 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:124990.3-125000.6" - process $proc$libresoc.v:124990$4696 + attribute \src "libresoc.v:125328.3-125338.6" + process $proc$libresoc.v:125328$4881 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:124991.5-124991.29" + attribute \src "libresoc.v:125329.5-125329.29" switch \initial - attribute \src "libresoc.v:124991.9-124991.17" + attribute \src "libresoc.v:125329.9-125329.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -194432,111 +197235,111 @@ module \dec_bi$162 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:124831$4677_Y - connect \$11 $pos$libresoc.v:124832$4679_Y - connect \$14 $sshl$libresoc.v:124833$4680_Y - connect \$17 $sshl$libresoc.v:124834$4681_Y - connect \$1 $pos$libresoc.v:124835$4683_Y - connect \$20 $sshl$libresoc.v:124836$4684_Y - connect \$23 $sshl$libresoc.v:124837$4685_Y - connect \$4 $sshl$libresoc.v:124838$4686_Y - connect \$3 $pos$libresoc.v:124839$4688_Y + connect \$9 $pos$libresoc.v:125169$4862_Y + connect \$11 $pos$libresoc.v:125170$4864_Y + connect \$14 $sshl$libresoc.v:125171$4865_Y + connect \$17 $sshl$libresoc.v:125172$4866_Y + connect \$1 $pos$libresoc.v:125173$4868_Y + connect \$20 $sshl$libresoc.v:125174$4869_Y + connect \$23 $sshl$libresoc.v:125175$4870_Y + connect \$4 $sshl$libresoc.v:125176$4871_Y + connect \$3 $pos$libresoc.v:125177$4873_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125009.1-125262.10" +attribute \src "libresoc.v:125347.1-125600.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" attribute \generator "nMigen" -module \dec_bi$178 - attribute \src "libresoc.v:125236.3-125246.6" +module \dec_bi$157 + attribute \src "libresoc.v:125574.3-125584.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125247.3-125257.6" + attribute \src "libresoc.v:125585.3-125595.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125098.3-125144.6" + attribute \src "libresoc.v:125436.3-125482.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125145.3-125191.6" + attribute \src "libresoc.v:125483.3-125529.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125010.7-125010.20" + attribute \src "libresoc.v:125348.7-125348.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125225.3-125235.6" + attribute \src "libresoc.v:125563.3-125573.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125192.3-125202.6" + attribute \src "libresoc.v:125530.3-125540.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125203.3-125213.6" + attribute \src "libresoc.v:125541.3-125551.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125214.3-125224.6" + attribute \src "libresoc.v:125552.3-125562.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125236.3-125246.6" + attribute \src "libresoc.v:125574.3-125584.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125247.3-125257.6" + attribute \src "libresoc.v:125585.3-125595.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125098.3-125144.6" + attribute \src "libresoc.v:125436.3-125482.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125145.3-125191.6" + attribute \src "libresoc.v:125483.3-125529.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125225.3-125235.6" + attribute \src "libresoc.v:125563.3-125573.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125192.3-125202.6" + attribute \src "libresoc.v:125530.3-125540.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125203.3-125213.6" + attribute \src "libresoc.v:125541.3-125551.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125214.3-125224.6" + attribute \src "libresoc.v:125552.3-125562.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:125088.17-125088.104" - wire width 64 $extend$libresoc.v:125088$4698_Y - attribute \src "libresoc.v:125089.18-125089.107" - wire width 64 $extend$libresoc.v:125089$4700_Y - attribute \src "libresoc.v:125092.17-125092.104" - wire width 64 $extend$libresoc.v:125092$4704_Y - attribute \src "libresoc.v:125096.17-125096.102" - wire width 64 $extend$libresoc.v:125096$4709_Y - attribute \src "libresoc.v:125088.17-125088.104" - wire width 64 $pos$libresoc.v:125088$4699_Y - attribute \src "libresoc.v:125089.18-125089.107" - wire width 64 $pos$libresoc.v:125089$4701_Y - attribute \src "libresoc.v:125092.17-125092.104" - wire width 64 $pos$libresoc.v:125092$4705_Y - attribute \src "libresoc.v:125096.17-125096.102" - wire width 64 $pos$libresoc.v:125096$4710_Y - attribute \src "libresoc.v:125090.18-125090.114" - wire width 47 $sshl$libresoc.v:125090$4702_Y - attribute \src "libresoc.v:125091.18-125091.113" - wire width 27 $sshl$libresoc.v:125091$4703_Y - attribute \src "libresoc.v:125093.18-125093.113" - wire width 17 $sshl$libresoc.v:125093$4706_Y - attribute \src "libresoc.v:125094.18-125094.113" - wire width 17 $sshl$libresoc.v:125094$4707_Y - attribute \src "libresoc.v:125095.17-125095.109" - wire width 47 $sshl$libresoc.v:125095$4708_Y + attribute \src "libresoc.v:125426.17-125426.104" + wire width 64 $extend$libresoc.v:125426$4883_Y + attribute \src "libresoc.v:125427.18-125427.107" + wire width 64 $extend$libresoc.v:125427$4885_Y + attribute \src "libresoc.v:125430.17-125430.104" + wire width 64 $extend$libresoc.v:125430$4889_Y + attribute \src "libresoc.v:125434.17-125434.102" + wire width 64 $extend$libresoc.v:125434$4894_Y + attribute \src "libresoc.v:125426.17-125426.104" + wire width 64 $pos$libresoc.v:125426$4884_Y + attribute \src "libresoc.v:125427.18-125427.107" + wire width 64 $pos$libresoc.v:125427$4886_Y + attribute \src "libresoc.v:125430.17-125430.104" + wire width 64 $pos$libresoc.v:125430$4890_Y + attribute \src "libresoc.v:125434.17-125434.102" + wire width 64 $pos$libresoc.v:125434$4895_Y + attribute \src "libresoc.v:125428.18-125428.114" + wire width 47 $sshl$libresoc.v:125428$4887_Y + attribute \src "libresoc.v:125429.18-125429.113" + wire width 27 $sshl$libresoc.v:125429$4888_Y + attribute \src "libresoc.v:125431.18-125431.113" + wire width 17 $sshl$libresoc.v:125431$4891_Y + attribute \src "libresoc.v:125432.18-125432.113" + wire width 17 $sshl$libresoc.v:125432$4892_Y + attribute \src "libresoc.v:125433.17-125433.109" + wire width 47 $sshl$libresoc.v:125433$4893_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -194554,17 +197357,17 @@ module \dec_bi$178 wire width 16 input 4 \DIV_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125010.7-125010.15" + attribute \src "libresoc.v:125348.7-125348.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -194581,80 +197384,80 @@ module \dec_bi$178 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125088$4698 + cell $pos $extend$libresoc.v:125426$4883 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \DIV_sh - connect \Y $extend$libresoc.v:125088$4698_Y + connect \Y $extend$libresoc.v:125426$4883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125089$4700 + cell $pos $extend$libresoc.v:125427$4885 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \DIV_SH32 - connect \Y $extend$libresoc.v:125089$4700_Y + connect \Y $extend$libresoc.v:125427$4885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125092$4704 + cell $pos $extend$libresoc.v:125430$4889 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \DIV_UI - connect \Y $extend$libresoc.v:125092$4704_Y + connect \Y $extend$libresoc.v:125430$4889_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $extend$libresoc.v:125096$4709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $extend$libresoc.v:125434$4894 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125096$4709_Y + connect \Y $extend$libresoc.v:125434$4894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125088$4699 + cell $pos $pos$libresoc.v:125426$4884 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125088$4698_Y - connect \Y $pos$libresoc.v:125088$4699_Y + connect \A $extend$libresoc.v:125426$4883_Y + connect \Y $pos$libresoc.v:125426$4884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125089$4701 + cell $pos $pos$libresoc.v:125427$4886 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125089$4700_Y - connect \Y $pos$libresoc.v:125089$4701_Y + connect \A $extend$libresoc.v:125427$4885_Y + connect \Y $pos$libresoc.v:125427$4886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125092$4705 + cell $pos $pos$libresoc.v:125430$4890 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125092$4704_Y - connect \Y $pos$libresoc.v:125092$4705_Y + connect \A $extend$libresoc.v:125430$4889_Y + connect \Y $pos$libresoc.v:125430$4890_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $pos$libresoc.v:125096$4710 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $pos$libresoc.v:125434$4895 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125096$4709_Y - connect \Y $pos$libresoc.v:125096$4710_Y + connect \A $extend$libresoc.v:125434$4894_Y + connect \Y $pos$libresoc.v:125434$4895_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - cell $sshl $sshl$libresoc.v:125090$4702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:125428$4887 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -194662,10 +197465,10 @@ module \dec_bi$178 parameter \Y_WIDTH 47 connect \A \DIV_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125090$4702_Y + connect \Y $sshl$libresoc.v:125428$4887_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" - cell $sshl $sshl$libresoc.v:125091$4703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125429$4888 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -194673,10 +197476,10 @@ module \dec_bi$178 parameter \Y_WIDTH 27 connect \A \DIV_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125091$4703_Y + connect \Y $sshl$libresoc.v:125429$4888_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" - cell $sshl $sshl$libresoc.v:125093$4706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:125431$4891 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194684,10 +197487,10 @@ module \dec_bi$178 parameter \Y_WIDTH 17 connect \A \DIV_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125093$4706_Y + connect \Y $sshl$libresoc.v:125431$4891_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - cell $sshl $sshl$libresoc.v:125094$4707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:125432$4892 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194695,10 +197498,10 @@ module \dec_bi$178 parameter \Y_WIDTH 17 connect \A \DIV_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125094$4707_Y + connect \Y $sshl$libresoc.v:125432$4892_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $sshl $sshl$libresoc.v:125095$4708 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $sshl $sshl$libresoc.v:125433$4893 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -194706,28 +197509,28 @@ module \dec_bi$178 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125095$4708_Y + connect \Y $sshl$libresoc.v:125433$4893_Y end - attribute \src "libresoc.v:125010.7-125010.20" - process $proc$libresoc.v:125010$4719 + attribute \src "libresoc.v:125348.7-125348.20" + process $proc$libresoc.v:125348$4904 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125098.3-125144.6" - process $proc$libresoc.v:125098$4711 + attribute \src "libresoc.v:125436.3-125482.6" + process $proc$libresoc.v:125436$4896 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125099.5-125099.29" + attribute \src "libresoc.v:125437.5-125437.29" switch \initial - attribute \src "libresoc.v:125099.9-125099.17" + attribute \src "libresoc.v:125437.9-125437.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -194775,18 +197578,18 @@ module \dec_bi$178 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125145.3-125191.6" - process $proc$libresoc.v:125145$4712 + attribute \src "libresoc.v:125483.3-125529.6" + process $proc$libresoc.v:125483$4897 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125146.5-125146.29" + attribute \src "libresoc.v:125484.5-125484.29" switch \initial - attribute \src "libresoc.v:125146.9-125146.17" + attribute \src "libresoc.v:125484.9-125484.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -194834,18 +197637,18 @@ module \dec_bi$178 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125192.3-125202.6" - process $proc$libresoc.v:125192$4713 + attribute \src "libresoc.v:125530.3-125540.6" + process $proc$libresoc.v:125530$4898 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125193.5-125193.29" + attribute \src "libresoc.v:125531.5-125531.29" switch \initial - attribute \src "libresoc.v:125193.9-125193.17" + attribute \src "libresoc.v:125531.9-125531.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -194857,18 +197660,18 @@ module \dec_bi$178 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125203.3-125213.6" - process $proc$libresoc.v:125203$4714 + attribute \src "libresoc.v:125541.3-125551.6" + process $proc$libresoc.v:125541$4899 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125204.5-125204.29" + attribute \src "libresoc.v:125542.5-125542.29" switch \initial - attribute \src "libresoc.v:125204.9-125204.17" + attribute \src "libresoc.v:125542.9-125542.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -194880,18 +197683,18 @@ module \dec_bi$178 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125214.3-125224.6" - process $proc$libresoc.v:125214$4715 + attribute \src "libresoc.v:125552.3-125562.6" + process $proc$libresoc.v:125552$4900 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125215.5-125215.29" + attribute \src "libresoc.v:125553.5-125553.29" switch \initial - attribute \src "libresoc.v:125215.9-125215.17" + attribute \src "libresoc.v:125553.9-125553.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -194903,18 +197706,18 @@ module \dec_bi$178 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125225.3-125235.6" - process $proc$libresoc.v:125225$4716 + attribute \src "libresoc.v:125563.3-125573.6" + process $proc$libresoc.v:125563$4901 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125226.5-125226.29" + attribute \src "libresoc.v:125564.5-125564.29" switch \initial - attribute \src "libresoc.v:125226.9-125226.17" + attribute \src "libresoc.v:125564.9-125564.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -194926,18 +197729,18 @@ module \dec_bi$178 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125236.3-125246.6" - process $proc$libresoc.v:125236$4717 + attribute \src "libresoc.v:125574.3-125584.6" + process $proc$libresoc.v:125574$4902 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125237.5-125237.29" + attribute \src "libresoc.v:125575.5-125575.29" switch \initial - attribute \src "libresoc.v:125237.9-125237.17" + attribute \src "libresoc.v:125575.9-125575.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -194949,18 +197752,18 @@ module \dec_bi$178 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125247.3-125257.6" - process $proc$libresoc.v:125247$4718 + attribute \src "libresoc.v:125585.3-125595.6" + process $proc$libresoc.v:125585$4903 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125248.5-125248.29" + attribute \src "libresoc.v:125586.5-125586.29" switch \initial - attribute \src "libresoc.v:125248.9-125248.17" + attribute \src "libresoc.v:125586.9-125586.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -194972,111 +197775,111 @@ module \dec_bi$178 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:125088$4699_Y - connect \$11 $pos$libresoc.v:125089$4701_Y - connect \$14 $sshl$libresoc.v:125090$4702_Y - connect \$17 $sshl$libresoc.v:125091$4703_Y - connect \$1 $pos$libresoc.v:125092$4705_Y - connect \$20 $sshl$libresoc.v:125093$4706_Y - connect \$23 $sshl$libresoc.v:125094$4707_Y - connect \$4 $sshl$libresoc.v:125095$4708_Y - connect \$3 $pos$libresoc.v:125096$4710_Y + connect \$9 $pos$libresoc.v:125426$4884_Y + connect \$11 $pos$libresoc.v:125427$4886_Y + connect \$14 $sshl$libresoc.v:125428$4887_Y + connect \$17 $sshl$libresoc.v:125429$4888_Y + connect \$1 $pos$libresoc.v:125430$4890_Y + connect \$20 $sshl$libresoc.v:125431$4891_Y + connect \$23 $sshl$libresoc.v:125432$4892_Y + connect \$4 $sshl$libresoc.v:125433$4893_Y + connect \$3 $pos$libresoc.v:125434$4895_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125266.1-125519.10" +attribute \src "libresoc.v:125604.1-125857.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" attribute \generator "nMigen" -module \dec_bi$186 - attribute \src "libresoc.v:125493.3-125503.6" +module \dec_bi$161 + attribute \src "libresoc.v:125831.3-125841.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125504.3-125514.6" + attribute \src "libresoc.v:125842.3-125852.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125355.3-125401.6" + attribute \src "libresoc.v:125693.3-125739.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125402.3-125448.6" + attribute \src "libresoc.v:125740.3-125786.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125267.7-125267.20" + attribute \src "libresoc.v:125605.7-125605.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125482.3-125492.6" + attribute \src "libresoc.v:125820.3-125830.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125449.3-125459.6" + attribute \src "libresoc.v:125787.3-125797.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125460.3-125470.6" + attribute \src "libresoc.v:125798.3-125808.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125471.3-125481.6" + attribute \src "libresoc.v:125809.3-125819.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125493.3-125503.6" + attribute \src "libresoc.v:125831.3-125841.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125504.3-125514.6" + attribute \src "libresoc.v:125842.3-125852.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125355.3-125401.6" + attribute \src "libresoc.v:125693.3-125739.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125402.3-125448.6" + attribute \src "libresoc.v:125740.3-125786.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125482.3-125492.6" + attribute \src "libresoc.v:125820.3-125830.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125449.3-125459.6" + attribute \src "libresoc.v:125787.3-125797.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125460.3-125470.6" + attribute \src "libresoc.v:125798.3-125808.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125471.3-125481.6" + attribute \src "libresoc.v:125809.3-125819.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:125345.17-125345.104" - wire width 64 $extend$libresoc.v:125345$4720_Y - attribute \src "libresoc.v:125346.18-125346.107" - wire width 64 $extend$libresoc.v:125346$4722_Y - attribute \src "libresoc.v:125349.17-125349.104" - wire width 64 $extend$libresoc.v:125349$4726_Y - attribute \src "libresoc.v:125353.17-125353.102" - wire width 64 $extend$libresoc.v:125353$4731_Y - attribute \src "libresoc.v:125345.17-125345.104" - wire width 64 $pos$libresoc.v:125345$4721_Y - attribute \src "libresoc.v:125346.18-125346.107" - wire width 64 $pos$libresoc.v:125346$4723_Y - attribute \src "libresoc.v:125349.17-125349.104" - wire width 64 $pos$libresoc.v:125349$4727_Y - attribute \src "libresoc.v:125353.17-125353.102" - wire width 64 $pos$libresoc.v:125353$4732_Y - attribute \src "libresoc.v:125347.18-125347.114" - wire width 47 $sshl$libresoc.v:125347$4724_Y - attribute \src "libresoc.v:125348.18-125348.113" - wire width 27 $sshl$libresoc.v:125348$4725_Y - attribute \src "libresoc.v:125350.18-125350.113" - wire width 17 $sshl$libresoc.v:125350$4728_Y - attribute \src "libresoc.v:125351.18-125351.113" - wire width 17 $sshl$libresoc.v:125351$4729_Y - attribute \src "libresoc.v:125352.17-125352.109" - wire width 47 $sshl$libresoc.v:125352$4730_Y + attribute \src "libresoc.v:125683.17-125683.104" + wire width 64 $extend$libresoc.v:125683$4905_Y + attribute \src "libresoc.v:125684.18-125684.107" + wire width 64 $extend$libresoc.v:125684$4907_Y + attribute \src "libresoc.v:125687.17-125687.104" + wire width 64 $extend$libresoc.v:125687$4911_Y + attribute \src "libresoc.v:125691.17-125691.102" + wire width 64 $extend$libresoc.v:125691$4916_Y + attribute \src "libresoc.v:125683.17-125683.104" + wire width 64 $pos$libresoc.v:125683$4906_Y + attribute \src "libresoc.v:125684.18-125684.107" + wire width 64 $pos$libresoc.v:125684$4908_Y + attribute \src "libresoc.v:125687.17-125687.104" + wire width 64 $pos$libresoc.v:125687$4912_Y + attribute \src "libresoc.v:125691.17-125691.102" + wire width 64 $pos$libresoc.v:125691$4917_Y + attribute \src "libresoc.v:125685.18-125685.114" + wire width 47 $sshl$libresoc.v:125685$4909_Y + attribute \src "libresoc.v:125686.18-125686.113" + wire width 27 $sshl$libresoc.v:125686$4910_Y + attribute \src "libresoc.v:125688.18-125688.113" + wire width 17 $sshl$libresoc.v:125688$4913_Y + attribute \src "libresoc.v:125689.18-125689.113" + wire width 17 $sshl$libresoc.v:125689$4914_Y + attribute \src "libresoc.v:125690.17-125690.109" + wire width 47 $sshl$libresoc.v:125690$4915_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -195094,17 +197897,17 @@ module \dec_bi$186 wire width 16 input 4 \MUL_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125267.7-125267.15" + attribute \src "libresoc.v:125605.7-125605.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -195121,80 +197924,80 @@ module \dec_bi$186 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125345$4720 + cell $pos $extend$libresoc.v:125683$4905 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \MUL_sh - connect \Y $extend$libresoc.v:125345$4720_Y + connect \Y $extend$libresoc.v:125683$4905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125346$4722 + cell $pos $extend$libresoc.v:125684$4907 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \MUL_SH32 - connect \Y $extend$libresoc.v:125346$4722_Y + connect \Y $extend$libresoc.v:125684$4907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125349$4726 + cell $pos $extend$libresoc.v:125687$4911 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \MUL_UI - connect \Y $extend$libresoc.v:125349$4726_Y + connect \Y $extend$libresoc.v:125687$4911_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $extend$libresoc.v:125353$4731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $extend$libresoc.v:125691$4916 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125353$4731_Y + connect \Y $extend$libresoc.v:125691$4916_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125345$4721 + cell $pos $pos$libresoc.v:125683$4906 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125345$4720_Y - connect \Y $pos$libresoc.v:125345$4721_Y + connect \A $extend$libresoc.v:125683$4905_Y + connect \Y $pos$libresoc.v:125683$4906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125346$4723 + cell $pos $pos$libresoc.v:125684$4908 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125346$4722_Y - connect \Y $pos$libresoc.v:125346$4723_Y + connect \A $extend$libresoc.v:125684$4907_Y + connect \Y $pos$libresoc.v:125684$4908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125349$4727 + cell $pos $pos$libresoc.v:125687$4912 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125349$4726_Y - connect \Y $pos$libresoc.v:125349$4727_Y + connect \A $extend$libresoc.v:125687$4911_Y + connect \Y $pos$libresoc.v:125687$4912_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $pos$libresoc.v:125353$4732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $pos$libresoc.v:125691$4917 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125353$4731_Y - connect \Y $pos$libresoc.v:125353$4732_Y + connect \A $extend$libresoc.v:125691$4916_Y + connect \Y $pos$libresoc.v:125691$4917_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - cell $sshl $sshl$libresoc.v:125347$4724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:125685$4909 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -195202,10 +198005,10 @@ module \dec_bi$186 parameter \Y_WIDTH 47 connect \A \MUL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125347$4724_Y + connect \Y $sshl$libresoc.v:125685$4909_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" - cell $sshl $sshl$libresoc.v:125348$4725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125686$4910 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -195213,10 +198016,10 @@ module \dec_bi$186 parameter \Y_WIDTH 27 connect \A \MUL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125348$4725_Y + connect \Y $sshl$libresoc.v:125686$4910_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" - cell $sshl $sshl$libresoc.v:125350$4728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:125688$4913 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195224,10 +198027,10 @@ module \dec_bi$186 parameter \Y_WIDTH 17 connect \A \MUL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125350$4728_Y + connect \Y $sshl$libresoc.v:125688$4913_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - cell $sshl $sshl$libresoc.v:125351$4729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:125689$4914 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195235,10 +198038,10 @@ module \dec_bi$186 parameter \Y_WIDTH 17 connect \A \MUL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125351$4729_Y + connect \Y $sshl$libresoc.v:125689$4914_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $sshl $sshl$libresoc.v:125352$4730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $sshl $sshl$libresoc.v:125690$4915 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -195246,28 +198049,28 @@ module \dec_bi$186 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125352$4730_Y + connect \Y $sshl$libresoc.v:125690$4915_Y end - attribute \src "libresoc.v:125267.7-125267.20" - process $proc$libresoc.v:125267$4741 + attribute \src "libresoc.v:125605.7-125605.20" + process $proc$libresoc.v:125605$4926 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125355.3-125401.6" - process $proc$libresoc.v:125355$4733 + attribute \src "libresoc.v:125693.3-125739.6" + process $proc$libresoc.v:125693$4918 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125356.5-125356.29" + attribute \src "libresoc.v:125694.5-125694.29" switch \initial - attribute \src "libresoc.v:125356.9-125356.17" + attribute \src "libresoc.v:125694.9-125694.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -195315,18 +198118,18 @@ module \dec_bi$186 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125402.3-125448.6" - process $proc$libresoc.v:125402$4734 + attribute \src "libresoc.v:125740.3-125786.6" + process $proc$libresoc.v:125740$4919 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125403.5-125403.29" + attribute \src "libresoc.v:125741.5-125741.29" switch \initial - attribute \src "libresoc.v:125403.9-125403.17" + attribute \src "libresoc.v:125741.9-125741.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -195374,18 +198177,18 @@ module \dec_bi$186 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125449.3-125459.6" - process $proc$libresoc.v:125449$4735 + attribute \src "libresoc.v:125787.3-125797.6" + process $proc$libresoc.v:125787$4920 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125450.5-125450.29" + attribute \src "libresoc.v:125788.5-125788.29" switch \initial - attribute \src "libresoc.v:125450.9-125450.17" + attribute \src "libresoc.v:125788.9-125788.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -195397,18 +198200,18 @@ module \dec_bi$186 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125460.3-125470.6" - process $proc$libresoc.v:125460$4736 + attribute \src "libresoc.v:125798.3-125808.6" + process $proc$libresoc.v:125798$4921 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125461.5-125461.29" + attribute \src "libresoc.v:125799.5-125799.29" switch \initial - attribute \src "libresoc.v:125461.9-125461.17" + attribute \src "libresoc.v:125799.9-125799.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -195420,18 +198223,18 @@ module \dec_bi$186 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125471.3-125481.6" - process $proc$libresoc.v:125471$4737 + attribute \src "libresoc.v:125809.3-125819.6" + process $proc$libresoc.v:125809$4922 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125472.5-125472.29" + attribute \src "libresoc.v:125810.5-125810.29" switch \initial - attribute \src "libresoc.v:125472.9-125472.17" + attribute \src "libresoc.v:125810.9-125810.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -195443,18 +198246,18 @@ module \dec_bi$186 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125482.3-125492.6" - process $proc$libresoc.v:125482$4738 + attribute \src "libresoc.v:125820.3-125830.6" + process $proc$libresoc.v:125820$4923 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125483.5-125483.29" + attribute \src "libresoc.v:125821.5-125821.29" switch \initial - attribute \src "libresoc.v:125483.9-125483.17" + attribute \src "libresoc.v:125821.9-125821.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -195466,18 +198269,18 @@ module \dec_bi$186 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125493.3-125503.6" - process $proc$libresoc.v:125493$4739 + attribute \src "libresoc.v:125831.3-125841.6" + process $proc$libresoc.v:125831$4924 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125494.5-125494.29" + attribute \src "libresoc.v:125832.5-125832.29" switch \initial - attribute \src "libresoc.v:125494.9-125494.17" + attribute \src "libresoc.v:125832.9-125832.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -195489,18 +198292,18 @@ module \dec_bi$186 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125504.3-125514.6" - process $proc$libresoc.v:125504$4740 + attribute \src "libresoc.v:125842.3-125852.6" + process $proc$libresoc.v:125842$4925 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125505.5-125505.29" + attribute \src "libresoc.v:125843.5-125843.29" switch \initial - attribute \src "libresoc.v:125505.9-125505.17" + attribute \src "libresoc.v:125843.9-125843.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -195512,111 +198315,111 @@ module \dec_bi$186 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:125345$4721_Y - connect \$11 $pos$libresoc.v:125346$4723_Y - connect \$14 $sshl$libresoc.v:125347$4724_Y - connect \$17 $sshl$libresoc.v:125348$4725_Y - connect \$1 $pos$libresoc.v:125349$4727_Y - connect \$20 $sshl$libresoc.v:125350$4728_Y - connect \$23 $sshl$libresoc.v:125351$4729_Y - connect \$4 $sshl$libresoc.v:125352$4730_Y - connect \$3 $pos$libresoc.v:125353$4732_Y + connect \$9 $pos$libresoc.v:125683$4906_Y + connect \$11 $pos$libresoc.v:125684$4908_Y + connect \$14 $sshl$libresoc.v:125685$4909_Y + connect \$17 $sshl$libresoc.v:125686$4910_Y + connect \$1 $pos$libresoc.v:125687$4912_Y + connect \$20 $sshl$libresoc.v:125688$4913_Y + connect \$23 $sshl$libresoc.v:125689$4914_Y + connect \$4 $sshl$libresoc.v:125690$4915_Y + connect \$3 $pos$libresoc.v:125691$4917_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125523.1-125776.10" +attribute \src "libresoc.v:125861.1-126114.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" attribute \generator "nMigen" -module \dec_bi$194 - attribute \src "libresoc.v:125750.3-125760.6" +module \dec_bi$165 + attribute \src "libresoc.v:126088.3-126098.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:125761.3-125771.6" + attribute \src "libresoc.v:126099.3-126109.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125612.3-125658.6" + attribute \src "libresoc.v:125950.3-125996.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125659.3-125705.6" + attribute \src "libresoc.v:125997.3-126043.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125524.7-125524.20" + attribute \src "libresoc.v:125862.7-125862.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125739.3-125749.6" + attribute \src "libresoc.v:126077.3-126087.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125706.3-125716.6" + attribute \src "libresoc.v:126044.3-126054.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125717.3-125727.6" + attribute \src "libresoc.v:126055.3-126065.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125728.3-125738.6" + attribute \src "libresoc.v:126066.3-126076.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:125750.3-125760.6" + attribute \src "libresoc.v:126088.3-126098.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:125761.3-125771.6" + attribute \src "libresoc.v:126099.3-126109.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125612.3-125658.6" + attribute \src "libresoc.v:125950.3-125996.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125659.3-125705.6" + attribute \src "libresoc.v:125997.3-126043.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125739.3-125749.6" + attribute \src "libresoc.v:126077.3-126087.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125706.3-125716.6" + attribute \src "libresoc.v:126044.3-126054.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125717.3-125727.6" + attribute \src "libresoc.v:126055.3-126065.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125728.3-125738.6" + attribute \src "libresoc.v:126066.3-126076.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:125602.17-125602.110" - wire width 64 $extend$libresoc.v:125602$4742_Y - attribute \src "libresoc.v:125603.18-125603.113" - wire width 64 $extend$libresoc.v:125603$4744_Y - attribute \src "libresoc.v:125606.17-125606.110" - wire width 64 $extend$libresoc.v:125606$4748_Y - attribute \src "libresoc.v:125610.17-125610.102" - wire width 64 $extend$libresoc.v:125610$4753_Y - attribute \src "libresoc.v:125602.17-125602.110" - wire width 64 $pos$libresoc.v:125602$4743_Y - attribute \src "libresoc.v:125603.18-125603.113" - wire width 64 $pos$libresoc.v:125603$4745_Y - attribute \src "libresoc.v:125606.17-125606.110" - wire width 64 $pos$libresoc.v:125606$4749_Y - attribute \src "libresoc.v:125610.17-125610.102" - wire width 64 $pos$libresoc.v:125610$4754_Y - attribute \src "libresoc.v:125604.18-125604.120" - wire width 47 $sshl$libresoc.v:125604$4746_Y - attribute \src "libresoc.v:125605.18-125605.119" - wire width 27 $sshl$libresoc.v:125605$4747_Y - attribute \src "libresoc.v:125607.18-125607.119" - wire width 17 $sshl$libresoc.v:125607$4750_Y - attribute \src "libresoc.v:125608.18-125608.119" - wire width 17 $sshl$libresoc.v:125608$4751_Y - attribute \src "libresoc.v:125609.17-125609.109" - wire width 47 $sshl$libresoc.v:125609$4752_Y + attribute \src "libresoc.v:125940.17-125940.110" + wire width 64 $extend$libresoc.v:125940$4927_Y + attribute \src "libresoc.v:125941.18-125941.113" + wire width 64 $extend$libresoc.v:125941$4929_Y + attribute \src "libresoc.v:125944.17-125944.110" + wire width 64 $extend$libresoc.v:125944$4933_Y + attribute \src "libresoc.v:125948.17-125948.102" + wire width 64 $extend$libresoc.v:125948$4938_Y + attribute \src "libresoc.v:125940.17-125940.110" + wire width 64 $pos$libresoc.v:125940$4928_Y + attribute \src "libresoc.v:125941.18-125941.113" + wire width 64 $pos$libresoc.v:125941$4930_Y + attribute \src "libresoc.v:125944.17-125944.110" + wire width 64 $pos$libresoc.v:125944$4934_Y + attribute \src "libresoc.v:125948.17-125948.102" + wire width 64 $pos$libresoc.v:125948$4939_Y + attribute \src "libresoc.v:125942.18-125942.120" + wire width 47 $sshl$libresoc.v:125942$4931_Y + attribute \src "libresoc.v:125943.18-125943.119" + wire width 27 $sshl$libresoc.v:125943$4932_Y + attribute \src "libresoc.v:125945.18-125945.119" + wire width 17 $sshl$libresoc.v:125945$4935_Y + attribute \src "libresoc.v:125946.18-125946.119" + wire width 17 $sshl$libresoc.v:125946$4936_Y + attribute \src "libresoc.v:125947.17-125947.109" + wire width 47 $sshl$libresoc.v:125947$4937_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -195634,17 +198437,17 @@ module \dec_bi$194 wire width 16 input 4 \SHIFT_ROT_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125524.7-125524.15" + attribute \src "libresoc.v:125862.7-125862.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -195661,80 +198464,80 @@ module \dec_bi$194 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125602$4742 + cell $pos $extend$libresoc.v:125940$4927 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_sh - connect \Y $extend$libresoc.v:125602$4742_Y + connect \Y $extend$libresoc.v:125940$4927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125603$4744 + cell $pos $extend$libresoc.v:125941$4929 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_SH32 - connect \Y $extend$libresoc.v:125603$4744_Y + connect \Y $extend$libresoc.v:125941$4929_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125606$4748 + cell $pos $extend$libresoc.v:125944$4933 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_UI - connect \Y $extend$libresoc.v:125606$4748_Y + connect \Y $extend$libresoc.v:125944$4933_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $extend$libresoc.v:125610$4753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $extend$libresoc.v:125948$4938 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125610$4753_Y + connect \Y $extend$libresoc.v:125948$4938_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125602$4743 + cell $pos $pos$libresoc.v:125940$4928 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125602$4742_Y - connect \Y $pos$libresoc.v:125602$4743_Y + connect \A $extend$libresoc.v:125940$4927_Y + connect \Y $pos$libresoc.v:125940$4928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125603$4745 + cell $pos $pos$libresoc.v:125941$4930 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125603$4744_Y - connect \Y $pos$libresoc.v:125603$4745_Y + connect \A $extend$libresoc.v:125941$4929_Y + connect \Y $pos$libresoc.v:125941$4930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125606$4749 + cell $pos $pos$libresoc.v:125944$4934 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125606$4748_Y - connect \Y $pos$libresoc.v:125606$4749_Y + connect \A $extend$libresoc.v:125944$4933_Y + connect \Y $pos$libresoc.v:125944$4934_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $pos$libresoc.v:125610$4754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $pos$libresoc.v:125948$4939 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125610$4753_Y - connect \Y $pos$libresoc.v:125610$4754_Y + connect \A $extend$libresoc.v:125948$4938_Y + connect \Y $pos$libresoc.v:125948$4939_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - cell $sshl $sshl$libresoc.v:125604$4746 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:125942$4931 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -195742,10 +198545,10 @@ module \dec_bi$194 parameter \Y_WIDTH 47 connect \A \SHIFT_ROT_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125604$4746_Y + connect \Y $sshl$libresoc.v:125942$4931_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" - cell $sshl $sshl$libresoc.v:125605$4747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:125943$4932 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -195753,10 +198556,10 @@ module \dec_bi$194 parameter \Y_WIDTH 27 connect \A \SHIFT_ROT_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125605$4747_Y + connect \Y $sshl$libresoc.v:125943$4932_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" - cell $sshl $sshl$libresoc.v:125607$4750 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:125945$4935 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195764,10 +198567,10 @@ module \dec_bi$194 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125607$4750_Y + connect \Y $sshl$libresoc.v:125945$4935_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - cell $sshl $sshl$libresoc.v:125608$4751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:125946$4936 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195775,10 +198578,10 @@ module \dec_bi$194 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125608$4751_Y + connect \Y $sshl$libresoc.v:125946$4936_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $sshl $sshl$libresoc.v:125609$4752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $sshl $sshl$libresoc.v:125947$4937 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -195786,28 +198589,28 @@ module \dec_bi$194 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125609$4752_Y + connect \Y $sshl$libresoc.v:125947$4937_Y end - attribute \src "libresoc.v:125524.7-125524.20" - process $proc$libresoc.v:125524$4763 + attribute \src "libresoc.v:125862.7-125862.20" + process $proc$libresoc.v:125862$4948 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125612.3-125658.6" - process $proc$libresoc.v:125612$4755 + attribute \src "libresoc.v:125950.3-125996.6" + process $proc$libresoc.v:125950$4940 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125613.5-125613.29" + attribute \src "libresoc.v:125951.5-125951.29" switch \initial - attribute \src "libresoc.v:125613.9-125613.17" + attribute \src "libresoc.v:125951.9-125951.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -195855,18 +198658,18 @@ module \dec_bi$194 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125659.3-125705.6" - process $proc$libresoc.v:125659$4756 + attribute \src "libresoc.v:125997.3-126043.6" + process $proc$libresoc.v:125997$4941 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125660.5-125660.29" + attribute \src "libresoc.v:125998.5-125998.29" switch \initial - attribute \src "libresoc.v:125660.9-125660.17" + attribute \src "libresoc.v:125998.9-125998.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -195914,18 +198717,18 @@ module \dec_bi$194 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125706.3-125716.6" - process $proc$libresoc.v:125706$4757 + attribute \src "libresoc.v:126044.3-126054.6" + process $proc$libresoc.v:126044$4942 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125707.5-125707.29" + attribute \src "libresoc.v:126045.5-126045.29" switch \initial - attribute \src "libresoc.v:125707.9-125707.17" + attribute \src "libresoc.v:126045.9-126045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -195937,18 +198740,18 @@ module \dec_bi$194 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125717.3-125727.6" - process $proc$libresoc.v:125717$4758 + attribute \src "libresoc.v:126055.3-126065.6" + process $proc$libresoc.v:126055$4943 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125718.5-125718.29" + attribute \src "libresoc.v:126056.5-126056.29" switch \initial - attribute \src "libresoc.v:125718.9-125718.17" + attribute \src "libresoc.v:126056.9-126056.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -195960,18 +198763,18 @@ module \dec_bi$194 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125728.3-125738.6" - process $proc$libresoc.v:125728$4759 + attribute \src "libresoc.v:126066.3-126076.6" + process $proc$libresoc.v:126066$4944 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125729.5-125729.29" + attribute \src "libresoc.v:126067.5-126067.29" switch \initial - attribute \src "libresoc.v:125729.9-125729.17" + attribute \src "libresoc.v:126067.9-126067.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -195983,18 +198786,18 @@ module \dec_bi$194 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125739.3-125749.6" - process $proc$libresoc.v:125739$4760 + attribute \src "libresoc.v:126077.3-126087.6" + process $proc$libresoc.v:126077$4945 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125740.5-125740.29" + attribute \src "libresoc.v:126078.5-126078.29" switch \initial - attribute \src "libresoc.v:125740.9-125740.17" + attribute \src "libresoc.v:126078.9-126078.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -196006,18 +198809,18 @@ module \dec_bi$194 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:125750.3-125760.6" - process $proc$libresoc.v:125750$4761 + attribute \src "libresoc.v:126088.3-126098.6" + process $proc$libresoc.v:126088$4946 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:125751.5-125751.29" + attribute \src "libresoc.v:126089.5-126089.29" switch \initial - attribute \src "libresoc.v:125751.9-125751.17" + attribute \src "libresoc.v:126089.9-126089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -196029,18 +198832,18 @@ module \dec_bi$194 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:125761.3-125771.6" - process $proc$libresoc.v:125761$4762 + attribute \src "libresoc.v:126099.3-126109.6" + process $proc$libresoc.v:126099$4947 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:125762.5-125762.29" + attribute \src "libresoc.v:126100.5-126100.29" switch \initial - attribute \src "libresoc.v:125762.9-125762.17" + attribute \src "libresoc.v:126100.9-126100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -196052,111 +198855,111 @@ module \dec_bi$194 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:125602$4743_Y - connect \$11 $pos$libresoc.v:125603$4745_Y - connect \$14 $sshl$libresoc.v:125604$4746_Y - connect \$17 $sshl$libresoc.v:125605$4747_Y - connect \$1 $pos$libresoc.v:125606$4749_Y - connect \$20 $sshl$libresoc.v:125607$4750_Y - connect \$23 $sshl$libresoc.v:125608$4751_Y - connect \$4 $sshl$libresoc.v:125609$4752_Y - connect \$3 $pos$libresoc.v:125610$4754_Y + connect \$9 $pos$libresoc.v:125940$4928_Y + connect \$11 $pos$libresoc.v:125941$4930_Y + connect \$14 $sshl$libresoc.v:125942$4931_Y + connect \$17 $sshl$libresoc.v:125943$4932_Y + connect \$1 $pos$libresoc.v:125944$4934_Y + connect \$20 $sshl$libresoc.v:125945$4935_Y + connect \$23 $sshl$libresoc.v:125946$4936_Y + connect \$4 $sshl$libresoc.v:125947$4937_Y + connect \$3 $pos$libresoc.v:125948$4939_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:125780.1-126033.10" +attribute \src "libresoc.v:126118.1-126371.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" attribute \generator "nMigen" -module \dec_bi$203 - attribute \src "libresoc.v:126007.3-126017.6" +module \dec_bi$170 + attribute \src "libresoc.v:126345.3-126355.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:126018.3-126028.6" + attribute \src "libresoc.v:126356.3-126366.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:125869.3-125915.6" + attribute \src "libresoc.v:126207.3-126253.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:125916.3-125962.6" + attribute \src "libresoc.v:126254.3-126300.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:125781.7-125781.20" + attribute \src "libresoc.v:126119.7-126119.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125996.3-126006.6" + attribute \src "libresoc.v:126334.3-126344.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:125963.3-125973.6" + attribute \src "libresoc.v:126301.3-126311.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:125974.3-125984.6" + attribute \src "libresoc.v:126312.3-126322.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:125985.3-125995.6" + attribute \src "libresoc.v:126323.3-126333.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:126007.3-126017.6" + attribute \src "libresoc.v:126345.3-126355.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:126018.3-126028.6" + attribute \src "libresoc.v:126356.3-126366.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:125869.3-125915.6" + attribute \src "libresoc.v:126207.3-126253.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:125916.3-125962.6" + attribute \src "libresoc.v:126254.3-126300.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125996.3-126006.6" + attribute \src "libresoc.v:126334.3-126344.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:125963.3-125973.6" + attribute \src "libresoc.v:126301.3-126311.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:125974.3-125984.6" + attribute \src "libresoc.v:126312.3-126322.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:125985.3-125995.6" + attribute \src "libresoc.v:126323.3-126333.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:125859.17-125859.105" - wire width 64 $extend$libresoc.v:125859$4764_Y - attribute \src "libresoc.v:125860.18-125860.108" - wire width 64 $extend$libresoc.v:125860$4766_Y - attribute \src "libresoc.v:125863.17-125863.105" - wire width 64 $extend$libresoc.v:125863$4770_Y - attribute \src "libresoc.v:125867.17-125867.102" - wire width 64 $extend$libresoc.v:125867$4775_Y - attribute \src "libresoc.v:125859.17-125859.105" - wire width 64 $pos$libresoc.v:125859$4765_Y - attribute \src "libresoc.v:125860.18-125860.108" - wire width 64 $pos$libresoc.v:125860$4767_Y - attribute \src "libresoc.v:125863.17-125863.105" - wire width 64 $pos$libresoc.v:125863$4771_Y - attribute \src "libresoc.v:125867.17-125867.102" - wire width 64 $pos$libresoc.v:125867$4776_Y - attribute \src "libresoc.v:125861.18-125861.115" - wire width 47 $sshl$libresoc.v:125861$4768_Y - attribute \src "libresoc.v:125862.18-125862.114" - wire width 27 $sshl$libresoc.v:125862$4769_Y - attribute \src "libresoc.v:125864.18-125864.114" - wire width 17 $sshl$libresoc.v:125864$4772_Y - attribute \src "libresoc.v:125865.18-125865.114" - wire width 17 $sshl$libresoc.v:125865$4773_Y - attribute \src "libresoc.v:125866.17-125866.109" - wire width 47 $sshl$libresoc.v:125866$4774_Y + attribute \src "libresoc.v:126197.17-126197.105" + wire width 64 $extend$libresoc.v:126197$4949_Y + attribute \src "libresoc.v:126198.18-126198.108" + wire width 64 $extend$libresoc.v:126198$4951_Y + attribute \src "libresoc.v:126201.17-126201.105" + wire width 64 $extend$libresoc.v:126201$4955_Y + attribute \src "libresoc.v:126205.17-126205.102" + wire width 64 $extend$libresoc.v:126205$4960_Y + attribute \src "libresoc.v:126197.17-126197.105" + wire width 64 $pos$libresoc.v:126197$4950_Y + attribute \src "libresoc.v:126198.18-126198.108" + wire width 64 $pos$libresoc.v:126198$4952_Y + attribute \src "libresoc.v:126201.17-126201.105" + wire width 64 $pos$libresoc.v:126201$4956_Y + attribute \src "libresoc.v:126205.17-126205.102" + wire width 64 $pos$libresoc.v:126205$4961_Y + attribute \src "libresoc.v:126199.18-126199.115" + wire width 47 $sshl$libresoc.v:126199$4953_Y + attribute \src "libresoc.v:126200.18-126200.114" + wire width 27 $sshl$libresoc.v:126200$4954_Y + attribute \src "libresoc.v:126202.18-126202.114" + wire width 17 $sshl$libresoc.v:126202$4957_Y + attribute \src "libresoc.v:126203.18-126203.114" + wire width 17 $sshl$libresoc.v:126203$4958_Y + attribute \src "libresoc.v:126204.17-126204.109" + wire width 47 $sshl$libresoc.v:126204$4959_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:274" wire width 64 \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 64 \$9 @@ -196174,17 +198977,17 @@ module \dec_bi$203 wire width 16 input 4 \LDST_UI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 6 input 6 \LDST_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" wire width 16 \ds attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:125781.7-125781.15" + attribute \src "libresoc.v:126119.7-126119.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 26 \li attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" @@ -196201,80 +199004,80 @@ module \dec_bi$203 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:231" wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125859$4764 + cell $pos $extend$libresoc.v:126197$4949 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LDST_sh - connect \Y $extend$libresoc.v:125859$4764_Y + connect \Y $extend$libresoc.v:126197$4949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125860$4766 + cell $pos $extend$libresoc.v:126198$4951 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LDST_SH32 - connect \Y $extend$libresoc.v:125860$4766_Y + connect \Y $extend$libresoc.v:126198$4951_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $extend$libresoc.v:125863$4770 + cell $pos $extend$libresoc.v:126201$4955 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LDST_UI - connect \Y $extend$libresoc.v:125863$4770_Y + connect \Y $extend$libresoc.v:126201$4955_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $extend$libresoc.v:125867$4775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $extend$libresoc.v:126205$4960 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:125867$4775_Y + connect \Y $extend$libresoc.v:126205$4960_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125859$4765 + cell $pos $pos$libresoc.v:126197$4950 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125859$4764_Y - connect \Y $pos$libresoc.v:125859$4765_Y + connect \A $extend$libresoc.v:126197$4949_Y + connect \Y $pos$libresoc.v:126197$4950_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125860$4767 + cell $pos $pos$libresoc.v:126198$4952 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125860$4766_Y - connect \Y $pos$libresoc.v:125860$4767_Y + connect \A $extend$libresoc.v:126198$4951_Y + connect \Y $pos$libresoc.v:126198$4952_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - cell $pos $pos$libresoc.v:125863$4771 + cell $pos $pos$libresoc.v:126201$4956 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125863$4770_Y - connect \Y $pos$libresoc.v:125863$4771_Y + connect \A $extend$libresoc.v:126201$4955_Y + connect \Y $pos$libresoc.v:126201$4956_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $pos $pos$libresoc.v:125867$4776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $pos $pos$libresoc.v:126205$4961 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:125867$4775_Y - connect \Y $pos$libresoc.v:125867$4776_Y + connect \A $extend$libresoc.v:126205$4960_Y + connect \Y $pos$libresoc.v:126205$4961_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - cell $sshl $sshl$libresoc.v:125861$4768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$libresoc.v:126199$4953 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196282,10 +199085,10 @@ module \dec_bi$203 parameter \Y_WIDTH 47 connect \A \LDST_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:125861$4768_Y + connect \Y $sshl$libresoc.v:126199$4953_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" - cell $sshl $sshl$libresoc.v:125862$4769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" + cell $sshl $sshl$libresoc.v:126200$4954 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -196293,10 +199096,10 @@ module \dec_bi$203 parameter \Y_WIDTH 27 connect \A \LDST_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:125862$4769_Y + connect \Y $sshl$libresoc.v:126200$4954_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" - cell $sshl $sshl$libresoc.v:125864$4772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" + cell $sshl $sshl$libresoc.v:126202$4957 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196304,10 +199107,10 @@ module \dec_bi$203 parameter \Y_WIDTH 17 connect \A \LDST_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:125864$4772_Y + connect \Y $sshl$libresoc.v:126202$4957_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - cell $sshl $sshl$libresoc.v:125865$4773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + cell $sshl $sshl$libresoc.v:126203$4958 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196315,10 +199118,10 @@ module \dec_bi$203 parameter \Y_WIDTH 17 connect \A \LDST_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:125865$4773_Y + connect \Y $sshl$libresoc.v:126203$4958_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" - cell $sshl $sshl$libresoc.v:125866$4774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" + cell $sshl $sshl$libresoc.v:126204$4959 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -196326,28 +199129,28 @@ module \dec_bi$203 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:125866$4774_Y + connect \Y $sshl$libresoc.v:126204$4959_Y end - attribute \src "libresoc.v:125781.7-125781.20" - process $proc$libresoc.v:125781$4785 + attribute \src "libresoc.v:126119.7-126119.20" + process $proc$libresoc.v:126119$4970 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125869.3-125915.6" - process $proc$libresoc.v:125869$4777 + attribute \src "libresoc.v:126207.3-126253.6" + process $proc$libresoc.v:126207$4962 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:125870.5-125870.29" + attribute \src "libresoc.v:126208.5-126208.29" switch \initial - attribute \src "libresoc.v:125870.9-125870.17" + attribute \src "libresoc.v:126208.9-126208.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196395,18 +199198,18 @@ module \dec_bi$203 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:125916.3-125962.6" - process $proc$libresoc.v:125916$4778 + attribute \src "libresoc.v:126254.3-126300.6" + process $proc$libresoc.v:126254$4963 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:125917.5-125917.29" + attribute \src "libresoc.v:126255.5-126255.29" switch \initial - attribute \src "libresoc.v:125917.9-125917.17" + attribute \src "libresoc.v:126255.9-126255.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0010 @@ -196454,18 +199257,18 @@ module \dec_bi$203 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:125963.3-125973.6" - process $proc$libresoc.v:125963$4779 + attribute \src "libresoc.v:126301.3-126311.6" + process $proc$libresoc.v:126301$4964 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:125964.5-125964.29" + attribute \src "libresoc.v:126302.5-126302.29" switch \initial - attribute \src "libresoc.v:125964.9-125964.17" + attribute \src "libresoc.v:126302.9-126302.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0011 @@ -196477,18 +199280,18 @@ module \dec_bi$203 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:125974.3-125984.6" - process $proc$libresoc.v:125974$4780 + attribute \src "libresoc.v:126312.3-126322.6" + process $proc$libresoc.v:126312$4965 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:125975.5-125975.29" + attribute \src "libresoc.v:126313.5-126313.29" switch \initial - attribute \src "libresoc.v:125975.9-125975.17" + attribute \src "libresoc.v:126313.9-126313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0101 @@ -196500,18 +199303,18 @@ module \dec_bi$203 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:125985.3-125995.6" - process $proc$libresoc.v:125985$4781 + attribute \src "libresoc.v:126323.3-126333.6" + process $proc$libresoc.v:126323$4966 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:125986.5-125986.29" + attribute \src "libresoc.v:126324.5-126324.29" switch \initial - attribute \src "libresoc.v:125986.9-125986.17" + attribute \src "libresoc.v:126324.9-126324.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0100 @@ -196523,18 +199326,18 @@ module \dec_bi$203 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:125996.3-126006.6" - process $proc$libresoc.v:125996$4782 + attribute \src "libresoc.v:126334.3-126344.6" + process $proc$libresoc.v:126334$4967 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:125997.5-125997.29" + attribute \src "libresoc.v:126335.5-126335.29" switch \initial - attribute \src "libresoc.v:125997.9-125997.17" + attribute \src "libresoc.v:126335.9-126335.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0110 @@ -196546,18 +199349,18 @@ module \dec_bi$203 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:126007.3-126017.6" - process $proc$libresoc.v:126007$4783 + attribute \src "libresoc.v:126345.3-126355.6" + process $proc$libresoc.v:126345$4968 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:126008.5-126008.29" + attribute \src "libresoc.v:126346.5-126346.29" switch \initial - attribute \src "libresoc.v:126008.9-126008.17" + attribute \src "libresoc.v:126346.9-126346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'0111 @@ -196569,18 +199372,18 @@ module \dec_bi$203 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:126018.3-126028.6" - process $proc$libresoc.v:126018$4784 + attribute \src "libresoc.v:126356.3-126366.6" + process $proc$libresoc.v:126356$4969 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:126019.5-126019.29" + attribute \src "libresoc.v:126357.5-126357.29" switch \initial - attribute \src "libresoc.v:126019.9-126019.17" + attribute \src "libresoc.v:126357.9-126357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 4'1000 @@ -196592,41 +199395,41 @@ module \dec_bi$203 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:125859$4765_Y - connect \$11 $pos$libresoc.v:125860$4767_Y - connect \$14 $sshl$libresoc.v:125861$4768_Y - connect \$17 $sshl$libresoc.v:125862$4769_Y - connect \$1 $pos$libresoc.v:125863$4771_Y - connect \$20 $sshl$libresoc.v:125864$4772_Y - connect \$23 $sshl$libresoc.v:125865$4773_Y - connect \$4 $sshl$libresoc.v:125866$4774_Y - connect \$3 $pos$libresoc.v:125867$4776_Y + connect \$9 $pos$libresoc.v:126197$4950_Y + connect \$11 $pos$libresoc.v:126198$4952_Y + connect \$14 $sshl$libresoc.v:126199$4953_Y + connect \$17 $sshl$libresoc.v:126200$4954_Y + connect \$1 $pos$libresoc.v:126201$4956_Y + connect \$20 $sshl$libresoc.v:126202$4957_Y + connect \$23 $sshl$libresoc.v:126203$4958_Y + connect \$4 $sshl$libresoc.v:126204$4959_Y + connect \$3 $pos$libresoc.v:126205$4961_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:126037.1-126085.10" +attribute \src "libresoc.v:126375.1-126423.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" attribute \generator "nMigen" module \dec_c - attribute \src "libresoc.v:126038.7-126038.20" + attribute \src "libresoc.v:126376.7-126376.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126055.3-126069.6" + attribute \src "libresoc.v:126393.3-126407.6" wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:126070.3-126084.6" + attribute \src "libresoc.v:126408.3-126422.6" wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:126055.3-126069.6" + attribute \src "libresoc.v:126393.3-126407.6" wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:126070.3-126084.6" + attribute \src "libresoc.v:126408.3-126422.6" wire $1\reg_c_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 4 \RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" wire width 5 input 3 \RS - attribute \src "libresoc.v:126038.7-126038.15" + attribute \src "libresoc.v:126376.7-126376.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 1 \reg_c @@ -196636,28 +199439,28 @@ module \dec_c attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:428" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:294" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:126038.7-126038.20" - process $proc$libresoc.v:126038$4788 + attribute \src "libresoc.v:126376.7-126376.20" + process $proc$libresoc.v:126376$4973 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126055.3-126069.6" - process $proc$libresoc.v:126055$4786 + attribute \src "libresoc.v:126393.3-126407.6" + process $proc$libresoc.v:126393$4971 assign { } { } assign { } { } assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:126056.5-126056.29" + attribute \src "libresoc.v:126394.5-126394.29" switch \initial - attribute \src "libresoc.v:126056.9-126056.17" + attribute \src "libresoc.v:126394.9-126394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:439" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -196673,18 +199476,18 @@ module \dec_c sync always update \reg_c $0\reg_c[4:0] end - attribute \src "libresoc.v:126070.3-126084.6" - process $proc$libresoc.v:126070$4787 + attribute \src "libresoc.v:126408.3-126422.6" + process $proc$libresoc.v:126408$4972 assign { } { } assign { } { } assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:126071.5-126071.29" + attribute \src "libresoc.v:126409.5-126409.29" switch \initial - attribute \src "libresoc.v:126071.9-126071.17" + attribute \src "libresoc.v:126409.9-126409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:439" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -196701,85 +199504,111 @@ module \dec_c update \reg_c_ok $0\reg_c_ok[0:0] end end -attribute \src "libresoc.v:126089.1-126387.10" +attribute \src "libresoc.v:126427.1-126759.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" module \dec_cr_in - attribute \src "libresoc.v:126292.3-126318.6" + attribute \src "libresoc.v:126679.3-126709.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:126319.3-126329.6" + attribute \src "libresoc.v:126710.3-126720.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126259.3-126269.6" + attribute \src "libresoc.v:126612.3-126622.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126330.3-126340.6" + attribute \src "libresoc.v:126721.3-126731.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126270.3-126280.6" + attribute \src "libresoc.v:126642.3-126652.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126232.3-126258.6" + attribute \src "libresoc.v:126581.3-126611.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126368.3-126386.6" + attribute \src "libresoc.v:126623.3-126641.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:126281.3-126291.6" + attribute \src "libresoc.v:126653.3-126663.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126090.7-126090.20" + attribute \src "libresoc.v:126428.7-126428.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126341.3-126351.6" + attribute \src "libresoc.v:126732.3-126742.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:126352.3-126367.6" + attribute \src "libresoc.v:126743.3-126758.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:126292.3-126318.6" + attribute \src "libresoc.v:126664.3-126678.6" + wire width 2 $0\sv_override[1:0] + attribute \src "libresoc.v:126679.3-126709.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:126319.3-126329.6" + attribute \src "libresoc.v:126710.3-126720.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126259.3-126269.6" + attribute \src "libresoc.v:126612.3-126622.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126330.3-126340.6" + attribute \src "libresoc.v:126721.3-126731.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126270.3-126280.6" + attribute \src "libresoc.v:126642.3-126652.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126232.3-126258.6" + attribute \src "libresoc.v:126581.3-126611.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126368.3-126386.6" + attribute \src "libresoc.v:126623.3-126641.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:126281.3-126291.6" + attribute \src "libresoc.v:126653.3-126663.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126341.3-126351.6" + attribute \src "libresoc.v:126732.3-126742.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:126352.3-126367.6" + attribute \src "libresoc.v:126743.3-126758.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:126368.3-126386.6" + attribute \src "libresoc.v:126664.3-126678.6" + wire width 2 $1\sv_override[1:0] + attribute \src "libresoc.v:126623.3-126641.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:126352.3-126367.6" + attribute \src "libresoc.v:126743.3-126758.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:126225.17-126225.112" - wire $and$libresoc.v:126225$4790_Y - attribute \src "libresoc.v:126227.17-126227.112" - wire $and$libresoc.v:126227$4792_Y - attribute \src "libresoc.v:126224.17-126224.121" - wire $eq$libresoc.v:126224$4789_Y - attribute \src "libresoc.v:126226.17-126226.121" - wire $eq$libresoc.v:126226$4791_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "libresoc.v:126574.17-126574.112" + wire $and$libresoc.v:126574$4975_Y + attribute \src "libresoc.v:126576.17-126576.112" + wire $and$libresoc.v:126576$4977_Y + attribute \src "libresoc.v:126573.17-126573.117" + wire $eq$libresoc.v:126573$4974_Y + attribute \src "libresoc.v:126575.17-126575.117" + wire $eq$libresoc.v:126575$4976_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 4 \ALU_BA + wire width 5 input 13 \BA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 3 \ALU_BB + wire width 5 input 12 \BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 8 \ALU_BC + wire width 5 input 17 \BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 7 \ALU_BI + wire width 5 input 16 \BI attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 5 \ALU_BT + wire width 5 input 14 \BT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 6 \ALU_FXM + wire width 8 input 15 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 18 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 5 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 8 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 9 \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 10 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 11 \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 3 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_fxm_ok + attribute \src "libresoc.v:126428.7-126428.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:517" + wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -196855,30 +199684,8 @@ module \dec_cr_in attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 2 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:126090.7-126090.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire width 7 input 19 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:568" wire \move_one attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \ppick_i @@ -196893,10 +199700,12 @@ module \dec_cr_in attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:126225$4790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:516" + wire width 3 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" + wire width 2 output 6 \sv_override + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + cell $and $and$libresoc.v:126574$4975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196904,10 +199713,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:126225$4790_Y + connect \Y $and$libresoc.v:126574$4975_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:126227$4792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + cell $and $and$libresoc.v:126576$4977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196915,62 +199724,66 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:126227$4792_Y + connect \Y $and$libresoc.v:126576$4977_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:126224$4789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + cell $eq $eq$libresoc.v:126573$4974 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \ALU_internal_op + connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:126224$4789_Y + connect \Y $eq$libresoc.v:126573$4974_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:126226$4791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + cell $eq $eq$libresoc.v:126575$4976 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \ALU_internal_op + connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:126226$4791_Y + connect \Y $eq$libresoc.v:126575$4976_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:126228.9-126231.4" + attribute \src "libresoc.v:126577.9-126580.4" cell \ppick \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:126090.7-126090.20" - process $proc$libresoc.v:126090$4803 + attribute \src "libresoc.v:126428.7-126428.20" + process $proc$libresoc.v:126428$4989 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126232.3-126258.6" - process $proc$libresoc.v:126232$4793 + attribute \src "libresoc.v:126581.3-126611.6" + process $proc$libresoc.v:126581$4978 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126233.5-126233.29" + attribute \src "libresoc.v:126582.5-126582.29" switch \initial - attribute \src "libresoc.v:126233.9-126233.17" + attribute \src "libresoc.v:126582.9-126582.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 @@ -196992,18 +199805,18 @@ module \dec_cr_in sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:126259.3-126269.6" - process $proc$libresoc.v:126259$4794 + attribute \src "libresoc.v:126612.3-126622.6" + process $proc$libresoc.v:126612$4979 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126260.5-126260.29" + attribute \src "libresoc.v:126613.5-126613.29" switch \initial - attribute \src "libresoc.v:126260.9-126260.17" + attribute \src "libresoc.v:126613.9-126613.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 @@ -197015,210 +199828,24 @@ module \dec_cr_in sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:126270.3-126280.6" - process $proc$libresoc.v:126270$4795 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126271.5-126271.29" - switch \initial - attribute \src "libresoc.v:126271.9-126271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:126281.3-126291.6" - process $proc$libresoc.v:126281$4796 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126282.5-126282.29" - switch \initial - attribute \src "libresoc.v:126282.9-126282.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:126292.3-126318.6" - process $proc$libresoc.v:126292$4797 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:126293.5-126293.29" - switch \initial - attribute \src "libresoc.v:126293.9-126293.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:126319.3-126329.6" - process $proc$libresoc.v:126319$4798 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126320.5-126320.29" - switch \initial - attribute \src "libresoc.v:126320.9-126320.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \ALU_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:126330.3-126340.6" - process $proc$libresoc.v:126330$4799 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126331.5-126331.29" - switch \initial - attribute \src "libresoc.v:126331.9-126331.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \ALU_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:126341.3-126351.6" - process $proc$libresoc.v:126341$4800 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:126342.5-126342.29" - switch \initial - attribute \src "libresoc.v:126342.9-126342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:126352.3-126367.6" - process $proc$libresoc.v:126352$4801 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:126353.5-126353.29" - switch \initial - attribute \src "libresoc.v:126353.9-126353.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \ALU_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:126368.3-126386.6" - process $proc$libresoc.v:126368$4802 + attribute \src "libresoc.v:126623.3-126641.6" + process $proc$libresoc.v:126623$4980 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:126369.5-126369.29" + attribute \src "libresoc.v:126624.5-126624.29" switch \initial - attribute \src "libresoc.v:126369.9-126369.17" + attribute \src "libresoc.v:126624.9-126624.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -197235,392 +199862,104 @@ module \dec_cr_in sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:126224$4789_Y - connect \$3 $and$libresoc.v:126225$4790_Y - connect \$5 $eq$libresoc.v:126226$4791_Y - connect \$7 $and$libresoc.v:126227$4792_Y -end -attribute \src "libresoc.v:126391.1-126689.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$142 - attribute \src "libresoc.v:126594.3-126620.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:126621.3-126631.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126561.3-126571.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126632.3-126642.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126572.3-126582.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126534.3-126560.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126670.3-126688.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:126583.3-126593.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126392.7-126392.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:126643.3-126653.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:126654.3-126669.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:126594.3-126620.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:126621.3-126631.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126561.3-126571.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126632.3-126642.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126572.3-126582.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126534.3-126560.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126670.3-126688.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:126583.3-126593.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126643.3-126653.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:126654.3-126669.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:126670.3-126688.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:126654.3-126669.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:126527.17-126527.112" - wire $and$libresoc.v:126527$4805_Y - attribute \src "libresoc.v:126529.17-126529.112" - wire $and$libresoc.v:126529$4807_Y - attribute \src "libresoc.v:126526.17-126526.120" - wire $eq$libresoc.v:126526$4804_Y - attribute \src "libresoc.v:126528.17-126528.120" - wire $eq$libresoc.v:126528$4806_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 4 \CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 3 \CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 8 \CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 7 \CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 5 \CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 6 \CR_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 2 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:126392.7-126392.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:126527$4805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:126527$4805_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:126529$4807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:126529$4807_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:126526$4804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:126526$4804_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:126528$4806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:126528$4806_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:126530.15-126533.4" - cell \ppick$143 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:126392.7-126392.20" - process $proc$libresoc.v:126392$4818 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:126534.3-126560.6" - process $proc$libresoc.v:126534$4808 + attribute \src "libresoc.v:126642.3-126652.6" + process $proc$libresoc.v:126642$4981 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126535.5-126535.29" + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126643.5-126643.29" switch \initial - attribute \src "libresoc.v:126535.9-126535.17" + attribute \src "libresoc.v:126643.9-126643.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\cr_bitfield_o_ok[0:0] 1'1 case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\cr_bitfield_o_ok[0:0] 1'0 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:126561.3-126571.6" - process $proc$libresoc.v:126561$4809 + attribute \src "libresoc.v:126653.3-126663.6" + process $proc$libresoc.v:126653$4982 assign { } { } assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126562.5-126562.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126654.5-126654.29" switch \initial - attribute \src "libresoc.v:126562.9-126562.17" + attribute \src "libresoc.v:126654.9-126654.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'110 assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\cr_bitfield_b_ok[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:126572.3-126582.6" - process $proc$libresoc.v:126572$4810 + attribute \src "libresoc.v:126664.3-126678.6" + process $proc$libresoc.v:126664$4983 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126573.5-126573.29" + assign $0\sv_override[1:0] $1\sv_override[1:0] + attribute \src "libresoc.v:126665.5-126665.29" switch \initial - attribute \src "libresoc.v:126573.9-126573.17" + attribute \src "libresoc.v:126665.9-126665.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'001 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:126583.3-126593.6" - process $proc$libresoc.v:126583$4811 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126584.5-126584.29" - switch \initial - attribute \src "libresoc.v:126584.9-126584.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + assign $1\sv_override[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'111 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\sv_override[1:0] 2'10 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\sv_override[1:0] 2'00 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:126594.3-126620.6" - process $proc$libresoc.v:126594$4812 + attribute \src "libresoc.v:126679.3-126709.6" + process $proc$libresoc.v:126679$4984 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:126595.5-126595.29" + attribute \src "libresoc.v:126680.5-126680.29" switch \initial - attribute \src "libresoc.v:126595.9-126595.17" + attribute \src "libresoc.v:126680.9-126680.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign { } { } + assign $1\cr_bitfield[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\cr_bitfield[2:0] \CR_BI [4:2] + assign $1\cr_bitfield[2:0] \BI [4:2] attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } @@ -197628,75 +199967,75 @@ module \dec_cr_in$142 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\cr_bitfield[2:0] \CR_BA [4:2] + assign $1\cr_bitfield[2:0] \BA [4:2] attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } - assign $1\cr_bitfield[2:0] \CR_BC [4:2] + assign $1\cr_bitfield[2:0] \BC [4:2] case assign $1\cr_bitfield[2:0] 3'000 end sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:126621.3-126631.6" - process $proc$libresoc.v:126621$4813 + attribute \src "libresoc.v:126710.3-126720.6" + process $proc$libresoc.v:126710$4985 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126622.5-126622.29" + attribute \src "libresoc.v:126711.5-126711.29" switch \initial - attribute \src "libresoc.v:126622.9-126622.17" + attribute \src "libresoc.v:126711.9-126711.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\cr_bitfield_b[2:0] \CR_BB [4:2] + assign $1\cr_bitfield_b[2:0] \BB [4:2] case assign $1\cr_bitfield_b[2:0] 3'000 end sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:126632.3-126642.6" - process $proc$libresoc.v:126632$4814 + attribute \src "libresoc.v:126721.3-126731.6" + process $proc$libresoc.v:126721$4986 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126633.5-126633.29" + attribute \src "libresoc.v:126722.5-126722.29" switch \initial - attribute \src "libresoc.v:126633.9-126633.17" + attribute \src "libresoc.v:126722.9-126722.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\cr_bitfield_o[2:0] \CR_BT [4:2] + assign $1\cr_bitfield_o[2:0] \BT [4:2] case assign $1\cr_bitfield_o[2:0] 3'000 end sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:126643.3-126653.6" - process $proc$libresoc.v:126643$4815 + attribute \src "libresoc.v:126732.3-126742.6" + process $proc$libresoc.v:126732$4987 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:126644.5-126644.29" + attribute \src "libresoc.v:126733.5-126733.29" switch \initial - attribute \src "libresoc.v:126644.9-126644.17" + attribute \src "libresoc.v:126733.9-126733.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -197708,29 +200047,29 @@ module \dec_cr_in$142 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:126654.3-126669.6" - process $proc$libresoc.v:126654$4816 + attribute \src "libresoc.v:126743.3-126758.6" + process $proc$libresoc.v:126743$4988 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:126655.5-126655.29" + attribute \src "libresoc.v:126744.5-126744.29" switch \initial - attribute \src "libresoc.v:126655.9-126655.17" + attribute \src "libresoc.v:126744.9-126744.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ppick_i[7:0] \CR_FXM + assign $2\ppick_i[7:0] \FXM case assign $2\ppick_i[7:0] 8'00000000 end @@ -197740,124 +200079,82 @@ module \dec_cr_in$142 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:126670.3-126688.6" - process $proc$libresoc.v:126670$4817 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:126671.5-126671.29" - switch \initial - attribute \src "libresoc.v:126671.9-126671.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:126526$4804_Y - connect \$3 $and$libresoc.v:126527$4805_Y - connect \$5 $eq$libresoc.v:126528$4806_Y - connect \$7 $and$libresoc.v:126529$4807_Y + connect \$1 $eq$libresoc.v:126573$4974_Y + connect \$3 $and$libresoc.v:126574$4975_Y + connect \$5 $eq$libresoc.v:126575$4976_Y + connect \$7 $and$libresoc.v:126576$4977_Y end -attribute \src "libresoc.v:126693.1-126991.10" +attribute \src "libresoc.v:126763.1-127033.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" attribute \generator "nMigen" -module \dec_cr_in$149 - attribute \src "libresoc.v:126896.3-126922.6" +module \dec_cr_out + attribute \src "libresoc.v:126943.3-126965.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:126923.3-126933.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126863.3-126873.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126934.3-126944.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126874.3-126884.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126836.3-126862.6" + attribute \src "libresoc.v:126894.3-126916.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126972.3-126990.6" + attribute \src "libresoc.v:126998.3-127032.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:126885.3-126895.6" + attribute \src "libresoc.v:126917.3-126927.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126694.7-126694.20" + attribute \src "libresoc.v:126764.7-126764.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126945.3-126955.6" + attribute \src "libresoc.v:126966.3-126976.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:126956.3-126971.6" + attribute \src "libresoc.v:126977.3-126997.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:126896.3-126922.6" + attribute \src "libresoc.v:126928.3-126942.6" + wire width 2 $0\sv_override[1:0] + attribute \src "libresoc.v:126943.3-126965.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:126923.3-126933.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126863.3-126873.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126934.3-126944.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126874.3-126884.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126836.3-126862.6" + attribute \src "libresoc.v:126894.3-126916.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126972.3-126990.6" + attribute \src "libresoc.v:126998.3-127032.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:126885.3-126895.6" + attribute \src "libresoc.v:126917.3-126927.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126945.3-126955.6" + attribute \src "libresoc.v:126966.3-126976.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:126956.3-126971.6" + attribute \src "libresoc.v:126977.3-126997.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:126972.3-126990.6" + attribute \src "libresoc.v:126928.3-126942.6" + wire width 2 $1\sv_override[1:0] + attribute \src "libresoc.v:126998.3-127032.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:126956.3-126971.6" + attribute \src "libresoc.v:126977.3-126997.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:126829.17-126829.112" - wire $and$libresoc.v:126829$4820_Y - attribute \src "libresoc.v:126831.17-126831.112" - wire $and$libresoc.v:126831$4822_Y - attribute \src "libresoc.v:126828.17-126828.124" - wire $eq$libresoc.v:126828$4819_Y - attribute \src "libresoc.v:126830.17-126830.124" - wire $eq$libresoc.v:126830$4821_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "libresoc.v:126998.3-127032.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:126977.3-126997.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:126998.3-127032.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:126887.17-126887.117" + wire $eq$libresoc.v:126887$4990_Y + attribute \src "libresoc.v:126888.17-126888.117" + wire $eq$libresoc.v:126888$4991_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 4 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 3 \BRANCH_BB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 8 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 7 \BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 5 \BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 6 \BRANCH_FXM + wire width 8 input 9 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 11 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 10 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 8 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \cr_fxm_ok + attribute \src "libresoc.v:126764.7-126764.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:592" + wire width 32 input 1 \insn_in attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -197933,135 +200230,92 @@ module \dec_cr_in$149 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 2 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:126694.7-126694.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire width 7 input 12 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" wire width 8 \ppick_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590" + wire input 3 \rc_in + attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:126829$4820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:126829$4820_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:126831$4822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:126831$4822_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:126828$4819 + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:591" + wire width 3 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:595" + wire width 2 output 7 \sv_override + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" + cell $eq $eq$libresoc.v:126887$4990 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:126828$4819_Y + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:126887$4990_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:126830$4821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" + cell $eq $eq$libresoc.v:126888$4991 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:126830$4821_Y + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:126888$4991_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:126832.15-126835.4" - cell \ppick$150 \ppick + attribute \src "libresoc.v:126889.15-126893.4" + cell \ppick$175 \ppick + connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:126694.7-126694.20" - process $proc$libresoc.v:126694$4833 + attribute \src "libresoc.v:126764.7-126764.20" + process $proc$libresoc.v:126764$4999 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126836.3-126862.6" - process $proc$libresoc.v:126836$4823 + attribute \src "libresoc.v:126894.3-126916.6" + process $proc$libresoc.v:126894$4992 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:126837.5-126837.29" + attribute \src "libresoc.v:126895.5-126895.29" switch \initial - attribute \src "libresoc.v:126837.9-126837.17" + attribute \src "libresoc.v:126895.9-126895.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\cr_bitfield_ok[0:0] \rc_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'010 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'011 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 case @@ -198070,175 +200324,106 @@ module \dec_cr_in$149 sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:126863.3-126873.6" - process $proc$libresoc.v:126863$4824 + attribute \src "libresoc.v:126917.3-126927.6" + process $proc$libresoc.v:126917$4993 assign { } { } assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:126864.5-126864.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126918.5-126918.29" switch \initial - attribute \src "libresoc.v:126864.9-126864.17" + attribute \src "libresoc.v:126918.9-126918.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\cr_bitfield_b_ok[0:0] 1'0 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:126874.3-126884.6" - process $proc$libresoc.v:126874$4825 + attribute \src "libresoc.v:126928.3-126942.6" + process $proc$libresoc.v:126928$4994 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:126875.5-126875.29" + assign $0\sv_override[1:0] $1\sv_override[1:0] + attribute \src "libresoc.v:126929.5-126929.29" switch \initial - attribute \src "libresoc.v:126875.9-126875.17" + attribute \src "libresoc.v:126929.9-126929.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'001 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:126885.3-126895.6" - process $proc$libresoc.v:126885$4826 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126886.5-126886.29" - switch \initial - attribute \src "libresoc.v:126886.9-126886.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + assign $1\sv_override[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'101 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\sv_override[1:0] 2'10 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\sv_override[1:0] 2'00 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:126896.3-126922.6" - process $proc$libresoc.v:126896$4827 + attribute \src "libresoc.v:126943.3-126965.6" + process $proc$libresoc.v:126943$4995 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:126897.5-126897.29" + attribute \src "libresoc.v:126944.5-126944.29" switch \initial - attribute \src "libresoc.v:126897.9-126897.17" + attribute \src "libresoc.v:126944.9-126944.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" switch \sel_in attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 3'101 assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA + assign $1\cr_bitfield[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 3'010 assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BA [4:2] + assign $1\cr_bitfield[2:0] \X_BF attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 3'011 assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BC [4:2] + assign $1\cr_bitfield[2:0] \XL_BT [4:2] case assign $1\cr_bitfield[2:0] 3'000 end sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:126923.3-126933.6" - process $proc$libresoc.v:126923$4828 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:126924.5-126924.29" - switch \initial - attribute \src "libresoc.v:126924.9-126924.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \BRANCH_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:126934.3-126944.6" - process $proc$libresoc.v:126934$4829 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:126935.5-126935.29" - switch \initial - attribute \src "libresoc.v:126935.9-126935.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \BRANCH_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:126945.3-126955.6" - process $proc$libresoc.v:126945$4830 + attribute \src "libresoc.v:126966.3-126976.6" + process $proc$libresoc.v:126966$4996 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:126946.5-126946.29" + attribute \src "libresoc.v:126967.5-126967.29" switch \initial - attribute \src "libresoc.v:126946.9-126946.17" + attribute \src "libresoc.v:126967.9-126967.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'100 assign { } { } assign $1\move_one[0:0] \insn_in [20] case @@ -198247,29 +200432,38 @@ module \dec_cr_in$149 sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:126956.3-126971.6" - process $proc$libresoc.v:126956$4831 + attribute \src "libresoc.v:126977.3-126997.6" + process $proc$libresoc.v:126977$4997 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:126957.5-126957.29" + attribute \src "libresoc.v:126978.5-126978.29" switch \initial - attribute \src "libresoc.v:126957.9-126957.17" + attribute \src "libresoc.v:126978.9-126978.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" + switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ppick_i[7:0] \BRANCH_FXM + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:636" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end case assign $2\ppick_i[7:0] 8'00000000 end @@ -198279,29 +200473,51 @@ module \dec_cr_in$149 sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:126972.3-126990.6" - process $proc$libresoc.v:126972$4832 + attribute \src "libresoc.v:126998.3-127032.6" + process $proc$libresoc.v:126998$4998 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:126973.5-126973.29" + attribute \src "libresoc.v:126999.5-126999.29" switch \initial - attribute \src "libresoc.v:126973.9-126973.17" + attribute \src "libresoc.v:126999.9-126999.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:614" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:635" + switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_fxm[7:0] \ppick_o + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:636" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:639" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \FXM + end attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -198313,90 +200529,96 @@ module \dec_cr_in$149 sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:126828$4819_Y - connect \$3 $and$libresoc.v:126829$4820_Y - connect \$5 $eq$libresoc.v:126830$4821_Y - connect \$7 $and$libresoc.v:126831$4822_Y + connect \$1 $eq$libresoc.v:126887$4990_Y + connect \$3 $eq$libresoc.v:126888$4991_Y end -attribute \src "libresoc.v:126995.1-127293.10" +attribute \src "libresoc.v:127037.1-127520.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" attribute \generator "nMigen" -module \dec_cr_in$157 - attribute \src "libresoc.v:127198.3-127224.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:127225.3-127235.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127165.3-127175.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127236.3-127246.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127176.3-127186.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:127138.3-127164.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127274.3-127292.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:127187.3-127197.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:126996.7-126996.20" +module \dec_o + attribute \src "libresoc.v:127481.3-127519.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:127481.3-127519.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:127038.7-127038.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127247.3-127257.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:127258.3-127273.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:127198.3-127224.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127225.3-127235.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127165.3-127175.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127236.3-127246.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127176.3-127186.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:127138.3-127164.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127274.3-127292.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:127187.3-127197.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127247.3-127257.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:127258.3-127273.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:127274.3-127292.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:127258.3-127273.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:127131.17-127131.112" - wire $and$libresoc.v:127131$4835_Y - attribute \src "libresoc.v:127133.17-127133.112" - wire $and$libresoc.v:127133$4837_Y - attribute \src "libresoc.v:127130.17-127130.125" - wire $eq$libresoc.v:127130$4834_Y - attribute \src "libresoc.v:127132.17-127132.125" - wire $eq$libresoc.v:127132$4836_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "libresoc.v:127407.3-127421.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:127422.3-127436.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:127437.3-127447.6" + wire width 10 $0\spr[9:0] + attribute \src "libresoc.v:127464.3-127480.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:127464.3-127480.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:127448.3-127463.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "libresoc.v:127481.3-127519.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:127481.3-127519.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:127407.3-127421.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:127422.3-127436.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:127437.3-127447.6" + wire width 10 $1\spr[9:0] + attribute \src "libresoc.v:127464.3-127480.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:127464.3-127480.6" + wire $1\spr_o_ok[0:0] + attribute \src "libresoc.v:127448.3-127463.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:127481.3-127519.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:127481.3-127519.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:127464.3-127480.6" + wire width 10 $2\spr_o[9:0] + attribute \src "libresoc.v:127464.3-127480.6" + wire $2\spr_o_ok[0:0] + attribute \src "libresoc.v:127448.3-127463.6" + wire width 10 $2\sprmap_spr_i[9:0] + attribute \src "libresoc.v:127481.3-127519.6" + wire width 3 $3\fast_o[2:0] + attribute \src "libresoc.v:127481.3-127519.6" + wire $3\fast_o_ok[0:0] + attribute \src "libresoc.v:127481.3-127519.6" + wire width 3 $4\fast_o[2:0] + attribute \src "libresoc.v:127481.3-127519.6" + wire $4\fast_o_ok[0:0] + attribute \src "libresoc.v:127396.17-127396.117" + wire $eq$libresoc.v:127396$5000_Y + attribute \src "libresoc.v:127397.17-127397.117" + wire $eq$libresoc.v:127397$5001_Y + attribute \src "libresoc.v:127398.17-127398.117" + wire $eq$libresoc.v:127398$5002_Y + attribute \src "libresoc.v:127399.17-127399.104" + wire $not$libresoc.v:127399$5003_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360" wire \$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 4 \LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 3 \LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 8 \LOGICAL_BC + wire width 5 input 11 \BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 7 \LOGICAL_BI + wire width 5 input 10 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 5 \LOGICAL_BT + wire width 5 input 9 \RT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 6 \LOGICAL_FXM + wire width 10 input 1 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 7 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 8 \fast_o_ok + attribute \src "libresoc.v:127038.7-127038.15" + wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -198472,470 +200694,591 @@ module \dec_cr_in$157 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 2 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 9 \X_BFA + wire width 7 input 12 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield + wire width 5 output 3 \reg_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b + wire output 4 \reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" + wire width 2 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok + wire width 10 output 5 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o + wire output 6 \spr_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok + wire width 3 \sprmap_fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire width 10 \sprmap_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:126996.7-126996.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:127131$4835 + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + cell $eq $eq$libresoc.v:127396$5000 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:127131$4835_Y + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:127396$5000_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:127133$4837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + cell $eq $eq$libresoc.v:127397$5001 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:127133$4837_Y + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:127397$5001_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:127130$4834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + cell $eq $eq$libresoc.v:127398$5002 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:127130$4834_Y + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:127398$5002_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:127132$4836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360" + cell $not $not$libresoc.v:127399$5003 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:127132$4836_Y + connect \A \BO [2] + connect \Y $not$libresoc.v:127399$5003_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:127134.15-127137.4" - cell \ppick$158 \ppick - connect \i \ppick_i - connect \o \ppick_o + attribute \src "libresoc.v:127400.16-127406.4" + cell \sprmap$174 \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:126996.7-126996.20" - process $proc$libresoc.v:126996$4848 + attribute \src "libresoc.v:127038.7-127038.20" + process $proc$libresoc.v:127038$5010 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127138.3-127164.6" - process $proc$libresoc.v:127138$4838 + attribute \src "libresoc.v:127407.3-127421.6" + process $proc$libresoc.v:127407$5004 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127139.5-127139.29" + assign $0\reg_o[4:0] $1\reg_o[4:0] + attribute \src "libresoc.v:127408.5-127408.29" switch \initial - attribute \src "libresoc.v:127139.9-127139.17" + attribute \src "libresoc.v:127408.9-127408.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 2'01 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:127165.3-127175.6" - process $proc$libresoc.v:127165$4839 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127166.5-127166.29" - switch \initial - attribute \src "libresoc.v:127166.9-127166.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + assign $1\reg_o[4:0] \RT attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 + assign $1\reg_o[4:0] \RA case - assign $1\cr_bitfield_b_ok[0:0] 1'0 + assign $1\reg_o[4:0] 5'00000 end sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:127176.3-127186.6" - process $proc$libresoc.v:127176$4840 + attribute \src "libresoc.v:127422.3-127436.6" + process $proc$libresoc.v:127422$5005 assign { } { } assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:127177.5-127177.29" + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:127423.5-127423.29" switch \initial - attribute \src "libresoc.v:127177.9-127177.17" + attribute \src "libresoc.v:127423.9-127423.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'01 assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:127187.3-127197.6" - process $proc$libresoc.v:127187$4841 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127188.5-127188.29" - switch \initial - attribute \src "libresoc.v:127188.9-127188.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + assign $1\reg_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'10 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\reg_o_ok[0:0] 1'1 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\reg_o_ok[0:0] 1'0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:127198.3-127224.6" - process $proc$libresoc.v:127198$4842 + attribute \src "libresoc.v:127437.3-127447.6" + process $proc$libresoc.v:127437$5006 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127199.5-127199.29" + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:127438.5-127438.29" switch \initial - attribute \src "libresoc.v:127199.9-127199.17" + attribute \src "libresoc.v:127438.9-127438.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 + case 2'11 assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BC [4:2] + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\spr[9:0] 10'0000000000 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \spr $0\spr[9:0] end - attribute \src "libresoc.v:127225.3-127235.6" - process $proc$libresoc.v:127225$4843 + attribute \src "libresoc.v:127448.3-127463.6" + process $proc$libresoc.v:127448$5007 assign { } { } assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127226.5-127226.29" + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:127449.5-127449.29" switch \initial - attribute \src "libresoc.v:127226.9-127226.17" + attribute \src "libresoc.v:127449.9-127449.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'11 assign { } { } - assign $1\cr_bitfield_b[2:0] \LOGICAL_BB [4:2] + assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sprmap_spr_i[9:0] \spr + case + assign $2\sprmap_spr_i[9:0] 10'0000000000 + end case - assign $1\cr_bitfield_b[2:0] 3'000 + assign $1\sprmap_spr_i[9:0] 10'0000000000 end sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] + update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:127236.3-127246.6" - process $proc$libresoc.v:127236$4844 + attribute \src "libresoc.v:127464.3-127480.6" + process $proc$libresoc.v:127464$5008 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127237.5-127237.29" - switch \initial - attribute \src "libresoc.v:127237.9-127237.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \LOGICAL_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:127247.3-127257.6" - process $proc$libresoc.v:127247$4845 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:127248.5-127248.29" + assign $0\spr_o[9:0] $1\spr_o[9:0] + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:127465.5-127465.29" switch \initial - attribute \src "libresoc.v:127248.9-127248.17" + attribute \src "libresoc.v:127465.9-127465.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'11 assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:127258.3-127273.6" - process $proc$libresoc.v:127258$4846 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:127259.5-127259.29" - switch \initial - attribute \src "libresoc.v:127259.9-127259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + assign $1\spr_o[9:0] $2\spr_o[9:0] + assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ppick_i[7:0] \LOGICAL_FXM + assign { } { } + assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\spr_o[9:0] 10'0000000000 + assign $2\spr_o_ok[0:0] 1'0 end case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 end sync always - update \ppick_i $0\ppick_i[7:0] + update \spr_o $0\spr_o[9:0] + update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:127274.3-127292.6" - process $proc$libresoc.v:127274$4847 + attribute \src "libresoc.v:127481.3-127519.6" + process $proc$libresoc.v:127481$5009 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:127275.5-127275.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $3\fast_o[2:0] + assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] + attribute \src "libresoc.v:127482.5-127482.29" switch \initial - attribute \src "libresoc.v:127275.9-127275.17" + attribute \src "libresoc.v:127482.9-127482.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 2'11 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$7 + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $2\fast_o[2:0] 3'000 + assign $2\fast_o_ok[0:0] 1'0 end case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:356" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0001000 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] $4\fast_o[2:0] + assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:360" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $4\fast_o[2:0] 3'000 + assign $4\fast_o_ok[0:0] 1'1 + case + assign $4\fast_o[2:0] $1\fast_o[2:0] + assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] 3'011 + assign $3\fast_o_ok[0:0] 1'1 + case + assign $3\fast_o[2:0] $1\fast_o[2:0] + assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \fast_o $0\fast_o[2:0] + update \fast_o_ok $0\fast_o_ok[0:0] end - connect \$1 $eq$libresoc.v:127130$4834_Y - connect \$3 $and$libresoc.v:127131$4835_Y - connect \$5 $eq$libresoc.v:127132$4836_Y - connect \$7 $and$libresoc.v:127133$4837_Y + connect \$1 $eq$libresoc.v:127396$5000_Y + connect \$3 $eq$libresoc.v:127397$5001_Y + connect \$5 $eq$libresoc.v:127398$5002_Y + connect \$7 $not$libresoc.v:127399$5003_Y end -attribute \src "libresoc.v:127297.1-127595.10" +attribute \src "libresoc.v:127524.1-127691.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" attribute \generator "nMigen" -module \dec_cr_in$166 - attribute \src "libresoc.v:127500.3-127526.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:127527.3-127537.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127467.3-127477.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127538.3-127548.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127478.3-127488.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:127440.3-127466.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127576.3-127594.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:127489.3-127499.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127298.7-127298.20" +module \dec_o2 + attribute \src "libresoc.v:127651.3-127670.6" + wire width 3 $0\fast_o2[2:0] + attribute \src "libresoc.v:127671.3-127690.6" + wire $0\fast_o2_ok[0:0] + attribute \src "libresoc.v:127525.7-127525.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127549.3-127559.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:127560.3-127575.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:127500.3-127526.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127527.3-127537.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127467.3-127477.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127538.3-127548.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127478.3-127488.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:127440.3-127466.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127576.3-127594.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:127489.3-127499.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127549.3-127559.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:127560.3-127575.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:127576.3-127594.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:127560.3-127575.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:127433.17-127433.112" - wire $and$libresoc.v:127433$4850_Y - attribute \src "libresoc.v:127435.17-127435.112" - wire $and$libresoc.v:127435$4852_Y - attribute \src "libresoc.v:127432.17-127432.121" - wire $eq$libresoc.v:127432$4849_Y - attribute \src "libresoc.v:127434.17-127434.121" - wire $eq$libresoc.v:127434$4851_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "libresoc.v:127631.3-127640.6" + wire width 5 $0\reg_o2[4:0] + attribute \src "libresoc.v:127641.3-127650.6" + wire $0\reg_o2_ok[0:0] + attribute \src "libresoc.v:127651.3-127670.6" + wire width 3 $1\fast_o2[2:0] + attribute \src "libresoc.v:127671.3-127690.6" + wire $1\fast_o2_ok[0:0] + attribute \src "libresoc.v:127631.3-127640.6" + wire width 5 $1\reg_o2[4:0] + attribute \src "libresoc.v:127641.3-127650.6" + wire $1\reg_o2_ok[0:0] + attribute \src "libresoc.v:127651.3-127670.6" + wire width 3 $2\fast_o2[2:0] + attribute \src "libresoc.v:127671.3-127690.6" + wire $2\fast_o2_ok[0:0] + attribute \src "libresoc.v:127629.17-127629.108" + wire $eq$libresoc.v:127629$5011_Y + attribute \src "libresoc.v:127630.17-127630.108" + wire $eq$libresoc.v:127630$5012_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 4 \SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 3 \SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 8 \SPR_BC attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 7 \SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 5 \SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 6 \SPR_FXM + wire width 5 input 7 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 4 \fast_o2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \fast_o2_ok + attribute \src "libresoc.v:127525.7-127525.15" + wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -199011,470 +201354,192 @@ module \dec_cr_in$166 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 2 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire width 7 input 8 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire input 1 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire width 5 output 2 \reg_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:127298.7-127298.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:127433$4850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:127433$4850_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:127435$4852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:127435$4852_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:127432$4849 + wire output 3 \reg_o2_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + cell $eq $eq$libresoc.v:127629$5011 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:127432$4849_Y + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:127629$5011_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:127434$4851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + cell $eq $eq$libresoc.v:127630$5012 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:127434$4851_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:127436.15-127439.4" - cell \ppick$167 \ppick - connect \i \ppick_i - connect \o \ppick_o + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:127630$5012_Y end - attribute \src "libresoc.v:127298.7-127298.20" - process $proc$libresoc.v:127298$4863 + attribute \src "libresoc.v:127525.7-127525.20" + process $proc$libresoc.v:127525$5017 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127440.3-127466.6" - process $proc$libresoc.v:127440$4853 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127441.5-127441.29" - switch \initial - attribute \src "libresoc.v:127441.9-127441.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:127467.3-127477.6" - process $proc$libresoc.v:127467$4854 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127468.5-127468.29" - switch \initial - attribute \src "libresoc.v:127468.9-127468.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:127478.3-127488.6" - process $proc$libresoc.v:127478$4855 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:127479.5-127479.29" - switch \initial - attribute \src "libresoc.v:127479.9-127479.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:127489.3-127499.6" - process $proc$libresoc.v:127489$4856 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127490.5-127490.29" - switch \initial - attribute \src "libresoc.v:127490.9-127490.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:127500.3-127526.6" - process $proc$libresoc.v:127500$4857 + attribute \src "libresoc.v:127631.3-127640.6" + process $proc$libresoc.v:127631$5013 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127501.5-127501.29" + assign $0\reg_o2[4:0] $1\reg_o2[4:0] + attribute \src "libresoc.v:127632.5-127632.29" switch \initial - attribute \src "libresoc.v:127501.9-127501.17" + attribute \src "libresoc.v:127632.9-127632.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + switch \$1 attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:127527.3-127537.6" - process $proc$libresoc.v:127527$4858 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127528.5-127528.29" - switch \initial - attribute \src "libresoc.v:127528.9-127528.17" case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 assign { } { } - assign $1\cr_bitfield_b[2:0] \SPR_BB [4:2] + assign $1\reg_o2[4:0] \RA case - assign $1\cr_bitfield_b[2:0] 3'000 + assign $1\reg_o2[4:0] 5'00000 end sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] + update \reg_o2 $0\reg_o2[4:0] end - attribute \src "libresoc.v:127538.3-127548.6" - process $proc$libresoc.v:127538$4859 + attribute \src "libresoc.v:127641.3-127650.6" + process $proc$libresoc.v:127641$5014 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127539.5-127539.29" + assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] + attribute \src "libresoc.v:127642.5-127642.29" switch \initial - attribute \src "libresoc.v:127539.9-127539.17" + attribute \src "libresoc.v:127642.9-127642.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:406" + switch \$3 attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \SPR_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:127549.3-127559.6" - process $proc$libresoc.v:127549$4860 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:127550.5-127550.29" - switch \initial - attribute \src "libresoc.v:127550.9-127550.17" case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\reg_o2_ok[0:0] 1'1 case - assign $1\move_one[0:0] 1'0 + assign $1\reg_o2_ok[0:0] 1'0 end sync always - update \move_one $0\move_one[0:0] + update \reg_o2_ok $0\reg_o2_ok[0:0] end - attribute \src "libresoc.v:127560.3-127575.6" - process $proc$libresoc.v:127560$4861 + attribute \src "libresoc.v:127651.3-127670.6" + process $proc$libresoc.v:127651$5015 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:127561.5-127561.29" + assign $0\fast_o2[2:0] $1\fast_o2[2:0] + attribute \src "libresoc.v:127652.5-127652.29" switch \initial - attribute \src "libresoc.v:127561.9-127561.17" + attribute \src "libresoc.v:127652.9-127652.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:412" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$3 + assign $1\fast_o2[2:0] $2\fast_o2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ppick_i[7:0] \SPR_FXM + assign $2\fast_o2[2:0] 3'001 case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\fast_o2[2:0] 3'000 end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o2[2:0] 3'100 case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\fast_o2[2:0] 3'000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \fast_o2 $0\fast_o2[2:0] end - attribute \src "libresoc.v:127576.3-127594.6" - process $proc$libresoc.v:127576$4862 + attribute \src "libresoc.v:127671.3-127690.6" + process $proc$libresoc.v:127671$5016 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:127577.5-127577.29" + assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] + attribute \src "libresoc.v:127672.5-127672.29" switch \initial - attribute \src "libresoc.v:127577.9-127577.17" + attribute \src "libresoc.v:127672.9-127672.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:412" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 7'0000111 , 7'0000110 , 7'0001000 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$7 + assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + switch \lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" + assign $2\fast_o2_ok[0:0] 1'1 case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\fast_o2_ok[0:0] 1'0 end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o2_ok[0:0] 1'1 case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\fast_o2_ok[0:0] 1'0 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \fast_o2_ok $0\fast_o2_ok[0:0] end - connect \$1 $eq$libresoc.v:127432$4849_Y - connect \$3 $and$libresoc.v:127433$4850_Y - connect \$5 $eq$libresoc.v:127434$4851_Y - connect \$7 $and$libresoc.v:127435$4852_Y + connect \$1 $eq$libresoc.v:127629$5011_Y + connect \$3 $eq$libresoc.v:127630$5012_Y end -attribute \src "libresoc.v:127599.1-127897.10" +attribute \src "libresoc.v:127695.1-127829.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" attribute \generator "nMigen" -module \dec_cr_in$173 - attribute \src "libresoc.v:127802.3-127828.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:127829.3-127839.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127769.3-127779.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127840.3-127850.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127780.3-127790.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:127742.3-127768.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127878.3-127896.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:127791.3-127801.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127600.7-127600.20" +module \dec_oe + attribute \src "libresoc.v:127696.7-127696.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127851.3-127861.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:127862.3-127877.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:127802.3-127828.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127829.3-127839.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127769.3-127779.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127840.3-127850.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127780.3-127790.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:127742.3-127768.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127878.3-127896.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:127791.3-127801.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127851.3-127861.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:127862.3-127877.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:127878.3-127896.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:127862.3-127877.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:127735.17-127735.112" - wire $and$libresoc.v:127735$4865_Y - attribute \src "libresoc.v:127737.17-127737.112" - wire $and$libresoc.v:127737$4867_Y - attribute \src "libresoc.v:127734.17-127734.121" - wire $eq$libresoc.v:127734$4864_Y - attribute \src "libresoc.v:127736.17-127736.121" - wire $eq$libresoc.v:127736$4866_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 4 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 3 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 8 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 7 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 5 \DIV_BT + attribute \src "libresoc.v:127787.3-127807.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:127808.3-127828.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:127787.3-127807.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:127808.3-127828.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:127787.3-127807.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:127808.3-127828.6" + wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 6 \DIV_FXM + wire input 4 \ALU_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -199550,470 +201615,115 @@ module \dec_cr_in$173 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 2 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire width 7 input 1 \ALU_internal_op + attribute \src "libresoc.v:127696.7-127696.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:127600.7-127600.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:127735$4865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:127735$4865_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:127737$4867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:127737$4867_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:127734$4864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:127734$4864_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:127736$4866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:127736$4866_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:127738.15-127741.4" - cell \ppick$174 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:127600.7-127600.20" - process $proc$libresoc.v:127600$4878 + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:127696.7-127696.20" + process $proc$libresoc.v:127696$5020 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127742.3-127768.6" - process $proc$libresoc.v:127742$4868 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:127743.5-127743.29" - switch \initial - attribute \src "libresoc.v:127743.9-127743.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:127769.3-127779.6" - process $proc$libresoc.v:127769$4869 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:127770.5-127770.29" - switch \initial - attribute \src "libresoc.v:127770.9-127770.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:127780.3-127790.6" - process $proc$libresoc.v:127780$4870 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:127781.5-127781.29" - switch \initial - attribute \src "libresoc.v:127781.9-127781.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:127791.3-127801.6" - process $proc$libresoc.v:127791$4871 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127792.5-127792.29" - switch \initial - attribute \src "libresoc.v:127792.9-127792.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:127802.3-127828.6" - process $proc$libresoc.v:127802$4872 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:127803.5-127803.29" - switch \initial - attribute \src "libresoc.v:127803.9-127803.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \DIV_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \DIV_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \DIV_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:127829.3-127839.6" - process $proc$libresoc.v:127829$4873 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:127830.5-127830.29" - switch \initial - attribute \src "libresoc.v:127830.9-127830.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \DIV_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:127840.3-127850.6" - process $proc$libresoc.v:127840$4874 + attribute \src "libresoc.v:127787.3-127807.6" + process $proc$libresoc.v:127787$5018 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:127841.5-127841.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:127788.5-127788.29" switch \initial - attribute \src "libresoc.v:127841.9-127841.17" + attribute \src "libresoc.v:127788.9-127788.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \DIV_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:127851.3-127861.6" - process $proc$libresoc.v:127851$4875 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:127852.5-127852.29" - switch \initial - attribute \src "libresoc.v:127852.9-127852.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:127862.3-127877.6" - process $proc$libresoc.v:127862$4876 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:127863.5-127863.29" - switch \initial - attribute \src "libresoc.v:127863.9-127863.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$3 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\ppick_i[7:0] \DIV_FXM + assign $2\oe[0:0] \ALU_OE case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\oe[0:0] 1'0 end - case - assign $1\ppick_i[7:0] 8'00000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:127878.3-127896.6" - process $proc$libresoc.v:127878$4877 + attribute \src "libresoc.v:127808.3-127828.6" + process $proc$libresoc.v:127808$5019 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:127879.5-127879.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:127809.5-127809.29" switch \initial - attribute \src "libresoc.v:127879.9-127879.17" + attribute \src "libresoc.v:127809.9-127809.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \ALU_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$7 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" + assign $2\oe_ok[0:0] 1'1 case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\oe_ok[0:0] 1'0 end - case - assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \oe_ok $0\oe_ok[0:0] end - connect \$1 $eq$libresoc.v:127734$4864_Y - connect \$3 $and$libresoc.v:127735$4865_Y - connect \$5 $eq$libresoc.v:127736$4866_Y - connect \$7 $and$libresoc.v:127737$4867_Y end -attribute \src "libresoc.v:127901.1-128199.10" +attribute \src "libresoc.v:127833.1-127965.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" -module \dec_cr_in$182 - attribute \src "libresoc.v:128104.3-128130.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:128131.3-128141.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128071.3-128081.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128142.3-128152.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128082.3-128092.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128044.3-128070.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128180.3-128198.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:128093.3-128103.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:127902.7-127902.20" +module \dec_oe$140 + attribute \src "libresoc.v:127834.7-127834.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128153.3-128163.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:128164.3-128179.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:128104.3-128130.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128131.3-128141.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128071.3-128081.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128142.3-128152.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128082.3-128092.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128044.3-128070.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128180.3-128198.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:128093.3-128103.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128153.3-128163.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:128164.3-128179.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:128180.3-128198.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:128164.3-128179.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:128037.17-128037.112" - wire $and$libresoc.v:128037$4880_Y - attribute \src "libresoc.v:128039.17-128039.112" - wire $and$libresoc.v:128039$4882_Y - attribute \src "libresoc.v:128036.17-128036.121" - wire $eq$libresoc.v:128036$4879_Y - attribute \src "libresoc.v:128038.17-128038.121" - wire $eq$libresoc.v:128038$4881_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 4 \MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 3 \MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 8 \MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 7 \MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 5 \MUL_BT + attribute \src "libresoc.v:127923.3-127943.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:127944.3-127964.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:127923.3-127943.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:127944.3-127964.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:127923.3-127943.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:127944.3-127964.6" + wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 6 \MUL_FXM + wire input 2 \CR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -200089,470 +201799,115 @@ module \dec_cr_in$182 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 2 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire width 7 input 1 \CR_internal_op + attribute \src "libresoc.v:127834.7-127834.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:127902.7-127902.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:128037$4880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:128037$4880_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:128039$4882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:128039$4882_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:128036$4879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:128036$4879_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:128038$4881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:128038$4881_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:128040.15-128043.4" - cell \ppick$183 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:127902.7-127902.20" - process $proc$libresoc.v:127902$4893 + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:127834.7-127834.20" + process $proc$libresoc.v:127834$5023 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128044.3-128070.6" - process $proc$libresoc.v:128044$4883 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128045.5-128045.29" - switch \initial - attribute \src "libresoc.v:128045.9-128045.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:128071.3-128081.6" - process $proc$libresoc.v:128071$4884 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128072.5-128072.29" - switch \initial - attribute \src "libresoc.v:128072.9-128072.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:128082.3-128092.6" - process $proc$libresoc.v:128082$4885 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128083.5-128083.29" - switch \initial - attribute \src "libresoc.v:128083.9-128083.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:128093.3-128103.6" - process $proc$libresoc.v:128093$4886 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128094.5-128094.29" - switch \initial - attribute \src "libresoc.v:128094.9-128094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:128104.3-128130.6" - process $proc$libresoc.v:128104$4887 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128105.5-128105.29" - switch \initial - attribute \src "libresoc.v:128105.9-128105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:128131.3-128141.6" - process $proc$libresoc.v:128131$4888 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128132.5-128132.29" - switch \initial - attribute \src "libresoc.v:128132.9-128132.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \MUL_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:128142.3-128152.6" - process $proc$libresoc.v:128142$4889 + attribute \src "libresoc.v:127923.3-127943.6" + process $proc$libresoc.v:127923$5021 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128143.5-128143.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:127924.5-127924.29" switch \initial - attribute \src "libresoc.v:128143.9-128143.17" + attribute \src "libresoc.v:127924.9-127924.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \MUL_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:128153.3-128163.6" - process $proc$libresoc.v:128153$4890 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:128154.5-128154.29" - switch \initial - attribute \src "libresoc.v:128154.9-128154.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:128164.3-128179.6" - process $proc$libresoc.v:128164$4891 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:128165.5-128165.29" - switch \initial - attribute \src "libresoc.v:128165.9-128165.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$3 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\ppick_i[7:0] \MUL_FXM + assign $2\oe[0:0] \CR_OE case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\oe[0:0] 1'0 end - case - assign $1\ppick_i[7:0] 8'00000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128180.3-128198.6" - process $proc$libresoc.v:128180$4892 + attribute \src "libresoc.v:127944.3-127964.6" + process $proc$libresoc.v:127944$5022 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:128181.5-128181.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:127945.5-127945.29" switch \initial - attribute \src "libresoc.v:128181.9-128181.17" + attribute \src "libresoc.v:127945.9-127945.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \CR_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$7 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" + assign $2\oe_ok[0:0] 1'1 case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\oe_ok[0:0] 1'0 end - case - assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \oe_ok $0\oe_ok[0:0] end - connect \$1 $eq$libresoc.v:128036$4879_Y - connect \$3 $and$libresoc.v:128037$4880_Y - connect \$5 $eq$libresoc.v:128038$4881_Y - connect \$7 $and$libresoc.v:128039$4882_Y end -attribute \src "libresoc.v:128203.1-128501.10" +attribute \src "libresoc.v:127969.1-128101.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" attribute \generator "nMigen" -module \dec_cr_in$190 - attribute \src "libresoc.v:128406.3-128432.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:128433.3-128443.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128373.3-128383.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128444.3-128454.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128384.3-128394.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128346.3-128372.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128482.3-128500.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:128395.3-128405.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128204.7-128204.20" +module \dec_oe$143 + attribute \src "libresoc.v:127970.7-127970.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128455.3-128465.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:128466.3-128481.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:128406.3-128432.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128433.3-128443.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128373.3-128383.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128444.3-128454.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128384.3-128394.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128346.3-128372.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128482.3-128500.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:128395.3-128405.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128455.3-128465.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:128466.3-128481.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:128482.3-128500.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:128466.3-128481.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:128339.17-128339.112" - wire $and$libresoc.v:128339$4895_Y - attribute \src "libresoc.v:128341.17-128341.112" - wire $and$libresoc.v:128341$4897_Y - attribute \src "libresoc.v:128338.17-128338.127" - wire $eq$libresoc.v:128338$4894_Y - attribute \src "libresoc.v:128340.17-128340.127" - wire $eq$libresoc.v:128340$4896_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 4 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 3 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 8 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 7 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 5 \SHIFT_ROT_BT + attribute \src "libresoc.v:128059.3-128079.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:128080.3-128100.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:128059.3-128079.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:128080.3-128100.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:128059.3-128079.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:128080.3-128100.6" + wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 6 \SHIFT_ROT_FXM + wire input 2 \BRANCH_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -200628,470 +201983,115 @@ module \dec_cr_in$190 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 2 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire width 7 input 1 \BRANCH_internal_op + attribute \src "libresoc.v:127970.7-127970.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:128204.7-128204.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:128339$4895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:128339$4895_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:128341$4897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:128341$4897_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:128338$4894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:128338$4894_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:128340$4896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:128340$4896_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:128342.15-128345.4" - cell \ppick$191 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:128204.7-128204.20" - process $proc$libresoc.v:128204$4908 + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:127970.7-127970.20" + process $proc$libresoc.v:127970$5026 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128346.3-128372.6" - process $proc$libresoc.v:128346$4898 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128347.5-128347.29" - switch \initial - attribute \src "libresoc.v:128347.9-128347.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:128373.3-128383.6" - process $proc$libresoc.v:128373$4899 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128374.5-128374.29" - switch \initial - attribute \src "libresoc.v:128374.9-128374.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:128384.3-128394.6" - process $proc$libresoc.v:128384$4900 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128385.5-128385.29" - switch \initial - attribute \src "libresoc.v:128385.9-128385.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:128395.3-128405.6" - process $proc$libresoc.v:128395$4901 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128396.5-128396.29" - switch \initial - attribute \src "libresoc.v:128396.9-128396.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:128406.3-128432.6" - process $proc$libresoc.v:128406$4902 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128407.5-128407.29" - switch \initial - attribute \src "libresoc.v:128407.9-128407.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:128433.3-128443.6" - process $proc$libresoc.v:128433$4903 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128434.5-128434.29" - switch \initial - attribute \src "libresoc.v:128434.9-128434.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \SHIFT_ROT_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:128444.3-128454.6" - process $proc$libresoc.v:128444$4904 + attribute \src "libresoc.v:128059.3-128079.6" + process $proc$libresoc.v:128059$5024 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128445.5-128445.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:128060.5-128060.29" switch \initial - attribute \src "libresoc.v:128445.9-128445.17" + attribute \src "libresoc.v:128060.9-128060.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \SHIFT_ROT_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:128455.3-128465.6" - process $proc$libresoc.v:128455$4905 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:128456.5-128456.29" - switch \initial - attribute \src "libresoc.v:128456.9-128456.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:128466.3-128481.6" - process $proc$libresoc.v:128466$4906 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:128467.5-128467.29" - switch \initial - attribute \src "libresoc.v:128467.9-128467.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$3 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\ppick_i[7:0] \SHIFT_ROT_FXM + assign $2\oe[0:0] \BRANCH_OE case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\oe[0:0] 1'0 end - case - assign $1\ppick_i[7:0] 8'00000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128482.3-128500.6" - process $proc$libresoc.v:128482$4907 + attribute \src "libresoc.v:128080.3-128100.6" + process $proc$libresoc.v:128080$5025 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:128483.5-128483.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:128081.5-128081.29" switch \initial - attribute \src "libresoc.v:128483.9-128483.17" + attribute \src "libresoc.v:128081.9-128081.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \BRANCH_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$7 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" + assign $2\oe_ok[0:0] 1'1 case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\oe_ok[0:0] 1'0 end - case - assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \oe_ok $0\oe_ok[0:0] end - connect \$1 $eq$libresoc.v:128338$4894_Y - connect \$3 $and$libresoc.v:128339$4895_Y - connect \$5 $eq$libresoc.v:128340$4896_Y - connect \$7 $and$libresoc.v:128341$4897_Y end -attribute \src "libresoc.v:128505.1-128803.10" +attribute \src "libresoc.v:128105.1-128239.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" attribute \generator "nMigen" -module \dec_cr_in$198 - attribute \src "libresoc.v:128708.3-128734.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:128735.3-128745.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128675.3-128685.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128746.3-128756.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128686.3-128696.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128648.3-128674.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128784.3-128802.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:128697.3-128707.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128506.7-128506.20" +module \dec_oe$147 + attribute \src "libresoc.v:128106.7-128106.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128757.3-128767.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:128768.3-128783.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:128708.3-128734.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128735.3-128745.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128675.3-128685.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128746.3-128756.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128686.3-128696.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128648.3-128674.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128784.3-128802.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:128697.3-128707.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128757.3-128767.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:128768.3-128783.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:128784.3-128802.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:128768.3-128783.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:128641.17-128641.112" - wire $and$libresoc.v:128641$4910_Y - attribute \src "libresoc.v:128643.17-128643.112" - wire $and$libresoc.v:128643$4912_Y - attribute \src "libresoc.v:128640.17-128640.122" - wire $eq$libresoc.v:128640$4909_Y - attribute \src "libresoc.v:128642.17-128642.122" - wire $eq$libresoc.v:128642$4911_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 4 \LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 3 \LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 8 \LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 7 \LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 5 \LDST_BT + attribute \src "libresoc.v:128197.3-128217.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:128218.3-128238.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:128197.3-128217.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:128218.3-128238.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:128197.3-128217.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:128218.3-128238.6" + wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 6 \LDST_FXM + wire input 4 \LOGICAL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -201167,492 +202167,115 @@ module \dec_cr_in$198 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 2 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire width 7 input 1 \LOGICAL_internal_op + attribute \src "libresoc.v:128106.7-128106.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:128506.7-128506.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:128641$4910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:128641$4910_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:128643$4912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:128643$4912_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:128640$4909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:128640$4909_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:128642$4911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:128642$4911_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:128644.15-128647.4" - cell \ppick$199 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:128506.7-128506.20" - process $proc$libresoc.v:128506$4923 + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:128106.7-128106.20" + process $proc$libresoc.v:128106$5029 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128648.3-128674.6" - process $proc$libresoc.v:128648$4913 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128649.5-128649.29" - switch \initial - attribute \src "libresoc.v:128649.9-128649.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:128675.3-128685.6" - process $proc$libresoc.v:128675$4914 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128676.5-128676.29" - switch \initial - attribute \src "libresoc.v:128676.9-128676.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:128686.3-128696.6" - process $proc$libresoc.v:128686$4915 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128687.5-128687.29" - switch \initial - attribute \src "libresoc.v:128687.9-128687.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:128697.3-128707.6" - process $proc$libresoc.v:128697$4916 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128698.5-128698.29" - switch \initial - attribute \src "libresoc.v:128698.9-128698.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:128708.3-128734.6" - process $proc$libresoc.v:128708$4917 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128709.5-128709.29" - switch \initial - attribute \src "libresoc.v:128709.9-128709.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \LDST_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \LDST_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \LDST_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:128735.3-128745.6" - process $proc$libresoc.v:128735$4918 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128736.5-128736.29" - switch \initial - attribute \src "libresoc.v:128736.9-128736.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \LDST_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:128746.3-128756.6" - process $proc$libresoc.v:128746$4919 + attribute \src "libresoc.v:128197.3-128217.6" + process $proc$libresoc.v:128197$5027 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128747.5-128747.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:128198.5-128198.29" switch \initial - attribute \src "libresoc.v:128747.9-128747.17" + attribute \src "libresoc.v:128198.9-128198.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \LDST_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:128757.3-128767.6" - process $proc$libresoc.v:128757$4920 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:128758.5-128758.29" - switch \initial - attribute \src "libresoc.v:128758.9-128758.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:128768.3-128783.6" - process $proc$libresoc.v:128768$4921 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:128769.5-128769.29" - switch \initial - attribute \src "libresoc.v:128769.9-128769.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$3 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\ppick_i[7:0] \LDST_FXM + assign $2\oe[0:0] \LOGICAL_OE case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\oe[0:0] 1'0 end - case - assign $1\ppick_i[7:0] 8'00000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:128784.3-128802.6" - process $proc$libresoc.v:128784$4922 + attribute \src "libresoc.v:128218.3-128238.6" + process $proc$libresoc.v:128218$5028 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:128785.5-128785.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:128219.5-128219.29" switch \initial - attribute \src "libresoc.v:128785.9-128785.17" + attribute \src "libresoc.v:128219.9-128219.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \LOGICAL_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$7 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" + assign $2\oe_ok[0:0] 1'1 case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\oe_ok[0:0] 1'0 end - case - assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \oe_ok $0\oe_ok[0:0] end - connect \$1 $eq$libresoc.v:128640$4909_Y - connect \$3 $and$libresoc.v:128641$4910_Y - connect \$5 $eq$libresoc.v:128642$4911_Y - connect \$7 $and$libresoc.v:128643$4912_Y end -attribute \src "libresoc.v:128807.1-129113.10" +attribute \src "libresoc.v:128243.1-128375.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" attribute \generator "nMigen" -module \dec_cr_in$207 - attribute \src "libresoc.v:129018.3-129044.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:129045.3-129055.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128985.3-128995.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:129056.3-129066.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128996.3-129006.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128958.3-128984.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129094.3-129112.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:129007.3-129017.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128808.7-128808.20" +module \dec_oe$152 + attribute \src "libresoc.v:128244.7-128244.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129067.3-129077.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:129078.3-129093.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:129018.3-129044.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129045.3-129055.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128985.3-128995.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:129056.3-129066.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128996.3-129006.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128958.3-128984.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129094.3-129112.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:129007.3-129017.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129067.3-129077.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:129078.3-129093.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:129094.3-129112.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:129078.3-129093.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:128951.17-128951.112" - wire $and$libresoc.v:128951$4925_Y - attribute \src "libresoc.v:128953.17-128953.112" - wire $and$libresoc.v:128953$4927_Y - attribute \src "libresoc.v:128950.17-128950.117" - wire $eq$libresoc.v:128950$4924_Y - attribute \src "libresoc.v:128952.17-128952.117" - wire $eq$libresoc.v:128952$4926_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 12 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 11 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 16 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 15 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 13 \BT + attribute \src "libresoc.v:128333.3-128353.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:128354.3-128374.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:128333.3-128353.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:128354.3-128374.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:128333.3-128353.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:128354.3-128374.6" + wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 14 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 17 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 5 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 7 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 8 \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 9 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 10 \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 6 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 output 3 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_fxm_ok - attribute \src "libresoc.v:128808.7-128808.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" - wire width 32 input 18 \insn_in + wire input 2 \SPR_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -201728,420 +202351,115 @@ module \dec_cr_in$207 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 2 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \enum_value_111 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:128951$4925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:128951$4925_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $and $and$libresoc.v:128953$4927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:128953$4927_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:128950$4924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:128950$4924_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - cell $eq $eq$libresoc.v:128952$4926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:128952$4926_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:128954.15-128957.4" - cell \ppick$208 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:128808.7-128808.20" - process $proc$libresoc.v:128808$4938 + wire width 7 input 1 \SPR_internal_op + attribute \src "libresoc.v:128244.7-128244.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:128244.7-128244.20" + process $proc$libresoc.v:128244$5032 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128958.3-128984.6" - process $proc$libresoc.v:128958$4928 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128959.5-128959.29" - switch \initial - attribute \src "libresoc.v:128959.9-128959.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:128985.3-128995.6" - process $proc$libresoc.v:128985$4929 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128986.5-128986.29" - switch \initial - attribute \src "libresoc.v:128986.9-128986.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:128996.3-129006.6" - process $proc$libresoc.v:128996$4930 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128997.5-128997.29" - switch \initial - attribute \src "libresoc.v:128997.9-128997.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:129007.3-129017.6" - process $proc$libresoc.v:129007$4931 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129008.5-129008.29" - switch \initial - attribute \src "libresoc.v:129008.9-129008.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:129018.3-129044.6" - process $proc$libresoc.v:129018$4932 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129019.5-129019.29" - switch \initial - attribute \src "libresoc.v:129019.9-129019.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:129045.3-129055.6" - process $proc$libresoc.v:129045$4933 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:129046.5-129046.29" - switch \initial - attribute \src "libresoc.v:129046.9-129046.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:129056.3-129066.6" - process $proc$libresoc.v:129056$4934 + attribute \src "libresoc.v:128333.3-128353.6" + process $proc$libresoc.v:128333$5030 assign { } { } assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:129057.5-129057.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:128334.5-128334.29" switch \initial - attribute \src "libresoc.v:129057.9-129057.17" + attribute \src "libresoc.v:128334.9-128334.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:129067.3-129077.6" - process $proc$libresoc.v:129067$4935 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:129068.5-129068.29" - switch \initial - attribute \src "libresoc.v:129068.9-129068.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:129078.3-129093.6" - process $proc$libresoc.v:129078$4936 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:129079.5-129079.29" - switch \initial - attribute \src "libresoc.v:129079.9-129079.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$3 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\ppick_i[7:0] \FXM + assign $2\oe[0:0] \SPR_OE case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\oe[0:0] 1'0 end - case - assign $1\ppick_i[7:0] 8'00000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129094.3-129112.6" - process $proc$libresoc.v:129094$4937 + attribute \src "libresoc.v:128354.3-128374.6" + process $proc$libresoc.v:128354$5031 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:129095.5-129095.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:128355.5-128355.29" switch \initial - attribute \src "libresoc.v:129095.9-129095.17" + attribute \src "libresoc.v:128355.9-128355.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \SPR_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'110 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" - switch \$7 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" + assign $2\oe_ok[0:0] 1'1 case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\oe_ok[0:0] 1'0 end - case - assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \oe_ok $0\oe_ok[0:0] end - connect \$1 $eq$libresoc.v:128950$4924_Y - connect \$3 $and$libresoc.v:128951$4925_Y - connect \$5 $eq$libresoc.v:128952$4926_Y - connect \$7 $and$libresoc.v:128953$4927_Y end -attribute \src "libresoc.v:129117.1-129358.10" +attribute \src "libresoc.v:128379.1-128513.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" attribute \generator "nMigen" -module \dec_cr_out - attribute \src "libresoc.v:129272.3-129290.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:129242.3-129260.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129323.3-129357.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:129261.3-129271.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129118.7-129118.20" +module \dec_oe$155 + attribute \src "libresoc.v:128380.7-128380.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129291.3-129301.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:129302.3-129322.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:129272.3-129290.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129242.3-129260.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129323.3-129357.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:129261.3-129271.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129291.3-129301.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:129302.3-129322.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:129323.3-129357.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:129302.3-129322.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:129323.3-129357.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:129302.3-129322.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:129323.3-129357.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:129235.17-129235.121" - wire $eq$libresoc.v:129235$4939_Y - attribute \src "libresoc.v:129236.17-129236.121" - wire $eq$libresoc.v:129236$4940_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$3 + attribute \src "libresoc.v:128471.3-128491.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:128492.3-128512.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:128471.3-128491.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:128492.3-128512.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:128471.3-128491.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:128492.3-128512.6" + wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 5 \ALU_FXM + wire input 4 \DIV_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -202217,338 +202535,115 @@ module \dec_cr_out attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 3 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok + wire width 7 input 1 \DIV_internal_op + attribute \src "libresoc.v:128380.7-128380.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:129118.7-129118.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:129235$4939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:129235$4939_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:129236$4940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:129236$4940_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:129237.15-129241.4" - cell \ppick$138 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:129118.7-129118.20" - process $proc$libresoc.v:129118$4947 + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:128380.7-128380.20" + process $proc$libresoc.v:128380$5035 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129242.3-129260.6" - process $proc$libresoc.v:129242$4941 + attribute \src "libresoc.v:128471.3-128491.6" + process $proc$libresoc.v:128471$5033 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129243.5-129243.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:128472.5-128472.29" switch \initial - attribute \src "libresoc.v:129243.9-129243.17" + attribute \src "libresoc.v:128472.9-128472.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:129261.3-129271.6" - process $proc$libresoc.v:129261$4942 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129262.5-129262.29" - switch \initial - attribute \src "libresoc.v:129262.9-129262.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:129272.3-129290.6" - process $proc$libresoc.v:129272$4943 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129273.5-129273.29" - switch \initial - attribute \src "libresoc.v:129273.9-129273.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:129291.3-129301.6" - process $proc$libresoc.v:129291$4944 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:129292.5-129292.29" - switch \initial - attribute \src "libresoc.v:129292.9-129292.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:129302.3-129322.6" - process $proc$libresoc.v:129302$4945 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:129303.5-129303.29" - switch \initial - attribute \src "libresoc.v:129303.9-129303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$1 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \ALU_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end + assign $2\oe[0:0] \DIV_OE case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\oe[0:0] 1'0 end - case - assign $1\ppick_i[7:0] 8'00000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129323.3-129357.6" - process $proc$libresoc.v:129323$4946 + attribute \src "libresoc.v:128492.3-128512.6" + process $proc$libresoc.v:128492$5034 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:129324.5-129324.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:128493.5-128493.29" switch \initial - attribute \src "libresoc.v:129324.9-129324.17" + attribute \src "libresoc.v:128493.9-128493.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \DIV_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$3 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \ALU_FXM - end - attribute \src "libresoc.v:0.0-0.0" + assign $2\oe_ok[0:0] 1'1 case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\oe_ok[0:0] 1'0 end - case - assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \oe_ok $0\oe_ok[0:0] end - connect \$1 $eq$libresoc.v:129235$4939_Y - connect \$3 $eq$libresoc.v:129236$4940_Y end -attribute \src "libresoc.v:129362.1-129602.10" +attribute \src "libresoc.v:128517.1-128651.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" attribute \generator "nMigen" -module \dec_cr_out$144 - attribute \src "libresoc.v:129516.3-129534.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:129486.3-129504.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129567.3-129601.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:129505.3-129515.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129363.7-129363.20" +module \dec_oe$160 + attribute \src "libresoc.v:128518.7-128518.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129535.3-129545.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:129546.3-129566.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:129516.3-129534.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129486.3-129504.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129567.3-129601.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:129505.3-129515.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129535.3-129545.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:129546.3-129566.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:129567.3-129601.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:129546.3-129566.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:129567.3-129601.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:129546.3-129566.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:129567.3-129601.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:129479.17-129479.120" - wire $eq$libresoc.v:129479$4948_Y - attribute \src "libresoc.v:129480.17-129480.120" - wire $eq$libresoc.v:129480$4949_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$3 + attribute \src "libresoc.v:128609.3-128629.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:128630.3-128650.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:128609.3-128629.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:128630.3-128650.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:128609.3-128629.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:128630.3-128650.6" + wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 4 \CR_FXM + wire input 4 \MUL_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -202624,338 +202719,115 @@ module \dec_cr_out$144 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 3 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire width 7 input 1 \MUL_internal_op + attribute \src "libresoc.v:128518.7-128518.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:129363.7-129363.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:129479$4948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:129479$4948_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:129480$4949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:129480$4949_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:129481.15-129485.4" - cell \ppick$145 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:129363.7-129363.20" - process $proc$libresoc.v:129363$4956 + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:128518.7-128518.20" + process $proc$libresoc.v:128518$5038 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129486.3-129504.6" - process $proc$libresoc.v:129486$4950 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129487.5-129487.29" - switch \initial - attribute \src "libresoc.v:129487.9-129487.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:129505.3-129515.6" - process $proc$libresoc.v:129505$4951 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129506.5-129506.29" - switch \initial - attribute \src "libresoc.v:129506.9-129506.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:129516.3-129534.6" - process $proc$libresoc.v:129516$4952 + attribute \src "libresoc.v:128609.3-128629.6" + process $proc$libresoc.v:128609$5036 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129517.5-129517.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:128610.5-128610.29" switch \initial - attribute \src "libresoc.v:129517.9-129517.17" + attribute \src "libresoc.v:128610.9-128610.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:129535.3-129545.6" - process $proc$libresoc.v:129535$4953 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:129536.5-129536.29" - switch \initial - attribute \src "libresoc.v:129536.9-129536.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:129546.3-129566.6" - process $proc$libresoc.v:129546$4954 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:129547.5-129547.29" - switch \initial - attribute \src "libresoc.v:129547.9-129547.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$1 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \CR_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end + assign $2\oe[0:0] \MUL_OE case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\oe[0:0] 1'0 end - case - assign $1\ppick_i[7:0] 8'00000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129567.3-129601.6" - process $proc$libresoc.v:129567$4955 + attribute \src "libresoc.v:128630.3-128650.6" + process $proc$libresoc.v:128630$5037 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:129568.5-129568.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:128631.5-128631.29" switch \initial - attribute \src "libresoc.v:129568.9-129568.17" + attribute \src "libresoc.v:128631.9-128631.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \MUL_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$3 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \CR_FXM - end - attribute \src "libresoc.v:0.0-0.0" + assign $2\oe_ok[0:0] 1'1 case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\oe_ok[0:0] 1'0 end - case - assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \oe_ok $0\oe_ok[0:0] end - connect \$1 $eq$libresoc.v:129479$4948_Y - connect \$3 $eq$libresoc.v:129480$4949_Y end -attribute \src "libresoc.v:129606.1-129846.10" +attribute \src "libresoc.v:128655.1-128789.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" attribute \generator "nMigen" -module \dec_cr_out$151 - attribute \src "libresoc.v:129760.3-129778.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:129730.3-129748.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129811.3-129845.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:129749.3-129759.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129607.7-129607.20" +module \dec_oe$164 + attribute \src "libresoc.v:128656.7-128656.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129779.3-129789.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:129790.3-129810.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:129760.3-129778.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129730.3-129748.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129811.3-129845.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:129749.3-129759.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129779.3-129789.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:129790.3-129810.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:129811.3-129845.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:129790.3-129810.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:129811.3-129845.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:129790.3-129810.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:129811.3-129845.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:129723.17-129723.124" - wire $eq$libresoc.v:129723$4957_Y - attribute \src "libresoc.v:129724.17-129724.124" - wire $eq$libresoc.v:129724$4958_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$3 + attribute \src "libresoc.v:128747.3-128767.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:128768.3-128788.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:128747.3-128767.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:128768.3-128788.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:128747.3-128767.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:128768.3-128788.6" + wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 4 \BRANCH_FXM + wire input 4 \SHIFT_ROT_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -203031,338 +202903,115 @@ module \dec_cr_out$151 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 3 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire width 7 input 1 \SHIFT_ROT_internal_op + attribute \src "libresoc.v:128656.7-128656.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:129607.7-129607.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:129723$4957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:129723$4957_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:129724$4958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:129724$4958_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:129725.15-129729.4" - cell \ppick$152 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:129607.7-129607.20" - process $proc$libresoc.v:129607$4965 + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:128656.7-128656.20" + process $proc$libresoc.v:128656$5041 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129730.3-129748.6" - process $proc$libresoc.v:129730$4959 + attribute \src "libresoc.v:128747.3-128767.6" + process $proc$libresoc.v:128747$5039 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129731.5-129731.29" - switch \initial - attribute \src "libresoc.v:129731.9-129731.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:129749.3-129759.6" - process $proc$libresoc.v:129749$4960 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129750.5-129750.29" - switch \initial - attribute \src "libresoc.v:129750.9-129750.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:129760.3-129778.6" - process $proc$libresoc.v:129760$4961 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129761.5-129761.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:128748.5-128748.29" switch \initial - attribute \src "libresoc.v:129761.9-129761.17" + attribute \src "libresoc.v:128748.9-128748.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:129779.3-129789.6" - process $proc$libresoc.v:129779$4962 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:129780.5-129780.29" - switch \initial - attribute \src "libresoc.v:129780.9-129780.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:129790.3-129810.6" - process $proc$libresoc.v:129790$4963 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:129791.5-129791.29" - switch \initial - attribute \src "libresoc.v:129791.9-129791.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$1 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \BRANCH_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end + assign $2\oe[0:0] \SHIFT_ROT_OE case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\oe[0:0] 1'0 end - case - assign $1\ppick_i[7:0] 8'00000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129811.3-129845.6" - process $proc$libresoc.v:129811$4964 + attribute \src "libresoc.v:128768.3-128788.6" + process $proc$libresoc.v:128768$5040 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:129812.5-129812.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:128769.5-128769.29" switch \initial - attribute \src "libresoc.v:129812.9-129812.17" + attribute \src "libresoc.v:128769.9-128769.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \SHIFT_ROT_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$3 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \BRANCH_FXM - end - attribute \src "libresoc.v:0.0-0.0" + assign $2\oe_ok[0:0] 1'1 case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\oe_ok[0:0] 1'0 end - case - assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \oe_ok $0\oe_ok[0:0] end - connect \$1 $eq$libresoc.v:129723$4957_Y - connect \$3 $eq$libresoc.v:129724$4958_Y end -attribute \src "libresoc.v:129850.1-130091.10" +attribute \src "libresoc.v:128793.1-128927.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" attribute \generator "nMigen" -module \dec_cr_out$159 - attribute \src "libresoc.v:130005.3-130023.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:129975.3-129993.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130056.3-130090.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:129994.3-130004.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129851.7-129851.20" +module \dec_oe$168 + attribute \src "libresoc.v:128794.7-128794.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130024.3-130034.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:130035.3-130055.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:130005.3-130023.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:129975.3-129993.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130056.3-130090.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:129994.3-130004.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130024.3-130034.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:130035.3-130055.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:130056.3-130090.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:130035.3-130055.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:130056.3-130090.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:130035.3-130055.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:130056.3-130090.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:129968.17-129968.125" - wire $eq$libresoc.v:129968$4966_Y - attribute \src "libresoc.v:129969.17-129969.125" - wire $eq$libresoc.v:129969$4967_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$3 + attribute \src "libresoc.v:128885.3-128905.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:128906.3-128926.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:128885.3-128905.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:128906.3-128926.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:128885.3-128905.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:128906.3-128926.6" + wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 5 \LOGICAL_FXM + wire input 4 \LDST_OE attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -203438,338 +203087,117 @@ module \dec_cr_out$159 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 3 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok + wire width 7 input 1 \LDST_internal_op + attribute \src "libresoc.v:128794.7-128794.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:129851.7-129851.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:129968$4966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:129968$4966_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:129969$4967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:129969$4967_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:129970.15-129974.4" - cell \ppick$160 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:129851.7-129851.20" - process $proc$libresoc.v:129851$4974 + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:128794.7-128794.20" + process $proc$libresoc.v:128794$5044 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129975.3-129993.6" - process $proc$libresoc.v:129975$4968 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:129976.5-129976.29" - switch \initial - attribute \src "libresoc.v:129976.9-129976.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:129994.3-130004.6" - process $proc$libresoc.v:129994$4969 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:129995.5-129995.29" - switch \initial - attribute \src "libresoc.v:129995.9-129995.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:130005.3-130023.6" - process $proc$libresoc.v:130005$4970 + attribute \src "libresoc.v:128885.3-128905.6" + process $proc$libresoc.v:128885$5042 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:130006.5-130006.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:128886.5-128886.29" switch \initial - attribute \src "libresoc.v:130006.9-130006.17" + attribute \src "libresoc.v:128886.9-128886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:130024.3-130034.6" - process $proc$libresoc.v:130024$4971 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:130025.5-130025.29" - switch \initial - attribute \src "libresoc.v:130025.9-130025.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:130035.3-130055.6" - process $proc$libresoc.v:130035$4972 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:130036.5-130036.29" - switch \initial - attribute \src "libresoc.v:130036.9-130036.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$1 + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \LOGICAL_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end + assign $2\oe[0:0] \LDST_OE case - assign $2\ppick_i[7:0] 8'00000000 + assign $2\oe[0:0] 1'0 end - case - assign $1\ppick_i[7:0] 8'00000000 end sync always - update \ppick_i $0\ppick_i[7:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130056.3-130090.6" - process $proc$libresoc.v:130056$4973 + attribute \src "libresoc.v:128906.3-128926.6" + process $proc$libresoc.v:128906$5043 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:130057.5-130057.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:128907.5-128907.29" switch \initial - attribute \src "libresoc.v:130057.9-130057.17" + attribute \src "libresoc.v:128907.9-128907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \LDST_internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$3 + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \LOGICAL_FXM - end - attribute \src "libresoc.v:0.0-0.0" + assign $2\oe_ok[0:0] 1'1 case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 + assign $2\oe_ok[0:0] 1'0 end - case - assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \oe_ok $0\oe_ok[0:0] end - connect \$1 $eq$libresoc.v:129968$4966_Y - connect \$3 $eq$libresoc.v:129969$4967_Y end -attribute \src "libresoc.v:130095.1-130335.10" +attribute \src "libresoc.v:128931.1-129065.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" -module \dec_cr_out$168 - attribute \src "libresoc.v:130249.3-130267.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:130219.3-130237.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130300.3-130334.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:130238.3-130248.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130096.7-130096.20" +module \dec_oe$173 + attribute \src "libresoc.v:128932.7-128932.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130268.3-130278.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:130279.3-130299.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:130249.3-130267.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:130219.3-130237.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130300.3-130334.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:130238.3-130248.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130268.3-130278.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:130279.3-130299.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:130300.3-130334.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:130279.3-130299.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:130300.3-130334.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:130279.3-130299.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:130300.3-130334.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:130212.17-130212.121" - wire $eq$libresoc.v:130212$4975_Y - attribute \src "libresoc.v:130213.17-130213.121" - wire $eq$libresoc.v:130213$4976_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$3 + attribute \src "libresoc.v:129023.3-129043.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:129044.3-129064.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:129023.3-129043.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:129044.3-129064.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:129023.3-129043.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:129044.3-129064.6" + wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 4 \SPR_FXM + wire input 4 \OE + attribute \src "libresoc.v:128932.7-128932.15" + wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -203845,1559 +203273,1805 @@ module \dec_cr_out$168 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 3 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire width 7 input 1 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire output 2 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:130096.7-130096.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:130212$4975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:130212$4975_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:130213$4976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:130213$4976_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130214.15-130218.4" - cell \ppick$169 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:130096.7-130096.20" - process $proc$libresoc.v:130096$4983 + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:128932.7-128932.20" + process $proc$libresoc.v:128932$5047 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130219.3-130237.6" - process $proc$libresoc.v:130219$4977 + attribute \src "libresoc.v:129023.3-129043.6" + process $proc$libresoc.v:129023$5045 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130220.5-130220.29" + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:129024.5-129024.29" switch \initial - attribute \src "libresoc.v:130220.9-130220.17" + attribute \src "libresoc.v:129024.9-129024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \OE + case + assign $2\oe[0:0] 1'0 + end end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130238.3-130248.6" - process $proc$libresoc.v:130238$4978 + attribute \src "libresoc.v:129044.3-129064.6" + process $proc$libresoc.v:129044$5046 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130239.5-130239.29" + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:129045.5-129045.29" switch \initial - attribute \src "libresoc.v:130239.9-130239.17" + attribute \src "libresoc.v:129045.9-129045.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:129069.1-129123.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" +attribute \generator "nMigen" +module \dec_rc + attribute \src "libresoc.v:129070.7-129070.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129085.3-129103.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:129104.3-129122.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:129085.3-129103.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:129104.3-129122.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \ALU_Rc + attribute \src "libresoc.v:129070.7-129070.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:129070.7-129070.20" + process $proc$libresoc.v:129070$5050 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:130249.3-130267.6" - process $proc$libresoc.v:130249$4979 + attribute \src "libresoc.v:129085.3-129103.6" + process $proc$libresoc.v:129085$5048 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:130250.5-130250.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:129086.5-129086.29" switch \initial - attribute \src "libresoc.v:130250.9-130250.17" + attribute \src "libresoc.v:129086.9-129086.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 2'10 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 + assign $1\rc[0:0] \ALU_Rc attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 2'01 assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 2'00 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\rc[0:0] 1'0 case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\rc[0:0] 1'0 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:130268.3-130278.6" - process $proc$libresoc.v:130268$4980 + attribute \src "libresoc.v:129104.3-129122.6" + process $proc$libresoc.v:129104$5049 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:130269.5-130269.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:129105.5-129105.29" switch \initial - attribute \src "libresoc.v:130269.9-130269.17" + attribute \src "libresoc.v:129105.9-129105.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:130279.3-130299.6" - process $proc$libresoc.v:130279$4981 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:130280.5-130280.29" - switch \initial - attribute \src "libresoc.v:130280.9-130280.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'01 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \SPR_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:130300.3-130334.6" - process $proc$libresoc.v:130300$4982 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:130301.5-130301.29" - switch \initial - attribute \src "libresoc.v:130301.9-130301.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in + assign $1\rc_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'00 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \SPR_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\rc_ok[0:0] 1'1 case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\rc_ok[0:0] 1'0 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \rc_ok $0\rc_ok[0:0] end - connect \$1 $eq$libresoc.v:130212$4975_Y - connect \$3 $eq$libresoc.v:130213$4976_Y end -attribute \src "libresoc.v:130339.1-130580.10" +attribute \src "libresoc.v:129127.1-129179.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" attribute \generator "nMigen" -module \dec_cr_out$175 - attribute \src "libresoc.v:130494.3-130512.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:130464.3-130482.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130545.3-130579.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:130483.3-130493.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130340.7-130340.20" +module \dec_rc$139 + attribute \src "libresoc.v:129128.7-129128.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130513.3-130523.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:130524.3-130544.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:130494.3-130512.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:130464.3-130482.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130545.3-130579.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:130483.3-130493.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130513.3-130523.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:130524.3-130544.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:130545.3-130579.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:130524.3-130544.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:130545.3-130579.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:130524.3-130544.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:130545.3-130579.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:130457.17-130457.121" - wire $eq$libresoc.v:130457$4984_Y - attribute \src "libresoc.v:130458.17-130458.121" - wire $eq$libresoc.v:130458$4985_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$3 + attribute \src "libresoc.v:129141.3-129159.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:129160.3-129178.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:129141.3-129159.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:129160.3-129178.6" + wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 5 \DIV_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 3 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok + wire input 1 \CR_Rc + attribute \src "libresoc.v:129128.7-129128.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:130340.7-130340.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:130457$4984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:130457$4984_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:130458$4985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:130458$4985_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130459.15-130463.4" - cell \ppick$176 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:130340.7-130340.20" - process $proc$libresoc.v:130340$4992 + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + wire width 2 input 2 \sel_in + attribute \src "libresoc.v:129128.7-129128.20" + process $proc$libresoc.v:129128$5053 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130464.3-130482.6" - process $proc$libresoc.v:130464$4986 + attribute \src "libresoc.v:129141.3-129159.6" + process $proc$libresoc.v:129141$5051 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130465.5-130465.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:129142.5-129142.29" switch \initial - attribute \src "libresoc.v:130465.9-130465.17" + attribute \src "libresoc.v:129142.9-129142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 2'10 assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + assign $1\rc[0:0] \CR_Rc attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 2'01 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 2'00 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\rc[0:0] 1'0 case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\rc[0:0] 1'0 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:130483.3-130493.6" - process $proc$libresoc.v:130483$4987 + attribute \src "libresoc.v:129160.3-129178.6" + process $proc$libresoc.v:129160$5052 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130484.5-130484.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:129161.5-129161.29" switch \initial - attribute \src "libresoc.v:130484.9-130484.17" + attribute \src "libresoc.v:129161.9-129161.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\rc_ok[0:0] 1'0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:129183.1-129235.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" +attribute \generator "nMigen" +module \dec_rc$142 + attribute \src "libresoc.v:129184.7-129184.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129197.3-129215.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:129216.3-129234.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:129197.3-129215.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:129216.3-129234.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 1 \BRANCH_Rc + attribute \src "libresoc.v:129184.7-129184.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + wire width 2 input 2 \sel_in + attribute \src "libresoc.v:129184.7-129184.20" + process $proc$libresoc.v:129184$5056 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:130494.3-130512.6" - process $proc$libresoc.v:130494$4988 + attribute \src "libresoc.v:129197.3-129215.6" + process $proc$libresoc.v:129197$5054 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:130495.5-130495.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:129198.5-129198.29" switch \initial - attribute \src "libresoc.v:130495.9-130495.17" + attribute \src "libresoc.v:129198.9-129198.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 2'10 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 + assign $1\rc[0:0] \BRANCH_Rc attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 2'01 assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 2'00 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\rc[0:0] 1'0 case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\rc[0:0] 1'0 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:130513.3-130523.6" - process $proc$libresoc.v:130513$4989 + attribute \src "libresoc.v:129216.3-129234.6" + process $proc$libresoc.v:129216$5055 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:130514.5-130514.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:129217.5-129217.29" switch \initial - attribute \src "libresoc.v:130514.9-130514.17" + attribute \src "libresoc.v:129217.9-129217.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 case - assign $1\move_one[0:0] 1'0 + assign $1\rc_ok[0:0] 1'0 end sync always - update \move_one $0\move_one[0:0] + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:129239.1-129293.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$146 + attribute \src "libresoc.v:129240.7-129240.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129255.3-129273.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:129274.3-129292.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:129255.3-129273.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:129274.3-129292.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \LOGICAL_Rc + attribute \src "libresoc.v:129240.7-129240.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:129240.7-129240.20" + process $proc$libresoc.v:129240$5059 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:130524.3-130544.6" - process $proc$libresoc.v:130524$4990 + attribute \src "libresoc.v:129255.3-129273.6" + process $proc$libresoc.v:129255$5057 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:130525.5-130525.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:129256.5-129256.29" switch \initial - attribute \src "libresoc.v:130525.9-130525.17" + attribute \src "libresoc.v:129256.9-129256.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \DIV_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\rc[0:0] \LOGICAL_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\rc[0:0] 1'0 end sync always - update \ppick_i $0\ppick_i[7:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:130545.3-130579.6" - process $proc$libresoc.v:130545$4991 + attribute \src "libresoc.v:129274.3-129292.6" + process $proc$libresoc.v:129274$5058 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:130546.5-130546.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:129275.5-129275.29" switch \initial - attribute \src "libresoc.v:130546.9-130546.17" + attribute \src "libresoc.v:129275.9-129275.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \DIV_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\rc_ok[0:0] 1'0 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \rc_ok $0\rc_ok[0:0] end - connect \$1 $eq$libresoc.v:130457$4984_Y - connect \$3 $eq$libresoc.v:130458$4985_Y end -attribute \src "libresoc.v:130584.1-130825.10" +attribute \src "libresoc.v:129297.1-129349.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" attribute \generator "nMigen" -module \dec_cr_out$184 - attribute \src "libresoc.v:130739.3-130757.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:130709.3-130727.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130790.3-130824.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:130728.3-130738.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130585.7-130585.20" +module \dec_rc$151 + attribute \src "libresoc.v:129298.7-129298.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130758.3-130768.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:130769.3-130789.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:130739.3-130757.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:130709.3-130727.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130790.3-130824.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:130728.3-130738.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130758.3-130768.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:130769.3-130789.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:130790.3-130824.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:130769.3-130789.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:130790.3-130824.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:130769.3-130789.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:130790.3-130824.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:130702.17-130702.121" - wire $eq$libresoc.v:130702$4993_Y - attribute \src "libresoc.v:130703.17-130703.121" - wire $eq$libresoc.v:130703$4994_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$3 + attribute \src "libresoc.v:129311.3-129329.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:129330.3-129348.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:129311.3-129329.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:129330.3-129348.6" + wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 5 \MUL_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 3 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok + wire input 1 \SPR_Rc + attribute \src "libresoc.v:129298.7-129298.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:130585.7-130585.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:130702$4993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:130702$4993_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:130703$4994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:130703$4994_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130704.15-130708.4" - cell \ppick$185 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:130585.7-130585.20" - process $proc$libresoc.v:130585$5001 + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + wire width 2 input 2 \sel_in + attribute \src "libresoc.v:129298.7-129298.20" + process $proc$libresoc.v:129298$5062 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130709.3-130727.6" - process $proc$libresoc.v:130709$4995 + attribute \src "libresoc.v:129311.3-129329.6" + process $proc$libresoc.v:129311$5060 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130710.5-130710.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:129312.5-129312.29" switch \initial - attribute \src "libresoc.v:130710.9-130710.17" + attribute \src "libresoc.v:129312.9-129312.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 2'10 assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + assign $1\rc[0:0] \SPR_Rc attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 2'01 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 2'00 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\rc[0:0] 1'0 case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\rc[0:0] 1'0 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:130728.3-130738.6" - process $proc$libresoc.v:130728$4996 + attribute \src "libresoc.v:129330.3-129348.6" + process $proc$libresoc.v:129330$5061 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130729.5-130729.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:129331.5-129331.29" switch \initial - attribute \src "libresoc.v:130729.9-130729.17" + attribute \src "libresoc.v:129331.9-129331.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\rc_ok[0:0] 1'0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:129353.1-129407.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" +attribute \generator "nMigen" +module \dec_rc$154 + attribute \src "libresoc.v:129354.7-129354.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129369.3-129387.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:129388.3-129406.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:129369.3-129387.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:129388.3-129406.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \DIV_Rc + attribute \src "libresoc.v:129354.7-129354.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:129354.7-129354.20" + process $proc$libresoc.v:129354$5065 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:130739.3-130757.6" - process $proc$libresoc.v:130739$4997 + attribute \src "libresoc.v:129369.3-129387.6" + process $proc$libresoc.v:129369$5063 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:130740.5-130740.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:129370.5-129370.29" switch \initial - attribute \src "libresoc.v:130740.9-130740.17" + attribute \src "libresoc.v:129370.9-129370.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 2'10 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 + assign $1\rc[0:0] \DIV_Rc attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 2'01 assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 2'00 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\rc[0:0] 1'0 case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\rc[0:0] 1'0 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:130758.3-130768.6" - process $proc$libresoc.v:130758$4998 + attribute \src "libresoc.v:129388.3-129406.6" + process $proc$libresoc.v:129388$5064 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:130759.5-130759.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:129389.5-129389.29" switch \initial - attribute \src "libresoc.v:130759.9-130759.17" + attribute \src "libresoc.v:129389.9-129389.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 case - assign $1\move_one[0:0] 1'0 + assign $1\rc_ok[0:0] 1'0 end sync always - update \move_one $0\move_one[0:0] + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:129411.1-129465.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$159 + attribute \src "libresoc.v:129412.7-129412.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129427.3-129445.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:129446.3-129464.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:129427.3-129445.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:129446.3-129464.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \MUL_Rc + attribute \src "libresoc.v:129412.7-129412.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:129412.7-129412.20" + process $proc$libresoc.v:129412$5068 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:130769.3-130789.6" - process $proc$libresoc.v:130769$4999 + attribute \src "libresoc.v:129427.3-129445.6" + process $proc$libresoc.v:129427$5066 assign { } { } assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:130770.5-130770.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:129428.5-129428.29" switch \initial - attribute \src "libresoc.v:130770.9-130770.17" + attribute \src "libresoc.v:129428.9-129428.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \MUL_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\rc[0:0] \MUL_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\rc[0:0] 1'0 end sync always - update \ppick_i $0\ppick_i[7:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:130790.3-130824.6" - process $proc$libresoc.v:130790$5000 + attribute \src "libresoc.v:129446.3-129464.6" + process $proc$libresoc.v:129446$5067 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:130791.5-130791.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:129447.5-129447.29" switch \initial - attribute \src "libresoc.v:130791.9-130791.17" + attribute \src "libresoc.v:129447.9-129447.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \MUL_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\rc_ok[0:0] 1'0 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \rc_ok $0\rc_ok[0:0] end - connect \$1 $eq$libresoc.v:130702$4993_Y - connect \$3 $eq$libresoc.v:130703$4994_Y end -attribute \src "libresoc.v:130829.1-131070.10" +attribute \src "libresoc.v:129469.1-129523.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" attribute \generator "nMigen" -module \dec_cr_out$192 - attribute \src "libresoc.v:130984.3-131002.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:130954.3-130972.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:131035.3-131069.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:130973.3-130983.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130830.7-130830.20" +module \dec_rc$163 + attribute \src "libresoc.v:129470.7-129470.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131003.3-131013.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:131014.3-131034.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:130984.3-131002.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:130954.3-130972.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:131035.3-131069.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:130973.3-130983.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:131003.3-131013.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:131014.3-131034.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:131035.3-131069.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:131014.3-131034.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:131035.3-131069.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:131014.3-131034.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:131035.3-131069.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:130947.17-130947.127" - wire $eq$libresoc.v:130947$5002_Y - attribute \src "libresoc.v:130948.17-130948.127" - wire $eq$libresoc.v:130948$5003_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$3 + attribute \src "libresoc.v:129485.3-129503.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:129504.3-129522.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:129485.3-129503.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:129504.3-129522.6" + wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 5 \SHIFT_ROT_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 3 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok + wire input 3 \SHIFT_ROT_Rc + attribute \src "libresoc.v:129470.7-129470.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire output 1 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:130830.7-130830.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:130947$5002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:130947$5002_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:130948$5003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:130948$5003_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130949.15-130953.4" - cell \ppick$193 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:130830.7-130830.20" - process $proc$libresoc.v:130830$5010 + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:129470.7-129470.20" + process $proc$libresoc.v:129470$5071 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130954.3-130972.6" - process $proc$libresoc.v:130954$5004 + attribute \src "libresoc.v:129485.3-129503.6" + process $proc$libresoc.v:129485$5069 assign { } { } assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:130955.5-130955.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:129486.5-129486.29" switch \initial - attribute \src "libresoc.v:130955.9-130955.17" + attribute \src "libresoc.v:129486.9-129486.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 2'10 assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in + assign $1\rc[0:0] \SHIFT_ROT_Rc attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 2'01 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 2'00 assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 + assign $1\rc[0:0] 1'0 case - assign $1\cr_bitfield_ok[0:0] 1'0 + assign $1\rc[0:0] 1'0 end sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:130973.3-130983.6" - process $proc$libresoc.v:130973$5005 + attribute \src "libresoc.v:129504.3-129522.6" + process $proc$libresoc.v:129504$5070 assign { } { } assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:130974.5-130974.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:129505.5-129505.29" switch \initial - attribute \src "libresoc.v:130974.9-130974.17" + attribute \src "libresoc.v:129505.9-129505.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 case - assign $1\cr_fxm_ok[0:0] 1'0 + assign $1\rc_ok[0:0] 1'0 end sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] + update \rc_ok $0\rc_ok[0:0] end - attribute \src "libresoc.v:130984.3-131002.6" - process $proc$libresoc.v:130984$5006 +end +attribute \src "libresoc.v:129527.1-129581.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" +attribute \generator "nMigen" +module \dec_rc$167 + attribute \src "libresoc.v:129528.7-129528.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129543.3-129561.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:129562.3-129580.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:129543.3-129561.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:129562.3-129580.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \LDST_Rc + attribute \src "libresoc.v:129528.7-129528.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:129528.7-129528.20" + process $proc$libresoc.v:129528$5074 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129543.3-129561.6" + process $proc$libresoc.v:129543$5072 assign { } { } assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:130985.5-130985.29" + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:129544.5-129544.29" switch \initial - attribute \src "libresoc.v:130985.9-130985.17" + attribute \src "libresoc.v:129544.9-129544.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'001 + case 2'10 assign { } { } - assign $1\cr_bitfield[2:0] 3'000 + assign $1\rc[0:0] \LDST_Rc attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 2'01 assign { } { } - assign $1\cr_bitfield[2:0] \X_BF + assign $1\rc[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 2'00 assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] + assign $1\rc[0:0] 1'0 case - assign $1\cr_bitfield[2:0] 3'000 + assign $1\rc[0:0] 1'0 end sync always - update \cr_bitfield $0\cr_bitfield[2:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131003.3-131013.6" - process $proc$libresoc.v:131003$5007 + attribute \src "libresoc.v:129562.3-129580.6" + process $proc$libresoc.v:129562$5073 assign { } { } assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:131004.5-131004.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:129563.5-129563.29" switch \initial - attribute \src "libresoc.v:131004.9-131004.17" + attribute \src "libresoc.v:129563.9-129563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\move_one[0:0] \insn_in [20] + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 case - assign $1\move_one[0:0] 1'0 + assign $1\rc_ok[0:0] 1'0 end sync always - update \move_one $0\move_one[0:0] + update \rc_ok $0\rc_ok[0:0] end - attribute \src "libresoc.v:131014.3-131034.6" - process $proc$libresoc.v:131014$5008 - assign { } { } +end +attribute \src "libresoc.v:129585.1-129639.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" +attribute \generator "nMigen" +module \dec_rc$172 + attribute \src "libresoc.v:129586.7-129586.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129601.3-129619.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:129620.3-129638.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:129601.3-129619.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:129620.3-129638.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \Rc + attribute \src "libresoc.v:129586.7-129586.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:436" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:129586.7-129586.20" + process $proc$libresoc.v:129586$5077 assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:131015.5-131015.29" + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129601.3-129619.6" + process $proc$libresoc.v:129601$5075 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:129602.5-129602.29" switch \initial - attribute \src "libresoc.v:131015.9-131015.17" + attribute \src "libresoc.v:129602.9-129602.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \SHIFT_ROT_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end + assign $1\rc[0:0] \Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 case - assign $1\ppick_i[7:0] 8'00000000 + assign $1\rc[0:0] 1'0 end sync always - update \ppick_i $0\ppick_i[7:0] + update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131035.3-131069.6" - process $proc$libresoc.v:131035$5009 + attribute \src "libresoc.v:129620.3-129638.6" + process $proc$libresoc.v:129620$5076 assign { } { } assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:131036.5-131036.29" + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:129621.5-129621.29" switch \initial - attribute \src "libresoc.v:131036.9-131036.17" + attribute \src "libresoc.v:129621.9-129621.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 2'10 assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \SHIFT_ROT_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 case - assign $1\cr_fxm[7:0] 8'00000000 + assign $1\rc_ok[0:0] 1'0 end sync always - update \cr_fxm $0\cr_fxm[7:0] + update \rc_ok $0\rc_ok[0:0] end - connect \$1 $eq$libresoc.v:130947$5002_Y - connect \$3 $eq$libresoc.v:130948$5003_Y end -attribute \src "libresoc.v:131074.1-131314.10" +attribute \src "libresoc.v:129643.1-130883.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" -module \dec_cr_out$200 - attribute \src "libresoc.v:131228.3-131246.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:131198.3-131216.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:131279.3-131313.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:131217.3-131227.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:131075.7-131075.20" +module \div0 + attribute \src "libresoc.v:130440.3-130441.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5217 + attribute \src "libresoc.v:130412.3-130413.75" + wire width 4 $0\alu_div0_logical_op__data_len[3:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 13 $0\alu_div0_logical_op__fn_unit$next[12:0]$5218 + attribute \src "libresoc.v:130382.3-130383.73" + wire width 13 $0\alu_div0_logical_op__fn_unit[12:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5219 + attribute \src "libresoc.v:130384.3-130385.87" + wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5220 + attribute \src "libresoc.v:130386.3-130387.83" + wire $0\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5221 + attribute \src "libresoc.v:130400.3-130401.81" + wire width 2 $0\alu_div0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5222 + attribute \src "libresoc.v:130414.3-130415.67" + wire width 32 $0\alu_div0_logical_op__insn[31:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5223 + attribute \src "libresoc.v:130380.3-130381.77" + wire width 7 $0\alu_div0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$5224 + attribute \src "libresoc.v:130396.3-130397.77" + wire $0\alu_div0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$5225 + attribute \src "libresoc.v:130402.3-130403.79" + wire $0\alu_div0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5226 + attribute \src "libresoc.v:130408.3-130409.75" + wire $0\alu_div0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$5227 + attribute \src "libresoc.v:130410.3-130411.77" + wire $0\alu_div0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5228 + attribute \src "libresoc.v:130392.3-130393.71" + wire $0\alu_div0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5229 + attribute \src "libresoc.v:130394.3-130395.71" + wire $0\alu_div0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$5230 + attribute \src "libresoc.v:130406.3-130407.83" + wire $0\alu_div0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5231 + attribute \src "libresoc.v:130390.3-130391.71" + wire $0\alu_div0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5232 + attribute \src "libresoc.v:130388.3-130389.71" + wire $0\alu_div0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5233 + attribute \src "libresoc.v:130404.3-130405.77" + wire $0\alu_div0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$5234 + attribute \src "libresoc.v:130398.3-130399.71" + wire $0\alu_div0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:130438.3-130439.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:130793.3-130801.6" + wire $0\alu_l_r_alu$next[0:0]$5304 + attribute \src "libresoc.v:130354.3-130355.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:130784.3-130792.6" + wire $0\alui_l_r_alui$next[0:0]$5301 + attribute \src "libresoc.v:130356.3-130357.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:130666.3-130687.6" + wire width 64 $0\data_r0__o$next[63:0]$5260 + attribute \src "libresoc.v:130376.3-130377.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:130666.3-130687.6" + wire $0\data_r0__o_ok$next[0:0]$5261 + attribute \src "libresoc.v:130378.3-130379.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:130688.3-130709.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$5268 + attribute \src "libresoc.v:130372.3-130373.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:130688.3-130709.6" + wire $0\data_r1__cr_a_ok$next[0:0]$5269 + attribute \src "libresoc.v:130374.3-130375.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:130710.3-130731.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$5276 + attribute \src "libresoc.v:130368.3-130369.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:130710.3-130731.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$5277 + attribute \src "libresoc.v:130370.3-130371.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:130732.3-130753.6" + wire $0\data_r3__xer_so$next[0:0]$5284 + attribute \src "libresoc.v:130364.3-130365.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:130732.3-130753.6" + wire $0\data_r3__xer_so_ok$next[0:0]$5285 + attribute \src "libresoc.v:130366.3-130367.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:130802.3-130811.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:130812.3-130821.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:130822.3-130831.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:130832.3-130841.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:129644.7-129644.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131247.3-131257.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:131258.3-131278.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:131228.3-131246.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:131198.3-131216.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:131279.3-131313.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:131217.3-131227.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:131247.3-131257.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:131258.3-131278.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:131279.3-131313.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:131258.3-131278.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:131279.3-131313.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:131258.3-131278.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:131279.3-131313.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:131191.17-131191.122" - wire $eq$libresoc.v:131191$5011_Y - attribute \src "libresoc.v:131192.17-131192.122" - wire $eq$libresoc.v:131192$5012_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 4 \LDST_FXM + attribute \src "libresoc.v:130582.3-130590.6" + wire $0\opc_l_r_opc$next[0:0]$5202 + attribute \src "libresoc.v:130424.3-130425.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:130573.3-130581.6" + wire $0\opc_l_s_opc$next[0:0]$5199 + attribute \src "libresoc.v:130426.3-130427.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:130842.3-130850.6" + wire width 4 $0\prev_wr_go$next[3:0]$5311 + attribute \src "libresoc.v:130436.3-130437.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "libresoc.v:130527.3-130536.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:130618.3-130626.6" + wire width 4 $0\req_l_r_req$next[3:0]$5214 + attribute \src "libresoc.v:130416.3-130417.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "libresoc.v:130609.3-130617.6" + wire width 4 $0\req_l_s_req$next[3:0]$5211 + attribute \src "libresoc.v:130418.3-130419.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "libresoc.v:130546.3-130554.6" + wire $0\rok_l_r_rdok$next[0:0]$5190 + attribute \src "libresoc.v:130432.3-130433.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:130537.3-130545.6" + wire $0\rok_l_s_rdok$next[0:0]$5187 + attribute \src "libresoc.v:130434.3-130435.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:130564.3-130572.6" + wire $0\rst_l_r_rst$next[0:0]$5196 + attribute \src "libresoc.v:130428.3-130429.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:130555.3-130563.6" + wire $0\rst_l_s_rst$next[0:0]$5193 + attribute \src "libresoc.v:130430.3-130431.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:130600.3-130608.6" + wire width 3 $0\src_l_r_src$next[2:0]$5208 + attribute \src "libresoc.v:130420.3-130421.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:130591.3-130599.6" + wire width 3 $0\src_l_s_src$next[2:0]$5205 + attribute \src "libresoc.v:130422.3-130423.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:130754.3-130763.6" + wire width 64 $0\src_r0$next[63:0]$5292 + attribute \src "libresoc.v:130362.3-130363.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:130764.3-130773.6" + wire width 64 $0\src_r1$next[63:0]$5295 + attribute \src "libresoc.v:130360.3-130361.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:130774.3-130783.6" + wire $0\src_r2$next[0:0]$5298 + attribute \src "libresoc.v:130358.3-130359.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:129774.7-129774.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5235 + attribute \src "libresoc.v:129784.13-129784.49" + wire width 4 $1\alu_div0_logical_op__data_len[3:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 13 $1\alu_div0_logical_op__fn_unit$next[12:0]$5236 + attribute \src "libresoc.v:129802.14-129802.53" + wire width 13 $1\alu_div0_logical_op__fn_unit[12:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5237 + attribute \src "libresoc.v:129806.14-129806.72" + wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5238 + attribute \src "libresoc.v:129810.7-129810.47" + wire $1\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5239 + attribute \src "libresoc.v:129818.13-129818.52" + wire width 2 $1\alu_div0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5240 + attribute \src "libresoc.v:129822.14-129822.47" + wire width 32 $1\alu_div0_logical_op__insn[31:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5241 + attribute \src "libresoc.v:129900.13-129900.51" + wire width 7 $1\alu_div0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$5242 + attribute \src "libresoc.v:129904.7-129904.44" + wire $1\alu_div0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$5243 + attribute \src "libresoc.v:129908.7-129908.45" + wire $1\alu_div0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5244 + attribute \src "libresoc.v:129912.7-129912.43" + wire $1\alu_div0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$5245 + attribute \src "libresoc.v:129916.7-129916.44" + wire $1\alu_div0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5246 + attribute \src "libresoc.v:129920.7-129920.41" + wire $1\alu_div0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5247 + attribute \src "libresoc.v:129924.7-129924.41" + wire $1\alu_div0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$5248 + attribute \src "libresoc.v:129928.7-129928.47" + wire $1\alu_div0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5249 + attribute \src "libresoc.v:129932.7-129932.41" + wire $1\alu_div0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5250 + attribute \src "libresoc.v:129936.7-129936.41" + wire $1\alu_div0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5251 + attribute \src "libresoc.v:129940.7-129940.44" + wire $1\alu_div0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:130627.3-130665.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$5252 + attribute \src "libresoc.v:129944.7-129944.41" + wire $1\alu_div0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:129970.7-129970.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:130793.3-130801.6" + wire $1\alu_l_r_alu$next[0:0]$5305 + attribute \src "libresoc.v:129978.7-129978.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:130784.3-130792.6" + wire $1\alui_l_r_alui$next[0:0]$5302 + attribute \src "libresoc.v:129990.7-129990.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:130666.3-130687.6" + wire width 64 $1\data_r0__o$next[63:0]$5262 + attribute \src "libresoc.v:130024.14-130024.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:130666.3-130687.6" + wire $1\data_r0__o_ok$next[0:0]$5263 + attribute \src "libresoc.v:130028.7-130028.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:130688.3-130709.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$5270 + attribute \src "libresoc.v:130032.13-130032.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:130688.3-130709.6" + wire $1\data_r1__cr_a_ok$next[0:0]$5271 + attribute \src "libresoc.v:130036.7-130036.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:130710.3-130731.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$5278 + attribute \src "libresoc.v:130040.13-130040.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:130710.3-130731.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$5279 + attribute \src "libresoc.v:130044.7-130044.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:130732.3-130753.6" + wire $1\data_r3__xer_so$next[0:0]$5286 + attribute \src "libresoc.v:130048.7-130048.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:130732.3-130753.6" + wire $1\data_r3__xer_so_ok$next[0:0]$5287 + attribute \src "libresoc.v:130052.7-130052.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:130802.3-130811.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:130812.3-130821.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:130822.3-130831.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:130832.3-130841.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:130582.3-130590.6" + wire $1\opc_l_r_opc$next[0:0]$5203 + attribute \src "libresoc.v:130072.7-130072.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:130573.3-130581.6" + wire $1\opc_l_s_opc$next[0:0]$5200 + attribute \src "libresoc.v:130076.7-130076.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:130842.3-130850.6" + wire width 4 $1\prev_wr_go$next[3:0]$5312 + attribute \src "libresoc.v:130208.13-130208.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "libresoc.v:130527.3-130536.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:130618.3-130626.6" + wire width 4 $1\req_l_r_req$next[3:0]$5215 + attribute \src "libresoc.v:130216.13-130216.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "libresoc.v:130609.3-130617.6" + wire width 4 $1\req_l_s_req$next[3:0]$5212 + attribute \src "libresoc.v:130220.13-130220.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "libresoc.v:130546.3-130554.6" + wire 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\alu_div0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_div0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_div0_logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_div0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_div0_logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_div0_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_div0_logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_div0_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_div0_logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_div0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_div0_logical_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -205472,355 +205146,214 @@ module \dec_cr_out$200 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 3 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_div0_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_div0_logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \alu_div0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \alu_div0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield + wire width 64 \alu_div0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \alu_div0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \alu_div0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok + wire width 2 \alu_div0_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm + wire \alu_div0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_div0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:131075.7-131075.15" + wire output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 21 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 20 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 24 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 23 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 22 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 33 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 35 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 37 \dest4_o + attribute \src "libresoc.v:129644.7-129644.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \enum_value_101 "CR1" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:131191$5011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:131191$5011_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - cell $eq $eq$libresoc.v:131192$5012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:131192$5012_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:131193.15-131197.4" - cell \ppick$201 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:131075.7-131075.20" - process $proc$libresoc.v:131075$5019 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:131198.3-131216.6" - process $proc$libresoc.v:131198$5013 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:131199.5-131199.29" - switch \initial - attribute \src "libresoc.v:131199.9-131199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:131217.3-131227.6" - process $proc$libresoc.v:131217$5014 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:131218.5-131218.29" - switch \initial - attribute \src "libresoc.v:131218.9-131218.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:131228.3-131246.6" - process $proc$libresoc.v:131228$5015 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:131229.5-131229.29" - switch \initial - attribute \src "libresoc.v:131229.9-131229.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:131247.3-131257.6" - process $proc$libresoc.v:131247$5016 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:131248.5-131248.29" - switch \initial - attribute \src "libresoc.v:131248.9-131248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:131258.3-131278.6" - process $proc$libresoc.v:131258$5017 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:131259.5-131259.29" - switch \initial - attribute \src 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8 $3\ppick_i[7:0] - attribute \src "libresoc.v:131527.3-131561.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:131439.17-131439.117" - wire $eq$libresoc.v:131439$5020_Y - attribute \src "libresoc.v:131440.17-131440.117" - wire $eq$libresoc.v:131440$5021_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 8 input 8 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 5 input 10 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" - wire width 3 input 9 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 6 \cr_bitfield - attribute \src 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\opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 18 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 3 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 12 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \oper_i_alu_div0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -205895,1646 +205428,2756 @@ module \dec_cr_out$209 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 3 \internal_op - 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_div0__output_carry + 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$eq$libresoc.v:131923$5029_Y + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130305$5092_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - cell $eq $eq$libresoc.v:131924$5030 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:130306$5093 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:131924$5030_Y + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130306$5093_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - cell $eq $eq$libresoc.v:131925$5031 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:130308$5095 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:131925$5031_Y + connect \A \all_rd + connect \B \$12 + connect \Y $and$libresoc.v:130308$5095_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:494" - cell $not $not$libresoc.v:131926$5032 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:130310$5097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $not$libresoc.v:131926$5032_Y + connect \A \alu_done + connect \B \$16 + connect \Y $and$libresoc.v:130310$5097_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:131927.16-131933.4" - cell \sprmap$211 \sprmap - connect \fast_o \sprmap_fast_o - connect \fast_o_ok \sprmap_fast_o_ok - connect \spr_i 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attribute \src "libresoc.v:131975.3-131990.6" - process $proc$libresoc.v:131975$5036 - assign { } { } - assign { } { } - assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:131976.5-131976.29" - switch \initial - attribute \src "libresoc.v:131976.9-131976.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sprmap_spr_i[9:0] \spr - case - assign $2\sprmap_spr_i[9:0] 10'0000000000 - end - case - assign $1\sprmap_spr_i[9:0] 10'0000000000 - end - sync always - update \sprmap_spr_i $0\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:130323$5110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:130323$5110_Y end - attribute \src "libresoc.v:131991.3-132007.6" - process $proc$libresoc.v:131991$5037 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:131992.5-131992.29" - switch \initial - attribute \src "libresoc.v:131992.9-131992.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign $1\spr_o[9:0] $2\spr_o[9:0] - assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } - case - assign $2\spr_o[9:0] 10'0000000000 - assign $2\spr_o_ok[0:0] 1'0 - end - case - assign $1\spr_o[9:0] 10'0000000000 - assign $1\spr_o_ok[0:0] 1'0 - end - sync always - update \spr_o $0\spr_o[9:0] - update \spr_o_ok $0\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:130325$5112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \B \$44 + connect \Y $and$libresoc.v:130325$5112_Y end - attribute \src "libresoc.v:132008.3-132046.6" - process $proc$libresoc.v:132008$5038 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $3\fast_o[2:0] - assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:132009.5-132009.29" - switch \initial - attribute \src "libresoc.v:132009.9-132009.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign $1\fast_o[2:0] $2\fast_o[2:0] - assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } - case - assign $2\fast_o[2:0] 3'000 - assign $2\fast_o_ok[0:0] 1'0 - end - case - assign $1\fast_o[2:0] 3'000 - assign $1\fast_o_ok[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0001000 - assign { } { } - assign { } { } - assign $3\fast_o[2:0] $4\fast_o[2:0] - assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:494" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $4\fast_o[2:0] 3'000 - assign $4\fast_o_ok[0:0] 1'1 - case - assign $4\fast_o[2:0] $1\fast_o[2:0] - assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign { } { } - assign $3\fast_o[2:0] 3'011 - assign $3\fast_o_ok[0:0] 1'1 - case - assign $3\fast_o[2:0] $1\fast_o[2:0] - assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] - end - sync always - update \fast_o $0\fast_o[2:0] - update \fast_o_ok $0\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:130327$5114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$48 + connect \B \alu_div0_n_ready_i + connect \Y $and$libresoc.v:130327$5114_Y end - connect \$1 $eq$libresoc.v:131923$5029_Y - connect \$3 $eq$libresoc.v:131924$5030_Y - connect \$5 $eq$libresoc.v:131925$5031_Y - connect \$7 $not$libresoc.v:131926$5032_Y -end -attribute \src "libresoc.v:132051.1-132218.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" -attribute \generator "nMigen" -module \dec_o2 - attribute \src "libresoc.v:132178.3-132197.6" - wire width 3 $0\fast_o2[2:0] - attribute \src "libresoc.v:132198.3-132217.6" - wire $0\fast_o2_ok[0:0] - attribute \src "libresoc.v:132052.7-132052.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:132158.3-132167.6" - wire width 5 $0\reg_o2[4:0] - attribute \src "libresoc.v:132168.3-132177.6" - wire $0\reg_o2_ok[0:0] - attribute \src "libresoc.v:132178.3-132197.6" - wire width 3 $1\fast_o2[2:0] - attribute \src "libresoc.v:132198.3-132217.6" - wire $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:132158.3-132167.6" - wire width 5 $1\reg_o2[4:0] - attribute \src "libresoc.v:132168.3-132177.6" - wire $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:132178.3-132197.6" - wire width 3 $2\fast_o2[2:0] - attribute \src "libresoc.v:132198.3-132217.6" - wire $2\fast_o2_ok[0:0] - attribute \src "libresoc.v:132156.17-132156.108" - wire $eq$libresoc.v:132156$5040_Y - attribute \src "libresoc.v:132157.17-132157.108" - wire $eq$libresoc.v:132157$5041_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire width 5 input 7 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 4 \fast_o2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \fast_o2_ok - attribute \src "libresoc.v:132052.7-132052.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - wire input 1 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 2 \reg_o2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \reg_o2_ok - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - cell $eq $eq$libresoc.v:132156$5040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:130328$5115 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \upd - connect \B 2'01 - connect \Y $eq$libresoc.v:132156$5040_Y + connect \A \$50 + connect \B \alu_div0_n_valid_o + connect \Y $and$libresoc.v:130328$5115_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - cell $eq $eq$libresoc.v:132157$5041 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:130329$5116 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \upd - connect \B 2'01 - connect \Y $eq$libresoc.v:132157$5041_Y + connect \A \$52 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130329$5116_Y end - attribute \src "libresoc.v:132052.7-132052.20" - process $proc$libresoc.v:132052$5046 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:130335$5122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130335$5122_Y end - attribute \src "libresoc.v:132158.3-132167.6" - process $proc$libresoc.v:132158$5042 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:130336$5123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:130336$5123_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:130338$5125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130338$5125_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:130339$5126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130339$5126_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:130340$5127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130340$5127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:130341$5128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:130341$5128_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:130351$5138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:130351$5138_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:130352$5139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:130352$5139_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:130353$5140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:130353$5140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:130324$5111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$libresoc.v:130324$5111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:130326$5113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:130326$5113_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:130291$5078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__zero_a + connect \Y $not$libresoc.v:130291$5078_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:130292$5079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__imm_data__ok + connect \Y $not$libresoc.v:130292$5079_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:130294$5081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:130294$5081_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:130307$5094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:130307$5094_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:130309$5096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:130309$5096_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:130312$5099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:130312$5099_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:130315$5102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:130315$5102_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:130321$5108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_ready_i + connect \Y $not$libresoc.v:130321$5108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:130332$5119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:130332$5119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:130320$5107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:130320$5107_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:130330$5117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130330$5117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:130331$5118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:130331$5118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:130333$5120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:130333$5120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:130334$5121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:130334$5121_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:130337$5124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:130337$5124_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:130343$5130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:130343$5130_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:130348$5135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:130348$5135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:130314$5101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:130314$5101_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:130318$5105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:130318$5105_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:130319$5106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:130319$5106_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:130342$5129 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$libresoc.v:130342$5129_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:130344$5131 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$libresoc.v:130344$5131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:130345$5132 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:130345$5132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:130346$5133 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_div0_logical_op__imm_data__data + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:130346$5133_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:130347$5134 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:130347$5134_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:130349$5136 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$85 + connect \S \src_sel$82 + connect \Y $ternary$libresoc.v:130349$5136_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:130350$5137 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:130350$5137_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130442.12-130478.4" + cell \alu_div0 \alu_div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_div0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_div0_logical_op__data_len + connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_div0_logical_op__input_carry + connect \logical_op__insn \alu_div0_logical_op__insn + connect \logical_op__insn_type \alu_div0_logical_op__insn_type + connect \logical_op__invert_in \alu_div0_logical_op__invert_in + connect \logical_op__invert_out \alu_div0_logical_op__invert_out + connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit + connect \logical_op__is_signed \alu_div0_logical_op__is_signed + connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok + connect \logical_op__output_carry \alu_div0_logical_op__output_carry + connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_div0_logical_op__zero_a + connect \n_ready_i \alu_div0_n_ready_i + connect \n_valid_o \alu_div0_n_valid_o + connect \o \alu_div0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_div0_p_ready_o + connect \p_valid_i \alu_div0_p_valid_i + connect \ra \alu_div0_ra + connect \rb \alu_div0_rb + connect \xer_ov \alu_div0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_div0_xer_so + connect \xer_so$1 \alu_div0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130479.14-130485.4" + cell \alu_l$90 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130486.15-130492.4" + cell \alui_l$89 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130493.14-130499.4" + cell \opc_l$85 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130500.14-130506.4" + cell \req_l$86 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130507.14-130513.4" + cell \rok_l$88 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130514.14-130519.4" + cell \rst_l$87 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130520.14-130526.4" + cell \src_l$84 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:129644.7-129644.20" + process $proc$libresoc.v:129644$5313 assign { } { } - assign $0\reg_o2[4:0] $1\reg_o2[4:0] - attribute \src "libresoc.v:132159.5-132159.29" + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129774.7-129774.24" + process $proc$libresoc.v:129774$5314 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:129784.13-129784.49" + process $proc$libresoc.v:129784$5315 + assign { } { } + assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:129802.14-129802.53" + process $proc$libresoc.v:129802$5316 + assign { } { } + assign $1\alu_div0_logical_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:129806.14-129806.72" + process $proc$libresoc.v:129806$5317 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:129810.7-129810.47" + process $proc$libresoc.v:129810$5318 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:129818.13-129818.52" + process $proc$libresoc.v:129818$5319 + assign { } { } + assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:129822.14-129822.47" + process $proc$libresoc.v:129822$5320 + assign { } { } + assign $1\alu_div0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:129900.13-129900.51" + process $proc$libresoc.v:129900$5321 + assign { } { } + assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:129904.7-129904.44" + process $proc$libresoc.v:129904$5322 + assign { } { } + assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:129908.7-129908.45" + process $proc$libresoc.v:129908$5323 + assign { } { } + assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:129912.7-129912.43" + process $proc$libresoc.v:129912$5324 + assign { } { } + assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:129916.7-129916.44" + process $proc$libresoc.v:129916$5325 + assign { } { } + assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:129920.7-129920.41" + process $proc$libresoc.v:129920$5326 + assign { } { } + assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:129924.7-129924.41" + process $proc$libresoc.v:129924$5327 + assign { } { } + assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:129928.7-129928.47" + process $proc$libresoc.v:129928$5328 + assign { } { } + assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:129932.7-129932.41" + process $proc$libresoc.v:129932$5329 + assign { } { } + assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:129936.7-129936.41" + process $proc$libresoc.v:129936$5330 + assign { } { } + assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:129940.7-129940.44" + process $proc$libresoc.v:129940$5331 + assign { } { } + assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:129944.7-129944.41" + process $proc$libresoc.v:129944$5332 + assign { } { } + assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:129970.7-129970.26" + process $proc$libresoc.v:129970$5333 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:129978.7-129978.25" + process $proc$libresoc.v:129978$5334 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:129990.7-129990.27" + process $proc$libresoc.v:129990$5335 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:130024.14-130024.47" + process $proc$libresoc.v:130024$5336 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:130028.7-130028.27" + process $proc$libresoc.v:130028$5337 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:130032.13-130032.33" + process $proc$libresoc.v:130032$5338 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:130036.7-130036.30" + process $proc$libresoc.v:130036$5339 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:130040.13-130040.35" + process $proc$libresoc.v:130040$5340 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:130044.7-130044.32" + process $proc$libresoc.v:130044$5341 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:130048.7-130048.29" + process $proc$libresoc.v:130048$5342 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:130052.7-130052.32" + process $proc$libresoc.v:130052$5343 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:130072.7-130072.25" + process $proc$libresoc.v:130072$5344 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:130076.7-130076.25" + process $proc$libresoc.v:130076$5345 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:130208.13-130208.30" + process $proc$libresoc.v:130208$5346 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "libresoc.v:130216.13-130216.31" + process $proc$libresoc.v:130216$5347 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "libresoc.v:130220.13-130220.31" + process $proc$libresoc.v:130220$5348 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "libresoc.v:130232.7-130232.26" + process $proc$libresoc.v:130232$5349 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:130236.7-130236.26" + process $proc$libresoc.v:130236$5350 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:130240.7-130240.25" + process $proc$libresoc.v:130240$5351 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:130244.7-130244.25" + process $proc$libresoc.v:130244$5352 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:130258.13-130258.31" + process $proc$libresoc.v:130258$5353 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:130262.13-130262.31" + process $proc$libresoc.v:130262$5354 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:130270.14-130270.43" + process $proc$libresoc.v:130270$5355 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:130274.14-130274.43" + process $proc$libresoc.v:130274$5356 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:130278.7-130278.20" + process $proc$libresoc.v:130278$5357 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:130354.3-130355.39" + process $proc$libresoc.v:130354$5141 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:130356.3-130357.43" + process $proc$libresoc.v:130356$5142 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:130358.3-130359.29" + process $proc$libresoc.v:130358$5143 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:130360.3-130361.29" + process $proc$libresoc.v:130360$5144 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:130362.3-130363.29" + process $proc$libresoc.v:130362$5145 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:130364.3-130365.47" + process $proc$libresoc.v:130364$5146 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:130366.3-130367.53" + process $proc$libresoc.v:130366$5147 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:130368.3-130369.47" + process $proc$libresoc.v:130368$5148 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:130370.3-130371.53" + process $proc$libresoc.v:130370$5149 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:130372.3-130373.43" + process $proc$libresoc.v:130372$5150 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:130374.3-130375.49" + process $proc$libresoc.v:130374$5151 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:130376.3-130377.37" + process $proc$libresoc.v:130376$5152 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:130378.3-130379.43" + process $proc$libresoc.v:130378$5153 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:130380.3-130381.77" + process $proc$libresoc.v:130380$5154 + assign { } { } + assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:130382.3-130383.73" + process $proc$libresoc.v:130382$5155 + assign { } { } + assign $0\alu_div0_logical_op__fn_unit[12:0] \alu_div0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:130384.3-130385.87" + process $proc$libresoc.v:130384$5156 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:130386.3-130387.83" + process $proc$libresoc.v:130386$5157 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:130388.3-130389.71" + process $proc$libresoc.v:130388$5158 + assign { } { } + assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:130390.3-130391.71" + process $proc$libresoc.v:130390$5159 + assign { } { } + assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:130392.3-130393.71" + process $proc$libresoc.v:130392$5160 + assign { } { } + assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:130394.3-130395.71" + process $proc$libresoc.v:130394$5161 + assign { } { } + assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:130396.3-130397.77" + process $proc$libresoc.v:130396$5162 + assign { } { } + assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:130398.3-130399.71" + process $proc$libresoc.v:130398$5163 + assign { } { } + assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:130400.3-130401.81" + process $proc$libresoc.v:130400$5164 + assign { } { } + assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:130402.3-130403.79" + process $proc$libresoc.v:130402$5165 + assign { } { } + assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:130404.3-130405.77" + process $proc$libresoc.v:130404$5166 + assign { } { } + assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:130406.3-130407.83" + process $proc$libresoc.v:130406$5167 + assign { } { } + assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:130408.3-130409.75" + process $proc$libresoc.v:130408$5168 + assign { } { } + assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:130410.3-130411.77" + process $proc$libresoc.v:130410$5169 + assign { } { } + assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:130412.3-130413.75" + process $proc$libresoc.v:130412$5170 + assign { } { } + assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:130414.3-130415.67" + process $proc$libresoc.v:130414$5171 + assign { } { } + assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:130416.3-130417.39" + process $proc$libresoc.v:130416$5172 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "libresoc.v:130418.3-130419.39" + process $proc$libresoc.v:130418$5173 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "libresoc.v:130420.3-130421.39" + process $proc$libresoc.v:130420$5174 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:130422.3-130423.39" + process $proc$libresoc.v:130422$5175 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:130424.3-130425.39" + process $proc$libresoc.v:130424$5176 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:130426.3-130427.39" + process $proc$libresoc.v:130426$5177 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:130428.3-130429.39" + process $proc$libresoc.v:130428$5178 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:130430.3-130431.39" + process $proc$libresoc.v:130430$5179 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:130432.3-130433.41" + process $proc$libresoc.v:130432$5180 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:130434.3-130435.41" + process $proc$libresoc.v:130434$5181 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:130436.3-130437.37" + process $proc$libresoc.v:130436$5182 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "libresoc.v:130438.3-130439.40" + process $proc$libresoc.v:130438$5183 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:130440.3-130441.25" + process $proc$libresoc.v:130440$5184 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:130527.3-130536.6" + process $proc$libresoc.v:130527$5185 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:130528.5-130528.29" switch \initial - attribute \src "libresoc.v:132159.9-132159.17" + attribute \src "libresoc.v:130528.9-130528.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - switch \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg_o2[4:0] \RA + assign $1\req_done[0:0] 1'1 case - assign $1\reg_o2[4:0] 5'00000 + assign $1\req_done[0:0] \$46 end sync always - update \reg_o2 $0\reg_o2[4:0] + update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:132168.3-132177.6" - process $proc$libresoc.v:132168$5043 + attribute \src "libresoc.v:130537.3-130545.6" + process $proc$libresoc.v:130537$5186 assign { } { } assign { } { } - assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:132169.5-132169.29" + assign $0\rok_l_s_rdok$next[0:0]$5187 $1\rok_l_s_rdok$next[0:0]$5188 + attribute \src "libresoc.v:130538.5-130538.29" switch \initial - attribute \src "libresoc.v:132169.9-132169.17" + attribute \src "libresoc.v:130538.9-130538.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - switch \$3 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg_o2_ok[0:0] 1'1 + assign $1\rok_l_s_rdok$next[0:0]$5188 1'0 case - assign $1\reg_o2_ok[0:0] 1'0 + assign $1\rok_l_s_rdok$next[0:0]$5188 \cu_issue_i end sync always - update \reg_o2_ok $0\reg_o2_ok[0:0] + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5187 end - attribute \src "libresoc.v:132178.3-132197.6" - process $proc$libresoc.v:132178$5044 + attribute \src "libresoc.v:130546.3-130554.6" + process $proc$libresoc.v:130546$5189 assign { } { } assign { } { } - assign $0\fast_o2[2:0] $1\fast_o2[2:0] - attribute \src "libresoc.v:132179.5-132179.29" + assign $0\rok_l_r_rdok$next[0:0]$5190 $1\rok_l_r_rdok$next[0:0]$5191 + attribute \src "libresoc.v:130547.5-130547.29" switch \initial - attribute \src "libresoc.v:132179.9-132179.17" + attribute \src "libresoc.v:130547.9-130547.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:546" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0000110 , 7'0001000 - assign { } { } - assign $1\fast_o2[2:0] $2\fast_o2[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - switch \lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast_o2[2:0] 3'001 - case - assign $2\fast_o2[2:0] 3'000 - end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 + case 1'1 assign { } { } - assign $1\fast_o2[2:0] 3'100 + assign $1\rok_l_r_rdok$next[0:0]$5191 1'1 case - assign $1\fast_o2[2:0] 3'000 + assign $1\rok_l_r_rdok$next[0:0]$5191 \$64 end sync always - update \fast_o2 $0\fast_o2[2:0] + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5190 end - attribute \src "libresoc.v:132198.3-132217.6" - process $proc$libresoc.v:132198$5045 + attribute \src "libresoc.v:130555.3-130563.6" + process $proc$libresoc.v:130555$5192 assign { } { } assign { } { } - assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:132199.5-132199.29" + assign $0\rst_l_s_rst$next[0:0]$5193 $1\rst_l_s_rst$next[0:0]$5194 + attribute \src "libresoc.v:130556.5-130556.29" switch \initial - attribute \src "libresoc.v:132199.9-132199.17" + attribute \src "libresoc.v:130556.9-130556.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:546" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0000110 , 7'0001000 - assign { } { } - assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - switch \lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast_o2_ok[0:0] 1'1 - case - assign $2\fast_o2_ok[0:0] 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 + case 1'1 assign { } { } - assign $1\fast_o2_ok[0:0] 1'1 + assign $1\rst_l_s_rst$next[0:0]$5194 1'0 case - assign $1\fast_o2_ok[0:0] 1'0 + assign $1\rst_l_s_rst$next[0:0]$5194 \all_rd end sync always - update \fast_o2_ok $0\fast_o2_ok[0:0] - end - connect \$1 $eq$libresoc.v:132156$5040_Y - connect \$3 $eq$libresoc.v:132157$5041_Y -end -attribute \src "libresoc.v:132222.1-132356.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" -attribute \generator "nMigen" -module \dec_oe - attribute \src "libresoc.v:132223.7-132223.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:132314.3-132334.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:132335.3-132355.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:132314.3-132334.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:132335.3-132355.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:132314.3-132334.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:132335.3-132355.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 4 \ALU_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 1 \ALU_internal_op - attribute \src "libresoc.v:132223.7-132223.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:132223.7-132223.20" - process $proc$libresoc.v:132223$5049 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5193 end - attribute \src "libresoc.v:132314.3-132334.6" - process $proc$libresoc.v:132314$5047 + attribute \src "libresoc.v:130564.3-130572.6" + process $proc$libresoc.v:130564$5195 assign { } { } assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:132315.5-132315.29" + assign $0\rst_l_r_rst$next[0:0]$5196 $1\rst_l_r_rst$next[0:0]$5197 + attribute \src "libresoc.v:130565.5-130565.29" switch \initial - attribute \src "libresoc.v:132315.9-132315.17" + attribute \src "libresoc.v:130565.9-130565.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$5197 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$5197 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5196 + end + attribute \src "libresoc.v:130573.3-130581.6" + process $proc$libresoc.v:130573$5198 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$5199 $1\opc_l_s_opc$next[0:0]$5200 + attribute \src "libresoc.v:130574.5-130574.29" + switch \initial + attribute \src "libresoc.v:130574.9-130574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$5200 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$5200 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5199 + end + attribute \src "libresoc.v:130582.3-130590.6" + process $proc$libresoc.v:130582$5201 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$5202 $1\opc_l_r_opc$next[0:0]$5203 + attribute \src "libresoc.v:130583.5-130583.29" + switch \initial + attribute \src "libresoc.v:130583.9-130583.17" + case 1'1 case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \ALU_OE - case - assign $2\oe[0:0] 1'0 - end + assign $1\opc_l_r_opc$next[0:0]$5203 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$5203 \req_done end sync always - update \oe $0\oe[0:0] + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5202 end - attribute \src "libresoc.v:132335.3-132355.6" - process $proc$libresoc.v:132335$5048 + attribute \src "libresoc.v:130591.3-130599.6" + process $proc$libresoc.v:130591$5204 assign { } { } assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:132336.5-132336.29" + assign $0\src_l_s_src$next[2:0]$5205 $1\src_l_s_src$next[2:0]$5206 + attribute \src "libresoc.v:130592.5-130592.29" switch \initial - attribute \src "libresoc.v:132336.9-132336.17" + attribute \src "libresoc.v:130592.9-130592.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$5206 3'000 + case + assign $1\src_l_s_src$next[2:0]$5206 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5205 + end + attribute \src "libresoc.v:130600.3-130608.6" + process $proc$libresoc.v:130600$5207 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$5208 $1\src_l_r_src$next[2:0]$5209 + attribute \src "libresoc.v:130601.5-130601.29" + switch \initial + attribute \src "libresoc.v:130601.9-130601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$5209 3'111 + case + assign $1\src_l_r_src$next[2:0]$5209 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5208 + end + attribute \src "libresoc.v:130609.3-130617.6" + process $proc$libresoc.v:130609$5210 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[3:0]$5211 $1\req_l_s_req$next[3:0]$5212 + attribute \src "libresoc.v:130610.5-130610.29" + switch \initial + attribute \src "libresoc.v:130610.9-130610.17" + case 1'1 case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end + assign $1\req_l_s_req$next[3:0]$5212 4'0000 + case + assign $1\req_l_s_req$next[3:0]$5212 \$66 end sync always - update \oe_ok $0\oe_ok[0:0] + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5211 + end + attribute \src "libresoc.v:130618.3-130626.6" + process $proc$libresoc.v:130618$5213 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$5214 $1\req_l_r_req$next[3:0]$5215 + attribute \src "libresoc.v:130619.5-130619.29" + switch \initial + attribute \src "libresoc.v:130619.9-130619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[3:0]$5215 4'1111 + case + assign $1\req_l_r_req$next[3:0]$5215 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5214 + end + attribute \src "libresoc.v:130627.3-130665.6" + process $proc$libresoc.v:130627$5216 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__data_len$next[3:0]$5217 $1\alu_div0_logical_op__data_len$next[3:0]$5235 + assign $0\alu_div0_logical_op__fn_unit$next[12:0]$5218 $1\alu_div0_logical_op__fn_unit$next[12:0]$5236 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__input_carry$next[1:0]$5221 $1\alu_div0_logical_op__input_carry$next[1:0]$5239 + assign $0\alu_div0_logical_op__insn$next[31:0]$5222 $1\alu_div0_logical_op__insn$next[31:0]$5240 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$5223 $1\alu_div0_logical_op__insn_type$next[6:0]$5241 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$5224 $1\alu_div0_logical_op__invert_in$next[0:0]$5242 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$5225 $1\alu_div0_logical_op__invert_out$next[0:0]$5243 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5226 $1\alu_div0_logical_op__is_32bit$next[0:0]$5244 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$5227 $1\alu_div0_logical_op__is_signed$next[0:0]$5245 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__output_carry$next[0:0]$5230 $1\alu_div0_logical_op__output_carry$next[0:0]$5248 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5233 $1\alu_div0_logical_op__write_cr0$next[0:0]$5251 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$5234 $1\alu_div0_logical_op__zero_a$next[0:0]$5252 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5219 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5253 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5220 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5254 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5228 $2\alu_div0_logical_op__oe__oe$next[0:0]$5255 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5229 $2\alu_div0_logical_op__oe__ok$next[0:0]$5256 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5231 $2\alu_div0_logical_op__rc__ok$next[0:0]$5257 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5232 $2\alu_div0_logical_op__rc__rc$next[0:0]$5258 + attribute \src "libresoc.v:130628.5-130628.29" + switch \initial + attribute \src "libresoc.v:130628.9-130628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_div0_logical_op__insn$next[31:0]$5240 $1\alu_div0_logical_op__data_len$next[3:0]$5235 $1\alu_div0_logical_op__is_signed$next[0:0]$5245 $1\alu_div0_logical_op__is_32bit$next[0:0]$5244 $1\alu_div0_logical_op__output_carry$next[0:0]$5248 $1\alu_div0_logical_op__write_cr0$next[0:0]$5251 $1\alu_div0_logical_op__invert_out$next[0:0]$5243 $1\alu_div0_logical_op__input_carry$next[1:0]$5239 $1\alu_div0_logical_op__zero_a$next[0:0]$5252 $1\alu_div0_logical_op__invert_in$next[0:0]$5242 $1\alu_div0_logical_op__oe__ok$next[0:0]$5247 $1\alu_div0_logical_op__oe__oe$next[0:0]$5246 $1\alu_div0_logical_op__rc__ok$next[0:0]$5249 $1\alu_div0_logical_op__rc__rc$next[0:0]$5250 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5238 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5237 $1\alu_div0_logical_op__fn_unit$next[12:0]$5236 $1\alu_div0_logical_op__insn_type$next[6:0]$5241 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + case + assign $1\alu_div0_logical_op__data_len$next[3:0]$5235 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[12:0]$5236 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5237 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5238 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$5239 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$5240 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$5241 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$5242 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$5243 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5244 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$5245 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5246 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5247 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$5248 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5249 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5250 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5251 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$5252 \alu_div0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5253 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5254 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5258 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5257 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5255 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5256 1'0 + case + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5253 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5237 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5254 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5238 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5255 $1\alu_div0_logical_op__oe__oe$next[0:0]$5246 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5256 $1\alu_div0_logical_op__oe__ok$next[0:0]$5247 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5257 $1\alu_div0_logical_op__rc__ok$next[0:0]$5249 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5258 $1\alu_div0_logical_op__rc__rc$next[0:0]$5250 + end + sync always + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5217 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[12:0]$5218 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5219 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5220 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5221 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5222 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5223 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5224 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5225 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5226 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5227 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5228 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5229 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5230 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5231 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5232 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5233 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5234 + end + attribute \src "libresoc.v:130666.3-130687.6" + process $proc$libresoc.v:130666$5259 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$5260 $2\data_r0__o$next[63:0]$5264 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$5261 $3\data_r0__o_ok$next[0:0]$5266 + attribute \src "libresoc.v:130667.5-130667.29" + switch \initial + attribute \src "libresoc.v:130667.9-130667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$5263 $1\data_r0__o$next[63:0]$5262 } { \o_ok \alu_div0_o } + case + assign $1\data_r0__o$next[63:0]$5262 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$5263 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$5265 $2\data_r0__o$next[63:0]$5264 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$5264 $1\data_r0__o$next[63:0]$5262 + assign $2\data_r0__o_ok$next[0:0]$5265 $1\data_r0__o_ok$next[0:0]$5263 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$5266 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$5266 $2\data_r0__o_ok$next[0:0]$5265 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$5260 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5261 + end + attribute \src "libresoc.v:130688.3-130709.6" + process $proc$libresoc.v:130688$5267 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$5268 $2\data_r1__cr_a$next[3:0]$5272 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$5269 $3\data_r1__cr_a_ok$next[0:0]$5274 + attribute \src "libresoc.v:130689.5-130689.29" + switch \initial + attribute \src "libresoc.v:130689.9-130689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$5271 $1\data_r1__cr_a$next[3:0]$5270 } { \cr_a_ok \alu_div0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$5270 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$5271 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$5273 $2\data_r1__cr_a$next[3:0]$5272 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$5272 $1\data_r1__cr_a$next[3:0]$5270 + assign $2\data_r1__cr_a_ok$next[0:0]$5273 $1\data_r1__cr_a_ok$next[0:0]$5271 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$5274 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$5274 $2\data_r1__cr_a_ok$next[0:0]$5273 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5268 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5269 + end + attribute \src "libresoc.v:130710.3-130731.6" + process $proc$libresoc.v:130710$5275 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$5276 $2\data_r2__xer_ov$next[1:0]$5280 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$5277 $3\data_r2__xer_ov_ok$next[0:0]$5282 + attribute \src "libresoc.v:130711.5-130711.29" + switch \initial + attribute \src "libresoc.v:130711.9-130711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ov_ok$next[0:0]$5279 $1\data_r2__xer_ov$next[1:0]$5278 } { \xer_ov_ok \alu_div0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$5278 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$5279 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ov_ok$next[0:0]$5281 $2\data_r2__xer_ov$next[1:0]$5280 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$5280 $1\data_r2__xer_ov$next[1:0]$5278 + assign $2\data_r2__xer_ov_ok$next[0:0]$5281 $1\data_r2__xer_ov_ok$next[0:0]$5279 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ov_ok$next[0:0]$5282 1'0 + case + assign $3\data_r2__xer_ov_ok$next[0:0]$5282 $2\data_r2__xer_ov_ok$next[0:0]$5281 + end + sync always + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5276 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5277 + end + attribute \src "libresoc.v:130732.3-130753.6" + process $proc$libresoc.v:130732$5283 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$5284 $2\data_r3__xer_so$next[0:0]$5288 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$5285 $3\data_r3__xer_so_ok$next[0:0]$5290 + attribute \src "libresoc.v:130733.5-130733.29" + switch \initial + attribute \src "libresoc.v:130733.9-130733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$5287 $1\data_r3__xer_so$next[0:0]$5286 } { \xer_so_ok \alu_div0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$5286 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$5287 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$5289 $2\data_r3__xer_so$next[0:0]$5288 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$5288 $1\data_r3__xer_so$next[0:0]$5286 + assign $2\data_r3__xer_so_ok$next[0:0]$5289 $1\data_r3__xer_so_ok$next[0:0]$5287 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$5290 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$5290 $2\data_r3__xer_so_ok$next[0:0]$5289 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5284 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5285 + end + attribute \src "libresoc.v:130754.3-130763.6" + process $proc$libresoc.v:130754$5291 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$5292 $1\src_r0$next[63:0]$5293 + attribute \src "libresoc.v:130755.5-130755.29" + switch \initial + attribute \src "libresoc.v:130755.9-130755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$5293 \src_or_imm + case + assign $1\src_r0$next[63:0]$5293 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$5292 + end + attribute \src "libresoc.v:130764.3-130773.6" + process $proc$libresoc.v:130764$5294 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$5295 $1\src_r1$next[63:0]$5296 + attribute \src "libresoc.v:130765.5-130765.29" + switch \initial + attribute \src "libresoc.v:130765.9-130765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel$82 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$5296 \src_or_imm$85 + case + assign $1\src_r1$next[63:0]$5296 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$5295 + end + attribute \src "libresoc.v:130774.3-130783.6" + process $proc$libresoc.v:130774$5297 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$5298 $1\src_r2$next[0:0]$5299 + attribute \src "libresoc.v:130775.5-130775.29" + switch \initial + attribute \src "libresoc.v:130775.9-130775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$5299 \src3_i + case + assign $1\src_r2$next[0:0]$5299 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$5298 + end + attribute \src "libresoc.v:130784.3-130792.6" + process $proc$libresoc.v:130784$5300 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$5301 $1\alui_l_r_alui$next[0:0]$5302 + attribute \src "libresoc.v:130785.5-130785.29" + switch \initial + attribute \src "libresoc.v:130785.9-130785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$5302 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$5302 \$94 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5301 + end + attribute \src "libresoc.v:130793.3-130801.6" + process $proc$libresoc.v:130793$5303 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$5304 $1\alu_l_r_alu$next[0:0]$5305 + attribute \src "libresoc.v:130794.5-130794.29" + switch \initial + attribute \src "libresoc.v:130794.9-130794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$5305 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$5305 \$96 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5304 + end + attribute \src "libresoc.v:130802.3-130811.6" + process $proc$libresoc.v:130802$5306 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:130803.5-130803.29" + switch \initial + attribute \src "libresoc.v:130803.9-130803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$122 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:130812.3-130821.6" + process $proc$libresoc.v:130812$5307 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:130813.5-130813.29" + switch \initial + attribute \src "libresoc.v:130813.9-130813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$124 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:130822.3-130831.6" + process $proc$libresoc.v:130822$5308 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:130823.5-130823.29" + switch \initial + attribute \src "libresoc.v:130823.9-130823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$126 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ov + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:130832.3-130841.6" + process $proc$libresoc.v:130832$5309 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:130833.5-130833.29" + switch \initial + attribute \src "libresoc.v:130833.9-130833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$128 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] end + attribute \src "libresoc.v:130842.3-130850.6" + process $proc$libresoc.v:130842$5310 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[3:0]$5311 $1\prev_wr_go$next[3:0]$5312 + attribute \src "libresoc.v:130843.5-130843.29" + switch \initial + attribute \src "libresoc.v:130843.9-130843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[3:0]$5312 4'0000 + case + assign $1\prev_wr_go$next[3:0]$5312 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5311 + end + connect \$100 $not$libresoc.v:130291$5078_Y + connect \$102 $not$libresoc.v:130292$5079_Y + connect \$104 $and$libresoc.v:130293$5080_Y + connect \$106 $not$libresoc.v:130294$5081_Y + connect \$108 $and$libresoc.v:130295$5082_Y + connect \$10 $and$libresoc.v:130296$5083_Y + connect \$110 $and$libresoc.v:130297$5084_Y + connect \$112 $and$libresoc.v:130298$5085_Y + connect \$114 $and$libresoc.v:130299$5086_Y + connect \$116 $and$libresoc.v:130300$5087_Y + connect \$118 $and$libresoc.v:130301$5088_Y + connect \$120 $and$libresoc.v:130302$5089_Y + connect \$122 $and$libresoc.v:130303$5090_Y + connect \$124 $and$libresoc.v:130304$5091_Y + connect \$126 $and$libresoc.v:130305$5092_Y + connect \$128 $and$libresoc.v:130306$5093_Y + connect \$12 $not$libresoc.v:130307$5094_Y + connect \$14 $and$libresoc.v:130308$5095_Y + connect \$16 $not$libresoc.v:130309$5096_Y + connect \$18 $and$libresoc.v:130310$5097_Y + connect \$20 $and$libresoc.v:130311$5098_Y + connect \$24 $not$libresoc.v:130312$5099_Y + connect \$26 $and$libresoc.v:130313$5100_Y + connect \$23 $reduce_or$libresoc.v:130314$5101_Y + connect \$22 $not$libresoc.v:130315$5102_Y + connect \$2 $and$libresoc.v:130316$5103_Y + connect \$30 $and$libresoc.v:130317$5104_Y + connect \$32 $reduce_or$libresoc.v:130318$5105_Y + connect \$34 $reduce_or$libresoc.v:130319$5106_Y + connect \$36 $or$libresoc.v:130320$5107_Y + connect \$38 $not$libresoc.v:130321$5108_Y + connect \$40 $and$libresoc.v:130322$5109_Y + connect \$42 $and$libresoc.v:130323$5110_Y + connect \$44 $eq$libresoc.v:130324$5111_Y + connect \$46 $and$libresoc.v:130325$5112_Y + connect \$48 $eq$libresoc.v:130326$5113_Y + connect \$50 $and$libresoc.v:130327$5114_Y + connect \$52 $and$libresoc.v:130328$5115_Y + connect \$54 $and$libresoc.v:130329$5116_Y + connect \$56 $or$libresoc.v:130330$5117_Y + connect \$58 $or$libresoc.v:130331$5118_Y + connect \$5 $not$libresoc.v:130332$5119_Y + connect \$60 $or$libresoc.v:130333$5120_Y + connect \$62 $or$libresoc.v:130334$5121_Y + connect \$64 $and$libresoc.v:130335$5122_Y + connect \$66 $and$libresoc.v:130336$5123_Y + connect \$68 $or$libresoc.v:130337$5124_Y + connect \$70 $and$libresoc.v:130338$5125_Y + connect \$72 $and$libresoc.v:130339$5126_Y + connect \$74 $and$libresoc.v:130340$5127_Y + connect \$76 $and$libresoc.v:130341$5128_Y + connect \$78 $ternary$libresoc.v:130342$5129_Y + connect \$7 $or$libresoc.v:130343$5130_Y + connect \$80 $ternary$libresoc.v:130344$5131_Y + connect \$83 $ternary$libresoc.v:130345$5132_Y + connect \$86 $ternary$libresoc.v:130346$5133_Y + connect \$88 $ternary$libresoc.v:130347$5134_Y + connect \$4 $reduce_and$libresoc.v:130348$5135_Y + connect \$90 $ternary$libresoc.v:130349$5136_Y + connect \$92 $ternary$libresoc.v:130350$5137_Y + connect \$94 $and$libresoc.v:130351$5138_Y + connect \$96 $and$libresoc.v:130352$5139_Y + connect \$98 $and$libresoc.v:130353$5140_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$120 + connect \cu_rd__rel_o \$108 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_div0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_div0_p_valid_i \alui_l_q_alui + connect \alu_div0_xer_so$1 \$92 + connect \alu_div0_rb \$90 + connect \alu_div0_ra \$88 + connect \src_or_imm$85 \$86 + connect \src_sel$82 \$83 + connect \src_or_imm \$80 + connect \src_sel \$78 + connect \cu_wrmask_o { \$76 \$74 \$72 \$70 } + connect \reset_r \$62 + connect \reset_w \$60 + connect \rst_r \$58 + connect \reset \$56 + connect \wr_any \$36 + connect \cu_done_o \$30 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$18 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_div0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$14 + connect \all_rd_dly$next \all_rd + connect \all_rd \$10 end -attribute \src "libresoc.v:132360.1-132492.10" +attribute \src "libresoc.v:130887.1-130896.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" +attribute \generator "nMigen" +module \div_state_init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 input 3 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 output 2 \o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 output 1 \o_q_bits_known + connect \o_dividend_quotient \dividend + connect \o_q_bits_known 7'0000000 +end +attribute \src "libresoc.v:130900.1-130982.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" attribute \generator "nMigen" -module \dec_oe$141 - attribute \src "libresoc.v:132361.7-132361.20" +module \div_state_next + attribute \src "libresoc.v:130901.7-130901.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132450.3-132470.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:132471.3-132491.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:132450.3-132470.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:132471.3-132491.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:132450.3-132470.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:132471.3-132491.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 2 \CR_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 1 \CR_internal_op - attribute \src "libresoc.v:132361.7-132361.15" + attribute \src "libresoc.v:130966.3-130977.6" + wire width 128 $0\o_dividend_quotient[127:0] + attribute \src "libresoc.v:130954.3-130965.6" + wire width 7 $0\o_q_bits_known[6:0] + attribute \src "libresoc.v:130942.3-130953.6" + wire width 128 $0\value[127:0] + attribute \src "libresoc.v:130966.3-130977.6" + wire width 128 $1\o_dividend_quotient[127:0] + attribute \src "libresoc.v:130954.3-130965.6" + wire width 7 $1\o_q_bits_known[6:0] + attribute \src "libresoc.v:130942.3-130953.6" + wire width 128 $1\value[127:0] + attribute \src "libresoc.v:130936.18-130936.106" + wire width 8 $add$libresoc.v:130936$5358_Y + attribute \src "libresoc.v:130937.18-130937.109" + wire $ge$libresoc.v:130937$5359_Y + attribute \src "libresoc.v:130941.17-130941.108" + wire $ge$libresoc.v:130941$5363_Y + attribute \src "libresoc.v:130940.17-130940.101" + wire $not$libresoc.v:130940$5362_Y + attribute \src "libresoc.v:130938.17-130938.101" + wire width 127 $sshl$libresoc.v:130938$5360_Y + attribute \src "libresoc.v:130939.17-130939.109" + wire width 129 $sub$libresoc.v:130939$5361_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + wire width 129 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" + wire width 8 \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" + wire width 8 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + wire width 127 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + wire width 129 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:64" + wire width 128 \difference + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" + wire width 64 input 4 \divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 input 3 \i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 input 2 \i_q_bits_known + attribute \src "libresoc.v:130901.7-130901.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:132361.7-132361.20" - process $proc$libresoc.v:132361$5052 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" + wire \next_quotient_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 output 5 \o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 output 1 \o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" + wire width 128 \value + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" + cell $add $add$libresoc.v:130936$5358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \i_q_bits_known + connect \B 1'1 + connect \Y $add$libresoc.v:130936$5358_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:130937$5359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $ge$libresoc.v:130937$5359_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:130941$5363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $ge$libresoc.v:130941$5363_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" + cell $not $not$libresoc.v:130940$5362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \difference [127] + connect \Y $not$libresoc.v:130940$5362_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + cell $sshl $sshl$libresoc.v:130938$5360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 127 + connect \A \divisor + connect \B 6'111111 + connect \Y $sshl$libresoc.v:130938$5360_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + cell $sub $sub$libresoc.v:130939$5361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 127 + parameter \Y_WIDTH 129 + connect \A \i_dividend_quotient + connect \B \$2 + connect \Y $sub$libresoc.v:130939$5361_Y + end + attribute \src "libresoc.v:130901.7-130901.20" + process $proc$libresoc.v:130901$5367 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132450.3-132470.6" - process $proc$libresoc.v:132450$5050 + attribute \src "libresoc.v:130942.3-130953.6" + process $proc$libresoc.v:130942$5364 assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:132451.5-132451.29" + assign $0\value[127:0] $1\value[127:0] + attribute \src "libresoc.v:130943.5-130943.29" switch \initial - attribute \src "libresoc.v:132451.9-132451.17" + attribute \src "libresoc.v:130943.9-130943.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" + switch \next_quotient_bit attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 + case 1'1 + assign { } { } + assign $1\value[127:0] \difference attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \CR_OE - case - assign $2\oe[0:0] 1'0 - end + assign $1\value[127:0] \i_dividend_quotient end sync always - update \oe $0\oe[0:0] + update \value $0\value[127:0] end - attribute \src "libresoc.v:132471.3-132491.6" - process $proc$libresoc.v:132471$5051 + attribute \src "libresoc.v:130954.3-130965.6" + process $proc$libresoc.v:130954$5365 assign { } { } + assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] + attribute \src "libresoc.v:130955.5-130955.29" + switch \initial + attribute \src "libresoc.v:130955.9-130955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + switch \$8 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o_q_bits_known[6:0] \i_q_bits_known + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o_q_bits_known[6:0] \$10 [6:0] + end + sync always + update \o_q_bits_known $0\o_q_bits_known[6:0] + end + attribute \src "libresoc.v:130966.3-130977.6" + process $proc$libresoc.v:130966$5366 assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:132472.5-132472.29" + assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] + attribute \src "libresoc.v:130967.5-130967.29" switch \initial - attribute \src "libresoc.v:132472.9-132472.17" + attribute \src "libresoc.v:130967.9-130967.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + switch \$13 attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 + case 1'1 + assign { } { } + assign $1\o_dividend_quotient[127:0] \i_dividend_quotient attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end + assign $1\o_dividend_quotient[127:0] { \value [126:0] \next_quotient_bit } end sync always - update \oe_ok $0\oe_ok[0:0] + update \o_dividend_quotient $0\o_dividend_quotient[127:0] end + connect \$11 $add$libresoc.v:130936$5358_Y + connect \$13 $ge$libresoc.v:130937$5359_Y + connect \$2 $sshl$libresoc.v:130938$5360_Y + connect \$4 $sub$libresoc.v:130939$5361_Y + connect \$6 $not$libresoc.v:130940$5362_Y + connect \$8 $ge$libresoc.v:130941$5363_Y + connect \$1 \$4 + connect \$10 \$11 + connect \next_quotient_bit \$6 + connect \difference \$4 [127:0] end -attribute \src "libresoc.v:132496.1-132628.10" +attribute \src "libresoc.v:130986.1-131225.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" attribute \generator "nMigen" -module \dec_oe$148 - attribute \src "libresoc.v:132497.7-132497.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:132586.3-132606.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:132607.3-132627.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:132586.3-132606.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:132607.3-132627.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:132586.3-132606.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:132607.3-132627.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 2 \BRANCH_OE +module \dummy + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 12 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 26 \fast1$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 27 \fast2$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 28 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 14 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 24 \ra$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 25 \rb$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \trap_op__cia$6 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 16 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \trap_op__insn$4 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -207609,116 +208252,8 @@ module \dec_oe$148 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 1 \BRANCH_internal_op - attribute \src "libresoc.v:132497.7-132497.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:132497.7-132497.20" - process $proc$libresoc.v:132497$5055 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:132586.3-132606.6" - process $proc$libresoc.v:132586$5053 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:132587.5-132587.29" - switch \initial - attribute \src "libresoc.v:132587.9-132587.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \BRANCH_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \BRANCH_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:132607.3-132627.6" - process $proc$libresoc.v:132607$5054 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:132608.5-132608.29" - switch \initial - attribute \src "libresoc.v:132608.9-132608.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \BRANCH_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:132632.1-132766.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" -attribute \generator "nMigen" -module \dec_oe$156 - attribute \src "libresoc.v:132633.7-132633.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:132724.3-132744.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:132745.3-132765.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:132724.3-132744.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:132745.3-132765.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:132724.3-132744.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:132745.3-132765.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 4 \LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -207793,116 +208328,942 @@ module \dec_oe$156 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 1 \LOGICAL_internal_op - attribute \src "libresoc.v:132633.7-132633.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 15 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 9 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 23 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 18 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 22 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 21 \trap_op__traptype$8 + connect \fast2$14 \fast2 + connect \fast1$13 \fast1 + connect \rb$12 \rb + connect \ra$11 \ra + connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \muxid$1 \muxid +end +attribute \src "libresoc.v:131229.1-131400.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fast" +attribute \generator "nMigen" +module \fast + attribute \src "libresoc.v:131324.3-131330.6" + wire width 3 $0$memwr$\memory$libresoc.v:131328$5376_ADDR[2:0]$5384 + attribute \src "libresoc.v:131324.3-131330.6" + wire width 64 $0$memwr$\memory$libresoc.v:131328$5376_DATA[63:0]$5385 + attribute \src "libresoc.v:131324.3-131330.6" + wire width 64 $0$memwr$\memory$libresoc.v:131328$5376_EN[63:0]$5386 + attribute \src "libresoc.v:131324.3-131330.6" + wire width 3 $0$memwr$\memory$libresoc.v:131329$5377_ADDR[2:0]$5387 + attribute \src "libresoc.v:131324.3-131330.6" + wire width 64 $0$memwr$\memory$libresoc.v:131329$5377_DATA[63:0]$5388 + attribute \src "libresoc.v:131324.3-131330.6" + wire width 64 $0$memwr$\memory$libresoc.v:131329$5377_EN[63:0]$5389 + attribute \src "libresoc.v:131324.3-131330.6" + wire width 3 $0\_0_[2:0] + attribute \src "libresoc.v:131324.3-131330.6" + wire width 3 $0\_1_[2:0] + attribute \src "libresoc.v:131324.3-131330.6" + wire width 3 $0\_2_[2:0] + attribute \src "libresoc.v:131230.7-131230.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131381.3-131390.6" + wire width 64 $0\issue__data_o[63:0] + attribute \src "libresoc.v:131353.3-131361.6" + wire $0\ren_delay$10$next[0:0]$5398 + attribute \src "libresoc.v:131306.3-131307.43" + wire $0\ren_delay$10[0:0]$5381 + attribute \src "libresoc.v:131281.7-131281.28" + wire $0\ren_delay$10[0:0]$5418 + attribute \src "libresoc.v:131372.3-131380.6" + wire $0\ren_delay$11$next[0:0]$5402 + attribute \src "libresoc.v:131304.3-131305.43" + wire $0\ren_delay$11[0:0]$5379 + attribute \src "libresoc.v:131285.7-131285.28" + wire $0\ren_delay$11[0:0]$5420 + attribute \src "libresoc.v:131334.3-131342.6" + wire $0\ren_delay$next[0:0]$5394 + attribute \src "libresoc.v:131308.3-131309.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:131343.3-131352.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "libresoc.v:131362.3-131371.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "libresoc.v:131381.3-131390.6" + wire width 64 $1\issue__data_o[63:0] + attribute \src "libresoc.v:131353.3-131361.6" + wire $1\ren_delay$10$next[0:0]$5399 + attribute \src "libresoc.v:131372.3-131380.6" + wire $1\ren_delay$11$next[0:0]$5403 + attribute \src "libresoc.v:131334.3-131342.6" + wire $1\ren_delay$next[0:0]$5395 + attribute \src "libresoc.v:131279.7-131279.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:131343.3-131352.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "libresoc.v:131362.3-131371.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "libresoc.v:131331.26-131331.32" + wire width 64 $memrd$\memory$libresoc.v:131331$5390_DATA + attribute \src "libresoc.v:131332.30-131332.36" + wire width 64 $memrd$\memory$libresoc.v:131332$5391_DATA + attribute \src "libresoc.v:131333.30-131333.36" + wire width 64 $memrd$\memory$libresoc.v:131333$5392_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 3 $memwr$\memory$libresoc.v:131328$5376_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:131328$5376_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:131328$5376_EN + attribute \src "libresoc.v:0.0-0.0" + wire width 3 $memwr$\memory$libresoc.v:131329$5377_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:131329$5377_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:131329$5377_EN + attribute \src "libresoc.v:131321.13-131321.16" + wire width 3 \_0_ + attribute \src "libresoc.v:131322.13-131322.16" + wire width 3 \_1_ + attribute \src "libresoc.v:131323.13-131323.16" + wire width 3 \_2_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 15 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 14 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 16 \dest1__wen + attribute \src "libresoc.v:131230.7-131230.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:132633.7-132633.20" - process $proc$libresoc.v:132633$5058 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 2 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 5 \issue__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 7 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 4 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 3 \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 9 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 8 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 12 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 11 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \src2__ren + attribute \src "libresoc.v:131310.14-131310.20" + memory width 64 size 8 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5405 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5405 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5406 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5406 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5407 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5407 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5408 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5408 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5409 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5409 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5410 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5410 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5411 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5411 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5412 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5412 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:131331.26-131331.32" + cell $memrd $memrd$\memory$libresoc.v:131331$5390 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:131331$5390_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:131332.30-131332.36" + cell $memrd $memrd$\memory$libresoc.v:131332$5391 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:131332$5391_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:131333.30-131333.36" + cell $memrd $memrd$\memory$libresoc.v:131333$5392 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:131333$5392_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5413 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5413 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:131328$5376_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:131328$5376_DATA + connect \EN $memwr$\memory$libresoc.v:131328$5376_EN + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5414 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5414 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:131329$5377_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:131329$5377_DATA + connect \EN $memwr$\memory$libresoc.v:131329$5377_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$5421 + sync always + sync init + end + attribute \src "libresoc.v:131230.7-131230.20" + process $proc$libresoc.v:131230$5415 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132724.3-132744.6" - process $proc$libresoc.v:132724$5056 + attribute \src "libresoc.v:131279.7-131279.23" + process $proc$libresoc.v:131279$5416 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:131281.7-131281.28" + process $proc$libresoc.v:131281$5417 assign { } { } + assign $0\ren_delay$10[0:0]$5418 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5418 + end + attribute \src "libresoc.v:131285.7-131285.28" + process $proc$libresoc.v:131285$5419 assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:132725.5-132725.29" + assign $0\ren_delay$11[0:0]$5420 1'0 + sync always + sync init + update \ren_delay$11 $0\ren_delay$11[0:0]$5420 + end + attribute \src "libresoc.v:131304.3-131305.43" + process $proc$libresoc.v:131304$5378 + assign { } { } + assign $0\ren_delay$11[0:0]$5379 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[0:0]$5379 + end + attribute \src "libresoc.v:131306.3-131307.43" + process $proc$libresoc.v:131306$5380 + assign { } { } + assign $0\ren_delay$10[0:0]$5381 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5381 + end + attribute \src "libresoc.v:131308.3-131309.35" + process $proc$libresoc.v:131308$5382 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:131324.3-131330.6" + process $proc$libresoc.v:131324$5383 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:131329$5377_ADDR[2:0]$5387 3'xxx + assign $0$memwr$\memory$libresoc.v:131329$5377_DATA[63:0]$5388 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:131329$5377_EN[63:0]$5389 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:131328$5376_ADDR[2:0]$5384 3'xxx + assign $0$memwr$\memory$libresoc.v:131328$5376_DATA[63:0]$5385 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:131328$5376_EN[63:0]$5386 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[2:0] \src1__addr + assign $0\_1_[2:0] \src2__addr + assign $0\_2_[2:0] \issue__addr + attribute \src "libresoc.v:131328.5-131328.62" + switch \issue__wen + attribute \src "libresoc.v:131328.9-131328.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:131328$5376_ADDR[2:0]$5384 \issue__addr$1 + assign $0$memwr$\memory$libresoc.v:131328$5376_DATA[63:0]$5385 \issue__data_i + assign $0$memwr$\memory$libresoc.v:131328$5376_EN[63:0]$5386 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + attribute \src "libresoc.v:131329.5-131329.58" + switch \dest1__wen + attribute \src "libresoc.v:131329.9-131329.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:131329$5377_ADDR[2:0]$5387 \dest1__addr + assign $0$memwr$\memory$libresoc.v:131329$5377_DATA[63:0]$5388 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:131329$5377_EN[63:0]$5389 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[2:0] + update \_1_ $0\_1_[2:0] + update \_2_ $0\_2_[2:0] + update $memwr$\memory$libresoc.v:131328$5376_ADDR $0$memwr$\memory$libresoc.v:131328$5376_ADDR[2:0]$5384 + update $memwr$\memory$libresoc.v:131328$5376_DATA $0$memwr$\memory$libresoc.v:131328$5376_DATA[63:0]$5385 + update $memwr$\memory$libresoc.v:131328$5376_EN $0$memwr$\memory$libresoc.v:131328$5376_EN[63:0]$5386 + update $memwr$\memory$libresoc.v:131329$5377_ADDR $0$memwr$\memory$libresoc.v:131329$5377_ADDR[2:0]$5387 + update $memwr$\memory$libresoc.v:131329$5377_DATA $0$memwr$\memory$libresoc.v:131329$5377_DATA[63:0]$5388 + update $memwr$\memory$libresoc.v:131329$5377_EN $0$memwr$\memory$libresoc.v:131329$5377_EN[63:0]$5389 + end + attribute \src "libresoc.v:131334.3-131342.6" + process $proc$libresoc.v:131334$5393 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$5394 $1\ren_delay$next[0:0]$5395 + attribute \src "libresoc.v:131335.5-131335.29" switch \initial - attribute \src "libresoc.v:132725.9-132725.17" + attribute \src "libresoc.v:131335.9-131335.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$5395 1'0 + case + assign $1\ren_delay$next[0:0]$5395 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$5394 + end + attribute \src "libresoc.v:131343.3-131352.6" + process $proc$libresoc.v:131343$5396 + assign { } { } + assign { } { } + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:131344.5-131344.29" + switch \initial + attribute \src "libresoc.v:131344.9-131344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[63:0] \memory_r_data + case + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src1__data_o $0\src1__data_o[63:0] + end + attribute \src "libresoc.v:131353.3-131361.6" + process $proc$libresoc.v:131353$5397 + assign { } { } + assign { } { } + assign $0\ren_delay$10$next[0:0]$5398 $1\ren_delay$10$next[0:0]$5399 + attribute \src "libresoc.v:131354.5-131354.29" + switch \initial + attribute \src "libresoc.v:131354.9-131354.17" + case 1'1 case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \LOGICAL_OE - case - assign $2\oe[0:0] 1'0 - end + assign $1\ren_delay$10$next[0:0]$5399 1'0 + case + assign $1\ren_delay$10$next[0:0]$5399 \src2__ren end sync always - update \oe $0\oe[0:0] + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5398 end - attribute \src "libresoc.v:132745.3-132765.6" - process $proc$libresoc.v:132745$5057 + attribute \src "libresoc.v:131362.3-131371.6" + process $proc$libresoc.v:131362$5400 assign { } { } assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:132746.5-132746.29" + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "libresoc.v:131363.5-131363.29" switch \initial - attribute \src "libresoc.v:132746.9-132746.17" + attribute \src "libresoc.v:131363.9-131363.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 + case 1'1 + assign { } { } + assign $1\src2__data_o[63:0] \memory_r_data$4 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "libresoc.v:131372.3-131380.6" + process $proc$libresoc.v:131372$5401 + assign { } { } + assign { } { } + assign $0\ren_delay$11$next[0:0]$5402 $1\ren_delay$11$next[0:0]$5403 + attribute \src "libresoc.v:131373.5-131373.29" + switch \initial + attribute \src "libresoc.v:131373.9-131373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$11$next[0:0]$5403 1'0 + case + assign $1\ren_delay$11$next[0:0]$5403 \issue__ren + end + sync always + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5402 + end + attribute \src "libresoc.v:131381.3-131390.6" + process $proc$libresoc.v:131381$5404 + assign { } { } + assign { } { } + assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] + attribute \src "libresoc.v:131382.5-131382.29" + switch \initial + attribute \src "libresoc.v:131382.9-131382.17" + case 1'1 case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end + assign $1\issue__data_o[63:0] \memory_r_data$6 + case + assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \oe_ok $0\oe_ok[0:0] + update \issue__data_o $0\issue__data_o[63:0] end + connect \memory_r_data $memrd$\memory$libresoc.v:131331$5390_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:131332$5391_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:131333$5392_DATA + connect \memory_w_data$9 \issue__data_i + connect \memory_w_en$7 \issue__wen + connect \memory_w_addr$8 \issue__addr$1 + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$5 \issue__addr + connect \memory_r_addr$3 \src2__addr + connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:132770.1-132902.10" +attribute \src "libresoc.v:131404.1-133334.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" -module \dec_oe$165 - attribute \src "libresoc.v:132771.7-132771.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:132860.3-132880.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:132881.3-132901.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:132860.3-132880.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:132881.3-132901.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:132860.3-132880.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:132881.3-132901.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 2 \SPR_OE +module \fus + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 330 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 257 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 258 \cr_a_ok$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 259 \cr_a_ok$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 260 \cr_a_ok$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 261 \cr_a_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 262 \cr_a_ok$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 3 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 4 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 25 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 75 \cu_busy_o$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 82 \cu_busy_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 103 \cu_busy_o$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 31 \cu_busy_o$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 118 \cu_busy_o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 138 \cu_busy_o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 157 \cu_busy_o$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 42 \cu_busy_o$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 54 \cu_busy_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 24 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 30 \cu_issue_i$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 74 \cu_issue_i$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 81 \cu_issue_i$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 102 \cu_issue_i$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 117 \cu_issue_i$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 137 \cu_issue_i$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 156 \cu_issue_i$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 41 \cu_issue_i$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 53 \cu_issue_i$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 160 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 163 \cu_rd__go_i$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 166 \cu_rd__go_i$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 169 \cu_rd__go_i$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 172 \cu_rd__go_i$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 175 \cu_rd__go_i$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 178 \cu_rd__go_i$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 181 \cu_rd__go_i$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 184 \cu_rd__go_i$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 209 \cu_rd__go_i$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 159 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 162 \cu_rd__rel_o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 165 \cu_rd__rel_o$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 168 \cu_rd__rel_o$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 171 \cu_rd__rel_o$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 174 \cu_rd__rel_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 177 \cu_rd__rel_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 180 \cu_rd__rel_o$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 183 \cu_rd__rel_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 208 \cu_rd__rel_o$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 26 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 76 \cu_rdmaskn_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 83 \cu_rdmaskn_i$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 104 \cu_rdmaskn_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 119 \cu_rdmaskn_i$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 input 139 \cu_rdmaskn_i$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 158 \cu_rdmaskn_i$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 32 \cu_rdmaskn_i$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 43 \cu_rdmaskn_i$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 55 \cu_rdmaskn_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 5 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 2 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 221 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 242 \cu_wr__go_i$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 244 \cu_wr__go_i$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 293 \cu_wr__go_i$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 224 \cu_wr__go_i$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 227 \cu_wr__go_i$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 230 \cu_wr__go_i$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 233 \cu_wr__go_i$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 236 \cu_wr__go_i$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 239 \cu_wr__go_i$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 220 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 243 \cu_wr__rel_o$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 292 \cu_wr__rel_o$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 223 \cu_wr__rel_o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 226 \cu_wr__rel_o$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 229 \cu_wr__rel_o$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 232 \cu_wr__rel_o$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 235 \cu_wr__rel_o$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 238 \cu_wr__rel_o$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 241 \cu_wr__rel_o$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 245 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 246 \dest1_o$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 247 \dest1_o$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 248 \dest1_o$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 249 \dest1_o$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 250 \dest1_o$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 251 \dest1_o$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 252 \dest1_o$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 298 \dest1_o$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 output 256 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 263 \dest2_o$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 265 \dest2_o$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 266 \dest2_o$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 267 \dest2_o$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 268 \dest2_o$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 299 \dest2_o$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 301 \dest2_o$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 310 \dest2_o$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 264 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 272 \dest3_o$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 274 \dest3_o$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 281 \dest3_o$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 282 \dest3_o$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 300 \dest3_o$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 302 \dest3_o$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 305 \dest3_o$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 279 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 288 \dest4_o$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 289 \dest4_o$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 290 \dest4_o$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 306 \dest4_o$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 280 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 287 \dest5_o$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 308 \dest5_o$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 273 \dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 254 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 291 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 294 \fast1_ok$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 295 \fast1_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 296 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 297 \fast2_ok$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 255 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 output 315 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 316 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 325 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 311 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 314 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 317 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 318 \ldst_port0_exc_$signal$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 319 \ldst_port0_exc_$signal$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 320 \ldst_port0_exc_$signal$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 321 \ldst_port0_exc_$signal$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 322 \ldst_port0_exc_$signal$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 323 \ldst_port0_exc_$signal$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 324 \ldst_port0_exc_$signal$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 312 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 313 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 326 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 327 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 328 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 329 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 307 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 303 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 304 \nia_ok$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 253 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 219 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 222 \o_ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 225 \o_ok$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 228 \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 231 \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 234 \o_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 237 \o_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 240 \o_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 22 \oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 7 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 23 \oper_i_alu_alu0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -207977,116 +209338,54 @@ module \dec_oe$165 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 1 \SPR_internal_op - attribute \src "libresoc.v:132771.7-132771.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:132771.7-132771.20" - process $proc$libresoc.v:132771$5061 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:132860.3-132880.6" - process $proc$libresoc.v:132860$5059 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:132861.5-132861.29" - switch \initial - attribute \src "libresoc.v:132861.9-132861.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \SPR_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \SPR_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:132881.3-132901.6" - process $proc$libresoc.v:132881$5060 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:132882.5-132882.29" - switch \initial - attribute \src "libresoc.v:132882.9-132882.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \SPR_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:132906.1-133040.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" -attribute \generator "nMigen" -module \dec_oe$172 - attribute \src "libresoc.v:132907.7-132907.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:132998.3-133018.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:133019.3-133039.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:132998.3-133018.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:133019.3-133039.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:132998.3-133018.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:133019.3-133039.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 4 \DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \oper_i_alu_alu0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_alu_alu0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 33 \oper_i_alu_branch0__cia + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 35 \oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 37 \oper_i_alu_branch0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \oper_i_alu_branch0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \oper_i_alu_branch0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -208161,116 +209460,30 @@ module \dec_oe$172 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 1 \DIV_internal_op - attribute \src "libresoc.v:132907.7-132907.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:132907.7-132907.20" - process $proc$libresoc.v:132907$5064 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:132998.3-133018.6" - process $proc$libresoc.v:132998$5062 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:132999.5-132999.29" - switch \initial - attribute \src "libresoc.v:132999.9-132999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \DIV_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \DIV_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:133019.3-133039.6" - process $proc$libresoc.v:133019$5063 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:133020.5-133020.29" - switch \initial - attribute \src "libresoc.v:133020.9-133020.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \DIV_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:133044.1-133178.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" -attribute \generator "nMigen" -module \dec_oe$181 - attribute \src "libresoc.v:133045.7-133045.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:133136.3-133156.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:133157.3-133177.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:133136.3-133156.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:133157.3-133177.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:133136.3-133156.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:133157.3-133177.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 4 \MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 34 \oper_i_alu_branch0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \oper_i_alu_branch0__lk + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 28 \oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 29 \oper_i_alu_cr0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -208345,116 +209558,38 @@ module \dec_oe$181 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 1 \MUL_internal_op - attribute \src "libresoc.v:133045.7-133045.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 27 \oper_i_alu_cr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 100 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 85 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 86 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 87 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:133045.7-133045.20" - process $proc$libresoc.v:133045$5067 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:133136.3-133156.6" - process $proc$libresoc.v:133136$5065 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:133137.5-133137.29" - switch \initial - attribute \src "libresoc.v:133137.9-133137.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \MUL_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \MUL_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:133157.3-133177.6" - process $proc$libresoc.v:133157$5066 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:133158.5-133158.29" - switch \initial - attribute \src "libresoc.v:133158.9-133158.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \MUL_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:133182.1-133316.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" -attribute \generator "nMigen" -module \dec_oe$189 - attribute \src "libresoc.v:133183.7-133183.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:133274.3-133294.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:133295.3-133315.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:133274.3-133294.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:133295.3-133315.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:133274.3-133294.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:133295.3-133315.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 4 \SHIFT_ROT_OE + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 94 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 101 \oper_i_alu_div0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -208529,116 +209664,60 @@ module \dec_oe$189 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "libresoc.v:133183.7-133183.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 84 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 92 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 95 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 98 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 99 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 90 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 91 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 97 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 89 \oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 88 \oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 96 \oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 93 \oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 72 \oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 57 \oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 58 \oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 59 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:133183.7-133183.20" - process $proc$libresoc.v:133183$5070 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:133274.3-133294.6" - process $proc$libresoc.v:133274$5068 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:133275.5-133275.29" - switch \initial - attribute \src "libresoc.v:133275.9-133275.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \SHIFT_ROT_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \SHIFT_ROT_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:133295.3-133315.6" - process $proc$libresoc.v:133295$5069 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:133296.5-133296.29" - switch \initial - attribute \src "libresoc.v:133296.9-133296.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \SHIFT_ROT_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:133320.1-133454.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" -attribute \generator "nMigen" -module \dec_oe$197 - attribute \src "libresoc.v:133321.7-133321.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:133412.3-133432.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:133433.3-133453.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:133412.3-133432.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:133433.3-133453.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:133412.3-133432.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:133433.3-133453.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 4 \LDST_OE + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 66 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 73 \oper_i_alu_logical0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -208713,118 +209792,172 @@ module \dec_oe$197 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 1 \LDST_internal_op - attribute \src "libresoc.v:133321.7-133321.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 56 \oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 64 \oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 67 \oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 70 \oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 71 \oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 62 \oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 63 \oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 69 \oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 61 \oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 60 \oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 68 \oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 65 \oper_i_alu_logical0__zero_a + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 106 \oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 107 \oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 108 \oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 116 \oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 105 \oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 114 \oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 115 \oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 111 \oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 112 \oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 110 \oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 109 \oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 113 \oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 121 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 122 \oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 123 \oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:133321.7-133321.20" - process $proc$libresoc.v:133321$5073 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:133412.3-133432.6" - process $proc$libresoc.v:133412$5071 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:133413.5-133413.29" - switch \initial - attribute \src "libresoc.v:133413.9-133413.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \LDST_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \LDST_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:133433.3-133453.6" - process $proc$libresoc.v:133433$5072 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:133434.5-133434.29" - switch \initial - attribute \src "libresoc.v:133434.9-133434.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \LDST_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:133458.1-133592.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" -attribute \generator "nMigen" -module \dec_oe$206 - attribute \src "libresoc.v:133459.7-133459.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:133550.3-133570.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:133571.3-133591.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:133550.3-133570.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:133571.3-133591.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:133550.3-133570.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:133571.3-133591.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 4 \OE - attribute \src "libresoc.v:133459.7-133459.15" - wire \initial + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 130 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 132 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 136 \oper_i_alu_shift_rot0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -208899,1768 +210032,3004 @@ module \dec_oe$206 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" - wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 120 \oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 129 \oper_i_alu_shift_rot0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 134 \oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 135 \oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 126 \oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 127 \oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 131 \oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 133 \oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 125 \oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 124 \oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 128 \oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 78 \oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 79 \oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute 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309 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 161 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 164 \src1_i$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 167 \src1_i$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 170 \src1_i$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 173 \src1_i$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 176 \src1_i$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 179 \src1_i$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 182 \src1_i$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 185 \src1_i$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 213 \src1_i$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 186 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 187 \src2_i$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 188 \src2_i$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 189 \src2_i$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 190 \src2_i$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 191 \src2_i$56 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 199 \src3_i$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 200 \src3_i$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 input 206 \src3_i$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 210 \src3_i$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 214 \src3_i$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 215 \src3_i$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 198 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 201 \src4_i$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 202 \src4_i$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 207 \src4_i$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 217 \src4_i$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 204 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 205 \src5_i$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 211 \src5_i$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 203 \src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 212 \src6_i$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:133459.7-133459.20" - process $proc$libresoc.v:133459$5076 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:133550.3-133570.6" - process $proc$libresoc.v:133550$5074 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:133551.5-133551.29" - switch \initial - attribute \src "libresoc.v:133551.9-133551.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:133571.3-133591.6" - process $proc$libresoc.v:133571$5075 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:133572.5-133572.29" - switch \initial - attribute \src "libresoc.v:133572.9-133572.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:133596.1-133650.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" -attribute \generator "nMigen" -module \dec_rc - attribute \src "libresoc.v:133597.7-133597.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:133612.3-133630.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:133631.3-133649.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:133612.3-133630.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:133631.3-133649.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 3 \ALU_Rc - attribute \src "libresoc.v:133597.7-133597.15" - wire \initial + wire output 269 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc + wire output 270 \xer_ca_ok$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:133597.7-133597.20" - process $proc$libresoc.v:133597$5079 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:133612.3-133630.6" - process $proc$libresoc.v:133612$5077 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:133613.5-133613.29" - switch \initial - attribute \src "libresoc.v:133613.9-133613.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \ALU_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:133631.3-133649.6" - process $proc$libresoc.v:133631$5078 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:133632.5-133632.29" - switch \initial - attribute \src "libresoc.v:133632.9-133632.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:133654.1-133707.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" -attribute \generator "nMigen" -module \dec_rc$140 - attribute \src "libresoc.v:133655.7-133655.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:133669.3-133687.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:133688.3-133706.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:133669.3-133687.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:133688.3-133706.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 2 \CR_Rc - attribute \src "libresoc.v:133655.7-133655.15" - wire \initial + wire output 271 \xer_ca_ok$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc + wire output 275 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:133655.7-133655.20" - process $proc$libresoc.v:133655$5082 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:133669.3-133687.6" - process $proc$libresoc.v:133669$5080 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:133670.5-133670.29" - switch \initial - attribute \src "libresoc.v:133670.9-133670.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \CR_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:133688.3-133706.6" - process $proc$libresoc.v:133688$5081 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:133689.5-133689.29" - switch \initial - attribute \src "libresoc.v:133689.9-133689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:133711.1-133764.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" -attribute \generator "nMigen" -module \dec_rc$147 - attribute \src "libresoc.v:133712.7-133712.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:133726.3-133744.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:133745.3-133763.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:133726.3-133744.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:133745.3-133763.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 2 \BRANCH_Rc - attribute \src "libresoc.v:133712.7-133712.15" - wire \initial + wire output 276 \xer_ov_ok$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc + wire output 277 \xer_ov_ok$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:133712.7-133712.20" - process $proc$libresoc.v:133712$5085 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + wire output 278 \xer_ov_ok$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 283 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 284 \xer_so_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 285 \xer_so_ok$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 286 \xer_so_ok$131 + attribute \module_not_derived 1 + attribute \src "libresoc.v:132966.8-133008.4" + cell \alu0 \alu0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok + connect \cu_busy_o \cu_busy_o + connect \cu_issue_i \cu_issue_i + connect \cu_rd__go_i \cu_rd__go_i + connect \cu_rd__rel_o \cu_rd__rel_o + connect \cu_rdmaskn_i \cu_rdmaskn_i + connect \cu_wr__go_i \cu_wr__go_i + connect \cu_wr__rel_o \cu_wr__rel_o + connect \dest1_o \dest1_o + connect \dest2_o \dest2_o$115 + connect \dest3_o \dest3_o$122 + connect \dest4_o \dest4_o + connect \dest5_o \dest5_o$132 + connect \o_ok \o_ok + connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a + connect \src1_i \src1_i + connect \src2_i \src2_i + connect \src3_i \src3_i$60 + connect \src4_i \src4_i$65 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov_ok \xer_ov_ok + connect \xer_so_ok \xer_so_ok end - attribute \src "libresoc.v:133726.3-133744.6" - process $proc$libresoc.v:133726$5083 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:133727.5-133727.29" - switch \initial - attribute \src "libresoc.v:133727.9-133727.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \BRANCH_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:133009.11-133036.4" + cell \branch0 \branch0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$5 + connect \cu_issue_i \cu_issue_i$4 + connect \cu_rd__go_i \cu_rd__go_i$70 + connect \cu_rd__rel_o \cu_rd__rel_o$69 + connect \cu_rdmaskn_i \cu_rdmaskn_i$6 + connect \cu_wr__go_i \cu_wr__go_i$137 + connect \cu_wr__rel_o \cu_wr__rel_o$136 + connect \dest1_o \dest1_o$141 + connect \dest2_o \dest2_o$144 + connect \dest3_o \dest3_o$147 + connect \fast1_ok \fast1_ok + connect \fast2_ok \fast2_ok + connect \nia_ok \nia_ok + connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk + connect \src1_i \src1_i$74 + connect \src2_i \src2_i$77 + connect \src3_i \src3_i$71 end - attribute \src "libresoc.v:133745.3-133763.6" - process $proc$libresoc.v:133745$5084 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:133746.5-133746.29" - switch \initial - attribute \src "libresoc.v:133746.9-133746.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:133037.7-133062.4" + cell \cr0 \cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$110 + connect \cu_busy_o \cu_busy_o$2 + connect \cu_issue_i \cu_issue_i$1 + connect \cu_rd__go_i \cu_rd__go_i$29 + connect \cu_rd__rel_o \cu_rd__rel_o$28 + connect \cu_rdmaskn_i \cu_rdmaskn_i$3 + connect \cu_wr__go_i \cu_wr__go_i$82 + connect \cu_wr__rel_o \cu_wr__rel_o$81 + connect \dest1_o \dest1_o$103 + connect \dest2_o \dest2_o + connect \dest3_o \dest3_o + connect \full_cr_ok \full_cr_ok + connect \o_ok \o_ok$80 + connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type + connect \src1_i \src1_i$30 + connect \src2_i \src2_i$52 + connect \src3_i \src3_i$67 + connect \src4_i \src4_i$68 + connect \src5_i \src5_i$72 + connect \src6_i \src6_i$73 end -end -attribute \src "libresoc.v:133768.1-133822.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" -attribute \generator "nMigen" -module \dec_rc$155 - attribute \src "libresoc.v:133769.7-133769.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:133784.3-133802.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:133803.3-133821.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:133784.3-133802.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:133803.3-133821.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 3 \LOGICAL_Rc - attribute \src "libresoc.v:133769.7-133769.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:133769.7-133769.20" - process $proc$libresoc.v:133769$5088 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \module_not_derived 1 + attribute \src "libresoc.v:133063.8-133102.4" + cell \div0 \div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$112 + connect \cu_busy_o \cu_busy_o$17 + connect \cu_issue_i \cu_issue_i$16 + connect \cu_rd__go_i \cu_rd__go_i$41 + connect \cu_rd__rel_o \cu_rd__rel_o$40 + connect \cu_rdmaskn_i \cu_rdmaskn_i$18 + connect \cu_wr__go_i \cu_wr__go_i$94 + connect \cu_wr__rel_o \cu_wr__rel_o$93 + connect \dest1_o \dest1_o$107 + connect \dest2_o \dest2_o$117 + connect \dest3_o \dest3_o$127 + connect \dest4_o \dest4_o$134 + connect \o_ok \o_ok$92 + connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a + connect \src1_i \src1_i$42 + connect \src2_i \src2_i$55 + connect \src3_i \src3_i$62 + connect \xer_ov_ok \xer_ov_ok$125 + connect \xer_so_ok \xer_so_ok$130 end - attribute \src "libresoc.v:133784.3-133802.6" - process $proc$libresoc.v:133784$5086 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:133785.5-133785.29" - switch \initial - attribute \src "libresoc.v:133785.9-133785.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \LOGICAL_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:133103.9-133157.4" + cell \ldst0 \ldst0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \cu_busy_o$26 + connect \cu_issue_i \cu_issue_i$25 + connect \cu_rd__go_i \cu_rd__go_i$50 + connect \cu_rd__rel_o \cu_rd__rel_o$49 + connect \cu_rdmaskn_i \cu_rdmaskn_i$27 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \cu_wr__go_i$102 + connect \cu_wr__rel_o \cu_wr__rel_o$101 + connect \ea \ea + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$151 + connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$152 + connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$153 + connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$154 + connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$155 + connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$156 + connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$157 + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \o \o + connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a + connect \src1_i \src1_i$51 + connect \src2_i \src2_i$58 + connect \src3_i \src3_i$59 end - attribute \src "libresoc.v:133803.3-133821.6" - process $proc$libresoc.v:133803$5087 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:133804.5-133804.29" - switch \initial - attribute \src "libresoc.v:133804.9-133804.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:133158.12-133193.4" + cell \logical0 \logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$111 + connect \cu_busy_o \cu_busy_o$11 + connect \cu_issue_i \cu_issue_i$10 + connect \cu_rd__go_i \cu_rd__go_i$35 + connect \cu_rd__rel_o \cu_rd__rel_o$34 + connect \cu_rdmaskn_i \cu_rdmaskn_i$12 + connect \cu_wr__go_i \cu_wr__go_i$88 + connect \cu_wr__rel_o \cu_wr__rel_o$87 + connect \dest1_o \dest1_o$105 + connect \dest2_o \dest2_o$116 + connect \o_ok \o_ok$86 + connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a + connect \src1_i \src1_i$36 + connect \src2_i \src2_i$54 + connect \src3_i \src3_i$61 end -end -attribute \src "libresoc.v:133826.1-133879.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" -attribute \generator "nMigen" -module \dec_rc$164 - attribute \src "libresoc.v:133827.7-133827.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:133841.3-133859.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:133860.3-133878.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:133841.3-133859.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:133860.3-133878.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 2 \SPR_Rc - attribute \src "libresoc.v:133827.7-133827.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:133827.7-133827.20" - process $proc$libresoc.v:133827$5091 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \module_not_derived 1 + attribute \src "libresoc.v:133194.8-133227.4" + cell \mul0 \mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$113 + connect \cu_busy_o \cu_busy_o$20 + connect \cu_issue_i \cu_issue_i$19 + connect \cu_rd__go_i \cu_rd__go_i$44 + connect \cu_rd__rel_o \cu_rd__rel_o$43 + connect \cu_rdmaskn_i \cu_rdmaskn_i$21 + connect \cu_wr__go_i \cu_wr__go_i$97 + connect \cu_wr__rel_o \cu_wr__rel_o$96 + connect \dest1_o \dest1_o$108 + connect \dest2_o \dest2_o$118 + connect \dest3_o \dest3_o$128 + connect \dest4_o \dest4_o$135 + connect \o_ok \o_ok$95 + connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 + connect \src1_i \src1_i$45 + connect \src2_i \src2_i$56 + connect \src3_i \src3_i$63 + connect \xer_ov_ok \xer_ov_ok$126 + connect \xer_so_ok \xer_so_ok$131 end - attribute \src "libresoc.v:133841.3-133859.6" - process $proc$libresoc.v:133841$5089 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:133842.5-133842.29" - switch \initial - attribute \src "libresoc.v:133842.9-133842.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \SPR_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:133228.13-133266.4" + cell \shiftrot0 \shiftrot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$114 + connect \cu_busy_o \cu_busy_o$23 + connect \cu_issue_i \cu_issue_i$22 + connect \cu_rd__go_i \cu_rd__go_i$47 + connect \cu_rd__rel_o \cu_rd__rel_o$46 + connect \cu_rdmaskn_i \cu_rdmaskn_i$24 + connect \cu_wr__go_i \cu_wr__go_i$100 + connect \cu_wr__rel_o \cu_wr__rel_o$99 + connect \dest1_o \dest1_o$109 + connect \dest2_o \dest2_o$119 + connect \dest3_o \dest3_o$123 + connect \o_ok \o_ok$98 + connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__invert_in + connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 + connect \src1_i \src1_i$48 + connect \src2_i \src2_i$57 + connect \src3_i \src3_i + connect \src4_i \src4_i$64 + connect \src5_i \src5_i + connect \xer_ca_ok \xer_ca_ok$121 end - attribute \src "libresoc.v:133860.3-133878.6" - process $proc$libresoc.v:133860$5090 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:133861.5-133861.29" - switch \initial - attribute \src "libresoc.v:133861.9-133861.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:133267.8-133299.4" + cell \spr0 \spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$14 + connect \cu_issue_i \cu_issue_i$13 + connect \cu_rd__go_i \cu_rd__go_i$38 + connect \cu_rd__rel_o \cu_rd__rel_o$37 + connect \cu_rdmaskn_i \cu_rdmaskn_i$15 + connect \cu_wr__go_i \cu_wr__go_i$91 + connect \cu_wr__rel_o \cu_wr__rel_o$90 + connect \dest1_o \dest1_o$106 + connect \dest2_o \dest2_o$150 + connect \dest3_o \dest3_o$143 + connect \dest4_o \dest4_o$133 + connect \dest5_o \dest5_o + connect \dest6_o \dest6_o + connect \fast1_ok \fast1_ok$139 + connect \o_ok \o_ok$89 + connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit + connect \spr1_ok \spr1_ok + connect \src1_i \src1_i$39 + connect \src2_i \src2_i$79 + connect \src3_i \src3_i$76 + connect \src4_i \src4_i + connect \src5_i \src5_i$66 + connect \src6_i \src6_i + connect \xer_ca_ok \xer_ca_ok$120 + connect \xer_ov_ok \xer_ov_ok$124 + connect \xer_so_ok \xer_so_ok$129 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:133300.9-133333.4" + cell \trap0 \trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$8 + connect \cu_issue_i \cu_issue_i$7 + connect \cu_rd__go_i \cu_rd__go_i$32 + connect \cu_rd__rel_o \cu_rd__rel_o$31 + connect \cu_rdmaskn_i \cu_rdmaskn_i$9 + connect \cu_wr__go_i \cu_wr__go_i$85 + connect \cu_wr__rel_o \cu_wr__rel_o$84 + connect \dest1_o \dest1_o$104 + connect \dest2_o \dest2_o$142 + connect \dest3_o \dest3_o$145 + connect \dest4_o \dest4_o$148 + connect \dest5_o \dest5_o$149 + connect \fast1_ok \fast1_ok$138 + connect \fast2_ok \fast2_ok$140 + connect \msr_ok \msr_ok + connect \nia_ok \nia_ok$146 + connect \o_ok \o_ok$83 + connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__ldst_exc + connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype + connect \src1_i \src1_i$33 + connect \src2_i \src2_i$53 + connect \src3_i \src3_i$75 + connect \src4_i \src4_i$78 end end -attribute \src "libresoc.v:133883.1-133937.10" +attribute \src "libresoc.v:133338.1-133396.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" attribute \generator "nMigen" -module \dec_rc$171 - attribute \src "libresoc.v:133884.7-133884.20" +module \idx_l + attribute \src "libresoc.v:133339.7-133339.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133899.3-133917.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:133918.3-133936.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:133899.3-133917.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:133918.3-133936.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 3 \DIV_Rc - attribute \src "libresoc.v:133884.7-133884.15" + attribute \src "libresoc.v:133384.3-133392.6" + wire $0\q_int$next[0:0]$5432 + attribute \src "libresoc.v:133382.3-133383.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:133384.3-133392.6" + wire $1\q_int$next[0:0]$5433 + attribute \src "libresoc.v:133363.7-133363.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:133374.17-133374.96" + wire $and$libresoc.v:133374$5422_Y + attribute \src "libresoc.v:133379.17-133379.96" + wire $and$libresoc.v:133379$5427_Y + attribute \src "libresoc.v:133376.18-133376.95" + wire $not$libresoc.v:133376$5424_Y + attribute \src "libresoc.v:133378.17-133378.94" + wire $not$libresoc.v:133378$5426_Y + attribute \src "libresoc.v:133381.17-133381.94" + wire $not$libresoc.v:133381$5429_Y + attribute \src "libresoc.v:133375.18-133375.100" + wire $or$libresoc.v:133375$5423_Y + attribute \src "libresoc.v:133377.18-133377.101" + wire $or$libresoc.v:133377$5425_Y + attribute \src "libresoc.v:133380.17-133380.99" + wire $or$libresoc.v:133380$5428_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:133339.7-133339.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:133884.7-133884.20" - process $proc$libresoc.v:133884$5094 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:133374$5422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:133374$5422_Y end - attribute \src "libresoc.v:133899.3-133917.6" - process $proc$libresoc.v:133899$5092 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:133900.5-133900.29" - switch \initial - attribute \src "libresoc.v:133900.9-133900.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \DIV_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:133379$5427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:133379$5427_Y end - attribute \src "libresoc.v:133918.3-133936.6" - process $proc$libresoc.v:133918$5093 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:133919.5-133919.29" - switch \initial - attribute \src "libresoc.v:133919.9-133919.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:133376$5424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \Y $not$libresoc.v:133376$5424_Y end -end -attribute \src "libresoc.v:133941.1-133995.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" -attribute \generator "nMigen" -module \dec_rc$180 - attribute \src "libresoc.v:133942.7-133942.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:133957.3-133975.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:133976.3-133994.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:133957.3-133975.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:133976.3-133994.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 3 \MUL_Rc - attribute \src "libresoc.v:133942.7-133942.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:133942.7-133942.20" - process $proc$libresoc.v:133942$5097 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:133378$5426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$libresoc.v:133378$5426_Y end - attribute \src "libresoc.v:133957.3-133975.6" - process $proc$libresoc.v:133957$5095 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:133958.5-133958.29" - switch \initial - attribute \src "libresoc.v:133958.9-133958.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \MUL_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:133381$5429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$libresoc.v:133381$5429_Y end - attribute \src "libresoc.v:133976.3-133994.6" - process $proc$libresoc.v:133976$5096 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:133977.5-133977.29" - switch \initial - attribute \src "libresoc.v:133977.9-133977.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:133375$5423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_idx_l + connect \Y $or$libresoc.v:133375$5423_Y end -end -attribute \src "libresoc.v:133999.1-134053.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" -attribute \generator "nMigen" -module \dec_rc$188 - attribute \src "libresoc.v:134000.7-134000.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:134015.3-134033.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:134034.3-134052.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:134015.3-134033.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:134034.3-134052.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 3 \SHIFT_ROT_Rc - attribute \src "libresoc.v:134000.7-134000.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:134000.7-134000.20" - process $proc$libresoc.v:134000$5100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:133377$5425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \B \q_int + connect \Y $or$libresoc.v:133377$5425_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:133380$5428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_idx_l + connect \Y $or$libresoc.v:133380$5428_Y + end + attribute \src "libresoc.v:133339.7-133339.20" + process $proc$libresoc.v:133339$5434 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134015.3-134033.6" - process $proc$libresoc.v:134015$5098 + attribute \src "libresoc.v:133363.7-133363.19" + process $proc$libresoc.v:133363$5435 assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:134016.5-134016.29" - switch \initial - attribute \src "libresoc.v:134016.9-134016.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \SHIFT_ROT_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end + assign $1\q_int[0:0] 1'0 sync always - update \rc $0\rc[0:0] + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:133382.3-133383.27" + process $proc$libresoc.v:133382$5430 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:134034.3-134052.6" - process $proc$libresoc.v:134034$5099 + attribute \src "libresoc.v:133384.3-133392.6" + process $proc$libresoc.v:133384$5431 assign { } { } assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:134035.5-134035.29" + assign $0\q_int$next[0:0]$5432 $1\q_int$next[0:0]$5433 + attribute \src "libresoc.v:133385.5-133385.29" switch \initial - attribute \src "libresoc.v:134035.9-134035.17" + attribute \src "libresoc.v:133385.9-133385.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 1'1 assign { } { } - assign $1\rc_ok[0:0] 1'1 + assign $1\q_int$next[0:0]$5433 1'0 case - assign $1\rc_ok[0:0] 1'0 + assign $1\q_int$next[0:0]$5433 \$5 end sync always - update \rc_ok $0\rc_ok[0:0] + update \q_int$next $0\q_int$next[0:0]$5432 end + connect \$9 $and$libresoc.v:133374$5422_Y + connect \$11 $or$libresoc.v:133375$5423_Y + connect \$13 $not$libresoc.v:133376$5424_Y + connect \$15 $or$libresoc.v:133377$5425_Y + connect \$1 $not$libresoc.v:133378$5426_Y + connect \$3 $and$libresoc.v:133379$5427_Y + connect \$5 $or$libresoc.v:133380$5428_Y + connect \$7 $not$libresoc.v:133381$5429_Y + connect \qlq_idx_l \$15 + connect \qn_idx_l \$13 + connect \q_idx_l \$11 end -attribute \src "libresoc.v:134057.1-134111.10" +attribute \src "libresoc.v:133400.1-133779.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.imem" attribute \generator "nMigen" -module \dec_rc$196 - attribute \src "libresoc.v:134058.7-134058.20" +module \imem + attribute \src "libresoc.v:133731.3-133740.6" + wire $0\a_busy_o[0:0] + attribute \src "libresoc.v:133711.3-133730.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5504 + attribute \src "libresoc.v:133542.3-133543.39" + wire width 45 $0\f_badaddr_o[44:0] + attribute \src "libresoc.v:133741.3-133758.6" + wire $0\f_busy_o[0:0] + attribute \src "libresoc.v:133688.3-133710.6" + wire $0\f_fetch_err_o$next[0:0]$5499 + attribute \src "libresoc.v:133544.3-133545.43" + wire $0\f_fetch_err_o[0:0] + attribute \src "libresoc.v:133759.3-133776.6" + wire width 64 $0\f_instr_o[63:0] + attribute \src "libresoc.v:133665.3-133687.6" + wire width 45 $0\ibus__adr$next[44:0]$5494 + attribute \src "libresoc.v:133546.3-133547.35" + wire width 45 $0\ibus__adr[44:0] + attribute \src "libresoc.v:133556.3-133583.6" + wire $0\ibus__cyc$next[0:0]$5470 + attribute \src "libresoc.v:133554.3-133555.35" + wire $0\ibus__cyc[0:0] + attribute \src "libresoc.v:133612.3-133639.6" + wire width 8 $0\ibus__sel$next[7:0]$5482 + attribute \src "libresoc.v:133550.3-133551.35" + wire width 8 $0\ibus__sel[7:0] + attribute \src "libresoc.v:133584.3-133611.6" + wire $0\ibus__stb$next[0:0]$5476 + attribute \src "libresoc.v:133552.3-133553.35" + wire $0\ibus__stb[0:0] + attribute \src "libresoc.v:133640.3-133664.6" + wire width 64 $0\ibus_rdata$next[63:0]$5488 + attribute \src "libresoc.v:133548.3-133549.37" + wire width 64 $0\ibus_rdata[63:0] + attribute \src "libresoc.v:133401.7-133401.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134073.3-134091.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:134092.3-134110.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:134073.3-134091.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:134092.3-134110.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 3 \LDST_Rc - attribute \src "libresoc.v:134058.7-134058.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:134058.7-134058.20" - process $proc$libresoc.v:134058$5103 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:134073.3-134091.6" - process $proc$libresoc.v:134073$5101 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:134074.5-134074.29" - switch \initial - attribute \src "libresoc.v:134074.9-134074.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \LDST_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:133731.3-133740.6" + wire $1\a_busy_o[0:0] + attribute \src "libresoc.v:133711.3-133730.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5505 + attribute \src "libresoc.v:133465.14-133465.44" + wire width 45 $1\f_badaddr_o[44:0] + attribute \src "libresoc.v:133741.3-133758.6" + wire $1\f_busy_o[0:0] + attribute \src "libresoc.v:133688.3-133710.6" + wire $1\f_fetch_err_o$next[0:0]$5500 + attribute \src "libresoc.v:133472.7-133472.27" + wire $1\f_fetch_err_o[0:0] + attribute \src "libresoc.v:133759.3-133776.6" + wire width 64 $1\f_instr_o[63:0] + attribute \src "libresoc.v:133665.3-133687.6" + wire width 45 $1\ibus__adr$next[44:0]$5495 + attribute \src "libresoc.v:133486.14-133486.42" + wire width 45 $1\ibus__adr[44:0] + attribute \src "libresoc.v:133556.3-133583.6" + wire $1\ibus__cyc$next[0:0]$5471 + attribute \src "libresoc.v:133491.7-133491.23" + wire $1\ibus__cyc[0:0] + attribute \src "libresoc.v:133612.3-133639.6" + wire width 8 $1\ibus__sel$next[7:0]$5483 + attribute \src "libresoc.v:133500.13-133500.30" + wire width 8 $1\ibus__sel[7:0] + attribute \src "libresoc.v:133584.3-133611.6" + wire $1\ibus__stb$next[0:0]$5477 + attribute \src "libresoc.v:133505.7-133505.23" + wire $1\ibus__stb[0:0] + attribute \src "libresoc.v:133640.3-133664.6" + wire width 64 $1\ibus_rdata$next[63:0]$5489 + attribute \src "libresoc.v:133509.14-133509.47" + wire width 64 $1\ibus_rdata[63:0] + attribute \src "libresoc.v:133711.3-133730.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5506 + attribute \src "libresoc.v:133741.3-133758.6" + wire $2\f_busy_o[0:0] + attribute \src "libresoc.v:133688.3-133710.6" + wire $2\f_fetch_err_o$next[0:0]$5501 + attribute \src "libresoc.v:133759.3-133776.6" + wire width 64 $2\f_instr_o[63:0] + attribute \src "libresoc.v:133665.3-133687.6" + wire width 45 $2\ibus__adr$next[44:0]$5496 + attribute \src "libresoc.v:133556.3-133583.6" + wire $2\ibus__cyc$next[0:0]$5472 + attribute \src "libresoc.v:133612.3-133639.6" + wire width 8 $2\ibus__sel$next[7:0]$5484 + attribute \src "libresoc.v:133584.3-133611.6" + wire $2\ibus__stb$next[0:0]$5478 + attribute \src "libresoc.v:133640.3-133664.6" + wire width 64 $2\ibus_rdata$next[63:0]$5490 + attribute \src "libresoc.v:133711.3-133730.6" + wire width 45 $3\f_badaddr_o$next[44:0]$5507 + attribute \src "libresoc.v:133688.3-133710.6" + wire $3\f_fetch_err_o$next[0:0]$5502 + attribute \src "libresoc.v:133665.3-133687.6" + wire width 45 $3\ibus__adr$next[44:0]$5497 + attribute \src "libresoc.v:133556.3-133583.6" + wire $3\ibus__cyc$next[0:0]$5473 + attribute \src "libresoc.v:133612.3-133639.6" + wire width 8 $3\ibus__sel$next[7:0]$5485 + attribute \src "libresoc.v:133584.3-133611.6" + wire $3\ibus__stb$next[0:0]$5479 + attribute \src "libresoc.v:133640.3-133664.6" + wire width 64 $3\ibus_rdata$next[63:0]$5491 + attribute \src "libresoc.v:133556.3-133583.6" + wire $4\ibus__cyc$next[0:0]$5474 + attribute \src "libresoc.v:133612.3-133639.6" + wire width 8 $4\ibus__sel$next[7:0]$5486 + attribute \src "libresoc.v:133584.3-133611.6" + wire $4\ibus__stb$next[0:0]$5480 + attribute \src "libresoc.v:133640.3-133664.6" + wire width 64 $4\ibus_rdata$next[63:0]$5492 + attribute \src "libresoc.v:133518.18-133518.110" + wire $and$libresoc.v:133518$5438_Y + attribute \src "libresoc.v:133524.18-133524.110" + wire $and$libresoc.v:133524$5444_Y + attribute \src "libresoc.v:133529.18-133529.110" + wire $and$libresoc.v:133529$5449_Y + attribute \src "libresoc.v:133532.17-133532.108" + wire $and$libresoc.v:133532$5452_Y + attribute \src "libresoc.v:133535.18-133535.110" + wire $and$libresoc.v:133535$5455_Y + attribute \src "libresoc.v:133536.18-133536.115" + wire $and$libresoc.v:133536$5456_Y + attribute \src "libresoc.v:133538.18-133538.115" + wire $and$libresoc.v:133538$5458_Y + attribute \src "libresoc.v:133517.18-133517.105" + wire $not$libresoc.v:133517$5437_Y + attribute \src "libresoc.v:133520.18-133520.105" + wire $not$libresoc.v:133520$5440_Y + attribute \src "libresoc.v:133521.17-133521.104" + wire $not$libresoc.v:133521$5441_Y + attribute \src "libresoc.v:133523.18-133523.105" + wire $not$libresoc.v:133523$5443_Y + attribute \src "libresoc.v:133526.18-133526.105" + wire $not$libresoc.v:133526$5446_Y + attribute \src "libresoc.v:133528.18-133528.105" + wire $not$libresoc.v:133528$5448_Y + attribute \src "libresoc.v:133531.18-133531.105" + wire $not$libresoc.v:133531$5451_Y + attribute \src "libresoc.v:133534.18-133534.105" + wire $not$libresoc.v:133534$5454_Y + attribute \src "libresoc.v:133537.18-133537.105" + wire $not$libresoc.v:133537$5457_Y + attribute \src "libresoc.v:133539.18-133539.105" + wire $not$libresoc.v:133539$5459_Y + attribute \src "libresoc.v:133541.17-133541.104" + wire $not$libresoc.v:133541$5461_Y + attribute \src "libresoc.v:133516.17-133516.103" + wire $or$libresoc.v:133516$5436_Y + attribute \src "libresoc.v:133519.18-133519.115" + wire $or$libresoc.v:133519$5439_Y + attribute \src "libresoc.v:133522.18-133522.106" + wire $or$libresoc.v:133522$5442_Y + attribute \src "libresoc.v:133525.18-133525.115" + wire $or$libresoc.v:133525$5445_Y + attribute \src "libresoc.v:133527.18-133527.106" + wire $or$libresoc.v:133527$5447_Y + attribute \src "libresoc.v:133530.18-133530.115" + wire $or$libresoc.v:133530$5450_Y + attribute \src "libresoc.v:133533.18-133533.106" + wire $or$libresoc.v:133533$5453_Y + attribute \src "libresoc.v:133540.17-133540.114" + wire $or$libresoc.v:133540$5460_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" + wire \a_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 input 2 \a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" + wire \a_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire input 3 \a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" + wire input 15 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire output 5 \f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 output 6 \f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" + wire \f_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire input 4 \f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 9 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 14 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 \ibus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 8 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 13 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 10 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 12 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 \ibus__sel$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 11 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__stb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" + wire width 64 \ibus_rdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" + wire width 64 \ibus_rdata$next + attribute \src "libresoc.v:133401.7-133401.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire input 7 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:133518$5438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$11 + connect \Y $and$libresoc.v:133518$5438_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:133524$5444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$21 + connect \Y $and$libresoc.v:133524$5444_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:133529$5449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$31 + connect \Y $and$libresoc.v:133529$5449_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:133532$5452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$1 + connect \Y $and$libresoc.v:133532$5452_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:133535$5455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$41 + connect \Y $and$libresoc.v:133535$5455_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + cell $and $and$libresoc.v:133536$5456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:133536$5456_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + cell $and $and$libresoc.v:133538$5458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:133538$5458_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:133517$5437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:133517$5437_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:133520$5440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:133520$5440_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:133521$5441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:133521$5441_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:133523$5443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:133523$5443_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:133526$5446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:133526$5446_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:133528$5448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:133528$5448_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:133531$5451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:133531$5451_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:133534$5454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:133534$5454_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + cell $not $not$libresoc.v:133537$5457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:133537$5457_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + cell $not $not$libresoc.v:133539$5459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:133539$5459_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:133541$5461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:133541$5461_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:133516$5436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $or$libresoc.v:133516$5436_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:133519$5439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:133519$5439_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:133522$5442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $or$libresoc.v:133522$5442_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:133525$5445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:133525$5445_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:133527$5447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \$27 + connect \Y $or$libresoc.v:133527$5447_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:133530$5450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:133530$5450_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:133533$5453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$35 + connect \B \$37 + connect \Y $or$libresoc.v:133533$5453_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:133540$5460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:133540$5460_Y + end + attribute \src "libresoc.v:133401.7-133401.20" + process $proc$libresoc.v:133401$5511 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133465.14-133465.44" + process $proc$libresoc.v:133465$5512 + assign { } { } + assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \f_badaddr_o $1\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:133472.7-133472.27" + process $proc$libresoc.v:133472$5513 + assign { } { } + assign $1\f_fetch_err_o[0:0] 1'0 + sync always + sync init + update \f_fetch_err_o $1\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:133486.14-133486.42" + process $proc$libresoc.v:133486$5514 + assign { } { } + assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus__adr $1\ibus__adr[44:0] + end + attribute \src "libresoc.v:133491.7-133491.23" + process $proc$libresoc.v:133491$5515 + assign { } { } + assign $1\ibus__cyc[0:0] 1'0 + sync always + sync init + update \ibus__cyc $1\ibus__cyc[0:0] + end + attribute \src "libresoc.v:133500.13-133500.30" + process $proc$libresoc.v:133500$5516 + assign { } { } + assign $1\ibus__sel[7:0] 8'00000000 + sync always + sync init + update \ibus__sel $1\ibus__sel[7:0] + end + attribute \src "libresoc.v:133505.7-133505.23" + process $proc$libresoc.v:133505$5517 + assign { } { } + assign $1\ibus__stb[0:0] 1'0 + sync always + sync init + update \ibus__stb $1\ibus__stb[0:0] + end + attribute \src "libresoc.v:133509.14-133509.47" + process $proc$libresoc.v:133509$5518 + assign { } { } + assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus_rdata $1\ibus_rdata[63:0] + end + attribute \src "libresoc.v:133542.3-133543.39" + process $proc$libresoc.v:133542$5462 + assign { } { } + assign $0\f_badaddr_o[44:0] \f_badaddr_o$next + sync posedge \clk + update \f_badaddr_o $0\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:133544.3-133545.43" + process $proc$libresoc.v:133544$5463 + assign { } { } + assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next + sync posedge \clk + update \f_fetch_err_o $0\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:133546.3-133547.35" + process $proc$libresoc.v:133546$5464 + assign { } { } + assign $0\ibus__adr[44:0] \ibus__adr$next + sync posedge \clk + update \ibus__adr $0\ibus__adr[44:0] + end + attribute \src "libresoc.v:133548.3-133549.37" + process $proc$libresoc.v:133548$5465 + assign { } { } + assign $0\ibus_rdata[63:0] \ibus_rdata$next + sync posedge \clk + update \ibus_rdata $0\ibus_rdata[63:0] + end + attribute \src "libresoc.v:133550.3-133551.35" + process $proc$libresoc.v:133550$5466 + assign { } { } + assign $0\ibus__sel[7:0] \ibus__sel$next + sync posedge \clk + update \ibus__sel $0\ibus__sel[7:0] + end + attribute \src "libresoc.v:133552.3-133553.35" + process $proc$libresoc.v:133552$5467 + assign { } { } + assign $0\ibus__stb[0:0] \ibus__stb$next + sync posedge \clk + update \ibus__stb $0\ibus__stb[0:0] + end + attribute \src "libresoc.v:133554.3-133555.35" + process $proc$libresoc.v:133554$5468 + assign { } { } + assign $0\ibus__cyc[0:0] \ibus__cyc$next + sync posedge \clk + update \ibus__cyc $0\ibus__cyc[0:0] + end + attribute \src "libresoc.v:133556.3-133583.6" + process $proc$libresoc.v:133556$5469 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__cyc$next[0:0]$5470 $4\ibus__cyc$next[0:0]$5474 + attribute \src "libresoc.v:133557.5-133557.29" + switch \initial + attribute \src "libresoc.v:133557.9-133557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 1'1 assign { } { } - assign $1\rc[0:0] 1'0 + assign $1\ibus__cyc$next[0:0]$5471 $2\ibus__cyc$next[0:0]$5472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$3 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__cyc$next[0:0]$5472 $3\ibus__cyc$next[0:0]$5473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$5473 1'0 + case + assign $3\ibus__cyc$next[0:0]$5473 \ibus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__cyc$next[0:0]$5472 1'1 + case + assign $2\ibus__cyc$next[0:0]$5472 \ibus__cyc + end case - assign $1\rc[0:0] 1'0 + assign $1\ibus__cyc$next[0:0]$5471 \ibus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__cyc$next[0:0]$5474 1'0 + case + assign $4\ibus__cyc$next[0:0]$5474 $1\ibus__cyc$next[0:0]$5471 end sync always - update \rc $0\rc[0:0] + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5470 end - attribute \src "libresoc.v:134092.3-134110.6" - process $proc$libresoc.v:134092$5102 + attribute \src "libresoc.v:133584.3-133611.6" + process $proc$libresoc.v:133584$5475 assign { } { } assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:134093.5-134093.29" + assign { } { } + assign $0\ibus__stb$next[0:0]$5476 $4\ibus__stb$next[0:0]$5480 + attribute \src "libresoc.v:133585.5-133585.29" switch \initial - attribute \src "libresoc.v:134093.9-134093.17" + attribute \src "libresoc.v:133585.9-133585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'1 assign { } { } - assign $1\rc_ok[0:0] 1'1 + assign $1\ibus__stb$next[0:0]$5477 $2\ibus__stb$next[0:0]$5478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$13 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__stb$next[0:0]$5478 $3\ibus__stb$next[0:0]$5479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$5479 1'0 + case + assign $3\ibus__stb$next[0:0]$5479 \ibus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__stb$next[0:0]$5478 1'1 + case + assign $2\ibus__stb$next[0:0]$5478 \ibus__stb + end + case + assign $1\ibus__stb$next[0:0]$5477 \ibus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 1'1 assign { } { } - assign $1\rc_ok[0:0] 1'1 + assign $4\ibus__stb$next[0:0]$5480 1'0 + case + assign $4\ibus__stb$next[0:0]$5480 $1\ibus__stb$next[0:0]$5477 + end + sync always + update \ibus__stb$next $0\ibus__stb$next[0:0]$5476 + end + attribute \src "libresoc.v:133612.3-133639.6" + process $proc$libresoc.v:133612$5481 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__sel$next[7:0]$5482 $4\ibus__sel$next[7:0]$5486 + attribute \src "libresoc.v:133613.5-133613.29" + switch \initial + attribute \src "libresoc.v:133613.9-133613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 1'1 assign { } { } - assign $1\rc_ok[0:0] 1'1 + assign $1\ibus__sel$next[7:0]$5483 $2\ibus__sel$next[7:0]$5484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$23 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__sel$next[7:0]$5484 $3\ibus__sel$next[7:0]$5485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$5485 8'00000000 + case + assign $3\ibus__sel$next[7:0]$5485 \ibus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__sel$next[7:0]$5484 8'11111111 + case + assign $2\ibus__sel$next[7:0]$5484 \ibus__sel + end case - assign $1\rc_ok[0:0] 1'0 + assign $1\ibus__sel$next[7:0]$5483 \ibus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__sel$next[7:0]$5486 8'00000000 + case + assign $4\ibus__sel$next[7:0]$5486 $1\ibus__sel$next[7:0]$5483 end sync always - update \rc_ok $0\rc_ok[0:0] + update \ibus__sel$next $0\ibus__sel$next[7:0]$5482 + end + attribute \src "libresoc.v:133640.3-133664.6" + process $proc$libresoc.v:133640$5487 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus_rdata$next[63:0]$5488 $4\ibus_rdata$next[63:0]$5492 + attribute \src "libresoc.v:133641.5-133641.29" + switch \initial + attribute \src "libresoc.v:133641.9-133641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus_rdata$next[63:0]$5489 $2\ibus_rdata$next[63:0]$5490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$33 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus_rdata$next[63:0]$5490 $3\ibus_rdata$next[63:0]$5491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$5491 \ibus__dat_r + case + assign $3\ibus_rdata$next[63:0]$5491 \ibus_rdata + end + case + assign $2\ibus_rdata$next[63:0]$5490 \ibus_rdata + end + case + assign $1\ibus_rdata$next[63:0]$5489 \ibus_rdata + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus_rdata$next[63:0]$5492 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\ibus_rdata$next[63:0]$5492 $1\ibus_rdata$next[63:0]$5489 + end + sync always + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5488 + end + attribute \src "libresoc.v:133665.3-133687.6" + process $proc$libresoc.v:133665$5493 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__adr$next[44:0]$5494 $3\ibus__adr$next[44:0]$5497 + attribute \src "libresoc.v:133666.5-133666.29" + switch \initial + attribute \src "libresoc.v:133666.9-133666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__adr$next[44:0]$5495 $2\ibus__adr$next[44:0]$5496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$43 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\ibus__adr$next[44:0]$5496 \ibus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__adr$next[44:0]$5496 \a_pc_i [47:3] + case + assign $2\ibus__adr$next[44:0]$5496 \ibus__adr + end + case + assign $1\ibus__adr$next[44:0]$5495 \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__adr$next[44:0]$5497 45'000000000000000000000000000000000000000000000 + case + assign $3\ibus__adr$next[44:0]$5497 $1\ibus__adr$next[44:0]$5495 + end + sync always + update \ibus__adr$next $0\ibus__adr$next[44:0]$5494 + end + attribute \src "libresoc.v:133688.3-133710.6" + process $proc$libresoc.v:133688$5498 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_fetch_err_o$next[0:0]$5499 $3\f_fetch_err_o$next[0:0]$5502 + attribute \src "libresoc.v:133689.5-133689.29" + switch \initial + attribute \src "libresoc.v:133689.9-133689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$5500 $2\f_fetch_err_o$next[0:0]$5501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$47 \$45 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5501 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5501 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$5501 \f_fetch_err_o + end + case + assign $1\f_fetch_err_o$next[0:0]$5500 \f_fetch_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\f_fetch_err_o$next[0:0]$5502 1'0 + case + assign $3\f_fetch_err_o$next[0:0]$5502 $1\f_fetch_err_o$next[0:0]$5500 + end + sync always + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5499 + end + attribute \src "libresoc.v:133711.3-133730.6" + process $proc$libresoc.v:133711$5503 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_badaddr_o$next[44:0]$5504 $3\f_badaddr_o$next[44:0]$5507 + attribute \src "libresoc.v:133712.5-133712.29" + switch \initial + attribute \src "libresoc.v:133712.9-133712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_badaddr_o$next[44:0]$5505 $2\f_badaddr_o$next[44:0]$5506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$51 \$49 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$5506 \ibus__adr + case + assign $2\f_badaddr_o$next[44:0]$5506 \f_badaddr_o + end + case + assign $1\f_badaddr_o$next[44:0]$5505 \f_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\f_badaddr_o$next[44:0]$5507 45'000000000000000000000000000000000000000000000 + case + assign $3\f_badaddr_o$next[44:0]$5507 $1\f_badaddr_o$next[44:0]$5505 + end + sync always + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5504 + end + attribute \src "libresoc.v:133731.3-133740.6" + process $proc$libresoc.v:133731$5508 + assign { } { } + assign { } { } + assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] + attribute \src "libresoc.v:133732.5-133732.29" + switch \initial + attribute \src "libresoc.v:133732.9-133732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_busy_o[0:0] \ibus__cyc + case + assign $1\a_busy_o[0:0] 1'0 + end + sync always + update \a_busy_o $0\a_busy_o[0:0] + end + attribute \src "libresoc.v:133741.3-133758.6" + process $proc$libresoc.v:133741$5509 + assign { } { } + assign { } { } + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "libresoc.v:133742.5-133742.29" + switch \initial + attribute \src "libresoc.v:133742.9-133742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_busy_o[0:0] $2\f_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_busy_o[0:0] \ibus__cyc + end + case + assign $1\f_busy_o[0:0] 1'0 + end + sync always + update \f_busy_o $0\f_busy_o[0:0] + end + attribute \src "libresoc.v:133759.3-133776.6" + process $proc$libresoc.v:133759$5510 + assign { } { } + assign { } { } + assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] + attribute \src "libresoc.v:133760.5-133760.29" + switch \initial + attribute \src "libresoc.v:133760.9-133760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_instr_o[63:0] $2\f_instr_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_instr_o[63:0] \ibus_rdata + end + case + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \f_instr_o $0\f_instr_o[63:0] end + connect \$9 $or$libresoc.v:133516$5436_Y + connect \$11 $not$libresoc.v:133517$5437_Y + connect \$13 $and$libresoc.v:133518$5438_Y + connect \$15 $or$libresoc.v:133519$5439_Y + connect \$17 $not$libresoc.v:133520$5440_Y + connect \$1 $not$libresoc.v:133521$5441_Y + connect \$19 $or$libresoc.v:133522$5442_Y + connect \$21 $not$libresoc.v:133523$5443_Y + connect \$23 $and$libresoc.v:133524$5444_Y + connect \$25 $or$libresoc.v:133525$5445_Y + connect \$27 $not$libresoc.v:133526$5446_Y + connect \$29 $or$libresoc.v:133527$5447_Y + connect \$31 $not$libresoc.v:133528$5448_Y + connect \$33 $and$libresoc.v:133529$5449_Y + connect \$35 $or$libresoc.v:133530$5450_Y + connect \$37 $not$libresoc.v:133531$5451_Y + connect \$3 $and$libresoc.v:133532$5452_Y + connect \$39 $or$libresoc.v:133533$5453_Y + connect \$41 $not$libresoc.v:133534$5454_Y + connect \$43 $and$libresoc.v:133535$5455_Y + connect \$45 $and$libresoc.v:133536$5456_Y + connect \$47 $not$libresoc.v:133537$5457_Y + connect \$49 $and$libresoc.v:133538$5458_Y + connect \$51 $not$libresoc.v:133539$5459_Y + connect \$5 $or$libresoc.v:133540$5460_Y + connect \$7 $not$libresoc.v:133541$5461_Y + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 end -attribute \src "libresoc.v:134115.1-134169.10" +attribute \src "libresoc.v:133783.1-133943.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.in1_svdec" attribute \generator "nMigen" -module \dec_rc$205 - attribute \src "libresoc.v:134116.7-134116.20" +module \in1_svdec + attribute \src "libresoc.v:133878.3-133894.6" + wire width 3 $0\extra3_idx0[2:0] + attribute \src "libresoc.v:133895.3-133911.6" + wire width 3 $0\extra3_idx1[2:0] + attribute \src "libresoc.v:133912.3-133928.6" + wire width 3 $0\extra3_idx2[2:0] + attribute \src "libresoc.v:133784.7-133784.20" wire $0\initial[0:0] - attribute \src "libresoc.v:134131.3-134149.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:134150.3-134168.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:134131.3-134149.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:134150.3-134168.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" - wire input 3 \Rc - attribute \src "libresoc.v:134116.7-134116.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" + attribute \src "libresoc.v:133929.3-133940.6" + wire width 7 $0\reg_out[6:0] + attribute \src "libresoc.v:133819.3-133877.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:133878.3-133894.6" + wire width 3 $1\extra3_idx0[2:0] + attribute \src "libresoc.v:133895.3-133911.6" + wire width 3 $1\extra3_idx1[2:0] + attribute \src "libresoc.v:133912.3-133928.6" + wire width 3 $1\extra3_idx2[2:0] + attribute \src "libresoc.v:133929.3-133940.6" + wire width 7 $1\reg_out[6:0] + attribute \src "libresoc.v:133819.3-133877.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:133878.3-133894.6" + wire width 3 $2\extra3_idx0[2:0] + attribute \src "libresoc.v:133895.3-133911.6" + wire width 3 $2\extra3_idx1[2:0] + attribute \src "libresoc.v:133912.3-133928.6" + wire width 3 $2\extra3_idx2[2:0] + attribute \src "libresoc.v:133819.3-133877.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:133819.3-133877.6" + wire width 3 $3\spec[2:0] + attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:134116.7-134116.20" - process $proc$libresoc.v:134116$5106 + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" + wire width 2 input 1 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" + wire width 9 input 6 \extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57" + wire width 3 \extra3_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60" + wire width 3 \extra3_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63" + wire width 3 \extra3_idx2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" + wire width 3 input 5 \idx + attribute \src "libresoc.v:133784.7-133784.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85" + wire output 3 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83" + wire width 5 input 2 \reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84" + wire width 7 output 4 \reg_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25" + wire width 3 \spec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:101" + wire width 2 \spec_aug + attribute \src "libresoc.v:133784.7-133784.20" + process $proc$libresoc.v:133784$5524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134131.3-134149.6" - process $proc$libresoc.v:134131$5104 + attribute \src "libresoc.v:133819.3-133877.6" + process $proc$libresoc.v:133819$5519 assign { } { } assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:134132.5-134132.29" + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:133820.5-133820.29" switch \initial - attribute \src "libresoc.v:134132.9-134132.17" + attribute \src "libresoc.v:133820.9-133820.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\rc[0:0] \Rc + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra3_idx0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra3_idx1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra3_idx2 + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:133878.3-133894.6" + process $proc$libresoc.v:133878$5520 + assign { } { } + assign { } { } + assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0] + attribute \src "libresoc.v:133879.5-133879.29" + switch \initial + attribute \src "libresoc.v:133879.9-133879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 2'10 assign { } { } - assign $1\rc[0:0] 1'1 + assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\extra3_idx0[2:0] \extra [8:6] + case + assign $2\extra3_idx0[2:0] 3'000 + end + case + assign $1\extra3_idx0[2:0] 3'000 + end + sync always + update \extra3_idx0 $0\extra3_idx0[2:0] + end + attribute \src "libresoc.v:133895.3-133911.6" + process $proc$libresoc.v:133895$5521 + assign { } { } + assign { } { } + assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0] + attribute \src "libresoc.v:133896.5-133896.29" + switch \initial + attribute \src "libresoc.v:133896.9-133896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 2'10 assign { } { } - assign $1\rc[0:0] 1'0 + assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\extra3_idx1[2:0] \extra [5:3] + case + assign $2\extra3_idx1[2:0] 3'000 + end case - assign $1\rc[0:0] 1'0 + assign $1\extra3_idx1[2:0] 3'000 end sync always - update \rc $0\rc[0:0] + update \extra3_idx1 $0\extra3_idx1[2:0] end - attribute \src "libresoc.v:134150.3-134168.6" - process $proc$libresoc.v:134150$5105 + attribute \src "libresoc.v:133912.3-133928.6" + process $proc$libresoc.v:133912$5522 assign { } { } assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:134151.5-134151.29" + assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0] + attribute \src "libresoc.v:133913.5-133913.29" switch \initial - attribute \src "libresoc.v:134151.9-134151.17" + attribute \src "libresoc.v:133913.9-133913.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\rc_ok[0:0] 1'1 + assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\extra3_idx2[2:0] \extra [2:0] + case + assign $2\extra3_idx2[2:0] 3'000 + end + case + assign $1\extra3_idx2[2:0] 3'000 + end + sync always + update \extra3_idx2 $0\extra3_idx2[2:0] + end + attribute \src "libresoc.v:133929.3-133940.6" + process $proc$libresoc.v:133929$5523 + assign { } { } + assign $0\reg_out[6:0] $1\reg_out[6:0] + attribute \src "libresoc.v:133930.5-133930.29" + switch \initial + attribute \src "libresoc.v:133930.9-133930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:105" + switch \isvec attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 1'1 assign { } { } - assign $1\rc_ok[0:0] 1'1 + assign $1\reg_out[6:0] { \reg_in \spec_aug } attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 case - assign $1\rc_ok[0:0] 1'0 + assign { } { } + assign $1\reg_out[6:0] { \spec_aug \reg_in } end sync always - update \rc_ok $0\rc_ok[0:0] + update \reg_out $0\reg_out[6:0] end + connect \spec_aug \spec [1:0] + connect \isvec \spec [2] end -attribute \src "libresoc.v:134173.1-135413.10" +attribute \src "libresoc.v:133947.1-134107.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.in2_svdec" attribute \generator "nMigen" -module \div0 - attribute \src "libresoc.v:134970.3-134971.25" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5246 - attribute \src "libresoc.v:134942.3-134943.75" - wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 13 $0\alu_div0_logical_op__fn_unit$next[12:0]$5247 - attribute \src "libresoc.v:134912.3-134913.73" - wire width 13 $0\alu_div0_logical_op__fn_unit[12:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5248 - attribute \src "libresoc.v:134914.3-134915.87" - wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5249 - attribute \src "libresoc.v:134916.3-134917.83" - wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5250 - attribute \src "libresoc.v:134930.3-134931.81" - wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5251 - attribute \src "libresoc.v:134944.3-134945.67" - wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5252 - attribute \src "libresoc.v:134910.3-134911.77" - wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__invert_in$next[0:0]$5253 - attribute \src "libresoc.v:134926.3-134927.77" - wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__invert_out$next[0:0]$5254 - attribute \src "libresoc.v:134932.3-134933.79" - wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5255 - attribute \src "libresoc.v:134938.3-134939.75" - wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__is_signed$next[0:0]$5256 - attribute \src "libresoc.v:134940.3-134941.77" - wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5257 - attribute \src "libresoc.v:134922.3-134923.71" - wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5258 - attribute \src "libresoc.v:134924.3-134925.71" - wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__output_carry$next[0:0]$5259 - attribute \src "libresoc.v:134936.3-134937.83" - wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5260 - attribute \src "libresoc.v:134920.3-134921.71" - wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5261 - attribute \src "libresoc.v:134918.3-134919.71" - wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5262 - attribute \src "libresoc.v:134934.3-134935.77" - wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $0\alu_div0_logical_op__zero_a$next[0:0]$5263 - attribute \src "libresoc.v:134928.3-134929.71" - wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:134968.3-134969.40" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:135323.3-135331.6" - wire $0\alu_l_r_alu$next[0:0]$5333 - attribute \src "libresoc.v:134884.3-134885.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:135314.3-135322.6" - wire $0\alui_l_r_alui$next[0:0]$5330 - attribute \src "libresoc.v:134886.3-134887.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:135196.3-135217.6" - wire width 64 $0\data_r0__o$next[63:0]$5289 - attribute \src "libresoc.v:134906.3-134907.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:135196.3-135217.6" - wire $0\data_r0__o_ok$next[0:0]$5290 - attribute \src "libresoc.v:134908.3-134909.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:135218.3-135239.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$5297 - attribute \src "libresoc.v:134902.3-134903.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:135218.3-135239.6" - wire $0\data_r1__cr_a_ok$next[0:0]$5298 - attribute \src "libresoc.v:134904.3-134905.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:135240.3-135261.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$5305 - attribute \src "libresoc.v:134898.3-134899.47" - wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:135240.3-135261.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$5306 - attribute \src "libresoc.v:134900.3-134901.53" - wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:135262.3-135283.6" - wire $0\data_r3__xer_so$next[0:0]$5313 - attribute \src "libresoc.v:134894.3-134895.47" - wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:135262.3-135283.6" - wire $0\data_r3__xer_so_ok$next[0:0]$5314 - attribute \src "libresoc.v:134896.3-134897.53" - wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:135332.3-135341.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:135342.3-135351.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:135352.3-135361.6" - wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:135362.3-135371.6" - wire $0\dest4_o[0:0] - attribute \src "libresoc.v:134174.7-134174.20" +module \in2_svdec + attribute \src "libresoc.v:134042.3-134058.6" + wire width 3 $0\extra3_idx0[2:0] + attribute \src "libresoc.v:134059.3-134075.6" + wire width 3 $0\extra3_idx1[2:0] + attribute \src "libresoc.v:134076.3-134092.6" + wire width 3 $0\extra3_idx2[2:0] + attribute \src "libresoc.v:133948.7-133948.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135112.3-135120.6" - wire $0\opc_l_r_opc$next[0:0]$5231 - attribute \src "libresoc.v:134954.3-134955.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:135103.3-135111.6" - wire $0\opc_l_s_opc$next[0:0]$5228 - attribute \src "libresoc.v:134956.3-134957.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:135372.3-135380.6" - wire width 4 $0\prev_wr_go$next[3:0]$5340 - attribute \src "libresoc.v:134966.3-134967.37" - wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:135057.3-135066.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:135148.3-135156.6" - wire width 4 $0\req_l_r_req$next[3:0]$5243 - attribute \src "libresoc.v:134946.3-134947.39" - wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:135139.3-135147.6" - wire width 4 $0\req_l_s_req$next[3:0]$5240 - attribute \src "libresoc.v:134948.3-134949.39" - wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:135076.3-135084.6" - wire $0\rok_l_r_rdok$next[0:0]$5219 - attribute \src "libresoc.v:134962.3-134963.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:135067.3-135075.6" - wire $0\rok_l_s_rdok$next[0:0]$5216 - attribute \src "libresoc.v:134964.3-134965.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:135094.3-135102.6" - wire $0\rst_l_r_rst$next[0:0]$5225 - attribute \src "libresoc.v:134958.3-134959.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:135085.3-135093.6" - wire $0\rst_l_s_rst$next[0:0]$5222 - attribute \src "libresoc.v:134960.3-134961.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:135130.3-135138.6" - wire width 3 $0\src_l_r_src$next[2:0]$5237 - attribute \src "libresoc.v:134950.3-134951.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:135121.3-135129.6" - wire width 3 $0\src_l_s_src$next[2:0]$5234 - attribute \src "libresoc.v:134952.3-134953.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:135284.3-135293.6" - wire width 64 $0\src_r0$next[63:0]$5321 - attribute \src "libresoc.v:134892.3-134893.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:135294.3-135303.6" - wire width 64 $0\src_r1$next[63:0]$5324 - attribute \src "libresoc.v:134890.3-134891.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:135304.3-135313.6" - wire $0\src_r2$next[0:0]$5327 - attribute \src "libresoc.v:134888.3-134889.29" - wire $0\src_r2[0:0] - attribute \src "libresoc.v:134304.7-134304.24" - wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5264 - attribute \src "libresoc.v:134314.13-134314.49" - wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 13 $1\alu_div0_logical_op__fn_unit$next[12:0]$5265 - attribute \src "libresoc.v:134332.14-134332.53" - wire width 13 $1\alu_div0_logical_op__fn_unit[12:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5266 - attribute \src "libresoc.v:134336.14-134336.72" - wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5267 - attribute \src "libresoc.v:134340.7-134340.47" - wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5268 - attribute \src "libresoc.v:134348.13-134348.52" - wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5269 - attribute \src "libresoc.v:134352.14-134352.47" - wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5270 - attribute \src "libresoc.v:134430.13-134430.51" - wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__invert_in$next[0:0]$5271 - attribute \src "libresoc.v:134434.7-134434.44" - wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__invert_out$next[0:0]$5272 - attribute \src "libresoc.v:134438.7-134438.45" - wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5273 - attribute \src "libresoc.v:134442.7-134442.43" - wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__is_signed$next[0:0]$5274 - attribute \src "libresoc.v:134446.7-134446.44" - wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5275 - attribute \src "libresoc.v:134450.7-134450.41" - wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5276 - attribute \src "libresoc.v:134454.7-134454.41" - wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__output_carry$next[0:0]$5277 - attribute \src "libresoc.v:134458.7-134458.47" - wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5278 - attribute \src "libresoc.v:134462.7-134462.41" - wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5279 - attribute \src "libresoc.v:134466.7-134466.41" - wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5280 - attribute \src "libresoc.v:134470.7-134470.44" - wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire $1\alu_div0_logical_op__zero_a$next[0:0]$5281 - attribute \src "libresoc.v:134474.7-134474.41" - wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:134500.7-134500.26" - wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:135323.3-135331.6" - wire $1\alu_l_r_alu$next[0:0]$5334 - attribute \src "libresoc.v:134508.7-134508.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:135314.3-135322.6" - wire $1\alui_l_r_alui$next[0:0]$5331 - attribute \src "libresoc.v:134520.7-134520.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:135196.3-135217.6" - wire width 64 $1\data_r0__o$next[63:0]$5291 - attribute \src "libresoc.v:134554.14-134554.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:135196.3-135217.6" - wire $1\data_r0__o_ok$next[0:0]$5292 - attribute \src "libresoc.v:134558.7-134558.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:135218.3-135239.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$5299 - attribute \src "libresoc.v:134562.13-134562.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:135218.3-135239.6" - wire $1\data_r1__cr_a_ok$next[0:0]$5300 - attribute \src "libresoc.v:134566.7-134566.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:135240.3-135261.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$5307 - attribute \src "libresoc.v:134570.13-134570.35" - wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:135240.3-135261.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$5308 - attribute \src "libresoc.v:134574.7-134574.32" - wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:135262.3-135283.6" - wire $1\data_r3__xer_so$next[0:0]$5315 - attribute \src "libresoc.v:134578.7-134578.29" - wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:135262.3-135283.6" - wire $1\data_r3__xer_so_ok$next[0:0]$5316 - attribute \src "libresoc.v:134582.7-134582.32" - wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:135332.3-135341.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:135342.3-135351.6" - wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:135352.3-135361.6" - wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:135362.3-135371.6" - wire $1\dest4_o[0:0] - attribute \src "libresoc.v:135112.3-135120.6" - wire $1\opc_l_r_opc$next[0:0]$5232 - attribute \src "libresoc.v:134602.7-134602.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:135103.3-135111.6" - wire $1\opc_l_s_opc$next[0:0]$5229 - attribute \src "libresoc.v:134606.7-134606.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:135372.3-135380.6" - wire width 4 $1\prev_wr_go$next[3:0]$5341 - attribute \src "libresoc.v:134738.13-134738.30" - wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:135057.3-135066.6" - wire $1\req_done[0:0] - attribute \src "libresoc.v:135148.3-135156.6" - wire width 4 $1\req_l_r_req$next[3:0]$5244 - attribute \src "libresoc.v:134746.13-134746.31" - wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:135139.3-135147.6" - wire width 4 $1\req_l_s_req$next[3:0]$5241 - attribute \src "libresoc.v:134750.13-134750.31" - wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:135076.3-135084.6" - wire $1\rok_l_r_rdok$next[0:0]$5220 - attribute \src "libresoc.v:134762.7-134762.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:135067.3-135075.6" - wire $1\rok_l_s_rdok$next[0:0]$5217 - attribute \src "libresoc.v:134766.7-134766.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:135094.3-135102.6" - wire $1\rst_l_r_rst$next[0:0]$5226 - attribute \src "libresoc.v:134770.7-134770.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:135085.3-135093.6" - wire $1\rst_l_s_rst$next[0:0]$5223 - attribute \src "libresoc.v:134774.7-134774.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:135130.3-135138.6" - wire width 3 $1\src_l_r_src$next[2:0]$5238 - attribute \src "libresoc.v:134788.13-134788.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:135121.3-135129.6" - wire width 3 $1\src_l_s_src$next[2:0]$5235 - attribute \src "libresoc.v:134792.13-134792.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:135284.3-135293.6" - wire width 64 $1\src_r0$next[63:0]$5322 - attribute \src "libresoc.v:134800.14-134800.43" - wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:135294.3-135303.6" - wire width 64 $1\src_r1$next[63:0]$5325 - attribute \src "libresoc.v:134804.14-134804.43" - wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:135304.3-135313.6" - wire $1\src_r2$next[0:0]$5328 - attribute \src "libresoc.v:134808.7-134808.20" - wire $1\src_r2[0:0] - attribute \src "libresoc.v:135157.3-135195.6" - wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5282 - attribute \src "libresoc.v:135157.3-135195.6" - wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5283 - attribute \src "libresoc.v:135157.3-135195.6" - wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5284 - attribute \src "libresoc.v:135157.3-135195.6" - wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5285 - attribute \src "libresoc.v:135157.3-135195.6" - wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5286 - attribute \src "libresoc.v:135157.3-135195.6" - wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5287 - attribute \src "libresoc.v:135196.3-135217.6" - wire width 64 $2\data_r0__o$next[63:0]$5293 - attribute \src "libresoc.v:135196.3-135217.6" - wire $2\data_r0__o_ok$next[0:0]$5294 - attribute \src "libresoc.v:135218.3-135239.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$5301 - attribute \src "libresoc.v:135218.3-135239.6" - wire $2\data_r1__cr_a_ok$next[0:0]$5302 - attribute \src "libresoc.v:135240.3-135261.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$5309 - attribute \src "libresoc.v:135240.3-135261.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$5310 - attribute \src "libresoc.v:135262.3-135283.6" - wire $2\data_r3__xer_so$next[0:0]$5317 - attribute \src "libresoc.v:135262.3-135283.6" - wire $2\data_r3__xer_so_ok$next[0:0]$5318 - attribute \src "libresoc.v:135196.3-135217.6" - wire $3\data_r0__o_ok$next[0:0]$5295 - attribute \src "libresoc.v:135218.3-135239.6" - wire $3\data_r1__cr_a_ok$next[0:0]$5303 - attribute \src "libresoc.v:135240.3-135261.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$5311 - attribute \src "libresoc.v:135262.3-135283.6" - wire $3\data_r3__xer_so_ok$next[0:0]$5319 - attribute \src "libresoc.v:134823.19-134823.133" - wire width 3 $and$libresoc.v:134823$5109_Y - attribute \src "libresoc.v:134825.19-134825.115" - wire width 3 $and$libresoc.v:134825$5111_Y - attribute \src "libresoc.v:134826.18-134826.110" - wire $and$libresoc.v:134826$5112_Y - attribute \src "libresoc.v:134827.19-134827.125" - wire $and$libresoc.v:134827$5113_Y - attribute \src "libresoc.v:134828.19-134828.125" - wire $and$libresoc.v:134828$5114_Y - attribute \src "libresoc.v:134829.19-134829.125" - wire $and$libresoc.v:134829$5115_Y - attribute \src "libresoc.v:134830.19-134830.125" - wire $and$libresoc.v:134830$5116_Y - attribute \src "libresoc.v:134831.19-134831.149" - wire width 4 $and$libresoc.v:134831$5117_Y - attribute \src "libresoc.v:134832.19-134832.121" - wire width 4 $and$libresoc.v:134832$5118_Y - attribute \src "libresoc.v:134833.19-134833.127" - wire $and$libresoc.v:134833$5119_Y - attribute \src "libresoc.v:134834.19-134834.127" - wire $and$libresoc.v:134834$5120_Y - attribute \src "libresoc.v:134835.19-134835.127" - wire $and$libresoc.v:134835$5121_Y - attribute \src "libresoc.v:134836.19-134836.127" - wire $and$libresoc.v:134836$5122_Y - attribute \src "libresoc.v:134838.18-134838.98" - wire $and$libresoc.v:134838$5124_Y - attribute \src "libresoc.v:134840.18-134840.100" - wire $and$libresoc.v:134840$5126_Y - attribute \src "libresoc.v:134841.18-134841.160" - wire width 4 $and$libresoc.v:134841$5127_Y - attribute \src "libresoc.v:134843.18-134843.119" - wire width 4 $and$libresoc.v:134843$5129_Y - attribute \src "libresoc.v:134846.17-134846.123" - wire $and$libresoc.v:134846$5132_Y - attribute \src "libresoc.v:134847.18-134847.116" - wire $and$libresoc.v:134847$5133_Y - attribute \src "libresoc.v:134852.18-134852.113" - wire $and$libresoc.v:134852$5138_Y - attribute \src "libresoc.v:134853.18-134853.125" - wire width 4 $and$libresoc.v:134853$5139_Y - attribute \src "libresoc.v:134855.18-134855.112" - wire $and$libresoc.v:134855$5141_Y - attribute \src "libresoc.v:134857.18-134857.126" - wire $and$libresoc.v:134857$5143_Y - attribute \src "libresoc.v:134858.18-134858.126" - wire $and$libresoc.v:134858$5144_Y - attribute \src "libresoc.v:134859.18-134859.117" - wire $and$libresoc.v:134859$5145_Y - attribute \src "libresoc.v:134865.18-134865.130" - wire $and$libresoc.v:134865$5151_Y - attribute \src "libresoc.v:134866.18-134866.124" - wire width 4 $and$libresoc.v:134866$5152_Y - attribute \src "libresoc.v:134868.18-134868.116" - wire $and$libresoc.v:134868$5154_Y - attribute \src "libresoc.v:134869.18-134869.119" - wire $and$libresoc.v:134869$5155_Y - attribute \src "libresoc.v:134870.18-134870.121" - wire $and$libresoc.v:134870$5156_Y - attribute \src "libresoc.v:134871.18-134871.121" - wire $and$libresoc.v:134871$5157_Y - attribute \src "libresoc.v:134881.18-134881.134" - wire $and$libresoc.v:134881$5167_Y - attribute \src "libresoc.v:134882.18-134882.132" - wire $and$libresoc.v:134882$5168_Y - attribute \src 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"EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" + wire width 2 input 1 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" + wire width 9 input 6 \extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57" + wire width 3 \extra3_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60" + wire width 3 \extra3_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63" + wire width 3 \extra3_idx2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" + wire width 3 input 5 \idx + attribute \src "libresoc.v:133948.7-133948.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85" + wire output 3 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83" + wire width 5 input 2 \reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84" + wire width 7 output 4 \reg_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25" + wire width 3 \spec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:101" + wire width 2 \spec_aug + attribute \src "libresoc.v:133948.7-133948.20" + process $proc$libresoc.v:133948$5530 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133983.3-134041.6" + process $proc$libresoc.v:133983$5525 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:133984.5-133984.29" + switch \initial + attribute \src "libresoc.v:133984.9-133984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra3_idx0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra3_idx1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra3_idx2 + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:134042.3-134058.6" + process $proc$libresoc.v:134042$5526 + assign { } { } + assign { } { } + assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0] + attribute \src "libresoc.v:134043.5-134043.29" + switch \initial + attribute \src "libresoc.v:134043.9-134043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\extra3_idx0[2:0] \extra [8:6] + case + assign $2\extra3_idx0[2:0] 3'000 + end + case + assign $1\extra3_idx0[2:0] 3'000 + end + sync always + update \extra3_idx0 $0\extra3_idx0[2:0] + end + attribute \src "libresoc.v:134059.3-134075.6" + process $proc$libresoc.v:134059$5527 + assign { } { } + assign { } { } + assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0] + attribute \src "libresoc.v:134060.5-134060.29" + switch \initial + attribute \src "libresoc.v:134060.9-134060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\extra3_idx1[2:0] \extra [5:3] + case + assign $2\extra3_idx1[2:0] 3'000 + end + case + assign $1\extra3_idx1[2:0] 3'000 + end + sync always + update \extra3_idx1 $0\extra3_idx1[2:0] + end + attribute \src "libresoc.v:134076.3-134092.6" + process $proc$libresoc.v:134076$5528 + assign { } { } + assign { } { } + assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0] + attribute \src "libresoc.v:134077.5-134077.29" + switch \initial + attribute \src "libresoc.v:134077.9-134077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\extra3_idx2[2:0] \extra [2:0] + case + assign $2\extra3_idx2[2:0] 3'000 + end + case + assign $1\extra3_idx2[2:0] 3'000 + end + sync always + update \extra3_idx2 $0\extra3_idx2[2:0] + end + attribute \src "libresoc.v:134093.3-134104.6" + process $proc$libresoc.v:134093$5529 + assign { } { } + assign $0\reg_out[6:0] $1\reg_out[6:0] + attribute \src "libresoc.v:134094.5-134094.29" + switch \initial + attribute \src "libresoc.v:134094.9-134094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:105" + switch \isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_out[6:0] { \reg_in \spec_aug } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\reg_out[6:0] { \spec_aug \reg_in } + end + sync always + update \reg_out $0\reg_out[6:0] + end + connect \spec_aug \spec [1:0] + connect \isvec \spec [2] +end +attribute \src "libresoc.v:134111.1-134271.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.in3_svdec" +attribute \generator "nMigen" +module \in3_svdec + attribute \src "libresoc.v:134206.3-134222.6" + wire width 3 $0\extra3_idx0[2:0] + attribute \src "libresoc.v:134223.3-134239.6" + wire width 3 $0\extra3_idx1[2:0] + attribute \src "libresoc.v:134240.3-134256.6" + wire width 3 $0\extra3_idx2[2:0] + attribute \src "libresoc.v:134112.7-134112.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:134257.3-134268.6" + wire width 7 $0\reg_out[6:0] + attribute \src "libresoc.v:134147.3-134205.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:134206.3-134222.6" + wire width 3 $1\extra3_idx0[2:0] + attribute \src "libresoc.v:134223.3-134239.6" + wire width 3 $1\extra3_idx1[2:0] + attribute \src "libresoc.v:134240.3-134256.6" + wire width 3 $1\extra3_idx2[2:0] + attribute \src "libresoc.v:134257.3-134268.6" + wire width 7 $1\reg_out[6:0] + attribute \src "libresoc.v:134147.3-134205.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:134206.3-134222.6" + wire width 3 $2\extra3_idx0[2:0] + attribute \src "libresoc.v:134223.3-134239.6" + wire width 3 $2\extra3_idx1[2:0] + attribute \src "libresoc.v:134240.3-134256.6" + wire width 3 $2\extra3_idx2[2:0] + attribute \src "libresoc.v:134147.3-134205.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:134147.3-134205.6" + wire width 3 $3\spec[2:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" + wire width 2 input 1 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" + wire width 9 input 6 \extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57" + wire width 3 \extra3_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60" + wire width 3 \extra3_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63" + wire width 3 \extra3_idx2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" + wire width 3 input 5 \idx + attribute \src "libresoc.v:134112.7-134112.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85" + wire output 3 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83" + wire width 5 input 2 \reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84" + wire width 7 output 4 \reg_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25" + wire width 3 \spec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:101" + wire width 2 \spec_aug + attribute \src "libresoc.v:134112.7-134112.20" + process $proc$libresoc.v:134112$5536 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:134147.3-134205.6" + process $proc$libresoc.v:134147$5531 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:134148.5-134148.29" + switch \initial + attribute \src "libresoc.v:134148.9-134148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra3_idx0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra3_idx1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra3_idx2 + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:134206.3-134222.6" + process $proc$libresoc.v:134206$5532 + assign { } { } + assign { } { } + assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0] + attribute \src "libresoc.v:134207.5-134207.29" + switch \initial + attribute \src "libresoc.v:134207.9-134207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\extra3_idx0[2:0] \extra [8:6] + case + assign $2\extra3_idx0[2:0] 3'000 + end + case + assign $1\extra3_idx0[2:0] 3'000 + end + sync always + update \extra3_idx0 $0\extra3_idx0[2:0] + end + attribute \src "libresoc.v:134223.3-134239.6" + process $proc$libresoc.v:134223$5533 + assign { } { } + assign { } { } + assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0] + attribute \src "libresoc.v:134224.5-134224.29" + switch \initial + attribute \src "libresoc.v:134224.9-134224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\extra3_idx1[2:0] \extra [5:3] + case + assign $2\extra3_idx1[2:0] 3'000 + end + case + assign $1\extra3_idx1[2:0] 3'000 + end + sync always + update \extra3_idx1 $0\extra3_idx1[2:0] + end + attribute \src "libresoc.v:134240.3-134256.6" + process $proc$libresoc.v:134240$5534 + assign { } { } + assign { } { } + assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0] + attribute \src "libresoc.v:134241.5-134241.29" + switch \initial + attribute \src "libresoc.v:134241.9-134241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\extra3_idx2[2:0] \extra [2:0] + case + assign $2\extra3_idx2[2:0] 3'000 + end + case + assign $1\extra3_idx2[2:0] 3'000 + end + sync always + update \extra3_idx2 $0\extra3_idx2[2:0] + end + attribute \src "libresoc.v:134257.3-134268.6" + process $proc$libresoc.v:134257$5535 + assign { } { } + assign $0\reg_out[6:0] $1\reg_out[6:0] + attribute \src "libresoc.v:134258.5-134258.29" + switch \initial + attribute \src "libresoc.v:134258.9-134258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:105" + switch \isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_out[6:0] { \reg_in \spec_aug } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\reg_out[6:0] { \spec_aug \reg_in } + end + sync always + update \reg_out $0\reg_out[6:0] + end + connect \spec_aug \spec [1:0] + connect \isvec \spec [2] +end +attribute \src "libresoc.v:134275.1-134598.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" +attribute \generator "nMigen" +module \input + attribute \src "libresoc.v:134561.3-134572.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:134276.7-134276.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:134573.3-134591.6" + wire width 2 $0\xer_ca$23[1:0]$5540 + attribute \src "libresoc.v:134561.3-134572.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:134573.3-134591.6" + wire width 2 $1\xer_ca$23[1:0]$5541 + attribute \src "libresoc.v:134560.18-134560.100" + wire width 64 $not$libresoc.v:134560$5537_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_div0_logical_op__data_len + wire width 4 input 17 \alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_div0_logical_op__data_len$next + wire width 4 output 40 \alu_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -210676,29 +213045,47 @@ module \div0 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_div0_logical_op__fn_unit + wire width 13 input 2 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_div0_logical_op__fn_unit$next + wire width 13 output 25 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_div0_logical_op__imm_data__data + wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_div0_logical_op__imm_data__data$next + wire width 64 output 26 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__imm_data__ok + wire input 4 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__imm_data__ok$next + wire output 27 \alu_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_div0_logical_op__input_carry + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_div0_logical_op__input_carry$next + wire width 2 output 36 \alu_op__input_carry$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_div0_logical_op__insn + wire width 32 input 18 \alu_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_div0_logical_op__insn$next + wire width 32 output 41 \alu_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -210774,185 +213161,287 @@ module \div0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_div0_logical_op__insn_type + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_div0_logical_op__insn_type$next + wire width 7 output 24 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__invert_in + wire input 9 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__invert_in$next + wire output 32 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__invert_out + wire input 11 \alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__invert_out$next + wire output 34 \alu_op__invert_out$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__is_32bit + wire input 15 \alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__is_32bit$next + wire output 38 \alu_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__is_signed + wire input 16 \alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__is_signed$next + wire output 39 \alu_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__oe__oe + wire input 7 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__oe__oe$next + wire output 30 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__oe__ok + wire input 8 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__oe__ok$next + wire output 31 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__output_carry + wire input 14 \alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__output_carry$next + wire output 37 \alu_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__rc__ok + wire input 6 \alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__rc__ok$next + wire output 29 \alu_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__rc__rc + wire input 5 \alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__rc__rc$next + wire output 28 \alu_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__write_cr0 + wire input 12 \alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__write_cr0$next + wire output 35 \alu_op__write_cr0$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__zero_a + wire input 10 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_div0_logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire \alu_div0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire \alu_div0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \alu_div0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire \alu_div0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire \alu_div0_p_valid_i + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:134276.7-134276.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_div0_ra + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_div0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \alu_div0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \alu_div0_xer_so + wire width 64 output 42 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \alu_div0_xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 4 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 21 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 20 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 24 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 23 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 22 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 30 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 29 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 4 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 31 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 33 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 35 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 37 \dest4_o - attribute \src "libresoc.v:134174.7-134174.15" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:134560$5537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:134560$5537_Y + end + attribute \src "libresoc.v:134276.7-134276.20" + process $proc$libresoc.v:134276$5542 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:134561.3-134572.6" + process $proc$libresoc.v:134561$5538 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:134562.5-134562.29" + switch \initial + attribute \src "libresoc.v:134562.9-134562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \alu_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:134573.3-134591.6" + process $proc$libresoc.v:134573$5539 + assign { } { } + assign { } { } + assign $0\xer_ca$23[1:0]$5540 $1\xer_ca$23[1:0]$5541 + attribute \src "libresoc.v:134574.5-134574.29" + switch \initial + attribute \src "libresoc.v:134574.9-134574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \alu_op__input_carry + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\xer_ca$23[1:0]$5541 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\xer_ca$23[1:0]$5541 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\xer_ca$23[1:0]$5541 \xer_ca + case + assign $1\xer_ca$23[1:0]$5541 2'00 + end + sync always + update \xer_ca$23 $0\xer_ca$23[1:0]$5540 + end + connect \$24 $not$libresoc.v:134560$5537_Y + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "libresoc.v:134602.1-134926.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" +attribute \generator "nMigen" +module \input$113 + attribute \src "libresoc.v:134888.3-134899.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:134603.7-134603.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:134900.3-134918.6" + wire width 2 $0\xer_ca$23[1:0]$5546 + attribute \src "libresoc.v:134888.3-134899.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:134900.3-134918.6" + wire width 2 $1\xer_ca$23[1:0]$5547 + attribute \src "libresoc.v:134887.18-134887.100" + wire width 64 $not$libresoc.v:134887$5543_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:134603.7-134603.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rc$21 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 18 \oper_i_alu_div0__data_len + wire width 13 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -210968,19 +213457,35 @@ module \div0 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_div0__fn_unit + wire width 13 output 25 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \oper_i_alu_div0__imm_data__data + wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_div0__imm_data__ok + wire width 64 output 26 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 12 \oper_i_alu_div0__input_carry + wire width 2 input 11 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 19 \oper_i_alu_div0__insn + wire width 2 output 34 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \sr_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -211056,2719 +213561,236 @@ module \div0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \oper_i_alu_div0__insn_type + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src 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connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:134869$5155_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:134870$5156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ov_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:134870$5156_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:134871$5157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:134871$5157_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:134881$5167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:134881$5167_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:134882$5168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:134882$5168_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:134883$5169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:134883$5169_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:134854$5140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$42 - connect \B 1'0 - connect \Y $eq$libresoc.v:134854$5140_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:134856$5142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$libresoc.v:134856$5142_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:134821$5107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_logical_op__zero_a - connect \Y $not$libresoc.v:134821$5107_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:134822$5108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:134822$5108_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:134824$5110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:134824$5110_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:134837$5123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$libresoc.v:134837$5123_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:134839$5125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$libresoc.v:134839$5125_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:134842$5128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:134842$5128_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:134845$5131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$23 - connect \Y $not$libresoc.v:134845$5131_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:134851$5137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_n_ready_i - connect \Y $not$libresoc.v:134851$5137_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:134862$5148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:134862$5148_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:134850$5136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$32 - connect \B \$34 - connect \Y $or$libresoc.v:134850$5136_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:134860$5146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:134860$5146_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:134861$5147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:134861$5147_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:134863$5149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:134863$5149_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:134864$5150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:134864$5150_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:134867$5153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$libresoc.v:134867$5153_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:134873$5159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$5 - connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:134873$5159_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:134878$5164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$7 - connect \Y $reduce_and$libresoc.v:134878$5164_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:134844$5130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $reduce_or$libresoc.v:134844$5130_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:134848$5134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:134848$5134_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:134849$5135 + wire output 31 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:134887$5543 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:134849$5135_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:134872$5158 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:134872$5158_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:134874$5160 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:134874$5160_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:134875$5161 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:134875$5161_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:134876$5162 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_div0_logical_op__imm_data__data - connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:134876$5162_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:134877$5163 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$libresoc.v:134877$5163_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:134879$5165 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$85 - connect \S \src_sel$82 - connect \Y $ternary$libresoc.v:134879$5165_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:134880$5166 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:134880$5166_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:134972.12-135008.4" - cell \alu_div0 \alu_div0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_div0_cr_a - connect \cr_a_ok \cr_a_ok - connect \logical_op__data_len \alu_div0_logical_op__data_len - connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit - connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data - connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok - connect \logical_op__input_carry \alu_div0_logical_op__input_carry - connect \logical_op__insn \alu_div0_logical_op__insn - connect \logical_op__insn_type \alu_div0_logical_op__insn_type - connect \logical_op__invert_in \alu_div0_logical_op__invert_in - connect \logical_op__invert_out \alu_div0_logical_op__invert_out - connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit - connect \logical_op__is_signed \alu_div0_logical_op__is_signed - connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe - connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok - connect \logical_op__output_carry \alu_div0_logical_op__output_carry - connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok - connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc - connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 - connect \logical_op__zero_a \alu_div0_logical_op__zero_a - connect \n_ready_i \alu_div0_n_ready_i - connect \n_valid_o \alu_div0_n_valid_o - connect \o \alu_div0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_div0_p_ready_o - connect \p_valid_i \alu_div0_p_valid_i - connect \ra \alu_div0_ra - connect \rb \alu_div0_rb - connect \xer_ov \alu_div0_xer_ov - connect \xer_ov_ok \xer_ov_ok - connect \xer_so \alu_div0_xer_so - connect \xer_so$1 \alu_div0_xer_so$1 - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:135009.14-135015.4" - cell \alu_l$90 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:135016.15-135022.4" - cell \alui_l$89 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:135023.14-135029.4" - cell \opc_l$85 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:135030.14-135036.4" - cell \req_l$86 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:135037.14-135043.4" - cell \rok_l$88 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:135044.14-135049.4" - cell \rst_l$87 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:135050.14-135056.4" - cell \src_l$84 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:134887$5543_Y end - attribute \src "libresoc.v:134174.7-134174.20" - process $proc$libresoc.v:134174$5342 + attribute \src "libresoc.v:134603.7-134603.20" + process $proc$libresoc.v:134603$5548 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:134304.7-134304.24" - process $proc$libresoc.v:134304$5343 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:134314.13-134314.49" - process $proc$libresoc.v:134314$5344 - assign { } { } - assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] - end - attribute \src "libresoc.v:134332.14-134332.53" - process $proc$libresoc.v:134332$5345 - assign { } { } - assign $1\alu_div0_logical_op__fn_unit[12:0] 13'0000000000000 - sync always - sync init - update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[12:0] - end - attribute \src "libresoc.v:134336.14-134336.72" - process $proc$libresoc.v:134336$5346 - assign { } { } - assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:134340.7-134340.47" - process $proc$libresoc.v:134340$5347 - assign { } { } - assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:134348.13-134348.52" - process $proc$libresoc.v:134348$5348 - assign { } { } - assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:134352.14-134352.47" - process $proc$libresoc.v:134352$5349 - assign { } { } - assign $1\alu_div0_logical_op__insn[31:0] 0 - sync always - sync init - update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] - end - attribute \src "libresoc.v:134430.13-134430.51" - process $proc$libresoc.v:134430$5350 - assign { } { } - assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:134434.7-134434.44" - process $proc$libresoc.v:134434$5351 - assign { } { } - assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:134438.7-134438.45" - process $proc$libresoc.v:134438$5352 - assign { } { } - assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:134442.7-134442.43" - process $proc$libresoc.v:134442$5353 - assign { } { } - assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:134446.7-134446.44" - process $proc$libresoc.v:134446$5354 - assign { } { } - assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:134450.7-134450.41" - process $proc$libresoc.v:134450$5355 - assign { } { } - assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:134454.7-134454.41" - process $proc$libresoc.v:134454$5356 - assign { } { } - assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:134458.7-134458.47" - process $proc$libresoc.v:134458$5357 - assign { } { } - assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:134462.7-134462.41" - process $proc$libresoc.v:134462$5358 - assign { } { } - assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:134466.7-134466.41" - process $proc$libresoc.v:134466$5359 - assign { } { } - assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:134470.7-134470.44" - process $proc$libresoc.v:134470$5360 - assign { } { } - assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:134474.7-134474.41" - process $proc$libresoc.v:134474$5361 - assign { } { } - assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:134500.7-134500.26" - process $proc$libresoc.v:134500$5362 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:134508.7-134508.25" - process $proc$libresoc.v:134508$5363 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:134520.7-134520.27" - process $proc$libresoc.v:134520$5364 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:134554.14-134554.47" - process $proc$libresoc.v:134554$5365 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "libresoc.v:134558.7-134558.27" - process $proc$libresoc.v:134558$5366 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:134562.13-134562.33" - process $proc$libresoc.v:134562$5367 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:134566.7-134566.30" - process $proc$libresoc.v:134566$5368 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:134570.13-134570.35" - process $proc$libresoc.v:134570$5369 - assign { } { } - assign $1\data_r2__xer_ov[1:0] 2'00 - sync always - sync init - update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] - end - attribute \src "libresoc.v:134574.7-134574.32" - process $proc$libresoc.v:134574$5370 - assign { } { } - assign $1\data_r2__xer_ov_ok[0:0] 1'0 - sync always - sync init - update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:134578.7-134578.29" - process $proc$libresoc.v:134578$5371 - assign { } { } - assign $1\data_r3__xer_so[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so $1\data_r3__xer_so[0:0] - end - attribute \src "libresoc.v:134582.7-134582.32" - process $proc$libresoc.v:134582$5372 - assign { } { } - assign $1\data_r3__xer_so_ok[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] - end - attribute \src "libresoc.v:134602.7-134602.25" - process $proc$libresoc.v:134602$5373 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:134606.7-134606.25" - process $proc$libresoc.v:134606$5374 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:134738.13-134738.30" - process $proc$libresoc.v:134738$5375 - assign { } { } - assign $1\prev_wr_go[3:0] 4'0000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[3:0] - end - attribute \src "libresoc.v:134746.13-134746.31" - process $proc$libresoc.v:134746$5376 - assign { } { } - assign $1\req_l_r_req[3:0] 4'1111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[3:0] - end - attribute \src "libresoc.v:134750.13-134750.31" - process $proc$libresoc.v:134750$5377 - assign { } { } - assign $1\req_l_s_req[3:0] 4'0000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[3:0] - end - attribute \src "libresoc.v:134762.7-134762.26" - process $proc$libresoc.v:134762$5378 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:134766.7-134766.26" - process $proc$libresoc.v:134766$5379 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:134770.7-134770.25" - process $proc$libresoc.v:134770$5380 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:134774.7-134774.25" - process $proc$libresoc.v:134774$5381 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:134788.13-134788.31" - process $proc$libresoc.v:134788$5382 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "libresoc.v:134792.13-134792.31" - process $proc$libresoc.v:134792$5383 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "libresoc.v:134800.14-134800.43" - process $proc$libresoc.v:134800$5384 + attribute \src "libresoc.v:134888.3-134899.6" + process $proc$libresoc.v:134888$5544 assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:134889.5-134889.29" + switch \initial + attribute \src "libresoc.v:134889.9-134889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \sr_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end sync always - sync init - update \src_r0 $1\src_r0[63:0] + update \a $0\a[63:0] end - attribute \src "libresoc.v:134804.14-134804.43" - process $proc$libresoc.v:134804$5385 + attribute \src "libresoc.v:134900.3-134918.6" + process $proc$libresoc.v:134900$5545 assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "libresoc.v:134808.7-134808.20" - process $proc$libresoc.v:134808$5386 assign { } { } - assign $1\src_r2[0:0] 1'0 + assign $0\xer_ca$23[1:0]$5546 $1\xer_ca$23[1:0]$5547 + attribute \src "libresoc.v:134901.5-134901.29" + switch \initial + attribute \src "libresoc.v:134901.9-134901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \sr_op__input_carry + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\xer_ca$23[1:0]$5547 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\xer_ca$23[1:0]$5547 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\xer_ca$23[1:0]$5547 \xer_ca + case + assign $1\xer_ca$23[1:0]$5547 2'00 + end sync always - sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "libresoc.v:134884.3-134885.39" - process $proc$libresoc.v:134884$5170 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:134886.3-134887.43" - process $proc$libresoc.v:134886$5171 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:134888.3-134889.29" - process $proc$libresoc.v:134888$5172 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "libresoc.v:134890.3-134891.29" - process $proc$libresoc.v:134890$5173 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:134892.3-134893.29" - process $proc$libresoc.v:134892$5174 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:134894.3-134895.47" - process $proc$libresoc.v:134894$5175 - assign { } { } - assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next - sync posedge \coresync_clk - update \data_r3__xer_so $0\data_r3__xer_so[0:0] - end - attribute \src "libresoc.v:134896.3-134897.53" - process $proc$libresoc.v:134896$5176 - assign { } { } - assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next - sync posedge \coresync_clk - update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + update \xer_ca$23 $0\xer_ca$23[1:0]$5546 end - attribute \src "libresoc.v:134898.3-134899.47" - process $proc$libresoc.v:134898$5177 - assign { } { } - assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next - sync posedge \coresync_clk - update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] - end - attribute \src "libresoc.v:134900.3-134901.53" - process $proc$libresoc.v:134900$5178 - assign { } { } - assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next - sync posedge \coresync_clk - update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:134902.3-134903.43" - process $proc$libresoc.v:134902$5179 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:134904.3-134905.49" - process $proc$libresoc.v:134904$5180 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:134906.3-134907.37" - process $proc$libresoc.v:134906$5181 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "libresoc.v:134908.3-134909.43" - process $proc$libresoc.v:134908$5182 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:134910.3-134911.77" - process $proc$libresoc.v:134910$5183 - assign { } { } - assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next - sync posedge \coresync_clk - update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:134912.3-134913.73" - process $proc$libresoc.v:134912$5184 - assign { } { } - assign $0\alu_div0_logical_op__fn_unit[12:0] \alu_div0_logical_op__fn_unit$next - sync posedge \coresync_clk - update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[12:0] - end - attribute \src "libresoc.v:134914.3-134915.87" - process $proc$libresoc.v:134914$5185 - assign { } { } - assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:134916.3-134917.83" - process $proc$libresoc.v:134916$5186 - assign { } { } - assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:134918.3-134919.71" - process $proc$libresoc.v:134918$5187 - assign { } { } - assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next - sync posedge \coresync_clk - update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:134920.3-134921.71" - process $proc$libresoc.v:134920$5188 - assign { } { } - assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next - sync posedge \coresync_clk - update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:134922.3-134923.71" - process $proc$libresoc.v:134922$5189 - assign { } { } - assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next - sync posedge \coresync_clk - update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:134924.3-134925.71" - process $proc$libresoc.v:134924$5190 - assign { } { } - assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next - sync posedge \coresync_clk - update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:134926.3-134927.77" - process $proc$libresoc.v:134926$5191 - assign { } { } - assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next - sync posedge \coresync_clk - update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:134928.3-134929.71" - process $proc$libresoc.v:134928$5192 - assign { } { } - assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next - sync posedge \coresync_clk - update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:134930.3-134931.81" - process $proc$libresoc.v:134930$5193 - assign { } { } - assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next - sync posedge \coresync_clk - update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:134932.3-134933.79" - process $proc$libresoc.v:134932$5194 - assign { } { } - assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next - sync posedge \coresync_clk - update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:134934.3-134935.77" - process $proc$libresoc.v:134934$5195 - assign { } { } - assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next - sync posedge \coresync_clk - update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:134936.3-134937.83" - process $proc$libresoc.v:134936$5196 - assign { } { } - assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next - sync posedge \coresync_clk - update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:134938.3-134939.75" - process $proc$libresoc.v:134938$5197 - assign { } { } - assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next - sync posedge \coresync_clk - update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:134940.3-134941.77" - process $proc$libresoc.v:134940$5198 - assign { } { } - assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next - sync posedge \coresync_clk - update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:134942.3-134943.75" - process $proc$libresoc.v:134942$5199 - assign { } { } - assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next - sync posedge \coresync_clk - update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] - end - attribute \src "libresoc.v:134944.3-134945.67" - process $proc$libresoc.v:134944$5200 - assign { } { } - assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next - sync posedge \coresync_clk - update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] - end - attribute \src "libresoc.v:134946.3-134947.39" - process $proc$libresoc.v:134946$5201 - assign { } { } - assign $0\req_l_r_req[3:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[3:0] - end - attribute \src "libresoc.v:134948.3-134949.39" - process $proc$libresoc.v:134948$5202 - assign { } { } - assign $0\req_l_s_req[3:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[3:0] - end - attribute \src "libresoc.v:134950.3-134951.39" - process $proc$libresoc.v:134950$5203 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "libresoc.v:134952.3-134953.39" - process $proc$libresoc.v:134952$5204 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "libresoc.v:134954.3-134955.39" - process $proc$libresoc.v:134954$5205 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:134956.3-134957.39" - process $proc$libresoc.v:134956$5206 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:134958.3-134959.39" - process $proc$libresoc.v:134958$5207 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:134960.3-134961.39" - process $proc$libresoc.v:134960$5208 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:134962.3-134963.41" - process $proc$libresoc.v:134962$5209 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:134964.3-134965.41" - process $proc$libresoc.v:134964$5210 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:134966.3-134967.37" - process $proc$libresoc.v:134966$5211 - assign { } { } - assign $0\prev_wr_go[3:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[3:0] - end - attribute \src "libresoc.v:134968.3-134969.40" - process $proc$libresoc.v:134968$5212 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:134970.3-134971.25" - process $proc$libresoc.v:134970$5213 - assign { } { } - assign $0\all_rd_dly[0:0] \$10 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "libresoc.v:135057.3-135066.6" - process $proc$libresoc.v:135057$5214 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:135058.5-135058.29" - switch \initial - attribute \src "libresoc.v:135058.9-135058.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$54 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$46 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "libresoc.v:135067.3-135075.6" - process $proc$libresoc.v:135067$5215 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$5216 $1\rok_l_s_rdok$next[0:0]$5217 - attribute \src "libresoc.v:135068.5-135068.29" - switch \initial - attribute \src "libresoc.v:135068.9-135068.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$5217 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$5217 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5216 - end - attribute \src "libresoc.v:135076.3-135084.6" - process $proc$libresoc.v:135076$5218 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$5219 $1\rok_l_r_rdok$next[0:0]$5220 - attribute \src "libresoc.v:135077.5-135077.29" - switch \initial - attribute \src "libresoc.v:135077.9-135077.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$5220 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$5220 \$64 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5219 - end - attribute \src "libresoc.v:135085.3-135093.6" - process $proc$libresoc.v:135085$5221 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$5222 $1\rst_l_s_rst$next[0:0]$5223 - attribute \src "libresoc.v:135086.5-135086.29" - switch \initial - attribute \src "libresoc.v:135086.9-135086.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$5223 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$5223 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5222 - end - attribute \src "libresoc.v:135094.3-135102.6" - process $proc$libresoc.v:135094$5224 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$5225 $1\rst_l_r_rst$next[0:0]$5226 - attribute \src "libresoc.v:135095.5-135095.29" - switch \initial - attribute \src "libresoc.v:135095.9-135095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$5226 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$5226 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5225 - end - attribute \src "libresoc.v:135103.3-135111.6" - process $proc$libresoc.v:135103$5227 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$5228 $1\opc_l_s_opc$next[0:0]$5229 - attribute \src "libresoc.v:135104.5-135104.29" - switch \initial - attribute \src "libresoc.v:135104.9-135104.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$5229 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$5229 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5228 - end - attribute \src "libresoc.v:135112.3-135120.6" - process $proc$libresoc.v:135112$5230 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$5231 $1\opc_l_r_opc$next[0:0]$5232 - attribute \src "libresoc.v:135113.5-135113.29" - switch \initial - attribute \src "libresoc.v:135113.9-135113.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$5232 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$5232 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5231 - end - attribute \src "libresoc.v:135121.3-135129.6" - process $proc$libresoc.v:135121$5233 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$5234 $1\src_l_s_src$next[2:0]$5235 - attribute \src "libresoc.v:135122.5-135122.29" - switch \initial - attribute \src "libresoc.v:135122.9-135122.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$5235 3'000 - case - assign $1\src_l_s_src$next[2:0]$5235 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5234 - end - attribute \src "libresoc.v:135130.3-135138.6" - process $proc$libresoc.v:135130$5236 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$5237 $1\src_l_r_src$next[2:0]$5238 - attribute \src "libresoc.v:135131.5-135131.29" - switch \initial - attribute \src "libresoc.v:135131.9-135131.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$5238 3'111 - case - assign $1\src_l_r_src$next[2:0]$5238 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5237 - end - attribute \src "libresoc.v:135139.3-135147.6" - process $proc$libresoc.v:135139$5239 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[3:0]$5240 $1\req_l_s_req$next[3:0]$5241 - attribute \src "libresoc.v:135140.5-135140.29" - switch \initial - attribute \src "libresoc.v:135140.9-135140.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[3:0]$5241 4'0000 - case - assign $1\req_l_s_req$next[3:0]$5241 \$66 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5240 - end - attribute \src "libresoc.v:135148.3-135156.6" - process $proc$libresoc.v:135148$5242 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[3:0]$5243 $1\req_l_r_req$next[3:0]$5244 - attribute \src "libresoc.v:135149.5-135149.29" - switch \initial - attribute \src "libresoc.v:135149.9-135149.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[3:0]$5244 4'1111 - case - assign $1\req_l_r_req$next[3:0]$5244 \$68 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5243 - end - attribute \src "libresoc.v:135157.3-135195.6" - process $proc$libresoc.v:135157$5245 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__data_len$next[3:0]$5246 $1\alu_div0_logical_op__data_len$next[3:0]$5264 - assign $0\alu_div0_logical_op__fn_unit$next[12:0]$5247 $1\alu_div0_logical_op__fn_unit$next[12:0]$5265 - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__input_carry$next[1:0]$5250 $1\alu_div0_logical_op__input_carry$next[1:0]$5268 - assign $0\alu_div0_logical_op__insn$next[31:0]$5251 $1\alu_div0_logical_op__insn$next[31:0]$5269 - assign $0\alu_div0_logical_op__insn_type$next[6:0]$5252 $1\alu_div0_logical_op__insn_type$next[6:0]$5270 - assign $0\alu_div0_logical_op__invert_in$next[0:0]$5253 $1\alu_div0_logical_op__invert_in$next[0:0]$5271 - assign $0\alu_div0_logical_op__invert_out$next[0:0]$5254 $1\alu_div0_logical_op__invert_out$next[0:0]$5272 - assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5255 $1\alu_div0_logical_op__is_32bit$next[0:0]$5273 - assign $0\alu_div0_logical_op__is_signed$next[0:0]$5256 $1\alu_div0_logical_op__is_signed$next[0:0]$5274 - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__output_carry$next[0:0]$5259 $1\alu_div0_logical_op__output_carry$next[0:0]$5277 - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5262 $1\alu_div0_logical_op__write_cr0$next[0:0]$5280 - assign $0\alu_div0_logical_op__zero_a$next[0:0]$5263 $1\alu_div0_logical_op__zero_a$next[0:0]$5281 - assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5248 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5282 - assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5249 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5283 - assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5257 $2\alu_div0_logical_op__oe__oe$next[0:0]$5284 - assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5258 $2\alu_div0_logical_op__oe__ok$next[0:0]$5285 - assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5260 $2\alu_div0_logical_op__rc__ok$next[0:0]$5286 - assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5261 $2\alu_div0_logical_op__rc__rc$next[0:0]$5287 - attribute \src "libresoc.v:135158.5-135158.29" - switch \initial - attribute \src "libresoc.v:135158.9-135158.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_div0_logical_op__insn$next[31:0]$5269 $1\alu_div0_logical_op__data_len$next[3:0]$5264 $1\alu_div0_logical_op__is_signed$next[0:0]$5274 $1\alu_div0_logical_op__is_32bit$next[0:0]$5273 $1\alu_div0_logical_op__output_carry$next[0:0]$5277 $1\alu_div0_logical_op__write_cr0$next[0:0]$5280 $1\alu_div0_logical_op__invert_out$next[0:0]$5272 $1\alu_div0_logical_op__input_carry$next[1:0]$5268 $1\alu_div0_logical_op__zero_a$next[0:0]$5281 $1\alu_div0_logical_op__invert_in$next[0:0]$5271 $1\alu_div0_logical_op__oe__ok$next[0:0]$5276 $1\alu_div0_logical_op__oe__oe$next[0:0]$5275 $1\alu_div0_logical_op__rc__ok$next[0:0]$5278 $1\alu_div0_logical_op__rc__rc$next[0:0]$5279 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5267 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5266 $1\alu_div0_logical_op__fn_unit$next[12:0]$5265 $1\alu_div0_logical_op__insn_type$next[6:0]$5270 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } - case - assign $1\alu_div0_logical_op__data_len$next[3:0]$5264 \alu_div0_logical_op__data_len - assign $1\alu_div0_logical_op__fn_unit$next[12:0]$5265 \alu_div0_logical_op__fn_unit - assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5266 \alu_div0_logical_op__imm_data__data - assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5267 \alu_div0_logical_op__imm_data__ok - assign $1\alu_div0_logical_op__input_carry$next[1:0]$5268 \alu_div0_logical_op__input_carry - assign $1\alu_div0_logical_op__insn$next[31:0]$5269 \alu_div0_logical_op__insn - assign $1\alu_div0_logical_op__insn_type$next[6:0]$5270 \alu_div0_logical_op__insn_type - assign $1\alu_div0_logical_op__invert_in$next[0:0]$5271 \alu_div0_logical_op__invert_in - assign $1\alu_div0_logical_op__invert_out$next[0:0]$5272 \alu_div0_logical_op__invert_out - assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5273 \alu_div0_logical_op__is_32bit - assign $1\alu_div0_logical_op__is_signed$next[0:0]$5274 \alu_div0_logical_op__is_signed - assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5275 \alu_div0_logical_op__oe__oe - assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5276 \alu_div0_logical_op__oe__ok - assign $1\alu_div0_logical_op__output_carry$next[0:0]$5277 \alu_div0_logical_op__output_carry - assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5278 \alu_div0_logical_op__rc__ok - assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5279 \alu_div0_logical_op__rc__rc - assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5280 \alu_div0_logical_op__write_cr0 - assign $1\alu_div0_logical_op__zero_a$next[0:0]$5281 \alu_div0_logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5282 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5283 1'0 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5287 1'0 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5286 1'0 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5284 1'0 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5285 1'0 - case - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5282 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5266 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5283 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5267 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5284 $1\alu_div0_logical_op__oe__oe$next[0:0]$5275 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5285 $1\alu_div0_logical_op__oe__ok$next[0:0]$5276 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5286 $1\alu_div0_logical_op__rc__ok$next[0:0]$5278 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5287 $1\alu_div0_logical_op__rc__rc$next[0:0]$5279 - end - sync always - update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5246 - update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[12:0]$5247 - update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5248 - update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5249 - update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5250 - update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5251 - update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5252 - update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5253 - update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5254 - update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5255 - update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5256 - update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5257 - update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5258 - update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5259 - update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5260 - update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5261 - update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5262 - update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5263 - end - attribute \src "libresoc.v:135196.3-135217.6" - process $proc$libresoc.v:135196$5288 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$5289 $2\data_r0__o$next[63:0]$5293 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$5290 $3\data_r0__o_ok$next[0:0]$5295 - attribute \src "libresoc.v:135197.5-135197.29" - switch \initial - attribute \src "libresoc.v:135197.9-135197.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$5292 $1\data_r0__o$next[63:0]$5291 } { \o_ok \alu_div0_o } - case - assign $1\data_r0__o$next[63:0]$5291 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$5292 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$5294 $2\data_r0__o$next[63:0]$5293 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$5293 $1\data_r0__o$next[63:0]$5291 - assign $2\data_r0__o_ok$next[0:0]$5294 $1\data_r0__o_ok$next[0:0]$5292 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$5295 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$5295 $2\data_r0__o_ok$next[0:0]$5294 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$5289 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5290 - end - attribute \src "libresoc.v:135218.3-135239.6" - process $proc$libresoc.v:135218$5296 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$5297 $2\data_r1__cr_a$next[3:0]$5301 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$5298 $3\data_r1__cr_a_ok$next[0:0]$5303 - attribute \src "libresoc.v:135219.5-135219.29" - switch \initial - attribute \src "libresoc.v:135219.9-135219.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$5300 $1\data_r1__cr_a$next[3:0]$5299 } { \cr_a_ok \alu_div0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$5299 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$5300 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$5302 $2\data_r1__cr_a$next[3:0]$5301 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$5301 $1\data_r1__cr_a$next[3:0]$5299 - assign $2\data_r1__cr_a_ok$next[0:0]$5302 $1\data_r1__cr_a_ok$next[0:0]$5300 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$5303 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$5303 $2\data_r1__cr_a_ok$next[0:0]$5302 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5297 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5298 - end - attribute \src "libresoc.v:135240.3-135261.6" - process $proc$libresoc.v:135240$5304 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$5305 $2\data_r2__xer_ov$next[1:0]$5309 - assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$5306 $3\data_r2__xer_ov_ok$next[0:0]$5311 - attribute \src "libresoc.v:135241.5-135241.29" - switch \initial - attribute \src "libresoc.v:135241.9-135241.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$5308 $1\data_r2__xer_ov$next[1:0]$5307 } { \xer_ov_ok \alu_div0_xer_ov } - case - assign $1\data_r2__xer_ov$next[1:0]$5307 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$5308 \data_r2__xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$5310 $2\data_r2__xer_ov$next[1:0]$5309 } 3'000 - case - assign $2\data_r2__xer_ov$next[1:0]$5309 $1\data_r2__xer_ov$next[1:0]$5307 - assign $2\data_r2__xer_ov_ok$next[0:0]$5310 $1\data_r2__xer_ov_ok$next[0:0]$5308 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$5311 1'0 - case - assign $3\data_r2__xer_ov_ok$next[0:0]$5311 $2\data_r2__xer_ov_ok$next[0:0]$5310 - end - sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5305 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5306 - end - attribute \src "libresoc.v:135262.3-135283.6" - process $proc$libresoc.v:135262$5312 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r3__xer_so$next[0:0]$5313 $2\data_r3__xer_so$next[0:0]$5317 - assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$5314 $3\data_r3__xer_so_ok$next[0:0]$5319 - attribute \src "libresoc.v:135263.5-135263.29" - switch \initial - attribute \src "libresoc.v:135263.9-135263.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$5316 $1\data_r3__xer_so$next[0:0]$5315 } { \xer_so_ok \alu_div0_xer_so } - case - assign $1\data_r3__xer_so$next[0:0]$5315 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$5316 \data_r3__xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$5318 $2\data_r3__xer_so$next[0:0]$5317 } 2'00 - case - assign $2\data_r3__xer_so$next[0:0]$5317 $1\data_r3__xer_so$next[0:0]$5315 - assign $2\data_r3__xer_so_ok$next[0:0]$5318 $1\data_r3__xer_so_ok$next[0:0]$5316 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$5319 1'0 - case - assign $3\data_r3__xer_so_ok$next[0:0]$5319 $2\data_r3__xer_so_ok$next[0:0]$5318 - end - sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5313 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5314 - end - attribute \src "libresoc.v:135284.3-135293.6" - process $proc$libresoc.v:135284$5320 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$5321 $1\src_r0$next[63:0]$5322 - attribute \src "libresoc.v:135285.5-135285.29" - switch \initial - attribute \src "libresoc.v:135285.9-135285.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \src_sel - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$5322 \src_or_imm - case - assign $1\src_r0$next[63:0]$5322 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$5321 - end - attribute \src "libresoc.v:135294.3-135303.6" - process $proc$libresoc.v:135294$5323 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$5324 $1\src_r1$next[63:0]$5325 - attribute \src "libresoc.v:135295.5-135295.29" - switch \initial - attribute \src "libresoc.v:135295.9-135295.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \src_sel$82 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$5325 \src_or_imm$85 - case - assign $1\src_r1$next[63:0]$5325 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$5324 - end - attribute \src "libresoc.v:135304.3-135313.6" - process $proc$libresoc.v:135304$5326 - assign { } { } - assign { } { } - assign $0\src_r2$next[0:0]$5327 $1\src_r2$next[0:0]$5328 - attribute \src "libresoc.v:135305.5-135305.29" - switch \initial - attribute \src "libresoc.v:135305.9-135305.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \src_l_q_src [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[0:0]$5328 \src3_i - case - assign $1\src_r2$next[0:0]$5328 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[0:0]$5327 - end - attribute \src "libresoc.v:135314.3-135322.6" - process $proc$libresoc.v:135314$5329 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$5330 $1\alui_l_r_alui$next[0:0]$5331 - attribute \src "libresoc.v:135315.5-135315.29" - switch \initial - attribute \src "libresoc.v:135315.9-135315.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$5331 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$5331 \$94 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5330 - end - attribute \src "libresoc.v:135323.3-135331.6" - process $proc$libresoc.v:135323$5332 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$5333 $1\alu_l_r_alu$next[0:0]$5334 - attribute \src "libresoc.v:135324.5-135324.29" - switch \initial - attribute \src "libresoc.v:135324.9-135324.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$5334 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$5334 \$96 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5333 - end - attribute \src "libresoc.v:135332.3-135341.6" - process $proc$libresoc.v:135332$5335 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:135333.5-135333.29" - switch \initial - attribute \src "libresoc.v:135333.9-135333.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$122 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:135342.3-135351.6" - process $proc$libresoc.v:135342$5336 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:135343.5-135343.29" - switch \initial - attribute \src "libresoc.v:135343.9-135343.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$124 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a - case - assign $1\dest2_o[3:0] 4'0000 - end - sync always - update \dest2_o $0\dest2_o[3:0] - end - attribute \src "libresoc.v:135352.3-135361.6" - process $proc$libresoc.v:135352$5337 - assign { } { } - assign { } { } - assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:135353.5-135353.29" - switch \initial - attribute \src "libresoc.v:135353.9-135353.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$126 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[1:0] \data_r2__xer_ov - case - assign $1\dest3_o[1:0] 2'00 - end - sync always - update \dest3_o $0\dest3_o[1:0] - end - attribute \src "libresoc.v:135362.3-135371.6" - process $proc$libresoc.v:135362$5338 - assign { } { } - assign { } { } - assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:135363.5-135363.29" - switch \initial - attribute \src "libresoc.v:135363.9-135363.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$128 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest4_o[0:0] \data_r3__xer_so - case - assign $1\dest4_o[0:0] 1'0 - end - sync always - update \dest4_o $0\dest4_o[0:0] - end - attribute \src "libresoc.v:135372.3-135380.6" - process $proc$libresoc.v:135372$5339 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[3:0]$5340 $1\prev_wr_go$next[3:0]$5341 - attribute \src "libresoc.v:135373.5-135373.29" - switch \initial - attribute \src "libresoc.v:135373.9-135373.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[3:0]$5341 4'0000 - case - assign $1\prev_wr_go$next[3:0]$5341 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5340 - end - connect \$100 $not$libresoc.v:134821$5107_Y - connect \$102 $not$libresoc.v:134822$5108_Y - connect \$104 $and$libresoc.v:134823$5109_Y - connect \$106 $not$libresoc.v:134824$5110_Y - connect \$108 $and$libresoc.v:134825$5111_Y - connect \$10 $and$libresoc.v:134826$5112_Y - connect \$110 $and$libresoc.v:134827$5113_Y - connect \$112 $and$libresoc.v:134828$5114_Y - connect \$114 $and$libresoc.v:134829$5115_Y - connect \$116 $and$libresoc.v:134830$5116_Y - connect \$118 $and$libresoc.v:134831$5117_Y - connect \$120 $and$libresoc.v:134832$5118_Y - connect \$122 $and$libresoc.v:134833$5119_Y - connect \$124 $and$libresoc.v:134834$5120_Y - connect \$126 $and$libresoc.v:134835$5121_Y - connect \$128 $and$libresoc.v:134836$5122_Y - connect \$12 $not$libresoc.v:134837$5123_Y - connect \$14 $and$libresoc.v:134838$5124_Y - connect \$16 $not$libresoc.v:134839$5125_Y - connect \$18 $and$libresoc.v:134840$5126_Y - connect \$20 $and$libresoc.v:134841$5127_Y - connect \$24 $not$libresoc.v:134842$5128_Y - connect \$26 $and$libresoc.v:134843$5129_Y - connect \$23 $reduce_or$libresoc.v:134844$5130_Y - connect \$22 $not$libresoc.v:134845$5131_Y - connect \$2 $and$libresoc.v:134846$5132_Y - connect \$30 $and$libresoc.v:134847$5133_Y - connect \$32 $reduce_or$libresoc.v:134848$5134_Y - connect \$34 $reduce_or$libresoc.v:134849$5135_Y - connect \$36 $or$libresoc.v:134850$5136_Y - connect \$38 $not$libresoc.v:134851$5137_Y - connect \$40 $and$libresoc.v:134852$5138_Y - connect \$42 $and$libresoc.v:134853$5139_Y - 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\$86 $ternary$libresoc.v:134876$5162_Y - connect \$88 $ternary$libresoc.v:134877$5163_Y - connect \$4 $reduce_and$libresoc.v:134878$5164_Y - connect \$90 $ternary$libresoc.v:134879$5165_Y - connect \$92 $ternary$libresoc.v:134880$5166_Y - connect \$94 $and$libresoc.v:134881$5167_Y - connect \$96 $and$libresoc.v:134882$5168_Y - connect \$98 $and$libresoc.v:134883$5169_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$120 - connect \cu_rd__rel_o \$108 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_div0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_div0_p_valid_i \alui_l_q_alui - connect \alu_div0_xer_so$1 \$92 - connect \alu_div0_rb \$90 - connect \alu_div0_ra \$88 - connect \src_or_imm$85 \$86 - connect \src_sel$82 \$83 - connect \src_or_imm \$80 - connect \src_sel \$78 - connect \cu_wrmask_o { \$76 \$74 \$72 \$70 } - connect \reset_r \$62 - connect \reset_w \$60 - connect \rst_r \$58 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\o_dividend_quotient \dividend - connect \o_q_bits_known 7'0000000 + connect \$24 $not$libresoc.v:134887$5543_Y + connect \rc$21 \rc + connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$20 \b + connect \b \rb + connect \ra$19 \a end -attribute \src "libresoc.v:135430.1-135512.10" +attribute \src "libresoc.v:134930.1-135229.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" attribute \generator "nMigen" -module \div_state_next - attribute \src "libresoc.v:135431.7-135431.20" +module \input$50 + attribute \src "libresoc.v:135211.3-135222.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:134931.7-134931.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135496.3-135507.6" - wire width 128 $0\o_dividend_quotient[127:0] - attribute \src "libresoc.v:135484.3-135495.6" - wire width 7 $0\o_q_bits_known[6:0] - attribute \src "libresoc.v:135472.3-135483.6" - wire width 128 $0\value[127:0] - attribute \src "libresoc.v:135496.3-135507.6" - wire width 128 $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:135484.3-135495.6" - wire width 7 $1\o_q_bits_known[6:0] - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - wire width 127 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - wire width 129 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:64" - wire width 128 \difference - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" - wire width 64 input 4 \divisor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 input 3 \i_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 input 2 \i_q_bits_known - attribute \src "libresoc.v:135431.7-135431.15" + attribute \src "libresoc.v:135211.3-135222.6" + wire width 64 $1\b[63:0] + attribute \src "libresoc.v:135210.18-135210.100" + wire width 64 $not$libresoc.v:135210$5549_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:134931.7-134931.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" - wire \next_quotient_bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 output 5 \o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 output 1 \o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" - wire width 128 \value - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - cell $add $add$libresoc.v:135466$5387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \i_q_bits_known - connect \B 1'1 - connect \Y $add$libresoc.v:135466$5387_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:135467$5388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \i_q_bits_known - connect \B 7'1000000 - connect \Y $ge$libresoc.v:135467$5388_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:135471$5392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \i_q_bits_known - connect \B 7'1000000 - connect \Y $ge$libresoc.v:135471$5392_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - cell $not $not$libresoc.v:135470$5391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \difference [127] - connect \Y $not$libresoc.v:135470$5391_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sshl $sshl$libresoc.v:135468$5389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 127 - connect \A \divisor - connect \B 6'111111 - connect \Y $sshl$libresoc.v:135468$5389_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sub $sub$libresoc.v:135469$5390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \B_SIGNED 0 - parameter \B_WIDTH 127 - parameter \Y_WIDTH 129 - connect \A \i_dividend_quotient - connect \B \$2 - connect \Y $sub$libresoc.v:135469$5390_Y - end - attribute \src "libresoc.v:135431.7-135431.20" - process $proc$libresoc.v:135431$5396 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:135472.3-135483.6" - process $proc$libresoc.v:135472$5393 - assign { } { } - assign $0\value[127:0] $1\value[127:0] - attribute \src "libresoc.v:135473.5-135473.29" - switch \initial - attribute \src "libresoc.v:135473.9-135473.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" - switch \next_quotient_bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\value[127:0] \difference - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\value[127:0] \i_dividend_quotient - end - sync always - update \value $0\value[127:0] - end - attribute \src "libresoc.v:135484.3-135495.6" - process $proc$libresoc.v:135484$5394 - assign { } { } - assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:135485.5-135485.29" - switch \initial - attribute \src "libresoc.v:135485.9-135485.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" - switch \$8 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o_q_bits_known[6:0] \i_q_bits_known - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\o_q_bits_known[6:0] \$10 [6:0] - end - sync always - update \o_q_bits_known $0\o_q_bits_known[6:0] - end - attribute \src "libresoc.v:135496.3-135507.6" - process $proc$libresoc.v:135496$5395 - assign { } { } - assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:135497.5-135497.29" - switch \initial - attribute \src "libresoc.v:135497.9-135497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o_dividend_quotient[127:0] \i_dividend_quotient - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\o_dividend_quotient[127:0] { \value [126:0] \next_quotient_bit } - end - sync always - update \o_dividend_quotient $0\o_dividend_quotient[127:0] - end - connect \$11 $add$libresoc.v:135466$5387_Y - connect \$13 $ge$libresoc.v:135467$5388_Y - connect \$2 $sshl$libresoc.v:135468$5389_Y - connect \$4 $sub$libresoc.v:135469$5390_Y - connect \$6 $not$libresoc.v:135470$5391_Y - connect \$8 $ge$libresoc.v:135471$5392_Y - connect \$1 \$4 - connect \$10 \$11 - connect \next_quotient_bit \$6 - connect \difference \$4 [127:0] -end -attribute \src "libresoc.v:135516.1-135755.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" -attribute \generator "nMigen" -module \dummy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 12 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 26 \fast1$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 27 \fast2$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 28 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 14 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 24 \ra$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 25 \rb$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \trap_op__cia + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \trap_op__cia$6 + wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -213784,7 +213806,7 @@ module \dummy attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \trap_op__fn_unit + wire width 13 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -213800,11 +213822,31 @@ module \dummy attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 16 \trap_op__fn_unit$3 + wire width 13 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \trap_op__insn + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 17 \trap_op__insn$4 + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -213880,7 +213922,7 @@ module \dummy attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \trap_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -213956,913 +213998,140 @@ module \dummy attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 15 \trap_op__insn_type$2 + wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \trap_op__is_32bit + wire input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \trap_op__is_32bit$7 + wire output 31 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 9 \trap_op__ldst_exc + wire input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 23 \trap_op__ldst_exc$10 + wire output 34 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \trap_op__msr + wire input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 18 \trap_op__msr$5 + wire output 37 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 8 \trap_op__trapaddr + wire input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 22 \trap_op__trapaddr$9 + wire output 38 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 7 \trap_op__traptype + wire input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 21 \trap_op__traptype$8 - connect \fast2$14 \fast2 - connect \fast1$13 \fast1 - connect \rb$12 \rb - connect \ra$11 \ra - connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \muxid$1 \muxid -end -attribute \src "libresoc.v:135759.1-135930.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fast" -attribute \generator "nMigen" -module \fast - attribute \src "libresoc.v:135854.3-135860.6" - wire width 3 $0$memwr$\memory$libresoc.v:135858$5405_ADDR[2:0]$5413 - attribute \src "libresoc.v:135854.3-135860.6" - wire width 64 $0$memwr$\memory$libresoc.v:135858$5405_DATA[63:0]$5414 - attribute \src "libresoc.v:135854.3-135860.6" - wire width 64 $0$memwr$\memory$libresoc.v:135858$5405_EN[63:0]$5415 - attribute \src "libresoc.v:135854.3-135860.6" - wire width 3 $0$memwr$\memory$libresoc.v:135859$5406_ADDR[2:0]$5416 - attribute \src "libresoc.v:135854.3-135860.6" - wire width 64 $0$memwr$\memory$libresoc.v:135859$5406_DATA[63:0]$5417 - attribute \src "libresoc.v:135854.3-135860.6" - wire width 64 $0$memwr$\memory$libresoc.v:135859$5406_EN[63:0]$5418 - attribute \src "libresoc.v:135854.3-135860.6" - wire width 3 $0\_0_[2:0] - attribute \src "libresoc.v:135854.3-135860.6" - wire width 3 $0\_1_[2:0] - attribute \src "libresoc.v:135854.3-135860.6" - wire width 3 $0\_2_[2:0] - attribute \src "libresoc.v:135760.7-135760.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:135911.3-135920.6" - wire width 64 $0\issue__data_o[63:0] - attribute \src "libresoc.v:135883.3-135891.6" - wire $0\ren_delay$10$next[0:0]$5427 - attribute \src "libresoc.v:135836.3-135837.43" - wire $0\ren_delay$10[0:0]$5410 - attribute \src "libresoc.v:135811.7-135811.28" - wire $0\ren_delay$10[0:0]$5447 - attribute \src "libresoc.v:135902.3-135910.6" - wire $0\ren_delay$11$next[0:0]$5431 - attribute \src "libresoc.v:135834.3-135835.43" - wire $0\ren_delay$11[0:0]$5408 - attribute \src "libresoc.v:135815.7-135815.28" - wire $0\ren_delay$11[0:0]$5449 - attribute \src "libresoc.v:135864.3-135872.6" - wire $0\ren_delay$next[0:0]$5423 - attribute \src "libresoc.v:135838.3-135839.35" - wire $0\ren_delay[0:0] - attribute \src "libresoc.v:135873.3-135882.6" - wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:135892.3-135901.6" - wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:135911.3-135920.6" - wire width 64 $1\issue__data_o[63:0] - attribute \src "libresoc.v:135883.3-135891.6" - wire $1\ren_delay$10$next[0:0]$5428 - attribute \src "libresoc.v:135902.3-135910.6" - wire $1\ren_delay$11$next[0:0]$5432 - attribute \src "libresoc.v:135864.3-135872.6" - wire $1\ren_delay$next[0:0]$5424 - attribute \src "libresoc.v:135809.7-135809.23" - wire $1\ren_delay[0:0] - attribute \src "libresoc.v:135873.3-135882.6" - wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:135892.3-135901.6" - wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:135861.26-135861.32" - wire width 64 $memrd$\memory$libresoc.v:135861$5419_DATA - attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 15 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 14 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 16 \dest1__wen - attribute \src "libresoc.v:135760.7-135760.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 2 \issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 5 \issue__addr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 7 \issue__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 4 \issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 3 \issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 6 \issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 3 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 3 \memory_w_addr$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 9 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 8 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 12 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 11 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \src2__ren - attribute \src "libresoc.v:135840.14-135840.20" - memory width 64 size 8 \memory - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5434 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5434 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 0 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5435 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5435 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 1 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5436 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5436 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 2 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5437 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5437 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 3 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5438 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5438 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 4 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5439 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5439 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 5 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5440 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5440 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 6 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5441 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5441 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 7 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:135861.26-135861.32" - cell $memrd $memrd$\memory$libresoc.v:135861$5419 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_0_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135861$5419_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:135862.30-135862.36" - cell $memrd $memrd$\memory$libresoc.v:135862$5420 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_1_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135862$5420_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:135863.30-135863.36" - cell $memrd $memrd$\memory$libresoc.v:135863$5421 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_2_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:135863$5421_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5442 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5442 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:135858$5405_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:135858$5405_DATA - connect \EN $memwr$\memory$libresoc.v:135858$5405_EN - end - attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5443 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5443 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:135859$5406_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:135859$5406_DATA - connect \EN $memwr$\memory$libresoc.v:135859$5406_EN - end - attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5450 - sync always - sync init + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + cell $not $not$libresoc.v:135210$5549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rb + connect \Y $not$libresoc.v:135210$5549_Y end - attribute \src "libresoc.v:135760.7-135760.20" - process $proc$libresoc.v:135760$5444 + attribute \src "libresoc.v:134931.7-134931.20" + process $proc$libresoc.v:134931$5551 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135809.7-135809.23" - process $proc$libresoc.v:135809$5445 - assign { } { } - assign $1\ren_delay[0:0] 1'0 - sync always - sync init - update \ren_delay $1\ren_delay[0:0] - end - attribute \src "libresoc.v:135811.7-135811.28" - process $proc$libresoc.v:135811$5446 - assign { } { } - assign $0\ren_delay$10[0:0]$5447 1'0 - sync always - sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5447 - end - attribute \src "libresoc.v:135815.7-135815.28" - process $proc$libresoc.v:135815$5448 - assign { } { } - assign $0\ren_delay$11[0:0]$5449 1'0 - sync always - sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5449 - end - attribute \src "libresoc.v:135834.3-135835.43" - process $proc$libresoc.v:135834$5407 - assign { } { } - assign $0\ren_delay$11[0:0]$5408 \ren_delay$11$next - sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5408 - end - attribute \src "libresoc.v:135836.3-135837.43" - process $proc$libresoc.v:135836$5409 - assign { } { } - assign $0\ren_delay$10[0:0]$5410 \ren_delay$10$next - sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5410 - end - attribute \src "libresoc.v:135838.3-135839.35" - process $proc$libresoc.v:135838$5411 - assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "libresoc.v:135854.3-135860.6" - process $proc$libresoc.v:135854$5412 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\memory$libresoc.v:135859$5406_ADDR[2:0]$5416 3'xxx - assign $0$memwr$\memory$libresoc.v:135859$5406_DATA[63:0]$5417 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:135859$5406_EN[63:0]$5418 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\memory$libresoc.v:135858$5405_ADDR[2:0]$5413 3'xxx - assign $0$memwr$\memory$libresoc.v:135858$5405_DATA[63:0]$5414 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:135858$5405_EN[63:0]$5415 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[2:0] \src1__addr - assign $0\_1_[2:0] \src2__addr - assign $0\_2_[2:0] \issue__addr - attribute \src "libresoc.v:135858.5-135858.62" - switch \issue__wen - attribute \src "libresoc.v:135858.9-135858.19" - case 1'1 - assign $0$memwr$\memory$libresoc.v:135858$5405_ADDR[2:0]$5413 \issue__addr$1 - assign $0$memwr$\memory$libresoc.v:135858$5405_DATA[63:0]$5414 \issue__data_i - assign $0$memwr$\memory$libresoc.v:135858$5405_EN[63:0]$5415 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - attribute \src "libresoc.v:135859.5-135859.58" - switch \dest1__wen - attribute \src "libresoc.v:135859.9-135859.19" - case 1'1 - assign $0$memwr$\memory$libresoc.v:135859$5406_ADDR[2:0]$5416 \dest1__addr - assign $0$memwr$\memory$libresoc.v:135859$5406_DATA[63:0]$5417 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:135859$5406_EN[63:0]$5418 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - sync posedge \coresync_clk - update \_0_ $0\_0_[2:0] - update \_1_ $0\_1_[2:0] - update \_2_ $0\_2_[2:0] - update $memwr$\memory$libresoc.v:135858$5405_ADDR $0$memwr$\memory$libresoc.v:135858$5405_ADDR[2:0]$5413 - update $memwr$\memory$libresoc.v:135858$5405_DATA $0$memwr$\memory$libresoc.v:135858$5405_DATA[63:0]$5414 - update $memwr$\memory$libresoc.v:135858$5405_EN $0$memwr$\memory$libresoc.v:135858$5405_EN[63:0]$5415 - update $memwr$\memory$libresoc.v:135859$5406_ADDR $0$memwr$\memory$libresoc.v:135859$5406_ADDR[2:0]$5416 - update $memwr$\memory$libresoc.v:135859$5406_DATA $0$memwr$\memory$libresoc.v:135859$5406_DATA[63:0]$5417 - update $memwr$\memory$libresoc.v:135859$5406_EN $0$memwr$\memory$libresoc.v:135859$5406_EN[63:0]$5418 - end - attribute \src "libresoc.v:135864.3-135872.6" - process $proc$libresoc.v:135864$5422 - assign { } { } - assign { } { } - assign $0\ren_delay$next[0:0]$5423 $1\ren_delay$next[0:0]$5424 - attribute \src "libresoc.v:135865.5-135865.29" - switch \initial - attribute \src "libresoc.v:135865.9-135865.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$next[0:0]$5424 1'0 - case - assign $1\ren_delay$next[0:0]$5424 \src1__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5423 - end - attribute \src "libresoc.v:135873.3-135882.6" - process $proc$libresoc.v:135873$5425 - assign { } { } - assign { } { } - assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:135874.5-135874.29" - switch \initial - attribute \src "libresoc.v:135874.9-135874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src1__data_o[63:0] \memory_r_data - case - assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src1__data_o $0\src1__data_o[63:0] - end - attribute \src "libresoc.v:135883.3-135891.6" - process $proc$libresoc.v:135883$5426 - assign { } { } - assign { } { } - assign $0\ren_delay$10$next[0:0]$5427 $1\ren_delay$10$next[0:0]$5428 - attribute \src "libresoc.v:135884.5-135884.29" - switch \initial - attribute \src "libresoc.v:135884.9-135884.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$10$next[0:0]$5428 1'0 - case - assign $1\ren_delay$10$next[0:0]$5428 \src2__ren - end - sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5427 - end - attribute \src "libresoc.v:135892.3-135901.6" - process $proc$libresoc.v:135892$5429 - assign { } { } + attribute \src "libresoc.v:135211.3-135222.6" + process $proc$libresoc.v:135211$5550 assign { } { } - assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:135893.5-135893.29" + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:135212.5-135212.29" switch \initial - attribute \src "libresoc.v:135893.9-135893.17" + attribute \src "libresoc.v:135212.9-135212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" + switch \logical_op__invert_in attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src2__data_o[63:0] \memory_r_data$4 - case - assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src2__data_o $0\src2__data_o[63:0] - end - attribute \src "libresoc.v:135902.3-135910.6" - process $proc$libresoc.v:135902$5430 - assign { } { } - assign { } { } - assign $0\ren_delay$11$next[0:0]$5431 $1\ren_delay$11$next[0:0]$5432 - attribute \src "libresoc.v:135903.5-135903.29" - switch \initial - attribute \src "libresoc.v:135903.9-135903.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\b[63:0] \$23 attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$11$next[0:0]$5432 1'0 - case - assign $1\ren_delay$11$next[0:0]$5432 \issue__ren - end - sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5431 - end - attribute \src "libresoc.v:135911.3-135920.6" - process $proc$libresoc.v:135911$5433 - assign { } { } - assign { } { } - assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "libresoc.v:135912.5-135912.29" - switch \initial - attribute \src "libresoc.v:135912.9-135912.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\issue__data_o[63:0] \memory_r_data$6 - case - assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\b[63:0] \rb end sync always - update \issue__data_o $0\issue__data_o[63:0] + update \b $0\b[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:135861$5419_DATA - connect \memory_r_data$4 $memrd$\memory$libresoc.v:135862$5420_DATA - connect \memory_r_data$6 $memrd$\memory$libresoc.v:135863$5421_DATA - connect \memory_w_data$9 \issue__data_i - connect \memory_w_en$7 \issue__wen - connect \memory_w_addr$8 \issue__addr$1 - connect \memory_w_data \dest1__data_i - connect \memory_w_en \dest1__wen - connect \memory_w_addr \dest1__addr - connect \memory_r_addr$5 \issue__addr - connect \memory_r_addr$3 \src2__addr - connect \memory_r_addr \src1__addr + connect \$23 $not$libresoc.v:135210$5549_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \b + connect \ra$20 \a + connect \a \ra end -attribute \src "libresoc.v:135934.1-137864.10" +attribute \src "libresoc.v:135233.1-135532.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" -module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 330 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 257 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 258 \cr_a_ok$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 259 \cr_a_ok$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 260 \cr_a_ok$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 261 \cr_a_ok$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 262 \cr_a_ok$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 3 \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 4 \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 25 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 75 \cu_busy_o$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 82 \cu_busy_o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 103 \cu_busy_o$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 31 \cu_busy_o$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 118 \cu_busy_o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 138 \cu_busy_o$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 157 \cu_busy_o$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 42 \cu_busy_o$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 54 \cu_busy_o$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 24 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 30 \cu_issue_i$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 74 \cu_issue_i$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 81 \cu_issue_i$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 102 \cu_issue_i$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 117 \cu_issue_i$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 137 \cu_issue_i$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 156 \cu_issue_i$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 41 \cu_issue_i$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 53 \cu_issue_i$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 160 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 163 \cu_rd__go_i$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 166 \cu_rd__go_i$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 169 \cu_rd__go_i$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 172 \cu_rd__go_i$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 175 \cu_rd__go_i$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 178 \cu_rd__go_i$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 181 \cu_rd__go_i$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 184 \cu_rd__go_i$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 209 \cu_rd__go_i$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 159 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 162 \cu_rd__rel_o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 165 \cu_rd__rel_o$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 168 \cu_rd__rel_o$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 171 \cu_rd__rel_o$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 174 \cu_rd__rel_o$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 177 \cu_rd__rel_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 180 \cu_rd__rel_o$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 183 \cu_rd__rel_o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 208 \cu_rd__rel_o$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 26 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 76 \cu_rdmaskn_i$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 83 \cu_rdmaskn_i$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 104 \cu_rdmaskn_i$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 119 \cu_rdmaskn_i$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 input 139 \cu_rdmaskn_i$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 158 \cu_rdmaskn_i$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 32 \cu_rdmaskn_i$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 43 \cu_rdmaskn_i$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 55 \cu_rdmaskn_i$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 5 \cu_st__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 2 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 221 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 242 \cu_wr__go_i$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 244 \cu_wr__go_i$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 293 \cu_wr__go_i$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 224 \cu_wr__go_i$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 227 \cu_wr__go_i$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 230 \cu_wr__go_i$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 233 \cu_wr__go_i$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 236 \cu_wr__go_i$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 239 \cu_wr__go_i$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 220 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 243 \cu_wr__rel_o$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 292 \cu_wr__rel_o$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 223 \cu_wr__rel_o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 226 \cu_wr__rel_o$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 229 \cu_wr__rel_o$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 232 \cu_wr__rel_o$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 235 \cu_wr__rel_o$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 238 \cu_wr__rel_o$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 241 \cu_wr__rel_o$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 245 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 246 \dest1_o$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 247 \dest1_o$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 248 \dest1_o$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 249 \dest1_o$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 250 \dest1_o$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 251 \dest1_o$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 252 \dest1_o$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 298 \dest1_o$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 output 256 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 263 \dest2_o$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 265 \dest2_o$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 266 \dest2_o$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 267 \dest2_o$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 268 \dest2_o$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 299 \dest2_o$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 301 \dest2_o$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 310 \dest2_o$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 264 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 272 \dest3_o$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 274 \dest3_o$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 281 \dest3_o$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 282 \dest3_o$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 300 \dest3_o$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 302 \dest3_o$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 305 \dest3_o$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 279 \dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 288 \dest4_o$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 289 \dest4_o$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 290 \dest4_o$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 306 \dest4_o$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 280 \dest5_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 287 \dest5_o$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 308 \dest5_o$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 273 \dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 254 \ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 291 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 294 \fast1_ok$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 295 \fast1_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 296 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 297 \fast2_ok$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 255 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 96 output 315 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 316 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 325 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire input 311 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 314 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 317 \ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 318 \ldst_port0_exc_$signal$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 319 \ldst_port0_exc_$signal$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 320 \ldst_port0_exc_$signal$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 321 \ldst_port0_exc_$signal$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 322 \ldst_port0_exc_$signal$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 323 \ldst_port0_exc_$signal$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 324 \ldst_port0_exc_$signal$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire output 312 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire output 313 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 326 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 327 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 328 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 329 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 307 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 303 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 304 \nia_ok$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 253 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 219 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 222 \o_ok$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 225 \o_ok$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 228 \o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 231 \o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 234 \o_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 237 \o_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 240 \o_ok$98 +module \input$78 + attribute \src "libresoc.v:135514.3-135525.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:135234.7-135234.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:135514.3-135525.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:135513.18-135513.100" + wire width 64 $not$libresoc.v:135513$5552_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:135234.7-135234.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 22 \oper_i_alu_alu0__data_len + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -214878,19 +214147,47 @@ module \fus attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 7 \oper_i_alu_alu0__fn_unit + wire width 13 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \oper_i_alu_alu0__imm_data__data + wire width 13 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_alu0__imm_data__ok + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 18 \oper_i_alu_alu0__input_carry + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 23 \oper_i_alu_alu0__insn + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -214966,53 +214263,7 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 6 \oper_i_alu_alu0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_alu_alu0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_alu_alu0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \oper_i_alu_alu0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 21 \oper_i_alu_alu0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_alu0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_alu_alu0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \oper_i_alu_alu0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_alu_alu0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_alu0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \oper_i_alu_alu0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_alu0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 33 \oper_i_alu_branch0__cia - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 35 \oper_i_alu_branch0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 37 \oper_i_alu_branch0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 38 \oper_i_alu_branch0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 36 \oper_i_alu_branch0__insn + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -215088,11 +214339,124 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 34 \oper_i_alu_branch0__insn_type + wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \oper_i_alu_branch0__is_32bit + wire input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \oper_i_alu_branch0__lk + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:135513$5552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:135513$5552_Y + end + attribute \src "libresoc.v:135234.7-135234.20" + process $proc$libresoc.v:135234$5554 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:135514.3-135525.6" + process $proc$libresoc.v:135514$5553 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:135515.5-135515.29" + switch \initial + attribute \src "libresoc.v:135515.9-135515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \logical_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + connect \$23 $not$libresoc.v:135513$5552_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "libresoc.v:135536.1-135788.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" +attribute \generator "nMigen" +module \input$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -215108,9 +214472,35 @@ module \fus attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 28 \oper_i_alu_cr0__fn_unit + wire width 13 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 29 \oper_i_alu_cr0__insn + wire width 13 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -215186,37 +214576,7 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 27 \oper_i_alu_cr0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 100 \oper_i_alu_div0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 85 \oper_i_alu_div0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 86 \oper_i_alu_div0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 87 \oper_i_alu_div0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 94 \oper_i_alu_div0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 101 \oper_i_alu_div0__insn + wire width 7 input 1 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -215292,1392 +214652,726 @@ module \fus attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 84 \oper_i_alu_div0__insn_type + wire width 7 output 17 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 92 \oper_i_alu_div0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 95 \oper_i_alu_div0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 98 \oper_i_alu_div0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 99 \oper_i_alu_div0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 90 \oper_i_alu_div0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 91 \oper_i_alu_div0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 97 \oper_i_alu_div0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 89 \oper_i_alu_div0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 88 \oper_i_alu_div0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 96 \oper_i_alu_div0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 93 \oper_i_alu_div0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 72 \oper_i_alu_logical0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 57 \oper_i_alu_logical0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 58 \oper_i_alu_logical0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 59 \oper_i_alu_logical0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 66 \oper_i_alu_logical0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 73 \oper_i_alu_logical0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 56 \oper_i_alu_logical0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 64 \oper_i_alu_logical0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 67 \oper_i_alu_logical0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 70 \oper_i_alu_logical0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 71 \oper_i_alu_logical0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 62 \oper_i_alu_logical0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 63 \oper_i_alu_logical0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 69 \oper_i_alu_logical0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 61 \oper_i_alu_logical0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 60 \oper_i_alu_logical0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 68 \oper_i_alu_logical0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 65 \oper_i_alu_logical0__zero_a - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 106 \oper_i_alu_mul0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 107 \oper_i_alu_mul0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 108 \oper_i_alu_mul0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 116 \oper_i_alu_mul0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 105 \oper_i_alu_mul0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 114 \oper_i_alu_mul0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 115 \oper_i_alu_mul0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 111 \oper_i_alu_mul0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 112 \oper_i_alu_mul0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 110 \oper_i_alu_mul0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 109 \oper_i_alu_mul0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 113 \oper_i_alu_mul0__write_cr0 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 121 \oper_i_alu_shift_rot0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 122 \oper_i_alu_shift_rot0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 123 \oper_i_alu_shift_rot0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 130 \oper_i_alu_shift_rot0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 132 \oper_i_alu_shift_rot0__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 136 \oper_i_alu_shift_rot0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 120 \oper_i_alu_shift_rot0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 129 \oper_i_alu_shift_rot0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 134 \oper_i_alu_shift_rot0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 135 \oper_i_alu_shift_rot0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 126 \oper_i_alu_shift_rot0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 127 \oper_i_alu_shift_rot0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 131 \oper_i_alu_shift_rot0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 133 \oper_i_alu_shift_rot0__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 125 \oper_i_alu_shift_rot0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 124 \oper_i_alu_shift_rot0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 128 \oper_i_alu_shift_rot0__write_cr0 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 78 \oper_i_alu_spr0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 79 \oper_i_alu_spr0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 77 \oper_i_alu_spr0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 80 \oper_i_alu_spr0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 48 \oper_i_alu_trap0__cia - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 45 \oper_i_alu_trap0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 46 \oper_i_alu_trap0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 44 \oper_i_alu_trap0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 49 \oper_i_alu_trap0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 52 \oper_i_alu_trap0__ldst_exc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 47 \oper_i_alu_trap0__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 51 \oper_i_alu_trap0__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 50 \oper_i_alu_trap0__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 152 \oper_i_ldst_ldst0__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 151 \oper_i_ldst_ldst0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 141 \oper_i_ldst_ldst0__fn_unit + wire input 10 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 142 \oper_i_ldst_ldst0__imm_data__data + wire output 26 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 143 \oper_i_ldst_ldst0__imm_data__ok + wire input 11 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 155 \oper_i_ldst_ldst0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire output 27 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 140 \oper_i_ldst_ldst0__insn_type + wire input 7 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 149 \oper_i_ldst_ldst0__is_32bit + wire output 23 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 150 \oper_i_ldst_ldst0__is_signed - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" + wire input 8 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 154 \oper_i_ldst_ldst0__ldst_mode + wire output 24 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 147 \oper_i_ldst_ldst0__oe__oe + wire input 6 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 148 \oper_i_ldst_ldst0__oe__ok + wire output 22 \mul_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 146 \oper_i_ldst_ldst0__rc__ok + wire input 5 \mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 145 \oper_i_ldst_ldst0__rc__rc + wire output 21 \mul_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 153 \oper_i_ldst_ldst0__sign_extend + wire input 9 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 144 \oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 309 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 161 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 164 \src1_i$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 167 \src1_i$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 170 \src1_i$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 173 \src1_i$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 176 \src1_i$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 179 \src1_i$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 182 \src1_i$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 185 \src1_i$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 213 \src1_i$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 186 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 187 \src2_i$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 188 \src2_i$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 189 \src2_i$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 190 \src2_i$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 191 \src2_i$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 192 \src2_i$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 193 \src2_i$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 216 \src2_i$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 218 \src2_i$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 194 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 195 \src3_i$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 196 \src3_i$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 197 \src3_i$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 199 \src3_i$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 200 \src3_i$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 input 206 \src3_i$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 210 \src3_i$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 214 \src3_i$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 215 \src3_i$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 198 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 201 \src4_i$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 202 \src4_i$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 207 \src4_i$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 217 \src4_i$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 204 \src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 205 \src5_i$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 211 \src5_i$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 203 \src6_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 212 \src6_i$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 269 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 270 \xer_ca_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 271 \xer_ca_ok$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 275 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 276 \xer_ov_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 277 \xer_ov_ok$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 278 \xer_ov_ok$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 283 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 284 \xer_so_ok$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 285 \xer_so_ok$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 286 \xer_so_ok$131 - attribute \module_not_derived 1 - attribute \src "libresoc.v:137496.8-137538.4" - cell \alu0 \alu0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok - connect \cu_busy_o \cu_busy_o - connect \cu_issue_i \cu_issue_i - connect \cu_rd__go_i \cu_rd__go_i - connect \cu_rd__rel_o \cu_rd__rel_o - connect \cu_rdmaskn_i \cu_rdmaskn_i - connect \cu_wr__go_i \cu_wr__go_i - connect \cu_wr__rel_o \cu_wr__rel_o - connect \dest1_o \dest1_o - connect \dest2_o \dest2_o$115 - connect \dest3_o \dest3_o$122 - connect \dest4_o \dest4_o - connect \dest5_o \dest5_o$132 - connect \o_ok \o_ok - connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len - connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data - connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok - connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry - connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn - connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type - connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in - connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out - connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit - connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed - connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok - connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry - connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok - connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 - connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a - connect \src1_i \src1_i - connect \src2_i \src2_i - connect \src3_i \src3_i$60 - connect \src4_i \src4_i$65 - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:137539.11-137566.4" - cell \branch0 \branch0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_busy_o \cu_busy_o$5 - connect \cu_issue_i \cu_issue_i$4 - connect \cu_rd__go_i \cu_rd__go_i$70 - connect \cu_rd__rel_o \cu_rd__rel_o$69 - connect \cu_rdmaskn_i \cu_rdmaskn_i$6 - connect \cu_wr__go_i \cu_wr__go_i$137 - connect \cu_wr__rel_o \cu_wr__rel_o$136 - connect \dest1_o \dest1_o$141 - connect \dest2_o \dest2_o$144 - connect \dest3_o \dest3_o$147 - connect \fast1_ok \fast1_ok - connect \fast2_ok \fast2_ok - connect \nia_ok \nia_ok - connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia - connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit - connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data - connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok - connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type - connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit - connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk - connect \src1_i \src1_i$74 - connect \src2_i \src2_i$77 - connect \src3_i \src3_i$71 + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 32 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 \rb + connect \b \rb + connect \ra$14 \a + connect \a \ra +end +attribute \src "libresoc.v:135792.1-136011.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.int" +attribute \generator "nMigen" +module \int + attribute \src "libresoc.v:135917.3-135923.6" + wire width 5 $0$memwr$\memory$libresoc.v:135922$5587_ADDR[4:0]$5596 + attribute \src "libresoc.v:135917.3-135923.6" + wire width 64 $0$memwr$\memory$libresoc.v:135922$5587_DATA[63:0]$5597 + attribute \src "libresoc.v:135917.3-135923.6" + wire width 64 $0$memwr$\memory$libresoc.v:135922$5587_EN[63:0]$5598 + attribute \src "libresoc.v:135917.3-135923.6" + wire width 5 $0\_0_[4:0] + attribute \src "libresoc.v:135917.3-135923.6" + wire width 5 $0\_1_[4:0] + attribute \src "libresoc.v:135917.3-135923.6" + wire width 5 $0\_2_[4:0] + attribute \src "libresoc.v:135917.3-135923.6" + wire width 5 $0\_3_[4:0] + attribute \src "libresoc.v:135946.3-135955.6" + wire width 64 $0\dmi__data_o[63:0] + attribute \src "libresoc.v:135793.7-135793.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:135937.3-135945.6" + wire $0\ren_delay$10$next[0:0]$5607 + attribute \src "libresoc.v:135870.3-135871.43" + wire $0\ren_delay$10[0:0]$5589 + attribute \src "libresoc.v:135836.7-135836.28" + wire $0\ren_delay$10[0:0]$5655 + attribute \src "libresoc.v:135966.3-135974.6" + wire $0\ren_delay$8$next[0:0]$5612 + attribute \src "libresoc.v:135874.3-135875.41" + wire $0\ren_delay$8[0:0]$5593 + attribute \src "libresoc.v:135840.7-135840.27" + wire $0\ren_delay$8[0:0]$5657 + attribute \src "libresoc.v:135985.3-135993.6" + wire $0\ren_delay$9$next[0:0]$5616 + attribute \src "libresoc.v:135872.3-135873.41" + wire $0\ren_delay$9[0:0]$5591 + attribute \src "libresoc.v:135844.7-135844.27" + wire $0\ren_delay$9[0:0]$5659 + attribute \src "libresoc.v:135928.3-135936.6" + wire $0\ren_delay$next[0:0]$5604 + attribute \src "libresoc.v:135876.3-135877.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:135956.3-135965.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "libresoc.v:135975.3-135984.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "libresoc.v:135994.3-136003.6" + wire width 64 $0\src3__data_o[63:0] + attribute \src "libresoc.v:135946.3-135955.6" + wire width 64 $1\dmi__data_o[63:0] + attribute \src "libresoc.v:135937.3-135945.6" + wire $1\ren_delay$10$next[0:0]$5608 + attribute \src "libresoc.v:135966.3-135974.6" + wire $1\ren_delay$8$next[0:0]$5613 + attribute \src "libresoc.v:135985.3-135993.6" + wire $1\ren_delay$9$next[0:0]$5617 + attribute \src "libresoc.v:135928.3-135936.6" + wire $1\ren_delay$next[0:0]$5605 + attribute \src "libresoc.v:135834.7-135834.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:135956.3-135965.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "libresoc.v:135975.3-135984.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "libresoc.v:135994.3-136003.6" + wire width 64 $1\src3__data_o[63:0] + attribute \src "libresoc.v:135924.26-135924.32" + wire width 64 $memrd$\memory$libresoc.v:135924$5599_DATA + attribute \src "libresoc.v:135925.30-135925.36" + wire width 64 $memrd$\memory$libresoc.v:135925$5600_DATA + attribute \src "libresoc.v:135926.30-135926.36" + wire width 64 $memrd$\memory$libresoc.v:135926$5601_DATA + attribute \src "libresoc.v:135927.30-135927.36" + wire width 64 $memrd$\memory$libresoc.v:135927$5602_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 5 $memwr$\memory$libresoc.v:135922$5587_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:135922$5587_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:135922$5587_EN + attribute \src "libresoc.v:135913.13-135913.16" + wire width 5 \_0_ + attribute \src "libresoc.v:135914.13-135914.16" + wire width 5 \_1_ + attribute \src "libresoc.v:135915.13-135915.16" + wire width 5 \_2_ + attribute \src "libresoc.v:135916.13-135916.16" + wire width 5 \_3_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 15 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 14 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 16 \dest1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 2 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 4 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 3 \dmi__ren + attribute \src "libresoc.v:135793.7-135793.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 5 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 6 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 7 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 9 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 8 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 12 \src3__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 11 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \src3__ren + attribute \src "libresoc.v:135878.14-135878.20" + memory width 64 size 32 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5619 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5619 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \module_not_derived 1 - attribute \src "libresoc.v:137567.7-137592.4" - cell \cr0 \cr0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$110 - connect \cu_busy_o \cu_busy_o$2 - connect \cu_issue_i \cu_issue_i$1 - connect \cu_rd__go_i \cu_rd__go_i$29 - connect \cu_rd__rel_o \cu_rd__rel_o$28 - connect \cu_rdmaskn_i \cu_rdmaskn_i$3 - connect \cu_wr__go_i \cu_wr__go_i$82 - connect \cu_wr__rel_o \cu_wr__rel_o$81 - connect \dest1_o \dest1_o$103 - connect \dest2_o \dest2_o - connect \dest3_o \dest3_o - connect \full_cr_ok \full_cr_ok - connect \o_ok \o_ok$80 - connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit - connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn - connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type - connect \src1_i \src1_i$30 - connect \src2_i \src2_i$52 - connect \src3_i \src3_i$67 - connect \src4_i \src4_i$68 - connect \src5_i \src5_i$72 - connect \src6_i \src6_i$73 + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5620 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5620 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \module_not_derived 1 - attribute \src "libresoc.v:137593.8-137632.4" - cell \div0 \div0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$112 - connect \cu_busy_o \cu_busy_o$17 - connect \cu_issue_i \cu_issue_i$16 - connect \cu_rd__go_i \cu_rd__go_i$41 - connect \cu_rd__rel_o \cu_rd__rel_o$40 - connect \cu_rdmaskn_i \cu_rdmaskn_i$18 - connect \cu_wr__go_i \cu_wr__go_i$94 - connect \cu_wr__rel_o \cu_wr__rel_o$93 - connect \dest1_o \dest1_o$107 - connect \dest2_o \dest2_o$117 - connect \dest3_o \dest3_o$127 - connect \dest4_o \dest4_o$134 - connect \o_ok \o_ok$92 - connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len - connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data - connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok - connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry - connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn - connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type - connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in - connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out - connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit - connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed - connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok - connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry - connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok - connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 - connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a - connect \src1_i \src1_i$42 - connect \src2_i \src2_i$55 - connect \src3_i \src3_i$62 - connect \xer_ov_ok \xer_ov_ok$125 - connect \xer_so_ok \xer_so_ok$130 + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5621 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5621 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \module_not_derived 1 - attribute \src "libresoc.v:137633.9-137687.4" - cell \ldst0 \ldst0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_ad__go_i \cu_ad__go_i - connect \cu_ad__rel_o \cu_ad__rel_o - connect \cu_busy_o \cu_busy_o$26 - connect \cu_issue_i \cu_issue_i$25 - connect \cu_rd__go_i \cu_rd__go_i$50 - connect \cu_rd__rel_o \cu_rd__rel_o$49 - connect \cu_rdmaskn_i \cu_rdmaskn_i$27 - connect \cu_st__go_i \cu_st__go_i - connect \cu_st__rel_o \cu_st__rel_o - connect \cu_wr__go_i \cu_wr__go_i$102 - connect \cu_wr__rel_o \cu_wr__rel_o$101 - connect \ea \ea - connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal - connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$151 - connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$152 - connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$153 - connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$154 - connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$155 - connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$156 - connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$157 - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \o \o - connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse - connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len - connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit - connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data - connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok - connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn - connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type - connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit - connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed - connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode - connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe - connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok - connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok - connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc - connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend - connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a - connect \src1_i \src1_i$51 - connect \src2_i \src2_i$58 - connect \src3_i \src3_i$59 + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5622 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5622 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \module_not_derived 1 - attribute \src "libresoc.v:137688.12-137723.4" - cell \logical0 \logical0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$111 - connect \cu_busy_o \cu_busy_o$11 - connect \cu_issue_i \cu_issue_i$10 - connect \cu_rd__go_i \cu_rd__go_i$35 - connect \cu_rd__rel_o \cu_rd__rel_o$34 - connect \cu_rdmaskn_i \cu_rdmaskn_i$12 - connect \cu_wr__go_i \cu_wr__go_i$88 - connect \cu_wr__rel_o \cu_wr__rel_o$87 - connect \dest1_o \dest1_o$105 - connect \dest2_o \dest2_o$116 - connect \o_ok \o_ok$86 - connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len - connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data - connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok - connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry - connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn - connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type - connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in - connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out - connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit - connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed - connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok - connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry - connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok - connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 - connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a - connect \src1_i \src1_i$36 - connect \src2_i \src2_i$54 - connect \src3_i \src3_i$61 + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5623 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5623 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \module_not_derived 1 - attribute \src "libresoc.v:137724.8-137757.4" - cell \mul0 \mul0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$113 - connect \cu_busy_o \cu_busy_o$20 - connect \cu_issue_i \cu_issue_i$19 - connect \cu_rd__go_i \cu_rd__go_i$44 - connect \cu_rd__rel_o \cu_rd__rel_o$43 - connect \cu_rdmaskn_i \cu_rdmaskn_i$21 - connect \cu_wr__go_i \cu_wr__go_i$97 - connect \cu_wr__rel_o \cu_wr__rel_o$96 - connect \dest1_o \dest1_o$108 - connect \dest2_o \dest2_o$118 - connect \dest3_o \dest3_o$128 - connect \dest4_o \dest4_o$135 - connect \o_ok \o_ok$95 - connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit - connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data - connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok - connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn - connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type - connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit - connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed - connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe - connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok - connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok - connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc - connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 - connect \src1_i \src1_i$45 - connect \src2_i \src2_i$56 - connect \src3_i \src3_i$63 - connect \xer_ov_ok \xer_ov_ok$126 - connect \xer_so_ok \xer_so_ok$131 + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5624 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5624 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \module_not_derived 1 - attribute \src "libresoc.v:137758.13-137796.4" - cell \shiftrot0 \shiftrot0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$114 - connect \cu_busy_o \cu_busy_o$23 - connect \cu_issue_i \cu_issue_i$22 - connect \cu_rd__go_i \cu_rd__go_i$47 - connect \cu_rd__rel_o \cu_rd__rel_o$46 - connect \cu_rdmaskn_i \cu_rdmaskn_i$24 - connect \cu_wr__go_i \cu_wr__go_i$100 - connect \cu_wr__rel_o \cu_wr__rel_o$99 - connect \dest1_o \dest1_o$109 - connect \dest2_o \dest2_o$119 - connect \dest3_o \dest3_o$123 - connect \o_ok \o_ok$98 - connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit - connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data - connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok - connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry - connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr - connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn - connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type - connect \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__invert_in - connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit - connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed - connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe - connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok - connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry - connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr - connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok - connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc - connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 - connect \src1_i \src1_i$48 - connect \src2_i \src2_i$57 - connect \src3_i \src3_i - connect \src4_i \src4_i$64 - connect \src5_i \src5_i - connect \xer_ca_ok \xer_ca_ok$121 + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5625 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5625 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \module_not_derived 1 - attribute \src "libresoc.v:137797.8-137829.4" - cell \spr0 \spr0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_busy_o \cu_busy_o$14 - connect \cu_issue_i \cu_issue_i$13 - connect \cu_rd__go_i \cu_rd__go_i$38 - connect \cu_rd__rel_o \cu_rd__rel_o$37 - connect \cu_rdmaskn_i \cu_rdmaskn_i$15 - connect \cu_wr__go_i \cu_wr__go_i$91 - connect \cu_wr__rel_o \cu_wr__rel_o$90 - connect \dest1_o \dest1_o$106 - connect \dest2_o \dest2_o$150 - connect \dest3_o \dest3_o$143 - connect \dest4_o \dest4_o$133 - connect \dest5_o \dest5_o - connect \dest6_o \dest6_o - connect \fast1_ok \fast1_ok$139 - connect \o_ok \o_ok$89 - connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit - connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn - connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type - connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit - connect \spr1_ok \spr1_ok - connect \src1_i \src1_i$39 - connect \src2_i \src2_i$79 - connect \src3_i \src3_i$76 - connect \src4_i \src4_i - connect \src5_i \src5_i$66 - connect \src6_i \src6_i - connect \xer_ca_ok \xer_ca_ok$120 - connect \xer_ov_ok \xer_ov_ok$124 - connect \xer_so_ok \xer_so_ok$129 + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5626 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5626 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \module_not_derived 1 - attribute \src "libresoc.v:137830.9-137863.4" - cell \trap0 \trap0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_busy_o \cu_busy_o$8 - connect \cu_issue_i \cu_issue_i$7 - connect \cu_rd__go_i \cu_rd__go_i$32 - connect \cu_rd__rel_o \cu_rd__rel_o$31 - connect \cu_rdmaskn_i \cu_rdmaskn_i$9 - connect \cu_wr__go_i \cu_wr__go_i$85 - connect \cu_wr__rel_o \cu_wr__rel_o$84 - connect \dest1_o \dest1_o$104 - connect \dest2_o \dest2_o$142 - connect \dest3_o \dest3_o$145 - connect \dest4_o \dest4_o$148 - connect \dest5_o \dest5_o$149 - connect \fast1_ok \fast1_ok$138 - connect \fast2_ok \fast2_ok$140 - connect \msr_ok \msr_ok - connect \nia_ok \nia_ok$146 - connect \o_ok \o_ok$83 - connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia - connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit - connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn - connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type - connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit - connect \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__ldst_exc - connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr - connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr - connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype - connect \src1_i \src1_i$33 - connect \src2_i \src2_i$53 - connect \src3_i \src3_i$75 - connect \src4_i \src4_i$78 + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5627 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5627 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 8 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end -end -attribute \src "libresoc.v:137868.1-137926.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" -attribute \generator "nMigen" -module \idx_l - attribute \src "libresoc.v:137869.7-137869.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:137914.3-137922.6" - wire $0\q_int$next[0:0]$5461 - attribute \src "libresoc.v:137912.3-137913.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:137914.3-137922.6" - wire $1\q_int$next[0:0]$5462 - attribute \src "libresoc.v:137893.7-137893.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:137904.17-137904.96" - wire $and$libresoc.v:137904$5451_Y - attribute \src "libresoc.v:137909.17-137909.96" - wire $and$libresoc.v:137909$5456_Y - attribute \src "libresoc.v:137906.18-137906.95" - wire $not$libresoc.v:137906$5453_Y - attribute \src "libresoc.v:137908.17-137908.94" - wire $not$libresoc.v:137908$5455_Y - attribute \src "libresoc.v:137911.17-137911.94" - wire $not$libresoc.v:137911$5458_Y - attribute \src "libresoc.v:137905.18-137905.100" - wire $or$libresoc.v:137905$5452_Y - attribute \src "libresoc.v:137907.18-137907.101" - wire $or$libresoc.v:137907$5454_Y - attribute \src "libresoc.v:137910.17-137910.99" - wire $or$libresoc.v:137910$5457_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:137869.7-137869.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 2 \q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 4 \r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 3 \s_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:137904$5451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:137904$5451_Y + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5628 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5628 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 9 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:137909$5456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:137909$5456_Y + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5629 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5629 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 10 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:137906$5453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_idx_l - connect \Y $not$libresoc.v:137906$5453_Y + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5630 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5630 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 11 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:137908$5455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_idx_l - connect \Y $not$libresoc.v:137908$5455_Y + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5631 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5631 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 12 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:137911$5458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_idx_l - connect \Y $not$libresoc.v:137911$5458_Y + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5632 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5632 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 13 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:137905$5452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_idx_l - connect \Y $or$libresoc.v:137905$5452_Y + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5633 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5633 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 14 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:137907$5454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_idx_l - connect \B \q_int - connect \Y $or$libresoc.v:137907$5454_Y + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5634 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5634 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 15 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:137910$5457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_idx_l - connect \Y $or$libresoc.v:137910$5457_Y + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5635 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5635 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 16 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5636 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5636 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 17 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5637 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5637 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 18 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5638 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5638 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 19 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5639 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5639 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 20 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5640 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5640 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 21 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5641 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5641 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 22 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5642 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5642 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 23 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5643 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5643 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 24 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5644 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5644 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 25 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5645 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5645 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 26 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5646 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5646 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 27 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5647 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5647 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 28 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5648 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5648 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 29 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5649 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5649 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 30 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5650 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5650 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 31 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:135924.26-135924.32" + cell $memrd $memrd$\memory$libresoc.v:135924$5599 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:135924$5599_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:135925.30-135925.36" + cell $memrd $memrd$\memory$libresoc.v:135925$5600 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:135925$5600_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:135926.30-135926.36" + cell $memrd $memrd$\memory$libresoc.v:135926$5601 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:135926$5601_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:135927.30-135927.36" + cell $memrd $memrd$\memory$libresoc.v:135927$5602 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_3_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:135927$5602_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5651 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5651 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:135922$5587_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:135922$5587_DATA + connect \EN $memwr$\memory$libresoc.v:135922$5587_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$5660 + sync always + sync init end - attribute \src "libresoc.v:137869.7-137869.20" - process $proc$libresoc.v:137869$5463 + attribute \src "libresoc.v:135793.7-135793.20" + process $proc$libresoc.v:135793$5652 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137893.7-137893.19" - process $proc$libresoc.v:137893$5464 + attribute \src "libresoc.v:135834.7-135834.23" + process $proc$libresoc.v:135834$5653 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $1\ren_delay[0:0] 1'0 sync always sync init - update \q_int $1\q_int[0:0] + update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:137912.3-137913.27" - process $proc$libresoc.v:137912$5459 + attribute \src "libresoc.v:135836.7-135836.28" + process $proc$libresoc.v:135836$5654 assign { } { } - assign $0\q_int[0:0] \q_int$next + assign $0\ren_delay$10[0:0]$5655 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5655 + end + attribute \src "libresoc.v:135840.7-135840.27" + process $proc$libresoc.v:135840$5656 + assign { } { } + assign $0\ren_delay$8[0:0]$5657 1'0 + sync always + sync init + update \ren_delay$8 $0\ren_delay$8[0:0]$5657 + end + attribute \src "libresoc.v:135844.7-135844.27" + process $proc$libresoc.v:135844$5658 + assign { } { } + assign $0\ren_delay$9[0:0]$5659 1'0 + sync always + sync init + update \ren_delay$9 $0\ren_delay$9[0:0]$5659 + end + attribute \src "libresoc.v:135870.3-135871.43" + process $proc$libresoc.v:135870$5588 + assign { } { } + assign $0\ren_delay$10[0:0]$5589 \ren_delay$10$next sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \ren_delay$10 $0\ren_delay$10[0:0]$5589 + end + attribute \src "libresoc.v:135872.3-135873.41" + process $proc$libresoc.v:135872$5590 + assign { } { } + assign $0\ren_delay$9[0:0]$5591 \ren_delay$9$next + sync posedge \coresync_clk + update \ren_delay$9 $0\ren_delay$9[0:0]$5591 + end + attribute \src "libresoc.v:135874.3-135875.41" + process $proc$libresoc.v:135874$5592 + assign { } { } + assign $0\ren_delay$8[0:0]$5593 \ren_delay$8$next + sync posedge \coresync_clk + update \ren_delay$8 $0\ren_delay$8[0:0]$5593 + end + attribute \src "libresoc.v:135876.3-135877.35" + process $proc$libresoc.v:135876$5594 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:135917.3-135923.6" + process $proc$libresoc.v:135917$5595 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:135922$5587_ADDR[4:0]$5596 5'xxxxx + assign $0$memwr$\memory$libresoc.v:135922$5587_DATA[63:0]$5597 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:135922$5587_EN[63:0]$5598 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[4:0] \src1__addr + assign $0\_1_[4:0] \src2__addr + assign $0\_2_[4:0] \src3__addr + assign $0\_3_[4:0] \dmi__addr + attribute \src "libresoc.v:135922.5-135922.58" + switch \dest1__wen + attribute \src "libresoc.v:135922.9-135922.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:135922$5587_ADDR[4:0]$5596 \dest1__addr + assign $0$memwr$\memory$libresoc.v:135922$5587_DATA[63:0]$5597 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:135922$5587_EN[63:0]$5598 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[4:0] + update \_1_ $0\_1_[4:0] + update \_2_ $0\_2_[4:0] + update \_3_ $0\_3_[4:0] + update $memwr$\memory$libresoc.v:135922$5587_ADDR $0$memwr$\memory$libresoc.v:135922$5587_ADDR[4:0]$5596 + update $memwr$\memory$libresoc.v:135922$5587_DATA $0$memwr$\memory$libresoc.v:135922$5587_DATA[63:0]$5597 + update $memwr$\memory$libresoc.v:135922$5587_EN $0$memwr$\memory$libresoc.v:135922$5587_EN[63:0]$5598 end - attribute \src "libresoc.v:137914.3-137922.6" - process $proc$libresoc.v:137914$5460 + attribute \src "libresoc.v:135928.3-135936.6" + process $proc$libresoc.v:135928$5603 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$5461 $1\q_int$next[0:0]$5462 - attribute \src "libresoc.v:137915.5-137915.29" + assign $0\ren_delay$next[0:0]$5604 $1\ren_delay$next[0:0]$5605 + attribute \src "libresoc.v:135929.5-135929.29" switch \initial - attribute \src "libresoc.v:137915.9-137915.17" + attribute \src "libresoc.v:135929.9-135929.17" case 1'1 case end @@ -216686,13505 +215380,15258 @@ module \idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$5462 1'0 + assign $1\ren_delay$next[0:0]$5605 1'0 case - assign $1\q_int$next[0:0]$5462 \$5 + assign $1\ren_delay$next[0:0]$5605 \src1__ren end sync always - update \q_int$next $0\q_int$next[0:0]$5461 + update \ren_delay$next $0\ren_delay$next[0:0]$5604 end - connect \$9 $and$libresoc.v:137904$5451_Y - connect \$11 $or$libresoc.v:137905$5452_Y - connect \$13 $not$libresoc.v:137906$5453_Y - connect \$15 $or$libresoc.v:137907$5454_Y - connect \$1 $not$libresoc.v:137908$5455_Y - connect \$3 $and$libresoc.v:137909$5456_Y - connect \$5 $or$libresoc.v:137910$5457_Y - connect \$7 $not$libresoc.v:137911$5458_Y - connect \qlq_idx_l \$15 - connect \qn_idx_l \$13 - connect \q_idx_l \$11 + attribute \src "libresoc.v:135937.3-135945.6" + process $proc$libresoc.v:135937$5606 + assign { } { } + assign { } { } + assign $0\ren_delay$10$next[0:0]$5607 $1\ren_delay$10$next[0:0]$5608 + attribute \src "libresoc.v:135938.5-135938.29" + switch \initial + attribute \src "libresoc.v:135938.9-135938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$10$next[0:0]$5608 1'0 + case + assign $1\ren_delay$10$next[0:0]$5608 \dmi__ren + end + sync always + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5607 + end + attribute \src "libresoc.v:135946.3-135955.6" + process $proc$libresoc.v:135946$5609 + assign { } { } + assign { } { } + assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] + attribute \src "libresoc.v:135947.5-135947.29" + switch \initial + attribute \src "libresoc.v:135947.9-135947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi__data_o[63:0] \memory_r_data$7 + case + assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi__data_o $0\dmi__data_o[63:0] + end + attribute \src "libresoc.v:135956.3-135965.6" + process $proc$libresoc.v:135956$5610 + assign { } { } + assign { } { } + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:135957.5-135957.29" + switch \initial + attribute \src "libresoc.v:135957.9-135957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[63:0] \memory_r_data + case + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src1__data_o $0\src1__data_o[63:0] + end + attribute \src "libresoc.v:135966.3-135974.6" + process $proc$libresoc.v:135966$5611 + assign { } { } + assign { } { } + assign $0\ren_delay$8$next[0:0]$5612 $1\ren_delay$8$next[0:0]$5613 + attribute \src "libresoc.v:135967.5-135967.29" + switch \initial + attribute \src "libresoc.v:135967.9-135967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$8$next[0:0]$5613 1'0 + case + assign $1\ren_delay$8$next[0:0]$5613 \src2__ren + end + sync always + update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5612 + end + attribute \src "libresoc.v:135975.3-135984.6" + process $proc$libresoc.v:135975$5614 + assign { } { } + assign { } { } + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "libresoc.v:135976.5-135976.29" + switch \initial + attribute \src "libresoc.v:135976.9-135976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$8 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[63:0] \memory_r_data$3 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "libresoc.v:135985.3-135993.6" + process $proc$libresoc.v:135985$5615 + assign { } { } + assign { } { } + assign $0\ren_delay$9$next[0:0]$5616 $1\ren_delay$9$next[0:0]$5617 + attribute \src "libresoc.v:135986.5-135986.29" + switch \initial + attribute \src "libresoc.v:135986.9-135986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$9$next[0:0]$5617 1'0 + case + assign $1\ren_delay$9$next[0:0]$5617 \src3__ren + end + sync always + update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5616 + end + attribute \src "libresoc.v:135994.3-136003.6" + process $proc$libresoc.v:135994$5618 + assign { } { } + assign { } { } + assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] + attribute \src "libresoc.v:135995.5-135995.29" + switch \initial + attribute \src "libresoc.v:135995.9-135995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[63:0] \memory_r_data$5 + case + assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src3__data_o $0\src3__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:135924$5599_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:135925$5600_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:135926$5601_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:135927$5602_DATA + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$6 \dmi__addr + connect \memory_r_addr$4 \src3__addr + connect \memory_r_addr$2 \src2__addr + connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:137930.1-138309.10" +attribute \src "libresoc.v:136015.1-138738.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.imem" +attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" -module \imem - attribute \src "libresoc.v:138261.3-138270.6" - wire $0\a_busy_o[0:0] - attribute \src "libresoc.v:138241.3-138260.6" - wire width 45 $0\f_badaddr_o$next[44:0]$5533 - attribute \src "libresoc.v:138072.3-138073.39" - wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:138271.3-138288.6" - wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:138218.3-138240.6" - wire $0\f_fetch_err_o$next[0:0]$5528 - attribute \src "libresoc.v:138074.3-138075.43" - wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:138289.3-138306.6" - wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:138195.3-138217.6" - wire width 45 $0\ibus__adr$next[44:0]$5523 - attribute \src "libresoc.v:138076.3-138077.35" - wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:138086.3-138113.6" - wire $0\ibus__cyc$next[0:0]$5499 - attribute \src "libresoc.v:138084.3-138085.35" - wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:138142.3-138169.6" - wire width 8 $0\ibus__sel$next[7:0]$5511 - attribute \src "libresoc.v:138080.3-138081.35" - wire width 8 $0\ibus__sel[7:0] - attribute \src "libresoc.v:138114.3-138141.6" - wire $0\ibus__stb$next[0:0]$5505 - attribute \src "libresoc.v:138082.3-138083.35" - wire $0\ibus__stb[0:0] - attribute \src "libresoc.v:138170.3-138194.6" - wire width 64 $0\ibus_rdata$next[63:0]$5517 - attribute \src "libresoc.v:138078.3-138079.37" - wire width 64 $0\ibus_rdata[63:0] - attribute \src "libresoc.v:137931.7-137931.20" +module \jtag + attribute \src "libresoc.v:138168.3-138194.6" + wire $0\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:137816.3-137831.6" + wire $0\TAP_tdo[0:0] + attribute \src "libresoc.v:138329.3-138361.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$6072 + attribute \src "libresoc.v:137719.3-137720.41" + wire width 4 $0\dmi0__addr_i[3:0] + attribute \src "libresoc.v:138415.3-138441.6" + wire width 64 $0\dmi0__din$next[63:0]$6085 + attribute \src "libresoc.v:137715.3-137716.35" + wire width 64 $0\dmi0__din[63:0] + attribute \src "libresoc.v:138018.3-138034.6" + wire $0\dmi0_addrsr__oe$next[0:0]$6009 + attribute \src "libresoc.v:137747.3-137748.47" + wire $0\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:138035.3-138055.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6013 + attribute \src "libresoc.v:137745.3-137746.47" + wire width 8 $0\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:138000.3-138008.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$6003 + attribute \src "libresoc.v:137751.3-137752.63" + wire $0\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:138009.3-138017.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6006 + attribute \src "libresoc.v:137749.3-137750.73" + wire $0\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:138442.3-138462.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$6090 + attribute \src "libresoc.v:137713.3-137714.45" + wire width 64 $0\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:138074.3-138090.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$6024 + attribute \src "libresoc.v:137739.3-137740.47" + wire width 2 $0\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:138091.3-138111.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$6028 + attribute \src "libresoc.v:137737.3-137738.47" + wire width 64 $0\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:138056.3-138064.6" + wire $0\dmi0_datasr_update_core$next[0:0]$6018 + attribute \src "libresoc.v:137743.3-137744.63" + wire $0\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:138065.3-138073.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$6021 + attribute \src "libresoc.v:137741.3-137742.73" + wire $0\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:138362.3-138414.6" + wire width 3 $0\fsm_state$503$next[2:0]$6078 + attribute \src "libresoc.v:137717.3-137718.45" + wire width 3 $0\fsm_state$503[2:0]$5924 + attribute \src "libresoc.v:136661.13-136661.35" + wire width 3 $0\fsm_state$503[2:0]$6127 + attribute \src "libresoc.v:138228.3-138280.6" + wire width 3 $0\fsm_state$next[2:0]$6055 + attribute \src "libresoc.v:137725.3-137726.35" + wire width 3 $0\fsm_state[2:0] + attribute \src "libresoc.v:136016.7-136016.20" wire $0\initial[0:0] - attribute \src "libresoc.v:138261.3-138270.6" - wire $1\a_busy_o[0:0] - attribute \src "libresoc.v:138241.3-138260.6" - wire width 45 $1\f_badaddr_o$next[44:0]$5534 - attribute \src "libresoc.v:137995.14-137995.44" - wire width 45 $1\f_badaddr_o[44:0] - attribute \src "libresoc.v:138271.3-138288.6" - wire $1\f_busy_o[0:0] - attribute \src "libresoc.v:138218.3-138240.6" - wire $1\f_fetch_err_o$next[0:0]$5529 - attribute \src "libresoc.v:138002.7-138002.27" - wire $1\f_fetch_err_o[0:0] - attribute \src "libresoc.v:138289.3-138306.6" - wire width 64 $1\f_instr_o[63:0] - attribute \src "libresoc.v:138195.3-138217.6" - wire width 45 $1\ibus__adr$next[44:0]$5524 - attribute \src "libresoc.v:138016.14-138016.42" - wire width 45 $1\ibus__adr[44:0] - attribute \src "libresoc.v:138086.3-138113.6" - wire $1\ibus__cyc$next[0:0]$5500 - attribute \src "libresoc.v:138021.7-138021.23" - wire $1\ibus__cyc[0:0] - attribute \src "libresoc.v:138142.3-138169.6" - wire width 8 $1\ibus__sel$next[7:0]$5512 - attribute \src "libresoc.v:138030.13-138030.30" - wire width 8 $1\ibus__sel[7:0] - attribute \src "libresoc.v:138114.3-138141.6" - wire $1\ibus__stb$next[0:0]$5506 - attribute \src "libresoc.v:138035.7-138035.23" - wire $1\ibus__stb[0:0] - attribute \src "libresoc.v:138170.3-138194.6" - wire width 64 $1\ibus_rdata$next[63:0]$5518 - attribute \src "libresoc.v:138039.14-138039.47" - wire width 64 $1\ibus_rdata[63:0] - attribute \src "libresoc.v:138241.3-138260.6" - wire width 45 $2\f_badaddr_o$next[44:0]$5535 - attribute \src "libresoc.v:138271.3-138288.6" - wire $2\f_busy_o[0:0] - attribute \src "libresoc.v:138218.3-138240.6" - wire $2\f_fetch_err_o$next[0:0]$5530 - attribute \src "libresoc.v:138289.3-138306.6" - wire width 64 $2\f_instr_o[63:0] - attribute \src "libresoc.v:138195.3-138217.6" - wire width 45 $2\ibus__adr$next[44:0]$5525 - attribute \src "libresoc.v:138086.3-138113.6" - wire $2\ibus__cyc$next[0:0]$5501 - attribute \src "libresoc.v:138142.3-138169.6" - wire width 8 $2\ibus__sel$next[7:0]$5513 - attribute \src "libresoc.v:138114.3-138141.6" - wire $2\ibus__stb$next[0:0]$5507 - attribute \src "libresoc.v:138170.3-138194.6" - wire width 64 $2\ibus_rdata$next[63:0]$5519 - attribute \src "libresoc.v:138241.3-138260.6" - wire width 45 $3\f_badaddr_o$next[44:0]$5536 - attribute \src "libresoc.v:138218.3-138240.6" - wire $3\f_fetch_err_o$next[0:0]$5531 - attribute \src "libresoc.v:138195.3-138217.6" - wire width 45 $3\ibus__adr$next[44:0]$5526 - attribute \src "libresoc.v:138086.3-138113.6" - wire $3\ibus__cyc$next[0:0]$5502 - attribute \src "libresoc.v:138142.3-138169.6" - wire width 8 $3\ibus__sel$next[7:0]$5514 - attribute \src "libresoc.v:138114.3-138141.6" - wire $3\ibus__stb$next[0:0]$5508 - attribute \src "libresoc.v:138170.3-138194.6" - wire width 64 $3\ibus_rdata$next[63:0]$5520 - attribute \src "libresoc.v:138086.3-138113.6" - wire $4\ibus__cyc$next[0:0]$5503 - attribute \src "libresoc.v:138142.3-138169.6" - wire width 8 $4\ibus__sel$next[7:0]$5515 - attribute \src "libresoc.v:138114.3-138141.6" - wire $4\ibus__stb$next[0:0]$5509 - attribute \src "libresoc.v:138170.3-138194.6" - wire width 64 $4\ibus_rdata$next[63:0]$5521 - attribute \src "libresoc.v:138048.18-138048.110" - wire $and$libresoc.v:138048$5467_Y - attribute \src "libresoc.v:138054.18-138054.110" - wire $and$libresoc.v:138054$5473_Y - attribute \src "libresoc.v:138059.18-138059.110" - wire $and$libresoc.v:138059$5478_Y - attribute \src "libresoc.v:138062.17-138062.108" - wire $and$libresoc.v:138062$5481_Y - attribute \src "libresoc.v:138065.18-138065.110" - wire $and$libresoc.v:138065$5484_Y - attribute \src "libresoc.v:138066.18-138066.115" - wire $and$libresoc.v:138066$5485_Y - attribute \src "libresoc.v:138068.18-138068.115" - wire $and$libresoc.v:138068$5487_Y - attribute \src "libresoc.v:138047.18-138047.105" - wire $not$libresoc.v:138047$5466_Y - attribute \src "libresoc.v:138050.18-138050.105" - wire $not$libresoc.v:138050$5469_Y - attribute \src "libresoc.v:138051.17-138051.104" - wire $not$libresoc.v:138051$5470_Y - attribute \src "libresoc.v:138053.18-138053.105" - wire $not$libresoc.v:138053$5472_Y - attribute \src "libresoc.v:138056.18-138056.105" - wire $not$libresoc.v:138056$5475_Y - attribute \src "libresoc.v:138058.18-138058.105" - wire $not$libresoc.v:138058$5477_Y - attribute \src "libresoc.v:138061.18-138061.105" - wire $not$libresoc.v:138061$5480_Y - attribute \src "libresoc.v:138064.18-138064.105" - wire $not$libresoc.v:138064$5483_Y - attribute \src "libresoc.v:138067.18-138067.105" - wire $not$libresoc.v:138067$5486_Y - attribute \src "libresoc.v:138069.18-138069.105" - wire $not$libresoc.v:138069$5488_Y - attribute \src "libresoc.v:138071.17-138071.104" - wire $not$libresoc.v:138071$5490_Y - attribute \src "libresoc.v:138046.17-138046.103" - wire $or$libresoc.v:138046$5465_Y - attribute \src "libresoc.v:138049.18-138049.115" - wire $or$libresoc.v:138049$5468_Y - attribute \src "libresoc.v:138052.18-138052.106" - wire $or$libresoc.v:138052$5471_Y - attribute \src "libresoc.v:138055.18-138055.115" - wire $or$libresoc.v:138055$5474_Y - attribute \src "libresoc.v:138057.18-138057.106" - wire $or$libresoc.v:138057$5476_Y - attribute \src "libresoc.v:138060.18-138060.115" - wire $or$libresoc.v:138060$5479_Y - attribute \src "libresoc.v:138063.18-138063.106" - wire $or$libresoc.v:138063$5482_Y - attribute \src "libresoc.v:138070.17-138070.114" - wire $or$libresoc.v:138070$5489_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + attribute \src "libresoc.v:138512.3-138532.6" + wire width 154 $0\io_bd$next[153:0]$6110 + attribute \src "libresoc.v:137777.3-137778.27" + wire width 154 $0\io_bd[153:0] + attribute \src "libresoc.v:138494.3-138511.6" + wire width 154 $0\io_sr$next[153:0]$6106 + attribute \src "libresoc.v:137779.3-137780.27" + wire width 154 $0\io_sr[153:0] + attribute \src "libresoc.v:138195.3-138227.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$6049 + attribute \src "libresoc.v:137727.3-137728.41" + wire width 29 $0\jtag_wb__adr[28:0] + attribute \src "libresoc.v:138281.3-138307.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$6062 + attribute \src "libresoc.v:137723.3-137724.45" + wire width 64 $0\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:137906.3-137922.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5979 + attribute \src "libresoc.v:137763.3-137764.53" + wire $0\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:137923.3-137943.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5983 + attribute \src "libresoc.v:137761.3-137762.53" + wire width 29 $0\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:137888.3-137896.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5973 + attribute \src "libresoc.v:137767.3-137768.69" + wire $0\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:137897.3-137905.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5976 + attribute \src "libresoc.v:137765.3-137766.79" + wire $0\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:138308.3-138328.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6067 + attribute \src "libresoc.v:137721.3-137722.51" + wire width 64 $0\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:137962.3-137978.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5994 + attribute \src "libresoc.v:137755.3-137756.53" + wire width 2 $0\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:137979.3-137999.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5998 + attribute \src "libresoc.v:137753.3-137754.53" + wire width 64 $0\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:137944.3-137952.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$5988 + attribute \src "libresoc.v:137759.3-137760.69" + wire $0\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:137953.3-137961.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5991 + attribute \src "libresoc.v:137757.3-137758.79" + wire $0\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:137850.3-137866.6" + wire $0\sr0__oe$next[0:0]$5964 + attribute \src "libresoc.v:137771.3-137772.31" + wire $0\sr0__oe[0:0] + attribute \src "libresoc.v:137867.3-137887.6" + wire width 3 $0\sr0_reg$next[2:0]$5968 + attribute \src "libresoc.v:137769.3-137770.31" + wire width 3 $0\sr0_reg[2:0] + attribute \src "libresoc.v:137832.3-137840.6" + wire $0\sr0_update_core$next[0:0]$5958 + attribute \src "libresoc.v:137775.3-137776.47" + wire $0\sr0_update_core[0:0] + attribute \src "libresoc.v:137841.3-137849.6" + wire $0\sr0_update_core_prev$next[0:0]$5961 + attribute \src "libresoc.v:137773.3-137774.57" + wire $0\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:138484.3-138493.6" + wire width 3 $0\sr5__i[2:0] + attribute \src "libresoc.v:138130.3-138146.6" + wire $0\sr5__oe$next[0:0]$6039 + attribute \src "libresoc.v:137731.3-137732.31" + wire $0\sr5__oe[0:0] + attribute \src "libresoc.v:138147.3-138167.6" + wire width 3 $0\sr5_reg$next[2:0]$6043 + attribute \src "libresoc.v:137729.3-137730.31" + wire width 3 $0\sr5_reg[2:0] + attribute \src "libresoc.v:138112.3-138120.6" + wire $0\sr5_update_core$next[0:0]$6033 + attribute \src "libresoc.v:137735.3-137736.47" + wire $0\sr5_update_core[0:0] + attribute \src "libresoc.v:138121.3-138129.6" + wire $0\sr5_update_core_prev$next[0:0]$6036 + attribute \src "libresoc.v:137733.3-137734.57" + wire $0\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:138463.3-138483.6" + wire $0\wb_dcache_en$next[0:0]$6095 + attribute \src "libresoc.v:137709.3-137710.41" + wire $0\wb_dcache_en[0:0] + attribute \src "libresoc.v:138463.3-138483.6" + wire $0\wb_icache_en$next[0:0]$6096 + attribute \src "libresoc.v:137707.3-137708.41" + wire $0\wb_icache_en[0:0] + attribute \src "libresoc.v:138463.3-138483.6" + wire $0\wb_sram_en$next[0:0]$6097 + attribute \src "libresoc.v:137711.3-137712.37" + wire $0\wb_sram_en[0:0] + attribute \src "libresoc.v:138168.3-138194.6" + wire $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:137816.3-137831.6" + wire $1\TAP_tdo[0:0] + attribute \src "libresoc.v:138329.3-138361.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$6073 + attribute \src "libresoc.v:136574.13-136574.32" + wire width 4 $1\dmi0__addr_i[3:0] + attribute \src "libresoc.v:138415.3-138441.6" + wire width 64 $1\dmi0__din$next[63:0]$6086 + attribute \src "libresoc.v:136579.14-136579.46" + wire width 64 $1\dmi0__din[63:0] + attribute \src "libresoc.v:138018.3-138034.6" + wire $1\dmi0_addrsr__oe$next[0:0]$6010 + attribute \src "libresoc.v:136593.7-136593.29" + wire $1\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:138035.3-138055.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6014 + attribute \src "libresoc.v:136601.13-136601.36" + wire width 8 $1\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:138000.3-138008.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$6004 + attribute \src "libresoc.v:136609.7-136609.37" + wire $1\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:138009.3-138017.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6007 + attribute \src "libresoc.v:136613.7-136613.42" + wire $1\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:138442.3-138462.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$6091 + attribute \src "libresoc.v:136617.14-136617.51" + wire width 64 $1\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:138074.3-138090.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$6025 + attribute \src "libresoc.v:136623.13-136623.35" + wire width 2 $1\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:138091.3-138111.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$6029 + attribute \src "libresoc.v:136631.14-136631.52" + wire width 64 $1\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:138056.3-138064.6" + wire $1\dmi0_datasr_update_core$next[0:0]$6019 + attribute \src "libresoc.v:136639.7-136639.37" + wire $1\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:138065.3-138073.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$6022 + attribute \src "libresoc.v:136643.7-136643.42" + wire $1\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:138362.3-138414.6" + wire width 3 $1\fsm_state$503$next[2:0]$6079 + attribute \src "libresoc.v:138228.3-138280.6" + wire width 3 $1\fsm_state$next[2:0]$6056 + attribute \src "libresoc.v:136659.13-136659.29" + wire width 3 $1\fsm_state[2:0] + attribute \src "libresoc.v:138512.3-138532.6" + wire width 154 $1\io_bd$next[153:0]$6111 + attribute \src "libresoc.v:136859.15-136859.67" + wire width 154 $1\io_bd[153:0] + attribute \src "libresoc.v:138494.3-138511.6" + wire width 154 $1\io_sr$next[153:0]$6107 + attribute \src "libresoc.v:136871.15-136871.67" + wire width 154 $1\io_sr[153:0] + attribute \src "libresoc.v:138195.3-138227.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$6050 + attribute \src "libresoc.v:136880.14-136880.41" + wire width 29 $1\jtag_wb__adr[28:0] + attribute \src "libresoc.v:138281.3-138307.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$6063 + attribute \src "libresoc.v:136889.14-136889.51" + wire width 64 $1\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:137906.3-137922.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5980 + attribute \src "libresoc.v:136903.7-136903.32" + wire $1\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:137923.3-137943.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5984 + attribute \src "libresoc.v:136911.14-136911.47" + wire width 29 $1\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:137888.3-137896.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5974 + attribute \src "libresoc.v:136919.7-136919.40" + wire $1\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:137897.3-137905.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5977 + attribute \src "libresoc.v:136923.7-136923.45" + wire $1\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:138308.3-138328.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6068 + attribute \src "libresoc.v:136927.14-136927.54" + wire width 64 $1\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:137962.3-137978.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5995 + attribute \src "libresoc.v:136933.13-136933.38" + wire width 2 $1\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:137979.3-137999.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5999 + attribute \src "libresoc.v:136941.14-136941.55" + wire width 64 $1\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:137944.3-137952.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$5989 + attribute \src "libresoc.v:136949.7-136949.40" + wire $1\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:137953.3-137961.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5992 + attribute \src "libresoc.v:136953.7-136953.45" + wire $1\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:137850.3-137866.6" + wire $1\sr0__oe$next[0:0]$5965 + attribute \src "libresoc.v:137383.7-137383.21" + wire $1\sr0__oe[0:0] + attribute \src "libresoc.v:137867.3-137887.6" + wire width 3 $1\sr0_reg$next[2:0]$5969 + attribute \src "libresoc.v:137391.13-137391.27" + wire width 3 $1\sr0_reg[2:0] + attribute \src "libresoc.v:137832.3-137840.6" + wire $1\sr0_update_core$next[0:0]$5959 + attribute \src "libresoc.v:137399.7-137399.29" + wire $1\sr0_update_core[0:0] + attribute \src "libresoc.v:137841.3-137849.6" + wire $1\sr0_update_core_prev$next[0:0]$5962 + attribute \src "libresoc.v:137403.7-137403.34" + wire $1\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:138484.3-138493.6" + wire width 3 $1\sr5__i[2:0] + attribute \src "libresoc.v:138130.3-138146.6" + wire $1\sr5__oe$next[0:0]$6040 + attribute \src "libresoc.v:137413.7-137413.21" + wire $1\sr5__oe[0:0] + attribute \src "libresoc.v:138147.3-138167.6" + wire width 3 $1\sr5_reg$next[2:0]$6044 + attribute \src "libresoc.v:137421.13-137421.27" + wire width 3 $1\sr5_reg[2:0] + attribute \src "libresoc.v:138112.3-138120.6" + wire $1\sr5_update_core$next[0:0]$6034 + attribute \src "libresoc.v:137429.7-137429.29" + wire $1\sr5_update_core[0:0] + attribute \src "libresoc.v:138121.3-138129.6" + wire $1\sr5_update_core_prev$next[0:0]$6037 + attribute \src "libresoc.v:137433.7-137433.34" + wire $1\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:138463.3-138483.6" + wire $1\wb_dcache_en$next[0:0]$6098 + attribute \src "libresoc.v:137438.7-137438.26" + wire $1\wb_dcache_en[0:0] + attribute \src "libresoc.v:138463.3-138483.6" + wire $1\wb_icache_en$next[0:0]$6099 + attribute \src "libresoc.v:137443.7-137443.26" + wire $1\wb_icache_en[0:0] + attribute \src "libresoc.v:138463.3-138483.6" + wire $1\wb_sram_en$next[0:0]$6100 + attribute \src "libresoc.v:137448.7-137448.24" + wire $1\wb_sram_en[0:0] + attribute \src "libresoc.v:138329.3-138361.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$6074 + attribute \src "libresoc.v:138415.3-138441.6" + wire width 64 $2\dmi0__din$next[63:0]$6087 + attribute \src "libresoc.v:138018.3-138034.6" + wire $2\dmi0_addrsr__oe$next[0:0]$6011 + attribute \src "libresoc.v:138035.3-138055.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6015 + attribute \src "libresoc.v:138442.3-138462.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$6092 + attribute \src "libresoc.v:138074.3-138090.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$6026 + attribute \src "libresoc.v:138091.3-138111.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$6030 + attribute \src "libresoc.v:138362.3-138414.6" + wire width 3 $2\fsm_state$503$next[2:0]$6080 + attribute \src "libresoc.v:138228.3-138280.6" + wire width 3 $2\fsm_state$next[2:0]$6057 + attribute \src "libresoc.v:138512.3-138532.6" + wire width 154 $2\io_bd$next[153:0]$6112 + attribute \src "libresoc.v:138494.3-138511.6" + wire width 154 $2\io_sr$next[153:0]$6108 + attribute \src "libresoc.v:138195.3-138227.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$6051 + attribute \src "libresoc.v:138281.3-138307.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$6064 + attribute \src "libresoc.v:137906.3-137922.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$5981 + attribute \src "libresoc.v:137923.3-137943.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5985 + attribute \src "libresoc.v:138308.3-138328.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6069 + attribute \src "libresoc.v:137962.3-137978.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5996 + attribute \src "libresoc.v:137979.3-137999.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6000 + attribute \src "libresoc.v:137850.3-137866.6" + wire $2\sr0__oe$next[0:0]$5966 + attribute \src "libresoc.v:137867.3-137887.6" + wire width 3 $2\sr0_reg$next[2:0]$5970 + attribute \src "libresoc.v:138130.3-138146.6" + wire $2\sr5__oe$next[0:0]$6041 + attribute \src "libresoc.v:138147.3-138167.6" + wire width 3 $2\sr5_reg$next[2:0]$6045 + attribute \src "libresoc.v:138463.3-138483.6" + wire $2\wb_dcache_en$next[0:0]$6101 + attribute \src "libresoc.v:138463.3-138483.6" + wire $2\wb_icache_en$next[0:0]$6102 + attribute \src "libresoc.v:138463.3-138483.6" + wire $2\wb_sram_en$next[0:0]$6103 + attribute \src "libresoc.v:138329.3-138361.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$6075 + attribute \src "libresoc.v:138415.3-138441.6" + wire width 64 $3\dmi0__din$next[63:0]$6088 + attribute \src "libresoc.v:138035.3-138055.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6016 + attribute \src "libresoc.v:138442.3-138462.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$6093 + attribute \src "libresoc.v:138091.3-138111.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$6031 + attribute \src "libresoc.v:138362.3-138414.6" + wire width 3 $3\fsm_state$503$next[2:0]$6081 + attribute \src "libresoc.v:138228.3-138280.6" + wire width 3 $3\fsm_state$next[2:0]$6058 + attribute \src "libresoc.v:138195.3-138227.6" + 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$4\jtag_wb__adr$next[28:0]$6053 + attribute \src "libresoc.v:138362.3-138414.6" + wire width 3 $5\fsm_state$503$next[2:0]$6083 + attribute \src "libresoc.v:138228.3-138280.6" + wire width 3 $5\fsm_state$next[2:0]$6060 + attribute \src "libresoc.v:137671.19-137671.112" + wire width 30 $add$libresoc.v:137671$5881_Y + attribute \src "libresoc.v:137673.19-137673.112" + wire width 30 $add$libresoc.v:137673$5883_Y + attribute \src "libresoc.v:137679.19-137679.112" + wire width 5 $add$libresoc.v:137679$5890_Y + attribute \src "libresoc.v:137680.19-137680.112" + wire width 5 $add$libresoc.v:137680$5891_Y + attribute \src "libresoc.v:137495.18-137495.112" + wire $and$libresoc.v:137495$5705_Y + attribute \src "libresoc.v:137562.18-137562.108" + wire $and$libresoc.v:137562$5772_Y + attribute \src "libresoc.v:137573.18-137573.110" + wire $and$libresoc.v:137573$5783_Y + attribute \src "libresoc.v:137601.19-137601.110" + wire $and$libresoc.v:137601$5811_Y + attribute \src "libresoc.v:137604.19-137604.114" + wire $and$libresoc.v:137604$5814_Y + attribute \src "libresoc.v:137607.19-137607.112" + wire $and$libresoc.v:137607$5817_Y + attribute \src "libresoc.v:137609.19-137609.113" + wire $and$libresoc.v:137609$5819_Y + attribute \src "libresoc.v:137611.19-137611.121" + wire $and$libresoc.v:137611$5821_Y + attribute \src "libresoc.v:137614.19-137614.114" + wire $and$libresoc.v:137614$5824_Y + attribute \src "libresoc.v:137616.19-137616.112" + wire $and$libresoc.v:137616$5826_Y + attribute \src "libresoc.v:137620.19-137620.113" + wire $and$libresoc.v:137620$5830_Y + attribute \src "libresoc.v:137622.19-137622.132" + wire $and$libresoc.v:137622$5832_Y + attribute \src "libresoc.v:137626.19-137626.114" + wire $and$libresoc.v:137626$5836_Y + attribute \src "libresoc.v:137628.19-137628.112" + wire $and$libresoc.v:137628$5838_Y + attribute \src "libresoc.v:137631.19-137631.113" + wire $and$libresoc.v:137631$5841_Y + attribute \src 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$ternary$libresoc.v:137469$5679_Y + attribute \src "libresoc.v:137470.19-137470.133" + wire $ternary$libresoc.v:137470$5680_Y + attribute \src "libresoc.v:137471.19-137471.133" + wire $ternary$libresoc.v:137471$5681_Y + attribute \src "libresoc.v:137472.19-137472.132" + wire $ternary$libresoc.v:137472$5682_Y + attribute \src "libresoc.v:137474.19-137474.133" + wire $ternary$libresoc.v:137474$5684_Y + attribute \src "libresoc.v:137475.19-137475.133" + wire $ternary$libresoc.v:137475$5685_Y + attribute \src "libresoc.v:137476.19-137476.132" + wire $ternary$libresoc.v:137476$5686_Y + attribute \src "libresoc.v:137477.19-137477.133" + wire $ternary$libresoc.v:137477$5687_Y + attribute \src "libresoc.v:137478.19-137478.133" + wire $ternary$libresoc.v:137478$5688_Y + attribute \src "libresoc.v:137479.19-137479.132" + wire $ternary$libresoc.v:137479$5689_Y + attribute \src "libresoc.v:137480.19-137480.133" + wire $ternary$libresoc.v:137480$5690_Y + attribute \src "libresoc.v:137481.19-137481.134" + wire $ternary$libresoc.v:137481$5691_Y + attribute \src "libresoc.v:137482.19-137482.135" + wire $ternary$libresoc.v:137482$5692_Y + attribute \src "libresoc.v:137483.19-137483.135" + wire $ternary$libresoc.v:137483$5693_Y + attribute \src "libresoc.v:137485.19-137485.136" + wire $ternary$libresoc.v:137485$5695_Y + attribute \src "libresoc.v:137486.19-137486.134" + wire $ternary$libresoc.v:137486$5696_Y + attribute \src "libresoc.v:137487.19-137487.135" + wire $ternary$libresoc.v:137487$5697_Y + attribute \src "libresoc.v:137488.19-137488.135" + wire $ternary$libresoc.v:137488$5698_Y + attribute \src "libresoc.v:137489.19-137489.136" + wire $ternary$libresoc.v:137489$5699_Y + attribute \src "libresoc.v:137490.19-137490.134" + wire $ternary$libresoc.v:137490$5700_Y + attribute \src "libresoc.v:137491.19-137491.133" + wire $ternary$libresoc.v:137491$5701_Y + attribute \src "libresoc.v:137492.19-137492.134" + wire $ternary$libresoc.v:137492$5702_Y + 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$ternary$libresoc.v:137541$5751_Y + attribute \src "libresoc.v:137542.19-137542.135" + wire $ternary$libresoc.v:137542$5752_Y + attribute \src "libresoc.v:137543.19-137543.133" + wire $ternary$libresoc.v:137543$5753_Y + attribute \src "libresoc.v:137544.19-137544.133" + wire $ternary$libresoc.v:137544$5754_Y + attribute \src "libresoc.v:137545.19-137545.133" + wire $ternary$libresoc.v:137545$5755_Y + attribute \src "libresoc.v:137546.19-137546.133" + wire $ternary$libresoc.v:137546$5756_Y + attribute \src "libresoc.v:137547.19-137547.133" + wire $ternary$libresoc.v:137547$5757_Y + attribute \src "libresoc.v:137548.19-137548.133" + wire $ternary$libresoc.v:137548$5758_Y + attribute \src "libresoc.v:137549.19-137549.133" + wire $ternary$libresoc.v:137549$5759_Y + attribute \src "libresoc.v:137550.19-137550.133" + wire $ternary$libresoc.v:137550$5760_Y + attribute \src "libresoc.v:137552.19-137552.133" + wire $ternary$libresoc.v:137552$5762_Y + attribute \src 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attribute \src "libresoc.v:137565.19-137565.134" + wire $ternary$libresoc.v:137565$5775_Y + attribute \src "libresoc.v:137566.19-137566.135" + wire $ternary$libresoc.v:137566$5776_Y + attribute \src "libresoc.v:137567.19-137567.134" + wire $ternary$libresoc.v:137567$5777_Y + attribute \src "libresoc.v:137568.19-137568.135" + wire $ternary$libresoc.v:137568$5778_Y + attribute \src "libresoc.v:137569.19-137569.135" + wire $ternary$libresoc.v:137569$5779_Y + attribute \src "libresoc.v:137570.19-137570.134" + wire $ternary$libresoc.v:137570$5780_Y + attribute \src "libresoc.v:137571.19-137571.135" + wire $ternary$libresoc.v:137571$5781_Y + attribute \src "libresoc.v:137572.19-137572.135" + wire $ternary$libresoc.v:137572$5782_Y + attribute \src "libresoc.v:137574.19-137574.134" + wire $ternary$libresoc.v:137574$5784_Y + attribute \src "libresoc.v:137575.19-137575.135" + wire $ternary$libresoc.v:137575$5785_Y + attribute \src "libresoc.v:137576.19-137576.136" + wire $ternary$libresoc.v:137576$5786_Y + attribute \src "libresoc.v:137577.19-137577.135" + wire $ternary$libresoc.v:137577$5787_Y + attribute \src "libresoc.v:137578.19-137578.136" + wire $ternary$libresoc.v:137578$5788_Y + attribute \src "libresoc.v:137579.19-137579.136" + wire $ternary$libresoc.v:137579$5789_Y + attribute \src "libresoc.v:137580.19-137580.135" + wire $ternary$libresoc.v:137580$5790_Y + attribute \src "libresoc.v:137581.19-137581.136" + wire $ternary$libresoc.v:137581$5791_Y + attribute \src "libresoc.v:137582.19-137582.136" + wire $ternary$libresoc.v:137582$5792_Y + attribute \src "libresoc.v:137583.19-137583.135" + wire $ternary$libresoc.v:137583$5793_Y + attribute \src "libresoc.v:137585.19-137585.136" + wire $ternary$libresoc.v:137585$5795_Y + attribute \src "libresoc.v:137586.19-137586.136" + wire $ternary$libresoc.v:137586$5796_Y + attribute \src "libresoc.v:137587.19-137587.135" + wire $ternary$libresoc.v:137587$5797_Y + attribute \src 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attribute \src "libresoc.v:137686.18-137686.130" + wire $ternary$libresoc.v:137686$5897_Y + attribute \src "libresoc.v:137687.18-137687.131" + wire $ternary$libresoc.v:137687$5898_Y + attribute \src "libresoc.v:137688.18-137688.131" + wire $ternary$libresoc.v:137688$5899_Y + attribute \src "libresoc.v:137689.18-137689.130" + wire $ternary$libresoc.v:137689$5900_Y + attribute \src "libresoc.v:137690.18-137690.131" + wire $ternary$libresoc.v:137690$5901_Y + attribute \src "libresoc.v:137691.18-137691.132" + wire $ternary$libresoc.v:137691$5902_Y + attribute \src "libresoc.v:137692.18-137692.132" + wire $ternary$libresoc.v:137692$5903_Y + attribute \src "libresoc.v:137693.18-137693.133" + wire $ternary$libresoc.v:137693$5904_Y + attribute \src "libresoc.v:137694.18-137694.133" + wire $ternary$libresoc.v:137694$5905_Y + attribute \src "libresoc.v:137695.18-137695.132" + wire $ternary$libresoc.v:137695$5906_Y + attribute \src "libresoc.v:137697.18-137697.133" + wire $ternary$libresoc.v:137697$5908_Y + attribute \src "libresoc.v:137698.18-137698.133" + wire $ternary$libresoc.v:137698$5909_Y + attribute \src "libresoc.v:137699.18-137699.132" + wire $ternary$libresoc.v:137699$5910_Y + attribute \src "libresoc.v:137700.18-137700.133" + wire $ternary$libresoc.v:137700$5911_Y + attribute \src "libresoc.v:137701.18-137701.133" + wire $ternary$libresoc.v:137701$5912_Y + attribute \src "libresoc.v:137702.18-137702.132" + wire $ternary$libresoc.v:137702$5913_Y + attribute \src "libresoc.v:137703.18-137703.133" + wire $ternary$libresoc.v:137703$5914_Y + attribute \src "libresoc.v:137704.18-137704.133" + wire $ternary$libresoc.v:137704$5915_Y + attribute \src "libresoc.v:137705.18-137705.132" + wire $ternary$libresoc.v:137705$5916_Y + attribute \src "libresoc.v:137706.18-137706.133" + wire $ternary$libresoc.v:137706$5917_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$131 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$137 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$139 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$141 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$143 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$145 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wire \$165 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$167 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$169 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$171 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$173 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$175 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$177 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$179 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$181 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$183 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$185 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$187 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$189 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$191 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$193 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$195 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$197 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$199 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$201 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$203 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$205 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$207 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$209 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$211 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$213 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$215 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$217 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$219 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$221 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$223 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$225 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$227 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$229 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$231 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$233 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$235 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$237 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$239 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$241 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$243 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$245 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$247 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$249 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$251 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$253 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$255 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$257 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$259 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$261 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$263 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$265 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$267 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$269 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$271 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$273 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$275 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$277 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$279 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$281 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$283 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$285 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$287 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$289 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$291 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$293 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$295 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$297 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$299 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$301 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$303 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$305 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$307 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$309 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$311 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$313 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$315 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$317 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$319 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$321 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$323 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$325 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$327 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$329 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$331 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$333 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$335 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$337 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$339 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$341 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$343 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$345 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$347 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$349 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$351 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$353 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$355 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$357 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$359 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$361 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$363 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + wire \$365 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$367 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$369 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$371 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$373 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$375 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$377 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$379 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$381 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$383 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$385 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$387 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$389 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$391 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$393 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$395 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$397 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$399 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$401 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$403 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$405 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$407 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$409 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$411 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$413 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$415 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$417 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$419 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$421 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$423 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$425 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$427 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$429 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$431 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$433 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$435 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$437 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$439 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$441 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$443 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$445 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$447 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$449 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$451 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$453 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$455 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$457 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$459 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$461 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$463 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$465 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$471 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$475 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$477 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$481 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$483 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$484 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$487 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$489 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" + wire \$493 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + wire width 30 \$495 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + wire width 30 \$496 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + wire width 30 \$498 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + wire width 30 \$499 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 8 \$501 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$504 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$506 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$508 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" + wire \$510 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + wire width 5 \$512 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + wire width 5 \$513 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + wire width 5 \$515 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + wire width 5 \$516 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" - wire \a_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 input 2 \a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" - wire \a_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire input 3 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" - wire input 15 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire output 5 \f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire \f_fetch_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire \f_fetch_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 output 6 \f_instr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" - wire \f_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire input 4 \f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 9 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 14 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 \ibus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 8 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire \ibus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 13 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 10 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 12 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 \ibus__sel$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 11 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire \ibus__stb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" - wire width 64 \ibus_rdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" - wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:137931.7-137931.15" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 329 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 165 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 320 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 330 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" + wire \TAP_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \_fsm_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \_fsm_isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \_fsm_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire \_fsm_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire \_fsm_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire \_idblock_id_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire \_idblock_select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \_irblock_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire \_irblock_tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" + wire input 331 \clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire input 6 \dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 output 2 \dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \dmi0__addr_i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 output 5 \dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \dmi0__din$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 input 7 \dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 3 \dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 4 \dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \dmi0_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \dmi0_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 166 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 11 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 12 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 13 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 21 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 176 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 177 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 178 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 23 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 15 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 16 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 14 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 170 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 171 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 172 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 18 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 19 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 17 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \gpio_s7__pad__oe + attribute \src "libresoc.v:136016.7-136016.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" + wire \io_bd2core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + wire \io_bd2io + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" + wire \io_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + wire \io_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" + wire \io_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 327 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 321 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 \jtag_wb__adr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 323 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 328 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 326 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 \jtag_wb__dat_w$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 322 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 324 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 325 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \jtag_wb_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \jtag_wb_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire input 7 \wb_icache_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:138048$5467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$11 - connect \Y $and$libresoc.v:138048$5467_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:138054$5473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$21 - connect \Y $and$libresoc.v:138054$5473_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:138059$5478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$31 - connect \Y $and$libresoc.v:138059$5478_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:138062$5481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$1 - connect \Y $and$libresoc.v:138062$5481_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:138065$5484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$41 - connect \Y $and$libresoc.v:138065$5484_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:138066$5485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $and$libresoc.v:138066$5485_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:138068$5487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $and$libresoc.v:138068$5487_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:138047$5466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:138047$5466_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:138050$5469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:138050$5469_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:138051$5470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:138051$5470_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:138053$5472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:138053$5472_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:138056$5475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:138056$5475_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:138058$5477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:138058$5477_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:138061$5480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:138061$5480_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:138064$5483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:138064$5483_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:138067$5486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $not$libresoc.v:138067$5486_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:138069$5488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $not$libresoc.v:138069$5488_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:138071$5490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:138071$5490_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:138046$5465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \$7 - connect \Y $or$libresoc.v:138046$5465_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:138049$5468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:138049$5468_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:138052$5471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \$17 - connect \Y $or$libresoc.v:138052$5471_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 163 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 318 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr0_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr0_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr0_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr0_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire width 3 \sr5__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \sr5__ie + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire width 3 \sr5__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \sr5__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \sr5__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr5_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr5_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr5_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr5_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr5_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr5_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" + wire output 9 \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" + wire \wb_dcache_en$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire output 10 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \wb_icache_en$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" + wire output 8 \wb_sram_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" + wire \wb_sram_en$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + cell $add $add$libresoc.v:137671$5881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:137671$5881_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:138055$5474 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + cell $add $add$libresoc.v:137673$5883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:137673$5883_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + cell $add $add$libresoc.v:137679$5890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:137679$5890_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + cell $add $add$libresoc.v:137680$5891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:137680$5891_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" + cell $and $and$libresoc.v:137495$5705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:138055$5474_Y + connect \A \$15 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:137495$5705_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:138057$5476 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:137562$5772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$25 + connect \A \_fsm_isdr connect \B \$27 - connect \Y $or$libresoc.v:138057$5476_Y + connect \Y $and$libresoc.v:137562$5772_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:138060$5479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" + cell $and $and$libresoc.v:137573$5783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:138060$5479_Y + connect \A \$29 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:137573$5783_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:138063$5482 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:137601$5811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$35 - connect \B \$37 - connect \Y $or$libresoc.v:138063$5482_Y + connect \A \_fsm_isdr + connect \B \$367 + connect \Y $and$libresoc.v:137601$5811_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:138070$5489 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:137604$5814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:138070$5489_Y - end - attribute \src "libresoc.v:137931.7-137931.20" - process $proc$libresoc.v:137931$5540 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + connect \A \$373 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:137604$5814_Y end - attribute \src "libresoc.v:137995.14-137995.44" - process $proc$libresoc.v:137995$5541 - assign { } { } - assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \f_badaddr_o $1\f_badaddr_o[44:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:137607$5817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$377 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:137607$5817_Y end - attribute \src "libresoc.v:138002.7-138002.27" - process $proc$libresoc.v:138002$5542 - assign { } { } - assign $1\f_fetch_err_o[0:0] 1'0 - sync always - sync init - update \f_fetch_err_o $1\f_fetch_err_o[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:137609$5819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$381 + connect \B \_fsm_update + connect \Y $and$libresoc.v:137609$5819_Y end - attribute \src "libresoc.v:138016.14-138016.42" - process $proc$libresoc.v:138016$5543 - assign { } { } - assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \ibus__adr $1\ibus__adr[44:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:137611$5821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core_prev + connect \B \$385 + connect \Y $and$libresoc.v:137611$5821_Y end - attribute \src "libresoc.v:138021.7-138021.23" - process $proc$libresoc.v:138021$5544 - assign { } { } - assign $1\ibus__cyc[0:0] 1'0 - sync always - sync init - update \ibus__cyc $1\ibus__cyc[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:137614$5824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$391 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:137614$5824_Y end - attribute \src "libresoc.v:138030.13-138030.30" - process $proc$libresoc.v:138030$5545 - assign { } { } - assign $1\ibus__sel[7:0] 8'00000000 - sync always - sync init - update \ibus__sel $1\ibus__sel[7:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:137616$5826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$395 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:137616$5826_Y end - attribute \src "libresoc.v:138035.7-138035.23" - process $proc$libresoc.v:138035$5546 - assign { } { } - assign $1\ibus__stb[0:0] 1'0 - sync always - sync init - update \ibus__stb $1\ibus__stb[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:137620$5830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$399 + connect \B \_fsm_update + connect \Y $and$libresoc.v:137620$5830_Y end - attribute \src "libresoc.v:138039.14-138039.47" - process $proc$libresoc.v:138039$5547 - assign { } { } - assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ibus_rdata $1\ibus_rdata[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:137622$5832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core_prev + connect \B \$403 + connect \Y $and$libresoc.v:137622$5832_Y end - attribute \src "libresoc.v:138072.3-138073.39" - process $proc$libresoc.v:138072$5491 - assign { } { } - assign $0\f_badaddr_o[44:0] \f_badaddr_o$next - sync posedge \clk - update \f_badaddr_o $0\f_badaddr_o[44:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:137626$5836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$411 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:137626$5836_Y end - attribute \src "libresoc.v:138074.3-138075.43" - process $proc$libresoc.v:138074$5492 - assign { } { } - assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next - sync posedge \clk - update \f_fetch_err_o $0\f_fetch_err_o[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:137628$5838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$415 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:137628$5838_Y end - attribute \src "libresoc.v:138076.3-138077.35" - process $proc$libresoc.v:138076$5493 - assign { } { } - assign $0\ibus__adr[44:0] \ibus__adr$next - sync posedge \clk - update \ibus__adr $0\ibus__adr[44:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:137631$5841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$419 + connect \B \_fsm_update + connect \Y $and$libresoc.v:137631$5841_Y end - attribute \src "libresoc.v:138078.3-138079.37" - process $proc$libresoc.v:138078$5494 - assign { } { } - assign $0\ibus_rdata[63:0] \ibus_rdata$next - sync posedge \clk - update \ibus_rdata $0\ibus_rdata[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:137633$5843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core_prev + connect \B \$423 + connect \Y $and$libresoc.v:137633$5843_Y end - attribute \src "libresoc.v:138080.3-138081.35" - process $proc$libresoc.v:138080$5495 - assign { } { } - assign $0\ibus__sel[7:0] \ibus__sel$next - sync posedge \clk - update \ibus__sel $0\ibus__sel[7:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:137636$5846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$429 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:137636$5846_Y end - attribute \src "libresoc.v:138082.3-138083.35" - process $proc$libresoc.v:138082$5496 - assign { } { } - assign $0\ibus__stb[0:0] \ibus__stb$next - sync posedge \clk - update \ibus__stb $0\ibus__stb[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:137638$5848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$433 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:137638$5848_Y end - attribute \src "libresoc.v:138084.3-138085.35" - process $proc$libresoc.v:138084$5497 - assign { } { } - assign $0\ibus__cyc[0:0] \ibus__cyc$next - sync posedge \clk - update \ibus__cyc $0\ibus__cyc[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:137640$5850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$41 + connect \Y $and$libresoc.v:137640$5850_Y end - attribute \src "libresoc.v:138086.3-138113.6" - process $proc$libresoc.v:138086$5498 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__cyc$next[0:0]$5499 $4\ibus__cyc$next[0:0]$5503 - attribute \src "libresoc.v:138087.5-138087.29" - switch \initial - attribute \src "libresoc.v:138087.9-138087.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ibus__cyc$next[0:0]$5500 $2\ibus__cyc$next[0:0]$5501 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$3 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus__cyc$next[0:0]$5501 $3\ibus__cyc$next[0:0]$5502 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__cyc$next[0:0]$5502 1'0 - case - assign $3\ibus__cyc$next[0:0]$5502 \ibus__cyc - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__cyc$next[0:0]$5501 1'1 - case - assign $2\ibus__cyc$next[0:0]$5501 \ibus__cyc - end - case - assign $1\ibus__cyc$next[0:0]$5500 \ibus__cyc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ibus__cyc$next[0:0]$5503 1'0 - case - assign $4\ibus__cyc$next[0:0]$5503 $1\ibus__cyc$next[0:0]$5500 - end - sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5499 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:137641$5851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$437 + connect \B \_fsm_update + connect \Y $and$libresoc.v:137641$5851_Y end - attribute \src "libresoc.v:138114.3-138141.6" - process $proc$libresoc.v:138114$5504 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__stb$next[0:0]$5505 $4\ibus__stb$next[0:0]$5509 - attribute \src "libresoc.v:138115.5-138115.29" - switch \initial - attribute \src "libresoc.v:138115.9-138115.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ibus__stb$next[0:0]$5506 $2\ibus__stb$next[0:0]$5507 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$13 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus__stb$next[0:0]$5507 $3\ibus__stb$next[0:0]$5508 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__stb$next[0:0]$5508 1'0 - case - assign $3\ibus__stb$next[0:0]$5508 \ibus__stb - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__stb$next[0:0]$5507 1'1 - case - assign $2\ibus__stb$next[0:0]$5507 \ibus__stb - end - case - assign $1\ibus__stb$next[0:0]$5506 \ibus__stb - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ibus__stb$next[0:0]$5509 1'0 - case - assign $4\ibus__stb$next[0:0]$5509 $1\ibus__stb$next[0:0]$5506 - end - sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$5505 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:137643$5853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core_prev + connect \B \$441 + connect \Y $and$libresoc.v:137643$5853_Y end - attribute \src "libresoc.v:138142.3-138169.6" - process $proc$libresoc.v:138142$5510 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__sel$next[7:0]$5511 $4\ibus__sel$next[7:0]$5515 - attribute \src "libresoc.v:138143.5-138143.29" - switch \initial - attribute \src "libresoc.v:138143.9-138143.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ibus__sel$next[7:0]$5512 $2\ibus__sel$next[7:0]$5513 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$23 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus__sel$next[7:0]$5513 $3\ibus__sel$next[7:0]$5514 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__sel$next[7:0]$5514 8'00000000 - case - assign $3\ibus__sel$next[7:0]$5514 \ibus__sel - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__sel$next[7:0]$5513 8'11111111 - case - assign $2\ibus__sel$next[7:0]$5513 \ibus__sel - end - case - assign $1\ibus__sel$next[7:0]$5512 \ibus__sel - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ibus__sel$next[7:0]$5515 8'00000000 - case - assign $4\ibus__sel$next[7:0]$5515 $1\ibus__sel$next[7:0]$5512 - end - sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$5511 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:137647$5857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$449 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:137647$5857_Y end - attribute \src "libresoc.v:138170.3-138194.6" - process $proc$libresoc.v:138170$5516 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus_rdata$next[63:0]$5517 $4\ibus_rdata$next[63:0]$5521 - attribute \src "libresoc.v:138171.5-138171.29" - switch \initial - attribute \src "libresoc.v:138171.9-138171.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ibus_rdata$next[63:0]$5518 $2\ibus_rdata$next[63:0]$5519 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$33 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus_rdata$next[63:0]$5519 $3\ibus_rdata$next[63:0]$5520 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$39 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus_rdata$next[63:0]$5520 \ibus__dat_r - case - assign $3\ibus_rdata$next[63:0]$5520 \ibus_rdata - end - case - assign $2\ibus_rdata$next[63:0]$5519 \ibus_rdata - end - case - assign $1\ibus_rdata$next[63:0]$5518 \ibus_rdata - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ibus_rdata$next[63:0]$5521 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $4\ibus_rdata$next[63:0]$5521 $1\ibus_rdata$next[63:0]$5518 - end - sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5517 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:137649$5859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$453 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:137649$5859_Y end - attribute \src "libresoc.v:138195.3-138217.6" - process $proc$libresoc.v:138195$5522 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__adr$next[44:0]$5523 $3\ibus__adr$next[44:0]$5526 - attribute \src "libresoc.v:138196.5-138196.29" - switch \initial - attribute \src "libresoc.v:138196.9-138196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ibus__adr$next[44:0]$5524 $2\ibus__adr$next[44:0]$5525 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$43 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $2\ibus__adr$next[44:0]$5525 \ibus__adr - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__adr$next[44:0]$5525 \a_pc_i [47:3] - case - assign $2\ibus__adr$next[44:0]$5525 \ibus__adr - end - case - assign $1\ibus__adr$next[44:0]$5524 \ibus__adr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__adr$next[44:0]$5526 45'000000000000000000000000000000000000000000000 - case - assign $3\ibus__adr$next[44:0]$5526 $1\ibus__adr$next[44:0]$5524 - end - sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$5523 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + cell $and $and$libresoc.v:137651$5861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \_fsm_update + connect \Y $and$libresoc.v:137651$5861_Y end - attribute \src "libresoc.v:138218.3-138240.6" - process $proc$libresoc.v:138218$5527 - assign { } { } - assign { } { } - assign { } { } - assign $0\f_fetch_err_o$next[0:0]$5528 $3\f_fetch_err_o$next[0:0]$5531 - attribute \src "libresoc.v:138219.5-138219.29" - switch \initial - attribute \src "libresoc.v:138219.9-138219.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5529 $2\f_fetch_err_o$next[0:0]$5530 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch { \$47 \$45 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5530 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5530 1'0 - case - assign $2\f_fetch_err_o$next[0:0]$5530 \f_fetch_err_o - end - case - assign $1\f_fetch_err_o$next[0:0]$5529 \f_fetch_err_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\f_fetch_err_o$next[0:0]$5531 1'0 - case - assign $3\f_fetch_err_o$next[0:0]$5531 $1\f_fetch_err_o$next[0:0]$5529 - end - sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5528 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:137652$5862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$457 + connect \B \_fsm_update + connect \Y $and$libresoc.v:137652$5862_Y end - attribute \src "libresoc.v:138241.3-138260.6" - process $proc$libresoc.v:138241$5532 - assign { } { } - assign { } { } - assign { } { } - assign $0\f_badaddr_o$next[44:0]$5533 $3\f_badaddr_o$next[44:0]$5536 - attribute \src "libresoc.v:138242.5-138242.29" - switch \initial - attribute \src "libresoc.v:138242.9-138242.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\f_badaddr_o$next[44:0]$5534 $2\f_badaddr_o$next[44:0]$5535 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch { \$51 \$49 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\f_badaddr_o$next[44:0]$5535 \ibus__adr - case - assign $2\f_badaddr_o$next[44:0]$5535 \f_badaddr_o - end - case - assign $1\f_badaddr_o$next[44:0]$5534 \f_badaddr_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\f_badaddr_o$next[44:0]$5536 45'000000000000000000000000000000000000000000000 - case - assign $3\f_badaddr_o$next[44:0]$5536 $1\f_badaddr_o$next[44:0]$5534 - end - sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5533 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:137654$5864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core_prev + connect \B \$461 + connect \Y $and$libresoc.v:137654$5864_Y end - attribute \src "libresoc.v:138261.3-138270.6" - process $proc$libresoc.v:138261$5537 - assign { } { } - assign { } { } - assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] - attribute \src "libresoc.v:138262.5-138262.29" - switch \initial - attribute \src "libresoc.v:138262.9-138262.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a_busy_o[0:0] \ibus__cyc - case - assign $1\a_busy_o[0:0] 1'0 - end - sync always - update \a_busy_o $0\a_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:137657$5867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$467 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:137657$5867_Y end - attribute \src "libresoc.v:138271.3-138288.6" - process $proc$libresoc.v:138271$5538 - assign { } { } - assign { } { } - assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:138272.5-138272.29" - switch \initial - attribute \src "libresoc.v:138272.9-138272.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\f_busy_o[0:0] $2\f_busy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" - switch \f_fetch_err_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\f_busy_o[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\f_busy_o[0:0] \ibus__cyc - end - case - assign $1\f_busy_o[0:0] 1'0 - end - sync always - update \f_busy_o $0\f_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:137659$5869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$471 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:137659$5869_Y end - attribute \src "libresoc.v:138289.3-138306.6" - process $proc$libresoc.v:138289$5539 - assign { } { } - assign { } { } - assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:138290.5-138290.29" - switch \initial - attribute \src "libresoc.v:138290.9-138290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\f_instr_o[63:0] $2\f_instr_o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" - switch \f_fetch_err_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\f_instr_o[63:0] \ibus_rdata - end - case - assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \f_instr_o $0\f_instr_o[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:137661$5871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$475 + connect \B \_fsm_update + connect \Y $and$libresoc.v:137661$5871_Y end - connect \$9 $or$libresoc.v:138046$5465_Y - connect \$11 $not$libresoc.v:138047$5466_Y - connect \$13 $and$libresoc.v:138048$5467_Y - connect \$15 $or$libresoc.v:138049$5468_Y - connect \$17 $not$libresoc.v:138050$5469_Y - connect \$1 $not$libresoc.v:138051$5470_Y - connect \$19 $or$libresoc.v:138052$5471_Y - connect \$21 $not$libresoc.v:138053$5472_Y - connect \$23 $and$libresoc.v:138054$5473_Y - connect \$25 $or$libresoc.v:138055$5474_Y - connect \$27 $not$libresoc.v:138056$5475_Y - connect \$29 $or$libresoc.v:138057$5476_Y - connect \$31 $not$libresoc.v:138058$5477_Y - connect \$33 $and$libresoc.v:138059$5478_Y - connect \$35 $or$libresoc.v:138060$5479_Y - connect \$37 $not$libresoc.v:138061$5480_Y - connect \$3 $and$libresoc.v:138062$5481_Y - connect \$39 $or$libresoc.v:138063$5482_Y - connect \$41 $not$libresoc.v:138064$5483_Y - connect \$43 $and$libresoc.v:138065$5484_Y - connect \$45 $and$libresoc.v:138066$5485_Y - connect \$47 $not$libresoc.v:138067$5486_Y - connect \$49 $and$libresoc.v:138068$5487_Y - connect \$51 $not$libresoc.v:138069$5488_Y - connect \$5 $or$libresoc.v:138070$5489_Y - connect \$7 $not$libresoc.v:138071$5490_Y - connect \a_stall_i 1'0 - connect \f_stall_i 1'0 -end -attribute \src "libresoc.v:138313.1-138413.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.in1_svdec" -attribute \generator "nMigen" -module \in1_svdec - attribute \src "libresoc.v:138314.7-138314.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:138400.3-138411.6" - wire width 7 $0\reg_out[6:0] - attribute \src "libresoc.v:138341.3-138399.6" - wire width 3 $0\spec[2:0] - attribute \src "libresoc.v:138400.3-138411.6" - wire width 7 $1\reg_out[6:0] - attribute \src "libresoc.v:138341.3-138399.6" - wire width 3 $1\spec[2:0] - attribute \src "libresoc.v:138341.3-138399.6" - wire width 2 $2\spec[2:1] - attribute \src "libresoc.v:138341.3-138399.6" - wire width 3 $3\spec[2:0] - attribute \enum_base_type "SVEtype" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "EXTRA2" - attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" - wire width 2 input 1 \etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" - wire width 9 input 6 \extra - attribute \enum_base_type "SVEXTRA" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "Idx0" - attribute \enum_value_010 "Idx1" - attribute \enum_value_011 "Idx2" - attribute \enum_value_100 "Idx3" - attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" - wire width 3 input 5 \idx - attribute \src "libresoc.v:138314.7-138314.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire output 3 \isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - wire width 5 input 2 \reg_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 7 output 4 \reg_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" - wire width 3 \spec - attribute \src "libresoc.v:138314.7-138314.20" - process $proc$libresoc.v:138314$5550 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:137664$5874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_update_core_prev + connect \B \$479 + connect \Y $and$libresoc.v:137664$5874_Y end - attribute \src "libresoc.v:138341.3-138399.6" - process $proc$libresoc.v:138341$5548 - assign { } { } - assign { } { } - assign $0\spec[2:0] $1\spec[2:0] - attribute \src "libresoc.v:138342.5-138342.29" - switch \initial - attribute \src "libresoc.v:138342.9-138342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch \etype - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign $1\spec[2:0] [0] 1'0 - assign $1\spec[2:0] [2:1] $2\spec[2:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" - switch \idx - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $2\spec[2:1] [1] \extra [8] - assign $2\spec[2:1] [0] \extra [7] - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $2\spec[2:1] [1] \extra [6] - assign $2\spec[2:1] [0] \extra [5] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $2\spec[2:1] [1] \extra [4] - assign $2\spec[2:1] [0] \extra [3] - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $2\spec[2:1] [1] \extra [2] - assign $2\spec[2:1] [0] \extra [1] - case - assign $2\spec[2:1] 2'00 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\spec[2:0] $3\spec[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" - switch \idx - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $3\spec[2:0] \extra [8:6] - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $3\spec[2:0] \extra [5:3] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $3\spec[2:0] \extra [2:0] - case - assign $3\spec[2:0] 3'000 - end - case - assign $1\spec[2:0] 3'000 - end - sync always - update \spec $0\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $and $and$libresoc.v:137696$5907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$5 + connect \Y $and$libresoc.v:137696$5907_Y end - attribute \src "libresoc.v:138400.3-138411.6" - process $proc$libresoc.v:138400$5549 - assign { } { } - assign $0\reg_out[6:0] $1\reg_out[6:0] - attribute \src "libresoc.v:138401.5-138401.29" - switch \initial - attribute \src "libresoc.v:138401.9-138401.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" - switch \isvec - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg_out[6:0] { \reg_in \spec [1:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\reg_out[6:0] { \spec [1:0] \reg_in } - end - sync always - update \reg_out $0\reg_out[6:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + cell $eq $eq$libresoc.v:137451$5661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:137451$5661_Y end - connect \isvec \spec [2] -end -attribute \src "libresoc.v:138417.1-138517.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.in2_svdec" -attribute \generator "nMigen" -module \in2_svdec - attribute \src "libresoc.v:138418.7-138418.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:138504.3-138515.6" - wire width 7 $0\reg_out[6:0] - attribute \src "libresoc.v:138445.3-138503.6" - wire width 3 $0\spec[2:0] - attribute \src "libresoc.v:138504.3-138515.6" - wire width 7 $1\reg_out[6:0] - attribute \src "libresoc.v:138445.3-138503.6" - wire width 3 $1\spec[2:0] - attribute \src "libresoc.v:138445.3-138503.6" - wire width 2 $2\spec[2:1] - attribute \src "libresoc.v:138445.3-138503.6" - wire width 3 $3\spec[2:0] - attribute \enum_base_type "SVEtype" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "EXTRA2" - attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" - wire width 2 input 1 \etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" - wire width 9 input 6 \extra - attribute \enum_base_type "SVEXTRA" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "Idx0" - attribute \enum_value_010 "Idx1" - attribute \enum_value_011 "Idx2" - attribute \enum_value_100 "Idx3" - attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" - wire width 3 input 5 \idx - attribute \src "libresoc.v:138418.7-138418.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire output 3 \isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - wire width 5 input 2 \reg_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 7 output 4 \reg_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" - wire width 3 \spec - attribute \src "libresoc.v:138418.7-138418.20" - process $proc$libresoc.v:138418$5553 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:137462$5672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:137462$5672_Y end - attribute \src "libresoc.v:138445.3-138503.6" - process $proc$libresoc.v:138445$5551 - assign { } { } - assign { } { } - assign $0\spec[2:0] $1\spec[2:0] - attribute \src "libresoc.v:138446.5-138446.29" - switch \initial - attribute \src "libresoc.v:138446.9-138446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch \etype - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign $1\spec[2:0] [0] 1'0 - assign $1\spec[2:0] [2:1] $2\spec[2:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" - switch \idx - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $2\spec[2:1] [1] \extra [8] - assign $2\spec[2:1] [0] \extra [7] - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $2\spec[2:1] [1] \extra [6] - assign $2\spec[2:1] [0] \extra [5] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $2\spec[2:1] [1] \extra [4] - assign $2\spec[2:1] [0] \extra [3] - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $2\spec[2:1] [1] \extra [2] - assign $2\spec[2:1] [0] \extra [1] - case - assign $2\spec[2:1] 2'00 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\spec[2:0] $3\spec[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" - switch \idx - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $3\spec[2:0] \extra [8:6] - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $3\spec[2:0] \extra [5:3] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $3\spec[2:0] \extra [2:0] - case - assign $3\spec[2:0] 3'000 - end - case - assign $1\spec[2:0] 3'000 - end - sync always - update \spec $0\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:137473$5683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:137473$5683_Y end - attribute \src "libresoc.v:138504.3-138515.6" - process $proc$libresoc.v:138504$5552 - assign { } { } - assign $0\reg_out[6:0] $1\reg_out[6:0] - attribute \src "libresoc.v:138505.5-138505.29" - switch \initial - attribute \src "libresoc.v:138505.9-138505.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" - switch \isvec - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg_out[6:0] { \reg_in \spec [1:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\reg_out[6:0] { \spec [1:0] \reg_in } - end - sync always - update \reg_out $0\reg_out[6:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $eq $eq$libresoc.v:137506$5716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'1 + connect \Y $eq$libresoc.v:137506$5716_Y end - connect \isvec \spec [2] -end -attribute \src "libresoc.v:138521.1-138621.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.in3_svdec" -attribute \generator "nMigen" -module \in3_svdec - attribute \src "libresoc.v:138522.7-138522.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:138608.3-138619.6" - wire width 7 $0\reg_out[6:0] - attribute \src "libresoc.v:138549.3-138607.6" - wire width 3 $0\spec[2:0] - attribute \src "libresoc.v:138608.3-138619.6" - wire width 7 $1\reg_out[6:0] - attribute \src "libresoc.v:138549.3-138607.6" - wire width 3 $1\spec[2:0] - attribute \src "libresoc.v:138549.3-138607.6" - wire width 2 $2\spec[2:1] - attribute \src "libresoc.v:138549.3-138607.6" - wire width 3 $3\spec[2:0] - attribute \enum_base_type "SVEtype" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "EXTRA2" - attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" - wire width 2 input 1 \etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" - wire width 9 input 6 \extra - attribute \enum_base_type "SVEXTRA" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "Idx0" - attribute \enum_value_010 "Idx1" - attribute \enum_value_011 "Idx2" - attribute \enum_value_100 "Idx3" - attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" - wire width 3 input 5 \idx - attribute \src "libresoc.v:138522.7-138522.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire output 3 \isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - wire width 5 input 2 \reg_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 7 output 4 \reg_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" - wire width 3 \spec - attribute \src "libresoc.v:138522.7-138522.20" - process $proc$libresoc.v:138522$5556 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:137507$5717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:137507$5717_Y end - attribute \src "libresoc.v:138549.3-138607.6" - process $proc$libresoc.v:138549$5554 - assign { } { } - assign { } { } - assign $0\spec[2:0] $1\spec[2:0] - attribute \src "libresoc.v:138550.5-138550.29" - switch \initial - attribute \src "libresoc.v:138550.9-138550.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch \etype - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign $1\spec[2:0] [0] 1'0 - assign $1\spec[2:0] [2:1] $2\spec[2:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" - switch \idx - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $2\spec[2:1] [1] \extra [8] - assign $2\spec[2:1] [0] \extra [7] - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $2\spec[2:1] [1] \extra [6] - assign $2\spec[2:1] [0] \extra [5] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $2\spec[2:1] [1] \extra [4] - assign $2\spec[2:1] [0] \extra [3] - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $2\spec[2:1] [1] \extra [2] - assign $2\spec[2:1] [0] \extra [1] - case - assign $2\spec[2:1] 2'00 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\spec[2:0] $3\spec[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" - switch \idx - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $3\spec[2:0] \extra [8:6] - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $3\spec[2:0] \extra [5:3] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $3\spec[2:0] \extra [2:0] - case - assign $3\spec[2:0] 3'000 - end - case - assign $1\spec[2:0] 3'000 - end - sync always - update \spec $0\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:137518$5728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:137518$5728_Y end - attribute \src "libresoc.v:138608.3-138619.6" - process $proc$libresoc.v:138608$5555 - assign { } { } - assign $0\reg_out[6:0] $1\reg_out[6:0] - attribute \src "libresoc.v:138609.5-138609.29" - switch \initial - attribute \src "libresoc.v:138609.9-138609.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" - switch \isvec - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reg_out[6:0] { \reg_in \spec [1:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\reg_out[6:0] { \spec [1:0] \reg_in } - end - sync always - update \reg_out $0\reg_out[6:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:137540$5750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:137540$5750_Y end - connect \isvec \spec [2] -end -attribute \src "libresoc.v:138625.1-138948.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" -attribute \generator "nMigen" -module \input - attribute \src "libresoc.v:138911.3-138922.6" - wire width 64 $0\a[63:0] - attribute \src "libresoc.v:138626.7-138626.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:138923.3-138941.6" - wire width 2 $0\xer_ca$23[1:0]$5560 - attribute \src "libresoc.v:138911.3-138922.6" - wire width 64 $1\a[63:0] - attribute \src "libresoc.v:138923.3-138941.6" - wire width 2 $1\xer_ca$23[1:0]$5561 - attribute \src "libresoc.v:138910.18-138910.100" - wire width 64 $not$libresoc.v:138910$5557_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - wire width 64 \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 40 \alu_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 25 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \alu_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 36 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \alu_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \alu_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "libresoc.v:138626.7-138626.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 46 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 43 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 output 45 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 44 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:138910$5557 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:137584$5794 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $not$libresoc.v:138910$5557_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:137584$5794_Y end - attribute \src "libresoc.v:138626.7-138626.20" - process $proc$libresoc.v:138626$5562 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:137595$5805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:137595$5805_Y end - attribute \src "libresoc.v:138911.3-138922.6" - process $proc$libresoc.v:138911$5558 - assign { } { } - assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:138912.5-138912.29" - switch \initial - attribute \src "libresoc.v:138912.9-138912.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" - switch \alu_op__invert_in - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[63:0] \$24 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\a[63:0] \ra - end - sync always - update \a $0\a[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:137596$5806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:137596$5806_Y end - attribute \src "libresoc.v:138923.3-138941.6" - process $proc$libresoc.v:138923$5559 - assign { } { } - assign { } { } - assign $0\xer_ca$23[1:0]$5560 $1\xer_ca$23[1:0]$5561 - attribute \src "libresoc.v:138924.5-138924.29" - switch \initial - attribute \src "libresoc.v:138924.9-138924.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" - switch \alu_op__input_carry - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\xer_ca$23[1:0]$5561 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\xer_ca$23[1:0]$5561 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\xer_ca$23[1:0]$5561 \xer_ca - case - assign $1\xer_ca$23[1:0]$5561 2'00 - end - sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5560 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:137597$5807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:137597$5807_Y end - connect \$24 $not$libresoc.v:138910$5557_Y - connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$22 \xer_so - connect \rb$21 \rb - connect \b \rb - connect \ra$20 \a -end -attribute \src "libresoc.v:138952.1-139276.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" -attribute \generator "nMigen" -module \input$113 - attribute \src "libresoc.v:139238.3-139249.6" - wire width 64 $0\a[63:0] - attribute \src "libresoc.v:138953.7-138953.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:139250.3-139268.6" - wire width 2 $0\xer_ca$23[1:0]$5566 - attribute \src "libresoc.v:139238.3-139249.6" - wire width 64 $1\a[63:0] - attribute \src "libresoc.v:139250.3-139268.6" - wire width 2 $1\xer_ca$23[1:0]$5567 - attribute \src "libresoc.v:139237.18-139237.100" - wire width 64 $not$libresoc.v:139237$5563_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - wire width 64 \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "libresoc.v:138953.7-138953.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 46 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \ra$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \rb$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 43 \rc$21 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 25 \sr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \sr_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 34 \sr_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__input_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 17 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \sr_op__insn$18 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \sr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \sr_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \sr_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \sr_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \sr_op__output_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__output_cr$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \sr_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \sr_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \sr_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 output 45 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 44 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:139237$5563 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:137599$5809 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $not$libresoc.v:139237$5563_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:137599$5809_Y end - attribute \src "libresoc.v:138953.7-138953.20" - process $proc$libresoc.v:138953$5568 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:137602$5812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'100 + connect \Y $eq$libresoc.v:137602$5812_Y end - attribute \src "libresoc.v:139238.3-139249.6" - process $proc$libresoc.v:139238$5564 - assign { } { } - assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:139239.5-139239.29" - switch \initial - attribute \src "libresoc.v:139239.9-139239.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" - switch \sr_op__invert_in - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[63:0] \$24 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\a[63:0] \ra - end - sync always - update \a $0\a[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:137612$5822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'101 + connect \Y $eq$libresoc.v:137612$5822_Y end - attribute \src "libresoc.v:139250.3-139268.6" - process $proc$libresoc.v:139250$5565 - assign { } { } - assign { } { } - assign $0\xer_ca$23[1:0]$5566 $1\xer_ca$23[1:0]$5567 - attribute \src "libresoc.v:139251.5-139251.29" - switch \initial - attribute \src "libresoc.v:139251.9-139251.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" - switch \sr_op__input_carry - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\xer_ca$23[1:0]$5567 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\xer_ca$23[1:0]$5567 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\xer_ca$23[1:0]$5567 \xer_ca - case - assign $1\xer_ca$23[1:0]$5567 2'00 - end - sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5566 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $eq $eq$libresoc.v:137617$5827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1111 + connect \Y $eq$libresoc.v:137617$5827_Y end - connect \$24 $not$libresoc.v:139237$5563_Y - connect \rc$21 \rc - connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$22 \xer_so - connect \rb$20 \b - connect \b \rb - connect \ra$19 \a -end -attribute \src "libresoc.v:139280.1-139579.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" -attribute \generator "nMigen" -module \input$50 - attribute \src "libresoc.v:139561.3-139572.6" - wire width 64 $0\b[63:0] - attribute \src "libresoc.v:139281.7-139281.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:139561.3-139572.6" - wire width 64 $1\b[63:0] - attribute \src "libresoc.v:139560.18-139560.100" - wire width 64 $not$libresoc.v:139560$5569_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - wire width 64 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "libresoc.v:139281.7-139281.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 24 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 43 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $not$libresoc.v:139560$5569 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:137618$5828 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rb - connect \Y $not$libresoc.v:139560$5569_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:137618$5828_Y end - attribute \src "libresoc.v:139281.7-139281.20" - process $proc$libresoc.v:139281$5571 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:137623$5833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'110 + connect \Y $eq$libresoc.v:137623$5833_Y end - attribute \src "libresoc.v:139561.3-139572.6" - process $proc$libresoc.v:139561$5570 - assign { } { } - assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:139562.5-139562.29" - switch \initial - attribute \src "libresoc.v:139562.9-139562.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" - switch \logical_op__invert_in - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\b[63:0] \$23 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\b[63:0] \rb - end - sync always - update \b $0\b[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:137624$5834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 3'111 + connect \Y $eq$libresoc.v:137624$5834_Y end - connect \$23 $not$libresoc.v:139560$5569_Y - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$22 \xer_so - connect \rb$21 \b - connect \ra$20 \a - connect \a \ra -end -attribute \src "libresoc.v:139583.1-139882.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" -attribute \generator "nMigen" -module \input$78 - attribute \src "libresoc.v:139864.3-139875.6" - wire width 64 $0\a[63:0] - attribute \src "libresoc.v:139584.7-139584.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:139864.3-139875.6" - wire width 64 $1\a[63:0] - attribute \src "libresoc.v:139863.18-139863.100" - wire width 64 $not$libresoc.v:139863$5572_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - wire width 64 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "libresoc.v:139584.7-139584.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 24 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 43 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:139863$5572 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:137634$5844 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $not$libresoc.v:139863$5572_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1000 + connect \Y $eq$libresoc.v:137634$5844_Y end - attribute \src "libresoc.v:139584.7-139584.20" - process $proc$libresoc.v:139584$5574 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:137644$5854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1001 + connect \Y $eq$libresoc.v:137644$5854_Y end - attribute \src "libresoc.v:139864.3-139875.6" - process $proc$libresoc.v:139864$5573 - assign { } { } - assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:139865.5-139865.29" - switch \initial - attribute \src "libresoc.v:139865.9-139865.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" - switch \logical_op__invert_in - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[63:0] \$23 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\a[63:0] \ra - end - sync always - update \a $0\a[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:137645$5855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1010 + connect \Y $eq$libresoc.v:137645$5855_Y end - connect \$23 $not$libresoc.v:139863$5572_Y - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$22 \xer_so - connect \rb$21 \rb - connect \b \rb - connect \ra$20 \a -end -attribute \src "libresoc.v:139886.1-140138.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" -attribute \generator "nMigen" -module \input$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 18 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 28 \mul_op__insn$13 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 22 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 32 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 29 \ra$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 30 \rb$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 15 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 31 \xer_so$16 - connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$16 \xer_so - connect \rb$15 \rb - connect \b \rb - connect \ra$14 \a - connect \a \ra -end -attribute \src "libresoc.v:140142.1-140361.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.int" -attribute \generator "nMigen" -module \int - attribute \src "libresoc.v:140267.3-140273.6" - wire width 5 $0$memwr$\memory$libresoc.v:140272$5607_ADDR[4:0]$5616 - attribute \src "libresoc.v:140267.3-140273.6" - wire width 64 $0$memwr$\memory$libresoc.v:140272$5607_DATA[63:0]$5617 - attribute \src "libresoc.v:140267.3-140273.6" - wire width 64 $0$memwr$\memory$libresoc.v:140272$5607_EN[63:0]$5618 - attribute \src "libresoc.v:140267.3-140273.6" - wire width 5 $0\_0_[4:0] - attribute \src "libresoc.v:140267.3-140273.6" - wire width 5 $0\_1_[4:0] - attribute \src "libresoc.v:140267.3-140273.6" - wire width 5 $0\_2_[4:0] - attribute \src "libresoc.v:140267.3-140273.6" - wire width 5 $0\_3_[4:0] - attribute \src "libresoc.v:140296.3-140305.6" - wire width 64 $0\dmi__data_o[63:0] - attribute \src "libresoc.v:140143.7-140143.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:140287.3-140295.6" - wire $0\ren_delay$10$next[0:0]$5627 - attribute \src "libresoc.v:140220.3-140221.43" - wire $0\ren_delay$10[0:0]$5609 - attribute \src "libresoc.v:140186.7-140186.28" - wire $0\ren_delay$10[0:0]$5675 - attribute \src "libresoc.v:140316.3-140324.6" - wire $0\ren_delay$8$next[0:0]$5632 - attribute \src "libresoc.v:140224.3-140225.41" - wire $0\ren_delay$8[0:0]$5613 - attribute \src "libresoc.v:140190.7-140190.27" - wire $0\ren_delay$8[0:0]$5677 - attribute \src "libresoc.v:140335.3-140343.6" - wire $0\ren_delay$9$next[0:0]$5636 - attribute \src "libresoc.v:140222.3-140223.41" - wire $0\ren_delay$9[0:0]$5611 - attribute \src "libresoc.v:140194.7-140194.27" - wire $0\ren_delay$9[0:0]$5679 - attribute \src "libresoc.v:140278.3-140286.6" - wire $0\ren_delay$next[0:0]$5624 - attribute \src "libresoc.v:140226.3-140227.35" - wire $0\ren_delay[0:0] - attribute \src "libresoc.v:140306.3-140315.6" - wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:140325.3-140334.6" - wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:140344.3-140353.6" - wire width 64 $0\src3__data_o[63:0] - attribute \src "libresoc.v:140296.3-140305.6" - wire width 64 $1\dmi__data_o[63:0] - attribute \src "libresoc.v:140287.3-140295.6" - wire $1\ren_delay$10$next[0:0]$5628 - attribute \src "libresoc.v:140316.3-140324.6" - wire $1\ren_delay$8$next[0:0]$5633 - attribute \src "libresoc.v:140335.3-140343.6" - wire $1\ren_delay$9$next[0:0]$5637 - attribute \src "libresoc.v:140278.3-140286.6" - wire $1\ren_delay$next[0:0]$5625 - attribute \src "libresoc.v:140184.7-140184.23" - wire $1\ren_delay[0:0] - attribute \src "libresoc.v:140306.3-140315.6" - wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:140325.3-140334.6" - wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:140344.3-140353.6" - wire width 64 $1\src3__data_o[63:0] - attribute \src "libresoc.v:140274.26-140274.32" - wire width 64 $memrd$\memory$libresoc.v:140274$5619_DATA - attribute \src "libresoc.v:140275.30-140275.36" - wire width 64 $memrd$\memory$libresoc.v:140275$5620_DATA - attribute \src "libresoc.v:140276.30-140276.36" - wire width 64 $memrd$\memory$libresoc.v:140276$5621_DATA - attribute \src "libresoc.v:140277.30-140277.36" - wire width 64 $memrd$\memory$libresoc.v:140277$5622_DATA - attribute \src "libresoc.v:0.0-0.0" - wire width 5 $memwr$\memory$libresoc.v:140272$5607_ADDR - attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:140272$5607_DATA - attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:140272$5607_EN - attribute \src "libresoc.v:140263.13-140263.16" - wire width 5 \_0_ - attribute \src "libresoc.v:140264.13-140264.16" - wire width 5 \_1_ - attribute \src "libresoc.v:140265.13-140265.16" - wire width 5 \_2_ - attribute \src "libresoc.v:140266.13-140266.16" - wire width 5 \_3_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 15 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 14 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 16 \dest1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 2 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 4 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 3 \dmi__ren - attribute \src "libresoc.v:140143.7-140143.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 5 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 6 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 5 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 7 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 9 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 8 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 10 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 5 input 12 \src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 11 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire input 13 \src3__ren - attribute \src "libresoc.v:140228.14-140228.20" - memory width 64 size 32 \memory - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5639 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5639 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 0 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5640 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5640 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 1 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5641 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5641 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 2 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:137655$5865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 4'1011 + connect \Y $eq$libresoc.v:137655$5865_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5642 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5642 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 3 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + cell $eq $eq$libresoc.v:137662$5872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:137662$5872_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5643 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5643 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 4 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + cell $eq $eq$libresoc.v:137665$5875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:137665$5875_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5644 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5644 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 5 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $eq $eq$libresoc.v:137667$5877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'1 + connect \Y $eq$libresoc.v:137667$5877_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5645 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5645 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 6 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $eq $eq$libresoc.v:137668$5878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'10 + connect \Y $eq$libresoc.v:137668$5878_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5646 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5646 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 7 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" + cell $eq $eq$libresoc.v:137670$5880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'10 + connect \Y $eq$libresoc.v:137670$5880_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5647 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5647 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 8 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + cell $eq $eq$libresoc.v:137672$5882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:137672$5882_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5648 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5648 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 9 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $eq $eq$libresoc.v:137675$5886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state$503 + connect \B 1'1 + connect \Y $eq$libresoc.v:137675$5886_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5649 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5649 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 10 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $eq $eq$libresoc.v:137676$5887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state$503 + connect \B 2'10 + connect \Y $eq$libresoc.v:137676$5887_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5650 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5650 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 11 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" + cell $eq $eq$libresoc.v:137678$5889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state$503 + connect \B 2'10 + connect \Y $eq$libresoc.v:137678$5889_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5651 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5651 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 12 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + cell $pos $extend$libresoc.v:137674$5884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \dmi0__addr_i + connect \Y $extend$libresoc.v:137674$5884_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5652 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5652 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 13 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:137603$5813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137603$5813_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5653 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5653 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 14 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:137605$5815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137605$5815_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5654 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5654 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 15 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:137608$5818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137608$5818_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5655 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5655 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 16 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:137613$5823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137613$5823_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5656 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5656 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 17 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:137615$5825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137615$5825_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5657 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5657 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 18 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:137619$5829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137619$5829_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5658 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5658 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 19 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:137625$5835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137625$5835_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5659 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5659 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 20 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:137627$5837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137627$5837_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5660 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5660 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 21 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:137630$5840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137630$5840_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5661 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5661 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 22 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:137635$5845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137635$5845_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5662 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5662 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 23 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:137637$5847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137637$5847_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5663 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5663 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 24 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:137639$5849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137639$5849_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5664 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5664 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 25 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:137646$5856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137646$5856_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5665 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5665 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 26 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:137648$5858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137648$5858_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5666 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5666 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 27 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:137650$5860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137650$5860_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5667 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5667 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 28 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:137656$5866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137656$5866_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5668 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5668 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 29 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:137658$5868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137658$5868_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5669 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5669 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 30 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:137660$5870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:137660$5870_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5670 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5670 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 31 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:137610$5820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core + connect \Y $not$libresoc.v:137610$5820_Y end - attribute \src "libresoc.v:140274.26-140274.32" - cell $memrd $memrd$\memory$libresoc.v:140274$5619 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_0_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:140274$5619_DATA - connect \EN 1'x + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:137621$5831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core + connect \Y $not$libresoc.v:137621$5831_Y end - attribute \src "libresoc.v:140275.30-140275.36" - cell $memrd $memrd$\memory$libresoc.v:140275$5620 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_1_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:140275$5620_DATA - connect \EN 1'x + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:137632$5842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core + connect \Y $not$libresoc.v:137632$5842_Y end - attribute \src "libresoc.v:140276.30-140276.36" - cell $memrd $memrd$\memory$libresoc.v:140276$5621 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_2_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:140276$5621_DATA - connect \EN 1'x + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:137642$5852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core + connect \Y $not$libresoc.v:137642$5852_Y end - attribute \src "libresoc.v:140277.30-140277.36" - cell $memrd $memrd$\memory$libresoc.v:140277$5622 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_3_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:140277$5622_DATA - connect \EN 1'x + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:137653$5863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core + connect \Y $not$libresoc.v:137653$5863_Y end - attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5671 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5671 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:140272$5607_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:140272$5607_DATA - connect \EN $memwr$\memory$libresoc.v:140272$5607_EN + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:137663$5873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_update_core + connect \Y $not$libresoc.v:137663$5873_Y end - attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5680 - sync always - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + cell $not $not$libresoc.v:137666$5876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$484 + connect \Y $not$libresoc.v:137666$5876_Y end - attribute \src "libresoc.v:140143.7-140143.20" - process $proc$libresoc.v:140143$5672 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:137484$5694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \B \$13 + connect \Y $or$libresoc.v:137484$5694_Y end - attribute \src "libresoc.v:140184.7-140184.23" - process $proc$libresoc.v:140184$5673 - assign { } { } - assign $1\ren_delay[0:0] 1'0 - sync always - sync init - update \ren_delay $1\ren_delay[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:137529$5739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \$21 + connect \Y $or$libresoc.v:137529$5739_Y end - attribute \src "libresoc.v:140186.7-140186.28" - process $proc$libresoc.v:140186$5674 - assign { } { } - assign $0\ren_delay$10[0:0]$5675 1'0 - sync always - sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5675 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:137551$5761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:137551$5761_Y end - attribute \src "libresoc.v:140190.7-140190.27" - process $proc$libresoc.v:140190$5676 - assign { } { } - assign $0\ren_delay$8[0:0]$5677 1'0 - sync always - sync init - update \ren_delay$8 $0\ren_delay$8[0:0]$5677 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:137598$5808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$359 + connect \B \$361 + connect \Y $or$libresoc.v:137598$5808_Y end - attribute \src "libresoc.v:140194.7-140194.27" - process $proc$libresoc.v:140194$5678 - assign { } { } - assign $0\ren_delay$9[0:0]$5679 1'0 - sync always - sync init - update \ren_delay$9 $0\ren_delay$9[0:0]$5679 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:137600$5810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$363 + connect \B \$365 + connect \Y $or$libresoc.v:137600$5810_Y end - attribute \src "libresoc.v:140220.3-140221.43" - process $proc$libresoc.v:140220$5608 - assign { } { } - assign $0\ren_delay$10[0:0]$5609 \ren_delay$10$next - sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5609 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:137606$5816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:137606$5816_Y end - attribute \src "libresoc.v:140222.3-140223.41" - process $proc$libresoc.v:140222$5610 - assign { } { } - assign $0\ren_delay$9[0:0]$5611 \ren_delay$9$next - sync posedge \coresync_clk - update \ren_delay$9 $0\ren_delay$9[0:0]$5611 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:137629$5839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:137629$5839_Y end - attribute \src "libresoc.v:140224.3-140225.41" - process $proc$libresoc.v:140224$5612 - assign { } { } - assign $0\ren_delay$8[0:0]$5613 \ren_delay$8$next - sync posedge \coresync_clk - update \ren_delay$8 $0\ren_delay$8[0:0]$5613 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $or $or$libresoc.v:137669$5879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$487 + connect \B \$489 + connect \Y $or$libresoc.v:137669$5879_Y end - attribute \src "libresoc.v:140226.3-140227.35" - process $proc$libresoc.v:140226$5614 - assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $or $or$libresoc.v:137677$5888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$504 + connect \B \$506 + connect \Y $or$libresoc.v:137677$5888_Y end - attribute \src "libresoc.v:140267.3-140273.6" - process $proc$libresoc.v:140267$5615 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\memory$libresoc.v:140272$5607_ADDR[4:0]$5616 5'xxxxx - assign $0$memwr$\memory$libresoc.v:140272$5607_DATA[63:0]$5617 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:140272$5607_EN[63:0]$5618 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[4:0] \src1__addr - assign $0\_1_[4:0] \src2__addr - assign $0\_2_[4:0] \src3__addr - assign $0\_3_[4:0] \dmi__addr - attribute \src "libresoc.v:140272.5-140272.58" - switch \dest1__wen - attribute \src "libresoc.v:140272.9-140272.19" - case 1'1 - assign $0$memwr$\memory$libresoc.v:140272$5607_ADDR[4:0]$5616 \dest1__addr - assign $0$memwr$\memory$libresoc.v:140272$5607_DATA[63:0]$5617 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:140272$5607_EN[63:0]$5618 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - sync posedge \coresync_clk - update \_0_ $0\_0_[4:0] - update \_1_ $0\_1_[4:0] - update \_2_ $0\_2_[4:0] - update \_3_ $0\_3_[4:0] - update $memwr$\memory$libresoc.v:140272$5607_ADDR $0$memwr$\memory$libresoc.v:140272$5607_ADDR[4:0]$5616 - update $memwr$\memory$libresoc.v:140272$5607_DATA $0$memwr$\memory$libresoc.v:140272$5607_DATA[63:0]$5617 - update $memwr$\memory$libresoc.v:140272$5607_EN $0$memwr$\memory$libresoc.v:140272$5607_EN[63:0]$5618 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $or $or$libresoc.v:137685$5896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:137685$5896_Y end - attribute \src "libresoc.v:140278.3-140286.6" - process $proc$libresoc.v:140278$5623 - assign { } { } - assign { } { } - assign $0\ren_delay$next[0:0]$5624 $1\ren_delay$next[0:0]$5625 - attribute \src "libresoc.v:140279.5-140279.29" - switch \initial - attribute \src "libresoc.v:140279.9-140279.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$next[0:0]$5625 1'0 - case - assign $1\ren_delay$next[0:0]$5625 \src1__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5624 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + cell $pos $pos$libresoc.v:137674$5885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:137674$5884_Y + connect \Y $pos$libresoc.v:137674$5885_Y end - attribute \src "libresoc.v:140287.3-140295.6" - process $proc$libresoc.v:140287$5626 - assign { } { } - assign { } { } - assign $0\ren_delay$10$next[0:0]$5627 $1\ren_delay$10$next[0:0]$5628 - attribute \src "libresoc.v:140288.5-140288.29" - switch \initial - attribute \src "libresoc.v:140288.9-140288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$10$next[0:0]$5628 1'0 - case - assign $1\ren_delay$10$next[0:0]$5628 \dmi__ren - end - sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5627 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:137452$5662 + parameter \WIDTH 1 + connect \A \gpio_e15__pad__i + connect \B \io_bd [24] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137452$5662_Y end - attribute \src "libresoc.v:140296.3-140305.6" - process $proc$libresoc.v:140296$5629 - assign { } { } - assign { } { } - assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "libresoc.v:140297.5-140297.29" - switch \initial - attribute \src "libresoc.v:140297.9-140297.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$10 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi__data_o[63:0] \memory_r_data$7 - case - assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dmi__data_o $0\dmi__data_o[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:137453$5663 + parameter \WIDTH 1 + connect \A \gpio_e15__core__o + connect \B \io_bd [25] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137453$5663_Y end - attribute \src "libresoc.v:140306.3-140315.6" - process $proc$libresoc.v:140306$5630 - assign { } { } - assign { } { } - assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:140307.5-140307.29" - switch \initial - attribute \src "libresoc.v:140307.9-140307.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src1__data_o[63:0] \memory_r_data - case - assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src1__data_o $0\src1__data_o[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:137454$5664 + parameter \WIDTH 1 + connect \A \gpio_e15__core__oe + connect \B \io_bd [26] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137454$5664_Y end - attribute \src "libresoc.v:140316.3-140324.6" - process $proc$libresoc.v:140316$5631 - assign { } { } - assign { } { } - assign $0\ren_delay$8$next[0:0]$5632 $1\ren_delay$8$next[0:0]$5633 - attribute \src "libresoc.v:140317.5-140317.29" - switch \initial - attribute \src "libresoc.v:140317.9-140317.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$8$next[0:0]$5633 1'0 - case - assign $1\ren_delay$8$next[0:0]$5633 \src2__ren - end - sync always - update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5632 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:137455$5665 + parameter \WIDTH 1 + connect \A \gpio_s0__pad__i + connect \B \io_bd [27] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137455$5665_Y end - attribute \src "libresoc.v:140325.3-140334.6" - process $proc$libresoc.v:140325$5634 - assign { } { } - assign { } { } - assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:140326.5-140326.29" - switch \initial - attribute \src "libresoc.v:140326.9-140326.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$8 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[63:0] \memory_r_data$3 - case - assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src2__data_o $0\src2__data_o[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:137456$5666 + parameter \WIDTH 1 + connect \A \gpio_s0__core__o + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137456$5666_Y end - attribute \src "libresoc.v:140335.3-140343.6" - process $proc$libresoc.v:140335$5635 - assign { } { } - assign { } { } - assign $0\ren_delay$9$next[0:0]$5636 $1\ren_delay$9$next[0:0]$5637 - attribute \src "libresoc.v:140336.5-140336.29" - switch \initial - attribute \src "libresoc.v:140336.9-140336.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$9$next[0:0]$5637 1'0 - case - assign $1\ren_delay$9$next[0:0]$5637 \src3__ren - end - sync always - update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5636 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:137457$5667 + parameter \WIDTH 1 + connect \A \gpio_s0__core__oe + connect \B \io_bd [29] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137457$5667_Y end - attribute \src "libresoc.v:140344.3-140353.6" - process $proc$libresoc.v:140344$5638 - assign { } { } - assign { } { } - assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] - attribute \src "libresoc.v:140345.5-140345.29" - switch \initial - attribute \src "libresoc.v:140345.9-140345.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src3__data_o[63:0] \memory_r_data$5 - case - assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src3__data_o $0\src3__data_o[63:0] + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:137458$5668 + parameter \WIDTH 1 + connect \A \gpio_s1__pad__i + connect \B \io_bd [30] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137458$5668_Y end - connect \memory_r_data $memrd$\memory$libresoc.v:140274$5619_DATA - connect \memory_r_data$3 $memrd$\memory$libresoc.v:140275$5620_DATA - connect \memory_r_data$5 $memrd$\memory$libresoc.v:140276$5621_DATA - connect \memory_r_data$7 $memrd$\memory$libresoc.v:140277$5622_DATA - connect \memory_w_data \dest1__data_i - connect \memory_w_en \dest1__wen - connect \memory_w_addr \dest1__addr - connect \memory_r_addr$6 \dmi__addr - connect \memory_r_addr$4 \src3__addr - connect \memory_r_addr$2 \src2__addr - connect \memory_r_addr \src1__addr -end -attribute \src "libresoc.v:140365.1-143079.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag" -attribute \generator "nMigen" -module \jtag - attribute \src "libresoc.v:142511.3-142537.6" - wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:142159.3-142174.6" - wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:142672.3-142704.6" - wire width 4 $0\dmi0__addr_i$next[3:0]$6091 - attribute \src "libresoc.v:142062.3-142063.41" - wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:142758.3-142784.6" - wire width 64 $0\dmi0__din$next[63:0]$6104 - attribute \src "libresoc.v:142058.3-142059.35" - wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:142361.3-142377.6" - wire $0\dmi0_addrsr__oe$next[0:0]$6028 - attribute \src "libresoc.v:142090.3-142091.47" - wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:142378.3-142398.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6032 - attribute \src "libresoc.v:142088.3-142089.47" - wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:142343.3-142351.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$6022 - attribute \src "libresoc.v:142094.3-142095.63" - wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:142352.3-142360.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 - attribute \src "libresoc.v:142092.3-142093.73" - wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:142785.3-142805.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$6109 - attribute \src "libresoc.v:142056.3-142057.45" - wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:142417.3-142433.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$6043 - attribute \src "libresoc.v:142082.3-142083.47" - wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:142434.3-142454.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$6047 - attribute \src "libresoc.v:142080.3-142081.47" - wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:142399.3-142407.6" - wire $0\dmi0_datasr_update_core$next[0:0]$6037 - attribute \src "libresoc.v:142086.3-142087.63" - wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:142408.3-142416.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$6040 - attribute \src "libresoc.v:142084.3-142085.73" - wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:142705.3-142757.6" - wire width 3 $0\fsm_state$503$next[2:0]$6097 - attribute \src "libresoc.v:142060.3-142061.45" - wire width 3 $0\fsm_state$503[2:0]$5943 - attribute \src "libresoc.v:141011.13-141011.35" - wire width 3 $0\fsm_state$503[2:0]$6143 - attribute \src "libresoc.v:142571.3-142623.6" - wire width 3 $0\fsm_state$next[2:0]$6074 - attribute \src "libresoc.v:142068.3-142069.35" - wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:140366.7-140366.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:142853.3-142873.6" - wire width 154 $0\io_bd$next[153:0]$6126 - attribute \src "libresoc.v:142120.3-142121.27" - wire width 154 $0\io_bd[153:0] - attribute \src "libresoc.v:142835.3-142852.6" - wire width 154 $0\io_sr$next[153:0]$6122 - attribute \src "libresoc.v:142122.3-142123.27" - wire width 154 $0\io_sr[153:0] - attribute \src "libresoc.v:142538.3-142570.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$6068 - attribute \src "libresoc.v:142070.3-142071.41" - wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:142624.3-142650.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$6081 - attribute \src "libresoc.v:142066.3-142067.45" - wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:142249.3-142265.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$5998 - attribute \src "libresoc.v:142106.3-142107.53" - wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:142266.3-142286.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$6002 - attribute \src "libresoc.v:142104.3-142105.53" - wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:142231.3-142239.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$5992 - attribute \src "libresoc.v:142110.3-142111.69" - wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:142240.3-142248.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 - attribute \src "libresoc.v:142108.3-142109.79" - wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:142651.3-142671.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6086 - attribute \src "libresoc.v:142064.3-142065.51" - wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:142305.3-142321.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$6013 - attribute \src "libresoc.v:142098.3-142099.53" - wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:142322.3-142342.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$6017 - attribute \src "libresoc.v:142096.3-142097.53" - wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:142287.3-142295.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$6007 - attribute \src "libresoc.v:142102.3-142103.69" - wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:142296.3-142304.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 - attribute \src "libresoc.v:142100.3-142101.79" - wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:142193.3-142209.6" - wire $0\sr0__oe$next[0:0]$5983 - attribute \src "libresoc.v:142114.3-142115.31" - wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:142210.3-142230.6" - wire width 3 $0\sr0_reg$next[2:0]$5987 - attribute \src "libresoc.v:142112.3-142113.31" - wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:142175.3-142183.6" - wire $0\sr0_update_core$next[0:0]$5977 - attribute \src "libresoc.v:142118.3-142119.47" - wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:142184.3-142192.6" - wire $0\sr0_update_core_prev$next[0:0]$5980 - attribute \src "libresoc.v:142116.3-142117.57" - wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:142825.3-142834.6" - wire width 2 $0\sr5__i[1:0] - attribute \src "libresoc.v:142473.3-142489.6" - wire $0\sr5__oe$next[0:0]$6058 - attribute \src "libresoc.v:142074.3-142075.31" - wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:142490.3-142510.6" - wire width 2 $0\sr5_reg$next[1:0]$6062 - attribute \src "libresoc.v:142072.3-142073.31" - wire width 2 $0\sr5_reg[1:0] - attribute \src "libresoc.v:142455.3-142463.6" - wire $0\sr5_update_core$next[0:0]$6052 - attribute \src "libresoc.v:142078.3-142079.47" - wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:142464.3-142472.6" - wire $0\sr5_update_core_prev$next[0:0]$6055 - attribute \src "libresoc.v:142076.3-142077.57" - wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:142806.3-142824.6" - wire $0\wb_dcache_en$next[0:0]$6114 - attribute \src "libresoc.v:142054.3-142055.41" - wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:142806.3-142824.6" - wire $0\wb_icache_en$next[0:0]$6115 - attribute \src "libresoc.v:142052.3-142053.41" - wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:142511.3-142537.6" - wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:142159.3-142174.6" - wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:142672.3-142704.6" - wire width 4 $1\dmi0__addr_i$next[3:0]$6092 - attribute \src "libresoc.v:140924.13-140924.32" - wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:142758.3-142784.6" - wire width 64 $1\dmi0__din$next[63:0]$6105 - attribute \src "libresoc.v:140929.14-140929.46" - wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:142361.3-142377.6" - wire $1\dmi0_addrsr__oe$next[0:0]$6029 - attribute \src "libresoc.v:140943.7-140943.29" - wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:142378.3-142398.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6033 - attribute \src "libresoc.v:140951.13-140951.36" - wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:142343.3-142351.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$6023 - attribute \src "libresoc.v:140959.7-140959.37" - wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:142352.3-142360.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 - attribute \src "libresoc.v:140963.7-140963.42" - wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:142785.3-142805.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$6110 - attribute \src "libresoc.v:140967.14-140967.51" - wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:142417.3-142433.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$6044 - attribute \src "libresoc.v:140973.13-140973.35" - wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:142434.3-142454.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$6048 - attribute \src "libresoc.v:140981.14-140981.52" - wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:142399.3-142407.6" - wire $1\dmi0_datasr_update_core$next[0:0]$6038 - attribute \src "libresoc.v:140989.7-140989.37" - wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:142408.3-142416.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$6041 - attribute \src "libresoc.v:140993.7-140993.42" - wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:142705.3-142757.6" - wire width 3 $1\fsm_state$503$next[2:0]$6098 - attribute \src "libresoc.v:142571.3-142623.6" - wire width 3 $1\fsm_state$next[2:0]$6075 - attribute \src "libresoc.v:141009.13-141009.29" - wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:142853.3-142873.6" - wire width 154 $1\io_bd$next[153:0]$6127 - attribute \src "libresoc.v:141209.15-141209.67" - wire width 154 $1\io_bd[153:0] - attribute \src "libresoc.v:142835.3-142852.6" - wire width 154 $1\io_sr$next[153:0]$6123 - attribute \src "libresoc.v:141221.15-141221.67" - wire width 154 $1\io_sr[153:0] - attribute \src "libresoc.v:142538.3-142570.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$6069 - attribute \src "libresoc.v:141230.14-141230.41" - wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:142624.3-142650.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$6082 - attribute \src "libresoc.v:141239.14-141239.51" - wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:142249.3-142265.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$5999 - attribute \src "libresoc.v:141253.7-141253.32" - wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:142266.3-142286.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$6003 - attribute \src "libresoc.v:141261.14-141261.47" - wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:142231.3-142239.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$5993 - attribute \src "libresoc.v:141269.7-141269.40" - wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:142240.3-142248.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 - attribute \src "libresoc.v:141273.7-141273.45" - wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:142651.3-142671.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6087 - attribute \src "libresoc.v:141277.14-141277.54" - wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:142305.3-142321.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$6014 - attribute \src "libresoc.v:141283.13-141283.38" - wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:142322.3-142342.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$6018 - attribute \src "libresoc.v:141291.14-141291.55" - wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:142287.3-142295.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$6008 - attribute \src "libresoc.v:141299.7-141299.40" - wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:142296.3-142304.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 - attribute \src "libresoc.v:141303.7-141303.45" - wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:142193.3-142209.6" - wire $1\sr0__oe$next[0:0]$5984 - attribute \src "libresoc.v:141733.7-141733.21" - wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:142210.3-142230.6" - wire width 3 $1\sr0_reg$next[2:0]$5988 - attribute \src "libresoc.v:141741.13-141741.27" - wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:142175.3-142183.6" - wire $1\sr0_update_core$next[0:0]$5978 - attribute \src "libresoc.v:141749.7-141749.29" - wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:142184.3-142192.6" - wire $1\sr0_update_core_prev$next[0:0]$5981 - attribute \src "libresoc.v:141753.7-141753.34" - wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:142825.3-142834.6" - wire width 2 $1\sr5__i[1:0] - attribute \src "libresoc.v:142473.3-142489.6" - wire $1\sr5__oe$next[0:0]$6059 - attribute \src "libresoc.v:141763.7-141763.21" - wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:142490.3-142510.6" - wire width 2 $1\sr5_reg$next[1:0]$6063 - attribute \src "libresoc.v:141771.13-141771.27" - wire width 2 $1\sr5_reg[1:0] - attribute \src "libresoc.v:142455.3-142463.6" - wire $1\sr5_update_core$next[0:0]$6053 - attribute \src "libresoc.v:141779.7-141779.29" - wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:142464.3-142472.6" - wire $1\sr5_update_core_prev$next[0:0]$6056 - attribute \src "libresoc.v:141783.7-141783.34" - wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:142806.3-142824.6" - wire $1\wb_dcache_en$next[0:0]$6116 - attribute \src "libresoc.v:141788.7-141788.26" - wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:142806.3-142824.6" - wire $1\wb_icache_en$next[0:0]$6117 - attribute \src "libresoc.v:141793.7-141793.26" - wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:142672.3-142704.6" - wire width 4 $2\dmi0__addr_i$next[3:0]$6093 - attribute \src "libresoc.v:142758.3-142784.6" - wire width 64 $2\dmi0__din$next[63:0]$6106 - attribute \src "libresoc.v:142361.3-142377.6" - wire $2\dmi0_addrsr__oe$next[0:0]$6030 - attribute \src "libresoc.v:142378.3-142398.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6034 - attribute \src "libresoc.v:142785.3-142805.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$6111 - attribute \src "libresoc.v:142417.3-142433.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$6045 - attribute \src "libresoc.v:142434.3-142454.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$6049 - attribute \src "libresoc.v:142705.3-142757.6" - wire width 3 $2\fsm_state$503$next[2:0]$6099 - attribute \src "libresoc.v:142571.3-142623.6" - wire width 3 $2\fsm_state$next[2:0]$6076 - attribute \src "libresoc.v:142853.3-142873.6" - wire width 154 $2\io_bd$next[153:0]$6128 - attribute \src "libresoc.v:142835.3-142852.6" - wire width 154 $2\io_sr$next[153:0]$6124 - attribute \src "libresoc.v:142538.3-142570.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$6070 - attribute \src "libresoc.v:142624.3-142650.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$6083 - attribute \src "libresoc.v:142249.3-142265.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$6000 - attribute \src "libresoc.v:142266.3-142286.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$6004 - attribute \src "libresoc.v:142651.3-142671.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6088 - attribute \src "libresoc.v:142305.3-142321.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$6015 - attribute \src "libresoc.v:142322.3-142342.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6019 - attribute \src "libresoc.v:142193.3-142209.6" - wire $2\sr0__oe$next[0:0]$5985 - attribute \src "libresoc.v:142210.3-142230.6" - wire width 3 $2\sr0_reg$next[2:0]$5989 - attribute \src "libresoc.v:142473.3-142489.6" - wire $2\sr5__oe$next[0:0]$6060 - attribute \src "libresoc.v:142490.3-142510.6" - wire width 2 $2\sr5_reg$next[1:0]$6064 - attribute \src "libresoc.v:142806.3-142824.6" - wire $2\wb_dcache_en$next[0:0]$6118 - attribute \src "libresoc.v:142806.3-142824.6" - wire $2\wb_icache_en$next[0:0]$6119 - attribute \src "libresoc.v:142672.3-142704.6" - wire width 4 $3\dmi0__addr_i$next[3:0]$6094 - attribute \src "libresoc.v:142758.3-142784.6" - wire width 64 $3\dmi0__din$next[63:0]$6107 - attribute \src "libresoc.v:142378.3-142398.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6035 - attribute \src "libresoc.v:142785.3-142805.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$6112 - attribute \src "libresoc.v:142434.3-142454.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$6050 - attribute \src "libresoc.v:142705.3-142757.6" - wire width 3 $3\fsm_state$503$next[2:0]$6100 - attribute \src "libresoc.v:142571.3-142623.6" - wire width 3 $3\fsm_state$next[2:0]$6077 - attribute \src "libresoc.v:142538.3-142570.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$6071 - attribute \src "libresoc.v:142624.3-142650.6" - wire width 64 $3\jtag_wb__dat_w$next[63:0]$6084 - attribute \src "libresoc.v:142266.3-142286.6" - wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$6005 - attribute \src "libresoc.v:142651.3-142671.6" - wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6089 - attribute \src "libresoc.v:142322.3-142342.6" - wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6020 - attribute \src "libresoc.v:142210.3-142230.6" - wire width 3 $3\sr0_reg$next[2:0]$5990 - attribute \src "libresoc.v:142490.3-142510.6" - wire width 2 $3\sr5_reg$next[1:0]$6065 - attribute \src "libresoc.v:142672.3-142704.6" - wire width 4 $4\dmi0__addr_i$next[3:0]$6095 - attribute \src "libresoc.v:142705.3-142757.6" - wire width 3 $4\fsm_state$503$next[2:0]$6101 - attribute \src "libresoc.v:142571.3-142623.6" - wire width 3 $4\fsm_state$next[2:0]$6078 - attribute \src "libresoc.v:142538.3-142570.6" - wire width 29 $4\jtag_wb__adr$next[28:0]$6072 - attribute \src "libresoc.v:142705.3-142757.6" - wire width 3 $5\fsm_state$503$next[2:0]$6102 - attribute \src "libresoc.v:142571.3-142623.6" - wire width 3 $5\fsm_state$next[2:0]$6079 - attribute \src "libresoc.v:142016.19-142016.112" - wire width 30 $add$libresoc.v:142016$5901_Y - attribute \src "libresoc.v:142018.19-142018.112" - wire width 30 $add$libresoc.v:142018$5903_Y - attribute \src "libresoc.v:142024.19-142024.112" - wire width 5 $add$libresoc.v:142024$5910_Y - attribute \src "libresoc.v:142025.19-142025.112" - wire width 5 $add$libresoc.v:142025$5911_Y - attribute \src "libresoc.v:141840.18-141840.112" - wire $and$libresoc.v:141840$5725_Y - attribute \src "libresoc.v:141907.18-141907.108" - wire $and$libresoc.v:141907$5792_Y - attribute \src "libresoc.v:141918.18-141918.110" - wire $and$libresoc.v:141918$5803_Y - attribute \src "libresoc.v:141946.19-141946.110" - wire $and$libresoc.v:141946$5831_Y - attribute \src "libresoc.v:141949.19-141949.114" - wire $and$libresoc.v:141949$5834_Y - attribute \src "libresoc.v:141952.19-141952.112" - wire $and$libresoc.v:141952$5837_Y - attribute \src "libresoc.v:141954.19-141954.113" - wire $and$libresoc.v:141954$5839_Y - attribute \src "libresoc.v:141956.19-141956.121" - wire $and$libresoc.v:141956$5841_Y - attribute \src "libresoc.v:141959.19-141959.114" - wire $and$libresoc.v:141959$5844_Y - attribute \src "libresoc.v:141961.19-141961.112" - wire $and$libresoc.v:141961$5846_Y - attribute \src "libresoc.v:141965.19-141965.113" - wire $and$libresoc.v:141965$5850_Y - attribute \src "libresoc.v:141967.19-141967.132" - wire $and$libresoc.v:141967$5852_Y - attribute \src "libresoc.v:141971.19-141971.114" - wire $and$libresoc.v:141971$5856_Y - attribute \src "libresoc.v:141973.19-141973.112" - wire $and$libresoc.v:141973$5858_Y - attribute \src "libresoc.v:141976.19-141976.113" - wire $and$libresoc.v:141976$5861_Y - attribute \src "libresoc.v:141978.19-141978.132" - wire $and$libresoc.v:141978$5863_Y - attribute \src "libresoc.v:141981.19-141981.114" - wire $and$libresoc.v:141981$5866_Y - attribute \src "libresoc.v:141983.19-141983.112" - wire $and$libresoc.v:141983$5868_Y - attribute \src "libresoc.v:141985.18-141985.108" - wire $and$libresoc.v:141985$5870_Y - attribute \src "libresoc.v:141986.19-141986.113" - wire $and$libresoc.v:141986$5871_Y - attribute \src "libresoc.v:141988.19-141988.129" - wire $and$libresoc.v:141988$5873_Y - attribute \src "libresoc.v:141992.19-141992.114" - wire $and$libresoc.v:141992$5877_Y - attribute \src "libresoc.v:141994.19-141994.112" - wire $and$libresoc.v:141994$5879_Y - attribute \src "libresoc.v:141996.18-141996.111" - wire $and$libresoc.v:141996$5881_Y - attribute \src "libresoc.v:141997.19-141997.113" - wire $and$libresoc.v:141997$5882_Y - attribute \src "libresoc.v:141999.19-141999.129" - wire $and$libresoc.v:141999$5884_Y - attribute \src "libresoc.v:142002.19-142002.114" - wire $and$libresoc.v:142002$5887_Y - attribute \src "libresoc.v:142004.19-142004.112" - wire $and$libresoc.v:142004$5889_Y - attribute \src "libresoc.v:142006.19-142006.113" - wire $and$libresoc.v:142006$5891_Y - attribute \src "libresoc.v:142009.19-142009.121" - wire $and$libresoc.v:142009$5894_Y - attribute \src "libresoc.v:142041.17-142041.106" - wire $and$libresoc.v:142041$5927_Y - attribute \src "libresoc.v:141796.17-141796.110" - wire $eq$libresoc.v:141796$5681_Y - attribute \src "libresoc.v:141807.18-141807.111" - wire $eq$libresoc.v:141807$5692_Y - attribute \src "libresoc.v:141818.18-141818.111" - wire $eq$libresoc.v:141818$5703_Y - attribute \src "libresoc.v:141851.17-141851.110" - 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attribute \src "libresoc.v:141963.18-141963.111" - wire $eq$libresoc.v:141963$5848_Y - attribute \src "libresoc.v:141968.19-141968.112" - wire $eq$libresoc.v:141968$5853_Y - attribute \src "libresoc.v:141969.19-141969.112" - wire $eq$libresoc.v:141969$5854_Y - attribute \src "libresoc.v:141979.19-141979.112" - wire $eq$libresoc.v:141979$5864_Y - attribute \src "libresoc.v:141989.19-141989.112" - wire $eq$libresoc.v:141989$5874_Y - attribute \src "libresoc.v:141990.19-141990.112" - wire $eq$libresoc.v:141990$5875_Y - attribute \src "libresoc.v:142000.19-142000.112" - wire $eq$libresoc.v:142000$5885_Y - attribute \src "libresoc.v:142007.18-142007.111" - wire $eq$libresoc.v:142007$5892_Y - attribute \src "libresoc.v:142010.19-142010.110" - wire $eq$libresoc.v:142010$5895_Y - attribute \src "libresoc.v:142012.19-142012.110" - wire $eq$libresoc.v:142012$5897_Y - attribute \src "libresoc.v:142013.19-142013.110" - wire $eq$libresoc.v:142013$5898_Y - attribute \src "libresoc.v:142015.19-142015.110" - wire $eq$libresoc.v:142015$5900_Y - attribute \src "libresoc.v:142017.18-142017.111" - wire $eq$libresoc.v:142017$5902_Y - attribute \src "libresoc.v:142020.19-142020.116" - wire $eq$libresoc.v:142020$5906_Y - attribute \src "libresoc.v:142021.19-142021.116" - wire $eq$libresoc.v:142021$5907_Y - attribute \src "libresoc.v:142023.19-142023.116" - wire $eq$libresoc.v:142023$5909_Y - attribute \src "libresoc.v:142019.19-142019.106" - wire width 8 $extend$libresoc.v:142019$5904_Y - attribute \src "libresoc.v:141948.19-141948.109" - wire $ne$libresoc.v:141948$5833_Y - attribute \src "libresoc.v:141950.19-141950.109" - wire $ne$libresoc.v:141950$5835_Y - attribute \src "libresoc.v:141953.19-141953.109" - wire $ne$libresoc.v:141953$5838_Y - attribute \src "libresoc.v:141958.19-141958.120" - wire $ne$libresoc.v:141958$5843_Y - attribute \src "libresoc.v:141960.19-141960.120" - wire $ne$libresoc.v:141960$5845_Y - attribute \src "libresoc.v:141964.19-141964.120" - wire $ne$libresoc.v:141964$5849_Y - attribute \src "libresoc.v:141970.19-141970.120" - wire $ne$libresoc.v:141970$5855_Y - attribute \src "libresoc.v:141972.19-141972.120" - wire $ne$libresoc.v:141972$5857_Y - attribute \src "libresoc.v:141975.19-141975.120" - wire $ne$libresoc.v:141975$5860_Y - attribute \src "libresoc.v:141980.19-141980.117" - wire $ne$libresoc.v:141980$5865_Y - attribute \src "libresoc.v:141982.19-141982.117" - wire $ne$libresoc.v:141982$5867_Y - attribute \src "libresoc.v:141984.19-141984.117" - wire $ne$libresoc.v:141984$5869_Y - attribute \src "libresoc.v:141991.19-141991.117" - wire $ne$libresoc.v:141991$5876_Y - attribute \src "libresoc.v:141993.19-141993.117" - wire $ne$libresoc.v:141993$5878_Y - attribute \src "libresoc.v:141995.19-141995.117" - wire $ne$libresoc.v:141995$5880_Y - attribute \src "libresoc.v:142001.19-142001.109" - wire $ne$libresoc.v:142001$5886_Y - attribute \src "libresoc.v:142003.19-142003.109" - wire $ne$libresoc.v:142003$5888_Y - attribute \src "libresoc.v:142005.19-142005.109" - wire $ne$libresoc.v:142005$5890_Y - attribute \src "libresoc.v:141955.19-141955.110" - wire $not$libresoc.v:141955$5840_Y - attribute \src "libresoc.v:141966.19-141966.121" - wire $not$libresoc.v:141966$5851_Y - attribute \src "libresoc.v:141977.19-141977.121" - wire $not$libresoc.v:141977$5862_Y - attribute \src "libresoc.v:141987.19-141987.118" - wire $not$libresoc.v:141987$5872_Y - attribute \src "libresoc.v:141998.19-141998.118" - wire $not$libresoc.v:141998$5883_Y - attribute \src "libresoc.v:142008.19-142008.110" - wire $not$libresoc.v:142008$5893_Y - attribute \src "libresoc.v:142011.19-142011.100" - wire $not$libresoc.v:142011$5896_Y - attribute \src "libresoc.v:141829.18-141829.104" - wire $or$libresoc.v:141829$5714_Y - attribute \src "libresoc.v:141874.18-141874.104" - wire $or$libresoc.v:141874$5759_Y - attribute \src "libresoc.v:141896.18-141896.104" - wire $or$libresoc.v:141896$5781_Y - attribute \src "libresoc.v:141943.19-141943.107" - wire $or$libresoc.v:141943$5828_Y - attribute \src "libresoc.v:141945.19-141945.107" - wire $or$libresoc.v:141945$5830_Y - attribute \src "libresoc.v:141951.18-141951.104" - wire $or$libresoc.v:141951$5836_Y - attribute \src "libresoc.v:141974.18-141974.104" - wire $or$libresoc.v:141974$5859_Y - attribute \src "libresoc.v:142014.19-142014.107" - wire $or$libresoc.v:142014$5899_Y - attribute \src "libresoc.v:142022.19-142022.107" - wire $or$libresoc.v:142022$5908_Y - attribute \src "libresoc.v:142030.17-142030.101" - wire $or$libresoc.v:142030$5916_Y - attribute \src "libresoc.v:142019.19-142019.106" - wire width 8 $pos$libresoc.v:142019$5905_Y - attribute \src "libresoc.v:141797.18-141797.133" - wire $ternary$libresoc.v:141797$5682_Y - attribute \src "libresoc.v:141798.19-141798.133" - wire $ternary$libresoc.v:141798$5683_Y - attribute \src "libresoc.v:141799.19-141799.134" - wire $ternary$libresoc.v:141799$5684_Y - attribute \src "libresoc.v:141800.19-141800.133" - wire $ternary$libresoc.v:141800$5685_Y - attribute \src "libresoc.v:141801.19-141801.132" - wire $ternary$libresoc.v:141801$5686_Y - attribute \src "libresoc.v:141802.19-141802.133" - wire $ternary$libresoc.v:141802$5687_Y - attribute \src "libresoc.v:141803.19-141803.133" - wire $ternary$libresoc.v:141803$5688_Y - attribute \src "libresoc.v:141804.19-141804.132" - wire $ternary$libresoc.v:141804$5689_Y - attribute \src "libresoc.v:141805.19-141805.133" - wire $ternary$libresoc.v:141805$5690_Y - attribute \src "libresoc.v:141806.19-141806.133" - wire $ternary$libresoc.v:141806$5691_Y - attribute \src "libresoc.v:141808.19-141808.132" - wire $ternary$libresoc.v:141808$5693_Y - attribute \src "libresoc.v:141809.19-141809.133" - wire $ternary$libresoc.v:141809$5694_Y - attribute \src "libresoc.v:141810.19-141810.133" - wire $ternary$libresoc.v:141810$5695_Y - attribute \src "libresoc.v:141811.19-141811.132" - wire $ternary$libresoc.v:141811$5696_Y - attribute \src "libresoc.v:141812.19-141812.133" - wire $ternary$libresoc.v:141812$5697_Y - attribute \src "libresoc.v:141813.19-141813.133" - wire $ternary$libresoc.v:141813$5698_Y - attribute \src "libresoc.v:141814.19-141814.132" - wire $ternary$libresoc.v:141814$5699_Y - attribute \src "libresoc.v:141815.19-141815.133" - wire $ternary$libresoc.v:141815$5700_Y - attribute \src "libresoc.v:141816.19-141816.133" - wire $ternary$libresoc.v:141816$5701_Y - attribute \src "libresoc.v:141817.19-141817.132" - wire $ternary$libresoc.v:141817$5702_Y - attribute \src "libresoc.v:141819.19-141819.133" - wire $ternary$libresoc.v:141819$5704_Y - attribute \src "libresoc.v:141820.19-141820.133" - wire $ternary$libresoc.v:141820$5705_Y - attribute \src "libresoc.v:141821.19-141821.132" - wire $ternary$libresoc.v:141821$5706_Y - attribute \src "libresoc.v:141822.19-141822.133" - wire $ternary$libresoc.v:141822$5707_Y - attribute \src "libresoc.v:141823.19-141823.133" - wire $ternary$libresoc.v:141823$5708_Y - attribute \src "libresoc.v:141824.19-141824.132" - wire $ternary$libresoc.v:141824$5709_Y - attribute \src "libresoc.v:141825.19-141825.133" - wire $ternary$libresoc.v:141825$5710_Y - attribute \src "libresoc.v:141826.19-141826.134" - wire $ternary$libresoc.v:141826$5711_Y - attribute \src "libresoc.v:141827.19-141827.135" - wire $ternary$libresoc.v:141827$5712_Y - attribute \src "libresoc.v:141828.19-141828.135" - wire $ternary$libresoc.v:141828$5713_Y - attribute \src "libresoc.v:141830.19-141830.136" - wire $ternary$libresoc.v:141830$5715_Y - attribute \src "libresoc.v:141831.19-141831.134" - wire $ternary$libresoc.v:141831$5716_Y - attribute \src "libresoc.v:141832.19-141832.135" - wire $ternary$libresoc.v:141832$5717_Y - attribute \src "libresoc.v:141833.19-141833.135" - wire $ternary$libresoc.v:141833$5718_Y - attribute \src "libresoc.v:141834.19-141834.136" - wire $ternary$libresoc.v:141834$5719_Y - attribute \src "libresoc.v:141835.19-141835.134" - wire $ternary$libresoc.v:141835$5720_Y - attribute \src "libresoc.v:141836.19-141836.133" - wire $ternary$libresoc.v:141836$5721_Y - attribute \src "libresoc.v:141837.19-141837.134" - wire $ternary$libresoc.v:141837$5722_Y - attribute \src "libresoc.v:141838.19-141838.133" - wire $ternary$libresoc.v:141838$5723_Y - attribute \src "libresoc.v:141839.19-141839.130" - wire $ternary$libresoc.v:141839$5724_Y - attribute \src "libresoc.v:141841.19-141841.130" - wire $ternary$libresoc.v:141841$5726_Y - attribute \src "libresoc.v:141842.19-141842.133" - wire $ternary$libresoc.v:141842$5727_Y - attribute \src "libresoc.v:141843.19-141843.132" - wire $ternary$libresoc.v:141843$5728_Y - attribute \src "libresoc.v:141844.19-141844.133" - wire $ternary$libresoc.v:141844$5729_Y - attribute \src "libresoc.v:141845.19-141845.132" - wire $ternary$libresoc.v:141845$5730_Y - attribute \src "libresoc.v:141846.19-141846.135" - wire $ternary$libresoc.v:141846$5731_Y - attribute \src "libresoc.v:141847.19-141847.134" - wire $ternary$libresoc.v:141847$5732_Y - attribute \src "libresoc.v:141848.19-141848.135" - wire $ternary$libresoc.v:141848$5733_Y - attribute \src "libresoc.v:141849.19-141849.135" - wire $ternary$libresoc.v:141849$5734_Y - attribute \src "libresoc.v:141850.19-141850.134" - wire $ternary$libresoc.v:141850$5735_Y - attribute \src "libresoc.v:141853.19-141853.135" - wire $ternary$libresoc.v:141853$5738_Y - attribute \src "libresoc.v:141854.19-141854.135" - wire $ternary$libresoc.v:141854$5739_Y - attribute \src "libresoc.v:141855.19-141855.134" - wire $ternary$libresoc.v:141855$5740_Y - attribute \src "libresoc.v:141856.19-141856.135" - wire $ternary$libresoc.v:141856$5741_Y - attribute \src "libresoc.v:141857.19-141857.135" - wire $ternary$libresoc.v:141857$5742_Y - attribute \src "libresoc.v:141858.19-141858.134" - wire $ternary$libresoc.v:141858$5743_Y - attribute \src "libresoc.v:141859.19-141859.135" - wire $ternary$libresoc.v:141859$5744_Y - attribute \src "libresoc.v:141860.19-141860.133" - wire $ternary$libresoc.v:141860$5745_Y - attribute \src "libresoc.v:141861.19-141861.134" - wire $ternary$libresoc.v:141861$5746_Y - attribute \src "libresoc.v:141862.19-141862.133" - wire $ternary$libresoc.v:141862$5747_Y - attribute \src "libresoc.v:141864.19-141864.134" - wire $ternary$libresoc.v:141864$5749_Y - attribute \src "libresoc.v:141865.19-141865.134" - wire $ternary$libresoc.v:141865$5750_Y - attribute \src "libresoc.v:141866.19-141866.133" - wire $ternary$libresoc.v:141866$5751_Y - attribute \src "libresoc.v:141867.19-141867.134" - wire $ternary$libresoc.v:141867$5752_Y - attribute \src "libresoc.v:141868.19-141868.134" - wire $ternary$libresoc.v:141868$5753_Y - attribute \src "libresoc.v:141869.19-141869.133" - wire $ternary$libresoc.v:141869$5754_Y - attribute \src "libresoc.v:141870.19-141870.134" - wire $ternary$libresoc.v:141870$5755_Y - attribute \src "libresoc.v:141871.19-141871.134" - wire $ternary$libresoc.v:141871$5756_Y - attribute \src "libresoc.v:141872.19-141872.133" - wire $ternary$libresoc.v:141872$5757_Y - attribute \src "libresoc.v:141873.19-141873.134" - wire $ternary$libresoc.v:141873$5758_Y - attribute \src "libresoc.v:141875.19-141875.134" - wire $ternary$libresoc.v:141875$5760_Y - attribute \src "libresoc.v:141876.19-141876.133" - wire $ternary$libresoc.v:141876$5761_Y - attribute \src "libresoc.v:141877.19-141877.134" - wire $ternary$libresoc.v:141877$5762_Y - attribute \src "libresoc.v:141878.19-141878.134" - wire $ternary$libresoc.v:141878$5763_Y - attribute \src "libresoc.v:141879.19-141879.133" - wire $ternary$libresoc.v:141879$5764_Y - attribute \src "libresoc.v:141880.19-141880.134" - wire $ternary$libresoc.v:141880$5765_Y - attribute \src "libresoc.v:141881.19-141881.135" - wire $ternary$libresoc.v:141881$5766_Y - attribute \src "libresoc.v:141882.19-141882.134" - wire $ternary$libresoc.v:141882$5767_Y - attribute \src "libresoc.v:141883.19-141883.135" - wire $ternary$libresoc.v:141883$5768_Y - attribute \src "libresoc.v:141884.19-141884.135" - wire $ternary$libresoc.v:141884$5769_Y - attribute \src "libresoc.v:141886.19-141886.134" - wire $ternary$libresoc.v:141886$5771_Y - attribute \src "libresoc.v:141887.19-141887.135" - wire $ternary$libresoc.v:141887$5772_Y - attribute \src "libresoc.v:141888.19-141888.133" - wire $ternary$libresoc.v:141888$5773_Y - attribute \src "libresoc.v:141889.19-141889.133" - wire $ternary$libresoc.v:141889$5774_Y - attribute \src "libresoc.v:141890.19-141890.133" - wire $ternary$libresoc.v:141890$5775_Y - attribute \src "libresoc.v:141891.19-141891.133" - wire $ternary$libresoc.v:141891$5776_Y - attribute \src "libresoc.v:141892.19-141892.133" - wire $ternary$libresoc.v:141892$5777_Y - attribute \src "libresoc.v:141893.19-141893.133" - wire $ternary$libresoc.v:141893$5778_Y - attribute \src "libresoc.v:141894.19-141894.133" - wire $ternary$libresoc.v:141894$5779_Y - attribute \src "libresoc.v:141895.19-141895.133" - wire $ternary$libresoc.v:141895$5780_Y - attribute \src "libresoc.v:141897.19-141897.133" - wire $ternary$libresoc.v:141897$5782_Y - attribute \src "libresoc.v:141898.19-141898.133" - wire $ternary$libresoc.v:141898$5783_Y - attribute \src "libresoc.v:141899.19-141899.134" - wire $ternary$libresoc.v:141899$5784_Y - attribute \src "libresoc.v:141900.19-141900.134" - wire $ternary$libresoc.v:141900$5785_Y - attribute \src "libresoc.v:141901.19-141901.135" - wire $ternary$libresoc.v:141901$5786_Y - attribute \src "libresoc.v:141902.19-141902.133" - wire $ternary$libresoc.v:141902$5787_Y - attribute \src "libresoc.v:141903.19-141903.135" - wire $ternary$libresoc.v:141903$5788_Y - attribute \src "libresoc.v:141904.19-141904.135" - wire $ternary$libresoc.v:141904$5789_Y - attribute \src "libresoc.v:141905.19-141905.134" - wire $ternary$libresoc.v:141905$5790_Y - attribute \src "libresoc.v:141906.19-141906.134" - wire $ternary$libresoc.v:141906$5791_Y - attribute \src "libresoc.v:141908.19-141908.134" - wire $ternary$libresoc.v:141908$5793_Y - attribute \src "libresoc.v:141909.19-141909.134" - wire $ternary$libresoc.v:141909$5794_Y - attribute \src "libresoc.v:141910.19-141910.134" - wire $ternary$libresoc.v:141910$5795_Y - attribute \src "libresoc.v:141911.19-141911.135" - wire $ternary$libresoc.v:141911$5796_Y - attribute \src "libresoc.v:141912.19-141912.134" - wire $ternary$libresoc.v:141912$5797_Y - attribute \src "libresoc.v:141913.19-141913.135" - wire $ternary$libresoc.v:141913$5798_Y - attribute \src "libresoc.v:141914.19-141914.135" - wire $ternary$libresoc.v:141914$5799_Y - attribute \src "libresoc.v:141915.19-141915.134" - wire $ternary$libresoc.v:141915$5800_Y - attribute \src "libresoc.v:141916.19-141916.135" - wire $ternary$libresoc.v:141916$5801_Y - attribute \src "libresoc.v:141917.19-141917.135" - wire $ternary$libresoc.v:141917$5802_Y - attribute \src "libresoc.v:141919.19-141919.134" - wire $ternary$libresoc.v:141919$5804_Y - attribute \src "libresoc.v:141920.19-141920.135" - wire $ternary$libresoc.v:141920$5805_Y - attribute \src "libresoc.v:141921.19-141921.136" - wire $ternary$libresoc.v:141921$5806_Y - attribute \src "libresoc.v:141922.19-141922.135" - wire $ternary$libresoc.v:141922$5807_Y - attribute \src "libresoc.v:141923.19-141923.136" - wire $ternary$libresoc.v:141923$5808_Y - attribute \src "libresoc.v:141924.19-141924.136" - wire $ternary$libresoc.v:141924$5809_Y - attribute \src "libresoc.v:141925.19-141925.135" - wire $ternary$libresoc.v:141925$5810_Y - attribute \src "libresoc.v:141926.19-141926.136" - wire $ternary$libresoc.v:141926$5811_Y - attribute \src "libresoc.v:141927.19-141927.136" - wire $ternary$libresoc.v:141927$5812_Y - attribute \src "libresoc.v:141928.19-141928.135" - wire $ternary$libresoc.v:141928$5813_Y - attribute \src "libresoc.v:141930.19-141930.136" - wire $ternary$libresoc.v:141930$5815_Y - attribute \src "libresoc.v:141931.19-141931.136" - wire $ternary$libresoc.v:141931$5816_Y - attribute \src "libresoc.v:141932.19-141932.135" - wire $ternary$libresoc.v:141932$5817_Y - attribute \src "libresoc.v:141933.19-141933.136" - wire $ternary$libresoc.v:141933$5818_Y - attribute \src "libresoc.v:141934.19-141934.136" - wire $ternary$libresoc.v:141934$5819_Y - attribute \src "libresoc.v:141935.19-141935.135" - wire $ternary$libresoc.v:141935$5820_Y - attribute \src "libresoc.v:141936.19-141936.136" - wire $ternary$libresoc.v:141936$5821_Y - attribute \src "libresoc.v:141937.19-141937.136" - wire $ternary$libresoc.v:141937$5822_Y - attribute \src "libresoc.v:141938.19-141938.135" - wire $ternary$libresoc.v:141938$5823_Y - attribute \src "libresoc.v:141939.19-141939.136" - wire $ternary$libresoc.v:141939$5824_Y - attribute \src "libresoc.v:142026.18-142026.130" - wire $ternary$libresoc.v:142026$5912_Y - attribute \src "libresoc.v:142027.18-142027.130" - wire $ternary$libresoc.v:142027$5913_Y - attribute \src "libresoc.v:142028.18-142028.130" - wire $ternary$libresoc.v:142028$5914_Y - attribute \src "libresoc.v:142029.18-142029.131" - wire $ternary$libresoc.v:142029$5915_Y - attribute \src "libresoc.v:142031.18-142031.130" - wire $ternary$libresoc.v:142031$5917_Y - attribute \src "libresoc.v:142032.18-142032.131" - wire $ternary$libresoc.v:142032$5918_Y - attribute \src "libresoc.v:142033.18-142033.131" - wire $ternary$libresoc.v:142033$5919_Y - attribute \src "libresoc.v:142034.18-142034.130" - wire $ternary$libresoc.v:142034$5920_Y - attribute \src "libresoc.v:142035.18-142035.131" - wire $ternary$libresoc.v:142035$5921_Y - attribute \src "libresoc.v:142036.18-142036.132" - wire $ternary$libresoc.v:142036$5922_Y - attribute \src "libresoc.v:142037.18-142037.132" - wire $ternary$libresoc.v:142037$5923_Y - attribute \src "libresoc.v:142038.18-142038.133" - wire $ternary$libresoc.v:142038$5924_Y - attribute \src "libresoc.v:142039.18-142039.133" - wire $ternary$libresoc.v:142039$5925_Y - attribute \src "libresoc.v:142040.18-142040.132" - wire $ternary$libresoc.v:142040$5926_Y - attribute \src "libresoc.v:142042.18-142042.133" - wire $ternary$libresoc.v:142042$5928_Y - attribute \src "libresoc.v:142043.18-142043.133" - wire $ternary$libresoc.v:142043$5929_Y - attribute \src "libresoc.v:142044.18-142044.132" - wire $ternary$libresoc.v:142044$5930_Y - attribute \src "libresoc.v:142045.18-142045.133" - wire $ternary$libresoc.v:142045$5931_Y - attribute \src "libresoc.v:142046.18-142046.133" - wire $ternary$libresoc.v:142046$5932_Y - attribute \src "libresoc.v:142047.18-142047.132" - wire $ternary$libresoc.v:142047$5933_Y - attribute \src "libresoc.v:142048.18-142048.133" - wire $ternary$libresoc.v:142048$5934_Y - attribute \src "libresoc.v:142049.18-142049.133" - wire $ternary$libresoc.v:142049$5935_Y - attribute \src "libresoc.v:142050.18-142050.132" - wire $ternary$libresoc.v:142050$5936_Y - attribute \src "libresoc.v:142051.18-142051.133" - wire $ternary$libresoc.v:142051$5937_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$101 + cell $mux $ternary$libresoc.v:137459$5669 + parameter \WIDTH 1 + connect \A \gpio_s1__core__o + connect \B \io_bd [31] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137459$5669_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$103 + cell $mux $ternary$libresoc.v:137460$5670 + parameter \WIDTH 1 + connect \A \gpio_s1__core__oe + connect \B \io_bd [32] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137460$5670_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$105 + cell $mux $ternary$libresoc.v:137461$5671 + parameter \WIDTH 1 + connect \A \gpio_s2__pad__i + connect \B \io_bd [33] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137461$5671_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$107 + cell $mux $ternary$libresoc.v:137463$5673 + parameter \WIDTH 1 + connect \A \gpio_s2__core__o + connect \B \io_bd [34] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137463$5673_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$11 + cell $mux $ternary$libresoc.v:137464$5674 + parameter \WIDTH 1 + connect \A \gpio_s2__core__oe + connect \B \io_bd [35] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137464$5674_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$111 + cell $mux $ternary$libresoc.v:137465$5675 + parameter \WIDTH 1 + connect \A \gpio_s3__pad__i + connect \B \io_bd [36] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137465$5675_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$113 + cell $mux $ternary$libresoc.v:137466$5676 + parameter \WIDTH 1 + connect \A \gpio_s3__core__o + connect \B \io_bd [37] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137466$5676_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$115 + cell $mux $ternary$libresoc.v:137467$5677 + parameter \WIDTH 1 + connect \A \gpio_s3__core__oe + connect \B \io_bd [38] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137467$5677_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$117 + cell $mux $ternary$libresoc.v:137468$5678 + parameter \WIDTH 1 + connect \A \gpio_s4__pad__i + connect \B \io_bd [39] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137468$5678_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$119 + cell $mux $ternary$libresoc.v:137469$5679 + parameter \WIDTH 1 + connect \A \gpio_s4__core__o + connect \B \io_bd [40] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137469$5679_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$121 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$123 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$125 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$127 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$129 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$131 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$133 + cell $mux $ternary$libresoc.v:137470$5680 + parameter \WIDTH 1 + connect \A \gpio_s4__core__oe + connect \B \io_bd [41] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137470$5680_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$135 + cell $mux $ternary$libresoc.v:137471$5681 + parameter \WIDTH 1 + connect \A \gpio_s5__pad__i + connect \B \io_bd [42] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137471$5681_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$137 + cell $mux $ternary$libresoc.v:137472$5682 + parameter \WIDTH 1 + connect \A \gpio_s5__core__o + connect \B \io_bd [43] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137472$5682_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$139 + cell $mux $ternary$libresoc.v:137474$5684 + parameter \WIDTH 1 + connect \A \gpio_s5__core__oe + connect \B \io_bd [44] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137474$5684_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$141 + cell $mux $ternary$libresoc.v:137475$5685 + parameter \WIDTH 1 + connect \A \gpio_s6__pad__i + connect \B \io_bd [45] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137475$5685_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$143 + cell $mux $ternary$libresoc.v:137476$5686 + parameter \WIDTH 1 + connect \A \gpio_s6__core__o + connect \B \io_bd [46] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137476$5686_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$145 + cell $mux $ternary$libresoc.v:137477$5687 + parameter \WIDTH 1 + connect \A \gpio_s6__core__oe + connect \B \io_bd [47] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137477$5687_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$147 + cell $mux $ternary$libresoc.v:137478$5688 + parameter \WIDTH 1 + connect \A \gpio_s7__pad__i + connect \B \io_bd [48] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137478$5688_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$149 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$15 + cell $mux $ternary$libresoc.v:137479$5689 + parameter \WIDTH 1 + connect \A \gpio_s7__core__o + connect \B \io_bd [49] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137479$5689_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$151 + cell $mux $ternary$libresoc.v:137480$5690 + parameter \WIDTH 1 + connect \A \gpio_s7__core__oe + connect \B \io_bd [50] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137480$5690_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$153 + cell $mux $ternary$libresoc.v:137481$5691 + parameter \WIDTH 1 + connect \A \mspi0_clk__core__o + connect \B \io_bd [51] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137481$5691_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$155 + cell $mux $ternary$libresoc.v:137482$5692 + parameter \WIDTH 1 + connect \A \mspi0_cs_n__core__o + connect \B \io_bd [52] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137482$5692_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$157 + cell $mux $ternary$libresoc.v:137483$5693 + parameter \WIDTH 1 + connect \A \mspi0_mosi__core__o + connect \B \io_bd [53] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137483$5693_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$159 + cell $mux $ternary$libresoc.v:137485$5695 + parameter \WIDTH 1 + connect \A \mspi0_miso__pad__i + connect \B \io_bd [54] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137485$5695_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$161 + cell $mux $ternary$libresoc.v:137486$5696 + parameter \WIDTH 1 + connect \A \mspi1_clk__core__o + connect \B \io_bd [55] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137486$5696_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$163 + cell $mux $ternary$libresoc.v:137487$5697 + parameter \WIDTH 1 + connect \A \mspi1_cs_n__core__o + connect \B \io_bd [56] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137487$5697_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$165 + cell $mux $ternary$libresoc.v:137488$5698 + parameter \WIDTH 1 + connect \A \mspi1_mosi__core__o + connect \B \io_bd [57] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137488$5698_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$167 + cell $mux $ternary$libresoc.v:137489$5699 + parameter \WIDTH 1 + connect \A \mspi1_miso__pad__i + connect \B \io_bd [58] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137489$5699_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$169 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - wire \$17 + cell $mux $ternary$libresoc.v:137490$5700 + parameter \WIDTH 1 + connect \A \mtwi_sda__pad__i + connect \B \io_bd [59] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137490$5700_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$171 + cell $mux $ternary$libresoc.v:137491$5701 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__o + connect \B \io_bd [60] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137491$5701_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$173 + cell $mux $ternary$libresoc.v:137492$5702 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__oe + connect \B \io_bd [61] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137492$5702_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$175 + cell $mux $ternary$libresoc.v:137493$5703 + parameter \WIDTH 1 + connect \A \mtwi_scl__core__o + connect \B \io_bd [62] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137493$5703_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$177 + cell $mux $ternary$libresoc.v:137494$5704 + parameter \WIDTH 1 + connect \A \pwm_0__core__o + connect \B \io_bd [63] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137494$5704_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$179 + cell $mux $ternary$libresoc.v:137496$5706 + parameter \WIDTH 1 + connect \A \pwm_1__core__o + connect \B \io_bd [64] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137496$5706_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$181 + cell $mux $ternary$libresoc.v:137497$5707 + parameter \WIDTH 1 + connect \A \sd0_cmd__pad__i + connect \B \io_bd [65] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137497$5707_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$183 + cell $mux $ternary$libresoc.v:137498$5708 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__o + connect \B \io_bd [66] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137498$5708_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$185 + cell $mux $ternary$libresoc.v:137499$5709 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__oe + connect \B \io_bd [67] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137499$5709_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$187 + cell $mux $ternary$libresoc.v:137500$5710 + parameter \WIDTH 1 + connect \A \sd0_clk__core__o + connect \B \io_bd [68] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137500$5710_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$189 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$19 + cell $mux $ternary$libresoc.v:137501$5711 + parameter \WIDTH 1 + connect \A \sd0_data0__pad__i + connect \B \io_bd [69] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137501$5711_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$191 + cell $mux $ternary$libresoc.v:137502$5712 + parameter \WIDTH 1 + connect \A \sd0_data0__core__o + connect \B \io_bd [70] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137502$5712_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$193 + cell $mux $ternary$libresoc.v:137503$5713 + parameter \WIDTH 1 + connect \A \sd0_data0__core__oe + connect \B \io_bd [71] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137503$5713_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$195 + cell $mux $ternary$libresoc.v:137504$5714 + parameter \WIDTH 1 + connect \A \sd0_data1__pad__i + connect \B \io_bd [72] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137504$5714_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$197 + cell $mux $ternary$libresoc.v:137505$5715 + parameter \WIDTH 1 + connect \A \sd0_data1__core__o + connect \B \io_bd [73] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137505$5715_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$199 + cell $mux $ternary$libresoc.v:137508$5718 + parameter \WIDTH 1 + connect \A \sd0_data1__core__oe + connect \B \io_bd [74] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137508$5718_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$201 + cell $mux $ternary$libresoc.v:137509$5719 + parameter \WIDTH 1 + connect \A \sd0_data2__pad__i + connect \B \io_bd [75] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137509$5719_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$203 + cell $mux $ternary$libresoc.v:137510$5720 + parameter \WIDTH 1 + connect \A \sd0_data2__core__o + connect \B \io_bd [76] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137510$5720_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$205 + cell $mux $ternary$libresoc.v:137511$5721 + parameter \WIDTH 1 + connect \A \sd0_data2__core__oe + connect \B \io_bd [77] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137511$5721_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$207 + cell $mux $ternary$libresoc.v:137512$5722 + parameter \WIDTH 1 + connect \A \sd0_data3__pad__i + connect \B \io_bd [78] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137512$5722_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$209 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$21 + cell $mux $ternary$libresoc.v:137513$5723 + parameter \WIDTH 1 + connect \A \sd0_data3__core__o + connect \B \io_bd [79] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137513$5723_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$211 + cell $mux $ternary$libresoc.v:137514$5724 + parameter \WIDTH 1 + connect \A \sd0_data3__core__oe + connect \B \io_bd [80] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137514$5724_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$213 + cell $mux $ternary$libresoc.v:137515$5725 + parameter \WIDTH 1 + connect \A \sdr_dm_0__core__o + connect \B \io_bd [81] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137515$5725_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$215 + cell $mux $ternary$libresoc.v:137516$5726 + parameter \WIDTH 1 + connect \A \sdr_dq_0__pad__i + connect \B \io_bd [82] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137516$5726_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$217 + cell $mux $ternary$libresoc.v:137517$5727 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__o + connect \B \io_bd [83] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137517$5727_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$219 + cell $mux $ternary$libresoc.v:137519$5729 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__oe + connect \B \io_bd [84] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137519$5729_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$221 + cell $mux $ternary$libresoc.v:137520$5730 + parameter \WIDTH 1 + connect \A \sdr_dq_1__pad__i + connect \B \io_bd [85] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137520$5730_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$223 + cell $mux $ternary$libresoc.v:137521$5731 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__o + connect \B \io_bd [86] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137521$5731_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$225 + cell $mux $ternary$libresoc.v:137522$5732 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__oe + connect \B \io_bd [87] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137522$5732_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$227 + cell $mux $ternary$libresoc.v:137523$5733 + parameter \WIDTH 1 + connect \A \sdr_dq_2__pad__i + connect \B \io_bd [88] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137523$5733_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$229 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$23 + cell $mux $ternary$libresoc.v:137524$5734 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__o + connect \B \io_bd [89] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137524$5734_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$231 + cell $mux $ternary$libresoc.v:137525$5735 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__oe + connect \B \io_bd [90] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137525$5735_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$233 + cell $mux $ternary$libresoc.v:137526$5736 + parameter \WIDTH 1 + connect \A \sdr_dq_3__pad__i + connect \B \io_bd [91] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137526$5736_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$235 + cell $mux $ternary$libresoc.v:137527$5737 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__o + connect \B \io_bd [92] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137527$5737_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$237 + cell $mux $ternary$libresoc.v:137528$5738 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__oe + connect \B \io_bd [93] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137528$5738_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$239 + cell $mux $ternary$libresoc.v:137530$5740 + parameter \WIDTH 1 + connect \A \sdr_dq_4__pad__i + connect \B \io_bd [94] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137530$5740_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$241 + cell $mux $ternary$libresoc.v:137531$5741 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__o + connect \B \io_bd [95] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137531$5741_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$243 + cell $mux $ternary$libresoc.v:137532$5742 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__oe + connect \B \io_bd [96] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137532$5742_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$245 + cell $mux $ternary$libresoc.v:137533$5743 + parameter \WIDTH 1 + connect \A \sdr_dq_5__pad__i + connect \B \io_bd [97] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137533$5743_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$247 + cell $mux $ternary$libresoc.v:137534$5744 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__o + connect \B \io_bd [98] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137534$5744_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$249 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - wire \$25 + cell $mux $ternary$libresoc.v:137535$5745 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__oe + connect \B \io_bd [99] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137535$5745_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$251 + cell $mux $ternary$libresoc.v:137536$5746 + parameter \WIDTH 1 + connect \A \sdr_dq_6__pad__i + connect \B \io_bd [100] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137536$5746_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$253 + cell $mux $ternary$libresoc.v:137537$5747 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__o + connect \B \io_bd [101] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137537$5747_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$255 + cell $mux $ternary$libresoc.v:137538$5748 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__oe + connect \B \io_bd [102] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137538$5748_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$257 + cell $mux $ternary$libresoc.v:137539$5749 + parameter \WIDTH 1 + connect \A \sdr_dq_7__pad__i + connect \B \io_bd [103] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137539$5749_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$259 + cell $mux $ternary$libresoc.v:137541$5751 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__o + connect \B \io_bd [104] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137541$5751_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$261 + cell $mux $ternary$libresoc.v:137542$5752 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__oe + connect \B \io_bd [105] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137542$5752_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$263 + cell $mux $ternary$libresoc.v:137543$5753 + parameter \WIDTH 1 + connect \A \sdr_a_0__core__o + connect \B \io_bd [106] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137543$5753_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$265 + cell $mux $ternary$libresoc.v:137544$5754 + parameter \WIDTH 1 + connect \A \sdr_a_1__core__o + connect \B \io_bd [107] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137544$5754_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$267 + cell $mux $ternary$libresoc.v:137545$5755 + parameter \WIDTH 1 + connect \A \sdr_a_2__core__o + connect \B \io_bd [108] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137545$5755_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$269 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$27 + cell $mux $ternary$libresoc.v:137546$5756 + parameter \WIDTH 1 + connect \A \sdr_a_3__core__o + connect \B \io_bd [109] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137546$5756_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$271 + cell $mux $ternary$libresoc.v:137547$5757 + parameter \WIDTH 1 + connect \A \sdr_a_4__core__o + connect \B \io_bd [110] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137547$5757_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$273 + cell $mux $ternary$libresoc.v:137548$5758 + parameter \WIDTH 1 + connect \A \sdr_a_5__core__o + connect \B \io_bd [111] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137548$5758_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$275 + cell $mux $ternary$libresoc.v:137549$5759 + parameter \WIDTH 1 + connect \A \sdr_a_6__core__o + connect \B \io_bd [112] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137549$5759_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$277 + cell $mux $ternary$libresoc.v:137550$5760 + parameter \WIDTH 1 + connect \A \sdr_a_7__core__o + connect \B \io_bd [113] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137550$5760_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$279 + cell $mux $ternary$libresoc.v:137552$5762 + parameter \WIDTH 1 + connect \A \sdr_a_8__core__o + connect \B \io_bd [114] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137552$5762_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$281 + cell $mux $ternary$libresoc.v:137553$5763 + parameter \WIDTH 1 + connect \A \sdr_a_9__core__o + connect \B \io_bd [115] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137553$5763_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$283 + cell $mux $ternary$libresoc.v:137554$5764 + parameter \WIDTH 1 + connect \A \sdr_ba_0__core__o + connect \B \io_bd [116] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137554$5764_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$285 + cell $mux $ternary$libresoc.v:137555$5765 + parameter \WIDTH 1 + connect \A \sdr_ba_1__core__o + connect \B \io_bd [117] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137555$5765_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$287 + cell $mux $ternary$libresoc.v:137556$5766 + parameter \WIDTH 1 + connect \A \sdr_clock__core__o + connect \B \io_bd [118] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137556$5766_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$289 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$29 + cell $mux $ternary$libresoc.v:137557$5767 + parameter \WIDTH 1 + connect \A \sdr_cke__core__o + connect \B \io_bd [119] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137557$5767_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$291 + cell $mux $ternary$libresoc.v:137558$5768 + parameter \WIDTH 1 + connect \A \sdr_ras_n__core__o + connect \B \io_bd [120] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137558$5768_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$293 + cell $mux $ternary$libresoc.v:137559$5769 + parameter \WIDTH 1 + connect \A \sdr_cas_n__core__o + connect \B \io_bd [121] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137559$5769_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$295 + cell $mux $ternary$libresoc.v:137560$5770 + parameter \WIDTH 1 + connect \A \sdr_we_n__core__o + connect \B \io_bd [122] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137560$5770_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$297 + cell $mux $ternary$libresoc.v:137561$5771 + parameter \WIDTH 1 + connect \A \sdr_cs_n__core__o + connect \B \io_bd [123] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137561$5771_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$299 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \$3 + cell $mux $ternary$libresoc.v:137563$5773 + parameter \WIDTH 1 + connect \A \sdr_a_10__core__o + connect \B \io_bd [124] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137563$5773_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$301 + cell $mux $ternary$libresoc.v:137564$5774 + parameter \WIDTH 1 + connect \A \sdr_a_11__core__o + connect \B \io_bd [125] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137564$5774_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$303 + cell $mux $ternary$libresoc.v:137565$5775 + parameter \WIDTH 1 + connect \A \sdr_a_12__core__o + connect \B \io_bd [126] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137565$5775_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$305 + cell $mux $ternary$libresoc.v:137566$5776 + parameter \WIDTH 1 + connect \A \sdr_dm_1__pad__i + connect \B \io_bd [127] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137566$5776_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$307 + cell $mux $ternary$libresoc.v:137567$5777 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__o + connect \B \io_bd [128] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137567$5777_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$309 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - wire \$31 + cell $mux $ternary$libresoc.v:137568$5778 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__oe + connect \B \io_bd [129] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137568$5778_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$311 + cell $mux $ternary$libresoc.v:137569$5779 + parameter \WIDTH 1 + connect \A \sdr_dq_8__pad__i + connect \B \io_bd [130] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137569$5779_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$313 + cell $mux $ternary$libresoc.v:137570$5780 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__o + connect \B \io_bd [131] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137570$5780_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$315 + cell $mux $ternary$libresoc.v:137571$5781 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__oe + connect \B \io_bd [132] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137571$5781_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$317 + cell $mux $ternary$libresoc.v:137572$5782 + parameter \WIDTH 1 + connect \A \sdr_dq_9__pad__i + connect \B \io_bd [133] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137572$5782_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$319 + cell $mux $ternary$libresoc.v:137574$5784 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__o + connect \B \io_bd [134] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137574$5784_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$321 + cell $mux $ternary$libresoc.v:137575$5785 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__oe + connect \B \io_bd [135] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137575$5785_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$323 + cell $mux $ternary$libresoc.v:137576$5786 + parameter \WIDTH 1 + connect \A \sdr_dq_10__pad__i + connect \B \io_bd [136] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137576$5786_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$325 + cell $mux $ternary$libresoc.v:137577$5787 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__o + connect \B \io_bd [137] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137577$5787_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$327 + cell $mux $ternary$libresoc.v:137578$5788 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__oe + connect \B \io_bd [138] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137578$5788_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$329 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$33 + cell $mux $ternary$libresoc.v:137579$5789 + parameter \WIDTH 1 + connect \A \sdr_dq_11__pad__i + connect \B \io_bd [139] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137579$5789_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$331 + cell $mux $ternary$libresoc.v:137580$5790 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__o + connect \B \io_bd [140] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137580$5790_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$333 + cell $mux $ternary$libresoc.v:137581$5791 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__oe + connect \B \io_bd [141] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137581$5791_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$335 + cell $mux $ternary$libresoc.v:137582$5792 + parameter \WIDTH 1 + connect \A \sdr_dq_12__pad__i + connect \B \io_bd [142] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137582$5792_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$337 + cell $mux $ternary$libresoc.v:137583$5793 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__o + connect \B \io_bd [143] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137583$5793_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$339 + cell $mux $ternary$libresoc.v:137585$5795 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__oe + connect \B \io_bd [144] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137585$5795_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$341 + cell $mux $ternary$libresoc.v:137586$5796 + parameter \WIDTH 1 + connect \A \sdr_dq_13__pad__i + connect \B \io_bd [145] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137586$5796_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$343 + cell $mux $ternary$libresoc.v:137587$5797 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__o + connect \B \io_bd [146] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137587$5797_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$345 + cell $mux $ternary$libresoc.v:137588$5798 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__oe + connect \B \io_bd [147] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137588$5798_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$347 + cell $mux $ternary$libresoc.v:137589$5799 + parameter \WIDTH 1 + connect \A \sdr_dq_14__pad__i + connect \B \io_bd [148] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137589$5799_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$349 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$35 + cell $mux $ternary$libresoc.v:137590$5800 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__o + connect \B \io_bd [149] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137590$5800_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$351 + cell $mux $ternary$libresoc.v:137591$5801 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__oe + connect \B \io_bd [150] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137591$5801_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$353 + cell $mux $ternary$libresoc.v:137592$5802 + parameter \WIDTH 1 + connect \A \sdr_dq_15__pad__i + connect \B \io_bd [151] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137592$5802_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$355 + cell $mux $ternary$libresoc.v:137593$5803 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__o + connect \B \io_bd [152] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137593$5803_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$357 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$359 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$361 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$363 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - wire \$365 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$367 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$369 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$371 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$373 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$375 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$377 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$379 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$381 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$383 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$385 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$387 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$389 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$391 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$393 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$395 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$397 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$399 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$401 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$403 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$405 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$407 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$409 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$411 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$413 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$415 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$417 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$419 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$421 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$423 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$425 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$427 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$429 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$431 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$433 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$435 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$437 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$439 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$441 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$443 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$445 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$447 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$449 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$451 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$453 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$455 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$457 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$459 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$461 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$463 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$465 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$467 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$469 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$471 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$473 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$475 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$477 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$479 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$481 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$483 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$484 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$487 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$489 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$491 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - wire \$493 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$495 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$496 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$498 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$499 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 8 \$501 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$504 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$506 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$508 + cell $mux $ternary$libresoc.v:137594$5804 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__oe + connect \B \io_bd [153] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137594$5804_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - wire \$510 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$512 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$513 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$515 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$516 + cell $mux $ternary$libresoc.v:137681$5892 + parameter \WIDTH 1 + connect \A \eint_0__pad__i + connect \B \io_bd [0] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137681$5892_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$53 + cell $mux $ternary$libresoc.v:137682$5893 + parameter \WIDTH 1 + connect \A \eint_1__pad__i + connect \B \io_bd [1] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137682$5893_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$55 + cell $mux $ternary$libresoc.v:137683$5894 + parameter \WIDTH 1 + connect \A \eint_2__pad__i + connect \B \io_bd [2] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137683$5894_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$57 + cell $mux $ternary$libresoc.v:137684$5895 + parameter \WIDTH 1 + connect \A \gpio_e8__pad__i + connect \B \io_bd [3] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137684$5895_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$59 + cell $mux $ternary$libresoc.v:137686$5897 + parameter \WIDTH 1 + connect \A \gpio_e8__core__o + connect \B \io_bd [4] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137686$5897_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$61 + cell $mux $ternary$libresoc.v:137687$5898 + parameter \WIDTH 1 + connect \A \gpio_e8__core__oe + connect \B \io_bd [5] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137687$5898_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$63 + cell $mux $ternary$libresoc.v:137688$5899 + parameter \WIDTH 1 + connect \A \gpio_e9__pad__i + connect \B \io_bd [6] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137688$5899_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$65 + cell $mux $ternary$libresoc.v:137689$5900 + parameter \WIDTH 1 + connect \A \gpio_e9__core__o + connect \B \io_bd [7] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137689$5900_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$67 + cell $mux $ternary$libresoc.v:137690$5901 + parameter \WIDTH 1 + connect \A \gpio_e9__core__oe + connect \B \io_bd [8] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137690$5901_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \$7 + cell $mux $ternary$libresoc.v:137691$5902 + parameter \WIDTH 1 + connect \A \gpio_e10__pad__i + connect \B \io_bd [9] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137691$5902_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$71 + cell $mux $ternary$libresoc.v:137692$5903 + parameter \WIDTH 1 + connect \A \gpio_e10__core__o + connect \B \io_bd [10] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137692$5903_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$73 + cell $mux $ternary$libresoc.v:137693$5904 + parameter \WIDTH 1 + connect \A \gpio_e10__core__oe + connect \B \io_bd [11] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137693$5904_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$75 + cell $mux $ternary$libresoc.v:137694$5905 + parameter \WIDTH 1 + connect \A \gpio_e11__pad__i + connect \B \io_bd [12] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137694$5905_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$77 + cell $mux $ternary$libresoc.v:137695$5906 + parameter \WIDTH 1 + connect \A \gpio_e11__core__o + connect \B \io_bd [13] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137695$5906_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$79 + cell $mux $ternary$libresoc.v:137697$5908 + parameter \WIDTH 1 + connect \A \gpio_e11__core__oe + connect \B \io_bd [14] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137697$5908_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$81 + cell $mux $ternary$libresoc.v:137698$5909 + parameter \WIDTH 1 + connect \A \gpio_e12__pad__i + connect \B \io_bd [15] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137698$5909_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$83 + cell $mux $ternary$libresoc.v:137699$5910 + parameter \WIDTH 1 + connect \A \gpio_e12__core__o + connect \B \io_bd [16] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137699$5910_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$85 + cell $mux $ternary$libresoc.v:137700$5911 + parameter \WIDTH 1 + connect \A \gpio_e12__core__oe + connect \B \io_bd [17] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137700$5911_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$87 + cell $mux $ternary$libresoc.v:137701$5912 + parameter \WIDTH 1 + connect \A \gpio_e13__pad__i + connect \B \io_bd [18] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137701$5912_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$9 + cell $mux $ternary$libresoc.v:137702$5913 + parameter \WIDTH 1 + connect \A \gpio_e13__core__o + connect \B \io_bd [19] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137702$5913_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$91 + cell $mux $ternary$libresoc.v:137703$5914 + parameter \WIDTH 1 + connect \A \gpio_e13__core__oe + connect \B \io_bd [20] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137703$5914_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 328 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 164 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 319 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 329 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" - wire \TAP_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire \_fsm_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire \_fsm_isdr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" - wire \_fsm_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire \_fsm_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire \_fsm_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" - wire \_idblock_TAP_id_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" - wire \_idblock_id_bypass - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire \_idblock_select_id - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 \_irblock_ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" - wire input 330 \clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire input 6 \dmi0__ack_o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 4 output 2 \dmi0__addr_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 4 \dmi0__addr_i$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 output 5 \dmi0__din - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 \dmi0__din$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 input 7 \dmi0__dout - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire output 3 \dmi0__req_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire output 4 \dmi0__we_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire width 8 \dmi0_addrsr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire width 8 \dmi0_addrsr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire \dmi0_addrsr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire \dmi0_addrsr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \dmi0_addrsr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \dmi0_addrsr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 8 \dmi0_addrsr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 8 \dmi0_addrsr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \dmi0_addrsr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \dmi0_addrsr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_addrsr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_addrsr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_addrsr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_addrsr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 64 \dmi0_datasr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 64 \dmi0_datasr__i$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 64 \dmi0_datasr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 2 \dmi0_datasr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 2 \dmi0_datasr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \dmi0_datasr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire width 2 \dmi0_datasr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \dmi0_datasr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \dmi0_datasr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \dmi0_datasr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \dmi0_datasr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_datasr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_datasr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_datasr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_datasr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 165 \eint_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 10 \eint_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \eint_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 11 \eint_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \eint_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 12 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - wire width 3 \fsm_state - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$503 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$503$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - wire width 3 \fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \gpio_e10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 21 \gpio_e10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 19 \gpio_e10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 23 \gpio_e11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \gpio_e11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \gpio_e11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 25 \gpio_e12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 29 \gpio_e13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 30 \gpio_e13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 31 \gpio_e14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 35 \gpio_e15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 36 \gpio_e15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \gpio_e8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 14 \gpio_e8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 15 \gpio_e8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 13 \gpio_e8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 17 \gpio_e9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 18 \gpio_e9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 16 \gpio_e9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_s0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_s0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_s0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 37 \gpio_s0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 41 \gpio_s1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 42 \gpio_s1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_s1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_s2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_s2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 43 \gpio_s2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 47 \gpio_s3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 48 \gpio_s3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_s3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_s4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_s4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 49 \gpio_s4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 53 \gpio_s5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 54 \gpio_s5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_s5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_s6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_s6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 55 \gpio_s6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 59 \gpio_s7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 60 \gpio_s7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_s7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s7__pad__oe - attribute \src "libresoc.v:140366.7-140366.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 154 \io_bd - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 154 \io_bd$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" - wire \io_bd2core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" - wire \io_bd2io - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" - wire \io_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" - wire \io_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 154 \io_sr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 154 \io_sr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" - wire \io_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 326 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 320 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 \jtag_wb__adr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 322 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 327 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 325 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 \jtag_wb__dat_w$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 321 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 323 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 324 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire width 29 \jtag_wb_addrsr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire width 29 \jtag_wb_addrsr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire \jtag_wb_addrsr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire \jtag_wb_addrsr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \jtag_wb_addrsr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \jtag_wb_addrsr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 29 \jtag_wb_addrsr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 29 \jtag_wb_addrsr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \jtag_wb_addrsr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \jtag_wb_addrsr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_addrsr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_addrsr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_addrsr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_addrsr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 64 \jtag_wb_datasr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 64 \jtag_wb_datasr__i$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 64 \jtag_wb_datasr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 2 \jtag_wb_datasr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 2 \jtag_wb_datasr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \jtag_wb_datasr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire width 2 \jtag_wb_datasr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \jtag_wb_datasr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \jtag_wb_datasr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \jtag_wb_datasr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \jtag_wb_datasr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_datasr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_datasr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_datasr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_datasr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 61 \mspi0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \mspi0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \mspi0_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \mspi0_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \mspi0_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \mspi0_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \mspi0_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \mspi0_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \mspi1_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \mspi1_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \mtwi_scl__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \mtwi_scl__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mtwi_sda__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \mtwi_sda__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \mtwi_sda__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire \negjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire \negjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_data1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sd0_data1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sd0_data1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \sd0_data1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_data1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sd0_data2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sd0_data2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sd0_data2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_data3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_data3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sd0_data3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_data3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_data3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_a_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_a_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_a_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_a_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_a_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_a_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_a_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_a_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_a_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_a_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_a_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_a_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_a_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_a_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_a_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_a_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_a_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_a_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_ba_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_ba_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_ba_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_ba_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_cas_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_cas_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_cke__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_cke__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_clock__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_clock__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sdr_dm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_dm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_dm_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dq_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sdr_dq_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sdr_dq_0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sdr_dq_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_dq_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_dq_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sdr_dq_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_dq_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_dq_2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_dq_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_dq_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_dq_3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_dq_3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dq_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_dq_4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dq_8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_ras_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_ras_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_we_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire width 3 \sr0__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire width 3 \sr0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire \sr0__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire \sr0__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \sr0_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \sr0_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 3 \sr0_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 3 \sr0_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \sr0_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \sr0_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr0_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr0_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr0_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr0_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire width 2 \sr5__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire \sr5__ie - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire width 2 \sr5__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire \sr5__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire \sr5__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \sr5_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \sr5_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 2 \sr5_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 2 \sr5_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \sr5_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \sr5_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr5_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr5_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr5_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr5_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire output 8 \wb_dcache_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire \wb_dcache_en$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire output 9 \wb_icache_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire \wb_icache_en$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:142016$5901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 29 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 30 - connect \A \jtag_wb__adr - connect \B 1'1 - connect \Y $add$libresoc.v:142016$5901_Y + cell $mux $ternary$libresoc.v:137704$5915 + parameter \WIDTH 1 + connect \A \gpio_e14__pad__i + connect \B \io_bd [21] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:137704$5915_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:142018$5903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 29 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 30 - connect \A \jtag_wb__adr - connect \B 1'1 - connect \Y $add$libresoc.v:142018$5903_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:137705$5916 + parameter \WIDTH 1 + connect \A \gpio_e14__core__o + connect \B \io_bd [22] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137705$5916_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:142024$5910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \dmi0__addr_i - connect \B 1'1 - connect \Y $add$libresoc.v:142024$5910_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:137706$5917 + parameter \WIDTH 1 + connect \A \gpio_e14__core__oe + connect \B \io_bd [23] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:137706$5917_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:142025$5911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \dmi0__addr_i - connect \B 1'1 - connect \Y $add$libresoc.v:142025$5911_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:137781.8-137793.4" + cell \_fsm \_fsm + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tms \TAP_bus__tms + connect \capture \_fsm_capture + connect \isdr \_fsm_isdr + connect \isir \_fsm_isir + connect \negjtag_clk \negjtag_clk + connect \negjtag_rst \negjtag_rst + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:141840$5725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:141840$5725_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:137794.12-137804.4" + cell \_idblock \_idblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_id_tdo \_idblock_TAP_id_tdo + connect \capture \_fsm_capture + connect \id_bypass \_idblock_id_bypass + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \select_id \_idblock_select_id + connect \shift \_fsm_shift + connect \update \_fsm_update end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:141907$5792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$27 - connect \Y $and$libresoc.v:141907$5792_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:137805.12-137815.4" + cell \_irblock \_irblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isir \_fsm_isir + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \tdo \_irblock_tdo + connect \update \_fsm_update end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:141918$5803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$29 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:141918$5803_Y + attribute \src "libresoc.v:136016.7-136016.20" + process $proc$libresoc.v:136016$6113 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:141946$5831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$367 - connect \Y $and$libresoc.v:141946$5831_Y + attribute \src "libresoc.v:136574.13-136574.32" + process $proc$libresoc.v:136574$6114 + assign { } { } + assign $1\dmi0__addr_i[3:0] 4'0000 + sync always + sync init + update \dmi0__addr_i $1\dmi0__addr_i[3:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:141949$5834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$373 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:141949$5834_Y + attribute \src "libresoc.v:136579.14-136579.46" + process $proc$libresoc.v:136579$6115 + assign { } { } + assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0__din $1\dmi0__din[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:141952$5837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$377 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:141952$5837_Y + attribute \src "libresoc.v:136593.7-136593.29" + process $proc$libresoc.v:136593$6116 + assign { } { } + assign $1\dmi0_addrsr__oe[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:141954$5839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$381 - connect \B \_fsm_update - connect \Y $and$libresoc.v:141954$5839_Y + attribute \src "libresoc.v:136601.13-136601.36" + process $proc$libresoc.v:136601$6117 + assign { } { } + assign $1\dmi0_addrsr_reg[7:0] 8'00000000 + sync always + sync init + update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:141956$5841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_update_core_prev - connect \B \$385 - connect \Y $and$libresoc.v:141956$5841_Y + attribute \src "libresoc.v:136609.7-136609.37" + process $proc$libresoc.v:136609$6118 + assign { } { } + assign $1\dmi0_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:141959$5844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$391 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:141959$5844_Y + attribute \src "libresoc.v:136613.7-136613.42" + process $proc$libresoc.v:136613$6119 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:141961$5846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$395 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:141961$5846_Y + attribute \src "libresoc.v:136617.14-136617.51" + process $proc$libresoc.v:136617$6120 + assign { } { } + assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:141965$5850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$399 - connect \B \_fsm_update - connect \Y $and$libresoc.v:141965$5850_Y + attribute \src "libresoc.v:136623.13-136623.35" + process $proc$libresoc.v:136623$6121 + assign { } { } + assign $1\dmi0_datasr__oe[1:0] 2'00 + sync always + sync init + update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:141967$5852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_update_core_prev - connect \B \$403 - connect \Y $and$libresoc.v:141967$5852_Y + attribute \src "libresoc.v:136631.14-136631.52" + process $proc$libresoc.v:136631$6122 + assign { } { } + assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:141971$5856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$411 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:141971$5856_Y + attribute \src "libresoc.v:136639.7-136639.37" + process $proc$libresoc.v:136639$6123 + assign { } { } + assign $1\dmi0_datasr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:141973$5858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$415 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:141973$5858_Y + attribute \src "libresoc.v:136643.7-136643.42" + process $proc$libresoc.v:136643$6124 + assign { } { } + assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:141976$5861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$419 - connect \B \_fsm_update - connect \Y $and$libresoc.v:141976$5861_Y + attribute \src "libresoc.v:136659.13-136659.29" + process $proc$libresoc.v:136659$6125 + assign { } { } + assign $1\fsm_state[2:0] 3'000 + sync always + sync init + update \fsm_state $1\fsm_state[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:141978$5863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_update_core_prev - connect \B \$423 - connect \Y $and$libresoc.v:141978$5863_Y + attribute \src "libresoc.v:136661.13-136661.35" + process $proc$libresoc.v:136661$6126 + assign { } { } + assign $0\fsm_state$503[2:0]$6127 3'000 + sync always + sync init + update \fsm_state$503 $0\fsm_state$503[2:0]$6127 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:141981$5866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$429 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:141981$5866_Y + attribute \src "libresoc.v:136859.15-136859.67" + process $proc$libresoc.v:136859$6128 + assign { } { } + assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_bd $1\io_bd[153:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:141983$5868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$433 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:141983$5868_Y + attribute \src "libresoc.v:136871.15-136871.67" + process $proc$libresoc.v:136871$6129 + assign { } { } + assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_sr $1\io_sr[153:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:141985$5870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$41 - connect \Y $and$libresoc.v:141985$5870_Y + attribute \src "libresoc.v:136880.14-136880.41" + process $proc$libresoc.v:136880$6130 + assign { } { } + assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:141986$5871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$437 - connect \B \_fsm_update - connect \Y $and$libresoc.v:141986$5871_Y + attribute \src "libresoc.v:136889.14-136889.51" + process $proc$libresoc.v:136889$6131 + assign { } { } + assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:141988$5873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_update_core_prev - connect \B \$441 - connect \Y $and$libresoc.v:141988$5873_Y + attribute \src "libresoc.v:136903.7-136903.32" + process $proc$libresoc.v:136903$6132 + assign { } { } + assign $1\jtag_wb_addrsr__oe[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:141992$5877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$449 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:141992$5877_Y + attribute \src "libresoc.v:136911.14-136911.47" + process $proc$libresoc.v:136911$6133 + assign { } { } + assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:141994$5879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$453 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:141994$5879_Y + attribute \src "libresoc.v:136919.7-136919.40" + process $proc$libresoc.v:136919$6134 + assign { } { } + assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:141996$5881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$43 - connect \B \_fsm_update - connect \Y $and$libresoc.v:141996$5881_Y + attribute \src "libresoc.v:136923.7-136923.45" + process $proc$libresoc.v:136923$6135 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:141997$5882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$457 - connect \B \_fsm_update - connect \Y $and$libresoc.v:141997$5882_Y + attribute \src "libresoc.v:136927.14-136927.54" + process $proc$libresoc.v:136927$6136 + assign { } { } + assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:141999$5884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_update_core_prev - connect \B \$461 - connect \Y $and$libresoc.v:141999$5884_Y + attribute \src "libresoc.v:136933.13-136933.38" + process $proc$libresoc.v:136933$6137 + assign { } { } + assign $1\jtag_wb_datasr__oe[1:0] 2'00 + sync always + sync init + update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:142002$5887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$467 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:142002$5887_Y + attribute \src "libresoc.v:136941.14-136941.55" + process $proc$libresoc.v:136941$6138 + assign { } { } + assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:142004$5889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$471 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:142004$5889_Y + attribute \src "libresoc.v:136949.7-136949.40" + process $proc$libresoc.v:136949$6139 + assign { } { } + assign $1\jtag_wb_datasr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:142006$5891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$475 - connect \B \_fsm_update - connect \Y $and$libresoc.v:142006$5891_Y + attribute \src "libresoc.v:136953.7-136953.45" + process $proc$libresoc.v:136953$6140 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:142009$5894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr5_update_core_prev - connect \B \$479 - connect \Y $and$libresoc.v:142009$5894_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:142041$5927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$5 - connect \Y $and$libresoc.v:142041$5927_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:141796$5681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:141796$5681_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:141807$5692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:141807$5692_Y + attribute \src "libresoc.v:137383.7-137383.21" + process $proc$libresoc.v:137383$6141 + assign { } { } + assign $1\sr0__oe[0:0] 1'0 + sync always + sync init + update \sr0__oe $1\sr0__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:141818$5703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:141818$5703_Y + attribute \src "libresoc.v:137391.13-137391.27" + process $proc$libresoc.v:137391$6142 + assign { } { } + assign $1\sr0_reg[2:0] 3'000 + sync always + sync init + update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:141851$5736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'1 - connect \Y $eq$libresoc.v:141851$5736_Y + attribute \src "libresoc.v:137399.7-137399.29" + process $proc$libresoc.v:137399$6143 + assign { } { } + assign $1\sr0_update_core[0:0] 1'0 + sync always + sync init + update \sr0_update_core $1\sr0_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:141852$5737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:141852$5737_Y + attribute \src "libresoc.v:137403.7-137403.34" + process $proc$libresoc.v:137403$6144 + assign { } { } + assign $1\sr0_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:141863$5748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:141863$5748_Y + attribute \src "libresoc.v:137413.7-137413.21" + process $proc$libresoc.v:137413$6145 + assign { } { } + assign $1\sr5__oe[0:0] 1'0 + sync always + sync init + update \sr5__oe $1\sr5__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:141885$5770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:141885$5770_Y + attribute \src "libresoc.v:137421.13-137421.27" + process $proc$libresoc.v:137421$6146 + assign { } { } + assign $1\sr5_reg[2:0] 3'000 + sync always + sync init + update \sr5_reg $1\sr5_reg[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:141929$5814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:141929$5814_Y + attribute \src "libresoc.v:137429.7-137429.29" + process $proc$libresoc.v:137429$6147 + assign { } { } + assign $1\sr5_update_core[0:0] 1'0 + sync always + sync init + update \sr5_update_core $1\sr5_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:141940$5825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:141940$5825_Y + attribute \src "libresoc.v:137433.7-137433.34" + process $proc$libresoc.v:137433$6148 + assign { } { } + assign $1\sr5_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:141941$5826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:141941$5826_Y + attribute \src "libresoc.v:137438.7-137438.26" + process $proc$libresoc.v:137438$6149 + assign { } { } + assign $1\wb_dcache_en[0:0] 1'1 + sync always + sync init + update \wb_dcache_en $1\wb_dcache_en[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:141942$5827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:141942$5827_Y + attribute \src "libresoc.v:137443.7-137443.26" + process $proc$libresoc.v:137443$6150 + assign { } { } + assign $1\wb_icache_en[0:0] 1'1 + sync always + sync init + update \wb_icache_en $1\wb_icache_en[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:141944$5829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:141944$5829_Y + attribute \src "libresoc.v:137448.7-137448.24" + process $proc$libresoc.v:137448$6151 + assign { } { } + assign $1\wb_sram_en[0:0] 1'1 + sync always + sync init + update \wb_sram_en $1\wb_sram_en[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:141947$5832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'100 - connect \Y $eq$libresoc.v:141947$5832_Y + attribute \src "libresoc.v:137707.3-137708.41" + process $proc$libresoc.v:137707$5918 + assign { } { } + assign $0\wb_icache_en[0:0] \wb_icache_en$next + sync posedge \clk + update \wb_icache_en $0\wb_icache_en[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:141957$5842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'101 - connect \Y $eq$libresoc.v:141957$5842_Y + attribute \src "libresoc.v:137709.3-137710.41" + process $proc$libresoc.v:137709$5919 + assign { } { } + assign $0\wb_dcache_en[0:0] \wb_dcache_en$next + sync posedge \clk + update \wb_dcache_en $0\wb_dcache_en[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:141962$5847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:141962$5847_Y + attribute \src "libresoc.v:137711.3-137712.37" + process $proc$libresoc.v:137711$5920 + assign { } { } + assign $0\wb_sram_en[0:0] \wb_sram_en$next + sync posedge \clk + update \wb_sram_en $0\wb_sram_en[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:141963$5848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:141963$5848_Y + attribute \src "libresoc.v:137713.3-137714.45" + process $proc$libresoc.v:137713$5921 + assign { } { } + assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next + sync posedge \clk + update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:141968$5853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'110 - connect \Y $eq$libresoc.v:141968$5853_Y + attribute \src "libresoc.v:137715.3-137716.35" + process $proc$libresoc.v:137715$5922 + assign { } { } + assign $0\dmi0__din[63:0] \dmi0__din$next + sync posedge \clk + update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:141969$5854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'111 - connect \Y $eq$libresoc.v:141969$5854_Y + attribute \src "libresoc.v:137717.3-137718.45" + process $proc$libresoc.v:137717$5923 + assign { } { } + assign $0\fsm_state$503[2:0]$5924 \fsm_state$503$next + sync posedge \clk + update \fsm_state$503 $0\fsm_state$503[2:0]$5924 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:141979$5864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1000 - connect \Y $eq$libresoc.v:141979$5864_Y + attribute \src "libresoc.v:137719.3-137720.41" + process $proc$libresoc.v:137719$5925 + assign { } { } + assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next + sync posedge \clk + update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:141989$5874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1001 - connect \Y $eq$libresoc.v:141989$5874_Y + attribute \src "libresoc.v:137721.3-137722.51" + process $proc$libresoc.v:137721$5926 + assign { } { } + assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next + sync posedge \clk + update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:141990$5875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1010 - connect \Y $eq$libresoc.v:141990$5875_Y + attribute \src "libresoc.v:137723.3-137724.45" + process $proc$libresoc.v:137723$5927 + assign { } { } + assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next + sync posedge \clk + update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:142000$5885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1011 - connect \Y $eq$libresoc.v:142000$5885_Y + attribute \src "libresoc.v:137725.3-137726.35" + process $proc$libresoc.v:137725$5928 + assign { } { } + assign $0\fsm_state[2:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:142007$5892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:142007$5892_Y + attribute \src "libresoc.v:137727.3-137728.41" + process $proc$libresoc.v:137727$5929 + assign { } { } + assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next + sync posedge \clk + update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:142010$5895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'0 - connect \Y $eq$libresoc.v:142010$5895_Y + attribute \src "libresoc.v:137729.3-137730.31" + process $proc$libresoc.v:137729$5930 + assign { } { } + assign $0\sr5_reg[2:0] \sr5_reg$next + sync posedge \posjtag_clk + update \sr5_reg $0\sr5_reg[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:142012$5897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'1 - connect \Y $eq$libresoc.v:142012$5897_Y + attribute \src "libresoc.v:137731.3-137732.31" + process $proc$libresoc.v:137731$5931 + assign { } { } + assign $0\sr5__oe[0:0] \sr5__oe$next + sync posedge \clk + update \sr5__oe $0\sr5__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:142013$5898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'10 - connect \Y $eq$libresoc.v:142013$5898_Y + attribute \src "libresoc.v:137733.3-137734.57" + process $proc$libresoc.v:137733$5932 + assign { } { } + assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next + sync posedge \clk + update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:142015$5900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'10 - connect \Y $eq$libresoc.v:142015$5900_Y + attribute \src "libresoc.v:137735.3-137736.47" + process $proc$libresoc.v:137735$5933 + assign { } { } + assign $0\sr5_update_core[0:0] \sr5_update_core$next + sync posedge \clk + update \sr5_update_core $0\sr5_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:142017$5902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:142017$5902_Y + attribute \src "libresoc.v:137737.3-137738.47" + process $proc$libresoc.v:137737$5934 + assign { } { } + assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next + sync posedge \posjtag_clk + update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:142020$5906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state$503 - connect \B 1'1 - connect \Y $eq$libresoc.v:142020$5906_Y + attribute \src "libresoc.v:137739.3-137740.47" + process $proc$libresoc.v:137739$5935 + assign { } { } + assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next + sync posedge \clk + update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:142021$5907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state$503 - connect \B 2'10 - connect \Y $eq$libresoc.v:142021$5907_Y + attribute \src "libresoc.v:137741.3-137742.73" + process $proc$libresoc.v:137741$5936 + assign { } { } + assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next + sync posedge \clk + update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:142023$5909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state$503 - connect \B 2'10 - connect \Y $eq$libresoc.v:142023$5909_Y + attribute \src "libresoc.v:137743.3-137744.63" + process $proc$libresoc.v:137743$5937 + assign { } { } + assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next + sync posedge \clk + update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:142019$5904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:142019$5904_Y + attribute \src "libresoc.v:137745.3-137746.47" + process $proc$libresoc.v:137745$5938 + assign { } { } + assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next + sync posedge \posjtag_clk + update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:141948$5833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141948$5833_Y + attribute \src "libresoc.v:137747.3-137748.47" + process $proc$libresoc.v:137747$5939 + assign { } { } + assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next + sync posedge \clk + update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:141950$5835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141950$5835_Y + attribute \src "libresoc.v:137749.3-137750.73" + process $proc$libresoc.v:137749$5940 + assign { } { } + assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next + sync posedge \clk + update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:141953$5838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141953$5838_Y + attribute \src "libresoc.v:137751.3-137752.63" + process $proc$libresoc.v:137751$5941 + assign { } { } + assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next + sync posedge \clk + update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:141958$5843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141958$5843_Y + attribute \src "libresoc.v:137753.3-137754.53" + process $proc$libresoc.v:137753$5942 + assign { } { } + assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:141960$5845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141960$5845_Y + attribute \src "libresoc.v:137755.3-137756.53" + process $proc$libresoc.v:137755$5943 + assign { } { } + assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next + sync posedge \clk + update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:141964$5849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141964$5849_Y + attribute \src "libresoc.v:137757.3-137758.79" + process $proc$libresoc.v:137757$5944 + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next + sync posedge \clk + update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:141970$5855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141970$5855_Y + attribute \src "libresoc.v:137759.3-137760.69" + process $proc$libresoc.v:137759$5945 + assign { } { } + assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next + sync posedge \clk + update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:141972$5857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141972$5857_Y + attribute \src "libresoc.v:137761.3-137762.53" + process $proc$libresoc.v:137761$5946 + assign { } { } + assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:141975$5860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141975$5860_Y + attribute \src "libresoc.v:137763.3-137764.53" + process $proc$libresoc.v:137763$5947 + assign { } { } + assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next + sync posedge \clk + update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:141980$5865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141980$5865_Y + attribute \src "libresoc.v:137765.3-137766.79" + process $proc$libresoc.v:137765$5948 + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next + sync posedge \clk + update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:141982$5867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141982$5867_Y + attribute \src "libresoc.v:137767.3-137768.69" + process $proc$libresoc.v:137767$5949 + assign { } { } + assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next + sync posedge \clk + update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:141984$5869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141984$5869_Y + attribute \src "libresoc.v:137769.3-137770.31" + process $proc$libresoc.v:137769$5950 + assign { } { } + assign $0\sr0_reg[2:0] \sr0_reg$next + sync posedge \posjtag_clk + update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:141991$5876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141991$5876_Y + attribute \src "libresoc.v:137771.3-137772.31" + process $proc$libresoc.v:137771$5951 + assign { } { } + assign $0\sr0__oe[0:0] \sr0__oe$next + sync posedge \clk + update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:141993$5878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141993$5878_Y + attribute \src "libresoc.v:137773.3-137774.57" + process $proc$libresoc.v:137773$5952 + assign { } { } + assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next + sync posedge \clk + update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:141995$5880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:141995$5880_Y + attribute \src "libresoc.v:137775.3-137776.47" + process $proc$libresoc.v:137775$5953 + assign { } { } + assign $0\sr0_update_core[0:0] \sr0_update_core$next + sync posedge \clk + update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:142001$5886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr5_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:142001$5886_Y + attribute \src "libresoc.v:137777.3-137778.27" + process $proc$libresoc.v:137777$5954 + assign { } { } + assign $0\io_bd[153:0] \io_bd$next + sync negedge \negjtag_clk + update \io_bd $0\io_bd[153:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:142003$5888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr5_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:142003$5888_Y + attribute \src "libresoc.v:137779.3-137780.27" + process $proc$libresoc.v:137779$5955 + assign { } { } + assign $0\io_sr[153:0] \io_sr$next + sync posedge \posjtag_clk + update \io_sr $0\io_sr[153:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:142005$5890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr5_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:142005$5890_Y + attribute \src "libresoc.v:137816.3-137831.6" + process $proc$libresoc.v:137816$5956 + assign { } { } + assign { } { } + assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] + attribute \src "libresoc.v:137817.5-137817.29" + switch \initial + attribute \src "libresoc.v:137817.9-137817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" + switch { \$369 \_idblock_select_id \_fsm_isir } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\TAP_tdo[0:0] \_irblock_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\TAP_tdo[0:0] \io_sr [153] + case + assign $1\TAP_tdo[0:0] 1'0 + end + sync always + update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:141955$5840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_update_core - connect \Y $not$libresoc.v:141955$5840_Y + attribute \src "libresoc.v:137832.3-137840.6" + process $proc$libresoc.v:137832$5957 + assign { } { } + assign { } { } + assign $0\sr0_update_core$next[0:0]$5958 $1\sr0_update_core$next[0:0]$5959 + attribute \src "libresoc.v:137833.5-137833.29" + switch \initial + attribute \src "libresoc.v:137833.9-137833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core$next[0:0]$5959 1'0 + case + assign $1\sr0_update_core$next[0:0]$5959 \sr0_update + end + sync always + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5958 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:141966$5851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:141966$5851_Y + attribute \src "libresoc.v:137841.3-137849.6" + process $proc$libresoc.v:137841$5960 + assign { } { } + assign { } { } + assign $0\sr0_update_core_prev$next[0:0]$5961 $1\sr0_update_core_prev$next[0:0]$5962 + attribute \src "libresoc.v:137842.5-137842.29" + switch \initial + attribute \src "libresoc.v:137842.9-137842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core_prev$next[0:0]$5962 1'0 + case + assign $1\sr0_update_core_prev$next[0:0]$5962 \sr0_update_core + end + sync always + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5961 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:141977$5862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:141977$5862_Y + attribute \src "libresoc.v:137850.3-137866.6" + process $proc$libresoc.v:137850$5963 + assign { } { } + assign { } { } + assign $0\sr0__oe$next[0:0]$5964 $2\sr0__oe$next[0:0]$5966 + attribute \src "libresoc.v:137851.5-137851.29" + switch \initial + attribute \src "libresoc.v:137851.9-137851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$387 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0__oe$next[0:0]$5965 \sr0_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr0__oe$next[0:0]$5965 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0__oe$next[0:0]$5966 1'0 + case + assign $2\sr0__oe$next[0:0]$5966 $1\sr0__oe$next[0:0]$5965 + end + sync always + update \sr0__oe$next $0\sr0__oe$next[0:0]$5964 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:141987$5872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:141987$5872_Y + attribute \src "libresoc.v:137867.3-137887.6" + process $proc$libresoc.v:137867$5967 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr0_reg$next[2:0]$5968 $3\sr0_reg$next[2:0]$5971 + attribute \src "libresoc.v:137868.5-137868.29" + switch \initial + attribute \src "libresoc.v:137868.9-137868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr0_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_reg$next[2:0]$5969 { \TAP_bus__tdi \sr0_reg [2:1] } + case + assign $1\sr0_reg$next[2:0]$5969 \sr0_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr0_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0_reg$next[2:0]$5970 \sr0__i + case + assign $2\sr0_reg$next[2:0]$5970 $1\sr0_reg$next[2:0]$5969 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr0_reg$next[2:0]$5971 3'000 + case + assign $3\sr0_reg$next[2:0]$5971 $2\sr0_reg$next[2:0]$5970 + end + sync always + update \sr0_reg$next $0\sr0_reg$next[2:0]$5968 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:141998$5883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:141998$5883_Y + attribute \src "libresoc.v:137888.3-137896.6" + process $proc$libresoc.v:137888$5972 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5973 $1\jtag_wb_addrsr_update_core$next[0:0]$5974 + attribute \src "libresoc.v:137889.5-137889.29" + switch \initial + attribute \src "libresoc.v:137889.9-137889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5974 1'0 + case + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5974 \jtag_wb_addrsr_update + end + sync always + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5973 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:142008$5893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr5_update_core - connect \Y $not$libresoc.v:142008$5893_Y + attribute \src "libresoc.v:137897.3-137905.6" + process $proc$libresoc.v:137897$5975 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5976 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5977 + attribute \src "libresoc.v:137898.5-137898.29" + switch \initial + attribute \src "libresoc.v:137898.9-137898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5977 1'0 + case + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5977 \jtag_wb_addrsr_update_core + end + sync always + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5976 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:142011$5896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$484 - connect \Y $not$libresoc.v:142011$5896_Y + attribute \src "libresoc.v:137906.3-137922.6" + process $proc$libresoc.v:137906$5978 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr__oe$next[0:0]$5979 $2\jtag_wb_addrsr__oe$next[0:0]$5981 + attribute \src "libresoc.v:137907.5-137907.29" + switch \initial + attribute \src "libresoc.v:137907.9-137907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$405 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5980 \jtag_wb_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5980 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr__oe$next[0:0]$5981 1'0 + case + assign $2\jtag_wb_addrsr__oe$next[0:0]$5981 $1\jtag_wb_addrsr__oe$next[0:0]$5980 + end + sync always + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5979 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:141829$5714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$11 - connect \B \$13 - connect \Y $or$libresoc.v:141829$5714_Y + attribute \src "libresoc.v:137923.3-137943.6" + process $proc$libresoc.v:137923$5982 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_reg$next[28:0]$5983 $3\jtag_wb_addrsr_reg$next[28:0]$5986 + attribute \src "libresoc.v:137924.5-137924.29" + switch \initial + attribute \src "libresoc.v:137924.9-137924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_reg$next[28:0]$5984 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + case + assign $1\jtag_wb_addrsr_reg$next[28:0]$5984 \jtag_wb_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr_reg$next[28:0]$5985 \jtag_wb_addrsr__i + case + assign $2\jtag_wb_addrsr_reg$next[28:0]$5985 $1\jtag_wb_addrsr_reg$next[28:0]$5984 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_addrsr_reg$next[28:0]$5986 29'00000000000000000000000000000 + case + assign $3\jtag_wb_addrsr_reg$next[28:0]$5986 $2\jtag_wb_addrsr_reg$next[28:0]$5985 + end + sync always + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5983 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:141874$5759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$19 - connect \B \$21 - connect \Y $or$libresoc.v:141874$5759_Y + attribute \src "libresoc.v:137944.3-137952.6" + process $proc$libresoc.v:137944$5987 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core$next[0:0]$5988 $1\jtag_wb_datasr_update_core$next[0:0]$5989 + attribute \src "libresoc.v:137945.5-137945.29" + switch \initial + attribute \src "libresoc.v:137945.9-137945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core$next[0:0]$5989 1'0 + case + assign $1\jtag_wb_datasr_update_core$next[0:0]$5989 \jtag_wb_datasr_update + end + sync always + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5988 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:141896$5781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$23 - connect \B \$25 - connect \Y $or$libresoc.v:141896$5781_Y + attribute \src "libresoc.v:137953.3-137961.6" + process $proc$libresoc.v:137953$5990 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5991 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5992 + attribute \src "libresoc.v:137954.5-137954.29" + switch \initial + attribute \src "libresoc.v:137954.9-137954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5992 1'0 + case + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5992 \jtag_wb_datasr_update_core + end + sync always + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5991 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:141943$5828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$359 - connect \B \$361 - connect \Y $or$libresoc.v:141943$5828_Y + attribute \src "libresoc.v:137962.3-137978.6" + process $proc$libresoc.v:137962$5993 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__oe$next[1:0]$5994 $2\jtag_wb_datasr__oe$next[1:0]$5996 + attribute \src "libresoc.v:137963.5-137963.29" + switch \initial + attribute \src "libresoc.v:137963.9-137963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$425 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$5995 \jtag_wb_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$5995 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__oe$next[1:0]$5996 2'00 + case + assign $2\jtag_wb_datasr__oe$next[1:0]$5996 $1\jtag_wb_datasr__oe$next[1:0]$5995 + end + sync always + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5994 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:141945$5830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$363 - connect \B \$365 - connect \Y $or$libresoc.v:141945$5830_Y + attribute \src "libresoc.v:137979.3-137999.6" + process $proc$libresoc.v:137979$5997 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_reg$next[63:0]$5998 $3\jtag_wb_datasr_reg$next[63:0]$6001 + attribute \src "libresoc.v:137980.5-137980.29" + switch \initial + attribute \src "libresoc.v:137980.9-137980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_reg$next[63:0]$5999 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + case + assign $1\jtag_wb_datasr_reg$next[63:0]$5999 \jtag_wb_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr_reg$next[63:0]$6000 \jtag_wb_datasr__i + case + assign $2\jtag_wb_datasr_reg$next[63:0]$6000 $1\jtag_wb_datasr_reg$next[63:0]$5999 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr_reg$next[63:0]$6001 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr_reg$next[63:0]$6001 $2\jtag_wb_datasr_reg$next[63:0]$6000 + end + sync always + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5998 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:141951$5836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $or$libresoc.v:141951$5836_Y + attribute \src "libresoc.v:138000.3-138008.6" + process $proc$libresoc.v:138000$6002 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core$next[0:0]$6003 $1\dmi0_addrsr_update_core$next[0:0]$6004 + attribute \src "libresoc.v:138001.5-138001.29" + switch \initial + attribute \src "libresoc.v:138001.9-138001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core$next[0:0]$6004 1'0 + case + assign $1\dmi0_addrsr_update_core$next[0:0]$6004 \dmi0_addrsr_update + end + sync always + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6003 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:141974$5859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$37 - connect \B \$39 - connect \Y $or$libresoc.v:141974$5859_Y + attribute \src "libresoc.v:138009.3-138017.6" + process $proc$libresoc.v:138009$6005 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6006 $1\dmi0_addrsr_update_core_prev$next[0:0]$6007 + attribute \src "libresoc.v:138010.5-138010.29" + switch \initial + attribute \src "libresoc.v:138010.9-138010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6007 1'0 + case + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6007 \dmi0_addrsr_update_core + end + sync always + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6006 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:142014$5899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$487 - connect \B \$489 - connect \Y $or$libresoc.v:142014$5899_Y + attribute \src "libresoc.v:138018.3-138034.6" + process $proc$libresoc.v:138018$6008 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr__oe$next[0:0]$6009 $2\dmi0_addrsr__oe$next[0:0]$6011 + attribute \src "libresoc.v:138019.5-138019.29" + switch \initial + attribute \src "libresoc.v:138019.9-138019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$443 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$6010 \dmi0_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$6010 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr__oe$next[0:0]$6011 1'0 + case + assign $2\dmi0_addrsr__oe$next[0:0]$6011 $1\dmi0_addrsr__oe$next[0:0]$6010 + end + sync always + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6009 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:142022$5908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$504 - connect \B \$506 - connect \Y $or$libresoc.v:142022$5908_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:142030$5916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $or$libresoc.v:142030$5916_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:142019$5905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:142019$5904_Y - connect \Y $pos$libresoc.v:142019$5905_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141797$5682 - parameter \WIDTH 1 - connect \A \gpio_e15__pad__i - connect \B \io_bd [24] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141797$5682_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141798$5683 - parameter \WIDTH 1 - connect \A \gpio_e15__core__o - connect \B \io_bd [25] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141798$5683_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141799$5684 - parameter \WIDTH 1 - connect \A \gpio_e15__core__oe - connect \B \io_bd [26] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141799$5684_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141800$5685 - parameter \WIDTH 1 - connect \A \gpio_s0__pad__i - connect \B \io_bd [27] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141800$5685_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141801$5686 - parameter \WIDTH 1 - connect \A \gpio_s0__core__o - connect \B \io_bd [28] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141801$5686_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141802$5687 - parameter \WIDTH 1 - connect \A \gpio_s0__core__oe - connect \B \io_bd [29] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141802$5687_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141803$5688 - parameter \WIDTH 1 - connect \A \gpio_s1__pad__i - connect \B \io_bd [30] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141803$5688_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141804$5689 - parameter \WIDTH 1 - connect \A \gpio_s1__core__o - connect \B \io_bd [31] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141804$5689_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141805$5690 - parameter \WIDTH 1 - connect \A \gpio_s1__core__oe - connect \B \io_bd [32] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141805$5690_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141806$5691 - parameter \WIDTH 1 - connect \A \gpio_s2__pad__i - connect \B \io_bd [33] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141806$5691_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141808$5693 - parameter \WIDTH 1 - connect \A \gpio_s2__core__o - connect \B \io_bd [34] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141808$5693_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141809$5694 - parameter \WIDTH 1 - connect \A \gpio_s2__core__oe - connect \B \io_bd [35] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141809$5694_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141810$5695 - parameter \WIDTH 1 - connect \A \gpio_s3__pad__i - connect \B \io_bd [36] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141810$5695_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141811$5696 - parameter \WIDTH 1 - connect \A \gpio_s3__core__o - connect \B \io_bd [37] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141811$5696_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141812$5697 - parameter \WIDTH 1 - connect \A \gpio_s3__core__oe - connect \B \io_bd [38] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141812$5697_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141813$5698 - parameter \WIDTH 1 - connect \A \gpio_s4__pad__i - connect \B \io_bd [39] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141813$5698_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141814$5699 - parameter \WIDTH 1 - connect \A \gpio_s4__core__o - connect \B \io_bd [40] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141814$5699_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141815$5700 - parameter \WIDTH 1 - connect \A \gpio_s4__core__oe - connect \B \io_bd [41] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141815$5700_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141816$5701 - parameter \WIDTH 1 - connect \A \gpio_s5__pad__i - connect \B \io_bd [42] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141816$5701_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141817$5702 - parameter \WIDTH 1 - connect \A \gpio_s5__core__o - connect \B \io_bd [43] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141817$5702_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141819$5704 - parameter \WIDTH 1 - connect \A \gpio_s5__core__oe - connect \B \io_bd [44] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141819$5704_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141820$5705 - parameter \WIDTH 1 - connect \A \gpio_s6__pad__i - connect \B \io_bd [45] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141820$5705_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141821$5706 - parameter \WIDTH 1 - connect \A \gpio_s6__core__o - connect \B \io_bd [46] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141821$5706_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141822$5707 - parameter \WIDTH 1 - connect \A \gpio_s6__core__oe - connect \B \io_bd [47] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141822$5707_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141823$5708 - parameter \WIDTH 1 - connect \A \gpio_s7__pad__i - connect \B \io_bd [48] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141823$5708_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141824$5709 - parameter \WIDTH 1 - connect \A \gpio_s7__core__o - connect \B \io_bd [49] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141824$5709_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141825$5710 - parameter \WIDTH 1 - connect \A \gpio_s7__core__oe - connect \B \io_bd [50] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141825$5710_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141826$5711 - parameter \WIDTH 1 - connect \A \mspi0_clk__core__o - connect \B \io_bd [51] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141826$5711_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141827$5712 - parameter \WIDTH 1 - connect \A \mspi0_cs_n__core__o - connect \B \io_bd [52] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141827$5712_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141828$5713 - parameter \WIDTH 1 - connect \A \mspi0_mosi__core__o - connect \B \io_bd [53] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141828$5713_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:141830$5715 - parameter \WIDTH 1 - connect \A \mspi0_miso__pad__i - connect \B \io_bd [54] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141830$5715_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141831$5716 - parameter \WIDTH 1 - connect \A \mspi1_clk__core__o - connect \B \io_bd [55] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141831$5716_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141832$5717 - parameter \WIDTH 1 - connect \A \mspi1_cs_n__core__o - connect \B \io_bd [56] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141832$5717_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141833$5718 - parameter \WIDTH 1 - connect \A \mspi1_mosi__core__o - connect \B \io_bd [57] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141833$5718_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:141834$5719 - parameter \WIDTH 1 - connect \A \mspi1_miso__pad__i - connect \B \io_bd [58] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141834$5719_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141835$5720 - parameter \WIDTH 1 - connect \A \mtwi_sda__pad__i - connect \B \io_bd [59] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141835$5720_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141836$5721 - parameter \WIDTH 1 - connect \A \mtwi_sda__core__o - connect \B \io_bd [60] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141836$5721_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141837$5722 - parameter \WIDTH 1 - connect \A \mtwi_sda__core__oe - connect \B \io_bd [61] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141837$5722_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141838$5723 - parameter \WIDTH 1 - connect \A \mtwi_scl__core__o - connect \B \io_bd [62] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141838$5723_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141839$5724 - parameter \WIDTH 1 - connect \A \pwm_0__core__o - connect \B \io_bd [63] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141839$5724_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141841$5726 - parameter \WIDTH 1 - connect \A \pwm_1__core__o - connect \B \io_bd [64] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141841$5726_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141842$5727 - parameter \WIDTH 1 - connect \A \sd0_cmd__pad__i - connect \B \io_bd [65] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141842$5727_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141843$5728 - parameter \WIDTH 1 - connect \A \sd0_cmd__core__o - connect \B \io_bd [66] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141843$5728_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141844$5729 - parameter \WIDTH 1 - connect \A \sd0_cmd__core__oe - connect \B \io_bd [67] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141844$5729_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141845$5730 - parameter \WIDTH 1 - connect \A \sd0_clk__core__o - connect \B \io_bd [68] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141845$5730_Y + attribute \src "libresoc.v:138035.3-138055.6" + process $proc$libresoc.v:138035$6012 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_reg$next[7:0]$6013 $3\dmi0_addrsr_reg$next[7:0]$6016 + attribute \src "libresoc.v:138036.5-138036.29" + switch \initial + attribute \src "libresoc.v:138036.9-138036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_reg$next[7:0]$6014 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + case + assign $1\dmi0_addrsr_reg$next[7:0]$6014 \dmi0_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr_reg$next[7:0]$6015 \dmi0_addrsr__i + case + assign $2\dmi0_addrsr_reg$next[7:0]$6015 $1\dmi0_addrsr_reg$next[7:0]$6014 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_addrsr_reg$next[7:0]$6016 8'00000000 + case + assign $3\dmi0_addrsr_reg$next[7:0]$6016 $2\dmi0_addrsr_reg$next[7:0]$6015 + end + sync always + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6013 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141846$5731 - parameter \WIDTH 1 - connect \A \sd0_data0__pad__i - connect \B \io_bd [69] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141846$5731_Y + attribute \src "libresoc.v:138056.3-138064.6" + process $proc$libresoc.v:138056$6017 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core$next[0:0]$6018 $1\dmi0_datasr_update_core$next[0:0]$6019 + attribute \src "libresoc.v:138057.5-138057.29" + switch \initial + attribute \src "libresoc.v:138057.9-138057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core$next[0:0]$6019 1'0 + case + assign $1\dmi0_datasr_update_core$next[0:0]$6019 \dmi0_datasr_update + end + sync always + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6018 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141847$5732 - parameter \WIDTH 1 - connect \A \sd0_data0__core__o - connect \B \io_bd [70] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141847$5732_Y + attribute \src "libresoc.v:138065.3-138073.6" + process $proc$libresoc.v:138065$6020 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core_prev$next[0:0]$6021 $1\dmi0_datasr_update_core_prev$next[0:0]$6022 + attribute \src "libresoc.v:138066.5-138066.29" + switch \initial + attribute \src "libresoc.v:138066.9-138066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6022 1'0 + case + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6022 \dmi0_datasr_update_core + end + sync always + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6021 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141848$5733 - parameter \WIDTH 1 - connect \A \sd0_data0__core__oe - connect \B \io_bd [71] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141848$5733_Y + attribute \src "libresoc.v:138074.3-138090.6" + process $proc$libresoc.v:138074$6023 + assign { } { } + assign { } { } + assign $0\dmi0_datasr__oe$next[1:0]$6024 $2\dmi0_datasr__oe$next[1:0]$6026 + attribute \src "libresoc.v:138075.5-138075.29" + switch \initial + attribute \src "libresoc.v:138075.9-138075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$463 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$6025 \dmi0_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$6025 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__oe$next[1:0]$6026 2'00 + case + assign $2\dmi0_datasr__oe$next[1:0]$6026 $1\dmi0_datasr__oe$next[1:0]$6025 + end + sync always + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6024 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141849$5734 - parameter \WIDTH 1 - connect \A \sd0_data1__pad__i - connect \B \io_bd [72] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141849$5734_Y + attribute \src "libresoc.v:138091.3-138111.6" + process $proc$libresoc.v:138091$6027 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr_reg$next[63:0]$6028 $3\dmi0_datasr_reg$next[63:0]$6031 + attribute \src "libresoc.v:138092.5-138092.29" + switch \initial + attribute \src "libresoc.v:138092.9-138092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_reg$next[63:0]$6029 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + case + assign $1\dmi0_datasr_reg$next[63:0]$6029 \dmi0_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr_reg$next[63:0]$6030 \dmi0_datasr__i + case + assign $2\dmi0_datasr_reg$next[63:0]$6030 $1\dmi0_datasr_reg$next[63:0]$6029 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr_reg$next[63:0]$6031 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr_reg$next[63:0]$6031 $2\dmi0_datasr_reg$next[63:0]$6030 + end + sync always + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6028 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141850$5735 - parameter \WIDTH 1 - connect \A \sd0_data1__core__o - connect \B \io_bd [73] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141850$5735_Y + attribute \src "libresoc.v:138112.3-138120.6" + process $proc$libresoc.v:138112$6032 + assign { } { } + assign { } { } + assign $0\sr5_update_core$next[0:0]$6033 $1\sr5_update_core$next[0:0]$6034 + attribute \src "libresoc.v:138113.5-138113.29" + switch \initial + attribute \src "libresoc.v:138113.9-138113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core$next[0:0]$6034 1'0 + case + assign $1\sr5_update_core$next[0:0]$6034 \sr5_update + end + sync always + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6033 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141853$5738 - parameter \WIDTH 1 - connect \A \sd0_data1__core__oe - connect \B \io_bd [74] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141853$5738_Y + attribute \src "libresoc.v:138121.3-138129.6" + process $proc$libresoc.v:138121$6035 + assign { } { } + assign { } { } + assign $0\sr5_update_core_prev$next[0:0]$6036 $1\sr5_update_core_prev$next[0:0]$6037 + attribute \src "libresoc.v:138122.5-138122.29" + switch \initial + attribute \src "libresoc.v:138122.9-138122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core_prev$next[0:0]$6037 1'0 + case + assign $1\sr5_update_core_prev$next[0:0]$6037 \sr5_update_core + end + sync always + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6036 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141854$5739 - parameter \WIDTH 1 - connect \A \sd0_data2__pad__i - connect \B \io_bd [75] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141854$5739_Y + attribute \src "libresoc.v:138130.3-138146.6" + process $proc$libresoc.v:138130$6038 + assign { } { } + assign { } { } + assign $0\sr5__oe$next[0:0]$6039 $2\sr5__oe$next[0:0]$6041 + attribute \src "libresoc.v:138131.5-138131.29" + switch \initial + attribute \src "libresoc.v:138131.9-138131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$481 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__oe$next[0:0]$6040 \sr5_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr5__oe$next[0:0]$6040 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5__oe$next[0:0]$6041 1'0 + case + assign $2\sr5__oe$next[0:0]$6041 $1\sr5__oe$next[0:0]$6040 + end + sync always + update \sr5__oe$next $0\sr5__oe$next[0:0]$6039 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141855$5740 - parameter \WIDTH 1 - connect \A \sd0_data2__core__o - connect \B \io_bd [76] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141855$5740_Y + attribute \src "libresoc.v:138147.3-138167.6" + process $proc$libresoc.v:138147$6042 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr5_reg$next[2:0]$6043 $3\sr5_reg$next[2:0]$6046 + attribute \src "libresoc.v:138148.5-138148.29" + switch \initial + attribute \src "libresoc.v:138148.9-138148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr5_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_reg$next[2:0]$6044 { \TAP_bus__tdi \sr5_reg [2:1] } + case + assign $1\sr5_reg$next[2:0]$6044 \sr5_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr5_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5_reg$next[2:0]$6045 \sr5__i + case + assign $2\sr5_reg$next[2:0]$6045 $1\sr5_reg$next[2:0]$6044 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr5_reg$next[2:0]$6046 3'000 + case + assign $3\sr5_reg$next[2:0]$6046 $2\sr5_reg$next[2:0]$6045 + end + sync always + update \sr5_reg$next $0\sr5_reg$next[2:0]$6043 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141856$5741 - parameter \WIDTH 1 - connect \A \sd0_data2__core__oe - connect \B \io_bd [77] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141856$5741_Y + attribute \src "libresoc.v:138168.3-138194.6" + process $proc$libresoc.v:138168$6047 + assign { } { } + assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:138169.5-138169.29" + switch \initial + attribute \src "libresoc.v:138169.9-138169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" + switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } + attribute \src "libresoc.v:0.0-0.0" + case 6'-----1 + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'----1- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'---1-- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'--1--- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'-1---- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'1----- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\TAP_bus__tdo[0:0] \TAP_tdo + end + sync always + update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141857$5742 - parameter \WIDTH 1 - connect \A \sd0_data3__pad__i - connect \B \io_bd [78] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141857$5742_Y + attribute \src "libresoc.v:138195.3-138227.6" + process $proc$libresoc.v:138195$6048 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__adr$next[28:0]$6049 $4\jtag_wb__adr$next[28:0]$6053 + attribute \src "libresoc.v:138196.5-138196.29" + switch \initial + attribute \src "libresoc.v:138196.9-138196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$6050 $2\jtag_wb__adr$next[28:0]$6051 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$6051 \jtag_wb_addrsr__o + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$6051 \$495 [28:0] + case + assign $2\jtag_wb__adr$next[28:0]$6051 \jtag_wb__adr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$6050 $3\jtag_wb__adr$next[28:0]$6052 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__adr$next[28:0]$6052 \$498 [28:0] + case + assign $3\jtag_wb__adr$next[28:0]$6052 \jtag_wb__adr + end + case + assign $1\jtag_wb__adr$next[28:0]$6050 \jtag_wb__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\jtag_wb__adr$next[28:0]$6053 29'00000000000000000000000000000 + case + assign $4\jtag_wb__adr$next[28:0]$6053 $1\jtag_wb__adr$next[28:0]$6050 + end + sync always + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6049 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141858$5743 - parameter \WIDTH 1 - connect \A \sd0_data3__core__o - connect \B \io_bd [79] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141858$5743_Y + attribute \src "libresoc.v:138228.3-138280.6" + process $proc$libresoc.v:138228$6054 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[2:0]$6055 $5\fsm_state$next[2:0]$6060 + attribute \src "libresoc.v:138229.5-138229.29" + switch \initial + attribute \src "libresoc.v:138229.9-138229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$next[2:0]$6056 $2\fsm_state$next[2:0]$6057 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$next[2:0]$6057 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$next[2:0]$6057 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$next[2:0]$6057 3'010 + case + assign $2\fsm_state$next[2:0]$6057 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$next[2:0]$6056 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$next[2:0]$6056 $3\fsm_state$next[2:0]$6058 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[2:0]$6058 3'000 + case + assign $3\fsm_state$next[2:0]$6058 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$next[2:0]$6056 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$next[2:0]$6056 $4\fsm_state$next[2:0]$6059 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[2:0]$6059 3'001 + case + assign $4\fsm_state$next[2:0]$6059 \fsm_state + end + case + assign $1\fsm_state$next[2:0]$6056 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[2:0]$6060 3'000 + case + assign $5\fsm_state$next[2:0]$6060 $1\fsm_state$next[2:0]$6056 + end + sync always + update \fsm_state$next $0\fsm_state$next[2:0]$6055 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141859$5744 - parameter \WIDTH 1 - connect \A \sd0_data3__core__oe - connect \B \io_bd [80] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141859$5744_Y + attribute \src "libresoc.v:138281.3-138307.6" + process $proc$libresoc.v:138281$6061 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__dat_w$next[63:0]$6062 $3\jtag_wb__dat_w$next[63:0]$6065 + attribute \src "libresoc.v:138282.5-138282.29" + switch \initial + attribute \src "libresoc.v:138282.9-138282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__dat_w$next[63:0]$6063 $2\jtag_wb__dat_w$next[63:0]$6064 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\jtag_wb__dat_w$next[63:0]$6064 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\jtag_wb__dat_w$next[63:0]$6064 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\jtag_wb__dat_w$next[63:0]$6064 \jtag_wb_datasr__o + case + assign $2\jtag_wb__dat_w$next[63:0]$6064 \jtag_wb__dat_w + end + case + assign $1\jtag_wb__dat_w$next[63:0]$6063 \jtag_wb__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__dat_w$next[63:0]$6065 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb__dat_w$next[63:0]$6065 $1\jtag_wb__dat_w$next[63:0]$6063 + end + sync always + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6062 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141860$5745 - parameter \WIDTH 1 - connect \A \sdr_dm_0__core__o - connect \B \io_bd [81] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141860$5745_Y + attribute \src "libresoc.v:138308.3-138328.6" + process $proc$libresoc.v:138308$6066 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__i$next[63:0]$6067 $3\jtag_wb_datasr__i$next[63:0]$6070 + attribute \src "libresoc.v:138309.5-138309.29" + switch \initial + attribute \src "libresoc.v:138309.9-138309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\jtag_wb_datasr__i$next[63:0]$6068 $2\jtag_wb_datasr__i$next[63:0]$6069 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__i$next[63:0]$6069 \jtag_wb__dat_r + case + assign $2\jtag_wb_datasr__i$next[63:0]$6069 \jtag_wb_datasr__i + end + case + assign $1\jtag_wb_datasr__i$next[63:0]$6068 \jtag_wb_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr__i$next[63:0]$6070 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr__i$next[63:0]$6070 $1\jtag_wb_datasr__i$next[63:0]$6068 + end + sync always + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6067 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141861$5746 - parameter \WIDTH 1 - connect \A \sdr_dq_0__pad__i - connect \B \io_bd [82] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141861$5746_Y + attribute \src "libresoc.v:138329.3-138361.6" + process $proc$libresoc.v:138329$6071 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__addr_i$next[3:0]$6072 $4\dmi0__addr_i$next[3:0]$6076 + attribute \src "libresoc.v:138330.5-138330.29" + switch \initial + attribute \src "libresoc.v:138330.9-138330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$6073 $2\dmi0__addr_i$next[3:0]$6074 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$6074 \dmi0_addrsr__o [3:0] + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$6074 \$512 [3:0] + case + assign $2\dmi0__addr_i$next[3:0]$6074 \dmi0__addr_i + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$6073 $3\dmi0__addr_i$next[3:0]$6075 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__addr_i$next[3:0]$6075 \$515 [3:0] + case + assign $3\dmi0__addr_i$next[3:0]$6075 \dmi0__addr_i + end + case + assign $1\dmi0__addr_i$next[3:0]$6073 \dmi0__addr_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dmi0__addr_i$next[3:0]$6076 4'0000 + case + assign $4\dmi0__addr_i$next[3:0]$6076 $1\dmi0__addr_i$next[3:0]$6073 + end + sync always + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6072 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141862$5747 - parameter \WIDTH 1 - connect \A \sdr_dq_0__core__o - connect \B \io_bd [83] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141862$5747_Y + attribute \src "libresoc.v:138362.3-138414.6" + process $proc$libresoc.v:138362$6077 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$503$next[2:0]$6078 $5\fsm_state$503$next[2:0]$6083 + attribute \src "libresoc.v:138363.5-138363.29" + switch \initial + attribute \src "libresoc.v:138363.9-138363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$503$next[2:0]$6079 $2\fsm_state$503$next[2:0]$6080 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$503$next[2:0]$6080 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$503$next[2:0]$6080 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$503$next[2:0]$6080 3'010 + case + assign $2\fsm_state$503$next[2:0]$6080 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$503$next[2:0]$6079 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$503$next[2:0]$6079 $3\fsm_state$503$next[2:0]$6081 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$503$next[2:0]$6081 3'000 + case + assign $3\fsm_state$503$next[2:0]$6081 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$503$next[2:0]$6079 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$503$next[2:0]$6079 $4\fsm_state$503$next[2:0]$6082 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$503$next[2:0]$6082 3'001 + case + assign $4\fsm_state$503$next[2:0]$6082 \fsm_state$503 + end + case + assign $1\fsm_state$503$next[2:0]$6079 \fsm_state$503 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$503$next[2:0]$6083 3'000 + case + assign $5\fsm_state$503$next[2:0]$6083 $1\fsm_state$503$next[2:0]$6079 + end + sync always + update \fsm_state$503$next $0\fsm_state$503$next[2:0]$6078 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141864$5749 - parameter \WIDTH 1 - connect \A \sdr_dq_0__core__oe - connect \B \io_bd [84] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141864$5749_Y + attribute \src "libresoc.v:138415.3-138441.6" + process $proc$libresoc.v:138415$6084 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__din$next[63:0]$6085 $3\dmi0__din$next[63:0]$6088 + attribute \src "libresoc.v:138416.5-138416.29" + switch \initial + attribute \src "libresoc.v:138416.9-138416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__din$next[63:0]$6086 $2\dmi0__din$next[63:0]$6087 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\dmi0__din$next[63:0]$6087 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\dmi0__din$next[63:0]$6087 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\dmi0__din$next[63:0]$6087 \dmi0_datasr__o + case + assign $2\dmi0__din$next[63:0]$6087 \dmi0__din + end + case + assign $1\dmi0__din$next[63:0]$6086 \dmi0__din + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__din$next[63:0]$6088 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0__din$next[63:0]$6088 $1\dmi0__din$next[63:0]$6086 + end + sync always + update \dmi0__din$next $0\dmi0__din$next[63:0]$6085 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141865$5750 - parameter \WIDTH 1 - connect \A \sdr_dq_1__pad__i - connect \B \io_bd [85] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141865$5750_Y + attribute \src "libresoc.v:138442.3-138462.6" + process $proc$libresoc.v:138442$6089 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr__i$next[63:0]$6090 $3\dmi0_datasr__i$next[63:0]$6093 + attribute \src "libresoc.v:138443.5-138443.29" + switch \initial + attribute \src "libresoc.v:138443.9-138443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\dmi0_datasr__i$next[63:0]$6091 $2\dmi0_datasr__i$next[63:0]$6092 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__i$next[63:0]$6092 \dmi0__dout + case + assign $2\dmi0_datasr__i$next[63:0]$6092 \dmi0_datasr__i + end + case + assign $1\dmi0_datasr__i$next[63:0]$6091 \dmi0_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr__i$next[63:0]$6093 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr__i$next[63:0]$6093 $1\dmi0_datasr__i$next[63:0]$6091 + end + sync always + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6090 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141866$5751 - parameter \WIDTH 1 - connect \A \sdr_dq_1__core__o - connect \B \io_bd [86] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141866$5751_Y + attribute \src "libresoc.v:138463.3-138483.6" + process $proc$libresoc.v:138463$6094 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\wb_dcache_en$next[0:0]$6095 $2\wb_dcache_en$next[0:0]$6101 + assign $0\wb_icache_en$next[0:0]$6096 $2\wb_icache_en$next[0:0]$6102 + assign $0\wb_sram_en$next[0:0]$6097 $2\wb_sram_en$next[0:0]$6103 + attribute \src "libresoc.v:138464.5-138464.29" + switch \initial + attribute \src "libresoc.v:138464.9-138464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:106" + switch \sr5__oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\wb_sram_en$next[0:0]$6100 $1\wb_dcache_en$next[0:0]$6098 $1\wb_icache_en$next[0:0]$6099 } \sr5__o + case + assign $1\wb_dcache_en$next[0:0]$6098 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$6099 \wb_icache_en + assign $1\wb_sram_en$next[0:0]$6100 \wb_sram_en + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $2\wb_icache_en$next[0:0]$6102 1'1 + assign $2\wb_dcache_en$next[0:0]$6101 1'1 + assign $2\wb_sram_en$next[0:0]$6103 1'1 + case + assign $2\wb_dcache_en$next[0:0]$6101 $1\wb_dcache_en$next[0:0]$6098 + assign $2\wb_icache_en$next[0:0]$6102 $1\wb_icache_en$next[0:0]$6099 + assign $2\wb_sram_en$next[0:0]$6103 $1\wb_sram_en$next[0:0]$6100 + end + sync always + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6095 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6096 + update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6097 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141867$5752 - parameter \WIDTH 1 - connect \A \sdr_dq_1__core__oe - connect \B \io_bd [87] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141867$5752_Y + attribute \src "libresoc.v:138484.3-138493.6" + process $proc$libresoc.v:138484$6104 + assign { } { } + assign { } { } + assign $0\sr5__i[2:0] $1\sr5__i[2:0] + attribute \src "libresoc.v:138485.5-138485.29" + switch \initial + attribute \src "libresoc.v:138485.9-138485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:109" + switch \sr5__ie + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__i[2:0] { \wb_sram_en \wb_dcache_en \wb_icache_en } + case + assign $1\sr5__i[2:0] 3'000 + end + sync always + update \sr5__i $0\sr5__i[2:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141868$5753 - parameter \WIDTH 1 - connect \A \sdr_dq_2__pad__i - connect \B \io_bd [88] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141868$5753_Y + attribute \src "libresoc.v:138494.3-138511.6" + process $proc$libresoc.v:138494$6105 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_sr$next[153:0]$6106 $2\io_sr$next[153:0]$6108 + attribute \src "libresoc.v:138495.5-138495.29" + switch \initial + attribute \src "libresoc.v:138495.9-138495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\io_sr$next[153:0]$6107 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\io_sr$next[153:0]$6107 { \io_sr [152:0] \TAP_bus__tdi } + case + assign $1\io_sr$next[153:0]$6107 \io_sr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_sr$next[153:0]$6108 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_sr$next[153:0]$6108 $1\io_sr$next[153:0]$6107 + end + sync always + update \io_sr$next $0\io_sr$next[153:0]$6106 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141869$5754 - parameter \WIDTH 1 - connect \A \sdr_dq_2__core__o - connect \B \io_bd [89] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141869$5754_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141870$5755 - parameter \WIDTH 1 - connect \A \sdr_dq_2__core__oe - connect \B \io_bd [90] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141870$5755_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141871$5756 - parameter \WIDTH 1 - connect \A \sdr_dq_3__pad__i - connect \B \io_bd [91] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141871$5756_Y + attribute \src "libresoc.v:138512.3-138532.6" + process $proc$libresoc.v:138512$6109 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_bd$next[153:0]$6110 $2\io_bd$next[153:0]$6112 + attribute \src "libresoc.v:138513.5-138513.29" + switch \initial + attribute \src "libresoc.v:138513.9-138513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\io_bd$next[153:0]$6111 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\io_bd$next[153:0]$6111 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\io_bd$next[153:0]$6111 \io_sr + case + assign $1\io_bd$next[153:0]$6111 \io_bd + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \negjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_bd$next[153:0]$6112 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[153:0]$6112 $1\io_bd$next[153:0]$6111 + end + sync always + update \io_bd$next $0\io_bd$next[153:0]$6110 + end + connect \$9 $eq$libresoc.v:137451$5661_Y + connect \$99 $ternary$libresoc.v:137452$5662_Y + connect \$101 $ternary$libresoc.v:137453$5663_Y + connect \$103 $ternary$libresoc.v:137454$5664_Y + connect \$105 $ternary$libresoc.v:137455$5665_Y + connect \$107 $ternary$libresoc.v:137456$5666_Y + connect \$109 $ternary$libresoc.v:137457$5667_Y + connect \$111 $ternary$libresoc.v:137458$5668_Y + connect \$113 $ternary$libresoc.v:137459$5669_Y + connect \$115 $ternary$libresoc.v:137460$5670_Y + connect \$117 $ternary$libresoc.v:137461$5671_Y + connect \$11 $eq$libresoc.v:137462$5672_Y + connect \$119 $ternary$libresoc.v:137463$5673_Y + connect \$121 $ternary$libresoc.v:137464$5674_Y + connect \$123 $ternary$libresoc.v:137465$5675_Y + connect \$125 $ternary$libresoc.v:137466$5676_Y + connect \$127 $ternary$libresoc.v:137467$5677_Y + connect \$129 $ternary$libresoc.v:137468$5678_Y + connect \$131 $ternary$libresoc.v:137469$5679_Y + connect \$133 $ternary$libresoc.v:137470$5680_Y + connect \$135 $ternary$libresoc.v:137471$5681_Y + connect \$137 $ternary$libresoc.v:137472$5682_Y + connect \$13 $eq$libresoc.v:137473$5683_Y + connect \$139 $ternary$libresoc.v:137474$5684_Y + connect \$141 $ternary$libresoc.v:137475$5685_Y + connect \$143 $ternary$libresoc.v:137476$5686_Y + connect \$145 $ternary$libresoc.v:137477$5687_Y + connect \$147 $ternary$libresoc.v:137478$5688_Y + connect \$149 $ternary$libresoc.v:137479$5689_Y + connect \$151 $ternary$libresoc.v:137480$5690_Y + connect \$153 $ternary$libresoc.v:137481$5691_Y + connect \$155 $ternary$libresoc.v:137482$5692_Y + connect \$157 $ternary$libresoc.v:137483$5693_Y + connect \$15 $or$libresoc.v:137484$5694_Y + connect \$159 $ternary$libresoc.v:137485$5695_Y + connect \$161 $ternary$libresoc.v:137486$5696_Y + connect \$163 $ternary$libresoc.v:137487$5697_Y + connect \$165 $ternary$libresoc.v:137488$5698_Y + connect \$167 $ternary$libresoc.v:137489$5699_Y + connect \$169 $ternary$libresoc.v:137490$5700_Y + connect \$171 $ternary$libresoc.v:137491$5701_Y + connect \$173 $ternary$libresoc.v:137492$5702_Y + connect \$175 $ternary$libresoc.v:137493$5703_Y + connect \$177 $ternary$libresoc.v:137494$5704_Y + connect \$17 $and$libresoc.v:137495$5705_Y + connect \$179 $ternary$libresoc.v:137496$5706_Y + connect \$181 $ternary$libresoc.v:137497$5707_Y + connect \$183 $ternary$libresoc.v:137498$5708_Y + connect \$185 $ternary$libresoc.v:137499$5709_Y + connect \$187 $ternary$libresoc.v:137500$5710_Y + connect \$189 $ternary$libresoc.v:137501$5711_Y + connect \$191 $ternary$libresoc.v:137502$5712_Y + connect \$193 $ternary$libresoc.v:137503$5713_Y + connect \$195 $ternary$libresoc.v:137504$5714_Y + connect \$197 $ternary$libresoc.v:137505$5715_Y + connect \$1 $eq$libresoc.v:137506$5716_Y + connect \$19 $eq$libresoc.v:137507$5717_Y + connect \$199 $ternary$libresoc.v:137508$5718_Y + connect \$201 $ternary$libresoc.v:137509$5719_Y + connect \$203 $ternary$libresoc.v:137510$5720_Y + connect \$205 $ternary$libresoc.v:137511$5721_Y + connect \$207 $ternary$libresoc.v:137512$5722_Y + connect \$209 $ternary$libresoc.v:137513$5723_Y + connect \$211 $ternary$libresoc.v:137514$5724_Y + connect \$213 $ternary$libresoc.v:137515$5725_Y + connect \$215 $ternary$libresoc.v:137516$5726_Y + connect \$217 $ternary$libresoc.v:137517$5727_Y + connect \$21 $eq$libresoc.v:137518$5728_Y + connect \$219 $ternary$libresoc.v:137519$5729_Y + connect \$221 $ternary$libresoc.v:137520$5730_Y + connect \$223 $ternary$libresoc.v:137521$5731_Y + connect \$225 $ternary$libresoc.v:137522$5732_Y + connect \$227 $ternary$libresoc.v:137523$5733_Y + connect \$229 $ternary$libresoc.v:137524$5734_Y + connect \$231 $ternary$libresoc.v:137525$5735_Y + connect \$233 $ternary$libresoc.v:137526$5736_Y + connect \$235 $ternary$libresoc.v:137527$5737_Y + connect \$237 $ternary$libresoc.v:137528$5738_Y + connect \$23 $or$libresoc.v:137529$5739_Y + connect \$239 $ternary$libresoc.v:137530$5740_Y + connect \$241 $ternary$libresoc.v:137531$5741_Y + connect \$243 $ternary$libresoc.v:137532$5742_Y + connect \$245 $ternary$libresoc.v:137533$5743_Y + connect \$247 $ternary$libresoc.v:137534$5744_Y + connect \$249 $ternary$libresoc.v:137535$5745_Y + connect \$251 $ternary$libresoc.v:137536$5746_Y + connect \$253 $ternary$libresoc.v:137537$5747_Y + connect \$255 $ternary$libresoc.v:137538$5748_Y + connect \$257 $ternary$libresoc.v:137539$5749_Y + connect \$25 $eq$libresoc.v:137540$5750_Y + connect \$259 $ternary$libresoc.v:137541$5751_Y + connect \$261 $ternary$libresoc.v:137542$5752_Y + connect \$263 $ternary$libresoc.v:137543$5753_Y + connect \$265 $ternary$libresoc.v:137544$5754_Y + connect \$267 $ternary$libresoc.v:137545$5755_Y + connect \$269 $ternary$libresoc.v:137546$5756_Y + connect \$271 $ternary$libresoc.v:137547$5757_Y + connect \$273 $ternary$libresoc.v:137548$5758_Y + connect \$275 $ternary$libresoc.v:137549$5759_Y + connect \$277 $ternary$libresoc.v:137550$5760_Y + connect \$27 $or$libresoc.v:137551$5761_Y + connect \$279 $ternary$libresoc.v:137552$5762_Y + connect \$281 $ternary$libresoc.v:137553$5763_Y + connect \$283 $ternary$libresoc.v:137554$5764_Y + connect \$285 $ternary$libresoc.v:137555$5765_Y + connect \$287 $ternary$libresoc.v:137556$5766_Y + connect \$289 $ternary$libresoc.v:137557$5767_Y + connect \$291 $ternary$libresoc.v:137558$5768_Y + connect \$293 $ternary$libresoc.v:137559$5769_Y + connect \$295 $ternary$libresoc.v:137560$5770_Y + connect \$297 $ternary$libresoc.v:137561$5771_Y + connect \$29 $and$libresoc.v:137562$5772_Y + connect \$299 $ternary$libresoc.v:137563$5773_Y + connect \$301 $ternary$libresoc.v:137564$5774_Y + connect \$303 $ternary$libresoc.v:137565$5775_Y + connect \$305 $ternary$libresoc.v:137566$5776_Y + connect \$307 $ternary$libresoc.v:137567$5777_Y + connect \$309 $ternary$libresoc.v:137568$5778_Y + connect \$311 $ternary$libresoc.v:137569$5779_Y + connect \$313 $ternary$libresoc.v:137570$5780_Y + connect \$315 $ternary$libresoc.v:137571$5781_Y + connect \$317 $ternary$libresoc.v:137572$5782_Y + connect \$31 $and$libresoc.v:137573$5783_Y + connect \$319 $ternary$libresoc.v:137574$5784_Y + connect \$321 $ternary$libresoc.v:137575$5785_Y + connect \$323 $ternary$libresoc.v:137576$5786_Y + connect \$325 $ternary$libresoc.v:137577$5787_Y + connect \$327 $ternary$libresoc.v:137578$5788_Y + connect \$329 $ternary$libresoc.v:137579$5789_Y + connect \$331 $ternary$libresoc.v:137580$5790_Y + connect \$333 $ternary$libresoc.v:137581$5791_Y + connect \$335 $ternary$libresoc.v:137582$5792_Y + connect \$337 $ternary$libresoc.v:137583$5793_Y + connect \$33 $eq$libresoc.v:137584$5794_Y + connect \$339 $ternary$libresoc.v:137585$5795_Y + connect \$341 $ternary$libresoc.v:137586$5796_Y + connect \$343 $ternary$libresoc.v:137587$5797_Y + connect \$345 $ternary$libresoc.v:137588$5798_Y + connect \$347 $ternary$libresoc.v:137589$5799_Y + connect \$349 $ternary$libresoc.v:137590$5800_Y + connect \$351 $ternary$libresoc.v:137591$5801_Y + connect \$353 $ternary$libresoc.v:137592$5802_Y + connect \$355 $ternary$libresoc.v:137593$5803_Y + connect \$357 $ternary$libresoc.v:137594$5804_Y + connect \$35 $eq$libresoc.v:137595$5805_Y + connect \$359 $eq$libresoc.v:137596$5806_Y + connect \$361 $eq$libresoc.v:137597$5807_Y + connect \$363 $or$libresoc.v:137598$5808_Y + connect \$365 $eq$libresoc.v:137599$5809_Y + connect \$367 $or$libresoc.v:137600$5810_Y + connect \$369 $and$libresoc.v:137601$5811_Y + connect \$371 $eq$libresoc.v:137602$5812_Y + connect \$373 $ne$libresoc.v:137603$5813_Y + connect \$375 $and$libresoc.v:137604$5814_Y + connect \$377 $ne$libresoc.v:137605$5815_Y + connect \$37 $or$libresoc.v:137606$5816_Y + connect \$379 $and$libresoc.v:137607$5817_Y + connect \$381 $ne$libresoc.v:137608$5818_Y + connect \$383 $and$libresoc.v:137609$5819_Y + connect \$385 $not$libresoc.v:137610$5820_Y + connect \$387 $and$libresoc.v:137611$5821_Y + connect \$389 $eq$libresoc.v:137612$5822_Y + connect \$391 $ne$libresoc.v:137613$5823_Y + connect \$393 $and$libresoc.v:137614$5824_Y + connect \$395 $ne$libresoc.v:137615$5825_Y + connect \$397 $and$libresoc.v:137616$5826_Y + connect \$3 $eq$libresoc.v:137617$5827_Y + connect \$39 $eq$libresoc.v:137618$5828_Y + connect \$399 $ne$libresoc.v:137619$5829_Y + connect \$401 $and$libresoc.v:137620$5830_Y + connect \$403 $not$libresoc.v:137621$5831_Y + connect \$405 $and$libresoc.v:137622$5832_Y + connect \$407 $eq$libresoc.v:137623$5833_Y + connect \$409 $eq$libresoc.v:137624$5834_Y + connect \$411 $ne$libresoc.v:137625$5835_Y + connect \$413 $and$libresoc.v:137626$5836_Y + connect \$415 $ne$libresoc.v:137627$5837_Y + connect \$417 $and$libresoc.v:137628$5838_Y + connect \$41 $or$libresoc.v:137629$5839_Y + connect \$419 $ne$libresoc.v:137630$5840_Y + connect \$421 $and$libresoc.v:137631$5841_Y + connect \$423 $not$libresoc.v:137632$5842_Y + connect \$425 $and$libresoc.v:137633$5843_Y + connect \$427 $eq$libresoc.v:137634$5844_Y + connect \$429 $ne$libresoc.v:137635$5845_Y + connect \$431 $and$libresoc.v:137636$5846_Y + connect \$433 $ne$libresoc.v:137637$5847_Y + connect \$435 $and$libresoc.v:137638$5848_Y + connect \$437 $ne$libresoc.v:137639$5849_Y + connect \$43 $and$libresoc.v:137640$5850_Y + connect \$439 $and$libresoc.v:137641$5851_Y + connect \$441 $not$libresoc.v:137642$5852_Y + connect \$443 $and$libresoc.v:137643$5853_Y + connect \$445 $eq$libresoc.v:137644$5854_Y + connect \$447 $eq$libresoc.v:137645$5855_Y + connect \$449 $ne$libresoc.v:137646$5856_Y + connect \$451 $and$libresoc.v:137647$5857_Y + connect \$453 $ne$libresoc.v:137648$5858_Y + connect \$455 $and$libresoc.v:137649$5859_Y + connect \$457 $ne$libresoc.v:137650$5860_Y + connect \$45 $and$libresoc.v:137651$5861_Y + connect \$459 $and$libresoc.v:137652$5862_Y + connect \$461 $not$libresoc.v:137653$5863_Y + connect \$463 $and$libresoc.v:137654$5864_Y + connect \$465 $eq$libresoc.v:137655$5865_Y + connect \$467 $ne$libresoc.v:137656$5866_Y + connect \$469 $and$libresoc.v:137657$5867_Y + connect \$471 $ne$libresoc.v:137658$5868_Y + connect \$473 $and$libresoc.v:137659$5869_Y + connect \$475 $ne$libresoc.v:137660$5870_Y + connect \$477 $and$libresoc.v:137661$5871_Y + connect \$47 $eq$libresoc.v:137662$5872_Y + connect \$479 $not$libresoc.v:137663$5873_Y + connect \$481 $and$libresoc.v:137664$5874_Y + connect \$484 $eq$libresoc.v:137665$5875_Y + connect \$483 $not$libresoc.v:137666$5876_Y + connect \$487 $eq$libresoc.v:137667$5877_Y + connect \$489 $eq$libresoc.v:137668$5878_Y + connect \$491 $or$libresoc.v:137669$5879_Y + connect \$493 $eq$libresoc.v:137670$5880_Y + connect \$496 $add$libresoc.v:137671$5881_Y + connect \$49 $eq$libresoc.v:137672$5882_Y + connect \$499 $add$libresoc.v:137673$5883_Y + connect \$501 $pos$libresoc.v:137674$5885_Y + connect \$504 $eq$libresoc.v:137675$5886_Y + connect \$506 $eq$libresoc.v:137676$5887_Y + connect \$508 $or$libresoc.v:137677$5888_Y + connect \$510 $eq$libresoc.v:137678$5889_Y + connect \$513 $add$libresoc.v:137679$5890_Y + connect \$516 $add$libresoc.v:137680$5891_Y + connect \$51 $ternary$libresoc.v:137681$5892_Y + connect \$53 $ternary$libresoc.v:137682$5893_Y + connect \$55 $ternary$libresoc.v:137683$5894_Y + connect \$57 $ternary$libresoc.v:137684$5895_Y + connect \$5 $or$libresoc.v:137685$5896_Y + connect \$59 $ternary$libresoc.v:137686$5897_Y + connect \$61 $ternary$libresoc.v:137687$5898_Y + connect \$63 $ternary$libresoc.v:137688$5899_Y + connect \$65 $ternary$libresoc.v:137689$5900_Y + connect \$67 $ternary$libresoc.v:137690$5901_Y + connect \$69 $ternary$libresoc.v:137691$5902_Y + connect \$71 $ternary$libresoc.v:137692$5903_Y + connect \$73 $ternary$libresoc.v:137693$5904_Y + connect \$75 $ternary$libresoc.v:137694$5905_Y + connect \$77 $ternary$libresoc.v:137695$5906_Y + connect \$7 $and$libresoc.v:137696$5907_Y + connect \$79 $ternary$libresoc.v:137697$5908_Y + connect \$81 $ternary$libresoc.v:137698$5909_Y + connect \$83 $ternary$libresoc.v:137699$5910_Y + connect \$85 $ternary$libresoc.v:137700$5911_Y + connect \$87 $ternary$libresoc.v:137701$5912_Y + connect \$89 $ternary$libresoc.v:137702$5913_Y + connect \$91 $ternary$libresoc.v:137703$5914_Y + connect \$93 $ternary$libresoc.v:137704$5915_Y + connect \$95 $ternary$libresoc.v:137705$5916_Y + connect \$97 $ternary$libresoc.v:137706$5917_Y + connect \$495 \$496 + connect \$498 \$499 + connect \$512 \$513 + connect \$515 \$516 + connect \sr5__ie 1'0 + connect \sr0__i \sr0__o + connect \dmi0__we_i \$510 + connect \dmi0__req_i \$508 + connect \dmi0_addrsr__i \$501 + connect \jtag_wb__we \$493 + connect \jtag_wb__stb \$491 + connect \jtag_wb__cyc \$483 + connect \jtag_wb__sel 1'1 + connect \jtag_wb_addrsr__i \jtag_wb__adr + connect \sr5_update \$477 + connect \sr5_shift \$473 + connect \sr5_capture \$469 + connect \sr5_isir \$465 + connect \sr5__o \sr5_reg + connect \dmi0_datasr_update \$459 + connect \dmi0_datasr_shift \$455 + connect \dmi0_datasr_capture \$451 + connect \dmi0_datasr_isir { \$447 \$445 } + connect \dmi0_datasr__o \dmi0_datasr_reg + connect \dmi0_addrsr_update \$439 + connect \dmi0_addrsr_shift \$435 + connect \dmi0_addrsr_capture \$431 + connect \dmi0_addrsr_isir \$427 + connect \dmi0_addrsr__o \dmi0_addrsr_reg + connect \jtag_wb_datasr_update \$421 + connect \jtag_wb_datasr_shift \$417 + connect \jtag_wb_datasr_capture \$413 + connect \jtag_wb_datasr_isir { \$409 \$407 } + connect \jtag_wb_datasr__o \jtag_wb_datasr_reg + connect \jtag_wb_addrsr_update \$401 + connect \jtag_wb_addrsr_shift \$397 + connect \jtag_wb_addrsr_capture \$393 + connect \jtag_wb_addrsr_isir \$389 + connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg + connect \sr0_update \$383 + connect \sr0_shift \$379 + connect \sr0_capture \$375 + connect \sr0_isir \$371 + connect \sr0__o \sr0_reg + connect \sdr_dq_15__pad__oe \$357 + connect \sdr_dq_15__pad__o \$355 + connect \sdr_dq_15__core__i \$353 + connect \sdr_dq_14__pad__oe \$351 + connect \sdr_dq_14__pad__o \$349 + connect \sdr_dq_14__core__i \$347 + connect \sdr_dq_13__pad__oe \$345 + connect \sdr_dq_13__pad__o \$343 + connect \sdr_dq_13__core__i \$341 + connect \sdr_dq_12__pad__oe \$339 + connect \sdr_dq_12__pad__o \$337 + connect \sdr_dq_12__core__i \$335 + connect \sdr_dq_11__pad__oe \$333 + connect \sdr_dq_11__pad__o \$331 + connect \sdr_dq_11__core__i \$329 + connect \sdr_dq_10__pad__oe \$327 + connect \sdr_dq_10__pad__o \$325 + connect \sdr_dq_10__core__i \$323 + connect \sdr_dq_9__pad__oe \$321 + connect \sdr_dq_9__pad__o \$319 + connect \sdr_dq_9__core__i \$317 + connect \sdr_dq_8__pad__oe \$315 + connect \sdr_dq_8__pad__o \$313 + connect \sdr_dq_8__core__i \$311 + connect \sdr_dm_1__pad__oe \$309 + connect \sdr_dm_1__pad__o \$307 + connect \sdr_dm_1__core__i \$305 + connect \sdr_a_12__pad__o \$303 + connect \sdr_a_11__pad__o \$301 + connect \sdr_a_10__pad__o \$299 + connect \sdr_cs_n__pad__o \$297 + connect \sdr_we_n__pad__o \$295 + connect \sdr_cas_n__pad__o \$293 + connect \sdr_ras_n__pad__o \$291 + connect \sdr_cke__pad__o \$289 + connect \sdr_clock__pad__o \$287 + connect \sdr_ba_1__pad__o \$285 + connect \sdr_ba_0__pad__o \$283 + connect \sdr_a_9__pad__o \$281 + connect \sdr_a_8__pad__o \$279 + connect \sdr_a_7__pad__o \$277 + connect \sdr_a_6__pad__o \$275 + connect \sdr_a_5__pad__o \$273 + connect \sdr_a_4__pad__o \$271 + connect \sdr_a_3__pad__o \$269 + connect \sdr_a_2__pad__o \$267 + connect \sdr_a_1__pad__o \$265 + connect \sdr_a_0__pad__o \$263 + connect \sdr_dq_7__pad__oe \$261 + connect \sdr_dq_7__pad__o \$259 + connect \sdr_dq_7__core__i \$257 + connect \sdr_dq_6__pad__oe \$255 + connect \sdr_dq_6__pad__o \$253 + connect \sdr_dq_6__core__i \$251 + connect \sdr_dq_5__pad__oe \$249 + connect \sdr_dq_5__pad__o \$247 + connect \sdr_dq_5__core__i \$245 + connect \sdr_dq_4__pad__oe \$243 + connect \sdr_dq_4__pad__o \$241 + connect \sdr_dq_4__core__i \$239 + connect \sdr_dq_3__pad__oe \$237 + connect \sdr_dq_3__pad__o \$235 + connect \sdr_dq_3__core__i \$233 + connect \sdr_dq_2__pad__oe \$231 + connect \sdr_dq_2__pad__o \$229 + connect \sdr_dq_2__core__i \$227 + connect \sdr_dq_1__pad__oe \$225 + connect \sdr_dq_1__pad__o \$223 + connect \sdr_dq_1__core__i \$221 + connect \sdr_dq_0__pad__oe \$219 + connect \sdr_dq_0__pad__o \$217 + connect \sdr_dq_0__core__i \$215 + connect \sdr_dm_0__pad__o \$213 + connect \sd0_data3__pad__oe \$211 + connect \sd0_data3__pad__o \$209 + connect \sd0_data3__core__i \$207 + connect \sd0_data2__pad__oe \$205 + connect \sd0_data2__pad__o \$203 + connect \sd0_data2__core__i \$201 + connect \sd0_data1__pad__oe \$199 + connect \sd0_data1__pad__o \$197 + connect \sd0_data1__core__i \$195 + connect \sd0_data0__pad__oe \$193 + connect \sd0_data0__pad__o \$191 + connect \sd0_data0__core__i \$189 + connect \sd0_clk__pad__o \$187 + connect \sd0_cmd__pad__oe \$185 + connect \sd0_cmd__pad__o \$183 + connect \sd0_cmd__core__i \$181 + connect \pwm_1__pad__o \$179 + connect \pwm_0__pad__o \$177 + connect \mtwi_scl__pad__o \$175 + connect \mtwi_sda__pad__oe \$173 + connect \mtwi_sda__pad__o \$171 + connect \mtwi_sda__core__i \$169 + connect \mspi1_miso__core__i \$167 + connect \mspi1_mosi__pad__o \$165 + connect \mspi1_cs_n__pad__o \$163 + connect \mspi1_clk__pad__o \$161 + connect \mspi0_miso__core__i \$159 + connect \mspi0_mosi__pad__o \$157 + connect \mspi0_cs_n__pad__o \$155 + connect \mspi0_clk__pad__o \$153 + connect \gpio_s7__pad__oe \$151 + connect \gpio_s7__pad__o \$149 + connect \gpio_s7__core__i \$147 + connect \gpio_s6__pad__oe \$145 + connect \gpio_s6__pad__o \$143 + connect \gpio_s6__core__i \$141 + connect \gpio_s5__pad__oe \$139 + connect \gpio_s5__pad__o \$137 + connect \gpio_s5__core__i \$135 + connect \gpio_s4__pad__oe \$133 + connect \gpio_s4__pad__o \$131 + connect \gpio_s4__core__i \$129 + connect \gpio_s3__pad__oe \$127 + connect \gpio_s3__pad__o \$125 + connect \gpio_s3__core__i \$123 + connect \gpio_s2__pad__oe \$121 + connect \gpio_s2__pad__o \$119 + connect \gpio_s2__core__i \$117 + connect \gpio_s1__pad__oe \$115 + connect \gpio_s1__pad__o \$113 + connect \gpio_s1__core__i \$111 + connect \gpio_s0__pad__oe \$109 + connect \gpio_s0__pad__o \$107 + connect \gpio_s0__core__i \$105 + connect \gpio_e15__pad__oe \$103 + connect \gpio_e15__pad__o \$101 + connect \gpio_e15__core__i \$99 + connect \gpio_e14__pad__oe \$97 + connect \gpio_e14__pad__o \$95 + connect \gpio_e14__core__i \$93 + connect \gpio_e13__pad__oe \$91 + connect \gpio_e13__pad__o \$89 + connect \gpio_e13__core__i \$87 + connect \gpio_e12__pad__oe \$85 + connect \gpio_e12__pad__o \$83 + connect \gpio_e12__core__i \$81 + connect \gpio_e11__pad__oe \$79 + connect \gpio_e11__pad__o \$77 + connect \gpio_e11__core__i \$75 + connect \gpio_e10__pad__oe \$73 + connect \gpio_e10__pad__o \$71 + connect \gpio_e10__core__i \$69 + connect \gpio_e9__pad__oe \$67 + connect \gpio_e9__pad__o \$65 + connect \gpio_e9__core__i \$63 + connect \gpio_e8__pad__oe \$61 + connect \gpio_e8__pad__o \$59 + connect \gpio_e8__core__i \$57 + connect \eint_2__core__i \$55 + connect \eint_1__core__i \$53 + connect \eint_0__core__i \$51 + connect \io_bd2core \$49 + connect \io_bd2io \$47 + connect \io_update \$45 + connect \io_shift \$31 + connect \io_capture \$17 + connect \_idblock_id_bypass \$9 + connect \_idblock_select_id \$7 +end +attribute \src "libresoc.v:138742.1-138931.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0" +attribute \generator "nMigen" +module \l0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 31 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 23 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 28 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 22 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 27 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 30 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 24 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 26 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 25 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 29 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 16 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 8 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 9 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 10 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 11 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 12 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 13 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 14 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 15 \ldst_port0_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 48 \pimem_ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire \pimem_ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire \pimem_ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 \pimem_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \pimem_ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire \pimem_ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire \pimem_ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pimem_ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pimem_ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" + wire width 64 \pimem_m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" + wire \pimem_m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire width 48 \pimem_x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" + wire \pimem_x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" + wire \pimem_x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" + wire width 8 \pimem_x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire width 64 \pimem_x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" + wire \pimem_x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" + wire \pimem_x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" + wire input 21 \wb_dcache_en + attribute \module_not_derived 1 + attribute \src "libresoc.v:138847.12-138881.4" + cell \l0$130 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i$12 \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_i_ok$13 \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_addr_ok_o$14 \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_busy_o$10 \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_data_len$11 \pimem_ldst_port0_data_len + connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$1 + connect \ldst_port0_exc_$signal$19 \pimem_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$2 + connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$3 + connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$4 + connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$5 + connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$6 + connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$7 + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_ld_i$8 \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_is_st_i$9 \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o$15 \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_ld_data_o_ok$16 \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i$18 \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141872$5757 - parameter \WIDTH 1 - connect \A \sdr_dq_3__core__o - connect \B \io_bd [92] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141872$5757_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:138882.9-138904.4" + cell \lsmem \lsmem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \wb_dcache_en \wb_dcache_en + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141873$5758 - parameter \WIDTH 1 - connect \A \sdr_dq_3__core__oe - connect \B \io_bd [93] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141873$5758_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:138905.9-138929.4" + cell \pimem \pimem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \pimem_ldst_port0_data_len + connect \ldst_port0_exc_$signal \pimem_ldst_port0_exc_$signal + connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141875$5760 - parameter \WIDTH 1 - connect \A \sdr_dq_4__pad__i - connect \B \io_bd [94] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141875$5760_Y + connect \pimem_ldst_port0_exc_$signal 1'0 +end +attribute \src "libresoc.v:138935.1-139343.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" +attribute \generator "nMigen" +module \l0$130 + attribute \src "libresoc.v:139198.3-139212.6" + wire $0\idx_l$23$next[0:0]$6191 + attribute \src "libresoc.v:139098.3-139099.35" + wire $0\idx_l$23[0:0]$6158 + attribute \src "libresoc.v:138956.7-138956.24" + wire $0\idx_l$23[0:0]$6213 + attribute \src "libresoc.v:139253.3-139262.6" + wire $0\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:139243.3-139252.6" + wire $0\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:138936.7-138936.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:139119.3-139128.6" + wire width 48 $0\ldst_port0_addr_i$12[47:0]$6160 + attribute \src "libresoc.v:139129.3-139138.6" + wire $0\ldst_port0_addr_i_ok$13[0:0]$6163 + attribute \src "libresoc.v:139171.3-139180.6" + wire $0\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:139161.3-139170.6" + wire $0\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:139233.3-139242.6" + wire $0\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:139308.3-139317.6" + wire width 4 $0\ldst_port0_data_len$11[3:0]$6208 + attribute \src "libresoc.v:139181.3-139197.6" + wire $0\ldst_port0_exc_$signal$1[0:0]$6175 + attribute \src "libresoc.v:139181.3-139197.6" + wire $0\ldst_port0_exc_$signal$2[0:0]$6176 + attribute \src "libresoc.v:139181.3-139197.6" + wire $0\ldst_port0_exc_$signal$3[0:0]$6177 + attribute \src "libresoc.v:139181.3-139197.6" + wire $0\ldst_port0_exc_$signal$4[0:0]$6178 + attribute \src "libresoc.v:139181.3-139197.6" + wire $0\ldst_port0_exc_$signal$5[0:0]$6179 + attribute \src "libresoc.v:139181.3-139197.6" + wire $0\ldst_port0_exc_$signal$6[0:0]$6180 + attribute \src "libresoc.v:139181.3-139197.6" + wire $0\ldst_port0_exc_$signal$7[0:0]$6181 + attribute \src "libresoc.v:139181.3-139197.6" + wire $0\ldst_port0_exc_$signal[0:0]$6174 + attribute \src "libresoc.v:139318.3-139327.6" + wire $0\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:139288.3-139297.6" + wire $0\ldst_port0_is_ld_i$8[0:0]$6202 + attribute \src "libresoc.v:139298.3-139307.6" + wire $0\ldst_port0_is_st_i$9[0:0]$6205 + attribute \src "libresoc.v:139150.3-139160.6" + wire width 64 $0\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:139150.3-139160.6" + wire $0\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:139223.3-139232.6" + wire $0\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:139213.3-139222.6" + wire $0\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:139139.3-139149.6" + wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6166 + attribute \src "libresoc.v:139139.3-139149.6" + wire $0\ldst_port0_st_data_i_ok$17[0:0]$6167 + attribute \src "libresoc.v:139096.3-139097.36" + wire $0\reset_delay[0:0] + attribute \src "libresoc.v:139278.3-139287.6" + wire $0\reset_l_r_reset[0:0] + attribute \src "libresoc.v:139263.3-139277.6" + wire $0\reset_l_s_reset[0:0] + attribute \src "libresoc.v:139198.3-139212.6" + wire $1\idx_l$23$next[0:0]$6192 + attribute \src "libresoc.v:139253.3-139262.6" + wire $1\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:139243.3-139252.6" + wire $1\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:139119.3-139128.6" + wire width 48 $1\ldst_port0_addr_i$12[47:0]$6161 + attribute \src "libresoc.v:139129.3-139138.6" + wire $1\ldst_port0_addr_i_ok$13[0:0]$6164 + attribute \src "libresoc.v:139171.3-139180.6" + wire $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:139161.3-139170.6" + wire $1\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:139233.3-139242.6" + wire $1\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:139308.3-139317.6" + wire width 4 $1\ldst_port0_data_len$11[3:0]$6209 + attribute \src "libresoc.v:139181.3-139197.6" + wire $1\ldst_port0_exc_$signal$1[0:0]$6183 + attribute \src "libresoc.v:139181.3-139197.6" + wire $1\ldst_port0_exc_$signal$2[0:0]$6184 + attribute \src "libresoc.v:139181.3-139197.6" + wire $1\ldst_port0_exc_$signal$3[0:0]$6185 + attribute \src "libresoc.v:139181.3-139197.6" + wire $1\ldst_port0_exc_$signal$4[0:0]$6186 + attribute \src "libresoc.v:139181.3-139197.6" + wire $1\ldst_port0_exc_$signal$5[0:0]$6187 + attribute \src "libresoc.v:139181.3-139197.6" + wire $1\ldst_port0_exc_$signal$6[0:0]$6188 + attribute \src "libresoc.v:139181.3-139197.6" + wire $1\ldst_port0_exc_$signal$7[0:0]$6189 + attribute \src "libresoc.v:139181.3-139197.6" + wire $1\ldst_port0_exc_$signal[0:0]$6182 + attribute \src "libresoc.v:139318.3-139327.6" + wire $1\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:139288.3-139297.6" + wire $1\ldst_port0_is_ld_i$8[0:0]$6203 + attribute \src "libresoc.v:139298.3-139307.6" + wire $1\ldst_port0_is_st_i$9[0:0]$6206 + attribute \src "libresoc.v:139150.3-139160.6" + wire width 64 $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:139150.3-139160.6" + wire $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:139223.3-139232.6" + wire $1\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:139213.3-139222.6" + wire $1\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:139139.3-139149.6" + wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6168 + attribute \src "libresoc.v:139139.3-139149.6" + wire $1\ldst_port0_st_data_i_ok$17[0:0]$6169 + attribute \src "libresoc.v:139083.7-139083.25" + wire $1\reset_delay[0:0] + attribute \src "libresoc.v:139278.3-139287.6" + wire $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:139263.3-139277.6" + wire $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:139198.3-139212.6" + wire $2\idx_l$23$next[0:0]$6193 + attribute \src "libresoc.v:139263.3-139277.6" + wire $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:139094.18-139094.103" + wire $not$libresoc.v:139094$6154_Y + attribute \src "libresoc.v:139095.18-139095.118" + wire $not$libresoc.v:139095$6155_Y + attribute \src "libresoc.v:139092.18-139092.134" + wire $or$libresoc.v:139092$6152_Y + attribute \src "libresoc.v:139093.18-139093.120" + wire $ternary$libresoc.v:139093$6153_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" + wire width 96 \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" + wire width 96 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire \idx_l$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire \idx_l$23$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \idx_l_r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \idx_l_s_idx_l + attribute \src "libresoc.v:138936.7-138936.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 48 output 25 \ldst_port0_addr_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \ldst_port0_addr_i_ok$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 16 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 27 \ldst_port0_addr_ok_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 23 \ldst_port0_busy_o$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire \ldst_port0_cache_paradox + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire \ldst_port0_cache_paradox$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 24 \ldst_port0_data_len$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 8 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 9 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 32 \ldst_port0_exc_$signal$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 10 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 11 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 12 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 13 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 14 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 15 \ldst_port0_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 21 \ldst_port0_is_ld_i$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 22 \ldst_port0_is_st_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 28 \ldst_port0_ld_data_o$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 29 \ldst_port0_ld_data_o_ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + wire \ldst_port0_ldst_error + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + wire \ldst_port0_ldst_error$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + wire \ldst_port0_mmu_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + wire \ldst_port0_mmu_done$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \ldst_port0_st_data_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \ldst_port0_st_data_i_ok$17 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire \pick_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire \pick_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire \pick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + cell $not $not$libresoc.v:139094$6154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pick_n + connect \Y $not$libresoc.v:139094$6154_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141876$5761 - parameter \WIDTH 1 - connect \A \sdr_dq_4__core__o - connect \B \io_bd [95] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141876$5761_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + cell $not $not$libresoc.v:139095$6155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o$10 + connect \Y $not$libresoc.v:139095$6155_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141877$5762 - parameter \WIDTH 1 - connect \A \sdr_dq_4__core__oe - connect \B \io_bd [96] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141877$5762_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + cell $or $or$libresoc.v:139092$6152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:139092$6152_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141878$5763 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:139093$6153 parameter \WIDTH 1 - connect \A \sdr_dq_5__pad__i - connect \B \io_bd [97] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141878$5763_Y + connect \A \idx_l$23 + connect \B \pick_o + connect \S \idx_l_q_idx_l + connect \Y $ternary$libresoc.v:139093$6153_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141879$5764 - parameter \WIDTH 1 - connect \A \sdr_dq_5__core__o - connect \B \io_bd [98] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141879$5764_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:139100.9-139106.4" + cell \idx_l \idx_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_idx_l \idx_l_q_idx_l + connect \r_idx_l \idx_l_r_idx_l + connect \s_idx_l \idx_l_s_idx_l end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141880$5765 - parameter \WIDTH 1 - connect \A \sdr_dq_5__core__oe - connect \B \io_bd [99] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141880$5765_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:139107.8-139111.4" + cell \pick \pick + connect \i \pick_i + connect \n \pick_n + connect \o \pick_o end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141881$5766 - parameter \WIDTH 1 - connect \A \sdr_dq_6__pad__i - connect \B \io_bd [100] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141881$5766_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:139112.17-139118.4" + cell \reset_l$131 \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141882$5767 - parameter \WIDTH 1 - connect \A \sdr_dq_6__core__o - connect \B \io_bd [101] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141882$5767_Y + attribute \src "libresoc.v:138936.7-138936.20" + process $proc$libresoc.v:138936$6211 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141883$5768 - parameter \WIDTH 1 - connect \A \sdr_dq_6__core__oe - connect \B \io_bd [102] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141883$5768_Y + attribute \src "libresoc.v:138956.7-138956.24" + process $proc$libresoc.v:138956$6212 + assign { } { } + assign $0\idx_l$23[0:0]$6213 1'0 + sync always + sync init + update \idx_l$23 $0\idx_l$23[0:0]$6213 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141884$5769 - parameter \WIDTH 1 - connect \A \sdr_dq_7__pad__i - connect \B \io_bd [103] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141884$5769_Y + attribute \src "libresoc.v:139083.7-139083.25" + process $proc$libresoc.v:139083$6214 + assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141886$5771 - parameter \WIDTH 1 - connect \A \sdr_dq_7__core__o - connect \B \io_bd [104] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141886$5771_Y + attribute \src "libresoc.v:139096.3-139097.36" + process $proc$libresoc.v:139096$6156 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141887$5772 - parameter \WIDTH 1 - connect \A \sdr_dq_7__core__oe - connect \B \io_bd [105] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141887$5772_Y + attribute \src "libresoc.v:139098.3-139099.35" + process $proc$libresoc.v:139098$6157 + assign { } { } + assign $0\idx_l$23[0:0]$6158 \idx_l$23$next + sync posedge \coresync_clk + update \idx_l$23 $0\idx_l$23[0:0]$6158 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141888$5773 - parameter \WIDTH 1 - connect \A \sdr_a_0__core__o - connect \B \io_bd [106] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141888$5773_Y + attribute \src "libresoc.v:139119.3-139128.6" + process $proc$libresoc.v:139119$6159 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i$12[47:0]$6160 $1\ldst_port0_addr_i$12[47:0]$6161 + attribute \src "libresoc.v:139120.5-139120.29" + switch \initial + attribute \src "libresoc.v:139120.9-139120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i$12[47:0]$6161 \$32 [47:0] + case + assign $1\ldst_port0_addr_i$12[47:0]$6161 48'000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6160 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141889$5774 - parameter \WIDTH 1 - connect \A \sdr_a_1__core__o - connect \B \io_bd [107] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141889$5774_Y + attribute \src "libresoc.v:139129.3-139138.6" + process $proc$libresoc.v:139129$6162 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$13[0:0]$6163 $1\ldst_port0_addr_i_ok$13[0:0]$6164 + attribute \src "libresoc.v:139130.5-139130.29" + switch \initial + attribute \src "libresoc.v:139130.9-139130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i_ok$13[0:0]$6164 \ldst_port0_addr_i_ok + case + assign $1\ldst_port0_addr_i_ok$13[0:0]$6164 1'0 + end + sync always + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6163 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141890$5775 - parameter \WIDTH 1 - connect \A \sdr_a_2__core__o - connect \B \io_bd [108] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141890$5775_Y + attribute \src "libresoc.v:139139.3-139149.6" + process $proc$libresoc.v:139139$6165 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_st_data_i$18[63:0]$6166 $1\ldst_port0_st_data_i$18[63:0]$6168 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$6167 $1\ldst_port0_st_data_i_ok$17[0:0]$6169 + attribute \src "libresoc.v:139140.5-139140.29" + switch \initial + attribute \src "libresoc.v:139140.9-139140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6169 $1\ldst_port0_st_data_i$18[63:0]$6168 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + case + assign $1\ldst_port0_st_data_i$18[63:0]$6168 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$6169 1'0 + end + sync always + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6166 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6167 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141891$5776 - parameter \WIDTH 1 - connect \A \sdr_a_3__core__o - connect \B \io_bd [109] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141891$5776_Y + attribute \src "libresoc.v:139150.3-139160.6" + process $proc$libresoc.v:139150$6170 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:139151.5-139151.29" + switch \initial + attribute \src "libresoc.v:139151.9-139151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$16 \ldst_port0_ld_data_o$15 } + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141892$5777 - parameter \WIDTH 1 - connect \A \sdr_a_4__core__o - connect \B \io_bd [110] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141892$5777_Y + attribute \src "libresoc.v:139161.3-139170.6" + process $proc$libresoc.v:139161$6171 + assign { } { } + assign { } { } + assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:139162.5-139162.29" + switch \initial + attribute \src "libresoc.v:139162.9-139162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$10 + case + assign $1\ldst_port0_busy_o[0:0] 1'0 + end + sync always + update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141893$5778 - parameter \WIDTH 1 - connect \A \sdr_a_5__core__o - connect \B \io_bd [111] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141893$5778_Y + attribute \src "libresoc.v:139171.3-139180.6" + process $proc$libresoc.v:139171$6172 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:139172.5-139172.29" + switch \initial + attribute \src "libresoc.v:139172.9-139172.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$14 + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141894$5779 - parameter \WIDTH 1 - connect \A \sdr_a_6__core__o - connect \B \io_bd [112] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141894$5779_Y + attribute \src "libresoc.v:139181.3-139197.6" + process $proc$libresoc.v:139181$6173 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_exc_$signal[0:0]$6174 $1\ldst_port0_exc_$signal[0:0]$6182 + assign $0\ldst_port0_exc_$signal$1[0:0]$6175 $1\ldst_port0_exc_$signal$1[0:0]$6183 + assign $0\ldst_port0_exc_$signal$2[0:0]$6176 $1\ldst_port0_exc_$signal$2[0:0]$6184 + assign $0\ldst_port0_exc_$signal$3[0:0]$6177 $1\ldst_port0_exc_$signal$3[0:0]$6185 + assign $0\ldst_port0_exc_$signal$4[0:0]$6178 $1\ldst_port0_exc_$signal$4[0:0]$6186 + assign $0\ldst_port0_exc_$signal$5[0:0]$6179 $1\ldst_port0_exc_$signal$5[0:0]$6187 + assign $0\ldst_port0_exc_$signal$6[0:0]$6180 $1\ldst_port0_exc_$signal$6[0:0]$6188 + assign $0\ldst_port0_exc_$signal$7[0:0]$6181 $1\ldst_port0_exc_$signal$7[0:0]$6189 + attribute \src "libresoc.v:139182.5-139182.29" + switch \initial + attribute \src "libresoc.v:139182.9-139182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\ldst_port0_exc_$signal$7[0:0]$6189 $1\ldst_port0_exc_$signal$6[0:0]$6188 $1\ldst_port0_exc_$signal$5[0:0]$6187 $1\ldst_port0_exc_$signal$4[0:0]$6186 $1\ldst_port0_exc_$signal$3[0:0]$6185 $1\ldst_port0_exc_$signal$2[0:0]$6184 $1\ldst_port0_exc_$signal$1[0:0]$6183 $1\ldst_port0_exc_$signal[0:0]$6182 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } + case + assign $1\ldst_port0_exc_$signal[0:0]$6182 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$6183 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$6184 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$6185 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$6186 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$6187 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$6188 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$6189 1'0 + end + sync always + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6174 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6175 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6176 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6177 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6178 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6179 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6180 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6181 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141895$5780 - parameter \WIDTH 1 - connect \A \sdr_a_7__core__o - connect \B \io_bd [113] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141895$5780_Y + attribute \src "libresoc.v:139198.3-139212.6" + process $proc$libresoc.v:139198$6190 + assign { } { } + assign { } { } + assign { } { } + assign $0\idx_l$23$next[0:0]$6191 $2\idx_l$23$next[0:0]$6193 + attribute \src "libresoc.v:139199.5-139199.29" + switch \initial + attribute \src "libresoc.v:139199.9-139199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l$23$next[0:0]$6192 \pick_o + case + assign $1\idx_l$23$next[0:0]$6192 \idx_l$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\idx_l$23$next[0:0]$6193 1'0 + case + assign $2\idx_l$23$next[0:0]$6193 $1\idx_l$23$next[0:0]$6192 + end + sync always + update \idx_l$23$next $0\idx_l$23$next[0:0]$6191 end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141897$5782 - parameter \WIDTH 1 - connect \A \sdr_a_8__core__o - connect \B \io_bd [114] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141897$5782_Y + attribute \src "libresoc.v:139213.3-139222.6" + process $proc$libresoc.v:139213$6194 + assign { } { } + assign { } { } + assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:139214.5-139214.29" + switch \initial + attribute \src "libresoc.v:139214.9-139214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_mmu_done[0:0] \ldst_port0_mmu_done$40 + case + assign $1\ldst_port0_mmu_done[0:0] 1'0 + end + sync always + update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141898$5783 - parameter \WIDTH 1 - connect \A \sdr_a_9__core__o - connect \B \io_bd [115] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141898$5783_Y + attribute \src "libresoc.v:139223.3-139232.6" + process $proc$libresoc.v:139223$6195 + assign { } { } + assign { } { } + assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:139224.5-139224.29" + switch \initial + attribute \src "libresoc.v:139224.9-139224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ldst_error[0:0] \ldst_port0_ldst_error$41 + case + assign $1\ldst_port0_ldst_error[0:0] 1'0 + end + sync always + update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141899$5784 - parameter \WIDTH 1 - connect \A \sdr_ba_0__core__o - connect \B \io_bd [116] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141899$5784_Y + attribute \src "libresoc.v:139233.3-139242.6" + process $proc$libresoc.v:139233$6196 + assign { } { } + assign { } { } + assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:139234.5-139234.29" + switch \initial + attribute \src "libresoc.v:139234.9-139234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_cache_paradox[0:0] \ldst_port0_cache_paradox$42 + case + assign $1\ldst_port0_cache_paradox[0:0] 1'0 + end + sync always + update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141900$5785 - parameter \WIDTH 1 - connect \A \sdr_ba_1__core__o - connect \B \io_bd [117] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141900$5785_Y + attribute \src "libresoc.v:139243.3-139252.6" + process $proc$libresoc.v:139243$6197 + assign { } { } + assign { } { } + assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:139244.5-139244.29" + switch \initial + attribute \src "libresoc.v:139244.9-139244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + switch \$26 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l_s_idx_l[0:0] 1'1 + case + assign $1\idx_l_s_idx_l[0:0] 1'0 + end + sync always + update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141901$5786 - parameter \WIDTH 1 - connect \A \sdr_clock__core__o - connect \B \io_bd [118] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141901$5786_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141902$5787 - parameter \WIDTH 1 - connect \A \sdr_cke__core__o - connect \B \io_bd [119] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141902$5787_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141903$5788 - parameter \WIDTH 1 - connect \A \sdr_ras_n__core__o - connect \B \io_bd [120] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141903$5788_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141904$5789 - parameter \WIDTH 1 - connect \A \sdr_cas_n__core__o - connect \B \io_bd [121] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141904$5789_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141905$5790 - parameter \WIDTH 1 - connect \A \sdr_we_n__core__o - connect \B \io_bd [122] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141905$5790_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141906$5791 - parameter \WIDTH 1 - connect \A \sdr_cs_n__core__o - connect \B \io_bd [123] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141906$5791_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141908$5793 - parameter \WIDTH 1 - connect \A \sdr_a_10__core__o - connect \B \io_bd [124] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141908$5793_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141909$5794 - parameter \WIDTH 1 - connect \A \sdr_a_11__core__o - connect \B \io_bd [125] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141909$5794_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:141910$5795 - parameter \WIDTH 1 - connect \A \sdr_a_12__core__o - connect \B \io_bd [126] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141910$5795_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141911$5796 - parameter \WIDTH 1 - connect \A \sdr_dm_1__pad__i - connect \B \io_bd [127] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141911$5796_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141912$5797 - parameter \WIDTH 1 - connect \A \sdr_dm_1__core__o - connect \B \io_bd [128] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141912$5797_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141913$5798 - parameter \WIDTH 1 - connect \A \sdr_dm_1__core__oe - connect \B \io_bd [129] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141913$5798_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141914$5799 - parameter \WIDTH 1 - connect \A \sdr_dq_8__pad__i - connect \B \io_bd [130] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141914$5799_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141915$5800 - parameter \WIDTH 1 - connect \A \sdr_dq_8__core__o - connect \B \io_bd [131] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141915$5800_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141916$5801 - parameter \WIDTH 1 - connect \A \sdr_dq_8__core__oe - connect \B \io_bd [132] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141916$5801_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141917$5802 - parameter \WIDTH 1 - connect \A \sdr_dq_9__pad__i - connect \B \io_bd [133] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141917$5802_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141919$5804 - parameter \WIDTH 1 - connect \A \sdr_dq_9__core__o - connect \B \io_bd [134] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141919$5804_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141920$5805 - parameter \WIDTH 1 - connect \A \sdr_dq_9__core__oe - connect \B \io_bd [135] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141920$5805_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141921$5806 - parameter \WIDTH 1 - connect \A \sdr_dq_10__pad__i - connect \B \io_bd [136] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141921$5806_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141922$5807 - parameter \WIDTH 1 - connect \A \sdr_dq_10__core__o - connect \B \io_bd [137] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141922$5807_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141923$5808 - parameter \WIDTH 1 - connect \A \sdr_dq_10__core__oe - connect \B \io_bd [138] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141923$5808_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141924$5809 - parameter \WIDTH 1 - connect \A \sdr_dq_11__pad__i - connect \B \io_bd [139] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141924$5809_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141925$5810 - parameter \WIDTH 1 - connect \A \sdr_dq_11__core__o - connect \B \io_bd [140] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141925$5810_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141926$5811 - parameter \WIDTH 1 - connect \A \sdr_dq_11__core__oe - connect \B \io_bd [141] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141926$5811_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141927$5812 - parameter \WIDTH 1 - connect \A \sdr_dq_12__pad__i - connect \B \io_bd [142] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141927$5812_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141928$5813 - parameter \WIDTH 1 - connect \A \sdr_dq_12__core__o - connect \B \io_bd [143] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141928$5813_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141930$5815 - parameter \WIDTH 1 - connect \A \sdr_dq_12__core__oe - connect \B \io_bd [144] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141930$5815_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141931$5816 - parameter \WIDTH 1 - connect \A \sdr_dq_13__pad__i - connect \B \io_bd [145] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141931$5816_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141932$5817 - parameter \WIDTH 1 - connect \A \sdr_dq_13__core__o - connect \B \io_bd [146] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141932$5817_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141933$5818 - parameter \WIDTH 1 - connect \A \sdr_dq_13__core__oe - connect \B \io_bd [147] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141933$5818_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141934$5819 - parameter \WIDTH 1 - connect \A \sdr_dq_14__pad__i - connect \B \io_bd [148] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141934$5819_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141935$5820 - parameter \WIDTH 1 - connect \A \sdr_dq_14__core__o - connect \B \io_bd [149] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141935$5820_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141936$5821 - parameter \WIDTH 1 - connect \A \sdr_dq_14__core__oe - connect \B \io_bd [150] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141936$5821_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:141937$5822 - parameter \WIDTH 1 - connect \A \sdr_dq_15__pad__i - connect \B \io_bd [151] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:141937$5822_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:141938$5823 - parameter \WIDTH 1 - connect \A \sdr_dq_15__core__o - connect \B \io_bd [152] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141938$5823_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:141939$5824 - parameter \WIDTH 1 - connect \A \sdr_dq_15__core__oe - connect \B \io_bd [153] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:141939$5824_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:142026$5912 - parameter \WIDTH 1 - connect \A \eint_0__pad__i - connect \B \io_bd [0] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:142026$5912_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:142027$5913 - parameter \WIDTH 1 - connect \A \eint_1__pad__i - connect \B \io_bd [1] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:142027$5913_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:142028$5914 - parameter \WIDTH 1 - connect \A \eint_2__pad__i - connect \B \io_bd [2] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:142028$5914_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:142029$5915 - parameter \WIDTH 1 - connect \A \gpio_e8__pad__i - connect \B \io_bd [3] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:142029$5915_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:142031$5917 - parameter \WIDTH 1 - connect \A \gpio_e8__core__o - connect \B \io_bd [4] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142031$5917_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:142032$5918 - parameter \WIDTH 1 - connect \A \gpio_e8__core__oe - connect \B \io_bd [5] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142032$5918_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:142033$5919 - parameter \WIDTH 1 - connect \A \gpio_e9__pad__i - connect \B \io_bd [6] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:142033$5919_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:142034$5920 - parameter \WIDTH 1 - connect \A \gpio_e9__core__o - connect \B \io_bd [7] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142034$5920_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:142035$5921 - parameter \WIDTH 1 - connect \A \gpio_e9__core__oe - connect \B \io_bd [8] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142035$5921_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:142036$5922 - parameter \WIDTH 1 - connect \A \gpio_e10__pad__i - connect \B \io_bd [9] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:142036$5922_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:142037$5923 - parameter \WIDTH 1 - connect \A \gpio_e10__core__o - connect \B \io_bd [10] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142037$5923_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:142038$5924 - parameter \WIDTH 1 - connect \A \gpio_e10__core__oe - connect \B \io_bd [11] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142038$5924_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:142039$5925 - parameter \WIDTH 1 - connect \A \gpio_e11__pad__i - connect \B \io_bd [12] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:142039$5925_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:142040$5926 - parameter \WIDTH 1 - connect \A \gpio_e11__core__o - connect \B \io_bd [13] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142040$5926_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:142042$5928 - parameter \WIDTH 1 - connect \A \gpio_e11__core__oe - connect \B \io_bd [14] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142042$5928_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:142043$5929 - parameter \WIDTH 1 - connect \A \gpio_e12__pad__i - connect \B \io_bd [15] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:142043$5929_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:142044$5930 - parameter \WIDTH 1 - connect \A \gpio_e12__core__o - connect \B \io_bd [16] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142044$5930_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:142045$5931 - parameter \WIDTH 1 - connect \A \gpio_e12__core__oe - connect \B \io_bd [17] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142045$5931_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:142046$5932 - parameter \WIDTH 1 - connect \A \gpio_e13__pad__i - connect \B \io_bd [18] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:142046$5932_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:142047$5933 - parameter \WIDTH 1 - connect \A \gpio_e13__core__o - connect \B \io_bd [19] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142047$5933_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:142048$5934 - parameter \WIDTH 1 - connect \A \gpio_e13__core__oe - connect \B \io_bd [20] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142048$5934_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:142049$5935 - parameter \WIDTH 1 - connect \A \gpio_e14__pad__i - connect \B \io_bd [21] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:142049$5935_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:142050$5936 - parameter \WIDTH 1 - connect \A \gpio_e14__core__o - connect \B \io_bd [22] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142050$5936_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:142051$5937 - parameter \WIDTH 1 - connect \A \gpio_e14__core__oe - connect \B \io_bd [23] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:142051$5937_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:142124.8-142136.4" - cell \_fsm \_fsm - connect \TAP_bus__tck \TAP_bus__tck - connect \TAP_bus__tms \TAP_bus__tms - connect \capture \_fsm_capture - connect \isdr \_fsm_isdr - connect \isir \_fsm_isir - connect \negjtag_clk \negjtag_clk - connect \negjtag_rst \negjtag_rst - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \shift \_fsm_shift - connect \update \_fsm_update - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:142137.12-142147.4" - cell \_idblock \_idblock - connect \TAP_bus__tdi \TAP_bus__tdi - connect \TAP_id_tdo \_idblock_TAP_id_tdo - connect \capture \_fsm_capture - connect \id_bypass \_idblock_id_bypass - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \select_id \_idblock_select_id - connect \shift \_fsm_shift - connect \update \_fsm_update - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:142148.12-142158.4" - cell \_irblock \_irblock - connect \TAP_bus__tdi \TAP_bus__tdi - connect \capture \_fsm_capture - connect \ir \_irblock_ir - connect \isir \_fsm_isir - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \shift \_fsm_shift - connect \tdo \_irblock_tdo - connect \update \_fsm_update - end - attribute \src "libresoc.v:140366.7-140366.20" - process $proc$libresoc.v:140366$6129 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:140924.13-140924.32" - process $proc$libresoc.v:140924$6130 - assign { } { } - assign $1\dmi0__addr_i[3:0] 4'0000 - sync always - sync init - update \dmi0__addr_i $1\dmi0__addr_i[3:0] - end - attribute \src "libresoc.v:140929.14-140929.46" - process $proc$libresoc.v:140929$6131 - assign { } { } - assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0__din $1\dmi0__din[63:0] - end - attribute \src "libresoc.v:140943.7-140943.29" - process $proc$libresoc.v:140943$6132 - assign { } { } - assign $1\dmi0_addrsr__oe[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] - end - attribute \src "libresoc.v:140951.13-140951.36" - process $proc$libresoc.v:140951$6133 - assign { } { } - assign $1\dmi0_addrsr_reg[7:0] 8'00000000 - sync always - sync init - update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] - end - attribute \src "libresoc.v:140959.7-140959.37" - process $proc$libresoc.v:140959$6134 - assign { } { } - assign $1\dmi0_addrsr_update_core[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:140963.7-140963.42" - process $proc$libresoc.v:140963$6135 - assign { } { } - assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:140967.14-140967.51" - process $proc$libresoc.v:140967$6136 - assign { } { } - assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] - end - attribute \src "libresoc.v:140973.13-140973.35" - process $proc$libresoc.v:140973$6137 - assign { } { } - assign $1\dmi0_datasr__oe[1:0] 2'00 - sync always - sync init - update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] - end - attribute \src "libresoc.v:140981.14-140981.52" - process $proc$libresoc.v:140981$6138 - assign { } { } - assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] - end - attribute \src "libresoc.v:140989.7-140989.37" - process $proc$libresoc.v:140989$6139 - assign { } { } - assign $1\dmi0_datasr_update_core[0:0] 1'0 - sync always - sync init - update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] - end - attribute \src "libresoc.v:140993.7-140993.42" - process $proc$libresoc.v:140993$6140 - assign { } { } - assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 - sync always - sync init - update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:141009.13-141009.29" - process $proc$libresoc.v:141009$6141 - assign { } { } - assign $1\fsm_state[2:0] 3'000 - sync always - sync init - update \fsm_state $1\fsm_state[2:0] - end - attribute \src "libresoc.v:141011.13-141011.35" - process $proc$libresoc.v:141011$6142 - assign { } { } - assign $0\fsm_state$503[2:0]$6143 3'000 - sync always - sync init - update \fsm_state$503 $0\fsm_state$503[2:0]$6143 - end - attribute \src "libresoc.v:141209.15-141209.67" - process $proc$libresoc.v:141209$6144 - assign { } { } - assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \io_bd $1\io_bd[153:0] - end - attribute \src "libresoc.v:141221.15-141221.67" - process $proc$libresoc.v:141221$6145 - assign { } { } - assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \io_sr $1\io_sr[153:0] - end - attribute \src "libresoc.v:141230.14-141230.41" - process $proc$libresoc.v:141230$6146 - assign { } { } - assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 - sync always - sync init - update \jtag_wb__adr $1\jtag_wb__adr[28:0] - end - attribute \src "libresoc.v:141239.14-141239.51" - process $proc$libresoc.v:141239$6147 - assign { } { } - assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] - end - attribute \src "libresoc.v:141253.7-141253.32" - process $proc$libresoc.v:141253$6148 - assign { } { } - assign $1\jtag_wb_addrsr__oe[0:0] 1'0 - sync always - sync init - update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] - end - attribute \src "libresoc.v:141261.14-141261.47" - process $proc$libresoc.v:141261$6149 - assign { } { } - assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 - sync always - sync init - update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] - end - attribute \src "libresoc.v:141269.7-141269.40" - process $proc$libresoc.v:141269$6150 - assign { } { } - assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 - sync always - sync init - update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:141273.7-141273.45" - process $proc$libresoc.v:141273$6151 - assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 - sync always - sync init - update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:141277.14-141277.54" - process $proc$libresoc.v:141277$6152 - assign { } { } - assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] - end - attribute \src "libresoc.v:141283.13-141283.38" - process $proc$libresoc.v:141283$6153 - assign { } { } - assign $1\jtag_wb_datasr__oe[1:0] 2'00 - sync always - sync init - update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] - end - attribute \src "libresoc.v:141291.14-141291.55" - process $proc$libresoc.v:141291$6154 - assign { } { } - assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] - end - attribute \src "libresoc.v:141299.7-141299.40" - process $proc$libresoc.v:141299$6155 - assign { } { } - assign $1\jtag_wb_datasr_update_core[0:0] 1'0 - sync always - sync init - update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] - end - attribute \src "libresoc.v:141303.7-141303.45" - process $proc$libresoc.v:141303$6156 - assign { } { } - assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 - sync always - sync init - update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:141733.7-141733.21" - process $proc$libresoc.v:141733$6157 - assign { } { } - assign $1\sr0__oe[0:0] 1'0 - sync always - sync init - update \sr0__oe $1\sr0__oe[0:0] - end - attribute \src "libresoc.v:141741.13-141741.27" - process $proc$libresoc.v:141741$6158 - assign { } { } - assign $1\sr0_reg[2:0] 3'000 - sync always - sync init - update \sr0_reg $1\sr0_reg[2:0] - end - attribute \src "libresoc.v:141749.7-141749.29" - process $proc$libresoc.v:141749$6159 - assign { } { } - assign $1\sr0_update_core[0:0] 1'0 - sync always - sync init - update \sr0_update_core $1\sr0_update_core[0:0] - end - attribute \src "libresoc.v:141753.7-141753.34" - process $proc$libresoc.v:141753$6160 - assign { } { } - assign $1\sr0_update_core_prev[0:0] 1'0 - sync always - sync init - update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] - end - attribute \src "libresoc.v:141763.7-141763.21" - process $proc$libresoc.v:141763$6161 - assign { } { } - assign $1\sr5__oe[0:0] 1'0 - sync always - sync init - update \sr5__oe $1\sr5__oe[0:0] - end - attribute \src "libresoc.v:141771.13-141771.27" - process $proc$libresoc.v:141771$6162 - assign { } { } - assign $1\sr5_reg[1:0] 2'00 - sync always - sync init - update \sr5_reg $1\sr5_reg[1:0] - end - attribute \src "libresoc.v:141779.7-141779.29" - process $proc$libresoc.v:141779$6163 - assign { } { } - assign $1\sr5_update_core[0:0] 1'0 - sync always - sync init - update \sr5_update_core $1\sr5_update_core[0:0] - end - attribute \src "libresoc.v:141783.7-141783.34" - process $proc$libresoc.v:141783$6164 - assign { } { } - assign $1\sr5_update_core_prev[0:0] 1'0 - sync always - sync init - update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] - end - attribute \src "libresoc.v:141788.7-141788.26" - process $proc$libresoc.v:141788$6165 - assign { } { } - assign $1\wb_dcache_en[0:0] 1'1 - sync always - sync init - update \wb_dcache_en $1\wb_dcache_en[0:0] - end - attribute \src "libresoc.v:141793.7-141793.26" - process $proc$libresoc.v:141793$6166 - assign { } { } - assign $1\wb_icache_en[0:0] 1'1 - sync always - sync init - update \wb_icache_en $1\wb_icache_en[0:0] - end - attribute \src "libresoc.v:142052.3-142053.41" - process $proc$libresoc.v:142052$5938 - assign { } { } - assign $0\wb_icache_en[0:0] \wb_icache_en$next - sync posedge \clk - update \wb_icache_en $0\wb_icache_en[0:0] - end - attribute \src "libresoc.v:142054.3-142055.41" - process $proc$libresoc.v:142054$5939 - assign { } { } - assign $0\wb_dcache_en[0:0] \wb_dcache_en$next - sync posedge \clk - update \wb_dcache_en $0\wb_dcache_en[0:0] - end - attribute \src "libresoc.v:142056.3-142057.45" - process $proc$libresoc.v:142056$5940 - assign { } { } - assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next - sync posedge \clk - update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] - end - attribute \src "libresoc.v:142058.3-142059.35" - process $proc$libresoc.v:142058$5941 - assign { } { } - assign $0\dmi0__din[63:0] \dmi0__din$next - sync posedge \clk - update \dmi0__din $0\dmi0__din[63:0] - end - attribute \src "libresoc.v:142060.3-142061.45" - process $proc$libresoc.v:142060$5942 - assign { } { } - assign $0\fsm_state$503[2:0]$5943 \fsm_state$503$next - sync posedge \clk - update \fsm_state$503 $0\fsm_state$503[2:0]$5943 - end - attribute \src "libresoc.v:142062.3-142063.41" - process $proc$libresoc.v:142062$5944 - assign { } { } - assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next - sync posedge \clk - update \dmi0__addr_i $0\dmi0__addr_i[3:0] - end - attribute \src "libresoc.v:142064.3-142065.51" - process $proc$libresoc.v:142064$5945 - assign { } { } - assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next - sync posedge \clk - update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] - end - attribute \src "libresoc.v:142066.3-142067.45" - process $proc$libresoc.v:142066$5946 - assign { } { } - assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next - sync posedge \clk - update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] - end - attribute \src "libresoc.v:142068.3-142069.35" - process $proc$libresoc.v:142068$5947 - assign { } { } - assign $0\fsm_state[2:0] \fsm_state$next - sync posedge \clk - update \fsm_state $0\fsm_state[2:0] - end - attribute \src "libresoc.v:142070.3-142071.41" - process $proc$libresoc.v:142070$5948 - assign { } { } - assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next - sync posedge \clk - update \jtag_wb__adr $0\jtag_wb__adr[28:0] - end - attribute \src "libresoc.v:142072.3-142073.31" - process $proc$libresoc.v:142072$5949 - assign { } { } - assign $0\sr5_reg[1:0] \sr5_reg$next - sync posedge \posjtag_clk - update \sr5_reg $0\sr5_reg[1:0] - end - attribute \src "libresoc.v:142074.3-142075.31" - process $proc$libresoc.v:142074$5950 - assign { } { } - assign $0\sr5__oe[0:0] \sr5__oe$next - sync posedge \clk - update \sr5__oe $0\sr5__oe[0:0] - end - attribute \src "libresoc.v:142076.3-142077.57" - process $proc$libresoc.v:142076$5951 - assign { } { } - assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next - sync posedge \clk - update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] - end - attribute \src "libresoc.v:142078.3-142079.47" - process $proc$libresoc.v:142078$5952 - assign { } { } - assign $0\sr5_update_core[0:0] \sr5_update_core$next - sync posedge \clk - update \sr5_update_core $0\sr5_update_core[0:0] - end - attribute \src "libresoc.v:142080.3-142081.47" - process $proc$libresoc.v:142080$5953 - assign { } { } - assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next - sync posedge \posjtag_clk - update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] - end - attribute \src "libresoc.v:142082.3-142083.47" - process $proc$libresoc.v:142082$5954 - assign { } { } - assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next - sync posedge \clk - update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] - end - attribute \src "libresoc.v:142084.3-142085.73" - process $proc$libresoc.v:142084$5955 - assign { } { } - assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next - sync posedge \clk - update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:142086.3-142087.63" - process $proc$libresoc.v:142086$5956 - assign { } { } - assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next - sync posedge \clk - update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] - end - attribute \src "libresoc.v:142088.3-142089.47" - process $proc$libresoc.v:142088$5957 - assign { } { } - assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next - sync posedge \posjtag_clk - update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] - end - attribute \src "libresoc.v:142090.3-142091.47" - process $proc$libresoc.v:142090$5958 - assign { } { } - assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next - sync posedge \clk - update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] - end - attribute \src "libresoc.v:142092.3-142093.73" - process $proc$libresoc.v:142092$5959 - assign { } { } - assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next - sync posedge \clk - update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:142094.3-142095.63" - process $proc$libresoc.v:142094$5960 - assign { } { } - assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next - sync posedge \clk - update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:142096.3-142097.53" - process $proc$libresoc.v:142096$5961 - assign { } { } - assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next - sync posedge \posjtag_clk - update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] - end - attribute \src "libresoc.v:142098.3-142099.53" - process $proc$libresoc.v:142098$5962 - assign { } { } - assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next - sync posedge \clk - update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] - end - attribute \src "libresoc.v:142100.3-142101.79" - process $proc$libresoc.v:142100$5963 - assign { } { } - assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next - sync posedge \clk - update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:142102.3-142103.69" - process $proc$libresoc.v:142102$5964 - assign { } { } - assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next - sync posedge \clk - update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] - end - attribute \src "libresoc.v:142104.3-142105.53" - process $proc$libresoc.v:142104$5965 - assign { } { } - assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next - sync posedge \posjtag_clk - update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] - end - attribute \src "libresoc.v:142106.3-142107.53" - process $proc$libresoc.v:142106$5966 - assign { } { } - assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next - sync posedge \clk - update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] - end - attribute \src "libresoc.v:142108.3-142109.79" - process $proc$libresoc.v:142108$5967 - assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next - sync posedge \clk - update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:142110.3-142111.69" - process $proc$libresoc.v:142110$5968 - assign { } { } - assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next - sync posedge \clk - update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:142112.3-142113.31" - process $proc$libresoc.v:142112$5969 - assign { } { } - assign $0\sr0_reg[2:0] \sr0_reg$next - sync posedge \posjtag_clk - update \sr0_reg $0\sr0_reg[2:0] - end - attribute \src "libresoc.v:142114.3-142115.31" - process $proc$libresoc.v:142114$5970 - assign { } { } - assign $0\sr0__oe[0:0] \sr0__oe$next - sync posedge \clk - update \sr0__oe $0\sr0__oe[0:0] - end - attribute \src "libresoc.v:142116.3-142117.57" - process $proc$libresoc.v:142116$5971 - assign { } { } - assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next - sync posedge \clk - update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] - end - attribute \src "libresoc.v:142118.3-142119.47" - process $proc$libresoc.v:142118$5972 - assign { } { } - assign $0\sr0_update_core[0:0] \sr0_update_core$next - sync posedge \clk - update \sr0_update_core $0\sr0_update_core[0:0] - end - attribute \src "libresoc.v:142120.3-142121.27" - process $proc$libresoc.v:142120$5973 - assign { } { } - assign $0\io_bd[153:0] \io_bd$next - sync negedge \negjtag_clk - update \io_bd $0\io_bd[153:0] - end - attribute \src "libresoc.v:142122.3-142123.27" - process $proc$libresoc.v:142122$5974 - assign { } { } - assign $0\io_sr[153:0] \io_sr$next - sync posedge \posjtag_clk - update \io_sr $0\io_sr[153:0] - end - attribute \src "libresoc.v:142159.3-142174.6" - process $proc$libresoc.v:142159$5975 + attribute \src "libresoc.v:139253.3-139262.6" + process $proc$libresoc.v:139253$6198 assign { } { } assign { } { } - assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:142160.5-142160.29" + assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:139254.5-139254.29" switch \initial - attribute \src "libresoc.v:142160.9-142160.17" + attribute \src "libresoc.v:139254.9-139254.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" - switch { \$369 \_idblock_select_id \_fsm_isir } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\TAP_tdo[0:0] \_irblock_tdo - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" - case 3'1-- + case 1'1 assign { } { } - assign $1\TAP_tdo[0:0] \io_sr [153] + assign $1\idx_l_r_idx_l[0:0] 1'1 case - assign $1\TAP_tdo[0:0] 1'0 + assign $1\idx_l_r_idx_l[0:0] 1'1 end sync always - update \TAP_tdo $0\TAP_tdo[0:0] + update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end - attribute \src "libresoc.v:142175.3-142183.6" - process $proc$libresoc.v:142175$5976 + attribute \src "libresoc.v:139263.3-139277.6" + process $proc$libresoc.v:139263$6199 assign { } { } assign { } { } - assign $0\sr0_update_core$next[0:0]$5977 $1\sr0_update_core$next[0:0]$5978 - attribute \src "libresoc.v:142176.5-142176.29" + assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:139264.5-139264.29" switch \initial - attribute \src "libresoc.v:142176.9-142176.17" + attribute \src "libresoc.v:139264.9-139264.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core$next[0:0]$5978 1'0 + assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + switch \$28 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] 1'1 + case + assign $2\reset_l_s_reset[0:0] 1'0 + end case - assign $1\sr0_update_core$next[0:0]$5978 \sr0_update + assign $1\reset_l_s_reset[0:0] 1'0 end sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5977 + update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:142184.3-142192.6" - process $proc$libresoc.v:142184$5979 + attribute \src "libresoc.v:139278.3-139287.6" + process $proc$libresoc.v:139278$6200 assign { } { } assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$5980 $1\sr0_update_core_prev$next[0:0]$5981 - attribute \src "libresoc.v:142185.5-142185.29" + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:139279.5-139279.29" switch \initial - attribute \src "libresoc.v:142185.9-142185.17" + attribute \src "libresoc.v:139279.9-139279.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$5981 1'0 + assign $1\reset_l_r_reset[0:0] 1'1 case - assign $1\sr0_update_core_prev$next[0:0]$5981 \sr0_update_core + assign $1\reset_l_r_reset[0:0] 1'0 end sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5980 + update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:142193.3-142209.6" - process $proc$libresoc.v:142193$5982 + attribute \src "libresoc.v:139288.3-139297.6" + process $proc$libresoc.v:139288$6201 assign { } { } assign { } { } - assign $0\sr0__oe$next[0:0]$5983 $2\sr0__oe$next[0:0]$5985 - attribute \src "libresoc.v:142194.5-142194.29" + assign $0\ldst_port0_is_ld_i$8[0:0]$6202 $1\ldst_port0_is_ld_i$8[0:0]$6203 + attribute \src "libresoc.v:139289.5-139289.29" switch \initial - attribute \src "libresoc.v:142194.9-142194.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$387 - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:139289.9-139289.17" case 1'1 - assign { } { } - assign $1\sr0__oe$next[0:0]$5984 \sr0_isir - attribute \src "libresoc.v:0.0-0.0" case - assign { } { } - assign $1\sr0__oe$next[0:0]$5984 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0__oe$next[0:0]$5985 1'0 + assign $1\ldst_port0_is_ld_i$8[0:0]$6203 \ldst_port0_is_ld_i case - assign $2\sr0__oe$next[0:0]$5985 $1\sr0__oe$next[0:0]$5984 + assign $1\ldst_port0_is_ld_i$8[0:0]$6203 1'0 end sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$5983 + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6202 end - attribute \src "libresoc.v:142210.3-142230.6" - process $proc$libresoc.v:142210$5986 + attribute \src "libresoc.v:139298.3-139307.6" + process $proc$libresoc.v:139298$6204 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\sr0_reg$next[2:0]$5987 $3\sr0_reg$next[2:0]$5990 - attribute \src "libresoc.v:142211.5-142211.29" + assign $0\ldst_port0_is_st_i$9[0:0]$6205 $1\ldst_port0_is_st_i$9[0:0]$6206 + attribute \src "libresoc.v:139299.5-139299.29" switch \initial - attribute \src "libresoc.v:142211.9-142211.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \sr0_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr0_reg$next[2:0]$5988 { \TAP_bus__tdi \sr0_reg [2:1] } - case - assign $1\sr0_reg$next[2:0]$5988 \sr0_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \sr0_capture - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:139299.9-139299.17" case 1'1 - assign { } { } - assign $2\sr0_reg$next[2:0]$5989 \sr0__i case - assign $2\sr0_reg$next[2:0]$5989 $1\sr0_reg$next[2:0]$5988 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr0_reg$next[2:0]$5990 3'000 + assign $1\ldst_port0_is_st_i$9[0:0]$6206 \ldst_port0_is_st_i case - assign $3\sr0_reg$next[2:0]$5990 $2\sr0_reg$next[2:0]$5989 + assign $1\ldst_port0_is_st_i$9[0:0]$6206 1'0 end sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$5987 + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6205 end - attribute \src "libresoc.v:142231.3-142239.6" - process $proc$libresoc.v:142231$5991 + attribute \src "libresoc.v:139308.3-139317.6" + process $proc$libresoc.v:139308$6207 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$5992 $1\jtag_wb_addrsr_update_core$next[0:0]$5993 - attribute \src "libresoc.v:142232.5-142232.29" + assign $0\ldst_port0_data_len$11[3:0]$6208 $1\ldst_port0_data_len$11[3:0]$6209 + attribute \src "libresoc.v:139309.5-139309.29" switch \initial - attribute \src "libresoc.v:142232.9-142232.17" + attribute \src "libresoc.v:139309.9-139309.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 1'0 + assign $1\ldst_port0_data_len$11[3:0]$6209 \ldst_port0_data_len case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 \jtag_wb_addrsr_update + assign $1\ldst_port0_data_len$11[3:0]$6209 4'0000 end sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5992 + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6208 end - attribute \src "libresoc.v:142240.3-142248.6" - process $proc$libresoc.v:142240$5994 + attribute \src "libresoc.v:139318.3-139327.6" + process $proc$libresoc.v:139318$6210 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 - attribute \src "libresoc.v:142241.5-142241.29" + assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:139319.5-139319.29" switch \initial - attribute \src "libresoc.v:142241.9-142241.17" + attribute \src "libresoc.v:139319.9-139319.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 1'0 + assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$30 case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 \jtag_wb_addrsr_update_core + assign $1\ldst_port0_go_die_i[0:0] 1'0 end sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 + update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] + end + connect \$20 $or$libresoc.v:139092$6152_Y + connect \$24 $ternary$libresoc.v:139093$6153_Y + connect \$26 $not$libresoc.v:139094$6154_Y + connect \$28 $not$libresoc.v:139095$6155_Y + connect \$22 \$24 + connect \$32 \ldst_port0_addr_i + connect \ldst_port0_go_die_i$30 1'0 + connect \ldst_port0_exc_$signal$33 1'0 + connect \ldst_port0_exc_$signal$34 1'0 + connect \ldst_port0_exc_$signal$35 1'0 + connect \ldst_port0_exc_$signal$36 1'0 + connect \ldst_port0_exc_$signal$37 1'0 + connect \ldst_port0_exc_$signal$38 1'0 + connect \ldst_port0_exc_$signal$39 1'0 + connect \ldst_port0_mmu_done$40 1'0 + connect \ldst_port0_ldst_error$41 1'0 + connect \ldst_port0_cache_paradox$42 1'0 + connect \reset_delay$next \reset_l_q_reset + connect \pick_i \$20 +end +attribute \src "libresoc.v:139347.1-139405.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" +attribute \generator "nMigen" +module \ld_active + attribute \src "libresoc.v:139348.7-139348.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:139393.3-139401.6" + wire $0\q_int$next[0:0]$6225 + attribute \src "libresoc.v:139391.3-139392.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:139393.3-139401.6" + wire $1\q_int$next[0:0]$6226 + attribute \src "libresoc.v:139370.7-139370.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:139383.17-139383.96" + wire $and$libresoc.v:139383$6215_Y + attribute \src "libresoc.v:139388.17-139388.96" + wire $and$libresoc.v:139388$6220_Y + attribute \src "libresoc.v:139385.18-139385.99" + wire $not$libresoc.v:139385$6217_Y + attribute \src "libresoc.v:139387.17-139387.98" + wire $not$libresoc.v:139387$6219_Y + attribute \src "libresoc.v:139390.17-139390.98" + wire $not$libresoc.v:139390$6222_Y + attribute \src "libresoc.v:139384.18-139384.104" + wire $or$libresoc.v:139384$6216_Y + attribute \src "libresoc.v:139386.18-139386.105" + wire $or$libresoc.v:139386$6218_Y + attribute \src "libresoc.v:139389.17-139389.103" + wire $or$libresoc.v:139389$6221_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:139348.7-139348.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 2 \r_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:139383$6215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:139383$6215_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:139388$6220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:139388$6220_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:139385$6217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \Y $not$libresoc.v:139385$6217_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:139387$6219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$libresoc.v:139387$6219_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:139390$6222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$libresoc.v:139390$6222_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:139384$6216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_ld_active + connect \Y $or$libresoc.v:139384$6216_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:139386$6218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \B \q_int + connect \Y $or$libresoc.v:139386$6218_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:139389$6221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_ld_active + connect \Y $or$libresoc.v:139389$6221_Y + end + attribute \src "libresoc.v:139348.7-139348.20" + process $proc$libresoc.v:139348$6227 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:139370.7-139370.19" + process $proc$libresoc.v:139370$6228 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:139391.3-139392.27" + process $proc$libresoc.v:139391$6223 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:142249.3-142265.6" - process $proc$libresoc.v:142249$5997 + attribute \src "libresoc.v:139393.3-139401.6" + process $proc$libresoc.v:139393$6224 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$5998 $2\jtag_wb_addrsr__oe$next[0:0]$6000 - attribute \src "libresoc.v:142250.5-142250.29" + assign $0\q_int$next[0:0]$6225 $1\q_int$next[0:0]$6226 + attribute \src "libresoc.v:139394.5-139394.29" switch \initial - attribute \src "libresoc.v:142250.9-142250.17" + attribute \src "libresoc.v:139394.9-139394.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$405 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 \jtag_wb_addrsr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 1'0 + assign $1\q_int$next[0:0]$6226 1'0 case - assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 $1\jtag_wb_addrsr__oe$next[0:0]$5999 + assign $1\q_int$next[0:0]$6226 \$5 end sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5998 + update \q_int$next $0\q_int$next[0:0]$6225 end - attribute \src "libresoc.v:142266.3-142286.6" - process $proc$libresoc.v:142266$6001 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$6002 $3\jtag_wb_addrsr_reg$next[28:0]$6005 - attribute \src "libresoc.v:142267.5-142267.29" - switch \initial - attribute \src "libresoc.v:142267.9-142267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \jtag_wb_addrsr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } - case - assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 \jtag_wb_addrsr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \jtag_wb_addrsr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 \jtag_wb_addrsr__i - case - assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 $1\jtag_wb_addrsr_reg$next[28:0]$6003 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 29'00000000000000000000000000000 - case - assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 $2\jtag_wb_addrsr_reg$next[28:0]$6004 - end - sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$6002 + connect \$9 $and$libresoc.v:139383$6215_Y + connect \$11 $or$libresoc.v:139384$6216_Y + connect \$13 $not$libresoc.v:139385$6217_Y + connect \$15 $or$libresoc.v:139386$6218_Y + connect \$1 $not$libresoc.v:139387$6219_Y + connect \$3 $and$libresoc.v:139388$6220_Y + connect \$5 $or$libresoc.v:139389$6221_Y + connect \$7 $not$libresoc.v:139390$6222_Y + connect \qlq_ld_active \$15 + connect \qn_ld_active \$13 + connect \q_ld_active \$11 +end +attribute \src "libresoc.v:139409.1-140768.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" +attribute \generator "nMigen" +module \ldst0 + attribute \src "libresoc.v:140423.3-140431.6" + wire $0\adr_l_r_adr$next[0:0]$6371 + attribute \src "libresoc.v:140305.3-140306.39" + wire $0\adr_l_r_adr[0:0] + attribute \src "libresoc.v:140251.3-140252.21" + wire $0\alu_ok[0:0] + attribute \src "libresoc.v:140588.3-140597.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:140598.3-140607.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:140578.3-140587.6" + wire width 64 $0\ea_r$next[63:0]$6459 + attribute \src "libresoc.v:140253.3-140254.25" + wire width 64 $0\ea_r[63:0] + attribute \src "libresoc.v:139410.7-139410.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:140653.3-140672.6" + wire width 64 $0\ldd_o[63:0] + attribute \src "libresoc.v:140617.3-140640.6" + wire width 64 $0\lddata_r[63:0] + attribute \src "libresoc.v:140520.3-140529.6" + wire width 64 $0\ldo_r$next[63:0]$6444 + attribute \src "libresoc.v:140261.3-140262.27" + wire width 64 $0\ldo_r[63:0] + attribute \src "libresoc.v:140249.3-140250.33" + wire width 96 $0\ldst_port0_addr_i[95:0] + attribute \src "libresoc.v:140608.3-140616.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6464 + attribute \src "libresoc.v:140247.3-140248.57" + wire $0\ldst_port0_addr_i_ok[0:0] + attribute \src "libresoc.v:140697.3-140708.6" + wire width 64 $0\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:140468.3-140476.6" + wire $0\lsd_l_r_lsd$next[0:0]$6386 + attribute \src "libresoc.v:140295.3-140296.39" + wire $0\lsd_l_r_lsd[0:0] + attribute \src "libresoc.v:140396.3-140404.6" + wire $0\opc_l_r_opc$next[0:0]$6362 + attribute \src "libresoc.v:140311.3-140312.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:140387.3-140395.6" + wire $0\opc_l_s_opc$next[0:0]$6359 + attribute \src "libresoc.v:140313.3-140314.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $0\oper_r__byte_reverse$next[0:0]$6389 + attribute \src "libresoc.v:140287.3-140288.57" + wire $0\oper_r__byte_reverse[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6390 + attribute \src "libresoc.v:140285.3-140286.49" + wire width 4 $0\oper_r__data_len[3:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 13 $0\oper_r__fn_unit$next[12:0]$6391 + attribute \src "libresoc.v:140265.3-140266.47" + wire width 13 $0\oper_r__fn_unit[12:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6392 + attribute \src "libresoc.v:140267.3-140268.61" + wire width 64 $0\oper_r__imm_data__data[63:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6393 + attribute \src "libresoc.v:140269.3-140270.57" + wire $0\oper_r__imm_data__ok[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 32 $0\oper_r__insn$next[31:0]$6394 + attribute \src "libresoc.v:140293.3-140294.41" + wire width 32 $0\oper_r__insn[31:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6395 + attribute \src "libresoc.v:140263.3-140264.51" + wire width 7 $0\oper_r__insn_type[6:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $0\oper_r__is_32bit$next[0:0]$6396 + attribute \src "libresoc.v:140281.3-140282.49" + wire $0\oper_r__is_32bit[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $0\oper_r__is_signed$next[0:0]$6397 + attribute \src "libresoc.v:140283.3-140284.51" + wire $0\oper_r__is_signed[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6398 + attribute \src "libresoc.v:140291.3-140292.51" + wire width 2 $0\oper_r__ldst_mode[1:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $0\oper_r__oe__oe$next[0:0]$6399 + attribute \src "libresoc.v:140277.3-140278.45" + wire $0\oper_r__oe__oe[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $0\oper_r__oe__ok$next[0:0]$6400 + attribute \src "libresoc.v:140279.3-140280.45" + wire $0\oper_r__oe__ok[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $0\oper_r__rc__ok$next[0:0]$6401 + attribute \src "libresoc.v:140275.3-140276.45" + wire $0\oper_r__rc__ok[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $0\oper_r__rc__rc$next[0:0]$6402 + attribute \src "libresoc.v:140273.3-140274.45" + wire $0\oper_r__rc__rc[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $0\oper_r__sign_extend$next[0:0]$6403 + attribute \src "libresoc.v:140289.3-140290.55" + wire $0\oper_r__sign_extend[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $0\oper_r__zero_a$next[0:0]$6404 + attribute \src "libresoc.v:140271.3-140272.45" + wire $0\oper_r__zero_a[0:0] + attribute \src "libresoc.v:140315.3-140316.28" + wire $0\p_st_go[0:0] + attribute \src "libresoc.v:140641.3-140652.6" + wire width 64 $0\revnorev[63:0] + attribute \src "libresoc.v:140414.3-140422.6" + wire width 3 $0\src_l_r_src$next[2:0]$6368 + attribute \src "libresoc.v:140307.3-140308.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:140405.3-140413.6" + wire width 3 $0\src_l_s_src$next[2:0]$6365 + attribute \src "libresoc.v:140309.3-140310.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:140530.3-140545.6" + wire width 64 $0\src_r0$next[63:0]$6447 + attribute \src "libresoc.v:140259.3-140260.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:140546.3-140561.6" + wire width 64 $0\src_r1$next[63:0]$6451 + attribute \src "libresoc.v:140257.3-140258.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:140562.3-140577.6" + wire width 64 $0\src_r2$next[63:0]$6455 + attribute \src "libresoc.v:140255.3-140256.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:140673.3-140696.6" + wire width 64 $0\stdata_r[63:0] + attribute \src "libresoc.v:140459.3-140467.6" + wire $0\sto_l_r_sto$next[0:0]$6383 + attribute \src "libresoc.v:140297.3-140298.39" + wire $0\sto_l_r_sto[0:0] + attribute \src "libresoc.v:140450.3-140458.6" + wire $0\upd_l_r_upd$next[0:0]$6380 + attribute \src "libresoc.v:140299.3-140300.39" + wire $0\upd_l_r_upd[0:0] + attribute \src "libresoc.v:140441.3-140449.6" + wire $0\upd_l_s_upd$next[0:0]$6377 + attribute \src "libresoc.v:140301.3-140302.39" + wire $0\upd_l_s_upd[0:0] + attribute \src "libresoc.v:140432.3-140440.6" + wire $0\wri_l_r_wri$next[0:0]$6374 + attribute \src "libresoc.v:140303.3-140304.39" + wire $0\wri_l_r_wri[0:0] + attribute \src "libresoc.v:140423.3-140431.6" + wire $1\adr_l_r_adr$next[0:0]$6372 + attribute \src "libresoc.v:139606.7-139606.25" + wire $1\adr_l_r_adr[0:0] + attribute \src "libresoc.v:139620.7-139620.20" + wire $1\alu_ok[0:0] + attribute \src "libresoc.v:140588.3-140597.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:140598.3-140607.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:140578.3-140587.6" + wire width 64 $1\ea_r$next[63:0]$6460 + attribute \src "libresoc.v:139666.14-139666.41" + wire width 64 $1\ea_r[63:0] + attribute \src "libresoc.v:140653.3-140672.6" + wire width 64 $1\ldd_o[63:0] + attribute \src "libresoc.v:140617.3-140640.6" + wire width 64 $1\lddata_r[63:0] + attribute \src "libresoc.v:140520.3-140529.6" + wire width 64 $1\ldo_r$next[63:0]$6445 + attribute \src "libresoc.v:139696.14-139696.42" + wire width 64 $1\ldo_r[63:0] + attribute \src "libresoc.v:139701.14-139701.62" + wire width 96 $1\ldst_port0_addr_i[95:0] + attribute \src "libresoc.v:140608.3-140616.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6465 + attribute \src "libresoc.v:139706.7-139706.34" + wire $1\ldst_port0_addr_i_ok[0:0] + attribute \src "libresoc.v:140697.3-140708.6" + wire width 64 $1\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:140468.3-140476.6" + wire $1\lsd_l_r_lsd$next[0:0]$6387 + attribute \src "libresoc.v:139755.7-139755.25" + wire $1\lsd_l_r_lsd[0:0] + attribute \src "libresoc.v:140396.3-140404.6" + wire $1\opc_l_r_opc$next[0:0]$6363 + attribute \src "libresoc.v:139769.7-139769.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:140387.3-140395.6" + wire $1\opc_l_s_opc$next[0:0]$6360 + attribute \src "libresoc.v:139773.7-139773.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $1\oper_r__byte_reverse$next[0:0]$6405 + attribute \src "libresoc.v:139902.7-139902.34" + wire $1\oper_r__byte_reverse[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6406 + attribute \src "libresoc.v:139906.13-139906.36" + wire width 4 $1\oper_r__data_len[3:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 13 $1\oper_r__fn_unit$next[12:0]$6407 + attribute \src "libresoc.v:139924.14-139924.40" + wire width 13 $1\oper_r__fn_unit[12:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6408 + attribute \src "libresoc.v:139928.14-139928.59" + wire width 64 $1\oper_r__imm_data__data[63:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6409 + attribute \src "libresoc.v:139932.7-139932.34" + wire $1\oper_r__imm_data__ok[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 32 $1\oper_r__insn$next[31:0]$6410 + attribute \src "libresoc.v:139936.14-139936.34" + wire width 32 $1\oper_r__insn[31:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6411 + attribute \src "libresoc.v:140014.13-140014.38" + wire width 7 $1\oper_r__insn_type[6:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $1\oper_r__is_32bit$next[0:0]$6412 + attribute \src "libresoc.v:140018.7-140018.30" + wire $1\oper_r__is_32bit[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $1\oper_r__is_signed$next[0:0]$6413 + attribute \src "libresoc.v:140022.7-140022.31" + wire $1\oper_r__is_signed[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6414 + attribute \src "libresoc.v:140031.13-140031.37" + wire width 2 $1\oper_r__ldst_mode[1:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $1\oper_r__oe__oe$next[0:0]$6415 + attribute \src "libresoc.v:140035.7-140035.28" + wire $1\oper_r__oe__oe[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $1\oper_r__oe__ok$next[0:0]$6416 + attribute \src "libresoc.v:140039.7-140039.28" + wire $1\oper_r__oe__ok[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $1\oper_r__rc__ok$next[0:0]$6417 + attribute \src "libresoc.v:140043.7-140043.28" + wire $1\oper_r__rc__ok[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $1\oper_r__rc__rc$next[0:0]$6418 + attribute \src "libresoc.v:140047.7-140047.28" + wire $1\oper_r__rc__rc[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $1\oper_r__sign_extend$next[0:0]$6419 + attribute \src "libresoc.v:140051.7-140051.33" + wire $1\oper_r__sign_extend[0:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $1\oper_r__zero_a$next[0:0]$6420 + attribute \src "libresoc.v:140055.7-140055.28" + wire $1\oper_r__zero_a[0:0] + attribute \src "libresoc.v:140059.7-140059.21" + wire $1\p_st_go[0:0] + attribute \src "libresoc.v:140641.3-140652.6" + wire width 64 $1\revnorev[63:0] + attribute \src "libresoc.v:140414.3-140422.6" + wire width 3 $1\src_l_r_src$next[2:0]$6369 + attribute \src "libresoc.v:140101.13-140101.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:140405.3-140413.6" + wire width 3 $1\src_l_s_src$next[2:0]$6366 + attribute \src "libresoc.v:140105.13-140105.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:140530.3-140545.6" + wire width 64 $1\src_r0$next[63:0]$6448 + attribute \src "libresoc.v:140109.14-140109.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:140546.3-140561.6" + wire width 64 $1\src_r1$next[63:0]$6452 + attribute \src "libresoc.v:140113.14-140113.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:140562.3-140577.6" + wire width 64 $1\src_r2$next[63:0]$6456 + attribute \src "libresoc.v:140117.14-140117.43" + wire width 64 $1\src_r2[63:0] + attribute \src "libresoc.v:140673.3-140696.6" + wire width 64 $1\stdata_r[63:0] + attribute \src "libresoc.v:140459.3-140467.6" + wire $1\sto_l_r_sto$next[0:0]$6384 + attribute \src "libresoc.v:140127.7-140127.25" + wire $1\sto_l_r_sto[0:0] + attribute \src "libresoc.v:140450.3-140458.6" + wire $1\upd_l_r_upd$next[0:0]$6381 + attribute \src "libresoc.v:140137.7-140137.25" + wire $1\upd_l_r_upd[0:0] + attribute \src "libresoc.v:140441.3-140449.6" + wire $1\upd_l_s_upd$next[0:0]$6378 + attribute \src "libresoc.v:140141.7-140141.25" + wire $1\upd_l_s_upd[0:0] + attribute \src "libresoc.v:140432.3-140440.6" + wire $1\wri_l_r_wri$next[0:0]$6375 + attribute \src "libresoc.v:140151.7-140151.25" + wire $1\wri_l_r_wri[0:0] + attribute \src "libresoc.v:140653.3-140672.6" + wire width 64 $2\ldd_o[63:0] + attribute \src "libresoc.v:140617.3-140640.6" + wire width 64 $2\lddata_r[63:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire $2\oper_r__byte_reverse$next[0:0]$6421 + attribute \src "libresoc.v:140477.3-140519.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6422 + attribute \src "libresoc.v:140477.3-140519.6" + wire width 13 $2\oper_r__fn_unit$next[12:0]$6423 + attribute \src "libresoc.v:140477.3-140519.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6424 + attribute \src "libresoc.v:140477.3-140519.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6425 + attribute \src "libresoc.v:140477.3-140519.6" + wire width 32 $2\oper_r__insn$next[31:0]$6426 + attribute \src "libresoc.v:140477.3-140519.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6427 + attribute \src "libresoc.v:140477.3-140519.6" + wire $2\oper_r__is_32bit$next[0:0]$6428 + attribute \src "libresoc.v:140477.3-140519.6" + wire $2\oper_r__is_signed$next[0:0]$6429 + attribute \src "libresoc.v:140477.3-140519.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6430 + attribute \src "libresoc.v:140477.3-140519.6" + wire $2\oper_r__oe__oe$next[0:0]$6431 + attribute \src "libresoc.v:140477.3-140519.6" + wire $2\oper_r__oe__ok$next[0:0]$6432 + attribute \src "libresoc.v:140477.3-140519.6" + wire $2\oper_r__rc__ok$next[0:0]$6433 + attribute \src "libresoc.v:140477.3-140519.6" + wire $2\oper_r__rc__rc$next[0:0]$6434 + attribute \src "libresoc.v:140477.3-140519.6" + wire $2\oper_r__sign_extend$next[0:0]$6435 + attribute \src "libresoc.v:140477.3-140519.6" + wire $2\oper_r__zero_a$next[0:0]$6436 + attribute \src "libresoc.v:140530.3-140545.6" + wire width 64 $2\src_r0$next[63:0]$6449 + attribute \src "libresoc.v:140546.3-140561.6" + wire width 64 $2\src_r1$next[63:0]$6453 + attribute \src "libresoc.v:140562.3-140577.6" + wire width 64 $2\src_r2$next[63:0]$6457 + attribute \src "libresoc.v:140673.3-140696.6" + wire width 64 $2\stdata_r[63:0] + attribute \src "libresoc.v:140477.3-140519.6" + wire width 64 $3\oper_r__imm_data__data$next[63:0]$6437 + attribute \src "libresoc.v:140477.3-140519.6" + wire $3\oper_r__imm_data__ok$next[0:0]$6438 + attribute \src "libresoc.v:140477.3-140519.6" + wire $3\oper_r__oe__oe$next[0:0]$6439 + attribute \src "libresoc.v:140477.3-140519.6" + wire $3\oper_r__oe__ok$next[0:0]$6440 + attribute \src "libresoc.v:140477.3-140519.6" + wire $3\oper_r__rc__ok$next[0:0]$6441 + attribute \src "libresoc.v:140477.3-140519.6" + wire $3\oper_r__rc__rc$next[0:0]$6442 + attribute \src "libresoc.v:140233.18-140233.124" + wire width 65 $add$libresoc.v:140233$6309_Y + attribute \src "libresoc.v:140156.19-140156.118" + wire $and$libresoc.v:140156$6229_Y + attribute \src "libresoc.v:140157.19-140157.125" + wire $and$libresoc.v:140157$6230_Y + attribute \src "libresoc.v:140158.19-140158.120" + wire $and$libresoc.v:140158$6231_Y + attribute \src "libresoc.v:140159.19-140159.125" + wire $and$libresoc.v:140159$6232_Y + attribute \src "libresoc.v:140160.19-140160.118" + wire $and$libresoc.v:140160$6233_Y + attribute \src "libresoc.v:140162.19-140162.119" + wire $and$libresoc.v:140162$6235_Y + attribute \src "libresoc.v:140163.19-140163.123" + wire $and$libresoc.v:140163$6236_Y + attribute \src "libresoc.v:140164.19-140164.123" + wire $and$libresoc.v:140164$6237_Y + attribute \src "libresoc.v:140165.19-140165.120" + wire $and$libresoc.v:140165$6238_Y + attribute \src "libresoc.v:140166.19-140166.123" + wire $and$libresoc.v:140166$6239_Y + attribute \src "libresoc.v:140167.19-140167.119" + wire $and$libresoc.v:140167$6240_Y + attribute \src "libresoc.v:140168.19-140168.123" + wire $and$libresoc.v:140168$6241_Y + attribute \src "libresoc.v:140169.19-140169.125" + wire $and$libresoc.v:140169$6242_Y + attribute \src "libresoc.v:140171.19-140171.116" + wire $and$libresoc.v:140171$6244_Y + attribute \src "libresoc.v:140173.19-140173.120" + wire $and$libresoc.v:140173$6246_Y + attribute \src "libresoc.v:140174.19-140174.123" + wire $and$libresoc.v:140174$6247_Y + attribute \src "libresoc.v:140178.19-140178.125" + wire $and$libresoc.v:140178$6251_Y + attribute \src "libresoc.v:140179.19-140179.123" + wire $and$libresoc.v:140179$6252_Y + attribute \src "libresoc.v:140184.19-140184.116" + wire $and$libresoc.v:140184$6257_Y + attribute \src "libresoc.v:140186.19-140186.116" + wire $and$libresoc.v:140186$6259_Y + attribute \src "libresoc.v:140189.19-140189.118" + wire $and$libresoc.v:140189$6262_Y + attribute \src "libresoc.v:140191.19-140191.125" + wire $and$libresoc.v:140191$6264_Y + attribute \src "libresoc.v:140194.19-140194.160" + wire width 3 $and$libresoc.v:140194$6267_Y + attribute \src "libresoc.v:140195.19-140195.122" + wire $and$libresoc.v:140195$6268_Y + attribute \src "libresoc.v:140196.19-140196.122" + wire $and$libresoc.v:140196$6269_Y + attribute \src "libresoc.v:140198.19-140198.122" + wire $and$libresoc.v:140198$6272_Y + attribute \src "libresoc.v:140210.18-140210.123" + wire $and$libresoc.v:140210$6286_Y + attribute \src "libresoc.v:140211.18-140211.123" + wire $and$libresoc.v:140211$6287_Y + attribute \src "libresoc.v:140213.18-140213.114" + wire $and$libresoc.v:140213$6289_Y + attribute \src "libresoc.v:140215.18-140215.113" + wire $and$libresoc.v:140215$6291_Y + attribute \src "libresoc.v:140218.18-140218.113" + wire $and$libresoc.v:140218$6294_Y + attribute \src "libresoc.v:140222.18-140222.113" + wire $and$libresoc.v:140222$6298_Y + attribute \src "libresoc.v:140225.18-140225.119" + wire $and$libresoc.v:140225$6301_Y + attribute \src "libresoc.v:140234.18-140234.150" + wire width 3 $and$libresoc.v:140234$6310_Y + attribute \src "libresoc.v:140236.18-140236.113" + wire width 3 $and$libresoc.v:140236$6312_Y + attribute \src "libresoc.v:140238.18-140238.113" + wire width 3 $and$libresoc.v:140238$6314_Y + attribute \src "libresoc.v:140239.18-140239.127" + wire $and$libresoc.v:140239$6315_Y + attribute \src "libresoc.v:140240.18-140240.117" + wire $and$libresoc.v:140240$6316_Y + attribute \src "libresoc.v:140245.18-140245.117" + wire $and$libresoc.v:140245$6321_Y + attribute \src "libresoc.v:140170.19-140170.127" + wire $eq$libresoc.v:140170$6243_Y + attribute \src "libresoc.v:140190.19-140190.127" + wire $eq$libresoc.v:140190$6263_Y + attribute \src "libresoc.v:140192.19-140192.127" + wire $eq$libresoc.v:140192$6265_Y + attribute \src "libresoc.v:140203.19-140203.126" + wire $eq$libresoc.v:140203$6278_Y + attribute \src "libresoc.v:140208.18-140208.127" + wire $eq$libresoc.v:140208$6284_Y + attribute \src "libresoc.v:140209.18-140209.127" + wire $eq$libresoc.v:140209$6285_Y + attribute \src "libresoc.v:140217.18-140217.126" + wire $eq$libresoc.v:140217$6293_Y + attribute \src "libresoc.v:140221.18-140221.126" + wire $eq$libresoc.v:140221$6297_Y + attribute \src "libresoc.v:140197.19-140197.110" + wire width 96 $extend$libresoc.v:140197$6270_Y + attribute \src "libresoc.v:140199.19-140199.116" + wire width 64 $extend$libresoc.v:140199$6273_Y + attribute \src "libresoc.v:140204.19-140204.102" + wire width 64 $extend$libresoc.v:140204$6279_Y + attribute \src "libresoc.v:140182.19-140182.109" + wire $not$libresoc.v:140182$6255_Y + attribute \src "libresoc.v:140187.19-140187.121" + wire $not$libresoc.v:140187$6260_Y + attribute \src "libresoc.v:140212.18-140212.112" + wire $not$libresoc.v:140212$6288_Y + attribute \src "libresoc.v:140214.18-140214.110" + wire $not$libresoc.v:140214$6290_Y + attribute \src "libresoc.v:140216.18-140216.120" + wire $not$libresoc.v:140216$6292_Y + attribute \src "libresoc.v:140220.18-140220.120" + wire $not$libresoc.v:140220$6296_Y + attribute \src "libresoc.v:140235.18-140235.143" + wire width 2 $not$libresoc.v:140235$6311_Y + attribute \src "libresoc.v:140237.18-140237.115" + wire width 3 $not$libresoc.v:140237$6313_Y + attribute \src "libresoc.v:140244.18-140244.107" + wire $not$libresoc.v:140244$6320_Y + attribute \src "libresoc.v:140246.18-140246.118" + wire $not$libresoc.v:140246$6322_Y + attribute \src "libresoc.v:140161.18-140161.124" + wire $or$libresoc.v:140161$6234_Y + attribute \src "libresoc.v:140172.18-140172.129" + wire $or$libresoc.v:140172$6245_Y + attribute \src "libresoc.v:140175.19-140175.123" + wire $or$libresoc.v:140175$6248_Y + attribute \src "libresoc.v:140176.19-140176.125" + wire $or$libresoc.v:140176$6249_Y + attribute \src "libresoc.v:140177.19-140177.125" + wire $or$libresoc.v:140177$6250_Y + attribute \src "libresoc.v:140180.19-140180.132" + wire $or$libresoc.v:140180$6253_Y + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 49 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 50 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 51 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 52 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" + wire \load_mem_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \lod_l_qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \lod_l_r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \lod_l_s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \lsd_l_q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \lsd_l_r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \lsd_l_r_lsd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \lsd_l_s_lsd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 32 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" + wire \op_is_ld + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" + wire \op_is_st + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 7 \oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 21 \oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_ldst_ldst0__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 20 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \oper_i_ldst_ldst0__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__byte_reverse$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \oper_r__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \oper_r__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \oper_r__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \oper_r__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \oper_r__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \oper_r__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \oper_r__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \oper_r__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \oper_r__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \oper_r__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__is_signed$next + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \oper_r__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \oper_r__ldst_mode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__sign_extend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \oper_r__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" + wire \p_st_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" + wire \p_st_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" + wire \rd_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" + wire \rda_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" + wire \reset_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" + wire \reset_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" + wire \reset_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" + wire \reset_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" + wire \reset_u + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" + wire \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + wire width 64 \revnorev + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \rst_l_q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 27 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" + wire width 64 \src1_or_z + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 28 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" + wire width 64 \src2_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 29 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:111" + wire \st_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" + wire width 64 \stdata_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \sto_l_q_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \sto_l_r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \sto_l_r_sto$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \wri_l_r_wri$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \wri_l_s_wri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" + cell $add $add$libresoc.v:140233$6309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \src1_or_z + connect \B \src2_or_imm + connect \Y $add$libresoc.v:140233$6309_Y end - attribute \src "libresoc.v:142287.3-142295.6" - process $proc$libresoc.v:142287$6006 - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$6007 $1\jtag_wb_datasr_update_core$next[0:0]$6008 - attribute \src "libresoc.v:142288.5-142288.29" - switch \initial - attribute \src "libresoc.v:142288.9-142288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src 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end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 1'0 - case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 \jtag_wb_datasr_update_core - end - sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" + cell $and $and$libresoc.v:140157$6230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \B \adr_l_q_adr + connect \Y $and$libresoc.v:140157$6230_Y end - attribute \src "libresoc.v:142305.3-142321.6" - process $proc$libresoc.v:142305$6012 - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$6013 $2\jtag_wb_datasr__oe$next[1:0]$6015 - attribute \src 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\A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$102 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:140158$6231_Y end - attribute \src "libresoc.v:142322.3-142342.6" - process $proc$libresoc.v:142322$6016 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$6017 $3\jtag_wb_datasr_reg$next[63:0]$6020 - attribute \src "libresoc.v:142323.5-142323.29" - switch \initial - attribute \src "libresoc.v:142323.9-142323.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \jtag_wb_datasr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$6018 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } - case - assign $1\jtag_wb_datasr_reg$next[63:0]$6018 \jtag_wb_datasr_reg - end - attribute \src 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\B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sto_l_q_sto + connect \B \cu_busy_o + connect \Y $and$libresoc.v:140159$6232_Y end - attribute \src "libresoc.v:142343.3-142351.6" - process $proc$libresoc.v:142343$6021 - assign { } { } - assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$6022 $1\dmi0_addrsr_update_core$next[0:0]$6023 - attribute \src "libresoc.v:142344.5-142344.29" - switch \initial - attribute \src "libresoc.v:142344.9-142344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$6023 1'0 - case - assign $1\dmi0_addrsr_update_core$next[0:0]$6023 \dmi0_addrsr_update - end - sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + cell $and $and$libresoc.v:140160$6233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$106 + connect \B \rd_done + connect \Y $and$libresoc.v:140160$6233_Y end - attribute \src "libresoc.v:142352.3-142360.6" - process $proc$libresoc.v:142352$6024 - assign { } { } - assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 - attribute \src "libresoc.v:142353.5-142353.29" - switch \initial - attribute \src "libresoc.v:142353.9-142353.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 1'0 - case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 \dmi0_addrsr_update_core - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + cell $and 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$and$libresoc.v:140171$6244_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" + cell $and $and$libresoc.v:140173$6246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$128 + connect \B \alu_valid + connect \Y $and$libresoc.v:140173$6246_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" + cell $and $and$libresoc.v:140174$6247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$130 + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:140174$6247_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $and $and$libresoc.v:140178$6251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rst_l_q_rst + connect \B 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connect \B \$152 + connect \Y $and$libresoc.v:140186$6259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" + cell $and $and$libresoc.v:140189$6262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B \$158 + connect \Y $and$libresoc.v:140189$6262_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" + cell $and $and$libresoc.v:140191$6264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$162 + connect \B \cu_wr__go_i [1] + connect \Y $and$libresoc.v:140191$6264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" + cell $and $and$libresoc.v:140194$6267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \B { 1'0 \$167 \op_is_ld } + connect \Y $and$libresoc.v:140194$6267_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" + cell $and $and$libresoc.v:140195$6268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_ld + connect \B \cu_busy_o + connect \Y $and$libresoc.v:140195$6268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" + cell $and $and$libresoc.v:140196$6269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_st + connect \B \cu_busy_o + connect \Y $and$libresoc.v:140196$6269_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" + cell $and $and$libresoc.v:140198$6272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter 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parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $or$libresoc.v:140227$6303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" + cell $or $or$libresoc.v:140228$6304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$61 + connect \B \ld_ok + connect \Y $or$libresoc.v:140228$6304_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" + cell $or $or$libresoc.v:140241$6317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:140241$6317_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" + cell $or $or$libresoc.v:140242$6318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__go_i [0] + connect \B \cu_rd__go_i [1] + connect \Y $or$libresoc.v:140242$6318_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + cell $or $or$libresoc.v:140243$6319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__rel_o [0] + connect \B \cu_rd__rel_o [1] + connect \Y $or$libresoc.v:140243$6319_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" + cell $pos $pos$libresoc.v:140197$6271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 96 + parameter \Y_WIDTH 96 + connect \A $extend$libresoc.v:140197$6270_Y + connect \Y $pos$libresoc.v:140197$6271_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140199$6274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:140199$6273_Y + connect \Y $pos$libresoc.v:140199$6274_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140200$6275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } + connect \Y $pos$libresoc.v:140200$6275_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140202$6277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } + connect \Y $pos$libresoc.v:140202$6277_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140204$6280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:140204$6279_Y + connect \Y $pos$libresoc.v:140204$6280_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140205$6281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } + connect \Y $pos$libresoc.v:140205$6281_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" + cell $pos $pos$libresoc.v:140206$6282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } + connect \Y $pos$libresoc.v:140206$6282_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:140229$6305 + parameter \WIDTH 64 + connect \A \ldo_r + connect \B \ldd_o + connect \S \ld_ok + connect \Y $ternary$libresoc.v:140229$6305_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:140230$6306 + parameter \WIDTH 64 + connect \A \ea_r + connect \B \alu_o + connect \S \alu_l_q_alu + connect \Y $ternary$libresoc.v:140230$6306_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" + cell $mux $ternary$libresoc.v:140231$6307 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \oper_r__zero_a + connect \Y $ternary$libresoc.v:140231$6307_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" + cell $mux $ternary$libresoc.v:140232$6308 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \oper_r__imm_data__data + connect \S \oper_r__imm_data__ok + connect \Y $ternary$libresoc.v:140232$6308_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140317.9-140323.4" + cell \adr_l \adr_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_adr \adr_l_q_adr + connect \r_adr \adr_l_r_adr + connect \s_adr \adr_l_s_adr + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140324.15-140330.4" + cell \alu_l$128 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140331.9-140337.4" + cell \lod_l \lod_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \qn_lod \lod_l_qn_lod + connect \r_lod \lod_l_r_lod + connect \s_lod \lod_l_s_lod + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140338.9-140344.4" + cell \lsd_l \lsd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_lsd \lsd_l_q_lsd + connect \r_lsd \lsd_l_r_lsd + connect \s_lsd \lsd_l_s_lsd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140345.15-140351.4" + cell \opc_l$126 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140352.15-140358.4" + cell \rst_l$129 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rst \rst_l_q_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140359.15-140365.4" + cell \src_l$127 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140366.9-140372.4" + cell \sto_l \sto_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_sto \sto_l_q_sto + connect \r_sto \sto_l_r_sto + connect \s_sto \sto_l_s_sto + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140373.9-140379.4" + cell \upd_l \upd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_upd \upd_l_q_upd + connect \r_upd \upd_l_r_upd + connect \s_upd \upd_l_s_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:140380.9-140386.4" + cell \wri_l \wri_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_wri \wri_l_q_wri + connect \r_wri \wri_l_r_wri + connect \s_wri \wri_l_s_wri + end + attribute \src "libresoc.v:139410.7-139410.20" + process $proc$libresoc.v:139410$6471 + assign { } { } + assign $0\initial[0:0] 1'0 sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:142361.3-142377.6" - process $proc$libresoc.v:142361$6027 + attribute \src "libresoc.v:139606.7-139606.25" + process $proc$libresoc.v:139606$6472 assign { } { } + assign $1\adr_l_r_adr[0:0] 1'1 + sync always + sync init + update \adr_l_r_adr $1\adr_l_r_adr[0:0] + end + attribute \src "libresoc.v:139620.7-139620.20" + process $proc$libresoc.v:139620$6473 assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$6028 $2\dmi0_addrsr__oe$next[0:0]$6030 - attribute \src "libresoc.v:142362.5-142362.29" - switch \initial - attribute \src "libresoc.v:142362.9-142362.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$443 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$6029 \dmi0_addrsr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$6029 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$6030 1'0 - case - assign $2\dmi0_addrsr__oe$next[0:0]$6030 $1\dmi0_addrsr__oe$next[0:0]$6029 - end + assign $1\alu_ok[0:0] 1'0 sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6028 + sync init + update \alu_ok $1\alu_ok[0:0] end - attribute \src "libresoc.v:142378.3-142398.6" - process $proc$libresoc.v:142378$6031 + attribute \src "libresoc.v:139666.14-139666.41" + process $proc$libresoc.v:139666$6474 assign { } { } + assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ea_r $1\ea_r[63:0] + end + attribute \src "libresoc.v:139696.14-139696.42" + process $proc$libresoc.v:139696$6475 assign { } { } + assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldo_r $1\ldo_r[63:0] + end + attribute \src "libresoc.v:139701.14-139701.62" + process $proc$libresoc.v:139701$6476 assign { } { } + assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] + end + attribute \src "libresoc.v:139706.7-139706.34" + process $proc$libresoc.v:139706$6477 assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$6032 $3\dmi0_addrsr_reg$next[7:0]$6035 - attribute \src "libresoc.v:142379.5-142379.29" - switch \initial - attribute \src "libresoc.v:142379.9-142379.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \dmi0_addrsr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$6033 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } - case - assign $1\dmi0_addrsr_reg$next[7:0]$6033 \dmi0_addrsr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \dmi0_addrsr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$6034 \dmi0_addrsr__i - case - assign $2\dmi0_addrsr_reg$next[7:0]$6034 $1\dmi0_addrsr_reg$next[7:0]$6033 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$6035 8'00000000 - case - assign $3\dmi0_addrsr_reg$next[7:0]$6035 $2\dmi0_addrsr_reg$next[7:0]$6034 - end + assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6032 + sync init + update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:142399.3-142407.6" - process $proc$libresoc.v:142399$6036 + attribute \src "libresoc.v:139755.7-139755.25" + process $proc$libresoc.v:139755$6478 assign { } { } + assign $1\lsd_l_r_lsd[0:0] 1'1 + sync always + sync init + update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] + end + attribute \src "libresoc.v:139769.7-139769.25" + process $proc$libresoc.v:139769$6479 assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$6037 $1\dmi0_datasr_update_core$next[0:0]$6038 - attribute \src "libresoc.v:142400.5-142400.29" - switch \initial - attribute \src "libresoc.v:142400.9-142400.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$6038 1'0 - case - assign $1\dmi0_datasr_update_core$next[0:0]$6038 \dmi0_datasr_update - end + assign $1\opc_l_r_opc[0:0] 1'1 sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6037 + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:142408.3-142416.6" - process $proc$libresoc.v:142408$6039 + attribute \src "libresoc.v:139773.7-139773.25" + process $proc$libresoc.v:139773$6480 assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:139902.7-139902.34" + process $proc$libresoc.v:139902$6481 assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$6040 $1\dmi0_datasr_update_core_prev$next[0:0]$6041 - attribute \src "libresoc.v:142409.5-142409.29" - switch \initial - attribute \src "libresoc.v:142409.9-142409.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 1'0 - case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 \dmi0_datasr_update_core - end + assign $1\oper_r__byte_reverse[0:0] 1'0 sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6040 + sync init + update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:142417.3-142433.6" - process $proc$libresoc.v:142417$6042 + attribute \src "libresoc.v:139906.13-139906.36" + process $proc$libresoc.v:139906$6482 assign { } { } + assign $1\oper_r__data_len[3:0] 4'0000 + sync always + sync init + update \oper_r__data_len $1\oper_r__data_len[3:0] + end + attribute \src "libresoc.v:139924.14-139924.40" + process $proc$libresoc.v:139924$6483 assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$6043 $2\dmi0_datasr__oe$next[1:0]$6045 - attribute \src "libresoc.v:142418.5-142418.29" - switch \initial - attribute \src "libresoc.v:142418.9-142418.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$463 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$6044 \dmi0_datasr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$6044 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$6045 2'00 - case - assign $2\dmi0_datasr__oe$next[1:0]$6045 $1\dmi0_datasr__oe$next[1:0]$6044 - end + assign $1\oper_r__fn_unit[12:0] 13'0000000000000 sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6043 + sync init + update \oper_r__fn_unit $1\oper_r__fn_unit[12:0] end - attribute \src "libresoc.v:142434.3-142454.6" - process $proc$libresoc.v:142434$6046 + attribute \src "libresoc.v:139928.14-139928.59" + process $proc$libresoc.v:139928$6484 assign { } { } + assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] + end + attribute \src "libresoc.v:139932.7-139932.34" + process $proc$libresoc.v:139932$6485 assign { } { } + assign $1\oper_r__imm_data__ok[0:0] 1'0 + sync always + sync init + update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] + end + attribute \src "libresoc.v:139936.14-139936.34" + process $proc$libresoc.v:139936$6486 assign { } { } + assign $1\oper_r__insn[31:0] 0 + sync always + sync init + update \oper_r__insn $1\oper_r__insn[31:0] + end + attribute \src "libresoc.v:140014.13-140014.38" + process $proc$libresoc.v:140014$6487 assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$6047 $3\dmi0_datasr_reg$next[63:0]$6050 - attribute \src "libresoc.v:142435.5-142435.29" - switch \initial - attribute \src "libresoc.v:142435.9-142435.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \dmi0_datasr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$6048 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } - case - assign $1\dmi0_datasr_reg$next[63:0]$6048 \dmi0_datasr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \dmi0_datasr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$6049 \dmi0_datasr__i - case - assign $2\dmi0_datasr_reg$next[63:0]$6049 $1\dmi0_datasr_reg$next[63:0]$6048 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$6050 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dmi0_datasr_reg$next[63:0]$6050 $2\dmi0_datasr_reg$next[63:0]$6049 - end + assign $1\oper_r__insn_type[6:0] 7'0000000 sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6047 + sync init + update \oper_r__insn_type $1\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:142455.3-142463.6" - process $proc$libresoc.v:142455$6051 + attribute \src "libresoc.v:140018.7-140018.30" + process $proc$libresoc.v:140018$6488 assign { } { } + assign $1\oper_r__is_32bit[0:0] 1'0 + sync always + sync init + update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] + end + attribute \src "libresoc.v:140022.7-140022.31" + process $proc$libresoc.v:140022$6489 assign { } { } - assign $0\sr5_update_core$next[0:0]$6052 $1\sr5_update_core$next[0:0]$6053 - attribute \src "libresoc.v:142456.5-142456.29" - switch \initial - attribute \src "libresoc.v:142456.9-142456.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5_update_core$next[0:0]$6053 1'0 - case - assign $1\sr5_update_core$next[0:0]$6053 \sr5_update - end + assign $1\oper_r__is_signed[0:0] 1'0 sync always - update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6052 + sync init + update \oper_r__is_signed $1\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:142464.3-142472.6" - process $proc$libresoc.v:142464$6054 + attribute \src "libresoc.v:140031.13-140031.37" + process $proc$libresoc.v:140031$6490 assign { } { } + assign $1\oper_r__ldst_mode[1:0] 2'00 + sync always + sync init + update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] + end + attribute \src "libresoc.v:140035.7-140035.28" + process $proc$libresoc.v:140035$6491 assign { } { } - assign $0\sr5_update_core_prev$next[0:0]$6055 $1\sr5_update_core_prev$next[0:0]$6056 - attribute \src "libresoc.v:142465.5-142465.29" - switch \initial - attribute \src "libresoc.v:142465.9-142465.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5_update_core_prev$next[0:0]$6056 1'0 - case - assign $1\sr5_update_core_prev$next[0:0]$6056 \sr5_update_core - end + assign $1\oper_r__oe__oe[0:0] 1'0 sync always - update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6055 + sync init + update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:142473.3-142489.6" - process $proc$libresoc.v:142473$6057 + attribute \src "libresoc.v:140039.7-140039.28" + process $proc$libresoc.v:140039$6492 assign { } { } + assign $1\oper_r__oe__ok[0:0] 1'0 + sync always + sync init + update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] + end + attribute \src "libresoc.v:140043.7-140043.28" + process $proc$libresoc.v:140043$6493 assign { } { } - assign $0\sr5__oe$next[0:0]$6058 $2\sr5__oe$next[0:0]$6060 - attribute \src "libresoc.v:142474.5-142474.29" - switch \initial - attribute \src "libresoc.v:142474.9-142474.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$481 - attribute \src "libresoc.v:0.0-0.0" + assign $1\oper_r__rc__ok[0:0] 1'0 + sync always + sync init + update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] + end + attribute \src "libresoc.v:140047.7-140047.28" + process $proc$libresoc.v:140047$6494 + assign { } { } + assign $1\oper_r__rc__rc[0:0] 1'0 + sync always + sync init + update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] + end + attribute \src "libresoc.v:140051.7-140051.33" + process $proc$libresoc.v:140051$6495 + assign { } { } + assign $1\oper_r__sign_extend[0:0] 1'0 + sync always + sync init + update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] + end + attribute \src "libresoc.v:140055.7-140055.28" + process $proc$libresoc.v:140055$6496 + assign { } { } + assign $1\oper_r__zero_a[0:0] 1'0 + sync always + sync init + update \oper_r__zero_a $1\oper_r__zero_a[0:0] + end + attribute \src "libresoc.v:140059.7-140059.21" + process $proc$libresoc.v:140059$6497 + assign { } { } + assign $1\p_st_go[0:0] 1'0 + sync always + sync init + update \p_st_go $1\p_st_go[0:0] + end + attribute \src "libresoc.v:140101.13-140101.31" + process $proc$libresoc.v:140101$6498 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:140105.13-140105.31" + process $proc$libresoc.v:140105$6499 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:140109.14-140109.43" + process $proc$libresoc.v:140109$6500 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:140113.14-140113.43" + process $proc$libresoc.v:140113$6501 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:140117.14-140117.43" + process $proc$libresoc.v:140117$6502 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:140127.7-140127.25" + process $proc$libresoc.v:140127$6503 + assign { } { } + assign $1\sto_l_r_sto[0:0] 1'1 + sync always + sync init + update \sto_l_r_sto $1\sto_l_r_sto[0:0] + end + attribute \src "libresoc.v:140137.7-140137.25" + process $proc$libresoc.v:140137$6504 + assign { } { } + assign $1\upd_l_r_upd[0:0] 1'1 + sync always + sync init + update \upd_l_r_upd $1\upd_l_r_upd[0:0] + end + attribute \src "libresoc.v:140141.7-140141.25" + process $proc$libresoc.v:140141$6505 + assign { } { } + assign $1\upd_l_s_upd[0:0] 1'0 + sync always + sync init + update \upd_l_s_upd $1\upd_l_s_upd[0:0] + end + attribute \src "libresoc.v:140151.7-140151.25" + process $proc$libresoc.v:140151$6506 + assign { } { } + assign $1\wri_l_r_wri[0:0] 1'1 + sync always + sync init + update \wri_l_r_wri $1\wri_l_r_wri[0:0] + end + attribute \src "libresoc.v:140247.3-140248.57" + process $proc$libresoc.v:140247$6323 + assign { } { } + assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next + sync posedge \coresync_clk + update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] + end + attribute \src "libresoc.v:140249.3-140250.33" + process $proc$libresoc.v:140249$6324 + assign { } { } + assign $0\ldst_port0_addr_i[95:0] \$175 + sync posedge \coresync_clk + update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] + end + attribute \src "libresoc.v:140251.3-140252.21" + process $proc$libresoc.v:140251$6325 + assign { } { } + assign $0\alu_ok[0:0] \$96 + sync posedge \coresync_clk + update \alu_ok $0\alu_ok[0:0] + end + attribute \src "libresoc.v:140253.3-140254.25" + process $proc$libresoc.v:140253$6326 + assign { } { } + assign $0\ea_r[63:0] \ea_r$next + sync posedge \coresync_clk + update \ea_r $0\ea_r[63:0] + end + attribute \src "libresoc.v:140255.3-140256.29" + process $proc$libresoc.v:140255$6327 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:140257.3-140258.29" + process $proc$libresoc.v:140257$6328 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:140259.3-140260.29" + process $proc$libresoc.v:140259$6329 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:140261.3-140262.27" + process $proc$libresoc.v:140261$6330 + assign { } { } + assign $0\ldo_r[63:0] \ldo_r$next + sync posedge \coresync_clk + update \ldo_r $0\ldo_r[63:0] + end + attribute \src "libresoc.v:140263.3-140264.51" + process $proc$libresoc.v:140263$6331 + assign { } { } + assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next + sync posedge \coresync_clk + update \oper_r__insn_type $0\oper_r__insn_type[6:0] + end + attribute \src "libresoc.v:140265.3-140266.47" + process $proc$libresoc.v:140265$6332 + assign { } { } + assign $0\oper_r__fn_unit[12:0] \oper_r__fn_unit$next + sync posedge \coresync_clk + update \oper_r__fn_unit $0\oper_r__fn_unit[12:0] + end + attribute \src "libresoc.v:140267.3-140268.61" + process $proc$libresoc.v:140267$6333 + assign { } { } + assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next + sync posedge \coresync_clk + update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] + end + attribute \src "libresoc.v:140269.3-140270.57" + process $proc$libresoc.v:140269$6334 + assign { } { } + assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next + sync posedge \coresync_clk + update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] + end + attribute \src "libresoc.v:140271.3-140272.45" + process $proc$libresoc.v:140271$6335 + assign { } { } + assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next + sync posedge \coresync_clk + update \oper_r__zero_a $0\oper_r__zero_a[0:0] + end + attribute \src "libresoc.v:140273.3-140274.45" + process $proc$libresoc.v:140273$6336 + assign { } { } + assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next + sync posedge \coresync_clk + update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] + end + attribute \src "libresoc.v:140275.3-140276.45" + process $proc$libresoc.v:140275$6337 + assign { } { } + assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next + sync posedge \coresync_clk + update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] + end + attribute \src "libresoc.v:140277.3-140278.45" + process $proc$libresoc.v:140277$6338 + assign { } { } + assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next + sync posedge \coresync_clk + update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] + end + attribute \src "libresoc.v:140279.3-140280.45" + process $proc$libresoc.v:140279$6339 + assign { } { } + assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next + sync posedge \coresync_clk + update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] + end + attribute \src "libresoc.v:140281.3-140282.49" + process $proc$libresoc.v:140281$6340 + assign { } { } + assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next + sync posedge \coresync_clk + update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] + end + attribute \src "libresoc.v:140283.3-140284.51" + process $proc$libresoc.v:140283$6341 + assign { } { } + assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next + sync posedge \coresync_clk + update \oper_r__is_signed $0\oper_r__is_signed[0:0] + end + attribute \src "libresoc.v:140285.3-140286.49" + process $proc$libresoc.v:140285$6342 + assign { } { } + assign $0\oper_r__data_len[3:0] \oper_r__data_len$next + sync posedge \coresync_clk + update \oper_r__data_len $0\oper_r__data_len[3:0] + end + attribute \src "libresoc.v:140287.3-140288.57" + process $proc$libresoc.v:140287$6343 + assign { } { } + assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next + sync posedge \coresync_clk + update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] + end + attribute \src "libresoc.v:140289.3-140290.55" + process $proc$libresoc.v:140289$6344 + assign { } { } + assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next + sync posedge \coresync_clk + update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] + end + attribute \src "libresoc.v:140291.3-140292.51" + process $proc$libresoc.v:140291$6345 + assign { } { } + assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next + sync posedge \coresync_clk + update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] + end + attribute \src "libresoc.v:140293.3-140294.41" + process $proc$libresoc.v:140293$6346 + assign { } { } + assign $0\oper_r__insn[31:0] \oper_r__insn$next + sync posedge \coresync_clk + update \oper_r__insn $0\oper_r__insn[31:0] + end + attribute \src "libresoc.v:140295.3-140296.39" + process $proc$libresoc.v:140295$6347 + assign { } { } + assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next + sync posedge \coresync_clk + update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] + end + attribute \src "libresoc.v:140297.3-140298.39" + process $proc$libresoc.v:140297$6348 + assign { } { } + assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next + sync posedge \coresync_clk + update \sto_l_r_sto $0\sto_l_r_sto[0:0] + end + attribute \src "libresoc.v:140299.3-140300.39" + process $proc$libresoc.v:140299$6349 + assign { } { } + assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next + sync posedge \coresync_clk + update \upd_l_r_upd $0\upd_l_r_upd[0:0] + end + attribute \src "libresoc.v:140301.3-140302.39" + process $proc$libresoc.v:140301$6350 + assign { } { } + assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next + sync posedge \coresync_clk + update \upd_l_s_upd $0\upd_l_s_upd[0:0] + end + attribute \src "libresoc.v:140303.3-140304.39" + process $proc$libresoc.v:140303$6351 + assign { } { } + assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next + sync posedge \coresync_clk + update \wri_l_r_wri $0\wri_l_r_wri[0:0] + end + attribute \src "libresoc.v:140305.3-140306.39" + process $proc$libresoc.v:140305$6352 + assign { } { } + assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next + sync posedge \coresync_clk + update \adr_l_r_adr $0\adr_l_r_adr[0:0] + end + attribute \src "libresoc.v:140307.3-140308.39" + process $proc$libresoc.v:140307$6353 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:140309.3-140310.39" + process $proc$libresoc.v:140309$6354 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:140311.3-140312.39" + process $proc$libresoc.v:140311$6355 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:140313.3-140314.39" + process $proc$libresoc.v:140313$6356 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:140315.3-140316.28" + process $proc$libresoc.v:140315$6357 + assign { } { } + assign $0\p_st_go[0:0] \cu_st__go_i + sync posedge \coresync_clk + update \p_st_go $0\p_st_go[0:0] + end + attribute \src "libresoc.v:140387.3-140395.6" + process $proc$libresoc.v:140387$6358 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$6359 $1\opc_l_s_opc$next[0:0]$6360 + attribute \src "libresoc.v:140388.5-140388.29" + switch \initial + attribute \src "libresoc.v:140388.9-140388.17" case 1'1 - assign { } { } - assign $1\sr5__oe$next[0:0]$6059 \sr5_isir - attribute \src "libresoc.v:0.0-0.0" case - assign { } { } - assign $1\sr5__oe$next[0:0]$6059 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5__oe$next[0:0]$6060 1'0 + assign $1\opc_l_s_opc$next[0:0]$6360 1'0 case - assign $2\sr5__oe$next[0:0]$6060 $1\sr5__oe$next[0:0]$6059 + assign $1\opc_l_s_opc$next[0:0]$6360 \cu_issue_i end sync always - update \sr5__oe$next $0\sr5__oe$next[0:0]$6058 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6359 end - attribute \src "libresoc.v:142490.3-142510.6" - process $proc$libresoc.v:142490$6061 - assign { } { } + attribute \src "libresoc.v:140396.3-140404.6" + process $proc$libresoc.v:140396$6361 assign { } { } assign { } { } - assign { } { } - assign $0\sr5_reg$next[1:0]$6062 $3\sr5_reg$next[1:0]$6065 - attribute \src "libresoc.v:142491.5-142491.29" + assign $0\opc_l_r_opc$next[0:0]$6362 $1\opc_l_r_opc$next[0:0]$6363 + attribute \src "libresoc.v:140397.5-140397.29" switch \initial - attribute \src "libresoc.v:142491.9-142491.17" + attribute \src "libresoc.v:140397.9-140397.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \sr5_shift + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_reg$next[1:0]$6063 { \TAP_bus__tdi \sr5_reg [1] } + assign $1\opc_l_r_opc$next[0:0]$6363 1'1 case - assign $1\sr5_reg$next[1:0]$6063 \sr5_reg + assign $1\opc_l_r_opc$next[0:0]$6363 \reset_o end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \sr5_capture - attribute \src "libresoc.v:0.0-0.0" + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6362 + end + attribute \src "libresoc.v:140405.3-140413.6" + process $proc$libresoc.v:140405$6364 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$6365 $1\src_l_s_src$next[2:0]$6366 + attribute \src "libresoc.v:140406.5-140406.29" + switch \initial + attribute \src "libresoc.v:140406.9-140406.17" case 1'1 - assign { } { } - assign $2\sr5_reg$next[1:0]$6064 \sr5__i case - assign $2\sr5_reg$next[1:0]$6064 $1\sr5_reg$next[1:0]$6063 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr5_reg$next[1:0]$6065 2'00 + assign $1\src_l_s_src$next[2:0]$6366 3'000 case - assign $3\sr5_reg$next[1:0]$6065 $2\sr5_reg$next[1:0]$6064 + assign $1\src_l_s_src$next[2:0]$6366 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \sr5_reg$next $0\sr5_reg$next[1:0]$6062 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6365 end - attribute \src "libresoc.v:142511.3-142537.6" - process $proc$libresoc.v:142511$6066 + attribute \src "libresoc.v:140414.3-140422.6" + process $proc$libresoc.v:140414$6367 assign { } { } - assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:142512.5-142512.29" + assign { } { } + assign $0\src_l_r_src$next[2:0]$6368 $1\src_l_r_src$next[2:0]$6369 + attribute \src "libresoc.v:140415.5-140415.29" switch \initial - attribute \src "libresoc.v:142512.9-142512.17" + attribute \src "libresoc.v:140415.9-140415.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" - switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } - attribute \src "libresoc.v:0.0-0.0" - case 6'-----1 - assign { } { } - assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'----1- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'---1-- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'--1--- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'-1---- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 6'1----- + case 1'1 assign { } { } - assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] - attribute \src "libresoc.v:0.0-0.0" + assign $1\src_l_r_src$next[2:0]$6369 3'111 case - assign { } { } - assign $1\TAP_bus__tdo[0:0] \TAP_tdo + assign $1\src_l_r_src$next[2:0]$6369 \reset_r end sync always - update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6368 end - attribute \src "libresoc.v:142538.3-142570.6" - process $proc$libresoc.v:142538$6067 - assign { } { } + attribute \src "libresoc.v:140423.3-140431.6" + process $proc$libresoc.v:140423$6370 assign { } { } assign { } { } - assign $0\jtag_wb__adr$next[28:0]$6068 $4\jtag_wb__adr$next[28:0]$6072 - attribute \src "libresoc.v:142539.5-142539.29" + assign $0\adr_l_r_adr$next[0:0]$6371 $1\adr_l_r_adr$next[0:0]$6372 + attribute \src "libresoc.v:140424.5-140424.29" switch \initial - attribute \src "libresoc.v:142539.9-142539.17" + attribute \src "libresoc.v:140424.9-140424.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\jtag_wb__adr$next[28:0]$6069 $2\jtag_wb__adr$next[28:0]$6070 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb_addrsr__o - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\jtag_wb__adr$next[28:0]$6070 \$495 [28:0] - case - assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb__adr - end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$6069 $3\jtag_wb__adr$next[28:0]$6071 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb__adr$next[28:0]$6071 \$498 [28:0] - case - assign $3\jtag_wb__adr$next[28:0]$6071 \jtag_wb__adr - end + assign $1\adr_l_r_adr$next[0:0]$6372 1'1 + case + assign $1\adr_l_r_adr$next[0:0]$6372 \reset_a + end + sync always + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6371 + end + attribute \src "libresoc.v:140432.3-140440.6" + process $proc$libresoc.v:140432$6373 + assign { } { } + assign { } { } + assign $0\wri_l_r_wri$next[0:0]$6374 $1\wri_l_r_wri$next[0:0]$6375 + attribute \src "libresoc.v:140433.5-140433.29" + switch \initial + attribute \src "libresoc.v:140433.9-140433.17" + case 1'1 case - assign $1\jtag_wb__adr$next[28:0]$6069 \jtag_wb__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\jtag_wb__adr$next[28:0]$6072 29'00000000000000000000000000000 + assign $1\wri_l_r_wri$next[0:0]$6375 1'1 case - assign $4\jtag_wb__adr$next[28:0]$6072 $1\jtag_wb__adr$next[28:0]$6069 + assign $1\wri_l_r_wri$next[0:0]$6375 \$38 [0] end sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6068 + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6374 end - attribute \src "libresoc.v:142571.3-142623.6" - process $proc$libresoc.v:142571$6073 + attribute \src "libresoc.v:140441.3-140449.6" + process $proc$libresoc.v:140441$6376 assign { } { } assign { } { } - assign { } { } - assign $0\fsm_state$next[2:0]$6074 $5\fsm_state$next[2:0]$6079 - attribute \src "libresoc.v:142572.5-142572.29" + assign $0\upd_l_s_upd$next[0:0]$6377 $1\upd_l_s_upd$next[0:0]$6378 + attribute \src "libresoc.v:140442.5-140442.29" switch \initial - attribute \src "libresoc.v:142572.9-142572.17" + attribute \src "libresoc.v:140442.9-140442.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\fsm_state$next[2:0]$6075 $2\fsm_state$next[2:0]$6076 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\fsm_state$next[2:0]$6076 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\fsm_state$next[2:0]$6076 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\fsm_state$next[2:0]$6076 3'010 - case - assign $2\fsm_state$next[2:0]$6076 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\fsm_state$next[2:0]$6075 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\fsm_state$next[2:0]$6075 $3\fsm_state$next[2:0]$6077 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[2:0]$6077 3'000 - case - assign $3\fsm_state$next[2:0]$6077 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\fsm_state$next[2:0]$6075 3'100 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\fsm_state$next[2:0]$6075 $4\fsm_state$next[2:0]$6078 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[2:0]$6078 3'001 - case - assign $4\fsm_state$next[2:0]$6078 \fsm_state - end + assign $1\upd_l_s_upd$next[0:0]$6378 1'0 + case + assign $1\upd_l_s_upd$next[0:0]$6378 \reset_i + end + sync always + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6377 + end + attribute \src "libresoc.v:140450.3-140458.6" + process $proc$libresoc.v:140450$6379 + assign { } { } + assign { } { } + assign $0\upd_l_r_upd$next[0:0]$6380 $1\upd_l_r_upd$next[0:0]$6381 + attribute \src "libresoc.v:140451.5-140451.29" + switch \initial + attribute \src "libresoc.v:140451.9-140451.17" + case 1'1 case - assign $1\fsm_state$next[2:0]$6075 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[2:0]$6079 3'000 + assign $1\upd_l_r_upd$next[0:0]$6381 1'1 case - assign $5\fsm_state$next[2:0]$6079 $1\fsm_state$next[2:0]$6075 + assign $1\upd_l_r_upd$next[0:0]$6381 \reset_u end sync always - update \fsm_state$next $0\fsm_state$next[2:0]$6074 + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6380 end - attribute \src "libresoc.v:142624.3-142650.6" - process $proc$libresoc.v:142624$6080 + attribute \src "libresoc.v:140459.3-140467.6" + process $proc$libresoc.v:140459$6382 assign { } { } assign { } { } - assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$6081 $3\jtag_wb__dat_w$next[63:0]$6084 - attribute \src "libresoc.v:142625.5-142625.29" + assign $0\sto_l_r_sto$next[0:0]$6383 $1\sto_l_r_sto$next[0:0]$6384 + attribute \src "libresoc.v:140460.5-140460.29" switch \initial - attribute \src "libresoc.v:142625.9-142625.17" + attribute \src "libresoc.v:140460.9-140460.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 3'000 + case 1'1 assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$6082 $2\jtag_wb__dat_w$next[63:0]$6083 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb_datasr__o - case - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w - end + assign $1\sto_l_r_sto$next[0:0]$6384 1'1 + case + assign $1\sto_l_r_sto$next[0:0]$6384 \$59 + end + sync always + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6383 + end + attribute \src "libresoc.v:140468.3-140476.6" + process $proc$libresoc.v:140468$6385 + assign { } { } + assign { } { } + assign $0\lsd_l_r_lsd$next[0:0]$6386 $1\lsd_l_r_lsd$next[0:0]$6387 + attribute \src "libresoc.v:140469.5-140469.29" + switch \initial + attribute \src "libresoc.v:140469.9-140469.17" + case 1'1 case - assign $1\jtag_wb__dat_w$next[63:0]$6082 \jtag_wb__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$6084 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\lsd_l_r_lsd$next[0:0]$6387 1'1 case - assign $3\jtag_wb__dat_w$next[63:0]$6084 $1\jtag_wb__dat_w$next[63:0]$6082 + assign $1\lsd_l_r_lsd$next[0:0]$6387 \$63 end sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6081 + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6386 end - attribute \src "libresoc.v:142651.3-142671.6" - process $proc$libresoc.v:142651$6085 + attribute \src "libresoc.v:140477.3-140519.6" + process $proc$libresoc.v:140477$6388 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$6086 $3\jtag_wb_datasr__i$next[63:0]$6089 - attribute \src "libresoc.v:142652.5-142652.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__byte_reverse$next[0:0]$6389 $2\oper_r__byte_reverse$next[0:0]$6421 + assign $0\oper_r__data_len$next[3:0]$6390 $2\oper_r__data_len$next[3:0]$6422 + assign $0\oper_r__fn_unit$next[12:0]$6391 $2\oper_r__fn_unit$next[12:0]$6423 + assign { } { } + assign { } { } + assign $0\oper_r__insn$next[31:0]$6394 $2\oper_r__insn$next[31:0]$6426 + assign $0\oper_r__insn_type$next[6:0]$6395 $2\oper_r__insn_type$next[6:0]$6427 + assign $0\oper_r__is_32bit$next[0:0]$6396 $2\oper_r__is_32bit$next[0:0]$6428 + assign $0\oper_r__is_signed$next[0:0]$6397 $2\oper_r__is_signed$next[0:0]$6429 + assign $0\oper_r__ldst_mode$next[1:0]$6398 $2\oper_r__ldst_mode$next[1:0]$6430 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__sign_extend$next[0:0]$6403 $2\oper_r__sign_extend$next[0:0]$6435 + assign $0\oper_r__zero_a$next[0:0]$6404 $2\oper_r__zero_a$next[0:0]$6436 + assign $0\oper_r__imm_data__data$next[63:0]$6392 $3\oper_r__imm_data__data$next[63:0]$6437 + assign $0\oper_r__imm_data__ok$next[0:0]$6393 $3\oper_r__imm_data__ok$next[0:0]$6438 + assign $0\oper_r__oe__oe$next[0:0]$6399 $3\oper_r__oe__oe$next[0:0]$6439 + assign $0\oper_r__oe__ok$next[0:0]$6400 $3\oper_r__oe__ok$next[0:0]$6440 + assign $0\oper_r__rc__ok$next[0:0]$6401 $3\oper_r__rc__ok$next[0:0]$6441 + assign $0\oper_r__rc__rc$next[0:0]$6402 $3\oper_r__rc__rc$next[0:0]$6442 + attribute \src "libresoc.v:140478.5-140478.29" switch \initial - attribute \src "libresoc.v:142652.9-142652.17" + attribute \src "libresoc.v:140478.9-140478.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 1'1 assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$6087 $2\jtag_wb_datasr__i$next[63:0]$6088 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb__dat_r - case - assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb_datasr__i - end + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\oper_r__insn$next[31:0]$6410 $1\oper_r__ldst_mode$next[1:0]$6414 $1\oper_r__sign_extend$next[0:0]$6419 $1\oper_r__byte_reverse$next[0:0]$6405 $1\oper_r__data_len$next[3:0]$6406 $1\oper_r__is_signed$next[0:0]$6413 $1\oper_r__is_32bit$next[0:0]$6412 $1\oper_r__oe__ok$next[0:0]$6416 $1\oper_r__oe__oe$next[0:0]$6415 $1\oper_r__rc__ok$next[0:0]$6417 $1\oper_r__rc__rc$next[0:0]$6418 $1\oper_r__zero_a$next[0:0]$6420 $1\oper_r__imm_data__ok$next[0:0]$6409 $1\oper_r__imm_data__data$next[63:0]$6408 $1\oper_r__fn_unit$next[12:0]$6407 $1\oper_r__insn_type$next[6:0]$6411 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + case + assign $1\oper_r__byte_reverse$next[0:0]$6405 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6406 \oper_r__data_len + assign $1\oper_r__fn_unit$next[12:0]$6407 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6408 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6409 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6410 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6411 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6412 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6413 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6414 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6415 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6416 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6417 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6418 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6419 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6420 \oper_r__zero_a + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" + switch \cu_done_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\oper_r__insn$next[31:0]$6426 $2\oper_r__ldst_mode$next[1:0]$6430 $2\oper_r__sign_extend$next[0:0]$6435 $2\oper_r__byte_reverse$next[0:0]$6421 $2\oper_r__data_len$next[3:0]$6422 $2\oper_r__is_signed$next[0:0]$6429 $2\oper_r__is_32bit$next[0:0]$6428 $2\oper_r__oe__ok$next[0:0]$6432 $2\oper_r__oe__oe$next[0:0]$6431 $2\oper_r__rc__ok$next[0:0]$6433 $2\oper_r__rc__rc$next[0:0]$6434 $2\oper_r__zero_a$next[0:0]$6436 $2\oper_r__imm_data__ok$next[0:0]$6425 $2\oper_r__imm_data__data$next[63:0]$6424 $2\oper_r__fn_unit$next[12:0]$6423 $2\oper_r__insn_type$next[6:0]$6427 } 132'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $1\jtag_wb_datasr__i$next[63:0]$6087 \jtag_wb_datasr__i + assign $2\oper_r__byte_reverse$next[0:0]$6421 $1\oper_r__byte_reverse$next[0:0]$6405 + assign $2\oper_r__data_len$next[3:0]$6422 $1\oper_r__data_len$next[3:0]$6406 + assign $2\oper_r__fn_unit$next[12:0]$6423 $1\oper_r__fn_unit$next[12:0]$6407 + assign $2\oper_r__imm_data__data$next[63:0]$6424 $1\oper_r__imm_data__data$next[63:0]$6408 + assign $2\oper_r__imm_data__ok$next[0:0]$6425 $1\oper_r__imm_data__ok$next[0:0]$6409 + assign $2\oper_r__insn$next[31:0]$6426 $1\oper_r__insn$next[31:0]$6410 + assign $2\oper_r__insn_type$next[6:0]$6427 $1\oper_r__insn_type$next[6:0]$6411 + assign $2\oper_r__is_32bit$next[0:0]$6428 $1\oper_r__is_32bit$next[0:0]$6412 + assign $2\oper_r__is_signed$next[0:0]$6429 $1\oper_r__is_signed$next[0:0]$6413 + assign $2\oper_r__ldst_mode$next[1:0]$6430 $1\oper_r__ldst_mode$next[1:0]$6414 + assign $2\oper_r__oe__oe$next[0:0]$6431 $1\oper_r__oe__oe$next[0:0]$6415 + assign $2\oper_r__oe__ok$next[0:0]$6432 $1\oper_r__oe__ok$next[0:0]$6416 + assign $2\oper_r__rc__ok$next[0:0]$6433 $1\oper_r__rc__ok$next[0:0]$6417 + assign $2\oper_r__rc__rc$next[0:0]$6434 $1\oper_r__rc__rc$next[0:0]$6418 + assign $2\oper_r__sign_extend$next[0:0]$6435 $1\oper_r__sign_extend$next[0:0]$6419 + assign $2\oper_r__zero_a$next[0:0]$6436 $1\oper_r__zero_a$next[0:0]$6420 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$6089 64'0000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\oper_r__imm_data__data$next[63:0]$6437 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6438 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6442 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6441 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6439 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6440 1'0 case - assign $3\jtag_wb_datasr__i$next[63:0]$6089 $1\jtag_wb_datasr__i$next[63:0]$6087 + assign $3\oper_r__imm_data__data$next[63:0]$6437 $2\oper_r__imm_data__data$next[63:0]$6424 + assign $3\oper_r__imm_data__ok$next[0:0]$6438 $2\oper_r__imm_data__ok$next[0:0]$6425 + assign $3\oper_r__oe__oe$next[0:0]$6439 $2\oper_r__oe__oe$next[0:0]$6431 + assign $3\oper_r__oe__ok$next[0:0]$6440 $2\oper_r__oe__ok$next[0:0]$6432 + assign $3\oper_r__rc__ok$next[0:0]$6441 $2\oper_r__rc__ok$next[0:0]$6433 + assign $3\oper_r__rc__rc$next[0:0]$6442 $2\oper_r__rc__rc$next[0:0]$6434 end sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6086 + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6389 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6390 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[12:0]$6391 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6392 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6393 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6394 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6395 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6396 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6397 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6398 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6399 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6400 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6401 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6402 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6403 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6404 end - attribute \src "libresoc.v:142672.3-142704.6" - process $proc$libresoc.v:142672$6090 + attribute \src "libresoc.v:140520.3-140529.6" + process $proc$libresoc.v:140520$6443 assign { } { } assign { } { } - assign { } { } - assign $0\dmi0__addr_i$next[3:0]$6091 $4\dmi0__addr_i$next[3:0]$6095 - attribute \src "libresoc.v:142673.5-142673.29" + assign $0\ldo_r$next[63:0]$6444 $1\ldo_r$next[63:0]$6445 + attribute \src "libresoc.v:140521.5-140521.29" switch \initial - attribute \src "libresoc.v:142673.9-142673.17" + attribute \src "libresoc.v:140521.9-140521.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \ld_ok attribute \src "libresoc.v:0.0-0.0" - case 3'000 + case 1'1 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$6092 $2\dmi0__addr_i$next[3:0]$6093 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0_addrsr__o [3:0] - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6093 \$512 [3:0] - case - assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0__addr_i - end + assign $1\ldo_r$next[63:0]$6445 \ldd_o + case + assign $1\ldo_r$next[63:0]$6445 \ldo_r + end + sync always + update \ldo_r$next $0\ldo_r$next[63:0]$6444 + end + attribute \src "libresoc.v:140530.3-140545.6" + process $proc$libresoc.v:140530$6446 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$6447 $2\src_r0$next[63:0]$6449 + attribute \src "libresoc.v:140531.5-140531.29" + switch \initial + attribute \src "libresoc.v:140531.9-140531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [0] attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$6092 $3\dmi0__addr_i$next[3:0]$6094 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0__addr_i$next[3:0]$6094 \$515 [3:0] - case - assign $3\dmi0__addr_i$next[3:0]$6094 \dmi0__addr_i - end + assign $1\src_r0$next[63:0]$6448 \src1_i case - assign $1\dmi0__addr_i$next[3:0]$6092 \dmi0__addr_i + assign $1\src_r0$next[63:0]$6448 \src_r0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dmi0__addr_i$next[3:0]$6095 4'0000 + assign $2\src_r0$next[63:0]$6449 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\dmi0__addr_i$next[3:0]$6095 $1\dmi0__addr_i$next[3:0]$6092 + assign $2\src_r0$next[63:0]$6449 $1\src_r0$next[63:0]$6448 end sync always - update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6091 + update \src_r0$next $0\src_r0$next[63:0]$6447 end - attribute \src "libresoc.v:142705.3-142757.6" - process $proc$libresoc.v:142705$6096 + attribute \src "libresoc.v:140546.3-140561.6" + process $proc$libresoc.v:140546$6450 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$503$next[2:0]$6097 $5\fsm_state$503$next[2:0]$6102 - attribute \src "libresoc.v:142706.5-142706.29" + assign $0\src_r1$next[63:0]$6451 $2\src_r1$next[63:0]$6453 + attribute \src "libresoc.v:140547.5-140547.29" switch \initial - attribute \src "libresoc.v:142706.9-142706.17" + attribute \src "libresoc.v:140547.9-140547.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\fsm_state$503$next[2:0]$6098 $2\fsm_state$503$next[2:0]$6099 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\fsm_state$503$next[2:0]$6099 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\fsm_state$503$next[2:0]$6099 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\fsm_state$503$next[2:0]$6099 3'010 - case - assign $2\fsm_state$503$next[2:0]$6099 \fsm_state$503 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\fsm_state$503$next[2:0]$6098 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\fsm_state$503$next[2:0]$6098 $3\fsm_state$503$next[2:0]$6100 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$503$next[2:0]$6100 3'000 - case - assign $3\fsm_state$503$next[2:0]$6100 \fsm_state$503 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\fsm_state$503$next[2:0]$6098 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [1] attribute \src "libresoc.v:0.0-0.0" - case 3'100 + case 1'1 assign { } { } - assign $1\fsm_state$503$next[2:0]$6098 $4\fsm_state$503$next[2:0]$6101 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$503$next[2:0]$6101 3'001 - case - assign $4\fsm_state$503$next[2:0]$6101 \fsm_state$503 - end + assign $1\src_r1$next[63:0]$6452 \src2_i case - assign $1\fsm_state$503$next[2:0]$6098 \fsm_state$503 + assign $1\src_r1$next[63:0]$6452 \src_r1 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$503$next[2:0]$6102 3'000 + assign $2\src_r1$next[63:0]$6453 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\fsm_state$503$next[2:0]$6102 $1\fsm_state$503$next[2:0]$6098 + assign $2\src_r1$next[63:0]$6453 $1\src_r1$next[63:0]$6452 end sync always - update \fsm_state$503$next $0\fsm_state$503$next[2:0]$6097 + update \src_r1$next $0\src_r1$next[63:0]$6451 end - attribute \src "libresoc.v:142758.3-142784.6" - process $proc$libresoc.v:142758$6103 + attribute \src "libresoc.v:140562.3-140577.6" + process $proc$libresoc.v:140562$6454 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__din$next[63:0]$6104 $3\dmi0__din$next[63:0]$6107 - attribute \src "libresoc.v:142759.5-142759.29" + assign $0\src_r2$next[63:0]$6455 $2\src_r2$next[63:0]$6457 + attribute \src "libresoc.v:140563.5-140563.29" switch \initial - attribute \src "libresoc.v:142759.9-142759.17" + attribute \src "libresoc.v:140563.9-140563.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [2] attribute \src "libresoc.v:0.0-0.0" - case 3'000 + case 1'1 assign { } { } - assign $1\dmi0__din$next[63:0]$6105 $2\dmi0__din$next[63:0]$6106 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $2\dmi0__din$next[63:0]$6106 \dmi0__din - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $2\dmi0__din$next[63:0]$6106 \dmi0__din - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\dmi0__din$next[63:0]$6106 \dmi0_datasr__o - case - assign $2\dmi0__din$next[63:0]$6106 \dmi0__din - end + assign $1\src_r2$next[63:0]$6456 \src3_i case - assign $1\dmi0__din$next[63:0]$6105 \dmi0__din + assign $1\src_r2$next[63:0]$6456 \src_r2 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__din$next[63:0]$6107 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r2$next[63:0]$6457 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0__din$next[63:0]$6107 $1\dmi0__din$next[63:0]$6105 + assign $2\src_r2$next[63:0]$6457 $1\src_r2$next[63:0]$6456 end sync always - update \dmi0__din$next $0\dmi0__din$next[63:0]$6104 + update \src_r2$next $0\src_r2$next[63:0]$6455 end - attribute \src "libresoc.v:142785.3-142805.6" - process $proc$libresoc.v:142785$6108 - assign { } { } + attribute \src "libresoc.v:140578.3-140587.6" + process $proc$libresoc.v:140578$6458 assign { } { } assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$6109 $3\dmi0_datasr__i$next[63:0]$6112 - attribute \src "libresoc.v:142786.5-142786.29" + assign $0\ea_r$next[63:0]$6459 $1\ea_r$next[63:0]$6460 + attribute \src "libresoc.v:140579.5-140579.29" switch \initial - attribute \src "libresoc.v:142786.9-142786.17" + attribute \src "libresoc.v:140579.9-140579.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \alu_l_q_alu attribute \src "libresoc.v:0.0-0.0" - case 3'011 + case 1'1 assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$6110 $2\dmi0_datasr__i$next[63:0]$6111 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0__dout - case - assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0_datasr__i - end + assign $1\ea_r$next[63:0]$6460 \alu_o case - assign $1\dmi0_datasr__i$next[63:0]$6110 \dmi0_datasr__i + assign $1\ea_r$next[63:0]$6460 \ea_r end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + sync always + update \ea_r$next $0\ea_r$next[63:0]$6459 + end + attribute \src "libresoc.v:140588.3-140597.6" + process $proc$libresoc.v:140588$6461 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:140589.5-140589.29" + switch \initial + attribute \src "libresoc.v:140589.9-140589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" + switch \cu_wr__go_i [0] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$6112 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dest1_o[63:0] \ldd_r case - assign $3\dmi0_datasr__i$next[63:0]$6112 $1\dmi0_datasr__i$next[63:0]$6110 + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6109 + update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:142806.3-142824.6" - process $proc$libresoc.v:142806$6113 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:140598.3-140607.6" + process $proc$libresoc.v:140598$6462 assign { } { } assign { } { } - assign { } { } - assign $0\wb_dcache_en$next[0:0]$6114 $2\wb_dcache_en$next[0:0]$6118 - assign $0\wb_icache_en$next[0:0]$6115 $2\wb_icache_en$next[0:0]$6119 - attribute \src "libresoc.v:142807.5-142807.29" + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:140599.5-140599.29" switch \initial - attribute \src "libresoc.v:142807.9-142807.17" + attribute \src "libresoc.v:140599.9-140599.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:102" - switch \sr5__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" + switch \$164 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { $1\wb_dcache_en$next[0:0]$6116 $1\wb_icache_en$next[0:0]$6117 } \sr5__o + assign $1\dest2_o[63:0] \addr_r + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:140608.3-140616.6" + process $proc$libresoc.v:140608$6463 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$next[0:0]$6464 $1\ldst_port0_addr_i_ok$next[0:0]$6465 + attribute \src "libresoc.v:140609.5-140609.29" + switch \initial + attribute \src "libresoc.v:140609.9-140609.17" + case 1'1 case - assign $1\wb_dcache_en$next[0:0]$6116 \wb_dcache_en - assign $1\wb_icache_en$next[0:0]$6117 \wb_icache_en end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign $2\wb_icache_en$next[0:0]$6119 1'1 - assign $2\wb_dcache_en$next[0:0]$6118 1'1 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6465 1'0 case - assign $2\wb_dcache_en$next[0:0]$6118 $1\wb_dcache_en$next[0:0]$6116 - assign $2\wb_icache_en$next[0:0]$6119 $1\wb_icache_en$next[0:0]$6117 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6465 \$177 end sync always - update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6114 - update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6115 + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6464 end - attribute \src "libresoc.v:142825.3-142834.6" - process $proc$libresoc.v:142825$6120 + attribute \src "libresoc.v:140617.3-140640.6" + process $proc$libresoc.v:140617$6466 assign { } { } assign { } { } - assign $0\sr5__i[1:0] $1\sr5__i[1:0] - attribute \src "libresoc.v:142826.5-142826.29" + assign $0\lddata_r[63:0] $1\lddata_r[63:0] + attribute \src "libresoc.v:140618.5-140618.29" switch \initial - attribute \src "libresoc.v:142826.9-142826.17" + attribute \src "libresoc.v:140618.9-140618.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:105" - switch \sr5__ie + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" + switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5__i[1:0] { \wb_dcache_en \wb_icache_en } + assign $1\lddata_r[63:0] $2\lddata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" + switch \oper_r__data_len + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\lddata_r[63:0] \$186 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\lddata_r[63:0] \$188 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\lddata_r[63:0] \$190 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\lddata_r[63:0] { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } + case + assign $2\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end case - assign $1\sr5__i[1:0] 2'00 + assign $1\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \sr5__i $0\sr5__i[1:0] + update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:142835.3-142852.6" - process $proc$libresoc.v:142835$6121 - assign { } { } + attribute \src "libresoc.v:140641.3-140652.6" + process $proc$libresoc.v:140641$6467 assign { } { } - assign { } { } - assign $0\io_sr$next[153:0]$6122 $2\io_sr$next[153:0]$6124 - attribute \src "libresoc.v:142836.5-142836.29" + assign $0\revnorev[63:0] $1\revnorev[63:0] + attribute \src "libresoc.v:140642.5-140642.29" switch \initial - attribute \src "libresoc.v:142836.9-142836.17" + attribute \src "libresoc.v:140642.9-140642.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" - switch { \io_update \io_shift \io_capture } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" + switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" - case 3'--1 + case 1'1 assign { } { } - assign $1\io_sr$next[153:0]$6123 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + assign $1\revnorev[63:0] \lddata_r attribute \src "libresoc.v:0.0-0.0" - case 3'-1- + case assign { } { } - assign $1\io_sr$next[153:0]$6123 { \io_sr [152:0] \TAP_bus__tdi } + assign $1\revnorev[63:0] \ldst_port0_ld_data_o + end + sync always + update \revnorev $0\revnorev[63:0] + end + attribute \src "libresoc.v:140653.3-140672.6" + process $proc$libresoc.v:140653$6468 + assign { } { } + assign $0\ldd_o[63:0] $1\ldd_o[63:0] + attribute \src "libresoc.v:140654.5-140654.29" + switch \initial + attribute \src "libresoc.v:140654.9-140654.17" + case 1'1 case - assign $1\io_sr$next[153:0]$6123 \io_sr end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" + switch \oper_r__sign_extend attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_sr$next[153:0]$6124 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldd_o[63:0] $2\ldd_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" + switch \$192 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldd_o[63:0] { \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ldd_o[63:0] { \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" case - assign $2\io_sr$next[153:0]$6124 $1\io_sr$next[153:0]$6123 + assign { } { } + assign $1\ldd_o[63:0] \revnorev end sync always - update \io_sr$next $0\io_sr$next[153:0]$6122 + update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:142853.3-142873.6" - process $proc$libresoc.v:142853$6125 + attribute \src "libresoc.v:140673.3-140696.6" + process $proc$libresoc.v:140673$6469 assign { } { } assign { } { } - assign { } { } - assign $0\io_bd$next[153:0]$6126 $2\io_bd$next[153:0]$6128 - attribute \src "libresoc.v:142854.5-142854.29" + assign $0\stdata_r[63:0] $1\stdata_r[63:0] + attribute \src "libresoc.v:140674.5-140674.29" switch \initial - attribute \src "libresoc.v:142854.9-142854.17" + attribute \src "libresoc.v:140674.9-140674.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" - switch { \io_update \io_shift \io_capture } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $1\io_bd$next[153:0]$6127 \io_bd - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $1\io_bd$next[153:0]$6127 \io_bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" - case 3'1-- + case 1'1 assign { } { } - assign $1\io_bd$next[153:0]$6127 \io_sr + assign $1\stdata_r[63:0] $2\stdata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" + switch \oper_r__data_len + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\stdata_r[63:0] \$194 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\stdata_r[63:0] \$196 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\stdata_r[63:0] \$198 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\stdata_r[63:0] { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } + case + assign $2\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end case - assign $1\io_bd$next[153:0]$6127 \io_bd + assign $1\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \negjtag_rst + sync always + update \stdata_r $0\stdata_r[63:0] + end + attribute \src "libresoc.v:140697.3-140708.6" + process $proc$libresoc.v:140697$6470 + assign { } { } + assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:140698.5-140698.29" + switch \initial + attribute \src "libresoc.v:140698.9-140698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + switch \oper_r__byte_reverse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_bd$next[153:0]$6128 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\io_bd$next[153:0]$6128 $1\io_bd$next[153:0]$6127 - end - sync always - update \io_bd$next $0\io_bd$next[153:0]$6126 - end - connect \$9 $eq$libresoc.v:141796$5681_Y - connect \$99 $ternary$libresoc.v:141797$5682_Y - connect \$101 $ternary$libresoc.v:141798$5683_Y - connect \$103 $ternary$libresoc.v:141799$5684_Y - connect \$105 $ternary$libresoc.v:141800$5685_Y - connect \$107 $ternary$libresoc.v:141801$5686_Y - connect \$109 $ternary$libresoc.v:141802$5687_Y - connect \$111 $ternary$libresoc.v:141803$5688_Y - connect \$113 $ternary$libresoc.v:141804$5689_Y - connect \$115 $ternary$libresoc.v:141805$5690_Y - connect \$117 $ternary$libresoc.v:141806$5691_Y - connect \$11 $eq$libresoc.v:141807$5692_Y - connect \$119 $ternary$libresoc.v:141808$5693_Y - connect \$121 $ternary$libresoc.v:141809$5694_Y - connect \$123 $ternary$libresoc.v:141810$5695_Y - connect \$125 $ternary$libresoc.v:141811$5696_Y - connect \$127 $ternary$libresoc.v:141812$5697_Y - connect \$129 $ternary$libresoc.v:141813$5698_Y - connect \$131 $ternary$libresoc.v:141814$5699_Y - connect \$133 $ternary$libresoc.v:141815$5700_Y - connect \$135 $ternary$libresoc.v:141816$5701_Y - connect \$137 $ternary$libresoc.v:141817$5702_Y - connect \$13 $eq$libresoc.v:141818$5703_Y - connect \$139 $ternary$libresoc.v:141819$5704_Y - connect \$141 $ternary$libresoc.v:141820$5705_Y - connect \$143 $ternary$libresoc.v:141821$5706_Y - connect \$145 $ternary$libresoc.v:141822$5707_Y - connect \$147 $ternary$libresoc.v:141823$5708_Y - connect \$149 $ternary$libresoc.v:141824$5709_Y - connect \$151 $ternary$libresoc.v:141825$5710_Y - connect \$153 $ternary$libresoc.v:141826$5711_Y - connect \$155 $ternary$libresoc.v:141827$5712_Y - connect \$157 $ternary$libresoc.v:141828$5713_Y - connect \$15 $or$libresoc.v:141829$5714_Y - connect \$159 $ternary$libresoc.v:141830$5715_Y - connect \$161 $ternary$libresoc.v:141831$5716_Y - connect \$163 $ternary$libresoc.v:141832$5717_Y - connect \$165 $ternary$libresoc.v:141833$5718_Y - connect \$167 $ternary$libresoc.v:141834$5719_Y - connect \$169 $ternary$libresoc.v:141835$5720_Y - connect \$171 $ternary$libresoc.v:141836$5721_Y - connect \$173 $ternary$libresoc.v:141837$5722_Y - connect \$175 $ternary$libresoc.v:141838$5723_Y - connect \$177 $ternary$libresoc.v:141839$5724_Y - connect \$17 $and$libresoc.v:141840$5725_Y - connect \$179 $ternary$libresoc.v:141841$5726_Y - connect \$181 $ternary$libresoc.v:141842$5727_Y - connect \$183 $ternary$libresoc.v:141843$5728_Y - connect \$185 $ternary$libresoc.v:141844$5729_Y - connect \$187 $ternary$libresoc.v:141845$5730_Y - connect \$189 $ternary$libresoc.v:141846$5731_Y - connect \$191 $ternary$libresoc.v:141847$5732_Y - connect \$193 $ternary$libresoc.v:141848$5733_Y - connect \$195 $ternary$libresoc.v:141849$5734_Y - connect \$197 $ternary$libresoc.v:141850$5735_Y - connect \$1 $eq$libresoc.v:141851$5736_Y - connect \$19 $eq$libresoc.v:141852$5737_Y - connect \$199 $ternary$libresoc.v:141853$5738_Y - connect \$201 $ternary$libresoc.v:141854$5739_Y - connect \$203 $ternary$libresoc.v:141855$5740_Y - connect \$205 $ternary$libresoc.v:141856$5741_Y - connect \$207 $ternary$libresoc.v:141857$5742_Y - connect \$209 $ternary$libresoc.v:141858$5743_Y - connect \$211 $ternary$libresoc.v:141859$5744_Y - connect \$213 $ternary$libresoc.v:141860$5745_Y - connect \$215 $ternary$libresoc.v:141861$5746_Y - connect \$217 $ternary$libresoc.v:141862$5747_Y - connect \$21 $eq$libresoc.v:141863$5748_Y - connect \$219 $ternary$libresoc.v:141864$5749_Y - connect \$221 $ternary$libresoc.v:141865$5750_Y - connect \$223 $ternary$libresoc.v:141866$5751_Y - connect \$225 $ternary$libresoc.v:141867$5752_Y - connect \$227 $ternary$libresoc.v:141868$5753_Y - connect \$229 $ternary$libresoc.v:141869$5754_Y - connect \$231 $ternary$libresoc.v:141870$5755_Y - connect \$233 $ternary$libresoc.v:141871$5756_Y - connect \$235 $ternary$libresoc.v:141872$5757_Y - connect \$237 $ternary$libresoc.v:141873$5758_Y - connect \$23 $or$libresoc.v:141874$5759_Y - connect \$239 $ternary$libresoc.v:141875$5760_Y - connect \$241 $ternary$libresoc.v:141876$5761_Y - connect \$243 $ternary$libresoc.v:141877$5762_Y - connect \$245 $ternary$libresoc.v:141878$5763_Y - connect \$247 $ternary$libresoc.v:141879$5764_Y - connect \$249 $ternary$libresoc.v:141880$5765_Y - connect \$251 $ternary$libresoc.v:141881$5766_Y - connect \$253 $ternary$libresoc.v:141882$5767_Y - connect \$255 $ternary$libresoc.v:141883$5768_Y - connect \$257 $ternary$libresoc.v:141884$5769_Y - connect \$25 $eq$libresoc.v:141885$5770_Y - connect \$259 $ternary$libresoc.v:141886$5771_Y - connect \$261 $ternary$libresoc.v:141887$5772_Y - connect \$263 $ternary$libresoc.v:141888$5773_Y - connect \$265 $ternary$libresoc.v:141889$5774_Y - connect \$267 $ternary$libresoc.v:141890$5775_Y - connect \$269 $ternary$libresoc.v:141891$5776_Y - connect \$271 $ternary$libresoc.v:141892$5777_Y - connect \$273 $ternary$libresoc.v:141893$5778_Y - connect \$275 $ternary$libresoc.v:141894$5779_Y - connect \$277 $ternary$libresoc.v:141895$5780_Y - connect \$27 $or$libresoc.v:141896$5781_Y - connect \$279 $ternary$libresoc.v:141897$5782_Y - connect \$281 $ternary$libresoc.v:141898$5783_Y - connect \$283 $ternary$libresoc.v:141899$5784_Y - connect \$285 $ternary$libresoc.v:141900$5785_Y - connect \$287 $ternary$libresoc.v:141901$5786_Y - connect \$289 $ternary$libresoc.v:141902$5787_Y - connect \$291 $ternary$libresoc.v:141903$5788_Y - connect \$293 $ternary$libresoc.v:141904$5789_Y - connect \$295 $ternary$libresoc.v:141905$5790_Y - connect \$297 $ternary$libresoc.v:141906$5791_Y - connect \$29 $and$libresoc.v:141907$5792_Y - connect \$299 $ternary$libresoc.v:141908$5793_Y - connect \$301 $ternary$libresoc.v:141909$5794_Y - connect \$303 $ternary$libresoc.v:141910$5795_Y - connect \$305 $ternary$libresoc.v:141911$5796_Y - connect \$307 $ternary$libresoc.v:141912$5797_Y - connect \$309 $ternary$libresoc.v:141913$5798_Y - connect \$311 $ternary$libresoc.v:141914$5799_Y - connect \$313 $ternary$libresoc.v:141915$5800_Y - connect \$315 $ternary$libresoc.v:141916$5801_Y - connect \$317 $ternary$libresoc.v:141917$5802_Y - connect \$31 $and$libresoc.v:141918$5803_Y - connect \$319 $ternary$libresoc.v:141919$5804_Y - connect \$321 $ternary$libresoc.v:141920$5805_Y - connect \$323 $ternary$libresoc.v:141921$5806_Y - connect \$325 $ternary$libresoc.v:141922$5807_Y - connect \$327 $ternary$libresoc.v:141923$5808_Y - connect \$329 $ternary$libresoc.v:141924$5809_Y - connect \$331 $ternary$libresoc.v:141925$5810_Y - connect \$333 $ternary$libresoc.v:141926$5811_Y - connect \$335 $ternary$libresoc.v:141927$5812_Y - connect \$337 $ternary$libresoc.v:141928$5813_Y - connect \$33 $eq$libresoc.v:141929$5814_Y - connect \$339 $ternary$libresoc.v:141930$5815_Y - connect \$341 $ternary$libresoc.v:141931$5816_Y - connect \$343 $ternary$libresoc.v:141932$5817_Y - connect \$345 $ternary$libresoc.v:141933$5818_Y - connect \$347 $ternary$libresoc.v:141934$5819_Y - connect \$349 $ternary$libresoc.v:141935$5820_Y - connect \$351 $ternary$libresoc.v:141936$5821_Y - connect \$353 $ternary$libresoc.v:141937$5822_Y - connect \$355 $ternary$libresoc.v:141938$5823_Y - connect \$357 $ternary$libresoc.v:141939$5824_Y - connect \$35 $eq$libresoc.v:141940$5825_Y - connect \$359 $eq$libresoc.v:141941$5826_Y - connect \$361 $eq$libresoc.v:141942$5827_Y - connect \$363 $or$libresoc.v:141943$5828_Y - connect \$365 $eq$libresoc.v:141944$5829_Y - connect \$367 $or$libresoc.v:141945$5830_Y - connect \$369 $and$libresoc.v:141946$5831_Y - connect \$371 $eq$libresoc.v:141947$5832_Y - connect \$373 $ne$libresoc.v:141948$5833_Y - connect \$375 $and$libresoc.v:141949$5834_Y - connect \$377 $ne$libresoc.v:141950$5835_Y - connect \$37 $or$libresoc.v:141951$5836_Y - connect \$379 $and$libresoc.v:141952$5837_Y - connect \$381 $ne$libresoc.v:141953$5838_Y - connect \$383 $and$libresoc.v:141954$5839_Y - connect \$385 $not$libresoc.v:141955$5840_Y - connect \$387 $and$libresoc.v:141956$5841_Y - connect \$389 $eq$libresoc.v:141957$5842_Y - connect \$391 $ne$libresoc.v:141958$5843_Y - connect \$393 $and$libresoc.v:141959$5844_Y - connect \$395 $ne$libresoc.v:141960$5845_Y - connect \$397 $and$libresoc.v:141961$5846_Y - connect \$3 $eq$libresoc.v:141962$5847_Y - connect \$39 $eq$libresoc.v:141963$5848_Y - connect \$399 $ne$libresoc.v:141964$5849_Y - connect \$401 $and$libresoc.v:141965$5850_Y - connect \$403 $not$libresoc.v:141966$5851_Y - connect \$405 $and$libresoc.v:141967$5852_Y - connect \$407 $eq$libresoc.v:141968$5853_Y - connect \$409 $eq$libresoc.v:141969$5854_Y - connect \$411 $ne$libresoc.v:141970$5855_Y - connect \$413 $and$libresoc.v:141971$5856_Y - connect \$415 $ne$libresoc.v:141972$5857_Y - connect \$417 $and$libresoc.v:141973$5858_Y - connect \$41 $or$libresoc.v:141974$5859_Y - connect \$419 $ne$libresoc.v:141975$5860_Y - connect \$421 $and$libresoc.v:141976$5861_Y - connect \$423 $not$libresoc.v:141977$5862_Y - connect \$425 $and$libresoc.v:141978$5863_Y - connect \$427 $eq$libresoc.v:141979$5864_Y - connect \$429 $ne$libresoc.v:141980$5865_Y - connect \$431 $and$libresoc.v:141981$5866_Y - connect \$433 $ne$libresoc.v:141982$5867_Y - connect \$435 $and$libresoc.v:141983$5868_Y - connect \$437 $ne$libresoc.v:141984$5869_Y - connect \$43 $and$libresoc.v:141985$5870_Y - connect \$439 $and$libresoc.v:141986$5871_Y - connect \$441 $not$libresoc.v:141987$5872_Y - connect \$443 $and$libresoc.v:141988$5873_Y - connect \$445 $eq$libresoc.v:141989$5874_Y - connect \$447 $eq$libresoc.v:141990$5875_Y - connect \$449 $ne$libresoc.v:141991$5876_Y - connect \$451 $and$libresoc.v:141992$5877_Y - connect \$453 $ne$libresoc.v:141993$5878_Y - connect \$455 $and$libresoc.v:141994$5879_Y - connect \$457 $ne$libresoc.v:141995$5880_Y - connect \$45 $and$libresoc.v:141996$5881_Y - connect \$459 $and$libresoc.v:141997$5882_Y - connect \$461 $not$libresoc.v:141998$5883_Y - connect \$463 $and$libresoc.v:141999$5884_Y - connect \$465 $eq$libresoc.v:142000$5885_Y - connect \$467 $ne$libresoc.v:142001$5886_Y - connect \$469 $and$libresoc.v:142002$5887_Y - connect \$471 $ne$libresoc.v:142003$5888_Y - connect \$473 $and$libresoc.v:142004$5889_Y - connect \$475 $ne$libresoc.v:142005$5890_Y - connect \$477 $and$libresoc.v:142006$5891_Y - connect \$47 $eq$libresoc.v:142007$5892_Y - connect \$479 $not$libresoc.v:142008$5893_Y - connect \$481 $and$libresoc.v:142009$5894_Y - connect \$484 $eq$libresoc.v:142010$5895_Y - connect \$483 $not$libresoc.v:142011$5896_Y - connect \$487 $eq$libresoc.v:142012$5897_Y - connect \$489 $eq$libresoc.v:142013$5898_Y - connect \$491 $or$libresoc.v:142014$5899_Y - connect \$493 $eq$libresoc.v:142015$5900_Y - connect \$496 $add$libresoc.v:142016$5901_Y - connect \$49 $eq$libresoc.v:142017$5902_Y - connect \$499 $add$libresoc.v:142018$5903_Y - connect \$501 $pos$libresoc.v:142019$5905_Y - connect \$504 $eq$libresoc.v:142020$5906_Y - connect \$506 $eq$libresoc.v:142021$5907_Y - connect \$508 $or$libresoc.v:142022$5908_Y - connect \$510 $eq$libresoc.v:142023$5909_Y - connect \$513 $add$libresoc.v:142024$5910_Y - connect \$516 $add$libresoc.v:142025$5911_Y - connect \$51 $ternary$libresoc.v:142026$5912_Y - connect \$53 $ternary$libresoc.v:142027$5913_Y - connect \$55 $ternary$libresoc.v:142028$5914_Y - connect \$57 $ternary$libresoc.v:142029$5915_Y - connect \$5 $or$libresoc.v:142030$5916_Y - connect \$59 $ternary$libresoc.v:142031$5917_Y - connect \$61 $ternary$libresoc.v:142032$5918_Y - connect \$63 $ternary$libresoc.v:142033$5919_Y - connect \$65 $ternary$libresoc.v:142034$5920_Y - connect \$67 $ternary$libresoc.v:142035$5921_Y - connect \$69 $ternary$libresoc.v:142036$5922_Y - connect \$71 $ternary$libresoc.v:142037$5923_Y - connect \$73 $ternary$libresoc.v:142038$5924_Y - connect \$75 $ternary$libresoc.v:142039$5925_Y - connect \$77 $ternary$libresoc.v:142040$5926_Y - connect \$7 $and$libresoc.v:142041$5927_Y - connect \$79 $ternary$libresoc.v:142042$5928_Y - connect \$81 $ternary$libresoc.v:142043$5929_Y - connect \$83 $ternary$libresoc.v:142044$5930_Y - connect \$85 $ternary$libresoc.v:142045$5931_Y - connect \$87 $ternary$libresoc.v:142046$5932_Y - connect \$89 $ternary$libresoc.v:142047$5933_Y - connect \$91 $ternary$libresoc.v:142048$5934_Y - connect \$93 $ternary$libresoc.v:142049$5935_Y - connect \$95 $ternary$libresoc.v:142050$5936_Y - connect \$97 $ternary$libresoc.v:142051$5937_Y - connect \$495 \$496 - connect \$498 \$499 - connect \$512 \$513 - connect \$515 \$516 - connect \sr5__ie 1'0 - connect \sr0__i \sr0__o - connect \dmi0__we_i \$510 - connect \dmi0__req_i \$508 - connect \dmi0_addrsr__i \$501 - connect \jtag_wb__we \$493 - connect \jtag_wb__stb \$491 - connect \jtag_wb__cyc \$483 - connect \jtag_wb__sel 1'1 - connect \jtag_wb_addrsr__i \jtag_wb__adr - connect \sr5_update \$477 - connect \sr5_shift \$473 - connect \sr5_capture \$469 - connect \sr5_isir \$465 - connect \sr5__o \sr5_reg - connect \dmi0_datasr_update \$459 - connect \dmi0_datasr_shift \$455 - connect \dmi0_datasr_capture \$451 - connect \dmi0_datasr_isir { \$447 \$445 } - connect \dmi0_datasr__o \dmi0_datasr_reg - connect \dmi0_addrsr_update \$439 - connect \dmi0_addrsr_shift \$435 - connect \dmi0_addrsr_capture \$431 - connect \dmi0_addrsr_isir \$427 - connect \dmi0_addrsr__o \dmi0_addrsr_reg - connect \jtag_wb_datasr_update \$421 - connect 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\$273 - connect \sdr_a_4__pad__o \$271 - connect \sdr_a_3__pad__o \$269 - connect \sdr_a_2__pad__o \$267 - connect \sdr_a_1__pad__o \$265 - connect \sdr_a_0__pad__o \$263 - connect \sdr_dq_7__pad__oe \$261 - connect \sdr_dq_7__pad__o \$259 - connect \sdr_dq_7__core__i \$257 - connect \sdr_dq_6__pad__oe \$255 - connect \sdr_dq_6__pad__o \$253 - connect \sdr_dq_6__core__i \$251 - connect \sdr_dq_5__pad__oe \$249 - connect \sdr_dq_5__pad__o \$247 - connect \sdr_dq_5__core__i \$245 - connect \sdr_dq_4__pad__oe \$243 - connect \sdr_dq_4__pad__o \$241 - connect \sdr_dq_4__core__i \$239 - connect \sdr_dq_3__pad__oe \$237 - connect \sdr_dq_3__pad__o \$235 - connect \sdr_dq_3__core__i \$233 - connect \sdr_dq_2__pad__oe \$231 - connect \sdr_dq_2__pad__o \$229 - connect \sdr_dq_2__core__i \$227 - connect \sdr_dq_1__pad__oe \$225 - connect \sdr_dq_1__pad__o \$223 - connect \sdr_dq_1__core__i \$221 - connect \sdr_dq_0__pad__oe \$219 - connect \sdr_dq_0__pad__o \$217 - connect \sdr_dq_0__core__i \$215 - connect \sdr_dm_0__pad__o \$213 - connect \sd0_data3__pad__oe \$211 - connect \sd0_data3__pad__o \$209 - connect \sd0_data3__core__i \$207 - connect \sd0_data2__pad__oe \$205 - connect \sd0_data2__pad__o \$203 - connect \sd0_data2__core__i \$201 - connect \sd0_data1__pad__oe \$199 - connect \sd0_data1__pad__o \$197 - connect \sd0_data1__core__i \$195 - connect \sd0_data0__pad__oe \$193 - connect \sd0_data0__pad__o \$191 - connect \sd0_data0__core__i \$189 - connect \sd0_clk__pad__o \$187 - connect \sd0_cmd__pad__oe \$185 - connect \sd0_cmd__pad__o \$183 - connect \sd0_cmd__core__i \$181 - connect \pwm_1__pad__o \$179 - connect \pwm_0__pad__o \$177 - connect \mtwi_scl__pad__o \$175 - connect \mtwi_sda__pad__oe \$173 - connect \mtwi_sda__pad__o \$171 - connect \mtwi_sda__core__i \$169 - connect \mspi1_miso__core__i \$167 - connect \mspi1_mosi__pad__o \$165 - connect \mspi1_cs_n__pad__o \$163 - connect \mspi1_clk__pad__o \$161 - connect \mspi0_miso__core__i \$159 - connect \mspi0_mosi__pad__o \$157 - connect \mspi0_cs_n__pad__o \$155 - connect \mspi0_clk__pad__o \$153 - connect \gpio_s7__pad__oe \$151 - connect \gpio_s7__pad__o \$149 - connect \gpio_s7__core__i \$147 - connect \gpio_s6__pad__oe \$145 - connect \gpio_s6__pad__o \$143 - connect \gpio_s6__core__i \$141 - connect \gpio_s5__pad__oe \$139 - connect \gpio_s5__pad__o \$137 - connect \gpio_s5__core__i \$135 - connect \gpio_s4__pad__oe \$133 - connect \gpio_s4__pad__o \$131 - connect \gpio_s4__core__i \$129 - connect \gpio_s3__pad__oe \$127 - connect \gpio_s3__pad__o \$125 - connect \gpio_s3__core__i \$123 - connect \gpio_s2__pad__oe \$121 - connect \gpio_s2__pad__o \$119 - connect \gpio_s2__core__i \$117 - connect \gpio_s1__pad__oe \$115 - connect \gpio_s1__pad__o \$113 - connect \gpio_s1__core__i \$111 - connect \gpio_s0__pad__oe \$109 - connect \gpio_s0__pad__o \$107 - connect \gpio_s0__core__i \$105 - connect \gpio_e15__pad__oe \$103 - connect \gpio_e15__pad__o \$101 - connect \gpio_e15__core__i \$99 - connect \gpio_e14__pad__oe \$97 - connect \gpio_e14__pad__o \$95 - connect \gpio_e14__core__i \$93 - connect \gpio_e13__pad__oe \$91 - connect \gpio_e13__pad__o \$89 - connect \gpio_e13__core__i \$87 - connect \gpio_e12__pad__oe \$85 - connect \gpio_e12__pad__o \$83 - connect \gpio_e12__core__i \$81 - connect \gpio_e11__pad__oe \$79 - connect \gpio_e11__pad__o \$77 - connect \gpio_e11__core__i \$75 - connect \gpio_e10__pad__oe \$73 - connect \gpio_e10__pad__o \$71 - connect \gpio_e10__core__i \$69 - connect \gpio_e9__pad__oe \$67 - connect \gpio_e9__pad__o \$65 - connect \gpio_e9__core__i \$63 - connect \gpio_e8__pad__oe \$61 - connect \gpio_e8__pad__o \$59 - connect \gpio_e8__core__i \$57 - connect \eint_2__core__i \$55 - connect \eint_1__core__i \$53 - connect \eint_0__core__i \$51 - connect \io_bd2core \$49 - connect \io_bd2io \$47 - connect \io_update \$45 - connect \io_shift \$31 - connect \io_capture \$17 - connect \_idblock_id_bypass \$9 - connect \_idblock_select_id \$7 -end -attribute \src "libresoc.v:143083.1-143272.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0" -attribute \generator "nMigen" -module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 23 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 28 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 22 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 27 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 30 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 24 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 26 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 25 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 29 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 16 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire output 2 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 8 \ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 9 \ldst_port0_exc_$signal$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 10 \ldst_port0_exc_$signal$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 11 \ldst_port0_exc_$signal$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 12 \ldst_port0_exc_$signal$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 13 \ldst_port0_exc_$signal$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 14 \ldst_port0_exc_$signal$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 15 \ldst_port0_exc_$signal$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire input 3 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire input 4 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 17 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 18 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 19 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 20 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 48 \pimem_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pimem_ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire \pimem_ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire \pimem_ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 \pimem_ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \pimem_ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire \pimem_ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire \pimem_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pimem_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pimem_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pimem_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pimem_ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" - wire width 64 \pimem_m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" - wire \pimem_m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 48 \pimem_x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" - wire \pimem_x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" - wire \pimem_x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" - wire width 8 \pimem_x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" - wire width 64 \pimem_x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" - wire \pimem_x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" - wire \pimem_x_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire input 21 \wb_dcache_en - attribute \module_not_derived 1 - attribute \src "libresoc.v:143188.12-143222.4" - cell \l0$130 \l0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i$12 \pimem_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_i_ok$13 \pimem_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_addr_ok_o$14 \pimem_ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_busy_o$10 \pimem_ldst_port0_busy_o - connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_data_len$11 \pimem_ldst_port0_data_len - connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal - connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$1 - connect \ldst_port0_exc_$signal$19 \pimem_ldst_port0_exc_$signal - connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$2 - connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$3 - connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$4 - connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$5 - connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$6 - connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$7 - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_ld_i$8 \pimem_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_is_st_i$9 \pimem_ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o$15 \pimem_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_ld_data_o_ok$16 \pimem_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i$18 \pimem_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:143223.9-143245.4" - cell \lsmem \lsmem - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dbus__ack \dbus__ack - connect \dbus__adr \dbus__adr - connect \dbus__cyc \dbus__cyc - connect \dbus__dat_r \dbus__dat_r - connect \dbus__dat_w \dbus__dat_w - connect \dbus__err \dbus__err - connect \dbus__sel \dbus__sel - connect \dbus__stb \dbus__stb - connect \dbus__we \dbus__we - connect \m_ld_data_o \pimem_m_ld_data_o - connect \m_valid_i \pimem_m_valid_i - connect \wb_dcache_en \wb_dcache_en - connect \x_addr_i \pimem_x_addr_i - connect \x_busy_o \pimem_x_busy_o - connect \x_ld_i \pimem_x_ld_i - connect \x_mask_i \pimem_x_mask_i - connect \x_st_data_i \pimem_x_st_data_i - connect \x_st_i \pimem_x_st_i - connect \x_valid_i \pimem_x_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:143246.9-143270.4" - cell \pimem \pimem - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o - connect \ldst_port0_data_len \pimem_ldst_port0_data_len - connect \ldst_port0_exc_$signal \pimem_ldst_port0_exc_$signal - connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok - connect \m_ld_data_o \pimem_m_ld_data_o - connect \m_valid_i \pimem_m_valid_i - connect \x_addr_i \pimem_x_addr_i - connect \x_busy_o \pimem_x_busy_o - connect \x_ld_i \pimem_x_ld_i - connect \x_mask_i \pimem_x_mask_i - connect \x_st_data_i \pimem_x_st_data_i - connect \x_st_i \pimem_x_st_i - connect \x_valid_i \pimem_x_valid_i + assign $1\ldst_port0_st_data_i[63:0] \stdata_r + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \src_r2 + end + sync always + update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end - connect \pimem_ldst_port0_exc_$signal 1'0 + connect \$100 $and$libresoc.v:140156$6229_Y + connect \$102 $and$libresoc.v:140157$6230_Y + connect \$104 $and$libresoc.v:140158$6231_Y + connect \$106 $and$libresoc.v:140159$6232_Y + connect \$108 $and$libresoc.v:140160$6233_Y + connect \$10 $or$libresoc.v:140161$6234_Y + connect \$110 $and$libresoc.v:140162$6235_Y + connect \$112 $and$libresoc.v:140163$6236_Y + connect \$114 $and$libresoc.v:140164$6237_Y + connect \$116 $and$libresoc.v:140165$6238_Y + connect \$118 $and$libresoc.v:140166$6239_Y + connect \$120 $and$libresoc.v:140167$6240_Y + connect \$122 $and$libresoc.v:140168$6241_Y + connect \$124 $and$libresoc.v:140169$6242_Y + connect \$126 $eq$libresoc.v:140170$6243_Y + connect \$128 $and$libresoc.v:140171$6244_Y + connect \$12 $or$libresoc.v:140172$6245_Y + connect \$130 $and$libresoc.v:140173$6246_Y + connect \$132 $and$libresoc.v:140174$6247_Y + connect \$134 $or$libresoc.v:140175$6248_Y + connect \$136 $or$libresoc.v:140176$6249_Y + connect \$138 $or$libresoc.v:140177$6250_Y + connect \$140 $and$libresoc.v:140178$6251_Y + connect \$142 $and$libresoc.v:140179$6252_Y + connect \$145 $or$libresoc.v:140180$6253_Y + connect \$147 $or$libresoc.v:140181$6254_Y + connect \$144 $not$libresoc.v:140182$6255_Y + connect \$14 $or$libresoc.v:140183$6256_Y + connect \$150 $and$libresoc.v:140184$6257_Y + connect \$152 $or$libresoc.v:140185$6258_Y + connect \$154 $and$libresoc.v:140186$6259_Y + connect \$156 $not$libresoc.v:140187$6260_Y + connect \$158 $or$libresoc.v:140188$6261_Y + connect \$160 $and$libresoc.v:140189$6262_Y + connect \$162 $eq$libresoc.v:140190$6263_Y + connect \$164 $and$libresoc.v:140191$6264_Y + connect \$167 $eq$libresoc.v:140192$6265_Y + connect \$16 $or$libresoc.v:140193$6266_Y + connect \$169 $and$libresoc.v:140194$6267_Y + connect \$171 $and$libresoc.v:140195$6268_Y + connect \$173 $and$libresoc.v:140196$6269_Y + connect \$175 $pos$libresoc.v:140197$6271_Y + connect \$177 $and$libresoc.v:140198$6272_Y + connect \$186 $pos$libresoc.v:140199$6274_Y + connect \$188 $pos$libresoc.v:140200$6275_Y + connect \$18 $or$libresoc.v:140201$6276_Y + connect \$190 $pos$libresoc.v:140202$6277_Y + connect \$192 $eq$libresoc.v:140203$6278_Y + connect \$194 $pos$libresoc.v:140204$6280_Y + connect \$196 $pos$libresoc.v:140205$6281_Y + connect \$198 $pos$libresoc.v:140206$6282_Y + connect \$20 $or$libresoc.v:140207$6283_Y + connect \$22 $eq$libresoc.v:140208$6284_Y + connect \$24 $eq$libresoc.v:140209$6285_Y + connect \$26 $and$libresoc.v:140210$6286_Y + connect \$28 $and$libresoc.v:140211$6287_Y + connect \$30 $not$libresoc.v:140212$6288_Y + connect \$32 $and$libresoc.v:140213$6289_Y + connect \$34 $not$libresoc.v:140214$6290_Y + connect \$36 $and$libresoc.v:140215$6291_Y + connect \$39 $not$libresoc.v:140216$6292_Y + connect \$41 $eq$libresoc.v:140217$6293_Y + connect \$43 $and$libresoc.v:140218$6294_Y + connect \$45 $or$libresoc.v:140219$6295_Y + connect \$47 $not$libresoc.v:140220$6296_Y + connect \$49 $eq$libresoc.v:140221$6297_Y + connect \$51 $and$libresoc.v:140222$6298_Y + connect \$53 $or$libresoc.v:140223$6299_Y + connect \$55 $or$libresoc.v:140224$6300_Y + connect \$57 $and$libresoc.v:140225$6301_Y + connect \$59 $or$libresoc.v:140226$6302_Y + connect \$61 $or$libresoc.v:140227$6303_Y + connect \$63 $or$libresoc.v:140228$6304_Y + connect \$65 $ternary$libresoc.v:140229$6305_Y + connect \$67 $ternary$libresoc.v:140230$6306_Y + connect \$69 $ternary$libresoc.v:140231$6307_Y + connect \$71 $ternary$libresoc.v:140232$6308_Y + connect \$74 $add$libresoc.v:140233$6309_Y + connect \$76 $and$libresoc.v:140234$6310_Y + connect \$78 $not$libresoc.v:140235$6311_Y + connect \$80 $and$libresoc.v:140236$6312_Y + connect \$82 $not$libresoc.v:140237$6313_Y + connect \$84 $and$libresoc.v:140238$6314_Y + connect \$86 $and$libresoc.v:140239$6315_Y + connect \$88 $and$libresoc.v:140240$6316_Y + connect \$8 $or$libresoc.v:140241$6317_Y + connect \$90 $or$libresoc.v:140242$6318_Y + connect \$93 $or$libresoc.v:140243$6319_Y + connect \$92 $not$libresoc.v:140244$6320_Y + connect \$96 $and$libresoc.v:140245$6321_Y + connect \$98 $not$libresoc.v:140246$6322_Y + connect \$38 \$55 + connect \$73 \$74 + connect \$166 \$169 + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \ldst_port0_st_data_i_ok \cu_st__go_i + connect \ld_ok \ldst_port0_ld_data_o_ok + connect \addr_ok \ldst_port0_addr_ok_o + connect { \exc_$signal$185 \exc_$signal$184 \exc_$signal$183 \exc_$signal$182 \exc_$signal$181 \exc_$signal$180 \exc_$signal$179 \exc_$signal } { \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal } + connect \ldst_port0_addr_i$next \$175 + connect \ldst_port0_data_len \oper_r__data_len + connect \ldst_port0_is_st_i \$173 + connect \ldst_port0_is_ld_i \$171 + connect \cu_wrmask_o \$169 [1:0] + connect \ea \dest2_o + connect \o \dest1_o + connect \cu_done_o \$160 + connect \wr_reset \$154 + connect \wr_any \$138 + connect \cu_wr__rel_o [1] \$132 + connect \cu_wr__rel_o [0] \$122 + connect \cu_st__rel_o \$112 + connect \cu_ad__rel_o \$104 + connect \rd_done \$100 + connect \alu_valid \$96 + connect \rda_any \$90 + connect \cu_rd__rel_o [2] \$88 + connect \cu_rd__rel_o [1:0] \$84 [1:0] + connect \cu_busy_o \opc_l_q_opc + connect \alu_ok$next \alu_valid + connect \alu_o \$74 [63:0] + connect \src2_or_imm \$71 + connect \src1_or_z \$69 + connect \addr_r \$67 + connect \ldd_r \$65 + connect \rst_l_r_rst \cu_issue_i + connect \rst_l_s_rst \addr_ok + connect \lsd_l_s_lsd \cu_issue_i + connect \sto_l_s_sto \$57 + connect \wri_l_s_wri \cu_issue_i + connect \lod_l_r_lod \ld_ok + connect \lod_l_s_lod \reset_i + connect \adr_l_s_adr \reset_i + connect \alu_l_r_alu \$36 + connect \alu_l_s_alu \reset_i + connect \st_o \op_is_st + connect \ld_o \op_is_ld + connect \stwd_mem_o \$28 + connect \load_mem_o \$26 + connect \op_is_ld \$24 + connect \op_is_st \$22 + connect \p_st_go$next \cu_st__go_i + connect \reset_a \$20 + connect \reset_r \$18 + connect \reset_s \$16 + connect \reset_u \$14 + connect \reset_w \$12 + connect \reset_o \$10 + connect \reset_i \$8 end -attribute \src "libresoc.v:143276.1-143684.10" +attribute \src "libresoc.v:140772.1-141359.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" -module \l0$130 - attribute \src "libresoc.v:143539.3-143553.6" - wire $0\idx_l$23$next[0:0]$6206 - attribute \src "libresoc.v:143439.3-143440.35" - wire $0\idx_l$23[0:0]$6173 - attribute \src "libresoc.v:143297.7-143297.24" - wire $0\idx_l$23[0:0]$6228 - attribute \src "libresoc.v:143594.3-143603.6" - wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:143584.3-143593.6" - wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:143277.7-143277.20" +module \left_mask + attribute \src "libresoc.v:140773.7-140773.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143460.3-143469.6" - wire width 48 $0\ldst_port0_addr_i$12[47:0]$6175 - attribute \src "libresoc.v:143470.3-143479.6" - wire $0\ldst_port0_addr_i_ok$13[0:0]$6178 - attribute \src "libresoc.v:143512.3-143521.6" - wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:143502.3-143511.6" - wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:143574.3-143583.6" - wire $0\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:143649.3-143658.6" - wire width 4 $0\ldst_port0_data_len$11[3:0]$6223 - attribute \src "libresoc.v:143522.3-143538.6" - wire $0\ldst_port0_exc_$signal$1[0:0]$6190 - attribute \src "libresoc.v:143522.3-143538.6" - wire $0\ldst_port0_exc_$signal$2[0:0]$6191 - attribute \src "libresoc.v:143522.3-143538.6" - wire $0\ldst_port0_exc_$signal$3[0:0]$6192 - attribute \src "libresoc.v:143522.3-143538.6" - wire $0\ldst_port0_exc_$signal$4[0:0]$6193 - attribute \src "libresoc.v:143522.3-143538.6" - wire $0\ldst_port0_exc_$signal$5[0:0]$6194 - attribute \src "libresoc.v:143522.3-143538.6" - wire $0\ldst_port0_exc_$signal$6[0:0]$6195 - attribute \src "libresoc.v:143522.3-143538.6" - wire $0\ldst_port0_exc_$signal$7[0:0]$6196 - attribute \src "libresoc.v:143522.3-143538.6" - wire $0\ldst_port0_exc_$signal[0:0]$6189 - attribute \src "libresoc.v:143659.3-143668.6" - wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:143629.3-143638.6" - wire $0\ldst_port0_is_ld_i$8[0:0]$6217 - attribute \src "libresoc.v:143639.3-143648.6" - wire $0\ldst_port0_is_st_i$9[0:0]$6220 - attribute \src "libresoc.v:143491.3-143501.6" - wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:143491.3-143501.6" - wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:143564.3-143573.6" - wire $0\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:143554.3-143563.6" - wire $0\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:143480.3-143490.6" - wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6181 - attribute \src "libresoc.v:143480.3-143490.6" - wire $0\ldst_port0_st_data_i_ok$17[0:0]$6182 - attribute \src "libresoc.v:143437.3-143438.36" - wire $0\reset_delay[0:0] - attribute \src "libresoc.v:143619.3-143628.6" - wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:143604.3-143618.6" - wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:143539.3-143553.6" - wire $1\idx_l$23$next[0:0]$6207 - attribute \src "libresoc.v:143594.3-143603.6" - wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:143584.3-143593.6" - wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:143460.3-143469.6" - wire width 48 $1\ldst_port0_addr_i$12[47:0]$6176 - attribute \src "libresoc.v:143470.3-143479.6" - wire $1\ldst_port0_addr_i_ok$13[0:0]$6179 - attribute \src "libresoc.v:143512.3-143521.6" - wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:143502.3-143511.6" - wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:143574.3-143583.6" - wire $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:143649.3-143658.6" - wire width 4 $1\ldst_port0_data_len$11[3:0]$6224 - attribute \src "libresoc.v:143522.3-143538.6" - wire $1\ldst_port0_exc_$signal$1[0:0]$6198 - attribute \src "libresoc.v:143522.3-143538.6" - wire $1\ldst_port0_exc_$signal$2[0:0]$6199 - attribute \src "libresoc.v:143522.3-143538.6" - wire $1\ldst_port0_exc_$signal$3[0:0]$6200 - attribute \src "libresoc.v:143522.3-143538.6" - wire $1\ldst_port0_exc_$signal$4[0:0]$6201 - attribute \src "libresoc.v:143522.3-143538.6" - wire $1\ldst_port0_exc_$signal$5[0:0]$6202 - attribute \src "libresoc.v:143522.3-143538.6" - wire $1\ldst_port0_exc_$signal$6[0:0]$6203 - attribute \src "libresoc.v:143522.3-143538.6" - wire $1\ldst_port0_exc_$signal$7[0:0]$6204 - attribute \src "libresoc.v:143522.3-143538.6" - wire $1\ldst_port0_exc_$signal[0:0]$6197 - attribute \src "libresoc.v:143659.3-143668.6" - wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:143629.3-143638.6" - wire $1\ldst_port0_is_ld_i$8[0:0]$6218 - attribute \src "libresoc.v:143639.3-143648.6" - wire $1\ldst_port0_is_st_i$9[0:0]$6221 - attribute \src "libresoc.v:143491.3-143501.6" - wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:143491.3-143501.6" - wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:143564.3-143573.6" - wire $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:143554.3-143563.6" - wire $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:143480.3-143490.6" - wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6183 - attribute \src "libresoc.v:143480.3-143490.6" - wire $1\ldst_port0_st_data_i_ok$17[0:0]$6184 - attribute \src "libresoc.v:143424.7-143424.25" - wire $1\reset_delay[0:0] - attribute \src "libresoc.v:143619.3-143628.6" - wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:143604.3-143618.6" - wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:143539.3-143553.6" - wire $2\idx_l$23$next[0:0]$6208 - attribute \src "libresoc.v:143604.3-143618.6" - wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:143435.18-143435.103" - wire $not$libresoc.v:143435$6169_Y - attribute \src "libresoc.v:143436.18-143436.118" - wire $not$libresoc.v:143436$6170_Y - attribute \src "libresoc.v:143433.18-143433.134" - wire $or$libresoc.v:143433$6167_Y - attribute \src "libresoc.v:143434.18-143434.120" - wire $ternary$libresoc.v:143434$6168_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - wire \$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" - wire width 96 \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" - wire width 96 \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire \idx_l$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire \idx_l$23$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \idx_l_q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \idx_l_r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \idx_l_s_idx_l - attribute \src "libresoc.v:143277.7-143277.15" + attribute \src "libresoc.v:140971.3-141358.6" + wire width 64 $0\mask[63:0] + attribute \src "libresoc.v:140971.3-141358.6" + wire $10\mask[9:9] + attribute \src "libresoc.v:140971.3-141358.6" + wire $11\mask[10:10] + attribute \src "libresoc.v:140971.3-141358.6" + wire $12\mask[11:11] + attribute \src "libresoc.v:140971.3-141358.6" + wire $13\mask[12:12] + attribute \src "libresoc.v:140971.3-141358.6" + wire $14\mask[13:13] + attribute \src "libresoc.v:140971.3-141358.6" + wire $15\mask[14:14] + attribute \src "libresoc.v:140971.3-141358.6" + wire $16\mask[15:15] + attribute \src "libresoc.v:140971.3-141358.6" + wire $17\mask[16:16] + attribute \src "libresoc.v:140971.3-141358.6" + wire $18\mask[17:17] + attribute \src "libresoc.v:140971.3-141358.6" + wire $19\mask[18:18] + attribute \src "libresoc.v:140971.3-141358.6" + wire $1\mask[0:0] + attribute \src "libresoc.v:140971.3-141358.6" + wire $20\mask[19:19] + attribute \src "libresoc.v:140971.3-141358.6" + wire $21\mask[20:20] + attribute \src "libresoc.v:140971.3-141358.6" + wire $22\mask[21:21] + attribute \src "libresoc.v:140971.3-141358.6" + wire $23\mask[22:22] + attribute \src "libresoc.v:140971.3-141358.6" + wire $24\mask[23:23] + attribute \src "libresoc.v:140971.3-141358.6" + wire $25\mask[24:24] + attribute \src "libresoc.v:140971.3-141358.6" + wire $26\mask[25:25] + attribute \src "libresoc.v:140971.3-141358.6" + wire $27\mask[26:26] + attribute \src "libresoc.v:140971.3-141358.6" + wire $28\mask[27:27] + attribute \src "libresoc.v:140971.3-141358.6" + wire $29\mask[28:28] + attribute \src "libresoc.v:140971.3-141358.6" + wire $2\mask[1:1] + attribute \src "libresoc.v:140971.3-141358.6" + wire $30\mask[29:29] + attribute \src "libresoc.v:140971.3-141358.6" + wire $31\mask[30:30] + attribute \src "libresoc.v:140971.3-141358.6" + wire $32\mask[31:31] + attribute \src "libresoc.v:140971.3-141358.6" + wire $33\mask[32:32] + attribute \src "libresoc.v:140971.3-141358.6" + wire $34\mask[33:33] + attribute \src "libresoc.v:140971.3-141358.6" + wire $35\mask[34:34] + attribute \src "libresoc.v:140971.3-141358.6" + wire $36\mask[35:35] + attribute \src "libresoc.v:140971.3-141358.6" + wire $37\mask[36:36] + attribute \src "libresoc.v:140971.3-141358.6" + wire $38\mask[37:37] + attribute \src "libresoc.v:140971.3-141358.6" + wire $39\mask[38:38] + attribute \src "libresoc.v:140971.3-141358.6" + wire $3\mask[2:2] + attribute \src "libresoc.v:140971.3-141358.6" + wire $40\mask[39:39] + attribute \src "libresoc.v:140971.3-141358.6" + wire $41\mask[40:40] + attribute \src "libresoc.v:140971.3-141358.6" + wire $42\mask[41:41] + attribute \src "libresoc.v:140971.3-141358.6" + wire $43\mask[42:42] + attribute \src "libresoc.v:140971.3-141358.6" + wire $44\mask[43:43] + attribute \src "libresoc.v:140971.3-141358.6" + wire $45\mask[44:44] + attribute \src "libresoc.v:140971.3-141358.6" + wire $46\mask[45:45] + attribute \src "libresoc.v:140971.3-141358.6" + wire $47\mask[46:46] + attribute \src "libresoc.v:140971.3-141358.6" + wire $48\mask[47:47] + attribute \src "libresoc.v:140971.3-141358.6" + wire $49\mask[48:48] + attribute \src "libresoc.v:140971.3-141358.6" + wire $4\mask[3:3] + attribute \src "libresoc.v:140971.3-141358.6" + wire $50\mask[49:49] + attribute \src "libresoc.v:140971.3-141358.6" + wire $51\mask[50:50] + attribute \src "libresoc.v:140971.3-141358.6" + wire $52\mask[51:51] + attribute \src "libresoc.v:140971.3-141358.6" + wire $53\mask[52:52] + attribute \src "libresoc.v:140971.3-141358.6" + wire $54\mask[53:53] + attribute \src "libresoc.v:140971.3-141358.6" + wire $55\mask[54:54] + attribute \src "libresoc.v:140971.3-141358.6" + wire $56\mask[55:55] + attribute \src "libresoc.v:140971.3-141358.6" + wire $57\mask[56:56] + attribute \src "libresoc.v:140971.3-141358.6" + wire $58\mask[57:57] + attribute \src "libresoc.v:140971.3-141358.6" + wire $59\mask[58:58] + attribute \src "libresoc.v:140971.3-141358.6" + wire $5\mask[4:4] + attribute \src "libresoc.v:140971.3-141358.6" + wire $60\mask[59:59] + attribute \src "libresoc.v:140971.3-141358.6" + wire $61\mask[60:60] + attribute \src "libresoc.v:140971.3-141358.6" + wire $62\mask[61:61] + attribute \src "libresoc.v:140971.3-141358.6" + wire $63\mask[62:62] + attribute \src "libresoc.v:140971.3-141358.6" + wire $64\mask[63:63] + attribute \src "libresoc.v:140971.3-141358.6" + wire $6\mask[5:5] + attribute \src "libresoc.v:140971.3-141358.6" + wire $7\mask[6:6] + attribute \src "libresoc.v:140971.3-141358.6" + wire $8\mask[7:7] + attribute \src "libresoc.v:140971.3-141358.6" + wire $9\mask[8:8] + attribute \src "libresoc.v:140907.17-140907.96" + wire $gt$libresoc.v:140907$6507_Y + attribute \src "libresoc.v:140908.18-140908.98" + wire $gt$libresoc.v:140908$6508_Y + attribute \src "libresoc.v:140909.19-140909.99" + wire $gt$libresoc.v:140909$6509_Y + attribute \src "libresoc.v:140910.19-140910.99" + wire $gt$libresoc.v:140910$6510_Y + attribute \src "libresoc.v:140911.19-140911.99" + wire $gt$libresoc.v:140911$6511_Y + attribute \src "libresoc.v:140912.19-140912.99" + wire $gt$libresoc.v:140912$6512_Y + attribute \src "libresoc.v:140913.19-140913.99" + wire $gt$libresoc.v:140913$6513_Y + attribute \src "libresoc.v:140914.19-140914.99" + wire $gt$libresoc.v:140914$6514_Y + attribute \src "libresoc.v:140915.19-140915.99" + wire $gt$libresoc.v:140915$6515_Y + attribute \src "libresoc.v:140916.19-140916.99" + wire $gt$libresoc.v:140916$6516_Y + attribute \src "libresoc.v:140917.19-140917.99" + wire $gt$libresoc.v:140917$6517_Y + attribute \src "libresoc.v:140918.18-140918.97" + wire $gt$libresoc.v:140918$6518_Y + attribute \src "libresoc.v:140919.19-140919.99" + wire $gt$libresoc.v:140919$6519_Y + attribute \src "libresoc.v:140920.19-140920.99" + wire $gt$libresoc.v:140920$6520_Y + attribute \src "libresoc.v:140921.19-140921.99" + wire $gt$libresoc.v:140921$6521_Y + attribute \src "libresoc.v:140922.19-140922.99" + wire $gt$libresoc.v:140922$6522_Y + attribute \src "libresoc.v:140923.19-140923.99" + wire $gt$libresoc.v:140923$6523_Y + attribute \src "libresoc.v:140924.18-140924.97" + wire $gt$libresoc.v:140924$6524_Y + attribute \src "libresoc.v:140925.18-140925.97" + wire $gt$libresoc.v:140925$6525_Y + attribute \src "libresoc.v:140926.18-140926.97" + wire $gt$libresoc.v:140926$6526_Y + attribute \src "libresoc.v:140927.17-140927.96" + wire $gt$libresoc.v:140927$6527_Y + attribute \src "libresoc.v:140928.18-140928.97" + wire $gt$libresoc.v:140928$6528_Y + attribute \src "libresoc.v:140929.18-140929.97" + wire $gt$libresoc.v:140929$6529_Y + attribute \src "libresoc.v:140930.18-140930.97" + wire $gt$libresoc.v:140930$6530_Y + attribute \src "libresoc.v:140931.18-140931.97" + wire $gt$libresoc.v:140931$6531_Y + attribute \src "libresoc.v:140932.18-140932.97" + wire $gt$libresoc.v:140932$6532_Y + attribute \src "libresoc.v:140933.18-140933.97" + wire $gt$libresoc.v:140933$6533_Y + attribute \src "libresoc.v:140934.18-140934.97" + wire $gt$libresoc.v:140934$6534_Y + attribute \src "libresoc.v:140935.18-140935.98" + wire $gt$libresoc.v:140935$6535_Y + attribute \src "libresoc.v:140936.18-140936.98" + wire $gt$libresoc.v:140936$6536_Y + attribute \src "libresoc.v:140937.18-140937.98" + wire $gt$libresoc.v:140937$6537_Y + attribute \src "libresoc.v:140938.17-140938.96" + wire $gt$libresoc.v:140938$6538_Y + attribute \src "libresoc.v:140939.18-140939.98" + wire $gt$libresoc.v:140939$6539_Y + attribute \src "libresoc.v:140940.18-140940.98" + wire $gt$libresoc.v:140940$6540_Y + attribute \src "libresoc.v:140941.18-140941.98" + wire $gt$libresoc.v:140941$6541_Y + attribute \src "libresoc.v:140942.18-140942.98" + wire $gt$libresoc.v:140942$6542_Y + attribute \src "libresoc.v:140943.18-140943.98" + wire $gt$libresoc.v:140943$6543_Y + attribute \src "libresoc.v:140944.18-140944.98" + wire $gt$libresoc.v:140944$6544_Y + attribute \src "libresoc.v:140945.18-140945.98" + wire $gt$libresoc.v:140945$6545_Y + attribute \src "libresoc.v:140946.18-140946.98" + wire $gt$libresoc.v:140946$6546_Y + attribute \src "libresoc.v:140947.18-140947.98" + wire $gt$libresoc.v:140947$6547_Y + attribute \src "libresoc.v:140948.18-140948.98" + wire $gt$libresoc.v:140948$6548_Y + attribute \src "libresoc.v:140949.17-140949.96" + wire $gt$libresoc.v:140949$6549_Y + attribute \src "libresoc.v:140950.18-140950.98" + wire $gt$libresoc.v:140950$6550_Y + attribute \src "libresoc.v:140951.18-140951.98" + wire $gt$libresoc.v:140951$6551_Y + attribute \src "libresoc.v:140952.18-140952.98" + wire $gt$libresoc.v:140952$6552_Y + attribute \src "libresoc.v:140953.18-140953.98" + wire $gt$libresoc.v:140953$6553_Y + attribute \src "libresoc.v:140954.18-140954.98" + wire $gt$libresoc.v:140954$6554_Y + attribute \src "libresoc.v:140955.18-140955.98" + wire $gt$libresoc.v:140955$6555_Y + attribute \src "libresoc.v:140956.18-140956.98" + wire $gt$libresoc.v:140956$6556_Y + attribute \src "libresoc.v:140957.18-140957.98" + wire $gt$libresoc.v:140957$6557_Y + attribute \src "libresoc.v:140958.18-140958.98" + wire $gt$libresoc.v:140958$6558_Y + attribute \src "libresoc.v:140959.18-140959.98" + wire $gt$libresoc.v:140959$6559_Y + attribute \src "libresoc.v:140960.17-140960.96" + wire $gt$libresoc.v:140960$6560_Y + attribute \src "libresoc.v:140961.18-140961.98" + wire $gt$libresoc.v:140961$6561_Y + attribute \src "libresoc.v:140962.18-140962.98" + wire $gt$libresoc.v:140962$6562_Y + attribute \src "libresoc.v:140963.18-140963.98" + wire $gt$libresoc.v:140963$6563_Y + attribute \src "libresoc.v:140964.18-140964.98" + wire $gt$libresoc.v:140964$6564_Y + attribute \src "libresoc.v:140965.18-140965.98" + wire $gt$libresoc.v:140965$6565_Y + attribute \src "libresoc.v:140966.18-140966.98" + wire $gt$libresoc.v:140966$6566_Y + attribute \src "libresoc.v:140967.18-140967.98" + wire $gt$libresoc.v:140967$6567_Y + attribute \src "libresoc.v:140968.18-140968.98" + wire $gt$libresoc.v:140968$6568_Y + attribute \src "libresoc.v:140969.18-140969.98" + wire $gt$libresoc.v:140969$6569_Y + attribute \src "libresoc.v:140970.18-140970.98" + wire $gt$libresoc.v:140970$6570_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$99 + attribute \src "libresoc.v:140773.7-140773.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 48 output 25 \ldst_port0_addr_i$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 26 \ldst_port0_addr_i_ok$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 16 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 27 \ldst_port0_addr_ok_o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire output 2 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire input 23 \ldst_port0_busy_o$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" - wire \ldst_port0_cache_paradox - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" - wire \ldst_port0_cache_paradox$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 24 \ldst_port0_data_len$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 8 \ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 9 \ldst_port0_exc_$signal$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 32 \ldst_port0_exc_$signal$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 10 \ldst_port0_exc_$signal$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 11 \ldst_port0_exc_$signal$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 12 \ldst_port0_exc_$signal$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 13 \ldst_port0_exc_$signal$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 14 \ldst_port0_exc_$signal$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 15 \ldst_port0_exc_$signal$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire \ldst_port0_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire \ldst_port0_go_die_i$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire input 3 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire output 21 \ldst_port0_is_ld_i$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire input 4 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire output 22 \ldst_port0_is_st_i$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 17 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 28 \ldst_port0_ld_data_o$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 18 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 29 \ldst_port0_ld_data_o_ok$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" - wire \ldst_port0_ldst_error - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" - wire \ldst_port0_ldst_error$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" - wire \ldst_port0_mmu_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" - wire \ldst_port0_mmu_done$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 19 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 31 \ldst_port0_st_data_i$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 20 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 30 \ldst_port0_st_data_i_ok$17 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire \pick_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire \pick_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire \pick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" - wire \reset_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" - wire \reset_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \reset_l_q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \reset_l_s_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:143435$6169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140907$6507 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \pick_n - connect \Y $not$libresoc.v:143435$6169_Y + connect \A \shift + connect \B 3'100 + connect \Y $gt$libresoc.v:140907$6507_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:143436$6170 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140908$6508 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o$10 - connect \Y $not$libresoc.v:143436$6170_Y + connect \A \shift + connect \B 6'110001 + connect \Y $gt$libresoc.v:140908$6508_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:143433$6167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140909$6509 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 6 parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:143433$6167_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:143434$6168 - parameter \WIDTH 1 - connect \A \idx_l$23 - connect \B \pick_o - connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:143434$6168_Y + connect \A \shift + connect \B 6'110010 + connect \Y $gt$libresoc.v:140909$6509_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:143441.9-143447.4" - cell \idx_l \idx_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_idx_l \idx_l_q_idx_l - connect \r_idx_l \idx_l_r_idx_l - connect \s_idx_l \idx_l_s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140910$6510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $gt$libresoc.v:140910$6510_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:143448.8-143452.4" - cell \pick \pick - connect \i \pick_i - connect \n \pick_n - connect \o \pick_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140911$6511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $gt$libresoc.v:140911$6511_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:143453.17-143459.4" - cell \reset_l$131 \reset_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_reset \reset_l_q_reset - connect \r_reset \reset_l_r_reset - connect \s_reset \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140912$6512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $gt$libresoc.v:140912$6512_Y end - attribute \src "libresoc.v:143277.7-143277.20" - process $proc$libresoc.v:143277$6226 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140913$6513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $gt$libresoc.v:140913$6513_Y end - attribute \src "libresoc.v:143297.7-143297.24" - process $proc$libresoc.v:143297$6227 - assign { } { } - assign $0\idx_l$23[0:0]$6228 1'0 - sync always - sync init - update \idx_l$23 $0\idx_l$23[0:0]$6228 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140914$6514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $gt$libresoc.v:140914$6514_Y end - attribute \src "libresoc.v:143424.7-143424.25" - process $proc$libresoc.v:143424$6229 - assign { } { } - assign $1\reset_delay[0:0] 1'0 - sync always - sync init - update \reset_delay $1\reset_delay[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140915$6515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $gt$libresoc.v:140915$6515_Y end - attribute \src "libresoc.v:143437.3-143438.36" - process $proc$libresoc.v:143437$6171 - assign { } { } - assign $0\reset_delay[0:0] \reset_l_q_reset - sync posedge \coresync_clk - update \reset_delay $0\reset_delay[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140916$6516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $gt$libresoc.v:140916$6516_Y end - attribute \src "libresoc.v:143439.3-143440.35" - process $proc$libresoc.v:143439$6172 - assign { } { } - assign $0\idx_l$23[0:0]$6173 \idx_l$23$next - sync posedge \coresync_clk - update \idx_l$23 $0\idx_l$23[0:0]$6173 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140917$6517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $gt$libresoc.v:140917$6517_Y end - attribute \src "libresoc.v:143460.3-143469.6" - process $proc$libresoc.v:143460$6174 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_i$12[47:0]$6175 $1\ldst_port0_addr_i$12[47:0]$6176 - attribute \src "libresoc.v:143461.5-143461.29" - switch \initial - attribute \src "libresoc.v:143461.9-143461.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_i$12[47:0]$6176 \$32 [47:0] - case - assign $1\ldst_port0_addr_i$12[47:0]$6176 48'000000000000000000000000000000000000000000000000 - end - sync always - update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6175 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140918$6518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $gt$libresoc.v:140918$6518_Y end - attribute \src "libresoc.v:143470.3-143479.6" - process $proc$libresoc.v:143470$6177 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_i_ok$13[0:0]$6178 $1\ldst_port0_addr_i_ok$13[0:0]$6179 - attribute \src "libresoc.v:143471.5-143471.29" - switch \initial - attribute \src "libresoc.v:143471.9-143471.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_i_ok$13[0:0]$6179 \ldst_port0_addr_i_ok - case - assign $1\ldst_port0_addr_i_ok$13[0:0]$6179 1'0 - end - sync always - update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6178 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140919$6519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $gt$libresoc.v:140919$6519_Y end - attribute \src "libresoc.v:143480.3-143490.6" - process $proc$libresoc.v:143480$6180 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_st_data_i$18[63:0]$6181 $1\ldst_port0_st_data_i$18[63:0]$6183 - assign $0\ldst_port0_st_data_i_ok$17[0:0]$6182 $1\ldst_port0_st_data_i_ok$17[0:0]$6184 - attribute \src "libresoc.v:143481.5-143481.29" - switch \initial - attribute \src "libresoc.v:143481.9-143481.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6184 $1\ldst_port0_st_data_i$18[63:0]$6183 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } - case - assign $1\ldst_port0_st_data_i$18[63:0]$6183 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_st_data_i_ok$17[0:0]$6184 1'0 - end - sync always - update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6181 - update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6182 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140920$6520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $gt$libresoc.v:140920$6520_Y end - attribute \src "libresoc.v:143491.3-143501.6" - process $proc$libresoc.v:143491$6185 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:143492.5-143492.29" - switch \initial - attribute \src "libresoc.v:143492.9-143492.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$16 \ldst_port0_ld_data_o$15 } - case - assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 - end - sync always - update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] - update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140921$6521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $gt$libresoc.v:140921$6521_Y end - attribute \src "libresoc.v:143502.3-143511.6" - process $proc$libresoc.v:143502$6186 - assign { } { } - assign { } { } - assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:143503.5-143503.29" - switch \initial - attribute \src "libresoc.v:143503.9-143503.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$10 - case - assign $1\ldst_port0_busy_o[0:0] 1'0 - end - sync always - update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140922$6522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $gt$libresoc.v:140922$6522_Y end - attribute \src "libresoc.v:143512.3-143521.6" - process $proc$libresoc.v:143512$6187 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:143513.5-143513.29" - switch \initial - attribute \src "libresoc.v:143513.9-143513.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$14 - case - assign $1\ldst_port0_addr_ok_o[0:0] 1'0 - end - sync always - update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140923$6523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $gt$libresoc.v:140923$6523_Y end - attribute \src "libresoc.v:143522.3-143538.6" - process $proc$libresoc.v:143522$6188 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_exc_$signal[0:0]$6189 $1\ldst_port0_exc_$signal[0:0]$6197 - assign $0\ldst_port0_exc_$signal$1[0:0]$6190 $1\ldst_port0_exc_$signal$1[0:0]$6198 - assign $0\ldst_port0_exc_$signal$2[0:0]$6191 $1\ldst_port0_exc_$signal$2[0:0]$6199 - assign $0\ldst_port0_exc_$signal$3[0:0]$6192 $1\ldst_port0_exc_$signal$3[0:0]$6200 - assign $0\ldst_port0_exc_$signal$4[0:0]$6193 $1\ldst_port0_exc_$signal$4[0:0]$6201 - assign $0\ldst_port0_exc_$signal$5[0:0]$6194 $1\ldst_port0_exc_$signal$5[0:0]$6202 - assign $0\ldst_port0_exc_$signal$6[0:0]$6195 $1\ldst_port0_exc_$signal$6[0:0]$6203 - assign $0\ldst_port0_exc_$signal$7[0:0]$6196 $1\ldst_port0_exc_$signal$7[0:0]$6204 - attribute \src "libresoc.v:143523.5-143523.29" - switch \initial - attribute \src "libresoc.v:143523.9-143523.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\ldst_port0_exc_$signal$7[0:0]$6204 $1\ldst_port0_exc_$signal$6[0:0]$6203 $1\ldst_port0_exc_$signal$5[0:0]$6202 $1\ldst_port0_exc_$signal$4[0:0]$6201 $1\ldst_port0_exc_$signal$3[0:0]$6200 $1\ldst_port0_exc_$signal$2[0:0]$6199 $1\ldst_port0_exc_$signal$1[0:0]$6198 $1\ldst_port0_exc_$signal[0:0]$6197 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } - case - assign $1\ldst_port0_exc_$signal[0:0]$6197 1'0 - assign $1\ldst_port0_exc_$signal$1[0:0]$6198 1'0 - assign $1\ldst_port0_exc_$signal$2[0:0]$6199 1'0 - assign $1\ldst_port0_exc_$signal$3[0:0]$6200 1'0 - assign $1\ldst_port0_exc_$signal$4[0:0]$6201 1'0 - assign $1\ldst_port0_exc_$signal$5[0:0]$6202 1'0 - assign $1\ldst_port0_exc_$signal$6[0:0]$6203 1'0 - assign $1\ldst_port0_exc_$signal$7[0:0]$6204 1'0 - end - sync always - update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6189 - update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6190 - update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6191 - update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6192 - update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6193 - update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6194 - update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6195 - update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140924$6524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $gt$libresoc.v:140924$6524_Y end - attribute \src "libresoc.v:143539.3-143553.6" - process $proc$libresoc.v:143539$6205 - assign { } { } - assign { } { } - assign { } { } - assign $0\idx_l$23$next[0:0]$6206 $2\idx_l$23$next[0:0]$6208 - attribute \src "libresoc.v:143540.5-143540.29" - switch \initial - attribute \src "libresoc.v:143540.9-143540.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\idx_l$23$next[0:0]$6207 \pick_o - case - assign $1\idx_l$23$next[0:0]$6207 \idx_l$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\idx_l$23$next[0:0]$6208 1'0 - case - assign $2\idx_l$23$next[0:0]$6208 $1\idx_l$23$next[0:0]$6207 - end - sync always - update \idx_l$23$next $0\idx_l$23$next[0:0]$6206 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140925$6525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'111 + connect \Y $gt$libresoc.v:140925$6525_Y end - attribute \src "libresoc.v:143554.3-143563.6" - process $proc$libresoc.v:143554$6209 - assign { } { } - assign { } { } - assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:143555.5-143555.29" - switch \initial - attribute \src "libresoc.v:143555.9-143555.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_mmu_done[0:0] \ldst_port0_mmu_done$40 - case - assign $1\ldst_port0_mmu_done[0:0] 1'0 - end - sync always - update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140926$6526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1000 + connect \Y $gt$libresoc.v:140926$6526_Y end - attribute \src "libresoc.v:143564.3-143573.6" - process $proc$libresoc.v:143564$6210 - assign { } { } - assign { } { } - assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:143565.5-143565.29" - switch \initial - attribute \src "libresoc.v:143565.9-143565.17" - case 1'1 - case + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140927$6527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'0 + connect \Y $gt$libresoc.v:140927$6527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140928$6528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1001 + connect \Y $gt$libresoc.v:140928$6528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140929$6529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1010 + connect \Y $gt$libresoc.v:140929$6529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140930$6530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1011 + connect \Y $gt$libresoc.v:140930$6530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140931$6531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1100 + connect \Y $gt$libresoc.v:140931$6531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140932$6532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1101 + connect \Y $gt$libresoc.v:140932$6532_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140933$6533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1110 + connect \Y $gt$libresoc.v:140933$6533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140934$6534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1111 + connect \Y $gt$libresoc.v:140934$6534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140935$6535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10000 + connect \Y $gt$libresoc.v:140935$6535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140936$6536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10001 + connect \Y $gt$libresoc.v:140936$6536_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140937$6537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10010 + connect \Y $gt$libresoc.v:140937$6537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140938$6538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'1 + connect \Y $gt$libresoc.v:140938$6538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140939$6539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10011 + connect \Y $gt$libresoc.v:140939$6539_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140940$6540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10100 + connect \Y $gt$libresoc.v:140940$6540_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140941$6541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10101 + connect \Y $gt$libresoc.v:140941$6541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140942$6542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10110 + connect \Y $gt$libresoc.v:140942$6542_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140943$6543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10111 + connect \Y $gt$libresoc.v:140943$6543_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140944$6544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11000 + connect \Y $gt$libresoc.v:140944$6544_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140945$6545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11001 + connect \Y $gt$libresoc.v:140945$6545_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140946$6546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11010 + connect \Y $gt$libresoc.v:140946$6546_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140947$6547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11011 + connect \Y $gt$libresoc.v:140947$6547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140948$6548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11100 + connect \Y $gt$libresoc.v:140948$6548_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140949$6549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'10 + connect \Y $gt$libresoc.v:140949$6549_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140950$6550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11101 + connect \Y $gt$libresoc.v:140950$6550_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140951$6551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11110 + connect \Y $gt$libresoc.v:140951$6551_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140952$6552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11111 + connect \Y $gt$libresoc.v:140952$6552_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140953$6553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100000 + connect \Y $gt$libresoc.v:140953$6553_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140954$6554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100001 + connect \Y $gt$libresoc.v:140954$6554_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140955$6555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100010 + connect \Y $gt$libresoc.v:140955$6555_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140956$6556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $gt$libresoc.v:140956$6556_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140957$6557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $gt$libresoc.v:140957$6557_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140958$6558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $gt$libresoc.v:140958$6558_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140959$6559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $gt$libresoc.v:140959$6559_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140960$6560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $gt$libresoc.v:140960$6560_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140961$6561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $gt$libresoc.v:140961$6561_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140962$6562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $gt$libresoc.v:140962$6562_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140963$6563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $gt$libresoc.v:140963$6563_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140964$6564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $gt$libresoc.v:140964$6564_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140965$6565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $gt$libresoc.v:140965$6565_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140966$6566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $gt$libresoc.v:140966$6566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140967$6567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $gt$libresoc.v:140967$6567_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140968$6568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $gt$libresoc.v:140968$6568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140969$6569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $gt$libresoc.v:140969$6569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:140970$6570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $gt$libresoc.v:140970$6570_Y + end + attribute \src "libresoc.v:140773.7-140773.20" + process $proc$libresoc.v:140773$6572 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:140971.3-141358.6" + process $proc$libresoc.v:140971$6571 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "libresoc.v:140972.5-140972.29" + switch \initial + attribute \src "libresoc.v:140972.9-140972.17" + case 1'1 + case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_ldst_error[0:0] \ldst_port0_ldst_error$41 + assign $1\mask[0:0] 1'1 case - assign $1\ldst_port0_ldst_error[0:0] 1'0 + assign $1\mask[0:0] 1'0 end - sync always - update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] - end - attribute \src "libresoc.v:143574.3-143583.6" - process $proc$libresoc.v:143574$6211 - assign { } { } - assign { } { } - assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:143575.5-143575.29" - switch \initial - attribute \src "libresoc.v:143575.9-143575.17" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 case + assign $2\mask[1:1] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_cache_paradox[0:0] \ldst_port0_cache_paradox$42 + assign $3\mask[2:2] 1'1 case - assign $1\ldst_port0_cache_paradox[0:0] 1'0 + assign $3\mask[2:2] 1'0 end - sync always - update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] - end - attribute \src "libresoc.v:143584.3-143593.6" - process $proc$libresoc.v:143584$6212 - assign { } { } - assign { } { } - assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:143585.5-143585.29" - switch \initial - attribute \src "libresoc.v:143585.9-143585.17" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 case + assign $4\mask[3:3] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - switch \$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\idx_l_s_idx_l[0:0] 1'1 + assign $5\mask[4:4] 1'1 case - assign $1\idx_l_s_idx_l[0:0] 1'0 + assign $5\mask[4:4] 1'0 end - sync always - update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] - end - attribute \src "libresoc.v:143594.3-143603.6" - process $proc$libresoc.v:143594$6213 - assign { } { } - assign { } { } - assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:143595.5-143595.29" - switch \initial - attribute \src "libresoc.v:143595.9-143595.17" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 case + assign $6\mask[5:5] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - switch \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\idx_l_r_idx_l[0:0] 1'1 + assign $7\mask[6:6] 1'1 case - assign $1\idx_l_r_idx_l[0:0] 1'1 + assign $7\mask[6:6] 1'0 end - sync always - update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] - end - attribute \src "libresoc.v:143604.3-143618.6" - process $proc$libresoc.v:143604$6214 - assign { } { } - assign { } { } - assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:143605.5-143605.29" - switch \initial - attribute \src "libresoc.v:143605.9-143605.17" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 case + assign $8\mask[7:7] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - switch \$28 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reset_l_s_reset[0:0] 1'1 - case - assign $2\reset_l_s_reset[0:0] 1'0 - end + assign $9\mask[8:8] 1'1 case - assign $1\reset_l_s_reset[0:0] 1'0 + assign $9\mask[8:8] 1'0 end - sync always - update \reset_l_s_reset $0\reset_l_s_reset[0:0] - end - attribute \src "libresoc.v:143619.3-143628.6" - process $proc$libresoc.v:143619$6215 - assign { } { } - assign { } { } - assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:143620.5-143620.29" - switch \initial - attribute \src "libresoc.v:143620.9-143620.17" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 case + assign $10\mask[9:9] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - switch \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$21 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reset_l_r_reset[0:0] 1'1 + assign $11\mask[10:10] 1'1 case - assign $1\reset_l_r_reset[0:0] 1'0 + assign $11\mask[10:10] 1'0 end - sync always - update \reset_l_r_reset $0\reset_l_r_reset[0:0] - end - attribute \src "libresoc.v:143629.3-143638.6" - process $proc$libresoc.v:143629$6216 - assign { } { } - assign { } { } - assign $0\ldst_port0_is_ld_i$8[0:0]$6217 $1\ldst_port0_is_ld_i$8[0:0]$6218 - attribute \src "libresoc.v:143630.5-143630.29" - switch \initial - attribute \src "libresoc.v:143630.9-143630.17" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 case + assign $12\mask[11:11] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_ld_i$8[0:0]$6218 \ldst_port0_is_ld_i + assign $13\mask[12:12] 1'1 case - assign $1\ldst_port0_is_ld_i$8[0:0]$6218 1'0 + assign $13\mask[12:12] 1'0 end - sync always - update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6217 - end - attribute \src "libresoc.v:143639.3-143648.6" - process $proc$libresoc.v:143639$6219 - assign { } { } - assign { } { } - assign $0\ldst_port0_is_st_i$9[0:0]$6220 $1\ldst_port0_is_st_i$9[0:0]$6221 - attribute \src "libresoc.v:143640.5-143640.29" - switch \initial - attribute \src "libresoc.v:143640.9-143640.17" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 case + assign $14\mask[13:13] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_st_i$9[0:0]$6221 \ldst_port0_is_st_i + assign $15\mask[14:14] 1'1 case - assign $1\ldst_port0_is_st_i$9[0:0]$6221 1'0 + assign $15\mask[14:14] 1'0 end - sync always - update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6220 - end - attribute \src "libresoc.v:143649.3-143658.6" - process $proc$libresoc.v:143649$6222 - assign { } { } - assign { } { } - assign $0\ldst_port0_data_len$11[3:0]$6223 $1\ldst_port0_data_len$11[3:0]$6224 - attribute \src "libresoc.v:143650.5-143650.29" - switch \initial - attribute \src "libresoc.v:143650.9-143650.17" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 case + assign $16\mask[15:15] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$33 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_data_len$11[3:0]$6224 \ldst_port0_data_len + assign $17\mask[16:16] 1'1 case - assign $1\ldst_port0_data_len$11[3:0]$6224 4'0000 + assign $17\mask[16:16] 1'0 end - sync always - update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6223 - end - attribute \src "libresoc.v:143659.3-143668.6" - process $proc$libresoc.v:143659$6225 - assign { } { } - assign { } { } - assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:143660.5-143660.29" - switch \initial - attribute \src "libresoc.v:143660.9-143660.17" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 case + assign $18\mask[17:17] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$37 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$30 + assign $19\mask[18:18] 1'1 case - assign $1\ldst_port0_go_die_i[0:0] 1'0 + assign $19\mask[18:18] 1'0 end - sync always - update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] - end - connect \$20 $or$libresoc.v:143433$6167_Y - connect \$24 $ternary$libresoc.v:143434$6168_Y - connect \$26 $not$libresoc.v:143435$6169_Y - connect \$28 $not$libresoc.v:143436$6170_Y - connect \$22 \$24 - connect \$32 \ldst_port0_addr_i - connect \ldst_port0_go_die_i$30 1'0 - connect \ldst_port0_exc_$signal$33 1'0 - connect \ldst_port0_exc_$signal$34 1'0 - connect \ldst_port0_exc_$signal$35 1'0 - connect \ldst_port0_exc_$signal$36 1'0 - connect \ldst_port0_exc_$signal$37 1'0 - connect \ldst_port0_exc_$signal$38 1'0 - connect \ldst_port0_exc_$signal$39 1'0 - connect \ldst_port0_mmu_done$40 1'0 - connect \ldst_port0_ldst_error$41 1'0 - connect \ldst_port0_cache_paradox$42 1'0 - connect \reset_delay$next \reset_l_q_reset - connect \pick_i \$20 -end -attribute \src "libresoc.v:143688.1-143746.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" -attribute \generator "nMigen" -module \ld_active - attribute \src "libresoc.v:143689.7-143689.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:143734.3-143742.6" - wire $0\q_int$next[0:0]$6240 - attribute \src "libresoc.v:143732.3-143733.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:143734.3-143742.6" - wire $1\q_int$next[0:0]$6241 - attribute \src "libresoc.v:143711.7-143711.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:143724.17-143724.96" - wire $and$libresoc.v:143724$6230_Y - attribute \src "libresoc.v:143729.17-143729.96" - wire $and$libresoc.v:143729$6235_Y - attribute \src "libresoc.v:143726.18-143726.99" - wire $not$libresoc.v:143726$6232_Y - attribute \src "libresoc.v:143728.17-143728.98" - wire $not$libresoc.v:143728$6234_Y - attribute \src "libresoc.v:143731.17-143731.98" - wire $not$libresoc.v:143731$6237_Y - attribute \src "libresoc.v:143725.18-143725.104" - wire $or$libresoc.v:143725$6231_Y - attribute \src "libresoc.v:143727.18-143727.105" - wire $or$libresoc.v:143727$6233_Y - attribute \src "libresoc.v:143730.17-143730.103" - wire $or$libresoc.v:143730$6236_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:143689.7-143689.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 2 \r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 3 \s_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:143724$6230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:143724$6230_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:143729$6235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:143729$6235_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:143726$6232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_ld_active - connect \Y $not$libresoc.v:143726$6232_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:143728$6234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_ld_active - connect \Y $not$libresoc.v:143728$6234_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:143731$6237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_ld_active - connect \Y $not$libresoc.v:143731$6237_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:143725$6231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_ld_active - connect \Y $or$libresoc.v:143725$6231_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:143727$6233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_ld_active - connect \B \q_int - connect \Y $or$libresoc.v:143727$6233_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:143730$6236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_ld_active - connect \Y $or$libresoc.v:143730$6236_Y - end - attribute \src "libresoc.v:143689.7-143689.20" - process $proc$libresoc.v:143689$6242 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:143711.7-143711.19" - process $proc$libresoc.v:143711$6243 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:143732.3-143733.27" - process $proc$libresoc.v:143732$6238 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:143734.3-143742.6" - process $proc$libresoc.v:143734$6239 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$6240 $1\q_int$next[0:0]$6241 - attribute \src "libresoc.v:143735.5-143735.29" - switch \initial - attribute \src "libresoc.v:143735.9-143735.17" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 case + assign $20\mask[19:19] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6241 1'0 + assign $21\mask[20:20] 1'1 case - assign $1\q_int$next[0:0]$6241 \$5 + assign $21\mask[20:20] 1'0 end - sync always - update \q_int$next $0\q_int$next[0:0]$6240 - end - connect \$9 $and$libresoc.v:143724$6230_Y - connect \$11 $or$libresoc.v:143725$6231_Y - connect \$13 $not$libresoc.v:143726$6232_Y - connect \$15 $or$libresoc.v:143727$6233_Y - connect \$1 $not$libresoc.v:143728$6234_Y - connect \$3 $and$libresoc.v:143729$6235_Y - connect \$5 $or$libresoc.v:143730$6236_Y - connect \$7 $not$libresoc.v:143731$6237_Y - connect \qlq_ld_active \$15 - connect \qn_ld_active \$13 - connect \q_ld_active \$11 -end -attribute \src "libresoc.v:143750.1-145109.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" -attribute \generator "nMigen" -module \ldst0 - attribute \src "libresoc.v:144764.3-144772.6" - wire $0\adr_l_r_adr$next[0:0]$6386 - attribute \src "libresoc.v:144646.3-144647.39" - wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:144592.3-144593.21" - wire $0\alu_ok[0:0] - attribute \src "libresoc.v:144929.3-144938.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:144939.3-144948.6" - wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:144919.3-144928.6" - wire width 64 $0\ea_r$next[63:0]$6474 - attribute \src "libresoc.v:144594.3-144595.25" - wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:143751.7-143751.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:144994.3-145013.6" - wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:144958.3-144981.6" - wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:144861.3-144870.6" - wire width 64 $0\ldo_r$next[63:0]$6459 - attribute \src "libresoc.v:144602.3-144603.27" - wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:144590.3-144591.33" - wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:144949.3-144957.6" - wire $0\ldst_port0_addr_i_ok$next[0:0]$6479 - attribute \src "libresoc.v:144588.3-144589.57" - wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:145038.3-145049.6" - wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:144809.3-144817.6" - wire $0\lsd_l_r_lsd$next[0:0]$6401 - attribute \src "libresoc.v:144636.3-144637.39" - wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:144737.3-144745.6" - wire $0\opc_l_r_opc$next[0:0]$6377 - attribute \src "libresoc.v:144652.3-144653.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:144728.3-144736.6" - wire $0\opc_l_s_opc$next[0:0]$6374 - attribute \src "libresoc.v:144654.3-144655.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $0\oper_r__byte_reverse$next[0:0]$6404 - attribute \src "libresoc.v:144628.3-144629.57" - wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 4 $0\oper_r__data_len$next[3:0]$6405 - attribute \src "libresoc.v:144626.3-144627.49" - wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 13 $0\oper_r__fn_unit$next[12:0]$6406 - attribute \src "libresoc.v:144606.3-144607.47" - wire width 13 $0\oper_r__fn_unit[12:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 64 $0\oper_r__imm_data__data$next[63:0]$6407 - attribute \src "libresoc.v:144608.3-144609.61" - wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $0\oper_r__imm_data__ok$next[0:0]$6408 - attribute \src "libresoc.v:144610.3-144611.57" - wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 32 $0\oper_r__insn$next[31:0]$6409 - attribute \src "libresoc.v:144634.3-144635.41" - wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 7 $0\oper_r__insn_type$next[6:0]$6410 - attribute \src "libresoc.v:144604.3-144605.51" - wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $0\oper_r__is_32bit$next[0:0]$6411 - attribute \src "libresoc.v:144622.3-144623.49" - wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $0\oper_r__is_signed$next[0:0]$6412 - attribute \src "libresoc.v:144624.3-144625.51" - wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 2 $0\oper_r__ldst_mode$next[1:0]$6413 - attribute \src "libresoc.v:144632.3-144633.51" - wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $0\oper_r__oe__oe$next[0:0]$6414 - attribute \src "libresoc.v:144618.3-144619.45" - wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $0\oper_r__oe__ok$next[0:0]$6415 - attribute \src "libresoc.v:144620.3-144621.45" - wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $0\oper_r__rc__ok$next[0:0]$6416 - attribute \src "libresoc.v:144616.3-144617.45" - wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $0\oper_r__rc__rc$next[0:0]$6417 - attribute \src "libresoc.v:144614.3-144615.45" - wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $0\oper_r__sign_extend$next[0:0]$6418 - attribute \src "libresoc.v:144630.3-144631.55" - wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $0\oper_r__zero_a$next[0:0]$6419 - attribute \src "libresoc.v:144612.3-144613.45" - wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:144656.3-144657.28" - wire $0\p_st_go[0:0] - attribute \src "libresoc.v:144982.3-144993.6" - wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:144755.3-144763.6" - wire width 3 $0\src_l_r_src$next[2:0]$6383 - attribute \src "libresoc.v:144648.3-144649.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:144746.3-144754.6" - wire width 3 $0\src_l_s_src$next[2:0]$6380 - attribute \src "libresoc.v:144650.3-144651.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:144871.3-144886.6" - wire width 64 $0\src_r0$next[63:0]$6462 - attribute \src "libresoc.v:144600.3-144601.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:144887.3-144902.6" - wire width 64 $0\src_r1$next[63:0]$6466 - attribute \src "libresoc.v:144598.3-144599.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:144903.3-144918.6" - wire width 64 $0\src_r2$next[63:0]$6470 - attribute \src "libresoc.v:144596.3-144597.29" - wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:145014.3-145037.6" - wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:144800.3-144808.6" - wire $0\sto_l_r_sto$next[0:0]$6398 - attribute \src "libresoc.v:144638.3-144639.39" - wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:144791.3-144799.6" - wire $0\upd_l_r_upd$next[0:0]$6395 - attribute \src "libresoc.v:144640.3-144641.39" - wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:144782.3-144790.6" - wire $0\upd_l_s_upd$next[0:0]$6392 - attribute \src "libresoc.v:144642.3-144643.39" - wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:144773.3-144781.6" - wire $0\wri_l_r_wri$next[0:0]$6389 - attribute \src "libresoc.v:144644.3-144645.39" - wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:144764.3-144772.6" - wire $1\adr_l_r_adr$next[0:0]$6387 - attribute \src "libresoc.v:143947.7-143947.25" - wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:143961.7-143961.20" - wire $1\alu_ok[0:0] - attribute \src "libresoc.v:144929.3-144938.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:144939.3-144948.6" - wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:144919.3-144928.6" - wire width 64 $1\ea_r$next[63:0]$6475 - attribute \src "libresoc.v:144007.14-144007.41" - wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:144994.3-145013.6" - wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:144958.3-144981.6" - wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:144861.3-144870.6" - wire width 64 $1\ldo_r$next[63:0]$6460 - attribute \src "libresoc.v:144037.14-144037.42" - wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:144042.14-144042.62" - wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:144949.3-144957.6" - wire $1\ldst_port0_addr_i_ok$next[0:0]$6480 - attribute \src "libresoc.v:144047.7-144047.34" - wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:145038.3-145049.6" - wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:144809.3-144817.6" - wire $1\lsd_l_r_lsd$next[0:0]$6402 - attribute \src "libresoc.v:144096.7-144096.25" - wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:144737.3-144745.6" - wire $1\opc_l_r_opc$next[0:0]$6378 - attribute \src "libresoc.v:144110.7-144110.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:144728.3-144736.6" - wire $1\opc_l_s_opc$next[0:0]$6375 - attribute \src "libresoc.v:144114.7-144114.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $1\oper_r__byte_reverse$next[0:0]$6420 - attribute \src "libresoc.v:144243.7-144243.34" - wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 4 $1\oper_r__data_len$next[3:0]$6421 - attribute \src "libresoc.v:144247.13-144247.36" - wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 13 $1\oper_r__fn_unit$next[12:0]$6422 - attribute \src "libresoc.v:144265.14-144265.40" - wire width 13 $1\oper_r__fn_unit[12:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 64 $1\oper_r__imm_data__data$next[63:0]$6423 - attribute \src "libresoc.v:144269.14-144269.59" - wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $1\oper_r__imm_data__ok$next[0:0]$6424 - attribute \src "libresoc.v:144273.7-144273.34" - wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 32 $1\oper_r__insn$next[31:0]$6425 - attribute \src "libresoc.v:144277.14-144277.34" - wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 7 $1\oper_r__insn_type$next[6:0]$6426 - attribute \src "libresoc.v:144355.13-144355.38" - wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $1\oper_r__is_32bit$next[0:0]$6427 - attribute \src "libresoc.v:144359.7-144359.30" - wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $1\oper_r__is_signed$next[0:0]$6428 - attribute \src "libresoc.v:144363.7-144363.31" - wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 2 $1\oper_r__ldst_mode$next[1:0]$6429 - attribute \src "libresoc.v:144372.13-144372.37" - wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $1\oper_r__oe__oe$next[0:0]$6430 - attribute \src "libresoc.v:144376.7-144376.28" - wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $1\oper_r__oe__ok$next[0:0]$6431 - attribute \src "libresoc.v:144380.7-144380.28" - wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $1\oper_r__rc__ok$next[0:0]$6432 - attribute \src "libresoc.v:144384.7-144384.28" - wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $1\oper_r__rc__rc$next[0:0]$6433 - attribute \src "libresoc.v:144388.7-144388.28" - wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $1\oper_r__sign_extend$next[0:0]$6434 - attribute \src "libresoc.v:144392.7-144392.33" - wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $1\oper_r__zero_a$next[0:0]$6435 - attribute \src "libresoc.v:144396.7-144396.28" - wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:144400.7-144400.21" - wire $1\p_st_go[0:0] - attribute \src "libresoc.v:144982.3-144993.6" - wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:144755.3-144763.6" - wire width 3 $1\src_l_r_src$next[2:0]$6384 - attribute \src "libresoc.v:144442.13-144442.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:144746.3-144754.6" - wire width 3 $1\src_l_s_src$next[2:0]$6381 - attribute \src "libresoc.v:144446.13-144446.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:144871.3-144886.6" - wire width 64 $1\src_r0$next[63:0]$6463 - attribute \src "libresoc.v:144450.14-144450.43" - wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:144887.3-144902.6" - wire width 64 $1\src_r1$next[63:0]$6467 - attribute \src "libresoc.v:144454.14-144454.43" - wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:144903.3-144918.6" - wire width 64 $1\src_r2$next[63:0]$6471 - attribute \src "libresoc.v:144458.14-144458.43" - wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:145014.3-145037.6" - wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:144800.3-144808.6" - wire $1\sto_l_r_sto$next[0:0]$6399 - attribute \src "libresoc.v:144468.7-144468.25" - wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:144791.3-144799.6" - wire $1\upd_l_r_upd$next[0:0]$6396 - attribute \src "libresoc.v:144478.7-144478.25" - wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:144782.3-144790.6" - wire $1\upd_l_s_upd$next[0:0]$6393 - attribute \src "libresoc.v:144482.7-144482.25" - wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:144773.3-144781.6" - wire $1\wri_l_r_wri$next[0:0]$6390 - attribute \src "libresoc.v:144492.7-144492.25" - wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:144994.3-145013.6" - wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:144958.3-144981.6" - wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire $2\oper_r__byte_reverse$next[0:0]$6436 - attribute \src "libresoc.v:144818.3-144860.6" - wire width 4 $2\oper_r__data_len$next[3:0]$6437 - attribute \src "libresoc.v:144818.3-144860.6" - wire width 13 $2\oper_r__fn_unit$next[12:0]$6438 - attribute \src "libresoc.v:144818.3-144860.6" - wire width 64 $2\oper_r__imm_data__data$next[63:0]$6439 - attribute \src "libresoc.v:144818.3-144860.6" - wire $2\oper_r__imm_data__ok$next[0:0]$6440 - attribute \src "libresoc.v:144818.3-144860.6" - wire width 32 $2\oper_r__insn$next[31:0]$6441 - attribute \src "libresoc.v:144818.3-144860.6" - wire width 7 $2\oper_r__insn_type$next[6:0]$6442 - attribute \src "libresoc.v:144818.3-144860.6" - wire $2\oper_r__is_32bit$next[0:0]$6443 - attribute \src "libresoc.v:144818.3-144860.6" - wire $2\oper_r__is_signed$next[0:0]$6444 - attribute \src "libresoc.v:144818.3-144860.6" - wire width 2 $2\oper_r__ldst_mode$next[1:0]$6445 - attribute \src "libresoc.v:144818.3-144860.6" - wire $2\oper_r__oe__oe$next[0:0]$6446 - attribute \src "libresoc.v:144818.3-144860.6" - wire $2\oper_r__oe__ok$next[0:0]$6447 - attribute \src "libresoc.v:144818.3-144860.6" - wire $2\oper_r__rc__ok$next[0:0]$6448 - attribute \src "libresoc.v:144818.3-144860.6" - wire $2\oper_r__rc__rc$next[0:0]$6449 - attribute \src "libresoc.v:144818.3-144860.6" - wire $2\oper_r__sign_extend$next[0:0]$6450 - attribute \src "libresoc.v:144818.3-144860.6" - wire $2\oper_r__zero_a$next[0:0]$6451 - attribute \src "libresoc.v:144871.3-144886.6" - wire width 64 $2\src_r0$next[63:0]$6464 - attribute \src "libresoc.v:144887.3-144902.6" - wire width 64 $2\src_r1$next[63:0]$6468 - attribute \src "libresoc.v:144903.3-144918.6" - wire width 64 $2\src_r2$next[63:0]$6472 - attribute \src "libresoc.v:145014.3-145037.6" - wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:144818.3-144860.6" - wire width 64 $3\oper_r__imm_data__data$next[63:0]$6452 - attribute \src "libresoc.v:144818.3-144860.6" - wire $3\oper_r__imm_data__ok$next[0:0]$6453 - attribute \src "libresoc.v:144818.3-144860.6" - wire $3\oper_r__oe__oe$next[0:0]$6454 - attribute \src "libresoc.v:144818.3-144860.6" - wire $3\oper_r__oe__ok$next[0:0]$6455 - attribute \src "libresoc.v:144818.3-144860.6" - wire $3\oper_r__rc__ok$next[0:0]$6456 - attribute \src "libresoc.v:144818.3-144860.6" - wire $3\oper_r__rc__rc$next[0:0]$6457 - attribute \src "libresoc.v:144574.18-144574.124" - wire width 65 $add$libresoc.v:144574$6324_Y - attribute \src "libresoc.v:144497.19-144497.118" - wire $and$libresoc.v:144497$6244_Y - attribute \src "libresoc.v:144498.19-144498.125" - wire $and$libresoc.v:144498$6245_Y - attribute \src "libresoc.v:144499.19-144499.120" - wire $and$libresoc.v:144499$6246_Y - attribute \src "libresoc.v:144500.19-144500.125" - wire $and$libresoc.v:144500$6247_Y - attribute \src "libresoc.v:144501.19-144501.118" - wire $and$libresoc.v:144501$6248_Y - attribute \src "libresoc.v:144503.19-144503.119" - wire $and$libresoc.v:144503$6250_Y - attribute \src "libresoc.v:144504.19-144504.123" - wire $and$libresoc.v:144504$6251_Y - attribute \src "libresoc.v:144505.19-144505.123" - wire $and$libresoc.v:144505$6252_Y - attribute \src "libresoc.v:144506.19-144506.120" - wire $and$libresoc.v:144506$6253_Y - attribute \src "libresoc.v:144507.19-144507.123" - wire $and$libresoc.v:144507$6254_Y - attribute \src "libresoc.v:144508.19-144508.119" - wire $and$libresoc.v:144508$6255_Y - attribute \src "libresoc.v:144509.19-144509.123" - wire $and$libresoc.v:144509$6256_Y - attribute \src "libresoc.v:144510.19-144510.125" - wire $and$libresoc.v:144510$6257_Y - attribute \src "libresoc.v:144512.19-144512.116" - wire $and$libresoc.v:144512$6259_Y - attribute \src "libresoc.v:144514.19-144514.120" - wire $and$libresoc.v:144514$6261_Y - attribute \src "libresoc.v:144515.19-144515.123" - wire $and$libresoc.v:144515$6262_Y - attribute \src "libresoc.v:144519.19-144519.125" - wire $and$libresoc.v:144519$6266_Y - attribute \src "libresoc.v:144520.19-144520.123" - wire $and$libresoc.v:144520$6267_Y - attribute \src "libresoc.v:144525.19-144525.116" - wire $and$libresoc.v:144525$6272_Y - attribute \src "libresoc.v:144527.19-144527.116" - wire $and$libresoc.v:144527$6274_Y - attribute \src "libresoc.v:144530.19-144530.118" - wire $and$libresoc.v:144530$6277_Y - attribute \src "libresoc.v:144532.19-144532.125" - wire $and$libresoc.v:144532$6279_Y - attribute \src "libresoc.v:144535.19-144535.160" - wire width 3 $and$libresoc.v:144535$6282_Y - attribute \src "libresoc.v:144536.19-144536.122" - wire $and$libresoc.v:144536$6283_Y - attribute \src "libresoc.v:144537.19-144537.122" - wire $and$libresoc.v:144537$6284_Y - attribute \src "libresoc.v:144539.19-144539.122" - wire $and$libresoc.v:144539$6287_Y - attribute \src "libresoc.v:144551.18-144551.123" - wire $and$libresoc.v:144551$6301_Y - attribute \src "libresoc.v:144552.18-144552.123" - wire $and$libresoc.v:144552$6302_Y - attribute \src "libresoc.v:144554.18-144554.114" - wire $and$libresoc.v:144554$6304_Y - attribute \src "libresoc.v:144556.18-144556.113" - wire $and$libresoc.v:144556$6306_Y - attribute \src "libresoc.v:144559.18-144559.113" - wire $and$libresoc.v:144559$6309_Y - attribute \src "libresoc.v:144563.18-144563.113" - wire $and$libresoc.v:144563$6313_Y - attribute \src "libresoc.v:144566.18-144566.119" - wire $and$libresoc.v:144566$6316_Y - attribute \src "libresoc.v:144575.18-144575.150" - wire width 3 $and$libresoc.v:144575$6325_Y - attribute \src "libresoc.v:144577.18-144577.113" - wire width 3 $and$libresoc.v:144577$6327_Y - attribute \src "libresoc.v:144579.18-144579.113" - wire width 3 $and$libresoc.v:144579$6329_Y - attribute \src "libresoc.v:144580.18-144580.127" - wire $and$libresoc.v:144580$6330_Y - attribute \src "libresoc.v:144581.18-144581.117" - wire $and$libresoc.v:144581$6331_Y - attribute \src "libresoc.v:144586.18-144586.117" - wire $and$libresoc.v:144586$6336_Y - attribute \src "libresoc.v:144511.19-144511.127" - wire $eq$libresoc.v:144511$6258_Y - attribute \src "libresoc.v:144531.19-144531.127" - wire $eq$libresoc.v:144531$6278_Y - attribute \src "libresoc.v:144533.19-144533.127" - wire $eq$libresoc.v:144533$6280_Y - attribute \src "libresoc.v:144544.19-144544.126" - wire $eq$libresoc.v:144544$6293_Y - attribute \src "libresoc.v:144549.18-144549.127" - wire $eq$libresoc.v:144549$6299_Y - attribute \src "libresoc.v:144550.18-144550.127" - wire $eq$libresoc.v:144550$6300_Y - attribute \src "libresoc.v:144558.18-144558.126" - wire $eq$libresoc.v:144558$6308_Y - attribute \src "libresoc.v:144562.18-144562.126" - wire $eq$libresoc.v:144562$6312_Y - attribute \src "libresoc.v:144538.19-144538.110" - wire width 96 $extend$libresoc.v:144538$6285_Y - attribute \src "libresoc.v:144540.19-144540.116" - wire width 64 $extend$libresoc.v:144540$6288_Y - attribute \src "libresoc.v:144545.19-144545.102" - wire width 64 $extend$libresoc.v:144545$6294_Y - attribute \src "libresoc.v:144523.19-144523.109" - wire $not$libresoc.v:144523$6270_Y - attribute \src "libresoc.v:144528.19-144528.121" - wire $not$libresoc.v:144528$6275_Y - attribute \src "libresoc.v:144553.18-144553.112" - wire $not$libresoc.v:144553$6303_Y - attribute \src "libresoc.v:144555.18-144555.110" - wire $not$libresoc.v:144555$6305_Y - attribute \src "libresoc.v:144557.18-144557.120" - wire $not$libresoc.v:144557$6307_Y - attribute \src "libresoc.v:144561.18-144561.120" - wire $not$libresoc.v:144561$6311_Y - attribute \src "libresoc.v:144576.18-144576.143" - wire width 2 $not$libresoc.v:144576$6326_Y - attribute \src "libresoc.v:144578.18-144578.115" - wire width 3 $not$libresoc.v:144578$6328_Y - attribute \src "libresoc.v:144585.18-144585.107" - wire $not$libresoc.v:144585$6335_Y - attribute \src "libresoc.v:144587.18-144587.118" - wire $not$libresoc.v:144587$6337_Y - attribute \src "libresoc.v:144502.18-144502.124" - wire $or$libresoc.v:144502$6249_Y - attribute \src "libresoc.v:144513.18-144513.129" - wire $or$libresoc.v:144513$6260_Y - attribute \src "libresoc.v:144516.19-144516.123" - wire $or$libresoc.v:144516$6263_Y - attribute \src "libresoc.v:144517.19-144517.125" - wire $or$libresoc.v:144517$6264_Y - attribute \src "libresoc.v:144518.19-144518.125" - wire $or$libresoc.v:144518$6265_Y - attribute \src "libresoc.v:144521.19-144521.132" - wire $or$libresoc.v:144521$6268_Y - attribute \src "libresoc.v:144522.19-144522.126" - wire $or$libresoc.v:144522$6269_Y - attribute \src "libresoc.v:144524.18-144524.129" - wire $or$libresoc.v:144524$6271_Y - attribute \src "libresoc.v:144526.19-144526.125" - wire $or$libresoc.v:144526$6273_Y - attribute \src "libresoc.v:144529.19-144529.119" - wire $or$libresoc.v:144529$6276_Y - attribute \src "libresoc.v:144534.18-144534.126" - wire $or$libresoc.v:144534$6281_Y - attribute \src "libresoc.v:144542.18-144542.156" - wire width 3 $or$libresoc.v:144542$6291_Y - attribute \src "libresoc.v:144548.18-144548.126" - wire $or$libresoc.v:144548$6298_Y - attribute \src "libresoc.v:144560.18-144560.116" - wire $or$libresoc.v:144560$6310_Y - attribute \src "libresoc.v:144564.18-144564.116" - wire $or$libresoc.v:144564$6314_Y - attribute \src "libresoc.v:144565.18-144565.127" - wire width 2 $or$libresoc.v:144565$6315_Y - attribute \src "libresoc.v:144567.18-144567.118" - wire $or$libresoc.v:144567$6317_Y - attribute \src "libresoc.v:144568.18-144568.118" - wire $or$libresoc.v:144568$6318_Y - attribute \src "libresoc.v:144569.18-144569.114" - wire $or$libresoc.v:144569$6319_Y - attribute \src "libresoc.v:144582.17-144582.124" - wire $or$libresoc.v:144582$6332_Y - attribute \src "libresoc.v:144583.18-144583.132" - wire $or$libresoc.v:144583$6333_Y - attribute \src "libresoc.v:144584.18-144584.134" - wire $or$libresoc.v:144584$6334_Y - attribute \src "libresoc.v:144538.19-144538.110" - wire width 96 $pos$libresoc.v:144538$6286_Y - attribute \src "libresoc.v:144540.19-144540.116" - wire width 64 $pos$libresoc.v:144540$6289_Y - attribute \src "libresoc.v:144541.19-144541.148" - wire width 64 $pos$libresoc.v:144541$6290_Y - attribute \src "libresoc.v:144543.19-144543.206" - wire width 64 $pos$libresoc.v:144543$6292_Y - attribute \src "libresoc.v:144545.19-144545.102" - wire width 64 $pos$libresoc.v:144545$6295_Y - attribute \src "libresoc.v:144546.19-144546.120" - wire width 64 $pos$libresoc.v:144546$6296_Y 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\$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - wire \$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - wire \$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - wire \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - wire \$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - wire \$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - wire \$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - wire \$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - wire \$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - wire \$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - wire \$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - wire \$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - wire \$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - wire \$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - wire \$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - wire \$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - wire \$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - wire \$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - wire \$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - wire \$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - wire \$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - wire \$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - wire \$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - wire \$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - wire width 3 \$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - wire \$167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - wire width 3 \$169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - wire \$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" - wire \$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - wire width 96 \$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" - wire \$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - wire width 3 \$18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - wire width 64 \$186 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - wire width 64 \$188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - wire width 64 \$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - wire \$192 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - wire width 64 \$194 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - wire width 64 \$196 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - wire width 64 \$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" - wire width 2 \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$libresoc.v:140907$6507_Y + connect \$99 $gt$libresoc.v:140908$6508_Y + connect \$101 $gt$libresoc.v:140909$6509_Y + connect \$103 $gt$libresoc.v:140910$6510_Y + connect \$105 $gt$libresoc.v:140911$6511_Y + connect \$107 $gt$libresoc.v:140912$6512_Y + connect \$109 $gt$libresoc.v:140913$6513_Y + connect \$111 $gt$libresoc.v:140914$6514_Y + connect \$113 $gt$libresoc.v:140915$6515_Y + connect \$115 $gt$libresoc.v:140916$6516_Y + connect \$117 $gt$libresoc.v:140917$6517_Y + connect \$11 $gt$libresoc.v:140918$6518_Y + connect \$119 $gt$libresoc.v:140919$6519_Y + connect \$121 $gt$libresoc.v:140920$6520_Y + connect \$123 $gt$libresoc.v:140921$6521_Y + connect \$125 $gt$libresoc.v:140922$6522_Y + connect \$127 $gt$libresoc.v:140923$6523_Y + connect \$13 $gt$libresoc.v:140924$6524_Y + connect \$15 $gt$libresoc.v:140925$6525_Y + connect \$17 $gt$libresoc.v:140926$6526_Y + connect \$1 $gt$libresoc.v:140927$6527_Y + connect \$19 $gt$libresoc.v:140928$6528_Y + connect \$21 $gt$libresoc.v:140929$6529_Y + connect \$23 $gt$libresoc.v:140930$6530_Y + connect \$25 $gt$libresoc.v:140931$6531_Y + connect \$27 $gt$libresoc.v:140932$6532_Y + connect \$29 $gt$libresoc.v:140933$6533_Y + connect \$31 $gt$libresoc.v:140934$6534_Y + connect \$33 $gt$libresoc.v:140935$6535_Y + connect \$35 $gt$libresoc.v:140936$6536_Y + connect \$37 $gt$libresoc.v:140937$6537_Y + connect \$3 $gt$libresoc.v:140938$6538_Y + connect \$39 $gt$libresoc.v:140939$6539_Y + connect \$41 $gt$libresoc.v:140940$6540_Y + connect \$43 $gt$libresoc.v:140941$6541_Y + connect \$45 $gt$libresoc.v:140942$6542_Y + connect \$47 $gt$libresoc.v:140943$6543_Y + connect \$49 $gt$libresoc.v:140944$6544_Y + connect \$51 $gt$libresoc.v:140945$6545_Y + connect \$53 $gt$libresoc.v:140946$6546_Y + connect \$55 $gt$libresoc.v:140947$6547_Y + connect \$57 $gt$libresoc.v:140948$6548_Y + connect \$5 $gt$libresoc.v:140949$6549_Y + connect \$59 $gt$libresoc.v:140950$6550_Y + connect \$61 $gt$libresoc.v:140951$6551_Y + connect \$63 $gt$libresoc.v:140952$6552_Y + connect \$65 $gt$libresoc.v:140953$6553_Y + connect \$67 $gt$libresoc.v:140954$6554_Y + connect \$69 $gt$libresoc.v:140955$6555_Y + connect \$71 $gt$libresoc.v:140956$6556_Y + connect \$73 $gt$libresoc.v:140957$6557_Y + connect \$75 $gt$libresoc.v:140958$6558_Y + connect \$77 $gt$libresoc.v:140959$6559_Y + connect \$7 $gt$libresoc.v:140960$6560_Y + connect \$79 $gt$libresoc.v:140961$6561_Y + connect \$81 $gt$libresoc.v:140962$6562_Y + connect \$83 $gt$libresoc.v:140963$6563_Y + connect \$85 $gt$libresoc.v:140964$6564_Y + connect \$87 $gt$libresoc.v:140965$6565_Y + connect \$89 $gt$libresoc.v:140966$6566_Y + connect \$91 $gt$libresoc.v:140967$6567_Y + connect \$93 $gt$libresoc.v:140968$6568_Y + connect \$95 $gt$libresoc.v:140969$6569_Y + connect \$97 $gt$libresoc.v:140970$6570_Y +end +attribute \src "libresoc.v:141363.1-141392.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" +attribute \generator "nMigen" +module \lenexp + attribute \src "libresoc.v:141387.17-141387.101" + wire width 64 $extend$libresoc.v:141387$6576_Y + attribute \src "libresoc.v:141387.17-141387.101" + wire width 64 $pos$libresoc.v:141387$6577_Y + attribute \src "libresoc.v:141384.17-141384.111" + wire width 20 $sshl$libresoc.v:141384$6573_Y + attribute \src "libresoc.v:141386.17-141386.113" + wire width 32 $sshl$libresoc.v:141386$6575_Y + attribute \src "libresoc.v:141385.17-141385.107" + wire width 21 $sub$libresoc.v:141385$6574_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 20 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 64 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 32 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" + wire width 4 input 1 \addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" + wire width 17 \binlen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" + wire width 4 input 4 \len_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" + wire width 64 output 2 \lexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" + wire width 176 output 3 \rexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $extend$libresoc.v:141387$6576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$7 + connect \Y $extend$libresoc.v:141387$6576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $pos$libresoc.v:141387$6577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:141387$6576_Y + connect \Y $pos$libresoc.v:141387$6577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sshl $sshl$libresoc.v:141384$6573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 20 + connect \A 5'00001 + connect \B \len_i + connect \Y $sshl$libresoc.v:141384$6573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $sshl $sshl$libresoc.v:141386$6575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 17 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 32 + connect \A \binlen + connect \B \addr_i + connect \Y $sshl$libresoc.v:141386$6575_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sub $sub$libresoc.v:141385$6574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 21 + connect \A \$2 + connect \B 1'1 + connect \Y $sub$libresoc.v:141385$6574_Y + end + connect \$2 $sshl$libresoc.v:141384$6573_Y + connect \$4 $sub$libresoc.v:141385$6574_Y + connect \$7 $sshl$libresoc.v:141386$6575_Y + connect \$6 $pos$libresoc.v:141387$6577_Y + connect \$1 \$4 + connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } + connect \lexp_o \$6 + connect \binlen \$4 [16:0] +end +attribute \src "libresoc.v:141396.1-141454.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" +attribute \generator "nMigen" +module \lod_l + attribute \src "libresoc.v:141397.7-141397.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:141442.3-141450.6" + wire $0\q_int$next[0:0]$6588 + attribute \src "libresoc.v:141440.3-141441.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:141442.3-141450.6" + wire $1\q_int$next[0:0]$6589 + attribute \src "libresoc.v:141419.7-141419.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:141432.17-141432.96" + wire $and$libresoc.v:141432$6578_Y + attribute \src "libresoc.v:141437.17-141437.96" + wire $and$libresoc.v:141437$6583_Y + attribute \src "libresoc.v:141434.18-141434.93" + wire $not$libresoc.v:141434$6580_Y + attribute \src "libresoc.v:141436.17-141436.92" + wire $not$libresoc.v:141436$6582_Y + attribute \src "libresoc.v:141439.17-141439.92" + wire $not$libresoc.v:141439$6585_Y + attribute \src "libresoc.v:141433.18-141433.98" + wire $or$libresoc.v:141433$6579_Y + attribute \src "libresoc.v:141435.18-141435.99" + wire $or$libresoc.v:141435$6581_Y + attribute \src "libresoc.v:141438.17-141438.97" + wire $or$libresoc.v:141438$6584_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:141397.7-141397.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \q_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire output 4 \qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:141432$6578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:141432$6578_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:141437$6583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:141437$6583_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:141434$6580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \Y $not$libresoc.v:141434$6580_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:141436$6582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $not$libresoc.v:141436$6582_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:141439$6585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $not$libresoc.v:141439$6585_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:141433$6579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_lod + connect \Y $or$libresoc.v:141433$6579_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:141435$6581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \B \q_int + connect \Y $or$libresoc.v:141435$6581_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:141438$6584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_lod + connect \Y $or$libresoc.v:141438$6584_Y + end + attribute \src "libresoc.v:141397.7-141397.20" + process $proc$libresoc.v:141397$6590 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:141419.7-141419.19" + process $proc$libresoc.v:141419$6591 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:141440.3-141441.27" + process $proc$libresoc.v:141440$6586 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:141442.3-141450.6" + process $proc$libresoc.v:141442$6587 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$6588 $1\q_int$next[0:0]$6589 + attribute \src "libresoc.v:141443.5-141443.29" + switch \initial + attribute \src "libresoc.v:141443.9-141443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$6589 1'0 + case + assign $1\q_int$next[0:0]$6589 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$6588 + end + connect \$9 $and$libresoc.v:141432$6578_Y + connect \$11 $or$libresoc.v:141433$6579_Y + connect \$13 $not$libresoc.v:141434$6580_Y + connect \$15 $or$libresoc.v:141435$6581_Y + connect \$1 $not$libresoc.v:141436$6582_Y + connect \$3 $and$libresoc.v:141437$6583_Y + connect \$5 $or$libresoc.v:141438$6584_Y + connect \$7 $not$libresoc.v:141439$6585_Y + connect \qlq_lod \$15 + connect \qn_lod \$13 + connect \q_lod \$11 +end +attribute \src "libresoc.v:141458.1-142574.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" +attribute \generator "nMigen" +module \logical0 + attribute \src "libresoc.v:142199.3-142200.24" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:142197.3-142198.44" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:142504.3-142512.6" + wire $0\alu_l_r_alu$next[0:0]$6792 + attribute \src "libresoc.v:142121.3-142122.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6721 + attribute \src "libresoc.v:142171.3-142172.83" + wire width 4 $0\alu_logical0_logical_op__data_len[3:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 13 $0\alu_logical0_logical_op__fn_unit$next[12:0]$6722 + attribute \src "libresoc.v:142141.3-142142.81" + wire width 13 $0\alu_logical0_logical_op__fn_unit[12:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6723 + attribute \src "libresoc.v:142143.3-142144.95" + wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6724 + attribute \src "libresoc.v:142145.3-142146.91" + wire $0\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6725 + attribute \src "libresoc.v:142159.3-142160.89" + wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6726 + attribute \src "libresoc.v:142173.3-142174.75" + wire width 32 $0\alu_logical0_logical_op__insn[31:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6727 + attribute \src "libresoc.v:142139.3-142140.85" + wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6728 + attribute \src "libresoc.v:142155.3-142156.85" + wire $0\alu_logical0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6729 + attribute \src "libresoc.v:142161.3-142162.87" + wire $0\alu_logical0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6730 + attribute \src "libresoc.v:142167.3-142168.83" + wire $0\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6731 + attribute \src "libresoc.v:142169.3-142170.85" + wire $0\alu_logical0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6732 + attribute \src "libresoc.v:142151.3-142152.79" + wire $0\alu_logical0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6733 + attribute \src "libresoc.v:142153.3-142154.79" + wire $0\alu_logical0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6734 + attribute \src "libresoc.v:142165.3-142166.91" + wire $0\alu_logical0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6735 + attribute \src "libresoc.v:142149.3-142150.79" + wire $0\alu_logical0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6736 + attribute \src "libresoc.v:142147.3-142148.79" + wire $0\alu_logical0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6737 + attribute \src "libresoc.v:142163.3-142164.85" + wire $0\alu_logical0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6738 + attribute \src "libresoc.v:142157.3-142158.79" + wire $0\alu_logical0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:142495.3-142503.6" + wire $0\alui_l_r_alui$next[0:0]$6789 + attribute \src "libresoc.v:142123.3-142124.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:142421.3-142442.6" + wire width 64 $0\data_r0__o$next[63:0]$6764 + attribute \src "libresoc.v:142135.3-142136.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:142421.3-142442.6" + wire $0\data_r0__o_ok$next[0:0]$6765 + attribute \src "libresoc.v:142137.3-142138.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:142443.3-142464.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6772 + attribute \src "libresoc.v:142131.3-142132.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:142443.3-142464.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6773 + attribute \src "libresoc.v:142133.3-142134.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:142513.3-142522.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:142523.3-142532.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:141459.7-141459.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:142337.3-142345.6" + wire $0\opc_l_r_opc$next[0:0]$6706 + attribute \src "libresoc.v:142183.3-142184.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:142328.3-142336.6" + wire $0\opc_l_s_opc$next[0:0]$6703 + attribute \src "libresoc.v:142185.3-142186.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:142533.3-142541.6" + wire width 2 $0\prev_wr_go$next[1:0]$6797 + attribute \src "libresoc.v:142195.3-142196.37" + wire width 2 $0\prev_wr_go[1:0] + attribute \src "libresoc.v:142282.3-142291.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:142373.3-142381.6" + wire width 2 $0\req_l_r_req$next[1:0]$6718 + attribute \src "libresoc.v:142175.3-142176.39" + wire width 2 $0\req_l_r_req[1:0] + attribute \src "libresoc.v:142364.3-142372.6" + wire width 2 $0\req_l_s_req$next[1:0]$6715 + attribute \src "libresoc.v:142177.3-142178.39" + wire width 2 $0\req_l_s_req[1:0] + attribute \src "libresoc.v:142301.3-142309.6" + wire $0\rok_l_r_rdok$next[0:0]$6694 + attribute \src "libresoc.v:142191.3-142192.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:142292.3-142300.6" + wire $0\rok_l_s_rdok$next[0:0]$6691 + attribute \src "libresoc.v:142193.3-142194.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:142319.3-142327.6" + wire $0\rst_l_r_rst$next[0:0]$6700 + attribute \src "libresoc.v:142187.3-142188.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:142310.3-142318.6" + wire $0\rst_l_s_rst$next[0:0]$6697 + attribute \src "libresoc.v:142189.3-142190.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:142355.3-142363.6" + wire width 3 $0\src_l_r_src$next[2:0]$6712 + attribute \src "libresoc.v:142179.3-142180.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:142346.3-142354.6" + wire width 3 $0\src_l_s_src$next[2:0]$6709 + attribute \src "libresoc.v:142181.3-142182.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:142465.3-142474.6" + wire width 64 $0\src_r0$next[63:0]$6780 + attribute \src "libresoc.v:142129.3-142130.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:142475.3-142484.6" + wire width 64 $0\src_r1$next[63:0]$6783 + attribute \src "libresoc.v:142127.3-142128.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:142485.3-142494.6" + wire $0\src_r2$next[0:0]$6786 + attribute \src "libresoc.v:142125.3-142126.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:141577.7-141577.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:141587.7-141587.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:142504.3-142512.6" + wire $1\alu_l_r_alu$next[0:0]$6793 + attribute \src "libresoc.v:141595.7-141595.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6739 + attribute \src "libresoc.v:141603.13-141603.53" + wire width 4 $1\alu_logical0_logical_op__data_len[3:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 13 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6740 + attribute \src "libresoc.v:141621.14-141621.57" + wire width 13 $1\alu_logical0_logical_op__fn_unit[12:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6741 + attribute \src "libresoc.v:141625.14-141625.76" + wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6742 + attribute \src "libresoc.v:141629.7-141629.51" + wire $1\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6743 + attribute \src "libresoc.v:141637.13-141637.56" + wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6744 + attribute \src "libresoc.v:141641.14-141641.51" + wire width 32 $1\alu_logical0_logical_op__insn[31:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6745 + attribute \src "libresoc.v:141719.13-141719.55" + wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6746 + attribute \src "libresoc.v:141723.7-141723.48" + wire $1\alu_logical0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6747 + attribute \src "libresoc.v:141727.7-141727.49" + wire $1\alu_logical0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6748 + attribute \src "libresoc.v:141731.7-141731.47" + wire $1\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6749 + attribute \src "libresoc.v:141735.7-141735.48" + wire $1\alu_logical0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:142382.3-142420.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6750 + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - wire width 3 \$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - wire width 2 \$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - wire width 3 \$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - wire width 3 \$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - wire width 3 \$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - wire \$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - wire \$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - wire \$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - wire \$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - wire \$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - wire \$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" - wire \addr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - wire width 64 \addr_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \adr_l_q_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \adr_l_r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \adr_l_r_adr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \adr_l_s_adr + wire width 64 \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire \all_rd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \alu_done_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \alu_l_q_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" - wire width 64 \alu_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" - wire \alu_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" - wire \alu_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" - wire \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 3 \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 4 \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 23 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 22 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 26 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 25 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 24 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 5 \cu_st__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 2 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 31 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 30 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 2 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 33 \ea - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire width 64 \ea_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire width 64 \ea_r$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$185 - attribute \src "libresoc.v:143751.7-143751.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" - wire \ld_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" - wire \ld_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" - wire width 64 \ldd_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" - wire width 64 \ldd_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" - wire width 64 \lddata_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire width 64 \ldo_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire width 64 \ldo_r$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 96 output 38 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 96 \ldst_port0_addr_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 39 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \ldst_port0_addr_i_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 48 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire input 34 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 37 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 40 \ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 41 \ldst_port0_exc_$signal$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 42 \ldst_port0_exc_$signal$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 43 \ldst_port0_exc_$signal$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 44 \ldst_port0_exc_$signal$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 45 \ldst_port0_exc_$signal$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 46 \ldst_port0_exc_$signal$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 47 \ldst_port0_exc_$signal$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire output 35 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire output 36 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 49 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 50 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 51 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 52 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" - wire \load_mem_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \lod_l_qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \lod_l_r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \lod_l_s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \lsd_l_q_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \lsd_l_r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \lsd_l_r_lsd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \lsd_l_s_lsd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 32 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" - wire \op_is_ld - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" - wire \op_is_st - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \opc_l_s_opc$next + wire width 4 \alu_logical0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \oper_i_ldst_ldst0__byte_reverse + wire width 4 \alu_logical0_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \oper_i_ldst_ldst0__data_len + wire width 4 \alu_logical0_logical_op__data_len$next attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -230200,13 +230647,29 @@ module \ldst0 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 7 \oper_i_ldst_ldst0__fn_unit + wire width 13 \alu_logical0_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \oper_i_ldst_ldst0__imm_data__data + wire width 13 \alu_logical0_logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_ldst_ldst0__imm_data__ok + wire width 64 \alu_logical0_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 21 \oper_i_ldst_ldst0__insn + wire width 64 \alu_logical0_logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_logical0_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_logical0_logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_logical0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_logical0_logical_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -230282,38 +230745,145 @@ module \ldst0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 6 \oper_i_ldst_ldst0__insn_type + wire width 7 \alu_logical0_logical_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_ldst_ldst0__is_32bit + wire width 7 \alu_logical0_logical_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_ldst_ldst0__is_signed - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" + wire \alu_logical0_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 20 \oper_i_ldst_ldst0__ldst_mode + wire \alu_logical0_logical_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_ldst_ldst0__oe__oe + wire \alu_logical0_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_ldst_ldst0__oe__ok + wire \alu_logical0_logical_op__invert_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_ldst_ldst0__rc__ok + wire \alu_logical0_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_ldst_ldst0__rc__rc + wire \alu_logical0_logical_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \oper_i_ldst_ldst0__sign_extend + wire \alu_logical0_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_ldst_ldst0__zero_a + wire \alu_logical0_logical_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__byte_reverse + wire \alu_logical0_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__byte_reverse$next + wire \alu_logical0_logical_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len + wire \alu_logical0_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len$next + wire \alu_logical0_logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \alu_logical0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \alu_logical0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_logical0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \alu_logical0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \alu_logical0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_logical0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_logical0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_logical0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 2 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 21 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 20 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 24 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 23 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 22 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 2 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 33 \dest2_o + attribute \src "libresoc.v:141459.7-141459.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 18 \oper_i_alu_logical0__data_len attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -230329,21 +230899,19 @@ module \ldst0 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \oper_r__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \oper_r__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__data$next + wire width 13 input 3 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__imm_data__ok + wire width 64 input 4 \oper_i_alu_logical0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__imm_data__ok$next + wire input 5 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn + wire width 2 input 12 \oper_i_alu_logical0__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn$next + wire width 32 input 19 \oper_i_alu_logical0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -230419,90 +230987,77 @@ module \ldst0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__is_signed$next - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__ldst_mode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__oe__oe + wire width 7 input 2 \oper_i_alu_logical0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__oe__oe$next + wire input 10 \oper_i_alu_logical0__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__oe__ok + wire input 13 \oper_i_alu_logical0__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__oe__ok$next + wire input 16 \oper_i_alu_logical0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__rc__ok + wire input 17 \oper_i_alu_logical0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__rc__ok$next + wire input 8 \oper_i_alu_logical0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__rc__rc + wire input 9 \oper_i_alu_logical0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__rc__rc$next + wire input 15 \oper_i_alu_logical0__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__sign_extend + wire input 7 \oper_i_alu_logical0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__sign_extend$next + wire input 6 \oper_i_alu_logical0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__zero_a + wire input 14 \oper_i_alu_logical0__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" - wire \p_st_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" - wire \p_st_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" - wire \rd_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" - wire \rda_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" - wire \reset_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" - wire \reset_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" - wire \reset_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" + wire input 11 \oper_i_alu_logical0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 2 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 2 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 2 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 2 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 2 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 2 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 2 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" - wire \reset_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" - wire \reset_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" - wire \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" - wire width 64 \revnorev + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 2 \reset_w attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \rst_l_q_rst + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rst_l_r_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 27 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" - wire width 64 \src1_or_z + wire width 64 input 25 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 28 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - wire width 64 \src2_or_imm + wire width 64 input 26 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 29 \src3_i + wire input 27 \src3_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire width 3 \src_l_q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" @@ -230513,430 +231068,327 @@ module \ldst0 wire width 3 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm$80 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:111" - wire \st_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" - wire width 64 \stdata_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \sto_l_q_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \sto_l_r_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \sto_l_r_sto$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \sto_l_s_sto - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:115" - wire \stwd_mem_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \upd_l_q_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \upd_l_r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \upd_l_r_upd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \upd_l_s_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \upd_l_s_upd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" - wire \wr_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \wri_l_q_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \wri_l_r_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \wri_l_r_wri$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \wri_l_s_wri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" - cell $add $add$libresoc.v:144574$6324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \src1_or_z - connect \B \src2_or_imm - connect \Y $add$libresoc.v:144574$6324_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $and $and$libresoc.v:144497$6244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \B \$98 - connect \Y $and$libresoc.v:144497$6244_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:144498$6245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \B \adr_l_q_adr - connect \Y $and$libresoc.v:144498$6245_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:144499$6246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:142064$6592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$102 - connect \B \cu_busy_o - connect \Y $and$libresoc.v:144499$6246_Y + connect \A \$1 + connect \B \$3 + connect \Y $and$libresoc.v:142064$6592_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:144500$6247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:142065$6593 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sto_l_q_sto - connect \B \cu_busy_o - connect \Y $and$libresoc.v:144500$6247_Y + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$93 + connect \B { 1'1 \$97 \$95 } + connect \Y $and$libresoc.v:142065$6593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:144501$6248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:142067$6595 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$106 - connect \B \rd_done - connect \Y $and$libresoc.v:144501$6248_Y + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$99 + connect \B \$101 + connect \Y $and$libresoc.v:142067$6595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:144503$6250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:142068$6596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$108 - connect \B \op_is_st - connect \Y $and$libresoc.v:144503$6250_Y + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:142068$6596_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $and $and$libresoc.v:144504$6251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:142069$6597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$110 + connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:144504$6251_Y + connect \Y $and$libresoc.v:142069$6597_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:144505$6252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:142070$6598 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rd_done - connect \B \wri_l_q_wri - connect \Y $and$libresoc.v:144505$6252_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \req_l_q_req + connect \B { \$105 \$107 } + connect \Y $and$libresoc.v:142070$6598_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:144506$6253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:142071$6599 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$114 - connect \B \cu_busy_o - connect \Y $and$libresoc.v:144506$6253_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$109 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:142071$6599_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:144507$6254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:142072$6600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$116 - connect \B \lod_l_qn_lod - connect \Y $and$libresoc.v:144507$6254_Y + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:142072$6600_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:144508$6255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:142073$6601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$118 - connect \B \op_is_ld - connect \Y $and$libresoc.v:144508$6255_Y + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:142073$6601_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:144509$6256 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:142075$6603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$120 - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:144509$6256_Y + connect \A \all_rd + connect \B \$11 + connect \Y $and$libresoc.v:142075$6603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:144510$6257 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:142077$6605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \upd_l_q_upd - connect \B \cu_busy_o - connect \Y $and$libresoc.v:144510$6257_Y + connect \A \alu_done + connect \B \$15 + connect \Y $and$libresoc.v:142077$6605_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:144512$6259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and 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\B \cu_busy_o - connect \Y $and$libresoc.v:144519$6266_Y + connect \A \cu_busy_o + connect \B \$21 + connect \Y $and$libresoc.v:142084$6612_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:144520$6267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:142089$6617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$140 - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:144520$6267_Y + connect \A \wr_any + connect \B \$37 + connect \Y $and$libresoc.v:142089$6617_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:144525$6272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:142090$6618 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$142 - connect \B \$144 - connect \Y $and$libresoc.v:144525$6272_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:142090$6618_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $and $and$libresoc.v:144527$6274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:142092$6620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$150 - connect \B \$152 - connect \Y $and$libresoc.v:144527$6274_Y + connect \A \$39 + connect \B \$43 + connect \Y $and$libresoc.v:142092$6620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $and $and$libresoc.v:144530$6277 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:142095$6623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_reset - connect \B \$158 - connect \Y $and$libresoc.v:144530$6277_Y + connect \A \$47 + connect \B \alu_logical0_n_ready_i + connect \Y $and$libresoc.v:142095$6623_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - cell $and $and$libresoc.v:144532$6279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:142096$6624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$162 - connect \B \cu_wr__go_i [1] - connect \Y $and$libresoc.v:144532$6279_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - cell $and $and$libresoc.v:144535$6282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \B { 1'0 \$167 \op_is_ld } - connect \Y $and$libresoc.v:144535$6282_Y + connect \A \$49 + connect \B \alu_logical0_n_valid_o + connect \Y $and$libresoc.v:142096$6624_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $and$libresoc.v:144536$6283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:142097$6625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \op_is_ld + connect \A \$51 connect \B \cu_busy_o - connect \Y $and$libresoc.v:144536$6283_Y + connect \Y $and$libresoc.v:142097$6625_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" - cell $and $and$libresoc.v:144537$6284 + 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connect \Y $and$libresoc.v:144551$6301_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" - cell $and $and$libresoc.v:144552$6302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \op_is_st - connect \B \cu_st__go_i - connect \Y $and$libresoc.v:144552$6302_Y + connect \Y $and$libresoc.v:142102$6630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:144554$6304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:142103$6631 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_ok - connect \B \$30 - connect \Y $and$libresoc.v:144554$6304_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:142103$6631_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:144556$6306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:142106$6634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$32 - connect \B \$34 - connect \Y $and$libresoc.v:144556$6306_Y + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:142106$6634_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:144559$6309 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:142107$6635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$39 - connect \B \$41 - connect \Y $and$libresoc.v:144559$6309_Y + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:142107$6635_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:144563$6313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:142116$6644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$47 - connect \B \$49 - connect \Y $and$libresoc.v:144563$6313_Y + connect \A \alu_logical0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:142116$6644_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $and $and$libresoc.v:144566$6316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:142117$6645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \addr_ok - connect \B \op_is_st - connect \Y $and$libresoc.v:144566$6316_Y + connect \A \alu_logical0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:142117$6645_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:144575$6325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:142118$6646 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -230944,378 +231396,148 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:144575$6325_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:144577$6327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A \$76 - connect \B \$78 - connect \Y $and$libresoc.v:144577$6327_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:144579$6329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$80 - connect \B \$82 - connect \Y $and$libresoc.v:144579$6329_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:144580$6330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src_l_q_src [2] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:144580$6330_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:144581$6331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$86 - connect \B \op_is_st - connect \Y $and$libresoc.v:144581$6331_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $and$libresoc.v:144586$6336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \$92 - connect \Y $and$libresoc.v:144586$6336_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:144511$6258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $eq$libresoc.v:144511$6258_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:144531$6278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $eq$libresoc.v:144531$6278_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:144533$6280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $eq$libresoc.v:144533$6280_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - cell $eq $eq$libresoc.v:144544$6293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__data_len - connect \B 2'10 - connect \Y $eq$libresoc.v:144544$6293_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$libresoc.v:144549$6299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \oper_r__insn_type - connect \B 7'0100110 - connect \Y $eq$libresoc.v:144549$6299_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:144550$6300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \oper_r__insn_type - connect \B 7'0100101 - connect \Y $eq$libresoc.v:144550$6300_Y + connect \Y $and$libresoc.v:142118$6646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:144558$6308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:142091$6619 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $eq$libresoc.v:144558$6308_Y + connect \A \$41 + connect \B 1'0 + connect \Y $eq$libresoc.v:142091$6619_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:144562$6312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:142093$6621 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $eq$libresoc.v:144562$6312_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $extend$libresoc.v:144538$6285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 96 - connect \A \addr_r - connect \Y $extend$libresoc.v:144538$6285_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - cell $pos $extend$libresoc.v:144540$6288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$libresoc.v:144540$6288_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - cell $pos $extend$libresoc.v:144545$6294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A \src_r2 [7:0] - connect \Y $extend$libresoc.v:144545$6294_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $not $not$libresoc.v:144523$6270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$147 - connect \Y $not$libresoc.v:144523$6270_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $not $not$libresoc.v:144528$6275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:144528$6275_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:144553$6303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \Y $not$libresoc.v:144553$6303_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:144555$6305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rda_any - connect \Y $not$libresoc.v:144555$6305_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:144557$6307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:144557$6307_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:144561$6311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:144561$6311_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:144576$6326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$libresoc.v:144576$6326_Y + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:142093$6621_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:144578$6328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:142066$6594 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:144578$6328_Y + connect \Y $not$libresoc.v:142066$6594_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $not $not$libresoc.v:144585$6335 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:142074$6602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$93 - connect \Y $not$libresoc.v:144585$6335_Y + connect \A \all_rd_dly + connect \Y $not$libresoc.v:142074$6602_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $not $not$libresoc.v:144587$6337 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:142076$6604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_rd__rel_o [2] - connect \Y $not$libresoc.v:144587$6337_Y + connect \A \alu_done_dly + connect \Y $not$libresoc.v:142076$6604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$libresoc.v:144502$6249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:142080$6608 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_done_o - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:144502$6249_Y + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:142080$6608_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$libresoc.v:144513$6260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:142083$6611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:144513$6260_Y + connect \A \$22 + connect \Y $not$libresoc.v:142083$6611_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:144516$6263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:142088$6616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_st__go_i - connect \B \p_st_go - connect \Y $or$libresoc.v:144516$6263_Y + connect \A \alu_logical0_n_ready_i + connect \Y $not$libresoc.v:142088$6616_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:144517$6264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:142094$6622 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$134 - connect \B \cu_wr__go_i [0] - connect \Y $or$libresoc.v:144517$6264_Y + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:142094$6622_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:144518$6265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:142119$6647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$136 - connect \B \cu_wr__go_i [1] - connect \Y $or$libresoc.v:144518$6265_Y + connect \A \alu_logical0_logical_op__zero_a + connect \Y $not$libresoc.v:142119$6647_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:144521$6268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:142120$6648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o - connect \B \cu_wr__rel_o [0] - connect \Y $or$libresoc.v:144521$6268_Y + connect \A \alu_logical0_logical_op__imm_data__ok + connect \Y $not$libresoc.v:142120$6648_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:144522$6269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:142087$6615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$145 - connect \B \cu_wr__rel_o [1] - connect \Y $or$libresoc.v:144522$6269_Y + connect \A \$31 + connect \B \$33 + connect \Y $or$libresoc.v:142087$6615_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$libresoc.v:144524$6271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:142098$6626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] + connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:144524$6271_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $or $or$libresoc.v:144526$6273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lod_l_qn_lod - connect \B \op_is_st - connect \Y $or$libresoc.v:144526$6273_Y + connect \Y $or$libresoc.v:142098$6626_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $or $or$libresoc.v:144529$6276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:142099$6627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$156 - connect \B \op_is_ld - connect \Y $or$libresoc.v:144529$6276_Y + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:142099$6627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$libresoc.v:144534$6281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:142100$6628 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__go_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:144534$6281_Y + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:142100$6628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$libresoc.v:144542$6291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:142101$6629 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -231323,218 +231545,121 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:144542$6291_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - cell $or $or$libresoc.v:144548$6298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_ad__go_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:144548$6298_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:144560$6310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_reset - connect \B \$43 - connect \Y $or$libresoc.v:144560$6310_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:144564$6314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_reset - connect \B \$51 - connect \Y $or$libresoc.v:144564$6314_Y + connect \Y $or$libresoc.v:142101$6629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" - cell $or $or$libresoc.v:144565$6315 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:142104$6632 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 connect \A \reset_w - connect \B { \$45 \$53 } - connect \Y $or$libresoc.v:144565$6315_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - cell $or $or$libresoc.v:144567$6317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \reset_s - connect \B \p_st_go - connect \Y $or$libresoc.v:144567$6317_Y + connect \B \prev_wr_go + connect \Y $or$libresoc.v:142104$6632_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:144568$6318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:142105$6633 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \reset_s - connect \B \p_st_go - connect \Y $or$libresoc.v:144568$6318_Y + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$4 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:142105$6633_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:144569$6319 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:142111$6639 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$61 - connect \B \ld_ok - connect \Y $or$libresoc.v:144569$6319_Y + connect \A \$6 + connect \Y $reduce_and$libresoc.v:142111$6639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$libresoc.v:144582$6332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:142082$6610 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:144582$6332_Y + connect \A \$25 + connect \Y $reduce_or$libresoc.v:142082$6610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $or $or$libresoc.v:144583$6333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:142085$6613 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \cu_rd__go_i [0] - connect \B \cu_rd__go_i [1] - connect \Y $or$libresoc.v:144583$6333_Y + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:142085$6613_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $or $or$libresoc.v:144584$6334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:142086$6614 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \cu_rd__rel_o [0] - connect \B \cu_rd__rel_o [1] - connect \Y $or$libresoc.v:144584$6334_Y + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:142086$6614_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $pos$libresoc.v:144538$6286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 96 - parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:144538$6285_Y - connect \Y $pos$libresoc.v:144538$6286_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:142108$6636 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$libresoc.v:142108$6636_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - cell $pos $pos$libresoc.v:144540$6289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:144540$6288_Y - connect \Y $pos$libresoc.v:144540$6289_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - cell $pos $pos$libresoc.v:144541$6290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:144541$6290_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - cell $pos $pos$libresoc.v:144543$6292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:144543$6292_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - cell $pos $pos$libresoc.v:144545$6295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:144545$6294_Y - connect \Y $pos$libresoc.v:144545$6295_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - cell $pos $pos$libresoc.v:144546$6296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:144546$6296_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:142109$6637 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$libresoc.v:142109$6637_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" - cell $pos $pos$libresoc.v:144547$6297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:144547$6297_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:142110$6638 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:142110$6638_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:144570$6320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:142112$6640 parameter \WIDTH 64 - connect \A \ldo_r - connect \B \ldd_o - connect \S \ld_ok - connect \Y $ternary$libresoc.v:144570$6320_Y + connect \A \src2_i + connect \B \alu_logical0_logical_op__imm_data__data + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:142112$6640_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:144571$6321 - parameter \WIDTH 64 - connect \A \ea_r - connect \B \alu_o - connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:144571$6321_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" - cell $mux $ternary$libresoc.v:144572$6322 + cell $mux $ternary$libresoc.v:142113$6641 parameter \WIDTH 64 connect \A \src_r0 - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:144572$6322_Y + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:142113$6641_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" - cell $mux $ternary$libresoc.v:144573$6323 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:142114$6642 parameter \WIDTH 64 connect \A \src_r1 - connect \B \oper_r__imm_data__data - connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:144573$6323_Y + connect \B \src_or_imm$80 + connect \S \src_sel$77 + connect \Y $ternary$libresoc.v:142114$6642_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:144658.9-144664.4" - cell \adr_l \adr_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_adr \adr_l_q_adr - connect \r_adr \adr_l_r_adr - connect \s_adr \adr_l_s_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:142115$6643 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:142115$6643_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:144665.15-144671.4" - cell \alu_l$128 \alu_l + attribute \src "libresoc.v:142201.14-142207.4" + cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu @@ -231542,26 +231667,52 @@ module \ldst0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:144672.9-144678.4" - cell \lod_l \lod_l + attribute \src "libresoc.v:142208.16-142240.4" + cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \qn_lod \lod_l_qn_lod - connect \r_lod \lod_l_r_lod - connect \s_lod \lod_l_s_lod + connect \cr_a \alu_logical0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_logical0_logical_op__data_len + connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_logical0_logical_op__input_carry + connect \logical_op__insn \alu_logical0_logical_op__insn + connect \logical_op__insn_type \alu_logical0_logical_op__insn_type + connect \logical_op__invert_in \alu_logical0_logical_op__invert_in + connect \logical_op__invert_out \alu_logical0_logical_op__invert_out + connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit + connect \logical_op__is_signed \alu_logical0_logical_op__is_signed + connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok + connect \logical_op__output_carry \alu_logical0_logical_op__output_carry + connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_logical0_logical_op__zero_a + connect \n_ready_i \alu_logical0_n_ready_i + connect \n_valid_o \alu_logical0_n_valid_o + connect \o \alu_logical0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_logical0_p_ready_o + connect \p_valid_i \alu_logical0_p_valid_i + connect \ra \alu_logical0_ra + connect \rb \alu_logical0_rb + connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:144679.9-144685.4" - cell \lsd_l \lsd_l + attribute \src "libresoc.v:142241.15-142247.4" + cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \q_lsd \lsd_l_q_lsd - connect \r_lsd \lsd_l_r_lsd - connect \s_lsd \lsd_l_s_lsd + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:144686.15-144692.4" - cell \opc_l$126 \opc_l + attribute \src "libresoc.v:142248.14-142254.4" + cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_opc \opc_l_q_opc @@ -231569,614 +231720,679 @@ module \ldst0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:144693.15-144699.4" - cell \rst_l$129 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rst \rst_l_q_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:144700.15-144706.4" - cell \src_l$127 \src_l + attribute \src "libresoc.v:142255.14-142261.4" + cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:144707.9-144713.4" - cell \sto_l \sto_l + attribute \src "libresoc.v:142262.14-142268.4" + cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \q_sto \sto_l_q_sto - connect \r_sto \sto_l_r_sto - connect \s_sto \sto_l_s_sto + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:144714.9-144720.4" - cell \upd_l \upd_l + attribute \src "libresoc.v:142269.14-142274.4" + cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \q_upd \upd_l_q_upd - connect \r_upd \upd_l_r_upd - connect \s_upd \upd_l_s_upd + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:144721.9-144727.4" - cell \wri_l \wri_l + attribute \src "libresoc.v:142275.14-142281.4" + cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \q_wri \wri_l_q_wri - connect \r_wri \wri_l_r_wri - connect \s_wri \wri_l_s_wri + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src end - attribute \src "libresoc.v:143751.7-143751.20" - process $proc$libresoc.v:143751$6486 + attribute \src "libresoc.v:141459.7-141459.20" + process $proc$libresoc.v:141459$6799 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143947.7-143947.25" - process $proc$libresoc.v:143947$6487 + attribute \src "libresoc.v:141577.7-141577.24" + process $proc$libresoc.v:141577$6800 assign { } { } - assign $1\adr_l_r_adr[0:0] 1'1 + assign $1\all_rd_dly[0:0] 1'0 sync always sync init - update \adr_l_r_adr $1\adr_l_r_adr[0:0] + update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:143961.7-143961.20" - process $proc$libresoc.v:143961$6488 + attribute \src "libresoc.v:141587.7-141587.26" + process $proc$libresoc.v:141587$6801 assign { } { } - assign $1\alu_ok[0:0] 1'0 + assign $1\alu_done_dly[0:0] 1'0 sync always sync init - update \alu_ok $1\alu_ok[0:0] + update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:144007.14-144007.41" - process $proc$libresoc.v:144007$6489 + attribute \src "libresoc.v:141595.7-141595.25" + process $proc$libresoc.v:141595$6802 assign { } { } - assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init - update \ea_r $1\ea_r[63:0] + update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:144037.14-144037.42" - process $proc$libresoc.v:144037$6490 + attribute \src "libresoc.v:141603.13-141603.53" + process $proc$libresoc.v:141603$6803 assign { } { } - assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init - update \ldo_r $1\ldo_r[63:0] + update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:144042.14-144042.62" - process $proc$libresoc.v:144042$6491 + attribute \src "libresoc.v:141621.14-141621.57" + process $proc$libresoc.v:141621$6804 assign { } { } - assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_logical0_logical_op__fn_unit[12:0] 13'0000000000000 sync always sync init - update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] + update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[12:0] end - attribute \src "libresoc.v:144047.7-144047.34" - process $proc$libresoc.v:144047$6492 + attribute \src "libresoc.v:141625.14-141625.76" + process $proc$libresoc.v:141625$6805 assign { } { } - assign $1\ldst_port0_addr_i_ok[0:0] 1'0 + assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] + update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:144096.7-144096.25" - process $proc$libresoc.v:144096$6493 + attribute \src "libresoc.v:141629.7-141629.51" + process $proc$libresoc.v:141629$6806 assign { } { } - assign $1\lsd_l_r_lsd[0:0] 1'1 + assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init - update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] + update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:144110.7-144110.25" - process $proc$libresoc.v:144110$6494 + attribute \src "libresoc.v:141637.13-141637.56" + process $proc$libresoc.v:141637$6807 assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 + assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] + update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:144114.7-144114.25" - process $proc$libresoc.v:144114$6495 + attribute \src "libresoc.v:141641.14-141641.51" + process $proc$libresoc.v:141641$6808 assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 + assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] + update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:144243.7-144243.34" - process $proc$libresoc.v:144243$6496 + attribute \src "libresoc.v:141719.13-141719.55" + process $proc$libresoc.v:141719$6809 assign { } { } - assign $1\oper_r__byte_reverse[0:0] 1'0 + assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init - update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] + update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:144247.13-144247.36" - process $proc$libresoc.v:144247$6497 + attribute \src "libresoc.v:141723.7-141723.48" + process $proc$libresoc.v:141723$6810 assign { } { } - assign $1\oper_r__data_len[3:0] 4'0000 + assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init - update \oper_r__data_len $1\oper_r__data_len[3:0] + update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:144265.14-144265.40" - process $proc$libresoc.v:144265$6498 + attribute \src "libresoc.v:141727.7-141727.49" + process $proc$libresoc.v:141727$6811 assign { } { } - assign $1\oper_r__fn_unit[12:0] 13'0000000000000 + assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init - update \oper_r__fn_unit $1\oper_r__fn_unit[12:0] + update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:144269.14-144269.59" - process $proc$libresoc.v:144269$6499 + attribute \src "libresoc.v:141731.7-141731.47" + process $proc$libresoc.v:141731$6812 assign { } { } - assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init - update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] + update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:144273.7-144273.34" - process $proc$libresoc.v:144273$6500 + attribute \src "libresoc.v:141735.7-141735.48" + process $proc$libresoc.v:141735$6813 assign { } { } - assign $1\oper_r__imm_data__ok[0:0] 1'0 + assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init - update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] + update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:144277.14-144277.34" - process $proc$libresoc.v:144277$6501 + attribute \src "libresoc.v:141739.7-141739.45" + process $proc$libresoc.v:141739$6814 assign { } { } - assign $1\oper_r__insn[31:0] 0 + assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init - update \oper_r__insn $1\oper_r__insn[31:0] + update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:144355.13-144355.38" - process $proc$libresoc.v:144355$6502 + attribute \src "libresoc.v:141743.7-141743.45" + process $proc$libresoc.v:141743$6815 assign { } { } - assign $1\oper_r__insn_type[6:0] 7'0000000 + assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init - update \oper_r__insn_type $1\oper_r__insn_type[6:0] + update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:144359.7-144359.30" - process $proc$libresoc.v:144359$6503 + attribute \src "libresoc.v:141747.7-141747.51" + process $proc$libresoc.v:141747$6816 assign { } { } - assign $1\oper_r__is_32bit[0:0] 1'0 + assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init - update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] + update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:144363.7-144363.31" - process $proc$libresoc.v:144363$6504 + attribute \src "libresoc.v:141751.7-141751.45" + process $proc$libresoc.v:141751$6817 assign { } { } - assign $1\oper_r__is_signed[0:0] 1'0 + assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init - update \oper_r__is_signed $1\oper_r__is_signed[0:0] + update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:144372.13-144372.37" - process $proc$libresoc.v:144372$6505 + attribute \src "libresoc.v:141755.7-141755.45" + process $proc$libresoc.v:141755$6818 assign { } { } - assign $1\oper_r__ldst_mode[1:0] 2'00 + assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init - update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] + update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:144376.7-144376.28" - process $proc$libresoc.v:144376$6506 + attribute \src "libresoc.v:141759.7-141759.48" + process $proc$libresoc.v:141759$6819 assign { } { } - assign $1\oper_r__oe__oe[0:0] 1'0 + assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init - update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] + update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:144380.7-144380.28" - process $proc$libresoc.v:144380$6507 + attribute \src "libresoc.v:141763.7-141763.45" + process $proc$libresoc.v:141763$6820 assign { } { } - assign $1\oper_r__oe__ok[0:0] 1'0 + assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init - update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] + update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:144384.7-144384.28" - process $proc$libresoc.v:144384$6508 + attribute \src "libresoc.v:141789.7-141789.27" + process $proc$libresoc.v:141789$6821 assign { } { } - assign $1\oper_r__rc__ok[0:0] 1'0 + assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init - update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] + update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:144388.7-144388.28" - process $proc$libresoc.v:144388$6509 + attribute \src "libresoc.v:141823.14-141823.47" + process $proc$libresoc.v:141823$6822 assign { } { } - assign $1\oper_r__rc__rc[0:0] 1'0 + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] + update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:144392.7-144392.33" - process $proc$libresoc.v:144392$6510 + attribute \src "libresoc.v:141827.7-141827.27" + process $proc$libresoc.v:141827$6823 assign { } { } - assign $1\oper_r__sign_extend[0:0] 1'0 + assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init - update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] + update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:144396.7-144396.28" - process $proc$libresoc.v:144396$6511 + attribute \src "libresoc.v:141831.13-141831.33" + process $proc$libresoc.v:141831$6824 assign { } { } - assign $1\oper_r__zero_a[0:0] 1'0 + assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init - update \oper_r__zero_a $1\oper_r__zero_a[0:0] + update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:144400.7-144400.21" - process $proc$libresoc.v:144400$6512 + attribute \src "libresoc.v:141835.7-141835.30" + process $proc$libresoc.v:141835$6825 assign { } { } - assign $1\p_st_go[0:0] 1'0 + assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init - update \p_st_go $1\p_st_go[0:0] + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:144442.13-144442.31" - process $proc$libresoc.v:144442$6513 + attribute \src "libresoc.v:141849.7-141849.25" + process $proc$libresoc.v:141849$6826 assign { } { } - assign $1\src_l_r_src[2:0] 3'111 + assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init - update \src_l_r_src $1\src_l_r_src[2:0] + update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:144446.13-144446.31" - process $proc$libresoc.v:144446$6514 + attribute \src "libresoc.v:141853.7-141853.25" + process $proc$libresoc.v:141853$6827 assign { } { } - assign $1\src_l_s_src[2:0] 3'000 + assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init - update \src_l_s_src $1\src_l_s_src[2:0] + update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:144450.14-144450.43" - process $proc$libresoc.v:144450$6515 + attribute \src "libresoc.v:141985.13-141985.30" + process $proc$libresoc.v:141985$6828 assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\prev_wr_go[1:0] 2'00 sync always sync init - update \src_r0 $1\src_r0[63:0] + update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "libresoc.v:144454.14-144454.43" - process $proc$libresoc.v:144454$6516 + attribute \src "libresoc.v:141993.13-141993.31" + process $proc$libresoc.v:141993$6829 assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\req_l_r_req[1:0] 2'11 sync always sync init - update \src_r1 $1\src_r1[63:0] + update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "libresoc.v:144458.14-144458.43" - process $proc$libresoc.v:144458$6517 + attribute \src "libresoc.v:141997.13-141997.31" + process $proc$libresoc.v:141997$6830 assign { } { } - assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\req_l_s_req[1:0] 2'00 sync always sync init - update \src_r2 $1\src_r2[63:0] + update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "libresoc.v:144468.7-144468.25" - process $proc$libresoc.v:144468$6518 + attribute \src "libresoc.v:142009.7-142009.26" + process $proc$libresoc.v:142009$6831 assign { } { } - assign $1\sto_l_r_sto[0:0] 1'1 + assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init - update \sto_l_r_sto $1\sto_l_r_sto[0:0] + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:144478.7-144478.25" - process $proc$libresoc.v:144478$6519 + attribute \src "libresoc.v:142013.7-142013.26" + process $proc$libresoc.v:142013$6832 assign { } { } - assign $1\upd_l_r_upd[0:0] 1'1 + assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init - update \upd_l_r_upd $1\upd_l_r_upd[0:0] + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:144482.7-144482.25" - process $proc$libresoc.v:144482$6520 + attribute \src "libresoc.v:142017.7-142017.25" + process $proc$libresoc.v:142017$6833 assign { } { } - assign $1\upd_l_s_upd[0:0] 1'0 + assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init - update \upd_l_s_upd $1\upd_l_s_upd[0:0] + update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:144492.7-144492.25" - process $proc$libresoc.v:144492$6521 + attribute \src "libresoc.v:142021.7-142021.25" + process $proc$libresoc.v:142021$6834 assign { } { } - assign $1\wri_l_r_wri[0:0] 1'1 + assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init - update \wri_l_r_wri $1\wri_l_r_wri[0:0] + update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:144588.3-144589.57" - process $proc$libresoc.v:144588$6338 + attribute \src "libresoc.v:142035.13-142035.31" + process $proc$libresoc.v:142035$6835 assign { } { } - assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next - sync posedge \coresync_clk - update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:144590.3-144591.33" - process $proc$libresoc.v:144590$6339 + attribute \src "libresoc.v:142039.13-142039.31" + process $proc$libresoc.v:142039$6836 assign { } { } - assign $0\ldst_port0_addr_i[95:0] \$175 - sync posedge \coresync_clk - update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:144592.3-144593.21" - process $proc$libresoc.v:144592$6340 + attribute \src "libresoc.v:142047.14-142047.43" + process $proc$libresoc.v:142047$6837 assign { } { } - assign $0\alu_ok[0:0] \$96 + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:142051.14-142051.43" + process $proc$libresoc.v:142051$6838 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:142055.7-142055.20" + process $proc$libresoc.v:142055$6839 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:142121.3-142122.39" + process $proc$libresoc.v:142121$6649 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk - update \alu_ok $0\alu_ok[0:0] + update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:144594.3-144595.25" - process $proc$libresoc.v:144594$6341 + attribute \src "libresoc.v:142123.3-142124.43" + process $proc$libresoc.v:142123$6650 assign { } { } - assign $0\ea_r[63:0] \ea_r$next + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk - update \ea_r $0\ea_r[63:0] + update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:144596.3-144597.29" - process $proc$libresoc.v:144596$6342 + attribute \src "libresoc.v:142125.3-142126.29" + process $proc$libresoc.v:142125$6651 assign { } { } - assign $0\src_r2[63:0] \src_r2$next + assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk - update \src_r2 $0\src_r2[63:0] + update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:144598.3-144599.29" - process $proc$libresoc.v:144598$6343 + attribute \src "libresoc.v:142127.3-142128.29" + process $proc$libresoc.v:142127$6652 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:144600.3-144601.29" - process $proc$libresoc.v:144600$6344 + attribute \src "libresoc.v:142129.3-142130.29" + process $proc$libresoc.v:142129$6653 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:144602.3-144603.27" - process $proc$libresoc.v:144602$6345 + attribute \src "libresoc.v:142131.3-142132.43" + process $proc$libresoc.v:142131$6654 assign { } { } - assign $0\ldo_r[63:0] \ldo_r$next + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk - update \ldo_r $0\ldo_r[63:0] + update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:144604.3-144605.51" - process $proc$libresoc.v:144604$6346 + attribute \src "libresoc.v:142133.3-142134.49" + process $proc$libresoc.v:142133$6655 assign { } { } - assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk - update \oper_r__insn_type $0\oper_r__insn_type[6:0] + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:144606.3-144607.47" - process $proc$libresoc.v:144606$6347 + attribute \src "libresoc.v:142135.3-142136.37" + process $proc$libresoc.v:142135$6656 assign { } { } - assign $0\oper_r__fn_unit[12:0] \oper_r__fn_unit$next + assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk - update \oper_r__fn_unit $0\oper_r__fn_unit[12:0] + update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:144608.3-144609.61" - process $proc$libresoc.v:144608$6348 + attribute \src "libresoc.v:142137.3-142138.43" + process $proc$libresoc.v:142137$6657 assign { } { } - assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk - update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] + update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:144610.3-144611.57" - process $proc$libresoc.v:144610$6349 + attribute \src "libresoc.v:142139.3-142140.85" + process $proc$libresoc.v:142139$6658 assign { } { } - assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next + assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk - update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] + update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:144612.3-144613.45" - process $proc$libresoc.v:144612$6350 + attribute \src "libresoc.v:142141.3-142142.81" + process $proc$libresoc.v:142141$6659 assign { } { } - assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next + assign $0\alu_logical0_logical_op__fn_unit[12:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk - update \oper_r__zero_a $0\oper_r__zero_a[0:0] + update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[12:0] end - attribute \src "libresoc.v:144614.3-144615.45" - process $proc$libresoc.v:144614$6351 + attribute \src "libresoc.v:142143.3-142144.95" + process $proc$libresoc.v:142143$6660 assign { } { } - assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next + assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk - update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] + update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:144616.3-144617.45" - process $proc$libresoc.v:144616$6352 + attribute \src "libresoc.v:142145.3-142146.91" + process $proc$libresoc.v:142145$6661 assign { } { } - assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next + assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk - update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] + update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:144618.3-144619.45" - process $proc$libresoc.v:144618$6353 + attribute \src "libresoc.v:142147.3-142148.79" + process $proc$libresoc.v:142147$6662 assign { } { } - assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next + assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk - update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] + update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:144620.3-144621.45" - process $proc$libresoc.v:144620$6354 + attribute \src "libresoc.v:142149.3-142150.79" + process $proc$libresoc.v:142149$6663 assign { } { } - assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next + assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk - update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] + update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:144622.3-144623.49" - process $proc$libresoc.v:144622$6355 + attribute \src "libresoc.v:142151.3-142152.79" + process $proc$libresoc.v:142151$6664 assign { } { } - assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next + assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk - update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] + update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:144624.3-144625.51" - process $proc$libresoc.v:144624$6356 + attribute \src "libresoc.v:142153.3-142154.79" + process $proc$libresoc.v:142153$6665 assign { } { } - assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next + assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk - update \oper_r__is_signed $0\oper_r__is_signed[0:0] + update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:144626.3-144627.49" - process $proc$libresoc.v:144626$6357 + attribute \src "libresoc.v:142155.3-142156.85" + process $proc$libresoc.v:142155$6666 assign { } { } - assign $0\oper_r__data_len[3:0] \oper_r__data_len$next + assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk - update \oper_r__data_len $0\oper_r__data_len[3:0] + update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:144628.3-144629.57" - process $proc$libresoc.v:144628$6358 + attribute \src "libresoc.v:142157.3-142158.79" + process $proc$libresoc.v:142157$6667 assign { } { } - assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next + assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk - update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] + update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:144630.3-144631.55" - process $proc$libresoc.v:144630$6359 + attribute \src "libresoc.v:142159.3-142160.89" + process $proc$libresoc.v:142159$6668 assign { } { } - assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next + assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk - update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] + update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:144632.3-144633.51" - process $proc$libresoc.v:144632$6360 + attribute \src "libresoc.v:142161.3-142162.87" + process $proc$libresoc.v:142161$6669 assign { } { } - assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next + assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk - update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] + update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:144634.3-144635.41" - process $proc$libresoc.v:144634$6361 + attribute \src "libresoc.v:142163.3-142164.85" + process $proc$libresoc.v:142163$6670 assign { } { } - assign $0\oper_r__insn[31:0] \oper_r__insn$next + assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk - update \oper_r__insn $0\oper_r__insn[31:0] + update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:144636.3-144637.39" - process $proc$libresoc.v:144636$6362 + attribute \src "libresoc.v:142165.3-142166.91" + process $proc$libresoc.v:142165$6671 assign { } { } - assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next + assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk - update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] + update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:144638.3-144639.39" - process $proc$libresoc.v:144638$6363 + attribute \src "libresoc.v:142167.3-142168.83" + process $proc$libresoc.v:142167$6672 assign { } { } - assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next + assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk - update \sto_l_r_sto $0\sto_l_r_sto[0:0] + update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:144640.3-144641.39" - process $proc$libresoc.v:144640$6364 + attribute \src "libresoc.v:142169.3-142170.85" + process $proc$libresoc.v:142169$6673 assign { } { } - assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next + assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk - update \upd_l_r_upd $0\upd_l_r_upd[0:0] + update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:144642.3-144643.39" - process $proc$libresoc.v:144642$6365 + attribute \src "libresoc.v:142171.3-142172.83" + process $proc$libresoc.v:142171$6674 assign { } { } - assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next + assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk - update \upd_l_s_upd $0\upd_l_s_upd[0:0] + update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:144644.3-144645.39" - process $proc$libresoc.v:144644$6366 + attribute \src "libresoc.v:142173.3-142174.75" + process $proc$libresoc.v:142173$6675 assign { } { } - assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next + assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk - update \wri_l_r_wri $0\wri_l_r_wri[0:0] + update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:144646.3-144647.39" - process $proc$libresoc.v:144646$6367 + attribute \src "libresoc.v:142175.3-142176.39" + process $proc$libresoc.v:142175$6676 assign { } { } - assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next + assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk - update \adr_l_r_adr $0\adr_l_r_adr[0:0] + update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "libresoc.v:144648.3-144649.39" - process $proc$libresoc.v:144648$6368 + attribute \src "libresoc.v:142177.3-142178.39" + process $proc$libresoc.v:142177$6677 + assign { } { } + assign $0\req_l_s_req[1:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[1:0] + end + attribute \src "libresoc.v:142179.3-142180.39" + process $proc$libresoc.v:142179$6678 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:144650.3-144651.39" - process $proc$libresoc.v:144650$6369 + attribute \src "libresoc.v:142181.3-142182.39" + process $proc$libresoc.v:142181$6679 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:144652.3-144653.39" - process $proc$libresoc.v:144652$6370 + attribute \src "libresoc.v:142183.3-142184.39" + process $proc$libresoc.v:142183$6680 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:144654.3-144655.39" - process $proc$libresoc.v:144654$6371 + attribute \src "libresoc.v:142185.3-142186.39" + process $proc$libresoc.v:142185$6681 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:144656.3-144657.28" - process $proc$libresoc.v:144656$6372 + attribute \src "libresoc.v:142187.3-142188.39" + process $proc$libresoc.v:142187$6682 assign { } { } - assign $0\p_st_go[0:0] \cu_st__go_i + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk - update \p_st_go $0\p_st_go[0:0] + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:142189.3-142190.39" + process $proc$libresoc.v:142189$6683 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:142191.3-142192.41" + process $proc$libresoc.v:142191$6684 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:142193.3-142194.41" + process $proc$libresoc.v:142193$6685 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:142195.3-142196.37" + process $proc$libresoc.v:142195$6686 + assign { } { } + assign $0\prev_wr_go[1:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[1:0] + end + attribute \src "libresoc.v:142197.3-142198.44" + process $proc$libresoc.v:142197$6687 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:142199.3-142200.24" + process $proc$libresoc.v:142199$6688 + assign { } { } + assign $0\all_rd_dly[0:0] \$9 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:144728.3-144736.6" - process $proc$libresoc.v:144728$6373 + attribute \src "libresoc.v:142282.3-142291.6" + process $proc$libresoc.v:142282$6689 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6374 $1\opc_l_s_opc$next[0:0]$6375 - attribute \src "libresoc.v:144729.5-144729.29" + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:142283.5-142283.29" switch \initial - attribute \src "libresoc.v:144729.9-144729.17" + attribute \src "libresoc.v:142283.9-142283.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$53 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6375 1'0 + assign $1\req_done[0:0] 1'1 case - assign $1\opc_l_s_opc$next[0:0]$6375 \cu_issue_i + assign $1\req_done[0:0] \$45 end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6374 + update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:144737.3-144745.6" - process $proc$libresoc.v:144737$6376 + attribute \src "libresoc.v:142292.3-142300.6" + process $proc$libresoc.v:142292$6690 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6377 $1\opc_l_r_opc$next[0:0]$6378 - attribute \src "libresoc.v:144738.5-144738.29" + assign $0\rok_l_s_rdok$next[0:0]$6691 $1\rok_l_s_rdok$next[0:0]$6692 + attribute \src "libresoc.v:142293.5-142293.29" switch \initial - attribute \src "libresoc.v:144738.9-144738.17" + attribute \src "libresoc.v:142293.9-142293.17" case 1'1 case end @@ -232185,21 +232401,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6378 1'1 + assign $1\rok_l_s_rdok$next[0:0]$6692 1'0 case - assign $1\opc_l_r_opc$next[0:0]$6378 \reset_o + assign $1\rok_l_s_rdok$next[0:0]$6692 \cu_issue_i end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6377 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6691 end - attribute \src "libresoc.v:144746.3-144754.6" - process $proc$libresoc.v:144746$6379 + attribute \src "libresoc.v:142301.3-142309.6" + process $proc$libresoc.v:142301$6693 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6380 $1\src_l_s_src$next[2:0]$6381 - attribute \src "libresoc.v:144747.5-144747.29" + assign $0\rok_l_r_rdok$next[0:0]$6694 $1\rok_l_r_rdok$next[0:0]$6695 + attribute \src "libresoc.v:142302.5-142302.29" switch \initial - attribute \src "libresoc.v:144747.9-144747.17" + attribute \src "libresoc.v:142302.9-142302.17" case 1'1 case end @@ -232208,21 +232424,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6381 3'000 + assign $1\rok_l_r_rdok$next[0:0]$6695 1'1 case - assign $1\src_l_s_src$next[2:0]$6381 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\rok_l_r_rdok$next[0:0]$6695 \$63 end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6380 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6694 end - attribute \src "libresoc.v:144755.3-144763.6" - process $proc$libresoc.v:144755$6382 + attribute \src "libresoc.v:142310.3-142318.6" + process $proc$libresoc.v:142310$6696 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6383 $1\src_l_r_src$next[2:0]$6384 - attribute \src "libresoc.v:144756.5-144756.29" + assign $0\rst_l_s_rst$next[0:0]$6697 $1\rst_l_s_rst$next[0:0]$6698 + attribute \src "libresoc.v:142311.5-142311.29" switch \initial - attribute \src "libresoc.v:144756.9-144756.17" + attribute \src "libresoc.v:142311.9-142311.17" case 1'1 case end @@ -232231,21 +232447,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6384 3'111 + assign $1\rst_l_s_rst$next[0:0]$6698 1'0 case - assign $1\src_l_r_src$next[2:0]$6384 \reset_r + assign $1\rst_l_s_rst$next[0:0]$6698 \all_rd end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6383 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6697 end - attribute \src "libresoc.v:144764.3-144772.6" - process $proc$libresoc.v:144764$6385 + attribute \src "libresoc.v:142319.3-142327.6" + process $proc$libresoc.v:142319$6699 assign { } { } assign { } { } - assign $0\adr_l_r_adr$next[0:0]$6386 $1\adr_l_r_adr$next[0:0]$6387 - attribute \src "libresoc.v:144765.5-144765.29" + assign $0\rst_l_r_rst$next[0:0]$6700 $1\rst_l_r_rst$next[0:0]$6701 + attribute \src "libresoc.v:142320.5-142320.29" switch \initial - attribute \src "libresoc.v:144765.9-144765.17" + attribute \src "libresoc.v:142320.9-142320.17" case 1'1 case end @@ -232254,21 +232470,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adr_l_r_adr$next[0:0]$6387 1'1 + assign $1\rst_l_r_rst$next[0:0]$6701 1'1 case - assign $1\adr_l_r_adr$next[0:0]$6387 \reset_a + assign $1\rst_l_r_rst$next[0:0]$6701 \rst_r end sync always - update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6386 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6700 end - attribute \src "libresoc.v:144773.3-144781.6" - process $proc$libresoc.v:144773$6388 + attribute \src "libresoc.v:142328.3-142336.6" + process $proc$libresoc.v:142328$6702 assign { } { } assign { } { } - assign $0\wri_l_r_wri$next[0:0]$6389 $1\wri_l_r_wri$next[0:0]$6390 - attribute \src "libresoc.v:144774.5-144774.29" + assign $0\opc_l_s_opc$next[0:0]$6703 $1\opc_l_s_opc$next[0:0]$6704 + attribute \src "libresoc.v:142329.5-142329.29" switch \initial - attribute \src "libresoc.v:144774.9-144774.17" + attribute \src "libresoc.v:142329.9-142329.17" case 1'1 case end @@ -232277,21 +232493,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wri_l_r_wri$next[0:0]$6390 1'1 + assign $1\opc_l_s_opc$next[0:0]$6704 1'0 case - assign $1\wri_l_r_wri$next[0:0]$6390 \$38 [0] + assign $1\opc_l_s_opc$next[0:0]$6704 \cu_issue_i end sync always - update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6389 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6703 end - attribute \src "libresoc.v:144782.3-144790.6" - process $proc$libresoc.v:144782$6391 + attribute \src "libresoc.v:142337.3-142345.6" + process $proc$libresoc.v:142337$6705 assign { } { } assign { } { } - assign $0\upd_l_s_upd$next[0:0]$6392 $1\upd_l_s_upd$next[0:0]$6393 - attribute \src "libresoc.v:144783.5-144783.29" + assign $0\opc_l_r_opc$next[0:0]$6706 $1\opc_l_r_opc$next[0:0]$6707 + attribute \src "libresoc.v:142338.5-142338.29" switch \initial - attribute \src "libresoc.v:144783.9-144783.17" + attribute \src "libresoc.v:142338.9-142338.17" case 1'1 case end @@ -232300,21 +232516,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_s_upd$next[0:0]$6393 1'0 + assign $1\opc_l_r_opc$next[0:0]$6707 1'1 case - assign $1\upd_l_s_upd$next[0:0]$6393 \reset_i + assign $1\opc_l_r_opc$next[0:0]$6707 \req_done end sync always - update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6392 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6706 end - attribute \src "libresoc.v:144791.3-144799.6" - process $proc$libresoc.v:144791$6394 + attribute \src "libresoc.v:142346.3-142354.6" + process $proc$libresoc.v:142346$6708 assign { } { } assign { } { } - assign $0\upd_l_r_upd$next[0:0]$6395 $1\upd_l_r_upd$next[0:0]$6396 - attribute \src "libresoc.v:144792.5-144792.29" + assign $0\src_l_s_src$next[2:0]$6709 $1\src_l_s_src$next[2:0]$6710 + attribute \src "libresoc.v:142347.5-142347.29" switch \initial - attribute \src "libresoc.v:144792.9-144792.17" + attribute \src "libresoc.v:142347.9-142347.17" case 1'1 case end @@ -232323,21 +232539,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_r_upd$next[0:0]$6396 1'1 + assign $1\src_l_s_src$next[2:0]$6710 3'000 case - assign $1\upd_l_r_upd$next[0:0]$6396 \reset_u + assign $1\src_l_s_src$next[2:0]$6710 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6395 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6709 end - attribute \src "libresoc.v:144800.3-144808.6" - process $proc$libresoc.v:144800$6397 + attribute \src "libresoc.v:142355.3-142363.6" + process $proc$libresoc.v:142355$6711 assign { } { } assign { } { } - assign $0\sto_l_r_sto$next[0:0]$6398 $1\sto_l_r_sto$next[0:0]$6399 - attribute \src "libresoc.v:144801.5-144801.29" + assign $0\src_l_r_src$next[2:0]$6712 $1\src_l_r_src$next[2:0]$6713 + attribute \src "libresoc.v:142356.5-142356.29" switch \initial - attribute \src "libresoc.v:144801.9-144801.17" + attribute \src "libresoc.v:142356.9-142356.17" case 1'1 case end @@ -232346,21 +232562,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sto_l_r_sto$next[0:0]$6399 1'1 + assign $1\src_l_r_src$next[2:0]$6713 3'111 case - assign $1\sto_l_r_sto$next[0:0]$6399 \$59 + assign $1\src_l_r_src$next[2:0]$6713 \reset_r end sync always - update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6398 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6712 end - attribute \src "libresoc.v:144809.3-144817.6" - process $proc$libresoc.v:144809$6400 + attribute \src "libresoc.v:142364.3-142372.6" + process $proc$libresoc.v:142364$6714 assign { } { } assign { } { } - assign $0\lsd_l_r_lsd$next[0:0]$6401 $1\lsd_l_r_lsd$next[0:0]$6402 - attribute \src "libresoc.v:144810.5-144810.29" + assign $0\req_l_s_req$next[1:0]$6715 $1\req_l_s_req$next[1:0]$6716 + attribute \src "libresoc.v:142365.5-142365.29" switch \initial - attribute \src "libresoc.v:144810.9-144810.17" + attribute \src "libresoc.v:142365.9-142365.17" case 1'1 case end @@ -232369,27 +232585,38 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsd_l_r_lsd$next[0:0]$6402 1'1 + assign $1\req_l_s_req$next[1:0]$6716 2'00 case - assign $1\lsd_l_r_lsd$next[0:0]$6402 \$63 + assign $1\req_l_s_req$next[1:0]$6716 \$65 end sync always - update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6401 + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6715 end - attribute \src "libresoc.v:144818.3-144860.6" - process $proc$libresoc.v:144818$6403 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:142373.3-142381.6" + process $proc$libresoc.v:142373$6717 assign { } { } assign { } { } + assign $0\req_l_r_req$next[1:0]$6718 $1\req_l_r_req$next[1:0]$6719 + attribute \src "libresoc.v:142374.5-142374.29" + switch \initial + attribute \src "libresoc.v:142374.9-142374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[1:0]$6719 2'11 + case + assign $1\req_l_r_req$next[1:0]$6719 \$67 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6718 + end + attribute \src "libresoc.v:142382.3-142420.6" + process $proc$libresoc.v:142382$6720 assign { } { } assign { } { } assign { } { } @@ -232426,35 +232653,37 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $0\oper_r__byte_reverse$next[0:0]$6404 $2\oper_r__byte_reverse$next[0:0]$6436 - assign $0\oper_r__data_len$next[3:0]$6405 $2\oper_r__data_len$next[3:0]$6437 - assign $0\oper_r__fn_unit$next[12:0]$6406 $2\oper_r__fn_unit$next[12:0]$6438 + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6721 $1\alu_logical0_logical_op__data_len$next[3:0]$6739 + assign $0\alu_logical0_logical_op__fn_unit$next[12:0]$6722 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6740 assign { } { } assign { } { } - assign $0\oper_r__insn$next[31:0]$6409 $2\oper_r__insn$next[31:0]$6441 - assign $0\oper_r__insn_type$next[6:0]$6410 $2\oper_r__insn_type$next[6:0]$6442 - assign $0\oper_r__is_32bit$next[0:0]$6411 $2\oper_r__is_32bit$next[0:0]$6443 - assign $0\oper_r__is_signed$next[0:0]$6412 $2\oper_r__is_signed$next[0:0]$6444 - assign $0\oper_r__ldst_mode$next[1:0]$6413 $2\oper_r__ldst_mode$next[1:0]$6445 + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6725 $1\alu_logical0_logical_op__input_carry$next[1:0]$6743 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6726 $1\alu_logical0_logical_op__insn$next[31:0]$6744 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6727 $1\alu_logical0_logical_op__insn_type$next[6:0]$6745 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6728 $1\alu_logical0_logical_op__invert_in$next[0:0]$6746 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6729 $1\alu_logical0_logical_op__invert_out$next[0:0]$6747 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6730 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6748 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6731 $1\alu_logical0_logical_op__is_signed$next[0:0]$6749 assign { } { } assign { } { } + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6734 $1\alu_logical0_logical_op__output_carry$next[0:0]$6752 assign { } { } assign { } { } - assign $0\oper_r__sign_extend$next[0:0]$6418 $2\oper_r__sign_extend$next[0:0]$6450 - assign $0\oper_r__zero_a$next[0:0]$6419 $2\oper_r__zero_a$next[0:0]$6451 - assign $0\oper_r__imm_data__data$next[63:0]$6407 $3\oper_r__imm_data__data$next[63:0]$6452 - assign $0\oper_r__imm_data__ok$next[0:0]$6408 $3\oper_r__imm_data__ok$next[0:0]$6453 - assign $0\oper_r__oe__oe$next[0:0]$6414 $3\oper_r__oe__oe$next[0:0]$6454 - assign $0\oper_r__oe__ok$next[0:0]$6415 $3\oper_r__oe__ok$next[0:0]$6455 - assign $0\oper_r__rc__ok$next[0:0]$6416 $3\oper_r__rc__ok$next[0:0]$6456 - assign $0\oper_r__rc__rc$next[0:0]$6417 $3\oper_r__rc__rc$next[0:0]$6457 - attribute \src "libresoc.v:144819.5-144819.29" + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6737 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6755 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6738 $1\alu_logical0_logical_op__zero_a$next[0:0]$6756 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6723 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6757 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6724 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6758 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6732 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6759 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6733 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6760 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6735 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6761 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6736 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6762 + attribute \src "libresoc.v:142383.5-142383.29" switch \initial - attribute \src "libresoc.v:144819.9-144819.17" + attribute \src "libresoc.v:142383.9-142383.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -232464,39 +232693,6 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\oper_r__insn$next[31:0]$6425 $1\oper_r__ldst_mode$next[1:0]$6429 $1\oper_r__sign_extend$next[0:0]$6434 $1\oper_r__byte_reverse$next[0:0]$6420 $1\oper_r__data_len$next[3:0]$6421 $1\oper_r__is_signed$next[0:0]$6428 $1\oper_r__is_32bit$next[0:0]$6427 $1\oper_r__oe__ok$next[0:0]$6431 $1\oper_r__oe__oe$next[0:0]$6430 $1\oper_r__rc__ok$next[0:0]$6432 $1\oper_r__rc__rc$next[0:0]$6433 $1\oper_r__zero_a$next[0:0]$6435 $1\oper_r__imm_data__ok$next[0:0]$6424 $1\oper_r__imm_data__data$next[63:0]$6423 $1\oper_r__fn_unit$next[12:0]$6422 $1\oper_r__insn_type$next[6:0]$6426 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } - case - assign $1\oper_r__byte_reverse$next[0:0]$6420 \oper_r__byte_reverse - assign $1\oper_r__data_len$next[3:0]$6421 \oper_r__data_len - assign $1\oper_r__fn_unit$next[12:0]$6422 \oper_r__fn_unit - assign $1\oper_r__imm_data__data$next[63:0]$6423 \oper_r__imm_data__data - assign $1\oper_r__imm_data__ok$next[0:0]$6424 \oper_r__imm_data__ok - assign $1\oper_r__insn$next[31:0]$6425 \oper_r__insn - assign $1\oper_r__insn_type$next[6:0]$6426 \oper_r__insn_type - assign $1\oper_r__is_32bit$next[0:0]$6427 \oper_r__is_32bit - assign $1\oper_r__is_signed$next[0:0]$6428 \oper_r__is_signed - assign $1\oper_r__ldst_mode$next[1:0]$6429 \oper_r__ldst_mode - assign $1\oper_r__oe__oe$next[0:0]$6430 \oper_r__oe__oe - assign $1\oper_r__oe__ok$next[0:0]$6431 \oper_r__oe__ok - assign $1\oper_r__rc__ok$next[0:0]$6432 \oper_r__rc__ok - assign $1\oper_r__rc__rc$next[0:0]$6433 \oper_r__rc__rc - assign $1\oper_r__sign_extend$next[0:0]$6434 \oper_r__sign_extend - assign $1\oper_r__zero_a$next[0:0]$6435 \oper_r__zero_a - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" - switch \cu_done_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } assign { } { } assign { } { } @@ -232509,28 +232705,26 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\oper_r__insn$next[31:0]$6441 $2\oper_r__ldst_mode$next[1:0]$6445 $2\oper_r__sign_extend$next[0:0]$6450 $2\oper_r__byte_reverse$next[0:0]$6436 $2\oper_r__data_len$next[3:0]$6437 $2\oper_r__is_signed$next[0:0]$6444 $2\oper_r__is_32bit$next[0:0]$6443 $2\oper_r__oe__ok$next[0:0]$6447 $2\oper_r__oe__oe$next[0:0]$6446 $2\oper_r__rc__ok$next[0:0]$6448 $2\oper_r__rc__rc$next[0:0]$6449 $2\oper_r__zero_a$next[0:0]$6451 $2\oper_r__imm_data__ok$next[0:0]$6440 $2\oper_r__imm_data__data$next[63:0]$6439 $2\oper_r__fn_unit$next[12:0]$6438 $2\oper_r__insn_type$next[6:0]$6442 } 132'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6744 $1\alu_logical0_logical_op__data_len$next[3:0]$6739 $1\alu_logical0_logical_op__is_signed$next[0:0]$6749 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6748 $1\alu_logical0_logical_op__output_carry$next[0:0]$6752 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6755 $1\alu_logical0_logical_op__invert_out$next[0:0]$6747 $1\alu_logical0_logical_op__input_carry$next[1:0]$6743 $1\alu_logical0_logical_op__zero_a$next[0:0]$6756 $1\alu_logical0_logical_op__invert_in$next[0:0]$6746 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6751 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6750 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6753 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6754 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6742 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6741 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6740 $1\alu_logical0_logical_op__insn_type$next[6:0]$6745 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } case - assign $2\oper_r__byte_reverse$next[0:0]$6436 $1\oper_r__byte_reverse$next[0:0]$6420 - assign $2\oper_r__data_len$next[3:0]$6437 $1\oper_r__data_len$next[3:0]$6421 - assign $2\oper_r__fn_unit$next[12:0]$6438 $1\oper_r__fn_unit$next[12:0]$6422 - assign $2\oper_r__imm_data__data$next[63:0]$6439 $1\oper_r__imm_data__data$next[63:0]$6423 - assign $2\oper_r__imm_data__ok$next[0:0]$6440 $1\oper_r__imm_data__ok$next[0:0]$6424 - assign $2\oper_r__insn$next[31:0]$6441 $1\oper_r__insn$next[31:0]$6425 - assign $2\oper_r__insn_type$next[6:0]$6442 $1\oper_r__insn_type$next[6:0]$6426 - assign $2\oper_r__is_32bit$next[0:0]$6443 $1\oper_r__is_32bit$next[0:0]$6427 - assign $2\oper_r__is_signed$next[0:0]$6444 $1\oper_r__is_signed$next[0:0]$6428 - assign $2\oper_r__ldst_mode$next[1:0]$6445 $1\oper_r__ldst_mode$next[1:0]$6429 - assign $2\oper_r__oe__oe$next[0:0]$6446 $1\oper_r__oe__oe$next[0:0]$6430 - assign $2\oper_r__oe__ok$next[0:0]$6447 $1\oper_r__oe__ok$next[0:0]$6431 - assign $2\oper_r__rc__ok$next[0:0]$6448 $1\oper_r__rc__ok$next[0:0]$6432 - assign $2\oper_r__rc__rc$next[0:0]$6449 $1\oper_r__rc__rc$next[0:0]$6433 - assign $2\oper_r__sign_extend$next[0:0]$6450 $1\oper_r__sign_extend$next[0:0]$6434 - assign $2\oper_r__zero_a$next[0:0]$6451 $1\oper_r__zero_a$next[0:0]$6435 + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6739 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[12:0]$6740 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6741 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6742 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6743 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6744 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6745 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6746 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6747 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6748 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6749 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6750 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6751 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6752 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6753 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6754 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6755 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6756 \alu_logical0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -232542,237 +232736,221 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $3\oper_r__imm_data__data$next[63:0]$6452 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\oper_r__imm_data__ok$next[0:0]$6453 1'0 - assign $3\oper_r__rc__rc$next[0:0]$6457 1'0 - assign $3\oper_r__rc__ok$next[0:0]$6456 1'0 - assign $3\oper_r__oe__oe$next[0:0]$6454 1'0 - assign $3\oper_r__oe__ok$next[0:0]$6455 1'0 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6757 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6758 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6762 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6761 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6759 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6760 1'0 case - assign $3\oper_r__imm_data__data$next[63:0]$6452 $2\oper_r__imm_data__data$next[63:0]$6439 - assign $3\oper_r__imm_data__ok$next[0:0]$6453 $2\oper_r__imm_data__ok$next[0:0]$6440 - assign $3\oper_r__oe__oe$next[0:0]$6454 $2\oper_r__oe__oe$next[0:0]$6446 - assign $3\oper_r__oe__ok$next[0:0]$6455 $2\oper_r__oe__ok$next[0:0]$6447 - assign $3\oper_r__rc__ok$next[0:0]$6456 $2\oper_r__rc__ok$next[0:0]$6448 - assign $3\oper_r__rc__rc$next[0:0]$6457 $2\oper_r__rc__rc$next[0:0]$6449 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6757 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6741 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6758 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6742 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6759 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6750 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6760 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6751 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6761 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6753 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6762 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6754 end sync always - update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6404 - update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6405 - update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[12:0]$6406 - update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6407 - update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6408 - update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6409 - update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6410 - update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6411 - update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6412 - update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6413 - update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6414 - update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6415 - update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6416 - update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6417 - update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6418 - update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6419 + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6721 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[12:0]$6722 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6723 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6724 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6725 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6726 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6727 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6728 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6729 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6730 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6731 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6732 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6733 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6734 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6735 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6736 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6737 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6738 end - attribute \src "libresoc.v:144861.3-144870.6" - process $proc$libresoc.v:144861$6458 + attribute \src "libresoc.v:142421.3-142442.6" + process $proc$libresoc.v:142421$6763 + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\ldo_r$next[63:0]$6459 $1\ldo_r$next[63:0]$6460 - attribute \src "libresoc.v:144862.5-144862.29" + assign $0\data_r0__o$next[63:0]$6764 $2\data_r0__o$next[63:0]$6768 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$6765 $3\data_r0__o_ok$next[0:0]$6770 + attribute \src "libresoc.v:142422.5-142422.29" switch \initial - attribute \src "libresoc.v:144862.9-144862.17" + attribute \src "libresoc.v:142422.9-142422.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \ld_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldo_r$next[63:0]$6460 \ldd_o - case - assign $1\ldo_r$next[63:0]$6460 \ldo_r - end - sync always - update \ldo_r$next $0\ldo_r$next[63:0]$6459 - end - attribute \src "libresoc.v:144871.3-144886.6" - process $proc$libresoc.v:144871$6461 - assign { } { } - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$6462 $2\src_r0$next[63:0]$6464 - attribute \src "libresoc.v:144872.5-144872.29" - switch \initial - attribute \src "libresoc.v:144872.9-144872.17" - case 1'1 + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$6767 $1\data_r0__o$next[63:0]$6766 } { \o_ok \alu_logical0_o } case + assign $1\data_r0__o$next[63:0]$6766 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6767 \data_r0__o_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" - switch \cu_rd__go_i [0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6463 \src1_i + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$6769 $2\data_r0__o$next[63:0]$6768 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $1\src_r0$next[63:0]$6463 \src_r0 + assign $2\data_r0__o$next[63:0]$6768 $1\data_r0__o$next[63:0]$6766 + assign $2\data_r0__o_ok$next[0:0]$6769 $1\data_r0__o_ok$next[0:0]$6767 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" - switch \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r0$next[63:0]$6464 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\data_r0__o_ok$next[0:0]$6770 1'0 case - assign $2\src_r0$next[63:0]$6464 $1\src_r0$next[63:0]$6463 + assign $3\data_r0__o_ok$next[0:0]$6770 $2\data_r0__o_ok$next[0:0]$6769 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6462 + update \data_r0__o$next $0\data_r0__o$next[63:0]$6764 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6765 end - attribute \src "libresoc.v:144887.3-144902.6" - process $proc$libresoc.v:144887$6465 + attribute \src "libresoc.v:142443.3-142464.6" + process $proc$libresoc.v:142443$6771 assign { } { } assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6466 $2\src_r1$next[63:0]$6468 - attribute \src "libresoc.v:144888.5-144888.29" + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$6772 $2\data_r1__cr_a$next[3:0]$6776 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$6773 $3\data_r1__cr_a_ok$next[0:0]$6778 + attribute \src "libresoc.v:142444.5-142444.29" switch \initial - attribute \src "libresoc.v:144888.9-144888.17" + attribute \src "libresoc.v:142444.9-142444.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" - switch \cu_rd__go_i [1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6467 \src2_i + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$6775 $1\data_r1__cr_a$next[3:0]$6774 } { \cr_a_ok \alu_logical0_cr_a } case - assign $1\src_r1$next[63:0]$6467 \src_r1 + assign $1\data_r1__cr_a$next[3:0]$6774 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6775 \data_r1__cr_a_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r1$next[63:0]$6468 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\src_r1$next[63:0]$6468 $1\src_r1$next[63:0]$6467 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$6466 - end - attribute \src "libresoc.v:144903.3-144918.6" - process $proc$libresoc.v:144903$6469 - assign { } { } - assign { } { } - assign { } { } - assign $0\src_r2$next[63:0]$6470 $2\src_r2$next[63:0]$6472 - attribute \src "libresoc.v:144904.5-144904.29" - switch \initial - attribute \src "libresoc.v:144904.9-144904.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" - switch \cu_rd__go_i [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$6471 \src3_i + assign { $2\data_r1__cr_a_ok$next[0:0]$6777 $2\data_r1__cr_a$next[3:0]$6776 } 5'00000 case - assign $1\src_r2$next[63:0]$6471 \src_r2 + assign $2\data_r1__cr_a$next[3:0]$6776 $1\data_r1__cr_a$next[3:0]$6774 + assign $2\data_r1__cr_a_ok$next[0:0]$6777 $1\data_r1__cr_a_ok$next[0:0]$6775 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" - switch \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r2$next[63:0]$6472 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\data_r1__cr_a_ok$next[0:0]$6778 1'0 case - assign $2\src_r2$next[63:0]$6472 $1\src_r2$next[63:0]$6471 + assign $3\data_r1__cr_a_ok$next[0:0]$6778 $2\data_r1__cr_a_ok$next[0:0]$6777 end sync always - update \src_r2$next $0\src_r2$next[63:0]$6470 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6772 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6773 end - attribute \src "libresoc.v:144919.3-144928.6" - process $proc$libresoc.v:144919$6473 + attribute \src "libresoc.v:142465.3-142474.6" + process $proc$libresoc.v:142465$6779 assign { } { } assign { } { } - assign $0\ea_r$next[63:0]$6474 $1\ea_r$next[63:0]$6475 - attribute \src "libresoc.v:144920.5-144920.29" + assign $0\src_r0$next[63:0]$6780 $1\src_r0$next[63:0]$6781 + attribute \src "libresoc.v:142466.5-142466.29" switch \initial - attribute \src "libresoc.v:144920.9-144920.17" + attribute \src "libresoc.v:142466.9-142466.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \alu_l_q_alu + switch \src_sel attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ea_r$next[63:0]$6475 \alu_o + assign $1\src_r0$next[63:0]$6781 \src_or_imm case - assign $1\ea_r$next[63:0]$6475 \ea_r + assign $1\src_r0$next[63:0]$6781 \src_r0 end sync always - update \ea_r$next $0\ea_r$next[63:0]$6474 + update \src_r0$next $0\src_r0$next[63:0]$6780 end - attribute \src "libresoc.v:144929.3-144938.6" - process $proc$libresoc.v:144929$6476 + attribute \src "libresoc.v:142475.3-142484.6" + process $proc$libresoc.v:142475$6782 assign { } { } assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:144930.5-144930.29" + assign $0\src_r1$next[63:0]$6783 $1\src_r1$next[63:0]$6784 + attribute \src "libresoc.v:142476.5-142476.29" switch \initial - attribute \src "libresoc.v:144930.9-144930.17" + attribute \src "libresoc.v:142476.9-142476.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" - switch \cu_wr__go_i [0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dest1_o[63:0] \ldd_r + assign $1\src_r1$next[63:0]$6784 \src_or_imm$80 case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\src_r1$next[63:0]$6784 \src_r1 end sync always - update \dest1_o $0\dest1_o[63:0] + update \src_r1$next $0\src_r1$next[63:0]$6783 end - attribute \src "libresoc.v:144939.3-144948.6" - process $proc$libresoc.v:144939$6477 + attribute \src "libresoc.v:142485.3-142494.6" + process $proc$libresoc.v:142485$6785 assign { } { } assign { } { } - assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:144940.5-144940.29" + assign $0\src_r2$next[0:0]$6786 $1\src_r2$next[0:0]$6787 + attribute \src "libresoc.v:142486.5-142486.29" switch \initial - attribute \src "libresoc.v:144940.9-144940.17" + attribute \src "libresoc.v:142486.9-142486.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - switch \$164 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dest2_o[63:0] \addr_r + assign $1\src_r2$next[0:0]$6787 \src3_i case - assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\src_r2$next[0:0]$6787 \src_r2 end sync always - update \dest2_o $0\dest2_o[63:0] + update \src_r2$next $0\src_r2$next[0:0]$6786 end - attribute \src "libresoc.v:144949.3-144957.6" - process $proc$libresoc.v:144949$6478 + attribute \src "libresoc.v:142495.3-142503.6" + process $proc$libresoc.v:142495$6788 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$next[0:0]$6479 $1\ldst_port0_addr_i_ok$next[0:0]$6480 - attribute \src "libresoc.v:144950.5-144950.29" + assign $0\alui_l_r_alui$next[0:0]$6789 $1\alui_l_r_alui$next[0:0]$6790 + attribute \src "libresoc.v:142496.5-142496.29" switch \initial - attribute \src "libresoc.v:144950.9-144950.17" + attribute \src "libresoc.v:142496.9-142496.17" case 1'1 case end @@ -232781,89804 +232959,72900 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$next[0:0]$6480 1'0 + assign $1\alui_l_r_alui$next[0:0]$6790 1'1 case - assign $1\ldst_port0_addr_i_ok$next[0:0]$6480 \$177 + assign $1\alui_l_r_alui$next[0:0]$6790 \$89 end sync always - update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6479 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6789 end - attribute \src "libresoc.v:144958.3-144981.6" - process $proc$libresoc.v:144958$6481 + attribute \src "libresoc.v:142504.3-142512.6" + process $proc$libresoc.v:142504$6791 assign { } { } assign { } { } - assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:144959.5-144959.29" + assign $0\alu_l_r_alu$next[0:0]$6792 $1\alu_l_r_alu$next[0:0]$6793 + attribute \src "libresoc.v:142505.5-142505.29" switch \initial - attribute \src "libresoc.v:144959.9-144959.17" + attribute \src "libresoc.v:142505.9-142505.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" - switch \oper_r__byte_reverse + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lddata_r[63:0] $2\lddata_r[63:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - switch \oper_r__data_len - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $2\lddata_r[63:0] \$186 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $2\lddata_r[63:0] \$188 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $2\lddata_r[63:0] \$190 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $2\lddata_r[63:0] { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } - case - assign $2\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\alu_l_r_alu$next[0:0]$6793 1'1 case - assign $1\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_l_r_alu$next[0:0]$6793 \$91 end sync always - update \lddata_r $0\lddata_r[63:0] + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6792 end - attribute \src "libresoc.v:144982.3-144993.6" - process $proc$libresoc.v:144982$6482 + attribute \src "libresoc.v:142513.3-142522.6" + process $proc$libresoc.v:142513$6794 assign { } { } - assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:144983.5-144983.29" - switch \initial - attribute \src "libresoc.v:144983.9-144983.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" - switch \oper_r__byte_reverse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\revnorev[63:0] \lddata_r - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\revnorev[63:0] \ldst_port0_ld_data_o - end - sync always - update \revnorev $0\revnorev[63:0] - end - attribute \src "libresoc.v:144994.3-145013.6" - process $proc$libresoc.v:144994$6483 assign { } { } - assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:144995.5-144995.29" + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:142514.5-142514.29" switch \initial - attribute \src "libresoc.v:144995.9-144995.17" + attribute \src "libresoc.v:142514.9-142514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" - switch \oper_r__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldd_o[63:0] $2\ldd_o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - switch \$192 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ldd_o[63:0] { \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\ldd_o[63:0] { \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31:0] } - end - attribute \src "libresoc.v:0.0-0.0" + assign $1\dest1_o[63:0] \data_r0__o case - assign { } { } - assign $1\ldd_o[63:0] \revnorev + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \ldd_o $0\ldd_o[63:0] + update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:145014.3-145037.6" - process $proc$libresoc.v:145014$6484 + attribute \src "libresoc.v:142523.3-142532.6" + process $proc$libresoc.v:142523$6795 assign { } { } assign { } { } - assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:145015.5-145015.29" + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:142524.5-142524.29" switch \initial - attribute \src "libresoc.v:145015.9-145015.17" + attribute \src "libresoc.v:142524.9-142524.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" - switch \oper_r__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\stdata_r[63:0] $2\stdata_r[63:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - switch \oper_r__data_len - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $2\stdata_r[63:0] \$194 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $2\stdata_r[63:0] \$196 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $2\stdata_r[63:0] \$198 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $2\stdata_r[63:0] { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } - case - assign $2\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\dest2_o[3:0] \data_r1__cr_a case - assign $1\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dest2_o[3:0] 4'0000 end sync always - update \stdata_r $0\stdata_r[63:0] + update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:145038.3-145049.6" - process $proc$libresoc.v:145038$6485 + attribute \src "libresoc.v:142533.3-142541.6" + process $proc$libresoc.v:142533$6796 assign { } { } - assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:145039.5-145039.29" + assign { } { } + assign $0\prev_wr_go$next[1:0]$6797 $1\prev_wr_go$next[1:0]$6798 + attribute \src "libresoc.v:142534.5-142534.29" switch \initial - attribute \src "libresoc.v:145039.9-145039.17" + attribute \src "libresoc.v:142534.9-142534.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" - switch \oper_r__byte_reverse + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_st_data_i[63:0] \stdata_r - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ldst_port0_st_data_i[63:0] \src_r2 - end - sync always - update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] - end - connect \$100 $and$libresoc.v:144497$6244_Y - connect \$102 $and$libresoc.v:144498$6245_Y - connect \$104 $and$libresoc.v:144499$6246_Y - connect \$106 $and$libresoc.v:144500$6247_Y - connect \$108 $and$libresoc.v:144501$6248_Y - connect \$10 $or$libresoc.v:144502$6249_Y - connect \$110 $and$libresoc.v:144503$6250_Y - connect \$112 $and$libresoc.v:144504$6251_Y - connect \$114 $and$libresoc.v:144505$6252_Y - connect \$116 $and$libresoc.v:144506$6253_Y - connect \$118 $and$libresoc.v:144507$6254_Y - connect \$120 $and$libresoc.v:144508$6255_Y - connect \$122 $and$libresoc.v:144509$6256_Y - connect \$124 $and$libresoc.v:144510$6257_Y - connect \$126 $eq$libresoc.v:144511$6258_Y - connect \$128 $and$libresoc.v:144512$6259_Y - connect \$12 $or$libresoc.v:144513$6260_Y - connect \$130 $and$libresoc.v:144514$6261_Y - connect \$132 $and$libresoc.v:144515$6262_Y - connect \$134 $or$libresoc.v:144516$6263_Y - connect \$136 $or$libresoc.v:144517$6264_Y - connect \$138 $or$libresoc.v:144518$6265_Y - connect \$140 $and$libresoc.v:144519$6266_Y - connect \$142 $and$libresoc.v:144520$6267_Y - connect \$145 $or$libresoc.v:144521$6268_Y - connect \$147 $or$libresoc.v:144522$6269_Y - connect \$144 $not$libresoc.v:144523$6270_Y - connect \$14 $or$libresoc.v:144524$6271_Y - connect \$150 $and$libresoc.v:144525$6272_Y - connect \$152 $or$libresoc.v:144526$6273_Y - connect \$154 $and$libresoc.v:144527$6274_Y - connect \$156 $not$libresoc.v:144528$6275_Y - connect \$158 $or$libresoc.v:144529$6276_Y - connect \$160 $and$libresoc.v:144530$6277_Y - connect \$162 $eq$libresoc.v:144531$6278_Y - connect \$164 $and$libresoc.v:144532$6279_Y - connect \$167 $eq$libresoc.v:144533$6280_Y - connect \$16 $or$libresoc.v:144534$6281_Y - connect \$169 $and$libresoc.v:144535$6282_Y - connect \$171 $and$libresoc.v:144536$6283_Y - connect \$173 $and$libresoc.v:144537$6284_Y - connect \$175 $pos$libresoc.v:144538$6286_Y - connect \$177 $and$libresoc.v:144539$6287_Y - connect \$186 $pos$libresoc.v:144540$6289_Y - connect \$188 $pos$libresoc.v:144541$6290_Y - connect \$18 $or$libresoc.v:144542$6291_Y - connect \$190 $pos$libresoc.v:144543$6292_Y - connect \$192 $eq$libresoc.v:144544$6293_Y - connect \$194 $pos$libresoc.v:144545$6295_Y - connect \$196 $pos$libresoc.v:144546$6296_Y - connect \$198 $pos$libresoc.v:144547$6297_Y - connect \$20 $or$libresoc.v:144548$6298_Y - connect \$22 $eq$libresoc.v:144549$6299_Y - connect \$24 $eq$libresoc.v:144550$6300_Y - connect \$26 $and$libresoc.v:144551$6301_Y - connect \$28 $and$libresoc.v:144552$6302_Y - connect \$30 $not$libresoc.v:144553$6303_Y - connect \$32 $and$libresoc.v:144554$6304_Y - connect \$34 $not$libresoc.v:144555$6305_Y - connect \$36 $and$libresoc.v:144556$6306_Y - connect \$39 $not$libresoc.v:144557$6307_Y - connect \$41 $eq$libresoc.v:144558$6308_Y - connect \$43 $and$libresoc.v:144559$6309_Y - connect \$45 $or$libresoc.v:144560$6310_Y - connect \$47 $not$libresoc.v:144561$6311_Y - connect \$49 $eq$libresoc.v:144562$6312_Y - connect \$51 $and$libresoc.v:144563$6313_Y - connect \$53 $or$libresoc.v:144564$6314_Y - connect \$55 $or$libresoc.v:144565$6315_Y - connect \$57 $and$libresoc.v:144566$6316_Y - connect \$59 $or$libresoc.v:144567$6317_Y - connect \$61 $or$libresoc.v:144568$6318_Y - connect \$63 $or$libresoc.v:144569$6319_Y - connect \$65 $ternary$libresoc.v:144570$6320_Y - connect \$67 $ternary$libresoc.v:144571$6321_Y - connect \$69 $ternary$libresoc.v:144572$6322_Y - connect \$71 $ternary$libresoc.v:144573$6323_Y - connect \$74 $add$libresoc.v:144574$6324_Y - connect \$76 $and$libresoc.v:144575$6325_Y - connect \$78 $not$libresoc.v:144576$6326_Y - connect \$80 $and$libresoc.v:144577$6327_Y - connect \$82 $not$libresoc.v:144578$6328_Y - connect \$84 $and$libresoc.v:144579$6329_Y - connect \$86 $and$libresoc.v:144580$6330_Y - connect \$88 $and$libresoc.v:144581$6331_Y - connect \$8 $or$libresoc.v:144582$6332_Y - connect \$90 $or$libresoc.v:144583$6333_Y - connect \$93 $or$libresoc.v:144584$6334_Y - connect \$92 $not$libresoc.v:144585$6335_Y - connect \$96 $and$libresoc.v:144586$6336_Y - connect \$98 $not$libresoc.v:144587$6337_Y - connect \$38 \$55 - connect \$73 \$74 - connect \$166 \$169 + assign $1\prev_wr_go$next[1:0]$6798 2'00 + case + assign $1\prev_wr_go$next[1:0]$6798 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6797 + end + connect \$9 $and$libresoc.v:142064$6592_Y + connect \$99 $and$libresoc.v:142065$6593_Y + connect \$101 $not$libresoc.v:142066$6594_Y + connect \$103 $and$libresoc.v:142067$6595_Y + connect \$105 $and$libresoc.v:142068$6596_Y + connect \$107 $and$libresoc.v:142069$6597_Y + connect \$109 $and$libresoc.v:142070$6598_Y + connect \$111 $and$libresoc.v:142071$6599_Y + connect \$113 $and$libresoc.v:142072$6600_Y + connect \$115 $and$libresoc.v:142073$6601_Y + connect \$11 $not$libresoc.v:142074$6602_Y + connect \$13 $and$libresoc.v:142075$6603_Y + connect \$15 $not$libresoc.v:142076$6604_Y + connect \$17 $and$libresoc.v:142077$6605_Y + connect \$1 $and$libresoc.v:142078$6606_Y + connect \$19 $and$libresoc.v:142079$6607_Y + connect \$23 $not$libresoc.v:142080$6608_Y + connect \$25 $and$libresoc.v:142081$6609_Y + connect \$22 $reduce_or$libresoc.v:142082$6610_Y + connect \$21 $not$libresoc.v:142083$6611_Y + connect \$29 $and$libresoc.v:142084$6612_Y + connect \$31 $reduce_or$libresoc.v:142085$6613_Y + connect \$33 $reduce_or$libresoc.v:142086$6614_Y + connect \$35 $or$libresoc.v:142087$6615_Y + connect \$37 $not$libresoc.v:142088$6616_Y + connect \$39 $and$libresoc.v:142089$6617_Y + connect \$41 $and$libresoc.v:142090$6618_Y + connect \$43 $eq$libresoc.v:142091$6619_Y + connect \$45 $and$libresoc.v:142092$6620_Y + connect \$47 $eq$libresoc.v:142093$6621_Y + connect \$4 $not$libresoc.v:142094$6622_Y + connect \$49 $and$libresoc.v:142095$6623_Y + connect \$51 $and$libresoc.v:142096$6624_Y + connect \$53 $and$libresoc.v:142097$6625_Y + connect \$55 $or$libresoc.v:142098$6626_Y + connect \$57 $or$libresoc.v:142099$6627_Y + connect \$59 $or$libresoc.v:142100$6628_Y + connect \$61 $or$libresoc.v:142101$6629_Y + connect \$63 $and$libresoc.v:142102$6630_Y + connect \$65 $and$libresoc.v:142103$6631_Y + connect \$67 $or$libresoc.v:142104$6632_Y + connect \$6 $or$libresoc.v:142105$6633_Y + connect \$69 $and$libresoc.v:142106$6634_Y + connect \$71 $and$libresoc.v:142107$6635_Y + connect \$73 $ternary$libresoc.v:142108$6636_Y + connect \$75 $ternary$libresoc.v:142109$6637_Y + connect \$78 $ternary$libresoc.v:142110$6638_Y + connect \$3 $reduce_and$libresoc.v:142111$6639_Y + connect \$81 $ternary$libresoc.v:142112$6640_Y + connect \$83 $ternary$libresoc.v:142113$6641_Y + connect \$85 $ternary$libresoc.v:142114$6642_Y + connect \$87 $ternary$libresoc.v:142115$6643_Y + connect \$89 $and$libresoc.v:142116$6644_Y + connect \$91 $and$libresoc.v:142117$6645_Y + connect \$93 $and$libresoc.v:142118$6646_Y + connect \$95 $not$libresoc.v:142119$6647_Y + connect \$97 $not$libresoc.v:142120$6648_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 - connect \ldst_port0_st_data_i_ok \cu_st__go_i - connect \ld_ok \ldst_port0_ld_data_o_ok - connect \addr_ok \ldst_port0_addr_ok_o - connect { \exc_$signal$185 \exc_$signal$184 \exc_$signal$183 \exc_$signal$182 \exc_$signal$181 \exc_$signal$180 \exc_$signal$179 \exc_$signal } { \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal } - connect \ldst_port0_addr_i$next \$175 - connect \ldst_port0_data_len \oper_r__data_len - connect \ldst_port0_is_st_i \$173 - connect \ldst_port0_is_ld_i \$171 - connect \cu_wrmask_o \$169 [1:0] - connect \ea \dest2_o - connect \o \dest1_o - connect \cu_done_o \$160 - connect \wr_reset \$154 - connect \wr_any \$138 - connect \cu_wr__rel_o [1] \$132 - connect \cu_wr__rel_o [0] \$122 - connect \cu_st__rel_o \$112 - connect \cu_ad__rel_o \$104 - connect \rd_done \$100 - connect \alu_valid \$96 - connect \rda_any \$90 - connect \cu_rd__rel_o [2] \$88 - connect \cu_rd__rel_o [1:0] \$84 [1:0] + connect \cu_wr__rel_o \$111 + connect \cu_rd__rel_o \$103 connect \cu_busy_o \opc_l_q_opc - connect \alu_ok$next \alu_valid - connect \alu_o \$74 [63:0] - connect \src2_or_imm \$71 - connect \src1_or_z \$69 - connect \addr_r \$67 - connect \ldd_r \$65 - connect \rst_l_r_rst \cu_issue_i - connect \rst_l_s_rst \addr_ok - connect \lsd_l_s_lsd \cu_issue_i - connect \sto_l_s_sto \$57 - connect \wri_l_s_wri \cu_issue_i - connect \lod_l_r_lod \ld_ok - connect \lod_l_s_lod \reset_i - connect \adr_l_s_adr \reset_i - connect \alu_l_r_alu \$36 - connect \alu_l_s_alu \reset_i - connect \st_o \op_is_st - connect \ld_o \op_is_ld - connect \stwd_mem_o \$28 - connect \load_mem_o \$26 - connect \op_is_ld \$24 - connect \op_is_st \$22 - connect \p_st_go$next \cu_st__go_i - connect \reset_a \$20 - connect \reset_r \$18 - connect \reset_s \$16 - connect \reset_u \$14 - connect \reset_w \$12 - connect \reset_o \$10 - connect \reset_i \$8 + connect \alu_l_s_alu \all_rd_pulse + connect \alu_logical0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_logical0_p_valid_i \alui_l_q_alui + connect \alu_logical0_xer_so \$87 + connect \alu_logical0_rb \$85 + connect \alu_logical0_ra \$83 + connect \src_or_imm$80 \$81 + connect \src_sel$77 \$78 + connect \src_or_imm \$75 + connect \src_sel \$73 + connect \cu_wrmask_o { \$71 \$69 } + connect \reset_r \$61 + connect \reset_w \$59 + connect \rst_r \$57 + connect \reset \$55 + connect \wr_any \$35 + connect \cu_done_o \$29 + connect \alu_pulsem { \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$17 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_logical0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$13 + connect \all_rd_dly$next \all_rd + connect \all_rd \$9 end -attribute \src "libresoc.v:145113.1-145700.10" +attribute \src "libresoc.v:142578.1-143955.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" -module \left_mask - attribute \src "libresoc.v:145114.7-145114.20" +module \logical_pipe1 + attribute \src "libresoc.v:143894.3-143912.6" + wire width 4 $0\cr_a$next[3:0]$6924 + attribute \src "libresoc.v:143654.3-143655.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:143894.3-143912.6" + wire $0\cr_a_ok$next[0:0]$6925 + attribute \src "libresoc.v:143656.3-143657.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:142579.7-142579.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145312.3-145699.6" - wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:145312.3-145699.6" - wire $10\mask[9:9] - attribute \src "libresoc.v:145312.3-145699.6" - wire $11\mask[10:10] - attribute \src "libresoc.v:145312.3-145699.6" - wire $12\mask[11:11] - attribute \src "libresoc.v:145312.3-145699.6" - wire $13\mask[12:12] - attribute \src "libresoc.v:145312.3-145699.6" - wire $14\mask[13:13] - attribute \src "libresoc.v:145312.3-145699.6" - wire $15\mask[14:14] - attribute \src "libresoc.v:145312.3-145699.6" - wire $16\mask[15:15] - attribute \src "libresoc.v:145312.3-145699.6" - wire $17\mask[16:16] - attribute \src "libresoc.v:145312.3-145699.6" - wire $18\mask[17:17] - attribute \src "libresoc.v:145312.3-145699.6" - wire $19\mask[18:18] - attribute \src "libresoc.v:145312.3-145699.6" - wire $1\mask[0:0] - attribute \src "libresoc.v:145312.3-145699.6" - wire $20\mask[19:19] - attribute \src "libresoc.v:145312.3-145699.6" - wire $21\mask[20:20] - attribute \src "libresoc.v:145312.3-145699.6" - wire $22\mask[21:21] - attribute \src "libresoc.v:145312.3-145699.6" - wire $23\mask[22:22] - attribute \src "libresoc.v:145312.3-145699.6" - wire $24\mask[23:23] - attribute \src "libresoc.v:145312.3-145699.6" - wire $25\mask[24:24] - attribute \src "libresoc.v:145312.3-145699.6" - wire $26\mask[25:25] - attribute \src "libresoc.v:145312.3-145699.6" - wire $27\mask[26:26] - attribute \src "libresoc.v:145312.3-145699.6" - wire $28\mask[27:27] - attribute \src "libresoc.v:145312.3-145699.6" - wire $29\mask[28:28] - attribute \src "libresoc.v:145312.3-145699.6" - wire $2\mask[1:1] - attribute \src "libresoc.v:145312.3-145699.6" - wire $30\mask[29:29] - attribute \src "libresoc.v:145312.3-145699.6" - wire $31\mask[30:30] - attribute \src "libresoc.v:145312.3-145699.6" - wire $32\mask[31:31] - attribute \src "libresoc.v:145312.3-145699.6" - wire $33\mask[32:32] - attribute \src "libresoc.v:145312.3-145699.6" - wire $34\mask[33:33] - attribute \src "libresoc.v:145312.3-145699.6" - wire $35\mask[34:34] - attribute \src "libresoc.v:145312.3-145699.6" - wire $36\mask[35:35] - attribute \src "libresoc.v:145312.3-145699.6" - wire $37\mask[36:36] - attribute \src "libresoc.v:145312.3-145699.6" - wire $38\mask[37:37] - attribute \src "libresoc.v:145312.3-145699.6" - wire $39\mask[38:38] - attribute \src "libresoc.v:145312.3-145699.6" - wire $3\mask[2:2] - attribute \src "libresoc.v:145312.3-145699.6" - wire $40\mask[39:39] - attribute \src "libresoc.v:145312.3-145699.6" - wire $41\mask[40:40] - attribute \src "libresoc.v:145312.3-145699.6" - wire $42\mask[41:41] - attribute \src "libresoc.v:145312.3-145699.6" - wire $43\mask[42:42] - attribute \src "libresoc.v:145312.3-145699.6" - wire $44\mask[43:43] - attribute \src "libresoc.v:145312.3-145699.6" - wire $45\mask[44:44] - attribute \src "libresoc.v:145312.3-145699.6" - wire $46\mask[45:45] - attribute \src "libresoc.v:145312.3-145699.6" - wire $47\mask[46:46] - attribute \src "libresoc.v:145312.3-145699.6" - wire $48\mask[47:47] - attribute \src "libresoc.v:145312.3-145699.6" - wire $49\mask[48:48] - attribute \src "libresoc.v:145312.3-145699.6" - wire $4\mask[3:3] - attribute \src "libresoc.v:145312.3-145699.6" - wire $50\mask[49:49] - attribute \src "libresoc.v:145312.3-145699.6" - wire $51\mask[50:50] - attribute \src "libresoc.v:145312.3-145699.6" - wire $52\mask[51:51] - attribute \src "libresoc.v:145312.3-145699.6" - wire $53\mask[52:52] - attribute \src "libresoc.v:145312.3-145699.6" - wire $54\mask[53:53] - attribute \src "libresoc.v:145312.3-145699.6" - wire $55\mask[54:54] - attribute \src "libresoc.v:145312.3-145699.6" - wire $56\mask[55:55] - attribute \src "libresoc.v:145312.3-145699.6" - wire $57\mask[56:56] - attribute \src "libresoc.v:145312.3-145699.6" - wire $58\mask[57:57] - attribute \src "libresoc.v:145312.3-145699.6" - wire $59\mask[58:58] - attribute \src "libresoc.v:145312.3-145699.6" - wire $5\mask[4:4] - attribute \src "libresoc.v:145312.3-145699.6" - wire $60\mask[59:59] - attribute \src "libresoc.v:145312.3-145699.6" - wire $61\mask[60:60] - attribute \src "libresoc.v:145312.3-145699.6" - wire $62\mask[61:61] - attribute \src "libresoc.v:145312.3-145699.6" - wire $63\mask[62:62] - attribute \src "libresoc.v:145312.3-145699.6" - wire $64\mask[63:63] - attribute \src "libresoc.v:145312.3-145699.6" - wire $6\mask[5:5] - attribute \src "libresoc.v:145312.3-145699.6" - wire $7\mask[6:6] - attribute \src "libresoc.v:145312.3-145699.6" - wire $8\mask[7:7] - attribute \src "libresoc.v:145312.3-145699.6" - wire $9\mask[8:8] - attribute \src "libresoc.v:145248.17-145248.96" - wire $gt$libresoc.v:145248$6522_Y - attribute \src "libresoc.v:145249.18-145249.98" - wire $gt$libresoc.v:145249$6523_Y - attribute \src "libresoc.v:145250.19-145250.99" - wire $gt$libresoc.v:145250$6524_Y - attribute \src "libresoc.v:145251.19-145251.99" - wire $gt$libresoc.v:145251$6525_Y - attribute \src "libresoc.v:145252.19-145252.99" - wire $gt$libresoc.v:145252$6526_Y - attribute \src "libresoc.v:145253.19-145253.99" - wire $gt$libresoc.v:145253$6527_Y - attribute \src "libresoc.v:145254.19-145254.99" - wire $gt$libresoc.v:145254$6528_Y - attribute \src "libresoc.v:145255.19-145255.99" - wire $gt$libresoc.v:145255$6529_Y - attribute \src "libresoc.v:145256.19-145256.99" - wire $gt$libresoc.v:145256$6530_Y - attribute \src "libresoc.v:145257.19-145257.99" - wire $gt$libresoc.v:145257$6531_Y - attribute \src "libresoc.v:145258.19-145258.99" - wire $gt$libresoc.v:145258$6532_Y - attribute \src "libresoc.v:145259.18-145259.97" - wire $gt$libresoc.v:145259$6533_Y - attribute \src "libresoc.v:145260.19-145260.99" - wire $gt$libresoc.v:145260$6534_Y - attribute \src "libresoc.v:145261.19-145261.99" - wire $gt$libresoc.v:145261$6535_Y - attribute \src "libresoc.v:145262.19-145262.99" - wire $gt$libresoc.v:145262$6536_Y - attribute \src "libresoc.v:145263.19-145263.99" - wire $gt$libresoc.v:145263$6537_Y - attribute \src "libresoc.v:145264.19-145264.99" - wire $gt$libresoc.v:145264$6538_Y - attribute \src "libresoc.v:145265.18-145265.97" - wire $gt$libresoc.v:145265$6539_Y - attribute \src "libresoc.v:145266.18-145266.97" - wire $gt$libresoc.v:145266$6540_Y - attribute \src "libresoc.v:145267.18-145267.97" - wire $gt$libresoc.v:145267$6541_Y - attribute \src "libresoc.v:145268.17-145268.96" - wire $gt$libresoc.v:145268$6542_Y - attribute \src "libresoc.v:145269.18-145269.97" - wire $gt$libresoc.v:145269$6543_Y - attribute \src "libresoc.v:145270.18-145270.97" - wire $gt$libresoc.v:145270$6544_Y - attribute \src "libresoc.v:145271.18-145271.97" - wire $gt$libresoc.v:145271$6545_Y - attribute \src "libresoc.v:145272.18-145272.97" - wire $gt$libresoc.v:145272$6546_Y - attribute \src "libresoc.v:145273.18-145273.97" - wire $gt$libresoc.v:145273$6547_Y - attribute \src "libresoc.v:145274.18-145274.97" - wire $gt$libresoc.v:145274$6548_Y - attribute \src "libresoc.v:145275.18-145275.97" - wire $gt$libresoc.v:145275$6549_Y - attribute \src "libresoc.v:145276.18-145276.98" - wire $gt$libresoc.v:145276$6550_Y - attribute \src "libresoc.v:145277.18-145277.98" - wire $gt$libresoc.v:145277$6551_Y - attribute \src "libresoc.v:145278.18-145278.98" - wire $gt$libresoc.v:145278$6552_Y - attribute \src "libresoc.v:145279.17-145279.96" - wire $gt$libresoc.v:145279$6553_Y - attribute \src "libresoc.v:145280.18-145280.98" - wire $gt$libresoc.v:145280$6554_Y - attribute \src "libresoc.v:145281.18-145281.98" - wire $gt$libresoc.v:145281$6555_Y - attribute \src "libresoc.v:145282.18-145282.98" - wire $gt$libresoc.v:145282$6556_Y - attribute \src "libresoc.v:145283.18-145283.98" - wire $gt$libresoc.v:145283$6557_Y - attribute \src "libresoc.v:145284.18-145284.98" - wire $gt$libresoc.v:145284$6558_Y - attribute \src "libresoc.v:145285.18-145285.98" - wire $gt$libresoc.v:145285$6559_Y - attribute \src "libresoc.v:145286.18-145286.98" - wire $gt$libresoc.v:145286$6560_Y - attribute \src "libresoc.v:145287.18-145287.98" - wire $gt$libresoc.v:145287$6561_Y - attribute \src "libresoc.v:145288.18-145288.98" - wire $gt$libresoc.v:145288$6562_Y - attribute \src "libresoc.v:145289.18-145289.98" - wire $gt$libresoc.v:145289$6563_Y - attribute \src "libresoc.v:145290.17-145290.96" - wire $gt$libresoc.v:145290$6564_Y - attribute \src "libresoc.v:145291.18-145291.98" - wire $gt$libresoc.v:145291$6565_Y - attribute \src "libresoc.v:145292.18-145292.98" - wire $gt$libresoc.v:145292$6566_Y - attribute \src "libresoc.v:145293.18-145293.98" - wire $gt$libresoc.v:145293$6567_Y - attribute \src "libresoc.v:145294.18-145294.98" - wire $gt$libresoc.v:145294$6568_Y - attribute \src "libresoc.v:145295.18-145295.98" - wire $gt$libresoc.v:145295$6569_Y - attribute \src "libresoc.v:145296.18-145296.98" - wire $gt$libresoc.v:145296$6570_Y - attribute \src "libresoc.v:145297.18-145297.98" - wire $gt$libresoc.v:145297$6571_Y - attribute \src "libresoc.v:145298.18-145298.98" - wire $gt$libresoc.v:145298$6572_Y - attribute \src "libresoc.v:145299.18-145299.98" - wire $gt$libresoc.v:145299$6573_Y - attribute \src "libresoc.v:145300.18-145300.98" - wire $gt$libresoc.v:145300$6574_Y - attribute \src "libresoc.v:145301.17-145301.96" - wire $gt$libresoc.v:145301$6575_Y - attribute \src "libresoc.v:145302.18-145302.98" - wire $gt$libresoc.v:145302$6576_Y - attribute \src "libresoc.v:145303.18-145303.98" - wire $gt$libresoc.v:145303$6577_Y - attribute \src "libresoc.v:145304.18-145304.98" - wire $gt$libresoc.v:145304$6578_Y - attribute \src "libresoc.v:145305.18-145305.98" - wire $gt$libresoc.v:145305$6579_Y - attribute \src "libresoc.v:145306.18-145306.98" - wire $gt$libresoc.v:145306$6580_Y - attribute \src "libresoc.v:145307.18-145307.98" - wire $gt$libresoc.v:145307$6581_Y - attribute \src "libresoc.v:145308.18-145308.98" - wire $gt$libresoc.v:145308$6582_Y - attribute \src "libresoc.v:145309.18-145309.98" - wire $gt$libresoc.v:145309$6583_Y - attribute \src "libresoc.v:145310.18-145310.98" - wire $gt$libresoc.v:145310$6584_Y - attribute \src "libresoc.v:145311.18-145311.98" - wire $gt$libresoc.v:145311$6585_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - wire \$99 - attribute \src "libresoc.v:145114.7-145114.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" - wire width 64 output 1 \mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" - wire width 7 input 2 \shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145248$6522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'100 - connect \Y $gt$libresoc.v:145248$6522_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145249$6523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110001 - connect \Y $gt$libresoc.v:145249$6523_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145250$6524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110010 - connect \Y $gt$libresoc.v:145250$6524_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145251$6525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110011 - connect \Y $gt$libresoc.v:145251$6525_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145252$6526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110100 - connect \Y $gt$libresoc.v:145252$6526_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145253$6527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110101 - connect \Y $gt$libresoc.v:145253$6527_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145254$6528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110110 - connect \Y $gt$libresoc.v:145254$6528_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145255$6529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110111 - connect \Y $gt$libresoc.v:145255$6529_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145256$6530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111000 - connect \Y $gt$libresoc.v:145256$6530_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145257$6531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111001 - connect \Y $gt$libresoc.v:145257$6531_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145258$6532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111010 - connect \Y $gt$libresoc.v:145258$6532_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145259$6533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'101 - connect \Y $gt$libresoc.v:145259$6533_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145260$6534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111011 - connect \Y $gt$libresoc.v:145260$6534_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145261$6535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111100 - connect \Y $gt$libresoc.v:145261$6535_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145262$6536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111101 - connect \Y $gt$libresoc.v:145262$6536_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145263$6537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111110 - connect \Y $gt$libresoc.v:145263$6537_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145264$6538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111111 - connect \Y $gt$libresoc.v:145264$6538_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145265$6539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'110 - connect \Y $gt$libresoc.v:145265$6539_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145266$6540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'111 - connect \Y $gt$libresoc.v:145266$6540_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145267$6541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1000 - connect \Y $gt$libresoc.v:145267$6541_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145268$6542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'0 - connect \Y $gt$libresoc.v:145268$6542_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145269$6543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1001 - connect \Y $gt$libresoc.v:145269$6543_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145270$6544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1010 - connect \Y $gt$libresoc.v:145270$6544_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145271$6545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1011 - connect \Y $gt$libresoc.v:145271$6545_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145272$6546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1100 - connect \Y $gt$libresoc.v:145272$6546_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145273$6547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1101 - connect \Y $gt$libresoc.v:145273$6547_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145274$6548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1110 - connect \Y $gt$libresoc.v:145274$6548_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145275$6549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1111 - connect \Y $gt$libresoc.v:145275$6549_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145276$6550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10000 - connect \Y $gt$libresoc.v:145276$6550_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145277$6551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10001 - connect \Y $gt$libresoc.v:145277$6551_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145278$6552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10010 - connect \Y $gt$libresoc.v:145278$6552_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145279$6553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'1 - connect \Y $gt$libresoc.v:145279$6553_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145280$6554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10011 - connect \Y $gt$libresoc.v:145280$6554_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145281$6555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10100 - connect \Y $gt$libresoc.v:145281$6555_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145282$6556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10101 - connect \Y $gt$libresoc.v:145282$6556_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145283$6557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10110 - connect \Y $gt$libresoc.v:145283$6557_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145284$6558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10111 - connect \Y $gt$libresoc.v:145284$6558_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145285$6559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11000 - connect \Y $gt$libresoc.v:145285$6559_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145286$6560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11001 - connect \Y $gt$libresoc.v:145286$6560_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145287$6561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11010 - connect \Y $gt$libresoc.v:145287$6561_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145288$6562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11011 - connect \Y $gt$libresoc.v:145288$6562_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145289$6563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11100 - connect \Y $gt$libresoc.v:145289$6563_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145290$6564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'10 - connect \Y $gt$libresoc.v:145290$6564_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145291$6565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11101 - connect \Y $gt$libresoc.v:145291$6565_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145292$6566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11110 - connect \Y $gt$libresoc.v:145292$6566_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145293$6567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11111 - connect \Y $gt$libresoc.v:145293$6567_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145294$6568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100000 - connect \Y $gt$libresoc.v:145294$6568_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145295$6569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100001 - connect \Y $gt$libresoc.v:145295$6569_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145296$6570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100010 - connect \Y $gt$libresoc.v:145296$6570_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145297$6571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100011 - connect \Y $gt$libresoc.v:145297$6571_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145298$6572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100100 - connect \Y $gt$libresoc.v:145298$6572_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145299$6573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100101 - connect \Y $gt$libresoc.v:145299$6573_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145300$6574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100110 - connect \Y $gt$libresoc.v:145300$6574_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145301$6575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'11 - connect \Y $gt$libresoc.v:145301$6575_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145302$6576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100111 - connect \Y $gt$libresoc.v:145302$6576_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145303$6577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101000 - connect \Y $gt$libresoc.v:145303$6577_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145304$6578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101001 - connect \Y $gt$libresoc.v:145304$6578_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145305$6579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101010 - connect \Y $gt$libresoc.v:145305$6579_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145306$6580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101011 - connect \Y $gt$libresoc.v:145306$6580_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145307$6581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101100 - connect \Y $gt$libresoc.v:145307$6581_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145308$6582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101101 - connect \Y $gt$libresoc.v:145308$6582_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145309$6583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101110 - connect \Y $gt$libresoc.v:145309$6583_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145310$6584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101111 - connect \Y $gt$libresoc.v:145310$6584_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:145311$6585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110000 - connect \Y $gt$libresoc.v:145311$6585_Y - end - attribute \src "libresoc.v:145114.7-145114.20" - process $proc$libresoc.v:145114$6587 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:145312.3-145699.6" - process $proc$libresoc.v:145312$6586 - assign { } { } - assign { } { } - assign $0\mask[63:0] [0] $1\mask[0:0] - assign $0\mask[63:0] [1] $2\mask[1:1] - assign $0\mask[63:0] [2] $3\mask[2:2] - assign $0\mask[63:0] [3] $4\mask[3:3] - assign $0\mask[63:0] [4] $5\mask[4:4] - assign $0\mask[63:0] [5] $6\mask[5:5] - assign $0\mask[63:0] [6] $7\mask[6:6] - assign $0\mask[63:0] [7] $8\mask[7:7] - assign $0\mask[63:0] [8] $9\mask[8:8] - assign $0\mask[63:0] [9] $10\mask[9:9] - assign $0\mask[63:0] [10] $11\mask[10:10] - assign $0\mask[63:0] [11] $12\mask[11:11] - assign $0\mask[63:0] [12] $13\mask[12:12] - assign $0\mask[63:0] [13] $14\mask[13:13] - assign $0\mask[63:0] [14] $15\mask[14:14] - assign $0\mask[63:0] [15] $16\mask[15:15] - assign $0\mask[63:0] [16] $17\mask[16:16] - assign $0\mask[63:0] [17] $18\mask[17:17] - assign $0\mask[63:0] [18] $19\mask[18:18] - assign $0\mask[63:0] [19] $20\mask[19:19] - assign $0\mask[63:0] [20] $21\mask[20:20] - assign $0\mask[63:0] [21] $22\mask[21:21] - assign $0\mask[63:0] [22] $23\mask[22:22] - assign $0\mask[63:0] [23] $24\mask[23:23] - assign $0\mask[63:0] [24] $25\mask[24:24] - assign $0\mask[63:0] [25] $26\mask[25:25] - assign $0\mask[63:0] [26] $27\mask[26:26] - assign $0\mask[63:0] [27] $28\mask[27:27] - assign $0\mask[63:0] [28] $29\mask[28:28] - assign $0\mask[63:0] [29] $30\mask[29:29] - assign $0\mask[63:0] [30] $31\mask[30:30] - assign $0\mask[63:0] [31] $32\mask[31:31] - assign $0\mask[63:0] [32] $33\mask[32:32] - assign $0\mask[63:0] [33] $34\mask[33:33] - assign $0\mask[63:0] [34] $35\mask[34:34] - assign $0\mask[63:0] [35] $36\mask[35:35] - assign $0\mask[63:0] [36] $37\mask[36:36] - assign $0\mask[63:0] [37] $38\mask[37:37] - assign $0\mask[63:0] [38] $39\mask[38:38] - assign $0\mask[63:0] [39] $40\mask[39:39] - assign $0\mask[63:0] [40] $41\mask[40:40] - assign $0\mask[63:0] [41] $42\mask[41:41] - assign $0\mask[63:0] [42] $43\mask[42:42] - assign $0\mask[63:0] [43] $44\mask[43:43] - assign $0\mask[63:0] [44] $45\mask[44:44] - assign $0\mask[63:0] [45] $46\mask[45:45] - assign $0\mask[63:0] [46] $47\mask[46:46] - assign $0\mask[63:0] [47] $48\mask[47:47] - assign $0\mask[63:0] [48] $49\mask[48:48] - assign $0\mask[63:0] [49] $50\mask[49:49] - assign $0\mask[63:0] [50] $51\mask[50:50] - assign $0\mask[63:0] [51] $52\mask[51:51] - assign $0\mask[63:0] [52] $53\mask[52:52] - assign $0\mask[63:0] [53] $54\mask[53:53] - assign $0\mask[63:0] [54] $55\mask[54:54] - assign $0\mask[63:0] [55] $56\mask[55:55] - assign $0\mask[63:0] [56] $57\mask[56:56] - assign $0\mask[63:0] [57] $58\mask[57:57] - assign $0\mask[63:0] [58] $59\mask[58:58] - assign $0\mask[63:0] [59] $60\mask[59:59] - assign $0\mask[63:0] [60] $61\mask[60:60] - assign $0\mask[63:0] [61] $62\mask[61:61] - assign $0\mask[63:0] [62] $63\mask[62:62] - assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:145313.5-145313.29" - switch \initial - attribute \src "libresoc.v:145313.9-145313.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\mask[0:0] 1'1 - case - assign $1\mask[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\mask[1:1] 1'1 - case - assign $2\mask[1:1] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\mask[2:2] 1'1 - case - assign $3\mask[2:2] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\mask[3:3] 1'1 - case - assign $4\mask[3:3] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\mask[4:4] 1'1 - case - assign $5\mask[4:4] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\mask[5:5] 1'1 - case - assign $6\mask[5:5] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\mask[6:6] 1'1 - case - assign $7\mask[6:6] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\mask[7:7] 1'1 - case - assign $8\mask[7:7] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$17 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\mask[8:8] 1'1 - case - assign $9\mask[8:8] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\mask[9:9] 1'1 - case - assign $10\mask[9:9] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$21 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\mask[10:10] 1'1 - case - assign $11\mask[10:10] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $12\mask[11:11] 1'1 - case - assign $12\mask[11:11] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $13\mask[12:12] 1'1 - case - assign $13\mask[12:12] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $14\mask[13:13] 1'1 - case - assign $14\mask[13:13] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $15\mask[14:14] 1'1 - case - assign $15\mask[14:14] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$31 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $16\mask[15:15] 1'1 - case - assign $16\mask[15:15] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$33 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $17\mask[16:16] 1'1 - case - assign $17\mask[16:16] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$35 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $18\mask[17:17] 1'1 - case - assign $18\mask[17:17] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$37 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $19\mask[18:18] 1'1 - case - assign $19\mask[18:18] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$39 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $20\mask[19:19] 1'1 - case - assign $20\mask[19:19] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$41 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $21\mask[20:20] 1'1 - case - assign $21\mask[20:20] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$43 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $22\mask[21:21] 1'1 - case - assign $22\mask[21:21] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$45 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $23\mask[22:22] 1'1 - case - assign $23\mask[22:22] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$47 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $24\mask[23:23] 1'1 - case - assign $24\mask[23:23] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$49 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $25\mask[24:24] 1'1 - case - assign $25\mask[24:24] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$51 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $26\mask[25:25] 1'1 - case - assign $26\mask[25:25] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$53 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $27\mask[26:26] 1'1 - case - assign $27\mask[26:26] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$55 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $28\mask[27:27] 1'1 - case - assign $28\mask[27:27] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$57 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $29\mask[28:28] 1'1 - case - assign $29\mask[28:28] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$59 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $30\mask[29:29] 1'1 - case - assign $30\mask[29:29] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$61 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $31\mask[30:30] 1'1 - case - assign $31\mask[30:30] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$63 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $32\mask[31:31] 1'1 - case - assign $32\mask[31:31] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$65 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $33\mask[32:32] 1'1 - case - assign $33\mask[32:32] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$67 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $34\mask[33:33] 1'1 - case - assign $34\mask[33:33] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$69 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $35\mask[34:34] 1'1 - case - assign $35\mask[34:34] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$71 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $36\mask[35:35] 1'1 - case - assign $36\mask[35:35] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$73 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $37\mask[36:36] 1'1 - case - assign $37\mask[36:36] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$75 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $38\mask[37:37] 1'1 - case - assign $38\mask[37:37] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $39\mask[38:38] 1'1 - case - assign $39\mask[38:38] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$79 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $40\mask[39:39] 1'1 - case - assign $40\mask[39:39] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$81 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $41\mask[40:40] 1'1 - case - assign $41\mask[40:40] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$83 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $42\mask[41:41] 1'1 - case - assign $42\mask[41:41] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$85 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $43\mask[42:42] 1'1 - case - assign $43\mask[42:42] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$87 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $44\mask[43:43] 1'1 - case - assign $44\mask[43:43] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$89 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $45\mask[44:44] 1'1 - case - assign $45\mask[44:44] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$91 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $46\mask[45:45] 1'1 - case - assign $46\mask[45:45] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $47\mask[46:46] 1'1 - case - assign $47\mask[46:46] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$95 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $48\mask[47:47] 1'1 - case - assign $48\mask[47:47] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$97 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $49\mask[48:48] 1'1 - case - assign $49\mask[48:48] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$99 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $50\mask[49:49] 1'1 - case - assign $50\mask[49:49] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$101 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $51\mask[50:50] 1'1 - case - assign $51\mask[50:50] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$103 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $52\mask[51:51] 1'1 - case - assign $52\mask[51:51] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$105 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $53\mask[52:52] 1'1 - case - assign $53\mask[52:52] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$107 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $54\mask[53:53] 1'1 - case - assign $54\mask[53:53] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$109 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $55\mask[54:54] 1'1 - case - assign $55\mask[54:54] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$111 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $56\mask[55:55] 1'1 - case - assign $56\mask[55:55] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$113 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $57\mask[56:56] 1'1 - case - assign $57\mask[56:56] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$115 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $58\mask[57:57] 1'1 - case - assign $58\mask[57:57] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$117 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $59\mask[58:58] 1'1 - case - assign $59\mask[58:58] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$119 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $60\mask[59:59] 1'1 - case - assign $60\mask[59:59] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$121 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $61\mask[60:60] 1'1 - case - assign $61\mask[60:60] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$123 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $62\mask[61:61] 1'1 - case - assign $62\mask[61:61] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$125 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $63\mask[62:62] 1'1 - case - assign $63\mask[62:62] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - switch \$127 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $64\mask[63:63] 1'1 - case - assign $64\mask[63:63] 1'0 - end - sync always - update \mask $0\mask[63:0] - end - connect \$9 $gt$libresoc.v:145248$6522_Y - connect \$99 $gt$libresoc.v:145249$6523_Y - connect \$101 $gt$libresoc.v:145250$6524_Y - connect \$103 $gt$libresoc.v:145251$6525_Y - connect \$105 $gt$libresoc.v:145252$6526_Y - connect \$107 $gt$libresoc.v:145253$6527_Y - connect \$109 $gt$libresoc.v:145254$6528_Y - connect \$111 $gt$libresoc.v:145255$6529_Y - connect \$113 $gt$libresoc.v:145256$6530_Y - connect \$115 $gt$libresoc.v:145257$6531_Y - connect \$117 $gt$libresoc.v:145258$6532_Y - connect \$11 $gt$libresoc.v:145259$6533_Y - connect \$119 $gt$libresoc.v:145260$6534_Y - connect \$121 $gt$libresoc.v:145261$6535_Y - connect \$123 $gt$libresoc.v:145262$6536_Y - connect \$125 $gt$libresoc.v:145263$6537_Y - connect \$127 $gt$libresoc.v:145264$6538_Y - connect \$13 $gt$libresoc.v:145265$6539_Y - connect \$15 $gt$libresoc.v:145266$6540_Y - connect \$17 $gt$libresoc.v:145267$6541_Y - connect \$1 $gt$libresoc.v:145268$6542_Y - connect \$19 $gt$libresoc.v:145269$6543_Y - connect \$21 $gt$libresoc.v:145270$6544_Y - connect \$23 $gt$libresoc.v:145271$6545_Y - connect \$25 $gt$libresoc.v:145272$6546_Y - connect \$27 $gt$libresoc.v:145273$6547_Y - connect \$29 $gt$libresoc.v:145274$6548_Y - connect \$31 $gt$libresoc.v:145275$6549_Y - connect \$33 $gt$libresoc.v:145276$6550_Y - connect \$35 $gt$libresoc.v:145277$6551_Y - connect \$37 $gt$libresoc.v:145278$6552_Y - connect \$3 $gt$libresoc.v:145279$6553_Y - connect \$39 $gt$libresoc.v:145280$6554_Y - connect \$41 $gt$libresoc.v:145281$6555_Y - connect \$43 $gt$libresoc.v:145282$6556_Y - connect \$45 $gt$libresoc.v:145283$6557_Y - connect \$47 $gt$libresoc.v:145284$6558_Y - connect \$49 $gt$libresoc.v:145285$6559_Y - connect \$51 $gt$libresoc.v:145286$6560_Y - connect \$53 $gt$libresoc.v:145287$6561_Y - connect \$55 $gt$libresoc.v:145288$6562_Y - connect \$57 $gt$libresoc.v:145289$6563_Y - connect \$5 $gt$libresoc.v:145290$6564_Y - connect \$59 $gt$libresoc.v:145291$6565_Y - connect \$61 $gt$libresoc.v:145292$6566_Y - connect \$63 $gt$libresoc.v:145293$6567_Y - connect \$65 $gt$libresoc.v:145294$6568_Y - connect \$67 $gt$libresoc.v:145295$6569_Y - connect \$69 $gt$libresoc.v:145296$6570_Y - connect \$71 $gt$libresoc.v:145297$6571_Y - connect \$73 $gt$libresoc.v:145298$6572_Y - connect \$75 $gt$libresoc.v:145299$6573_Y - connect \$77 $gt$libresoc.v:145300$6574_Y - connect \$7 $gt$libresoc.v:145301$6575_Y - connect \$79 $gt$libresoc.v:145302$6576_Y - connect \$81 $gt$libresoc.v:145303$6577_Y - connect \$83 $gt$libresoc.v:145304$6578_Y - connect \$85 $gt$libresoc.v:145305$6579_Y - connect \$87 $gt$libresoc.v:145306$6580_Y - connect \$89 $gt$libresoc.v:145307$6581_Y - connect \$91 $gt$libresoc.v:145308$6582_Y - connect \$93 $gt$libresoc.v:145309$6583_Y - connect \$95 $gt$libresoc.v:145310$6584_Y - connect \$97 $gt$libresoc.v:145311$6585_Y -end -attribute \src "libresoc.v:145704.1-145733.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" -attribute \generator "nMigen" -module \lenexp - attribute \src "libresoc.v:145728.17-145728.101" - wire width 64 $extend$libresoc.v:145728$6591_Y - attribute \src "libresoc.v:145728.17-145728.101" - wire width 64 $pos$libresoc.v:145728$6592_Y - attribute \src "libresoc.v:145725.17-145725.111" - wire width 20 $sshl$libresoc.v:145725$6588_Y - attribute \src "libresoc.v:145727.17-145727.113" - wire width 32 $sshl$libresoc.v:145727$6590_Y - attribute \src "libresoc.v:145726.17-145726.107" - wire width 21 $sub$libresoc.v:145726$6589_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 21 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 20 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 21 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - wire width 64 \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - wire width 32 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" - wire width 4 input 1 \addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" - wire width 17 \binlen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" - wire width 4 input 4 \len_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" - wire width 64 output 2 \lexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" - wire width 176 output 3 \rexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:145728$6591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \$7 - connect \Y $extend$libresoc.v:145728$6591_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:145728$6592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:145728$6591_Y - connect \Y $pos$libresoc.v:145728$6592_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:145725$6588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 20 - connect \A 5'00001 - connect \B \len_i - connect \Y $sshl$libresoc.v:145725$6588_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:145727$6590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 17 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 32 - connect \A \binlen - connect \B \addr_i - connect \Y $sshl$libresoc.v:145727$6590_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:145726$6589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 21 - connect \A \$2 - connect \B 1'1 - connect \Y $sub$libresoc.v:145726$6589_Y - end - connect \$2 $sshl$libresoc.v:145725$6588_Y - connect \$4 $sub$libresoc.v:145726$6589_Y - connect \$7 $sshl$libresoc.v:145727$6590_Y - connect \$6 $pos$libresoc.v:145728$6592_Y - connect \$1 \$4 - connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } - connect \lexp_o \$6 - connect \binlen \$4 [16:0] -end -attribute \src "libresoc.v:145737.1-145795.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" -attribute \generator "nMigen" -module \lod_l - attribute \src "libresoc.v:145738.7-145738.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:145783.3-145791.6" - wire $0\q_int$next[0:0]$6603 - attribute \src "libresoc.v:145781.3-145782.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:145783.3-145791.6" - wire $1\q_int$next[0:0]$6604 - attribute \src "libresoc.v:145760.7-145760.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:145773.17-145773.96" - wire $and$libresoc.v:145773$6593_Y - attribute \src "libresoc.v:145778.17-145778.96" - wire $and$libresoc.v:145778$6598_Y - attribute \src "libresoc.v:145775.18-145775.93" - wire $not$libresoc.v:145775$6595_Y - attribute \src "libresoc.v:145777.17-145777.92" - wire $not$libresoc.v:145777$6597_Y - attribute \src "libresoc.v:145780.17-145780.92" - wire $not$libresoc.v:145780$6600_Y - attribute \src "libresoc.v:145774.18-145774.98" - wire $or$libresoc.v:145774$6594_Y - attribute \src "libresoc.v:145776.18-145776.99" - wire $or$libresoc.v:145776$6596_Y - attribute \src "libresoc.v:145779.17-145779.97" - wire $or$libresoc.v:145779$6599_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:145738.7-145738.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \q_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire output 4 \qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:145773$6593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:145773$6593_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:145778$6598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:145778$6598_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:145775$6595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lod - connect \Y $not$libresoc.v:145775$6595_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:145777$6597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lod - connect \Y $not$libresoc.v:145777$6597_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:145780$6600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lod - connect \Y $not$libresoc.v:145780$6600_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:145774$6594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_lod - connect \Y $or$libresoc.v:145774$6594_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:145776$6596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lod - connect \B \q_int - connect \Y $or$libresoc.v:145776$6596_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:145779$6599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_lod - connect \Y $or$libresoc.v:145779$6599_Y - end - attribute \src "libresoc.v:145738.7-145738.20" - process $proc$libresoc.v:145738$6605 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:145760.7-145760.19" - process $proc$libresoc.v:145760$6606 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:145781.3-145782.27" - process $proc$libresoc.v:145781$6601 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:145783.3-145791.6" - process $proc$libresoc.v:145783$6602 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$6603 $1\q_int$next[0:0]$6604 - attribute \src "libresoc.v:145784.5-145784.29" - switch \initial - attribute \src "libresoc.v:145784.9-145784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$6604 1'0 - case - assign $1\q_int$next[0:0]$6604 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$6603 - end - connect \$9 $and$libresoc.v:145773$6593_Y - connect \$11 $or$libresoc.v:145774$6594_Y - connect \$13 $not$libresoc.v:145775$6595_Y - connect \$15 $or$libresoc.v:145776$6596_Y - connect \$1 $not$libresoc.v:145777$6597_Y - connect \$3 $and$libresoc.v:145778$6598_Y - connect \$5 $or$libresoc.v:145779$6599_Y - connect \$7 $not$libresoc.v:145780$6600_Y - connect \qlq_lod \$15 - connect \qn_lod \$13 - connect \q_lod \$11 -end -attribute \src "libresoc.v:145799.1-146915.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" -attribute \generator "nMigen" -module \logical0 - attribute \src "libresoc.v:146540.3-146541.24" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:146538.3-146539.44" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:146845.3-146853.6" - wire $0\alu_l_r_alu$next[0:0]$6807 - attribute \src "libresoc.v:146462.3-146463.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6736 - attribute \src "libresoc.v:146512.3-146513.83" - wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 13 $0\alu_logical0_logical_op__fn_unit$next[12:0]$6737 - attribute \src "libresoc.v:146482.3-146483.81" - wire width 13 $0\alu_logical0_logical_op__fn_unit[12:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6738 - attribute \src "libresoc.v:146484.3-146485.95" - wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6739 - attribute \src "libresoc.v:146486.3-146487.91" - wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6740 - attribute \src "libresoc.v:146500.3-146501.89" - wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6741 - attribute \src "libresoc.v:146514.3-146515.75" - wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6742 - attribute \src "libresoc.v:146480.3-146481.85" - wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6743 - attribute \src "libresoc.v:146496.3-146497.85" - wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6744 - attribute \src "libresoc.v:146502.3-146503.87" - wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6745 - attribute \src "libresoc.v:146508.3-146509.83" - wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6746 - attribute \src "libresoc.v:146510.3-146511.85" - wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6747 - attribute \src "libresoc.v:146492.3-146493.79" - wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6748 - attribute \src "libresoc.v:146494.3-146495.79" - wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6749 - attribute \src "libresoc.v:146506.3-146507.91" - wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6750 - attribute \src "libresoc.v:146490.3-146491.79" - wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6751 - attribute \src "libresoc.v:146488.3-146489.79" - wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6752 - attribute \src "libresoc.v:146504.3-146505.85" - wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6753 - attribute \src "libresoc.v:146498.3-146499.79" - wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:146836.3-146844.6" - wire $0\alui_l_r_alui$next[0:0]$6804 - attribute \src "libresoc.v:146464.3-146465.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:146762.3-146783.6" - wire width 64 $0\data_r0__o$next[63:0]$6779 - attribute \src "libresoc.v:146476.3-146477.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:146762.3-146783.6" - wire $0\data_r0__o_ok$next[0:0]$6780 - attribute \src "libresoc.v:146478.3-146479.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:146784.3-146805.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$6787 - attribute \src "libresoc.v:146472.3-146473.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:146784.3-146805.6" - wire $0\data_r1__cr_a_ok$next[0:0]$6788 - attribute \src "libresoc.v:146474.3-146475.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:146854.3-146863.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:146864.3-146873.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:145800.7-145800.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:146678.3-146686.6" - wire $0\opc_l_r_opc$next[0:0]$6721 - attribute \src "libresoc.v:146524.3-146525.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:146669.3-146677.6" - wire $0\opc_l_s_opc$next[0:0]$6718 - attribute \src "libresoc.v:146526.3-146527.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:146874.3-146882.6" - wire width 2 $0\prev_wr_go$next[1:0]$6812 - attribute \src "libresoc.v:146536.3-146537.37" - wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:146623.3-146632.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:146714.3-146722.6" - wire width 2 $0\req_l_r_req$next[1:0]$6733 - attribute \src "libresoc.v:146516.3-146517.39" - wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:146705.3-146713.6" - wire width 2 $0\req_l_s_req$next[1:0]$6730 - attribute \src "libresoc.v:146518.3-146519.39" - wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:146642.3-146650.6" - wire $0\rok_l_r_rdok$next[0:0]$6709 - attribute \src "libresoc.v:146532.3-146533.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:146633.3-146641.6" - wire $0\rok_l_s_rdok$next[0:0]$6706 - attribute \src "libresoc.v:146534.3-146535.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:146660.3-146668.6" - wire $0\rst_l_r_rst$next[0:0]$6715 - attribute \src "libresoc.v:146528.3-146529.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:146651.3-146659.6" - wire $0\rst_l_s_rst$next[0:0]$6712 - attribute \src "libresoc.v:146530.3-146531.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:146696.3-146704.6" - wire width 3 $0\src_l_r_src$next[2:0]$6727 - attribute \src "libresoc.v:146520.3-146521.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:146687.3-146695.6" - wire width 3 $0\src_l_s_src$next[2:0]$6724 - attribute \src "libresoc.v:146522.3-146523.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:146806.3-146815.6" - wire width 64 $0\src_r0$next[63:0]$6795 - attribute \src "libresoc.v:146470.3-146471.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:146816.3-146825.6" - wire width 64 $0\src_r1$next[63:0]$6798 - attribute \src "libresoc.v:146468.3-146469.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:146826.3-146835.6" - wire $0\src_r2$next[0:0]$6801 - attribute \src "libresoc.v:146466.3-146467.29" - wire $0\src_r2[0:0] - attribute \src "libresoc.v:145918.7-145918.24" - wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:145928.7-145928.26" - wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:146845.3-146853.6" - wire $1\alu_l_r_alu$next[0:0]$6808 - attribute \src "libresoc.v:145936.7-145936.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6754 - attribute \src "libresoc.v:145944.13-145944.53" - wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 13 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6755 - attribute \src "libresoc.v:145962.14-145962.57" - wire width 13 $1\alu_logical0_logical_op__fn_unit[12:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6756 - attribute \src "libresoc.v:145966.14-145966.76" - wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6757 - attribute \src "libresoc.v:145970.7-145970.51" - wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6758 - attribute \src "libresoc.v:145978.13-145978.56" - wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6759 - attribute \src "libresoc.v:145982.14-145982.51" - wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6760 - attribute \src "libresoc.v:146060.13-146060.55" - wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6761 - attribute \src "libresoc.v:146064.7-146064.48" - wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6762 - attribute \src "libresoc.v:146068.7-146068.49" - wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6763 - attribute \src "libresoc.v:146072.7-146072.47" - wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6764 - attribute \src "libresoc.v:146076.7-146076.48" - wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6765 - attribute \src "libresoc.v:146080.7-146080.45" - wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6766 - attribute \src "libresoc.v:146084.7-146084.45" - wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6767 - attribute \src "libresoc.v:146088.7-146088.51" - wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6768 - attribute \src "libresoc.v:146092.7-146092.45" - wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6769 - attribute \src "libresoc.v:146096.7-146096.45" - wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6770 - attribute \src "libresoc.v:146100.7-146100.48" - wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:146723.3-146761.6" - wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6771 - attribute \src "libresoc.v:146104.7-146104.45" - wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:146836.3-146844.6" - wire $1\alui_l_r_alui$next[0:0]$6805 - attribute \src "libresoc.v:146130.7-146130.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:146762.3-146783.6" - wire width 64 $1\data_r0__o$next[63:0]$6781 - attribute \src "libresoc.v:146164.14-146164.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:146762.3-146783.6" - wire $1\data_r0__o_ok$next[0:0]$6782 - attribute \src "libresoc.v:146168.7-146168.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:146784.3-146805.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$6789 - attribute \src "libresoc.v:146172.13-146172.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:146784.3-146805.6" - wire $1\data_r1__cr_a_ok$next[0:0]$6790 - attribute \src "libresoc.v:146176.7-146176.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:146854.3-146863.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:146864.3-146873.6" - wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:146678.3-146686.6" - wire $1\opc_l_r_opc$next[0:0]$6722 - attribute \src "libresoc.v:146190.7-146190.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:146669.3-146677.6" - wire $1\opc_l_s_opc$next[0:0]$6719 - attribute \src "libresoc.v:146194.7-146194.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:146874.3-146882.6" - wire width 2 $1\prev_wr_go$next[1:0]$6813 - attribute \src "libresoc.v:146326.13-146326.30" - wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:146623.3-146632.6" - wire $1\req_done[0:0] - attribute \src "libresoc.v:146714.3-146722.6" - wire width 2 $1\req_l_r_req$next[1:0]$6734 - attribute \src "libresoc.v:146334.13-146334.31" - wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:146705.3-146713.6" - wire width 2 $1\req_l_s_req$next[1:0]$6731 - attribute \src "libresoc.v:146338.13-146338.31" - wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:146642.3-146650.6" - wire $1\rok_l_r_rdok$next[0:0]$6710 - attribute \src "libresoc.v:146350.7-146350.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:146633.3-146641.6" - wire $1\rok_l_s_rdok$next[0:0]$6707 - attribute \src "libresoc.v:146354.7-146354.26" - wire $1\rok_l_s_rdok[0:0] - attribute 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\enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_logical0_logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_logical0_logical_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire \alu_logical0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire \alu_logical0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \alu_logical0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire \alu_logical0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire \alu_logical0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_logical0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_logical0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \alu_logical0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 2 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 21 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 20 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 24 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 23 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 22 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 30 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 29 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 2 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 31 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 33 \dest2_o - attribute \src "libresoc.v:145800.7-145800.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 18 \oper_i_alu_logical0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_logical0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \oper_i_alu_logical0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_logical0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 12 \oper_i_alu_logical0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 19 \oper_i_alu_logical0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 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\$33 - connect \Y $or$libresoc.v:146428$6630_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:146439$6641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:146439$6641_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:146440$6642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:146440$6642_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:146441$6643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_wr__go_i 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:146427$6629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:146427$6629_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:146449$6651 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:146449$6651_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:146450$6652 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:146450$6652_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:146451$6653 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:146451$6653_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:146453$6655 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_logical0_logical_op__imm_data__data - connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:146453$6655_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:146454$6656 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$libresoc.v:146454$6656_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:146455$6657 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$80 - connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:146455$6657_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:146456$6658 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:146456$6658_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:146542.14-146548.4" - cell \alu_l$61 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:146549.16-146581.4" - cell \alu_logical0 \alu_logical0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_logical0_cr_a - connect \cr_a_ok \cr_a_ok - connect \logical_op__data_len \alu_logical0_logical_op__data_len - connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit - connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data - connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok - connect \logical_op__input_carry \alu_logical0_logical_op__input_carry - connect \logical_op__insn \alu_logical0_logical_op__insn - connect \logical_op__insn_type \alu_logical0_logical_op__insn_type - connect \logical_op__invert_in \alu_logical0_logical_op__invert_in - connect \logical_op__invert_out \alu_logical0_logical_op__invert_out - connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit - connect \logical_op__is_signed \alu_logical0_logical_op__is_signed - connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe - connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok - connect \logical_op__output_carry \alu_logical0_logical_op__output_carry - connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok - connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc - connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 - connect \logical_op__zero_a \alu_logical0_logical_op__zero_a - connect \n_ready_i \alu_logical0_n_ready_i - connect \n_valid_o \alu_logical0_n_valid_o - connect \o \alu_logical0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_logical0_p_ready_o - connect \p_valid_i \alu_logical0_p_valid_i - connect \ra \alu_logical0_ra - connect \rb \alu_logical0_rb - connect \xer_so \alu_logical0_xer_so - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:146582.15-146588.4" - cell \alui_l$60 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:146589.14-146595.4" - cell \opc_l$56 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:146596.14-146602.4" - cell \req_l$57 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:146603.14-146609.4" - cell \rok_l$59 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:146610.14-146615.4" - cell \rst_l$58 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:146616.14-146622.4" - cell \src_l$55 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "libresoc.v:145800.7-145800.20" - process $proc$libresoc.v:145800$6814 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:145918.7-145918.24" - process $proc$libresoc.v:145918$6815 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:145928.7-145928.26" - process $proc$libresoc.v:145928$6816 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:145936.7-145936.25" - process $proc$libresoc.v:145936$6817 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:145944.13-145944.53" - process $proc$libresoc.v:145944$6818 - assign { } { } - assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] - end - attribute \src "libresoc.v:145962.14-145962.57" - process $proc$libresoc.v:145962$6819 - assign { } { } - assign $1\alu_logical0_logical_op__fn_unit[12:0] 13'0000000000000 - sync always - sync init - update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[12:0] - end - attribute \src "libresoc.v:145966.14-145966.76" - process $proc$libresoc.v:145966$6820 - assign { } { } - assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:145970.7-145970.51" - process $proc$libresoc.v:145970$6821 - assign { } { } - assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:145978.13-145978.56" - process $proc$libresoc.v:145978$6822 - assign { } { } - assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:145982.14-145982.51" - process $proc$libresoc.v:145982$6823 - assign { } { } - assign $1\alu_logical0_logical_op__insn[31:0] 0 - sync always - sync init - update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] - end - attribute \src "libresoc.v:146060.13-146060.55" - process $proc$libresoc.v:146060$6824 - assign { } { } - assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:146064.7-146064.48" - process $proc$libresoc.v:146064$6825 - assign { } { } - assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:146068.7-146068.49" - process $proc$libresoc.v:146068$6826 - assign { } { } - assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:146072.7-146072.47" - process $proc$libresoc.v:146072$6827 - assign { } { } - assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:146076.7-146076.48" - process $proc$libresoc.v:146076$6828 - assign { } { } - assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:146080.7-146080.45" - process $proc$libresoc.v:146080$6829 - assign { } { } - assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:146084.7-146084.45" - process $proc$libresoc.v:146084$6830 - assign { } { } - assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:146088.7-146088.51" - process $proc$libresoc.v:146088$6831 - assign { } { } - assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:146092.7-146092.45" - process $proc$libresoc.v:146092$6832 - assign { } { } - assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:146096.7-146096.45" - process $proc$libresoc.v:146096$6833 - assign { } { } - assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:146100.7-146100.48" - process $proc$libresoc.v:146100$6834 - assign { } { } - assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:146104.7-146104.45" - process $proc$libresoc.v:146104$6835 - assign { } { } - assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:146130.7-146130.27" - process $proc$libresoc.v:146130$6836 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:146164.14-146164.47" - process $proc$libresoc.v:146164$6837 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "libresoc.v:146168.7-146168.27" - process $proc$libresoc.v:146168$6838 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:146172.13-146172.33" - process $proc$libresoc.v:146172$6839 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:146176.7-146176.30" - process $proc$libresoc.v:146176$6840 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:146190.7-146190.25" - process $proc$libresoc.v:146190$6841 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:146194.7-146194.25" - process $proc$libresoc.v:146194$6842 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:146326.13-146326.30" - process $proc$libresoc.v:146326$6843 - assign { } { } - assign $1\prev_wr_go[1:0] 2'00 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[1:0] - end - attribute \src "libresoc.v:146334.13-146334.31" - process $proc$libresoc.v:146334$6844 - assign { } { } - assign $1\req_l_r_req[1:0] 2'11 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[1:0] - end - attribute \src "libresoc.v:146338.13-146338.31" - process $proc$libresoc.v:146338$6845 - assign { } { } - assign $1\req_l_s_req[1:0] 2'00 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[1:0] - end - attribute \src "libresoc.v:146350.7-146350.26" - process $proc$libresoc.v:146350$6846 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:146354.7-146354.26" - process $proc$libresoc.v:146354$6847 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:146358.7-146358.25" - process $proc$libresoc.v:146358$6848 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:146362.7-146362.25" - process $proc$libresoc.v:146362$6849 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:146376.13-146376.31" - process $proc$libresoc.v:146376$6850 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "libresoc.v:146380.13-146380.31" - process $proc$libresoc.v:146380$6851 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "libresoc.v:146388.14-146388.43" - process $proc$libresoc.v:146388$6852 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "libresoc.v:146392.14-146392.43" - process $proc$libresoc.v:146392$6853 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "libresoc.v:146396.7-146396.20" - process $proc$libresoc.v:146396$6854 - assign { } { } - assign $1\src_r2[0:0] 1'0 - sync always - sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "libresoc.v:146462.3-146463.39" - process $proc$libresoc.v:146462$6664 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:146464.3-146465.43" - process $proc$libresoc.v:146464$6665 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:146466.3-146467.29" - process $proc$libresoc.v:146466$6666 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "libresoc.v:146468.3-146469.29" - process $proc$libresoc.v:146468$6667 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:146470.3-146471.29" - process $proc$libresoc.v:146470$6668 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:146472.3-146473.43" - process $proc$libresoc.v:146472$6669 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:146474.3-146475.49" - process $proc$libresoc.v:146474$6670 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:146476.3-146477.37" - process $proc$libresoc.v:146476$6671 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "libresoc.v:146478.3-146479.43" - process $proc$libresoc.v:146478$6672 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:146480.3-146481.85" - process $proc$libresoc.v:146480$6673 - assign { } { } - assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:146482.3-146483.81" - process $proc$libresoc.v:146482$6674 - assign { } { } - assign $0\alu_logical0_logical_op__fn_unit[12:0] \alu_logical0_logical_op__fn_unit$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[12:0] - end - attribute \src "libresoc.v:146484.3-146485.95" - process $proc$libresoc.v:146484$6675 - assign { } { } - assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:146486.3-146487.91" - process $proc$libresoc.v:146486$6676 - assign { } { } - assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:146488.3-146489.79" - process $proc$libresoc.v:146488$6677 - assign { } { } - assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:146490.3-146491.79" - process $proc$libresoc.v:146490$6678 - assign { } { } - assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:146492.3-146493.79" - process $proc$libresoc.v:146492$6679 - assign { } { } - assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:146494.3-146495.79" - process $proc$libresoc.v:146494$6680 - assign { } { } - assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:146496.3-146497.85" - process $proc$libresoc.v:146496$6681 - assign { } { } - assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:146498.3-146499.79" - process $proc$libresoc.v:146498$6682 - assign { } { } - assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:146500.3-146501.89" - process $proc$libresoc.v:146500$6683 - assign { } { } - assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:146502.3-146503.87" - process $proc$libresoc.v:146502$6684 - assign { } { } - assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:146504.3-146505.85" - process $proc$libresoc.v:146504$6685 - assign { } { } - assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:146506.3-146507.91" - process $proc$libresoc.v:146506$6686 - assign { } { } - assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:146508.3-146509.83" - process $proc$libresoc.v:146508$6687 - assign { } { } - assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:146510.3-146511.85" - process $proc$libresoc.v:146510$6688 - assign { } { } - assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:146512.3-146513.83" - process $proc$libresoc.v:146512$6689 - assign { } { } - assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] - end - attribute \src "libresoc.v:146514.3-146515.75" - process $proc$libresoc.v:146514$6690 - assign { } { } - assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] - end - attribute \src "libresoc.v:146516.3-146517.39" - process $proc$libresoc.v:146516$6691 - assign { } { } - assign $0\req_l_r_req[1:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[1:0] - end - attribute \src "libresoc.v:146518.3-146519.39" - process $proc$libresoc.v:146518$6692 - assign { } { } - assign $0\req_l_s_req[1:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[1:0] - end - attribute \src "libresoc.v:146520.3-146521.39" - process $proc$libresoc.v:146520$6693 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "libresoc.v:146522.3-146523.39" - process $proc$libresoc.v:146522$6694 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "libresoc.v:146524.3-146525.39" - process $proc$libresoc.v:146524$6695 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:146526.3-146527.39" - process $proc$libresoc.v:146526$6696 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:146528.3-146529.39" - process $proc$libresoc.v:146528$6697 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:146530.3-146531.39" - process $proc$libresoc.v:146530$6698 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:146532.3-146533.41" - process $proc$libresoc.v:146532$6699 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:146534.3-146535.41" - process $proc$libresoc.v:146534$6700 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:146536.3-146537.37" - process $proc$libresoc.v:146536$6701 - assign { } { } - assign $0\prev_wr_go[1:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[1:0] - end - attribute \src "libresoc.v:146538.3-146539.44" - process $proc$libresoc.v:146538$6702 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:146540.3-146541.24" - process $proc$libresoc.v:146540$6703 - assign { } { } - assign $0\all_rd_dly[0:0] \$9 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "libresoc.v:146623.3-146632.6" - process $proc$libresoc.v:146623$6704 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:146624.5-146624.29" - switch \initial - attribute \src "libresoc.v:146624.9-146624.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$53 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$45 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "libresoc.v:146633.3-146641.6" - process $proc$libresoc.v:146633$6705 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$6706 $1\rok_l_s_rdok$next[0:0]$6707 - attribute \src "libresoc.v:146634.5-146634.29" - switch \initial - attribute \src "libresoc.v:146634.9-146634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$6707 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$6707 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6706 - end - attribute \src "libresoc.v:146642.3-146650.6" - process $proc$libresoc.v:146642$6708 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$6709 $1\rok_l_r_rdok$next[0:0]$6710 - attribute \src "libresoc.v:146643.5-146643.29" - switch \initial - attribute \src "libresoc.v:146643.9-146643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$6710 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$6710 \$63 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6709 - end - attribute \src "libresoc.v:146651.3-146659.6" - process $proc$libresoc.v:146651$6711 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$6712 $1\rst_l_s_rst$next[0:0]$6713 - attribute \src "libresoc.v:146652.5-146652.29" - switch \initial - attribute \src "libresoc.v:146652.9-146652.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$6713 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$6713 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6712 - end - attribute \src "libresoc.v:146660.3-146668.6" - process $proc$libresoc.v:146660$6714 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$6715 $1\rst_l_r_rst$next[0:0]$6716 - attribute \src "libresoc.v:146661.5-146661.29" - switch \initial - attribute \src "libresoc.v:146661.9-146661.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$6716 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$6716 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6715 - end - attribute \src "libresoc.v:146669.3-146677.6" - process $proc$libresoc.v:146669$6717 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6718 $1\opc_l_s_opc$next[0:0]$6719 - attribute \src "libresoc.v:146670.5-146670.29" - switch \initial - attribute \src "libresoc.v:146670.9-146670.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6719 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$6719 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6718 - end - attribute \src "libresoc.v:146678.3-146686.6" - process $proc$libresoc.v:146678$6720 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6721 $1\opc_l_r_opc$next[0:0]$6722 - attribute \src "libresoc.v:146679.5-146679.29" - switch \initial - attribute \src "libresoc.v:146679.9-146679.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6722 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$6722 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6721 - end - attribute \src "libresoc.v:146687.3-146695.6" - process $proc$libresoc.v:146687$6723 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$6724 $1\src_l_s_src$next[2:0]$6725 - attribute \src "libresoc.v:146688.5-146688.29" - switch \initial - attribute \src "libresoc.v:146688.9-146688.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$6725 3'000 - case - assign $1\src_l_s_src$next[2:0]$6725 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6724 - end - attribute \src "libresoc.v:146696.3-146704.6" - process $proc$libresoc.v:146696$6726 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$6727 $1\src_l_r_src$next[2:0]$6728 - attribute \src "libresoc.v:146697.5-146697.29" - switch \initial - attribute \src "libresoc.v:146697.9-146697.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$6728 3'111 - case - assign $1\src_l_r_src$next[2:0]$6728 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6727 - end - attribute \src "libresoc.v:146705.3-146713.6" - process $proc$libresoc.v:146705$6729 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[1:0]$6730 $1\req_l_s_req$next[1:0]$6731 - attribute \src "libresoc.v:146706.5-146706.29" - switch \initial - attribute \src "libresoc.v:146706.9-146706.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[1:0]$6731 2'00 - case - assign $1\req_l_s_req$next[1:0]$6731 \$65 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6730 - end - attribute \src "libresoc.v:146714.3-146722.6" - process $proc$libresoc.v:146714$6732 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[1:0]$6733 $1\req_l_r_req$next[1:0]$6734 - attribute \src "libresoc.v:146715.5-146715.29" - switch \initial - attribute \src "libresoc.v:146715.9-146715.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[1:0]$6734 2'11 - case - assign $1\req_l_r_req$next[1:0]$6734 \$67 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6733 - end - attribute \src "libresoc.v:146723.3-146761.6" - process $proc$libresoc.v:146723$6735 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__data_len$next[3:0]$6736 $1\alu_logical0_logical_op__data_len$next[3:0]$6754 - assign $0\alu_logical0_logical_op__fn_unit$next[12:0]$6737 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6755 - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6740 $1\alu_logical0_logical_op__input_carry$next[1:0]$6758 - assign $0\alu_logical0_logical_op__insn$next[31:0]$6741 $1\alu_logical0_logical_op__insn$next[31:0]$6759 - assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6742 $1\alu_logical0_logical_op__insn_type$next[6:0]$6760 - assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6743 $1\alu_logical0_logical_op__invert_in$next[0:0]$6761 - assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6744 $1\alu_logical0_logical_op__invert_out$next[0:0]$6762 - assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6745 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6763 - assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6746 $1\alu_logical0_logical_op__is_signed$next[0:0]$6764 - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6749 $1\alu_logical0_logical_op__output_carry$next[0:0]$6767 - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6752 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6770 - assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6753 $1\alu_logical0_logical_op__zero_a$next[0:0]$6771 - assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6738 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6772 - assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6739 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6773 - assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6747 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6774 - assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6748 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6775 - assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6750 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6776 - assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6751 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6777 - attribute \src "libresoc.v:146724.5-146724.29" - switch \initial - attribute \src "libresoc.v:146724.9-146724.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_logical0_logical_op__insn$next[31:0]$6759 $1\alu_logical0_logical_op__data_len$next[3:0]$6754 $1\alu_logical0_logical_op__is_signed$next[0:0]$6764 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6763 $1\alu_logical0_logical_op__output_carry$next[0:0]$6767 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6770 $1\alu_logical0_logical_op__invert_out$next[0:0]$6762 $1\alu_logical0_logical_op__input_carry$next[1:0]$6758 $1\alu_logical0_logical_op__zero_a$next[0:0]$6771 $1\alu_logical0_logical_op__invert_in$next[0:0]$6761 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6766 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6765 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6768 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6769 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6757 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6756 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6755 $1\alu_logical0_logical_op__insn_type$next[6:0]$6760 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } - case - assign $1\alu_logical0_logical_op__data_len$next[3:0]$6754 \alu_logical0_logical_op__data_len - assign $1\alu_logical0_logical_op__fn_unit$next[12:0]$6755 \alu_logical0_logical_op__fn_unit - assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6756 \alu_logical0_logical_op__imm_data__data - assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6757 \alu_logical0_logical_op__imm_data__ok - assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6758 \alu_logical0_logical_op__input_carry - assign $1\alu_logical0_logical_op__insn$next[31:0]$6759 \alu_logical0_logical_op__insn - assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6760 \alu_logical0_logical_op__insn_type - assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6761 \alu_logical0_logical_op__invert_in - assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6762 \alu_logical0_logical_op__invert_out - assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6763 \alu_logical0_logical_op__is_32bit - assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6764 \alu_logical0_logical_op__is_signed - assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6765 \alu_logical0_logical_op__oe__oe - assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6766 \alu_logical0_logical_op__oe__ok - assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6767 \alu_logical0_logical_op__output_carry - assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6768 \alu_logical0_logical_op__rc__ok - assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6769 \alu_logical0_logical_op__rc__rc - assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6770 \alu_logical0_logical_op__write_cr0 - assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6771 \alu_logical0_logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6772 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6773 1'0 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6777 1'0 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6776 1'0 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6774 1'0 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6775 1'0 - case - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6772 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6756 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6773 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6757 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6774 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6765 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6775 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6766 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6776 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6768 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6777 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6769 - end - sync always - update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6736 - update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[12:0]$6737 - update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6738 - update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6739 - update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6740 - update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6741 - update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6742 - update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6743 - update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6744 - update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6745 - update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6746 - update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6747 - update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6748 - update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6749 - update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6750 - update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6751 - update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6752 - update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6753 - end - attribute \src "libresoc.v:146762.3-146783.6" - process $proc$libresoc.v:146762$6778 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$6779 $2\data_r0__o$next[63:0]$6783 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$6780 $3\data_r0__o_ok$next[0:0]$6785 - attribute \src "libresoc.v:146763.5-146763.29" - switch \initial - attribute \src "libresoc.v:146763.9-146763.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$6782 $1\data_r0__o$next[63:0]$6781 } { \o_ok \alu_logical0_o } - case - assign $1\data_r0__o$next[63:0]$6781 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$6782 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$6784 $2\data_r0__o$next[63:0]$6783 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$6783 $1\data_r0__o$next[63:0]$6781 - assign $2\data_r0__o_ok$next[0:0]$6784 $1\data_r0__o_ok$next[0:0]$6782 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$6785 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$6785 $2\data_r0__o_ok$next[0:0]$6784 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$6779 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6780 - end - attribute \src "libresoc.v:146784.3-146805.6" - process $proc$libresoc.v:146784$6786 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$6787 $2\data_r1__cr_a$next[3:0]$6791 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$6788 $3\data_r1__cr_a_ok$next[0:0]$6793 - attribute \src "libresoc.v:146785.5-146785.29" - switch \initial - attribute \src "libresoc.v:146785.9-146785.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$6790 $1\data_r1__cr_a$next[3:0]$6789 } { \cr_a_ok \alu_logical0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$6789 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$6790 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$6792 $2\data_r1__cr_a$next[3:0]$6791 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$6791 $1\data_r1__cr_a$next[3:0]$6789 - assign $2\data_r1__cr_a_ok$next[0:0]$6792 $1\data_r1__cr_a_ok$next[0:0]$6790 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$6793 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$6793 $2\data_r1__cr_a_ok$next[0:0]$6792 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6787 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6788 - end - attribute \src "libresoc.v:146806.3-146815.6" - process $proc$libresoc.v:146806$6794 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$6795 $1\src_r0$next[63:0]$6796 - attribute \src "libresoc.v:146807.5-146807.29" - switch \initial - attribute \src "libresoc.v:146807.9-146807.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \src_sel - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$6796 \src_or_imm - case - assign $1\src_r0$next[63:0]$6796 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$6795 - end - attribute \src "libresoc.v:146816.3-146825.6" - process $proc$libresoc.v:146816$6797 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$6798 $1\src_r1$next[63:0]$6799 - attribute \src "libresoc.v:146817.5-146817.29" - switch \initial - attribute \src "libresoc.v:146817.9-146817.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \src_sel$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$6799 \src_or_imm$80 - case - assign $1\src_r1$next[63:0]$6799 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$6798 - end - attribute \src "libresoc.v:146826.3-146835.6" - process $proc$libresoc.v:146826$6800 - assign { } { } - assign { } { } - assign $0\src_r2$next[0:0]$6801 $1\src_r2$next[0:0]$6802 - attribute \src "libresoc.v:146827.5-146827.29" - switch \initial - attribute \src "libresoc.v:146827.9-146827.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \src_l_q_src [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[0:0]$6802 \src3_i - case - assign $1\src_r2$next[0:0]$6802 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[0:0]$6801 - end - attribute \src "libresoc.v:146836.3-146844.6" - process $proc$libresoc.v:146836$6803 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$6804 $1\alui_l_r_alui$next[0:0]$6805 - attribute \src "libresoc.v:146837.5-146837.29" - switch \initial - attribute \src "libresoc.v:146837.9-146837.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$6805 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$6805 \$89 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6804 - end - attribute \src "libresoc.v:146845.3-146853.6" - process $proc$libresoc.v:146845$6806 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$6807 $1\alu_l_r_alu$next[0:0]$6808 - attribute \src "libresoc.v:146846.5-146846.29" - switch \initial - attribute \src "libresoc.v:146846.9-146846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$6808 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$6808 \$91 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6807 - end - attribute \src "libresoc.v:146854.3-146863.6" - process $proc$libresoc.v:146854$6809 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:146855.5-146855.29" - switch \initial - attribute \src "libresoc.v:146855.9-146855.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$113 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:146864.3-146873.6" - process $proc$libresoc.v:146864$6810 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:146865.5-146865.29" - switch \initial - attribute \src "libresoc.v:146865.9-146865.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$115 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a - case - assign $1\dest2_o[3:0] 4'0000 - end - sync always - update \dest2_o $0\dest2_o[3:0] - end - attribute \src "libresoc.v:146874.3-146882.6" - process $proc$libresoc.v:146874$6811 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[1:0]$6812 $1\prev_wr_go$next[1:0]$6813 - attribute \src "libresoc.v:146875.5-146875.29" - switch \initial - attribute \src "libresoc.v:146875.9-146875.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[1:0]$6813 2'00 - case - assign $1\prev_wr_go$next[1:0]$6813 \$19 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6812 - end - connect \$9 $and$libresoc.v:146405$6607_Y - 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$ternary$libresoc.v:146449$6651_Y - connect \$75 $ternary$libresoc.v:146450$6652_Y - connect \$78 $ternary$libresoc.v:146451$6653_Y - connect \$3 $reduce_and$libresoc.v:146452$6654_Y - connect \$81 $ternary$libresoc.v:146453$6655_Y - connect \$83 $ternary$libresoc.v:146454$6656_Y - connect \$85 $ternary$libresoc.v:146455$6657_Y - connect \$87 $ternary$libresoc.v:146456$6658_Y - connect \$89 $and$libresoc.v:146457$6659_Y - connect \$91 $and$libresoc.v:146458$6660_Y - connect \$93 $and$libresoc.v:146459$6661_Y - connect \$95 $not$libresoc.v:146460$6662_Y - connect \$97 $not$libresoc.v:146461$6663_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$111 - connect \cu_rd__rel_o \$103 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_logical0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_logical0_p_valid_i \alui_l_q_alui - connect \alu_logical0_xer_so \$87 - connect \alu_logical0_rb \$85 - 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\enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 47 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 38 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 37 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 36 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_logical_op__data_len$60 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_logical_op__fn_unit$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_logical_op__imm_data__data$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__imm_data__ok$47 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_logical_op__input_carry$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_logical_op__insn$61 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_logical_op__insn_type$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_in$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_out$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_32bit$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_signed$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__oe$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__ok$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__output_carry$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__rc$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__write_cr0$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__zero_a$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \main_muxid$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_so$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 31 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 30 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 29 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 50 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 51 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 27 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 52 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:147990$6855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$63 - connect \B \p_ready_o - connect \Y $and$libresoc.v:147990$6855_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:148043.14-148088.4" - cell \input$50 \input - connect \logical_op__data_len \input_logical_op__data_len - connect \logical_op__data_len$18 \input_logical_op__data_len$38 - connect \logical_op__fn_unit \input_logical_op__fn_unit - connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$23 - connect \logical_op__imm_data__data \input_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$24 - connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$25 - connect \logical_op__input_carry \input_logical_op__input_carry - connect \logical_op__input_carry$12 \input_logical_op__input_carry$32 - connect \logical_op__insn \input_logical_op__insn - connect \logical_op__insn$19 \input_logical_op__insn$39 - connect \logical_op__insn_type \input_logical_op__insn_type - connect \logical_op__insn_type$2 \input_logical_op__insn_type$22 - connect \logical_op__invert_in \input_logical_op__invert_in - connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 - connect \logical_op__invert_out \input_logical_op__invert_out - connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 - connect \logical_op__is_32bit \input_logical_op__is_32bit - connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 - connect \logical_op__is_signed \input_logical_op__is_signed - connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 - connect \logical_op__oe__oe \input_logical_op__oe__oe - connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 - connect \logical_op__oe__ok \input_logical_op__oe__ok - connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 - connect \logical_op__output_carry \input_logical_op__output_carry - connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 - connect \logical_op__rc__ok \input_logical_op__rc__ok - connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$27 - connect \logical_op__rc__rc \input_logical_op__rc__rc - connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$26 - connect \logical_op__write_cr0 \input_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$34 - connect \logical_op__zero_a \input_logical_op__zero_a - connect \logical_op__zero_a$11 \input_logical_op__zero_a$31 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$21 - connect \ra \input_ra - connect \ra$20 \input_ra$40 - connect \rb \input_rb - connect \rb$21 \input_rb$41 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$42 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:148089.13-148134.4" - cell \main$51 \main - connect \logical_op__data_len \main_logical_op__data_len - connect \logical_op__data_len$18 \main_logical_op__data_len$60 - connect \logical_op__fn_unit \main_logical_op__fn_unit - connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 - connect \logical_op__imm_data__data \main_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 - connect \logical_op__imm_data__ok \main_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 - connect \logical_op__input_carry \main_logical_op__input_carry - connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 - connect \logical_op__insn \main_logical_op__insn - connect \logical_op__insn$19 \main_logical_op__insn$61 - connect \logical_op__insn_type \main_logical_op__insn_type - connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 - connect \logical_op__invert_in \main_logical_op__invert_in - connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 - connect \logical_op__invert_out \main_logical_op__invert_out - connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 - connect \logical_op__is_32bit \main_logical_op__is_32bit - connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 - connect \logical_op__is_signed \main_logical_op__is_signed - connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 - connect \logical_op__oe__oe \main_logical_op__oe__oe - connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 - connect \logical_op__oe__ok \main_logical_op__oe__ok - connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 - connect \logical_op__output_carry \main_logical_op__output_carry - connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 - connect \logical_op__rc__ok \main_logical_op__rc__ok - connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 - connect \logical_op__rc__rc \main_logical_op__rc__rc - connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 - connect \logical_op__write_cr0 \main_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 - connect \logical_op__zero_a \main_logical_op__zero_a - connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$43 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \xer_so \main_xer_so - connect \xer_so$20 \main_xer_so$62 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:148135.10-148138.4" - cell \n$49 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:148139.10-148142.4" - cell \p$48 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:146920.7-146920.20" - process $proc$libresoc.v:146920$6950 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:146929.13-146929.24" - process $proc$libresoc.v:146929$6951 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "libresoc.v:146938.7-146938.21" - process $proc$libresoc.v:146938$6952 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:147219.13-147219.40" - process $proc$libresoc.v:147219$6953 - assign { } { } - assign $1\logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \logical_op__data_len $1\logical_op__data_len[3:0] - end - attribute \src "libresoc.v:147242.14-147242.44" - process $proc$libresoc.v:147242$6954 - assign { } { } - assign $1\logical_op__fn_unit[12:0] 13'0000000000000 - sync always - sync init - update \logical_op__fn_unit $1\logical_op__fn_unit[12:0] - end - attribute \src "libresoc.v:147279.14-147279.63" - process $proc$libresoc.v:147279$6955 - assign { } { } - assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:147288.7-147288.38" - process $proc$libresoc.v:147288$6956 - assign { } { } - assign $1\logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:147301.13-147301.43" - process $proc$libresoc.v:147301$6957 - assign { } { } - assign $1\logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \logical_op__input_carry $1\logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:147318.14-147318.38" - process $proc$libresoc.v:147318$6958 - assign { } { } - assign $1\logical_op__insn[31:0] 0 - sync always - sync init - update \logical_op__insn $1\logical_op__insn[31:0] - end - attribute \src "libresoc.v:147401.13-147401.42" - process $proc$libresoc.v:147401$6959 - assign { } { } - assign $1\logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \logical_op__insn_type $1\logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:147558.7-147558.35" - process $proc$libresoc.v:147558$6960 - assign { } { } - assign $1\logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \logical_op__invert_in $1\logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:147567.7-147567.36" - process $proc$libresoc.v:147567$6961 - assign { } { } - assign $1\logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \logical_op__invert_out $1\logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:147576.7-147576.34" - process $proc$libresoc.v:147576$6962 - assign { } { } - assign $1\logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:147585.7-147585.35" - process $proc$libresoc.v:147585$6963 - assign { } { } - assign $1\logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \logical_op__is_signed $1\logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:147594.7-147594.32" - process $proc$libresoc.v:147594$6964 - assign { } { } - assign $1\logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:147603.7-147603.32" - process $proc$libresoc.v:147603$6965 - assign { } { } - assign $1\logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:147612.7-147612.38" - process $proc$libresoc.v:147612$6966 - assign { } { } - assign $1\logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \logical_op__output_carry $1\logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:147621.7-147621.32" - process $proc$libresoc.v:147621$6967 - assign { } { } - assign $1\logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:147630.7-147630.32" - process $proc$libresoc.v:147630$6968 - assign { } { } - assign $1\logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:147639.7-147639.35" - process $proc$libresoc.v:147639$6969 - assign { } { } - assign $1\logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:147648.7-147648.32" - process $proc$libresoc.v:147648$6970 - assign { } { } - assign $1\logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \logical_op__zero_a $1\logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:147929.13-147929.25" - process $proc$libresoc.v:147929$6971 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "libresoc.v:147944.14-147944.38" - process $proc$libresoc.v:147944$6972 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:147951.7-147951.18" - process $proc$libresoc.v:147951$6973 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:147965.7-147965.20" - process $proc$libresoc.v:147965$6974 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:147974.7-147974.20" - process $proc$libresoc.v:147974$6975 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "libresoc.v:147983.7-147983.23" - process $proc$libresoc.v:147983$6976 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:147991.3-147992.29" - process $proc$libresoc.v:147991$6856 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:147993.3-147994.35" - process $proc$libresoc.v:147993$6857 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:147995.3-147996.25" - process $proc$libresoc.v:147995$6858 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "libresoc.v:147997.3-147998.31" - process $proc$libresoc.v:147997$6859 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:147999.3-148000.19" - process $proc$libresoc.v:147999$6860 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:148001.3-148002.25" - process $proc$libresoc.v:148001$6861 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:148003.3-148004.59" - process $proc$libresoc.v:148003$6862 - assign { } { } - assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next - sync posedge \coresync_clk - update \logical_op__insn_type $0\logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:148005.3-148006.55" - process $proc$libresoc.v:148005$6863 - assign { } { } - assign $0\logical_op__fn_unit[12:0] \logical_op__fn_unit$next - sync posedge \coresync_clk - update \logical_op__fn_unit $0\logical_op__fn_unit[12:0] - end - attribute \src "libresoc.v:148007.3-148008.69" - process $proc$libresoc.v:148007$6864 - assign { } { } - assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next - sync posedge \coresync_clk - update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:148009.3-148010.65" - process $proc$libresoc.v:148009$6865 - assign { } { } - assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:148011.3-148012.53" - process $proc$libresoc.v:148011$6866 - assign { } { } - assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next - sync posedge \coresync_clk - update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:148013.3-148014.53" - process $proc$libresoc.v:148013$6867 - assign { } { } - assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next - sync posedge \coresync_clk - update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:148015.3-148016.53" - process $proc$libresoc.v:148015$6868 - assign { } { } - assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next - sync posedge \coresync_clk - update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:148017.3-148018.53" - process $proc$libresoc.v:148017$6869 - assign { } { } - assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next - sync posedge \coresync_clk - update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:148019.3-148020.59" - process $proc$libresoc.v:148019$6870 - assign { } { } - assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next - sync posedge \coresync_clk - update \logical_op__invert_in $0\logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:148021.3-148022.53" - process $proc$libresoc.v:148021$6871 - assign { } { } - assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next - sync posedge \coresync_clk - update \logical_op__zero_a $0\logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:148023.3-148024.63" - process $proc$libresoc.v:148023$6872 - assign { } { } - assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next - sync posedge \coresync_clk - update \logical_op__input_carry $0\logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:148025.3-148026.61" - process $proc$libresoc.v:148025$6873 - assign { } { } - assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next - sync posedge \coresync_clk - update \logical_op__invert_out $0\logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:148027.3-148028.59" - process $proc$libresoc.v:148027$6874 - assign { } { } - assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next - sync posedge \coresync_clk - update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:148029.3-148030.65" - process $proc$libresoc.v:148029$6875 - assign { } { } - assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next - sync posedge \coresync_clk - update \logical_op__output_carry $0\logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:148031.3-148032.57" - process $proc$libresoc.v:148031$6876 - assign { } { } - assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next - sync posedge \coresync_clk - update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:148033.3-148034.59" - process $proc$libresoc.v:148033$6877 - assign { } { } - assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next - sync posedge \coresync_clk - update \logical_op__is_signed $0\logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:148035.3-148036.57" - process $proc$libresoc.v:148035$6878 - assign { } { } - assign $0\logical_op__data_len[3:0] \logical_op__data_len$next - sync posedge \coresync_clk - update \logical_op__data_len $0\logical_op__data_len[3:0] - end - attribute \src "libresoc.v:148037.3-148038.49" - process $proc$libresoc.v:148037$6879 - assign { } { } - assign $0\logical_op__insn[31:0] \logical_op__insn$next - sync posedge \coresync_clk - update \logical_op__insn $0\logical_op__insn[31:0] - end - attribute \src "libresoc.v:148039.3-148040.27" - process $proc$libresoc.v:148039$6880 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:148041.3-148042.29" - process $proc$libresoc.v:148041$6881 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:148143.3-148160.6" - process $proc$libresoc.v:148143$6882 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$6883 $2\r_busy$next[0:0]$6885 - attribute \src "libresoc.v:148144.5-148144.29" - switch \initial - attribute \src "libresoc.v:148144.9-148144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$6884 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$6884 1'0 - case - assign $1\r_busy$next[0:0]$6884 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$6885 1'0 - case - assign $2\r_busy$next[0:0]$6885 $1\r_busy$next[0:0]$6884 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$6883 - end - attribute \src "libresoc.v:148161.3-148173.6" - process $proc$libresoc.v:148161$6886 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$6887 $1\muxid$next[1:0]$6888 - attribute \src "libresoc.v:148162.5-148162.29" - switch \initial - attribute \src "libresoc.v:148162.9-148162.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$6888 \muxid$66 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$6888 \muxid$66 - case - assign $1\muxid$next[1:0]$6888 \muxid - end - sync always - update \muxid$next $0\muxid$next[1:0]$6887 - end - attribute \src "libresoc.v:148174.3-148215.6" - process $proc$libresoc.v:148174$6889 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$next[3:0]$6890 $1\logical_op__data_len$next[3:0]$6908 - assign $0\logical_op__fn_unit$next[12:0]$6891 $1\logical_op__fn_unit$next[12:0]$6909 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$next[1:0]$6894 $1\logical_op__input_carry$next[1:0]$6912 - assign $0\logical_op__insn$next[31:0]$6895 $1\logical_op__insn$next[31:0]$6913 - assign $0\logical_op__insn_type$next[6:0]$6896 $1\logical_op__insn_type$next[6:0]$6914 - assign $0\logical_op__invert_in$next[0:0]$6897 $1\logical_op__invert_in$next[0:0]$6915 - assign $0\logical_op__invert_out$next[0:0]$6898 $1\logical_op__invert_out$next[0:0]$6916 - assign $0\logical_op__is_32bit$next[0:0]$6899 $1\logical_op__is_32bit$next[0:0]$6917 - assign $0\logical_op__is_signed$next[0:0]$6900 $1\logical_op__is_signed$next[0:0]$6918 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$next[0:0]$6903 $1\logical_op__output_carry$next[0:0]$6921 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$6906 $1\logical_op__write_cr0$next[0:0]$6924 - assign $0\logical_op__zero_a$next[0:0]$6907 $1\logical_op__zero_a$next[0:0]$6925 - assign $0\logical_op__imm_data__data$next[63:0]$6892 $2\logical_op__imm_data__data$next[63:0]$6926 - assign $0\logical_op__imm_data__ok$next[0:0]$6893 $2\logical_op__imm_data__ok$next[0:0]$6927 - assign $0\logical_op__oe__oe$next[0:0]$6901 $2\logical_op__oe__oe$next[0:0]$6928 - assign $0\logical_op__oe__ok$next[0:0]$6902 $2\logical_op__oe__ok$next[0:0]$6929 - assign $0\logical_op__rc__ok$next[0:0]$6904 $2\logical_op__rc__ok$next[0:0]$6930 - assign $0\logical_op__rc__rc$next[0:0]$6905 $2\logical_op__rc__rc$next[0:0]$6931 - attribute \src "libresoc.v:148175.5-148175.29" - switch \initial - attribute \src "libresoc.v:148175.9-148175.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$6913 $1\logical_op__data_len$next[3:0]$6908 $1\logical_op__is_signed$next[0:0]$6918 $1\logical_op__is_32bit$next[0:0]$6917 $1\logical_op__output_carry$next[0:0]$6921 $1\logical_op__write_cr0$next[0:0]$6924 $1\logical_op__invert_out$next[0:0]$6916 $1\logical_op__input_carry$next[1:0]$6912 $1\logical_op__zero_a$next[0:0]$6925 $1\logical_op__invert_in$next[0:0]$6915 $1\logical_op__oe__ok$next[0:0]$6920 $1\logical_op__oe__oe$next[0:0]$6919 $1\logical_op__rc__ok$next[0:0]$6922 $1\logical_op__rc__rc$next[0:0]$6923 $1\logical_op__imm_data__ok$next[0:0]$6911 $1\logical_op__imm_data__data$next[63:0]$6910 $1\logical_op__fn_unit$next[12:0]$6909 $1\logical_op__insn_type$next[6:0]$6914 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$6913 $1\logical_op__data_len$next[3:0]$6908 $1\logical_op__is_signed$next[0:0]$6918 $1\logical_op__is_32bit$next[0:0]$6917 $1\logical_op__output_carry$next[0:0]$6921 $1\logical_op__write_cr0$next[0:0]$6924 $1\logical_op__invert_out$next[0:0]$6916 $1\logical_op__input_carry$next[1:0]$6912 $1\logical_op__zero_a$next[0:0]$6925 $1\logical_op__invert_in$next[0:0]$6915 $1\logical_op__oe__ok$next[0:0]$6920 $1\logical_op__oe__oe$next[0:0]$6919 $1\logical_op__rc__ok$next[0:0]$6922 $1\logical_op__rc__rc$next[0:0]$6923 $1\logical_op__imm_data__ok$next[0:0]$6911 $1\logical_op__imm_data__data$next[63:0]$6910 $1\logical_op__fn_unit$next[12:0]$6909 $1\logical_op__insn_type$next[6:0]$6914 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } - case - assign $1\logical_op__data_len$next[3:0]$6908 \logical_op__data_len - assign $1\logical_op__fn_unit$next[12:0]$6909 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$6910 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$6911 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$6912 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$6913 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$6914 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$6915 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$6916 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$6917 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$6918 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$6919 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$6920 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$6921 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$6922 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$6923 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$6924 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$6925 \logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$6926 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$6927 1'0 - assign $2\logical_op__rc__rc$next[0:0]$6931 1'0 - assign $2\logical_op__rc__ok$next[0:0]$6930 1'0 - assign $2\logical_op__oe__oe$next[0:0]$6928 1'0 - assign $2\logical_op__oe__ok$next[0:0]$6929 1'0 - case - assign $2\logical_op__imm_data__data$next[63:0]$6926 $1\logical_op__imm_data__data$next[63:0]$6910 - assign $2\logical_op__imm_data__ok$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6911 - assign $2\logical_op__oe__oe$next[0:0]$6928 $1\logical_op__oe__oe$next[0:0]$6919 - assign $2\logical_op__oe__ok$next[0:0]$6929 $1\logical_op__oe__ok$next[0:0]$6920 - assign $2\logical_op__rc__ok$next[0:0]$6930 $1\logical_op__rc__ok$next[0:0]$6922 - assign $2\logical_op__rc__rc$next[0:0]$6931 $1\logical_op__rc__rc$next[0:0]$6923 - end - sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6890 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$6891 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6892 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6893 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6894 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6895 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6896 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6897 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6898 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6899 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6900 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6901 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6902 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6903 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6904 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6905 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6906 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6907 - end - attribute \src "libresoc.v:148216.3-148234.6" - process $proc$libresoc.v:148216$6932 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$6933 $1\o$next[63:0]$6935 - assign { } { } - assign $0\o_ok$next[0:0]$6934 $2\o_ok$next[0:0]$6937 - attribute \src "libresoc.v:148217.5-148217.29" - switch \initial - attribute \src "libresoc.v:148217.9-148217.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$6936 $1\o$next[63:0]$6935 } { \o_ok$86 \o$85 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$6936 $1\o$next[63:0]$6935 } { \o_ok$86 \o$85 } - case - assign $1\o$next[63:0]$6935 \o - assign $1\o_ok$next[0:0]$6936 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$6937 1'0 - case - assign $2\o_ok$next[0:0]$6937 $1\o_ok$next[0:0]$6936 - end - sync always - update \o$next $0\o$next[63:0]$6933 - update \o_ok$next $0\o_ok$next[0:0]$6934 - end - attribute \src "libresoc.v:148235.3-148253.6" - process $proc$libresoc.v:148235$6938 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$6939 $1\cr_a$next[3:0]$6941 - assign { } { } - assign $0\cr_a_ok$next[0:0]$6940 $2\cr_a_ok$next[0:0]$6943 - attribute \src "libresoc.v:148236.5-148236.29" - switch \initial - attribute \src "libresoc.v:148236.9-148236.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$6942 $1\cr_a$next[3:0]$6941 } { \cr_a_ok$88 \cr_a$87 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$6942 $1\cr_a$next[3:0]$6941 } { \cr_a_ok$88 \cr_a$87 } - case - assign $1\cr_a$next[3:0]$6941 \cr_a - assign $1\cr_a_ok$next[0:0]$6942 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$6943 1'0 - case - assign $2\cr_a_ok$next[0:0]$6943 $1\cr_a_ok$next[0:0]$6942 - end - sync always - update \cr_a$next $0\cr_a$next[3:0]$6939 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6940 - end - attribute \src "libresoc.v:148254.3-148272.6" - process $proc$libresoc.v:148254$6944 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$next[0:0]$6945 $1\xer_so$next[0:0]$6947 - assign { } { } - assign $0\xer_so_ok$next[0:0]$6946 $2\xer_so_ok$next[0:0]$6949 - attribute \src "libresoc.v:148255.5-148255.29" - switch \initial - attribute \src "libresoc.v:148255.9-148255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$6948 $1\xer_so$next[0:0]$6947 } { \xer_so_ok$92 \xer_so$91 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$6948 $1\xer_so$next[0:0]$6947 } { \xer_so_ok$92 \xer_so$91 } - case - assign $1\xer_so$next[0:0]$6947 \xer_so - assign $1\xer_so_ok$next[0:0]$6948 \xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so_ok$next[0:0]$6949 1'0 - case - assign $2\xer_so_ok$next[0:0]$6949 $1\xer_so_ok$next[0:0]$6948 - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$6945 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6946 - end - connect \$64 $and$libresoc.v:147990$6855_Y - connect \cr_a$89 4'0000 - connect \cr_a_ok$90 1'0 - connect \xer_so_ok$93 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } - connect { \cr_a_ok$88 \cr_a$87 } 5'00000 - connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } - connect { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } - connect \muxid$66 \main_muxid$43 - connect \p_valid_i_p_ready_o \$64 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$63 \p_valid_i - connect \main_xer_so \input_xer_so$42 - connect \main_rb \input_rb$41 - connect \main_ra \input_ra$40 - connect { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in \main_logical_op__oe__ok \main_logical_op__oe__oe \main_logical_op__rc__ok \main_logical_op__rc__rc \main_logical_op__imm_data__ok \main_logical_op__imm_data__data \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } - connect \main_muxid \input_muxid$21 - connect \input_xer_so \xer_so$20 - connect \input_rb \rb - connect \input_ra \ra - connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "libresoc.v:148300.1-149323.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" -attribute \generator "nMigen" -module \logical_pipe2 - attribute \src "libresoc.v:149290.3-149308.6" - wire width 4 $0\cr_a$22$next[3:0]$7082 - attribute \src "libresoc.v:149094.3-149095.33" - wire width 4 $0\cr_a$22[3:0]$6979 - attribute \src "libresoc.v:148312.13-148312.29" - wire width 4 $0\cr_a$22[3:0]$7089 - attribute \src "libresoc.v:149290.3-149308.6" - wire $0\cr_a_ok$23$next[0:0]$7083 - attribute \src "libresoc.v:149096.3-149097.39" - wire $0\cr_a_ok$23[0:0]$6981 - attribute \src "libresoc.v:148321.7-148321.26" - wire $0\cr_a_ok$23[0:0]$7091 - attribute \src "libresoc.v:148301.7-148301.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:149229.3-149270.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$7033 - attribute \src "libresoc.v:149134.3-149135.65" - wire width 4 $0\logical_op__data_len$18[3:0]$7019 - attribute \src "libresoc.v:148332.13-148332.45" - wire width 4 $0\logical_op__data_len$18[3:0]$7093 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 13 $0\logical_op__fn_unit$3$next[12:0]$7034 - attribute \src "libresoc.v:149104.3-149105.61" - wire width 13 $0\logical_op__fn_unit$3[12:0]$6989 - attribute \src "libresoc.v:148369.14-148369.48" - wire width 13 $0\logical_op__fn_unit$3[12:0]$7095 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7035 - attribute \src "libresoc.v:149106.3-149107.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6991 - attribute \src "libresoc.v:148392.14-148392.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$7097 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$7036 - attribute \src "libresoc.v:149108.3-149109.71" - wire $0\logical_op__imm_data__ok$5[0:0]$6993 - attribute \src "libresoc.v:148401.7-148401.42" - wire $0\logical_op__imm_data__ok$5[0:0]$7099 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$7037 - attribute \src "libresoc.v:149122.3-149123.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$7007 - attribute \src "libresoc.v:148418.13-148418.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$7101 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$7038 - attribute \src "libresoc.v:149136.3-149137.57" - wire width 32 $0\logical_op__insn$19[31:0]$7021 - attribute \src "libresoc.v:148431.14-148431.43" - wire width 32 $0\logical_op__insn$19[31:0]$7103 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$7039 - attribute \src "libresoc.v:149102.3-149103.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$6987 - attribute \src "libresoc.v:148588.13-148588.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$7105 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__invert_in$10$next[0:0]$7040 - attribute \src "libresoc.v:149118.3-149119.67" - wire $0\logical_op__invert_in$10[0:0]$7003 - attribute \src "libresoc.v:148671.7-148671.40" - wire $0\logical_op__invert_in$10[0:0]$7107 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__invert_out$13$next[0:0]$7041 - attribute \src "libresoc.v:149124.3-149125.69" - wire $0\logical_op__invert_out$13[0:0]$7009 - attribute \src "libresoc.v:148680.7-148680.41" - wire $0\logical_op__invert_out$13[0:0]$7109 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__is_32bit$16$next[0:0]$7042 - attribute \src "libresoc.v:149130.3-149131.65" - wire $0\logical_op__is_32bit$16[0:0]$7015 - attribute \src "libresoc.v:148689.7-148689.39" - wire $0\logical_op__is_32bit$16[0:0]$7111 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__is_signed$17$next[0:0]$7043 - attribute \src "libresoc.v:149132.3-149133.67" - wire $0\logical_op__is_signed$17[0:0]$7017 - attribute \src "libresoc.v:148698.7-148698.40" - wire $0\logical_op__is_signed$17[0:0]$7113 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__oe__oe$8$next[0:0]$7044 - attribute \src "libresoc.v:149114.3-149115.59" - wire $0\logical_op__oe__oe$8[0:0]$6999 - attribute \src "libresoc.v:148709.7-148709.36" - wire $0\logical_op__oe__oe$8[0:0]$7115 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__oe__ok$9$next[0:0]$7045 - attribute \src "libresoc.v:149116.3-149117.59" - wire $0\logical_op__oe__ok$9[0:0]$7001 - attribute \src "libresoc.v:148718.7-148718.36" - wire $0\logical_op__oe__ok$9[0:0]$7117 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__output_carry$15$next[0:0]$7046 - attribute \src "libresoc.v:149128.3-149129.73" - wire $0\logical_op__output_carry$15[0:0]$7013 - attribute \src "libresoc.v:148725.7-148725.43" - wire $0\logical_op__output_carry$15[0:0]$7119 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__rc__ok$7$next[0:0]$7047 - attribute \src "libresoc.v:149112.3-149113.59" - wire $0\logical_op__rc__ok$7[0:0]$6997 - attribute \src "libresoc.v:148736.7-148736.36" - wire $0\logical_op__rc__ok$7[0:0]$7121 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__rc__rc$6$next[0:0]$7048 - attribute \src "libresoc.v:149110.3-149111.59" - wire $0\logical_op__rc__rc$6[0:0]$6995 - attribute \src "libresoc.v:148745.7-148745.36" - wire $0\logical_op__rc__rc$6[0:0]$7123 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__write_cr0$14$next[0:0]$7049 - attribute \src "libresoc.v:149126.3-149127.67" - wire $0\logical_op__write_cr0$14[0:0]$7011 - attribute \src "libresoc.v:148752.7-148752.40" - wire $0\logical_op__write_cr0$14[0:0]$7125 - attribute \src "libresoc.v:149229.3-149270.6" - wire $0\logical_op__zero_a$11$next[0:0]$7050 - attribute \src "libresoc.v:149120.3-149121.61" - wire $0\logical_op__zero_a$11[0:0]$7005 - attribute \src "libresoc.v:148761.7-148761.37" - wire $0\logical_op__zero_a$11[0:0]$7127 - attribute \src "libresoc.v:149216.3-149228.6" - wire width 2 $0\muxid$1$next[1:0]$7030 - attribute \src "libresoc.v:149138.3-149139.33" - wire width 2 $0\muxid$1[1:0]$7023 - attribute \src "libresoc.v:148770.13-148770.29" - wire width 2 $0\muxid$1[1:0]$7129 - attribute \src "libresoc.v:149271.3-149289.6" - wire width 64 $0\o$20$next[63:0]$7076 - attribute \src "libresoc.v:149098.3-149099.27" - wire width 64 $0\o$20[63:0]$6983 - attribute \src "libresoc.v:148785.14-148785.43" - wire width 64 $0\o$20[63:0]$7131 - attribute \src "libresoc.v:149271.3-149289.6" - wire $0\o_ok$21$next[0:0]$7077 - attribute \src "libresoc.v:149100.3-149101.33" - wire $0\o_ok$21[0:0]$6985 - attribute \src "libresoc.v:148794.7-148794.23" - wire $0\o_ok$21[0:0]$7133 - attribute \src "libresoc.v:149198.3-149215.6" - wire $0\r_busy$next[0:0]$7026 - attribute \src "libresoc.v:149140.3-149141.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:149290.3-149308.6" - wire width 4 $1\cr_a$22$next[3:0]$7084 - attribute \src "libresoc.v:149290.3-149308.6" - wire $1\cr_a_ok$23$next[0:0]$7085 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$7051 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 13 $1\logical_op__fn_unit$3$next[12:0]$7052 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7053 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$7054 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$7055 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$7056 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$7057 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__invert_in$10$next[0:0]$7058 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__invert_out$13$next[0:0]$7059 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__is_32bit$16$next[0:0]$7060 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__is_signed$17$next[0:0]$7061 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__oe__oe$8$next[0:0]$7062 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__oe__ok$9$next[0:0]$7063 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__output_carry$15$next[0:0]$7064 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__rc__ok$7$next[0:0]$7065 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__rc__rc$6$next[0:0]$7066 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__write_cr0$14$next[0:0]$7067 - attribute \src "libresoc.v:149229.3-149270.6" - wire $1\logical_op__zero_a$11$next[0:0]$7068 - attribute \src "libresoc.v:149216.3-149228.6" - wire width 2 $1\muxid$1$next[1:0]$7031 - attribute \src "libresoc.v:149271.3-149289.6" - wire width 64 $1\o$20$next[63:0]$7078 - attribute \src "libresoc.v:149271.3-149289.6" - wire $1\o_ok$21$next[0:0]$7079 - attribute \src "libresoc.v:149198.3-149215.6" - wire $1\r_busy$next[0:0]$7027 - attribute \src "libresoc.v:149084.7-149084.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:149290.3-149308.6" - wire $2\cr_a_ok$23$next[0:0]$7086 - attribute \src "libresoc.v:149229.3-149270.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7069 - attribute \src "libresoc.v:149229.3-149270.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$7070 - attribute \src "libresoc.v:149229.3-149270.6" - wire $2\logical_op__oe__oe$8$next[0:0]$7071 - attribute \src "libresoc.v:149229.3-149270.6" - wire $2\logical_op__oe__ok$9$next[0:0]$7072 - attribute \src "libresoc.v:149229.3-149270.6" - wire $2\logical_op__rc__ok$7$next[0:0]$7073 - attribute \src "libresoc.v:149229.3-149270.6" - wire $2\logical_op__rc__rc$6$next[0:0]$7074 - attribute \src "libresoc.v:149271.3-149289.6" - wire $2\o_ok$21$next[0:0]$7080 - attribute \src "libresoc.v:149198.3-149215.6" - wire $2\r_busy$next[0:0]$7028 - attribute \src "libresoc.v:149093.18-149093.118" - wire $and$libresoc.v:149093$6977_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 52 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 53 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$73 - attribute \src "libresoc.v:148301.7-148301.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 48 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$68 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 33 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 34 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$55 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 42 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 49 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$69 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 32 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 31 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 30 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 29 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 50 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 51 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len$41 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_logical_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok$28 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn$42 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a$34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_muxid$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 27 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 28 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:149093$6977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$48 - connect \B \p_ready_o - connect \Y $and$libresoc.v:149093$6977_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149142.10-149145.4" - cell \n$53 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149146.15-149193.4" - cell \output$54 \output - connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$45 - connect \cr_a_ok \output_cr_a_ok - connect \logical_op__data_len \output_logical_op__data_len - connect \logical_op__data_len$18 \output_logical_op__data_len$41 - connect \logical_op__fn_unit \output_logical_op__fn_unit - connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 - connect \logical_op__imm_data__data \output_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 - connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 - connect \logical_op__input_carry \output_logical_op__input_carry - connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 - connect \logical_op__insn \output_logical_op__insn - connect \logical_op__insn$19 \output_logical_op__insn$42 - connect \logical_op__insn_type \output_logical_op__insn_type - connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 - connect \logical_op__invert_in \output_logical_op__invert_in - connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 - connect \logical_op__invert_out \output_logical_op__invert_out - connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 - connect \logical_op__is_32bit \output_logical_op__is_32bit - connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 - connect \logical_op__is_signed \output_logical_op__is_signed - connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 - connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 - connect \logical_op__oe__ok \output_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 - connect \logical_op__output_carry \output_logical_op__output_carry - connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 - connect \logical_op__rc__ok \output_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 - connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 - connect \logical_op__write_cr0 \output_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 - connect \logical_op__zero_a \output_logical_op__zero_a - connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$24 - connect \o \output_o - connect \o$20 \output_o$43 - connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$44 - connect \xer_so \output_xer_so - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149194.10-149197.4" - cell \p$52 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:148301.7-148301.20" - process $proc$libresoc.v:148301$7087 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:148312.13-148312.29" - process $proc$libresoc.v:148312$7088 - assign { } { } - assign $0\cr_a$22[3:0]$7089 4'0000 - sync always - sync init - update \cr_a$22 $0\cr_a$22[3:0]$7089 - end - attribute \src "libresoc.v:148321.7-148321.26" - process $proc$libresoc.v:148321$7090 - assign { } { } - assign $0\cr_a_ok$23[0:0]$7091 1'0 - sync always - sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7091 - end - attribute \src "libresoc.v:148332.13-148332.45" - process $proc$libresoc.v:148332$7092 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$7093 4'0000 - sync always - sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7093 - end - attribute \src "libresoc.v:148369.14-148369.48" - process $proc$libresoc.v:148369$7094 - assign { } { } - assign $0\logical_op__fn_unit$3[12:0]$7095 13'0000000000000 - sync always - sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$7095 - end - attribute \src "libresoc.v:148392.14-148392.67" - process $proc$libresoc.v:148392$7096 - assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$7097 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7097 - end - attribute \src "libresoc.v:148401.7-148401.42" - process $proc$libresoc.v:148401$7098 - assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$7099 1'0 - sync always - sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7099 - end - attribute \src "libresoc.v:148418.13-148418.48" - process $proc$libresoc.v:148418$7100 - assign { } { } - assign $0\logical_op__input_carry$12[1:0]$7101 2'00 - sync always - sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7101 - end - attribute \src "libresoc.v:148431.14-148431.43" - process $proc$libresoc.v:148431$7102 - assign { } { } - assign $0\logical_op__insn$19[31:0]$7103 0 - sync always - sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7103 - end - attribute \src "libresoc.v:148588.13-148588.46" - process $proc$libresoc.v:148588$7104 - assign { } { } - assign $0\logical_op__insn_type$2[6:0]$7105 7'0000000 - sync always - sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7105 - end - attribute \src "libresoc.v:148671.7-148671.40" - process $proc$libresoc.v:148671$7106 - assign { } { } - assign $0\logical_op__invert_in$10[0:0]$7107 1'0 - sync always - sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7107 - end - attribute \src "libresoc.v:148680.7-148680.41" - process $proc$libresoc.v:148680$7108 - assign { } { } - assign $0\logical_op__invert_out$13[0:0]$7109 1'0 - sync always - sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7109 - end - attribute \src "libresoc.v:148689.7-148689.39" - process $proc$libresoc.v:148689$7110 - assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$7111 1'0 - sync always - sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7111 - end - attribute \src "libresoc.v:148698.7-148698.40" - process $proc$libresoc.v:148698$7112 - assign { } { } - assign $0\logical_op__is_signed$17[0:0]$7113 1'0 - sync always - sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7113 - end - attribute \src "libresoc.v:148709.7-148709.36" - process $proc$libresoc.v:148709$7114 - assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$7115 1'0 - sync always - sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7115 - end - attribute \src "libresoc.v:148718.7-148718.36" - process $proc$libresoc.v:148718$7116 - assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$7117 1'0 - sync always - sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7117 - end - attribute \src "libresoc.v:148725.7-148725.43" - process $proc$libresoc.v:148725$7118 - assign { } { } - assign $0\logical_op__output_carry$15[0:0]$7119 1'0 - sync always - sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7119 - end - attribute \src "libresoc.v:148736.7-148736.36" - process $proc$libresoc.v:148736$7120 - assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$7121 1'0 - sync always - sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7121 - end - attribute \src "libresoc.v:148745.7-148745.36" - process $proc$libresoc.v:148745$7122 - assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$7123 1'0 - sync always - sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7123 - end - attribute \src "libresoc.v:148752.7-148752.40" - process $proc$libresoc.v:148752$7124 - assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$7125 1'0 - sync always - sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7125 - end - attribute \src "libresoc.v:148761.7-148761.37" - process $proc$libresoc.v:148761$7126 - assign { } { } - assign $0\logical_op__zero_a$11[0:0]$7127 1'0 - sync always - sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7127 - end - attribute \src "libresoc.v:148770.13-148770.29" - process $proc$libresoc.v:148770$7128 - assign { } { } - assign $0\muxid$1[1:0]$7129 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$7129 - end - attribute \src "libresoc.v:148785.14-148785.43" - process $proc$libresoc.v:148785$7130 - assign { } { } - assign $0\o$20[63:0]$7131 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o$20 $0\o$20[63:0]$7131 - end - attribute \src "libresoc.v:148794.7-148794.23" - process $proc$libresoc.v:148794$7132 - assign { } { } - assign $0\o_ok$21[0:0]$7133 1'0 - sync always - sync init - update \o_ok$21 $0\o_ok$21[0:0]$7133 - end - attribute \src "libresoc.v:149084.7-149084.20" - process $proc$libresoc.v:149084$7134 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:149094.3-149095.33" - process $proc$libresoc.v:149094$6978 - assign { } { } - assign $0\cr_a$22[3:0]$6979 \cr_a$22$next - sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$6979 - end - attribute \src "libresoc.v:149096.3-149097.39" - process $proc$libresoc.v:149096$6980 - assign { } { } - assign $0\cr_a_ok$23[0:0]$6981 \cr_a_ok$23$next - sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6981 - end - attribute \src "libresoc.v:149098.3-149099.27" - process $proc$libresoc.v:149098$6982 - assign { } { } - assign $0\o$20[63:0]$6983 \o$20$next - sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$6983 - end - attribute \src "libresoc.v:149100.3-149101.33" - process $proc$libresoc.v:149100$6984 - assign { } { } - assign $0\o_ok$21[0:0]$6985 \o_ok$21$next - sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$6985 - end - attribute \src "libresoc.v:149102.3-149103.65" - process $proc$libresoc.v:149102$6986 - assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6987 \logical_op__insn_type$2$next - sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6987 - end - attribute \src "libresoc.v:149104.3-149105.61" - process $proc$libresoc.v:149104$6988 - assign { } { } - assign $0\logical_op__fn_unit$3[12:0]$6989 \logical_op__fn_unit$3$next - sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$6989 - end - attribute \src "libresoc.v:149106.3-149107.75" - process $proc$libresoc.v:149106$6990 - assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6991 \logical_op__imm_data__data$4$next - sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6991 - end - attribute \src "libresoc.v:149108.3-149109.71" - process $proc$libresoc.v:149108$6992 - assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6993 \logical_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6993 - end - attribute \src "libresoc.v:149110.3-149111.59" - process $proc$libresoc.v:149110$6994 - assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6995 \logical_op__rc__rc$6$next - sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6995 - end - attribute \src "libresoc.v:149112.3-149113.59" - process $proc$libresoc.v:149112$6996 - assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6997 \logical_op__rc__ok$7$next - sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6997 - end - attribute \src "libresoc.v:149114.3-149115.59" - process $proc$libresoc.v:149114$6998 - assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6999 \logical_op__oe__oe$8$next - sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6999 - end - attribute \src "libresoc.v:149116.3-149117.59" - process $proc$libresoc.v:149116$7000 - assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$7001 \logical_op__oe__ok$9$next - sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7001 - end - attribute \src "libresoc.v:149118.3-149119.67" - process $proc$libresoc.v:149118$7002 - assign { } { } - assign $0\logical_op__invert_in$10[0:0]$7003 \logical_op__invert_in$10$next - sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7003 - end - attribute \src "libresoc.v:149120.3-149121.61" - process $proc$libresoc.v:149120$7004 - assign { } { } - assign $0\logical_op__zero_a$11[0:0]$7005 \logical_op__zero_a$11$next - sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7005 - end - attribute \src "libresoc.v:149122.3-149123.71" - process $proc$libresoc.v:149122$7006 - assign { } { } - assign $0\logical_op__input_carry$12[1:0]$7007 \logical_op__input_carry$12$next - sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7007 - end - attribute \src "libresoc.v:149124.3-149125.69" - process $proc$libresoc.v:149124$7008 - assign { } { } - assign $0\logical_op__invert_out$13[0:0]$7009 \logical_op__invert_out$13$next - sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7009 - end - attribute \src "libresoc.v:149126.3-149127.67" - process $proc$libresoc.v:149126$7010 - assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$7011 \logical_op__write_cr0$14$next - sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7011 - end - attribute \src "libresoc.v:149128.3-149129.73" - process $proc$libresoc.v:149128$7012 - assign { } { } - assign $0\logical_op__output_carry$15[0:0]$7013 \logical_op__output_carry$15$next - sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7013 - end - attribute \src "libresoc.v:149130.3-149131.65" - process $proc$libresoc.v:149130$7014 - assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$7015 \logical_op__is_32bit$16$next - sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7015 - end - attribute \src "libresoc.v:149132.3-149133.67" - process $proc$libresoc.v:149132$7016 - assign { } { } - assign $0\logical_op__is_signed$17[0:0]$7017 \logical_op__is_signed$17$next - sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7017 - end - attribute \src "libresoc.v:149134.3-149135.65" - process $proc$libresoc.v:149134$7018 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$7019 \logical_op__data_len$18$next - sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7019 - end - attribute \src "libresoc.v:149136.3-149137.57" - process $proc$libresoc.v:149136$7020 - assign { } { } - assign $0\logical_op__insn$19[31:0]$7021 \logical_op__insn$19$next - sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7021 - end - attribute \src "libresoc.v:149138.3-149139.33" - process $proc$libresoc.v:149138$7022 - assign { } { } - assign $0\muxid$1[1:0]$7023 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7023 - end - attribute \src "libresoc.v:149140.3-149141.29" - process $proc$libresoc.v:149140$7024 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:149198.3-149215.6" - process $proc$libresoc.v:149198$7025 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$7026 $2\r_busy$next[0:0]$7028 - attribute \src "libresoc.v:149199.5-149199.29" - switch \initial - attribute \src "libresoc.v:149199.9-149199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$7027 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$7027 1'0 - case - assign $1\r_busy$next[0:0]$7027 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$7028 1'0 - case - assign $2\r_busy$next[0:0]$7028 $1\r_busy$next[0:0]$7027 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$7026 - end - attribute \src "libresoc.v:149216.3-149228.6" - process $proc$libresoc.v:149216$7029 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$7030 $1\muxid$1$next[1:0]$7031 - attribute \src "libresoc.v:149217.5-149217.29" - switch \initial - attribute \src "libresoc.v:149217.9-149217.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$7031 \muxid$51 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$7031 \muxid$51 - case - assign $1\muxid$1$next[1:0]$7031 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7030 - end - attribute \src "libresoc.v:149229.3-149270.6" - process $proc$libresoc.v:149229$7032 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$7033 $1\logical_op__data_len$18$next[3:0]$7051 - assign $0\logical_op__fn_unit$3$next[12:0]$7034 $1\logical_op__fn_unit$3$next[12:0]$7052 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$7037 $1\logical_op__input_carry$12$next[1:0]$7055 - assign $0\logical_op__insn$19$next[31:0]$7038 $1\logical_op__insn$19$next[31:0]$7056 - assign $0\logical_op__insn_type$2$next[6:0]$7039 $1\logical_op__insn_type$2$next[6:0]$7057 - assign $0\logical_op__invert_in$10$next[0:0]$7040 $1\logical_op__invert_in$10$next[0:0]$7058 - assign $0\logical_op__invert_out$13$next[0:0]$7041 $1\logical_op__invert_out$13$next[0:0]$7059 - assign $0\logical_op__is_32bit$16$next[0:0]$7042 $1\logical_op__is_32bit$16$next[0:0]$7060 - assign $0\logical_op__is_signed$17$next[0:0]$7043 $1\logical_op__is_signed$17$next[0:0]$7061 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$7046 $1\logical_op__output_carry$15$next[0:0]$7064 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$7049 $1\logical_op__write_cr0$14$next[0:0]$7067 - assign $0\logical_op__zero_a$11$next[0:0]$7050 $1\logical_op__zero_a$11$next[0:0]$7068 - assign $0\logical_op__imm_data__data$4$next[63:0]$7035 $2\logical_op__imm_data__data$4$next[63:0]$7069 - assign $0\logical_op__imm_data__ok$5$next[0:0]$7036 $2\logical_op__imm_data__ok$5$next[0:0]$7070 - assign $0\logical_op__oe__oe$8$next[0:0]$7044 $2\logical_op__oe__oe$8$next[0:0]$7071 - assign $0\logical_op__oe__ok$9$next[0:0]$7045 $2\logical_op__oe__ok$9$next[0:0]$7072 - assign $0\logical_op__rc__ok$7$next[0:0]$7047 $2\logical_op__rc__ok$7$next[0:0]$7073 - assign $0\logical_op__rc__rc$6$next[0:0]$7048 $2\logical_op__rc__rc$6$next[0:0]$7074 - attribute \src "libresoc.v:149230.5-149230.29" - switch \initial - attribute \src "libresoc.v:149230.9-149230.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$7056 $1\logical_op__data_len$18$next[3:0]$7051 $1\logical_op__is_signed$17$next[0:0]$7061 $1\logical_op__is_32bit$16$next[0:0]$7060 $1\logical_op__output_carry$15$next[0:0]$7064 $1\logical_op__write_cr0$14$next[0:0]$7067 $1\logical_op__invert_out$13$next[0:0]$7059 $1\logical_op__input_carry$12$next[1:0]$7055 $1\logical_op__zero_a$11$next[0:0]$7068 $1\logical_op__invert_in$10$next[0:0]$7058 $1\logical_op__oe__ok$9$next[0:0]$7063 $1\logical_op__oe__oe$8$next[0:0]$7062 $1\logical_op__rc__ok$7$next[0:0]$7065 $1\logical_op__rc__rc$6$next[0:0]$7066 $1\logical_op__imm_data__ok$5$next[0:0]$7054 $1\logical_op__imm_data__data$4$next[63:0]$7053 $1\logical_op__fn_unit$3$next[12:0]$7052 $1\logical_op__insn_type$2$next[6:0]$7057 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$7056 $1\logical_op__data_len$18$next[3:0]$7051 $1\logical_op__is_signed$17$next[0:0]$7061 $1\logical_op__is_32bit$16$next[0:0]$7060 $1\logical_op__output_carry$15$next[0:0]$7064 $1\logical_op__write_cr0$14$next[0:0]$7067 $1\logical_op__invert_out$13$next[0:0]$7059 $1\logical_op__input_carry$12$next[1:0]$7055 $1\logical_op__zero_a$11$next[0:0]$7068 $1\logical_op__invert_in$10$next[0:0]$7058 $1\logical_op__oe__ok$9$next[0:0]$7063 $1\logical_op__oe__oe$8$next[0:0]$7062 $1\logical_op__rc__ok$7$next[0:0]$7065 $1\logical_op__rc__rc$6$next[0:0]$7066 $1\logical_op__imm_data__ok$5$next[0:0]$7054 $1\logical_op__imm_data__data$4$next[63:0]$7053 $1\logical_op__fn_unit$3$next[12:0]$7052 $1\logical_op__insn_type$2$next[6:0]$7057 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } - case - assign $1\logical_op__data_len$18$next[3:0]$7051 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[12:0]$7052 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$7053 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$7054 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$7055 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$7056 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$7057 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$7058 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$7059 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$7060 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$7061 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$7062 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$7063 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$7064 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$7065 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$7066 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$7067 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$7068 \logical_op__zero_a$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$7069 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$7070 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$7074 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$7073 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$7071 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$7072 1'0 - case - assign $2\logical_op__imm_data__data$4$next[63:0]$7069 $1\logical_op__imm_data__data$4$next[63:0]$7053 - assign $2\logical_op__imm_data__ok$5$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7054 - assign $2\logical_op__oe__oe$8$next[0:0]$7071 $1\logical_op__oe__oe$8$next[0:0]$7062 - assign $2\logical_op__oe__ok$9$next[0:0]$7072 $1\logical_op__oe__ok$9$next[0:0]$7063 - assign $2\logical_op__rc__ok$7$next[0:0]$7073 $1\logical_op__rc__ok$7$next[0:0]$7065 - assign $2\logical_op__rc__rc$6$next[0:0]$7074 $1\logical_op__rc__rc$6$next[0:0]$7066 - end - sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7033 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$7034 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7035 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7036 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7037 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7038 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7039 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7040 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7041 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7042 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7043 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7044 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7045 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7046 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7047 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7048 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7049 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7050 - end - attribute \src "libresoc.v:149271.3-149289.6" - process $proc$libresoc.v:149271$7075 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$20$next[63:0]$7076 $1\o$20$next[63:0]$7078 - assign { } { } - assign $0\o_ok$21$next[0:0]$7077 $2\o_ok$21$next[0:0]$7080 - attribute \src "libresoc.v:149272.5-149272.29" - switch \initial - attribute \src "libresoc.v:149272.9-149272.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$7079 $1\o$20$next[63:0]$7078 } { \o_ok$71 \o$70 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$7079 $1\o$20$next[63:0]$7078 } { \o_ok$71 \o$70 } - case - assign $1\o$20$next[63:0]$7078 \o$20 - assign $1\o_ok$21$next[0:0]$7079 \o_ok$21 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$21$next[0:0]$7080 1'0 - case - assign $2\o_ok$21$next[0:0]$7080 $1\o_ok$21$next[0:0]$7079 - end - sync always - update \o$20$next $0\o$20$next[63:0]$7076 - update \o_ok$21$next $0\o_ok$21$next[0:0]$7077 - end - attribute \src "libresoc.v:149290.3-149308.6" - process $proc$libresoc.v:149290$7081 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$22$next[3:0]$7082 $1\cr_a$22$next[3:0]$7084 - assign { } { } - assign $0\cr_a_ok$23$next[0:0]$7083 $2\cr_a_ok$23$next[0:0]$7086 - attribute \src "libresoc.v:149291.5-149291.29" - switch \initial - attribute \src "libresoc.v:149291.9-149291.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$7085 $1\cr_a$22$next[3:0]$7084 } { \cr_a_ok$73 \cr_a$72 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$7085 $1\cr_a$22$next[3:0]$7084 } { \cr_a_ok$73 \cr_a$72 } - case - assign $1\cr_a$22$next[3:0]$7084 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$7085 \cr_a_ok$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$23$next[0:0]$7086 1'0 - case - assign $2\cr_a_ok$23$next[0:0]$7086 $1\cr_a_ok$23$next[0:0]$7085 - end - sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$7082 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7083 - end - connect \$49 $and$libresoc.v:149093$6977_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } - connect { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } - connect { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } - connect \muxid$51 \output_muxid$24 - connect \p_valid_i_p_ready_o \$49 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$48 \p_valid_i - connect { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } - connect { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \output_muxid \muxid -end -attribute \src "ls180.v:4.1-11026.10" -attribute \cells_not_processed 1 -module \ls180 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 - attribute \src "ls180.v:10350.1-10368.4" - wire width 64 $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 - attribute \src "ls180.v:10378.1-10396.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 - attribute \src "ls180.v:10406.1-10424.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 - attribute \src "ls180.v:10434.1-10452.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 - attribute \src "ls180.v:10462.1-10480.4" - wire width 64 $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 - attribute \src "ls180.v:10490.1-10494.4" - wire width 3 $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 - attribute \src "ls180.v:10490.1-10494.4" - wire width 25 $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 - attribute \src "ls180.v:10490.1-10494.4" - wire width 25 $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 - attribute \src "ls180.v:10504.1-10508.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 - attribute \src "ls180.v:10504.1-10508.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 - attribute \src "ls180.v:10504.1-10508.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 - attribute \src "ls180.v:10518.1-10522.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 - attribute \src "ls180.v:10518.1-10522.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 - attribute \src "ls180.v:10518.1-10522.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 - attribute \src "ls180.v:10532.1-10536.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 - attribute \src "ls180.v:10532.1-10536.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 - attribute \src "ls180.v:10532.1-10536.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 - attribute \src "ls180.v:10547.1-10551.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 - attribute \src "ls180.v:10547.1-10551.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 - attribute \src "ls180.v:10547.1-10551.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 - attribute \src "ls180.v:10564.1-10568.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 - attribute \src "ls180.v:10564.1-10568.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 - attribute \src "ls180.v:10564.1-10568.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 - attribute \src "ls180.v:10580.1-10584.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 - attribute \src "ls180.v:10580.1-10584.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 - attribute \src "ls180.v:10580.1-10584.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 - attribute \src "ls180.v:10594.1-10598.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 - attribute \src "ls180.v:10594.1-10598.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 - attribute \src "ls180.v:10594.1-10598.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 - attribute \src "ls180.v:3399.1-3492.4" - wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3556.1-3649.4" - wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3713.1-3806.4" - wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3870.1-3963.4" - wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6788.1-6804.4" - wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:7009.1-7025.4" - wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:7026.1-7042.4" - wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:7094.1-7101.4" - wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:7102.1-7109.4" - wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:7110.1-7117.4" - wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:7118.1-7125.4" - wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:7126.1-7133.4" - wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:7134.1-7141.4" - wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:7142.1-7149.4" - wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:7150.1-7157.4" - wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6805.1-6821.4" - wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7158.1-7165.4" - wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:7166.1-7173.4" - wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:7174.1-7181.4" - wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:7182.1-7189.4" - wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:7190.1-7209.4" - wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:7210.1-7229.4" - wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] - attribute \src "ls180.v:7230.1-7249.4" - wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] - attribute \src "ls180.v:7250.1-7269.4" - wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:7270.1-7289.4" - wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:7290.1-7309.4" - wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6822.1-6838.4" - wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:7310.1-7329.4" - wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:7330.1-7349.4" - wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6839.1-6855.4" - wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6856.1-6872.4" - wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6873.1-6889.4" - wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6941.1-6957.4" - wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6958.1-6974.4" - wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6975.1-6991.4" - wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6992.1-7008.4" - wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6890.1-6906.4" - wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6907.1-6923.4" - wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6924.1-6940.4" - wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:7043.1-7059.4" - wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:7060.1-7076.4" - wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:7077.1-7093.4" - wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2903.1-2949.4" - wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2963.1-3009.4" - wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:3023.1-3069.4" - wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:4216.1-4262.4" - wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:6028.1-6039.4" - wire $0\builder_error[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5845.1-5881.4" - wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5845.1-5881.4" - wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1990.5-1990.55" - wire $0\builder_libresocsim_converted_interface_ack[0:0] - attribute \src "ls180.v:1986.12-1986.65" - wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] - attribute \src "ls180.v:1994.5-1994.55" - wire $0\builder_libresocsim_converted_interface_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5845.1-5881.4" - wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5845.1-5881.4" - wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5845.1-5881.4" - wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5845.1-5881.4" - wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5845.1-5881.4" - wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1976.12-1976.52" - wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] - attribute \src "ls180.v:1980.5-1980.44" - wire $0\builder_libresocsim_wishbone_cyc[0:0] - attribute \src "ls180.v:5845.1-5881.4" - wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1977.12-1977.54" - wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] - attribute \src "ls180.v:1979.11-1979.50" - wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] - attribute \src "ls180.v:1981.5-1981.44" - wire $0\builder_libresocsim_wishbone_stb[0:0] - attribute \src "ls180.v:1983.5-1983.43" - wire $0\builder_libresocsim_wishbone_we[0:0] - attribute \src "ls180.v:1875.5-1875.27" - wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1876.5-1876.27" - wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1877.5-1877.27" - wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1878.5-1878.27" - wire $0\builder_locked3[0:0] - attribute \src "ls180.v:4088.1-4160.4" - wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5845.1-5881.4" - wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3305.1-3335.4" - wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5643.1-5682.4" - wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:5210.1-5289.4" - wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5702.1-5739.4" - wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5740.1-5776.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4885.1-4957.4" - wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4730.1-4823.4" - wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4620.1-4696.4" - wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4857.1-4884.4" - wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4991.1-5092.4" - wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4586.1-4619.4" - wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:6028.1-6039.4" - wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:6028.1-6039.4" - wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5906.1-5921.4" - wire width 13 $0\builder_slave_sel[12:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 13 $0\builder_slave_sel_r[12:0] - attribute \src "ls180.v:4417.1-4465.4" - wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:4476.1-4524.4" - wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7469.1-7497.4" - wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7498.1-7526.4" - wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7350.1-7366.4" - wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7367.1-7383.4" - wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7384.1-7400.4" - wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7401.1-7417.4" - wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7418.1-7434.4" - wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7435.1-7451.4" - wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7452.1-7468.4" - wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:4396.1-4400.4" - wire width 16 $0\gpio_o[15:0] - attribute \src "ls180.v:4401.1-4405.4" - wire width 16 $0\gpio_oe[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_converter0_counter[0:0] - attribute \src "ls180.v:2903.1-2949.4" - wire $0\main_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2903.1-2949.4" - wire $0\main_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 64 $0\main_converter0_dat_r[63:0] - attribute \src "ls180.v:2903.1-2949.4" - wire $0\main_converter0_skip[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_converter1_counter[0:0] - attribute \src "ls180.v:2963.1-3009.4" - wire $0\main_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2963.1-3009.4" - wire $0\main_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 64 $0\main_converter1_dat_r[63:0] - attribute \src "ls180.v:2963.1-3009.4" - wire $0\main_converter1_skip[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:4216.1-4262.4" - wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:4216.1-4262.4" - wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:4216.1-4262.4" - wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 24 $0\main_dummy[23:0] - attribute \src "ls180.v:1082.12-1082.53" - wire width 16 $0\main_gpiotristateasic0_oe_storage[15:0] - attribute \src "ls180.v:1084.12-1084.54" - wire width 16 $0\main_gpiotristateasic0_out_storage[15:0] - attribute \src "ls180.v:7584.1-7594.4" - wire width 16 $0\main_gpiotristateasic0_status[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_gpiotristateasic1_oe_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_gpiotristateasic1_oe_storage[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_gpiotristateasic1_out_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_gpiotristateasic1_out_storage[15:0] - attribute \src "ls180.v:7595.1-7605.4" - wire width 16 $0\main_gpiotristateasic1_status[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_i2c_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_i2c_storage[2:0] - attribute \src "ls180.v:7626.1-7628.4" - wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1663.11-1663.41" - wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1662.11-1662.41" - wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:2903.1-2949.4" - wire $0\main_interface0_converted_interface_ack[0:0] - attribute \src "ls180.v:316.5-316.51" - wire $0\main_interface0_converted_interface_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:256.5-256.39" - wire $0\main_interface0_ram_bus_err[0:0] - attribute \src "ls180.v:5702.1-5739.4" - wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1754.11-1754.41" - wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1753.11-1753.41" - wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5702.1-5739.4" - wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1746.12-1746.45" - wire width 64 $0\main_interface1_bus_dat_w[63:0] - attribute \src "ls180.v:5702.1-5739.4" - wire width 8 $0\main_interface1_bus_sel[7:0] - attribute \src "ls180.v:5702.1-5739.4" - wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5702.1-5739.4" - wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:2963.1-3009.4" - wire $0\main_interface1_converted_interface_ack[0:0] - attribute \src "ls180.v:331.5-331.51" - wire $0\main_interface1_converted_interface_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:271.5-271.39" - wire $0\main_interface1_ram_bus_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_interface2_ram_bus_ack[0:0] - attribute \src "ls180.v:286.5-286.39" - wire $0\main_interface2_ram_bus_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_interface3_ram_bus_ack[0:0] - attribute \src "ls180.v:301.5-301.39" - wire $0\main_interface3_ram_bus_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:75.11-75.52" - wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] - attribute \src "ls180.v:74.11-74.52" - wire width 3 $0\main_libresocsim_libresoc_dbus_cti[2:0] - attribute \src "ls180.v:86.11-86.52" - wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] - attribute \src "ls180.v:85.11-85.52" - wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] - attribute \src "ls180.v:2884.1-2889.4" - wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:115.11-115.55" - wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] - attribute \src "ls180.v:114.11-114.55" - wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] - attribute \src "ls180.v:2903.1-2949.4" - wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] - attribute \src "ls180.v:2903.1-2949.4" - wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] - attribute \src "ls180.v:2891.1-2901.4" - wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - attribute \src "ls180.v:2903.1-2949.4" - wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] - attribute \src "ls180.v:2903.1-2949.4" - wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] - attribute \src "ls180.v:2903.1-2949.4" - wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] - attribute \src "ls180.v:2963.1-3009.4" - wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] - attribute \src "ls180.v:2963.1-3009.4" - wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] - attribute \src "ls180.v:2951.1-2961.4" - wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] - attribute \src "ls180.v:2963.1-3009.4" - wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] - attribute \src "ls180.v:2963.1-3009.4" - wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] - attribute \src "ls180.v:2963.1-3009.4" - wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:214.5-214.40" - wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:3072.1-3082.4" - wire width 8 $0\main_libresocsim_we[7:0] - attribute \src "ls180.v:3088.1-3093.4" - wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:4216.1-4262.4" - wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:4216.1-4262.4" - wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:4204.1-4214.4" - wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:4216.1-4262.4" - wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:4216.1-4262.4" - wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:4216.1-4262.4" - wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdblock2mem_converter_demux[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1687.5-1687.41" - wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5610.1-5617.4" - wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5643.1-5682.4" - wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5643.1-5682.4" - wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] - attribute \src "ls180.v:5643.1-5682.4" - wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5643.1-5682.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5643.1-5682.4" - wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5643.1-5682.4" - wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5643.1-5682.4" - wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5392.1-5582.4" - wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5392.1-5582.4" - wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1496.5-1496.34" - wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5298.1-5305.4" - wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5354.1-5361.4" - wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5308.1-5315.4" - wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5364.1-5371.4" - wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5318.1-5325.4" - wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5374.1-5381.4" - wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5328.1-5335.4" - wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5384.1-5391.4" - wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5343.1-5350.4" - wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1602.5-1602.50" - wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5337.1-5342.4" - wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:5290.1-5295.4" - wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:5210.1-5289.4" - wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:5210.1-5289.4" - wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:5172.1-5179.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:5182.1-5189.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:5192.1-5199.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:5202.1-5209.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:5210.1-5289.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:5210.1-5289.4" - wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:5210.1-5289.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:5210.1-5289.4" - wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:5210.1-5289.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:5210.1-5289.4" - wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:5210.1-5289.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:5210.1-5289.4" - wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:5210.1-5289.4" - wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1559.5-1559.51" - wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:5210.1-5289.4" - wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:5210.1-5289.4" - wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:5210.1-5289.4" - wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:5150.1-5157.4" - wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5392.1-5582.4" - wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdmem2block_converter_mux[2:0] - attribute \src "ls180.v:5788.1-5816.4" - wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 64 $0\main_sdmem2block_dma_data[63:0] - attribute \src "ls180.v:5702.1-5739.4" - wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - attribute \src "ls180.v:5702.1-5739.4" - wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5740.1-5776.4" - wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5740.1-5776.4" - wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5740.1-5776.4" - wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5740.1-5776.4" - wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5740.1-5776.4" - wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5702.1-5739.4" - wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5740.1-5776.4" - wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1767.5-1767.45" - wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5702.1-5739.4" - wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5702.1-5739.4" - wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] - attribute \src "ls180.v:5702.1-5739.4" - wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1823.5-1823.41" - wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5830.1-5837.4" - wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4556.1-4584.4" - wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1288.5-1288.53" - wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1289.5-1289.52" - wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1269.5-1269.46" - wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4730.1-4823.4" - wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1242.5-1242.49" - wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1243.5-1243.48" - wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1244.5-1244.55" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1246.5-1246.57" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1247.5-1247.58" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1249.11-1249.64" - wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1250.5-1250.59" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1255.11-1255.57" - wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1256.5-1256.52" - wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4730.1-4823.4" - wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4730.1-4823.4" - wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4730.1-4823.4" - wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4730.1-4823.4" - wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4620.1-4696.4" - wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4620.1-4696.4" - wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4620.1-4696.4" - wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4620.1-4696.4" - wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4620.1-4696.4" - wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4620.1-4696.4" - wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1232.11-1232.57" - wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1233.5-1233.52" - wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4620.1-4696.4" - wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4991.1-5092.4" - wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4991.1-5092.4" - wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1444.5-1444.55" - wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1445.5-1445.54" - wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1425.5-1425.48" - wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4991.1-5092.4" - wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4991.1-5092.4" - wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4991.1-5092.4" - wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1396.5-1396.50" - wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1397.5-1397.49" - wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1398.5-1398.56" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1400.5-1400.58" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1401.5-1401.59" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1403.11-1403.65" - wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1404.5-1404.60" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4991.1-5092.4" - wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1407.5-1407.51" - wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1408.5-1408.52" - wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1409.11-1409.58" - wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1410.5-1410.53" - wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4991.1-5092.4" - wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1417.5-1417.41" - wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4991.1-5092.4" - wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4991.1-5092.4" - wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4991.1-5092.4" - wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4991.1-5092.4" - wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4991.1-5092.4" - wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4991.1-5092.4" - wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4991.1-5092.4" - wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4885.1-4957.4" - wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4885.1-4957.4" - wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1366.5-1366.54" - wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1367.5-1367.53" - wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1347.5-1347.47" - wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4857.1-4884.4" - wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4857.1-4884.4" - wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4857.1-4884.4" - wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4857.1-4884.4" - wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1334.5-1334.50" - wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1335.5-1335.49" - wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1336.5-1336.56" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1337.5-1337.58" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1338.5-1338.58" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1339.5-1339.59" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1340.11-1340.65" - wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1341.11-1341.65" - wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1342.5-1342.60" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1332.5-1332.50" - wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4885.1-4957.4" - wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1321.5-1321.51" - wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1322.5-1322.52" - wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4885.1-4957.4" - wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4885.1-4957.4" - wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4885.1-4957.4" - wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5392.1-5582.4" - wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4885.1-4957.4" - wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4885.1-4957.4" - wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4857.1-4884.4" - wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4586.1-4619.4" - wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4586.1-4619.4" - wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1214.5-1214.40" - wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4586.1-4619.4" - wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4586.1-4619.4" - wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4586.1-4619.4" - wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4586.1-4619.4" - wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4586.1-4619.4" - wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3361.1-3368.4" - wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:536.5-536.64" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:519.5-519.67" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:520.5-520.66" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3383.1-3390.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3350.1-3357.4" - wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:4048.1-4056.4" - wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3399.1-3492.4" - wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:578.32-578.76" - wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:576.32-576.75" - wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3518.1-3525.4" - wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:618.5-618.64" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:601.5-601.67" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:602.5-602.66" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3540.1-3547.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3507.1-3514.4" - wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:4057.1-4065.4" - wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3556.1-3649.4" - wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:660.32-660.76" - wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:658.32-658.75" - wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3675.1-3682.4" - wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:700.5-700.64" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:683.5-683.67" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:684.5-684.66" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3697.1-3704.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3664.1-3671.4" - wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:4066.1-4074.4" - wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3713.1-3806.4" - wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:742.32-742.76" - wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:740.32-740.75" - wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3832.1-3839.4" - wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:782.5-782.64" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:765.5-765.67" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:766.5-766.66" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3854.1-3861.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3821.1-3828.4" - wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:4075.1-4083.4" - wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3870.1-3963.4" - wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:824.32-824.76" - wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:822.32-822.75" - wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3997.1-4002.4" - wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:4003.1-4008.4" - wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:4009.1-4014.4" - wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:832.5-832.43" - wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3983.1-3989.4" - wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:830.5-830.48" - wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:829.5-829.43" - wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:827.5-827.44" - wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:828.5-828.45" - wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:4030.1-4035.4" - wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:4036.1-4041.4" - wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:4042.1-4047.4" - wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:4088.1-4160.4" - wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:4016.1-4022.4" - wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:4088.1-4160.4" - wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:4088.1-4160.4" - wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:4088.1-4160.4" - wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3305.1-3335.4" - wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:480.5-480.42" - wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:481.5-481.43" - wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:4088.1-4160.4" - wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3305.1-3335.4" - wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:416.5-416.38" - wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:465.5-465.35" - wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:4088.1-4160.4" - wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:4088.1-4160.4" - wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:4184.1-4197.4" - wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:4184.1-4197.4" - wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:366.5-366.36" - wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3246.1-3262.4" - wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3246.1-3262.4" - wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3246.1-3262.4" - wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3246.1-3262.4" - wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:3188.1-3242.4" - wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:863.12-863.36" - wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:864.11-864.35" - wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3305.1-3335.4" - wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:3188.1-3242.4" - wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:3188.1-3242.4" - wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:866.5-866.31" - wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:867.5-867.31" - wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:4088.1-4160.4" - wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:871.32-871.63" - wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:869.32-869.63" - wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:3023.1-3069.4" - wire $0\main_socbushandler_converted_interface_ack[0:0] - attribute \src "ls180.v:918.5-918.54" - wire $0\main_socbushandler_converted_interface_err[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_socbushandler_counter[0:0] - attribute \src "ls180.v:3023.1-3069.4" - wire $0\main_socbushandler_counter_converter2_next_value[0:0] - attribute \src "ls180.v:3023.1-3069.4" - wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 64 $0\main_socbushandler_dat_r[63:0] - attribute \src "ls180.v:3023.1-3069.4" - wire $0\main_socbushandler_skip[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_spimaster11_storage[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spimaster12_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_spimaster16_storage[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spimaster17_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spimaster1_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_spimaster1_storage[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spimaster21_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spimaster22_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spimaster23_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spimaster24_re[0:0] - attribute \src "ls180.v:4417.1-4465.4" - wire $0\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:4417.1-4465.4" - wire $0\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_spimaster27_count[2:0] - attribute \src "ls180.v:4417.1-4465.4" - wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4417.1-4465.4" - wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4417.1-4465.4" - wire $0\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:4417.1-4465.4" - wire $0\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:4417.1-4465.4" - wire $0\main_spimaster2_done[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:4417.1-4465.4" - wire $0\main_spimaster3_irq[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1105.12-1105.47" - wire width 16 $0\main_spimaster8_clk_divider[15:0] - attribute \src "ls180.v:6553.1-6558.4" - wire $0\main_spimaster9_start[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:4476.1-4524.4" - wire $0\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 16 $0\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_spisdcard_count[2:0] - attribute \src "ls180.v:4476.1-4524.4" - wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:4476.1-4524.4" - wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:4476.1-4524.4" - wire $0\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:4476.1-4524.4" - wire $0\main_spisdcard_done0[0:0] - attribute \src "ls180.v:4476.1-4524.4" - wire $0\main_spisdcard_irq[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_spisdcard_miso[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:4476.1-4524.4" - wire $0\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:4476.1-4524.4" - wire $0\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 3 $0\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:6599.1-6604.4" - wire $0\main_spisdcard_start1[0:0] - attribute \src "ls180.v:3097.1-3107.4" - wire width 8 $0\main_sram0_we[7:0] - attribute \src "ls180.v:3111.1-3121.4" - wire width 8 $0\main_sram1_we[7:0] - attribute \src "ls180.v:3125.1-3135.4" - wire width 8 $0\main_sram2_we[7:0] - attribute \src "ls180.v:3139.1-3149.4" - wire width 8 $0\main_sram3_we[7:0] - attribute \src "ls180.v:4324.1-4328.4" - wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4313.1-4317.4" - wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_phy_re[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:954.5-954.38" - wire $0\main_uart_phy_source_first[0:0] - attribute \src "ls180.v:955.5-955.37" - wire $0\main_uart_phy_source_last[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 32 $0\main_uart_phy_storage[31:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 8 $0\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:1081.5-1081.27" - wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4318.1-4323.4" - wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1063.5-1063.37" - wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4376.1-4383.4" - wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4307.1-4312.4" - wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:1026.5-1026.37" - wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:1009.5-1009.40" - wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:1010.5-1010.39" - wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4346.1-4353.4" - wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:4216.1-4262.4" - wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:3023.1-3069.4" - wire width 30 $0\main_wb_sdram_adr[29:0] - attribute \src "ls180.v:3023.1-3069.4" - wire $0\main_wb_sdram_cyc[0:0] - attribute \src "ls180.v:3011.1-3021.4" - wire width 32 $0\main_wb_sdram_dat_w[31:0] - attribute \src "ls180.v:3023.1-3069.4" - wire width 4 $0\main_wb_sdram_sel[3:0] - attribute \src "ls180.v:3023.1-3069.4" - wire $0\main_wb_sdram_stb[0:0] - attribute \src "ls180.v:3023.1-3069.4" - wire $0\main_wb_sdram_we[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:10350.1-10368.4" - wire width 6 $0\memadr[5:0] - attribute \src "ls180.v:10378.1-10396.4" - wire width 6 $0\memadr_1[5:0] - attribute \src "ls180.v:10406.1-10424.4" - wire width 6 $0\memadr_2[5:0] - attribute \src "ls180.v:10434.1-10452.4" - wire width 6 $0\memadr_3[5:0] - attribute \src "ls180.v:10462.1-10480.4" - wire width 6 $0\memadr_4[5:0] - attribute \src "ls180.v:10490.1-10494.4" - wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10504.1-10508.4" - wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10518.1-10522.4" - wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10532.1-10536.4" - wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10547.1-10551.4" - wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10553.1-10556.4" - wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10564.1-10568.4" - wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10570.1-10573.4" - wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10580.1-10584.4" - wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10594.1-10598.4" - wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7702.1-10346.4" - wire width 2 $0\pwm[1:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7630.1-7700.4" - wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7630.1-7700.4" - wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7630.1-7700.4" - wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\spimaster_clk[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\spimaster_cs_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\spimaster_mosi[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:7702.1-10346.4" - wire $0\uart_tx[0:0] - attribute \src "ls180.v:1854.11-1854.49" - wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1853.11-1853.44" - wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1856.11-1856.49" - wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1855.11-1855.44" - wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1858.11-1858.49" - wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1857.11-1857.44" - wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1860.11-1860.49" - wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1859.11-1859.44" - wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2713.5-2713.41" - wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2726.5-2726.42" - wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2727.5-2727.42" - wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2731.12-2731.50" - wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2732.5-2732.42" - wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2733.5-2733.42" - wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2734.12-2734.50" - wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2735.5-2735.42" - wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2736.5-2736.42" - wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2737.12-2737.50" - wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2738.5-2738.42" - wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2714.12-2714.49" - wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2739.5-2739.42" - wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2740.12-2740.50" - wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2741.5-2741.42" - wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2742.5-2742.42" - wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2743.12-2743.50" - wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2744.12-2744.50" - wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] - attribute \src "ls180.v:2745.11-2745.48" - wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] - attribute \src "ls180.v:2746.5-2746.42" - wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2747.5-2747.42" - wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2748.5-2748.42" - wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2715.11-2715.47" - wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2749.11-2749.48" - wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2750.11-2750.48" - wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2716.5-2716.41" - wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2717.5-2717.41" - wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2718.5-2718.41" - wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2722.5-2722.41" - wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2723.12-2723.49" - wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2724.11-2724.47" - wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2725.5-2725.41" - wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2719.5-2719.39" - wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2720.5-2720.39" - wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2721.5-2721.39" - wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2728.5-2728.39" - wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2729.5-2729.39" - wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2730.5-2730.39" - wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1840.5-1840.41" - wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1839.5-1839.36" - wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1844.5-1844.41" - wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1843.5-1843.36" - wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1848.5-1848.41" - wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1847.5-1847.36" - wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1885.5-1885.40" - wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1884.5-1884.35" - wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:2013.12-2013.39" - wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:2010.5-2010.25" - wire $1\builder_error[0:0] - attribute \src "ls180.v:2007.11-2007.31" - wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:2017.11-2017.51" - wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2519.11-2519.52" - wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2552.11-2552.52" - wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2593.11-2593.52" - wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2658.11-2658.52" - wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2683.11-2683.52" - wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2058.11-2058.51" - wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2087.11-2087.51" - wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2100.11-2100.51" - wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2141.11-2141.51" - wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2182.11-2182.51" - wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2247.11-2247.51" - wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2380.11-2380.51" - wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2461.11-2461.51" - wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2478.11-2478.51" - wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1972.12-1972.43" - wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2709.12-2709.55" - wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2710.5-2710.50" - wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1974.11-1974.43" - wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2707.11-2707.55" - wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2708.5-2708.52" - wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1973.5-1973.34" - wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2711.5-2711.46" - wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2712.5-2712.49" - wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1982.5-1982.44" - wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1978.12-1978.54" - wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1862.11-1862.48" - wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1861.11-1861.43" - wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2816.32-2816.66" - wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2817.32-2817.66" - wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2836.32-2836.67" - wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2837.32-2837.67" - wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2838.32-2838.67" - wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2839.32-2839.67" - wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2840.32-2840.67" - wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2841.32-2841.67" - wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2842.32-2842.67" - wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2843.32-2843.67" - wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2844.32-2844.67" - wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2845.32-2845.67" - wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2846.32-2846.67" - wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2847.32-2847.67" - wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2848.32-2848.67" - wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2849.32-2849.67" - wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2818.32-2818.66" - wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2819.32-2819.66" - wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2820.32-2820.66" - wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2821.32-2821.66" - wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2822.32-2822.66" - wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2823.32-2823.66" - wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2824.32-2824.66" - wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2825.32-2825.66" - wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2826.32-2826.66" - wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2827.32-2827.66" - wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2828.32-2828.66" - wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2829.32-2829.66" - wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2830.32-2830.66" - wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2831.32-2831.66" - wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2832.32-2832.66" - wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2833.32-2833.66" - wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2834.32-2834.66" - wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2835.32-2835.66" - wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1880.5-1880.43" - wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1881.5-1881.43" - wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1882.5-1882.43" - wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1883.5-1883.43" - wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1879.5-1879.42" - wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2706.11-2706.36" - wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1852.11-1852.46" - wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1851.11-1851.41" - wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1961.11-1961.51" - wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1960.11-1960.46" - wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1929.5-1929.57" - wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1928.5-1928.52" - wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1941.11-1941.47" - wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1940.11-1940.42" - wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1965.5-1965.49" - wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1964.5-1964.44" - wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1969.11-1969.65" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1968.11-1968.60" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1917.11-1917.46" - wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1916.11-1916.41" - wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1905.11-1905.52" - wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1904.11-1904.47" - wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1901.11-1901.52" - wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1900.11-1900.47" - wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1913.5-1913.46" - wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1912.5-1912.41" - wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1921.11-1921.53" - wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1920.11-1920.48" - wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1897.5-1897.46" - wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1896.5-1896.41" - wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:2001.5-2001.30" - wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1997.12-1997.40" - wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:2008.12-2008.37" - wire width 13 $1\builder_slave_sel[12:0] - attribute \src "ls180.v:2009.12-2009.39" - wire width 13 $1\builder_slave_sel_r[12:0] - attribute \src "ls180.v:1889.11-1889.47" - wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1888.11-1888.42" - wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1893.11-1893.47" - wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1892.11-1892.42" - wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2705.11-2705.31" - wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2758.5-2758.39" - wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2759.5-2759.39" - wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2751.11-2751.47" - wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2752.12-2752.49" - wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2753.5-2753.41" - wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2754.5-2754.41" - wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2755.5-2755.41" - wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2756.5-2756.41" - wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2757.5-2757.41" - wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:935.5-935.29" - wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:318.5-318.35" - wire $1\main_converter0_counter[0:0] - attribute \src "ls180.v:1841.5-1841.57" - wire $1\main_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1842.5-1842.60" - wire $1\main_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:320.12-320.41" - wire width 64 $1\main_converter0_dat_r[63:0] - attribute \src "ls180.v:317.5-317.32" - wire $1\main_converter0_skip[0:0] - attribute \src "ls180.v:333.5-333.35" - wire $1\main_converter1_counter[0:0] - attribute \src "ls180.v:1845.5-1845.57" - wire $1\main_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1846.5-1846.60" - wire $1\main_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:335.12-335.41" - wire width 64 $1\main_converter1_dat_r[63:0] - attribute \src "ls180.v:332.5-332.32" - wire $1\main_converter1_skip[0:0] - attribute \src "ls180.v:932.5-932.34" - wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1886.5-1886.55" - wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1887.5-1887.58" - wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:934.12-934.40" - wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:931.5-931.31" - wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:354.12-354.38" - wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:355.5-355.36" - wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:1172.12-1172.30" - wire width 24 $1\main_dummy[23:0] - attribute \src "ls180.v:1083.12-1083.49" - wire width 16 $1\main_gpiotristateasic0_status[15:0] - attribute \src "ls180.v:1089.5-1089.40" - wire $1\main_gpiotristateasic1_oe_re[0:0] - attribute \src "ls180.v:1088.12-1088.53" - wire width 16 $1\main_gpiotristateasic1_oe_storage[15:0] - attribute \src "ls180.v:1093.5-1093.41" - wire $1\main_gpiotristateasic1_out_re[0:0] - attribute \src "ls180.v:1092.12-1092.54" - wire width 16 $1\main_gpiotristateasic1_out_storage[15:0] - attribute \src "ls180.v:1090.12-1090.49" - wire width 16 $1\main_gpiotristateasic1_status[15:0] - attribute \src "ls180.v:1197.5-1197.23" - wire $1\main_i2c_re[0:0] - attribute \src "ls180.v:1196.11-1196.34" - wire width 3 $1\main_i2c_storage[2:0] - attribute \src "ls180.v:339.5-339.24" - wire $1\main_int_rst[0:0] - attribute \src "ls180.v:312.5-312.51" - wire $1\main_interface0_converted_interface_ack[0:0] - attribute \src "ls180.v:252.5-252.39" - wire $1\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:1745.12-1745.43" - wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1749.5-1749.35" - wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1748.11-1748.41" - wire width 8 $1\main_interface1_bus_sel[7:0] - attribute \src "ls180.v:1750.5-1750.35" - wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1752.5-1752.34" - wire $1\main_interface1_bus_we[0:0] - attribute \src "ls180.v:327.5-327.51" - wire $1\main_interface1_converted_interface_ack[0:0] - attribute \src "ls180.v:267.5-267.39" - wire $1\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:282.5-282.39" - wire $1\main_interface2_ram_bus_ack[0:0] - attribute \src "ls180.v:297.5-297.39" - wire $1\main_interface3_ram_bus_ack[0:0] - attribute \src "ls180.v:63.12-63.47" - wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:224.5-224.34" - wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:223.5-223.39" - wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:244.5-244.44" - wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:243.5-243.49" - wire $1\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:65.12-65.55" - wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:88.12-88.58" - wire width 30 $1\main_libresocsim_libresoc_xics_icp_adr[29:0] - attribute \src "ls180.v:92.5-92.50" - wire $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] - attribute \src "ls180.v:89.12-89.60" - wire width 32 $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - attribute \src "ls180.v:91.11-91.56" - wire width 4 $1\main_libresocsim_libresoc_xics_icp_sel[3:0] - attribute \src "ls180.v:93.5-93.50" - wire $1\main_libresocsim_libresoc_xics_icp_stb[0:0] - attribute \src "ls180.v:95.5-95.49" - wire $1\main_libresocsim_libresoc_xics_icp_we[0:0] - attribute \src "ls180.v:97.12-97.58" - wire width 30 $1\main_libresocsim_libresoc_xics_ics_adr[29:0] - attribute \src "ls180.v:101.5-101.50" - wire $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] - attribute \src "ls180.v:98.12-98.60" - wire width 32 $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] - attribute \src "ls180.v:100.11-100.56" - wire width 4 $1\main_libresocsim_libresoc_xics_ics_sel[3:0] - attribute \src "ls180.v:102.5-102.50" - wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] - attribute \src "ls180.v:104.5-104.49" - wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] - attribute \src "ls180.v:220.5-220.36" - wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:219.12-219.49" - wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:210.5-210.40" - wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:222.5-222.38" - wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:221.12-221.51" - wire width 32 $1\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:56.5-56.37" - wire $1\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:55.5-55.42" - wire $1\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:58.5-58.39" - wire $1\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:57.12-57.60" - wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:226.5-226.44" - wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:225.5-225.49" - wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:245.12-245.42" - wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:227.12-227.49" - wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:217.11-217.37" - wire width 8 $1\main_libresocsim_we[7:0] - attribute \src "ls180.v:233.5-233.39" - wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:234.5-234.45" - wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:231.5-231.41" - wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:923.12-923.40" - wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:927.5-927.32" - wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:924.12-924.42" - wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:926.11-926.38" - wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:928.5-928.32" - wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:930.5-930.31" - wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:1176.12-1176.37" - wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1178.5-1178.31" - wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1177.5-1177.36" - wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1182.5-1182.31" - wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1181.12-1181.44" - wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1180.5-1180.30" - wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1179.12-1179.43" - wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1186.12-1186.37" - wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1188.5-1188.31" - wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1187.5-1187.36" - wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1192.5-1192.31" - wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1191.12-1191.44" - wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1190.5-1190.30" - wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1189.12-1189.43" - wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:356.11-356.32" - wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:1714.11-1714.50" - wire width 3 $1\main_sdblock2mem_converter_demux[2:0] - attribute \src "ls180.v:1710.5-1710.51" - wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1711.5-1711.50" - wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1712.12-1712.66" - wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] - attribute \src "ls180.v:1713.11-1713.77" - wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1716.5-1716.49" - wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1689.11-1689.47" - wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1686.11-1686.45" - wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1688.11-1688.47" - wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1690.11-1690.50" - wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1724.12-1724.62" - wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1725.12-1725.60" - wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] - attribute \src "ls180.v:1722.5-1722.45" - wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1732.5-1732.54" - wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1731.12-1731.67" - wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1736.5-1736.56" - wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1735.5-1735.61" - wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1734.5-1734.56" - wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1733.12-1733.69" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1740.5-1740.54" - wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1739.5-1739.59" - wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1742.12-1742.61" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1962.12-1962.87" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1963.5-1963.82" - wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1727.5-1727.57" - wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1737.5-1737.53" - wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1506.5-1506.38" - wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1505.12-1505.51" - wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1504.5-1504.39" - wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1503.11-1503.51" - wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1490.5-1490.39" - wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1489.12-1489.52" - wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1492.5-1492.38" - wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1491.12-1491.51" - wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1645.11-1645.39" - wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1946.11-1946.62" - wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1947.5-1947.59" - wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1646.5-1646.32" - wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1942.5-1942.55" - wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1943.5-1943.58" - wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1647.5-1647.33" - wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1950.5-1950.56" - wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1951.5-1951.59" - wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1497.13-1497.53" - wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1958.13-1958.76" - wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1959.5-1959.69" - wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1648.5-1648.35" - wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1952.5-1952.58" - wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1953.5-1953.61" - wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1606.11-1606.47" - wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1612.5-1612.46" - wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1611.12-1611.54" - wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1607.12-1607.58" - wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1619.5-1619.46" - wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1618.12-1618.54" - wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1614.12-1614.58" - wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1626.5-1626.46" - wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1625.12-1625.54" - wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1621.12-1621.58" - wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1633.5-1633.46" - wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1632.12-1632.54" - wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1628.12-1628.58" - wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1635.12-1635.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1636.12-1636.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1637.12-1637.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1638.12-1638.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1640.12-1640.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1641.12-1641.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1642.12-1642.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1643.12-1643.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1597.5-1597.48" - wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1598.5-1598.47" - wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1599.11-1599.61" - wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1596.5-1596.48" - wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1595.5-1595.48" - wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1600.5-1600.50" - wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1605.11-1605.47" - wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1639.5-1639.43" - wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1562.11-1562.48" - wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1938.11-1938.87" - wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1939.5-1939.84" - wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1567.12-1567.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1563.12-1563.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1574.12-1574.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1570.12-1570.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1581.12-1581.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1577.12-1577.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1588.12-1588.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1584.12-1584.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1591.12-1591.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1930.12-1930.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1931.5-1931.88" - wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1592.12-1592.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1932.12-1932.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1933.5-1933.88" - wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1593.12-1593.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1934.12-1934.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1935.5-1935.88" - wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1594.12-1594.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1936.12-1936.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1937.5-1937.88" - wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1553.5-1553.49" - wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1560.5-1560.50" - wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1561.11-1561.64" - wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1558.5-1558.51" - wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1557.5-1557.51" - wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1549.11-1549.47" - wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1507.11-1507.51" - wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1650.12-1650.42" - wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1948.12-1948.65" - wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1949.5-1949.60" - wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1651.5-1651.33" - wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1944.5-1944.56" - wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1945.5-1945.59" - wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1652.5-1652.34" - wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1954.5-1954.57" - wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1955.5-1955.60" - wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1653.5-1653.36" - wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1956.5-1956.59" - wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1957.5-1957.62" - wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1798.11-1798.48" - wire width 3 $1\main_sdmem2block_converter_mux[2:0] - attribute \src "ls180.v:1796.11-1796.64" - wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1772.5-1772.40" - wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1771.12-1771.53" - wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1770.12-1770.45" - wire width 64 $1\main_sdmem2block_dma_data[63:0] - attribute \src "ls180.v:1966.12-1966.75" - wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - attribute \src "ls180.v:1967.5-1967.70" - wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1777.5-1777.44" - wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1776.5-1776.42" - wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1775.5-1775.47" - wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1774.5-1774.42" - wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1773.12-1773.55" - wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1780.5-1780.40" - wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1779.5-1779.45" - wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1784.12-1784.47" - wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1970.12-1970.87" - wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1971.5-1971.82" - wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1763.5-1763.42" - wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1764.12-1764.61" - wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1762.5-1762.43" - wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1761.5-1761.43" - wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1768.5-1768.44" - wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1769.12-1769.60" - wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] - attribute \src "ls180.v:1765.5-1765.45" - wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1825.11-1825.47" - wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1822.11-1822.45" - wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1824.11-1824.47" - wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1826.11-1826.50" - wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1206.5-1206.35" - wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1209.5-1209.35" - wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1210.5-1210.36" - wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1208.11-1208.41" - wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1204.5-1204.33" - wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1203.11-1203.46" - wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1312.5-1312.49" - wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1313.5-1313.48" - wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1314.11-1314.62" - wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1310.5-1310.49" - wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1297.11-1297.54" - wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1293.5-1293.55" - wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1294.5-1294.54" - wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1295.11-1295.68" - wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1296.11-1296.81" - wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1299.5-1299.53" - wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1315.5-1315.38" - wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1910.5-1910.66" - wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1911.5-1911.69" - wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1285.5-1285.36" - wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1280.5-1280.53" - wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1267.11-1267.39" - wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1906.11-1906.67" - wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1907.5-1907.64" - wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1252.5-1252.48" - wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1253.5-1253.50" - wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1254.5-1254.51" - wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1259.5-1259.37" - wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1260.11-1260.53" - wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1258.5-1258.38" - wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1257.5-1257.38" - wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1263.5-1263.39" - wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1264.11-1264.53" - wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1265.11-1265.55" - wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1262.5-1262.40" - wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1261.5-1261.40" - wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1266.12-1266.48" - wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1908.12-1908.71" - wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1909.5-1909.66" - wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1239.11-1239.39" - wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1902.11-1902.66" - wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1903.5-1903.63" - wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1238.5-1238.32" - wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1229.5-1229.48" - wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1230.5-1230.50" - wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1231.5-1231.51" - wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1236.5-1236.37" - wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1237.11-1237.51" - wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1235.5-1235.38" - wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1234.5-1234.38" - wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1423.11-1423.41" - wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1922.11-1922.70" - wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1923.5-1923.66" - wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1468.5-1468.51" - wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1469.5-1469.50" - wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1470.11-1470.64" - wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1466.5-1466.51" - wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1453.5-1453.50" - wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1449.5-1449.57" - wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1450.5-1450.56" - wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1451.11-1451.70" - wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1452.11-1452.83" - wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1455.5-1455.55" - wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1471.5-1471.40" - wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1926.5-1926.69" - wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1927.5-1927.72" - wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1441.5-1441.38" - wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1436.5-1436.55" - wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1406.5-1406.49" - wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1413.5-1413.38" - wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1414.11-1414.61" - wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1412.5-1412.39" - wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1411.5-1411.39" - wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1418.5-1418.40" - wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1419.11-1419.54" - wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1420.11-1420.56" - wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1416.5-1416.41" - wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1415.5-1415.41" - wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1421.5-1421.33" - wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1422.12-1422.49" - wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1924.12-1924.73" - wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1925.5-1925.68" - wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1331.11-1331.40" - wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1918.11-1918.61" - wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1919.5-1919.58" - wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1390.5-1390.50" - wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1391.5-1391.49" - wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1392.11-1392.63" - wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1388.5-1388.50" - wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1375.11-1375.55" - wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1371.5-1371.56" - wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1372.5-1372.55" - wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1373.11-1373.69" - wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1374.11-1374.82" - wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1377.5-1377.54" - wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1393.5-1393.39" - wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1914.5-1914.66" - wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1915.5-1915.69" - wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1363.5-1363.37" - wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1358.5-1358.54" - wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1345.5-1345.34" - wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1320.5-1320.49" - wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1323.11-1323.58" - wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1324.5-1324.53" - wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1327.5-1327.39" - wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1328.5-1328.38" - wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1329.11-1329.52" - wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1326.5-1326.39" - wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1325.5-1325.39" - wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1343.5-1343.34" - wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1330.5-1330.33" - wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1344.5-1344.34" - wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1224.11-1224.39" - wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1898.11-1898.66" - wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1899.5-1899.63" - wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1219.5-1219.48" - wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1220.5-1220.50" - wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1221.5-1221.51" - wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1222.11-1222.57" - wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1223.5-1223.52" - wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1473.5-1473.35" - wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1476.11-1476.42" - wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:418.5-418.33" - wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:417.12-417.46" - wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:420.5-420.34" - wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:419.11-419.45" - wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:516.5-516.50" - wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:538.11-538.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:535.11-535.68" - wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:537.11-537.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:539.11-539.73" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:562.5-562.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:563.5-563.58" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:565.12-565.74" - wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:564.5-564.64" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:560.5-560.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:508.12-508.57" - wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:510.5-510.51" - wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:513.5-513.54" - wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:514.5-514.55" - wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:515.5-515.56" - wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:511.5-511.51" - wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:512.5-512.50" - wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:507.5-507.45" - wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:506.5-506.45" - wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:505.5-505.47" - wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:503.5-503.51" - wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:502.5-502.51" - wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:566.12-566.47" - wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:570.5-570.45" - wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:571.5-571.54" - wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:569.5-569.44" - wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:567.5-567.46" - wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:574.11-574.55" - wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:573.32-573.76" - wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:598.5-598.50" - wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:620.11-620.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:617.11-617.68" - wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:619.11-619.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:621.11-621.73" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:644.5-644.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:645.5-645.58" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:647.12-647.74" - wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:646.5-646.64" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:642.5-642.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:590.12-590.57" - wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:592.5-592.51" - wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:595.5-595.54" - wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:596.5-596.55" - wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:597.5-597.56" - wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:593.5-593.51" - wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:594.5-594.50" - wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:589.5-589.45" - wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:588.5-588.45" - wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:587.5-587.47" - wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:585.5-585.51" - wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:584.5-584.51" - wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:648.12-648.47" - wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:652.5-652.45" - wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:653.5-653.54" - wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:651.5-651.44" - wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:649.5-649.46" - wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:656.11-656.55" - wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:655.32-655.76" - wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:680.5-680.50" - wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:702.11-702.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:699.11-699.68" - wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:701.11-701.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:703.11-703.73" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:726.5-726.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:727.5-727.58" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:729.12-729.74" - wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:728.5-728.64" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:724.5-724.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:672.12-672.57" - wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:674.5-674.51" - wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:677.5-677.54" - wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:678.5-678.55" - wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:679.5-679.56" - wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:675.5-675.51" - wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:676.5-676.50" - wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:671.5-671.45" - wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:670.5-670.45" - wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:669.5-669.47" - wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:667.5-667.51" - wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:666.5-666.51" - wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:730.12-730.47" - wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:734.5-734.45" - wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:735.5-735.54" - wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:733.5-733.44" - wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:731.5-731.46" - wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:738.11-738.55" - wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:737.32-737.76" - wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:762.5-762.50" - wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:784.11-784.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:781.11-781.68" - wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:783.11-783.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:785.11-785.73" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:808.5-808.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:809.5-809.58" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:811.12-811.74" - wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:810.5-810.64" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:806.5-806.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:754.12-754.57" - wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:756.5-756.51" - wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:759.5-759.54" - wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:760.5-760.55" - wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:761.5-761.56" - wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:757.5-757.51" - wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:758.5-758.50" - wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:753.5-753.45" - wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:752.5-752.45" - wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:751.5-751.47" - wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:749.5-749.51" - wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:748.5-748.51" - wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:812.12-812.47" - wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:816.5-816.45" - wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:817.5-817.54" - wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:815.5-815.44" - wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:813.5-813.46" - wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:820.11-820.55" - wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:819.32-819.76" - wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:835.5-835.49" - wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:836.5-836.49" - wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:837.5-837.48" - wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:843.11-843.45" - wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:841.11-841.46" - wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:853.5-853.49" - wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:854.5-854.49" - wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:855.5-855.48" - wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:850.5-850.43" - wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:861.11-861.45" - wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:859.11-859.46" - wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:848.5-848.48" - wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:845.5-845.44" - wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:846.5-846.45" - wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:474.5-474.31" - wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:475.12-475.44" - wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:476.11-476.43" - wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:477.5-477.38" - wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:478.5-478.38" - wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:479.5-479.37" - wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:473.5-473.32" - wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:472.5-472.32" - wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:412.5-412.33" - wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:411.11-411.44" - wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:456.12-456.45" - wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:457.11-457.40" - wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:458.5-458.35" - wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:459.5-459.34" - wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:460.5-460.35" - wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:469.5-469.39" - wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:461.5-461.34" - wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:467.5-467.39" - wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:880.5-880.26" - wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:883.5-883.26" - wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:453.12-453.46" - wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:454.11-454.47" - wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:359.5-359.36" - wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:360.5-360.35" - wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:361.5-361.36" - wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:371.12-371.45" - wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:372.5-372.43" - wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:362.5-362.35" - wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:398.5-398.38" - wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:389.12-389.48" - wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:390.11-390.43" - wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:391.5-391.38" - wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:395.5-395.36" - wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:392.5-392.37" - wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:396.5-396.36" - wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:393.5-393.38" - wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:402.5-402.42" - wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:397.5-397.40" - wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:394.5-394.37" - wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:399.12-399.47" - wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:400.5-400.42" - wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:401.11-401.50" - wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:490.5-490.38" - wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:489.5-489.38" - wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:410.5-410.25" - wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:496.5-496.38" - wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:495.11-495.46" - wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:494.5-494.38" - wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:491.5-491.39" - wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:387.12-387.46" - wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:388.5-388.44" - wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:423.12-423.37" - wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:865.11-865.40" - wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:409.11-409.36" - wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:874.5-874.36" - wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:873.32-873.63" - wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:882.11-882.34" - wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:885.11-885.34" - wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:487.11-487.44" - wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:877.11-877.42" - wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:876.32-876.63" - wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:422.5-422.32" - wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:421.12-421.45" - wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:914.5-914.54" - wire $1\main_socbushandler_converted_interface_ack[0:0] - attribute \src "ls180.v:920.5-920.38" - wire $1\main_socbushandler_counter[0:0] - attribute \src "ls180.v:1849.5-1849.60" - wire $1\main_socbushandler_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1850.5-1850.63" - wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:922.12-922.44" - wire width 64 $1\main_socbushandler_dat_r[63:0] - attribute \src "ls180.v:919.5-919.35" - wire $1\main_socbushandler_skip[0:0] - attribute \src "ls180.v:1108.12-1108.44" - wire width 16 $1\main_spimaster11_storage[15:0] - attribute \src "ls180.v:1109.5-1109.31" - wire $1\main_spimaster12_re[0:0] - attribute \src "ls180.v:1113.11-1113.42" - wire width 8 $1\main_spimaster16_storage[7:0] - attribute \src "ls180.v:1114.5-1114.31" - wire $1\main_spimaster17_re[0:0] - attribute \src "ls180.v:1170.5-1170.30" - wire $1\main_spimaster1_re[0:0] - attribute \src "ls180.v:1169.12-1169.45" - wire width 16 $1\main_spimaster1_storage[15:0] - attribute \src "ls180.v:1118.5-1118.36" - wire $1\main_spimaster21_storage[0:0] - attribute \src "ls180.v:1119.5-1119.31" - wire $1\main_spimaster22_re[0:0] - attribute \src "ls180.v:1120.5-1120.36" - wire $1\main_spimaster23_storage[0:0] - attribute \src "ls180.v:1121.5-1121.31" - wire $1\main_spimaster24_re[0:0] - attribute \src "ls180.v:1122.5-1122.39" - wire $1\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:1123.5-1123.38" - wire $1\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:1124.11-1124.40" - wire width 3 $1\main_spimaster27_count[2:0] - attribute \src "ls180.v:1890.11-1890.62" - wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1891.5-1891.59" - wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:1125.5-1125.39" - wire $1\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:1126.5-1126.39" - wire $1\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:1099.5-1099.32" - wire $1\main_spimaster2_done[0:0] - attribute \src "ls180.v:1127.12-1127.48" - wire width 16 $1\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:1130.11-1130.44" - wire width 8 $1\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:1131.11-1131.43" - wire width 3 $1\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:1132.11-1132.44" - wire width 8 $1\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:1100.5-1100.31" - wire $1\main_spimaster3_irq[0:0] - attribute \src "ls180.v:1102.11-1102.38" - wire width 8 $1\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1106.5-1106.33" - wire $1\main_spimaster9_start[0:0] - attribute \src "ls180.v:1163.12-1163.47" - wire width 16 $1\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:1158.5-1158.37" - wire $1\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:1145.5-1145.37" - wire $1\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:1144.12-1144.50" - wire width 16 $1\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:1160.11-1160.38" - wire width 3 $1\main_spisdcard_count[2:0] - attribute \src "ls180.v:1894.11-1894.60" - wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1895.5-1895.57" - wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1159.5-1159.36" - wire $1\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:1155.5-1155.32" - wire $1\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:1154.5-1154.37" - wire $1\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:1135.5-1135.32" - wire $1\main_spisdcard_done0[0:0] - attribute \src "ls180.v:1136.5-1136.30" - wire $1\main_spisdcard_irq[0:0] - attribute \src "ls180.v:1157.5-1157.38" - wire $1\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:1156.5-1156.43" - wire $1\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:1138.11-1138.37" - wire width 8 $1\main_spisdcard_miso[7:0] - attribute \src "ls180.v:1168.11-1168.42" - wire width 8 $1\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:1162.5-1162.37" - wire $1\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:1166.11-1166.42" - wire width 8 $1\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:1161.5-1161.37" - wire $1\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:1150.5-1150.34" - wire $1\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:1167.11-1167.41" - wire width 3 $1\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:1149.11-1149.45" - wire width 8 $1\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:1142.5-1142.33" - wire $1\main_spisdcard_start1[0:0] - attribute \src "ls180.v:259.11-259.31" - wire width 8 $1\main_sram0_we[7:0] - attribute \src "ls180.v:274.11-274.31" - wire width 8 $1\main_sram1_we[7:0] - attribute \src "ls180.v:289.11-289.31" - wire width 8 $1\main_sram2_we[7:0] - attribute \src "ls180.v:304.11-304.31" - wire width 8 $1\main_sram3_we[7:0] - attribute \src "ls180.v:990.11-990.50" - wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:992.5-992.37" - wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:986.11-986.49" - wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:991.11-991.48" - wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:958.12-958.54" - wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:948.12-948.54" - wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:941.5-941.28" - wire $1\main_uart_phy_re[0:0] - attribute \src "ls180.v:962.11-962.43" - wire width 4 $1\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:963.5-963.33" - wire $1\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:960.5-960.30" - wire $1\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:961.11-961.38" - wire width 8 $1\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:943.5-943.36" - wire $1\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:956.11-956.51" - wire width 8 $1\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:952.5-952.38" - wire $1\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:940.12-940.47" - wire width 32 $1\main_uart_phy_storage[31:0] - attribute \src "ls180.v:950.11-950.43" - wire width 4 $1\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:951.5-951.33" - wire $1\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:949.11-949.38" - wire width 8 $1\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:957.5-957.39" - wire $1\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:947.5-947.39" - wire $1\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:981.5-981.30" - wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:1065.11-1065.43" - wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:1062.11-1062.42" - wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:1064.11-1064.43" - wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:1055.5-1055.38" - wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1066.11-1066.46" - wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:982.5-982.36" - wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:979.5-979.32" - wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:976.5-976.30" - wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:1028.11-1028.43" - wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:1025.11-1025.42" - wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:1027.11-1027.43" - wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:1018.5-1018.38" - wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:1029.11-1029.46" - wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:977.5-977.36" - wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:974.5-974.32" - wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:906.5-906.29" - wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:900.12-900.37" - wire width 30 $1\main_wb_sdram_adr[29:0] - attribute \src "ls180.v:904.5-904.29" - wire $1\main_wb_sdram_cyc[0:0] - attribute \src "ls180.v:901.12-901.39" - wire width 32 $1\main_wb_sdram_dat_w[31:0] - attribute \src "ls180.v:903.11-903.35" - wire width 4 $1\main_wb_sdram_sel[3:0] - attribute \src "ls180.v:905.5-905.29" - wire $1\main_wb_sdram_stb[0:0] - attribute \src "ls180.v:907.5-907.28" - wire $1\main_wb_sdram_we[0:0] - attribute \src "ls180.v:936.5-936.31" - wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2932.56-2932.86" - wire $add$ls180.v:2932$58_Y - attribute \src "ls180.v:2992.56-2992.86" - wire $add$ls180.v:2992$69_Y - attribute \src "ls180.v:3052.59-3052.92" - wire $add$ls180.v:3052$80_Y - attribute \src "ls180.v:4245.54-4245.83" - wire $add$ls180.v:4245$685_Y - attribute \src "ls180.v:4345.36-4345.89" - wire width 5 $add$ls180.v:4345$731_Y - attribute \src "ls180.v:4375.36-4375.89" - wire width 5 $add$ls180.v:4375$742_Y - attribute \src "ls180.v:4441.54-4441.83" - wire width 3 $add$ls180.v:4441$757_Y - attribute \src "ls180.v:4500.52-4500.79" - wire width 3 $add$ls180.v:4500$765_Y - attribute \src "ls180.v:4604.58-4604.86" - wire width 8 $add$ls180.v:4604$793_Y - attribute \src "ls180.v:4661.58-4661.86" - wire width 8 $add$ls180.v:4661$796_Y - attribute \src "ls180.v:4678.58-4678.86" - wire width 8 $add$ls180.v:4678$798_Y - attribute \src "ls180.v:4771.59-4771.87" - wire width 8 $add$ls180.v:4771$815_Y - attribute \src "ls180.v:4796.59-4796.87" - wire width 8 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$xor$ls180.v:5115$877_Y - attribute \src "ls180.v:5116.353-5116.425" - wire $xor$ls180.v:5116$878_Y - attribute \src "ls180.v:5116.200-5116.272" - wire $xor$ls180.v:5116$879_Y - attribute \src "ls180.v:5116.160-5116.273" - wire $xor$ls180.v:5116$880_Y - attribute \src "ls180.v:5117.353-5117.425" - wire $xor$ls180.v:5117$881_Y - attribute \src "ls180.v:5117.200-5117.272" - wire $xor$ls180.v:5117$882_Y - attribute \src "ls180.v:5117.160-5117.273" - wire $xor$ls180.v:5117$883_Y - attribute \src "ls180.v:5118.353-5118.425" - wire $xor$ls180.v:5118$884_Y - attribute \src "ls180.v:5118.200-5118.272" - wire $xor$ls180.v:5118$885_Y - attribute \src "ls180.v:5118.160-5118.273" - wire $xor$ls180.v:5118$886_Y - attribute \src "ls180.v:5119.354-5119.426" - wire $xor$ls180.v:5119$887_Y - attribute \src "ls180.v:5119.201-5119.273" - wire $xor$ls180.v:5119$888_Y - attribute \src "ls180.v:5119.161-5119.274" - wire $xor$ls180.v:5119$889_Y - attribute \src "ls180.v:5120.361-5120.434" - wire $xor$ls180.v:5120$890_Y - attribute \src "ls180.v:5120.205-5120.278" - wire $xor$ls180.v:5120$891_Y - attribute \src "ls180.v:5120.164-5120.279" - wire $xor$ls180.v:5120$892_Y - attribute \src "ls180.v:5121.361-5121.434" - wire $xor$ls180.v:5121$893_Y - attribute \src "ls180.v:5121.205-5121.278" - wire $xor$ls180.v:5121$894_Y - attribute \src "ls180.v:5121.164-5121.279" - wire $xor$ls180.v:5121$895_Y - attribute \src "ls180.v:5122.361-5122.434" - wire $xor$ls180.v:5122$896_Y - attribute \src "ls180.v:5122.205-5122.278" - wire $xor$ls180.v:5122$897_Y - attribute \src "ls180.v:5122.164-5122.279" - wire $xor$ls180.v:5122$898_Y - attribute \src "ls180.v:5123.361-5123.434" - wire $xor$ls180.v:5123$899_Y - attribute \src "ls180.v:5123.205-5123.278" - wire $xor$ls180.v:5123$900_Y - attribute \src "ls180.v:5123.164-5123.279" - wire $xor$ls180.v:5123$901_Y - attribute \src "ls180.v:5124.361-5124.434" - wire $xor$ls180.v:5124$902_Y - attribute \src "ls180.v:5124.205-5124.278" - wire $xor$ls180.v:5124$903_Y - attribute \src "ls180.v:5124.164-5124.279" - wire $xor$ls180.v:5124$904_Y - attribute \src "ls180.v:5125.361-5125.434" - wire $xor$ls180.v:5125$905_Y - attribute \src "ls180.v:5125.205-5125.278" - wire $xor$ls180.v:5125$906_Y - attribute \src "ls180.v:5125.164-5125.279" - wire $xor$ls180.v:5125$907_Y - attribute \src "ls180.v:5126.361-5126.434" - wire $xor$ls180.v:5126$908_Y - attribute \src "ls180.v:5126.205-5126.278" - wire $xor$ls180.v:5126$909_Y - attribute \src "ls180.v:5126.164-5126.279" - wire $xor$ls180.v:5126$910_Y - attribute \src "ls180.v:5127.361-5127.434" - wire $xor$ls180.v:5127$911_Y - attribute \src "ls180.v:5127.205-5127.278" - wire $xor$ls180.v:5127$912_Y - attribute \src "ls180.v:5127.164-5127.279" - wire $xor$ls180.v:5127$913_Y - attribute \src "ls180.v:5128.361-5128.434" - wire $xor$ls180.v:5128$914_Y - attribute \src "ls180.v:5128.205-5128.278" - wire $xor$ls180.v:5128$915_Y - attribute \src "ls180.v:5128.164-5128.279" - wire $xor$ls180.v:5128$916_Y - attribute \src "ls180.v:5129.361-5129.434" - wire $xor$ls180.v:5129$917_Y - attribute \src "ls180.v:5129.205-5129.278" - wire $xor$ls180.v:5129$918_Y - attribute \src "ls180.v:5129.164-5129.279" - wire $xor$ls180.v:5129$919_Y - attribute \src "ls180.v:5130.361-5130.434" - wire $xor$ls180.v:5130$920_Y - attribute \src "ls180.v:5130.205-5130.278" - wire $xor$ls180.v:5130$921_Y - attribute \src "ls180.v:5130.164-5130.279" - wire $xor$ls180.v:5130$922_Y - attribute \src "ls180.v:5131.361-5131.434" - wire $xor$ls180.v:5131$923_Y - attribute \src "ls180.v:5131.205-5131.278" - wire $xor$ls180.v:5131$924_Y - attribute \src "ls180.v:5131.164-5131.279" - wire $xor$ls180.v:5131$925_Y - attribute \src "ls180.v:5132.361-5132.434" - wire $xor$ls180.v:5132$926_Y - attribute \src "ls180.v:5132.205-5132.278" - wire $xor$ls180.v:5132$927_Y - attribute \src "ls180.v:5132.164-5132.279" - wire $xor$ls180.v:5132$928_Y - attribute \src "ls180.v:5133.361-5133.434" - wire $xor$ls180.v:5133$929_Y - attribute \src "ls180.v:5133.205-5133.278" - wire $xor$ls180.v:5133$930_Y - attribute \src "ls180.v:5133.164-5133.279" - wire $xor$ls180.v:5133$931_Y - attribute \src "ls180.v:5134.361-5134.434" - wire $xor$ls180.v:5134$932_Y - attribute \src "ls180.v:5134.205-5134.278" - wire $xor$ls180.v:5134$933_Y - attribute \src "ls180.v:5134.164-5134.279" - wire $xor$ls180.v:5134$934_Y - attribute \src "ls180.v:5135.361-5135.434" - wire $xor$ls180.v:5135$935_Y - attribute \src "ls180.v:5135.205-5135.278" - wire $xor$ls180.v:5135$936_Y - attribute \src "ls180.v:5135.164-5135.279" - wire $xor$ls180.v:5135$937_Y - attribute \src "ls180.v:5136.361-5136.434" - wire $xor$ls180.v:5136$938_Y - attribute \src "ls180.v:5136.205-5136.278" - wire $xor$ls180.v:5136$939_Y - attribute \src "ls180.v:5136.164-5136.279" - wire $xor$ls180.v:5136$940_Y - attribute \src "ls180.v:5137.361-5137.434" - wire $xor$ls180.v:5137$941_Y - attribute \src "ls180.v:5137.205-5137.278" - wire $xor$ls180.v:5137$942_Y - attribute \src "ls180.v:5137.164-5137.279" - wire $xor$ls180.v:5137$943_Y - attribute \src "ls180.v:5138.361-5138.434" - wire $xor$ls180.v:5138$944_Y - attribute \src "ls180.v:5138.205-5138.278" - wire $xor$ls180.v:5138$945_Y - attribute \src "ls180.v:5138.164-5138.279" - wire $xor$ls180.v:5138$946_Y - attribute \src "ls180.v:5139.361-5139.434" - wire $xor$ls180.v:5139$947_Y - attribute \src "ls180.v:5139.205-5139.278" - wire $xor$ls180.v:5139$948_Y - attribute \src "ls180.v:5139.164-5139.279" - wire $xor$ls180.v:5139$949_Y - attribute \src "ls180.v:5140.360-5140.432" - wire $xor$ls180.v:5140$950_Y - attribute \src "ls180.v:5140.205-5140.277" - wire $xor$ls180.v:5140$951_Y - attribute \src "ls180.v:5140.164-5140.278" - wire $xor$ls180.v:5140$952_Y - attribute \src "ls180.v:5141.360-5141.432" - wire $xor$ls180.v:5141$953_Y - attribute \src "ls180.v:5141.205-5141.277" - wire $xor$ls180.v:5141$954_Y - attribute \src "ls180.v:5141.164-5141.278" - wire $xor$ls180.v:5141$955_Y - attribute \src "ls180.v:5142.360-5142.432" - wire $xor$ls180.v:5142$956_Y - attribute \src "ls180.v:5142.205-5142.277" - wire $xor$ls180.v:5142$957_Y - attribute \src "ls180.v:5142.164-5142.278" - wire $xor$ls180.v:5142$958_Y - attribute \src "ls180.v:5143.360-5143.432" - wire $xor$ls180.v:5143$959_Y - attribute \src "ls180.v:5143.205-5143.277" - wire $xor$ls180.v:5143$960_Y - attribute \src "ls180.v:5143.164-5143.278" - wire $xor$ls180.v:5143$961_Y - attribute \src "ls180.v:5144.360-5144.432" - wire $xor$ls180.v:5144$962_Y - attribute \src "ls180.v:5144.205-5144.277" - wire $xor$ls180.v:5144$963_Y - attribute \src "ls180.v:5144.164-5144.278" - wire $xor$ls180.v:5144$964_Y - attribute \src "ls180.v:5145.360-5145.432" - wire $xor$ls180.v:5145$965_Y - attribute \src "ls180.v:5145.205-5145.277" - wire $xor$ls180.v:5145$966_Y - attribute \src "ls180.v:5145.164-5145.278" - wire $xor$ls180.v:5145$967_Y - attribute \src "ls180.v:5146.360-5146.432" - wire $xor$ls180.v:5146$968_Y - attribute \src "ls180.v:5146.205-5146.277" - wire $xor$ls180.v:5146$969_Y - attribute \src "ls180.v:5146.164-5146.278" - wire $xor$ls180.v:5146$970_Y - attribute \src "ls180.v:5147.360-5147.432" - wire $xor$ls180.v:5147$971_Y - attribute \src "ls180.v:5147.205-5147.277" - wire $xor$ls180.v:5147$972_Y - attribute \src "ls180.v:5147.164-5147.278" - wire $xor$ls180.v:5147$973_Y - attribute \src "ls180.v:5148.360-5148.432" - wire $xor$ls180.v:5148$974_Y - attribute \src "ls180.v:5148.205-5148.277" - wire $xor$ls180.v:5148$975_Y - attribute \src "ls180.v:5148.164-5148.278" - wire $xor$ls180.v:5148$976_Y - attribute \src "ls180.v:5149.360-5149.432" - wire $xor$ls180.v:5149$977_Y - attribute \src "ls180.v:5149.205-5149.277" - wire $xor$ls180.v:5149$978_Y - attribute \src "ls180.v:5149.164-5149.278" - wire $xor$ls180.v:5149$979_Y - attribute \src "ls180.v:5170.899-5170.983" - wire $xor$ls180.v:5170$993_Y - attribute \src "ls180.v:5170.634-5170.718" - wire $xor$ls180.v:5170$994_Y - attribute \src "ls180.v:5170.588-5170.719" - wire $xor$ls180.v:5170$995_Y - attribute \src "ls180.v:5170.234-5170.318" - wire $xor$ls180.v:5170$996_Y - attribute \src "ls180.v:5170.187-5170.319" - wire $xor$ls180.v:5170$997_Y - attribute \src "ls180.v:5171.588-5171.719" - wire $xor$ls180.v:5171$1000_Y - attribute \src "ls180.v:5171.234-5171.318" - wire $xor$ls180.v:5171$1001_Y - attribute \src "ls180.v:5171.187-5171.319" - wire $xor$ls180.v:5171$1002_Y - attribute \src "ls180.v:5171.899-5171.983" - wire $xor$ls180.v:5171$998_Y - attribute \src "ls180.v:5171.634-5171.718" - wire $xor$ls180.v:5171$999_Y - attribute \src "ls180.v:5180.899-5180.983" - wire $xor$ls180.v:5180$1004_Y - attribute \src "ls180.v:5180.634-5180.718" - wire $xor$ls180.v:5180$1005_Y - attribute \src "ls180.v:5180.588-5180.719" - wire $xor$ls180.v:5180$1006_Y - attribute \src "ls180.v:5180.234-5180.318" - wire $xor$ls180.v:5180$1007_Y - attribute \src "ls180.v:5180.187-5180.319" - wire $xor$ls180.v:5180$1008_Y - attribute \src "ls180.v:5181.899-5181.983" - wire $xor$ls180.v:5181$1009_Y - attribute \src "ls180.v:5181.634-5181.718" - wire $xor$ls180.v:5181$1010_Y - attribute \src "ls180.v:5181.588-5181.719" - wire $xor$ls180.v:5181$1011_Y - attribute \src "ls180.v:5181.234-5181.318" - wire $xor$ls180.v:5181$1012_Y - attribute \src "ls180.v:5181.187-5181.319" - wire $xor$ls180.v:5181$1013_Y - attribute \src "ls180.v:5190.899-5190.983" - wire $xor$ls180.v:5190$1015_Y - attribute \src "ls180.v:5190.634-5190.718" - wire $xor$ls180.v:5190$1016_Y - attribute \src "ls180.v:5190.588-5190.719" - wire $xor$ls180.v:5190$1017_Y - attribute \src "ls180.v:5190.234-5190.318" - wire $xor$ls180.v:5190$1018_Y - attribute \src "ls180.v:5190.187-5190.319" - wire $xor$ls180.v:5190$1019_Y - attribute \src "ls180.v:5191.899-5191.983" - wire $xor$ls180.v:5191$1020_Y - attribute \src "ls180.v:5191.634-5191.718" - wire $xor$ls180.v:5191$1021_Y - attribute \src "ls180.v:5191.588-5191.719" - wire $xor$ls180.v:5191$1022_Y - attribute \src "ls180.v:5191.234-5191.318" - wire $xor$ls180.v:5191$1023_Y - attribute \src "ls180.v:5191.187-5191.319" - wire $xor$ls180.v:5191$1024_Y - attribute \src "ls180.v:5200.899-5200.983" - wire $xor$ls180.v:5200$1026_Y - attribute \src "ls180.v:5200.634-5200.718" - wire $xor$ls180.v:5200$1027_Y - attribute \src "ls180.v:5200.588-5200.719" - wire $xor$ls180.v:5200$1028_Y - attribute \src "ls180.v:5200.234-5200.318" - wire $xor$ls180.v:5200$1029_Y - attribute \src "ls180.v:5200.187-5200.319" - wire $xor$ls180.v:5200$1030_Y - attribute \src "ls180.v:5201.899-5201.983" - wire $xor$ls180.v:5201$1031_Y - attribute \src "ls180.v:5201.634-5201.718" - wire $xor$ls180.v:5201$1032_Y - attribute \src "ls180.v:5201.588-5201.719" - wire $xor$ls180.v:5201$1033_Y - attribute \src "ls180.v:5201.234-5201.318" - wire $xor$ls180.v:5201$1034_Y - attribute \src "ls180.v:5201.187-5201.319" - wire $xor$ls180.v:5201$1035_Y - attribute \src "ls180.v:5352.879-5352.961" - wire $xor$ls180.v:5352$1068_Y - attribute \src "ls180.v:5352.620-5352.702" - wire $xor$ls180.v:5352$1069_Y - attribute \src "ls180.v:5352.575-5352.703" - wire $xor$ls180.v:5352$1070_Y - attribute \src "ls180.v:5352.229-5352.311" - wire $xor$ls180.v:5352$1071_Y - attribute \src "ls180.v:5352.183-5352.312" - wire $xor$ls180.v:5352$1072_Y - attribute \src "ls180.v:5353.879-5353.961" - wire $xor$ls180.v:5353$1073_Y - attribute \src "ls180.v:5353.620-5353.702" - wire $xor$ls180.v:5353$1074_Y - attribute \src "ls180.v:5353.575-5353.703" - wire $xor$ls180.v:5353$1075_Y - attribute \src "ls180.v:5353.229-5353.311" - wire $xor$ls180.v:5353$1076_Y - attribute \src "ls180.v:5353.183-5353.312" - wire $xor$ls180.v:5353$1077_Y - attribute \src "ls180.v:5362.879-5362.961" - wire $xor$ls180.v:5362$1079_Y - attribute \src "ls180.v:5362.620-5362.702" - wire $xor$ls180.v:5362$1080_Y - attribute \src "ls180.v:5362.575-5362.703" - wire $xor$ls180.v:5362$1081_Y - attribute \src "ls180.v:5362.229-5362.311" - wire $xor$ls180.v:5362$1082_Y - attribute \src "ls180.v:5362.183-5362.312" - wire $xor$ls180.v:5362$1083_Y - attribute \src "ls180.v:5363.879-5363.961" - wire $xor$ls180.v:5363$1084_Y - attribute \src "ls180.v:5363.620-5363.702" - wire $xor$ls180.v:5363$1085_Y - attribute \src "ls180.v:5363.575-5363.703" - wire $xor$ls180.v:5363$1086_Y - attribute \src "ls180.v:5363.229-5363.311" - wire $xor$ls180.v:5363$1087_Y - attribute \src "ls180.v:5363.183-5363.312" - wire $xor$ls180.v:5363$1088_Y - attribute \src "ls180.v:5372.879-5372.961" - wire $xor$ls180.v:5372$1090_Y - attribute \src "ls180.v:5372.620-5372.702" - wire $xor$ls180.v:5372$1091_Y - attribute \src "ls180.v:5372.575-5372.703" - wire $xor$ls180.v:5372$1092_Y - attribute \src "ls180.v:5372.229-5372.311" - wire $xor$ls180.v:5372$1093_Y - attribute \src "ls180.v:5372.183-5372.312" - wire $xor$ls180.v:5372$1094_Y - attribute \src "ls180.v:5373.879-5373.961" - wire $xor$ls180.v:5373$1095_Y - attribute \src "ls180.v:5373.620-5373.702" - wire $xor$ls180.v:5373$1096_Y - attribute \src "ls180.v:5373.575-5373.703" - wire $xor$ls180.v:5373$1097_Y - attribute \src "ls180.v:5373.229-5373.311" - wire $xor$ls180.v:5373$1098_Y - attribute \src "ls180.v:5373.183-5373.312" - wire $xor$ls180.v:5373$1099_Y - attribute \src "ls180.v:5382.879-5382.961" - wire $xor$ls180.v:5382$1101_Y - attribute \src "ls180.v:5382.620-5382.702" - wire $xor$ls180.v:5382$1102_Y - attribute \src "ls180.v:5382.575-5382.703" - wire $xor$ls180.v:5382$1103_Y - attribute \src "ls180.v:5382.229-5382.311" - wire $xor$ls180.v:5382$1104_Y - attribute \src "ls180.v:5382.183-5382.312" - wire $xor$ls180.v:5382$1105_Y - attribute \src "ls180.v:5383.879-5383.961" - wire $xor$ls180.v:5383$1106_Y - attribute \src "ls180.v:5383.620-5383.702" - wire $xor$ls180.v:5383$1107_Y - attribute \src "ls180.v:5383.575-5383.703" - wire $xor$ls180.v:5383$1108_Y - attribute \src "ls180.v:5383.229-5383.311" - wire $xor$ls180.v:5383$1109_Y - attribute \src "ls180.v:5383.183-5383.312" - wire $xor$ls180.v:5383$1110_Y - attribute \src "ls180.v:1854.11-1854.42" - wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1853.11-1853.37" - wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1856.11-1856.42" - wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1855.11-1855.37" - wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1858.11-1858.42" - wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1857.11-1857.37" - wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1860.11-1860.42" - wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1859.11-1859.37" - wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2713.5-2713.34" - wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2714.12-2714.41" - wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2726.5-2726.35" - wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2727.5-2727.35" - wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2731.12-2731.42" - wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2732.5-2732.35" - wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2733.5-2733.35" - wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2734.12-2734.42" - wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2735.5-2735.35" - wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2736.5-2736.35" - wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2737.12-2737.42" - wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2738.5-2738.35" - wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2715.11-2715.40" - wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2739.5-2739.35" - wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2740.12-2740.42" - wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2741.5-2741.35" - wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2742.5-2742.35" - wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2743.12-2743.42" - wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2744.12-2744.42" - wire width 64 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2745.11-2745.41" - wire width 8 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2746.5-2746.35" - wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2747.5-2747.35" - wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2748.5-2748.35" - wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2716.5-2716.34" - wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2749.11-2749.41" - wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2750.11-2750.41" - wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2717.5-2717.34" - wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2718.5-2718.34" - wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2722.5-2722.34" - wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2723.12-2723.41" - wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2724.11-2724.40" - wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2725.5-2725.34" - wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2719.5-2719.32" - wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2720.5-2720.32" - wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2721.5-2721.32" - wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2728.5-2728.32" - wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2729.5-2729.32" - wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2730.5-2730.32" - wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1840.5-1840.34" - wire \builder_converter0_next_state - attribute \src "ls180.v:1839.5-1839.29" - wire \builder_converter0_state - attribute \src "ls180.v:1844.5-1844.34" - wire \builder_converter1_next_state - attribute \src "ls180.v:1843.5-1843.29" - wire \builder_converter1_state - attribute \src "ls180.v:1848.5-1848.34" - wire \builder_converter2_next_state - attribute \src "ls180.v:1847.5-1847.29" - wire \builder_converter2_state - attribute \src "ls180.v:1885.5-1885.33" - wire \builder_converter_next_state - attribute \src "ls180.v:1884.5-1884.28" - wire \builder_converter_state - attribute \src "ls180.v:2013.12-2013.25" - wire width 20 \builder_count - attribute \src "ls180.v:2701.13-2701.41" - wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2704.12-2704.42" - wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2703.12-2703.42" - wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2702.6-2702.33" - wire \builder_csr_interconnect_we - attribute \src "ls180.v:2051.12-2051.42" - wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:2050.6-2050.37" - wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:2053.12-2053.42" - wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:2052.6-2052.37" - wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:2047.12-2047.42" - wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:2046.6-2046.37" - wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:2049.12-2049.42" - wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:2048.6-2048.37" - wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:2043.12-2043.42" - wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:2042.6-2042.37" - wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:2045.12-2045.42" - wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:2044.6-2044.37" - wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:2039.12-2039.42" - wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:2038.6-2038.37" - wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:2041.12-2041.42" - wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:2040.6-2040.37" - wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:2019.6-2019.31" - wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:2018.6-2018.32" - wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:2021.6-2021.31" - wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:2020.6-2020.32" - wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:2035.12-2035.39" - wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:2034.6-2034.34" - wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:2037.12-2037.39" - wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:2036.6-2036.34" - wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:2031.12-2031.39" - wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:2030.6-2030.34" - wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:2033.12-2033.39" - wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:2032.6-2032.34" - wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:2027.12-2027.39" - wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:2026.6-2026.34" - wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:2029.12-2029.39" - wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:2028.6-2028.34" - wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:2023.12-2023.39" - wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:2022.6-2022.34" - wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:2025.12-2025.39" - wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:2024.6-2024.34" - wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:2054.6-2054.26" - wire \builder_csrbank0_sel - attribute \src "ls180.v:2525.12-2525.40" - wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2524.6-2524.35" - wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2527.12-2527.40" - wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2526.6-2526.35" - wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2521.12-2521.40" - wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2520.6-2520.35" - wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2523.12-2523.40" - wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2522.6-2522.35" - wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2541.6-2541.29" - wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2540.6-2540.30" - wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2543.6-2543.29" - wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2542.6-2542.30" - wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2545.6-2545.35" - wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2544.6-2544.36" - wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2547.6-2547.35" - wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2546.6-2546.36" - wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2537.12-2537.36" - wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2536.6-2536.31" - wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2539.12-2539.36" - wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2538.6-2538.31" - wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2533.12-2533.37" - wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2532.6-2532.32" - wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2535.12-2535.37" - wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2534.6-2534.32" - wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2548.6-2548.27" - wire \builder_csrbank10_sel - attribute \src "ls180.v:2529.6-2529.32" - wire \builder_csrbank10_status_r - attribute \src "ls180.v:2528.6-2528.33" - wire \builder_csrbank10_status_re - attribute \src "ls180.v:2531.6-2531.32" - wire \builder_csrbank10_status_w - attribute \src "ls180.v:2530.6-2530.33" - wire \builder_csrbank10_status_we - attribute \src "ls180.v:2586.12-2586.44" - wire width 8 \builder_csrbank11_clk_divider0_r - attribute \src "ls180.v:2585.6-2585.39" - wire \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:2588.12-2588.44" - wire width 8 \builder_csrbank11_clk_divider0_w - attribute \src "ls180.v:2587.6-2587.39" - wire \builder_csrbank11_clk_divider0_we - attribute \src "ls180.v:2582.12-2582.44" - wire width 8 \builder_csrbank11_clk_divider1_r - attribute \src "ls180.v:2581.6-2581.39" - wire \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:2584.12-2584.44" - wire width 8 \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:2583.6-2583.39" - wire \builder_csrbank11_clk_divider1_we - attribute \src "ls180.v:2558.12-2558.40" - wire width 8 \builder_csrbank11_control0_r - attribute \src "ls180.v:2557.6-2557.35" - wire \builder_csrbank11_control0_re - attribute \src "ls180.v:2560.12-2560.40" - wire width 8 \builder_csrbank11_control0_w - attribute \src "ls180.v:2559.6-2559.35" - wire \builder_csrbank11_control0_we - attribute \src "ls180.v:2554.12-2554.40" - wire width 8 \builder_csrbank11_control1_r - attribute \src "ls180.v:2553.6-2553.35" - wire \builder_csrbank11_control1_re - attribute \src "ls180.v:2556.12-2556.40" - wire width 8 \builder_csrbank11_control1_w - attribute \src "ls180.v:2555.6-2555.35" - wire \builder_csrbank11_control1_we - attribute \src "ls180.v:2574.6-2574.29" - wire \builder_csrbank11_cs0_r - attribute \src "ls180.v:2573.6-2573.30" - wire \builder_csrbank11_cs0_re - attribute \src "ls180.v:2576.6-2576.29" - wire \builder_csrbank11_cs0_w - attribute \src "ls180.v:2575.6-2575.30" - wire \builder_csrbank11_cs0_we - attribute \src "ls180.v:2578.6-2578.35" - wire \builder_csrbank11_loopback0_r - attribute \src "ls180.v:2577.6-2577.36" - wire \builder_csrbank11_loopback0_re - attribute \src "ls180.v:2580.6-2580.35" - wire \builder_csrbank11_loopback0_w - attribute \src "ls180.v:2579.6-2579.36" - wire \builder_csrbank11_loopback0_we - attribute \src "ls180.v:2570.12-2570.36" - wire width 8 \builder_csrbank11_miso_r - attribute \src "ls180.v:2569.6-2569.31" - wire \builder_csrbank11_miso_re - attribute \src "ls180.v:2572.12-2572.36" - wire width 8 \builder_csrbank11_miso_w - attribute \src "ls180.v:2571.6-2571.31" - wire \builder_csrbank11_miso_we - attribute \src "ls180.v:2566.12-2566.37" - wire width 8 \builder_csrbank11_mosi0_r - attribute \src "ls180.v:2565.6-2565.32" - wire \builder_csrbank11_mosi0_re - attribute \src "ls180.v:2568.12-2568.37" - wire width 8 \builder_csrbank11_mosi0_w - attribute \src "ls180.v:2567.6-2567.32" - wire \builder_csrbank11_mosi0_we - attribute \src "ls180.v:2589.6-2589.27" - wire \builder_csrbank11_sel - attribute \src "ls180.v:2562.6-2562.32" - wire \builder_csrbank11_status_r - attribute \src "ls180.v:2561.6-2561.33" - wire \builder_csrbank11_status_re - attribute \src "ls180.v:2564.6-2564.32" - wire \builder_csrbank11_status_w - attribute \src "ls180.v:2563.6-2563.33" - wire \builder_csrbank11_status_we - attribute \src "ls180.v:2627.6-2627.29" - wire \builder_csrbank12_en0_r - attribute \src "ls180.v:2626.6-2626.30" - wire \builder_csrbank12_en0_re - attribute \src "ls180.v:2629.6-2629.29" - wire \builder_csrbank12_en0_w - attribute \src "ls180.v:2628.6-2628.30" - wire \builder_csrbank12_en0_we - attribute \src "ls180.v:2651.6-2651.36" - wire \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2650.6-2650.37" - wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2653.6-2653.36" - wire \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2652.6-2652.37" - wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2607.12-2607.37" - wire width 8 \builder_csrbank12_load0_r - attribute \src "ls180.v:2606.6-2606.32" - wire \builder_csrbank12_load0_re - attribute \src "ls180.v:2609.12-2609.37" - wire width 8 \builder_csrbank12_load0_w - attribute \src "ls180.v:2608.6-2608.32" - wire \builder_csrbank12_load0_we - attribute \src "ls180.v:2603.12-2603.37" - wire width 8 \builder_csrbank12_load1_r - attribute \src "ls180.v:2602.6-2602.32" - wire \builder_csrbank12_load1_re - attribute \src "ls180.v:2605.12-2605.37" - wire width 8 \builder_csrbank12_load1_w - attribute \src "ls180.v:2604.6-2604.32" - wire \builder_csrbank12_load1_we - attribute \src "ls180.v:2599.12-2599.37" - wire width 8 \builder_csrbank12_load2_r - attribute \src "ls180.v:2598.6-2598.32" - wire \builder_csrbank12_load2_re - attribute \src "ls180.v:2601.12-2601.37" - wire width 8 \builder_csrbank12_load2_w - attribute \src "ls180.v:2600.6-2600.32" - wire \builder_csrbank12_load2_we - attribute \src "ls180.v:2595.12-2595.37" - wire width 8 \builder_csrbank12_load3_r - attribute \src "ls180.v:2594.6-2594.32" - wire \builder_csrbank12_load3_re - attribute \src "ls180.v:2597.12-2597.37" - wire width 8 \builder_csrbank12_load3_w - attribute \src "ls180.v:2596.6-2596.32" - wire \builder_csrbank12_load3_we - attribute \src "ls180.v:2623.12-2623.39" - wire width 8 \builder_csrbank12_reload0_r - attribute \src "ls180.v:2622.6-2622.34" - wire \builder_csrbank12_reload0_re - attribute \src "ls180.v:2625.12-2625.39" - wire width 8 \builder_csrbank12_reload0_w - attribute \src "ls180.v:2624.6-2624.34" - wire \builder_csrbank12_reload0_we - attribute \src "ls180.v:2619.12-2619.39" - wire width 8 \builder_csrbank12_reload1_r - attribute \src "ls180.v:2618.6-2618.34" - wire \builder_csrbank12_reload1_re - attribute \src "ls180.v:2621.12-2621.39" - wire width 8 \builder_csrbank12_reload1_w - attribute \src "ls180.v:2620.6-2620.34" - wire \builder_csrbank12_reload1_we - attribute \src "ls180.v:2615.12-2615.39" - wire width 8 \builder_csrbank12_reload2_r - attribute \src "ls180.v:2614.6-2614.34" - wire \builder_csrbank12_reload2_re - attribute \src "ls180.v:2617.12-2617.39" - wire width 8 \builder_csrbank12_reload2_w - attribute \src "ls180.v:2616.6-2616.34" - wire \builder_csrbank12_reload2_we - attribute \src "ls180.v:2611.12-2611.39" - wire width 8 \builder_csrbank12_reload3_r - attribute \src "ls180.v:2610.6-2610.34" - wire \builder_csrbank12_reload3_re - attribute \src "ls180.v:2613.12-2613.39" - wire width 8 \builder_csrbank12_reload3_w - attribute \src "ls180.v:2612.6-2612.34" - wire \builder_csrbank12_reload3_we - attribute \src "ls180.v:2654.6-2654.27" - wire \builder_csrbank12_sel - attribute \src "ls180.v:2631.6-2631.39" - wire \builder_csrbank12_update_value0_r - attribute \src "ls180.v:2630.6-2630.40" - wire \builder_csrbank12_update_value0_re - attribute \src "ls180.v:2633.6-2633.39" - wire \builder_csrbank12_update_value0_w - attribute \src "ls180.v:2632.6-2632.40" - wire \builder_csrbank12_update_value0_we - attribute \src "ls180.v:2647.12-2647.38" - wire width 8 \builder_csrbank12_value0_r - attribute \src "ls180.v:2646.6-2646.33" - wire \builder_csrbank12_value0_re - attribute \src "ls180.v:2649.12-2649.38" - wire width 8 \builder_csrbank12_value0_w - attribute \src "ls180.v:2648.6-2648.33" - wire \builder_csrbank12_value0_we - attribute \src "ls180.v:2643.12-2643.38" - wire width 8 \builder_csrbank12_value1_r - attribute \src "ls180.v:2642.6-2642.33" - wire \builder_csrbank12_value1_re - attribute \src "ls180.v:2645.12-2645.38" - wire width 8 \builder_csrbank12_value1_w - attribute \src "ls180.v:2644.6-2644.33" - wire \builder_csrbank12_value1_we - attribute \src "ls180.v:2639.12-2639.38" - wire width 8 \builder_csrbank12_value2_r - attribute \src "ls180.v:2638.6-2638.33" - wire \builder_csrbank12_value2_re - attribute \src "ls180.v:2641.12-2641.38" - wire width 8 \builder_csrbank12_value2_w - attribute \src "ls180.v:2640.6-2640.33" - wire \builder_csrbank12_value2_we - attribute \src "ls180.v:2635.12-2635.38" - wire width 8 \builder_csrbank12_value3_r - attribute \src "ls180.v:2634.6-2634.33" - wire \builder_csrbank12_value3_re - attribute \src "ls180.v:2637.12-2637.38" - wire width 8 \builder_csrbank12_value3_w - attribute \src "ls180.v:2636.6-2636.33" - wire \builder_csrbank12_value3_we - attribute \src "ls180.v:2668.12-2668.42" - wire width 2 \builder_csrbank13_ev_enable0_r - attribute \src "ls180.v:2667.6-2667.37" - wire \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:2670.12-2670.42" - wire width 2 \builder_csrbank13_ev_enable0_w - attribute \src "ls180.v:2669.6-2669.37" - wire \builder_csrbank13_ev_enable0_we - attribute \src "ls180.v:2664.6-2664.33" - wire \builder_csrbank13_rxempty_r - attribute \src "ls180.v:2663.6-2663.34" - wire \builder_csrbank13_rxempty_re - attribute \src "ls180.v:2666.6-2666.33" - wire \builder_csrbank13_rxempty_w - attribute \src "ls180.v:2665.6-2665.34" - wire \builder_csrbank13_rxempty_we - attribute \src "ls180.v:2676.6-2676.32" - wire \builder_csrbank13_rxfull_r - attribute \src "ls180.v:2675.6-2675.33" - wire \builder_csrbank13_rxfull_re - attribute \src "ls180.v:2678.6-2678.32" - wire \builder_csrbank13_rxfull_w - attribute \src "ls180.v:2677.6-2677.33" - wire \builder_csrbank13_rxfull_we - attribute \src "ls180.v:2679.6-2679.27" - wire \builder_csrbank13_sel - attribute \src "ls180.v:2672.6-2672.33" - wire \builder_csrbank13_txempty_r - attribute \src "ls180.v:2671.6-2671.34" - wire \builder_csrbank13_txempty_re - attribute \src "ls180.v:2674.6-2674.33" - wire \builder_csrbank13_txempty_w - attribute \src "ls180.v:2673.6-2673.34" - wire \builder_csrbank13_txempty_we - attribute \src "ls180.v:2660.6-2660.32" - wire \builder_csrbank13_txfull_r - attribute \src "ls180.v:2659.6-2659.33" - wire \builder_csrbank13_txfull_re - attribute \src "ls180.v:2662.6-2662.32" - wire \builder_csrbank13_txfull_w - attribute \src "ls180.v:2661.6-2661.33" - wire \builder_csrbank13_txfull_we - attribute \src "ls180.v:2700.6-2700.27" - wire \builder_csrbank14_sel - attribute \src "ls180.v:2697.12-2697.44" - wire width 8 \builder_csrbank14_tuning_word0_r - attribute \src "ls180.v:2696.6-2696.39" - wire \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:2699.12-2699.44" - wire width 8 \builder_csrbank14_tuning_word0_w - attribute \src "ls180.v:2698.6-2698.39" - wire \builder_csrbank14_tuning_word0_we - attribute \src "ls180.v:2693.12-2693.44" - wire width 8 \builder_csrbank14_tuning_word1_r - attribute \src "ls180.v:2692.6-2692.39" - wire \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:2695.12-2695.44" - wire width 8 \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:2694.6-2694.39" - wire \builder_csrbank14_tuning_word1_we - attribute \src "ls180.v:2689.12-2689.44" - wire width 8 \builder_csrbank14_tuning_word2_r - attribute \src "ls180.v:2688.6-2688.39" - wire \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:2691.12-2691.44" - wire width 8 \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:2690.6-2690.39" - wire \builder_csrbank14_tuning_word2_we - attribute \src "ls180.v:2685.12-2685.44" - wire width 8 \builder_csrbank14_tuning_word3_r - attribute \src "ls180.v:2684.6-2684.39" - wire \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:2687.12-2687.44" - wire width 8 \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:2686.6-2686.39" - wire \builder_csrbank14_tuning_word3_we - attribute \src "ls180.v:2072.12-2072.34" - wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:2071.6-2071.29" - wire \builder_csrbank1_in0_re - attribute \src "ls180.v:2074.12-2074.34" - wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:2073.6-2073.29" - wire \builder_csrbank1_in0_we - attribute \src "ls180.v:2068.12-2068.34" - wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:2067.6-2067.29" - wire \builder_csrbank1_in1_re - attribute \src "ls180.v:2070.12-2070.34" - wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:2069.6-2069.29" - wire \builder_csrbank1_in1_we - attribute \src "ls180.v:2064.12-2064.34" - wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:2063.6-2063.29" - wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:2066.12-2066.34" - wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:2065.6-2065.29" - wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:2060.12-2060.34" - wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:2059.6-2059.29" - wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:2062.12-2062.34" - wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:2061.6-2061.29" - wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:2080.12-2080.35" - wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:2079.6-2079.30" - wire \builder_csrbank1_out0_re - attribute \src "ls180.v:2082.12-2082.35" - wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:2081.6-2081.30" - wire \builder_csrbank1_out0_we - attribute \src "ls180.v:2076.12-2076.35" - wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:2075.6-2075.30" - wire \builder_csrbank1_out1_re - attribute \src "ls180.v:2078.12-2078.35" - wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:2077.6-2077.30" - wire \builder_csrbank1_out1_we - attribute \src "ls180.v:2083.6-2083.26" - wire \builder_csrbank1_sel - attribute \src "ls180.v:2093.6-2093.26" - wire \builder_csrbank2_r_r - attribute \src "ls180.v:2092.6-2092.27" - wire \builder_csrbank2_r_re - attribute \src "ls180.v:2095.6-2095.26" - wire \builder_csrbank2_r_w - attribute \src "ls180.v:2094.6-2094.27" - wire \builder_csrbank2_r_we - attribute \src "ls180.v:2096.6-2096.26" - wire \builder_csrbank2_sel - attribute \src "ls180.v:2089.12-2089.33" - wire width 3 \builder_csrbank2_w0_r - attribute \src "ls180.v:2088.6-2088.28" - wire \builder_csrbank2_w0_re - attribute \src "ls180.v:2091.12-2091.33" - wire width 3 \builder_csrbank2_w0_w - attribute \src "ls180.v:2090.6-2090.28" - wire \builder_csrbank2_w0_we - attribute \src "ls180.v:2102.6-2102.32" - wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:2101.6-2101.33" - wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:2104.6-2104.32" - wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:2103.6-2103.33" - wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2134.12-2134.38" - wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2133.6-2133.33" - wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2136.12-2136.38" - wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2135.6-2135.33" - wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2130.12-2130.38" - wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2129.6-2129.33" - wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2132.12-2132.38" - wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2131.6-2131.33" - wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2126.12-2126.38" - wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2125.6-2125.33" - wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2128.12-2128.38" - wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2127.6-2127.33" - wire \builder_csrbank3_period2_we - attribute \src "ls180.v:2122.12-2122.38" - wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:2121.6-2121.33" - wire \builder_csrbank3_period3_re - attribute \src "ls180.v:2124.12-2124.38" - wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:2123.6-2123.33" - wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2137.6-2137.26" - wire \builder_csrbank3_sel - attribute \src "ls180.v:2118.12-2118.37" - wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:2117.6-2117.32" - wire \builder_csrbank3_width0_re - attribute \src "ls180.v:2120.12-2120.37" - wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:2119.6-2119.32" - wire \builder_csrbank3_width0_we - attribute \src "ls180.v:2114.12-2114.37" - wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:2113.6-2113.32" - wire \builder_csrbank3_width1_re - attribute \src "ls180.v:2116.12-2116.37" - wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:2115.6-2115.32" - wire \builder_csrbank3_width1_we - attribute \src "ls180.v:2110.12-2110.37" - wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:2109.6-2109.32" - wire \builder_csrbank3_width2_re - attribute \src "ls180.v:2112.12-2112.37" - wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:2111.6-2111.32" - wire \builder_csrbank3_width2_we - attribute \src "ls180.v:2106.12-2106.37" - wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:2105.6-2105.32" - wire \builder_csrbank3_width3_re - attribute \src "ls180.v:2108.12-2108.37" - wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:2107.6-2107.32" - wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2143.6-2143.32" - wire \builder_csrbank4_enable0_r - attribute \src "ls180.v:2142.6-2142.33" - wire \builder_csrbank4_enable0_re - attribute \src "ls180.v:2145.6-2145.32" - wire \builder_csrbank4_enable0_w - attribute \src "ls180.v:2144.6-2144.33" - wire \builder_csrbank4_enable0_we - attribute \src "ls180.v:2175.12-2175.38" - wire width 8 \builder_csrbank4_period0_r - attribute \src "ls180.v:2174.6-2174.33" - wire \builder_csrbank4_period0_re - attribute \src "ls180.v:2177.12-2177.38" - wire width 8 \builder_csrbank4_period0_w - attribute \src "ls180.v:2176.6-2176.33" - wire \builder_csrbank4_period0_we - attribute \src "ls180.v:2171.12-2171.38" - wire width 8 \builder_csrbank4_period1_r - attribute \src "ls180.v:2170.6-2170.33" - wire \builder_csrbank4_period1_re - attribute \src "ls180.v:2173.12-2173.38" - wire width 8 \builder_csrbank4_period1_w - attribute \src "ls180.v:2172.6-2172.33" - wire \builder_csrbank4_period1_we - attribute \src "ls180.v:2167.12-2167.38" - wire width 8 \builder_csrbank4_period2_r - attribute \src "ls180.v:2166.6-2166.33" - wire \builder_csrbank4_period2_re - attribute \src "ls180.v:2169.12-2169.38" - wire width 8 \builder_csrbank4_period2_w - attribute \src "ls180.v:2168.6-2168.33" - wire \builder_csrbank4_period2_we - attribute \src "ls180.v:2163.12-2163.38" - wire width 8 \builder_csrbank4_period3_r - attribute \src "ls180.v:2162.6-2162.33" - wire \builder_csrbank4_period3_re - attribute \src "ls180.v:2165.12-2165.38" - wire width 8 \builder_csrbank4_period3_w - attribute \src "ls180.v:2164.6-2164.33" - wire \builder_csrbank4_period3_we - attribute \src "ls180.v:2178.6-2178.26" - wire \builder_csrbank4_sel - attribute \src "ls180.v:2159.12-2159.37" - wire width 8 \builder_csrbank4_width0_r - attribute \src "ls180.v:2158.6-2158.32" - wire \builder_csrbank4_width0_re - attribute \src "ls180.v:2161.12-2161.37" - wire width 8 \builder_csrbank4_width0_w - attribute \src "ls180.v:2160.6-2160.32" - wire \builder_csrbank4_width0_we - attribute \src "ls180.v:2155.12-2155.37" - wire width 8 \builder_csrbank4_width1_r - attribute \src "ls180.v:2154.6-2154.32" - wire \builder_csrbank4_width1_re - attribute \src "ls180.v:2157.12-2157.37" - wire width 8 \builder_csrbank4_width1_w - attribute \src "ls180.v:2156.6-2156.32" - wire \builder_csrbank4_width1_we - attribute \src "ls180.v:2151.12-2151.37" - wire width 8 \builder_csrbank4_width2_r - attribute \src "ls180.v:2150.6-2150.32" - wire \builder_csrbank4_width2_re - attribute \src "ls180.v:2153.12-2153.37" - wire width 8 \builder_csrbank4_width2_w - attribute \src "ls180.v:2152.6-2152.32" - wire \builder_csrbank4_width2_we - attribute \src "ls180.v:2147.12-2147.37" - wire width 8 \builder_csrbank4_width3_r - attribute \src "ls180.v:2146.6-2146.32" - wire \builder_csrbank4_width3_re - attribute \src "ls180.v:2149.12-2149.37" - wire width 8 \builder_csrbank4_width3_w - attribute \src "ls180.v:2148.6-2148.32" - wire \builder_csrbank4_width3_we - attribute \src "ls180.v:2212.12-2212.40" - wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2211.6-2211.35" - wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2214.12-2214.40" - wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2213.6-2213.35" - wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2208.12-2208.40" - wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2207.6-2207.35" - wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2210.12-2210.40" - wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2209.6-2209.35" - wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2204.12-2204.40" - wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2203.6-2203.35" - wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2206.12-2206.40" - wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2205.6-2205.35" - wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2200.12-2200.40" - wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2199.6-2199.35" - wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2202.12-2202.40" - wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2201.6-2201.35" - wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2196.12-2196.40" - wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2195.6-2195.35" - wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2198.12-2198.40" - wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2197.6-2197.35" - wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2192.12-2192.40" - wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2191.6-2191.35" - wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2194.12-2194.40" - wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2193.6-2193.35" - wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2188.12-2188.40" - wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2187.6-2187.35" - wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2190.12-2190.40" - wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2189.6-2189.35" - wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2184.12-2184.40" - wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2183.6-2183.35" - wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2186.12-2186.40" - wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2185.6-2185.35" - wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2236.6-2236.33" - wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2235.6-2235.34" - wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2238.6-2238.33" - wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2237.6-2237.34" - wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2232.6-2232.36" - wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2231.6-2231.37" - wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2234.6-2234.36" - wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2233.6-2233.37" - wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2228.12-2228.42" - wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2227.6-2227.37" - wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2230.12-2230.42" - wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2229.6-2229.37" - wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2224.12-2224.42" - wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2223.6-2223.37" - wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2226.12-2226.42" - wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2225.6-2225.37" - wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2220.12-2220.42" - wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2219.6-2219.37" - wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2222.12-2222.42" - wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2221.6-2221.37" - wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2216.12-2216.42" - wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2215.6-2215.37" - wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2218.12-2218.42" - wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2217.6-2217.37" - wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2240.6-2240.34" - wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2239.6-2239.35" - wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2242.6-2242.34" - wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2241.6-2241.35" - wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2243.6-2243.26" - wire \builder_csrbank5_sel - attribute \src "ls180.v:2373.12-2373.43" - wire width 8 \builder_csrbank6_block_count0_r - attribute \src "ls180.v:2372.6-2372.38" - wire \builder_csrbank6_block_count0_re - attribute \src "ls180.v:2375.12-2375.43" - wire width 8 \builder_csrbank6_block_count0_w - attribute \src "ls180.v:2374.6-2374.38" - wire \builder_csrbank6_block_count0_we - attribute \src "ls180.v:2369.12-2369.43" - wire width 8 \builder_csrbank6_block_count1_r - attribute \src "ls180.v:2368.6-2368.38" - wire \builder_csrbank6_block_count1_re - attribute \src "ls180.v:2371.12-2371.43" - wire width 8 \builder_csrbank6_block_count1_w - attribute \src "ls180.v:2370.6-2370.38" - wire \builder_csrbank6_block_count1_we - attribute \src "ls180.v:2365.12-2365.43" - wire width 8 \builder_csrbank6_block_count2_r - attribute \src "ls180.v:2364.6-2364.38" - wire \builder_csrbank6_block_count2_re - attribute \src "ls180.v:2367.12-2367.43" - wire width 8 \builder_csrbank6_block_count2_w - attribute \src "ls180.v:2366.6-2366.38" - wire \builder_csrbank6_block_count2_we - attribute \src "ls180.v:2361.12-2361.43" - wire width 8 \builder_csrbank6_block_count3_r - attribute \src "ls180.v:2360.6-2360.38" - wire \builder_csrbank6_block_count3_re - attribute \src "ls180.v:2363.12-2363.43" - wire width 8 \builder_csrbank6_block_count3_w - attribute \src "ls180.v:2362.6-2362.38" - wire \builder_csrbank6_block_count3_we - attribute \src "ls180.v:2357.12-2357.44" - wire width 8 \builder_csrbank6_block_length0_r - attribute \src "ls180.v:2356.6-2356.39" - wire \builder_csrbank6_block_length0_re - attribute \src "ls180.v:2359.12-2359.44" - wire width 8 \builder_csrbank6_block_length0_w - attribute \src "ls180.v:2358.6-2358.39" - wire \builder_csrbank6_block_length0_we - attribute \src "ls180.v:2353.12-2353.44" - wire width 2 \builder_csrbank6_block_length1_r - attribute \src "ls180.v:2352.6-2352.39" - wire \builder_csrbank6_block_length1_re - attribute \src "ls180.v:2355.12-2355.44" - wire width 2 \builder_csrbank6_block_length1_w - attribute \src "ls180.v:2354.6-2354.39" - wire \builder_csrbank6_block_length1_we - attribute \src "ls180.v:2261.12-2261.44" - wire width 8 \builder_csrbank6_cmd_argument0_r - attribute \src "ls180.v:2260.6-2260.39" - wire \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:2263.12-2263.44" - wire width 8 \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:2262.6-2262.39" - wire \builder_csrbank6_cmd_argument0_we - attribute \src "ls180.v:2257.12-2257.44" - wire width 8 \builder_csrbank6_cmd_argument1_r - attribute \src "ls180.v:2256.6-2256.39" - wire \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:2259.12-2259.44" - wire width 8 \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:2258.6-2258.39" - wire \builder_csrbank6_cmd_argument1_we - attribute \src "ls180.v:2253.12-2253.44" - wire width 8 \builder_csrbank6_cmd_argument2_r - attribute \src "ls180.v:2252.6-2252.39" - wire \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:2255.12-2255.44" - wire width 8 \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:2254.6-2254.39" - wire \builder_csrbank6_cmd_argument2_we - attribute \src "ls180.v:2249.12-2249.44" - wire width 8 \builder_csrbank6_cmd_argument3_r - attribute \src "ls180.v:2248.6-2248.39" - wire \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:2251.12-2251.44" - wire width 8 \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:2250.6-2250.39" - wire \builder_csrbank6_cmd_argument3_we - attribute \src "ls180.v:2277.12-2277.43" - wire width 8 \builder_csrbank6_cmd_command0_r - attribute \src "ls180.v:2276.6-2276.38" - wire \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:2279.12-2279.43" - wire width 8 \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:2278.6-2278.38" - wire \builder_csrbank6_cmd_command0_we - attribute \src "ls180.v:2273.12-2273.43" - wire width 8 \builder_csrbank6_cmd_command1_r - attribute \src "ls180.v:2272.6-2272.38" - wire \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:2275.12-2275.43" - wire width 8 \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:2274.6-2274.38" - wire \builder_csrbank6_cmd_command1_we - attribute \src "ls180.v:2269.12-2269.43" - wire width 8 \builder_csrbank6_cmd_command2_r - attribute \src "ls180.v:2268.6-2268.38" - wire \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:2271.12-2271.43" - wire width 8 \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:2270.6-2270.38" - wire \builder_csrbank6_cmd_command2_we - attribute \src "ls180.v:2265.12-2265.43" - wire width 8 \builder_csrbank6_cmd_command3_r - attribute \src "ls180.v:2264.6-2264.38" - wire \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:2267.12-2267.43" - wire width 8 \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:2266.6-2266.38" - wire \builder_csrbank6_cmd_command3_we - attribute \src "ls180.v:2345.12-2345.40" - wire width 4 \builder_csrbank6_cmd_event_r - attribute \src "ls180.v:2344.6-2344.35" - wire \builder_csrbank6_cmd_event_re - attribute \src "ls180.v:2347.12-2347.40" - wire width 4 \builder_csrbank6_cmd_event_w - attribute \src "ls180.v:2346.6-2346.35" - wire \builder_csrbank6_cmd_event_we - attribute \src "ls180.v:2341.12-2341.44" - wire width 8 \builder_csrbank6_cmd_response0_r - attribute \src "ls180.v:2340.6-2340.39" - wire \builder_csrbank6_cmd_response0_re - attribute \src "ls180.v:2343.12-2343.44" - wire width 8 \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:2342.6-2342.39" - wire \builder_csrbank6_cmd_response0_we - attribute \src "ls180.v:2301.12-2301.45" - wire width 8 \builder_csrbank6_cmd_response10_r - attribute \src "ls180.v:2300.6-2300.40" - wire \builder_csrbank6_cmd_response10_re - attribute \src "ls180.v:2303.12-2303.45" - wire width 8 \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:2302.6-2302.40" - wire \builder_csrbank6_cmd_response10_we - attribute \src "ls180.v:2297.12-2297.45" - wire width 8 \builder_csrbank6_cmd_response11_r - attribute \src "ls180.v:2296.6-2296.40" - wire \builder_csrbank6_cmd_response11_re - attribute \src "ls180.v:2299.12-2299.45" - wire width 8 \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:2298.6-2298.40" - wire \builder_csrbank6_cmd_response11_we - attribute \src "ls180.v:2293.12-2293.45" - wire width 8 \builder_csrbank6_cmd_response12_r - attribute \src "ls180.v:2292.6-2292.40" - wire \builder_csrbank6_cmd_response12_re - attribute \src "ls180.v:2295.12-2295.45" - wire width 8 \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:2294.6-2294.40" - wire \builder_csrbank6_cmd_response12_we - attribute \src "ls180.v:2289.12-2289.45" - wire width 8 \builder_csrbank6_cmd_response13_r - attribute \src "ls180.v:2288.6-2288.40" - wire \builder_csrbank6_cmd_response13_re - attribute \src "ls180.v:2291.12-2291.45" - wire width 8 \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:2290.6-2290.40" - wire \builder_csrbank6_cmd_response13_we - attribute \src "ls180.v:2285.12-2285.45" - wire width 8 \builder_csrbank6_cmd_response14_r - attribute \src "ls180.v:2284.6-2284.40" - wire \builder_csrbank6_cmd_response14_re - attribute \src "ls180.v:2287.12-2287.45" - wire width 8 \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:2286.6-2286.40" - wire \builder_csrbank6_cmd_response14_we - attribute \src "ls180.v:2281.12-2281.45" - wire width 8 \builder_csrbank6_cmd_response15_r - attribute \src "ls180.v:2280.6-2280.40" - wire \builder_csrbank6_cmd_response15_re - attribute \src "ls180.v:2283.12-2283.45" - wire width 8 \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:2282.6-2282.40" - wire \builder_csrbank6_cmd_response15_we - attribute \src "ls180.v:2337.12-2337.44" - wire width 8 \builder_csrbank6_cmd_response1_r - attribute \src "ls180.v:2336.6-2336.39" - wire \builder_csrbank6_cmd_response1_re - attribute \src "ls180.v:2339.12-2339.44" - wire width 8 \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:2338.6-2338.39" - wire \builder_csrbank6_cmd_response1_we - attribute \src "ls180.v:2333.12-2333.44" - wire width 8 \builder_csrbank6_cmd_response2_r - attribute \src "ls180.v:2332.6-2332.39" - wire \builder_csrbank6_cmd_response2_re - attribute \src "ls180.v:2335.12-2335.44" - wire width 8 \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:2334.6-2334.39" - wire \builder_csrbank6_cmd_response2_we - attribute \src "ls180.v:2329.12-2329.44" - wire width 8 \builder_csrbank6_cmd_response3_r - attribute \src "ls180.v:2328.6-2328.39" - wire \builder_csrbank6_cmd_response3_re - attribute \src "ls180.v:2331.12-2331.44" - wire width 8 \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:2330.6-2330.39" - wire \builder_csrbank6_cmd_response3_we - attribute \src "ls180.v:2325.12-2325.44" - wire width 8 \builder_csrbank6_cmd_response4_r - attribute \src "ls180.v:2324.6-2324.39" - wire \builder_csrbank6_cmd_response4_re - attribute \src "ls180.v:2327.12-2327.44" - wire width 8 \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:2326.6-2326.39" - wire \builder_csrbank6_cmd_response4_we - attribute \src "ls180.v:2321.12-2321.44" - wire width 8 \builder_csrbank6_cmd_response5_r - attribute \src "ls180.v:2320.6-2320.39" - wire \builder_csrbank6_cmd_response5_re - attribute \src "ls180.v:2323.12-2323.44" - wire width 8 \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:2322.6-2322.39" - wire \builder_csrbank6_cmd_response5_we - attribute \src "ls180.v:2317.12-2317.44" - wire width 8 \builder_csrbank6_cmd_response6_r - attribute \src "ls180.v:2316.6-2316.39" - wire \builder_csrbank6_cmd_response6_re - attribute \src "ls180.v:2319.12-2319.44" - wire width 8 \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:2318.6-2318.39" - wire \builder_csrbank6_cmd_response6_we - attribute \src "ls180.v:2313.12-2313.44" - wire width 8 \builder_csrbank6_cmd_response7_r - attribute \src "ls180.v:2312.6-2312.39" - wire \builder_csrbank6_cmd_response7_re - attribute \src "ls180.v:2315.12-2315.44" - wire width 8 \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:2314.6-2314.39" - wire \builder_csrbank6_cmd_response7_we - attribute \src "ls180.v:2309.12-2309.44" - wire width 8 \builder_csrbank6_cmd_response8_r - attribute \src "ls180.v:2308.6-2308.39" - wire \builder_csrbank6_cmd_response8_re - attribute \src "ls180.v:2311.12-2311.44" - wire width 8 \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:2310.6-2310.39" - wire \builder_csrbank6_cmd_response8_we - attribute \src "ls180.v:2305.12-2305.44" - wire width 8 \builder_csrbank6_cmd_response9_r - attribute \src "ls180.v:2304.6-2304.39" - wire \builder_csrbank6_cmd_response9_re - attribute \src "ls180.v:2307.12-2307.44" - wire width 8 \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:2306.6-2306.39" - wire \builder_csrbank6_cmd_response9_we - attribute \src "ls180.v:2349.12-2349.41" - wire width 4 \builder_csrbank6_data_event_r - attribute \src "ls180.v:2348.6-2348.36" - wire \builder_csrbank6_data_event_re - attribute \src "ls180.v:2351.12-2351.41" - wire width 4 \builder_csrbank6_data_event_w - attribute \src "ls180.v:2350.6-2350.36" - wire \builder_csrbank6_data_event_we - attribute \src "ls180.v:2376.6-2376.26" - wire \builder_csrbank6_sel - attribute \src "ls180.v:2410.12-2410.40" - wire width 8 \builder_csrbank7_dma_base0_r - attribute \src "ls180.v:2409.6-2409.35" - wire \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:2412.12-2412.40" - wire width 8 \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:2411.6-2411.35" - wire \builder_csrbank7_dma_base0_we - attribute \src "ls180.v:2406.12-2406.40" - wire width 8 \builder_csrbank7_dma_base1_r - attribute \src "ls180.v:2405.6-2405.35" - wire \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:2408.12-2408.40" - wire width 8 \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:2407.6-2407.35" - wire \builder_csrbank7_dma_base1_we - attribute \src "ls180.v:2402.12-2402.40" - wire width 8 \builder_csrbank7_dma_base2_r - attribute \src "ls180.v:2401.6-2401.35" - wire \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:2404.12-2404.40" - wire width 8 \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:2403.6-2403.35" - wire \builder_csrbank7_dma_base2_we - attribute \src "ls180.v:2398.12-2398.40" - wire width 8 \builder_csrbank7_dma_base3_r - attribute \src "ls180.v:2397.6-2397.35" - wire \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:2400.12-2400.40" - wire width 8 \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:2399.6-2399.35" - wire \builder_csrbank7_dma_base3_we - attribute \src "ls180.v:2394.12-2394.40" - wire width 8 \builder_csrbank7_dma_base4_r - attribute \src "ls180.v:2393.6-2393.35" - wire \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:2396.12-2396.40" - wire width 8 \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:2395.6-2395.35" - wire \builder_csrbank7_dma_base4_we - attribute \src "ls180.v:2390.12-2390.40" - wire width 8 \builder_csrbank7_dma_base5_r - attribute \src "ls180.v:2389.6-2389.35" - wire \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:2392.12-2392.40" - wire width 8 \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:2391.6-2391.35" - wire \builder_csrbank7_dma_base5_we - attribute \src "ls180.v:2386.12-2386.40" - wire width 8 \builder_csrbank7_dma_base6_r - attribute \src "ls180.v:2385.6-2385.35" - wire \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:2388.12-2388.40" - wire width 8 \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:2387.6-2387.35" - wire \builder_csrbank7_dma_base6_we - attribute \src "ls180.v:2382.12-2382.40" - wire width 8 \builder_csrbank7_dma_base7_r - attribute \src "ls180.v:2381.6-2381.35" - wire \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:2384.12-2384.40" - wire width 8 \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:2383.6-2383.35" - wire \builder_csrbank7_dma_base7_we - attribute \src "ls180.v:2434.6-2434.33" - wire \builder_csrbank7_dma_done_r - attribute \src "ls180.v:2433.6-2433.34" - wire \builder_csrbank7_dma_done_re - attribute \src "ls180.v:2436.6-2436.33" - wire \builder_csrbank7_dma_done_w - attribute \src "ls180.v:2435.6-2435.34" - wire \builder_csrbank7_dma_done_we - attribute \src "ls180.v:2430.6-2430.36" - wire \builder_csrbank7_dma_enable0_r - attribute \src "ls180.v:2429.6-2429.37" - wire \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:2432.6-2432.36" - wire \builder_csrbank7_dma_enable0_w - attribute \src "ls180.v:2431.6-2431.37" - wire \builder_csrbank7_dma_enable0_we - attribute \src "ls180.v:2426.12-2426.42" - wire width 8 \builder_csrbank7_dma_length0_r - attribute \src "ls180.v:2425.6-2425.37" - wire \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:2428.12-2428.42" - wire width 8 \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:2427.6-2427.37" - wire \builder_csrbank7_dma_length0_we - attribute \src "ls180.v:2422.12-2422.42" - wire width 8 \builder_csrbank7_dma_length1_r - attribute \src "ls180.v:2421.6-2421.37" - wire \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:2424.12-2424.42" - wire width 8 \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:2423.6-2423.37" - wire \builder_csrbank7_dma_length1_we - attribute \src "ls180.v:2418.12-2418.42" - wire width 8 \builder_csrbank7_dma_length2_r - attribute \src "ls180.v:2417.6-2417.37" - wire \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:2420.12-2420.42" - wire width 8 \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:2419.6-2419.37" - wire \builder_csrbank7_dma_length2_we - attribute \src "ls180.v:2414.12-2414.42" - wire width 8 \builder_csrbank7_dma_length3_r - attribute \src "ls180.v:2413.6-2413.37" - wire \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:2416.12-2416.42" - wire width 8 \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:2415.6-2415.37" - wire \builder_csrbank7_dma_length3_we - attribute \src "ls180.v:2438.6-2438.34" - wire \builder_csrbank7_dma_loop0_r - attribute \src "ls180.v:2437.6-2437.35" - wire \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:2440.6-2440.34" - wire \builder_csrbank7_dma_loop0_w - attribute \src "ls180.v:2439.6-2439.35" - wire \builder_csrbank7_dma_loop0_we - attribute \src "ls180.v:2454.12-2454.42" - wire width 8 \builder_csrbank7_dma_offset0_r - attribute \src "ls180.v:2453.6-2453.37" - wire \builder_csrbank7_dma_offset0_re - attribute \src "ls180.v:2456.12-2456.42" - wire width 8 \builder_csrbank7_dma_offset0_w - attribute \src "ls180.v:2455.6-2455.37" - wire \builder_csrbank7_dma_offset0_we - attribute \src "ls180.v:2450.12-2450.42" - wire width 8 \builder_csrbank7_dma_offset1_r - attribute \src "ls180.v:2449.6-2449.37" - wire \builder_csrbank7_dma_offset1_re - attribute \src "ls180.v:2452.12-2452.42" - wire width 8 \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:2451.6-2451.37" - wire \builder_csrbank7_dma_offset1_we - attribute \src "ls180.v:2446.12-2446.42" - wire width 8 \builder_csrbank7_dma_offset2_r - attribute \src "ls180.v:2445.6-2445.37" - wire \builder_csrbank7_dma_offset2_re - attribute \src "ls180.v:2448.12-2448.42" - wire width 8 \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:2447.6-2447.37" - wire \builder_csrbank7_dma_offset2_we - attribute \src "ls180.v:2442.12-2442.42" - wire width 8 \builder_csrbank7_dma_offset3_r - attribute \src "ls180.v:2441.6-2441.37" - wire \builder_csrbank7_dma_offset3_re - attribute \src "ls180.v:2444.12-2444.42" - wire width 8 \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:2443.6-2443.37" - wire \builder_csrbank7_dma_offset3_we - attribute \src "ls180.v:2457.6-2457.26" - wire \builder_csrbank7_sel - attribute \src "ls180.v:2463.6-2463.36" - wire \builder_csrbank8_card_detect_r - attribute \src "ls180.v:2462.6-2462.37" - wire \builder_csrbank8_card_detect_re - attribute \src "ls180.v:2465.6-2465.36" - wire \builder_csrbank8_card_detect_w - attribute \src "ls180.v:2464.6-2464.37" - wire \builder_csrbank8_card_detect_we - attribute \src "ls180.v:2471.12-2471.47" - wire width 8 \builder_csrbank8_clocker_divider0_r - attribute \src "ls180.v:2470.6-2470.42" - wire \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:2473.12-2473.47" - wire width 8 \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:2472.6-2472.42" - wire \builder_csrbank8_clocker_divider0_we - attribute \src "ls180.v:2467.6-2467.41" - wire \builder_csrbank8_clocker_divider1_r - attribute \src "ls180.v:2466.6-2466.42" - wire \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:2469.6-2469.41" - wire \builder_csrbank8_clocker_divider1_w - attribute \src "ls180.v:2468.6-2468.42" - wire \builder_csrbank8_clocker_divider1_we - attribute \src "ls180.v:2474.6-2474.26" - wire \builder_csrbank8_sel - attribute \src "ls180.v:2480.12-2480.44" - wire width 4 \builder_csrbank9_dfii_control0_r - attribute \src "ls180.v:2479.6-2479.39" - wire \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:2482.12-2482.44" - wire width 4 \builder_csrbank9_dfii_control0_w - attribute \src "ls180.v:2481.6-2481.39" - wire \builder_csrbank9_dfii_control0_we - attribute \src "ls180.v:2492.12-2492.48" - wire width 8 \builder_csrbank9_dfii_pi0_address0_r - attribute \src "ls180.v:2491.6-2491.43" - wire \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:2494.12-2494.48" - wire width 8 \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:2493.6-2493.43" - wire \builder_csrbank9_dfii_pi0_address0_we - attribute \src "ls180.v:2488.12-2488.48" - wire width 5 \builder_csrbank9_dfii_pi0_address1_r - attribute \src "ls180.v:2487.6-2487.43" - wire \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:2490.12-2490.48" - wire width 5 \builder_csrbank9_dfii_pi0_address1_w - attribute \src "ls180.v:2489.6-2489.43" - wire \builder_csrbank9_dfii_pi0_address1_we - attribute \src "ls180.v:2496.12-2496.49" - wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r - attribute \src "ls180.v:2495.6-2495.44" - wire \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:2498.12-2498.49" - wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w - attribute \src "ls180.v:2497.6-2497.44" - wire \builder_csrbank9_dfii_pi0_baddress0_we - attribute \src "ls180.v:2484.12-2484.48" - wire width 6 \builder_csrbank9_dfii_pi0_command0_r - attribute \src "ls180.v:2483.6-2483.43" - wire \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:2486.12-2486.48" - wire width 6 \builder_csrbank9_dfii_pi0_command0_w - attribute \src "ls180.v:2485.6-2485.43" - wire \builder_csrbank9_dfii_pi0_command0_we - attribute \src "ls180.v:2512.12-2512.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r - attribute \src "ls180.v:2511.6-2511.42" - wire \builder_csrbank9_dfii_pi0_rddata0_re - attribute \src "ls180.v:2514.12-2514.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w - attribute \src "ls180.v:2513.6-2513.42" - wire \builder_csrbank9_dfii_pi0_rddata0_we - attribute \src "ls180.v:2508.12-2508.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r - attribute \src "ls180.v:2507.6-2507.42" - wire \builder_csrbank9_dfii_pi0_rddata1_re - attribute \src "ls180.v:2510.12-2510.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:2509.6-2509.42" - wire \builder_csrbank9_dfii_pi0_rddata1_we - attribute \src "ls180.v:2504.12-2504.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2503.6-2503.42" - wire \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2506.12-2506.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2505.6-2505.42" - wire \builder_csrbank9_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2500.12-2500.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2499.6-2499.42" - wire \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2502.12-2502.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2501.6-2501.42" - wire \builder_csrbank9_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2515.6-2515.26" - wire \builder_csrbank9_sel - attribute \src "ls180.v:2012.6-2012.18" - wire \builder_done - attribute \src "ls180.v:2010.5-2010.18" - wire \builder_error - attribute \src "ls180.v:2007.11-2007.24" - wire width 3 \builder_grant - attribute \src "ls180.v:2014.13-2014.44" - wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:2017.11-2017.44" - wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:2016.12-2016.45" - wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:2015.6-2015.36" - wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2516.13-2516.45" - wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2519.11-2519.45" - wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2518.12-2518.46" - wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2517.6-2517.37" - wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2549.13-2549.45" - wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2552.11-2552.45" - wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2551.12-2551.46" - wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2550.6-2550.37" - wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2590.13-2590.45" - wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2593.11-2593.45" - wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2592.12-2592.46" - wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2591.6-2591.37" - wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2655.13-2655.45" - wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2658.11-2658.45" - wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2657.12-2657.46" - wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2656.6-2656.37" - wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:2680.13-2680.45" - wire width 14 \builder_interface14_bank_bus_adr - attribute \src "ls180.v:2683.11-2683.45" - wire width 8 \builder_interface14_bank_bus_dat_r - attribute \src "ls180.v:2682.12-2682.46" - wire width 8 \builder_interface14_bank_bus_dat_w - attribute \src "ls180.v:2681.6-2681.37" - wire \builder_interface14_bank_bus_we - attribute \src "ls180.v:2055.13-2055.44" - wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:2058.11-2058.44" - wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:2057.12-2057.45" - wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:2056.6-2056.36" - wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:2084.13-2084.44" - wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:2087.11-2087.44" - wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:2086.12-2086.45" - wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:2085.6-2085.36" - wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:2097.13-2097.44" - wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:2100.11-2100.44" - wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:2099.12-2099.45" - wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:2098.6-2098.36" - wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2138.13-2138.44" - wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2141.11-2141.44" - wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2140.12-2140.45" - wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2139.6-2139.36" - wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2179.13-2179.44" - wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2182.11-2182.44" - wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2181.12-2181.45" - wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2180.6-2180.36" - wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2244.13-2244.44" - wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2247.11-2247.44" - wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2246.12-2246.45" - wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2245.6-2245.36" - wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2377.13-2377.44" - wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2380.11-2380.44" - wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2379.12-2379.45" - wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2378.6-2378.36" - wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2458.13-2458.44" - wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2461.11-2461.44" - wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2460.12-2460.45" - wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2459.6-2459.36" - wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2475.13-2475.44" - wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2478.11-2478.44" - wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2477.12-2477.45" - wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2476.6-2476.36" - wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1972.12-1972.35" - wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2709.12-2709.47" - wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2710.5-2710.43" - wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1990.5-1990.48" - wire \builder_libresocsim_converted_interface_ack - attribute \src "ls180.v:1984.13-1984.56" - wire width 30 \builder_libresocsim_converted_interface_adr - attribute \src "ls180.v:1993.12-1993.55" - wire width 2 \builder_libresocsim_converted_interface_bte - attribute \src "ls180.v:1992.12-1992.55" - wire width 3 \builder_libresocsim_converted_interface_cti - attribute \src "ls180.v:1988.6-1988.49" - wire \builder_libresocsim_converted_interface_cyc - attribute \src "ls180.v:1986.12-1986.57" - wire width 64 \builder_libresocsim_converted_interface_dat_r - attribute \src "ls180.v:1985.13-1985.58" - wire width 64 \builder_libresocsim_converted_interface_dat_w - attribute \src "ls180.v:1994.5-1994.48" - wire \builder_libresocsim_converted_interface_err - attribute \src "ls180.v:1987.12-1987.55" - wire width 8 \builder_libresocsim_converted_interface_sel - attribute \src "ls180.v:1989.6-1989.49" - wire \builder_libresocsim_converted_interface_stb - attribute \src "ls180.v:1991.6-1991.48" - wire \builder_libresocsim_converted_interface_we - attribute \src "ls180.v:1975.12-1975.37" - wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1974.11-1974.36" - wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2707.11-2707.48" - wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2708.5-2708.45" - wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1973.5-1973.27" - wire \builder_libresocsim_we - attribute \src "ls180.v:2711.5-2711.39" - wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2712.5-2712.42" - wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1982.5-1982.37" - wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1976.12-1976.44" - wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1980.5-1980.37" - wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1978.12-1978.46" - wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1977.12-1977.46" - wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1979.11-1979.43" - wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1981.5-1981.37" - wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1983.5-1983.36" - wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1875.5-1875.20" - wire \builder_locked0 - attribute \src "ls180.v:1876.5-1876.20" - wire \builder_locked1 - attribute \src "ls180.v:1877.5-1877.20" - wire \builder_locked2 - attribute \src "ls180.v:1878.5-1878.20" - wire \builder_locked3 - attribute \src "ls180.v:1862.11-1862.41" - wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1861.11-1861.36" - wire width 3 \builder_multiplexer_state - attribute \no_retiming "true" - attribute \src "ls180.v:2816.32-2816.59" - wire \builder_multiregimpl0_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2817.32-2817.59" - wire \builder_multiregimpl0_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2836.32-2836.60" - wire \builder_multiregimpl10_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2837.32-2837.60" - wire \builder_multiregimpl10_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2838.32-2838.60" - wire \builder_multiregimpl11_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2839.32-2839.60" - wire \builder_multiregimpl11_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2840.32-2840.60" - wire \builder_multiregimpl12_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2841.32-2841.60" - wire \builder_multiregimpl12_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2842.32-2842.60" - wire \builder_multiregimpl13_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2843.32-2843.60" - wire \builder_multiregimpl13_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2844.32-2844.60" - wire \builder_multiregimpl14_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2845.32-2845.60" - wire \builder_multiregimpl14_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2846.32-2846.60" - wire \builder_multiregimpl15_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2847.32-2847.60" - wire \builder_multiregimpl15_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2848.32-2848.60" - wire \builder_multiregimpl16_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2849.32-2849.60" - wire \builder_multiregimpl16_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2818.32-2818.59" - wire \builder_multiregimpl1_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2819.32-2819.59" - wire \builder_multiregimpl1_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2820.32-2820.59" - wire \builder_multiregimpl2_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2821.32-2821.59" - wire \builder_multiregimpl2_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2822.32-2822.59" - wire \builder_multiregimpl3_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2823.32-2823.59" - wire \builder_multiregimpl3_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2824.32-2824.59" - wire \builder_multiregimpl4_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2825.32-2825.59" - wire \builder_multiregimpl4_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2826.32-2826.59" - wire \builder_multiregimpl5_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2827.32-2827.59" - wire \builder_multiregimpl5_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2828.32-2828.59" - wire \builder_multiregimpl6_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2829.32-2829.59" - wire \builder_multiregimpl6_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2830.32-2830.59" - wire \builder_multiregimpl7_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2831.32-2831.59" - wire \builder_multiregimpl7_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2832.32-2832.59" - wire \builder_multiregimpl8_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2833.32-2833.59" - wire \builder_multiregimpl8_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2834.32-2834.59" - wire \builder_multiregimpl9_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2835.32-2835.59" - wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1880.5-1880.36" - wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1881.5-1881.36" - wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1882.5-1882.36" - wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1883.5-1883.36" - wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1879.5-1879.35" - wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2706.11-2706.29" - wire width 2 \builder_next_state - attribute \src "ls180.v:1852.11-1852.39" - wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1851.11-1851.34" - wire width 2 \builder_refresher_state - attribute \src "ls180.v:2006.12-2006.27" - wire width 5 \builder_request - attribute \src "ls180.v:1865.6-1865.28" - wire \builder_roundrobin0_ce - attribute \src "ls180.v:1864.6-1864.31" - wire \builder_roundrobin0_grant - attribute \src "ls180.v:1863.6-1863.33" - wire \builder_roundrobin0_request - attribute \src "ls180.v:1868.6-1868.28" - wire \builder_roundrobin1_ce - attribute \src "ls180.v:1867.6-1867.31" - wire \builder_roundrobin1_grant - attribute \src "ls180.v:1866.6-1866.33" - wire \builder_roundrobin1_request - attribute \src "ls180.v:1871.6-1871.28" - wire \builder_roundrobin2_ce - attribute \src "ls180.v:1870.6-1870.31" - wire \builder_roundrobin2_grant - attribute \src "ls180.v:1869.6-1869.33" - wire \builder_roundrobin2_request - attribute \src "ls180.v:1874.6-1874.28" - wire \builder_roundrobin3_ce - attribute \src "ls180.v:1873.6-1873.31" - wire \builder_roundrobin3_grant - attribute \src "ls180.v:1872.6-1872.33" - wire \builder_roundrobin3_request - attribute \src "ls180.v:1961.11-1961.44" - wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1960.11-1960.39" - wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1929.5-1929.50" - wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1928.5-1928.45" - wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1941.11-1941.40" - wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1940.11-1940.35" - wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1965.5-1965.42" - wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1964.5-1964.37" - wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1969.11-1969.58" - wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1968.11-1968.53" - wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1917.11-1917.39" - wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1916.11-1916.34" - wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1905.11-1905.45" - wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1904.11-1904.40" - wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1901.11-1901.45" - wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1900.11-1900.40" - wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1913.5-1913.39" - wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1912.5-1912.34" - wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1921.11-1921.46" - wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1920.11-1920.41" - wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1897.5-1897.39" - wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1896.5-1896.34" - wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:2001.5-2001.23" - wire \builder_shared_ack - attribute \src "ls180.v:1995.13-1995.31" - wire width 30 \builder_shared_adr - attribute \src "ls180.v:2004.12-2004.30" - wire width 2 \builder_shared_bte - attribute \src "ls180.v:2003.12-2003.30" - wire width 3 \builder_shared_cti - attribute \src "ls180.v:1999.6-1999.24" - wire \builder_shared_cyc - attribute \src "ls180.v:1997.12-1997.32" - wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1996.13-1996.33" - wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:2005.6-2005.24" - wire \builder_shared_err - attribute \src "ls180.v:1998.12-1998.30" - wire width 4 \builder_shared_sel - attribute \src "ls180.v:2000.6-2000.24" - wire \builder_shared_stb - attribute \src "ls180.v:2002.6-2002.23" - wire \builder_shared_we - attribute \src "ls180.v:2008.12-2008.29" - wire width 13 \builder_slave_sel - attribute \src "ls180.v:2009.12-2009.31" - wire width 13 \builder_slave_sel_r - attribute \src "ls180.v:1889.11-1889.40" - wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1888.11-1888.35" - wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1893.11-1893.40" - wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1892.11-1892.35" - wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2705.11-2705.24" - wire width 2 \builder_state - attribute \src "ls180.v:2758.5-2758.32" - wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2759.5-2759.32" - wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2751.11-2751.40" - wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2752.12-2752.41" - wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2753.5-2753.34" - wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2754.5-2754.34" - wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2755.5-2755.34" - wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2756.5-2756.34" - wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2757.5-2757.34" - wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:2011.6-2011.18" - wire \builder_wait - attribute \src "ls180.v:5.19-5.23" - wire width 3 input 1 \eint - attribute \src "ls180.v:171.12-171.18" - wire width 3 \eint_1 - attribute \src "ls180.v:34.20-34.26" - wire width 16 input 30 \gpio_i - attribute \src "ls180.v:35.20-35.26" - wire width 16 output 31 \gpio_o - attribute \src "ls180.v:36.20-36.27" - wire width 16 output 32 \gpio_oe - attribute \src "ls180.v:30.14-30.21" - wire output 26 \i2c_scl - attribute \src "ls180.v:31.13-31.22" - wire input 27 \i2c_sda_i - attribute \src "ls180.v:32.14-32.23" - wire output 28 \i2c_sda_o - attribute \src "ls180.v:33.14-33.24" - wire output 29 \i2c_sda_oe - attribute \src "ls180.v:49.13-49.21" - wire input 45 \jtag_tck - attribute \src "ls180.v:50.13-50.21" - wire input 46 \jtag_tdi - attribute \src "ls180.v:51.14-51.22" - wire output 47 \jtag_tdo - attribute \src "ls180.v:48.13-48.21" - wire input 44 \jtag_tms - attribute \src "ls180.v:937.6-937.18" - wire \main_ack_cmd - attribute \src "ls180.v:939.6-939.20" - wire \main_ack_rdata - attribute \src "ls180.v:938.6-938.20" - wire \main_ack_wdata - attribute \src "ls180.v:935.5-935.22" - wire \main_cmd_consumed - attribute \src "ls180.v:318.5-318.28" - wire \main_converter0_counter - attribute \src "ls180.v:1841.5-1841.50" - wire \main_converter0_counter_converter0_next_value - attribute \src "ls180.v:1842.5-1842.53" - wire \main_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:320.12-320.33" - wire width 64 \main_converter0_dat_r - attribute \src "ls180.v:319.6-319.27" - wire \main_converter0_reset - attribute \src "ls180.v:317.5-317.25" - wire \main_converter0_skip - attribute \src "ls180.v:333.5-333.28" - wire \main_converter1_counter - attribute \src "ls180.v:1845.5-1845.50" - wire \main_converter1_counter_converter1_next_value - attribute \src "ls180.v:1846.5-1846.53" - wire \main_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:335.12-335.33" - wire width 64 \main_converter1_dat_r - attribute \src "ls180.v:334.6-334.27" - wire \main_converter1_reset - attribute \src "ls180.v:332.5-332.25" - wire \main_converter1_skip - attribute \src "ls180.v:932.5-932.27" - wire \main_converter_counter - attribute \src "ls180.v:1886.5-1886.48" - wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1887.5-1887.51" - wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:934.12-934.32" - wire width 32 \main_converter_dat_r - attribute \src "ls180.v:933.6-933.26" - wire \main_converter_reset - attribute \src "ls180.v:931.5-931.24" - wire \main_converter_skip - attribute \src "ls180.v:349.6-349.23" - wire \main_dfi_p0_act_n - attribute \src "ls180.v:340.13-340.32" - wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:341.12-341.28" - wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:342.6-342.23" - wire \main_dfi_p0_cas_n - attribute \src "ls180.v:346.6-346.21" - wire \main_dfi_p0_cke - attribute \src "ls180.v:343.6-343.22" - wire \main_dfi_p0_cs_n - attribute \src "ls180.v:347.6-347.21" - wire \main_dfi_p0_odt - attribute \src "ls180.v:344.6-344.23" - wire \main_dfi_p0_ras_n - attribute \src "ls180.v:354.12-354.30" - wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:353.6-353.27" - wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:355.5-355.29" - wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:348.6-348.25" - wire \main_dfi_p0_reset_n - attribute \src "ls180.v:345.6-345.22" - wire \main_dfi_p0_we_n - attribute \src "ls180.v:350.13-350.31" - wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:351.6-351.27" - wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:352.12-352.35" - wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:1172.12-1172.22" - wire width 24 \main_dummy - attribute \src "ls180.v:1082.12-1082.45" - wire width 16 \main_gpiotristateasic0_oe_storage - attribute \src "ls180.v:1084.12-1084.46" - wire width 16 \main_gpiotristateasic0_out_storage - attribute \src "ls180.v:1085.13-1085.42" - wire width 16 \main_gpiotristateasic0_pads_i - attribute \src "ls180.v:1086.13-1086.42" - wire width 16 \main_gpiotristateasic0_pads_o - attribute \src "ls180.v:1087.13-1087.43" - wire width 16 \main_gpiotristateasic0_pads_oe - attribute \src "ls180.v:1083.12-1083.41" - wire width 16 \main_gpiotristateasic0_status - attribute \src "ls180.v:1089.5-1089.33" - wire \main_gpiotristateasic1_oe_re - attribute \src "ls180.v:1088.12-1088.45" - wire width 16 \main_gpiotristateasic1_oe_storage - attribute \src "ls180.v:1093.5-1093.34" - wire \main_gpiotristateasic1_out_re - attribute \src "ls180.v:1092.12-1092.46" - wire width 16 \main_gpiotristateasic1_out_storage - attribute \src "ls180.v:1094.13-1094.42" - wire width 16 \main_gpiotristateasic1_pads_i - attribute \src "ls180.v:1095.13-1095.42" - wire width 16 \main_gpiotristateasic1_pads_o - attribute \src "ls180.v:1096.13-1096.43" - wire width 16 \main_gpiotristateasic1_pads_oe - attribute \src "ls180.v:1090.12-1090.41" - wire width 16 \main_gpiotristateasic1_status - attribute \src "ls180.v:1091.6-1091.31" - wire \main_gpiotristateasic1_we - attribute \src "ls180.v:1194.6-1194.17" - wire \main_i2c_oe - attribute \src "ls180.v:1197.5-1197.16" - wire \main_i2c_re - attribute \src "ls180.v:1193.6-1193.18" - wire \main_i2c_scl - attribute \src "ls180.v:1195.6-1195.19" - wire \main_i2c_sda0 - attribute \src "ls180.v:1198.6-1198.19" - wire \main_i2c_sda1 - attribute \src "ls180.v:1199.6-1199.21" - wire \main_i2c_status - attribute \src "ls180.v:1196.11-1196.27" - wire width 3 \main_i2c_storage - attribute \src "ls180.v:1200.6-1200.17" - wire \main_i2c_we - attribute \src "ls180.v:339.5-339.17" - wire \main_int_rst - attribute \src "ls180.v:1660.6-1660.29" - wire \main_interface0_bus_ack - attribute \src "ls180.v:1654.13-1654.36" - wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1663.11-1663.34" - wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1662.11-1662.34" - wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1658.6-1658.29" - wire \main_interface0_bus_cyc - attribute \src "ls180.v:1656.13-1656.38" - wire width 64 \main_interface0_bus_dat_r - attribute \src "ls180.v:1655.13-1655.38" - wire width 64 \main_interface0_bus_dat_w - attribute \src "ls180.v:1664.6-1664.29" - wire \main_interface0_bus_err - attribute \src "ls180.v:1657.12-1657.35" - wire width 8 \main_interface0_bus_sel - attribute \src "ls180.v:1659.6-1659.29" - wire \main_interface0_bus_stb - attribute \src "ls180.v:1661.6-1661.28" - wire \main_interface0_bus_we - attribute \src "ls180.v:312.5-312.44" - wire \main_interface0_converted_interface_ack - attribute \src "ls180.v:306.13-306.52" - wire width 30 \main_interface0_converted_interface_adr - attribute \src "ls180.v:315.12-315.51" - wire width 2 \main_interface0_converted_interface_bte - attribute \src "ls180.v:314.12-314.51" - wire width 3 \main_interface0_converted_interface_cti - attribute \src "ls180.v:310.6-310.45" - wire \main_interface0_converted_interface_cyc - attribute \src "ls180.v:308.13-308.54" - wire width 64 \main_interface0_converted_interface_dat_r - attribute \src "ls180.v:307.13-307.54" - wire width 64 \main_interface0_converted_interface_dat_w - attribute \src "ls180.v:316.5-316.44" - wire \main_interface0_converted_interface_err - attribute \src "ls180.v:309.12-309.51" - wire width 8 \main_interface0_converted_interface_sel - attribute \src "ls180.v:311.6-311.45" - wire \main_interface0_converted_interface_stb - attribute \src "ls180.v:313.6-313.44" - wire \main_interface0_converted_interface_we - attribute \src "ls180.v:252.5-252.32" - wire \main_interface0_ram_bus_ack - attribute \src "ls180.v:246.13-246.40" - wire width 30 \main_interface0_ram_bus_adr - attribute \src "ls180.v:255.12-255.39" - wire width 2 \main_interface0_ram_bus_bte - attribute \src "ls180.v:254.12-254.39" - wire width 3 \main_interface0_ram_bus_cti - attribute \src "ls180.v:250.6-250.33" - wire \main_interface0_ram_bus_cyc - attribute \src "ls180.v:248.13-248.42" - wire width 64 \main_interface0_ram_bus_dat_r - attribute \src "ls180.v:247.13-247.42" - wire width 64 \main_interface0_ram_bus_dat_w - attribute \src "ls180.v:256.5-256.32" - wire \main_interface0_ram_bus_err - attribute \src "ls180.v:249.12-249.39" - wire width 8 \main_interface0_ram_bus_sel - attribute \src "ls180.v:251.6-251.33" - wire \main_interface0_ram_bus_stb - attribute \src "ls180.v:253.6-253.32" - wire \main_interface0_ram_bus_we - attribute \src "ls180.v:1751.6-1751.29" - wire \main_interface1_bus_ack - attribute \src "ls180.v:1745.12-1745.35" - wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1754.11-1754.34" - wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1753.11-1753.34" - wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1749.5-1749.28" - wire \main_interface1_bus_cyc - attribute \src "ls180.v:1747.13-1747.38" - wire width 64 \main_interface1_bus_dat_r - attribute \src "ls180.v:1746.12-1746.37" - wire width 64 \main_interface1_bus_dat_w - attribute \src "ls180.v:1755.6-1755.29" - wire \main_interface1_bus_err - attribute \src "ls180.v:1748.11-1748.34" - wire width 8 \main_interface1_bus_sel - attribute \src "ls180.v:1750.5-1750.28" - wire \main_interface1_bus_stb - attribute \src "ls180.v:1752.5-1752.27" - wire \main_interface1_bus_we - attribute \src "ls180.v:327.5-327.44" - wire \main_interface1_converted_interface_ack - attribute \src "ls180.v:321.13-321.52" - wire width 30 \main_interface1_converted_interface_adr - attribute \src "ls180.v:330.12-330.51" - wire width 2 \main_interface1_converted_interface_bte - attribute \src "ls180.v:329.12-329.51" - wire width 3 \main_interface1_converted_interface_cti - attribute \src "ls180.v:325.6-325.45" - wire \main_interface1_converted_interface_cyc - attribute \src "ls180.v:323.13-323.54" - wire width 64 \main_interface1_converted_interface_dat_r - attribute \src "ls180.v:322.13-322.54" - wire width 64 \main_interface1_converted_interface_dat_w - attribute \src "ls180.v:331.5-331.44" - wire \main_interface1_converted_interface_err - attribute \src "ls180.v:324.12-324.51" - wire width 8 \main_interface1_converted_interface_sel - attribute \src "ls180.v:326.6-326.45" - wire \main_interface1_converted_interface_stb - attribute \src "ls180.v:328.6-328.44" - wire \main_interface1_converted_interface_we - attribute \src "ls180.v:267.5-267.32" - wire \main_interface1_ram_bus_ack - attribute \src "ls180.v:261.13-261.40" - wire width 30 \main_interface1_ram_bus_adr - attribute \src "ls180.v:270.12-270.39" - wire width 2 \main_interface1_ram_bus_bte - attribute \src "ls180.v:269.12-269.39" - wire width 3 \main_interface1_ram_bus_cti - attribute \src "ls180.v:265.6-265.33" - wire \main_interface1_ram_bus_cyc - attribute \src "ls180.v:263.13-263.42" - wire width 64 \main_interface1_ram_bus_dat_r - attribute \src "ls180.v:262.13-262.42" - wire width 64 \main_interface1_ram_bus_dat_w - attribute \src "ls180.v:271.5-271.32" - wire \main_interface1_ram_bus_err - attribute \src "ls180.v:264.12-264.39" - wire width 8 \main_interface1_ram_bus_sel - attribute \src "ls180.v:266.6-266.33" - wire \main_interface1_ram_bus_stb - attribute \src "ls180.v:268.6-268.32" - wire \main_interface1_ram_bus_we - attribute \src "ls180.v:282.5-282.32" - wire \main_interface2_ram_bus_ack - attribute \src "ls180.v:276.13-276.40" - wire width 30 \main_interface2_ram_bus_adr - attribute \src "ls180.v:285.12-285.39" - wire width 2 \main_interface2_ram_bus_bte - attribute \src "ls180.v:284.12-284.39" - wire width 3 \main_interface2_ram_bus_cti - attribute \src "ls180.v:280.6-280.33" - wire \main_interface2_ram_bus_cyc - attribute \src "ls180.v:278.13-278.42" - wire width 64 \main_interface2_ram_bus_dat_r - attribute \src "ls180.v:277.13-277.42" - wire width 64 \main_interface2_ram_bus_dat_w - attribute \src "ls180.v:286.5-286.32" - wire \main_interface2_ram_bus_err - attribute \src "ls180.v:279.12-279.39" - wire width 8 \main_interface2_ram_bus_sel - attribute \src "ls180.v:281.6-281.33" - wire \main_interface2_ram_bus_stb - attribute \src "ls180.v:283.6-283.32" - wire \main_interface2_ram_bus_we - attribute \src "ls180.v:297.5-297.32" - wire \main_interface3_ram_bus_ack - attribute \src "ls180.v:291.13-291.40" - wire width 30 \main_interface3_ram_bus_adr - attribute \src "ls180.v:300.12-300.39" - wire width 2 \main_interface3_ram_bus_bte - attribute \src "ls180.v:299.12-299.39" - wire width 3 \main_interface3_ram_bus_cti - attribute \src "ls180.v:295.6-295.33" - wire \main_interface3_ram_bus_cyc - attribute \src "ls180.v:293.13-293.42" - wire width 64 \main_interface3_ram_bus_dat_r - attribute \src "ls180.v:292.13-292.42" - wire width 64 \main_interface3_ram_bus_dat_w - attribute \src "ls180.v:301.5-301.32" - wire \main_interface3_ram_bus_err - attribute \src "ls180.v:294.12-294.39" - wire width 8 \main_interface3_ram_bus_sel - attribute \src "ls180.v:296.6-296.33" - wire \main_interface3_ram_bus_stb - attribute \src "ls180.v:298.6-298.32" - wire \main_interface3_ram_bus_we - attribute \src "ls180.v:215.12-215.32" - wire width 6 \main_libresocsim_adr - attribute \src "ls180.v:62.6-62.32" - wire \main_libresocsim_bus_error - attribute \src "ls180.v:63.12-63.39" - wire width 32 \main_libresocsim_bus_errors - attribute \src "ls180.v:59.13-59.47" - wire width 32 \main_libresocsim_bus_errors_status - attribute \src "ls180.v:60.6-60.36" - wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:216.13-216.35" - wire width 64 \main_libresocsim_dat_r - attribute \src "ls180.v:218.13-218.35" - wire width 64 \main_libresocsim_dat_w - attribute \src "ls180.v:224.5-224.27" - wire \main_libresocsim_en_re - attribute \src "ls180.v:223.5-223.32" - wire \main_libresocsim_en_storage - attribute \src "ls180.v:240.6-240.45" - wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:239.6-239.46" - wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:242.6-242.45" - wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:241.6-241.46" - wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:244.5-244.37" - wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:236.6-236.44" - wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:235.6-235.45" - wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:238.6-238.44" - wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:237.6-237.45" - wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:243.5-243.42" - wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:229.6-229.26" - wire \main_libresocsim_irq - attribute \src "ls180.v:165.6-165.32" - wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:166.6-166.32" - wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:167.13-167.39" - wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:169.12-169.45" - wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:197.13-197.67" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:198.13-198.67" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:199.13-199.68" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:193.6-193.61" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:194.6-194.63" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:195.6-195.63" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:196.6-196.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:189.6-189.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:190.6-190.66" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:191.6-191.66" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:192.6-192.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:172.13-172.68" - wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:181.12-181.68" - wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:178.6-178.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:180.6-180.63" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:179.6-179.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:182.12-182.68" - wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:173.13-173.71" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:174.13-174.71" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:175.6-175.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:177.6-177.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:176.6-176.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:200.6-200.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:202.6-202.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:203.6-203.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:201.6-201.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:185.6-185.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:187.6-187.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:188.6-188.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:186.6-186.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - attribute \src "ls180.v:72.6-72.40" - wire \main_libresocsim_libresoc_dbus_ack - attribute \src "ls180.v:66.13-66.47" - wire width 29 \main_libresocsim_libresoc_dbus_adr - attribute \src "ls180.v:75.11-75.45" - wire width 2 \main_libresocsim_libresoc_dbus_bte - attribute \src "ls180.v:74.11-74.45" - wire width 3 \main_libresocsim_libresoc_dbus_cti - attribute \src "ls180.v:70.6-70.40" - wire \main_libresocsim_libresoc_dbus_cyc - attribute \src "ls180.v:68.13-68.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_r - attribute \src "ls180.v:67.13-67.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:76.6-76.40" - wire \main_libresocsim_libresoc_dbus_err - attribute \src "ls180.v:69.12-69.46" - wire width 8 \main_libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:71.6-71.40" - wire \main_libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:73.6-73.39" - wire \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:83.6-83.40" - wire \main_libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:77.13-77.47" - wire width 29 \main_libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:86.11-86.45" - wire width 2 \main_libresocsim_libresoc_ibus_bte - attribute \src "ls180.v:85.11-85.45" - wire width 3 \main_libresocsim_libresoc_ibus_cti - attribute \src "ls180.v:81.6-81.40" - wire \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:79.13-79.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:78.13-78.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:87.6-87.40" - wire \main_libresocsim_libresoc_ibus_err - attribute \src "ls180.v:80.12-80.46" - wire width 8 \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:82.6-82.40" - wire \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:84.6-84.39" - wire \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:123.6-123.46" - wire \main_libresocsim_libresoc_interface0_ack - attribute \src "ls180.v:117.13-117.53" - wire width 29 \main_libresocsim_libresoc_interface0_adr - attribute \src "ls180.v:126.12-126.52" - wire width 2 \main_libresocsim_libresoc_interface0_bte - attribute \src "ls180.v:125.12-125.52" - wire width 3 \main_libresocsim_libresoc_interface0_cti - attribute \src "ls180.v:121.6-121.46" - wire \main_libresocsim_libresoc_interface0_cyc - attribute \src "ls180.v:119.13-119.55" - wire width 64 \main_libresocsim_libresoc_interface0_dat_r - attribute \src "ls180.v:118.13-118.55" - wire width 64 \main_libresocsim_libresoc_interface0_dat_w - attribute \src "ls180.v:127.6-127.46" - wire \main_libresocsim_libresoc_interface0_err - attribute \src "ls180.v:120.12-120.52" - wire width 8 \main_libresocsim_libresoc_interface0_sel - attribute \src "ls180.v:122.6-122.46" - wire \main_libresocsim_libresoc_interface0_stb - attribute \src "ls180.v:124.6-124.45" - wire \main_libresocsim_libresoc_interface0_we - attribute \src "ls180.v:134.6-134.46" - wire \main_libresocsim_libresoc_interface1_ack - attribute \src "ls180.v:128.13-128.53" - wire width 29 \main_libresocsim_libresoc_interface1_adr - attribute \src "ls180.v:137.12-137.52" - wire width 2 \main_libresocsim_libresoc_interface1_bte - attribute \src "ls180.v:136.12-136.52" - wire width 3 \main_libresocsim_libresoc_interface1_cti - attribute \src "ls180.v:132.6-132.46" - wire \main_libresocsim_libresoc_interface1_cyc - attribute \src "ls180.v:130.13-130.55" - wire width 64 \main_libresocsim_libresoc_interface1_dat_r - attribute \src "ls180.v:129.13-129.55" - wire width 64 \main_libresocsim_libresoc_interface1_dat_w - attribute \src "ls180.v:138.6-138.46" - wire \main_libresocsim_libresoc_interface1_err - attribute \src "ls180.v:131.12-131.52" - wire width 8 \main_libresocsim_libresoc_interface1_sel - attribute \src "ls180.v:133.6-133.46" - wire \main_libresocsim_libresoc_interface1_stb - attribute \src "ls180.v:135.6-135.45" - wire \main_libresocsim_libresoc_interface1_we - attribute \src "ls180.v:145.6-145.46" - wire \main_libresocsim_libresoc_interface2_ack - attribute \src "ls180.v:139.13-139.53" - wire width 29 \main_libresocsim_libresoc_interface2_adr - attribute \src "ls180.v:148.12-148.52" - wire width 2 \main_libresocsim_libresoc_interface2_bte - attribute \src "ls180.v:147.12-147.52" - wire width 3 \main_libresocsim_libresoc_interface2_cti - attribute \src "ls180.v:143.6-143.46" - wire \main_libresocsim_libresoc_interface2_cyc - attribute \src "ls180.v:141.13-141.55" - wire width 64 \main_libresocsim_libresoc_interface2_dat_r - attribute \src "ls180.v:140.13-140.55" - wire width 64 \main_libresocsim_libresoc_interface2_dat_w - attribute \src "ls180.v:149.6-149.46" - wire \main_libresocsim_libresoc_interface2_err - attribute \src "ls180.v:142.12-142.52" - wire width 8 \main_libresocsim_libresoc_interface2_sel - attribute \src "ls180.v:144.6-144.46" - wire \main_libresocsim_libresoc_interface2_stb - attribute \src "ls180.v:146.6-146.45" - wire \main_libresocsim_libresoc_interface2_we - attribute \src "ls180.v:156.6-156.46" - wire \main_libresocsim_libresoc_interface3_ack - attribute \src "ls180.v:150.13-150.53" - wire width 29 \main_libresocsim_libresoc_interface3_adr - attribute \src "ls180.v:159.12-159.52" - wire width 2 \main_libresocsim_libresoc_interface3_bte - attribute \src "ls180.v:158.12-158.52" - wire width 3 \main_libresocsim_libresoc_interface3_cti - attribute \src "ls180.v:154.6-154.46" - wire \main_libresocsim_libresoc_interface3_cyc - attribute \src "ls180.v:152.13-152.55" - wire width 64 \main_libresocsim_libresoc_interface3_dat_r - attribute \src "ls180.v:151.13-151.55" - wire width 64 \main_libresocsim_libresoc_interface3_dat_w - attribute \src "ls180.v:160.6-160.46" - wire \main_libresocsim_libresoc_interface3_err - attribute \src "ls180.v:153.12-153.52" - wire width 8 \main_libresocsim_libresoc_interface3_sel - attribute \src "ls180.v:155.6-155.46" - wire \main_libresocsim_libresoc_interface3_stb - attribute \src "ls180.v:157.6-157.45" - wire \main_libresocsim_libresoc_interface3_we - attribute \src "ls180.v:65.12-65.47" - wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:161.6-161.40" - wire \main_libresocsim_libresoc_jtag_tck - attribute \src "ls180.v:163.6-163.40" - wire \main_libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:164.6-164.40" - wire \main_libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:162.6-162.40" - wire \main_libresocsim_libresoc_jtag_tms - attribute \src "ls180.v:112.6-112.43" - wire \main_libresocsim_libresoc_jtag_wb_ack - attribute \src "ls180.v:106.13-106.50" - wire width 29 \main_libresocsim_libresoc_jtag_wb_adr - attribute \src "ls180.v:115.11-115.48" - wire width 2 \main_libresocsim_libresoc_jtag_wb_bte - attribute \src "ls180.v:114.11-114.48" - wire width 3 \main_libresocsim_libresoc_jtag_wb_cti - attribute \src "ls180.v:110.6-110.43" - wire \main_libresocsim_libresoc_jtag_wb_cyc - attribute \src "ls180.v:108.13-108.52" - wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r - attribute \src "ls180.v:107.13-107.52" - wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:116.6-116.43" - wire \main_libresocsim_libresoc_jtag_wb_err - attribute \src "ls180.v:109.12-109.49" - wire width 8 \main_libresocsim_libresoc_jtag_wb_sel - attribute \src "ls180.v:111.6-111.43" - wire \main_libresocsim_libresoc_jtag_wb_stb - attribute \src "ls180.v:113.6-113.42" - wire \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:168.6-168.40" - wire \main_libresocsim_libresoc_pll_18_o - attribute \src "ls180.v:170.6-170.41" - wire \main_libresocsim_libresoc_pll_lck_o - attribute \src "ls180.v:64.6-64.37" - wire \main_libresocsim_libresoc_reset - attribute \src "ls180.v:94.6-94.44" - wire \main_libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:88.12-88.50" - wire width 30 \main_libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:92.5-92.43" - wire \main_libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:90.13-90.53" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:89.12-89.52" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:96.6-96.44" - wire \main_libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:91.11-91.49" - wire width 4 \main_libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:93.5-93.43" - wire \main_libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:95.5-95.42" - wire \main_libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:103.6-103.44" - wire \main_libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:97.12-97.50" - wire width 30 \main_libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:101.5-101.43" - wire \main_libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:99.13-99.53" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:98.12-98.52" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w - attribute \src "ls180.v:105.6-105.44" - wire \main_libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:100.11-100.49" - wire width 4 \main_libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:102.5-102.43" - wire \main_libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:104.5-104.42" - wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:220.5-220.29" - wire \main_libresocsim_load_re - attribute \src "ls180.v:219.12-219.41" - wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:210.5-210.33" - wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:204.13-204.41" - wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:213.12-213.40" - wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:212.12-212.40" - wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:208.6-208.34" - wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:206.13-206.43" - wire width 64 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:205.13-205.43" - wire width 64 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:214.5-214.33" - wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:207.12-207.40" - wire width 8 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:209.6-209.34" - wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:211.6-211.33" - wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:222.5-222.31" - wire \main_libresocsim_reload_re - attribute \src "ls180.v:221.12-221.43" - wire width 32 \main_libresocsim_reload_storage - attribute \src "ls180.v:61.6-61.28" - wire \main_libresocsim_reset - attribute \src "ls180.v:56.5-56.30" - wire \main_libresocsim_reset_re - attribute \src "ls180.v:55.5-55.35" - wire \main_libresocsim_reset_storage - attribute \src "ls180.v:58.5-58.32" - wire \main_libresocsim_scratch_re - attribute \src "ls180.v:57.12-57.44" - wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:226.5-226.37" - wire \main_libresocsim_update_value_re - attribute \src "ls180.v:225.5-225.42" - wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:245.12-245.34" - wire width 32 \main_libresocsim_value - attribute \src "ls180.v:227.12-227.41" - wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:228.6-228.31" - wire \main_libresocsim_value_we - attribute \src "ls180.v:217.11-217.30" - wire width 8 \main_libresocsim_we - attribute \src "ls180.v:233.5-233.32" - wire \main_libresocsim_zero_clear - attribute \src "ls180.v:234.5-234.38" - wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:231.5-231.34" - wire \main_libresocsim_zero_pending - attribute \src "ls180.v:230.6-230.34" - wire \main_libresocsim_zero_status - attribute \src "ls180.v:232.6-232.35" - wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:929.6-929.26" - wire \main_litedram_wb_ack - attribute \src "ls180.v:923.12-923.32" - wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:927.5-927.25" - wire \main_litedram_wb_cyc - attribute \src "ls180.v:925.13-925.35" - wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:924.12-924.34" - wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:926.11-926.31" - wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:928.5-928.25" - wire \main_litedram_wb_stb - attribute \src "ls180.v:930.5-930.24" - wire \main_litedram_wb_we - attribute \src "ls180.v:1171.13-1171.20" - wire width 24 \main_nc - attribute \src "ls180.v:890.6-890.24" - wire \main_port_cmd_last - attribute \src "ls180.v:892.13-892.39" - wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:891.6-891.30" - wire \main_port_cmd_payload_we - attribute \src "ls180.v:889.6-889.25" - wire \main_port_cmd_ready - attribute \src "ls180.v:888.6-888.25" - wire \main_port_cmd_valid - attribute \src "ls180.v:887.6-887.21" - wire \main_port_flush - attribute \src "ls180.v:899.13-899.41" - wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:898.6-898.27" - wire \main_port_rdata_ready - attribute \src "ls180.v:897.6-897.27" - wire \main_port_rdata_valid - attribute \src "ls180.v:895.13-895.41" - wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:896.12-896.38" - wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:894.6-894.27" - wire \main_port_wdata_ready - attribute \src "ls180.v:893.6-893.27" - wire \main_port_wdata_valid - attribute \src "ls180.v:1176.12-1176.29" - wire width 32 \main_pwm0_counter - attribute \src "ls180.v:1173.6-1173.22" - wire \main_pwm0_enable - attribute \src "ls180.v:1178.5-1178.24" - wire \main_pwm0_enable_re - attribute \src "ls180.v:1177.5-1177.29" - wire \main_pwm0_enable_storage - attribute \src "ls180.v:1175.13-1175.29" - wire width 32 \main_pwm0_period - attribute \src "ls180.v:1182.5-1182.24" - wire \main_pwm0_period_re - attribute \src "ls180.v:1181.12-1181.36" - wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1174.13-1174.28" - wire width 32 \main_pwm0_width - attribute \src "ls180.v:1180.5-1180.23" - wire \main_pwm0_width_re - attribute \src "ls180.v:1179.12-1179.35" - wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1186.12-1186.29" - wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1183.6-1183.22" - wire \main_pwm1_enable - attribute \src "ls180.v:1188.5-1188.24" - wire \main_pwm1_enable_re - attribute \src "ls180.v:1187.5-1187.29" - wire \main_pwm1_enable_storage - attribute \src "ls180.v:1185.13-1185.29" - wire width 32 \main_pwm1_period - attribute \src "ls180.v:1192.5-1192.24" - wire \main_pwm1_period_re - attribute \src "ls180.v:1191.12-1191.36" - wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1184.13-1184.28" - wire width 32 \main_pwm1_width - attribute \src "ls180.v:1190.5-1190.23" - wire \main_pwm1_width_re - attribute \src "ls180.v:1189.12-1189.35" - wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:356.11-356.25" - wire width 3 \main_rddata_en - attribute \src "ls180.v:1714.11-1714.43" - wire width 3 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1715.6-1715.42" - wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1705.6-1705.43" - wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1706.6-1706.42" - wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1707.12-1707.56" - wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1704.6-1704.43" - wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1703.6-1703.43" - wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1710.5-1710.44" - wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1711.5-1711.43" - wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1712.12-1712.58" - wire width 64 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1713.11-1713.70" - wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1709.6-1709.45" - wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1708.6-1708.45" - wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1716.5-1716.42" - wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1689.11-1689.40" - wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1694.6-1694.35" - wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1698.6-1698.41" - wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1699.6-1699.40" - wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1697.12-1697.54" - wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1701.6-1701.42" - wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1702.6-1702.41" - wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1700.12-1700.55" - wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1686.11-1686.38" - wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1688.11-1688.40" - wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1695.12-1695.44" - wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1696.12-1696.46" - wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1687.5-1687.34" - wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1672.6-1672.38" - wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1673.6-1673.37" - wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1674.12-1674.51" - wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1671.6-1671.38" - wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1670.6-1670.38" - wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1677.6-1677.40" - wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1678.6-1678.39" - wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1679.12-1679.53" - wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1676.6-1676.40" - wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1675.6-1675.40" - wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1684.12-1684.46" - wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1685.12-1685.47" - wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1682.6-1682.39" - wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1683.6-1683.45" - wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1680.6-1680.39" - wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1681.6-1681.45" - wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1690.11-1690.43" - wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1691.12-1691.46" - wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1693.12-1693.46" - wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1692.6-1692.37" - wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1667.6-1667.38" - wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1668.6-1668.37" - wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1724.12-1724.54" - wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1669.12-1669.52" - wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1725.12-1725.52" - wire width 64 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1666.6-1666.39" - wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1723.6-1723.39" - wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1665.6-1665.39" - wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1722.5-1722.38" - wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1719.6-1719.42" - wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1720.6-1720.41" - wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1721.13-1721.56" - wire width 64 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1718.6-1718.42" - wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1717.6-1717.42" - wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1741.13-1741.52" - wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1732.5-1732.47" - wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1731.12-1731.59" - wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1736.5-1736.49" - wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1735.5-1735.54" - wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1743.13-1743.54" - wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1734.5-1734.49" - wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1733.12-1733.61" - wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1740.5-1740.47" - wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1739.5-1739.52" - wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1742.12-1742.53" - wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1962.12-1962.79" - wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1963.5-1963.75" - wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1744.6-1744.46" - wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1728.6-1728.51" - wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1729.6-1729.50" - wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1730.13-1730.65" - wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1727.5-1727.50" - wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1726.6-1726.51" - wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1737.5-1737.46" - wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1738.6-1738.43" - wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1506.5-1506.31" - wire \main_sdcore_block_count_re - attribute \src "ls180.v:1505.12-1505.43" - wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1504.5-1504.32" - wire \main_sdcore_block_length_re - attribute \src "ls180.v:1503.11-1503.43" - wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1490.5-1490.32" - wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1489.12-1489.44" - wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1492.5-1492.31" - wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1491.12-1491.43" - wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1645.11-1645.32" - wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1946.11-1946.55" - wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1947.5-1947.52" - wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1646.5-1646.25" - wire \main_sdcore_cmd_done - attribute \src "ls180.v:1942.5-1942.48" - wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1943.5-1943.51" - wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1647.5-1647.26" - wire \main_sdcore_cmd_error - attribute \src "ls180.v:1950.5-1950.49" - wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1951.5-1951.52" - wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1499.12-1499.40" - wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1500.6-1500.30" - wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1497.13-1497.44" - wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1958.13-1958.67" - wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1959.5-1959.62" - wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1498.6-1498.33" - wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1494.6-1494.28" - wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1493.6-1493.29" - wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1496.5-1496.27" - wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1495.6-1495.29" - wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1648.5-1648.28" - wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1952.5-1952.51" - wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1953.5-1953.54" - wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1644.12-1644.32" - wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1606.11-1606.40" - wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1612.5-1612.39" - wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1611.12-1611.46" - wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1607.12-1607.50" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1608.13-1608.51" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1609.13-1609.51" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1613.6-1613.43" - wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1610.12-1610.46" - wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1619.5-1619.39" - wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1618.12-1618.46" - wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1614.12-1614.50" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1615.13-1615.51" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1616.13-1616.51" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1620.6-1620.43" - wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1617.12-1617.46" - wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1626.5-1626.39" - wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1625.12-1625.46" - wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1621.12-1621.50" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1622.13-1622.51" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1623.13-1623.51" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1627.6-1627.43" - wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1624.12-1624.46" - wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1633.5-1633.39" - wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1632.12-1632.46" - wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1628.12-1628.50" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1629.13-1629.51" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1630.13-1630.51" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1634.6-1634.43" - wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1631.12-1631.46" - wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1635.12-1635.45" - wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1636.12-1636.45" - wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1637.12-1637.45" - wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1638.12-1638.45" - wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1640.12-1640.43" - wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1641.12-1641.43" - wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1642.12-1642.43" - wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1643.12-1643.43" - wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1597.5-1597.41" - wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1598.5-1598.40" - wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1599.11-1599.54" - wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1596.5-1596.41" - wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1595.5-1595.41" - wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1602.5-1602.43" - wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1603.6-1603.43" - wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1604.12-1604.57" - wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1601.6-1601.44" - wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1600.5-1600.43" - wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1605.11-1605.40" - wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1639.5-1639.36" - wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1562.11-1562.41" - wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1938.11-1938.80" - wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1939.5-1939.77" - wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1568.6-1568.41" - wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1567.12-1567.47" - wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1563.12-1563.51" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1564.13-1564.52" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1565.13-1565.52" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1569.6-1569.44" - wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1566.12-1566.47" - wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1575.6-1575.41" - wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1574.12-1574.47" - wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1570.12-1570.51" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1571.13-1571.52" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1572.13-1572.52" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1576.6-1576.44" - wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1573.12-1573.47" - wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1582.6-1582.41" - wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1581.12-1581.47" - wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1577.12-1577.51" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1578.13-1578.52" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1579.13-1579.52" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1583.6-1583.44" - wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1580.12-1580.47" - wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1589.6-1589.41" - wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1588.12-1588.47" - wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1584.12-1584.51" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1585.13-1585.52" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1586.13-1586.52" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1590.6-1590.44" - wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1587.12-1587.47" - wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1591.12-1591.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1930.12-1930.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1931.5-1931.81" - wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1592.12-1592.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1932.12-1932.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1933.5-1933.81" - wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1593.12-1593.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1934.12-1934.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1935.5-1935.81" - wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1594.12-1594.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1936.12-1936.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1937.5-1937.81" - wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1554.6-1554.43" - wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1555.6-1555.42" - wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1556.12-1556.56" - wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1553.5-1553.42" - wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1552.6-1552.43" - wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1559.5-1559.44" - wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1560.5-1560.43" - wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1561.11-1561.57" - wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1558.5-1558.44" - wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1557.5-1557.44" - wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1550.6-1550.35" - wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1549.11-1549.40" - wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1507.11-1507.44" - wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1508.12-1508.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1517.12-1517.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1518.12-1518.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1519.12-1519.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1520.12-1520.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1521.12-1521.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1522.12-1522.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1523.12-1523.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1524.12-1524.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1525.12-1525.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1526.12-1526.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1509.12-1509.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1527.12-1527.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1528.12-1528.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1529.12-1529.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1530.12-1530.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1531.12-1531.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1532.12-1532.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1533.12-1533.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1534.12-1534.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1535.12-1535.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1536.12-1536.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1510.12-1510.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1537.12-1537.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1538.12-1538.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1539.12-1539.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1540.12-1540.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1541.12-1541.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1542.12-1542.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1543.12-1543.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1544.12-1544.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1545.12-1545.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1546.12-1546.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1511.12-1511.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1547.12-1547.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1512.12-1512.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1513.12-1513.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1514.12-1514.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1515.12-1515.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1516.12-1516.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1551.6-1551.38" - wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1548.13-1548.42" - wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1650.12-1650.34" - wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1948.12-1948.57" - wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1949.5-1949.53" - wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1651.5-1651.26" - wire \main_sdcore_data_done - attribute \src "ls180.v:1944.5-1944.49" - wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1945.5-1945.52" - wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1652.5-1652.27" - wire \main_sdcore_data_error - attribute \src "ls180.v:1954.5-1954.50" - wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1955.5-1955.53" - wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1501.12-1501.41" - wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1502.6-1502.31" - wire \main_sdcore_data_event_we - attribute \src "ls180.v:1653.5-1653.29" - wire \main_sdcore_data_timeout - attribute \src "ls180.v:1956.5-1956.52" - wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1957.5-1957.55" - wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1649.12-1649.33" - wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1481.6-1481.33" - wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1482.6-1482.32" - wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1483.12-1483.46" - wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1480.6-1480.33" - wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1479.6-1479.33" - wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1486.6-1486.37" - wire \main_sdcore_source_source_first - attribute \src "ls180.v:1487.6-1487.36" - wire \main_sdcore_source_source_last - attribute \src "ls180.v:1488.12-1488.50" - wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1485.6-1485.37" - wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1484.6-1484.37" - wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1799.6-1799.38" - wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1800.6-1800.37" - wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1798.11-1798.41" - wire width 3 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1789.6-1789.43" - wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1790.6-1790.42" - wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1791.13-1791.57" - wire width 64 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1788.6-1788.43" - wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1787.6-1787.43" - wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1794.6-1794.45" - wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1795.6-1795.44" - wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1796.11-1796.57" - wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1797.6-1797.65" - wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1793.6-1793.45" - wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1792.6-1792.45" - wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1783.13-1783.38" - wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1772.5-1772.33" - wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1771.12-1771.45" - wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1770.12-1770.37" - wire width 64 \main_sdmem2block_dma_data - attribute \src "ls180.v:1966.12-1966.67" - wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1967.5-1967.63" - wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1777.5-1777.37" - wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1778.6-1778.34" - wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1776.5-1776.35" - wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1775.5-1775.40" - wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1785.13-1785.40" - wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1774.5-1774.35" - wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1773.12-1773.47" - wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1780.5-1780.33" - wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1779.5-1779.38" - wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1784.12-1784.39" - wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1970.12-1970.79" - wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1971.5-1971.75" - wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1781.13-1781.47" - wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1782.6-1782.36" - wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1786.6-1786.32" - wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1763.5-1763.35" - wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1764.12-1764.53" - wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1762.5-1762.36" - wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1761.5-1761.36" - wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1767.5-1767.38" - wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1768.5-1768.37" - wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1769.12-1769.52" - wire width 64 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1766.6-1766.39" - wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1765.5-1765.38" - wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1825.11-1825.40" - wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1830.6-1830.35" - wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1834.6-1834.41" - wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1835.6-1835.40" - wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1833.12-1833.54" - wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1837.6-1837.42" - wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1838.6-1838.41" - wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1836.12-1836.55" - wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1822.11-1822.38" - wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1824.11-1824.40" - wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1831.12-1831.44" - wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1832.12-1832.46" - wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1823.5-1823.34" - wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1808.6-1808.38" - wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1809.6-1809.37" - wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1810.12-1810.51" - wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1807.6-1807.38" - wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1806.6-1806.38" - wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1813.6-1813.40" - wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1814.6-1814.39" - wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1815.12-1815.53" - wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1812.6-1812.40" - wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1811.6-1811.40" - wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1820.12-1820.46" - wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1821.12-1821.47" - wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1818.6-1818.39" - wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1819.6-1819.45" - wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1816.6-1816.39" - wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1817.6-1817.45" - wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1826.11-1826.43" - wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1827.12-1827.46" - wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1829.12-1829.46" - wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1828.6-1828.37" - wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1758.6-1758.43" - wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1803.6-1803.43" - wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1759.6-1759.42" - wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1804.6-1804.42" - wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1760.12-1760.56" - wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1805.12-1805.56" - wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1757.6-1757.43" - wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1802.6-1802.43" - wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1756.6-1756.43" - wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1801.6-1801.43" - wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1207.6-1207.27" - wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1206.5-1206.28" - wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1209.5-1209.28" - wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1210.5-1210.29" - wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1208.11-1208.34" - wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1204.5-1204.26" - wire \main_sdphy_clocker_re - attribute \src "ls180.v:1205.6-1205.29" - wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1203.11-1203.37" - wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1307.6-1307.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1308.6-1308.40" - wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1309.12-1309.54" - wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1306.6-1306.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1305.6-1305.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1312.5-1312.42" - wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1313.5-1313.41" - wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1314.11-1314.55" - wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1311.6-1311.43" - wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1310.5-1310.42" - wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1297.11-1297.47" - wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1298.6-1298.46" - wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1288.5-1288.46" - wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1289.5-1289.45" - wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1290.6-1290.54" - wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1287.6-1287.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1286.6-1286.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1293.5-1293.48" - wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1294.5-1294.47" - wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1295.11-1295.61" - wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1296.11-1296.74" - wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1292.6-1292.49" - wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1291.6-1291.49" - wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1299.5-1299.46" - wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1270.6-1270.40" - wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1271.6-1271.39" - wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1272.6-1272.46" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1273.6-1273.48" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1274.6-1274.48" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1275.6-1275.49" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1276.12-1276.55" - wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1277.12-1277.55" - wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1278.6-1278.50" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1269.5-1269.39" - wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1268.6-1268.40" - wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1315.5-1315.31" - wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1910.5-1910.59" - wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1911.5-1911.62" - wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1285.5-1285.29" - wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1281.6-1281.47" - wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1302.6-1302.47" - wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1282.6-1282.46" - wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1303.6-1303.46" - wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1283.12-1283.60" - wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1304.12-1304.60" - wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1280.5-1280.46" - wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1301.6-1301.47" - wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1279.6-1279.47" - wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1300.6-1300.47" - wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1284.6-1284.32" - wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1267.11-1267.32" - wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1906.11-1906.60" - wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1907.5-1907.57" - wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1242.5-1242.42" - wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1243.5-1243.41" - wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1244.5-1244.48" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1245.6-1245.51" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1246.5-1246.50" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1247.5-1247.51" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1248.12-1248.58" - wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1249.11-1249.57" - wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1250.5-1250.52" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1241.6-1241.43" - wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1240.6-1240.43" - wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1252.5-1252.41" - wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1253.5-1253.43" - wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1254.5-1254.44" - wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1255.11-1255.50" - wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1256.5-1256.45" - wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1251.6-1251.36" - wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1259.5-1259.30" - wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1260.11-1260.46" - wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1258.5-1258.31" - wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1257.5-1257.31" - wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1263.5-1263.32" - wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1264.11-1264.46" - wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1265.11-1265.48" - wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1262.5-1262.33" - wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1261.5-1261.33" - wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1266.12-1266.35" - wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1908.12-1908.63" - wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1909.5-1909.59" - wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1239.11-1239.32" - wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1902.11-1902.59" - wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1903.5-1903.56" - wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1238.5-1238.25" - wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1226.6-1226.43" - wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1227.12-1227.50" - wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1225.6-1225.35" - wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1229.5-1229.41" - wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1230.5-1230.43" - wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1231.5-1231.44" - wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1232.11-1232.50" - wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1233.5-1233.45" - wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1228.6-1228.36" - wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1236.5-1236.30" - wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1237.11-1237.44" - wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1235.5-1235.31" - wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1234.5-1234.31" - wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1423.11-1423.33" - wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1922.11-1922.62" - wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1923.5-1923.59" - wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1463.6-1463.43" - wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1464.6-1464.42" - wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1465.12-1465.56" - wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1462.6-1462.43" - wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1461.6-1461.43" - wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1468.5-1468.44" - wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1469.5-1469.43" - wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1470.11-1470.57" - wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1467.6-1467.45" - wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1466.5-1466.44" - wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1453.5-1453.43" - wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1454.6-1454.48" - wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1444.5-1444.48" - wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1445.5-1445.47" - wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1446.12-1446.62" - wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1443.6-1443.49" - wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1442.6-1442.49" - wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1449.5-1449.50" - wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1450.5-1450.49" - wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1451.11-1451.63" - wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1452.11-1452.76" - wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1448.6-1448.51" - wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1447.6-1447.51" - wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1455.5-1455.48" - wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1426.6-1426.42" - wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1427.6-1427.41" - wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1428.6-1428.48" - wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1429.6-1429.50" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1430.6-1430.50" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1431.6-1431.51" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1432.12-1432.57" - wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1433.12-1433.57" - wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1434.6-1434.52" - wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1425.5-1425.41" - wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1424.6-1424.42" - wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1471.5-1471.33" - wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1926.5-1926.62" - wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1927.5-1927.65" - wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1441.5-1441.31" - wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1437.6-1437.49" - wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1458.6-1458.49" - wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1438.6-1438.48" - wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1459.6-1459.48" - wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1439.12-1439.62" - wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1460.12-1460.62" - wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1436.5-1436.48" - wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1457.6-1457.49" - wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1435.6-1435.49" - wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1456.6-1456.49" - wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1440.6-1440.34" - wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1396.5-1396.43" - wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1397.5-1397.42" - wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1398.5-1398.49" - wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1399.6-1399.52" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1400.5-1400.51" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1401.5-1401.52" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1402.12-1402.59" - wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1403.11-1403.58" - wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1404.5-1404.53" - wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1395.6-1395.44" - wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1394.6-1394.44" - wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1406.5-1406.42" - wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1407.5-1407.44" - wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1408.5-1408.45" - wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1409.11-1409.51" - wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1410.5-1410.46" - wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1405.6-1405.37" - wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1413.5-1413.31" - wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1414.11-1414.53" - wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1412.5-1412.32" - wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1411.5-1411.32" - wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1417.5-1417.34" - wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1418.5-1418.33" - wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1419.11-1419.47" - wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1420.11-1420.49" - wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1416.5-1416.34" - wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1415.5-1415.34" - wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1421.5-1421.26" - wire \main_sdphy_datar_stop - attribute \src "ls180.v:1422.12-1422.36" - wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1924.12-1924.65" - wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1925.5-1925.61" - wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1331.11-1331.33" - wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1918.11-1918.54" - wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1919.5-1919.51" - wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1385.6-1385.42" - wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1386.6-1386.41" - wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1387.12-1387.55" - wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1384.6-1384.42" - wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1383.6-1383.42" - wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1390.5-1390.43" - wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1391.5-1391.42" - wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1392.11-1392.56" - wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1389.6-1389.44" - wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1388.5-1388.43" - wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1375.11-1375.48" - wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1376.6-1376.47" - wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1366.5-1366.47" - wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1367.5-1367.46" - wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1368.6-1368.55" - wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1365.6-1365.48" - wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1364.6-1364.48" - wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1371.5-1371.49" - wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1372.5-1372.48" - wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1373.11-1373.62" - wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1374.11-1374.75" - wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1370.6-1370.50" - wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1369.6-1369.50" - wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1377.5-1377.47" - wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1348.6-1348.41" - wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1349.6-1349.40" - wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1350.6-1350.47" - wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1351.6-1351.49" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1352.6-1352.49" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1353.6-1353.50" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1354.12-1354.56" - wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1355.12-1355.56" - wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1356.6-1356.51" - wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1347.5-1347.40" - wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1346.6-1346.41" - wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1393.5-1393.32" - wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1914.5-1914.59" - wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1915.5-1915.62" - wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1363.5-1363.30" - wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1359.6-1359.48" - wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1380.6-1380.48" - wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1360.6-1360.47" - wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1381.6-1381.47" - wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1361.12-1361.61" - wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1382.12-1382.61" - wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1358.5-1358.47" - wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1379.6-1379.48" - wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1357.6-1357.48" - wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1378.6-1378.48" - wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1362.6-1362.33" - wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1345.5-1345.27" - wire \main_sdphy_dataw_error - attribute \src "ls180.v:1334.5-1334.43" - wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1335.5-1335.42" - wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1336.5-1336.49" - wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1337.5-1337.51" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1338.5-1338.51" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1339.5-1339.52" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1340.11-1340.58" - wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1341.11-1341.58" - wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1342.5-1342.53" - wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1333.6-1333.44" - wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1332.5-1332.43" - wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1317.6-1317.44" - wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1318.12-1318.51" - wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1316.6-1316.36" - wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1320.5-1320.42" - wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1321.5-1321.44" - wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1322.5-1322.45" - wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1323.11-1323.51" - wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1324.5-1324.46" - wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1319.6-1319.37" - wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1327.5-1327.32" - wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1328.5-1328.31" - wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1329.11-1329.45" - wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1326.5-1326.32" - wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1325.5-1325.32" - wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1343.5-1343.27" - wire \main_sdphy_dataw_start - attribute \src "ls180.v:1330.5-1330.26" - wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1344.5-1344.27" - wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1224.11-1224.32" - wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1898.11-1898.59" - wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1899.5-1899.56" - wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1212.6-1212.34" - wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1211.6-1211.35" - wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1214.5-1214.33" - wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1213.6-1213.35" - wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1216.6-1216.43" - wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1217.12-1217.50" - wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1215.6-1215.35" - wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1219.5-1219.41" - wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1220.5-1220.43" - wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1221.5-1221.44" - wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1222.11-1222.50" - wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1223.5-1223.45" - wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1218.6-1218.36" - wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1472.6-1472.27" - wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1473.5-1473.28" - wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1474.6-1474.29" - wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1475.6-1475.30" - wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1476.11-1476.35" - wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1477.12-1477.36" - wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1478.6-1478.31" - wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1201.6-1201.23" - wire \main_sdphy_status - attribute \src "ls180.v:1202.6-1202.19" - wire \main_sdphy_we - attribute \src "ls180.v:418.5-418.26" - wire \main_sdram_address_re - attribute \src "ls180.v:417.12-417.38" - wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:420.5-420.27" - wire \main_sdram_baddress_re - attribute \src "ls180.v:419.11-419.38" - wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:516.5-516.43" - wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:538.11-538.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:543.6-543.58" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:548.6-548.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:549.6-549.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:547.13-547.78" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:546.6-546.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:552.6-552.65" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:553.6-553.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:551.13-551.79" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:550.6-550.70" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:535.11-535.61" - wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:537.11-537.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:544.12-544.67" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:545.13-545.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:536.5-536.57" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:519.5-519.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:520.5-520.59" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:522.13-522.75" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:521.6-521.66" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:518.6-518.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:517.6-517.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:525.6-525.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:526.6-526.62" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:528.13-528.77" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:527.6-527.68" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:524.6-524.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:523.6-523.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:533.13-533.71" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:534.13-534.72" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:531.6-531.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:532.6-532.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:529.6-529.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:530.6-530.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:539.11-539.66" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:540.13-540.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:542.13-542.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:541.6-541.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:556.6-556.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:557.6-557.50" - wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:559.13-559.65" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:558.6-558.56" - wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:555.6-555.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:554.6-554.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:562.5-562.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:563.5-563.51" - wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:565.12-565.66" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:564.5-564.57" - wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:561.6-561.53" - wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:560.5-560.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:508.12-508.49" - wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:509.12-509.50" - wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:510.5-510.44" - wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:513.5-513.47" - wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:514.5-514.48" - wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:515.5-515.49" - wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:511.5-511.44" - wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:512.5-512.43" - wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:507.5-507.38" - wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:506.5-506.38" - wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:505.5-505.40" - wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:504.6-504.41" - wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:500.13-500.45" - wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:501.6-501.38" - wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:503.5-503.44" - wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:498.6-498.39" - wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:497.6-497.39" - wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:502.5-502.44" - wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:499.6-499.36" - wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:566.12-566.39" - wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:570.5-570.38" - wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:571.5-571.47" - wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:568.6-568.37" - wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:569.5-569.37" - wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:567.5-567.39" - wire \main_sdram_bankmachine0_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:578.32-578.69" - wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:577.6-577.43" - wire \main_sdram_bankmachine0_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:576.32-576.68" - wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:575.6-575.42" - wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:574.11-574.48" - wire width 3 \main_sdram_bankmachine0_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:573.32-573.69" - wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:572.6-572.43" - wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:598.5-598.43" - wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:620.11-620.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:625.6-625.58" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:630.6-630.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:631.6-631.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:629.13-629.78" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:628.6-628.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:634.6-634.65" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:635.6-635.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:633.13-633.79" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:632.6-632.70" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:617.11-617.61" - wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:619.11-619.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:626.12-626.67" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:627.13-627.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:618.5-618.57" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:601.5-601.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:602.5-602.59" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:604.13-604.75" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:603.6-603.66" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:600.6-600.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:599.6-599.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:607.6-607.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:608.6-608.62" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:610.13-610.77" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:609.6-609.68" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:606.6-606.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:605.6-605.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:615.13-615.71" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:616.13-616.72" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:613.6-613.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:614.6-614.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:611.6-611.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:612.6-612.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:621.11-621.66" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:622.13-622.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:624.13-624.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:623.6-623.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:638.6-638.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:639.6-639.50" - wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:641.13-641.65" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:640.6-640.56" - wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:637.6-637.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:636.6-636.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:644.5-644.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:645.5-645.51" - wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:647.12-647.66" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:646.5-646.57" - wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:643.6-643.53" - wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:642.5-642.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:590.12-590.49" - wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:591.12-591.50" - wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:592.5-592.44" - wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:595.5-595.47" - wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:596.5-596.48" - wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:597.5-597.49" - wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:593.5-593.44" - wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:594.5-594.43" - wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:589.5-589.38" - wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:588.5-588.38" - wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:587.5-587.40" - wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:586.6-586.41" - wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:582.13-582.45" - wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:583.6-583.38" - wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:585.5-585.44" - wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:580.6-580.39" - wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:579.6-579.39" - wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:584.5-584.44" - wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:581.6-581.36" - wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:648.12-648.39" - wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:652.5-652.38" - wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:653.5-653.47" - wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:650.6-650.37" - wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:651.5-651.37" - wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:649.5-649.39" - wire \main_sdram_bankmachine1_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:660.32-660.69" - wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:659.6-659.43" - wire \main_sdram_bankmachine1_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:658.32-658.68" - wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:657.6-657.42" - wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:656.11-656.48" - wire width 3 \main_sdram_bankmachine1_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:655.32-655.69" - wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:654.6-654.43" - wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:680.5-680.43" - wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:702.11-702.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:707.6-707.58" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:712.6-712.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:713.6-713.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:711.13-711.78" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:710.6-710.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:716.6-716.65" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:717.6-717.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:715.13-715.79" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:714.6-714.70" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:699.11-699.61" - wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:701.11-701.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:708.12-708.67" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:709.13-709.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:700.5-700.57" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:683.5-683.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:684.5-684.59" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:686.13-686.75" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:685.6-685.66" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:682.6-682.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:681.6-681.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:689.6-689.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:690.6-690.62" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:692.13-692.77" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:691.6-691.68" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:688.6-688.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:687.6-687.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:697.13-697.71" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:698.13-698.72" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:695.6-695.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:696.6-696.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:693.6-693.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:694.6-694.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:703.11-703.66" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:704.13-704.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:706.13-706.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:705.6-705.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:720.6-720.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:721.6-721.50" - wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:723.13-723.65" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:722.6-722.56" - wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:719.6-719.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:718.6-718.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:726.5-726.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:727.5-727.51" - wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:729.12-729.66" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:728.5-728.57" - wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:725.6-725.53" - wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:724.5-724.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:672.12-672.49" - wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:673.12-673.50" - wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:674.5-674.44" - wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:677.5-677.47" - wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:678.5-678.48" - wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:679.5-679.49" - wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:675.5-675.44" - wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:676.5-676.43" - wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:671.5-671.38" - wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:670.5-670.38" - wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:669.5-669.40" - wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:668.6-668.41" - wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:664.13-664.45" - wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:665.6-665.38" - wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:667.5-667.44" - wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:662.6-662.39" - wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:661.6-661.39" - wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:666.5-666.44" - wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:663.6-663.36" - wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:730.12-730.39" - wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:734.5-734.38" - wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:735.5-735.47" - wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:732.6-732.37" - wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:733.5-733.37" - wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:731.5-731.39" - wire \main_sdram_bankmachine2_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:742.32-742.69" - wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:741.6-741.43" - wire \main_sdram_bankmachine2_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:740.32-740.68" - wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:739.6-739.42" - wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:738.11-738.48" - wire width 3 \main_sdram_bankmachine2_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:737.32-737.69" - wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:736.6-736.43" - wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:762.5-762.43" - wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:784.11-784.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:789.6-789.58" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:794.6-794.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:795.6-795.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:793.13-793.78" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:792.6-792.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:798.6-798.65" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:799.6-799.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:797.13-797.79" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:796.6-796.70" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:781.11-781.61" - wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:783.11-783.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:790.12-790.67" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:791.13-791.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:782.5-782.57" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:765.5-765.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:766.5-766.59" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:768.13-768.75" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:767.6-767.66" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:764.6-764.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:763.6-763.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:771.6-771.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:772.6-772.62" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:774.13-774.77" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:773.6-773.68" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:770.6-770.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:769.6-769.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:779.13-779.71" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:780.13-780.72" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:777.6-777.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:778.6-778.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:775.6-775.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:776.6-776.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:785.11-785.66" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:786.13-786.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:788.13-788.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:787.6-787.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:802.6-802.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:803.6-803.50" - wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:805.13-805.65" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:804.6-804.56" - wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:801.6-801.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:800.6-800.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:808.5-808.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:809.5-809.51" - wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:811.12-811.66" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:810.5-810.57" - wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:807.6-807.53" - wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:806.5-806.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:754.12-754.49" - wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:755.12-755.50" - wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:756.5-756.44" - wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:759.5-759.47" - wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:760.5-760.48" - wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:761.5-761.49" - wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:757.5-757.44" - wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:758.5-758.43" - wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:753.5-753.38" - wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:752.5-752.38" - wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:751.5-751.40" - wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:750.6-750.41" - wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:746.13-746.45" - wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:747.6-747.38" - wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:749.5-749.44" - wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:744.6-744.39" - wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:743.6-743.39" - wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:748.5-748.44" - wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:745.6-745.36" - wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:812.12-812.39" - wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:816.5-816.38" - wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:817.5-817.47" - wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:814.6-814.37" - wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:815.5-815.37" - wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:813.5-813.39" - wire \main_sdram_bankmachine3_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:824.32-824.69" - wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:823.6-823.43" - wire \main_sdram_bankmachine3_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:822.32-822.68" - wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:821.6-821.42" - wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:820.11-820.48" - wire width 3 \main_sdram_bankmachine3_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:819.32-819.69" - wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:818.6-818.43" - wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:826.6-826.28" - wire \main_sdram_cas_allowed - attribute \src "ls180.v:844.6-844.30" - wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:833.13-833.48" - wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:834.12-834.48" - wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:835.5-835.42" - wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:838.6-838.46" - wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:839.6-839.47" - wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:840.6-840.48" - wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:836.5-836.42" - wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:837.5-837.41" - wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:832.5-832.36" - wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:831.6-831.37" - wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:843.11-843.38" - wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:842.12-842.41" - wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:841.11-841.39" - wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:830.5-830.41" - wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:829.5-829.36" - wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:827.5-827.37" - wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:828.5-828.38" - wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:862.6-862.30" - wire \main_sdram_choose_req_ce - attribute \src "ls180.v:851.13-851.48" - wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:852.12-852.48" - wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:853.5-853.42" - wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:856.6-856.46" - wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:857.6-857.47" - wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:858.6-858.48" - wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:854.5-854.42" - wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:855.5-855.41" - wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:850.5-850.36" - wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:849.6-849.37" - wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:861.11-861.38" - wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:860.12-860.41" - wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:859.11-859.39" - wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:848.5-848.41" - wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:847.6-847.37" - wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:845.5-845.37" - wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:846.5-846.38" - wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:406.6-406.20" - wire \main_sdram_cke - attribute \src "ls180.v:474.5-474.24" - wire \main_sdram_cmd_last - attribute \src "ls180.v:475.12-475.36" - wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:476.11-476.36" - wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:477.5-477.31" - wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:480.5-480.35" - wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:481.5-481.36" - wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:478.5-478.31" - wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:479.5-479.30" - wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:473.5-473.25" - wire \main_sdram_cmd_ready - attribute \src "ls180.v:472.5-472.25" - wire \main_sdram_cmd_valid - attribute \src "ls180.v:414.6-414.32" - wire \main_sdram_command_issue_r - attribute \src "ls180.v:413.6-413.33" - wire \main_sdram_command_issue_re - attribute \src "ls180.v:416.5-416.31" - wire \main_sdram_command_issue_w - attribute \src "ls180.v:415.6-415.33" - wire \main_sdram_command_issue_we - attribute \src "ls180.v:412.5-412.26" - wire \main_sdram_command_re - attribute \src "ls180.v:411.11-411.37" - wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:465.5-465.28" - wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:456.12-456.37" - wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:457.11-457.33" - wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:458.5-458.28" - wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:462.6-462.27" - wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:459.5-459.27" - wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:463.6-463.27" - wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:460.5-460.28" - wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:470.13-470.37" - wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:469.5-469.32" - wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:471.6-471.36" - wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:464.6-464.31" - wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:461.5-461.27" - wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:466.13-466.37" - wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:467.5-467.32" - wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:468.12-468.41" - wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:880.5-880.19" - wire \main_sdram_en0 - attribute \src "ls180.v:883.5-883.19" - wire \main_sdram_en1 - attribute \src "ls180.v:886.6-886.30" - wire \main_sdram_go_to_refresh - attribute \src "ls180.v:428.13-428.44" - wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:429.6-429.37" - wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:431.6-431.44" - wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:426.6-426.38" - wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:425.6-425.38" - wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:430.6-430.44" - wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:427.6-427.35" - wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:435.13-435.44" - wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:436.6-436.37" - wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:438.6-438.44" - wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:433.6-433.38" - wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:432.6-432.38" - wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:437.6-437.44" - wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:434.6-434.35" - wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:442.13-442.44" - wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:443.6-443.37" - wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:445.6-445.44" - wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:440.6-440.38" - wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:439.6-439.38" - wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:444.6-444.44" - wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:441.6-441.35" - wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:449.13-449.44" - wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:450.6-450.37" - wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:452.6-452.44" - wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:447.6-447.38" - wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:446.6-446.38" - wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:451.6-451.44" - wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:448.6-448.35" - wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:455.13-455.39" - wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:453.12-453.38" - wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:454.11-454.40" - wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:366.5-366.29" - wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:357.13-357.39" - wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:358.12-358.35" - wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:359.5-359.29" - wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:363.6-363.28" - wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:360.5-360.28" - wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:364.6-364.28" - wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:361.5-361.29" - wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:371.12-371.37" - wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:370.6-370.34" - wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:372.5-372.36" - wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:365.6-365.32" - wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:362.5-362.28" - wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:367.13-367.38" - wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:368.6-368.34" - wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:369.12-369.42" - wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:398.5-398.31" - wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:389.12-389.40" - wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:390.11-390.36" - wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:391.5-391.31" - wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:395.5-395.29" - wire \main_sdram_master_p0_cke - attribute \src "ls180.v:392.5-392.30" - wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:396.5-396.29" - wire \main_sdram_master_p0_odt - attribute \src "ls180.v:393.5-393.31" - wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:403.13-403.40" - wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:402.5-402.35" - wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:404.6-404.39" - wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:397.5-397.33" - wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:394.5-394.30" - wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:399.12-399.39" - wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:400.5-400.35" - wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:401.11-401.43" - wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:881.6-881.26" - wire \main_sdram_max_time0 - attribute \src "ls180.v:884.6-884.26" - wire \main_sdram_max_time1 - attribute \src "ls180.v:863.12-863.28" - wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:864.11-864.28" - wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:407.6-407.20" - wire \main_sdram_odt - attribute \src "ls180.v:490.5-490.31" - wire \main_sdram_postponer_count - attribute \src "ls180.v:488.6-488.32" - wire \main_sdram_postponer_req_i - attribute \src "ls180.v:489.5-489.31" - wire \main_sdram_postponer_req_o - attribute \src "ls180.v:825.6-825.28" - wire \main_sdram_ras_allowed - attribute \src "ls180.v:410.5-410.18" - wire \main_sdram_re - attribute \src "ls180.v:878.6-878.31" - wire \main_sdram_read_available - attribute \src "ls180.v:408.6-408.24" - wire \main_sdram_reset_n - attribute \src "ls180.v:405.6-405.20" - wire \main_sdram_sel - attribute \src "ls180.v:496.5-496.31" - wire \main_sdram_sequencer_count - attribute \src "ls180.v:495.11-495.39" - wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:492.6-492.32" - wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:494.5-494.31" - wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:491.5-491.32" - wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:493.6-493.33" - wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:382.6-382.31" - wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:373.13-373.40" - wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:374.12-374.36" - wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:375.6-375.31" - wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:379.6-379.29" - wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:376.6-376.30" - wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:380.6-380.29" - wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:377.6-377.31" - wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:387.12-387.38" - wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:386.6-386.35" - wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:388.5-388.37" - wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:381.6-381.33" - wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:378.6-378.30" - wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:383.13-383.39" - wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:384.6-384.35" - wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:385.12-385.43" - wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:423.12-423.29" - wire width 16 \main_sdram_status - attribute \src "ls180.v:866.5-866.24" - wire \main_sdram_steerer0 - attribute \src "ls180.v:867.5-867.24" - wire \main_sdram_steerer1 - attribute \src "ls180.v:865.11-865.33" - wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:409.11-409.29" - wire width 4 \main_sdram_storage - attribute \src "ls180.v:874.5-874.29" - wire \main_sdram_tccdcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:873.32-873.56" - wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:872.6-872.30" - wire \main_sdram_tccdcon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:871.32-871.56" - wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:870.6-870.30" - wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:882.11-882.27" - wire width 5 \main_sdram_time0 - attribute \src "ls180.v:885.11-885.27" - wire width 4 \main_sdram_time1 - attribute \src "ls180.v:485.12-485.35" - wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:487.11-487.34" - wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:484.6-484.28" - wire \main_sdram_timer_done0 - attribute \src "ls180.v:486.6-486.28" - wire \main_sdram_timer_done1 - attribute \src "ls180.v:483.6-483.27" - wire \main_sdram_timer_wait - attribute \no_retiming "true" - attribute \src "ls180.v:869.32-869.56" - wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:868.6-868.30" - wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:877.11-877.35" - wire width 3 \main_sdram_twtrcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:876.32-876.56" - wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:875.6-875.30" - wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:482.6-482.30" - wire \main_sdram_wants_refresh - attribute \src "ls180.v:424.6-424.19" - wire \main_sdram_we - attribute \src "ls180.v:422.5-422.25" - wire \main_sdram_wrdata_re - attribute \src "ls180.v:421.12-421.37" - wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:879.6-879.32" - wire \main_sdram_write_available - attribute \src "ls180.v:914.5-914.47" - wire \main_socbushandler_converted_interface_ack - attribute \src "ls180.v:908.13-908.55" - wire width 30 \main_socbushandler_converted_interface_adr - attribute \src "ls180.v:917.12-917.54" - wire width 2 \main_socbushandler_converted_interface_bte - attribute \src "ls180.v:916.12-916.54" - wire width 3 \main_socbushandler_converted_interface_cti - attribute \src "ls180.v:912.6-912.48" - wire \main_socbushandler_converted_interface_cyc - attribute \src "ls180.v:910.13-910.57" - wire width 64 \main_socbushandler_converted_interface_dat_r - attribute \src "ls180.v:909.13-909.57" - wire width 64 \main_socbushandler_converted_interface_dat_w - attribute \src "ls180.v:918.5-918.47" - wire \main_socbushandler_converted_interface_err - attribute \src "ls180.v:911.12-911.54" - wire width 8 \main_socbushandler_converted_interface_sel - attribute \src "ls180.v:913.6-913.48" - wire \main_socbushandler_converted_interface_stb - attribute \src "ls180.v:915.6-915.47" - wire \main_socbushandler_converted_interface_we - attribute \src "ls180.v:920.5-920.31" - wire \main_socbushandler_counter - attribute \src "ls180.v:1849.5-1849.53" - wire \main_socbushandler_counter_converter2_next_value - attribute \src "ls180.v:1850.5-1850.56" - wire \main_socbushandler_counter_converter2_next_value_ce - attribute \src "ls180.v:922.12-922.36" - wire width 64 \main_socbushandler_dat_r - attribute \src "ls180.v:921.6-921.30" - wire \main_socbushandler_reset - attribute \src "ls180.v:919.5-919.28" - wire \main_socbushandler_skip - attribute \src "ls180.v:1097.6-1097.27" - wire \main_spimaster0_start - attribute \src "ls180.v:1107.12-1107.35" - wire width 8 \main_spimaster10_length - attribute \src "ls180.v:1108.12-1108.36" - wire width 16 \main_spimaster11_storage - attribute \src "ls180.v:1109.5-1109.24" - wire \main_spimaster12_re - attribute \src "ls180.v:1110.6-1110.27" - wire \main_spimaster13_done - attribute \src "ls180.v:1111.6-1111.29" - wire \main_spimaster14_status - attribute \src "ls180.v:1112.6-1112.25" - wire \main_spimaster15_we - attribute \src "ls180.v:1113.11-1113.35" - wire width 8 \main_spimaster16_storage - attribute \src "ls180.v:1114.5-1114.24" - wire \main_spimaster17_re - attribute \src "ls180.v:1115.12-1115.35" - wire width 8 \main_spimaster18_status - attribute \src "ls180.v:1116.6-1116.25" - wire \main_spimaster19_we - attribute \src "ls180.v:1098.12-1098.34" - wire width 8 \main_spimaster1_length - attribute \src "ls180.v:1170.5-1170.23" - wire \main_spimaster1_re - attribute \src "ls180.v:1169.12-1169.35" - wire width 16 \main_spimaster1_storage - attribute \src "ls180.v:1117.6-1117.26" - wire \main_spimaster20_sel - attribute \src "ls180.v:1118.5-1118.29" - wire \main_spimaster21_storage - attribute \src "ls180.v:1119.5-1119.24" - wire \main_spimaster22_re - attribute \src "ls180.v:1120.5-1120.29" - wire \main_spimaster23_storage - attribute \src "ls180.v:1121.5-1121.24" - wire \main_spimaster24_re - attribute \src "ls180.v:1122.5-1122.32" - wire \main_spimaster25_clk_enable - attribute \src "ls180.v:1123.5-1123.31" - wire \main_spimaster26_cs_enable - attribute \src "ls180.v:1124.11-1124.33" - wire width 3 \main_spimaster27_count - attribute \src "ls180.v:1890.11-1890.55" - wire width 3 \main_spimaster27_count_spimaster0_next_value - attribute \src "ls180.v:1891.5-1891.52" - wire \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:1125.5-1125.32" - wire \main_spimaster28_mosi_latch - attribute \src "ls180.v:1126.5-1126.32" - wire \main_spimaster29_miso_latch - attribute \src "ls180.v:1099.5-1099.25" - wire \main_spimaster2_done - attribute \src "ls180.v:1127.12-1127.40" - wire width 16 \main_spimaster30_clk_divider - attribute \src "ls180.v:1128.6-1128.31" - wire \main_spimaster31_clk_rise - attribute \src "ls180.v:1129.6-1129.31" - wire \main_spimaster32_clk_fall - attribute \src "ls180.v:1130.11-1130.37" - wire width 8 \main_spimaster33_mosi_data - attribute \src "ls180.v:1131.11-1131.36" - wire width 3 \main_spimaster34_mosi_sel - attribute \src "ls180.v:1132.11-1132.37" - wire width 8 \main_spimaster35_miso_data - attribute \src "ls180.v:1100.5-1100.24" - wire \main_spimaster3_irq - attribute \src "ls180.v:1101.12-1101.32" - wire width 8 \main_spimaster4_mosi - attribute \src "ls180.v:1102.11-1102.31" - wire width 8 \main_spimaster5_miso - attribute \src "ls180.v:1103.6-1103.24" - wire \main_spimaster6_cs - attribute \src "ls180.v:1104.6-1104.30" - wire \main_spimaster7_loopback - attribute \src "ls180.v:1105.12-1105.39" - wire width 16 \main_spimaster8_clk_divider - attribute \src "ls180.v:1106.5-1106.26" - wire \main_spimaster9_start - attribute \src "ls180.v:1141.13-1141.40" - wire width 16 \main_spisdcard_clk_divider0 - attribute \src "ls180.v:1163.12-1163.39" - wire width 16 \main_spisdcard_clk_divider1 - attribute \src "ls180.v:1158.5-1158.30" - wire \main_spisdcard_clk_enable - attribute \src "ls180.v:1165.6-1165.29" - wire \main_spisdcard_clk_fall - attribute \src "ls180.v:1164.6-1164.29" - wire \main_spisdcard_clk_rise - attribute \src "ls180.v:1145.5-1145.30" - wire \main_spisdcard_control_re - attribute \src "ls180.v:1144.12-1144.42" - wire width 16 \main_spisdcard_control_storage - attribute \src "ls180.v:1160.11-1160.31" - wire width 3 \main_spisdcard_count - attribute \src "ls180.v:1894.11-1894.53" - wire width 3 \main_spisdcard_count_spimaster1_next_value - attribute \src "ls180.v:1895.5-1895.50" - wire \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:1139.6-1139.23" - wire \main_spisdcard_cs - attribute \src "ls180.v:1159.5-1159.29" - wire \main_spisdcard_cs_enable - attribute \src "ls180.v:1155.5-1155.25" - wire \main_spisdcard_cs_re - attribute \src "ls180.v:1154.5-1154.30" - wire \main_spisdcard_cs_storage - attribute \src "ls180.v:1135.5-1135.25" - wire \main_spisdcard_done0 - attribute \src "ls180.v:1146.6-1146.26" - wire \main_spisdcard_done1 - attribute \src "ls180.v:1136.5-1136.23" - wire \main_spisdcard_irq - attribute \src "ls180.v:1134.12-1134.34" - wire width 8 \main_spisdcard_length0 - attribute \src "ls180.v:1143.12-1143.34" - wire width 8 \main_spisdcard_length1 - attribute \src "ls180.v:1140.6-1140.29" - wire \main_spisdcard_loopback - attribute \src "ls180.v:1157.5-1157.31" - wire \main_spisdcard_loopback_re - attribute \src "ls180.v:1156.5-1156.36" - wire \main_spisdcard_loopback_storage - attribute \src "ls180.v:1138.11-1138.30" - wire width 8 \main_spisdcard_miso - attribute \src "ls180.v:1168.11-1168.35" - wire width 8 \main_spisdcard_miso_data - attribute \src "ls180.v:1162.5-1162.30" - wire \main_spisdcard_miso_latch - attribute \src "ls180.v:1151.12-1151.38" - wire width 8 \main_spisdcard_miso_status - attribute \src "ls180.v:1152.6-1152.28" - wire \main_spisdcard_miso_we - attribute \src "ls180.v:1137.12-1137.31" - wire width 8 \main_spisdcard_mosi - attribute \src "ls180.v:1166.11-1166.35" - wire width 8 \main_spisdcard_mosi_data - attribute \src "ls180.v:1161.5-1161.30" - wire \main_spisdcard_mosi_latch - attribute \src "ls180.v:1150.5-1150.27" - wire \main_spisdcard_mosi_re - attribute \src "ls180.v:1167.11-1167.34" - wire width 3 \main_spisdcard_mosi_sel - attribute \src "ls180.v:1149.11-1149.38" - wire width 8 \main_spisdcard_mosi_storage - attribute \src "ls180.v:1153.6-1153.24" - wire \main_spisdcard_sel - attribute \src "ls180.v:1133.6-1133.27" - wire \main_spisdcard_start0 - attribute \src "ls180.v:1142.5-1142.26" - wire \main_spisdcard_start1 - attribute \src "ls180.v:1147.6-1147.34" - wire \main_spisdcard_status_status - attribute \src "ls180.v:1148.6-1148.30" - wire \main_spisdcard_status_we - attribute \src "ls180.v:257.12-257.26" - wire width 6 \main_sram0_adr - attribute \src "ls180.v:258.13-258.29" - wire width 64 \main_sram0_dat_r - attribute \src "ls180.v:260.13-260.29" - wire width 64 \main_sram0_dat_w - attribute \src "ls180.v:259.11-259.24" - wire width 8 \main_sram0_we - attribute \src "ls180.v:272.12-272.26" - wire width 6 \main_sram1_adr - attribute \src "ls180.v:273.13-273.29" - wire width 64 \main_sram1_dat_r - attribute \src "ls180.v:275.13-275.29" - wire width 64 \main_sram1_dat_w - attribute \src "ls180.v:274.11-274.24" - wire width 8 \main_sram1_we - attribute \src "ls180.v:287.12-287.26" - wire width 6 \main_sram2_adr - attribute \src "ls180.v:288.13-288.29" - wire width 64 \main_sram2_dat_r - attribute \src "ls180.v:290.13-290.29" - wire width 64 \main_sram2_dat_w - attribute \src "ls180.v:289.11-289.24" - wire width 8 \main_sram2_we - attribute \src "ls180.v:302.12-302.26" - wire width 6 \main_sram3_adr - attribute \src "ls180.v:303.13-303.29" - wire width 64 \main_sram3_dat_r - attribute \src "ls180.v:305.13-305.29" - wire width 64 \main_sram3_dat_w - attribute \src "ls180.v:304.11-304.24" - wire width 8 \main_sram3_we - attribute \src "ls180.v:988.12-988.44" - wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:987.6-987.39" - wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:990.11-990.43" - wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:989.6-989.39" - wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:992.5-992.30" - wire \main_uart_eventmanager_re - attribute \src "ls180.v:984.12-984.43" - wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:983.6-983.38" - wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:986.11-986.42" - wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:985.6-985.38" - wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:991.11-991.41" - wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:972.6-972.19" - wire \main_uart_irq - attribute \src "ls180.v:958.12-958.46" - wire width 32 \main_uart_phy_phase_accumulator_rx - attribute \src "ls180.v:948.12-948.46" - wire width 32 \main_uart_phy_phase_accumulator_tx - attribute \src "ls180.v:941.5-941.21" - wire \main_uart_phy_re - attribute \src "ls180.v:959.6-959.22" - wire \main_uart_phy_rx - attribute \src "ls180.v:962.11-962.36" - wire width 4 \main_uart_phy_rx_bitcount - attribute \src "ls180.v:963.5-963.26" - wire \main_uart_phy_rx_busy - attribute \src "ls180.v:960.5-960.23" - wire \main_uart_phy_rx_r - attribute \src "ls180.v:961.11-961.31" - wire width 8 \main_uart_phy_rx_reg - attribute \src "ls180.v:944.6-944.30" - wire \main_uart_phy_sink_first - attribute \src "ls180.v:945.6-945.29" - wire \main_uart_phy_sink_last - attribute \src "ls180.v:946.12-946.43" - wire width 8 \main_uart_phy_sink_payload_data - attribute \src "ls180.v:943.5-943.29" - wire \main_uart_phy_sink_ready - attribute \src "ls180.v:942.6-942.30" - wire \main_uart_phy_sink_valid - attribute \src "ls180.v:954.5-954.31" - wire \main_uart_phy_source_first - attribute \src "ls180.v:955.5-955.30" - wire \main_uart_phy_source_last - attribute \src "ls180.v:956.11-956.44" - wire width 8 \main_uart_phy_source_payload_data - attribute \src "ls180.v:953.6-953.32" - wire \main_uart_phy_source_ready - attribute \src "ls180.v:952.5-952.31" - wire \main_uart_phy_source_valid - attribute \src "ls180.v:940.12-940.33" - wire width 32 \main_uart_phy_storage - attribute \src "ls180.v:950.11-950.36" - wire width 4 \main_uart_phy_tx_bitcount - attribute \src "ls180.v:951.5-951.26" - wire \main_uart_phy_tx_busy - attribute \src "ls180.v:949.11-949.31" - wire width 8 \main_uart_phy_tx_reg - attribute \src "ls180.v:957.5-957.32" - wire \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:947.5-947.32" - wire \main_uart_phy_uart_clk_txen - attribute \src "ls180.v:1081.5-1081.20" - wire \main_uart_reset - attribute \src "ls180.v:981.5-981.23" - wire \main_uart_rx_clear - attribute \src "ls180.v:1065.11-1065.36" - wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:1070.6-1070.31" - wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:1076.6-1076.37" - wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:1077.6-1077.36" - wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:1075.12-1075.50" - wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:1079.6-1079.38" - wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:1080.6-1080.37" - wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:1078.12-1078.51" - wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:1062.11-1062.35" - wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:1074.12-1074.36" - wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:1064.11-1064.36" - wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:1071.12-1071.40" - wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:1072.12-1072.42" - wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:1073.6-1073.33" - wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:1054.6-1054.26" - wire \main_uart_rx_fifo_re - attribute \src "ls180.v:1055.5-1055.31" - wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:1063.5-1063.30" - wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:1046.6-1046.34" - wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:1047.6-1047.33" - wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:1048.12-1048.47" - wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:1045.6-1045.34" - wire \main_uart_rx_fifo_sink_ready - attribute \src "ls180.v:1044.6-1044.34" - wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:1051.6-1051.36" - wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:1052.6-1052.35" - wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:1053.12-1053.49" - wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:1050.6-1050.36" - wire \main_uart_rx_fifo_source_ready - attribute \src "ls180.v:1049.6-1049.36" - wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:1060.12-1060.42" - wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:1061.12-1061.43" - wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:1058.6-1058.35" - wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:1059.6-1059.41" - wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:1056.6-1056.35" - wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:1057.6-1057.41" - wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:1066.11-1066.39" - wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:1067.12-1067.42" - wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:1069.12-1069.42" - wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:1068.6-1068.33" - wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:982.5-982.29" - wire \main_uart_rx_old_trigger - attribute \src "ls180.v:979.5-979.25" - wire \main_uart_rx_pending - attribute \src "ls180.v:978.6-978.25" - wire \main_uart_rx_status - attribute \src "ls180.v:980.6-980.26" - wire \main_uart_rx_trigger - attribute \src "ls180.v:970.6-970.30" - wire \main_uart_rxempty_status - attribute \src "ls180.v:971.6-971.26" - wire \main_uart_rxempty_we - attribute \src "ls180.v:995.6-995.29" - wire \main_uart_rxfull_status - attribute \src "ls180.v:996.6-996.25" - wire \main_uart_rxfull_we - attribute \src "ls180.v:965.12-965.28" - wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:964.6-964.23" - wire \main_uart_rxtx_re - attribute \src "ls180.v:967.12-967.28" - wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:966.6-966.23" - wire \main_uart_rxtx_we - attribute \src "ls180.v:976.5-976.23" - wire \main_uart_tx_clear - attribute \src "ls180.v:1028.11-1028.36" - wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:1033.6-1033.31" - wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:1039.6-1039.37" - wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:1040.6-1040.36" - wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:1038.12-1038.50" - wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:1042.6-1042.38" - wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:1043.6-1043.37" - wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:1041.12-1041.51" - wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:1025.11-1025.35" - wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:1037.12-1037.36" - wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:1027.11-1027.36" - wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:1034.12-1034.40" - wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:1035.12-1035.42" - wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:1036.6-1036.33" - wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:1017.6-1017.26" - wire \main_uart_tx_fifo_re - attribute \src "ls180.v:1018.5-1018.31" - wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:1026.5-1026.30" - wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:1009.5-1009.33" - wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:1010.5-1010.32" - wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:1011.12-1011.47" - wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:1008.6-1008.34" - wire \main_uart_tx_fifo_sink_ready - attribute \src "ls180.v:1007.6-1007.34" - wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:1014.6-1014.36" - wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:1015.6-1015.35" - wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:1016.12-1016.49" - wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:1013.6-1013.36" - wire \main_uart_tx_fifo_source_ready - attribute \src "ls180.v:1012.6-1012.36" - wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:1023.12-1023.42" - wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:1024.12-1024.43" - wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:1021.6-1021.35" - wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:1022.6-1022.41" - wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:1019.6-1019.35" - wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:1020.6-1020.41" - wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:1029.11-1029.39" - wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:1030.12-1030.42" - wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:1032.12-1032.42" - wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:1031.6-1031.33" - wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:977.5-977.29" - wire \main_uart_tx_old_trigger - attribute \src "ls180.v:974.5-974.25" - wire \main_uart_tx_pending - attribute \src "ls180.v:973.6-973.25" - wire \main_uart_tx_status - attribute \src "ls180.v:975.6-975.26" - wire \main_uart_tx_trigger - attribute \src "ls180.v:993.6-993.30" - wire \main_uart_txempty_status - attribute \src "ls180.v:994.6-994.26" - wire \main_uart_txempty_we - attribute \src "ls180.v:968.6-968.29" - wire \main_uart_txfull_status - attribute \src "ls180.v:969.6-969.25" - wire \main_uart_txfull_we - attribute \src "ls180.v:999.6-999.31" - wire \main_uart_uart_sink_first - attribute \src "ls180.v:1000.6-1000.30" - wire \main_uart_uart_sink_last - attribute \src "ls180.v:1001.12-1001.44" - wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:998.6-998.31" - wire \main_uart_uart_sink_ready - attribute \src "ls180.v:997.6-997.31" - wire \main_uart_uart_sink_valid - attribute \src "ls180.v:1004.6-1004.33" - wire \main_uart_uart_source_first - attribute \src "ls180.v:1005.6-1005.32" - wire \main_uart_uart_source_last - attribute \src "ls180.v:1006.12-1006.46" - wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:1003.6-1003.33" - wire \main_uart_uart_source_ready - attribute \src "ls180.v:1002.6-1002.33" - wire \main_uart_uart_source_valid - attribute \src "ls180.v:906.5-906.22" - wire \main_wb_sdram_ack - attribute \src "ls180.v:900.12-900.29" - wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:904.5-904.22" - wire \main_wb_sdram_cyc - attribute \src "ls180.v:902.13-902.32" - wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:901.12-901.31" - wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:903.11-903.28" - wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:905.5-905.22" - wire \main_wb_sdram_stb - attribute \src "ls180.v:907.5-907.21" - wire \main_wb_sdram_we - attribute \src "ls180.v:936.5-936.24" - wire \main_wdata_consumed - attribute \src "ls180.v:10349.11-10349.17" - wire width 6 \memadr - attribute \src "ls180.v:10377.11-10377.19" - wire width 6 \memadr_1 - attribute \src "ls180.v:10405.11-10405.19" - wire width 6 \memadr_2 - attribute \src "ls180.v:10433.11-10433.19" - wire width 6 \memadr_3 - attribute \src "ls180.v:10461.11-10461.19" - wire width 6 \memadr_4 - attribute \src "ls180.v:10489.12-10489.18" - wire width 25 \memdat - attribute \src "ls180.v:10503.12-10503.20" - wire width 25 \memdat_1 - attribute \src "ls180.v:10517.12-10517.20" - wire width 25 \memdat_2 - attribute \src "ls180.v:10531.12-10531.20" - wire width 25 \memdat_3 - attribute \src "ls180.v:10545.11-10545.19" - wire width 10 \memdat_4 - attribute \src "ls180.v:10546.11-10546.19" - wire width 10 \memdat_5 - attribute \src "ls180.v:10562.11-10562.19" - wire width 10 \memdat_6 - attribute \src "ls180.v:10563.11-10563.19" - wire width 10 \memdat_7 - attribute \src "ls180.v:10579.11-10579.19" - wire width 10 \memdat_8 - attribute \src "ls180.v:10593.11-10593.19" - wire width 10 \memdat_9 - attribute \src "ls180.v:52.20-52.22" - wire width 24 input 48 \nc - attribute \src "ls180.v:338.6-338.13" - wire \por_clk - attribute \src "ls180.v:18.19-18.22" - wire width 2 output 14 \pwm - attribute \src "ls180.v:184.12-184.17" - wire width 2 \pwm_1 - attribute \src "ls180.v:23.13-23.23" - wire output 19 \sdcard_clk - attribute \src "ls180.v:24.13-24.25" - wire input 20 \sdcard_cmd_i - attribute \src "ls180.v:25.13-25.25" - wire output 21 \sdcard_cmd_o - attribute \src "ls180.v:26.13-26.26" - wire output 22 \sdcard_cmd_oe - attribute \src "ls180.v:27.19-27.32" - wire width 4 input 23 \sdcard_data_i - attribute \src "ls180.v:28.19-28.32" - wire width 4 output 24 \sdcard_data_o - attribute \src "ls180.v:29.13-29.27" - wire output 25 \sdcard_data_oe - attribute \src "ls180.v:6.20-6.27" - wire width 13 output 2 \sdram_a - attribute \src "ls180.v:15.19-15.27" - wire width 2 output 11 \sdram_ba - attribute \src "ls180.v:12.13-12.24" - wire output 8 \sdram_cas_n - attribute \src "ls180.v:14.13-14.22" - wire output 10 \sdram_cke - attribute \src "ls180.v:17.13-17.24" - wire output 13 \sdram_clock - attribute \src "ls180.v:183.6-183.19" - wire \sdram_clock_1 - attribute \src "ls180.v:13.13-13.23" - wire output 9 \sdram_cs_n - attribute \src "ls180.v:16.19-16.27" - wire width 2 output 12 \sdram_dm - attribute \src "ls180.v:7.20-7.30" - wire width 16 input 3 \sdram_dq_i - attribute \src "ls180.v:8.20-8.30" - wire width 16 output 4 \sdram_dq_o - attribute \src "ls180.v:9.13-9.24" - wire output 5 \sdram_dq_oe - attribute \src "ls180.v:11.13-11.24" - wire output 7 \sdram_ras_n - attribute \src "ls180.v:10.13-10.23" - wire output 6 \sdram_we_n - attribute \src "ls180.v:2760.6-2760.15" - wire \sdrio_clk - attribute \src "ls180.v:2761.6-2761.17" - wire \sdrio_clk_1 - attribute \src "ls180.v:2770.6-2770.18" - wire \sdrio_clk_10 - attribute \src "ls180.v:2771.6-2771.18" - wire \sdrio_clk_11 - attribute \src "ls180.v:2772.6-2772.18" - wire \sdrio_clk_12 - attribute \src "ls180.v:2773.6-2773.18" - wire \sdrio_clk_13 - attribute \src "ls180.v:2774.6-2774.18" - wire \sdrio_clk_14 - attribute \src "ls180.v:2775.6-2775.18" - wire \sdrio_clk_15 - attribute \src "ls180.v:2776.6-2776.18" - wire \sdrio_clk_16 - attribute \src "ls180.v:2777.6-2777.18" - wire \sdrio_clk_17 - attribute \src "ls180.v:2778.6-2778.18" - wire \sdrio_clk_18 - attribute \src "ls180.v:2779.6-2779.18" - wire \sdrio_clk_19 - attribute \src "ls180.v:2762.6-2762.17" - wire \sdrio_clk_2 - attribute \src "ls180.v:2780.6-2780.18" - wire \sdrio_clk_20 - attribute \src "ls180.v:2781.6-2781.18" - wire \sdrio_clk_21 - attribute \src "ls180.v:2782.6-2782.18" - wire \sdrio_clk_22 - attribute \src "ls180.v:2783.6-2783.18" - wire \sdrio_clk_23 - attribute \src "ls180.v:2784.6-2784.18" - wire \sdrio_clk_24 - attribute \src "ls180.v:2785.6-2785.18" - wire \sdrio_clk_25 - attribute \src "ls180.v:2786.6-2786.18" - wire \sdrio_clk_26 - attribute \src "ls180.v:2787.6-2787.18" - wire \sdrio_clk_27 - attribute \src "ls180.v:2788.6-2788.18" - wire \sdrio_clk_28 - attribute \src "ls180.v:2789.6-2789.18" - wire \sdrio_clk_29 - attribute \src "ls180.v:2763.6-2763.17" - wire \sdrio_clk_3 - attribute \src "ls180.v:2790.6-2790.18" - wire \sdrio_clk_30 - attribute \src "ls180.v:2791.6-2791.18" - wire \sdrio_clk_31 - attribute \src "ls180.v:2792.6-2792.18" - wire \sdrio_clk_32 - attribute \src "ls180.v:2793.6-2793.18" - wire \sdrio_clk_33 - attribute \src "ls180.v:2794.6-2794.18" - wire \sdrio_clk_34 - attribute \src "ls180.v:2795.6-2795.18" - wire \sdrio_clk_35 - attribute \src "ls180.v:2796.6-2796.18" - wire \sdrio_clk_36 - attribute \src "ls180.v:2797.6-2797.18" - wire \sdrio_clk_37 - attribute \src "ls180.v:2798.6-2798.18" - wire \sdrio_clk_38 - attribute \src "ls180.v:2799.6-2799.18" - wire \sdrio_clk_39 - attribute \src "ls180.v:2764.6-2764.17" - wire \sdrio_clk_4 - attribute \src "ls180.v:2800.6-2800.18" - wire \sdrio_clk_40 - attribute \src "ls180.v:2801.6-2801.18" - wire \sdrio_clk_41 - attribute \src "ls180.v:2802.6-2802.18" - wire \sdrio_clk_42 - attribute \src "ls180.v:2803.6-2803.18" - wire \sdrio_clk_43 - attribute \src "ls180.v:2804.6-2804.18" - wire \sdrio_clk_44 - attribute \src "ls180.v:2805.6-2805.18" - wire \sdrio_clk_45 - attribute \src "ls180.v:2806.6-2806.18" - wire \sdrio_clk_46 - attribute \src "ls180.v:2807.6-2807.18" - wire \sdrio_clk_47 - attribute \src "ls180.v:2808.6-2808.18" - wire \sdrio_clk_48 - attribute \src "ls180.v:2809.6-2809.18" - wire \sdrio_clk_49 - attribute \src "ls180.v:2765.6-2765.17" - wire \sdrio_clk_5 - attribute \src "ls180.v:2810.6-2810.18" - wire \sdrio_clk_50 - attribute \src "ls180.v:2811.6-2811.18" - wire \sdrio_clk_51 - attribute \src "ls180.v:2812.6-2812.18" - wire \sdrio_clk_52 - attribute \src "ls180.v:2813.6-2813.18" - wire \sdrio_clk_53 - attribute \src "ls180.v:2814.6-2814.18" - wire \sdrio_clk_54 - attribute \src "ls180.v:2815.6-2815.18" - wire \sdrio_clk_55 - attribute \src "ls180.v:2850.6-2850.18" - wire \sdrio_clk_56 - attribute \src "ls180.v:2851.6-2851.18" - wire \sdrio_clk_57 - attribute \src "ls180.v:2852.6-2852.18" - wire \sdrio_clk_58 - attribute \src "ls180.v:2853.6-2853.18" - wire \sdrio_clk_59 - attribute \src "ls180.v:2766.6-2766.17" - wire \sdrio_clk_6 - attribute \src "ls180.v:2854.6-2854.18" - wire \sdrio_clk_60 - attribute \src "ls180.v:2855.6-2855.18" - wire \sdrio_clk_61 - attribute \src "ls180.v:2856.6-2856.18" - wire \sdrio_clk_62 - attribute \src "ls180.v:2857.6-2857.18" - wire \sdrio_clk_63 - attribute \src "ls180.v:2858.6-2858.18" - wire \sdrio_clk_64 - attribute \src "ls180.v:2859.6-2859.18" - wire \sdrio_clk_65 - attribute \src "ls180.v:2860.6-2860.18" - wire \sdrio_clk_66 - attribute \src "ls180.v:2861.6-2861.18" - wire \sdrio_clk_67 - attribute \src "ls180.v:2862.6-2862.18" - wire \sdrio_clk_68 - attribute \src "ls180.v:2767.6-2767.17" - wire \sdrio_clk_7 - attribute \src "ls180.v:2768.6-2768.17" - wire \sdrio_clk_8 - attribute \src "ls180.v:2769.6-2769.17" - wire \sdrio_clk_9 - attribute \src "ls180.v:39.13-39.26" - wire output 35 \spimaster_clk - attribute \src "ls180.v:41.13-41.27" - wire output 37 \spimaster_cs_n - attribute \src "ls180.v:42.13-42.27" - wire input 38 \spimaster_miso - attribute \src "ls180.v:40.13-40.27" - wire output 36 \spimaster_mosi - attribute \src "ls180.v:19.13-19.26" - wire output 15 \spisdcard_clk - attribute \src "ls180.v:21.13-21.27" - wire output 17 \spisdcard_cs_n - attribute \src "ls180.v:22.13-22.27" - wire input 18 \spisdcard_miso - attribute \src "ls180.v:20.13-20.27" - wire output 16 \spisdcard_mosi - attribute \src "ls180.v:43.13-43.20" - wire input 39 \sys_clk - attribute \src "ls180.v:336.6-336.15" - wire \sys_clk_1 - attribute \src "ls180.v:45.19-45.31" - wire width 2 input 41 \sys_clksel_i - attribute \src "ls180.v:46.14-46.26" - wire output 42 \sys_pll_18_o - attribute \src "ls180.v:47.14-47.27" - wire output 43 \sys_pll_lck_o - attribute \src "ls180.v:44.13-44.20" - wire input 40 \sys_rst - attribute \src "ls180.v:337.6-337.15" - wire \sys_rst_1 - attribute \src "ls180.v:38.13-38.20" - wire input 34 \uart_rx - attribute \src "ls180.v:37.13-37.20" - wire output 33 \uart_tx - attribute \src "ls180.v:10348.12-10348.15" - memory width 64 size 64 \mem - attribute \src "ls180.v:10376.12-10376.17" - memory width 64 size 64 \mem_1 - attribute \src "ls180.v:10404.12-10404.17" - memory width 64 size 64 \mem_2 - attribute \src "ls180.v:10432.12-10432.17" - memory width 64 size 64 \mem_3 - attribute \src "ls180.v:10460.12-10460.17" - memory width 64 size 64 \mem_4 - attribute \src "ls180.v:10488.12-10488.19" - memory width 25 size 8 \storage - attribute \src "ls180.v:10502.12-10502.21" - memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10516.12-10516.21" - memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10530.12-10530.21" - memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10544.11-10544.20" - memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10561.11-10561.20" - memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10578.11-10578.20" - memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10592.11-10592.20" - memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2932.56-2932.86" - cell $add $add$ls180.v:2932$58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter0_counter - connect \B 1'1 - connect \Y $add$ls180.v:2932$58_Y - end - attribute \src "ls180.v:2992.56-2992.86" - cell $add $add$ls180.v:2992$69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter1_counter - connect \B 1'1 - connect \Y $add$ls180.v:2992$69_Y - end - attribute \src "ls180.v:3052.59-3052.92" - cell $add $add$ls180.v:3052$80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_counter - connect \B 1'1 - connect \Y $add$ls180.v:3052$80_Y - end - attribute \src "ls180.v:4245.54-4245.83" - cell $add $add$ls180.v:4245$685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_counter - connect \B 1'1 - connect \Y $add$ls180.v:4245$685_Y - end - attribute \src "ls180.v:4345.36-4345.89" - cell $add $add$ls180.v:4345$731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4345$731_Y - end - attribute \src "ls180.v:4375.36-4375.89" - cell $add $add$ls180.v:4375$742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4375$742_Y - end - attribute \src "ls180.v:4441.54-4441.83" - cell $add $add$ls180.v:4441$757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spimaster27_count - connect \B 1'1 - connect \Y $add$ls180.v:4441$757_Y - end - attribute \src "ls180.v:4500.52-4500.79" - cell $add $add$ls180.v:4500$765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spisdcard_count - connect \B 1'1 - connect \Y $add$ls180.v:4500$765_Y - end - attribute \src "ls180.v:4604.58-4604.86" - cell $add $add$ls180.v:4604$793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_init_count - connect \B 1'1 - connect \Y $add$ls180.v:4604$793_Y - end - attribute \src "ls180.v:4661.58-4661.86" - cell $add $add$ls180.v:4661$796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4661$796_Y - end - attribute \src "ls180.v:4678.58-4678.86" - cell $add $add$ls180.v:4678$798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4678$798_Y - end - attribute \src "ls180.v:4771.59-4771.87" - cell $add $add$ls180.v:4771$815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_count - connect \B 1'1 - connect \Y $add$ls180.v:4771$815_Y - end - attribute \src "ls180.v:4796.59-4796.87" - cell $add $add$ls180.v:4796$818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_count - connect \B 1'1 - connect \Y $add$ls180.v:4796$818_Y - end - attribute \src "ls180.v:4918.53-4918.82" - cell $add $add$ls180.v:4918$835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_dataw_count - connect \B 1'1 - connect \Y $add$ls180.v:4918$835_Y - end - attribute \src "ls180.v:5029.65-5029.114" - cell $add $add$ls180.v:5029$849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_sink_payload_block_length - connect \B 4'1000 - connect \Y $add$ls180.v:5029$849_Y - end - attribute \src "ls180.v:5034.62-5034.91" - cell $add $add$ls180.v:5034$852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_count - connect \B 1'1 - connect \Y $add$ls180.v:5034$852_Y - end - attribute \src "ls180.v:5060.61-5060.90" - cell $add $add$ls180.v:5060$855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_count - connect \B 1'1 - connect \Y $add$ls180.v:5060$855_Y - end - attribute \src "ls180.v:5264.80-5264.117" - cell $add $add$ls180.v:5264$1040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 1'1 - connect \Y $add$ls180.v:5264$1040_Y - end - attribute \src "ls180.v:5458.54-5458.82" - cell $add $add$ls180.v:5458$1115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdcore_cmd_count - connect \B 1'1 - connect \Y $add$ls180.v:5458$1115_Y - end - attribute \src "ls180.v:5510.55-5510.84" - cell $add $add$ls180.v:5510$1125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5510$1125_Y - end - attribute \src "ls180.v:5536.57-5536.86" - cell $add $add$ls180.v:5536$1133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5536$1133_Y - end - attribute \src "ls180.v:5657.51-5657.134" - cell $add $add$ls180.v:5657$1149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_base - connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5657$1149_Y - end - attribute \src "ls180.v:5660.77-5660.125" - cell $add $add$ls180.v:5660$1151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B 1'1 - connect \Y $add$ls180.v:5660$1151_Y - end - attribute \src "ls180.v:5753.50-5753.105" - cell $add $add$ls180.v:5753$1160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_base - connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5753$1160_Y - end - attribute \src "ls180.v:5755.77-5755.111" - cell $add $add$ls180.v:5755$1161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_offset - connect \B 1'1 - connect \Y $add$ls180.v:5755$1161_Y - end - attribute \src "ls180.v:7762.36-7762.70" - cell $add $add$ls180.v:7762$2602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_bus_errors - connect \B 1'1 - connect \Y $add$ls180.v:7762$2602_Y - end - attribute \src "ls180.v:7863.37-7863.72" - cell $add $add$ls180.v:7863$2635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_sequencer_counter - connect \B 1'1 - connect \Y $add$ls180.v:7863$2635_Y - end - attribute \src "ls180.v:7880.60-7880.119" - cell $add $add$ls180.v:7880$2639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7880$2639_Y - end - attribute \src "ls180.v:7883.60-7883.119" - cell $add $add$ls180.v:7883$2640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7883$2640_Y - end - attribute \src "ls180.v:7887.59-7887.116" - cell $add $add$ls180.v:7887$2645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7887$2645_Y - end - attribute \src "ls180.v:7926.60-7926.119" - cell $add $add$ls180.v:7926$2655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7926$2655_Y - end - attribute \src "ls180.v:7929.60-7929.119" - cell $add $add$ls180.v:7929$2656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7929$2656_Y - end - attribute \src "ls180.v:7933.59-7933.116" - cell $add $add$ls180.v:7933$2661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7933$2661_Y - end - attribute \src "ls180.v:7972.60-7972.119" - cell $add $add$ls180.v:7972$2671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7972$2671_Y - end - attribute \src "ls180.v:7975.60-7975.119" - cell $add $add$ls180.v:7975$2672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7975$2672_Y - end - attribute \src "ls180.v:7979.59-7979.116" - cell $add $add$ls180.v:7979$2677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7979$2677_Y - end - attribute \src "ls180.v:8018.60-8018.119" - cell $add $add$ls180.v:8018$2687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:8018$2687_Y - end - attribute \src "ls180.v:8021.60-8021.119" - cell $add $add$ls180.v:8021$2688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:8021$2688_Y - end - attribute \src "ls180.v:8025.59-8025.116" - cell $add $add$ls180.v:8025$2693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:8025$2693_Y - end - attribute \src "ls180.v:8255.34-8255.66" - cell $add $add$ls180.v:8255$2747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_phy_tx_bitcount - connect \B 1'1 - connect \Y $add$ls180.v:8255$2747_Y - end - attribute \src "ls180.v:8271.73-8271.131" - cell $add $add$ls180.v:8271$2750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 33 - connect \A \main_uart_phy_phase_accumulator_tx - connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8271$2750_Y - end - attribute \src "ls180.v:8284.34-8284.66" - cell $add $add$ls180.v:8284$2754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_phy_rx_bitcount - connect \B 1'1 - connect \Y $add$ls180.v:8284$2754_Y - end - attribute \src "ls180.v:8303.73-8303.131" - cell $add $add$ls180.v:8303$2757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 33 - connect \A \main_uart_phy_phase_accumulator_rx - connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8303$2757_Y - end - attribute \src "ls180.v:8329.33-8329.65" - cell $add $add$ls180.v:8329$2765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8329$2765_Y - end - attribute \src "ls180.v:8332.33-8332.65" - cell $add $add$ls180.v:8332$2766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8332$2766_Y - end - attribute \src "ls180.v:8336.33-8336.64" - cell $add $add$ls180.v:8336$2771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'1 - connect \Y $add$ls180.v:8336$2771_Y - end - attribute \src "ls180.v:8351.33-8351.65" - cell $add $add$ls180.v:8351$2776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8351$2776_Y - end - attribute \src "ls180.v:8354.33-8354.65" - cell $add $add$ls180.v:8354$2777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8354$2777_Y - end - attribute \src "ls180.v:8358.33-8358.64" - cell $add $add$ls180.v:8358$2782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'1 - connect \Y $add$ls180.v:8358$2782_Y - end - attribute \src "ls180.v:8379.35-8379.70" - cell $add $add$ls180.v:8379$2784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster30_clk_divider - connect \B 1'1 - connect \Y $add$ls180.v:8379$2784_Y - end - attribute \src "ls180.v:8414.34-8414.68" - cell $add $add$ls180.v:8414$2789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider1 - connect \B 1'1 - connect \Y $add$ls180.v:8414$2789_Y - end - attribute \src "ls180.v:8450.25-8450.49" - cell $add $add$ls180.v:8450$2794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm0_counter - connect \B 1'1 - connect \Y $add$ls180.v:8450$2794_Y - end - attribute \src "ls180.v:8464.25-8464.49" - cell $add $add$ls180.v:8464$2798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm1_counter - connect \B 1'1 - connect \Y $add$ls180.v:8464$2798_Y - end - attribute \src "ls180.v:8478.31-8478.61" - cell $add $add$ls180.v:8478$2803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 9 - connect \A \main_sdphy_clocker_clks - connect \B 1'1 - connect \Y $add$ls180.v:8478$2803_Y - end - attribute \src "ls180.v:8501.45-8501.88" - cell $add $add$ls180.v:8501$2807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8501$2807_Y - end - attribute \src "ls180.v:8547.71-8547.114" - cell $add $add$ls180.v:8547$2813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8547$2813_Y - end - attribute \src "ls180.v:8582.46-8582.90" - cell $add $add$ls180.v:8582$2819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8582$2819_Y - end - attribute \src "ls180.v:8628.72-8628.116" - cell $add $add$ls180.v:8628$2825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8628$2825_Y - end - attribute \src "ls180.v:8661.47-8661.92" - cell $add $add$ls180.v:8661$2831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8661$2831_Y - end - attribute \src "ls180.v:8689.73-8689.118" - cell $add $add$ls180.v:8689$2837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8689$2837_Y - end - attribute \src "ls180.v:8801.39-8801.75" - cell $add $add$ls180.v:8801$2850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 1'1 - connect \Y $add$ls180.v:8801$2850_Y - end - attribute \src "ls180.v:8862.37-8862.73" - cell $add $add$ls180.v:8862$2854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8862$2854_Y - end - attribute \src "ls180.v:8865.37-8865.73" - cell $add $add$ls180.v:8865$2855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8865$2855_Y - end - attribute \src "ls180.v:8869.36-8869.70" - cell $add $add$ls180.v:8869$2860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8869$2860_Y - end - attribute \src "ls180.v:8884.41-8884.80" - cell $add $add$ls180.v:8884$2864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8884$2864_Y - end - attribute \src "ls180.v:8930.67-8930.106" - cell $add $add$ls180.v:8930$2870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8930$2870_Y - end - attribute \src "ls180.v:8956.39-8956.76" - cell $add $add$ls180.v:8956$2872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdmem2block_converter_mux - connect \B 1'1 - connect \Y $add$ls180.v:8956$2872_Y - end - attribute \src "ls180.v:8960.37-8960.73" - cell $add $add$ls180.v:8960$2876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8960$2876_Y - end - attribute \src "ls180.v:8963.37-8963.73" - cell $add $add$ls180.v:8963$2877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8963$2877_Y - end - attribute \src "ls180.v:8967.36-8967.70" - cell $add $add$ls180.v:8967$2882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8967$2882_Y - end - attribute \src "ls180.v:2926.9-2926.90" - cell $and $and$ls180.v:2926$53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_converted_interface_stb - connect \B \main_interface0_converted_interface_cyc - connect \Y $and$ls180.v:2926$53_Y - end - attribute \src "ls180.v:2944.9-2944.90" - cell $and $and$ls180.v:2944$60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_converted_interface_stb - connect \B \main_interface0_converted_interface_cyc - connect \Y $and$ls180.v:2944$60_Y - end - attribute \src "ls180.v:2986.9-2986.90" - cell $and $and$ls180.v:2986$64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_converted_interface_stb - connect \B \main_interface1_converted_interface_cyc - connect \Y $and$ls180.v:2986$64_Y - end - attribute \src "ls180.v:3004.9-3004.90" - cell $and $and$ls180.v:3004$71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_converted_interface_stb - connect \B \main_interface1_converted_interface_cyc - connect \Y $and$ls180.v:3004$71_Y - end - attribute \src "ls180.v:3046.9-3046.96" - cell $and $and$ls180.v:3046$75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_converted_interface_stb - connect \B \main_socbushandler_converted_interface_cyc - connect \Y $and$ls180.v:3046$75_Y - end - attribute \src "ls180.v:3064.9-3064.96" - cell $and $and$ls180.v:3064$82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_converted_interface_stb - connect \B \main_socbushandler_converted_interface_cyc - connect \Y $and$ls180.v:3064$82_Y - end - attribute \src "ls180.v:3074.31-3074.90" - cell $and $and$ls180.v:3074$84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3074$84_Y - end - attribute \src "ls180.v:3074.30-3074.121" - cell $and $and$ls180.v:3074$85 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3074$84_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3074$85_Y - end - attribute \src "ls180.v:3074.29-3074.156" - cell $and $and$ls180.v:3074$86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3074$85_Y - connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:3074$86_Y - end - attribute \src "ls180.v:3075.31-3075.90" - cell $and $and$ls180.v:3075$87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3075$87_Y - end - attribute \src "ls180.v:3075.30-3075.121" - cell $and $and$ls180.v:3075$88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3075$87_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3075$88_Y - end - attribute \src "ls180.v:3075.29-3075.156" - cell $and $and$ls180.v:3075$89 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3075$88_Y - connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:3075$89_Y - end - attribute \src "ls180.v:3076.31-3076.90" - cell $and $and$ls180.v:3076$90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3076$90_Y - end - attribute \src "ls180.v:3076.30-3076.121" - cell $and $and$ls180.v:3076$91 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3076$90_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3076$91_Y - end - attribute \src "ls180.v:3076.29-3076.156" - cell $and $and$ls180.v:3076$92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3076$91_Y - connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:3076$92_Y - end - attribute \src "ls180.v:3077.31-3077.90" - cell $and $and$ls180.v:3077$93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3077$93_Y - end - attribute \src "ls180.v:3077.30-3077.121" - cell $and $and$ls180.v:3077$94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3077$93_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3077$94_Y - end - attribute \src "ls180.v:3077.29-3077.156" - cell $and $and$ls180.v:3077$95 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3077$94_Y - connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:3077$95_Y - end - attribute \src "ls180.v:3078.31-3078.90" - cell $and $and$ls180.v:3078$96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3078$96_Y - end - attribute \src "ls180.v:3078.30-3078.121" - cell $and $and$ls180.v:3078$97 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3078$96_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3078$97_Y - end - attribute \src "ls180.v:3078.29-3078.156" - cell $and $and$ls180.v:3078$98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3078$97_Y - connect \B \main_libresocsim_ram_bus_sel [4] - connect \Y $and$ls180.v:3078$98_Y - end - attribute \src "ls180.v:3079.30-3079.121" - cell $and $and$ls180.v:3079$100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3079$99_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3079$100_Y - end - attribute \src "ls180.v:3079.29-3079.156" - cell $and $and$ls180.v:3079$101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3079$100_Y - connect \B \main_libresocsim_ram_bus_sel [5] - connect \Y $and$ls180.v:3079$101_Y - end - attribute \src "ls180.v:3079.31-3079.90" - cell $and $and$ls180.v:3079$99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3079$99_Y - end - attribute \src "ls180.v:3080.31-3080.90" - cell $and $and$ls180.v:3080$102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3080$102_Y - end - attribute \src "ls180.v:3080.30-3080.121" - cell $and $and$ls180.v:3080$103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3080$102_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3080$103_Y - end - attribute \src "ls180.v:3080.29-3080.156" - cell $and $and$ls180.v:3080$104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3080$103_Y - connect \B \main_libresocsim_ram_bus_sel [6] - connect \Y $and$ls180.v:3080$104_Y - end - attribute \src "ls180.v:3081.31-3081.90" - cell $and $and$ls180.v:3081$105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3081$105_Y - end - attribute \src "ls180.v:3081.30-3081.121" - cell $and $and$ls180.v:3081$106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3081$105_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3081$106_Y - end - attribute \src "ls180.v:3081.29-3081.156" - cell $and $and$ls180.v:3081$107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3081$106_Y - connect \B \main_libresocsim_ram_bus_sel [7] - connect \Y $and$ls180.v:3081$107_Y - end - attribute \src "ls180.v:3090.7-3090.89" - cell $and $and$ls180.v:3090$110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_re - connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:3090$110_Y - end - attribute \src "ls180.v:3095.32-3095.111" - cell $and $and$ls180.v:3095$111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_w - connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:3095$111_Y - end - attribute \src "ls180.v:3099.25-3099.82" - cell $and $and$ls180.v:3099$113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3099$113_Y - end - attribute \src "ls180.v:3099.24-3099.112" - cell $and $and$ls180.v:3099$114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3099$113_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3099$114_Y - end - attribute \src "ls180.v:3099.23-3099.146" - cell $and $and$ls180.v:3099$115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3099$114_Y - connect \B \main_interface0_ram_bus_sel [0] - connect \Y $and$ls180.v:3099$115_Y - end - attribute \src "ls180.v:3100.25-3100.82" - cell $and $and$ls180.v:3100$116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3100$116_Y - end - attribute \src "ls180.v:3100.24-3100.112" - cell $and $and$ls180.v:3100$117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3100$116_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3100$117_Y - end - attribute \src "ls180.v:3100.23-3100.146" - cell $and $and$ls180.v:3100$118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3100$117_Y - connect \B \main_interface0_ram_bus_sel [1] - connect \Y $and$ls180.v:3100$118_Y - end - attribute \src "ls180.v:3101.25-3101.82" - cell $and $and$ls180.v:3101$119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3101$119_Y - end - attribute \src "ls180.v:3101.24-3101.112" - cell $and $and$ls180.v:3101$120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3101$119_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3101$120_Y - end - attribute \src "ls180.v:3101.23-3101.146" - cell $and $and$ls180.v:3101$121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3101$120_Y - connect \B \main_interface0_ram_bus_sel [2] - connect \Y $and$ls180.v:3101$121_Y - end - attribute \src "ls180.v:3102.25-3102.82" - cell $and $and$ls180.v:3102$122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3102$122_Y - end - attribute \src "ls180.v:3102.24-3102.112" - cell $and $and$ls180.v:3102$123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3102$122_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3102$123_Y - end - attribute \src "ls180.v:3102.23-3102.146" - cell $and $and$ls180.v:3102$124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3102$123_Y - connect \B \main_interface0_ram_bus_sel [3] - connect \Y $and$ls180.v:3102$124_Y - end - attribute \src "ls180.v:3103.25-3103.82" - cell $and $and$ls180.v:3103$125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3103$125_Y - end - attribute \src "ls180.v:3103.24-3103.112" - cell $and $and$ls180.v:3103$126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3103$125_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3103$126_Y - end - attribute \src "ls180.v:3103.23-3103.146" - cell $and $and$ls180.v:3103$127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3103$126_Y - connect \B \main_interface0_ram_bus_sel [4] - connect \Y $and$ls180.v:3103$127_Y - end - attribute \src "ls180.v:3104.25-3104.82" - cell $and $and$ls180.v:3104$128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3104$128_Y - end - attribute \src "ls180.v:3104.24-3104.112" - cell $and $and$ls180.v:3104$129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3104$128_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3104$129_Y - end - attribute \src "ls180.v:3104.23-3104.146" - cell $and $and$ls180.v:3104$130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3104$129_Y - connect \B \main_interface0_ram_bus_sel [5] - connect \Y $and$ls180.v:3104$130_Y - end - attribute \src "ls180.v:3105.25-3105.82" - cell $and $and$ls180.v:3105$131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3105$131_Y - end - attribute \src "ls180.v:3105.24-3105.112" - cell $and $and$ls180.v:3105$132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3105$131_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3105$132_Y - end - attribute \src "ls180.v:3105.23-3105.146" - cell $and $and$ls180.v:3105$133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3105$132_Y - connect \B \main_interface0_ram_bus_sel [6] - connect \Y $and$ls180.v:3105$133_Y - end - attribute \src "ls180.v:3106.25-3106.82" - cell $and $and$ls180.v:3106$134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3106$134_Y - end - attribute \src "ls180.v:3106.24-3106.112" - cell $and $and$ls180.v:3106$135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3106$134_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3106$135_Y - end - attribute \src "ls180.v:3106.23-3106.146" - cell $and $and$ls180.v:3106$136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3106$135_Y - connect \B \main_interface0_ram_bus_sel [7] - connect \Y $and$ls180.v:3106$136_Y - end - attribute \src "ls180.v:3113.25-3113.82" - cell $and $and$ls180.v:3113$138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3113$138_Y - end - attribute \src "ls180.v:3113.24-3113.112" - cell $and $and$ls180.v:3113$139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3113$138_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3113$139_Y - end - attribute \src "ls180.v:3113.23-3113.146" - cell $and $and$ls180.v:3113$140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3113$139_Y - connect \B \main_interface1_ram_bus_sel [0] - connect \Y $and$ls180.v:3113$140_Y - end - attribute \src "ls180.v:3114.25-3114.82" - cell $and $and$ls180.v:3114$141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3114$141_Y - end - attribute \src "ls180.v:3114.24-3114.112" - cell $and $and$ls180.v:3114$142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3114$141_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3114$142_Y - end - attribute \src "ls180.v:3114.23-3114.146" - cell $and $and$ls180.v:3114$143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3114$142_Y - connect \B \main_interface1_ram_bus_sel [1] - connect \Y $and$ls180.v:3114$143_Y - end - attribute \src "ls180.v:3115.25-3115.82" - cell $and $and$ls180.v:3115$144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3115$144_Y - end - attribute \src "ls180.v:3115.24-3115.112" - cell $and $and$ls180.v:3115$145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3115$144_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3115$145_Y - end - attribute \src "ls180.v:3115.23-3115.146" - cell $and $and$ls180.v:3115$146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3115$145_Y - connect \B \main_interface1_ram_bus_sel [2] - connect \Y $and$ls180.v:3115$146_Y - end - attribute \src "ls180.v:3116.25-3116.82" - cell $and $and$ls180.v:3116$147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3116$147_Y - end - attribute \src "ls180.v:3116.24-3116.112" - cell $and $and$ls180.v:3116$148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3116$147_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3116$148_Y - end - attribute \src "ls180.v:3116.23-3116.146" - cell $and $and$ls180.v:3116$149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3116$148_Y - connect \B \main_interface1_ram_bus_sel [3] - connect \Y $and$ls180.v:3116$149_Y - end - attribute \src "ls180.v:3117.25-3117.82" - cell $and $and$ls180.v:3117$150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3117$150_Y - end - attribute \src "ls180.v:3117.24-3117.112" - cell $and $and$ls180.v:3117$151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3117$150_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3117$151_Y - end - attribute \src "ls180.v:3117.23-3117.146" - cell $and $and$ls180.v:3117$152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3117$151_Y - connect \B \main_interface1_ram_bus_sel [4] - connect \Y $and$ls180.v:3117$152_Y - end - attribute \src "ls180.v:3118.25-3118.82" - cell $and $and$ls180.v:3118$153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3118$153_Y - end - attribute \src "ls180.v:3118.24-3118.112" - cell $and $and$ls180.v:3118$154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3118$153_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3118$154_Y - end - attribute \src "ls180.v:3118.23-3118.146" - cell $and $and$ls180.v:3118$155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3118$154_Y - connect \B \main_interface1_ram_bus_sel [5] - connect \Y $and$ls180.v:3118$155_Y - end - attribute \src "ls180.v:3119.25-3119.82" - cell $and $and$ls180.v:3119$156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3119$156_Y - end - attribute \src "ls180.v:3119.24-3119.112" - cell $and $and$ls180.v:3119$157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3119$156_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3119$157_Y - end - attribute \src "ls180.v:3119.23-3119.146" - cell $and $and$ls180.v:3119$158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3119$157_Y - connect \B \main_interface1_ram_bus_sel [6] - connect \Y $and$ls180.v:3119$158_Y - end - attribute \src "ls180.v:3120.25-3120.82" - cell $and $and$ls180.v:3120$159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3120$159_Y - end - attribute \src "ls180.v:3120.24-3120.112" - cell $and $and$ls180.v:3120$160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3120$159_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3120$160_Y - end - attribute \src "ls180.v:3120.23-3120.146" - cell $and $and$ls180.v:3120$161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3120$160_Y - connect \B \main_interface1_ram_bus_sel [7] - connect \Y $and$ls180.v:3120$161_Y - end - attribute \src "ls180.v:3127.25-3127.82" - cell $and $and$ls180.v:3127$163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3127$163_Y - end - attribute \src "ls180.v:3127.24-3127.112" - cell $and $and$ls180.v:3127$164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3127$163_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3127$164_Y - end - attribute \src "ls180.v:3127.23-3127.146" - cell $and $and$ls180.v:3127$165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3127$164_Y - connect \B \main_interface2_ram_bus_sel [0] - connect \Y $and$ls180.v:3127$165_Y - end - attribute \src "ls180.v:3128.25-3128.82" - cell $and $and$ls180.v:3128$166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3128$166_Y - end - attribute \src "ls180.v:3128.24-3128.112" - cell $and $and$ls180.v:3128$167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3128$166_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3128$167_Y - end - attribute \src "ls180.v:3128.23-3128.146" - cell $and $and$ls180.v:3128$168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3128$167_Y - connect \B \main_interface2_ram_bus_sel [1] - connect \Y $and$ls180.v:3128$168_Y - end - attribute \src "ls180.v:3129.25-3129.82" - cell $and $and$ls180.v:3129$169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3129$169_Y - end - attribute \src "ls180.v:3129.24-3129.112" - cell $and $and$ls180.v:3129$170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3129$169_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3129$170_Y - end - attribute \src "ls180.v:3129.23-3129.146" - cell $and $and$ls180.v:3129$171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3129$170_Y - connect \B \main_interface2_ram_bus_sel [2] - connect \Y $and$ls180.v:3129$171_Y - end - attribute \src "ls180.v:3130.25-3130.82" - cell $and $and$ls180.v:3130$172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3130$172_Y - end - attribute \src "ls180.v:3130.24-3130.112" - cell $and $and$ls180.v:3130$173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3130$172_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3130$173_Y - end - attribute \src "ls180.v:3130.23-3130.146" - cell $and $and$ls180.v:3130$174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3130$173_Y - connect \B \main_interface2_ram_bus_sel [3] - connect \Y $and$ls180.v:3130$174_Y - end - attribute \src "ls180.v:3131.25-3131.82" - cell $and $and$ls180.v:3131$175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3131$175_Y - end - attribute \src "ls180.v:3131.24-3131.112" - cell $and $and$ls180.v:3131$176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3131$175_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3131$176_Y - end - attribute \src "ls180.v:3131.23-3131.146" - cell $and $and$ls180.v:3131$177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3131$176_Y - connect \B \main_interface2_ram_bus_sel [4] - connect \Y $and$ls180.v:3131$177_Y - end - attribute \src "ls180.v:3132.25-3132.82" - cell $and $and$ls180.v:3132$178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3132$178_Y - end - attribute \src "ls180.v:3132.24-3132.112" - cell $and $and$ls180.v:3132$179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3132$178_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3132$179_Y - end - attribute \src "ls180.v:3132.23-3132.146" - cell $and $and$ls180.v:3132$180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3132$179_Y - connect \B \main_interface2_ram_bus_sel [5] - connect \Y $and$ls180.v:3132$180_Y - end - attribute \src "ls180.v:3133.25-3133.82" - cell $and $and$ls180.v:3133$181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3133$181_Y - end - attribute \src "ls180.v:3133.24-3133.112" - cell $and $and$ls180.v:3133$182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3133$181_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3133$182_Y - end - attribute \src "ls180.v:3133.23-3133.146" - cell $and $and$ls180.v:3133$183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3133$182_Y - connect \B \main_interface2_ram_bus_sel [6] - connect \Y $and$ls180.v:3133$183_Y - end - attribute \src "ls180.v:3134.25-3134.82" - cell $and $and$ls180.v:3134$184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3134$184_Y - end - attribute \src "ls180.v:3134.24-3134.112" - cell $and $and$ls180.v:3134$185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3134$184_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3134$185_Y - end - attribute \src "ls180.v:3134.23-3134.146" - cell $and $and$ls180.v:3134$186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3134$185_Y - connect \B \main_interface2_ram_bus_sel [7] - connect \Y $and$ls180.v:3134$186_Y - end - attribute \src "ls180.v:3141.25-3141.82" - cell $and $and$ls180.v:3141$188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3141$188_Y - end - attribute \src "ls180.v:3141.24-3141.112" - cell $and $and$ls180.v:3141$189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3141$188_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3141$189_Y - end - attribute \src "ls180.v:3141.23-3141.146" - cell $and $and$ls180.v:3141$190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3141$189_Y - connect \B \main_interface3_ram_bus_sel [0] - connect \Y $and$ls180.v:3141$190_Y - end - attribute \src "ls180.v:3142.25-3142.82" - cell $and $and$ls180.v:3142$191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3142$191_Y - end - attribute \src "ls180.v:3142.24-3142.112" - cell $and $and$ls180.v:3142$192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3142$191_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3142$192_Y - end - attribute \src "ls180.v:3142.23-3142.146" - cell $and $and$ls180.v:3142$193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3142$192_Y - connect \B \main_interface3_ram_bus_sel [1] - connect \Y $and$ls180.v:3142$193_Y - end - attribute \src "ls180.v:3143.25-3143.82" - cell $and $and$ls180.v:3143$194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3143$194_Y - end - attribute \src "ls180.v:3143.24-3143.112" - cell $and $and$ls180.v:3143$195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3143$194_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3143$195_Y - end - attribute \src "ls180.v:3143.23-3143.146" - cell $and $and$ls180.v:3143$196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3143$195_Y - connect \B \main_interface3_ram_bus_sel [2] - connect \Y $and$ls180.v:3143$196_Y - end - attribute \src "ls180.v:3144.25-3144.82" - cell $and $and$ls180.v:3144$197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3144$197_Y - end - attribute \src "ls180.v:3144.24-3144.112" - cell $and $and$ls180.v:3144$198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3144$197_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3144$198_Y - end - attribute \src "ls180.v:3144.23-3144.146" - cell $and $and$ls180.v:3144$199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3144$198_Y - connect \B \main_interface3_ram_bus_sel [3] - connect \Y $and$ls180.v:3144$199_Y - end - attribute \src "ls180.v:3145.25-3145.82" - cell $and $and$ls180.v:3145$200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3145$200_Y - end - attribute \src "ls180.v:3145.24-3145.112" - cell $and $and$ls180.v:3145$201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3145$200_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3145$201_Y - end - attribute \src "ls180.v:3145.23-3145.146" - cell $and $and$ls180.v:3145$202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3145$201_Y - connect \B \main_interface3_ram_bus_sel [4] - connect \Y $and$ls180.v:3145$202_Y - end - attribute \src "ls180.v:3146.25-3146.82" - cell $and $and$ls180.v:3146$203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3146$203_Y - end - attribute \src "ls180.v:3146.24-3146.112" - cell $and $and$ls180.v:3146$204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3146$203_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3146$204_Y - end - attribute \src "ls180.v:3146.23-3146.146" - cell $and $and$ls180.v:3146$205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3146$204_Y - connect \B \main_interface3_ram_bus_sel [5] - connect \Y $and$ls180.v:3146$205_Y - end - attribute \src "ls180.v:3147.25-3147.82" - cell $and $and$ls180.v:3147$206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3147$206_Y - end - attribute \src "ls180.v:3147.24-3147.112" - cell $and $and$ls180.v:3147$207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3147$206_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3147$207_Y - end - attribute \src "ls180.v:3147.23-3147.146" - cell $and $and$ls180.v:3147$208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3147$207_Y - connect \B \main_interface3_ram_bus_sel [6] - connect \Y $and$ls180.v:3147$208_Y - end - attribute \src "ls180.v:3148.25-3148.82" - cell $and $and$ls180.v:3148$209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3148$209_Y - end - attribute \src "ls180.v:3148.24-3148.112" - cell $and $and$ls180.v:3148$210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3148$209_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3148$210_Y - end - attribute \src "ls180.v:3148.23-3148.146" - cell $and $and$ls180.v:3148$211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3148$210_Y - connect \B \main_interface3_ram_bus_sel [7] - connect \Y $and$ls180.v:3148$211_Y - end - attribute \src "ls180.v:3265.40-3265.99" - cell $and $and$ls180.v:3265$218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3265$218_Y - end - attribute \src "ls180.v:3266.40-3266.99" - cell $and $and$ls180.v:3266$219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3266$219_Y - end - attribute \src "ls180.v:3304.38-3304.103" - cell $and $and$ls180.v:3304$225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3304$224_Y - connect \Y $and$ls180.v:3304$225_Y - end - attribute \src "ls180.v:3358.50-3358.119" - cell $and $and$ls180.v:3358$233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3358$233_Y - end - attribute \src "ls180.v:3358.49-3358.167" - cell $and $and$ls180.v:3358$234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3358$233_Y - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3358$234_Y - end - attribute \src "ls180.v:3359.49-3359.118" - cell $and $and$ls180.v:3359$235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3359$235_Y - end - attribute \src "ls180.v:3359.48-3359.154" - cell $and $and$ls180.v:3359$236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3359$235_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3359$236_Y - end - attribute \src "ls180.v:3360.50-3360.119" - cell $and $and$ls180.v:3360$237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3360$237_Y - end - attribute \src "ls180.v:3360.49-3360.155" - cell $and $and$ls180.v:3360$238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3360$237_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3360$238_Y - end - attribute \src "ls180.v:3363.7-3363.114" - cell $and $and$ls180.v:3363$240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3363$240_Y - end - attribute \src "ls180.v:3392.66-3392.246" - cell $and $and$ls180.v:3392$246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3392$245_Y - connect \Y $and$ls180.v:3392$246_Y - end - attribute \src "ls180.v:3393.64-3393.187" - cell $and $and$ls180.v:3393$247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3393$247_Y - end - attribute \src "ls180.v:3417.9-3417.86" - cell $and $and$ls180.v:3417$253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3417$253_Y - end - attribute \src "ls180.v:3429.9-3429.86" - cell $and $and$ls180.v:3429$254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3429$254_Y - end - attribute \src "ls180.v:3479.13-3479.87" - cell $and $and$ls180.v:3479$256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_ready - connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3479$256_Y - end - attribute \src "ls180.v:3515.50-3515.119" - cell $and $and$ls180.v:3515$263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3515$263_Y - end - attribute \src "ls180.v:3515.49-3515.167" - cell $and $and$ls180.v:3515$264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3515$263_Y - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3515$264_Y - end - attribute \src "ls180.v:3516.49-3516.118" - cell $and $and$ls180.v:3516$265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3516$265_Y - end - attribute \src "ls180.v:3516.48-3516.154" - cell $and $and$ls180.v:3516$266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3516$265_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3516$266_Y - end - attribute \src "ls180.v:3517.50-3517.119" - cell $and $and$ls180.v:3517$267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3517$267_Y - end - attribute \src "ls180.v:3517.49-3517.155" - cell $and $and$ls180.v:3517$268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3517$267_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3517$268_Y - end - attribute \src "ls180.v:3520.7-3520.114" - cell $and $and$ls180.v:3520$270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3520$270_Y - end - attribute \src "ls180.v:3549.66-3549.246" - cell $and $and$ls180.v:3549$276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3549$275_Y - connect \Y $and$ls180.v:3549$276_Y - end - attribute \src "ls180.v:3550.64-3550.187" - cell $and $and$ls180.v:3550$277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3550$277_Y - end - attribute \src "ls180.v:3574.9-3574.86" - cell $and $and$ls180.v:3574$283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3574$283_Y - end - attribute \src "ls180.v:3586.9-3586.86" - cell $and $and$ls180.v:3586$284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3586$284_Y - end - attribute \src "ls180.v:3636.13-3636.87" - cell $and $and$ls180.v:3636$286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_ready - connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3636$286_Y - end - attribute \src "ls180.v:3672.50-3672.119" - cell $and $and$ls180.v:3672$293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3672$293_Y - end - attribute \src "ls180.v:3672.49-3672.167" - cell $and $and$ls180.v:3672$294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3672$293_Y - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3672$294_Y - end - attribute \src "ls180.v:3673.49-3673.118" - cell $and $and$ls180.v:3673$295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3673$295_Y - end - attribute \src "ls180.v:3673.48-3673.154" - cell $and $and$ls180.v:3673$296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3673$295_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3673$296_Y - end - attribute \src "ls180.v:3674.50-3674.119" - cell $and $and$ls180.v:3674$297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3674$297_Y - end - attribute \src "ls180.v:3674.49-3674.155" - cell $and $and$ls180.v:3674$298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3674$297_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3674$298_Y - end - attribute \src "ls180.v:3677.7-3677.114" - cell $and $and$ls180.v:3677$300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3677$300_Y - end - attribute \src "ls180.v:3706.66-3706.246" - cell $and $and$ls180.v:3706$306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3706$305_Y - connect \Y $and$ls180.v:3706$306_Y - end - attribute \src "ls180.v:3707.64-3707.187" - cell $and $and$ls180.v:3707$307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3707$307_Y - end - attribute \src "ls180.v:3731.9-3731.86" - cell $and $and$ls180.v:3731$313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3731$313_Y - end - attribute \src "ls180.v:3743.9-3743.86" - cell $and $and$ls180.v:3743$314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3743$314_Y - end - attribute \src "ls180.v:3793.13-3793.87" - cell $and $and$ls180.v:3793$316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_ready - connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3793$316_Y - end - attribute \src "ls180.v:3829.50-3829.119" - cell $and $and$ls180.v:3829$323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3829$323_Y - end - attribute \src "ls180.v:3829.49-3829.167" - cell $and $and$ls180.v:3829$324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3829$323_Y - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3829$324_Y - end - attribute \src "ls180.v:3830.49-3830.118" - cell $and $and$ls180.v:3830$325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3830$325_Y - end - attribute \src "ls180.v:3830.48-3830.154" - cell $and $and$ls180.v:3830$326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3830$325_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3830$326_Y - end - attribute \src "ls180.v:3831.50-3831.119" - cell $and $and$ls180.v:3831$327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3831$327_Y - end - attribute \src "ls180.v:3831.49-3831.155" - cell $and $and$ls180.v:3831$328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3831$327_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3831$328_Y - end - attribute \src "ls180.v:3834.7-3834.114" - cell $and $and$ls180.v:3834$330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3834$330_Y - end - attribute \src "ls180.v:3863.66-3863.246" - cell $and $and$ls180.v:3863$336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3863$335_Y - connect \Y $and$ls180.v:3863$336_Y - end - attribute \src "ls180.v:3864.64-3864.187" - cell $and $and$ls180.v:3864$337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3864$337_Y - end - attribute \src "ls180.v:3888.9-3888.86" - cell $and $and$ls180.v:3888$343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3888$343_Y - end - attribute \src "ls180.v:3900.9-3900.86" - cell $and $and$ls180.v:3900$344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3900$344_Y - end - attribute \src "ls180.v:3950.13-3950.87" - cell $and $and$ls180.v:3950$346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_ready - connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3950$346_Y - end - attribute \src "ls180.v:3965.37-3965.102" - cell $and $and$ls180.v:3965$347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3965$347_Y - end - attribute \src "ls180.v:3965.108-3965.188" - cell $and $and$ls180.v:3965$349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3965$348_Y - connect \Y $and$ls180.v:3965$349_Y - end - attribute \src "ls180.v:3965.107-3965.231" - cell $and $and$ls180.v:3965$351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3965$349_Y - connect \B $not$ls180.v:3965$350_Y - connect \Y $and$ls180.v:3965$351_Y - end - attribute \src "ls180.v:3965.36-3965.232" - cell $and $and$ls180.v:3965$352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3965$347_Y - connect \B $and$ls180.v:3965$351_Y - connect \Y $and$ls180.v:3965$352_Y - end - attribute \src "ls180.v:3966.37-3966.102" - cell $and $and$ls180.v:3966$353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3966$353_Y - end - attribute \src "ls180.v:3966.108-3966.188" - cell $and $and$ls180.v:3966$355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3966$354_Y - connect \Y $and$ls180.v:3966$355_Y - end - attribute \src "ls180.v:3966.107-3966.231" - cell $and $and$ls180.v:3966$357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3966$355_Y - connect \B $not$ls180.v:3966$356_Y - connect \Y $and$ls180.v:3966$357_Y - end - attribute \src "ls180.v:3966.36-3966.232" - cell $and $and$ls180.v:3966$358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3966$353_Y - connect \B $and$ls180.v:3966$357_Y - connect \Y $and$ls180.v:3966$358_Y - end - attribute \src "ls180.v:3967.34-3967.85" - cell $and $and$ls180.v:3967$359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_trrdcon_ready - connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3967$359_Y - end - attribute \src "ls180.v:3968.37-3968.102" - cell $and $and$ls180.v:3968$360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3968$360_Y - end - attribute \src "ls180.v:3968.36-3968.194" - cell $and $and$ls180.v:3968$362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3968$360_Y - connect \B $or$ls180.v:3968$361_Y - connect \Y $and$ls180.v:3968$362_Y - end - attribute \src "ls180.v:3970.37-3970.102" - cell $and $and$ls180.v:3970$363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3970$363_Y - end - attribute \src "ls180.v:3970.36-3970.148" - cell $and $and$ls180.v:3970$364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3970$363_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3970$364_Y - end - attribute \src "ls180.v:3971.40-3971.119" - cell $and $and$ls180.v:3971$365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3971$365_Y - end - attribute \src "ls180.v:3971.124-3971.203" - cell $and $and$ls180.v:3971$366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3971$366_Y - end - attribute \src "ls180.v:3971.209-3971.288" - cell $and $and$ls180.v:3971$368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3971$368_Y - end - attribute \src "ls180.v:3971.294-3971.373" - cell $and $and$ls180.v:3971$370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3971$370_Y - end - attribute \src "ls180.v:3972.41-3972.121" - cell $and $and$ls180.v:3972$372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3972$372_Y - end - attribute \src "ls180.v:3972.126-3972.206" - cell $and $and$ls180.v:3972$373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3972$373_Y - end - attribute \src "ls180.v:3972.212-3972.292" - cell $and $and$ls180.v:3972$375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3972$375_Y - end - attribute \src "ls180.v:3972.298-3972.378" - cell $and $and$ls180.v:3972$377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3972$377_Y - end - attribute \src "ls180.v:3979.38-3979.111" - cell $and $and$ls180.v:3979$381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_gnt - connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3979$381_Y - end - attribute \src "ls180.v:3979.37-3979.150" - cell $and $and$ls180.v:3979$382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3979$381_Y - connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3979$382_Y - end - attribute \src "ls180.v:3979.36-3979.189" - cell $and $and$ls180.v:3979$383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3979$382_Y - connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3979$383_Y - end - attribute \src "ls180.v:3985.77-3985.153" - cell $and $and$ls180.v:3985$386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3985$386_Y - end - attribute \src "ls180.v:3985.162-3985.246" - cell $and $and$ls180.v:3985$388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3985$387_Y - connect \Y $and$ls180.v:3985$388_Y - end - attribute \src "ls180.v:3985.161-3985.291" - cell $and $and$ls180.v:3985$390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3985$388_Y - connect \B $not$ls180.v:3985$389_Y - connect \Y $and$ls180.v:3985$390_Y - end - attribute \src "ls180.v:3985.76-3985.333" - cell $and $and$ls180.v:3985$393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3985$386_Y - connect \B $or$ls180.v:3985$392_Y - connect \Y $and$ls180.v:3985$393_Y - end - attribute \src "ls180.v:3985.338-3985.505" - cell $and $and$ls180.v:3985$396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3985$394_Y - connect \B $eq$ls180.v:3985$395_Y - connect \Y $and$ls180.v:3985$396_Y - end - attribute \src "ls180.v:3985.38-3985.507" - cell $and $and$ls180.v:3985$398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3985$397_Y - connect \Y $and$ls180.v:3985$398_Y - end - attribute \src "ls180.v:3986.77-3986.153" - cell $and $and$ls180.v:3986$399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3986$399_Y - end - attribute \src "ls180.v:3986.162-3986.246" - cell $and $and$ls180.v:3986$401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3986$400_Y - connect \Y $and$ls180.v:3986$401_Y - end - attribute \src "ls180.v:3986.161-3986.291" - cell $and $and$ls180.v:3986$403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3986$401_Y - connect \B $not$ls180.v:3986$402_Y - connect \Y $and$ls180.v:3986$403_Y - end - attribute \src "ls180.v:3986.76-3986.333" - cell $and $and$ls180.v:3986$406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3986$399_Y - connect \B $or$ls180.v:3986$405_Y - connect \Y $and$ls180.v:3986$406_Y - end - attribute \src "ls180.v:3986.338-3986.505" - cell $and $and$ls180.v:3986$409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3986$407_Y - connect \B $eq$ls180.v:3986$408_Y - connect \Y $and$ls180.v:3986$409_Y - end - attribute \src "ls180.v:3986.38-3986.507" - cell $and $and$ls180.v:3986$411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3986$410_Y - connect \Y $and$ls180.v:3986$411_Y - end - attribute \src "ls180.v:3987.77-3987.153" - cell $and $and$ls180.v:3987$412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3987$412_Y - end - attribute \src "ls180.v:3987.162-3987.246" - cell $and $and$ls180.v:3987$414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3987$413_Y - connect \Y $and$ls180.v:3987$414_Y - end - attribute \src "ls180.v:3987.161-3987.291" - cell $and $and$ls180.v:3987$416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3987$414_Y - connect \B $not$ls180.v:3987$415_Y - connect \Y $and$ls180.v:3987$416_Y - end - attribute \src "ls180.v:3987.76-3987.333" - cell $and $and$ls180.v:3987$419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3987$412_Y - connect \B $or$ls180.v:3987$418_Y - connect \Y $and$ls180.v:3987$419_Y - end - attribute \src "ls180.v:3987.338-3987.505" - cell $and $and$ls180.v:3987$422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3987$420_Y - connect \B $eq$ls180.v:3987$421_Y - connect \Y $and$ls180.v:3987$422_Y - end - attribute \src "ls180.v:3987.38-3987.507" - cell $and $and$ls180.v:3987$424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3987$423_Y - connect \Y $and$ls180.v:3987$424_Y - end - attribute \src "ls180.v:3988.77-3988.153" - cell $and $and$ls180.v:3988$425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3988$425_Y - end - attribute \src "ls180.v:3988.162-3988.246" - cell $and $and$ls180.v:3988$427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3988$426_Y - connect \Y $and$ls180.v:3988$427_Y - end - attribute \src "ls180.v:3988.161-3988.291" - cell $and $and$ls180.v:3988$429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$427_Y - connect \B $not$ls180.v:3988$428_Y - connect \Y $and$ls180.v:3988$429_Y - end - attribute \src "ls180.v:3988.76-3988.333" - cell $and $and$ls180.v:3988$432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$425_Y - connect \B $or$ls180.v:3988$431_Y - connect \Y $and$ls180.v:3988$432_Y - end - attribute \src "ls180.v:3988.338-3988.505" - cell $and $and$ls180.v:3988$435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$433_Y - connect \B $eq$ls180.v:3988$434_Y - connect \Y $and$ls180.v:3988$435_Y - end - attribute \src "ls180.v:3988.38-3988.507" - cell $and $and$ls180.v:3988$437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3988$436_Y - connect \Y $and$ls180.v:3988$437_Y - end - attribute \src "ls180.v:4018.77-4018.153" - cell $and $and$ls180.v:4018$444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4018$444_Y - end - attribute \src "ls180.v:4018.162-4018.246" - cell $and $and$ls180.v:4018$446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:4018$445_Y - connect \Y $and$ls180.v:4018$446_Y - end - attribute \src "ls180.v:4018.161-4018.291" - cell $and $and$ls180.v:4018$448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4018$446_Y - connect \B $not$ls180.v:4018$447_Y - connect \Y $and$ls180.v:4018$448_Y - end - attribute \src "ls180.v:4018.76-4018.333" - cell $and $and$ls180.v:4018$451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4018$444_Y - connect \B $or$ls180.v:4018$450_Y - connect \Y $and$ls180.v:4018$451_Y - end - attribute \src "ls180.v:4018.338-4018.505" - cell $and $and$ls180.v:4018$454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4018$452_Y - connect \B $eq$ls180.v:4018$453_Y - connect \Y $and$ls180.v:4018$454_Y - end - attribute \src "ls180.v:4018.38-4018.507" - cell $and $and$ls180.v:4018$456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:4018$455_Y - connect \Y $and$ls180.v:4018$456_Y - end - attribute \src "ls180.v:4019.77-4019.153" - cell $and $and$ls180.v:4019$457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4019$457_Y - end - attribute \src "ls180.v:4019.162-4019.246" - cell $and $and$ls180.v:4019$459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:4019$458_Y - connect \Y $and$ls180.v:4019$459_Y - end - attribute \src "ls180.v:4019.161-4019.291" - cell $and $and$ls180.v:4019$461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4019$459_Y - connect \B $not$ls180.v:4019$460_Y - connect \Y $and$ls180.v:4019$461_Y - end - attribute \src "ls180.v:4019.76-4019.333" - cell $and $and$ls180.v:4019$464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4019$457_Y - connect \B $or$ls180.v:4019$463_Y - connect \Y $and$ls180.v:4019$464_Y - end - attribute \src "ls180.v:4019.338-4019.505" - cell $and $and$ls180.v:4019$467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4019$465_Y - connect \B $eq$ls180.v:4019$466_Y - connect \Y $and$ls180.v:4019$467_Y - end - attribute \src "ls180.v:4019.38-4019.507" - cell $and $and$ls180.v:4019$469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:4019$468_Y - connect \Y $and$ls180.v:4019$469_Y - end - attribute \src "ls180.v:4020.77-4020.153" - cell $and $and$ls180.v:4020$470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4020$470_Y - end - attribute \src "ls180.v:4020.162-4020.246" - cell $and $and$ls180.v:4020$472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:4020$471_Y - connect \Y $and$ls180.v:4020$472_Y - end - attribute \src "ls180.v:4020.161-4020.291" - cell $and $and$ls180.v:4020$474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4020$472_Y - connect \B $not$ls180.v:4020$473_Y - connect \Y $and$ls180.v:4020$474_Y - end - attribute \src "ls180.v:4020.76-4020.333" - cell $and $and$ls180.v:4020$477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4020$470_Y - connect \B $or$ls180.v:4020$476_Y - connect \Y $and$ls180.v:4020$477_Y - end - attribute \src "ls180.v:4020.338-4020.505" - cell $and $and$ls180.v:4020$480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4020$478_Y - connect \B $eq$ls180.v:4020$479_Y - connect \Y $and$ls180.v:4020$480_Y - end - attribute \src "ls180.v:4020.38-4020.507" - cell $and $and$ls180.v:4020$482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:4020$481_Y - connect \Y $and$ls180.v:4020$482_Y - end - attribute \src "ls180.v:4021.77-4021.153" - cell $and $and$ls180.v:4021$483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4021$483_Y - end - attribute \src "ls180.v:4021.162-4021.246" - cell $and $and$ls180.v:4021$485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:4021$484_Y - connect \Y $and$ls180.v:4021$485_Y - end - attribute \src "ls180.v:4021.161-4021.291" - cell $and $and$ls180.v:4021$487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$485_Y - connect \B $not$ls180.v:4021$486_Y - connect \Y $and$ls180.v:4021$487_Y - end - attribute \src "ls180.v:4021.76-4021.333" - cell $and $and$ls180.v:4021$490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$483_Y - connect \B $or$ls180.v:4021$489_Y - connect \Y $and$ls180.v:4021$490_Y - end - attribute \src "ls180.v:4021.338-4021.505" - cell $and $and$ls180.v:4021$493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4021$491_Y - connect \B $eq$ls180.v:4021$492_Y - connect \Y $and$ls180.v:4021$493_Y - end - attribute \src "ls180.v:4021.38-4021.507" - cell $and $and$ls180.v:4021$495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:4021$494_Y - connect \Y $and$ls180.v:4021$495_Y - end - attribute \src "ls180.v:4050.8-4050.73" - cell $and $and$ls180.v:4050$500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4050$500_Y - end - attribute \src "ls180.v:4050.7-4050.114" - cell $and $and$ls180.v:4050$502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4050$500_Y - connect \B $eq$ls180.v:4050$501_Y - connect \Y $and$ls180.v:4050$502_Y - end - attribute \src "ls180.v:4053.8-4053.73" - cell $and $and$ls180.v:4053$503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4053$503_Y - end - attribute \src "ls180.v:4053.7-4053.114" - cell $and $and$ls180.v:4053$505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4053$503_Y - connect \B $eq$ls180.v:4053$504_Y - connect \Y $and$ls180.v:4053$505_Y - end - attribute \src "ls180.v:4059.8-4059.73" - cell $and $and$ls180.v:4059$507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4059$507_Y - end - attribute \src "ls180.v:4059.7-4059.114" - cell $and $and$ls180.v:4059$509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4059$507_Y - connect \B $eq$ls180.v:4059$508_Y - connect \Y $and$ls180.v:4059$509_Y - end - attribute \src "ls180.v:4062.8-4062.73" - cell $and $and$ls180.v:4062$510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4062$510_Y - end - attribute \src "ls180.v:4062.7-4062.114" - cell $and $and$ls180.v:4062$512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4062$510_Y - connect \B $eq$ls180.v:4062$511_Y - connect \Y $and$ls180.v:4062$512_Y - end - attribute \src "ls180.v:4068.8-4068.73" - cell $and $and$ls180.v:4068$514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4068$514_Y - end - attribute \src "ls180.v:4068.7-4068.114" - cell $and $and$ls180.v:4068$516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4068$514_Y - connect \B $eq$ls180.v:4068$515_Y - connect \Y $and$ls180.v:4068$516_Y - end - attribute \src "ls180.v:4071.8-4071.73" - cell $and $and$ls180.v:4071$517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4071$517_Y - end - attribute \src "ls180.v:4071.7-4071.114" - cell $and $and$ls180.v:4071$519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4071$517_Y - connect \B $eq$ls180.v:4071$518_Y - connect \Y $and$ls180.v:4071$519_Y - end - attribute \src "ls180.v:4077.8-4077.73" - cell $and $and$ls180.v:4077$521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4077$521_Y - end - attribute \src "ls180.v:4077.7-4077.114" - cell $and $and$ls180.v:4077$523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4077$521_Y - connect \B $eq$ls180.v:4077$522_Y - connect \Y $and$ls180.v:4077$523_Y - end - attribute \src "ls180.v:4080.8-4080.73" - cell $and $and$ls180.v:4080$524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4080$524_Y - end - attribute \src "ls180.v:4080.7-4080.114" - cell $and $and$ls180.v:4080$526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4080$524_Y - connect \B $eq$ls180.v:4080$525_Y - connect \Y $and$ls180.v:4080$526_Y - end - attribute \src "ls180.v:4105.71-4105.151" - cell $and $and$ls180.v:4105$531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4105$530_Y - connect \Y $and$ls180.v:4105$531_Y - end - attribute \src "ls180.v:4105.70-4105.194" - cell $and $and$ls180.v:4105$533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4105$531_Y - connect \B $not$ls180.v:4105$532_Y - connect \Y $and$ls180.v:4105$533_Y - end - attribute \src "ls180.v:4105.41-4105.222" - cell $and $and$ls180.v:4105$536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4105$535_Y - connect \Y $and$ls180.v:4105$536_Y - end - attribute \src "ls180.v:4143.71-4143.151" - cell $and $and$ls180.v:4143$540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4143$539_Y - connect \Y $and$ls180.v:4143$540_Y - end - attribute \src "ls180.v:4143.70-4143.194" - cell $and $and$ls180.v:4143$542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4143$540_Y - connect \B $not$ls180.v:4143$541_Y - connect \Y $and$ls180.v:4143$542_Y - end - attribute \src "ls180.v:4143.41-4143.222" - cell $and $and$ls180.v:4143$545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4143$544_Y - connect \Y $and$ls180.v:4143$545_Y - end - attribute \src "ls180.v:4161.110-4161.179" - cell $and $and$ls180.v:4161$550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4161$549_Y - connect \Y $and$ls180.v:4161$550_Y - end - attribute \src "ls180.v:4161.185-4161.254" - cell $and $and$ls180.v:4161$553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4161$552_Y - connect \Y $and$ls180.v:4161$553_Y - end - attribute \src "ls180.v:4161.260-4161.329" - cell $and $and$ls180.v:4161$556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4161$555_Y - connect \Y $and$ls180.v:4161$556_Y - end - attribute \src "ls180.v:4161.41-4161.332" - cell $and $and$ls180.v:4161$559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4161$548_Y - connect \B $not$ls180.v:4161$558_Y - connect \Y $and$ls180.v:4161$559_Y - end - attribute \src "ls180.v:4161.40-4161.355" - cell $and $and$ls180.v:4161$560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4161$559_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4161$560_Y - end - attribute \src "ls180.v:4162.34-4162.106" - cell $and $and$ls180.v:4162$563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4162$561_Y - connect \B $not$ls180.v:4162$562_Y - connect \Y $and$ls180.v:4162$563_Y - end - attribute \src "ls180.v:4166.110-4166.179" - cell $and $and$ls180.v:4166$566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4166$565_Y - connect \Y $and$ls180.v:4166$566_Y - end - attribute \src "ls180.v:4166.185-4166.254" - cell $and $and$ls180.v:4166$569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4166$568_Y - connect \Y $and$ls180.v:4166$569_Y - end - attribute \src "ls180.v:4166.260-4166.329" - cell $and $and$ls180.v:4166$572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4166$571_Y - connect \Y $and$ls180.v:4166$572_Y - end - attribute \src "ls180.v:4166.41-4166.332" - cell $and $and$ls180.v:4166$575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4166$564_Y - connect \B $not$ls180.v:4166$574_Y - connect \Y $and$ls180.v:4166$575_Y - end - attribute \src "ls180.v:4166.40-4166.355" - cell $and $and$ls180.v:4166$576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4166$575_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4166$576_Y - end - attribute \src "ls180.v:4167.34-4167.106" - cell $and $and$ls180.v:4167$579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4167$577_Y - connect \B $not$ls180.v:4167$578_Y - connect \Y $and$ls180.v:4167$579_Y - end - attribute \src "ls180.v:4171.110-4171.179" - cell $and $and$ls180.v:4171$582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4171$581_Y - connect \Y $and$ls180.v:4171$582_Y - end - attribute \src "ls180.v:4171.185-4171.254" - cell $and $and$ls180.v:4171$585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4171$584_Y - connect \Y $and$ls180.v:4171$585_Y - end - attribute \src "ls180.v:4171.260-4171.329" - cell $and $and$ls180.v:4171$588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4171$587_Y - connect \Y $and$ls180.v:4171$588_Y - end - attribute \src "ls180.v:4171.41-4171.332" - cell $and $and$ls180.v:4171$591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4171$580_Y - connect \B $not$ls180.v:4171$590_Y - connect \Y $and$ls180.v:4171$591_Y - end - attribute \src "ls180.v:4171.40-4171.355" - cell $and $and$ls180.v:4171$592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4171$591_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4171$592_Y - end - attribute \src "ls180.v:4172.34-4172.106" - cell $and $and$ls180.v:4172$595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4172$593_Y - connect \B $not$ls180.v:4172$594_Y - connect \Y $and$ls180.v:4172$595_Y - end - attribute \src "ls180.v:4176.110-4176.179" - cell $and $and$ls180.v:4176$598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4176$597_Y - connect \Y $and$ls180.v:4176$598_Y - end - attribute \src "ls180.v:4176.185-4176.254" - cell $and $and$ls180.v:4176$601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4176$600_Y - connect \Y $and$ls180.v:4176$601_Y - end - attribute \src "ls180.v:4176.260-4176.329" - cell $and $and$ls180.v:4176$604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4176$603_Y - connect \Y $and$ls180.v:4176$604_Y - end - attribute \src "ls180.v:4176.41-4176.332" - cell $and $and$ls180.v:4176$607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4176$596_Y - connect \B $not$ls180.v:4176$606_Y - connect \Y $and$ls180.v:4176$607_Y - end - attribute \src "ls180.v:4176.40-4176.355" - cell $and $and$ls180.v:4176$608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4176$607_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4176$608_Y - end - attribute \src "ls180.v:4177.34-4177.106" - cell $and $and$ls180.v:4177$611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4177$609_Y - connect \B $not$ls180.v:4177$610_Y - connect \Y $and$ls180.v:4177$611_Y - end - attribute \src "ls180.v:4181.151-4181.220" - cell $and $and$ls180.v:4181$615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4181$614_Y - connect \Y $and$ls180.v:4181$615_Y - end - attribute \src "ls180.v:4181.226-4181.295" - cell $and $and$ls180.v:4181$618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4181$617_Y - connect \Y $and$ls180.v:4181$618_Y - end - attribute \src "ls180.v:4181.301-4181.370" - cell $and $and$ls180.v:4181$621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4181$620_Y - connect \Y $and$ls180.v:4181$621_Y - end - attribute \src "ls180.v:4181.82-4181.373" - cell $and $and$ls180.v:4181$624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$613_Y - connect \B $not$ls180.v:4181$623_Y - connect \Y $and$ls180.v:4181$624_Y - end - attribute \src "ls180.v:4181.43-4181.374" - cell $and $and$ls180.v:4181$625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$612_Y - connect \B $and$ls180.v:4181$624_Y - connect \Y $and$ls180.v:4181$625_Y - end - attribute \src "ls180.v:4181.42-4181.410" - cell $and $and$ls180.v:4181$626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4181$625_Y - connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:4181$626_Y - end - attribute \src "ls180.v:4181.525-4181.594" - cell $and $and$ls180.v:4181$631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4181$630_Y - connect \Y $and$ls180.v:4181$631_Y - end - attribute \src "ls180.v:4181.600-4181.669" - cell $and $and$ls180.v:4181$634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4181$633_Y - connect \Y $and$ls180.v:4181$634_Y - end - attribute \src "ls180.v:4181.675-4181.744" - cell $and $and$ls180.v:4181$637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4181$636_Y - connect \Y $and$ls180.v:4181$637_Y - end - attribute \src "ls180.v:4181.456-4181.747" - cell $and $and$ls180.v:4181$640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$629_Y - connect \B $not$ls180.v:4181$639_Y - connect \Y $and$ls180.v:4181$640_Y - end - attribute \src "ls180.v:4181.417-4181.748" - cell $and $and$ls180.v:4181$641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$628_Y - connect \B $and$ls180.v:4181$640_Y - connect \Y $and$ls180.v:4181$641_Y - end - attribute \src "ls180.v:4181.416-4181.784" - cell $and $and$ls180.v:4181$642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4181$641_Y - connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:4181$642_Y - end - attribute \src "ls180.v:4181.899-4181.968" - cell $and $and$ls180.v:4181$647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4181$646_Y - connect \Y $and$ls180.v:4181$647_Y - end - attribute \src "ls180.v:4181.974-4181.1043" - cell $and $and$ls180.v:4181$650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4181$649_Y - connect \Y $and$ls180.v:4181$650_Y - end - attribute \src "ls180.v:4181.1049-4181.1118" - cell $and $and$ls180.v:4181$653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4181$652_Y - connect \Y $and$ls180.v:4181$653_Y - end - attribute \src "ls180.v:4181.830-4181.1121" - cell $and $and$ls180.v:4181$656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$645_Y - connect \B $not$ls180.v:4181$655_Y - connect \Y $and$ls180.v:4181$656_Y - end - attribute \src "ls180.v:4181.791-4181.1122" - cell $and $and$ls180.v:4181$657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$644_Y - connect \B $and$ls180.v:4181$656_Y - connect \Y $and$ls180.v:4181$657_Y - end - attribute \src "ls180.v:4181.790-4181.1158" - cell $and $and$ls180.v:4181$658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4181$657_Y - connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:4181$658_Y - end - attribute \src "ls180.v:4181.1273-4181.1342" - cell $and $and$ls180.v:4181$663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4181$662_Y - connect \Y $and$ls180.v:4181$663_Y - end - attribute \src "ls180.v:4181.1348-4181.1417" - cell $and $and$ls180.v:4181$666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4181$665_Y - connect \Y $and$ls180.v:4181$666_Y - end - attribute \src "ls180.v:4181.1423-4181.1492" - cell $and $and$ls180.v:4181$669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4181$668_Y - connect \Y $and$ls180.v:4181$669_Y - end - attribute \src "ls180.v:4181.1204-4181.1495" - cell $and $and$ls180.v:4181$672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$661_Y - connect \B $not$ls180.v:4181$671_Y - connect \Y $and$ls180.v:4181$672_Y - end - attribute \src "ls180.v:4181.1165-4181.1496" - cell $and $and$ls180.v:4181$673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4181$660_Y - connect \B $and$ls180.v:4181$672_Y - connect \Y $and$ls180.v:4181$673_Y - end - attribute \src "ls180.v:4181.1164-4181.1532" - cell $and $and$ls180.v:4181$674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4181$673_Y - connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:4181$674_Y - end - attribute \src "ls180.v:4239.9-4239.46" - cell $and $and$ls180.v:4239$680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4239$680_Y - end - attribute \src "ls180.v:4257.9-4257.46" - cell $and $and$ls180.v:4257$687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4257$687_Y - end - attribute \src "ls180.v:4270.32-4270.75" - cell $and $and$ls180.v:4270$691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4270$691_Y - end - attribute \src "ls180.v:4270.31-4270.99" - cell $and $and$ls180.v:4270$693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4270$691_Y - connect \B $not$ls180.v:4270$692_Y - connect \Y $and$ls180.v:4270$693_Y - end - attribute \src "ls180.v:4271.34-4271.102" - cell $and $and$ls180.v:4271$695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4271$694_Y - connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4271$695_Y - end - attribute \src "ls180.v:4271.33-4271.128" - cell $and $and$ls180.v:4271$697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4271$695_Y - connect \B $not$ls180.v:4271$696_Y - connect \Y $and$ls180.v:4271$697_Y - end - attribute \src "ls180.v:4272.33-4272.104" - cell $and $and$ls180.v:4272$700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4272$698_Y - connect \B $not$ls180.v:4272$699_Y - connect \Y $and$ls180.v:4272$700_Y - end - attribute \src "ls180.v:4273.49-4273.85" - cell $and $and$ls180.v:4273$701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \B \main_ack_wdata - connect \Y $and$ls180.v:4273$701_Y - end - attribute \src "ls180.v:4273.90-4273.129" - cell $and $and$ls180.v:4273$703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4273$702_Y - connect \B \main_ack_rdata - connect \Y $and$ls180.v:4273$703_Y - end - attribute \src "ls180.v:4273.32-4273.131" - cell $and $and$ls180.v:4273$705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_ack_cmd - connect \B $or$ls180.v:4273$704_Y - connect \Y $and$ls180.v:4273$705_Y - end - attribute \src "ls180.v:4274.25-4274.66" - cell $and $and$ls180.v:4274$706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4274$706_Y - end - attribute \src "ls180.v:4275.27-4275.72" - cell $and $and$ls180.v:4275$708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4275$708_Y - end - attribute \src "ls180.v:4276.26-4276.71" - cell $and $and$ls180.v:4276$710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_rdata_valid - connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4276$710_Y - end - attribute \src "ls180.v:4305.64-4305.88" - cell $and $and$ls180.v:4305$716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4305$716_Y - end - attribute \src "ls180.v:4309.7-4309.78" - cell $and $and$ls180.v:4309$720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_re - connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4309$720_Y - end - attribute \src "ls180.v:4320.7-4320.78" - cell $and $and$ls180.v:4320$723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_re - connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4320$723_Y - end - attribute \src "ls180.v:4329.26-4329.97" - cell $and $and$ls180.v:4329$725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_w [0] - connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4329$725_Y - end - attribute \src "ls180.v:4329.102-4329.173" - cell $and $and$ls180.v:4329$726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_w [1] - connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4329$726_Y - end - attribute \src "ls180.v:4344.41-4344.133" - cell $and $and$ls180.v:4344$730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4344$729_Y - connect \Y $and$ls180.v:4344$730_Y - end - attribute \src "ls180.v:4355.39-4355.136" - cell $and $and$ls180.v:4355$735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4355$734_Y - connect \Y $and$ls180.v:4355$735_Y - end - attribute \src "ls180.v:4356.37-4356.104" - cell $and $and$ls180.v:4356$736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4356$736_Y - end - attribute \src "ls180.v:4374.41-4374.133" - cell $and $and$ls180.v:4374$741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4374$740_Y - connect \Y $and$ls180.v:4374$741_Y - end - attribute \src "ls180.v:4385.39-4385.136" - cell $and $and$ls180.v:4385$746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4385$745_Y - connect \Y $and$ls180.v:4385$746_Y - end - attribute \src "ls180.v:4386.37-4386.104" - cell $and $and$ls180.v:4386$747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4386$747_Y - end - attribute \src "ls180.v:4585.33-4585.86" - cell $and $and$ls180.v:4585$791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4585$790_Y - connect \Y $and$ls180.v:4585$791_Y - end - attribute \src "ls180.v:4689.9-4689.68" - cell $and $and$ls180.v:4689$800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_sink_valid - connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4689$800_Y - end - attribute \src "ls180.v:4709.53-4709.145" - cell $and $and$ls180.v:4709$803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4709$802_Y - connect \Y $and$ls180.v:4709$803_Y - end - attribute \src "ls180.v:4728.52-4728.137" - cell $and $and$ls180.v:4728$806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4728$806_Y - end - attribute \src "ls180.v:4769.9-4769.68" - cell $and $and$ls180.v:4769$814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_valid - connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4769$814_Y - end - attribute \src "ls180.v:4807.9-4807.68" - cell $and $and$ls180.v:4807$820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_valid - connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4807$820_Y - end - attribute \src "ls180.v:4816.10-4816.69" - cell $and $and$ls180.v:4816$821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_sink_valid - connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4816$821_Y - end - attribute \src "ls180.v:4816.9-4816.93" - cell $and $and$ls180.v:4816$822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4816$821_Y - connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4816$822_Y - end - attribute \src "ls180.v:4836.54-4836.117" - cell $and $and$ls180.v:4836$824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_pads_in_valid - connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4836$824_Y - end - attribute \src "ls180.v:4855.53-4855.140" - cell $and $and$ls180.v:4855$827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4855$827_Y - end - attribute \src "ls180.v:4952.9-4952.70" - cell $and $and$ls180.v:4952$837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4952$837_Y - end - attribute \src "ls180.v:4970.55-4970.120" - cell $and $and$ls180.v:4970$839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_pads_in_valid - connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4970$839_Y - end - attribute \src "ls180.v:4989.54-4989.143" - cell $and $and$ls180.v:4989$842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4989$842_Y - end - attribute \src "ls180.v:5071.9-5071.70" - cell $and $and$ls180.v:5071$857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_valid - connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5071$857_Y - end - attribute \src "ls180.v:5078.9-5078.70" - cell $and $and$ls180.v:5078$858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_sink_valid - connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:5078$858_Y - end - attribute \src "ls180.v:5159.48-5159.124" - cell $and $and$ls180.v:5159$981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5159$981_Y - end - attribute \src "ls180.v:5159.47-5159.165" - cell $and $and$ls180.v:5159$982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5159$981_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5159$982_Y - end - attribute \src "ls180.v:5160.50-5160.127" - cell $and $and$ls180.v:5160$983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5160$983_Y - end - attribute \src "ls180.v:5162.48-5162.124" - cell $and $and$ls180.v:5162$984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5162$984_Y - end - attribute \src "ls180.v:5162.47-5162.165" - cell $and $and$ls180.v:5162$985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5162$984_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5162$985_Y - end - attribute \src "ls180.v:5163.50-5163.127" - cell $and $and$ls180.v:5163$986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5163$986_Y - end - attribute \src "ls180.v:5165.48-5165.124" - cell $and $and$ls180.v:5165$987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5165$987_Y - end - attribute \src "ls180.v:5165.47-5165.165" - cell $and $and$ls180.v:5165$988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5165$987_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5165$988_Y - end - attribute \src "ls180.v:5166.50-5166.127" - cell $and $and$ls180.v:5166$989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5166$989_Y - end - attribute \src "ls180.v:5168.48-5168.124" - cell $and $and$ls180.v:5168$990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5168$990_Y - end - attribute \src "ls180.v:5168.47-5168.165" - cell $and $and$ls180.v:5168$991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5168$990_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5168$991_Y - end - attribute \src "ls180.v:5169.50-5169.127" - cell $and $and$ls180.v:5169$992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5169$992_Y - end - attribute \src "ls180.v:5282.10-5282.86" - cell $and $and$ls180.v:5282$1041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:5282$1041_Y - end - attribute \src "ls180.v:5282.9-5282.127" - cell $and $and$ls180.v:5282$1042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5282$1041_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5282$1042_Y - end - attribute \src "ls180.v:5292.9-5292.152" - cell $and $and$ls180.v:5292$1046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:5292$1044_Y - connect \B $eq$ls180.v:5292$1045_Y - connect \Y $and$ls180.v:5292$1046_Y - end - attribute \src "ls180.v:5292.8-5292.226" - cell $and $and$ls180.v:5292$1048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5292$1046_Y - connect \B $eq$ls180.v:5292$1047_Y - connect \Y $and$ls180.v:5292$1048_Y - end - attribute \src "ls180.v:5292.7-5292.300" - cell $and $and$ls180.v:5292$1050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5292$1048_Y - connect \B $eq$ls180.v:5292$1049_Y - connect \Y $and$ls180.v:5292$1050_Y - end - attribute \src "ls180.v:5297.49-5297.124" - cell $and $and$ls180.v:5297$1051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5297$1051_Y - end - attribute \src "ls180.v:5307.49-5307.124" - cell $and $and$ls180.v:5307$1054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5307$1054_Y - end - attribute \src "ls180.v:5317.49-5317.124" - cell $and $and$ls180.v:5317$1057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5317$1057_Y - end - attribute \src "ls180.v:5327.49-5327.124" - cell $and $and$ls180.v:5327$1060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5327$1060_Y - end - attribute \src "ls180.v:5339.7-5339.84" - cell $and $and$ls180.v:5339$1065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5339$1064_Y - connect \Y $and$ls180.v:5339$1065_Y - end - attribute \src "ls180.v:5457.9-5457.64" - cell $and $and$ls180.v:5457$1114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_sink_valid - connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5457$1114_Y - end - attribute \src "ls180.v:5509.10-5509.66" - cell $and $and$ls180.v:5509$1123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5509$1123_Y - end - attribute \src "ls180.v:5509.9-5509.97" - cell $and $and$ls180.v:5509$1124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5509$1123_Y - connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5509$1124_Y - end - attribute \src "ls180.v:5535.11-5535.71" - cell $and $and$ls180.v:5535$1132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_last - connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5535$1132_Y - end - attribute \src "ls180.v:5619.43-5619.152" - cell $and $and$ls180.v:5619$1140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5619$1139_Y - connect \Y $and$ls180.v:5619$1140_Y - end - attribute \src "ls180.v:5620.41-5620.116" - cell $and $and$ls180.v:5620$1141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_readable - connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5620$1141_Y - end - attribute \src "ls180.v:5632.48-5632.125" - cell $and $and$ls180.v:5632$1146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5632$1146_Y - end - attribute \src "ls180.v:5659.9-5659.102" - cell $and $and$ls180.v:5659$1150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid - connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5659$1150_Y - end - attribute \src "ls180.v:5732.9-5732.58" - cell $and $and$ls180.v:5732$1156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_bus_stb - connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5732$1156_Y - end - attribute \src "ls180.v:5785.51-5785.123" - cell $and $and$ls180.v:5785$1164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_sink_first - connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5785$1164_Y - end - attribute \src "ls180.v:5786.50-5786.120" - cell $and $and$ls180.v:5786$1165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_sink_last - connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5786$1165_Y - end - attribute \src "ls180.v:5787.49-5787.122" - cell $and $and$ls180.v:5787$1166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_last - connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5787$1166_Y - end - attribute \src "ls180.v:5839.43-5839.152" - cell $and $and$ls180.v:5839$1171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5839$1170_Y - connect \Y $and$ls180.v:5839$1171_Y - end - attribute \src "ls180.v:5840.41-5840.116" - cell $and $and$ls180.v:5840$1172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_readable - connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5840$1172_Y - end - attribute \src "ls180.v:5872.9-5872.76" - cell $and $and$ls180.v:5872$1176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_cyc - connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5872$1176_Y - end - attribute \src "ls180.v:5875.44-5875.120" - cell $and $and$ls180.v:5875$1178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5875$1177_Y - connect \Y $and$ls180.v:5875$1178_Y - end - attribute \src "ls180.v:5895.46-5895.90" - cell $and $and$ls180.v:5895$1180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5895$1179_Y - connect \Y $and$ls180.v:5895$1180_Y - end - attribute \src "ls180.v:5896.46-5896.90" - cell $and $and$ls180.v:5896$1182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5896$1181_Y - connect \Y $and$ls180.v:5896$1182_Y - end - attribute \src "ls180.v:5897.49-5897.93" - cell $and $and$ls180.v:5897$1184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5897$1183_Y - connect \Y $and$ls180.v:5897$1184_Y - end - attribute \src "ls180.v:5898.35-5898.79" - cell $and $and$ls180.v:5898$1186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5898$1185_Y - connect \Y $and$ls180.v:5898$1186_Y - end - attribute \src "ls180.v:5899.35-5899.79" - cell $and $and$ls180.v:5899$1188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5899$1187_Y - connect \Y $and$ls180.v:5899$1188_Y - end - attribute \src "ls180.v:5900.46-5900.90" - cell $and $and$ls180.v:5900$1190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5900$1189_Y - connect \Y $and$ls180.v:5900$1190_Y - end - attribute \src "ls180.v:5901.46-5901.90" - cell $and $and$ls180.v:5901$1192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5901$1191_Y - connect \Y $and$ls180.v:5901$1192_Y - end - attribute \src "ls180.v:5902.49-5902.93" - cell $and $and$ls180.v:5902$1194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5902$1193_Y - connect \Y $and$ls180.v:5902$1194_Y - end - attribute \src "ls180.v:5903.35-5903.79" - cell $and $and$ls180.v:5903$1196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5903$1195_Y - connect \Y $and$ls180.v:5903$1196_Y - end - attribute \src "ls180.v:5904.35-5904.79" - cell $and $and$ls180.v:5904$1198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5904$1197_Y - connect \Y $and$ls180.v:5904$1198_Y - end - attribute \src "ls180.v:6013.40-6013.81" - cell $and $and$ls180.v:6013$1213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:6013$1213_Y - end - attribute \src "ls180.v:6014.39-6014.80" - cell $and $and$ls180.v:6014$1214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:6014$1214_Y - end - attribute \src "ls180.v:6015.39-6015.80" - cell $and $and$ls180.v:6015$1215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:6015$1215_Y - end - attribute \src "ls180.v:6016.39-6016.80" - cell $and $and$ls180.v:6016$1216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:6016$1216_Y - end - attribute \src "ls180.v:6017.39-6017.80" - cell $and $and$ls180.v:6017$1217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:6017$1217_Y - end - attribute \src "ls180.v:6018.51-6018.92" - cell $and $and$ls180.v:6018$1218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [5] - connect \Y $and$ls180.v:6018$1218_Y - end - attribute \src "ls180.v:6019.51-6019.92" - cell $and $and$ls180.v:6019$1219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [6] - connect \Y $and$ls180.v:6019$1219_Y - end - attribute \src "ls180.v:6020.52-6020.93" - cell $and $and$ls180.v:6020$1220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [7] - connect \Y $and$ls180.v:6020$1220_Y - end - attribute \src "ls180.v:6021.52-6021.93" - cell $and $and$ls180.v:6021$1221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [8] - connect \Y $and$ls180.v:6021$1221_Y - end - attribute \src "ls180.v:6022.52-6022.93" - cell $and $and$ls180.v:6022$1222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [9] - connect \Y $and$ls180.v:6022$1222_Y - end - attribute \src "ls180.v:6023.52-6023.94" - cell $and $and$ls180.v:6023$1223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [10] - connect \Y $and$ls180.v:6023$1223_Y - end - attribute \src "ls180.v:6024.54-6024.96" - cell $and $and$ls180.v:6024$1224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [11] - connect \Y $and$ls180.v:6024$1224_Y - end - attribute \src "ls180.v:6025.55-6025.97" - cell $and $and$ls180.v:6025$1225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [12] - connect \Y $and$ls180.v:6025$1225_Y - end - attribute \src "ls180.v:6027.25-6027.64" - cell $and $and$ls180.v:6027$1238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_stb - connect \B \builder_shared_cyc - connect \Y $and$ls180.v:6027$1238_Y - end - attribute \src "ls180.v:6027.24-6027.89" - cell $and $and$ls180.v:6027$1240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6027$1238_Y - connect \B $not$ls180.v:6027$1239_Y - connect \Y $and$ls180.v:6027$1240_Y - end - attribute \src "ls180.v:6033.39-6033.100" - cell $and $and$ls180.v:6033$1254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } - connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:6033$1254_Y - end - attribute \src "ls180.v:6033.105-6033.165" - cell $and $and$ls180.v:6033$1255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } - connect \B \main_interface0_ram_bus_dat_r - connect \Y $and$ls180.v:6033$1255_Y - end - attribute \src "ls180.v:6033.171-6033.231" - cell $and $and$ls180.v:6033$1257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } - connect \B \main_interface1_ram_bus_dat_r - connect \Y $and$ls180.v:6033$1257_Y - end - attribute \src "ls180.v:6033.237-6033.297" - cell $and $and$ls180.v:6033$1259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } - connect \B \main_interface2_ram_bus_dat_r - connect \Y $and$ls180.v:6033$1259_Y - end - attribute \src "ls180.v:6033.303-6033.363" - cell $and $and$ls180.v:6033$1261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } - connect \B \main_interface3_ram_bus_dat_r - connect \Y $and$ls180.v:6033$1261_Y - end - attribute \src "ls180.v:6033.369-6033.441" - cell $and $and$ls180.v:6033$1263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } - connect \B \main_interface0_converted_interface_dat_r - connect \Y $and$ls180.v:6033$1263_Y - end - attribute \src "ls180.v:6033.447-6033.519" - cell $and $and$ls180.v:6033$1265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } - connect \B \main_interface1_converted_interface_dat_r - connect \Y $and$ls180.v:6033$1265_Y - end - attribute \src "ls180.v:6033.525-6033.598" - cell $and $and$ls180.v:6033$1267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } - connect \B \main_libresocsim_libresoc_interface0_dat_r - connect \Y $and$ls180.v:6033$1267_Y - end - attribute \src "ls180.v:6033.604-6033.677" - cell $and $and$ls180.v:6033$1269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] } - connect \B \main_libresocsim_libresoc_interface1_dat_r - connect \Y $and$ls180.v:6033$1269_Y - end - attribute \src "ls180.v:6033.683-6033.756" - cell $and $and$ls180.v:6033$1271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] } - connect \B \main_libresocsim_libresoc_interface2_dat_r - connect \Y $and$ls180.v:6033$1271_Y - end - attribute \src "ls180.v:6033.762-6033.836" - cell $and $and$ls180.v:6033$1273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] } - connect \B \main_libresocsim_libresoc_interface3_dat_r - connect \Y $and$ls180.v:6033$1273_Y - end - attribute \src "ls180.v:6033.842-6033.918" - cell $and $and$ls180.v:6033$1275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] } - connect \B \main_socbushandler_converted_interface_dat_r - connect \Y $and$ls180.v:6033$1275_Y - end - attribute \src "ls180.v:6033.924-6033.1001" - cell $and $and$ls180.v:6033$1277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] } - connect \B \builder_libresocsim_converted_interface_dat_r - connect \Y $and$ls180.v:6033$1277_Y - end - attribute \src "ls180.v:6043.39-6043.92" - cell $and $and$ls180.v:6043$1281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6043$1281_Y - end - attribute \src "ls180.v:6043.38-6043.142" - cell $and $and$ls180.v:6043$1283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6043$1281_Y - connect \B $eq$ls180.v:6043$1282_Y - connect \Y $and$ls180.v:6043$1283_Y - end - attribute \src "ls180.v:6044.39-6044.95" - cell $and $and$ls180.v:6044$1285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6044$1284_Y - connect \Y $and$ls180.v:6044$1285_Y - end - attribute \src "ls180.v:6044.38-6044.145" - cell $and $and$ls180.v:6044$1287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6044$1285_Y - connect \B $eq$ls180.v:6044$1286_Y - connect \Y $and$ls180.v:6044$1287_Y - end - attribute \src "ls180.v:6046.41-6046.94" - cell $and $and$ls180.v:6046$1288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6046$1288_Y - end - attribute \src "ls180.v:6046.40-6046.144" - cell $and $and$ls180.v:6046$1290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6046$1288_Y - connect \B $eq$ls180.v:6046$1289_Y - connect \Y $and$ls180.v:6046$1290_Y - end - attribute \src "ls180.v:6047.41-6047.97" - cell $and $and$ls180.v:6047$1292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6047$1291_Y - connect \Y $and$ls180.v:6047$1292_Y - end - attribute \src "ls180.v:6047.40-6047.147" - cell $and $and$ls180.v:6047$1294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6047$1292_Y - connect \B $eq$ls180.v:6047$1293_Y - connect \Y $and$ls180.v:6047$1294_Y - end - attribute \src "ls180.v:6049.41-6049.94" - cell $and $and$ls180.v:6049$1295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6049$1295_Y - end - attribute \src "ls180.v:6049.40-6049.144" - cell $and $and$ls180.v:6049$1297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6049$1295_Y - connect \B $eq$ls180.v:6049$1296_Y - connect \Y $and$ls180.v:6049$1297_Y - end - attribute \src "ls180.v:6050.41-6050.97" - cell $and $and$ls180.v:6050$1299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6050$1298_Y - connect \Y $and$ls180.v:6050$1299_Y - end - attribute \src "ls180.v:6050.40-6050.147" - cell $and $and$ls180.v:6050$1301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6050$1299_Y - connect \B $eq$ls180.v:6050$1300_Y - connect \Y $and$ls180.v:6050$1301_Y - end - attribute \src "ls180.v:6052.41-6052.94" - cell $and $and$ls180.v:6052$1302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6052$1302_Y - end - attribute \src "ls180.v:6052.40-6052.144" - cell $and $and$ls180.v:6052$1304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6052$1302_Y - connect \B $eq$ls180.v:6052$1303_Y - connect \Y $and$ls180.v:6052$1304_Y - end - attribute \src "ls180.v:6053.41-6053.97" - cell $and $and$ls180.v:6053$1306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6053$1305_Y - connect \Y $and$ls180.v:6053$1306_Y - end - attribute \src "ls180.v:6053.40-6053.147" - cell $and $and$ls180.v:6053$1308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6053$1306_Y - connect \B $eq$ls180.v:6053$1307_Y - connect \Y $and$ls180.v:6053$1308_Y - end - attribute \src "ls180.v:6055.41-6055.94" - cell $and $and$ls180.v:6055$1309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6055$1309_Y - end - attribute \src "ls180.v:6055.40-6055.144" - cell $and $and$ls180.v:6055$1311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6055$1309_Y - connect \B $eq$ls180.v:6055$1310_Y - connect \Y $and$ls180.v:6055$1311_Y - end - attribute \src "ls180.v:6056.41-6056.97" - cell $and $and$ls180.v:6056$1313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6056$1312_Y - connect \Y $and$ls180.v:6056$1313_Y - end - attribute \src "ls180.v:6056.40-6056.147" - cell $and $and$ls180.v:6056$1315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6056$1313_Y - connect \B $eq$ls180.v:6056$1314_Y - connect \Y $and$ls180.v:6056$1315_Y - end - attribute \src "ls180.v:6058.44-6058.97" - cell $and $and$ls180.v:6058$1316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6058$1316_Y - end - attribute \src "ls180.v:6058.43-6058.147" - cell $and $and$ls180.v:6058$1318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6058$1316_Y - connect \B $eq$ls180.v:6058$1317_Y - connect \Y $and$ls180.v:6058$1318_Y - end - attribute \src "ls180.v:6059.44-6059.100" - cell $and $and$ls180.v:6059$1320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6059$1319_Y - connect \Y $and$ls180.v:6059$1320_Y - end - attribute \src "ls180.v:6059.43-6059.150" - cell $and $and$ls180.v:6059$1322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6059$1320_Y - connect \B $eq$ls180.v:6059$1321_Y - connect \Y $and$ls180.v:6059$1322_Y - end - attribute \src "ls180.v:6061.44-6061.97" - cell $and $and$ls180.v:6061$1323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6061$1323_Y - end - attribute \src "ls180.v:6061.43-6061.147" - cell $and $and$ls180.v:6061$1325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6061$1323_Y - connect \B $eq$ls180.v:6061$1324_Y - connect \Y $and$ls180.v:6061$1325_Y - end - attribute \src "ls180.v:6062.44-6062.100" - cell $and $and$ls180.v:6062$1327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6062$1326_Y - connect \Y $and$ls180.v:6062$1327_Y - end - attribute \src "ls180.v:6062.43-6062.150" - cell $and $and$ls180.v:6062$1329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6062$1327_Y - connect \B $eq$ls180.v:6062$1328_Y - connect \Y $and$ls180.v:6062$1329_Y - end - attribute \src "ls180.v:6064.44-6064.97" - cell $and $and$ls180.v:6064$1330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6064$1330_Y - end - attribute \src "ls180.v:6064.43-6064.147" - cell $and $and$ls180.v:6064$1332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6064$1330_Y - connect \B $eq$ls180.v:6064$1331_Y - connect \Y $and$ls180.v:6064$1332_Y - end - attribute \src "ls180.v:6065.44-6065.100" - cell $and $and$ls180.v:6065$1334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6065$1333_Y - connect \Y $and$ls180.v:6065$1334_Y - end - attribute \src "ls180.v:6065.43-6065.150" - cell $and $and$ls180.v:6065$1336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6065$1334_Y - connect \B $eq$ls180.v:6065$1335_Y - connect \Y $and$ls180.v:6065$1336_Y - end - attribute \src "ls180.v:6067.44-6067.97" - cell $and $and$ls180.v:6067$1337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6067$1337_Y - end - attribute \src "ls180.v:6067.43-6067.147" - cell $and $and$ls180.v:6067$1339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6067$1337_Y - connect \B $eq$ls180.v:6067$1338_Y - connect \Y $and$ls180.v:6067$1339_Y - end - attribute \src "ls180.v:6068.44-6068.100" - cell $and $and$ls180.v:6068$1341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6068$1340_Y - connect \Y $and$ls180.v:6068$1341_Y - end - attribute \src "ls180.v:6068.43-6068.150" - cell $and $and$ls180.v:6068$1343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6068$1341_Y - connect \B $eq$ls180.v:6068$1342_Y - connect \Y $and$ls180.v:6068$1343_Y - end - attribute \src "ls180.v:6081.36-6081.89" - cell $and $and$ls180.v:6081$1345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6081$1345_Y - end - attribute \src "ls180.v:6081.35-6081.139" - cell $and $and$ls180.v:6081$1347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6081$1345_Y - connect \B $eq$ls180.v:6081$1346_Y - connect \Y $and$ls180.v:6081$1347_Y - end - attribute \src "ls180.v:6082.36-6082.92" - cell $and $and$ls180.v:6082$1349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6082$1348_Y - connect \Y $and$ls180.v:6082$1349_Y - end - attribute \src "ls180.v:6082.35-6082.142" - cell $and $and$ls180.v:6082$1351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6082$1349_Y - connect \B $eq$ls180.v:6082$1350_Y - connect \Y $and$ls180.v:6082$1351_Y - end - attribute \src "ls180.v:6084.36-6084.89" - cell $and $and$ls180.v:6084$1352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6084$1352_Y - end - attribute \src "ls180.v:6084.35-6084.139" - cell $and $and$ls180.v:6084$1354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6084$1352_Y - connect \B $eq$ls180.v:6084$1353_Y - connect \Y $and$ls180.v:6084$1354_Y - end - attribute \src "ls180.v:6085.36-6085.92" - cell $and $and$ls180.v:6085$1356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6085$1355_Y - connect \Y $and$ls180.v:6085$1356_Y - end - attribute \src "ls180.v:6085.35-6085.142" - cell $and $and$ls180.v:6085$1358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6085$1356_Y - connect \B $eq$ls180.v:6085$1357_Y - connect \Y $and$ls180.v:6085$1358_Y - end - attribute \src "ls180.v:6087.36-6087.89" - cell $and $and$ls180.v:6087$1359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6087$1359_Y - end - attribute \src "ls180.v:6087.35-6087.139" - cell $and $and$ls180.v:6087$1361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6087$1359_Y - connect \B $eq$ls180.v:6087$1360_Y - connect \Y $and$ls180.v:6087$1361_Y - end - attribute \src "ls180.v:6088.36-6088.92" - cell $and $and$ls180.v:6088$1363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6088$1362_Y - connect \Y $and$ls180.v:6088$1363_Y - end - attribute \src "ls180.v:6088.35-6088.142" - cell $and $and$ls180.v:6088$1365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6088$1363_Y - connect \B $eq$ls180.v:6088$1364_Y - connect \Y $and$ls180.v:6088$1365_Y - end - attribute \src "ls180.v:6090.36-6090.89" - cell $and $and$ls180.v:6090$1366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6090$1366_Y - end - attribute \src "ls180.v:6090.35-6090.139" - cell $and $and$ls180.v:6090$1368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6090$1366_Y - connect \B $eq$ls180.v:6090$1367_Y - connect \Y $and$ls180.v:6090$1368_Y - end - attribute \src "ls180.v:6091.36-6091.92" - cell $and $and$ls180.v:6091$1370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6091$1369_Y - connect \Y $and$ls180.v:6091$1370_Y - end - attribute \src "ls180.v:6091.35-6091.142" - cell $and $and$ls180.v:6091$1372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6091$1370_Y - connect \B $eq$ls180.v:6091$1371_Y - connect \Y $and$ls180.v:6091$1372_Y - end - attribute \src "ls180.v:6093.37-6093.90" - cell $and $and$ls180.v:6093$1373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6093$1373_Y - end - attribute \src "ls180.v:6093.36-6093.140" - cell $and $and$ls180.v:6093$1375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6093$1373_Y - connect \B $eq$ls180.v:6093$1374_Y - connect \Y $and$ls180.v:6093$1375_Y - end - attribute \src "ls180.v:6094.37-6094.93" - cell $and $and$ls180.v:6094$1377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6094$1376_Y - connect \Y $and$ls180.v:6094$1377_Y - end - attribute \src "ls180.v:6094.36-6094.143" - cell $and $and$ls180.v:6094$1379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6094$1377_Y - connect \B $eq$ls180.v:6094$1378_Y - connect \Y $and$ls180.v:6094$1379_Y - end - attribute \src "ls180.v:6096.37-6096.90" - cell $and $and$ls180.v:6096$1380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6096$1380_Y - end - attribute \src "ls180.v:6096.36-6096.140" - cell $and $and$ls180.v:6096$1382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6096$1380_Y - connect \B $eq$ls180.v:6096$1381_Y - connect \Y $and$ls180.v:6096$1382_Y - end - attribute \src "ls180.v:6097.37-6097.93" - cell $and $and$ls180.v:6097$1384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6097$1383_Y - connect \Y $and$ls180.v:6097$1384_Y - end - attribute \src "ls180.v:6097.36-6097.143" - cell $and $and$ls180.v:6097$1386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6097$1384_Y - connect \B $eq$ls180.v:6097$1385_Y - connect \Y $and$ls180.v:6097$1386_Y - end - attribute \src "ls180.v:6107.35-6107.88" - cell $and $and$ls180.v:6107$1388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:6107$1388_Y - end - attribute \src "ls180.v:6107.34-6107.136" - cell $and $and$ls180.v:6107$1390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6107$1388_Y - connect \B $eq$ls180.v:6107$1389_Y - connect \Y $and$ls180.v:6107$1390_Y - end - attribute \src "ls180.v:6108.35-6108.91" - cell $and $and$ls180.v:6108$1392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:6108$1391_Y - connect \Y $and$ls180.v:6108$1392_Y - end - attribute \src "ls180.v:6108.34-6108.139" - cell $and $and$ls180.v:6108$1394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6108$1392_Y - connect \B $eq$ls180.v:6108$1393_Y - connect \Y $and$ls180.v:6108$1394_Y - end - attribute \src "ls180.v:6110.34-6110.87" - cell $and $and$ls180.v:6110$1395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:6110$1395_Y - end - attribute \src "ls180.v:6110.33-6110.135" - cell $and $and$ls180.v:6110$1397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6110$1395_Y - connect \B $eq$ls180.v:6110$1396_Y - connect \Y $and$ls180.v:6110$1397_Y - end - attribute \src "ls180.v:6111.34-6111.90" - cell $and $and$ls180.v:6111$1399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:6111$1398_Y - connect \Y $and$ls180.v:6111$1399_Y - end - attribute \src "ls180.v:6111.33-6111.138" - cell $and $and$ls180.v:6111$1401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6111$1399_Y - connect \B $eq$ls180.v:6111$1400_Y - connect \Y $and$ls180.v:6111$1401_Y - end - attribute \src "ls180.v:6121.40-6121.93" - cell $and $and$ls180.v:6121$1403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6121$1403_Y - end - attribute \src "ls180.v:6121.39-6121.143" - cell $and $and$ls180.v:6121$1405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6121$1403_Y - connect \B $eq$ls180.v:6121$1404_Y - connect \Y $and$ls180.v:6121$1405_Y - end - attribute \src "ls180.v:6122.40-6122.96" - cell $and $and$ls180.v:6122$1407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6122$1406_Y - connect \Y $and$ls180.v:6122$1407_Y - end - attribute \src "ls180.v:6122.39-6122.146" - cell $and $and$ls180.v:6122$1409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6122$1407_Y - connect \B $eq$ls180.v:6122$1408_Y - connect \Y $and$ls180.v:6122$1409_Y - end - attribute \src "ls180.v:6124.39-6124.92" - cell $and $and$ls180.v:6124$1410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6124$1410_Y - end - attribute \src "ls180.v:6124.38-6124.142" - cell $and $and$ls180.v:6124$1412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6124$1410_Y - connect \B $eq$ls180.v:6124$1411_Y - connect \Y $and$ls180.v:6124$1412_Y - end - attribute \src "ls180.v:6125.39-6125.95" - cell $and $and$ls180.v:6125$1414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6125$1413_Y - connect \Y $and$ls180.v:6125$1414_Y - end - attribute \src "ls180.v:6125.38-6125.145" - cell $and $and$ls180.v:6125$1416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6125$1414_Y - connect \B $eq$ls180.v:6125$1415_Y - connect \Y $and$ls180.v:6125$1416_Y - end - attribute \src "ls180.v:6127.39-6127.92" - cell $and $and$ls180.v:6127$1417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6127$1417_Y - end - attribute \src "ls180.v:6127.38-6127.142" - cell $and $and$ls180.v:6127$1419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6127$1417_Y - connect \B $eq$ls180.v:6127$1418_Y - connect \Y $and$ls180.v:6127$1419_Y - end - attribute \src "ls180.v:6128.39-6128.95" - cell $and $and$ls180.v:6128$1421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6128$1420_Y - connect \Y $and$ls180.v:6128$1421_Y - end - attribute \src "ls180.v:6128.38-6128.145" - cell $and $and$ls180.v:6128$1423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6128$1421_Y - connect \B $eq$ls180.v:6128$1422_Y - connect \Y $and$ls180.v:6128$1423_Y - end - attribute \src "ls180.v:6130.39-6130.92" - cell $and $and$ls180.v:6130$1424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6130$1424_Y - end - attribute \src "ls180.v:6130.38-6130.142" - cell $and $and$ls180.v:6130$1426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6130$1424_Y - connect \B $eq$ls180.v:6130$1425_Y - connect \Y $and$ls180.v:6130$1426_Y - end - attribute \src "ls180.v:6131.39-6131.95" - cell $and $and$ls180.v:6131$1428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6131$1427_Y - connect \Y $and$ls180.v:6131$1428_Y - end - attribute \src "ls180.v:6131.38-6131.145" - cell $and $and$ls180.v:6131$1430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6131$1428_Y - connect \B $eq$ls180.v:6131$1429_Y - connect \Y $and$ls180.v:6131$1430_Y - end - attribute \src "ls180.v:6133.39-6133.92" - cell $and $and$ls180.v:6133$1431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6133$1431_Y - end - attribute \src "ls180.v:6133.38-6133.142" - cell $and $and$ls180.v:6133$1433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6133$1431_Y - connect \B $eq$ls180.v:6133$1432_Y - connect \Y $and$ls180.v:6133$1433_Y - end - attribute \src "ls180.v:6134.39-6134.95" - cell $and $and$ls180.v:6134$1435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6134$1434_Y - connect \Y $and$ls180.v:6134$1435_Y - end - attribute \src "ls180.v:6134.38-6134.145" - cell $and $and$ls180.v:6134$1437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6134$1435_Y - connect \B $eq$ls180.v:6134$1436_Y - connect \Y $and$ls180.v:6134$1437_Y - end - attribute \src "ls180.v:6136.40-6136.93" - cell $and $and$ls180.v:6136$1438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6136$1438_Y - end - attribute \src "ls180.v:6136.39-6136.143" - cell $and $and$ls180.v:6136$1440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6136$1438_Y - connect \B $eq$ls180.v:6136$1439_Y - connect \Y $and$ls180.v:6136$1440_Y - end - attribute \src "ls180.v:6137.40-6137.96" - cell $and $and$ls180.v:6137$1442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6137$1441_Y - connect \Y $and$ls180.v:6137$1442_Y - end - attribute \src "ls180.v:6137.39-6137.146" - cell $and $and$ls180.v:6137$1444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6137$1442_Y - connect \B $eq$ls180.v:6137$1443_Y - connect \Y $and$ls180.v:6137$1444_Y - end - attribute \src "ls180.v:6139.40-6139.93" - cell $and $and$ls180.v:6139$1445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6139$1445_Y - end - attribute \src "ls180.v:6139.39-6139.143" - cell $and $and$ls180.v:6139$1447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6139$1445_Y - connect \B $eq$ls180.v:6139$1446_Y - connect \Y $and$ls180.v:6139$1447_Y - end - attribute \src "ls180.v:6140.40-6140.96" - cell $and $and$ls180.v:6140$1449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6140$1448_Y - connect \Y $and$ls180.v:6140$1449_Y - end - attribute \src "ls180.v:6140.39-6140.146" - cell $and $and$ls180.v:6140$1451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6140$1449_Y - connect \B $eq$ls180.v:6140$1450_Y - connect \Y $and$ls180.v:6140$1451_Y - end - attribute \src "ls180.v:6142.40-6142.93" - cell $and $and$ls180.v:6142$1452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6142$1452_Y - end - attribute \src "ls180.v:6142.39-6142.143" - cell $and $and$ls180.v:6142$1454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6142$1452_Y - connect \B $eq$ls180.v:6142$1453_Y - connect \Y $and$ls180.v:6142$1454_Y - end - attribute \src "ls180.v:6143.40-6143.96" - cell $and $and$ls180.v:6143$1456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6143$1455_Y - connect \Y $and$ls180.v:6143$1456_Y - end - attribute \src "ls180.v:6143.39-6143.146" - cell $and $and$ls180.v:6143$1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6143$1456_Y - connect \B $eq$ls180.v:6143$1457_Y - connect \Y $and$ls180.v:6143$1458_Y - end - attribute \src "ls180.v:6145.40-6145.93" - cell $and $and$ls180.v:6145$1459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6145$1459_Y - end - attribute \src "ls180.v:6145.39-6145.143" - cell $and $and$ls180.v:6145$1461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6145$1459_Y - connect \B $eq$ls180.v:6145$1460_Y - connect \Y $and$ls180.v:6145$1461_Y - end - attribute \src "ls180.v:6146.40-6146.96" - cell $and $and$ls180.v:6146$1463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6146$1462_Y - connect \Y $and$ls180.v:6146$1463_Y - end - attribute \src "ls180.v:6146.39-6146.146" - cell $and $and$ls180.v:6146$1465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6146$1463_Y - connect \B $eq$ls180.v:6146$1464_Y - connect \Y $and$ls180.v:6146$1465_Y - end - attribute \src "ls180.v:6158.40-6158.93" - cell $and $and$ls180.v:6158$1467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6158$1467_Y - end - attribute \src "ls180.v:6158.39-6158.143" - cell $and $and$ls180.v:6158$1469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6158$1467_Y - connect \B $eq$ls180.v:6158$1468_Y - connect \Y $and$ls180.v:6158$1469_Y - end - attribute \src "ls180.v:6159.40-6159.96" - cell $and $and$ls180.v:6159$1471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6159$1470_Y - connect \Y $and$ls180.v:6159$1471_Y - end - attribute \src "ls180.v:6159.39-6159.146" - cell $and $and$ls180.v:6159$1473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6159$1471_Y - connect \B $eq$ls180.v:6159$1472_Y - connect \Y $and$ls180.v:6159$1473_Y - end - attribute \src "ls180.v:6161.39-6161.92" - cell $and $and$ls180.v:6161$1474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6161$1474_Y - end - attribute \src "ls180.v:6161.38-6161.142" - cell $and $and$ls180.v:6161$1476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6161$1474_Y - connect \B $eq$ls180.v:6161$1475_Y - connect \Y $and$ls180.v:6161$1476_Y - end - attribute \src "ls180.v:6162.39-6162.95" - cell $and $and$ls180.v:6162$1478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6162$1477_Y - connect \Y $and$ls180.v:6162$1478_Y - end - attribute \src "ls180.v:6162.38-6162.145" - cell $and $and$ls180.v:6162$1480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6162$1478_Y - connect \B $eq$ls180.v:6162$1479_Y - connect \Y $and$ls180.v:6162$1480_Y - end - attribute \src "ls180.v:6164.39-6164.92" - cell $and $and$ls180.v:6164$1481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6164$1481_Y - end - attribute \src "ls180.v:6164.38-6164.142" - cell $and $and$ls180.v:6164$1483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6164$1481_Y - connect \B $eq$ls180.v:6164$1482_Y - connect \Y $and$ls180.v:6164$1483_Y - end - attribute \src "ls180.v:6165.39-6165.95" - cell $and $and$ls180.v:6165$1485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6165$1484_Y - connect \Y $and$ls180.v:6165$1485_Y - end - attribute \src "ls180.v:6165.38-6165.145" - cell $and $and$ls180.v:6165$1487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6165$1485_Y - connect \B $eq$ls180.v:6165$1486_Y - connect \Y $and$ls180.v:6165$1487_Y - end - attribute \src "ls180.v:6167.39-6167.92" - cell $and $and$ls180.v:6167$1488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6167$1488_Y - end - attribute \src "ls180.v:6167.38-6167.142" - cell $and $and$ls180.v:6167$1490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6167$1488_Y - connect \B $eq$ls180.v:6167$1489_Y - connect \Y $and$ls180.v:6167$1490_Y - end - attribute \src "ls180.v:6168.39-6168.95" - cell $and $and$ls180.v:6168$1492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6168$1491_Y - connect \Y $and$ls180.v:6168$1492_Y - end - attribute \src "ls180.v:6168.38-6168.145" - cell $and $and$ls180.v:6168$1494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6168$1492_Y - connect \B $eq$ls180.v:6168$1493_Y - connect \Y $and$ls180.v:6168$1494_Y - end - attribute \src "ls180.v:6170.39-6170.92" - cell $and $and$ls180.v:6170$1495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6170$1495_Y - end - attribute \src "ls180.v:6170.38-6170.142" - cell $and $and$ls180.v:6170$1497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6170$1495_Y - connect \B $eq$ls180.v:6170$1496_Y - connect \Y $and$ls180.v:6170$1497_Y - end - attribute \src "ls180.v:6171.39-6171.95" - cell $and $and$ls180.v:6171$1499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6171$1498_Y - connect \Y $and$ls180.v:6171$1499_Y - end - attribute \src "ls180.v:6171.38-6171.145" - cell $and $and$ls180.v:6171$1501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6171$1499_Y - connect \B $eq$ls180.v:6171$1500_Y - connect \Y $and$ls180.v:6171$1501_Y - end - attribute \src "ls180.v:6173.40-6173.93" - cell $and $and$ls180.v:6173$1502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6173$1502_Y - end - attribute \src "ls180.v:6173.39-6173.143" - cell $and $and$ls180.v:6173$1504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6173$1502_Y - connect \B $eq$ls180.v:6173$1503_Y - connect \Y $and$ls180.v:6173$1504_Y - end - attribute \src "ls180.v:6174.40-6174.96" - cell $and $and$ls180.v:6174$1506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6174$1505_Y - connect \Y $and$ls180.v:6174$1506_Y - end - attribute \src "ls180.v:6174.39-6174.146" - cell $and $and$ls180.v:6174$1508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6174$1506_Y - connect \B $eq$ls180.v:6174$1507_Y - connect \Y $and$ls180.v:6174$1508_Y - end - attribute \src "ls180.v:6176.40-6176.93" - cell $and $and$ls180.v:6176$1509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6176$1509_Y - end - attribute \src "ls180.v:6176.39-6176.143" - cell $and $and$ls180.v:6176$1511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6176$1509_Y - connect \B $eq$ls180.v:6176$1510_Y - connect \Y $and$ls180.v:6176$1511_Y - end - attribute \src "ls180.v:6177.40-6177.96" - cell $and $and$ls180.v:6177$1513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6177$1512_Y - connect \Y $and$ls180.v:6177$1513_Y - end - attribute \src "ls180.v:6177.39-6177.146" - cell $and $and$ls180.v:6177$1515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6177$1513_Y - connect \B $eq$ls180.v:6177$1514_Y - connect \Y $and$ls180.v:6177$1515_Y - end - attribute \src "ls180.v:6179.40-6179.93" - cell $and $and$ls180.v:6179$1516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6179$1516_Y - end - attribute \src "ls180.v:6179.39-6179.143" - cell $and $and$ls180.v:6179$1518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6179$1516_Y - connect \B $eq$ls180.v:6179$1517_Y - connect \Y $and$ls180.v:6179$1518_Y - end - attribute \src "ls180.v:6180.40-6180.96" - cell $and $and$ls180.v:6180$1520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6180$1519_Y - connect \Y $and$ls180.v:6180$1520_Y - end - attribute \src "ls180.v:6180.39-6180.146" - cell $and $and$ls180.v:6180$1522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6180$1520_Y - connect \B $eq$ls180.v:6180$1521_Y - connect \Y $and$ls180.v:6180$1522_Y - end - attribute \src "ls180.v:6182.40-6182.93" - cell $and $and$ls180.v:6182$1523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6182$1523_Y - end - attribute \src "ls180.v:6182.39-6182.143" - cell $and $and$ls180.v:6182$1525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6182$1523_Y - connect \B $eq$ls180.v:6182$1524_Y - connect \Y $and$ls180.v:6182$1525_Y - end - attribute \src "ls180.v:6183.40-6183.96" - cell $and $and$ls180.v:6183$1527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6183$1526_Y - connect \Y $and$ls180.v:6183$1527_Y - end - attribute \src "ls180.v:6183.39-6183.146" - cell $and $and$ls180.v:6183$1529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6183$1527_Y - connect \B $eq$ls180.v:6183$1528_Y - connect \Y $and$ls180.v:6183$1529_Y - end - attribute \src "ls180.v:6195.42-6195.95" - cell $and $and$ls180.v:6195$1531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6195$1531_Y - end - attribute \src "ls180.v:6195.41-6195.145" - cell $and $and$ls180.v:6195$1533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6195$1531_Y - connect \B $eq$ls180.v:6195$1532_Y - connect \Y $and$ls180.v:6195$1533_Y - end - attribute \src "ls180.v:6196.42-6196.98" - cell $and $and$ls180.v:6196$1535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6196$1534_Y - connect \Y $and$ls180.v:6196$1535_Y - end - attribute \src "ls180.v:6196.41-6196.148" - cell $and $and$ls180.v:6196$1537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6196$1535_Y - connect \B $eq$ls180.v:6196$1536_Y - connect \Y $and$ls180.v:6196$1537_Y - end - attribute \src "ls180.v:6198.42-6198.95" - cell $and $and$ls180.v:6198$1538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6198$1538_Y - end - attribute \src "ls180.v:6198.41-6198.145" - cell $and $and$ls180.v:6198$1540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6198$1538_Y - connect \B $eq$ls180.v:6198$1539_Y - connect \Y $and$ls180.v:6198$1540_Y - end - attribute \src "ls180.v:6199.42-6199.98" - cell $and $and$ls180.v:6199$1542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6199$1541_Y - connect \Y $and$ls180.v:6199$1542_Y - end - attribute \src "ls180.v:6199.41-6199.148" - cell $and $and$ls180.v:6199$1544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6199$1542_Y - connect \B $eq$ls180.v:6199$1543_Y - connect \Y $and$ls180.v:6199$1544_Y - end - attribute \src "ls180.v:6201.42-6201.95" - cell $and $and$ls180.v:6201$1545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6201$1545_Y - end - attribute \src "ls180.v:6201.41-6201.145" - cell $and $and$ls180.v:6201$1547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6201$1545_Y - connect \B $eq$ls180.v:6201$1546_Y - connect \Y $and$ls180.v:6201$1547_Y - end - attribute \src "ls180.v:6202.42-6202.98" - cell $and $and$ls180.v:6202$1549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6202$1548_Y - connect \Y $and$ls180.v:6202$1549_Y - end - attribute \src "ls180.v:6202.41-6202.148" - cell $and $and$ls180.v:6202$1551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6202$1549_Y - connect \B $eq$ls180.v:6202$1550_Y - connect \Y $and$ls180.v:6202$1551_Y - end - attribute \src "ls180.v:6204.42-6204.95" - cell $and $and$ls180.v:6204$1552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6204$1552_Y - end - attribute \src "ls180.v:6204.41-6204.145" - cell $and $and$ls180.v:6204$1554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6204$1552_Y - connect \B $eq$ls180.v:6204$1553_Y - connect \Y $and$ls180.v:6204$1554_Y - end - attribute \src "ls180.v:6205.42-6205.98" - cell $and $and$ls180.v:6205$1556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6205$1555_Y - connect \Y $and$ls180.v:6205$1556_Y - end - attribute \src "ls180.v:6205.41-6205.148" - cell $and $and$ls180.v:6205$1558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6205$1556_Y - connect \B $eq$ls180.v:6205$1557_Y - connect \Y $and$ls180.v:6205$1558_Y - end - attribute \src "ls180.v:6207.42-6207.95" - cell $and $and$ls180.v:6207$1559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6207$1559_Y - end - attribute \src "ls180.v:6207.41-6207.145" - cell $and $and$ls180.v:6207$1561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6207$1559_Y - connect \B $eq$ls180.v:6207$1560_Y - connect \Y $and$ls180.v:6207$1561_Y - end - attribute \src "ls180.v:6208.42-6208.98" - cell $and $and$ls180.v:6208$1563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6208$1562_Y - connect \Y $and$ls180.v:6208$1563_Y - end - attribute \src "ls180.v:6208.41-6208.148" - cell $and $and$ls180.v:6208$1565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6208$1563_Y - connect \B $eq$ls180.v:6208$1564_Y - connect \Y $and$ls180.v:6208$1565_Y - end - attribute \src "ls180.v:6210.42-6210.95" - cell $and $and$ls180.v:6210$1566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6210$1566_Y - end - attribute \src "ls180.v:6210.41-6210.145" - cell $and $and$ls180.v:6210$1568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6210$1566_Y - connect \B $eq$ls180.v:6210$1567_Y - connect \Y $and$ls180.v:6210$1568_Y - end - attribute \src "ls180.v:6211.42-6211.98" - cell $and $and$ls180.v:6211$1570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6211$1569_Y - connect \Y $and$ls180.v:6211$1570_Y - end - attribute \src "ls180.v:6211.41-6211.148" - cell $and $and$ls180.v:6211$1572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6211$1570_Y - connect \B $eq$ls180.v:6211$1571_Y - connect \Y $and$ls180.v:6211$1572_Y - end - attribute \src "ls180.v:6213.42-6213.95" - cell $and $and$ls180.v:6213$1573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6213$1573_Y - end - attribute \src "ls180.v:6213.41-6213.145" - cell $and $and$ls180.v:6213$1575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6213$1573_Y - connect \B $eq$ls180.v:6213$1574_Y - connect \Y $and$ls180.v:6213$1575_Y - end - attribute \src "ls180.v:6214.42-6214.98" - cell $and $and$ls180.v:6214$1577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6214$1576_Y - connect \Y $and$ls180.v:6214$1577_Y - end - attribute \src "ls180.v:6214.41-6214.148" - cell $and $and$ls180.v:6214$1579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6214$1577_Y - connect \B $eq$ls180.v:6214$1578_Y - connect \Y $and$ls180.v:6214$1579_Y - end - attribute \src "ls180.v:6216.42-6216.95" - cell $and $and$ls180.v:6216$1580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6216$1580_Y - end - attribute \src "ls180.v:6216.41-6216.145" - cell $and $and$ls180.v:6216$1582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6216$1580_Y - connect \B $eq$ls180.v:6216$1581_Y - connect \Y $and$ls180.v:6216$1582_Y - end - attribute \src "ls180.v:6217.42-6217.98" - cell $and $and$ls180.v:6217$1584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6217$1583_Y - connect \Y $and$ls180.v:6217$1584_Y - end - attribute \src "ls180.v:6217.41-6217.148" - cell $and $and$ls180.v:6217$1586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6217$1584_Y - connect \B $eq$ls180.v:6217$1585_Y - connect \Y $and$ls180.v:6217$1586_Y - end - attribute \src "ls180.v:6219.44-6219.97" - cell $and $and$ls180.v:6219$1587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6219$1587_Y - end - attribute \src "ls180.v:6219.43-6219.147" - cell $and $and$ls180.v:6219$1589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6219$1587_Y - connect \B $eq$ls180.v:6219$1588_Y - connect \Y $and$ls180.v:6219$1589_Y - end - attribute \src "ls180.v:6220.44-6220.100" - cell $and $and$ls180.v:6220$1591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6220$1590_Y - connect \Y $and$ls180.v:6220$1591_Y - end - attribute \src "ls180.v:6220.43-6220.150" - cell $and $and$ls180.v:6220$1593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6220$1591_Y - connect \B $eq$ls180.v:6220$1592_Y - connect \Y $and$ls180.v:6220$1593_Y - end - attribute \src "ls180.v:6222.44-6222.97" - cell $and $and$ls180.v:6222$1594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6222$1594_Y - end - attribute \src "ls180.v:6222.43-6222.147" - cell $and $and$ls180.v:6222$1596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6222$1594_Y - connect \B $eq$ls180.v:6222$1595_Y - connect \Y $and$ls180.v:6222$1596_Y - end - attribute \src "ls180.v:6223.44-6223.100" - cell $and $and$ls180.v:6223$1598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6223$1597_Y - connect \Y $and$ls180.v:6223$1598_Y - end - attribute \src "ls180.v:6223.43-6223.150" - cell $and $and$ls180.v:6223$1600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6223$1598_Y - connect \B $eq$ls180.v:6223$1599_Y - connect \Y $and$ls180.v:6223$1600_Y - end - attribute \src "ls180.v:6225.44-6225.97" - cell $and $and$ls180.v:6225$1601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6225$1601_Y - end - attribute \src "ls180.v:6225.43-6225.148" - cell $and $and$ls180.v:6225$1603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6225$1601_Y - connect \B $eq$ls180.v:6225$1602_Y - connect \Y $and$ls180.v:6225$1603_Y - end - attribute \src "ls180.v:6226.44-6226.100" - cell $and $and$ls180.v:6226$1605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6226$1604_Y - connect \Y $and$ls180.v:6226$1605_Y - end - attribute \src "ls180.v:6226.43-6226.151" - cell $and $and$ls180.v:6226$1607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6226$1605_Y - connect \B $eq$ls180.v:6226$1606_Y - connect \Y $and$ls180.v:6226$1607_Y - end - attribute \src "ls180.v:6228.44-6228.97" - cell $and $and$ls180.v:6228$1608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6228$1608_Y - end - attribute \src "ls180.v:6228.43-6228.148" - cell $and $and$ls180.v:6228$1610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6228$1608_Y - connect \B $eq$ls180.v:6228$1609_Y - connect \Y $and$ls180.v:6228$1610_Y - end - attribute \src "ls180.v:6229.44-6229.100" - cell $and $and$ls180.v:6229$1612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6229$1611_Y - connect \Y $and$ls180.v:6229$1612_Y - end - attribute \src "ls180.v:6229.43-6229.151" - cell $and $and$ls180.v:6229$1614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6229$1612_Y - connect \B $eq$ls180.v:6229$1613_Y - connect \Y $and$ls180.v:6229$1614_Y - end - attribute \src "ls180.v:6231.44-6231.97" - cell $and $and$ls180.v:6231$1615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6231$1615_Y - end - attribute \src "ls180.v:6231.43-6231.148" - cell $and $and$ls180.v:6231$1617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6231$1615_Y - connect \B $eq$ls180.v:6231$1616_Y - connect \Y $and$ls180.v:6231$1617_Y - end - attribute \src "ls180.v:6232.44-6232.100" - cell $and $and$ls180.v:6232$1619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6232$1618_Y - connect \Y $and$ls180.v:6232$1619_Y - end - attribute \src "ls180.v:6232.43-6232.151" - cell $and $and$ls180.v:6232$1621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6232$1619_Y - connect \B $eq$ls180.v:6232$1620_Y - connect \Y $and$ls180.v:6232$1621_Y - end - attribute \src "ls180.v:6234.41-6234.94" - cell $and $and$ls180.v:6234$1622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6234$1622_Y - end - attribute \src "ls180.v:6234.40-6234.145" - cell $and $and$ls180.v:6234$1624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6234$1622_Y - connect \B $eq$ls180.v:6234$1623_Y - connect \Y $and$ls180.v:6234$1624_Y - end - attribute \src "ls180.v:6235.41-6235.97" - cell $and $and$ls180.v:6235$1626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6235$1625_Y - connect \Y $and$ls180.v:6235$1626_Y - end - attribute \src "ls180.v:6235.40-6235.148" - cell $and $and$ls180.v:6235$1628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6235$1626_Y - connect \B $eq$ls180.v:6235$1627_Y - connect \Y $and$ls180.v:6235$1628_Y - end - attribute \src "ls180.v:6237.42-6237.95" - cell $and $and$ls180.v:6237$1629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6237$1629_Y - end - attribute \src "ls180.v:6237.41-6237.146" - cell $and $and$ls180.v:6237$1631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6237$1629_Y - connect \B $eq$ls180.v:6237$1630_Y - connect \Y $and$ls180.v:6237$1631_Y - end - attribute \src "ls180.v:6238.42-6238.98" - cell $and $and$ls180.v:6238$1633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6238$1632_Y - connect \Y $and$ls180.v:6238$1633_Y - end - attribute \src "ls180.v:6238.41-6238.149" - cell $and $and$ls180.v:6238$1635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6238$1633_Y - connect \B $eq$ls180.v:6238$1634_Y - connect \Y $and$ls180.v:6238$1635_Y - end - attribute \src "ls180.v:6257.46-6257.99" - cell $and $and$ls180.v:6257$1637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6257$1637_Y - end - attribute \src "ls180.v:6257.45-6257.149" - cell $and $and$ls180.v:6257$1639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6257$1637_Y - connect \B $eq$ls180.v:6257$1638_Y - connect \Y $and$ls180.v:6257$1639_Y - end - attribute \src "ls180.v:6258.46-6258.102" - cell $and $and$ls180.v:6258$1641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6258$1640_Y - connect \Y $and$ls180.v:6258$1641_Y - end - attribute \src "ls180.v:6258.45-6258.152" - cell $and $and$ls180.v:6258$1643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6258$1641_Y - connect \B $eq$ls180.v:6258$1642_Y - connect \Y $and$ls180.v:6258$1643_Y - end - attribute \src "ls180.v:6260.46-6260.99" - cell $and $and$ls180.v:6260$1644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6260$1644_Y - end - attribute \src "ls180.v:6260.45-6260.149" - cell $and $and$ls180.v:6260$1646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6260$1644_Y - connect \B $eq$ls180.v:6260$1645_Y - connect \Y $and$ls180.v:6260$1646_Y - end - attribute \src "ls180.v:6261.46-6261.102" - cell $and $and$ls180.v:6261$1648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6261$1647_Y - connect \Y $and$ls180.v:6261$1648_Y - end - attribute \src "ls180.v:6261.45-6261.152" - cell $and $and$ls180.v:6261$1650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6261$1648_Y - connect \B $eq$ls180.v:6261$1649_Y - connect \Y $and$ls180.v:6261$1650_Y - end - attribute \src "ls180.v:6263.46-6263.99" - cell $and $and$ls180.v:6263$1651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6263$1651_Y - end - attribute \src "ls180.v:6263.45-6263.149" - cell $and $and$ls180.v:6263$1653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6263$1651_Y - connect \B $eq$ls180.v:6263$1652_Y - connect \Y $and$ls180.v:6263$1653_Y - end - attribute \src "ls180.v:6264.46-6264.102" - cell $and $and$ls180.v:6264$1655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6264$1654_Y - connect \Y $and$ls180.v:6264$1655_Y - end - attribute \src "ls180.v:6264.45-6264.152" - cell $and $and$ls180.v:6264$1657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6264$1655_Y - connect \B $eq$ls180.v:6264$1656_Y - connect \Y $and$ls180.v:6264$1657_Y - end - attribute \src "ls180.v:6266.46-6266.99" - cell $and $and$ls180.v:6266$1658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6266$1658_Y - end - attribute \src "ls180.v:6266.45-6266.149" - cell $and $and$ls180.v:6266$1660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6266$1658_Y - connect \B $eq$ls180.v:6266$1659_Y - connect \Y $and$ls180.v:6266$1660_Y - end - attribute \src "ls180.v:6267.46-6267.102" - cell $and $and$ls180.v:6267$1662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6267$1661_Y - connect \Y $and$ls180.v:6267$1662_Y - end - attribute \src "ls180.v:6267.45-6267.152" - cell $and $and$ls180.v:6267$1664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6267$1662_Y - connect \B $eq$ls180.v:6267$1663_Y - connect \Y $and$ls180.v:6267$1664_Y - end - attribute \src "ls180.v:6269.45-6269.98" - cell $and $and$ls180.v:6269$1665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6269$1665_Y - end - attribute \src "ls180.v:6269.44-6269.148" - cell $and $and$ls180.v:6269$1667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6269$1665_Y - connect \B $eq$ls180.v:6269$1666_Y - connect \Y $and$ls180.v:6269$1667_Y - end - attribute \src "ls180.v:6270.45-6270.101" - cell $and $and$ls180.v:6270$1669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6270$1668_Y - connect \Y $and$ls180.v:6270$1669_Y - end - attribute \src "ls180.v:6270.44-6270.151" - cell $and $and$ls180.v:6270$1671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6270$1669_Y - connect \B $eq$ls180.v:6270$1670_Y - connect \Y $and$ls180.v:6270$1671_Y - end - attribute \src "ls180.v:6272.45-6272.98" - cell $and $and$ls180.v:6272$1672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6272$1672_Y - end - attribute \src "ls180.v:6272.44-6272.148" - cell $and $and$ls180.v:6272$1674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6272$1672_Y - connect \B $eq$ls180.v:6272$1673_Y - connect \Y $and$ls180.v:6272$1674_Y - end - attribute \src "ls180.v:6273.45-6273.101" - cell $and $and$ls180.v:6273$1676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6273$1675_Y - connect \Y $and$ls180.v:6273$1676_Y - end - attribute \src "ls180.v:6273.44-6273.151" - cell $and $and$ls180.v:6273$1678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6273$1676_Y - connect \B $eq$ls180.v:6273$1677_Y - connect \Y $and$ls180.v:6273$1678_Y - end - attribute \src "ls180.v:6275.45-6275.98" - cell $and $and$ls180.v:6275$1679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6275$1679_Y - end - attribute \src "ls180.v:6275.44-6275.148" - cell $and $and$ls180.v:6275$1681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6275$1679_Y - connect \B $eq$ls180.v:6275$1680_Y - connect \Y $and$ls180.v:6275$1681_Y - end - attribute \src "ls180.v:6276.45-6276.101" - cell $and $and$ls180.v:6276$1683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6276$1682_Y - connect \Y $and$ls180.v:6276$1683_Y - end - attribute \src "ls180.v:6276.44-6276.151" - cell $and $and$ls180.v:6276$1685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6276$1683_Y - connect \B $eq$ls180.v:6276$1684_Y - connect \Y $and$ls180.v:6276$1685_Y - end - attribute \src "ls180.v:6278.45-6278.98" - cell $and $and$ls180.v:6278$1686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6278$1686_Y - end - attribute \src "ls180.v:6278.44-6278.148" - cell $and $and$ls180.v:6278$1688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6278$1686_Y - connect \B $eq$ls180.v:6278$1687_Y - connect \Y $and$ls180.v:6278$1688_Y - end - attribute \src "ls180.v:6279.45-6279.101" - cell $and $and$ls180.v:6279$1690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6279$1689_Y - connect \Y $and$ls180.v:6279$1690_Y - end - attribute \src "ls180.v:6279.44-6279.151" - cell $and $and$ls180.v:6279$1692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6279$1690_Y - connect \B $eq$ls180.v:6279$1691_Y - connect \Y $and$ls180.v:6279$1692_Y - end - attribute \src "ls180.v:6281.36-6281.89" - cell $and $and$ls180.v:6281$1693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6281$1693_Y - end - attribute \src "ls180.v:6281.35-6281.139" - cell $and $and$ls180.v:6281$1695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6281$1693_Y - connect \B $eq$ls180.v:6281$1694_Y - connect \Y $and$ls180.v:6281$1695_Y - end - attribute \src "ls180.v:6282.36-6282.92" - cell $and $and$ls180.v:6282$1697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6282$1696_Y - connect \Y $and$ls180.v:6282$1697_Y - end - attribute \src "ls180.v:6282.35-6282.142" - cell $and $and$ls180.v:6282$1699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6282$1697_Y - connect \B $eq$ls180.v:6282$1698_Y - connect \Y $and$ls180.v:6282$1699_Y - end - attribute \src "ls180.v:6284.47-6284.100" - cell $and $and$ls180.v:6284$1700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6284$1700_Y - end - attribute \src "ls180.v:6284.46-6284.150" - cell $and $and$ls180.v:6284$1702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6284$1700_Y - connect \B $eq$ls180.v:6284$1701_Y - connect \Y $and$ls180.v:6284$1702_Y - end - attribute \src "ls180.v:6285.47-6285.103" - cell $and $and$ls180.v:6285$1704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6285$1703_Y - connect \Y $and$ls180.v:6285$1704_Y - end - attribute \src "ls180.v:6285.46-6285.153" - cell $and $and$ls180.v:6285$1706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6285$1704_Y - connect \B $eq$ls180.v:6285$1705_Y - connect \Y $and$ls180.v:6285$1706_Y - end - attribute \src "ls180.v:6287.47-6287.100" - cell $and $and$ls180.v:6287$1707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6287$1707_Y - end - attribute \src "ls180.v:6287.46-6287.151" - cell $and $and$ls180.v:6287$1709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6287$1707_Y - connect \B $eq$ls180.v:6287$1708_Y - connect \Y $and$ls180.v:6287$1709_Y - end - attribute \src "ls180.v:6288.47-6288.103" - cell $and $and$ls180.v:6288$1711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6288$1710_Y - connect \Y $and$ls180.v:6288$1711_Y - end - attribute \src "ls180.v:6288.46-6288.154" - cell $and $and$ls180.v:6288$1713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6288$1711_Y - connect \B $eq$ls180.v:6288$1712_Y - connect \Y $and$ls180.v:6288$1713_Y - end - attribute \src "ls180.v:6290.47-6290.100" - cell $and $and$ls180.v:6290$1714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6290$1714_Y - end - attribute \src "ls180.v:6290.46-6290.151" - cell $and $and$ls180.v:6290$1716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6290$1714_Y - connect \B $eq$ls180.v:6290$1715_Y - connect \Y $and$ls180.v:6290$1716_Y - end - attribute \src "ls180.v:6291.47-6291.103" - cell $and $and$ls180.v:6291$1718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6291$1717_Y - connect \Y $and$ls180.v:6291$1718_Y - end - attribute \src "ls180.v:6291.46-6291.154" - cell $and $and$ls180.v:6291$1720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6291$1718_Y - connect \B $eq$ls180.v:6291$1719_Y - connect \Y $and$ls180.v:6291$1720_Y - end - attribute \src "ls180.v:6293.47-6293.100" - cell $and $and$ls180.v:6293$1721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6293$1721_Y - end - attribute \src "ls180.v:6293.46-6293.151" - cell $and $and$ls180.v:6293$1723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6293$1721_Y - connect \B $eq$ls180.v:6293$1722_Y - connect \Y $and$ls180.v:6293$1723_Y - end - attribute \src "ls180.v:6294.47-6294.103" - cell $and $and$ls180.v:6294$1725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6294$1724_Y - connect \Y $and$ls180.v:6294$1725_Y - end - attribute \src "ls180.v:6294.46-6294.154" - cell $and $and$ls180.v:6294$1727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6294$1725_Y - connect \B $eq$ls180.v:6294$1726_Y - connect \Y $and$ls180.v:6294$1727_Y - end - attribute \src "ls180.v:6296.47-6296.100" - cell $and $and$ls180.v:6296$1728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6296$1728_Y - end - attribute \src "ls180.v:6296.46-6296.151" - cell $and $and$ls180.v:6296$1730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6296$1728_Y - connect \B $eq$ls180.v:6296$1729_Y - connect \Y $and$ls180.v:6296$1730_Y - end - attribute \src "ls180.v:6297.47-6297.103" - cell $and $and$ls180.v:6297$1732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6297$1731_Y - connect \Y $and$ls180.v:6297$1732_Y - end - attribute \src "ls180.v:6297.46-6297.154" - cell $and $and$ls180.v:6297$1734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6297$1732_Y - connect \B $eq$ls180.v:6297$1733_Y - connect \Y $and$ls180.v:6297$1734_Y - end - attribute \src "ls180.v:6299.47-6299.100" - cell $and $and$ls180.v:6299$1735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6299$1735_Y - end - attribute \src "ls180.v:6299.46-6299.151" - cell $and $and$ls180.v:6299$1737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6299$1735_Y - connect \B $eq$ls180.v:6299$1736_Y - connect \Y $and$ls180.v:6299$1737_Y - end - attribute \src "ls180.v:6300.47-6300.103" - cell $and $and$ls180.v:6300$1739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6300$1738_Y - connect \Y $and$ls180.v:6300$1739_Y - end - attribute \src "ls180.v:6300.46-6300.154" - cell $and $and$ls180.v:6300$1741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6300$1739_Y - connect \B $eq$ls180.v:6300$1740_Y - connect \Y $and$ls180.v:6300$1741_Y - end - attribute \src "ls180.v:6302.46-6302.99" - cell $and $and$ls180.v:6302$1742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6302$1742_Y - end - attribute \src "ls180.v:6302.45-6302.150" - cell $and $and$ls180.v:6302$1744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6302$1742_Y - connect \B $eq$ls180.v:6302$1743_Y - connect \Y $and$ls180.v:6302$1744_Y - end - attribute \src "ls180.v:6303.46-6303.102" - cell $and $and$ls180.v:6303$1746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6303$1745_Y - connect \Y $and$ls180.v:6303$1746_Y - end - attribute \src "ls180.v:6303.45-6303.153" - cell $and $and$ls180.v:6303$1748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6303$1746_Y - connect \B $eq$ls180.v:6303$1747_Y - connect \Y $and$ls180.v:6303$1748_Y - end - attribute \src "ls180.v:6305.46-6305.99" - cell $and $and$ls180.v:6305$1749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6305$1749_Y - end - attribute \src "ls180.v:6305.45-6305.150" - cell $and $and$ls180.v:6305$1751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6305$1749_Y - connect \B $eq$ls180.v:6305$1750_Y - connect \Y $and$ls180.v:6305$1751_Y - end - attribute \src "ls180.v:6306.46-6306.102" - cell $and $and$ls180.v:6306$1753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6306$1752_Y - connect \Y $and$ls180.v:6306$1753_Y - end - attribute \src "ls180.v:6306.45-6306.153" - cell $and $and$ls180.v:6306$1755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6306$1753_Y - connect \B $eq$ls180.v:6306$1754_Y - connect \Y $and$ls180.v:6306$1755_Y - end - attribute \src "ls180.v:6308.46-6308.99" - cell $and $and$ls180.v:6308$1756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6308$1756_Y - end - attribute \src "ls180.v:6308.45-6308.150" - cell $and $and$ls180.v:6308$1758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6308$1756_Y - connect \B $eq$ls180.v:6308$1757_Y - connect \Y $and$ls180.v:6308$1758_Y - end - attribute \src "ls180.v:6309.46-6309.102" - cell $and $and$ls180.v:6309$1760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6309$1759_Y - connect \Y $and$ls180.v:6309$1760_Y - end - attribute \src "ls180.v:6309.45-6309.153" - cell $and $and$ls180.v:6309$1762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6309$1760_Y - connect \B $eq$ls180.v:6309$1761_Y - connect \Y $and$ls180.v:6309$1762_Y - end - attribute \src "ls180.v:6311.46-6311.99" - cell $and $and$ls180.v:6311$1763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6311$1763_Y - end - attribute \src "ls180.v:6311.45-6311.150" - cell $and $and$ls180.v:6311$1765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6311$1763_Y - connect \B $eq$ls180.v:6311$1764_Y - connect \Y $and$ls180.v:6311$1765_Y - end - attribute \src "ls180.v:6312.46-6312.102" - cell $and $and$ls180.v:6312$1767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6312$1766_Y - connect \Y $and$ls180.v:6312$1767_Y - end - attribute \src "ls180.v:6312.45-6312.153" - cell $and $and$ls180.v:6312$1769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6312$1767_Y - connect \B $eq$ls180.v:6312$1768_Y - connect \Y $and$ls180.v:6312$1769_Y - end - attribute \src "ls180.v:6314.46-6314.99" - cell $and $and$ls180.v:6314$1770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6314$1770_Y - end - attribute \src "ls180.v:6314.45-6314.150" - cell $and $and$ls180.v:6314$1772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6314$1770_Y - connect \B $eq$ls180.v:6314$1771_Y - connect \Y $and$ls180.v:6314$1772_Y - end - attribute \src "ls180.v:6315.46-6315.102" - cell $and $and$ls180.v:6315$1774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6315$1773_Y - connect \Y $and$ls180.v:6315$1774_Y - end - attribute \src "ls180.v:6315.45-6315.153" - cell $and $and$ls180.v:6315$1776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6315$1774_Y - connect \B $eq$ls180.v:6315$1775_Y - connect \Y $and$ls180.v:6315$1776_Y - end - attribute \src "ls180.v:6317.46-6317.99" - cell $and $and$ls180.v:6317$1777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6317$1777_Y - end - attribute \src "ls180.v:6317.45-6317.150" - cell $and $and$ls180.v:6317$1779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6317$1777_Y - connect \B $eq$ls180.v:6317$1778_Y - connect \Y $and$ls180.v:6317$1779_Y - end - attribute \src "ls180.v:6318.46-6318.102" - cell $and $and$ls180.v:6318$1781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6318$1780_Y - connect \Y $and$ls180.v:6318$1781_Y - end - attribute \src "ls180.v:6318.45-6318.153" - cell $and $and$ls180.v:6318$1783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6318$1781_Y - connect \B $eq$ls180.v:6318$1782_Y - connect \Y $and$ls180.v:6318$1783_Y - end - attribute \src "ls180.v:6320.46-6320.99" - cell $and $and$ls180.v:6320$1784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6320$1784_Y - end - attribute \src "ls180.v:6320.45-6320.150" - cell $and $and$ls180.v:6320$1786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6320$1784_Y - connect \B $eq$ls180.v:6320$1785_Y - connect \Y $and$ls180.v:6320$1786_Y - end - attribute \src "ls180.v:6321.46-6321.102" - cell $and $and$ls180.v:6321$1788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6321$1787_Y - connect \Y $and$ls180.v:6321$1788_Y - end - attribute \src "ls180.v:6321.45-6321.153" - cell $and $and$ls180.v:6321$1790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6321$1788_Y - connect \B $eq$ls180.v:6321$1789_Y - connect \Y $and$ls180.v:6321$1790_Y - end - attribute \src "ls180.v:6323.46-6323.99" - cell $and $and$ls180.v:6323$1791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6323$1791_Y - end - attribute \src "ls180.v:6323.45-6323.150" - cell $and $and$ls180.v:6323$1793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6323$1791_Y - connect \B $eq$ls180.v:6323$1792_Y - connect \Y $and$ls180.v:6323$1793_Y - end - attribute \src "ls180.v:6324.46-6324.102" - cell $and $and$ls180.v:6324$1795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6324$1794_Y - connect \Y $and$ls180.v:6324$1795_Y - end - attribute \src "ls180.v:6324.45-6324.153" - cell $and $and$ls180.v:6324$1797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6324$1795_Y - connect \B $eq$ls180.v:6324$1796_Y - connect \Y $and$ls180.v:6324$1797_Y - end - attribute \src "ls180.v:6326.46-6326.99" - cell $and $and$ls180.v:6326$1798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6326$1798_Y - end - attribute \src "ls180.v:6326.45-6326.150" - cell $and $and$ls180.v:6326$1800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6326$1798_Y - connect \B $eq$ls180.v:6326$1799_Y - connect \Y $and$ls180.v:6326$1800_Y - end - attribute \src "ls180.v:6327.46-6327.102" - cell $and $and$ls180.v:6327$1802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6327$1801_Y - connect \Y $and$ls180.v:6327$1802_Y - end - attribute \src "ls180.v:6327.45-6327.153" - cell $and $and$ls180.v:6327$1804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6327$1802_Y - connect \B $eq$ls180.v:6327$1803_Y - connect \Y $and$ls180.v:6327$1804_Y - end - attribute \src "ls180.v:6329.46-6329.99" - cell $and $and$ls180.v:6329$1805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6329$1805_Y - end - attribute \src "ls180.v:6329.45-6329.150" - cell $and $and$ls180.v:6329$1807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6329$1805_Y - connect \B $eq$ls180.v:6329$1806_Y - connect \Y $and$ls180.v:6329$1807_Y - end - attribute \src "ls180.v:6330.46-6330.102" - cell $and $and$ls180.v:6330$1809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6330$1808_Y - connect \Y $and$ls180.v:6330$1809_Y - end - attribute \src "ls180.v:6330.45-6330.153" - cell $and $and$ls180.v:6330$1811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6330$1809_Y - connect \B $eq$ls180.v:6330$1810_Y - connect \Y $and$ls180.v:6330$1811_Y - end - attribute \src "ls180.v:6332.42-6332.95" - cell $and $and$ls180.v:6332$1812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6332$1812_Y - end - attribute \src "ls180.v:6332.41-6332.146" - cell $and $and$ls180.v:6332$1814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6332$1812_Y - connect \B $eq$ls180.v:6332$1813_Y - connect \Y $and$ls180.v:6332$1814_Y - end - attribute \src "ls180.v:6333.42-6333.98" - cell $and $and$ls180.v:6333$1816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6333$1815_Y - connect \Y $and$ls180.v:6333$1816_Y - end - attribute \src "ls180.v:6333.41-6333.149" - cell $and $and$ls180.v:6333$1818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6333$1816_Y - connect \B $eq$ls180.v:6333$1817_Y - connect \Y $and$ls180.v:6333$1818_Y - end - attribute \src "ls180.v:6335.43-6335.96" - cell $and $and$ls180.v:6335$1819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6335$1819_Y - end - attribute \src "ls180.v:6335.42-6335.147" - cell $and $and$ls180.v:6335$1821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6335$1819_Y - connect \B $eq$ls180.v:6335$1820_Y - connect \Y $and$ls180.v:6335$1821_Y - end - attribute \src "ls180.v:6336.43-6336.99" - cell $and $and$ls180.v:6336$1823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6336$1822_Y - connect \Y $and$ls180.v:6336$1823_Y - end - attribute \src "ls180.v:6336.42-6336.150" - cell $and $and$ls180.v:6336$1825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6336$1823_Y - connect \B $eq$ls180.v:6336$1824_Y - connect \Y $and$ls180.v:6336$1825_Y - end - attribute \src "ls180.v:6338.46-6338.99" - cell $and $and$ls180.v:6338$1826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6338$1826_Y - end - attribute \src "ls180.v:6338.45-6338.150" - cell $and $and$ls180.v:6338$1828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6338$1826_Y - connect \B $eq$ls180.v:6338$1827_Y - connect \Y $and$ls180.v:6338$1828_Y - end - attribute \src "ls180.v:6339.46-6339.102" - cell $and $and$ls180.v:6339$1830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6339$1829_Y - connect \Y $and$ls180.v:6339$1830_Y - end - attribute \src "ls180.v:6339.45-6339.153" - cell $and $and$ls180.v:6339$1832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6339$1830_Y - connect \B $eq$ls180.v:6339$1831_Y - connect \Y $and$ls180.v:6339$1832_Y - end - attribute \src "ls180.v:6341.46-6341.99" - cell $and $and$ls180.v:6341$1833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6341$1833_Y - end - attribute \src "ls180.v:6341.45-6341.150" - cell $and $and$ls180.v:6341$1835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6341$1833_Y - connect \B $eq$ls180.v:6341$1834_Y - connect \Y $and$ls180.v:6341$1835_Y - end - attribute \src "ls180.v:6342.46-6342.102" - cell $and $and$ls180.v:6342$1837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6342$1836_Y - connect \Y $and$ls180.v:6342$1837_Y - end - attribute \src "ls180.v:6342.45-6342.153" - cell $and $and$ls180.v:6342$1839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6342$1837_Y - connect \B $eq$ls180.v:6342$1838_Y - connect \Y $and$ls180.v:6342$1839_Y - end - attribute \src "ls180.v:6344.45-6344.98" - cell $and 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parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6345$1844_Y - connect \B $eq$ls180.v:6345$1845_Y - connect \Y $and$ls180.v:6345$1846_Y - end - attribute \src "ls180.v:6347.45-6347.98" - cell $and $and$ls180.v:6347$1847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6347$1847_Y - end - attribute \src "ls180.v:6347.44-6347.149" - cell $and $and$ls180.v:6347$1849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6347$1847_Y - connect \B $eq$ls180.v:6347$1848_Y - connect \Y $and$ls180.v:6347$1849_Y - end - attribute \src "ls180.v:6348.45-6348.101" - cell $and $and$ls180.v:6348$1851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6348$1850_Y - connect \Y $and$ls180.v:6348$1851_Y - end - attribute \src "ls180.v:6348.44-6348.152" - cell $and $and$ls180.v:6348$1853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6348$1851_Y - connect \B $eq$ls180.v:6348$1852_Y - connect \Y $and$ls180.v:6348$1853_Y - end - attribute \src "ls180.v:6350.45-6350.98" - cell $and $and$ls180.v:6350$1854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6350$1854_Y - end - attribute \src "ls180.v:6350.44-6350.149" - cell $and $and$ls180.v:6350$1856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6350$1854_Y - connect \B $eq$ls180.v:6350$1855_Y - connect \Y $and$ls180.v:6350$1856_Y - end - attribute \src "ls180.v:6351.45-6351.101" - cell $and $and$ls180.v:6351$1858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6351$1857_Y - connect \Y $and$ls180.v:6351$1858_Y - end - attribute \src "ls180.v:6351.44-6351.152" - cell $and $and$ls180.v:6351$1860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6351$1858_Y - connect \B $eq$ls180.v:6351$1859_Y - connect \Y $and$ls180.v:6351$1860_Y - end - attribute \src "ls180.v:6353.45-6353.98" - cell $and $and$ls180.v:6353$1861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6353$1861_Y - end - attribute \src "ls180.v:6353.44-6353.149" - cell $and $and$ls180.v:6353$1863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6353$1861_Y - connect \B $eq$ls180.v:6353$1862_Y - connect \Y $and$ls180.v:6353$1863_Y - end - attribute \src "ls180.v:6354.45-6354.101" - cell $and $and$ls180.v:6354$1865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6354$1864_Y - connect \Y $and$ls180.v:6354$1865_Y - end - attribute \src "ls180.v:6354.44-6354.152" - cell $and $and$ls180.v:6354$1867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6354$1865_Y - connect \B $eq$ls180.v:6354$1866_Y - connect \Y $and$ls180.v:6354$1867_Y - end - attribute \src "ls180.v:6392.42-6392.95" - cell $and $and$ls180.v:6392$1869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6392$1869_Y - end - attribute \src "ls180.v:6392.41-6392.145" - cell $and $and$ls180.v:6392$1871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6392$1869_Y - connect \B $eq$ls180.v:6392$1870_Y - connect \Y $and$ls180.v:6392$1871_Y - end - attribute \src "ls180.v:6393.42-6393.98" - cell $and $and$ls180.v:6393$1873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6393$1872_Y - connect \Y $and$ls180.v:6393$1873_Y - end - attribute \src "ls180.v:6393.41-6393.148" - cell $and $and$ls180.v:6393$1875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6393$1873_Y - connect \B $eq$ls180.v:6393$1874_Y - connect \Y $and$ls180.v:6393$1875_Y - end - attribute \src "ls180.v:6395.42-6395.95" - cell $and $and$ls180.v:6395$1876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6395$1876_Y - end - attribute \src "ls180.v:6395.41-6395.145" - cell $and $and$ls180.v:6395$1878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6395$1876_Y - connect \B $eq$ls180.v:6395$1877_Y - connect \Y $and$ls180.v:6395$1878_Y - end - attribute \src "ls180.v:6396.42-6396.98" - cell $and $and$ls180.v:6396$1880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6396$1879_Y - connect \Y $and$ls180.v:6396$1880_Y - end - attribute \src "ls180.v:6396.41-6396.148" - cell $and $and$ls180.v:6396$1882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6396$1880_Y - connect \B $eq$ls180.v:6396$1881_Y - connect \Y $and$ls180.v:6396$1882_Y - end - attribute \src "ls180.v:6398.42-6398.95" - cell $and $and$ls180.v:6398$1883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6398$1883_Y - end - attribute \src "ls180.v:6398.41-6398.145" - cell $and $and$ls180.v:6398$1885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6398$1883_Y - connect \B $eq$ls180.v:6398$1884_Y - connect \Y $and$ls180.v:6398$1885_Y - end - attribute \src "ls180.v:6399.42-6399.98" - cell $and $and$ls180.v:6399$1887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6399$1886_Y - connect \Y $and$ls180.v:6399$1887_Y - end - attribute \src "ls180.v:6399.41-6399.148" - cell $and $and$ls180.v:6399$1889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6399$1887_Y - connect \B $eq$ls180.v:6399$1888_Y - connect \Y $and$ls180.v:6399$1889_Y - end - attribute \src "ls180.v:6401.42-6401.95" - cell $and $and$ls180.v:6401$1890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6401$1890_Y - end - attribute \src "ls180.v:6401.41-6401.145" - cell $and $and$ls180.v:6401$1892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6401$1890_Y - connect \B $eq$ls180.v:6401$1891_Y - connect \Y $and$ls180.v:6401$1892_Y - end - attribute \src "ls180.v:6402.42-6402.98" - cell $and $and$ls180.v:6402$1894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6402$1893_Y - connect \Y $and$ls180.v:6402$1894_Y - end - attribute \src "ls180.v:6402.41-6402.148" - cell $and $and$ls180.v:6402$1896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6402$1894_Y - connect \B $eq$ls180.v:6402$1895_Y - connect \Y $and$ls180.v:6402$1896_Y - end - attribute \src "ls180.v:6404.42-6404.95" - cell $and $and$ls180.v:6404$1897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6404$1897_Y - end - attribute \src "ls180.v:6404.41-6404.145" - cell $and $and$ls180.v:6404$1899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6404$1897_Y - connect \B $eq$ls180.v:6404$1898_Y - connect \Y $and$ls180.v:6404$1899_Y - end - attribute \src "ls180.v:6405.42-6405.98" - cell $and $and$ls180.v:6405$1901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6405$1900_Y - connect \Y $and$ls180.v:6405$1901_Y - end - attribute \src "ls180.v:6405.41-6405.148" - cell $and $and$ls180.v:6405$1903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6405$1901_Y - connect \B $eq$ls180.v:6405$1902_Y - connect \Y $and$ls180.v:6405$1903_Y - end - attribute \src "ls180.v:6407.42-6407.95" - cell $and $and$ls180.v:6407$1904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6407$1904_Y - end - attribute \src "ls180.v:6407.41-6407.145" - cell $and $and$ls180.v:6407$1906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6407$1904_Y - connect \B $eq$ls180.v:6407$1905_Y - connect \Y $and$ls180.v:6407$1906_Y - end - attribute \src "ls180.v:6408.42-6408.98" - cell $and $and$ls180.v:6408$1908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6408$1907_Y - connect \Y $and$ls180.v:6408$1908_Y - end - attribute \src "ls180.v:6408.41-6408.148" - cell $and $and$ls180.v:6408$1910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6408$1908_Y - connect \B $eq$ls180.v:6408$1909_Y - connect \Y $and$ls180.v:6408$1910_Y - end - attribute \src "ls180.v:6410.42-6410.95" - cell $and $and$ls180.v:6410$1911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6410$1911_Y - end - attribute \src "ls180.v:6410.41-6410.145" - cell $and $and$ls180.v:6410$1913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6410$1911_Y - connect \B $eq$ls180.v:6410$1912_Y - connect \Y $and$ls180.v:6410$1913_Y - end - attribute \src "ls180.v:6411.42-6411.98" - cell $and $and$ls180.v:6411$1915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6411$1914_Y - connect \Y $and$ls180.v:6411$1915_Y - end - attribute \src "ls180.v:6411.41-6411.148" - cell $and $and$ls180.v:6411$1917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6411$1915_Y - connect \B $eq$ls180.v:6411$1916_Y - connect \Y $and$ls180.v:6411$1917_Y - end - attribute \src "ls180.v:6413.42-6413.95" - cell $and $and$ls180.v:6413$1918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6413$1918_Y - end - attribute \src "ls180.v:6413.41-6413.145" - cell $and $and$ls180.v:6413$1920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6413$1918_Y - connect \B $eq$ls180.v:6413$1919_Y - connect \Y $and$ls180.v:6413$1920_Y - end - attribute \src "ls180.v:6414.42-6414.98" - cell $and $and$ls180.v:6414$1922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6414$1921_Y - connect \Y $and$ls180.v:6414$1922_Y - end - attribute \src "ls180.v:6414.41-6414.148" - cell $and $and$ls180.v:6414$1924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6414$1922_Y - connect \B $eq$ls180.v:6414$1923_Y - connect \Y $and$ls180.v:6414$1924_Y - end - attribute \src "ls180.v:6416.44-6416.97" - cell $and $and$ls180.v:6416$1925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6416$1925_Y - end - attribute \src "ls180.v:6416.43-6416.147" - cell $and $and$ls180.v:6416$1927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6416$1925_Y - connect \B $eq$ls180.v:6416$1926_Y - connect \Y $and$ls180.v:6416$1927_Y - end - attribute \src "ls180.v:6417.44-6417.100" - cell $and $and$ls180.v:6417$1929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6417$1928_Y - connect \Y $and$ls180.v:6417$1929_Y - end - attribute \src "ls180.v:6417.43-6417.150" - cell $and $and$ls180.v:6417$1931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6417$1929_Y - connect \B $eq$ls180.v:6417$1930_Y - connect \Y $and$ls180.v:6417$1931_Y - end - attribute \src "ls180.v:6419.44-6419.97" - cell $and $and$ls180.v:6419$1932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6419$1932_Y - end - attribute \src "ls180.v:6419.43-6419.147" - cell $and $and$ls180.v:6419$1934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6419$1932_Y - connect \B $eq$ls180.v:6419$1933_Y - connect \Y $and$ls180.v:6419$1934_Y - end - attribute \src "ls180.v:6420.44-6420.100" - cell $and $and$ls180.v:6420$1936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6420$1935_Y - connect \Y $and$ls180.v:6420$1936_Y - end - attribute \src "ls180.v:6420.43-6420.150" - cell $and $and$ls180.v:6420$1938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6420$1936_Y - connect \B $eq$ls180.v:6420$1937_Y - connect \Y $and$ls180.v:6420$1938_Y - end - attribute \src "ls180.v:6422.44-6422.97" - cell $and $and$ls180.v:6422$1939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6422$1939_Y - end - attribute \src "ls180.v:6422.43-6422.148" - cell $and $and$ls180.v:6422$1941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6422$1939_Y - connect \B $eq$ls180.v:6422$1940_Y - connect \Y $and$ls180.v:6422$1941_Y - end - attribute \src "ls180.v:6423.44-6423.100" - cell $and $and$ls180.v:6423$1943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6423$1942_Y - connect \Y $and$ls180.v:6423$1943_Y - end - attribute \src "ls180.v:6423.43-6423.151" - cell $and $and$ls180.v:6423$1945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6423$1943_Y - connect \B $eq$ls180.v:6423$1944_Y - connect \Y $and$ls180.v:6423$1945_Y - end - attribute \src "ls180.v:6425.44-6425.97" - cell $and $and$ls180.v:6425$1946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6425$1946_Y - end - attribute \src "ls180.v:6425.43-6425.148" - cell $and $and$ls180.v:6425$1948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6425$1946_Y - connect \B $eq$ls180.v:6425$1947_Y - connect \Y $and$ls180.v:6425$1948_Y - end - attribute \src "ls180.v:6426.44-6426.100" - cell $and $and$ls180.v:6426$1950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6426$1949_Y - connect \Y $and$ls180.v:6426$1950_Y - end - attribute \src "ls180.v:6426.43-6426.151" - cell $and $and$ls180.v:6426$1952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6426$1950_Y - connect \B $eq$ls180.v:6426$1951_Y - connect \Y $and$ls180.v:6426$1952_Y - end - attribute \src "ls180.v:6428.44-6428.97" - cell $and $and$ls180.v:6428$1953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6428$1953_Y - end - attribute \src "ls180.v:6428.43-6428.148" - cell $and $and$ls180.v:6428$1955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6428$1953_Y - connect \B $eq$ls180.v:6428$1954_Y - connect \Y $and$ls180.v:6428$1955_Y - end - attribute \src "ls180.v:6429.44-6429.100" - cell $and $and$ls180.v:6429$1957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6429$1956_Y - connect \Y $and$ls180.v:6429$1957_Y - end - attribute \src "ls180.v:6429.43-6429.151" - cell $and $and$ls180.v:6429$1959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6429$1957_Y - connect \B $eq$ls180.v:6429$1958_Y - connect \Y $and$ls180.v:6429$1959_Y - end - attribute \src "ls180.v:6431.41-6431.94" - cell $and $and$ls180.v:6431$1960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6431$1960_Y - end - attribute \src "ls180.v:6431.40-6431.145" - cell $and $and$ls180.v:6431$1962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6431$1960_Y - connect \B $eq$ls180.v:6431$1961_Y - connect \Y $and$ls180.v:6431$1962_Y - end - attribute \src "ls180.v:6432.41-6432.97" - cell $and $and$ls180.v:6432$1964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6432$1963_Y - connect \Y $and$ls180.v:6432$1964_Y - end - attribute \src "ls180.v:6432.40-6432.148" - cell $and $and$ls180.v:6432$1966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6432$1964_Y - connect \B $eq$ls180.v:6432$1965_Y - connect \Y $and$ls180.v:6432$1966_Y - end - attribute \src "ls180.v:6434.42-6434.95" - cell $and $and$ls180.v:6434$1967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6434$1967_Y - end - attribute \src "ls180.v:6434.41-6434.146" - cell $and $and$ls180.v:6434$1969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6434$1967_Y - connect \B $eq$ls180.v:6434$1968_Y - connect \Y $and$ls180.v:6434$1969_Y - end - attribute \src "ls180.v:6435.42-6435.98" - cell $and $and$ls180.v:6435$1971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6435$1970_Y - connect \Y $and$ls180.v:6435$1971_Y - end - attribute \src "ls180.v:6435.41-6435.149" - cell $and $and$ls180.v:6435$1973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6435$1971_Y - connect \B $eq$ls180.v:6435$1972_Y - connect \Y $and$ls180.v:6435$1973_Y - end - attribute \src "ls180.v:6437.44-6437.97" - cell $and $and$ls180.v:6437$1974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6437$1974_Y - end - attribute \src "ls180.v:6437.43-6437.148" - cell $and $and$ls180.v:6437$1976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6437$1974_Y - connect \B $eq$ls180.v:6437$1975_Y - connect \Y $and$ls180.v:6437$1976_Y - end - attribute \src "ls180.v:6438.44-6438.100" - cell $and $and$ls180.v:6438$1978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6438$1977_Y - connect \Y $and$ls180.v:6438$1978_Y - end - attribute \src "ls180.v:6438.43-6438.151" - cell $and $and$ls180.v:6438$1980 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6438$1978_Y - connect \B $eq$ls180.v:6438$1979_Y - connect \Y $and$ls180.v:6438$1980_Y - end - attribute \src "ls180.v:6440.44-6440.97" - cell $and $and$ls180.v:6440$1981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6440$1981_Y - end - attribute \src "ls180.v:6440.43-6440.148" - cell $and $and$ls180.v:6440$1983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6440$1981_Y - connect \B $eq$ls180.v:6440$1982_Y - connect \Y $and$ls180.v:6440$1983_Y - end - attribute \src "ls180.v:6441.44-6441.100" - cell $and $and$ls180.v:6441$1985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6441$1984_Y - connect \Y $and$ls180.v:6441$1985_Y - end - attribute \src "ls180.v:6441.43-6441.151" - cell $and $and$ls180.v:6441$1987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6441$1985_Y - connect \B $eq$ls180.v:6441$1986_Y - connect \Y $and$ls180.v:6441$1987_Y - end - attribute \src "ls180.v:6443.44-6443.97" - cell $and $and$ls180.v:6443$1988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6443$1988_Y - end - attribute \src "ls180.v:6443.43-6443.148" - cell $and $and$ls180.v:6443$1990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6443$1988_Y - connect \B $eq$ls180.v:6443$1989_Y - connect \Y $and$ls180.v:6443$1990_Y - end - attribute \src "ls180.v:6444.44-6444.100" - cell $and $and$ls180.v:6444$1992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6444$1991_Y - connect \Y $and$ls180.v:6444$1992_Y - end - attribute \src "ls180.v:6444.43-6444.151" - cell $and $and$ls180.v:6444$1994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6444$1992_Y - connect \B $eq$ls180.v:6444$1993_Y - connect \Y $and$ls180.v:6444$1994_Y - end - attribute \src "ls180.v:6446.44-6446.97" - cell $and $and$ls180.v:6446$1995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6446$1995_Y - end - attribute \src "ls180.v:6446.43-6446.148" - cell $and $and$ls180.v:6446$1997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6446$1995_Y - connect \B $eq$ls180.v:6446$1996_Y - connect \Y $and$ls180.v:6446$1997_Y - end - attribute \src "ls180.v:6447.44-6447.100" - cell $and $and$ls180.v:6447$1999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6447$1998_Y - connect \Y $and$ls180.v:6447$1999_Y - end - attribute \src "ls180.v:6447.43-6447.151" - cell $and $and$ls180.v:6447$2001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6447$1999_Y - connect \B $eq$ls180.v:6447$2000_Y - connect \Y $and$ls180.v:6447$2001_Y - end - attribute \src "ls180.v:6471.44-6471.97" - cell $and $and$ls180.v:6471$2003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6471$2003_Y - end - attribute \src "ls180.v:6471.43-6471.147" - cell $and $and$ls180.v:6471$2005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6471$2003_Y - connect \B $eq$ls180.v:6471$2004_Y - connect \Y $and$ls180.v:6471$2005_Y - end - attribute \src "ls180.v:6472.44-6472.100" - cell $and $and$ls180.v:6472$2007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6472$2006_Y - connect \Y $and$ls180.v:6472$2007_Y - end - attribute \src "ls180.v:6472.43-6472.150" - cell $and $and$ls180.v:6472$2009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6472$2007_Y - connect \B $eq$ls180.v:6472$2008_Y - connect \Y $and$ls180.v:6472$2009_Y - end - attribute \src "ls180.v:6474.49-6474.102" - cell $and $and$ls180.v:6474$2010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6474$2010_Y - end - attribute \src "ls180.v:6474.48-6474.152" - cell $and $and$ls180.v:6474$2012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6474$2010_Y - connect \B $eq$ls180.v:6474$2011_Y - connect \Y $and$ls180.v:6474$2012_Y - end - attribute \src "ls180.v:6475.49-6475.105" - cell $and $and$ls180.v:6475$2014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6475$2013_Y - connect \Y $and$ls180.v:6475$2014_Y - end - attribute \src "ls180.v:6475.48-6475.155" - cell $and $and$ls180.v:6475$2016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6475$2014_Y - connect \B $eq$ls180.v:6475$2015_Y - connect \Y $and$ls180.v:6475$2016_Y - end - attribute \src "ls180.v:6477.49-6477.102" - cell $and $and$ls180.v:6477$2017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6477$2017_Y - end - attribute \src "ls180.v:6477.48-6477.152" - cell $and $and$ls180.v:6477$2019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6477$2017_Y - connect \B $eq$ls180.v:6477$2018_Y - connect \Y $and$ls180.v:6477$2019_Y - end - attribute \src "ls180.v:6478.49-6478.105" - cell $and $and$ls180.v:6478$2021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6478$2020_Y - connect \Y $and$ls180.v:6478$2021_Y - end - attribute \src "ls180.v:6478.48-6478.155" - cell $and $and$ls180.v:6478$2023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6478$2021_Y - connect \B $eq$ls180.v:6478$2022_Y - connect \Y $and$ls180.v:6478$2023_Y - end - attribute \src "ls180.v:6480.42-6480.95" - cell $and $and$ls180.v:6480$2024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6480$2024_Y - end - attribute \src "ls180.v:6480.41-6480.145" - cell $and $and$ls180.v:6480$2026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6480$2024_Y - connect \B $eq$ls180.v:6480$2025_Y - connect \Y $and$ls180.v:6480$2026_Y - end - attribute \src "ls180.v:6481.42-6481.98" - cell $and $and$ls180.v:6481$2028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6481$2027_Y - connect \Y $and$ls180.v:6481$2028_Y - end - attribute \src "ls180.v:6481.41-6481.148" - cell $and $and$ls180.v:6481$2030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6481$2028_Y - connect \B $eq$ls180.v:6481$2029_Y - connect \Y $and$ls180.v:6481$2030_Y - end - attribute \src "ls180.v:6488.46-6488.99" - cell $and $and$ls180.v:6488$2032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6488$2032_Y - end - attribute \src "ls180.v:6488.45-6488.149" - cell $and $and$ls180.v:6488$2034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6488$2032_Y - connect \B $eq$ls180.v:6488$2033_Y - connect \Y $and$ls180.v:6488$2034_Y - end - attribute \src "ls180.v:6489.46-6489.102" - cell $and $and$ls180.v:6489$2036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6489$2035_Y - connect \Y $and$ls180.v:6489$2036_Y - end - attribute \src "ls180.v:6489.45-6489.152" - cell $and $and$ls180.v:6489$2038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6489$2036_Y - connect \B $eq$ls180.v:6489$2037_Y - connect \Y $and$ls180.v:6489$2038_Y - end - attribute \src "ls180.v:6491.50-6491.103" - cell $and $and$ls180.v:6491$2039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6491$2039_Y - end - attribute \src "ls180.v:6491.49-6491.153" - cell $and $and$ls180.v:6491$2041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6491$2039_Y - connect \B $eq$ls180.v:6491$2040_Y - connect \Y $and$ls180.v:6491$2041_Y - end - attribute \src "ls180.v:6492.50-6492.106" - cell $and $and$ls180.v:6492$2043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6492$2042_Y - connect \Y $and$ls180.v:6492$2043_Y - end - attribute \src "ls180.v:6492.49-6492.156" - cell $and $and$ls180.v:6492$2045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6492$2043_Y - connect \B $eq$ls180.v:6492$2044_Y - connect \Y $and$ls180.v:6492$2045_Y - end - attribute \src "ls180.v:6494.40-6494.93" - cell $and $and$ls180.v:6494$2046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6494$2046_Y - end - attribute \src "ls180.v:6494.39-6494.143" - cell $and $and$ls180.v:6494$2048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6494$2046_Y - connect \B $eq$ls180.v:6494$2047_Y - connect \Y $and$ls180.v:6494$2048_Y - end - attribute \src "ls180.v:6495.40-6495.96" - cell $and $and$ls180.v:6495$2050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6495$2049_Y - connect \Y $and$ls180.v:6495$2050_Y - end - attribute \src "ls180.v:6495.39-6495.146" - cell $and $and$ls180.v:6495$2052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6495$2050_Y - connect \B $eq$ls180.v:6495$2051_Y - connect \Y $and$ls180.v:6495$2052_Y - end - attribute \src "ls180.v:6497.50-6497.103" - cell $and $and$ls180.v:6497$2053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6497$2053_Y - end - attribute \src "ls180.v:6497.49-6497.153" - cell $and $and$ls180.v:6497$2055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6497$2053_Y - connect \B $eq$ls180.v:6497$2054_Y - connect \Y $and$ls180.v:6497$2055_Y - end - attribute \src "ls180.v:6498.50-6498.106" - cell $and $and$ls180.v:6498$2057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6498$2056_Y - connect \Y $and$ls180.v:6498$2057_Y - end - attribute \src "ls180.v:6498.49-6498.156" - cell $and $and$ls180.v:6498$2059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6498$2057_Y - connect \B $eq$ls180.v:6498$2058_Y - connect \Y $and$ls180.v:6498$2059_Y - end - attribute \src "ls180.v:6500.50-6500.103" - cell $and $and$ls180.v:6500$2060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6500$2060_Y - end - attribute \src "ls180.v:6500.49-6500.153" - cell $and $and$ls180.v:6500$2062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6500$2060_Y - connect \B $eq$ls180.v:6500$2061_Y - connect \Y $and$ls180.v:6500$2062_Y - end - attribute \src "ls180.v:6501.50-6501.106" - cell $and $and$ls180.v:6501$2064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6501$2063_Y - connect \Y $and$ls180.v:6501$2064_Y - end - attribute \src "ls180.v:6501.49-6501.156" - cell $and $and$ls180.v:6501$2066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6501$2064_Y - connect \B $eq$ls180.v:6501$2065_Y - connect \Y $and$ls180.v:6501$2066_Y - end - attribute \src "ls180.v:6503.51-6503.104" - cell $and $and$ls180.v:6503$2067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6503$2067_Y - end - attribute \src "ls180.v:6503.50-6503.154" - cell $and $and$ls180.v:6503$2069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6503$2067_Y - connect \B $eq$ls180.v:6503$2068_Y - connect \Y $and$ls180.v:6503$2069_Y - end - attribute \src "ls180.v:6504.51-6504.107" - cell $and $and$ls180.v:6504$2071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6504$2070_Y - connect \Y $and$ls180.v:6504$2071_Y - end - attribute \src "ls180.v:6504.50-6504.157" - cell $and $and$ls180.v:6504$2073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6504$2071_Y - connect \B $eq$ls180.v:6504$2072_Y - connect \Y $and$ls180.v:6504$2073_Y - end - attribute \src "ls180.v:6506.49-6506.102" - cell $and $and$ls180.v:6506$2074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6506$2074_Y - end - attribute \src "ls180.v:6506.48-6506.152" - cell $and $and$ls180.v:6506$2076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6506$2074_Y - connect \B $eq$ls180.v:6506$2075_Y - connect \Y $and$ls180.v:6506$2076_Y - end - attribute \src "ls180.v:6507.49-6507.105" - cell $and $and$ls180.v:6507$2078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6507$2077_Y - connect \Y $and$ls180.v:6507$2078_Y - end - attribute \src "ls180.v:6507.48-6507.155" - cell $and $and$ls180.v:6507$2080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6507$2078_Y - connect \B $eq$ls180.v:6507$2079_Y - connect \Y $and$ls180.v:6507$2080_Y - end - attribute \src "ls180.v:6509.49-6509.102" - cell $and $and$ls180.v:6509$2081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6509$2081_Y - end - attribute \src "ls180.v:6509.48-6509.152" - cell $and $and$ls180.v:6509$2083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6509$2081_Y - connect \B $eq$ls180.v:6509$2082_Y - connect \Y $and$ls180.v:6509$2083_Y - end - attribute \src "ls180.v:6510.49-6510.105" - cell $and $and$ls180.v:6510$2085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6510$2084_Y - connect \Y $and$ls180.v:6510$2085_Y - end - attribute \src "ls180.v:6510.48-6510.155" - cell $and $and$ls180.v:6510$2087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6510$2085_Y - connect \B $eq$ls180.v:6510$2086_Y - connect \Y $and$ls180.v:6510$2087_Y - end - attribute \src "ls180.v:6512.49-6512.102" - cell $and $and$ls180.v:6512$2088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6512$2088_Y - end - attribute \src "ls180.v:6512.48-6512.152" - cell $and $and$ls180.v:6512$2090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6512$2088_Y - connect \B $eq$ls180.v:6512$2089_Y - connect \Y $and$ls180.v:6512$2090_Y - end - attribute \src "ls180.v:6513.49-6513.105" - cell $and $and$ls180.v:6513$2092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6513$2091_Y - connect \Y $and$ls180.v:6513$2092_Y - end - attribute \src "ls180.v:6513.48-6513.155" - cell $and $and$ls180.v:6513$2094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6513$2092_Y - connect \B $eq$ls180.v:6513$2093_Y - connect \Y $and$ls180.v:6513$2094_Y - end - attribute \src "ls180.v:6515.49-6515.102" - cell $and $and$ls180.v:6515$2095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6515$2095_Y - end - attribute \src "ls180.v:6515.48-6515.152" - cell $and $and$ls180.v:6515$2097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6515$2095_Y - connect \B $eq$ls180.v:6515$2096_Y - connect \Y $and$ls180.v:6515$2097_Y - end - attribute \src "ls180.v:6516.49-6516.105" - cell $and $and$ls180.v:6516$2099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6516$2098_Y - connect \Y $and$ls180.v:6516$2099_Y - end - attribute \src "ls180.v:6516.48-6516.155" - cell $and $and$ls180.v:6516$2101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6516$2099_Y - connect \B $eq$ls180.v:6516$2100_Y - connect \Y $and$ls180.v:6516$2101_Y - end - attribute \src "ls180.v:6533.42-6533.97" - cell $and $and$ls180.v:6533$2103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6533$2103_Y - end - attribute \src "ls180.v:6533.41-6533.148" - cell $and $and$ls180.v:6533$2105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6533$2103_Y - connect \B $eq$ls180.v:6533$2104_Y - connect \Y $and$ls180.v:6533$2105_Y - end - attribute \src "ls180.v:6534.42-6534.100" - cell $and $and$ls180.v:6534$2107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6534$2106_Y - connect \Y $and$ls180.v:6534$2107_Y - end - attribute \src "ls180.v:6534.41-6534.151" - cell $and $and$ls180.v:6534$2109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6534$2107_Y - connect \B $eq$ls180.v:6534$2108_Y - connect \Y $and$ls180.v:6534$2109_Y - end - attribute \src "ls180.v:6536.42-6536.97" - cell $and $and$ls180.v:6536$2110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6536$2110_Y - end - attribute \src "ls180.v:6536.41-6536.148" - cell $and $and$ls180.v:6536$2112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6536$2110_Y - connect \B $eq$ls180.v:6536$2111_Y - connect \Y $and$ls180.v:6536$2112_Y - end - attribute \src "ls180.v:6537.42-6537.100" - cell $and $and$ls180.v:6537$2114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6537$2113_Y - connect \Y $and$ls180.v:6537$2114_Y - end - attribute \src "ls180.v:6537.41-6537.151" - cell $and $and$ls180.v:6537$2116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6537$2114_Y - connect \B $eq$ls180.v:6537$2115_Y - connect \Y $and$ls180.v:6537$2116_Y - end - attribute \src "ls180.v:6539.40-6539.95" - cell $and $and$ls180.v:6539$2117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6539$2117_Y - end - attribute \src "ls180.v:6539.39-6539.146" - cell $and $and$ls180.v:6539$2119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6539$2117_Y - connect \B $eq$ls180.v:6539$2118_Y - connect \Y $and$ls180.v:6539$2119_Y - end - attribute \src "ls180.v:6540.40-6540.98" - cell $and $and$ls180.v:6540$2121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6540$2120_Y - connect \Y $and$ls180.v:6540$2121_Y - end - attribute \src "ls180.v:6540.39-6540.149" - cell $and $and$ls180.v:6540$2123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6540$2121_Y - connect \B $eq$ls180.v:6540$2122_Y - connect \Y $and$ls180.v:6540$2123_Y - end - attribute \src "ls180.v:6542.39-6542.94" - cell $and $and$ls180.v:6542$2124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6542$2124_Y - end - attribute \src "ls180.v:6542.38-6542.145" - cell $and $and$ls180.v:6542$2126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6542$2124_Y - connect \B $eq$ls180.v:6542$2125_Y - connect \Y $and$ls180.v:6542$2126_Y - end - attribute \src "ls180.v:6543.39-6543.97" - cell $and $and$ls180.v:6543$2128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6543$2127_Y - connect \Y $and$ls180.v:6543$2128_Y - end - attribute \src "ls180.v:6543.38-6543.148" - cell $and $and$ls180.v:6543$2130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6543$2128_Y - connect \B $eq$ls180.v:6543$2129_Y - connect \Y $and$ls180.v:6543$2130_Y - end - attribute \src "ls180.v:6545.38-6545.93" - cell $and $and$ls180.v:6545$2131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6545$2131_Y - end - attribute \src "ls180.v:6545.37-6545.144" - cell $and $and$ls180.v:6545$2133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6545$2131_Y - connect \B $eq$ls180.v:6545$2132_Y - connect \Y $and$ls180.v:6545$2133_Y - end - attribute \src "ls180.v:6546.38-6546.96" - cell $and $and$ls180.v:6546$2135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6546$2134_Y - connect \Y $and$ls180.v:6546$2135_Y - end - attribute \src "ls180.v:6546.37-6546.147" - cell $and $and$ls180.v:6546$2137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6546$2135_Y - connect \B $eq$ls180.v:6546$2136_Y - connect \Y $and$ls180.v:6546$2137_Y - end - attribute \src "ls180.v:6548.37-6548.92" - cell $and $and$ls180.v:6548$2138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6548$2138_Y - end - attribute \src "ls180.v:6548.36-6548.143" - cell $and $and$ls180.v:6548$2140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6548$2138_Y - connect \B $eq$ls180.v:6548$2139_Y - connect \Y $and$ls180.v:6548$2140_Y - end - attribute \src "ls180.v:6549.37-6549.95" - cell $and $and$ls180.v:6549$2142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6549$2141_Y - connect \Y $and$ls180.v:6549$2142_Y - end - attribute \src "ls180.v:6549.36-6549.146" - cell $and $and$ls180.v:6549$2144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6549$2142_Y - connect \B $eq$ls180.v:6549$2143_Y - connect \Y $and$ls180.v:6549$2144_Y - end - attribute \src "ls180.v:6551.43-6551.98" - cell $and $and$ls180.v:6551$2145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6551$2145_Y - end - attribute \src "ls180.v:6551.42-6551.149" - cell $and $and$ls180.v:6551$2147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6551$2145_Y - connect \B $eq$ls180.v:6551$2146_Y - connect \Y $and$ls180.v:6551$2147_Y - end - attribute \src "ls180.v:6552.43-6552.101" - cell $and $and$ls180.v:6552$2149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6552$2148_Y - connect \Y $and$ls180.v:6552$2149_Y - end - attribute \src "ls180.v:6552.42-6552.152" - cell $and $and$ls180.v:6552$2151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6552$2149_Y - connect \B $eq$ls180.v:6552$2150_Y - connect \Y $and$ls180.v:6552$2151_Y - end - attribute \src "ls180.v:6573.42-6573.97" - cell $and $and$ls180.v:6573$2154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6573$2154_Y - end - attribute \src "ls180.v:6573.41-6573.148" - cell $and $and$ls180.v:6573$2156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6573$2154_Y - connect \B $eq$ls180.v:6573$2155_Y - connect \Y $and$ls180.v:6573$2156_Y - end - attribute \src "ls180.v:6574.42-6574.100" - cell $and $and$ls180.v:6574$2158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6574$2157_Y - connect \Y $and$ls180.v:6574$2158_Y - end - attribute \src "ls180.v:6574.41-6574.151" - cell $and $and$ls180.v:6574$2160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6574$2158_Y - connect \B $eq$ls180.v:6574$2159_Y - connect \Y $and$ls180.v:6574$2160_Y - end - attribute \src "ls180.v:6576.42-6576.97" - cell $and $and$ls180.v:6576$2161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6576$2161_Y - end - attribute \src "ls180.v:6576.41-6576.148" - cell $and $and$ls180.v:6576$2163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6576$2161_Y - connect \B $eq$ls180.v:6576$2162_Y - connect \Y $and$ls180.v:6576$2163_Y - end - attribute \src "ls180.v:6577.42-6577.100" - cell $and $and$ls180.v:6577$2165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6577$2164_Y - connect \Y $and$ls180.v:6577$2165_Y - end - attribute \src "ls180.v:6577.41-6577.151" - cell $and $and$ls180.v:6577$2167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6577$2165_Y - connect \B $eq$ls180.v:6577$2166_Y - connect \Y $and$ls180.v:6577$2167_Y - end - attribute \src "ls180.v:6579.40-6579.95" - cell $and $and$ls180.v:6579$2168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6579$2168_Y - end - attribute \src "ls180.v:6579.39-6579.146" - cell $and $and$ls180.v:6579$2170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6579$2168_Y - connect \B $eq$ls180.v:6579$2169_Y - connect \Y $and$ls180.v:6579$2170_Y - end - attribute \src "ls180.v:6580.40-6580.98" - cell $and $and$ls180.v:6580$2172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6580$2171_Y - connect \Y $and$ls180.v:6580$2172_Y - end - attribute \src "ls180.v:6580.39-6580.149" - cell $and $and$ls180.v:6580$2174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6580$2172_Y - connect \B $eq$ls180.v:6580$2173_Y - connect \Y $and$ls180.v:6580$2174_Y - end - attribute \src "ls180.v:6582.39-6582.94" - cell $and $and$ls180.v:6582$2175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6582$2175_Y - end - attribute \src "ls180.v:6582.38-6582.145" - cell $and $and$ls180.v:6582$2177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6582$2175_Y - connect \B $eq$ls180.v:6582$2176_Y - connect \Y $and$ls180.v:6582$2177_Y - end - attribute \src "ls180.v:6583.39-6583.97" - cell $and $and$ls180.v:6583$2179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6583$2178_Y - connect \Y $and$ls180.v:6583$2179_Y - end - attribute \src "ls180.v:6583.38-6583.148" - cell $and $and$ls180.v:6583$2181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6583$2179_Y - connect \B $eq$ls180.v:6583$2180_Y - connect \Y $and$ls180.v:6583$2181_Y - end - attribute \src "ls180.v:6585.38-6585.93" - cell $and $and$ls180.v:6585$2182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6585$2182_Y - end - attribute \src "ls180.v:6585.37-6585.144" - cell $and $and$ls180.v:6585$2184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6585$2182_Y - connect \B $eq$ls180.v:6585$2183_Y - connect \Y $and$ls180.v:6585$2184_Y - end - attribute \src "ls180.v:6586.38-6586.96" - cell $and $and$ls180.v:6586$2186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6586$2185_Y - connect \Y $and$ls180.v:6586$2186_Y - end - attribute \src "ls180.v:6586.37-6586.147" - cell $and $and$ls180.v:6586$2188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6586$2186_Y - connect \B $eq$ls180.v:6586$2187_Y - connect \Y $and$ls180.v:6586$2188_Y - end - attribute \src "ls180.v:6588.37-6588.92" - cell $and $and$ls180.v:6588$2189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6588$2189_Y - end - attribute \src "ls180.v:6588.36-6588.143" - cell $and $and$ls180.v:6588$2191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6588$2189_Y - connect \B $eq$ls180.v:6588$2190_Y - connect \Y $and$ls180.v:6588$2191_Y - end - attribute \src "ls180.v:6589.37-6589.95" - cell $and $and$ls180.v:6589$2193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6589$2192_Y - connect \Y $and$ls180.v:6589$2193_Y - end - attribute \src "ls180.v:6589.36-6589.146" - cell $and $and$ls180.v:6589$2195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6589$2193_Y - connect \B $eq$ls180.v:6589$2194_Y - connect \Y $and$ls180.v:6589$2195_Y - end - attribute \src "ls180.v:6591.43-6591.98" - cell $and $and$ls180.v:6591$2196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6591$2196_Y - end - attribute \src "ls180.v:6591.42-6591.149" - cell $and $and$ls180.v:6591$2198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6591$2196_Y - connect \B $eq$ls180.v:6591$2197_Y - connect \Y $and$ls180.v:6591$2198_Y - end - attribute \src "ls180.v:6592.43-6592.101" - cell $and $and$ls180.v:6592$2200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6592$2199_Y - connect \Y $and$ls180.v:6592$2200_Y - end - attribute \src "ls180.v:6592.42-6592.152" - cell $and $and$ls180.v:6592$2202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6592$2200_Y - connect \B $eq$ls180.v:6592$2201_Y - connect \Y $and$ls180.v:6592$2202_Y - end - attribute \src "ls180.v:6594.46-6594.101" - cell $and $and$ls180.v:6594$2203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6594$2203_Y - end - attribute \src "ls180.v:6594.45-6594.152" - cell $and $and$ls180.v:6594$2205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6594$2203_Y - connect \B $eq$ls180.v:6594$2204_Y - connect \Y $and$ls180.v:6594$2205_Y - end - attribute \src "ls180.v:6595.46-6595.104" - cell $and $and$ls180.v:6595$2207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6595$2206_Y - connect \Y $and$ls180.v:6595$2207_Y - end - attribute \src "ls180.v:6595.45-6595.155" - cell $and $and$ls180.v:6595$2209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6595$2207_Y - connect \B $eq$ls180.v:6595$2208_Y - connect \Y $and$ls180.v:6595$2209_Y - end - attribute \src "ls180.v:6597.46-6597.101" - cell $and $and$ls180.v:6597$2210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6597$2210_Y - end - attribute \src "ls180.v:6597.45-6597.152" - cell $and $and$ls180.v:6597$2212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6597$2210_Y - connect \B $eq$ls180.v:6597$2211_Y - connect \Y $and$ls180.v:6597$2212_Y - end - attribute \src "ls180.v:6598.46-6598.104" - cell $and $and$ls180.v:6598$2214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6598$2213_Y - connect \Y $and$ls180.v:6598$2214_Y - end - attribute \src "ls180.v:6598.45-6598.155" - cell $and $and$ls180.v:6598$2216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6598$2214_Y - connect \B $eq$ls180.v:6598$2215_Y - connect \Y $and$ls180.v:6598$2216_Y - end - attribute \src "ls180.v:6621.39-6621.94" - cell $and $and$ls180.v:6621$2219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6621$2219_Y - end - attribute \src "ls180.v:6621.38-6621.145" - cell $and $and$ls180.v:6621$2221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6621$2219_Y - connect \B $eq$ls180.v:6621$2220_Y - connect \Y $and$ls180.v:6621$2221_Y - end - attribute \src "ls180.v:6622.39-6622.97" - cell $and $and$ls180.v:6622$2223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6622$2222_Y - connect \Y $and$ls180.v:6622$2223_Y - end - attribute \src "ls180.v:6622.38-6622.148" - cell $and $and$ls180.v:6622$2225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6622$2223_Y - connect \B $eq$ls180.v:6622$2224_Y - connect \Y $and$ls180.v:6622$2225_Y - end - attribute \src "ls180.v:6624.39-6624.94" - cell $and $and$ls180.v:6624$2226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6624$2226_Y - end - attribute \src "ls180.v:6624.38-6624.145" - cell $and $and$ls180.v:6624$2228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6624$2226_Y - connect \B $eq$ls180.v:6624$2227_Y - connect \Y $and$ls180.v:6624$2228_Y - end - attribute \src "ls180.v:6625.39-6625.97" - cell $and $and$ls180.v:6625$2230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6625$2229_Y - connect \Y $and$ls180.v:6625$2230_Y - end - attribute \src "ls180.v:6625.38-6625.148" - cell $and $and$ls180.v:6625$2232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6625$2230_Y - connect \B $eq$ls180.v:6625$2231_Y - connect \Y $and$ls180.v:6625$2232_Y - end - attribute \src "ls180.v:6627.39-6627.94" - cell $and $and$ls180.v:6627$2233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6627$2233_Y - end - attribute \src "ls180.v:6627.38-6627.145" - cell $and $and$ls180.v:6627$2235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6627$2233_Y - connect \B $eq$ls180.v:6627$2234_Y - connect \Y $and$ls180.v:6627$2235_Y - end - attribute \src "ls180.v:6628.39-6628.97" - cell $and $and$ls180.v:6628$2237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6628$2236_Y - connect \Y $and$ls180.v:6628$2237_Y - end - attribute \src "ls180.v:6628.38-6628.148" - cell $and $and$ls180.v:6628$2239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6628$2237_Y - connect \B $eq$ls180.v:6628$2238_Y - connect \Y $and$ls180.v:6628$2239_Y - end - attribute \src "ls180.v:6630.39-6630.94" - cell $and $and$ls180.v:6630$2240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6630$2240_Y - end - attribute \src "ls180.v:6630.38-6630.145" - cell $and $and$ls180.v:6630$2242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6630$2240_Y - connect \B $eq$ls180.v:6630$2241_Y - connect \Y $and$ls180.v:6630$2242_Y - end - attribute \src "ls180.v:6631.39-6631.97" - cell $and $and$ls180.v:6631$2244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6631$2243_Y - connect \Y $and$ls180.v:6631$2244_Y - end - attribute \src "ls180.v:6631.38-6631.148" - cell $and $and$ls180.v:6631$2246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6631$2244_Y - connect \B $eq$ls180.v:6631$2245_Y - connect \Y $and$ls180.v:6631$2246_Y - end - attribute \src "ls180.v:6633.41-6633.96" - cell $and $and$ls180.v:6633$2247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6633$2247_Y - end - attribute \src "ls180.v:6633.40-6633.147" - cell $and $and$ls180.v:6633$2249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6633$2247_Y - connect \B $eq$ls180.v:6633$2248_Y - connect \Y $and$ls180.v:6633$2249_Y - end - attribute \src "ls180.v:6634.41-6634.99" - cell $and $and$ls180.v:6634$2251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6634$2250_Y - connect \Y $and$ls180.v:6634$2251_Y - end - attribute \src "ls180.v:6634.40-6634.150" - cell $and $and$ls180.v:6634$2253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6634$2251_Y - connect \B $eq$ls180.v:6634$2252_Y - connect \Y $and$ls180.v:6634$2253_Y - end - attribute \src "ls180.v:6636.41-6636.96" - cell $and $and$ls180.v:6636$2254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6636$2254_Y - end - attribute \src "ls180.v:6636.40-6636.147" - cell $and $and$ls180.v:6636$2256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6636$2254_Y - connect \B $eq$ls180.v:6636$2255_Y - connect \Y $and$ls180.v:6636$2256_Y - end - attribute \src "ls180.v:6637.41-6637.99" - cell $and $and$ls180.v:6637$2258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6637$2257_Y - connect \Y $and$ls180.v:6637$2258_Y - end - attribute \src "ls180.v:6637.40-6637.150" - cell $and $and$ls180.v:6637$2260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6637$2258_Y - connect \B $eq$ls180.v:6637$2259_Y - connect \Y $and$ls180.v:6637$2260_Y - end - attribute \src "ls180.v:6639.41-6639.96" - cell $and $and$ls180.v:6639$2261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6639$2261_Y - end - attribute \src "ls180.v:6639.40-6639.147" - cell $and $and$ls180.v:6639$2263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6639$2261_Y - connect \B $eq$ls180.v:6639$2262_Y - connect \Y $and$ls180.v:6639$2263_Y - end - attribute \src "ls180.v:6640.41-6640.99" - cell $and $and$ls180.v:6640$2265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6640$2264_Y - connect \Y $and$ls180.v:6640$2265_Y - end - attribute \src "ls180.v:6640.40-6640.150" - cell $and $and$ls180.v:6640$2267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6640$2265_Y - connect \B $eq$ls180.v:6640$2266_Y - connect \Y $and$ls180.v:6640$2267_Y - end - attribute \src "ls180.v:6642.41-6642.96" - cell $and $and$ls180.v:6642$2268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6642$2268_Y - end - attribute \src "ls180.v:6642.40-6642.147" - cell $and $and$ls180.v:6642$2270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6642$2268_Y - connect \B $eq$ls180.v:6642$2269_Y - connect \Y $and$ls180.v:6642$2270_Y - end - attribute \src "ls180.v:6643.41-6643.99" - cell $and $and$ls180.v:6643$2272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6643$2271_Y - connect \Y $and$ls180.v:6643$2272_Y - end - attribute \src "ls180.v:6643.40-6643.150" - cell $and $and$ls180.v:6643$2274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6643$2272_Y - connect \B $eq$ls180.v:6643$2273_Y - connect \Y $and$ls180.v:6643$2274_Y - end - attribute \src "ls180.v:6645.37-6645.92" - cell $and $and$ls180.v:6645$2275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6645$2275_Y - end - attribute \src "ls180.v:6645.36-6645.143" - cell $and $and$ls180.v:6645$2277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6645$2275_Y - connect \B $eq$ls180.v:6645$2276_Y - connect \Y $and$ls180.v:6645$2277_Y - end - attribute \src "ls180.v:6646.37-6646.95" - cell $and $and$ls180.v:6646$2279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6646$2278_Y - connect \Y $and$ls180.v:6646$2279_Y - end - attribute \src "ls180.v:6646.36-6646.146" - cell $and $and$ls180.v:6646$2281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6646$2279_Y - connect \B $eq$ls180.v:6646$2280_Y - connect \Y $and$ls180.v:6646$2281_Y - end - attribute \src "ls180.v:6648.47-6648.102" - cell $and $and$ls180.v:6648$2282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6648$2282_Y - end - attribute \src "ls180.v:6648.46-6648.153" - cell $and $and$ls180.v:6648$2284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6648$2282_Y - connect \B $eq$ls180.v:6648$2283_Y - connect \Y $and$ls180.v:6648$2284_Y - end - attribute \src "ls180.v:6649.47-6649.105" - cell $and $and$ls180.v:6649$2286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6649$2285_Y - connect \Y $and$ls180.v:6649$2286_Y - end - attribute \src "ls180.v:6649.46-6649.156" - cell $and $and$ls180.v:6649$2288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6649$2286_Y - connect \B $eq$ls180.v:6649$2287_Y - connect \Y $and$ls180.v:6649$2288_Y - end - attribute \src "ls180.v:6651.40-6651.95" - cell $and $and$ls180.v:6651$2289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6651$2289_Y - end - attribute \src "ls180.v:6651.39-6651.147" - cell $and $and$ls180.v:6651$2291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6651$2289_Y - connect \B $eq$ls180.v:6651$2290_Y - connect \Y $and$ls180.v:6651$2291_Y - end - attribute \src "ls180.v:6652.40-6652.98" - cell $and $and$ls180.v:6652$2293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6652$2292_Y - connect \Y $and$ls180.v:6652$2293_Y - end - attribute \src "ls180.v:6652.39-6652.150" - cell $and $and$ls180.v:6652$2295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6652$2293_Y - connect \B $eq$ls180.v:6652$2294_Y - connect \Y $and$ls180.v:6652$2295_Y - end - attribute \src "ls180.v:6654.40-6654.95" - cell $and $and$ls180.v:6654$2296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6654$2296_Y - end - attribute \src "ls180.v:6654.39-6654.147" - cell $and $and$ls180.v:6654$2298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6654$2296_Y - connect \B $eq$ls180.v:6654$2297_Y - connect \Y $and$ls180.v:6654$2298_Y - end - attribute \src "ls180.v:6655.40-6655.98" - cell $and $and$ls180.v:6655$2300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6655$2299_Y - connect \Y $and$ls180.v:6655$2300_Y - end - attribute \src "ls180.v:6655.39-6655.150" - cell $and $and$ls180.v:6655$2302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6655$2300_Y - connect \B $eq$ls180.v:6655$2301_Y - connect \Y $and$ls180.v:6655$2302_Y - end - attribute \src "ls180.v:6657.40-6657.95" - cell $and $and$ls180.v:6657$2303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6657$2303_Y - end - attribute \src "ls180.v:6657.39-6657.147" - cell $and $and$ls180.v:6657$2305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6657$2303_Y - connect \B $eq$ls180.v:6657$2304_Y - connect \Y $and$ls180.v:6657$2305_Y - end - attribute \src "ls180.v:6658.40-6658.98" - cell $and $and$ls180.v:6658$2307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6658$2306_Y - connect \Y $and$ls180.v:6658$2307_Y - end - attribute \src "ls180.v:6658.39-6658.150" - cell $and $and$ls180.v:6658$2309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6658$2307_Y - connect \B $eq$ls180.v:6658$2308_Y - connect \Y $and$ls180.v:6658$2309_Y - end - attribute \src "ls180.v:6660.40-6660.95" - cell $and $and$ls180.v:6660$2310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6660$2310_Y - end - attribute \src "ls180.v:6660.39-6660.147" - cell $and $and$ls180.v:6660$2312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6660$2310_Y - connect \B $eq$ls180.v:6660$2311_Y - connect \Y $and$ls180.v:6660$2312_Y - end - attribute \src "ls180.v:6661.40-6661.98" - cell $and $and$ls180.v:6661$2314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6661$2313_Y - connect \Y $and$ls180.v:6661$2314_Y - end - attribute \src "ls180.v:6661.39-6661.150" - cell $and $and$ls180.v:6661$2316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6661$2314_Y - connect \B $eq$ls180.v:6661$2315_Y - connect \Y $and$ls180.v:6661$2316_Y - end - attribute \src "ls180.v:6663.52-6663.107" - cell $and $and$ls180.v:6663$2317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6663$2317_Y - end - attribute \src "ls180.v:6663.51-6663.159" - cell $and $and$ls180.v:6663$2319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6663$2317_Y - connect \B $eq$ls180.v:6663$2318_Y - connect \Y $and$ls180.v:6663$2319_Y - end - attribute \src "ls180.v:6664.52-6664.110" - cell $and $and$ls180.v:6664$2321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6664$2320_Y - connect \Y $and$ls180.v:6664$2321_Y - end - attribute \src "ls180.v:6664.51-6664.162" - cell $and $and$ls180.v:6664$2323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6664$2321_Y - connect \B $eq$ls180.v:6664$2322_Y - connect \Y $and$ls180.v:6664$2323_Y - end - attribute \src "ls180.v:6666.53-6666.108" - cell $and $and$ls180.v:6666$2324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6666$2324_Y - end - attribute \src "ls180.v:6666.52-6666.160" - cell $and $and$ls180.v:6666$2326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6666$2324_Y - connect \B $eq$ls180.v:6666$2325_Y - connect \Y $and$ls180.v:6666$2326_Y - end - attribute \src "ls180.v:6667.53-6667.111" - cell $and $and$ls180.v:6667$2328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6667$2327_Y - connect \Y $and$ls180.v:6667$2328_Y - end - attribute \src "ls180.v:6667.52-6667.163" - cell $and $and$ls180.v:6667$2330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6667$2328_Y - connect \B $eq$ls180.v:6667$2329_Y - connect \Y $and$ls180.v:6667$2330_Y - end - attribute \src "ls180.v:6669.44-6669.99" - cell $and $and$ls180.v:6669$2331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6669$2331_Y - end - attribute \src "ls180.v:6669.43-6669.151" - cell $and $and$ls180.v:6669$2333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6669$2331_Y - connect \B $eq$ls180.v:6669$2332_Y - connect \Y $and$ls180.v:6669$2333_Y - end - attribute \src "ls180.v:6670.44-6670.102" - cell $and $and$ls180.v:6670$2335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6670$2334_Y - connect \Y $and$ls180.v:6670$2335_Y - end - attribute \src "ls180.v:6670.43-6670.154" - cell $and $and$ls180.v:6670$2337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6670$2335_Y - connect \B $eq$ls180.v:6670$2336_Y - connect \Y $and$ls180.v:6670$2337_Y - end - attribute \src "ls180.v:6689.30-6689.85" - cell $and $and$ls180.v:6689$2339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6689$2339_Y - end - attribute \src "ls180.v:6689.29-6689.136" - cell $and $and$ls180.v:6689$2341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6689$2339_Y - connect \B $eq$ls180.v:6689$2340_Y - connect \Y $and$ls180.v:6689$2341_Y - end - attribute \src "ls180.v:6690.30-6690.88" - cell $and $and$ls180.v:6690$2343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6690$2342_Y - connect \Y $and$ls180.v:6690$2343_Y - end - attribute \src "ls180.v:6690.29-6690.139" - cell $and $and$ls180.v:6690$2345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6690$2343_Y - connect \B $eq$ls180.v:6690$2344_Y - connect \Y $and$ls180.v:6690$2345_Y - end - attribute \src "ls180.v:6692.40-6692.95" - cell $and $and$ls180.v:6692$2346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6692$2346_Y - end - attribute \src "ls180.v:6692.39-6692.146" - cell $and $and$ls180.v:6692$2348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6692$2346_Y - connect \B $eq$ls180.v:6692$2347_Y - connect \Y $and$ls180.v:6692$2348_Y - end - attribute \src "ls180.v:6693.40-6693.98" - cell $and $and$ls180.v:6693$2350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6693$2349_Y - connect \Y $and$ls180.v:6693$2350_Y - end - attribute \src "ls180.v:6693.39-6693.149" - cell $and $and$ls180.v:6693$2352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6693$2350_Y - connect \B $eq$ls180.v:6693$2351_Y - connect \Y $and$ls180.v:6693$2352_Y - end - attribute \src "ls180.v:6695.41-6695.96" - cell $and $and$ls180.v:6695$2353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6695$2353_Y - end - attribute \src "ls180.v:6695.40-6695.147" - cell $and $and$ls180.v:6695$2355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6695$2353_Y - connect \B $eq$ls180.v:6695$2354_Y - connect \Y $and$ls180.v:6695$2355_Y - end - attribute \src "ls180.v:6696.41-6696.99" - cell $and $and$ls180.v:6696$2357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6696$2356_Y - connect \Y $and$ls180.v:6696$2357_Y - end - attribute \src "ls180.v:6696.40-6696.150" - cell $and $and$ls180.v:6696$2359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6696$2357_Y - connect \B $eq$ls180.v:6696$2358_Y - connect \Y $and$ls180.v:6696$2359_Y - end - attribute \src "ls180.v:6698.45-6698.100" - cell $and $and$ls180.v:6698$2360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6698$2360_Y - end - attribute \src "ls180.v:6698.44-6698.151" - cell $and $and$ls180.v:6698$2362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6698$2360_Y - connect \B $eq$ls180.v:6698$2361_Y - connect \Y $and$ls180.v:6698$2362_Y - end - attribute \src "ls180.v:6699.45-6699.103" - cell $and $and$ls180.v:6699$2364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6699$2363_Y - connect \Y $and$ls180.v:6699$2364_Y - end - attribute \src "ls180.v:6699.44-6699.154" - cell $and $and$ls180.v:6699$2366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6699$2364_Y - connect \B $eq$ls180.v:6699$2365_Y - connect \Y $and$ls180.v:6699$2366_Y - end - attribute \src "ls180.v:6701.46-6701.101" - cell $and $and$ls180.v:6701$2367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6701$2367_Y - end - attribute \src "ls180.v:6701.45-6701.152" - cell $and $and$ls180.v:6701$2369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6701$2367_Y - connect \B $eq$ls180.v:6701$2368_Y - connect \Y $and$ls180.v:6701$2369_Y - end - attribute \src "ls180.v:6702.46-6702.104" - cell $and $and$ls180.v:6702$2371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6702$2370_Y - connect \Y $and$ls180.v:6702$2371_Y - end - attribute \src "ls180.v:6702.45-6702.155" - cell $and $and$ls180.v:6702$2373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6702$2371_Y - connect \B $eq$ls180.v:6702$2372_Y - connect \Y $and$ls180.v:6702$2373_Y - end - attribute \src "ls180.v:6704.44-6704.99" - cell $and $and$ls180.v:6704$2374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6704$2374_Y - end - attribute \src "ls180.v:6704.43-6704.150" - cell $and $and$ls180.v:6704$2376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6704$2374_Y - connect \B $eq$ls180.v:6704$2375_Y - connect \Y $and$ls180.v:6704$2376_Y - end - attribute \src "ls180.v:6705.44-6705.102" - cell $and $and$ls180.v:6705$2378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6705$2377_Y - connect \Y $and$ls180.v:6705$2378_Y - end - attribute \src "ls180.v:6705.43-6705.153" - cell $and $and$ls180.v:6705$2380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6705$2378_Y - connect \B $eq$ls180.v:6705$2379_Y - connect \Y $and$ls180.v:6705$2380_Y - end - attribute \src "ls180.v:6707.41-6707.96" - cell $and $and$ls180.v:6707$2381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6707$2381_Y - end - attribute \src "ls180.v:6707.40-6707.147" - cell $and $and$ls180.v:6707$2383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6707$2381_Y - connect \B $eq$ls180.v:6707$2382_Y - connect \Y $and$ls180.v:6707$2383_Y - end - attribute \src "ls180.v:6708.41-6708.99" - cell $and $and$ls180.v:6708$2385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6708$2384_Y - connect \Y $and$ls180.v:6708$2385_Y - end - attribute \src "ls180.v:6708.40-6708.150" - cell $and $and$ls180.v:6708$2387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6708$2385_Y - connect \B $eq$ls180.v:6708$2386_Y - connect \Y $and$ls180.v:6708$2387_Y - end - attribute \src "ls180.v:6710.40-6710.95" - cell $and $and$ls180.v:6710$2388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6710$2388_Y - end - attribute \src "ls180.v:6710.39-6710.146" - cell $and $and$ls180.v:6710$2390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6710$2388_Y - connect \B $eq$ls180.v:6710$2389_Y - connect \Y $and$ls180.v:6710$2390_Y - end - attribute \src "ls180.v:6711.40-6711.98" - cell $and $and$ls180.v:6711$2392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6711$2391_Y - connect \Y $and$ls180.v:6711$2392_Y - end - attribute \src "ls180.v:6711.39-6711.149" - cell $and $and$ls180.v:6711$2394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6711$2392_Y - connect \B $eq$ls180.v:6711$2393_Y - connect \Y $and$ls180.v:6711$2394_Y - end - attribute \src "ls180.v:6723.46-6723.101" - cell $and $and$ls180.v:6723$2396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6723$2396_Y - end - attribute \src "ls180.v:6723.45-6723.152" - cell $and $and$ls180.v:6723$2398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6723$2396_Y - connect \B $eq$ls180.v:6723$2397_Y - connect \Y $and$ls180.v:6723$2398_Y - end - attribute \src "ls180.v:6724.46-6724.104" - cell $and $and$ls180.v:6724$2400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6724$2399_Y - connect \Y $and$ls180.v:6724$2400_Y - end - attribute \src "ls180.v:6724.45-6724.155" - cell $and $and$ls180.v:6724$2402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6724$2400_Y - connect \B $eq$ls180.v:6724$2401_Y - connect \Y $and$ls180.v:6724$2402_Y - end - attribute \src "ls180.v:6726.46-6726.101" - cell $and $and$ls180.v:6726$2403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6726$2403_Y - end - attribute \src "ls180.v:6726.45-6726.152" - cell $and $and$ls180.v:6726$2405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6726$2403_Y - connect \B $eq$ls180.v:6726$2404_Y - connect \Y $and$ls180.v:6726$2405_Y - end - attribute \src "ls180.v:6727.46-6727.104" - cell $and $and$ls180.v:6727$2407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6727$2406_Y - connect \Y $and$ls180.v:6727$2407_Y - end - attribute \src "ls180.v:6727.45-6727.155" - cell $and $and$ls180.v:6727$2409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6727$2407_Y - connect \B $eq$ls180.v:6727$2408_Y - connect \Y $and$ls180.v:6727$2409_Y - end - attribute \src "ls180.v:6729.46-6729.101" - cell $and $and$ls180.v:6729$2410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6729$2410_Y - end - attribute \src "ls180.v:6729.45-6729.152" - cell $and $and$ls180.v:6729$2412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6729$2410_Y - connect \B $eq$ls180.v:6729$2411_Y - connect \Y $and$ls180.v:6729$2412_Y - end - attribute \src "ls180.v:6730.46-6730.104" - cell $and $and$ls180.v:6730$2414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6730$2413_Y - connect \Y $and$ls180.v:6730$2414_Y - end - attribute \src "ls180.v:6730.45-6730.155" - cell $and $and$ls180.v:6730$2416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6730$2414_Y - connect \B $eq$ls180.v:6730$2415_Y - connect \Y $and$ls180.v:6730$2416_Y - end - attribute \src "ls180.v:6732.46-6732.101" - cell $and $and$ls180.v:6732$2417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6732$2417_Y - end - attribute \src "ls180.v:6732.45-6732.152" - cell $and $and$ls180.v:6732$2419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6732$2417_Y - connect \B $eq$ls180.v:6732$2418_Y - connect \Y $and$ls180.v:6732$2419_Y - end - attribute \src "ls180.v:6733.46-6733.104" - cell $and $and$ls180.v:6733$2421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6733$2420_Y - connect \Y $and$ls180.v:6733$2421_Y - end - attribute \src "ls180.v:6733.45-6733.155" - cell $and $and$ls180.v:6733$2423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6733$2421_Y - connect \B $eq$ls180.v:6733$2422_Y - connect \Y $and$ls180.v:6733$2423_Y - end - attribute \src "ls180.v:7114.109-7114.178" - cell $and $and$ls180.v:7114$2461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7114$2460_Y - connect \Y $and$ls180.v:7114$2461_Y - end - attribute \src "ls180.v:7114.184-7114.253" - cell $and $and$ls180.v:7114$2464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7114$2463_Y - connect \Y $and$ls180.v:7114$2464_Y - end - attribute \src "ls180.v:7114.259-7114.328" - cell $and $and$ls180.v:7114$2467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7114$2466_Y - connect \Y $and$ls180.v:7114$2467_Y - end - attribute \src "ls180.v:7114.40-7114.331" - cell $and $and$ls180.v:7114$2470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7114$2459_Y - connect \B $not$ls180.v:7114$2469_Y - connect \Y $and$ls180.v:7114$2470_Y - end - attribute \src "ls180.v:7114.39-7114.354" - cell $and $and$ls180.v:7114$2471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7114$2470_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7114$2471_Y - end - attribute \src "ls180.v:7138.109-7138.178" - cell $and $and$ls180.v:7138$2477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7138$2476_Y - connect \Y $and$ls180.v:7138$2477_Y - end - attribute \src "ls180.v:7138.184-7138.253" - cell $and $and$ls180.v:7138$2480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7138$2479_Y - connect \Y $and$ls180.v:7138$2480_Y - end - attribute \src "ls180.v:7138.259-7138.328" - cell $and $and$ls180.v:7138$2483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7138$2482_Y - connect \Y $and$ls180.v:7138$2483_Y - end - attribute \src "ls180.v:7138.40-7138.331" - cell $and $and$ls180.v:7138$2486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7138$2475_Y - connect \B $not$ls180.v:7138$2485_Y - connect \Y $and$ls180.v:7138$2486_Y - end - attribute \src "ls180.v:7138.39-7138.354" - cell $and $and$ls180.v:7138$2487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7138$2486_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7138$2487_Y - end - attribute \src "ls180.v:7162.109-7162.178" - cell $and $and$ls180.v:7162$2493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7162$2492_Y - connect \Y $and$ls180.v:7162$2493_Y - end - attribute \src "ls180.v:7162.184-7162.253" - cell $and $and$ls180.v:7162$2496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7162$2495_Y - connect \Y $and$ls180.v:7162$2496_Y - end - attribute \src "ls180.v:7162.259-7162.328" - cell $and $and$ls180.v:7162$2499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7162$2498_Y - connect \Y $and$ls180.v:7162$2499_Y - end - attribute \src "ls180.v:7162.40-7162.331" - cell $and $and$ls180.v:7162$2502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7162$2491_Y - connect \B $not$ls180.v:7162$2501_Y - connect \Y $and$ls180.v:7162$2502_Y - end - attribute \src "ls180.v:7162.39-7162.354" - cell $and $and$ls180.v:7162$2503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7162$2502_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7162$2503_Y - end - attribute \src "ls180.v:7186.109-7186.178" - cell $and $and$ls180.v:7186$2509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7186$2508_Y - connect \Y $and$ls180.v:7186$2509_Y - end - attribute \src "ls180.v:7186.184-7186.253" - cell $and $and$ls180.v:7186$2512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7186$2511_Y - connect \Y $and$ls180.v:7186$2512_Y - end - attribute \src "ls180.v:7186.259-7186.328" - cell $and $and$ls180.v:7186$2515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7186$2514_Y - connect \Y $and$ls180.v:7186$2515_Y - end - attribute \src "ls180.v:7186.40-7186.331" - cell $and $and$ls180.v:7186$2518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7186$2507_Y - connect \B $not$ls180.v:7186$2517_Y - connect \Y $and$ls180.v:7186$2518_Y - end - attribute \src "ls180.v:7186.39-7186.354" - cell $and $and$ls180.v:7186$2519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7186$2518_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7186$2519_Y - end - attribute \src "ls180.v:7391.39-7391.104" - cell $and $and$ls180.v:7391$2531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7391$2531_Y - end - attribute \src "ls180.v:7391.38-7391.145" - cell $and $and$ls180.v:7391$2532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7391$2531_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7391$2532_Y - end - attribute \src "ls180.v:7394.39-7394.104" - cell $and $and$ls180.v:7394$2533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7394$2533_Y - end - attribute \src "ls180.v:7394.38-7394.145" - cell $and $and$ls180.v:7394$2534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7394$2533_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7394$2534_Y - end - attribute \src "ls180.v:7397.39-7397.82" - cell $and $and$ls180.v:7397$2535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7397$2535_Y - end - attribute \src "ls180.v:7397.38-7397.112" - cell $and $and$ls180.v:7397$2536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7397$2535_Y - connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7397$2536_Y - end - attribute \src "ls180.v:7408.39-7408.104" - cell $and $and$ls180.v:7408$2538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7408$2538_Y - end - attribute \src "ls180.v:7408.38-7408.145" - cell $and $and$ls180.v:7408$2539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7408$2538_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7408$2539_Y - end - attribute \src "ls180.v:7411.39-7411.104" - cell $and $and$ls180.v:7411$2540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7411$2540_Y - end - attribute \src "ls180.v:7411.38-7411.145" - cell $and $and$ls180.v:7411$2541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7411$2540_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7411$2541_Y - end - attribute \src "ls180.v:7414.39-7414.82" - cell $and $and$ls180.v:7414$2542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7414$2542_Y - end - attribute \src "ls180.v:7414.38-7414.112" - cell $and $and$ls180.v:7414$2543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7414$2542_Y - connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7414$2543_Y - end - attribute \src "ls180.v:7425.39-7425.104" - cell $and $and$ls180.v:7425$2545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7425$2545_Y - end - attribute \src "ls180.v:7425.38-7425.144" - cell $and $and$ls180.v:7425$2546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7425$2545_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7425$2546_Y - end - attribute \src "ls180.v:7428.39-7428.104" - cell $and $and$ls180.v:7428$2547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7428$2547_Y - end - attribute \src "ls180.v:7428.38-7428.144" - cell $and $and$ls180.v:7428$2548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7428$2547_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7428$2548_Y - end - attribute \src "ls180.v:7431.39-7431.82" - cell $and $and$ls180.v:7431$2549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7431$2549_Y - end - attribute \src "ls180.v:7431.38-7431.111" - cell $and $and$ls180.v:7431$2550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7431$2549_Y - connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7431$2550_Y - end - attribute \src "ls180.v:7442.39-7442.104" - cell $and $and$ls180.v:7442$2552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7442$2552_Y - end - attribute \src "ls180.v:7442.38-7442.149" - cell $and $and$ls180.v:7442$2553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7442$2552_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7442$2553_Y - end - attribute \src "ls180.v:7445.39-7445.104" - cell $and $and$ls180.v:7445$2554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7445$2554_Y - end - attribute \src "ls180.v:7445.38-7445.149" - cell $and $and$ls180.v:7445$2555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7445$2554_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7445$2555_Y - end - attribute \src "ls180.v:7448.39-7448.82" - cell $and $and$ls180.v:7448$2556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7448$2556_Y - end - attribute \src "ls180.v:7448.38-7448.116" - cell $and $and$ls180.v:7448$2557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7448$2556_Y - connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7448$2557_Y - end - attribute \src "ls180.v:7459.39-7459.104" - cell $and $and$ls180.v:7459$2559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7459$2559_Y - end - attribute \src "ls180.v:7459.38-7459.150" - cell $and $and$ls180.v:7459$2560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7459$2559_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7459$2560_Y - end - attribute \src "ls180.v:7462.39-7462.104" - cell $and $and$ls180.v:7462$2561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7462$2561_Y - end - attribute \src "ls180.v:7462.38-7462.150" - cell $and $and$ls180.v:7462$2562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7462$2561_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7462$2562_Y - end - attribute \src "ls180.v:7465.39-7465.82" - cell $and $and$ls180.v:7465$2563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7465$2563_Y - end - attribute \src "ls180.v:7465.38-7465.117" - cell $and $and$ls180.v:7465$2564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7465$2563_Y - connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7465$2564_Y - end - attribute \src "ls180.v:7687.17-7687.67" - cell $and $and$ls180.v:7687$2572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7687$2571_Y - connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7687$2572_Y - end - attribute \src "ls180.v:7766.8-7766.67" - cell $and $and$ls180.v:7766$2603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7766$2603_Y - end - attribute \src "ls180.v:7766.7-7766.102" - cell $and $and$ls180.v:7766$2605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7766$2603_Y - connect \B $not$ls180.v:7766$2604_Y - connect \Y $and$ls180.v:7766$2605_Y - end - attribute \src "ls180.v:7785.7-7785.75" - cell $and $and$ls180.v:7785$2609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7785$2608_Y - connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7785$2609_Y - end - attribute \src "ls180.v:7789.8-7789.65" - cell $and $and$ls180.v:7789$2610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:7789$2610_Y - end - attribute \src "ls180.v:7789.7-7789.99" - cell $and $and$ls180.v:7789$2612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7789$2610_Y - connect \B $not$ls180.v:7789$2611_Y - connect \Y $and$ls180.v:7789$2612_Y - end - attribute \src "ls180.v:7793.8-7793.65" - cell $and $and$ls180.v:7793$2613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:7793$2613_Y - end - attribute \src "ls180.v:7793.7-7793.99" - cell $and $and$ls180.v:7793$2615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7793$2613_Y - connect \B $not$ls180.v:7793$2614_Y - connect \Y $and$ls180.v:7793$2615_Y - end - attribute \src "ls180.v:7797.8-7797.65" - cell $and $and$ls180.v:7797$2616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:7797$2616_Y - end - attribute \src "ls180.v:7797.7-7797.99" - cell $and $and$ls180.v:7797$2618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7797$2616_Y - connect \B $not$ls180.v:7797$2617_Y - connect \Y $and$ls180.v:7797$2618_Y - end - attribute \src "ls180.v:7801.8-7801.65" - cell $and $and$ls180.v:7801$2619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:7801$2619_Y - end - attribute \src "ls180.v:7801.7-7801.99" - cell $and $and$ls180.v:7801$2621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7801$2619_Y - connect \B $not$ls180.v:7801$2620_Y - connect \Y $and$ls180.v:7801$2621_Y - end - attribute \src "ls180.v:7809.7-7809.56" - cell $and $and$ls180.v:7809$2623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7809$2622_Y - connect \Y $and$ls180.v:7809$2623_Y - end - attribute \src "ls180.v:7837.7-7837.75" - cell $and $and$ls180.v:7837$2630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7837$2629_Y - connect \Y $and$ls180.v:7837$2630_Y - end - attribute \src "ls180.v:7879.8-7879.131" - cell $and $and$ls180.v:7879$2636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7879$2636_Y - end - attribute \src "ls180.v:7879.7-7879.190" - cell $and $and$ls180.v:7879$2638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7879$2636_Y - connect \B $not$ls180.v:7879$2637_Y - connect \Y $and$ls180.v:7879$2638_Y - end - attribute \src "ls180.v:7885.8-7885.131" - cell $and $and$ls180.v:7885$2641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7885$2641_Y - end - attribute \src "ls180.v:7885.7-7885.190" - cell $and $and$ls180.v:7885$2643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7885$2641_Y - connect \B $not$ls180.v:7885$2642_Y - connect \Y $and$ls180.v:7885$2643_Y - end - attribute \src "ls180.v:7925.8-7925.131" - cell $and $and$ls180.v:7925$2652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7925$2652_Y - end - attribute \src "ls180.v:7925.7-7925.190" - cell $and $and$ls180.v:7925$2654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7925$2652_Y - connect \B $not$ls180.v:7925$2653_Y - connect \Y $and$ls180.v:7925$2654_Y - end - attribute \src "ls180.v:7931.8-7931.131" - cell $and $and$ls180.v:7931$2657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7931$2657_Y - end - attribute \src "ls180.v:7931.7-7931.190" - cell $and $and$ls180.v:7931$2659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7931$2657_Y - connect \B $not$ls180.v:7931$2658_Y - connect \Y $and$ls180.v:7931$2659_Y - end - attribute \src "ls180.v:7971.8-7971.131" - cell $and $and$ls180.v:7971$2668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7971$2668_Y - end - attribute \src "ls180.v:7971.7-7971.190" - cell $and $and$ls180.v:7971$2670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7971$2668_Y - connect \B $not$ls180.v:7971$2669_Y - connect \Y $and$ls180.v:7971$2670_Y - end - attribute \src "ls180.v:7977.8-7977.131" - cell $and $and$ls180.v:7977$2673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7977$2673_Y - end - attribute \src "ls180.v:7977.7-7977.190" - cell $and $and$ls180.v:7977$2675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7977$2673_Y - connect \B $not$ls180.v:7977$2674_Y - connect \Y $and$ls180.v:7977$2675_Y - end - attribute \src "ls180.v:8017.8-8017.131" - cell $and $and$ls180.v:8017$2684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8017$2684_Y - end - attribute \src "ls180.v:8017.7-8017.190" - cell $and $and$ls180.v:8017$2686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8017$2684_Y - connect \B $not$ls180.v:8017$2685_Y - connect \Y $and$ls180.v:8017$2686_Y - end - attribute \src "ls180.v:8023.8-8023.131" - cell $and $and$ls180.v:8023$2689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8023$2689_Y - end - attribute \src "ls180.v:8023.7-8023.190" - cell $and $and$ls180.v:8023$2691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8023$2689_Y - connect \B $not$ls180.v:8023$2690_Y - connect \Y $and$ls180.v:8023$2691_Y - end - attribute \src "ls180.v:8220.48-8220.124" - cell $and $and$ls180.v:8220$2716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8220$2715_Y - connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:8220$2716_Y - end - attribute \src "ls180.v:8220.130-8220.206" - cell $and $and$ls180.v:8220$2719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8220$2718_Y - connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:8220$2719_Y - end - attribute \src "ls180.v:8220.212-8220.288" - cell $and $and$ls180.v:8220$2722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8220$2721_Y - connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:8220$2722_Y - end - attribute \src "ls180.v:8220.294-8220.370" - cell $and $and$ls180.v:8220$2725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8220$2724_Y - connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:8220$2725_Y - end - attribute \src "ls180.v:8221.49-8221.125" - cell $and $and$ls180.v:8221$2728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8221$2727_Y - connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:8221$2728_Y - end - attribute \src "ls180.v:8221.131-8221.207" - cell $and $and$ls180.v:8221$2731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8221$2730_Y - connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:8221$2731_Y - end - attribute \src "ls180.v:8221.213-8221.289" - cell $and $and$ls180.v:8221$2734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8221$2733_Y - connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:8221$2734_Y - end - attribute \src "ls180.v:8221.295-8221.371" - cell $and $and$ls180.v:8221$2737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8221$2736_Y - connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:8221$2737_Y - end - attribute \src "ls180.v:8240.8-8240.49" - cell $and $and$ls180.v:8240$2740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:8240$2740_Y - end - attribute \src "ls180.v:8243.8-8243.53" - cell $and $and$ls180.v:8243$2741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:8243$2741_Y - end - attribute \src "ls180.v:8248.8-8248.59" - cell $and $and$ls180.v:8248$2743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:8248$2742_Y - connect \Y $and$ls180.v:8248$2743_Y - end - attribute \src "ls180.v:8248.7-8248.90" - cell $and $and$ls180.v:8248$2745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8248$2743_Y - connect \B $not$ls180.v:8248$2744_Y - connect \Y $and$ls180.v:8248$2745_Y - end - attribute \src "ls180.v:8254.8-8254.59" - cell $and $and$ls180.v:8254$2746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_uart_clk_txen - connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:8254$2746_Y - end - attribute \src "ls180.v:8278.8-8278.48" - cell $and $and$ls180.v:8278$2753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8278$2752_Y - connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:8278$2753_Y - end - attribute \src "ls180.v:8311.7-8311.57" - cell $and $and$ls180.v:8311$2759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8311$2758_Y - connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8311$2759_Y - end - attribute \src "ls180.v:8318.7-8318.57" - cell $and $and$ls180.v:8318$2761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8318$2760_Y - connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8318$2761_Y - end - attribute \src "ls180.v:8328.8-8328.75" - cell $and $and$ls180.v:8328$2762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8328$2762_Y - end - attribute \src "ls180.v:8328.7-8328.107" - cell $and $and$ls180.v:8328$2764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8328$2762_Y - connect \B $not$ls180.v:8328$2763_Y - connect \Y $and$ls180.v:8328$2764_Y - end - attribute \src "ls180.v:8334.8-8334.75" - cell $and $and$ls180.v:8334$2767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8334$2767_Y - end - attribute \src "ls180.v:8334.7-8334.107" - cell $and $and$ls180.v:8334$2769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8334$2767_Y - connect \B $not$ls180.v:8334$2768_Y - connect \Y $and$ls180.v:8334$2769_Y - end - attribute \src "ls180.v:8350.8-8350.75" - cell $and $and$ls180.v:8350$2773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8350$2773_Y - end - attribute \src "ls180.v:8350.7-8350.107" - cell $and $and$ls180.v:8350$2775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8350$2773_Y - connect \B $not$ls180.v:8350$2774_Y - connect \Y $and$ls180.v:8350$2775_Y - end - attribute \src "ls180.v:8356.8-8356.75" - cell $and $and$ls180.v:8356$2778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8356$2778_Y - end - attribute \src "ls180.v:8356.7-8356.107" - cell $and $and$ls180.v:8356$2780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8356$2778_Y - connect \B $not$ls180.v:8356$2779_Y - connect \Y $and$ls180.v:8356$2780_Y - end - attribute \src "ls180.v:8504.7-8504.96" - cell $and $and$ls180.v:8504$2808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_source_valid - connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8504$2808_Y - end - attribute \src "ls180.v:8505.8-8505.93" - cell $and $and$ls180.v:8505$2809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8505$2809_Y - end - attribute \src "ls180.v:8513.8-8513.93" - cell $and $and$ls180.v:8513$2810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8513$2810_Y - end - attribute \src "ls180.v:8585.7-8585.98" - cell $and $and$ls180.v:8585$2820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_source_valid - connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8585$2820_Y - end - attribute \src "ls180.v:8586.8-8586.95" - cell $and $and$ls180.v:8586$2821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8586$2821_Y - end - attribute \src "ls180.v:8594.8-8594.95" - cell $and $and$ls180.v:8594$2822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8594$2822_Y - end - attribute \src "ls180.v:8664.7-8664.100" - cell $and $and$ls180.v:8664$2832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_source_valid - connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8664$2832_Y - end - attribute \src "ls180.v:8665.8-8665.97" - cell $and $and$ls180.v:8665$2833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8665$2833_Y - end - attribute \src "ls180.v:8673.8-8673.97" - cell $and $and$ls180.v:8673$2834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8673$2834_Y - end - attribute \src "ls180.v:8764.7-8764.82" - cell $and $and$ls180.v:8764$2840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8764$2840_Y - end - attribute \src "ls180.v:8767.7-8767.82" - cell $and $and$ls180.v:8767$2841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8767$2841_Y - end - attribute \src "ls180.v:8770.7-8770.82" - cell $and $and$ls180.v:8770$2842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8770$2842_Y - end - attribute \src "ls180.v:8773.7-8773.82" - cell $and $and$ls180.v:8773$2843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8773$2843_Y - end - attribute \src "ls180.v:8776.7-8776.82" - cell $and $and$ls180.v:8776$2844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8776$2844_Y - end - attribute \src "ls180.v:8781.7-8781.82" - cell $and $and$ls180.v:8781$2845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8781$2845_Y - end - attribute \src "ls180.v:8786.7-8786.82" - cell $and $and$ls180.v:8786$2846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8786$2846_Y - end - attribute \src "ls180.v:8791.7-8791.82" - cell $and $and$ls180.v:8791$2847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8791$2847_Y - end - attribute \src "ls180.v:8796.7-8796.82" - cell $and $and$ls180.v:8796$2848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8796$2848_Y - end - attribute \src "ls180.v:8861.8-8861.83" - cell $and $and$ls180.v:8861$2851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8861$2851_Y - end - attribute \src "ls180.v:8861.7-8861.119" - cell $and $and$ls180.v:8861$2853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8861$2851_Y - connect \B $not$ls180.v:8861$2852_Y - connect \Y $and$ls180.v:8861$2853_Y - end - attribute \src "ls180.v:8867.8-8867.83" - cell $and $and$ls180.v:8867$2856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8867$2856_Y - end - attribute \src "ls180.v:8867.7-8867.119" - cell $and $and$ls180.v:8867$2858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8867$2856_Y - connect \B $not$ls180.v:8867$2857_Y - connect \Y $and$ls180.v:8867$2858_Y - end - attribute \src "ls180.v:8887.7-8887.88" - cell $and $and$ls180.v:8887$2865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_source_valid - connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8887$2865_Y - end - attribute \src "ls180.v:8888.8-8888.85" - cell $and $and$ls180.v:8888$2866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8888$2866_Y - end - attribute \src "ls180.v:8896.8-8896.85" - cell $and $and$ls180.v:8896$2867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8896$2867_Y - end - attribute \src "ls180.v:8952.7-8952.88" - cell $and $and$ls180.v:8952$2871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_source_valid - connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8952$2871_Y - end - attribute \src "ls180.v:8959.8-8959.83" - cell $and $and$ls180.v:8959$2873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8959$2873_Y - end - attribute \src "ls180.v:8959.7-8959.119" - cell $and $and$ls180.v:8959$2875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8959$2873_Y - connect \B $not$ls180.v:8959$2874_Y - connect \Y $and$ls180.v:8959$2875_Y - end - attribute \src "ls180.v:8965.8-8965.83" - cell $and $and$ls180.v:8965$2878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8965$2878_Y - end - attribute \src "ls180.v:8965.7-8965.119" - cell $and $and$ls180.v:8965$2880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8965$2878_Y - connect \B $not$ls180.v:8965$2879_Y - connect \Y $and$ls180.v:8965$2880_Y - end - attribute \src "ls180.v:2927.30-2927.76" - cell $eq $eq$ls180.v:2927$54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_icp_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2927$54_Y - end - attribute \src "ls180.v:2934.11-2934.42" - cell $eq $eq$ls180.v:2934$59 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter0_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2934$59_Y - end - attribute \src "ls180.v:2987.30-2987.76" - cell $eq $eq$ls180.v:2987$65 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_ics_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2987$65_Y - end - attribute \src "ls180.v:2994.11-2994.42" - cell $eq $eq$ls180.v:2994$70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter1_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2994$70_Y - end - attribute \src "ls180.v:3047.33-3047.58" - cell $eq $eq$ls180.v:3047$76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_sel - connect \B 1'0 - connect \Y $eq$ls180.v:3047$76_Y - end - attribute \src "ls180.v:3054.11-3054.45" - cell $eq $eq$ls180.v:3054$81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_counter - connect \B 1'1 - connect \Y $eq$ls180.v:3054$81_Y - end - attribute \src "ls180.v:3300.34-3300.65" - cell $eq $eq$ls180.v:3300$221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_count1 - connect \B 1'0 - connect \Y $eq$ls180.v:3300$221_Y - end - attribute \src "ls180.v:3304.68-3304.102" - cell $eq $eq$ls180.v:3304$224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $eq$ls180.v:3304$224_Y - end - attribute \src "ls180.v:3348.43-3348.134" - cell $eq $eq$ls180.v:3348$229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3348$229_Y - end - attribute \src "ls180.v:3365.47-3365.88" - cell $eq $eq$ls180.v:3365$242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3365$242_Y - end - attribute \src "ls180.v:3505.43-3505.134" - cell $eq $eq$ls180.v:3505$259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3505$259_Y - end - attribute \src "ls180.v:3522.47-3522.88" - cell $eq $eq$ls180.v:3522$272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3522$272_Y - end - attribute \src "ls180.v:3662.43-3662.134" - cell $eq $eq$ls180.v:3662$289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3662$289_Y - end - attribute \src "ls180.v:3679.47-3679.88" - cell $eq $eq$ls180.v:3679$302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3679$302_Y - end - attribute \src "ls180.v:3819.43-3819.134" - cell $eq $eq$ls180.v:3819$319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3819$319_Y - end - attribute \src "ls180.v:3836.47-3836.88" - cell $eq $eq$ls180.v:3836$332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3836$332_Y - end - attribute \src "ls180.v:3973.32-3973.56" - cell $eq $eq$ls180.v:3973$379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_time0 - connect \B 1'0 - connect \Y $eq$ls180.v:3973$379_Y - end - attribute \src "ls180.v:3974.32-3974.56" - cell $eq $eq$ls180.v:3974$380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_time1 - connect \B 1'0 - connect \Y $eq$ls180.v:3974$380_Y - end - attribute \src "ls180.v:3985.339-3985.418" - cell $eq $eq$ls180.v:3985$394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3985$394_Y - end - attribute \src "ls180.v:3985.423-3985.504" - cell $eq $eq$ls180.v:3985$395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3985$395_Y - end - attribute \src "ls180.v:3986.339-3986.418" - cell $eq $eq$ls180.v:3986$407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3986$407_Y - end - attribute \src "ls180.v:3986.423-3986.504" - cell $eq $eq$ls180.v:3986$408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3986$408_Y - end - attribute \src "ls180.v:3987.339-3987.418" - cell $eq $eq$ls180.v:3987$420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3987$420_Y - end - attribute \src "ls180.v:3987.423-3987.504" - cell $eq $eq$ls180.v:3987$421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3987$421_Y - end - attribute \src "ls180.v:3988.339-3988.418" - cell $eq $eq$ls180.v:3988$433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3988$433_Y - end - attribute \src "ls180.v:3988.423-3988.504" - cell $eq $eq$ls180.v:3988$434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3988$434_Y - end - attribute \src "ls180.v:4018.339-4018.418" - cell $eq $eq$ls180.v:4018$452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4018$452_Y - end - attribute \src "ls180.v:4018.423-4018.504" - cell $eq $eq$ls180.v:4018$453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4018$453_Y - end - attribute \src "ls180.v:4019.339-4019.418" - cell $eq $eq$ls180.v:4019$465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4019$465_Y - end - attribute \src "ls180.v:4019.423-4019.504" - cell $eq $eq$ls180.v:4019$466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4019$466_Y - end - attribute \src "ls180.v:4020.339-4020.418" - cell $eq $eq$ls180.v:4020$478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4020$478_Y - end - attribute \src "ls180.v:4020.423-4020.504" - cell $eq $eq$ls180.v:4020$479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4020$479_Y - end - attribute \src "ls180.v:4021.339-4021.418" - cell $eq $eq$ls180.v:4021$491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4021$491_Y - end - attribute \src "ls180.v:4021.423-4021.504" - cell $eq $eq$ls180.v:4021$492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4021$492_Y - end - attribute \src "ls180.v:4050.78-4050.113" - cell $eq $eq$ls180.v:4050$501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4050$501_Y - end - attribute \src "ls180.v:4053.78-4053.113" - cell $eq $eq$ls180.v:4053$504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$504_Y - end - attribute \src "ls180.v:4059.78-4059.113" - cell $eq $eq$ls180.v:4059$508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'1 - connect \Y $eq$ls180.v:4059$508_Y - end - attribute \src "ls180.v:4062.78-4062.113" - cell $eq $eq$ls180.v:4062$511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'1 - connect \Y $eq$ls180.v:4062$511_Y - end - attribute \src "ls180.v:4068.78-4068.113" - cell $eq $eq$ls180.v:4068$515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'10 - connect \Y $eq$ls180.v:4068$515_Y - end - attribute \src "ls180.v:4071.78-4071.113" - cell $eq $eq$ls180.v:4071$518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'10 - connect \Y $eq$ls180.v:4071$518_Y - end - attribute \src "ls180.v:4077.78-4077.113" - cell $eq $eq$ls180.v:4077$522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'11 - connect \Y $eq$ls180.v:4077$522_Y - end - attribute \src "ls180.v:4080.78-4080.113" - cell $eq $eq$ls180.v:4080$525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'11 - connect \Y $eq$ls180.v:4080$525_Y - end - attribute \src "ls180.v:4161.42-4161.82" - cell $eq $eq$ls180.v:4161$548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:4161$548_Y - end - attribute \src "ls180.v:4161.145-4161.178" - cell $eq $eq$ls180.v:4161$549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4161$549_Y - end - attribute \src "ls180.v:4161.220-4161.253" - cell $eq $eq$ls180.v:4161$552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4161$552_Y - end - attribute \src "ls180.v:4161.295-4161.328" - cell $eq $eq$ls180.v:4161$555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4161$555_Y - end - attribute \src "ls180.v:4166.42-4166.82" - cell $eq $eq$ls180.v:4166$564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:4166$564_Y - end - attribute \src "ls180.v:4166.145-4166.178" - cell $eq $eq$ls180.v:4166$565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4166$565_Y - end - attribute \src "ls180.v:4166.220-4166.253" - cell $eq $eq$ls180.v:4166$568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4166$568_Y - end - attribute \src "ls180.v:4166.295-4166.328" - cell $eq $eq$ls180.v:4166$571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4166$571_Y - end - attribute \src "ls180.v:4171.42-4171.82" - cell $eq $eq$ls180.v:4171$580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:4171$580_Y - end - attribute \src "ls180.v:4171.145-4171.178" - cell $eq $eq$ls180.v:4171$581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4171$581_Y - end - attribute \src "ls180.v:4171.220-4171.253" - cell $eq $eq$ls180.v:4171$584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4171$584_Y - end - attribute \src "ls180.v:4171.295-4171.328" - cell $eq $eq$ls180.v:4171$587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4171$587_Y - end - attribute \src "ls180.v:4176.42-4176.82" - cell $eq $eq$ls180.v:4176$596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:4176$596_Y - end - attribute \src "ls180.v:4176.145-4176.178" - cell $eq $eq$ls180.v:4176$597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4176$597_Y - end - attribute \src "ls180.v:4176.220-4176.253" - cell $eq $eq$ls180.v:4176$600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4176$600_Y - end - attribute \src "ls180.v:4176.295-4176.328" - cell $eq $eq$ls180.v:4176$603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4176$603_Y - end - attribute \src "ls180.v:4181.44-4181.77" - cell $eq $eq$ls180.v:4181$612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$612_Y - end - attribute \src "ls180.v:4181.83-4181.123" - cell $eq $eq$ls180.v:4181$613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:4181$613_Y - end - attribute \src "ls180.v:4181.186-4181.219" - cell $eq $eq$ls180.v:4181$614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$614_Y - end - attribute \src "ls180.v:4181.261-4181.294" - cell $eq $eq$ls180.v:4181$617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$617_Y - end - attribute \src "ls180.v:4181.336-4181.369" - cell $eq $eq$ls180.v:4181$620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$620_Y - end - attribute \src "ls180.v:4181.418-4181.451" - cell $eq $eq$ls180.v:4181$628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$628_Y - end - attribute \src "ls180.v:4181.457-4181.497" - cell $eq $eq$ls180.v:4181$629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:4181$629_Y - end - attribute \src "ls180.v:4181.560-4181.593" - cell $eq $eq$ls180.v:4181$630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$630_Y - end - attribute \src "ls180.v:4181.635-4181.668" - cell $eq $eq$ls180.v:4181$633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$633_Y - end - attribute \src "ls180.v:4181.710-4181.743" - cell $eq $eq$ls180.v:4181$636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$636_Y - end - attribute \src "ls180.v:4181.792-4181.825" - cell $eq $eq$ls180.v:4181$644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$644_Y - end - attribute \src "ls180.v:4181.831-4181.871" - cell $eq $eq$ls180.v:4181$645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:4181$645_Y - end - attribute \src "ls180.v:4181.934-4181.967" - cell $eq $eq$ls180.v:4181$646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$646_Y - end - attribute \src "ls180.v:4181.1009-4181.1042" - cell $eq $eq$ls180.v:4181$649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$649_Y - end - attribute \src "ls180.v:4181.1084-4181.1117" - cell $eq $eq$ls180.v:4181$652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$652_Y - end - attribute \src "ls180.v:4181.1166-4181.1199" - cell $eq $eq$ls180.v:4181$660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$660_Y - end - attribute \src "ls180.v:4181.1205-4181.1245" - cell $eq $eq$ls180.v:4181$661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:4181$661_Y - end - attribute \src "ls180.v:4181.1308-4181.1341" - cell $eq $eq$ls180.v:4181$662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$662_Y - end - attribute \src "ls180.v:4181.1383-4181.1416" - cell $eq $eq$ls180.v:4181$665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$665_Y - end - attribute \src "ls180.v:4181.1458-4181.1491" - cell $eq $eq$ls180.v:4181$668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4181$668_Y - end - attribute \src "ls180.v:4240.29-4240.57" - cell $eq $eq$ls180.v:4240$681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_sel - connect \B 1'0 - connect \Y $eq$ls180.v:4240$681_Y - end - attribute \src "ls180.v:4247.11-4247.41" - cell $eq $eq$ls180.v:4247$686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_counter - connect \B 1'1 - connect \Y $eq$ls180.v:4247$686_Y - end - attribute \src "ls180.v:4415.37-4415.111" - cell $eq $eq$ls180.v:4415$753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4415$752_Y - connect \Y $eq$ls180.v:4415$753_Y - end - attribute \src "ls180.v:4416.37-4416.105" - cell $eq $eq$ls180.v:4416$755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4416$754_Y - connect \Y $eq$ls180.v:4416$755_Y - end - attribute \src "ls180.v:4443.10-4443.67" - cell $eq $eq$ls180.v:4443$759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_spimaster27_count - connect \B $sub$ls180.v:4443$758_Y - connect \Y $eq$ls180.v:4443$759_Y - end - attribute \src "ls180.v:4473.35-4473.108" - cell $eq $eq$ls180.v:4473$761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4473$760_Y - connect \Y $eq$ls180.v:4473$761_Y - end - attribute \src "ls180.v:4474.35-4474.102" - cell $eq $eq$ls180.v:4474$763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4474$762_Y - connect \Y $eq$ls180.v:4474$763_Y - end - attribute \src "ls180.v:4502.10-4502.65" - cell $eq $eq$ls180.v:4502$767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_count - connect \B $sub$ls180.v:4502$766_Y - connect \Y $eq$ls180.v:4502$767_Y - end - attribute \src "ls180.v:4606.10-4606.40" - cell $eq $eq$ls180.v:4606$794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_count - connect \B 7'1001111 - connect \Y $eq$ls180.v:4606$794_Y - end - attribute \src "ls180.v:4663.10-4663.39" - cell $eq $eq$ls180.v:4663$797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4663$797_Y - end - attribute \src "ls180.v:4680.10-4680.39" - cell $eq $eq$ls180.v:4680$799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4680$799_Y - end - attribute \src "ls180.v:4708.38-4708.88" - cell $eq $eq$ls180.v:4708$801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - connect \B 1'0 - connect \Y $eq$ls180.v:4708$801_Y - end - attribute \src "ls180.v:4758.9-4758.40" - cell $eq $eq$ls180.v:4758$811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4758$811_Y - end - attribute \src "ls180.v:4767.36-4767.105" - cell $eq $eq$ls180.v:4767$813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4767$812_Y - connect \Y $eq$ls180.v:4767$813_Y - end - attribute \src "ls180.v:4786.9-4786.40" - cell $eq $eq$ls180.v:4786$817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4786$817_Y - end - attribute \src "ls180.v:4798.10-4798.39" - cell $eq $eq$ls180.v:4798$819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_count - connect \B 3'111 - connect \Y $eq$ls180.v:4798$819_Y - end - attribute \src "ls180.v:4835.39-4835.94" - cell $eq $eq$ls180.v:4835$823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] - connect \B 1'0 - connect \Y $eq$ls180.v:4835$823_Y - end - attribute \src "ls180.v:4872.32-4872.89" - cell $eq $eq$ls180.v:4872$832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $eq$ls180.v:4872$832_Y - end - attribute \src "ls180.v:4920.10-4920.40" - cell $eq $eq$ls180.v:4920$836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_count - connect \B 1'1 - connect \Y $eq$ls180.v:4920$836_Y - end - attribute \src "ls180.v:4969.40-4969.98" - cell $eq $eq$ls180.v:4969$838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_pads_in_payload_data_i - connect \B 1'0 - connect \Y $eq$ls180.v:4969$838_Y - end - attribute \src "ls180.v:5020.9-5020.41" - cell $eq $eq$ls180.v:5020$848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:5020$848_Y - end - attribute \src "ls180.v:5029.37-5029.123" - cell $eq $eq$ls180.v:5029$851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:5029$850_Y - connect \Y $eq$ls180.v:5029$851_Y - end - attribute \src "ls180.v:5052.9-5052.41" - cell $eq $eq$ls180.v:5052$854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:5052$854_Y - end - attribute \src "ls180.v:5062.10-5062.41" - cell $eq $eq$ls180.v:5062$856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_count - connect \B 6'100111 - connect \Y $eq$ls180.v:5062$856_Y - end - attribute \src "ls180.v:5231.9-5231.47" - cell $eq $eq$ls180.v:5231$1038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5231$1038_Y - end - attribute \src "ls180.v:5261.10-5261.48" - cell $eq $eq$ls180.v:5261$1039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5261$1039_Y - end - attribute \src "ls180.v:5292.10-5292.78" - cell $eq $eq$ls180.v:5292$1044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo0 - connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:5292$1044_Y - end - attribute \src "ls180.v:5292.83-5292.151" - cell $eq $eq$ls180.v:5292$1045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo1 - connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:5292$1045_Y - end - attribute \src "ls180.v:5292.157-5292.225" - cell $eq $eq$ls180.v:5292$1047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo2 - connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:5292$1047_Y - end - attribute \src "ls180.v:5292.231-5292.299" - cell $eq $eq$ls180.v:5292$1049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo3 - connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:5292$1049_Y - end - attribute \src "ls180.v:5300.7-5300.44" - cell $eq $eq$ls180.v:5300$1053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5300$1053_Y - end - attribute \src "ls180.v:5310.7-5310.44" - cell $eq $eq$ls180.v:5310$1056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5310$1056_Y - end - attribute \src "ls180.v:5320.7-5320.44" - cell $eq $eq$ls180.v:5320$1059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5320$1059_Y - end - attribute \src "ls180.v:5330.7-5330.44" - cell $eq $eq$ls180.v:5330$1062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5330$1062_Y - end - attribute \src "ls180.v:5454.36-5454.64" - cell $eq $eq$ls180.v:5454$1113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:5454$1113_Y - end - attribute \src "ls180.v:5460.10-5460.39" - cell $eq $eq$ls180.v:5460$1116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_count - connect \B 3'101 - connect \Y $eq$ls180.v:5460$1116_Y - end - attribute \src "ls180.v:5461.11-5461.39" - cell $eq $eq$ls180.v:5461$1117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:5461$1117_Y - end - attribute \src "ls180.v:5473.34-5473.63" - cell $eq $eq$ls180.v:5473$1118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 1'0 - connect \Y $eq$ls180.v:5473$1118_Y - end - attribute \src "ls180.v:5474.9-5474.37" - cell $eq $eq$ls180.v:5474$1119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 2'10 - connect \Y $eq$ls180.v:5474$1119_Y - end - attribute \src "ls180.v:5481.10-5481.55" - cell $eq $eq$ls180.v:5481$1120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5481$1120_Y - end - attribute \src "ls180.v:5487.12-5487.41" - cell $eq $eq$ls180.v:5487$1121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 2'10 - connect \Y $eq$ls180.v:5487$1121_Y - end - attribute \src "ls180.v:5490.13-5490.42" - cell $eq $eq$ls180.v:5490$1122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 1'1 - connect \Y $eq$ls180.v:5490$1122_Y - end - attribute \src "ls180.v:5512.10-5512.76" - cell $eq $eq$ls180.v:5512$1127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5512$1126_Y - connect \Y $eq$ls180.v:5512$1127_Y - end - attribute \src "ls180.v:5527.35-5527.101" - cell $eq $eq$ls180.v:5527$1130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5527$1129_Y - connect \Y $eq$ls180.v:5527$1130_Y - end - attribute \src "ls180.v:5529.10-5529.56" - cell $eq $eq$ls180.v:5529$1131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 1'0 - connect \Y $eq$ls180.v:5529$1131_Y - end - attribute \src "ls180.v:5538.12-5538.78" - cell $eq $eq$ls180.v:5538$1135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5538$1134_Y - connect \Y $eq$ls180.v:5538$1135_Y - end - attribute \src "ls180.v:5545.11-5545.57" - cell $eq $eq$ls180.v:5545$1136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5545$1136_Y - end - attribute \src "ls180.v:5662.10-5662.105" - cell $eq $eq$ls180.v:5662$1153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5662$1152_Y - connect \Y $eq$ls180.v:5662$1153_Y - end - attribute \src "ls180.v:5752.39-5752.106" - cell $eq $eq$ls180.v:5752$1159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5752$1158_Y - connect \Y $eq$ls180.v:5752$1159_Y - end - attribute \src "ls180.v:5782.44-5782.82" - cell $eq $eq$ls180.v:5782$1162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_mux - connect \B 1'0 - connect \Y $eq$ls180.v:5782$1162_Y - end - attribute \src "ls180.v:5783.43-5783.81" - cell $eq $eq$ls180.v:5783$1163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_mux - connect \B 3'111 - connect \Y $eq$ls180.v:5783$1163_Y - end - attribute \src "ls180.v:5895.68-5895.89" - cell $eq $eq$ls180.v:5895$1179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5895$1179_Y - end - attribute \src "ls180.v:5896.68-5896.89" - cell $eq $eq$ls180.v:5896$1181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5896$1181_Y - end - attribute \src "ls180.v:5897.71-5897.92" - cell $eq $eq$ls180.v:5897$1183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5897$1183_Y - end - attribute \src "ls180.v:5898.57-5898.78" - cell $eq $eq$ls180.v:5898$1185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5898$1185_Y - end - attribute \src "ls180.v:5899.57-5899.78" - cell $eq $eq$ls180.v:5899$1187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 3'100 - connect \Y $eq$ls180.v:5899$1187_Y - end - attribute \src "ls180.v:5900.68-5900.89" - cell $eq $eq$ls180.v:5900$1189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5900$1189_Y - end - attribute \src "ls180.v:5901.68-5901.89" - cell $eq $eq$ls180.v:5901$1191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5901$1191_Y - end - attribute \src "ls180.v:5902.71-5902.92" - cell $eq $eq$ls180.v:5902$1193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5902$1193_Y - end - attribute \src "ls180.v:5903.57-5903.78" - cell $eq $eq$ls180.v:5903$1195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5903$1195_Y - end - attribute \src "ls180.v:5904.57-5904.78" - cell $eq $eq$ls180.v:5904$1197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 3'100 - connect \Y $eq$ls180.v:5904$1197_Y - end - attribute \src "ls180.v:5908.27-5908.59" - cell $eq $eq$ls180.v:5908$1200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 1'0 - connect \Y $eq$ls180.v:5908$1200_Y - end - attribute \src "ls180.v:5909.27-5909.59" - cell $eq $eq$ls180.v:5909$1201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 1'1 - connect \Y $eq$ls180.v:5909$1201_Y - end - attribute \src "ls180.v:5910.27-5910.59" - cell $eq $eq$ls180.v:5910$1202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 2'10 - connect \Y $eq$ls180.v:5910$1202_Y - end - attribute \src "ls180.v:5911.27-5911.59" - cell $eq $eq$ls180.v:5911$1203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 2'11 - connect \Y $eq$ls180.v:5911$1203_Y - end - attribute \src "ls180.v:5912.27-5912.59" - cell $eq $eq$ls180.v:5912$1204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 3'100 - connect \Y $eq$ls180.v:5912$1204_Y - end - attribute \src "ls180.v:5913.27-5913.68" - cell $eq $eq$ls180.v:5913$1205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 28 - parameter \B_SIGNED 0 - parameter \B_WIDTH 27 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:2] - connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5913$1205_Y - end - attribute \src "ls180.v:5914.27-5914.65" - cell $eq $eq$ls180.v:5914$1206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 20 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5914$1206_Y - end - attribute \src "ls180.v:5915.27-5915.59" - cell $eq $eq$ls180.v:5915$1207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 1'1 - connect \Y $eq$ls180.v:5915$1207_Y - end - attribute \src "ls180.v:5916.27-5916.59" - cell $eq $eq$ls180.v:5916$1208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 2'10 - connect \Y $eq$ls180.v:5916$1208_Y - end - attribute \src "ls180.v:5917.27-5917.59" - cell $eq $eq$ls180.v:5917$1209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 2'11 - connect \Y $eq$ls180.v:5917$1209_Y - end - attribute \src "ls180.v:5918.28-5918.60" - cell $eq $eq$ls180.v:5918$1210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 3'100 - connect \Y $eq$ls180.v:5918$1210_Y - end - attribute \src "ls180.v:5919.28-5919.62" - cell $eq $eq$ls180.v:5919$1211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:22] - connect \B 7'1001000 - connect \Y $eq$ls180.v:5919$1211_Y - end - attribute \src "ls180.v:5920.28-5920.66" - cell $eq $eq$ls180.v:5920$1212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 17 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:13] - connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5920$1212_Y - end - attribute \src "ls180.v:6040.24-6040.45" - cell $eq $eq$ls180.v:6040$1279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_count - connect \B 1'0 - connect \Y $eq$ls180.v:6040$1279_Y - end - attribute \src "ls180.v:6041.32-6041.77" - cell $eq $eq$ls180.v:6041$1280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [13:8] - connect \B 1'0 - connect \Y $eq$ls180.v:6041$1280_Y - end - attribute \src "ls180.v:6043.97-6043.141" - cell $eq $eq$ls180.v:6043$1282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6043$1282_Y - end - attribute \src "ls180.v:6044.100-6044.144" - cell $eq $eq$ls180.v:6044$1286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6044$1286_Y - end - attribute \src "ls180.v:6046.99-6046.143" - cell $eq $eq$ls180.v:6046$1289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6046$1289_Y - end - attribute \src "ls180.v:6047.102-6047.146" - cell $eq $eq$ls180.v:6047$1293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6047$1293_Y - end - attribute \src "ls180.v:6049.99-6049.143" - cell $eq $eq$ls180.v:6049$1296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6049$1296_Y - end - attribute \src "ls180.v:6050.102-6050.146" - cell $eq $eq$ls180.v:6050$1300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6050$1300_Y - end - attribute \src "ls180.v:6052.99-6052.143" - cell $eq $eq$ls180.v:6052$1303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6052$1303_Y - end - attribute \src "ls180.v:6053.102-6053.146" - cell $eq $eq$ls180.v:6053$1307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6053$1307_Y - end - attribute \src "ls180.v:6055.99-6055.143" - cell $eq $eq$ls180.v:6055$1310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6055$1310_Y - end - attribute \src "ls180.v:6056.102-6056.146" - cell $eq $eq$ls180.v:6056$1314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6056$1314_Y - end - attribute \src "ls180.v:6058.102-6058.146" - cell $eq $eq$ls180.v:6058$1317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6058$1317_Y - end - attribute \src "ls180.v:6059.105-6059.149" - cell $eq $eq$ls180.v:6059$1321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6059$1321_Y - end - attribute \src "ls180.v:6061.102-6061.146" - cell $eq $eq$ls180.v:6061$1324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6061$1324_Y - end - attribute \src "ls180.v:6062.105-6062.149" - cell $eq $eq$ls180.v:6062$1328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6062$1328_Y - end - attribute \src "ls180.v:6064.102-6064.146" - cell $eq $eq$ls180.v:6064$1331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6064$1331_Y - end - attribute \src "ls180.v:6065.105-6065.149" - cell $eq $eq$ls180.v:6065$1335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6065$1335_Y - end - attribute \src "ls180.v:6067.102-6067.146" - cell $eq $eq$ls180.v:6067$1338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6067$1338_Y - end - attribute \src "ls180.v:6068.105-6068.149" - cell $eq $eq$ls180.v:6068$1342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6068$1342_Y - end - attribute \src "ls180.v:6079.32-6079.77" - cell $eq $eq$ls180.v:6079$1344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [13:8] - connect \B 3'110 - connect \Y $eq$ls180.v:6079$1344_Y - end - attribute \src "ls180.v:6081.94-6081.138" - cell $eq $eq$ls180.v:6081$1346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6081$1346_Y - end - attribute \src "ls180.v:6082.97-6082.141" - cell $eq $eq$ls180.v:6082$1350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6082$1350_Y - end - attribute \src "ls180.v:6084.94-6084.138" - cell $eq $eq$ls180.v:6084$1353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6084$1353_Y - end - attribute \src "ls180.v:6085.97-6085.141" - cell $eq $eq$ls180.v:6085$1357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6085$1357_Y - end - attribute \src "ls180.v:6087.94-6087.138" - cell $eq $eq$ls180.v:6087$1360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6087$1360_Y - end - attribute \src "ls180.v:6088.97-6088.141" - cell $eq $eq$ls180.v:6088$1364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6088$1364_Y - end - attribute \src "ls180.v:6090.94-6090.138" - cell $eq $eq$ls180.v:6090$1367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6090$1367_Y - end - attribute \src "ls180.v:6091.97-6091.141" - cell $eq $eq$ls180.v:6091$1371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6091$1371_Y - end - attribute \src "ls180.v:6093.95-6093.139" - cell $eq $eq$ls180.v:6093$1374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6093$1374_Y - end - attribute \src "ls180.v:6094.98-6094.142" - cell $eq $eq$ls180.v:6094$1378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6094$1378_Y - end - attribute \src "ls180.v:6096.95-6096.139" - cell $eq $eq$ls180.v:6096$1381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6096$1381_Y - end - attribute \src "ls180.v:6097.98-6097.142" - cell $eq $eq$ls180.v:6097$1385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6097$1385_Y - end - attribute \src "ls180.v:6105.32-6105.78" - cell $eq $eq$ls180.v:6105$1387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [13:8] - connect \B 4'1100 - connect \Y $eq$ls180.v:6105$1387_Y - end - attribute \src "ls180.v:6107.93-6107.135" - cell $eq $eq$ls180.v:6107$1389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:6107$1389_Y - end - attribute \src "ls180.v:6108.96-6108.138" - cell $eq $eq$ls180.v:6108$1393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:6108$1393_Y - end - attribute \src "ls180.v:6110.92-6110.134" - cell $eq $eq$ls180.v:6110$1396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'1 - connect \Y $eq$ls180.v:6110$1396_Y - end - attribute \src "ls180.v:6111.95-6111.137" - cell $eq $eq$ls180.v:6111$1400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'1 - connect \Y $eq$ls180.v:6111$1400_Y - end - attribute \src "ls180.v:6119.32-6119.78" - cell $eq $eq$ls180.v:6119$1402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [13:8] - connect \B 4'1010 - connect \Y $eq$ls180.v:6119$1402_Y - end - attribute \src "ls180.v:6121.98-6121.142" - cell $eq $eq$ls180.v:6121$1404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6121$1404_Y - end - attribute \src "ls180.v:6122.101-6122.145" - cell $eq $eq$ls180.v:6122$1408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6122$1408_Y - end - attribute \src "ls180.v:6124.97-6124.141" - cell $eq $eq$ls180.v:6124$1411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6124$1411_Y - end - attribute \src "ls180.v:6125.100-6125.144" - cell $eq $eq$ls180.v:6125$1415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6125$1415_Y - end - attribute \src "ls180.v:6127.97-6127.141" - cell $eq $eq$ls180.v:6127$1418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6127$1418_Y - end - attribute \src "ls180.v:6128.100-6128.144" - cell $eq $eq$ls180.v:6128$1422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6128$1422_Y - end - attribute \src "ls180.v:6130.97-6130.141" - cell $eq $eq$ls180.v:6130$1425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6130$1425_Y - end - attribute \src "ls180.v:6131.100-6131.144" - cell $eq $eq$ls180.v:6131$1429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6131$1429_Y - end - attribute \src "ls180.v:6133.97-6133.141" - cell $eq $eq$ls180.v:6133$1432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6133$1432_Y - end - attribute \src "ls180.v:6134.100-6134.144" - cell $eq $eq$ls180.v:6134$1436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6134$1436_Y - end - attribute \src "ls180.v:6136.98-6136.142" - cell $eq $eq$ls180.v:6136$1439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6136$1439_Y - end - attribute \src "ls180.v:6137.101-6137.145" - cell $eq $eq$ls180.v:6137$1443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6137$1443_Y - end - attribute \src "ls180.v:6139.98-6139.142" - cell $eq $eq$ls180.v:6139$1446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6139$1446_Y - end - attribute \src "ls180.v:6140.101-6140.145" - cell $eq $eq$ls180.v:6140$1450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6140$1450_Y - end - attribute \src "ls180.v:6142.98-6142.142" - cell $eq $eq$ls180.v:6142$1453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6142$1453_Y - end - attribute \src "ls180.v:6143.101-6143.145" - cell $eq $eq$ls180.v:6143$1457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6143$1457_Y - end - attribute \src "ls180.v:6145.98-6145.142" - cell $eq $eq$ls180.v:6145$1460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6145$1460_Y - end - attribute \src "ls180.v:6146.101-6146.145" - cell $eq $eq$ls180.v:6146$1464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6146$1464_Y - end - attribute \src "ls180.v:6156.32-6156.78" - cell $eq $eq$ls180.v:6156$1466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [13:8] - connect \B 4'1011 - connect \Y $eq$ls180.v:6156$1466_Y - end - attribute \src "ls180.v:6158.98-6158.142" - cell $eq $eq$ls180.v:6158$1468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6158$1468_Y - end - attribute \src "ls180.v:6159.101-6159.145" - cell $eq $eq$ls180.v:6159$1472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6159$1472_Y - end - attribute \src "ls180.v:6161.97-6161.141" - cell $eq $eq$ls180.v:6161$1475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6161$1475_Y - end - attribute \src "ls180.v:6162.100-6162.144" - cell $eq $eq$ls180.v:6162$1479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6162$1479_Y - end - attribute \src "ls180.v:6164.97-6164.141" - cell $eq $eq$ls180.v:6164$1482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6164$1482_Y - end - attribute \src "ls180.v:6165.100-6165.144" - cell $eq $eq$ls180.v:6165$1486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6165$1486_Y - end - attribute \src "ls180.v:6167.97-6167.141" - cell $eq $eq$ls180.v:6167$1489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6167$1489_Y - end - attribute \src "ls180.v:6168.100-6168.144" - cell $eq $eq$ls180.v:6168$1493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6168$1493_Y - end - attribute \src "ls180.v:6170.97-6170.141" - cell $eq $eq$ls180.v:6170$1496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6170$1496_Y - end - attribute \src "ls180.v:6171.100-6171.144" - cell $eq $eq$ls180.v:6171$1500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6171$1500_Y - end - attribute \src "ls180.v:6173.98-6173.142" - cell $eq $eq$ls180.v:6173$1503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6173$1503_Y - end - attribute \src "ls180.v:6174.101-6174.145" - cell $eq $eq$ls180.v:6174$1507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6174$1507_Y - end - attribute \src "ls180.v:6176.98-6176.142" - cell $eq $eq$ls180.v:6176$1510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6176$1510_Y - end - attribute \src "ls180.v:6177.101-6177.145" - cell $eq $eq$ls180.v:6177$1514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6177$1514_Y - end - attribute \src "ls180.v:6179.98-6179.142" - cell $eq $eq$ls180.v:6179$1517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6179$1517_Y - end - attribute \src "ls180.v:6180.101-6180.145" - cell $eq $eq$ls180.v:6180$1521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6180$1521_Y - end - attribute \src "ls180.v:6182.98-6182.142" - cell $eq $eq$ls180.v:6182$1524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6182$1524_Y - end - attribute \src "ls180.v:6183.101-6183.145" - cell $eq $eq$ls180.v:6183$1528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6183$1528_Y - end - attribute \src "ls180.v:6193.32-6193.78" - cell $eq $eq$ls180.v:6193$1530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [13:8] - connect \B 4'1111 - connect \Y $eq$ls180.v:6193$1530_Y - end - attribute \src "ls180.v:6195.100-6195.144" - cell $eq $eq$ls180.v:6195$1532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6195$1532_Y - end - attribute \src "ls180.v:6196.103-6196.147" - cell $eq $eq$ls180.v:6196$1536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6196$1536_Y - end - attribute \src "ls180.v:6198.100-6198.144" - cell $eq $eq$ls180.v:6198$1539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6198$1539_Y - end - attribute \src "ls180.v:6199.103-6199.147" - cell $eq $eq$ls180.v:6199$1543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6199$1543_Y - end - attribute \src "ls180.v:6201.100-6201.144" - cell $eq $eq$ls180.v:6201$1546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6201$1546_Y - end - attribute \src "ls180.v:6202.103-6202.147" - cell $eq $eq$ls180.v:6202$1550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6202$1550_Y - end - attribute \src "ls180.v:6204.100-6204.144" - cell $eq $eq$ls180.v:6204$1553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6204$1553_Y - end - attribute \src "ls180.v:6205.103-6205.147" - cell $eq $eq$ls180.v:6205$1557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6205$1557_Y - end - attribute \src "ls180.v:6207.100-6207.144" - cell $eq $eq$ls180.v:6207$1560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6207$1560_Y - end - attribute \src "ls180.v:6208.103-6208.147" - cell $eq $eq$ls180.v:6208$1564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6208$1564_Y - end - attribute \src "ls180.v:6210.100-6210.144" - cell $eq $eq$ls180.v:6210$1567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6210$1567_Y - end - attribute \src "ls180.v:6211.103-6211.147" - cell $eq $eq$ls180.v:6211$1571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6211$1571_Y - end - attribute \src "ls180.v:6213.100-6213.144" - cell $eq $eq$ls180.v:6213$1574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6213$1574_Y - end - attribute \src "ls180.v:6214.103-6214.147" - cell $eq $eq$ls180.v:6214$1578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6214$1578_Y - end - attribute \src "ls180.v:6216.100-6216.144" - cell $eq $eq$ls180.v:6216$1581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6216$1581_Y - end - attribute \src "ls180.v:6217.103-6217.147" - cell $eq $eq$ls180.v:6217$1585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6217$1585_Y - end - attribute \src "ls180.v:6219.102-6219.146" - cell $eq $eq$ls180.v:6219$1588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6219$1588_Y - end - attribute \src "ls180.v:6220.105-6220.149" - cell $eq $eq$ls180.v:6220$1592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6220$1592_Y - end - attribute \src "ls180.v:6222.102-6222.146" - cell $eq $eq$ls180.v:6222$1595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6222$1595_Y - end - attribute \src "ls180.v:6223.105-6223.149" - cell $eq $eq$ls180.v:6223$1599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6223$1599_Y - end - attribute \src "ls180.v:6225.102-6225.147" - cell $eq $eq$ls180.v:6225$1602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6225$1602_Y - end - attribute \src "ls180.v:6226.105-6226.150" - cell $eq $eq$ls180.v:6226$1606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6226$1606_Y - end - attribute \src "ls180.v:6228.102-6228.147" - cell $eq $eq$ls180.v:6228$1609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6228$1609_Y - end - attribute \src "ls180.v:6229.105-6229.150" - cell $eq $eq$ls180.v:6229$1613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6229$1613_Y - end - attribute \src "ls180.v:6231.102-6231.147" - cell $eq $eq$ls180.v:6231$1616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6231$1616_Y - end - attribute \src "ls180.v:6232.105-6232.150" - cell $eq $eq$ls180.v:6232$1620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6232$1620_Y - end - attribute \src "ls180.v:6234.99-6234.144" - cell $eq $eq$ls180.v:6234$1623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6234$1623_Y - end - attribute \src "ls180.v:6235.102-6235.147" - cell $eq $eq$ls180.v:6235$1627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6235$1627_Y - end - attribute \src "ls180.v:6237.100-6237.145" - cell $eq $eq$ls180.v:6237$1630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6237$1630_Y - end - attribute \src "ls180.v:6238.103-6238.148" - cell $eq $eq$ls180.v:6238$1634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6238$1634_Y - end - attribute \src "ls180.v:6255.32-6255.78" - cell $eq $eq$ls180.v:6255$1636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [13:8] - connect \B 4'1110 - connect \Y $eq$ls180.v:6255$1636_Y - end - attribute \src "ls180.v:6257.104-6257.148" - cell $eq $eq$ls180.v:6257$1638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6257$1638_Y - end - attribute \src "ls180.v:6258.107-6258.151" - cell $eq $eq$ls180.v:6258$1642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6258$1642_Y - end - attribute \src "ls180.v:6260.104-6260.148" - cell $eq $eq$ls180.v:6260$1645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6260$1645_Y - end - attribute \src "ls180.v:6261.107-6261.151" - cell $eq $eq$ls180.v:6261$1649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6261$1649_Y - end - attribute \src "ls180.v:6263.104-6263.148" - cell $eq $eq$ls180.v:6263$1652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6263$1652_Y - end - attribute \src "ls180.v:6264.107-6264.151" - cell $eq $eq$ls180.v:6264$1656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6264$1656_Y - end - attribute \src "ls180.v:6266.104-6266.148" - cell $eq $eq$ls180.v:6266$1659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6266$1659_Y - end - attribute \src "ls180.v:6267.107-6267.151" - cell $eq $eq$ls180.v:6267$1663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6267$1663_Y - end - attribute \src "ls180.v:6269.103-6269.147" - cell $eq $eq$ls180.v:6269$1666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6269$1666_Y - end - attribute \src "ls180.v:6270.106-6270.150" - cell $eq $eq$ls180.v:6270$1670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6270$1670_Y - end - attribute \src "ls180.v:6272.103-6272.147" - cell $eq $eq$ls180.v:6272$1673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6272$1673_Y - end - attribute \src "ls180.v:6273.106-6273.150" - cell $eq $eq$ls180.v:6273$1677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6273$1677_Y - end - attribute \src "ls180.v:6275.103-6275.147" - cell $eq $eq$ls180.v:6275$1680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6275$1680_Y - end - attribute \src "ls180.v:6276.106-6276.150" - cell $eq $eq$ls180.v:6276$1684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6276$1684_Y - end - attribute \src "ls180.v:6278.103-6278.147" - cell $eq $eq$ls180.v:6278$1687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6278$1687_Y - end - attribute \src "ls180.v:6279.106-6279.150" - cell $eq $eq$ls180.v:6279$1691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6279$1691_Y - end - attribute \src "ls180.v:6281.94-6281.138" - cell $eq $eq$ls180.v:6281$1694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6281$1694_Y - end - attribute \src "ls180.v:6282.97-6282.141" - cell $eq $eq$ls180.v:6282$1698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6282$1698_Y - end - attribute \src "ls180.v:6284.105-6284.149" - cell $eq $eq$ls180.v:6284$1701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6284$1701_Y - end - attribute \src "ls180.v:6285.108-6285.152" - cell $eq $eq$ls180.v:6285$1705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6285$1705_Y - end - attribute \src "ls180.v:6287.105-6287.150" - cell $eq $eq$ls180.v:6287$1708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6287$1708_Y - end - attribute \src "ls180.v:6288.108-6288.153" - cell $eq $eq$ls180.v:6288$1712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6288$1712_Y - end - attribute \src "ls180.v:6290.105-6290.150" - cell $eq $eq$ls180.v:6290$1715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6290$1715_Y - end - attribute \src "ls180.v:6291.108-6291.153" - cell $eq $eq$ls180.v:6291$1719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6291$1719_Y - end - attribute \src "ls180.v:6293.105-6293.150" - cell $eq $eq$ls180.v:6293$1722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6293$1722_Y - end - attribute \src "ls180.v:6294.108-6294.153" - cell $eq $eq$ls180.v:6294$1726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6294$1726_Y - end - attribute \src "ls180.v:6296.105-6296.150" - cell $eq $eq$ls180.v:6296$1729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6296$1729_Y - end - attribute \src "ls180.v:6297.108-6297.153" - cell $eq $eq$ls180.v:6297$1733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6297$1733_Y - end - attribute \src "ls180.v:6299.105-6299.150" - cell $eq $eq$ls180.v:6299$1736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6299$1736_Y - end - attribute \src "ls180.v:6300.108-6300.153" - cell $eq $eq$ls180.v:6300$1740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6300$1740_Y - end - attribute \src "ls180.v:6302.104-6302.149" - cell $eq $eq$ls180.v:6302$1743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6302$1743_Y - end - attribute \src "ls180.v:6303.107-6303.152" - cell $eq $eq$ls180.v:6303$1747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6303$1747_Y - end - attribute \src "ls180.v:6305.104-6305.149" - cell $eq $eq$ls180.v:6305$1750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6305$1750_Y - end - attribute \src "ls180.v:6306.107-6306.152" - cell $eq $eq$ls180.v:6306$1754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6306$1754_Y - end - attribute \src "ls180.v:6308.104-6308.149" - cell $eq $eq$ls180.v:6308$1757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6308$1757_Y - end - attribute \src "ls180.v:6309.107-6309.152" - cell $eq $eq$ls180.v:6309$1761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6309$1761_Y - end - attribute \src "ls180.v:6311.104-6311.149" - cell $eq $eq$ls180.v:6311$1764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6311$1764_Y - end - attribute \src "ls180.v:6312.107-6312.152" - cell $eq $eq$ls180.v:6312$1768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6312$1768_Y - end - attribute \src "ls180.v:6314.104-6314.149" - cell $eq $eq$ls180.v:6314$1771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:6314$1771_Y - end - attribute \src "ls180.v:6315.107-6315.152" - cell $eq $eq$ls180.v:6315$1775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:6315$1775_Y - end - attribute \src "ls180.v:6317.104-6317.149" - cell $eq $eq$ls180.v:6317$1778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:6317$1778_Y - end - attribute \src "ls180.v:6318.107-6318.152" - cell $eq $eq$ls180.v:6318$1782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:6318$1782_Y - end - attribute \src "ls180.v:6320.104-6320.149" - cell $eq $eq$ls180.v:6320$1785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:6320$1785_Y - end - attribute \src "ls180.v:6321.107-6321.152" - cell $eq $eq$ls180.v:6321$1789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:6321$1789_Y - end - attribute \src "ls180.v:6323.104-6323.149" - cell $eq $eq$ls180.v:6323$1792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:6323$1792_Y - end - attribute \src "ls180.v:6324.107-6324.152" - cell $eq $eq$ls180.v:6324$1796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:6324$1796_Y - end - attribute \src "ls180.v:6326.104-6326.149" - cell $eq $eq$ls180.v:6326$1799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:6326$1799_Y - end - attribute \src "ls180.v:6327.107-6327.152" - cell $eq $eq$ls180.v:6327$1803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:6327$1803_Y - end - attribute \src "ls180.v:6329.104-6329.149" - cell $eq $eq$ls180.v:6329$1806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:6329$1806_Y - end - attribute \src "ls180.v:6330.107-6330.152" - cell $eq $eq$ls180.v:6330$1810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:6330$1810_Y - end - attribute \src "ls180.v:6332.100-6332.145" - cell $eq $eq$ls180.v:6332$1813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:6332$1813_Y - end - attribute \src "ls180.v:6333.103-6333.148" - cell $eq $eq$ls180.v:6333$1817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:6333$1817_Y - end - attribute \src "ls180.v:6335.101-6335.146" - cell $eq $eq$ls180.v:6335$1820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:6335$1820_Y - end - attribute \src "ls180.v:6336.104-6336.149" - cell $eq $eq$ls180.v:6336$1824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:6336$1824_Y - end - attribute \src "ls180.v:6338.104-6338.149" - cell $eq $eq$ls180.v:6338$1827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:6338$1827_Y - end - attribute \src "ls180.v:6339.107-6339.152" - cell $eq $eq$ls180.v:6339$1831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:6339$1831_Y - end - attribute \src "ls180.v:6341.104-6341.149" - cell $eq $eq$ls180.v:6341$1834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:6341$1834_Y - end - attribute \src "ls180.v:6342.107-6342.152" - cell $eq $eq$ls180.v:6342$1838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:6342$1838_Y - end - attribute \src "ls180.v:6344.103-6344.148" - cell $eq $eq$ls180.v:6344$1841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:6344$1841_Y - end - attribute \src "ls180.v:6345.106-6345.151" - cell $eq $eq$ls180.v:6345$1845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:6345$1845_Y - end - attribute \src "ls180.v:6347.103-6347.148" - cell $eq $eq$ls180.v:6347$1848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:6347$1848_Y - end - attribute \src "ls180.v:6348.106-6348.151" - cell $eq $eq$ls180.v:6348$1852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:6348$1852_Y - end - attribute \src "ls180.v:6350.103-6350.148" - cell $eq $eq$ls180.v:6350$1855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:6350$1855_Y - end - attribute \src "ls180.v:6351.106-6351.151" - cell $eq $eq$ls180.v:6351$1859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:6351$1859_Y - end - attribute \src "ls180.v:6353.103-6353.148" - cell $eq $eq$ls180.v:6353$1862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:6353$1862_Y - end - attribute \src "ls180.v:6354.106-6354.151" - cell $eq $eq$ls180.v:6354$1866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:6354$1866_Y - end - attribute \src "ls180.v:6390.32-6390.78" - cell $eq $eq$ls180.v:6390$1868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [13:8] - connect \B 5'10000 - connect \Y $eq$ls180.v:6390$1868_Y - end - attribute \src "ls180.v:6392.100-6392.144" - cell $eq $eq$ls180.v:6392$1870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6392$1870_Y - end - attribute \src "ls180.v:6393.103-6393.147" - cell $eq $eq$ls180.v:6393$1874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6393$1874_Y - end - attribute \src "ls180.v:6395.100-6395.144" - cell $eq $eq$ls180.v:6395$1877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6395$1877_Y - end - attribute \src "ls180.v:6396.103-6396.147" - cell $eq $eq$ls180.v:6396$1881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6396$1881_Y - end - attribute \src "ls180.v:6398.100-6398.144" - cell $eq $eq$ls180.v:6398$1884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6398$1884_Y - end - attribute \src "ls180.v:6399.103-6399.147" - cell $eq $eq$ls180.v:6399$1888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6399$1888_Y - end - attribute \src "ls180.v:6401.100-6401.144" - cell $eq $eq$ls180.v:6401$1891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6401$1891_Y - end - attribute \src "ls180.v:6402.103-6402.147" - cell $eq $eq$ls180.v:6402$1895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6402$1895_Y - end - attribute \src "ls180.v:6404.100-6404.144" - cell $eq $eq$ls180.v:6404$1898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6404$1898_Y - end - attribute \src "ls180.v:6405.103-6405.147" - cell $eq $eq$ls180.v:6405$1902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6405$1902_Y - end - attribute \src "ls180.v:6407.100-6407.144" - cell $eq $eq$ls180.v:6407$1905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6407$1905_Y - end - attribute \src "ls180.v:6408.103-6408.147" - cell $eq $eq$ls180.v:6408$1909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6408$1909_Y - end - attribute \src "ls180.v:6410.100-6410.144" - cell $eq $eq$ls180.v:6410$1912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6410$1912_Y - end - attribute \src "ls180.v:6411.103-6411.147" - cell $eq $eq$ls180.v:6411$1916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6411$1916_Y - end - attribute \src "ls180.v:6413.100-6413.144" - cell $eq $eq$ls180.v:6413$1919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6413$1919_Y - end - attribute \src "ls180.v:6414.103-6414.147" - cell $eq $eq$ls180.v:6414$1923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6414$1923_Y - end - attribute \src "ls180.v:6416.102-6416.146" - cell $eq $eq$ls180.v:6416$1926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6416$1926_Y - end - attribute \src "ls180.v:6417.105-6417.149" - cell $eq $eq$ls180.v:6417$1930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6417$1930_Y - end - attribute \src "ls180.v:6419.102-6419.146" - cell $eq $eq$ls180.v:6419$1933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6419$1933_Y - end - attribute \src "ls180.v:6420.105-6420.149" - cell $eq $eq$ls180.v:6420$1937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6420$1937_Y - end - attribute \src "ls180.v:6422.102-6422.147" - cell $eq $eq$ls180.v:6422$1940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6422$1940_Y - end - attribute \src "ls180.v:6423.105-6423.150" - cell $eq $eq$ls180.v:6423$1944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6423$1944_Y - end - attribute \src "ls180.v:6425.102-6425.147" - cell $eq $eq$ls180.v:6425$1947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6425$1947_Y - end - attribute \src "ls180.v:6426.105-6426.150" - cell $eq $eq$ls180.v:6426$1951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6426$1951_Y - end - attribute \src "ls180.v:6428.102-6428.147" - cell $eq $eq$ls180.v:6428$1954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6428$1954_Y - end - attribute \src "ls180.v:6429.105-6429.150" - cell $eq $eq$ls180.v:6429$1958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6429$1958_Y - end - attribute \src "ls180.v:6431.99-6431.144" - cell $eq $eq$ls180.v:6431$1961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6431$1961_Y - end - attribute \src "ls180.v:6432.102-6432.147" - cell $eq $eq$ls180.v:6432$1965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6432$1965_Y - end - attribute \src "ls180.v:6434.100-6434.145" - cell $eq $eq$ls180.v:6434$1968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6434$1968_Y - end - attribute \src "ls180.v:6435.103-6435.148" - cell $eq $eq$ls180.v:6435$1972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6435$1972_Y - end - attribute \src "ls180.v:6437.102-6437.147" - cell $eq $eq$ls180.v:6437$1975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6437$1975_Y - end - attribute \src "ls180.v:6438.105-6438.150" - cell $eq $eq$ls180.v:6438$1979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6438$1979_Y - end - attribute \src "ls180.v:6440.102-6440.147" - cell $eq $eq$ls180.v:6440$1982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6440$1982_Y - end - attribute \src "ls180.v:6441.105-6441.150" - cell $eq $eq$ls180.v:6441$1986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6441$1986_Y - end - attribute \src "ls180.v:6443.102-6443.147" - cell $eq $eq$ls180.v:6443$1989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6443$1989_Y - end - attribute \src "ls180.v:6444.105-6444.150" - cell $eq $eq$ls180.v:6444$1993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6444$1993_Y - end - attribute \src "ls180.v:6446.102-6446.147" - cell $eq $eq$ls180.v:6446$1996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6446$1996_Y - end - attribute \src "ls180.v:6447.105-6447.150" - cell $eq $eq$ls180.v:6447$2000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6447$2000_Y - end - attribute \src "ls180.v:6469.32-6469.78" - cell $eq $eq$ls180.v:6469$2002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [13:8] - connect \B 4'1101 - connect \Y $eq$ls180.v:6469$2002_Y - end - attribute \src "ls180.v:6471.102-6471.146" - cell $eq $eq$ls180.v:6471$2004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6471$2004_Y - end - attribute \src "ls180.v:6472.105-6472.149" - cell $eq $eq$ls180.v:6472$2008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6472$2008_Y - end - attribute \src "ls180.v:6474.107-6474.151" - cell $eq $eq$ls180.v:6474$2011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6474$2011_Y - end - attribute \src "ls180.v:6475.110-6475.154" - cell $eq $eq$ls180.v:6475$2015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6475$2015_Y - end - attribute \src "ls180.v:6477.107-6477.151" - cell $eq $eq$ls180.v:6477$2018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6477$2018_Y - end - attribute \src "ls180.v:6478.110-6478.154" - cell $eq $eq$ls180.v:6478$2022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6478$2022_Y - end - attribute \src "ls180.v:6480.100-6480.144" - cell $eq $eq$ls180.v:6480$2025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6480$2025_Y - end - attribute \src "ls180.v:6481.103-6481.147" - cell $eq $eq$ls180.v:6481$2029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6481$2029_Y - end - attribute \src "ls180.v:6486.32-6486.77" - cell $eq $eq$ls180.v:6486$2031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [13:8] - connect \B 2'11 - connect \Y $eq$ls180.v:6486$2031_Y - end - attribute \src "ls180.v:6488.104-6488.148" - cell $eq $eq$ls180.v:6488$2033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6488$2033_Y - end - attribute \src "ls180.v:6489.107-6489.151" - cell $eq $eq$ls180.v:6489$2037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6489$2037_Y - end - attribute \src "ls180.v:6491.108-6491.152" - cell $eq $eq$ls180.v:6491$2040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6491$2040_Y - end - attribute \src "ls180.v:6492.111-6492.155" - cell $eq $eq$ls180.v:6492$2044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6492$2044_Y - end - attribute \src "ls180.v:6494.98-6494.142" - cell $eq $eq$ls180.v:6494$2047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6494$2047_Y - end - attribute \src "ls180.v:6495.101-6495.145" - cell $eq $eq$ls180.v:6495$2051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6495$2051_Y - end - attribute \src "ls180.v:6497.108-6497.152" - cell $eq $eq$ls180.v:6497$2054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6497$2054_Y - end - attribute \src "ls180.v:6498.111-6498.155" - cell $eq $eq$ls180.v:6498$2058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6498$2058_Y - end - attribute \src "ls180.v:6500.108-6500.152" - cell $eq $eq$ls180.v:6500$2061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6500$2061_Y - end - attribute \src "ls180.v:6501.111-6501.155" - cell $eq $eq$ls180.v:6501$2065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6501$2065_Y - end - attribute \src "ls180.v:6503.109-6503.153" - cell $eq $eq$ls180.v:6503$2068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6503$2068_Y - end - attribute \src "ls180.v:6504.112-6504.156" - cell $eq $eq$ls180.v:6504$2072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6504$2072_Y - end - attribute \src "ls180.v:6506.107-6506.151" - cell $eq $eq$ls180.v:6506$2075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6506$2075_Y - end - attribute \src "ls180.v:6507.110-6507.154" - cell $eq $eq$ls180.v:6507$2079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6507$2079_Y - end - attribute \src "ls180.v:6509.107-6509.151" - cell $eq $eq$ls180.v:6509$2082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6509$2082_Y - end - attribute \src "ls180.v:6510.110-6510.154" - cell $eq $eq$ls180.v:6510$2086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6510$2086_Y - end - attribute \src "ls180.v:6512.107-6512.151" - cell $eq $eq$ls180.v:6512$2089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6512$2089_Y - end - attribute \src "ls180.v:6513.110-6513.154" - cell $eq $eq$ls180.v:6513$2093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6513$2093_Y - end - attribute \src "ls180.v:6515.107-6515.151" - cell $eq $eq$ls180.v:6515$2096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6515$2096_Y - end - attribute \src "ls180.v:6516.110-6516.154" - cell $eq $eq$ls180.v:6516$2100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6516$2100_Y - end - attribute \src "ls180.v:6531.33-6531.79" - cell $eq $eq$ls180.v:6531$2102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [13:8] - connect \B 4'1000 - connect \Y $eq$ls180.v:6531$2102_Y - end - attribute \src "ls180.v:6533.102-6533.147" - cell $eq $eq$ls180.v:6533$2104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6533$2104_Y - end - attribute \src "ls180.v:6534.105-6534.150" - cell $eq $eq$ls180.v:6534$2108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6534$2108_Y - end - attribute \src "ls180.v:6536.102-6536.147" - cell $eq $eq$ls180.v:6536$2111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6536$2111_Y - end - attribute \src "ls180.v:6537.105-6537.150" - cell $eq $eq$ls180.v:6537$2115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6537$2115_Y - end - attribute \src "ls180.v:6539.100-6539.145" - cell $eq $eq$ls180.v:6539$2118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6539$2118_Y - end - attribute \src "ls180.v:6540.103-6540.148" - cell $eq $eq$ls180.v:6540$2122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6540$2122_Y - end - attribute \src "ls180.v:6542.99-6542.144" - cell $eq $eq$ls180.v:6542$2125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6542$2125_Y - end - attribute \src "ls180.v:6543.102-6543.147" - cell $eq $eq$ls180.v:6543$2129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6543$2129_Y - end - attribute \src "ls180.v:6545.98-6545.143" - cell $eq $eq$ls180.v:6545$2132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6545$2132_Y - end - attribute \src "ls180.v:6546.101-6546.146" - cell $eq $eq$ls180.v:6546$2136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6546$2136_Y - end - attribute \src "ls180.v:6548.97-6548.142" - cell $eq $eq$ls180.v:6548$2139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6548$2139_Y - end - attribute \src "ls180.v:6549.100-6549.145" - cell $eq $eq$ls180.v:6549$2143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6549$2143_Y - end - attribute \src "ls180.v:6551.103-6551.148" - cell $eq $eq$ls180.v:6551$2146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6551$2146_Y - end - attribute \src "ls180.v:6552.106-6552.151" - cell $eq $eq$ls180.v:6552$2150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6552$2150_Y - end - attribute \src "ls180.v:6571.33-6571.79" - cell $eq $eq$ls180.v:6571$2153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [13:8] - connect \B 4'1001 - connect \Y $eq$ls180.v:6571$2153_Y - end - attribute \src "ls180.v:6573.102-6573.147" - cell $eq $eq$ls180.v:6573$2155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6573$2155_Y - end - attribute \src "ls180.v:6574.105-6574.150" - cell $eq $eq$ls180.v:6574$2159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6574$2159_Y - end - attribute \src "ls180.v:6576.102-6576.147" - cell $eq $eq$ls180.v:6576$2162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6576$2162_Y - end - attribute \src "ls180.v:6577.105-6577.150" - cell $eq $eq$ls180.v:6577$2166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6577$2166_Y - end - attribute \src "ls180.v:6579.100-6579.145" - cell $eq $eq$ls180.v:6579$2169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6579$2169_Y - end - attribute \src "ls180.v:6580.103-6580.148" - cell $eq $eq$ls180.v:6580$2173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6580$2173_Y - end - attribute \src "ls180.v:6582.99-6582.144" - cell $eq $eq$ls180.v:6582$2176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6582$2176_Y - end - attribute \src "ls180.v:6583.102-6583.147" - cell $eq $eq$ls180.v:6583$2180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6583$2180_Y - end - attribute \src "ls180.v:6585.98-6585.143" - cell $eq $eq$ls180.v:6585$2183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6585$2183_Y - end - attribute \src "ls180.v:6586.101-6586.146" - cell $eq $eq$ls180.v:6586$2187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6586$2187_Y - end - attribute \src "ls180.v:6588.97-6588.142" - cell $eq $eq$ls180.v:6588$2190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6588$2190_Y - end - attribute \src "ls180.v:6589.100-6589.145" - cell $eq $eq$ls180.v:6589$2194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6589$2194_Y - end - attribute \src "ls180.v:6591.103-6591.148" - cell $eq $eq$ls180.v:6591$2197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6591$2197_Y - end - attribute \src "ls180.v:6592.106-6592.151" - cell $eq $eq$ls180.v:6592$2201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6592$2201_Y - end - attribute \src "ls180.v:6594.106-6594.151" - cell $eq $eq$ls180.v:6594$2204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6594$2204_Y - end - attribute \src "ls180.v:6595.109-6595.154" - cell $eq $eq$ls180.v:6595$2208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6595$2208_Y - end - attribute \src "ls180.v:6597.106-6597.151" - cell $eq $eq$ls180.v:6597$2211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6597$2211_Y - end - attribute \src "ls180.v:6598.109-6598.154" - cell $eq $eq$ls180.v:6598$2215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6598$2215_Y - end - attribute \src "ls180.v:6619.33-6619.79" - cell $eq $eq$ls180.v:6619$2218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [13:8] - connect \B 2'10 - connect \Y $eq$ls180.v:6619$2218_Y - end - attribute \src "ls180.v:6621.99-6621.144" - cell $eq $eq$ls180.v:6621$2220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6621$2220_Y - end - attribute \src "ls180.v:6622.102-6622.147" - cell $eq $eq$ls180.v:6622$2224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6622$2224_Y - end - attribute \src "ls180.v:6624.99-6624.144" - cell $eq $eq$ls180.v:6624$2227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6624$2227_Y - end - attribute \src "ls180.v:6625.102-6625.147" - cell $eq $eq$ls180.v:6625$2231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6625$2231_Y - end - attribute \src "ls180.v:6627.99-6627.144" - cell $eq $eq$ls180.v:6627$2234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6627$2234_Y - end - attribute \src "ls180.v:6628.102-6628.147" - cell $eq $eq$ls180.v:6628$2238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6628$2238_Y - end - attribute \src "ls180.v:6630.99-6630.144" - cell $eq $eq$ls180.v:6630$2241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6630$2241_Y - end - attribute \src "ls180.v:6631.102-6631.147" - cell $eq $eq$ls180.v:6631$2245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6631$2245_Y - end - attribute \src "ls180.v:6633.101-6633.146" - cell $eq $eq$ls180.v:6633$2248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6633$2248_Y - end - attribute \src "ls180.v:6634.104-6634.149" - cell $eq $eq$ls180.v:6634$2252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6634$2252_Y - end - attribute \src "ls180.v:6636.101-6636.146" - cell $eq $eq$ls180.v:6636$2255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6636$2255_Y - end - attribute \src "ls180.v:6637.104-6637.149" - cell $eq $eq$ls180.v:6637$2259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6637$2259_Y - end - attribute \src "ls180.v:6639.101-6639.146" - cell $eq $eq$ls180.v:6639$2262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6639$2262_Y - end - attribute \src "ls180.v:6640.104-6640.149" - cell $eq $eq$ls180.v:6640$2266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6640$2266_Y - end - attribute \src "ls180.v:6642.101-6642.146" - cell $eq $eq$ls180.v:6642$2269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6642$2269_Y - end - attribute \src "ls180.v:6643.104-6643.149" - cell $eq $eq$ls180.v:6643$2273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6643$2273_Y - end - attribute \src "ls180.v:6645.97-6645.142" - cell $eq $eq$ls180.v:6645$2276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6645$2276_Y - end - attribute \src "ls180.v:6646.100-6646.145" - cell $eq $eq$ls180.v:6646$2280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6646$2280_Y - end - attribute \src "ls180.v:6648.107-6648.152" - cell $eq $eq$ls180.v:6648$2283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6648$2283_Y - end - attribute \src "ls180.v:6649.110-6649.155" - cell $eq $eq$ls180.v:6649$2287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6649$2287_Y - end - attribute \src "ls180.v:6651.100-6651.146" - cell $eq $eq$ls180.v:6651$2290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6651$2290_Y - end - attribute \src "ls180.v:6652.103-6652.149" - cell $eq $eq$ls180.v:6652$2294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6652$2294_Y - end - attribute \src "ls180.v:6654.100-6654.146" - cell $eq $eq$ls180.v:6654$2297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6654$2297_Y - end - attribute \src "ls180.v:6655.103-6655.149" - cell $eq $eq$ls180.v:6655$2301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6655$2301_Y - end - attribute \src "ls180.v:6657.100-6657.146" - cell $eq $eq$ls180.v:6657$2304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6657$2304_Y - end - attribute \src "ls180.v:6658.103-6658.149" - cell $eq $eq$ls180.v:6658$2308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6658$2308_Y - end - attribute \src "ls180.v:6660.100-6660.146" - cell $eq $eq$ls180.v:6660$2311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6660$2311_Y - end - attribute \src "ls180.v:6661.103-6661.149" - cell $eq $eq$ls180.v:6661$2315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6661$2315_Y - end - attribute \src "ls180.v:6663.112-6663.158" - cell $eq $eq$ls180.v:6663$2318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6663$2318_Y - end - attribute \src "ls180.v:6664.115-6664.161" - cell $eq $eq$ls180.v:6664$2322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6664$2322_Y - end - attribute \src "ls180.v:6666.113-6666.159" - cell $eq $eq$ls180.v:6666$2325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6666$2325_Y - end - attribute \src "ls180.v:6667.116-6667.162" - cell $eq $eq$ls180.v:6667$2329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6667$2329_Y - end - attribute \src "ls180.v:6669.104-6669.150" - cell $eq $eq$ls180.v:6669$2332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6669$2332_Y - end - attribute \src "ls180.v:6670.107-6670.153" - cell $eq $eq$ls180.v:6670$2336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6670$2336_Y - end - attribute \src "ls180.v:6687.33-6687.79" - cell $eq $eq$ls180.v:6687$2338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [13:8] - connect \B 3'101 - connect \Y $eq$ls180.v:6687$2338_Y - end - attribute \src "ls180.v:6689.90-6689.135" - cell $eq $eq$ls180.v:6689$2340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6689$2340_Y - end - attribute \src "ls180.v:6690.93-6690.138" - cell $eq $eq$ls180.v:6690$2344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6690$2344_Y - end - attribute \src "ls180.v:6692.100-6692.145" - cell $eq $eq$ls180.v:6692$2347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6692$2347_Y - end - attribute \src "ls180.v:6693.103-6693.148" - cell $eq $eq$ls180.v:6693$2351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6693$2351_Y - end - attribute \src "ls180.v:6695.101-6695.146" - cell $eq $eq$ls180.v:6695$2354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6695$2354_Y - end - attribute \src "ls180.v:6696.104-6696.149" - cell $eq $eq$ls180.v:6696$2358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6696$2358_Y - end - attribute \src "ls180.v:6698.105-6698.150" - cell $eq $eq$ls180.v:6698$2361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6698$2361_Y - end - attribute \src "ls180.v:6699.108-6699.153" - cell $eq $eq$ls180.v:6699$2365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6699$2365_Y - end - attribute \src "ls180.v:6701.106-6701.151" - cell $eq $eq$ls180.v:6701$2368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6701$2368_Y - end - attribute \src "ls180.v:6702.109-6702.154" - cell $eq $eq$ls180.v:6702$2372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6702$2372_Y - end - attribute \src "ls180.v:6704.104-6704.149" - cell $eq $eq$ls180.v:6704$2375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6704$2375_Y - end - attribute \src "ls180.v:6705.107-6705.152" - cell $eq $eq$ls180.v:6705$2379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6705$2379_Y - end - attribute \src "ls180.v:6707.101-6707.146" - cell $eq $eq$ls180.v:6707$2382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6707$2382_Y - end - attribute \src "ls180.v:6708.104-6708.149" - cell $eq $eq$ls180.v:6708$2386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6708$2386_Y - end - attribute \src "ls180.v:6710.100-6710.145" - cell $eq $eq$ls180.v:6710$2389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6710$2389_Y - end - attribute \src "ls180.v:6711.103-6711.148" - cell $eq $eq$ls180.v:6711$2393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6711$2393_Y - end - attribute \src "ls180.v:6721.33-6721.79" - cell $eq $eq$ls180.v:6721$2395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [13:8] - connect \B 3'100 - connect \Y $eq$ls180.v:6721$2395_Y - end - attribute \src "ls180.v:6723.106-6723.151" - cell $eq $eq$ls180.v:6723$2397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6723$2397_Y - end - attribute \src "ls180.v:6724.109-6724.154" - cell $eq $eq$ls180.v:6724$2401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6724$2401_Y - end - attribute \src "ls180.v:6726.106-6726.151" - cell $eq $eq$ls180.v:6726$2404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6726$2404_Y - end - attribute \src "ls180.v:6727.109-6727.154" - cell $eq $eq$ls180.v:6727$2408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6727$2408_Y - end - attribute \src "ls180.v:6729.106-6729.151" - cell $eq $eq$ls180.v:6729$2411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6729$2411_Y - end - attribute \src "ls180.v:6730.109-6730.154" - cell $eq $eq$ls180.v:6730$2415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6730$2415_Y - end - attribute \src "ls180.v:6732.106-6732.151" - cell $eq $eq$ls180.v:6732$2418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6732$2418_Y - end - attribute \src "ls180.v:6733.109-6733.154" - cell $eq $eq$ls180.v:6733$2422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6733$2422_Y - end - attribute \src "ls180.v:7114.41-7114.81" - cell $eq $eq$ls180.v:7114$2459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:7114$2459_Y - end - attribute \src "ls180.v:7114.144-7114.177" - cell $eq $eq$ls180.v:7114$2460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7114$2460_Y - end - attribute \src "ls180.v:7114.219-7114.252" - cell $eq $eq$ls180.v:7114$2463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7114$2463_Y - end - attribute \src "ls180.v:7114.294-7114.327" - cell $eq $eq$ls180.v:7114$2466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7114$2466_Y - end - attribute \src "ls180.v:7138.41-7138.81" - cell $eq $eq$ls180.v:7138$2475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:7138$2475_Y - end - attribute \src "ls180.v:7138.144-7138.177" - cell $eq $eq$ls180.v:7138$2476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7138$2476_Y - end - attribute \src "ls180.v:7138.219-7138.252" - cell $eq $eq$ls180.v:7138$2479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7138$2479_Y - end - attribute \src "ls180.v:7138.294-7138.327" - cell $eq $eq$ls180.v:7138$2482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7138$2482_Y - end - attribute \src "ls180.v:7162.41-7162.81" - cell $eq $eq$ls180.v:7162$2491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:7162$2491_Y - end - attribute \src "ls180.v:7162.144-7162.177" - cell $eq $eq$ls180.v:7162$2492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7162$2492_Y - end - attribute \src "ls180.v:7162.219-7162.252" - cell $eq $eq$ls180.v:7162$2495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7162$2495_Y - end - attribute \src "ls180.v:7162.294-7162.327" - cell $eq $eq$ls180.v:7162$2498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7162$2498_Y - end - attribute \src "ls180.v:7186.41-7186.81" - cell $eq $eq$ls180.v:7186$2507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:7186$2507_Y - end - attribute \src "ls180.v:7186.144-7186.177" - cell $eq $eq$ls180.v:7186$2508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7186$2508_Y - end - attribute \src "ls180.v:7186.219-7186.252" - cell $eq $eq$ls180.v:7186$2511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7186$2511_Y - end - attribute \src "ls180.v:7186.294-7186.327" - cell $eq $eq$ls180.v:7186$2514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7186$2514_Y - end - attribute \src "ls180.v:7770.8-7770.38" - cell $eq $eq$ls180.v:7770$2606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_value - connect \B 1'0 - connect \Y $eq$ls180.v:7770$2606_Y - end - attribute \src "ls180.v:7817.8-7817.42" - cell $eq $eq$ls180.v:7817$2626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'0 - connect \Y $eq$ls180.v:7817$2626_Y - end - attribute \src "ls180.v:7837.38-7837.74" - cell $eq $eq$ls180.v:7837$2629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $eq$ls180.v:7837$2629_Y - end - attribute \src "ls180.v:7844.7-7844.43" - cell $eq $eq$ls180.v:7844$2631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 2'10 - connect \Y $eq$ls180.v:7844$2631_Y - end - attribute \src "ls180.v:7851.7-7851.43" - cell $eq $eq$ls180.v:7851$2632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7851$2632_Y - end - attribute \src "ls180.v:7859.7-7859.43" - cell $eq $eq$ls180.v:7859$2633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7859$2633_Y - end - attribute \src "ls180.v:7911.9-7911.54" - cell $eq $eq$ls180.v:7911$2651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7911$2651_Y - end - attribute \src "ls180.v:7957.9-7957.54" - cell $eq $eq$ls180.v:7957$2667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7957$2667_Y - end - attribute \src "ls180.v:8003.9-8003.54" - cell $eq $eq$ls180.v:8003$2683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:8003$2683_Y - end - attribute \src "ls180.v:8049.9-8049.54" - cell $eq $eq$ls180.v:8049$2699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:8049$2699_Y - end - attribute \src "ls180.v:8199.9-8199.41" - cell $eq $eq$ls180.v:8199$2711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:8199$2711_Y - end - attribute \src "ls180.v:8214.9-8214.41" - cell $eq $eq$ls180.v:8214$2714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:8214$2714_Y - end - attribute \src "ls180.v:8220.49-8220.82" - cell $eq $eq$ls180.v:8220$2715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8220$2715_Y - end - attribute \src "ls180.v:8220.131-8220.164" - cell $eq $eq$ls180.v:8220$2718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8220$2718_Y - end - attribute \src "ls180.v:8220.213-8220.246" - cell $eq $eq$ls180.v:8220$2721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8220$2721_Y - end - attribute \src "ls180.v:8220.295-8220.328" - cell $eq $eq$ls180.v:8220$2724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8220$2724_Y - end - attribute \src "ls180.v:8221.50-8221.83" - cell $eq $eq$ls180.v:8221$2727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8221$2727_Y - end - attribute \src "ls180.v:8221.132-8221.165" - cell $eq $eq$ls180.v:8221$2730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8221$2730_Y - end - attribute \src "ls180.v:8221.214-8221.247" - cell $eq $eq$ls180.v:8221$2733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8221$2733_Y - end - attribute \src "ls180.v:8221.296-8221.329" - cell $eq $eq$ls180.v:8221$2736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8221$2736_Y - end - attribute \src "ls180.v:8256.9-8256.42" - cell $eq $eq$ls180.v:8256$2748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_bitcount - connect \B 4'1000 - connect \Y $eq$ls180.v:8256$2748_Y - end - attribute \src "ls180.v:8259.10-8259.43" - cell $eq $eq$ls180.v:8259$2749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:8259$2749_Y - end - attribute \src "ls180.v:8285.9-8285.42" - cell $eq $eq$ls180.v:8285$2755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_bitcount - connect \B 1'0 - connect \Y $eq$ls180.v:8285$2755_Y - end - attribute \src "ls180.v:8290.10-8290.43" - cell $eq $eq$ls180.v:8290$2756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:8290$2756_Y - end - attribute \src "ls180.v:8497.9-8497.53" - cell $eq $eq$ls180.v:8497$2805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8497$2805_Y - end - attribute \src "ls180.v:8578.9-8578.54" - cell $eq $eq$ls180.v:8578$2817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8578$2817_Y - end - attribute \src "ls180.v:8657.9-8657.55" - cell $eq $eq$ls180.v:8657$2829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $eq$ls180.v:8657$2829_Y - end - attribute \src "ls180.v:8880.9-8880.49" - cell $eq $eq$ls180.v:8880$2862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8880$2862_Y - end - attribute \src "ls180.v:8456.8-8456.54" - cell $ge $ge$ls180.v:8456$2797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8456$2796_Y - connect \Y $ge$ls180.v:8456$2797_Y - end - attribute \src "ls180.v:8470.8-8470.54" - cell $ge $ge$ls180.v:8470$2801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8470$2800_Y - connect \Y $ge$ls180.v:8470$2801_Y - end - attribute \src "ls180.v:5339.47-5339.83" - cell $gt $gt$ls180.v:5339$1064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $gt$ls180.v:5339$1064_Y - end - attribute \src "ls180.v:5345.7-5345.43" - cell $lt $lt$ls180.v:5345$1067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 4'1000 - connect \Y $lt$ls180.v:5345$1067_Y - end - attribute \src "ls180.v:8451.8-8451.43" - cell $lt $lt$ls180.v:8451$2795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm0_counter - connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8451$2795_Y - end - attribute \src "ls180.v:8465.8-8465.43" - cell $lt $lt$ls180.v:8465$2799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm1_counter - connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8465$2799_Y - end - attribute \src "ls180.v:10370.33-10370.36" - cell $memrd $memrd$\mem$ls180.v:10370$2916 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr - connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10370$2916_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10398.27-10398.32" - cell $memrd $memrd$\mem_1$ls180.v:10398$2942 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_1 - connect \CLK 1'x - connect \DATA $memrd$\mem_1$ls180.v:10398$2942_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10426.27-10426.32" - cell $memrd $memrd$\mem_2$ls180.v:10426$2968 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_2 - connect \CLK 1'x - connect \DATA $memrd$\mem_2$ls180.v:10426$2968_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10454.27-10454.32" - cell $memrd $memrd$\mem_3$ls180.v:10454$2994 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_3 - connect \CLK 1'x - connect \DATA $memrd$\mem_3$ls180.v:10454$2994_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10482.27-10482.32" - cell $memrd $memrd$\mem_4$ls180.v:10482$3020 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_4 - connect \CLK 1'x - connect \DATA $memrd$\mem_4$ls180.v:10482$3020_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10493.12-10493.19" - cell $memrd $memrd$\storage$ls180.v:10493$3025 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10493$3025_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10500.68-10500.75" - cell $memrd $memrd$\storage$ls180.v:10500$3027 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10500$3027_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10507.14-10507.23" - cell $memrd $memrd$\storage_1$ls180.v:10507$3032 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10507$3032_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10514.68-10514.77" - cell $memrd $memrd$\storage_1$ls180.v:10514$3034 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10514$3034_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10521.14-10521.23" - cell $memrd $memrd$\storage_2$ls180.v:10521$3039 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10521$3039_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10528.68-10528.77" - cell $memrd $memrd$\storage_2$ls180.v:10528$3041 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10528$3041_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10535.14-10535.23" - cell $memrd $memrd$\storage_3$ls180.v:10535$3046 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10535$3046_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10542.68-10542.77" - cell $memrd $memrd$\storage_3$ls180.v:10542$3048 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10542$3048_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10550.14-10550.23" - cell $memrd $memrd$\storage_4$ls180.v:10550$3053 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_tx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10550$3053_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10555.15-10555.24" - cell $memrd $memrd$\storage_4$ls180.v:10555$3055 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_tx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10555$3055_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10567.14-10567.23" - cell $memrd $memrd$\storage_5$ls180.v:10567$3060 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_rx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10567$3060_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10572.15-10572.24" - cell $memrd $memrd$\storage_5$ls180.v:10572$3062 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_rx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10572$3062_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10583.14-10583.23" - cell $memrd $memrd$\storage_6$ls180.v:10583$3067 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdblock2mem_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10583$3067_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10590.45-10590.54" - cell $memrd $memrd$\storage_6$ls180.v:10590$3069 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdblock2mem_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10590$3069_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10597.14-10597.23" - cell $memrd $memrd$\storage_7$ls180.v:10597$3074 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdmem2block_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10597$3074_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10604.45-10604.54" - cell $memrd $memrd$\storage_7$ls180.v:10604$3076 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdmem2block_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10604$3076_DATA - connect \EN 1'x - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3078 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3078 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10352$1_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10352$1_DATA - connect \EN $memwr$\mem$ls180.v:10352$1_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3079 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3079 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10354$2_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10354$2_DATA - connect \EN $memwr$\mem$ls180.v:10354$2_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3080 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3080 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10356$3_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10356$3_DATA - connect \EN $memwr$\mem$ls180.v:10356$3_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3081 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3081 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10358$4_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10358$4_DATA - connect \EN $memwr$\mem$ls180.v:10358$4_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3082 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3082 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10360$5_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10360$5_DATA - connect \EN $memwr$\mem$ls180.v:10360$5_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3083 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3083 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10362$6_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10362$6_DATA - connect \EN $memwr$\mem$ls180.v:10362$6_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3084 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3084 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10364$7_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10364$7_DATA - connect \EN $memwr$\mem$ls180.v:10364$7_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3085 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 3085 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10366$8_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10366$8_DATA - connect \EN $memwr$\mem$ls180.v:10366$8_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3086 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3086 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10380$9_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10380$9_DATA - connect \EN $memwr$\mem_1$ls180.v:10380$9_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3087 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3087 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10382$10_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10382$10_DATA - connect \EN $memwr$\mem_1$ls180.v:10382$10_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3088 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3088 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10384$11_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10384$11_DATA - connect \EN $memwr$\mem_1$ls180.v:10384$11_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3089 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3089 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10386$12_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10386$12_DATA - connect \EN $memwr$\mem_1$ls180.v:10386$12_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3090 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3090 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10388$13_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10388$13_DATA - connect \EN $memwr$\mem_1$ls180.v:10388$13_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3091 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3091 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10390$14_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10390$14_DATA - connect \EN $memwr$\mem_1$ls180.v:10390$14_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3092 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3092 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10392$15_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10392$15_DATA - connect \EN $memwr$\mem_1$ls180.v:10392$15_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3093 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 3093 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10394$16_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10394$16_DATA - connect \EN $memwr$\mem_1$ls180.v:10394$16_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3094 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3094 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10408$17_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10408$17_DATA - connect \EN $memwr$\mem_2$ls180.v:10408$17_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3095 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3095 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10410$18_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10410$18_DATA - connect \EN $memwr$\mem_2$ls180.v:10410$18_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3096 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3096 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10412$19_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10412$19_DATA - connect \EN $memwr$\mem_2$ls180.v:10412$19_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3097 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3097 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10414$20_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10414$20_DATA - connect \EN $memwr$\mem_2$ls180.v:10414$20_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3098 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3098 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10416$21_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10416$21_DATA - connect \EN $memwr$\mem_2$ls180.v:10416$21_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3099 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3099 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10418$22_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10418$22_DATA - connect \EN $memwr$\mem_2$ls180.v:10418$22_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3100 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3100 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10420$23_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10420$23_DATA - connect \EN $memwr$\mem_2$ls180.v:10420$23_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3101 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3101 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10422$24_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10422$24_DATA - connect \EN $memwr$\mem_2$ls180.v:10422$24_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3102 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3102 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10436$25_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10436$25_DATA - connect \EN $memwr$\mem_3$ls180.v:10436$25_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3103 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3103 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10438$26_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10438$26_DATA - connect \EN $memwr$\mem_3$ls180.v:10438$26_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3104 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3104 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10440$27_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10440$27_DATA - connect \EN $memwr$\mem_3$ls180.v:10440$27_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3105 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3105 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10442$28_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10442$28_DATA - connect \EN $memwr$\mem_3$ls180.v:10442$28_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3106 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3106 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10444$29_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10444$29_DATA - connect \EN $memwr$\mem_3$ls180.v:10444$29_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3107 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3107 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10446$30_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10446$30_DATA - connect \EN $memwr$\mem_3$ls180.v:10446$30_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3108 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3108 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10448$31_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10448$31_DATA - connect \EN $memwr$\mem_3$ls180.v:10448$31_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3109 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3109 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10450$32_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10450$32_DATA - connect \EN $memwr$\mem_3$ls180.v:10450$32_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3110 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3110 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10464$33_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10464$33_DATA - connect \EN $memwr$\mem_4$ls180.v:10464$33_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3111 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3111 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10466$34_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10466$34_DATA - connect \EN $memwr$\mem_4$ls180.v:10466$34_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3112 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3112 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10468$35_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10468$35_DATA - connect \EN $memwr$\mem_4$ls180.v:10468$35_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3113 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3113 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10470$36_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10470$36_DATA - connect \EN $memwr$\mem_4$ls180.v:10470$36_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3114 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3114 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10472$37_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10472$37_DATA - connect \EN $memwr$\mem_4$ls180.v:10472$37_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3115 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3115 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10474$38_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10474$38_DATA - connect \EN $memwr$\mem_4$ls180.v:10474$38_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3116 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3116 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10476$39_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10476$39_DATA - connect \EN $memwr$\mem_4$ls180.v:10476$39_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3117 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3117 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10478$40_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10478$40_DATA - connect \EN $memwr$\mem_4$ls180.v:10478$40_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$3118 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \PRIORITY 3118 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10492$41_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10492$41_DATA - connect \EN $memwr$\storage$ls180.v:10492$41_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$3119 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \PRIORITY 3119 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10506$42_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10506$42_DATA - connect \EN $memwr$\storage_1$ls180.v:10506$42_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$3120 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \PRIORITY 3120 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10520$43_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10520$43_DATA - connect \EN $memwr$\storage_2$ls180.v:10520$43_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$3121 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \PRIORITY 3121 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10534$44_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10534$44_DATA - connect \EN $memwr$\storage_3$ls180.v:10534$44_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$3122 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \PRIORITY 3122 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10549$45_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10549$45_DATA - connect \EN $memwr$\storage_4$ls180.v:10549$45_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$3123 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \PRIORITY 3123 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10566$46_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10566$46_DATA - connect \EN $memwr$\storage_5$ls180.v:10566$46_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$3124 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \PRIORITY 3124 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10582$47_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10582$47_DATA - connect \EN $memwr$\storage_6$ls180.v:10582$47_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$3125 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \PRIORITY 3125 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10596$48_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10596$48_DATA - connect \EN $memwr$\storage_7$ls180.v:10596$48_EN - end - attribute \src "ls180.v:3086.41-3086.71" - cell $ne $ne$ls180.v:3086$108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_value - connect \B 1'0 - connect \Y $ne$ls180.v:3086$108_Y - end - attribute \src "ls180.v:3303.70-3303.104" - cell $ne $ne$ls180.v:3303$222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:3303$222_Y - end - attribute \src "ls180.v:3364.8-3364.142" - cell $ne $ne$ls180.v:3364$241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3364$241_Y - end - attribute \src "ls180.v:3396.75-3396.133" - cell $ne $ne$ls180.v:3396$248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3396$248_Y - end - attribute \src "ls180.v:3397.75-3397.133" - cell $ne $ne$ls180.v:3397$249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3397$249_Y - end - attribute \src "ls180.v:3521.8-3521.142" - cell $ne $ne$ls180.v:3521$271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3521$271_Y - end - attribute \src "ls180.v:3553.75-3553.133" - cell $ne $ne$ls180.v:3553$278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3553$278_Y - end - attribute \src "ls180.v:3554.75-3554.133" - cell $ne $ne$ls180.v:3554$279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3554$279_Y - end - attribute \src "ls180.v:3678.8-3678.142" - cell $ne $ne$ls180.v:3678$301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3678$301_Y - end - attribute \src "ls180.v:3710.75-3710.133" - cell $ne $ne$ls180.v:3710$308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3710$308_Y - end - attribute \src "ls180.v:3711.75-3711.133" - cell $ne $ne$ls180.v:3711$309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3711$309_Y - end - attribute \src "ls180.v:3835.8-3835.142" - cell $ne $ne$ls180.v:3835$331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3835$331_Y - end - attribute \src "ls180.v:3867.75-3867.133" - cell $ne $ne$ls180.v:3867$338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3867$338_Y - end - attribute \src "ls180.v:3868.75-3868.133" - cell $ne $ne$ls180.v:3868$339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3868$339_Y - end - attribute \src "ls180.v:4360.47-4360.80" - cell $ne $ne$ls180.v:4360$737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:4360$737_Y - end - attribute \src "ls180.v:4361.47-4361.79" - cell $ne $ne$ls180.v:4361$738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:4361$738_Y - end - attribute \src "ls180.v:4390.47-4390.80" - cell $ne $ne$ls180.v:4390$748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:4390$748_Y - end - attribute \src "ls180.v:4391.47-4391.79" - cell $ne $ne$ls180.v:4391$749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:4391$749_Y - end - attribute \src "ls180.v:4871.32-4871.89" - cell $ne $ne$ls180.v:4871$831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $ne$ls180.v:4871$831_Y - end - attribute \src "ls180.v:5518.10-5518.56" - cell $ne $ne$ls180.v:5518$1128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 2'10 - connect \Y $ne$ls180.v:5518$1128_Y - end - attribute \src "ls180.v:5623.51-5623.87" - cell $ne $ne$ls180.v:5623$1142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5623$1142_Y - end - attribute \src "ls180.v:5624.51-5624.86" - cell $ne $ne$ls180.v:5624$1143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5624$1143_Y - end - attribute \src "ls180.v:5843.51-5843.87" - cell $ne $ne$ls180.v:5843$1173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5843$1173_Y - end - attribute \src "ls180.v:5844.51-5844.86" - cell $ne $ne$ls180.v:5844$1174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5844$1174_Y - end - attribute \src "ls180.v:5875.79-5875.119" - cell $ne $ne$ls180.v:5875$1177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_sel - connect \B 1'0 - connect \Y $ne$ls180.v:5875$1177_Y - end - attribute \src "ls180.v:7760.7-7760.52" - cell $ne $ne$ls180.v:7760$2601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_bus_errors - connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7760$2601_Y - end - attribute \src "ls180.v:7826.9-7826.43" - cell $ne $ne$ls180.v:7826$2627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:7826$2627_Y - end - attribute \src "ls180.v:7862.8-7862.44" - cell $ne $ne$ls180.v:7862$2634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $ne$ls180.v:7862$2634_Y - end - attribute \src "ls180.v:8800.9-8800.47" - cell $ne $ne$ls180.v:8800$2849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 4'1010 - connect \Y $ne$ls180.v:8800$2849_Y - end - attribute \src "ls180.v:2890.33-2890.73" - cell $not $not$ls180.v:2890$50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_converted_interface_cyc - connect \Y $not$ls180.v:2890$50_Y - end - attribute \src "ls180.v:2929.48-2929.69" - cell $not $not$ls180.v:2929$55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter0_skip - connect \Y $not$ls180.v:2929$55_Y - end - attribute \src "ls180.v:2930.48-2930.69" - cell $not $not$ls180.v:2930$56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter0_skip - connect \Y $not$ls180.v:2930$56_Y - end - attribute \src "ls180.v:2950.33-2950.73" - cell $not $not$ls180.v:2950$61 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_converted_interface_cyc - connect \Y $not$ls180.v:2950$61_Y - end - attribute \src "ls180.v:2989.48-2989.69" - cell $not $not$ls180.v:2989$66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter1_skip - connect \Y $not$ls180.v:2989$66_Y - end - attribute \src "ls180.v:2990.48-2990.69" - cell $not $not$ls180.v:2990$67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter1_skip - connect \Y $not$ls180.v:2990$67_Y - end - attribute \src "ls180.v:3010.36-3010.79" - cell $not $not$ls180.v:3010$72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_converted_interface_cyc - connect \Y $not$ls180.v:3010$72_Y - end - attribute \src "ls180.v:3049.27-3049.51" - cell $not $not$ls180.v:3049$77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_skip - connect \Y $not$ls180.v:3049$77_Y - end - attribute \src "ls180.v:3050.27-3050.51" - cell $not $not$ls180.v:3050$78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_skip - connect \Y $not$ls180.v:3050$78_Y - end - attribute \src "ls180.v:3252.34-3252.64" - cell $not $not$ls180.v:3252$214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3252$214_Y - end - attribute \src "ls180.v:3253.31-3253.61" - cell $not $not$ls180.v:3253$215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3253$215_Y - end - attribute \src "ls180.v:3254.32-3254.62" - cell $not $not$ls180.v:3254$216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3254$216_Y - end - attribute \src "ls180.v:3255.32-3255.62" - cell $not $not$ls180.v:3255$217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3255$217_Y - end - attribute \src "ls180.v:3297.33-3297.56" - cell $not $not$ls180.v:3297$220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3297$220_Y - end - attribute \src "ls180.v:3398.58-3398.106" - cell $not $not$ls180.v:3398$250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3398$250_Y - end - attribute \src "ls180.v:3452.9-3452.45" - cell $not $not$ls180.v:3452$255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3452$255_Y - end - attribute \src "ls180.v:3555.58-3555.106" - cell $not $not$ls180.v:3555$280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3555$280_Y - end - attribute \src "ls180.v:3609.9-3609.45" - cell $not $not$ls180.v:3609$285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3609$285_Y - end - attribute \src "ls180.v:3712.58-3712.106" - cell $not $not$ls180.v:3712$310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3712$310_Y - end - attribute \src "ls180.v:3766.9-3766.45" - cell $not $not$ls180.v:3766$315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3766$315_Y - end - attribute \src "ls180.v:3869.58-3869.106" - cell $not $not$ls180.v:3869$340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3869$340_Y - end - attribute \src "ls180.v:3923.9-3923.45" - cell $not $not$ls180.v:3923$345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3923$345_Y - end - attribute \src "ls180.v:3965.149-3965.187" - cell $not $not$ls180.v:3965$348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3965$348_Y - end - attribute \src "ls180.v:3965.193-3965.230" - cell $not $not$ls180.v:3965$350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3965$350_Y - end - attribute \src "ls180.v:3966.149-3966.187" - cell $not $not$ls180.v:3966$354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3966$354_Y - end - attribute \src "ls180.v:3966.193-3966.230" - cell $not $not$ls180.v:3966$356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3966$356_Y - end - attribute \src "ls180.v:3982.43-3982.73" - cell $not $not$ls180.v:3982$384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3982$384_Y - end - attribute \src "ls180.v:3985.205-3985.245" - cell $not $not$ls180.v:3985$387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3985$387_Y - end - attribute \src "ls180.v:3985.251-3985.290" - cell $not $not$ls180.v:3985$389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3985$389_Y - end - attribute \src "ls180.v:3985.159-3985.292" - cell $not $not$ls180.v:3985$391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3985$390_Y - connect \Y $not$ls180.v:3985$391_Y - end - attribute \src "ls180.v:3986.205-3986.245" - cell $not $not$ls180.v:3986$400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3986$400_Y - end - attribute \src "ls180.v:3986.251-3986.290" - cell $not $not$ls180.v:3986$402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3986$402_Y - end - attribute \src "ls180.v:3986.159-3986.292" - cell $not $not$ls180.v:3986$404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3986$403_Y - connect \Y $not$ls180.v:3986$404_Y - end - attribute \src "ls180.v:3987.205-3987.245" - cell $not $not$ls180.v:3987$413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3987$413_Y - end - attribute \src "ls180.v:3987.251-3987.290" - cell $not $not$ls180.v:3987$415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3987$415_Y - end - attribute \src "ls180.v:3987.159-3987.292" - cell $not $not$ls180.v:3987$417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3987$416_Y - connect \Y $not$ls180.v:3987$417_Y - end - attribute \src "ls180.v:3988.205-3988.245" - cell $not $not$ls180.v:3988$426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3988$426_Y - end - attribute \src "ls180.v:3988.251-3988.290" - cell $not $not$ls180.v:3988$428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3988$428_Y - end - attribute \src "ls180.v:3988.159-3988.292" - cell $not $not$ls180.v:3988$430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$429_Y - connect \Y $not$ls180.v:3988$430_Y - end - attribute \src "ls180.v:4015.71-4015.103" - cell $not $not$ls180.v:4015$441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:4015$441_Y - end - attribute \src "ls180.v:4018.205-4018.245" - cell $not $not$ls180.v:4018$445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:4018$445_Y - end - attribute \src "ls180.v:4018.251-4018.290" - cell $not $not$ls180.v:4018$447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:4018$447_Y - end - attribute \src "ls180.v:4018.159-4018.292" - cell $not $not$ls180.v:4018$449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4018$448_Y - connect \Y $not$ls180.v:4018$449_Y - end - attribute \src "ls180.v:4019.205-4019.245" - cell $not $not$ls180.v:4019$458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:4019$458_Y - end - attribute \src "ls180.v:4019.251-4019.290" - cell $not $not$ls180.v:4019$460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:4019$460_Y - end - attribute \src "ls180.v:4019.159-4019.292" - cell $not $not$ls180.v:4019$462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4019$461_Y - connect \Y $not$ls180.v:4019$462_Y - end - attribute \src "ls180.v:4020.205-4020.245" - cell $not $not$ls180.v:4020$471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:4020$471_Y - end - attribute \src "ls180.v:4020.251-4020.290" - cell $not $not$ls180.v:4020$473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:4020$473_Y - end - attribute \src "ls180.v:4020.159-4020.292" - cell $not $not$ls180.v:4020$475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4020$474_Y - connect \Y $not$ls180.v:4020$475_Y - end - attribute \src "ls180.v:4021.205-4021.245" - cell $not $not$ls180.v:4021$484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:4021$484_Y - end - attribute \src "ls180.v:4021.251-4021.290" - cell $not $not$ls180.v:4021$486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:4021$486_Y - end - attribute \src "ls180.v:4021.159-4021.292" - cell $not $not$ls180.v:4021$488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$487_Y - connect \Y $not$ls180.v:4021$488_Y - end - attribute \src "ls180.v:4084.71-4084.103" - cell $not $not$ls180.v:4084$527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:4084$527_Y - end - attribute \src "ls180.v:4105.112-4105.150" - cell $not $not$ls180.v:4105$530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4105$530_Y - end - attribute \src "ls180.v:4105.156-4105.193" - cell $not $not$ls180.v:4105$532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4105$532_Y - end - attribute \src "ls180.v:4105.68-4105.195" - cell $not $not$ls180.v:4105$534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4105$533_Y - connect \Y $not$ls180.v:4105$534_Y - end - attribute \src "ls180.v:4113.11-4113.38" - cell $not $not$ls180.v:4113$537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_write_available - connect \Y $not$ls180.v:4113$537_Y - end - attribute \src "ls180.v:4143.112-4143.150" - cell $not $not$ls180.v:4143$539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4143$539_Y - end - attribute \src "ls180.v:4143.156-4143.193" - cell $not $not$ls180.v:4143$541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4143$541_Y - end - attribute \src "ls180.v:4143.68-4143.195" - cell $not $not$ls180.v:4143$543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4143$542_Y - connect \Y $not$ls180.v:4143$543_Y - end - attribute \src "ls180.v:4151.11-4151.37" - cell $not $not$ls180.v:4151$546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_read_available - connect \Y $not$ls180.v:4151$546_Y - end - attribute \src "ls180.v:4161.87-4161.331" - cell $not $not$ls180.v:4161$558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4161$557_Y - connect \Y $not$ls180.v:4161$558_Y - end - attribute \src "ls180.v:4162.35-4162.68" - cell $not $not$ls180.v:4162$561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:4162$561_Y - end - attribute \src "ls180.v:4162.73-4162.105" - cell $not $not$ls180.v:4162$562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:4162$562_Y - end - attribute \src "ls180.v:4166.87-4166.331" - cell $not $not$ls180.v:4166$574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4166$573_Y - connect \Y $not$ls180.v:4166$574_Y - end - attribute \src "ls180.v:4167.35-4167.68" - cell $not $not$ls180.v:4167$577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:4167$577_Y - end - attribute \src "ls180.v:4167.73-4167.105" - cell $not $not$ls180.v:4167$578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:4167$578_Y - end - attribute \src "ls180.v:4171.87-4171.331" - cell $not $not$ls180.v:4171$590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4171$589_Y - connect \Y $not$ls180.v:4171$590_Y - end - attribute \src "ls180.v:4172.35-4172.68" - cell $not $not$ls180.v:4172$593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:4172$593_Y - end - attribute \src "ls180.v:4172.73-4172.105" - cell $not $not$ls180.v:4172$594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:4172$594_Y - end - attribute \src "ls180.v:4176.87-4176.331" - cell $not $not$ls180.v:4176$606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4176$605_Y - connect \Y $not$ls180.v:4176$606_Y - end - attribute \src "ls180.v:4177.35-4177.68" - cell $not $not$ls180.v:4177$609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:4177$609_Y - end - attribute \src "ls180.v:4177.73-4177.105" - cell $not $not$ls180.v:4177$610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:4177$610_Y - end - attribute \src "ls180.v:4181.128-4181.372" - cell $not $not$ls180.v:4181$623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$622_Y - connect \Y $not$ls180.v:4181$623_Y - end - attribute \src "ls180.v:4181.502-4181.746" - cell $not $not$ls180.v:4181$639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$638_Y - connect \Y $not$ls180.v:4181$639_Y - end - attribute \src "ls180.v:4181.876-4181.1120" - cell $not $not$ls180.v:4181$655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$654_Y - connect \Y $not$ls180.v:4181$655_Y - end - attribute \src "ls180.v:4181.1250-4181.1494" - cell $not $not$ls180.v:4181$671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$670_Y - connect \Y $not$ls180.v:4181$671_Y - end - attribute \src "ls180.v:4203.32-4203.50" - cell $not $not$ls180.v:4203$677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:4203$677_Y - end - attribute \src "ls180.v:4242.30-4242.50" - cell $not $not$ls180.v:4242$682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:4242$682_Y - end - attribute \src "ls180.v:4243.30-4243.50" - cell $not $not$ls180.v:4243$683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:4243$683_Y - end - attribute \src "ls180.v:4268.27-4268.48" - cell $not $not$ls180.v:4268$689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4268$689_Y - end - attribute \src "ls180.v:4269.30-4269.50" - cell $not $not$ls180.v:4269$690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4269$690_Y - end - attribute \src "ls180.v:4270.80-4270.98" - cell $not $not$ls180.v:4270$692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4270$692_Y - end - attribute \src "ls180.v:4271.107-4271.127" - cell $not $not$ls180.v:4271$696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4271$696_Y - end - attribute \src "ls180.v:4272.78-4272.103" - cell $not $not$ls180.v:4272$699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4272$699_Y - end - attribute \src "ls180.v:4273.91-4273.111" - cell $not $not$ls180.v:4273$702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4273$702_Y - end - attribute \src "ls180.v:4289.35-4289.64" - cell $not $not$ls180.v:4289$711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4289$711_Y - end - attribute \src "ls180.v:4290.36-4290.67" - cell $not $not$ls180.v:4290$712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4290$712_Y - end - attribute \src "ls180.v:4296.32-4296.61" - cell $not $not$ls180.v:4296$713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4296$713_Y - end - attribute \src "ls180.v:4302.36-4302.67" - cell $not $not$ls180.v:4302$714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4302$714_Y - end - attribute \src "ls180.v:4303.35-4303.64" - cell $not $not$ls180.v:4303$715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4303$715_Y - end - attribute \src "ls180.v:4306.32-4306.63" - cell $not $not$ls180.v:4306$718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4306$718_Y - end - attribute \src "ls180.v:4344.81-4344.108" - cell $not $not$ls180.v:4344$728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4344$728_Y - end - attribute \src "ls180.v:4374.81-4374.108" - cell $not $not$ls180.v:4374$739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4374$739_Y - end - attribute \src "ls180.v:4585.60-4585.85" - cell $not $not$ls180.v:4585$790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4585$790_Y - end - attribute \src "ls180.v:4726.54-4726.96" - cell $not $not$ls180.v:4726$804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4726$804_Y - end - attribute \src "ls180.v:4729.48-4729.86" - cell $not $not$ls180.v:4729$807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4729$807_Y - end - attribute \src "ls180.v:4853.55-4853.98" - cell $not $not$ls180.v:4853$825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4853$825_Y - end - attribute \src "ls180.v:4856.49-4856.88" - cell $not $not$ls180.v:4856$828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4856$828_Y - end - attribute \src "ls180.v:4906.30-4906.58" - cell $not $not$ls180.v:4906$834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4906$834_Y - end - attribute \src "ls180.v:4987.56-4987.100" - cell $not $not$ls180.v:4987$840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4987$840_Y - end - attribute \src "ls180.v:4990.50-4990.90" - cell $not $not$ls180.v:4990$843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4990$843_Y - end - attribute \src "ls180.v:5106.42-5106.74" - cell $not $not$ls180.v:5106$859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:5106$859_Y - end - attribute \src "ls180.v:5630.50-5630.88" - cell $not $not$ls180.v:5630$1144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5630$1144_Y - end - attribute \src "ls180.v:5642.52-5642.102" - cell $not $not$ls180.v:5642$1147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5642$1147_Y - end - attribute \src "ls180.v:5701.38-5701.74" - cell $not $not$ls180.v:5701$1154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5701$1154_Y - end - attribute \src "ls180.v:6027.69-6027.88" - cell $not $not$ls180.v:6027$1239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \Y $not$ls180.v:6027$1239_Y - end - attribute \src "ls180.v:6044.63-6044.94" - cell $not $not$ls180.v:6044$1284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6044$1284_Y - end - attribute \src "ls180.v:6047.65-6047.96" - cell $not $not$ls180.v:6047$1291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6047$1291_Y - end - attribute \src "ls180.v:6050.65-6050.96" - cell $not $not$ls180.v:6050$1298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6050$1298_Y - end - attribute \src "ls180.v:6053.65-6053.96" - cell $not $not$ls180.v:6053$1305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6053$1305_Y - end - attribute \src "ls180.v:6056.65-6056.96" - cell $not $not$ls180.v:6056$1312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6056$1312_Y - end - attribute \src "ls180.v:6059.68-6059.99" - cell $not $not$ls180.v:6059$1319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6059$1319_Y - end - attribute \src "ls180.v:6062.68-6062.99" - cell $not $not$ls180.v:6062$1326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6062$1326_Y - end - attribute \src "ls180.v:6065.68-6065.99" - cell $not $not$ls180.v:6065$1333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6065$1333_Y - end - attribute \src "ls180.v:6068.68-6068.99" - cell $not $not$ls180.v:6068$1340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6068$1340_Y - end - attribute \src "ls180.v:6082.60-6082.91" - cell $not $not$ls180.v:6082$1348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6082$1348_Y - end - attribute \src "ls180.v:6085.60-6085.91" - cell $not $not$ls180.v:6085$1355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6085$1355_Y - end - attribute \src "ls180.v:6088.60-6088.91" - cell $not $not$ls180.v:6088$1362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6088$1362_Y - end - attribute \src "ls180.v:6091.60-6091.91" - cell $not $not$ls180.v:6091$1369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6091$1369_Y - end - attribute \src "ls180.v:6094.61-6094.92" - cell $not $not$ls180.v:6094$1376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6094$1376_Y - end - attribute \src "ls180.v:6097.61-6097.92" - cell $not $not$ls180.v:6097$1383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6097$1383_Y - end - attribute \src "ls180.v:6108.59-6108.90" - cell $not $not$ls180.v:6108$1391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:6108$1391_Y - end - attribute \src "ls180.v:6111.58-6111.89" - cell $not $not$ls180.v:6111$1398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:6111$1398_Y - end - attribute \src "ls180.v:6122.64-6122.95" - cell $not $not$ls180.v:6122$1406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6122$1406_Y - end - attribute \src "ls180.v:6125.63-6125.94" - cell $not $not$ls180.v:6125$1413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6125$1413_Y - end - attribute \src "ls180.v:6128.63-6128.94" - cell $not $not$ls180.v:6128$1420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6128$1420_Y - end - attribute \src "ls180.v:6131.63-6131.94" - cell $not $not$ls180.v:6131$1427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6131$1427_Y - end - attribute \src "ls180.v:6134.63-6134.94" - cell $not $not$ls180.v:6134$1434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6134$1434_Y - end - attribute \src "ls180.v:6137.64-6137.95" - cell $not $not$ls180.v:6137$1441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6137$1441_Y - end - attribute \src "ls180.v:6140.64-6140.95" - cell $not $not$ls180.v:6140$1448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6140$1448_Y - end - attribute \src "ls180.v:6143.64-6143.95" - cell $not $not$ls180.v:6143$1455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6143$1455_Y - end - attribute \src "ls180.v:6146.64-6146.95" - cell $not $not$ls180.v:6146$1462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6146$1462_Y - end - attribute \src "ls180.v:6159.64-6159.95" - cell $not $not$ls180.v:6159$1470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6159$1470_Y - end - attribute \src "ls180.v:6162.63-6162.94" - cell $not $not$ls180.v:6162$1477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6162$1477_Y - end - attribute \src "ls180.v:6165.63-6165.94" - cell $not $not$ls180.v:6165$1484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6165$1484_Y - end - attribute \src "ls180.v:6168.63-6168.94" - cell $not $not$ls180.v:6168$1491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6168$1491_Y - end - attribute \src "ls180.v:6171.63-6171.94" - cell $not $not$ls180.v:6171$1498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6171$1498_Y - end - attribute \src "ls180.v:6174.64-6174.95" - cell $not $not$ls180.v:6174$1505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6174$1505_Y - end - attribute \src "ls180.v:6177.64-6177.95" - cell $not $not$ls180.v:6177$1512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6177$1512_Y - end - attribute \src "ls180.v:6180.64-6180.95" - cell $not $not$ls180.v:6180$1519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6180$1519_Y - end - attribute \src "ls180.v:6183.64-6183.95" - cell $not $not$ls180.v:6183$1526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6183$1526_Y - end - attribute \src "ls180.v:6196.66-6196.97" - cell $not $not$ls180.v:6196$1534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6196$1534_Y - end - attribute \src "ls180.v:6199.66-6199.97" - cell $not $not$ls180.v:6199$1541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6199$1541_Y - end - attribute \src "ls180.v:6202.66-6202.97" - cell $not $not$ls180.v:6202$1548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6202$1548_Y - end - attribute \src "ls180.v:6205.66-6205.97" - cell $not $not$ls180.v:6205$1555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6205$1555_Y - end - attribute \src "ls180.v:6208.66-6208.97" - cell $not $not$ls180.v:6208$1562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6208$1562_Y - end - attribute \src "ls180.v:6211.66-6211.97" - cell $not $not$ls180.v:6211$1569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6211$1569_Y - end - attribute \src "ls180.v:6214.66-6214.97" - cell $not $not$ls180.v:6214$1576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6214$1576_Y - end - attribute \src "ls180.v:6217.66-6217.97" - cell $not $not$ls180.v:6217$1583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6217$1583_Y - end - attribute \src "ls180.v:6220.68-6220.99" - cell $not $not$ls180.v:6220$1590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6220$1590_Y - end - attribute \src "ls180.v:6223.68-6223.99" - cell $not $not$ls180.v:6223$1597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6223$1597_Y - end - attribute \src "ls180.v:6226.68-6226.99" - cell $not $not$ls180.v:6226$1604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6226$1604_Y - end - attribute \src "ls180.v:6229.68-6229.99" - cell $not $not$ls180.v:6229$1611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6229$1611_Y - end - attribute \src "ls180.v:6232.68-6232.99" - cell $not $not$ls180.v:6232$1618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6232$1618_Y - end - attribute \src "ls180.v:6235.65-6235.96" - cell $not $not$ls180.v:6235$1625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6235$1625_Y - end - attribute \src "ls180.v:6238.66-6238.97" - cell $not $not$ls180.v:6238$1632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6238$1632_Y - end - attribute \src "ls180.v:6258.70-6258.101" - cell $not $not$ls180.v:6258$1640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6258$1640_Y - end - attribute \src "ls180.v:6261.70-6261.101" - cell $not $not$ls180.v:6261$1647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6261$1647_Y - end - attribute \src "ls180.v:6264.70-6264.101" - cell $not $not$ls180.v:6264$1654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6264$1654_Y - end - attribute \src "ls180.v:6267.70-6267.101" - cell $not $not$ls180.v:6267$1661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6267$1661_Y - end - attribute \src "ls180.v:6270.69-6270.100" - cell $not $not$ls180.v:6270$1668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6270$1668_Y - end - attribute \src "ls180.v:6273.69-6273.100" - cell $not $not$ls180.v:6273$1675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6273$1675_Y - end - attribute \src "ls180.v:6276.69-6276.100" - cell $not $not$ls180.v:6276$1682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6276$1682_Y - end - attribute \src "ls180.v:6279.69-6279.100" - cell $not $not$ls180.v:6279$1689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6279$1689_Y - end - attribute \src "ls180.v:6282.60-6282.91" - cell $not $not$ls180.v:6282$1696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6282$1696_Y - end - attribute \src "ls180.v:6285.71-6285.102" - cell $not $not$ls180.v:6285$1703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6285$1703_Y - end - attribute \src "ls180.v:6288.71-6288.102" - cell $not $not$ls180.v:6288$1710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6288$1710_Y - end - attribute \src "ls180.v:6291.71-6291.102" - cell $not $not$ls180.v:6291$1717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6291$1717_Y - end - attribute \src "ls180.v:6294.71-6294.102" - cell $not $not$ls180.v:6294$1724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6294$1724_Y - end - attribute \src "ls180.v:6297.71-6297.102" - cell $not $not$ls180.v:6297$1731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6297$1731_Y - end - attribute \src "ls180.v:6300.71-6300.102" - cell $not $not$ls180.v:6300$1738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6300$1738_Y - end - attribute \src "ls180.v:6303.70-6303.101" - cell $not $not$ls180.v:6303$1745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6303$1745_Y - end - attribute \src "ls180.v:6306.70-6306.101" - cell $not $not$ls180.v:6306$1752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6306$1752_Y - end - attribute \src "ls180.v:6309.70-6309.101" - cell $not $not$ls180.v:6309$1759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6309$1759_Y - end - attribute \src "ls180.v:6312.70-6312.101" - cell $not $not$ls180.v:6312$1766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6312$1766_Y - end - attribute \src "ls180.v:6315.70-6315.101" - cell $not $not$ls180.v:6315$1773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6315$1773_Y - end - attribute \src "ls180.v:6318.70-6318.101" - cell $not $not$ls180.v:6318$1780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6318$1780_Y - end - attribute \src "ls180.v:6321.70-6321.101" - cell $not $not$ls180.v:6321$1787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6321$1787_Y - end - attribute \src "ls180.v:6324.70-6324.101" - cell $not $not$ls180.v:6324$1794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6324$1794_Y - end - attribute \src "ls180.v:6327.70-6327.101" - cell $not $not$ls180.v:6327$1801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6327$1801_Y - end - attribute \src "ls180.v:6330.70-6330.101" - cell $not $not$ls180.v:6330$1808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6330$1808_Y - end - attribute \src "ls180.v:6333.66-6333.97" - cell $not $not$ls180.v:6333$1815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6333$1815_Y - end - attribute \src "ls180.v:6336.67-6336.98" - cell $not $not$ls180.v:6336$1822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6336$1822_Y - end - attribute \src "ls180.v:6339.70-6339.101" - cell $not $not$ls180.v:6339$1829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6339$1829_Y - end - attribute \src "ls180.v:6342.70-6342.101" - cell $not $not$ls180.v:6342$1836 - parameter \A_SIGNED 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parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6661$2313_Y - end - attribute \src "ls180.v:6664.77-6664.109" - cell $not $not$ls180.v:6664$2320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6664$2320_Y - end - attribute \src "ls180.v:6667.78-6667.110" - cell $not $not$ls180.v:6667$2327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6667$2327_Y - end - attribute \src "ls180.v:6670.69-6670.101" - cell $not $not$ls180.v:6670$2334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6670$2334_Y - end - attribute \src "ls180.v:6690.55-6690.87" - cell $not $not$ls180.v:6690$2342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6690$2342_Y - end - attribute \src "ls180.v:6693.65-6693.97" - cell $not $not$ls180.v:6693$2349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6693$2349_Y - end - attribute \src "ls180.v:6696.66-6696.98" - cell $not $not$ls180.v:6696$2356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6696$2356_Y - end - attribute \src "ls180.v:6699.70-6699.102" - cell $not $not$ls180.v:6699$2363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6699$2363_Y - end - attribute \src "ls180.v:6702.71-6702.103" - cell $not $not$ls180.v:6702$2370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6702$2370_Y - end - attribute \src "ls180.v:6705.69-6705.101" - cell $not $not$ls180.v:6705$2377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6705$2377_Y - end - attribute \src "ls180.v:6708.66-6708.98" - cell $not $not$ls180.v:6708$2384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6708$2384_Y - end - attribute \src "ls180.v:6711.65-6711.97" - cell $not $not$ls180.v:6711$2391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6711$2391_Y - end - attribute \src "ls180.v:6724.71-6724.103" - cell $not $not$ls180.v:6724$2399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6724$2399_Y - end - attribute \src "ls180.v:6727.71-6727.103" - cell $not $not$ls180.v:6727$2406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6727$2406_Y - end - attribute \src "ls180.v:6730.71-6730.103" - cell $not $not$ls180.v:6730$2413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6730$2413_Y - end - attribute \src "ls180.v:6733.71-6733.103" - cell $not $not$ls180.v:6733$2420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6733$2420_Y - end - attribute \src "ls180.v:7114.86-7114.330" - cell $not $not$ls180.v:7114$2469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7114$2468_Y - connect \Y $not$ls180.v:7114$2469_Y - end - attribute \src "ls180.v:7138.86-7138.330" - cell $not $not$ls180.v:7138$2485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7138$2484_Y - connect \Y $not$ls180.v:7138$2485_Y - end - attribute \src "ls180.v:7162.86-7162.330" - cell $not $not$ls180.v:7162$2501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7162$2500_Y - connect \Y $not$ls180.v:7162$2501_Y - end - attribute \src "ls180.v:7186.86-7186.330" - cell $not $not$ls180.v:7186$2517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7186$2516_Y - connect \Y $not$ls180.v:7186$2517_Y - end - attribute \src "ls180.v:7687.18-7687.42" - cell $not $not$ls180.v:7687$2571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7687$2571_Y - end - attribute \src "ls180.v:7766.72-7766.101" - cell $not $not$ls180.v:7766$2604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7766$2604_Y - end - attribute \src "ls180.v:7785.8-7785.38" - cell $not $not$ls180.v:7785$2608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7785$2608_Y - end - attribute \src "ls180.v:7789.70-7789.98" - cell $not $not$ls180.v:7789$2611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_ack - connect \Y $not$ls180.v:7789$2611_Y - end - attribute \src "ls180.v:7793.70-7793.98" - cell $not $not$ls180.v:7793$2614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_ack - connect \Y $not$ls180.v:7793$2614_Y - end - attribute \src "ls180.v:7797.70-7797.98" - cell $not $not$ls180.v:7797$2617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_ack - connect \Y $not$ls180.v:7797$2617_Y - end - attribute \src "ls180.v:7801.70-7801.98" - cell $not $not$ls180.v:7801$2620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_ack - connect \Y $not$ls180.v:7801$2620_Y - end - attribute \src "ls180.v:7809.32-7809.55" - cell $not $not$ls180.v:7809$2622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7809$2622_Y - end - attribute \src "ls180.v:7879.136-7879.189" - cell $not $not$ls180.v:7879$2637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7879$2637_Y - end - attribute \src "ls180.v:7885.136-7885.189" - cell $not $not$ls180.v:7885$2642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7885$2642_Y - end - attribute \src "ls180.v:7886.8-7886.61" - cell $not $not$ls180.v:7886$2644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7886$2644_Y - end - attribute \src "ls180.v:7894.8-7894.56" - cell $not $not$ls180.v:7894$2647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7894$2647_Y - end - attribute \src "ls180.v:7909.8-7909.46" - cell $not $not$ls180.v:7909$2649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7909$2649_Y - end - attribute \src "ls180.v:7925.136-7925.189" - cell $not $not$ls180.v:7925$2653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7925$2653_Y - end - attribute \src "ls180.v:7931.136-7931.189" - cell $not $not$ls180.v:7931$2658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7931$2658_Y - end - attribute \src "ls180.v:7932.8-7932.61" - cell $not $not$ls180.v:7932$2660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7932$2660_Y - end - attribute \src "ls180.v:7940.8-7940.56" - cell $not $not$ls180.v:7940$2663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7940$2663_Y - end - attribute \src "ls180.v:7955.8-7955.46" - cell $not $not$ls180.v:7955$2665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7955$2665_Y - end - attribute \src "ls180.v:7971.136-7971.189" - cell $not $not$ls180.v:7971$2669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7971$2669_Y - end - attribute \src "ls180.v:7977.136-7977.189" - cell $not $not$ls180.v:7977$2674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7977$2674_Y - end - attribute \src "ls180.v:7978.8-7978.61" - cell $not $not$ls180.v:7978$2676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7978$2676_Y - end - attribute \src "ls180.v:7986.8-7986.56" - cell $not $not$ls180.v:7986$2679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7986$2679_Y - end - attribute \src "ls180.v:8001.8-8001.46" - cell $not $not$ls180.v:8001$2681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:8001$2681_Y - end - attribute \src "ls180.v:8017.136-8017.189" - cell $not $not$ls180.v:8017$2685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8017$2685_Y - end - attribute \src "ls180.v:8023.136-8023.189" - cell $not $not$ls180.v:8023$2690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8023$2690_Y - end - attribute \src "ls180.v:8024.8-8024.61" - cell $not $not$ls180.v:8024$2692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:8024$2692_Y - end - attribute \src "ls180.v:8032.8-8032.56" - cell $not $not$ls180.v:8032$2695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:8032$2695_Y - end - attribute \src "ls180.v:8047.8-8047.46" - cell $not $not$ls180.v:8047$2697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:8047$2697_Y - end - attribute \src "ls180.v:8055.7-8055.22" - cell $not $not$ls180.v:8055$2700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en0 - connect \Y $not$ls180.v:8055$2700_Y - end - attribute \src "ls180.v:8058.8-8058.29" - cell $not $not$ls180.v:8058$2701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:8058$2701_Y - end - attribute \src "ls180.v:8062.7-8062.22" - cell $not $not$ls180.v:8062$2703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en1 - connect \Y $not$ls180.v:8062$2703_Y - end - attribute \src "ls180.v:8065.8-8065.29" - cell $not $not$ls180.v:8065$2704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:8065$2704_Y - end - attribute \src "ls180.v:8184.30-8184.60" - cell $not $not$ls180.v:8184$2706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:8184$2706_Y - end - attribute \src "ls180.v:8185.30-8185.60" - cell $not $not$ls180.v:8185$2707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:8185$2707_Y - end - attribute \src "ls180.v:8186.29-8186.59" - cell $not $not$ls180.v:8186$2708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:8186$2708_Y - end - attribute \src "ls180.v:8197.8-8197.33" - cell $not $not$ls180.v:8197$2709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:8197$2709_Y - end - attribute \src "ls180.v:8212.8-8212.33" - cell $not $not$ls180.v:8212$2712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:8212$2712_Y - end - attribute \src "ls180.v:8248.36-8248.58" - cell $not $not$ls180.v:8248$2742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:8248$2742_Y - end - attribute \src "ls180.v:8248.64-8248.89" - cell $not $not$ls180.v:8248$2744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:8248$2744_Y - end - attribute \src "ls180.v:8277.7-8277.29" - cell $not $not$ls180.v:8277$2751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:8277$2751_Y - end - attribute \src "ls180.v:8278.9-8278.26" - cell $not $not$ls180.v:8278$2752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:8278$2752_Y - end - attribute \src "ls180.v:8311.8-8311.29" - cell $not $not$ls180.v:8311$2758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8311$2758_Y - end - attribute \src "ls180.v:8318.8-8318.29" - cell $not $not$ls180.v:8318$2760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8318$2760_Y - end - attribute \src "ls180.v:8328.80-8328.106" - cell $not $not$ls180.v:8328$2763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8328$2763_Y - end - attribute \src "ls180.v:8334.80-8334.106" - cell $not $not$ls180.v:8334$2768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8334$2768_Y - end - attribute \src "ls180.v:8335.8-8335.34" - cell $not $not$ls180.v:8335$2770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8335$2770_Y - end - attribute \src "ls180.v:8350.80-8350.106" - cell $not $not$ls180.v:8350$2774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8350$2774_Y - end - attribute \src "ls180.v:8356.80-8356.106" - cell $not $not$ls180.v:8356$2779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8356$2779_Y - end - attribute \src "ls180.v:8357.8-8357.34" - cell $not $not$ls180.v:8357$2781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8357$2781_Y - end - attribute \src "ls180.v:8388.22-8388.41" - cell $not $not$ls180.v:8388$2785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8388$2785_Y - end - attribute \src "ls180.v:8388.46-8388.73" - cell $not $not$ls180.v:8388$2786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8388$2786_Y - end - attribute \src "ls180.v:8423.22-8423.40" - cell $not $not$ls180.v:8423$2790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8423$2790_Y - end - attribute \src "ls180.v:8423.45-8423.70" - cell $not $not$ls180.v:8423$2791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8423$2791_Y - end - attribute \src "ls180.v:8477.7-8477.31" - cell $not $not$ls180.v:8477$2802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8477$2802_Y - end - attribute \src "ls180.v:8549.8-8549.46" - cell $not $not$ls180.v:8549$2814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8549$2814_Y - end - attribute \src "ls180.v:8630.8-8630.47" - cell $not $not$ls180.v:8630$2826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8630$2826_Y - end - attribute \src "ls180.v:8691.8-8691.48" - cell $not $not$ls180.v:8691$2838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8691$2838_Y - end - attribute \src "ls180.v:8861.88-8861.118" - cell $not $not$ls180.v:8861$2852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8861$2852_Y - end - attribute \src "ls180.v:8867.88-8867.118" - cell $not $not$ls180.v:8867$2857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8867$2857_Y - end - attribute \src "ls180.v:8868.8-8868.38" - cell $not $not$ls180.v:8868$2859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8868$2859_Y - end - attribute \src "ls180.v:8959.88-8959.118" - cell $not $not$ls180.v:8959$2874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8959$2874_Y - end - attribute \src "ls180.v:8965.88-8965.118" - cell $not $not$ls180.v:8965$2879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8965$2879_Y - end - attribute \src "ls180.v:8966.8-8966.38" - cell $not $not$ls180.v:8966$2881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8966$2881_Y - end - attribute \src "ls180.v:8986.9-8986.28" - cell $not $not$ls180.v:8986$2884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [0] - connect \Y $not$ls180.v:8986$2884_Y - end - attribute \src "ls180.v:9005.9-9005.28" - cell $not $not$ls180.v:9005$2885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [1] - connect \Y $not$ls180.v:9005$2885_Y - end - attribute \src "ls180.v:9024.9-9024.28" - cell $not $not$ls180.v:9024$2886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [2] - connect \Y $not$ls180.v:9024$2886_Y - end - attribute \src "ls180.v:9043.9-9043.28" - cell $not $not$ls180.v:9043$2887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [3] - connect \Y $not$ls180.v:9043$2887_Y - end - attribute \src "ls180.v:9062.9-9062.28" - cell $not $not$ls180.v:9062$2888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [4] - connect \Y $not$ls180.v:9062$2888_Y - end - attribute \src "ls180.v:9083.8-9083.21" - cell $not $not$ls180.v:9083$2889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_done - connect \Y $not$ls180.v:9083$2889_Y - end - attribute \src "ls180.v:10706.8-10706.51" - cell $or $or$ls180.v:10706$3077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sys_rst_1 - connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10706$3077_Y - end - attribute \src "ls180.v:2931.10-2931.71" - cell $or $or$ls180.v:2931$57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_icp_ack - connect \B \main_converter0_skip - connect \Y $or$ls180.v:2931$57_Y - end - attribute \src "ls180.v:2991.10-2991.71" - cell $or $or$ls180.v:2991$68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_ics_ack - connect \B \main_converter1_skip - connect \Y $or$ls180.v:2991$68_Y - end - attribute \src "ls180.v:3051.10-3051.53" - cell $or $or$ls180.v:3051$79 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_ack - connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:3051$79_Y - end - attribute \src "ls180.v:3303.39-3303.105" - cell $or $or$ls180.v:3303$223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3303$222_Y - connect \Y $or$ls180.v:3303$223_Y - end - attribute \src "ls180.v:3346.59-3346.140" - cell $or $or$ls180.v:3346$227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_req_wdata_ready - connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3346$227_Y - end - attribute \src "ls180.v:3347.44-3347.151" - cell $or $or$ls180.v:3347$228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3347$228_Y - end - attribute \src "ls180.v:3355.45-3355.170" - cell $or $or$ls180.v:3355$232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3355$231_Y - connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3355$232_Y - end - attribute \src "ls180.v:3392.127-3392.245" - cell $or $or$ls180.v:3392$245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3392$245_Y - end - attribute \src "ls180.v:3398.57-3398.157" - cell $or $or$ls180.v:3398$251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3398$250_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3398$251_Y - end - attribute \src "ls180.v:3503.59-3503.140" - cell $or $or$ls180.v:3503$257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_req_wdata_ready - connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3503$257_Y - end - attribute \src "ls180.v:3504.44-3504.151" - cell $or $or$ls180.v:3504$258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3504$258_Y - end - attribute \src "ls180.v:3512.45-3512.170" - cell $or $or$ls180.v:3512$262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3512$261_Y - connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3512$262_Y - end - attribute \src "ls180.v:3549.127-3549.245" - cell $or $or$ls180.v:3549$275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3549$275_Y - end - attribute \src "ls180.v:3555.57-3555.157" - cell $or $or$ls180.v:3555$281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3555$280_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3555$281_Y - end - attribute \src "ls180.v:3660.59-3660.140" - cell $or $or$ls180.v:3660$287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_req_wdata_ready - connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3660$287_Y - end - attribute \src "ls180.v:3661.44-3661.151" - cell $or $or$ls180.v:3661$288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3661$288_Y - end - attribute \src "ls180.v:3669.45-3669.170" - cell $or $or$ls180.v:3669$292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3669$291_Y - connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3669$292_Y - end - attribute \src "ls180.v:3706.127-3706.245" - cell $or $or$ls180.v:3706$305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3706$305_Y - end - attribute \src "ls180.v:3712.57-3712.157" - cell $or $or$ls180.v:3712$311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3712$310_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3712$311_Y - end - attribute \src "ls180.v:3817.59-3817.140" - cell $or $or$ls180.v:3817$317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_req_wdata_ready - connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3817$317_Y - end - attribute \src "ls180.v:3818.44-3818.151" - cell $or $or$ls180.v:3818$318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3818$318_Y - end - attribute \src "ls180.v:3826.45-3826.170" - cell $or $or$ls180.v:3826$322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3826$321_Y - connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3826$322_Y - end - attribute \src "ls180.v:3863.127-3863.245" - cell $or $or$ls180.v:3863$335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3863$335_Y - end - attribute \src "ls180.v:3869.57-3869.157" - cell $or $or$ls180.v:3869$341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3869$340_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3869$341_Y - end - attribute \src "ls180.v:3968.107-3968.193" - cell $or $or$ls180.v:3968$361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_is_write - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3968$361_Y - end - attribute \src "ls180.v:3971.39-3971.204" - cell $or $or$ls180.v:3971$367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3971$365_Y - connect \B $and$ls180.v:3971$366_Y - connect \Y $or$ls180.v:3971$367_Y - end - attribute \src "ls180.v:3971.38-3971.289" - cell $or $or$ls180.v:3971$369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3971$367_Y - connect \B $and$ls180.v:3971$368_Y - connect \Y $or$ls180.v:3971$369_Y - end - attribute \src "ls180.v:3971.37-3971.374" - cell $or $or$ls180.v:3971$371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3971$369_Y - connect \B $and$ls180.v:3971$370_Y - connect \Y $or$ls180.v:3971$371_Y - end - attribute \src "ls180.v:3972.40-3972.207" - cell $or $or$ls180.v:3972$374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3972$372_Y - connect \B $and$ls180.v:3972$373_Y - connect \Y $or$ls180.v:3972$374_Y - end - attribute \src "ls180.v:3972.39-3972.293" - cell $or $or$ls180.v:3972$376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3972$374_Y - connect \B $and$ls180.v:3972$375_Y - connect \Y $or$ls180.v:3972$376_Y - end - attribute \src "ls180.v:3972.38-3972.379" - cell $or $or$ls180.v:3972$378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3972$376_Y - connect \B $and$ls180.v:3972$377_Y - connect \Y $or$ls180.v:3972$378_Y - end - attribute \src "ls180.v:3985.158-3985.332" - cell $or $or$ls180.v:3985$392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3985$391_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3985$392_Y - end - attribute \src "ls180.v:3985.75-3985.506" - cell $or $or$ls180.v:3985$397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3985$393_Y - connect \B $and$ls180.v:3985$396_Y - connect \Y $or$ls180.v:3985$397_Y - end - attribute \src "ls180.v:3986.158-3986.332" - cell $or $or$ls180.v:3986$405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3986$404_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3986$405_Y - end - attribute \src "ls180.v:3986.75-3986.506" - cell $or $or$ls180.v:3986$410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3986$406_Y - connect \B $and$ls180.v:3986$409_Y - connect \Y $or$ls180.v:3986$410_Y - end - attribute \src "ls180.v:3987.158-3987.332" - cell $or $or$ls180.v:3987$418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3987$417_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3987$418_Y - end - attribute \src "ls180.v:3987.75-3987.506" - cell $or $or$ls180.v:3987$423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3987$419_Y - connect \B $and$ls180.v:3987$422_Y - connect \Y $or$ls180.v:3987$423_Y - end - attribute \src "ls180.v:3988.158-3988.332" - cell $or $or$ls180.v:3988$431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3988$430_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3988$431_Y - end - attribute \src "ls180.v:3988.75-3988.506" - cell $or $or$ls180.v:3988$436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$432_Y - connect \B $and$ls180.v:3988$435_Y - connect \Y $or$ls180.v:3988$436_Y - end - attribute \src "ls180.v:4015.36-4015.104" - cell $or $or$ls180.v:4015$442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:4015$441_Y - connect \Y $or$ls180.v:4015$442_Y - end - attribute \src "ls180.v:4018.158-4018.332" - cell $or $or$ls180.v:4018$450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4018$449_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4018$450_Y - end - attribute \src "ls180.v:4018.75-4018.506" - cell $or $or$ls180.v:4018$455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4018$451_Y - connect \B $and$ls180.v:4018$454_Y - connect \Y $or$ls180.v:4018$455_Y - end - attribute \src "ls180.v:4019.158-4019.332" - cell $or $or$ls180.v:4019$463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4019$462_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4019$463_Y - end - attribute \src "ls180.v:4019.75-4019.506" - cell $or $or$ls180.v:4019$468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4019$464_Y - connect \B $and$ls180.v:4019$467_Y - connect \Y $or$ls180.v:4019$468_Y - end - attribute \src "ls180.v:4020.158-4020.332" - cell $or $or$ls180.v:4020$476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4020$475_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4020$476_Y - end - attribute \src "ls180.v:4020.75-4020.506" - cell $or $or$ls180.v:4020$481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4020$477_Y - connect \B $and$ls180.v:4020$480_Y - connect \Y $or$ls180.v:4020$481_Y - end - attribute \src "ls180.v:4021.158-4021.332" - cell $or $or$ls180.v:4021$489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4021$488_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4021$489_Y - end - attribute \src "ls180.v:4021.75-4021.506" - cell $or $or$ls180.v:4021$494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$490_Y - connect \B $and$ls180.v:4021$493_Y - connect \Y $or$ls180.v:4021$494_Y - end - attribute \src "ls180.v:4084.36-4084.104" - cell $or $or$ls180.v:4084$528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:4084$527_Y - connect \Y $or$ls180.v:4084$528_Y - end - attribute \src "ls180.v:4105.67-4105.221" - cell $or $or$ls180.v:4105$535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4105$534_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4105$535_Y - end - attribute \src "ls180.v:4113.10-4113.62" - cell $or $or$ls180.v:4113$538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4113$537_Y - connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:4113$538_Y - end - attribute \src "ls180.v:4143.67-4143.221" - cell $or $or$ls180.v:4143$544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4143$543_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4143$544_Y - end - attribute \src "ls180.v:4151.10-4151.61" - cell $or $or$ls180.v:4151$547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4151$546_Y - connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:4151$547_Y - end - attribute \src "ls180.v:4161.91-4161.180" - cell $or $or$ls180.v:4161$551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:4161$550_Y - connect \Y $or$ls180.v:4161$551_Y - end - attribute \src "ls180.v:4161.90-4161.255" - cell $or $or$ls180.v:4161$554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4161$551_Y - connect \B $and$ls180.v:4161$553_Y - connect \Y $or$ls180.v:4161$554_Y - end - attribute \src "ls180.v:4161.89-4161.330" - cell $or $or$ls180.v:4161$557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4161$554_Y - connect \B $and$ls180.v:4161$556_Y - connect \Y $or$ls180.v:4161$557_Y - end - attribute \src "ls180.v:4166.91-4166.180" - cell $or $or$ls180.v:4166$567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:4166$566_Y - connect \Y $or$ls180.v:4166$567_Y - end - attribute \src "ls180.v:4166.90-4166.255" - cell $or $or$ls180.v:4166$570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4166$567_Y - connect \B $and$ls180.v:4166$569_Y - connect \Y $or$ls180.v:4166$570_Y - end - attribute \src "ls180.v:4166.89-4166.330" - cell $or $or$ls180.v:4166$573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4166$570_Y - connect \B $and$ls180.v:4166$572_Y - connect \Y $or$ls180.v:4166$573_Y - end - attribute \src "ls180.v:4171.91-4171.180" - cell $or $or$ls180.v:4171$583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:4171$582_Y - connect \Y $or$ls180.v:4171$583_Y - end - attribute \src "ls180.v:4171.90-4171.255" - cell $or $or$ls180.v:4171$586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4171$583_Y - connect \B $and$ls180.v:4171$585_Y - connect \Y $or$ls180.v:4171$586_Y - end - attribute \src "ls180.v:4171.89-4171.330" - cell $or $or$ls180.v:4171$589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4171$586_Y - connect \B $and$ls180.v:4171$588_Y - connect \Y $or$ls180.v:4171$589_Y - end - attribute \src "ls180.v:4176.91-4176.180" - cell $or $or$ls180.v:4176$599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:4176$598_Y - connect \Y $or$ls180.v:4176$599_Y - end - attribute \src "ls180.v:4176.90-4176.255" - cell $or $or$ls180.v:4176$602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4176$599_Y - connect \B $and$ls180.v:4176$601_Y - connect \Y $or$ls180.v:4176$602_Y - end - attribute \src "ls180.v:4176.89-4176.330" - cell $or $or$ls180.v:4176$605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4176$602_Y - connect \B $and$ls180.v:4176$604_Y - connect \Y $or$ls180.v:4176$605_Y - end - attribute \src "ls180.v:4181.132-4181.221" - cell $or $or$ls180.v:4181$616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:4181$615_Y - connect \Y $or$ls180.v:4181$616_Y - end - attribute \src "ls180.v:4181.131-4181.296" - cell $or $or$ls180.v:4181$619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$616_Y - connect \B $and$ls180.v:4181$618_Y - connect \Y $or$ls180.v:4181$619_Y - end - attribute \src "ls180.v:4181.130-4181.371" - cell $or $or$ls180.v:4181$622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$619_Y - connect \B $and$ls180.v:4181$621_Y - connect \Y $or$ls180.v:4181$622_Y - end - attribute \src "ls180.v:4181.34-4181.411" - cell $or $or$ls180.v:4181$627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:4181$626_Y - connect \Y $or$ls180.v:4181$627_Y - end - attribute \src "ls180.v:4181.506-4181.595" - cell $or $or$ls180.v:4181$632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:4181$631_Y - connect \Y $or$ls180.v:4181$632_Y - end - attribute \src "ls180.v:4181.505-4181.670" - cell $or $or$ls180.v:4181$635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$632_Y - connect \B $and$ls180.v:4181$634_Y - connect \Y $or$ls180.v:4181$635_Y - end - attribute \src "ls180.v:4181.504-4181.745" - cell $or $or$ls180.v:4181$638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$635_Y - connect \B $and$ls180.v:4181$637_Y - connect \Y $or$ls180.v:4181$638_Y - end - attribute \src "ls180.v:4181.33-4181.785" - cell $or $or$ls180.v:4181$643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$627_Y - connect \B $and$ls180.v:4181$642_Y - connect \Y $or$ls180.v:4181$643_Y - end - attribute \src "ls180.v:4181.880-4181.969" - cell $or $or$ls180.v:4181$648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:4181$647_Y - connect \Y $or$ls180.v:4181$648_Y - end - attribute \src "ls180.v:4181.879-4181.1044" - cell $or $or$ls180.v:4181$651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$648_Y - connect \B $and$ls180.v:4181$650_Y - connect \Y $or$ls180.v:4181$651_Y - end - attribute \src "ls180.v:4181.878-4181.1119" - cell $or $or$ls180.v:4181$654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$651_Y - connect \B $and$ls180.v:4181$653_Y - connect \Y $or$ls180.v:4181$654_Y - end - attribute \src "ls180.v:4181.32-4181.1159" - cell $or $or$ls180.v:4181$659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$643_Y - connect \B $and$ls180.v:4181$658_Y - connect \Y $or$ls180.v:4181$659_Y - end - attribute \src "ls180.v:4181.1254-4181.1343" - cell $or $or$ls180.v:4181$664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:4181$663_Y - connect \Y $or$ls180.v:4181$664_Y - end - attribute \src "ls180.v:4181.1253-4181.1418" - cell $or $or$ls180.v:4181$667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$664_Y - connect \B $and$ls180.v:4181$666_Y - connect \Y $or$ls180.v:4181$667_Y - end - attribute \src "ls180.v:4181.1252-4181.1493" - cell $or $or$ls180.v:4181$670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$667_Y - connect \B $and$ls180.v:4181$669_Y - connect \Y $or$ls180.v:4181$670_Y - end - attribute \src "ls180.v:4181.31-4181.1533" - cell $or $or$ls180.v:4181$675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4181$659_Y - connect \B $and$ls180.v:4181$674_Y - connect \Y $or$ls180.v:4181$675_Y - end - attribute \src "ls180.v:4244.10-4244.52" - cell $or $or$ls180.v:4244$684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:4244$684_Y - end - attribute \src "ls180.v:4271.35-4271.74" - cell $or $or$ls180.v:4271$694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4271$694_Y - end - attribute \src "ls180.v:4272.34-4272.73" - cell $or $or$ls180.v:4272$698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4272$698_Y - end - attribute \src "ls180.v:4273.48-4273.130" - cell $or $or$ls180.v:4273$704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4273$701_Y - connect \B $and$ls180.v:4273$703_Y - connect \Y $or$ls180.v:4273$704_Y - end - attribute \src "ls180.v:4274.24-4274.87" - cell $or $or$ls180.v:4274$707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4274$706_Y - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4274$707_Y - end - attribute \src "ls180.v:4275.26-4275.95" - cell $or $or$ls180.v:4275$709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4275$708_Y - connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4275$709_Y - end - attribute \src "ls180.v:4305.42-4305.89" - cell $or $or$ls180.v:4305$717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4305$716_Y - connect \Y $or$ls180.v:4305$717_Y - end - attribute \src "ls180.v:4329.25-4329.174" - cell $or $or$ls180.v:4329$727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4329$725_Y - connect \B $and$ls180.v:4329$726_Y - connect \Y $or$ls180.v:4329$727_Y - end - attribute \src "ls180.v:4344.80-4344.132" - cell $or $or$ls180.v:4344$729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4344$728_Y - connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4344$729_Y - end - attribute \src "ls180.v:4355.72-4355.135" - cell $or $or$ls180.v:4355$734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_writable - connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4355$734_Y - end - attribute \src "ls180.v:4374.80-4374.132" - cell $or $or$ls180.v:4374$740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4374$739_Y - connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4374$740_Y - end - attribute \src "ls180.v:4385.72-4385.135" - cell $or $or$ls180.v:4385$745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_writable - connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4385$745_Y - end - attribute \src "ls180.v:4530.36-4530.111" - cell $or $or$ls180.v:4530$768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_clk - connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4530$768_Y - end - attribute \src "ls180.v:4530.35-4530.151" - cell $or $or$ls180.v:4530$769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4530$768_Y - connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4530$769_Y - end - attribute \src "ls180.v:4530.34-4530.192" - cell $or $or$ls180.v:4530$770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4530$769_Y - connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4530$770_Y - end - attribute \src "ls180.v:4530.33-4530.233" - cell $or $or$ls180.v:4530$771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4530$770_Y - connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4530$771_Y - end - attribute \src "ls180.v:4531.39-4531.120" - cell $or $or$ls180.v:4531$772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_cmd_oe - connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4531$772_Y - end - attribute \src "ls180.v:4531.38-4531.163" - cell $or $or$ls180.v:4531$773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4531$772_Y - connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4531$773_Y - end - attribute \src "ls180.v:4531.37-4531.207" - cell $or $or$ls180.v:4531$774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4531$773_Y - connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4531$774_Y - end - attribute \src "ls180.v:4531.36-4531.251" - cell $or $or$ls180.v:4531$775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4531$774_Y - connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4531$775_Y - end - attribute \src "ls180.v:4532.38-4532.117" - cell $or $or$ls180.v:4532$776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_cmd_o - connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4532$776_Y - end - attribute \src "ls180.v:4532.37-4532.159" - cell $or $or$ls180.v:4532$777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4532$776_Y - connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4532$777_Y - end - attribute \src "ls180.v:4532.36-4532.202" - cell $or $or$ls180.v:4532$778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4532$777_Y - connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4532$778_Y - end - attribute \src "ls180.v:4532.35-4532.245" - cell $or $or$ls180.v:4532$779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4532$778_Y - connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4532$779_Y - end - attribute \src "ls180.v:4533.40-4533.123" - cell $or $or$ls180.v:4533$780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_data_oe - connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4533$780_Y - end - attribute \src "ls180.v:4533.39-4533.167" - cell $or $or$ls180.v:4533$781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$780_Y - connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4533$781_Y - end - attribute \src "ls180.v:4533.38-4533.212" - cell $or $or$ls180.v:4533$782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$781_Y - connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4533$782_Y - end - attribute \src "ls180.v:4533.37-4533.257" - cell $or $or$ls180.v:4533$783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$782_Y - connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4533$783_Y - end - attribute \src "ls180.v:4534.39-4534.120" - cell $or $or$ls180.v:4534$784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_init_pads_out_payload_data_o - connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4534$784_Y - end - attribute \src "ls180.v:4534.38-4534.163" - cell $or $or$ls180.v:4534$785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4534$784_Y - connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4534$785_Y - end - attribute \src "ls180.v:4534.37-4534.207" - cell $or $or$ls180.v:4534$786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4534$785_Y - connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4534$786_Y - end - attribute \src "ls180.v:4534.36-4534.251" - cell $or $or$ls180.v:4534$787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4534$786_Y - connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4534$787_Y - end - attribute \src "ls180.v:4555.35-4555.80" - cell $or $or$ls180.v:4555$788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_stop - connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4555$788_Y - end - attribute \src "ls180.v:4709.91-4709.144" - cell $or $or$ls180.v:4709$802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_start - connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4709$802_Y - end - attribute \src "ls180.v:4726.53-4726.143" - cell $or $or$ls180.v:4726$805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4726$804_Y - connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4726$805_Y - end - attribute \src "ls180.v:4729.47-4729.127" - cell $or $or$ls180.v:4729$808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4729$807_Y - connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4729$808_Y - end - attribute \src "ls180.v:4853.54-4853.146" - cell $or $or$ls180.v:4853$826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4853$825_Y - connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4853$826_Y - end - attribute \src "ls180.v:4856.48-4856.130" - cell $or $or$ls180.v:4856$829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4856$828_Y - connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4856$829_Y - end - attribute \src "ls180.v:4987.55-4987.149" - cell $or $or$ls180.v:4987$841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4987$840_Y - connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4987$841_Y - end - attribute \src "ls180.v:4990.49-4990.133" - cell $or $or$ls180.v:4990$844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4990$843_Y - connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4990$844_Y - end - attribute \src "ls180.v:5619.80-5619.151" - cell $or $or$ls180.v:5619$1139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_writable - connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5619$1139_Y - end - attribute \src "ls180.v:5630.49-5630.131" - cell $or $or$ls180.v:5630$1145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5630$1144_Y - connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5630$1145_Y - end - attribute \src "ls180.v:5839.80-5839.151" - cell $or $or$ls180.v:5839$1170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_writable - connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5839$1170_Y - end - attribute \src "ls180.v:6026.41-6026.99" - cell $or $or$ls180.v:6026$1226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_err - connect \B \main_interface0_ram_bus_err - connect \Y $or$ls180.v:6026$1226_Y - end - attribute \src "ls180.v:6026.40-6026.130" - cell $or $or$ls180.v:6026$1227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1226_Y - connect \B \main_interface1_ram_bus_err - connect \Y $or$ls180.v:6026$1227_Y - end - attribute \src "ls180.v:6026.39-6026.161" - cell $or $or$ls180.v:6026$1228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1227_Y - connect \B \main_interface2_ram_bus_err - connect \Y $or$ls180.v:6026$1228_Y - end - attribute \src "ls180.v:6026.38-6026.192" - cell $or $or$ls180.v:6026$1229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1228_Y - connect \B \main_interface3_ram_bus_err - connect \Y $or$ls180.v:6026$1229_Y - end - attribute \src "ls180.v:6026.37-6026.235" - cell $or $or$ls180.v:6026$1230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1229_Y - connect \B \main_interface0_converted_interface_err - connect \Y $or$ls180.v:6026$1230_Y - end - attribute \src "ls180.v:6026.36-6026.278" - cell $or $or$ls180.v:6026$1231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1230_Y - connect \B \main_interface1_converted_interface_err - connect \Y $or$ls180.v:6026$1231_Y - end - attribute \src "ls180.v:6026.35-6026.322" - cell $or $or$ls180.v:6026$1232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1231_Y - connect \B \main_libresocsim_libresoc_interface0_err - connect \Y $or$ls180.v:6026$1232_Y - end - attribute \src "ls180.v:6026.34-6026.366" - cell $or $or$ls180.v:6026$1233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1232_Y - connect \B \main_libresocsim_libresoc_interface1_err - connect \Y $or$ls180.v:6026$1233_Y - end - attribute \src "ls180.v:6026.33-6026.410" - cell $or $or$ls180.v:6026$1234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1233_Y - connect \B \main_libresocsim_libresoc_interface2_err - connect \Y $or$ls180.v:6026$1234_Y - end - attribute \src "ls180.v:6026.32-6026.454" - cell $or $or$ls180.v:6026$1235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1234_Y - connect \B \main_libresocsim_libresoc_interface3_err - connect \Y $or$ls180.v:6026$1235_Y - end - attribute \src "ls180.v:6026.31-6026.500" - cell $or $or$ls180.v:6026$1236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1235_Y - connect \B \main_socbushandler_converted_interface_err - connect \Y $or$ls180.v:6026$1236_Y - end - attribute \src "ls180.v:6026.30-6026.547" - cell $or $or$ls180.v:6026$1237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6026$1236_Y - connect \B \builder_libresocsim_converted_interface_err - connect \Y $or$ls180.v:6026$1237_Y - end - attribute \src "ls180.v:6032.36-6032.94" - cell $or $or$ls180.v:6032$1242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \B \main_interface0_ram_bus_ack - connect \Y $or$ls180.v:6032$1242_Y - end - attribute \src "ls180.v:6032.35-6032.125" - cell $or $or$ls180.v:6032$1243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1242_Y - connect \B \main_interface1_ram_bus_ack - connect \Y $or$ls180.v:6032$1243_Y - end - attribute \src "ls180.v:6032.34-6032.156" - cell $or $or$ls180.v:6032$1244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1243_Y - connect \B \main_interface2_ram_bus_ack - connect \Y $or$ls180.v:6032$1244_Y - end - attribute \src "ls180.v:6032.33-6032.187" - cell $or $or$ls180.v:6032$1245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1244_Y - connect \B \main_interface3_ram_bus_ack - connect \Y $or$ls180.v:6032$1245_Y - end - attribute \src "ls180.v:6032.32-6032.230" - cell $or $or$ls180.v:6032$1246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1245_Y - connect \B \main_interface0_converted_interface_ack - connect \Y $or$ls180.v:6032$1246_Y - end - attribute \src "ls180.v:6032.31-6032.273" - cell $or $or$ls180.v:6032$1247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1246_Y - connect \B \main_interface1_converted_interface_ack - connect \Y $or$ls180.v:6032$1247_Y - end - attribute \src "ls180.v:6032.30-6032.317" - cell $or $or$ls180.v:6032$1248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1247_Y - connect \B \main_libresocsim_libresoc_interface0_ack - connect \Y $or$ls180.v:6032$1248_Y - end - attribute \src "ls180.v:6032.29-6032.361" - cell $or $or$ls180.v:6032$1249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1248_Y - connect \B \main_libresocsim_libresoc_interface1_ack - connect \Y $or$ls180.v:6032$1249_Y - end - attribute \src "ls180.v:6032.28-6032.405" - cell $or $or$ls180.v:6032$1250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1249_Y - connect \B \main_libresocsim_libresoc_interface2_ack - connect \Y $or$ls180.v:6032$1250_Y - end - attribute \src "ls180.v:6032.27-6032.449" - cell $or $or$ls180.v:6032$1251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1250_Y - connect \B \main_libresocsim_libresoc_interface3_ack - connect \Y $or$ls180.v:6032$1251_Y - end - attribute \src "ls180.v:6032.26-6032.495" - cell $or $or$ls180.v:6032$1252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1251_Y - connect \B \main_socbushandler_converted_interface_ack - connect \Y $or$ls180.v:6032$1252_Y - end - attribute \src "ls180.v:6032.25-6032.542" - cell $or $or$ls180.v:6032$1253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6032$1252_Y - connect \B \builder_libresocsim_converted_interface_ack - connect \Y $or$ls180.v:6032$1253_Y - end - attribute \src "ls180.v:6033.38-6033.166" - cell $or $or$ls180.v:6033$1256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $and$ls180.v:6033$1254_Y - connect \B $and$ls180.v:6033$1255_Y - connect \Y $or$ls180.v:6033$1256_Y - end - attribute \src "ls180.v:6033.37-6033.232" - cell $or $or$ls180.v:6033$1258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1256_Y - connect \B $and$ls180.v:6033$1257_Y - connect \Y $or$ls180.v:6033$1258_Y - end - attribute \src "ls180.v:6033.36-6033.298" - cell $or $or$ls180.v:6033$1260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1258_Y - connect \B $and$ls180.v:6033$1259_Y - connect \Y $or$ls180.v:6033$1260_Y - end - attribute \src "ls180.v:6033.35-6033.364" - cell $or $or$ls180.v:6033$1262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1260_Y - connect \B $and$ls180.v:6033$1261_Y - connect \Y $or$ls180.v:6033$1262_Y - end - attribute \src "ls180.v:6033.34-6033.442" - cell $or $or$ls180.v:6033$1264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1262_Y - connect \B $and$ls180.v:6033$1263_Y - connect \Y $or$ls180.v:6033$1264_Y - end - attribute \src "ls180.v:6033.33-6033.520" - cell $or $or$ls180.v:6033$1266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1264_Y - connect \B $and$ls180.v:6033$1265_Y - connect \Y $or$ls180.v:6033$1266_Y - end - attribute \src "ls180.v:6033.32-6033.599" - cell $or $or$ls180.v:6033$1268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1266_Y - connect \B $and$ls180.v:6033$1267_Y - connect \Y $or$ls180.v:6033$1268_Y - end - attribute \src "ls180.v:6033.31-6033.678" - cell $or $or$ls180.v:6033$1270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1268_Y - connect \B $and$ls180.v:6033$1269_Y - connect \Y $or$ls180.v:6033$1270_Y - end - attribute \src "ls180.v:6033.30-6033.757" - cell $or $or$ls180.v:6033$1272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1270_Y - connect \B $and$ls180.v:6033$1271_Y - connect \Y $or$ls180.v:6033$1272_Y - end - attribute \src "ls180.v:6033.29-6033.837" - cell $or $or$ls180.v:6033$1274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1272_Y - connect \B $and$ls180.v:6033$1273_Y - connect \Y $or$ls180.v:6033$1274_Y - end - attribute \src "ls180.v:6033.28-6033.919" - cell $or $or$ls180.v:6033$1276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1274_Y - connect \B $and$ls180.v:6033$1275_Y - connect \Y $or$ls180.v:6033$1276_Y - end - attribute \src "ls180.v:6033.27-6033.1002" - cell $or $or$ls180.v:6033$1278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6033$1276_Y - connect \B $and$ls180.v:6033$1277_Y - connect \Y $or$ls180.v:6033$1278_Y - end - attribute \src "ls180.v:6787.55-6787.124" - cell $or $or$ls180.v:6787$2424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \builder_interface0_bank_bus_dat_r - connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2424_Y - end - attribute \src "ls180.v:6787.54-6787.161" - cell $or $or$ls180.v:6787$2425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2424_Y - connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2425_Y - end - attribute \src "ls180.v:6787.53-6787.198" - cell $or $or$ls180.v:6787$2426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2425_Y - connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2426_Y - end - attribute \src "ls180.v:6787.52-6787.235" - cell $or $or$ls180.v:6787$2427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2426_Y - connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2427_Y - end - attribute \src "ls180.v:6787.51-6787.272" - cell $or $or$ls180.v:6787$2428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2427_Y - connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2428_Y - end - attribute \src "ls180.v:6787.50-6787.309" - cell $or $or$ls180.v:6787$2429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2428_Y - connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2429_Y - end - attribute \src "ls180.v:6787.49-6787.346" - cell $or $or$ls180.v:6787$2430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2429_Y - connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2430_Y - end - attribute \src "ls180.v:6787.48-6787.383" - cell $or $or$ls180.v:6787$2431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2430_Y - connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2431_Y - end - attribute \src "ls180.v:6787.47-6787.420" - cell $or $or$ls180.v:6787$2432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2431_Y - connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2432_Y - end - attribute \src "ls180.v:6787.46-6787.458" - cell $or $or$ls180.v:6787$2433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2432_Y - connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2433_Y - end - attribute \src "ls180.v:6787.45-6787.496" - cell $or $or$ls180.v:6787$2434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2433_Y - connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2434_Y - end - attribute \src "ls180.v:6787.44-6787.534" - cell $or $or$ls180.v:6787$2435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2434_Y - connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2435_Y - end - attribute \src "ls180.v:6787.43-6787.572" - cell $or $or$ls180.v:6787$2436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2435_Y - connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2436_Y - end - attribute \src "ls180.v:6787.42-6787.610" - cell $or $or$ls180.v:6787$2437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6787$2436_Y - connect \B \builder_interface14_bank_bus_dat_r - connect \Y $or$ls180.v:6787$2437_Y - end - attribute \src "ls180.v:7114.90-7114.179" - cell $or $or$ls180.v:7114$2462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:7114$2461_Y - connect \Y $or$ls180.v:7114$2462_Y - end - attribute \src "ls180.v:7114.89-7114.254" - cell $or $or$ls180.v:7114$2465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7114$2462_Y - connect \B $and$ls180.v:7114$2464_Y - connect \Y $or$ls180.v:7114$2465_Y - end - attribute \src "ls180.v:7114.88-7114.329" - cell $or $or$ls180.v:7114$2468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7114$2465_Y - connect \B $and$ls180.v:7114$2467_Y - connect \Y $or$ls180.v:7114$2468_Y - end - attribute \src "ls180.v:7138.90-7138.179" - cell $or $or$ls180.v:7138$2478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:7138$2477_Y - connect \Y $or$ls180.v:7138$2478_Y - end - attribute \src "ls180.v:7138.89-7138.254" - cell $or $or$ls180.v:7138$2481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7138$2478_Y - connect \B $and$ls180.v:7138$2480_Y - connect \Y $or$ls180.v:7138$2481_Y - end - attribute \src "ls180.v:7138.88-7138.329" - cell $or $or$ls180.v:7138$2484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7138$2481_Y - connect \B $and$ls180.v:7138$2483_Y - connect \Y $or$ls180.v:7138$2484_Y - end - attribute \src "ls180.v:7162.90-7162.179" - cell $or $or$ls180.v:7162$2494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:7162$2493_Y - connect \Y $or$ls180.v:7162$2494_Y - end - attribute \src "ls180.v:7162.89-7162.254" - cell $or $or$ls180.v:7162$2497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7162$2494_Y - connect \B $and$ls180.v:7162$2496_Y - connect \Y $or$ls180.v:7162$2497_Y - end - attribute \src "ls180.v:7162.88-7162.329" - cell $or $or$ls180.v:7162$2500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7162$2497_Y - connect \B $and$ls180.v:7162$2499_Y - connect \Y $or$ls180.v:7162$2500_Y - end - attribute \src "ls180.v:7186.90-7186.179" - cell $or $or$ls180.v:7186$2510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:7186$2509_Y - connect \Y $or$ls180.v:7186$2510_Y - end - attribute \src "ls180.v:7186.89-7186.254" - cell $or $or$ls180.v:7186$2513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7186$2510_Y - connect \B $and$ls180.v:7186$2512_Y - connect \Y $or$ls180.v:7186$2513_Y - end - attribute \src "ls180.v:7186.88-7186.329" - cell $or $or$ls180.v:7186$2516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7186$2513_Y - connect \B $and$ls180.v:7186$2515_Y - connect \Y $or$ls180.v:7186$2516_Y - end - attribute \src "ls180.v:7703.20-7703.71" - cell $or $or$ls180.v:7703$2574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [0] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7703$2574_Y - end - attribute \src "ls180.v:7704.20-7704.71" - cell $or $or$ls180.v:7704$2575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [1] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7704$2575_Y - end - attribute \src "ls180.v:7705.20-7705.71" - cell $or $or$ls180.v:7705$2576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [2] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7705$2576_Y - end - attribute \src "ls180.v:7706.20-7706.71" - cell $or $or$ls180.v:7706$2577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [3] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7706$2577_Y - end - attribute \src "ls180.v:7707.20-7707.71" - cell $or $or$ls180.v:7707$2578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [4] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7707$2578_Y - end - attribute \src "ls180.v:7708.20-7708.71" - cell $or $or$ls180.v:7708$2579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [5] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7708$2579_Y - end - attribute \src "ls180.v:7709.20-7709.71" - cell $or $or$ls180.v:7709$2580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [6] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7709$2580_Y - end - attribute \src "ls180.v:7710.20-7710.71" - cell $or $or$ls180.v:7710$2581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [7] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7710$2581_Y - end - attribute \src "ls180.v:7711.20-7711.71" - cell $or $or$ls180.v:7711$2582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [8] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7711$2582_Y - end - attribute \src "ls180.v:7712.20-7712.71" - cell $or $or$ls180.v:7712$2583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [9] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7712$2583_Y - end - attribute \src "ls180.v:7713.21-7713.73" - cell $or $or$ls180.v:7713$2584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [10] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7713$2584_Y - end - attribute \src "ls180.v:7714.21-7714.73" - cell $or $or$ls180.v:7714$2585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [11] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7714$2585_Y - end - attribute \src "ls180.v:7715.21-7715.73" - cell $or $or$ls180.v:7715$2586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [12] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7715$2586_Y - end - attribute \src "ls180.v:7716.21-7716.73" - cell $or $or$ls180.v:7716$2587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [13] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7716$2587_Y - end - attribute \src "ls180.v:7717.21-7717.73" - cell $or $or$ls180.v:7717$2588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [14] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7717$2588_Y - end - attribute \src "ls180.v:7718.21-7718.73" - cell $or $or$ls180.v:7718$2589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [15] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7718$2589_Y - end - attribute \src "ls180.v:7719.21-7719.73" - cell $or $or$ls180.v:7719$2590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [16] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7719$2590_Y - end - attribute \src "ls180.v:7720.21-7720.73" - cell $or $or$ls180.v:7720$2591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [17] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7720$2591_Y - end - attribute \src "ls180.v:7721.21-7721.73" - cell $or $or$ls180.v:7721$2592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [18] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7721$2592_Y - end - attribute \src "ls180.v:7722.21-7722.73" - cell $or $or$ls180.v:7722$2593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [19] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7722$2593_Y - end - attribute \src "ls180.v:7723.21-7723.73" - cell $or $or$ls180.v:7723$2594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [20] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7723$2594_Y - end - attribute \src "ls180.v:7724.21-7724.73" - cell $or $or$ls180.v:7724$2595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [21] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7724$2595_Y - end - attribute \src "ls180.v:7725.21-7725.73" - cell $or $or$ls180.v:7725$2596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [22] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7725$2596_Y - end - attribute \src "ls180.v:7726.21-7726.73" - cell $or $or$ls180.v:7726$2597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [23] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7726$2597_Y - end - attribute \src "ls180.v:7727.7-7727.68" - cell $or $or$ls180.v:7727$2598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_icp_ack - connect \B \main_converter0_skip - connect \Y $or$ls180.v:7727$2598_Y - end - attribute \src "ls180.v:7738.7-7738.68" - cell $or $or$ls180.v:7738$2599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_ics_ack - connect \B \main_converter1_skip - connect \Y $or$ls180.v:7738$2599_Y - end - attribute \src "ls180.v:7749.7-7749.50" - cell $or $or$ls180.v:7749$2600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_ack - connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:7749$2600_Y - end - attribute \src "ls180.v:7894.7-7894.107" - cell $or $or$ls180.v:7894$2648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7894$2647_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7894$2648_Y - end - attribute \src "ls180.v:7940.7-7940.107" - cell $or $or$ls180.v:7940$2664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7940$2663_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7940$2664_Y - end - attribute \src "ls180.v:7986.7-7986.107" - cell $or $or$ls180.v:7986$2680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7986$2679_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7986$2680_Y - end - attribute \src "ls180.v:8032.7-8032.107" - cell $or $or$ls180.v:8032$2696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8032$2695_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:8032$2696_Y - end - attribute \src "ls180.v:8220.40-8220.125" - cell $or $or$ls180.v:8220$2717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:8220$2716_Y - connect \Y $or$ls180.v:8220$2717_Y - end - attribute \src "ls180.v:8220.39-8220.207" - cell $or $or$ls180.v:8220$2720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8220$2717_Y - connect \B $and$ls180.v:8220$2719_Y - connect \Y $or$ls180.v:8220$2720_Y - end - attribute \src "ls180.v:8220.38-8220.289" - cell $or $or$ls180.v:8220$2723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8220$2720_Y - connect \B $and$ls180.v:8220$2722_Y - connect \Y $or$ls180.v:8220$2723_Y - end - attribute \src "ls180.v:8220.37-8220.371" - cell $or $or$ls180.v:8220$2726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8220$2723_Y - connect \B $and$ls180.v:8220$2725_Y - connect \Y $or$ls180.v:8220$2726_Y - end - attribute \src "ls180.v:8221.41-8221.126" - cell $or $or$ls180.v:8221$2729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:8221$2728_Y - connect \Y $or$ls180.v:8221$2729_Y - end - attribute \src "ls180.v:8221.40-8221.208" - cell $or $or$ls180.v:8221$2732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8221$2729_Y - connect \B $and$ls180.v:8221$2731_Y - connect \Y $or$ls180.v:8221$2732_Y - end - attribute \src "ls180.v:8221.39-8221.290" - cell $or $or$ls180.v:8221$2735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8221$2732_Y - connect \B $and$ls180.v:8221$2734_Y - connect \Y $or$ls180.v:8221$2735_Y - end - attribute \src "ls180.v:8221.38-8221.372" - cell $or $or$ls180.v:8221$2738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8221$2735_Y - connect \B $and$ls180.v:8221$2737_Y - connect \Y $or$ls180.v:8221$2738_Y - end - attribute \src "ls180.v:8225.7-8225.49" - cell $or $or$ls180.v:8225$2739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:8225$2739_Y - end - attribute \src "ls180.v:8388.21-8388.74" - cell $or $or$ls180.v:8388$2787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8388$2785_Y - connect \B $not$ls180.v:8388$2786_Y - connect \Y $or$ls180.v:8388$2787_Y - end - attribute \src "ls180.v:8423.21-8423.71" - cell $or $or$ls180.v:8423$2792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8423$2790_Y - connect \B $not$ls180.v:8423$2791_Y - connect \Y $or$ls180.v:8423$2792_Y - end - attribute \src "ls180.v:8491.32-8491.85" - cell $or $or$ls180.v:8491$2804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_start - connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8491$2804_Y - end - attribute \src "ls180.v:8497.8-8497.97" - cell $or $or$ls180.v:8497$2806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8497$2805_Y - connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8497$2806_Y - end - attribute \src "ls180.v:8514.52-8514.139" - cell $or $or$ls180.v:8514$2811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_first - connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8514$2811_Y - end - attribute \src "ls180.v:8515.51-8515.136" - cell $or $or$ls180.v:8515$2812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_last - connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8515$2812_Y - end - attribute \src "ls180.v:8549.7-8549.87" - cell $or $or$ls180.v:8549$2815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8549$2814_Y - connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8549$2815_Y - end - attribute \src "ls180.v:8572.33-8572.88" - cell $or $or$ls180.v:8572$2816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_start - connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8572$2816_Y - end - attribute \src "ls180.v:8578.8-8578.99" - cell $or $or$ls180.v:8578$2818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8578$2817_Y - connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8578$2818_Y - end - attribute \src "ls180.v:8595.53-8595.142" - cell $or $or$ls180.v:8595$2823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_first - connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8595$2823_Y - end - attribute \src "ls180.v:8596.52-8596.139" - cell $or $or$ls180.v:8596$2824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_last - connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8596$2824_Y - end - attribute \src "ls180.v:8630.7-8630.89" - cell $or $or$ls180.v:8630$2827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8630$2826_Y - connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8630$2827_Y - end - attribute \src "ls180.v:8651.34-8651.91" - cell $or $or$ls180.v:8651$2828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_start - connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8651$2828_Y - end - attribute \src "ls180.v:8657.8-8657.101" - cell $or $or$ls180.v:8657$2830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8657$2829_Y - connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8657$2830_Y - end - attribute \src "ls180.v:8674.54-8674.145" - cell $or $or$ls180.v:8674$2835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_first - connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8674$2835_Y - end - attribute \src "ls180.v:8675.53-8675.142" - cell $or $or$ls180.v:8675$2836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_last - connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8675$2836_Y - end - attribute \src "ls180.v:8691.7-8691.91" - cell $or $or$ls180.v:8691$2839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8691$2838_Y - connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8691$2839_Y - end - attribute \src "ls180.v:8880.8-8880.89" - cell $or $or$ls180.v:8880$2863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8880$2862_Y - connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8880$2863_Y - end - attribute \src "ls180.v:8897.48-8897.127" - cell $or $or$ls180.v:8897$2868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_first - connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8897$2868_Y - end - attribute \src "ls180.v:8898.47-8898.124" - cell $or $or$ls180.v:8898$2869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_last - connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8898$2869_Y - end - attribute \src "ls180.v:3355.46-3355.94" - cell $sshl $sshl$ls180.v:3355$231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine0_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3355$231_Y - end - attribute \src "ls180.v:3512.46-3512.94" - cell $sshl $sshl$ls180.v:3512$261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine1_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3512$261_Y - end - attribute \src "ls180.v:3669.46-3669.94" - cell $sshl $sshl$ls180.v:3669$291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine2_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3669$291_Y - end - attribute \src "ls180.v:3826.46-3826.94" - cell $sshl $sshl$ls180.v:3826$321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine3_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3826$321_Y - end - attribute \src "ls180.v:3386.63-3386.122" - cell $sub $sub$ls180.v:3386$244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3386$244_Y - end - attribute \src "ls180.v:3543.63-3543.122" - cell $sub $sub$ls180.v:3543$274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3543$274_Y - end - attribute \src "ls180.v:3700.63-3700.122" - cell $sub $sub$ls180.v:3700$304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3700$304_Y - end - attribute \src "ls180.v:3857.63-3857.122" - cell $sub $sub$ls180.v:3857$334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3857$334_Y - end - attribute \src "ls180.v:4263.38-4263.75" - cell $sub $sub$ls180.v:4263$688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 30 - parameter \B_SIGNED 0 - parameter \B_WIDTH 31 - parameter \Y_WIDTH 31 - connect \A \main_litedram_wb_adr - connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4263$688_Y - end - attribute \src "ls180.v:4349.36-4349.68" - cell $sub $sub$ls180.v:4349$733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:4349$733_Y - end - attribute \src "ls180.v:4379.36-4379.68" - cell $sub $sub$ls180.v:4379$744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:4379$744_Y - end - attribute \src "ls180.v:4415.70-4415.110" - cell $sub $sub$ls180.v:4415$752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster8_clk_divider [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:4415$752_Y - end - attribute \src "ls180.v:4416.70-4416.104" - cell $sub $sub$ls180.v:4416$754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster8_clk_divider - connect \B 1'1 - connect \Y $sub$ls180.v:4416$754_Y - end - attribute \src "ls180.v:4443.37-4443.66" - cell $sub $sub$ls180.v:4443$758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_spimaster1_length - connect \B 1'1 - connect \Y $sub$ls180.v:4443$758_Y - end - attribute \src "ls180.v:4473.67-4473.107" - cell $sub $sub$ls180.v:4473$760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider0 [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:4473$760_Y - end - attribute \src "ls180.v:4474.67-4474.101" - cell $sub $sub$ls180.v:4474$762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider0 - connect \B 1'1 - connect \Y $sub$ls180.v:4474$762_Y - end - attribute \src "ls180.v:4502.35-4502.64" - cell $sub $sub$ls180.v:4502$766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_spisdcard_length0 - connect \B 1'1 - connect \Y $sub$ls180.v:4502$766_Y - end - attribute \src "ls180.v:4756.60-4756.90" - cell $sub $sub$ls180.v:4756$810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4756$810_Y - end - attribute \src "ls180.v:4767.62-4767.104" - cell $sub $sub$ls180.v:4767$812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_sink_payload_length - connect \B 1'1 - connect \Y $sub$ls180.v:4767$812_Y - end - attribute \src "ls180.v:4784.60-4784.90" - cell $sub $sub$ls180.v:4784$816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4784$816_Y - end - attribute \src "ls180.v:5013.62-5013.93" - cell $sub $sub$ls180.v:5013$846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:5013$846_Y - end - attribute \src "ls180.v:5018.62-5018.93" - cell $sub $sub$ls180.v:5018$847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:5018$847_Y - end - attribute \src "ls180.v:5029.64-5029.122" - cell $sub $sub$ls180.v:5029$850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A $add$ls180.v:5029$849_Y - connect \B 1'1 - connect \Y $sub$ls180.v:5029$850_Y - end - attribute \src "ls180.v:5050.62-5050.93" - cell $sub $sub$ls180.v:5050$853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:5050$853_Y - end - attribute \src "ls180.v:5512.37-5512.75" - cell $sub $sub$ls180.v:5512$1126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5512$1126_Y - end - attribute \src "ls180.v:5527.62-5527.100" - cell $sub $sub$ls180.v:5527$1129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5527$1129_Y - end - attribute \src "ls180.v:5538.39-5538.77" - cell $sub $sub$ls180.v:5538$1134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5538$1134_Y - end - attribute \src "ls180.v:5613.40-5613.76" - cell $sub $sub$ls180.v:5613$1138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5613$1138_Y - end - attribute \src "ls180.v:5662.56-5662.104" - cell $sub $sub$ls180.v:5662$1152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_length - connect \B 1'1 - connect \Y $sub$ls180.v:5662$1152_Y - end - attribute \src "ls180.v:5752.71-5752.105" - cell $sub $sub$ls180.v:5752$1158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_length - connect \B 1'1 - connect \Y $sub$ls180.v:5752$1158_Y - end - attribute \src "ls180.v:5833.40-5833.76" - cell $sub $sub$ls180.v:5833$1169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5833$1169_Y - end - attribute \src "ls180.v:7773.31-7773.60" - cell $sub $sub$ls180.v:7773$2607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_value - connect \B 1'1 - connect \Y $sub$ls180.v:7773$2607_Y - end - attribute \src "ls180.v:7810.31-7810.61" - cell $sub $sub$ls180.v:7810$2624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdram_timer_count1 - connect \B 1'1 - connect \Y $sub$ls180.v:7810$2624_Y - end - attribute \src "ls180.v:7816.34-7816.67" - cell $sub $sub$ls180.v:7816$2625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7816$2625_Y - end - attribute \src "ls180.v:7827.36-7827.69" - cell $sub $sub$ls180.v:7827$2628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7827$2628_Y - end - attribute \src "ls180.v:7891.59-7891.116" - cell $sub $sub$ls180.v:7891$2646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7891$2646_Y - end - attribute \src "ls180.v:7910.46-7910.90" - cell $sub $sub$ls180.v:7910$2650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7910$2650_Y - end - attribute \src "ls180.v:7937.59-7937.116" - cell $sub $sub$ls180.v:7937$2662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7937$2662_Y - end - attribute \src "ls180.v:7956.46-7956.90" - cell $sub $sub$ls180.v:7956$2666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7956$2666_Y - end - attribute \src "ls180.v:7983.59-7983.116" - cell $sub $sub$ls180.v:7983$2678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7983$2678_Y - end - attribute \src "ls180.v:8002.46-8002.90" - cell $sub $sub$ls180.v:8002$2682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:8002$2682_Y - end - attribute \src "ls180.v:8029.59-8029.116" - cell $sub $sub$ls180.v:8029$2694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:8029$2694_Y - end - attribute \src "ls180.v:8048.46-8048.90" - cell $sub $sub$ls180.v:8048$2698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:8048$2698_Y - end - attribute \src "ls180.v:8059.25-8059.48" - cell $sub $sub$ls180.v:8059$2702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdram_time0 - connect \B 1'1 - connect \Y $sub$ls180.v:8059$2702_Y - end - attribute \src "ls180.v:8066.25-8066.48" - cell $sub $sub$ls180.v:8066$2705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_time1 - connect \B 1'1 - connect \Y $sub$ls180.v:8066$2705_Y - end - attribute \src "ls180.v:8198.33-8198.64" - cell $sub $sub$ls180.v:8198$2710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:8198$2710_Y - end - attribute \src "ls180.v:8213.33-8213.64" - cell $sub $sub$ls180.v:8213$2713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:8213$2713_Y - end - attribute \src "ls180.v:8340.33-8340.64" - cell $sub $sub$ls180.v:8340$2772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:8340$2772_Y - end - attribute \src "ls180.v:8362.33-8362.64" - cell $sub $sub$ls180.v:8362$2783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:8362$2783_Y - end - attribute \src "ls180.v:8397.34-8397.66" - cell $sub $sub$ls180.v:8397$2788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spimaster34_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8397$2788_Y - end - attribute \src "ls180.v:8432.32-8432.62" - cell $sub $sub$ls180.v:8432$2793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spisdcard_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8432$2793_Y - end - attribute \src "ls180.v:8456.30-8456.53" - cell $sub $sub$ls180.v:8456$2796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm0_period - connect \B 1'1 - connect \Y $sub$ls180.v:8456$2796_Y - end - attribute \src "ls180.v:8470.30-8470.53" - cell $sub $sub$ls180.v:8470$2800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm1_period - connect \B 1'1 - connect \Y $sub$ls180.v:8470$2800_Y - end - attribute \src "ls180.v:8873.36-8873.70" - cell $sub $sub$ls180.v:8873$2861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8873$2861_Y - end - attribute \src "ls180.v:8971.36-8971.70" - cell $sub $sub$ls180.v:8971$2883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8971$2883_Y - end - attribute \src "ls180.v:9084.22-9084.42" - cell $sub $sub$ls180.v:9084$2890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 20 - connect \A \builder_count - connect \B 1'1 - connect \Y $sub$ls180.v:9084$2890_Y - end - attribute \src "ls180.v:5110.353-5110.425" - cell $xor $xor$ls180.v:5110$860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [39] - connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:5110$860_Y - end - attribute \src "ls180.v:5110.200-5110.272" - cell $xor $xor$ls180.v:5110$861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [39] - connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:5110$861_Y - end - attribute \src "ls180.v:5110.160-5110.273" - cell $xor $xor$ls180.v:5110$862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:5110$861_Y - connect \Y $xor$ls180.v:5110$862_Y - end - attribute \src "ls180.v:5111.353-5111.425" - cell $xor $xor$ls180.v:5111$863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [38] - connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:5111$863_Y - end - attribute \src "ls180.v:5111.200-5111.272" - cell $xor $xor$ls180.v:5111$864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [38] - connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:5111$864_Y - end - attribute \src "ls180.v:5111.160-5111.273" - cell $xor $xor$ls180.v:5111$865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:5111$864_Y - connect \Y $xor$ls180.v:5111$865_Y - end - attribute \src "ls180.v:5112.353-5112.425" - cell $xor $xor$ls180.v:5112$866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [37] - connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:5112$866_Y - end - attribute \src "ls180.v:5112.200-5112.272" - cell $xor $xor$ls180.v:5112$867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [37] - connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:5112$867_Y - end - attribute \src "ls180.v:5112.160-5112.273" - cell $xor $xor$ls180.v:5112$868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:5112$867_Y - connect \Y $xor$ls180.v:5112$868_Y - end - attribute \src "ls180.v:5113.353-5113.425" - cell $xor $xor$ls180.v:5113$869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [36] - connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5113$869_Y - end - attribute \src "ls180.v:5113.200-5113.272" - cell $xor $xor$ls180.v:5113$870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [36] - connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5113$870_Y - end - attribute \src "ls180.v:5113.160-5113.273" - cell $xor $xor$ls180.v:5113$871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:5113$870_Y - connect \Y $xor$ls180.v:5113$871_Y - end - attribute \src "ls180.v:5114.353-5114.425" - cell $xor $xor$ls180.v:5114$872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [35] - connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5114$872_Y - end - attribute \src "ls180.v:5114.200-5114.272" - cell $xor $xor$ls180.v:5114$873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [35] - connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5114$873_Y - end - attribute \src "ls180.v:5114.160-5114.273" - cell $xor $xor$ls180.v:5114$874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:5114$873_Y - connect \Y $xor$ls180.v:5114$874_Y - end - attribute \src "ls180.v:5115.353-5115.425" - cell $xor $xor$ls180.v:5115$875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [34] - connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5115$875_Y - end - attribute \src "ls180.v:5115.200-5115.272" - cell $xor $xor$ls180.v:5115$876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [34] - connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5115$876_Y - end - attribute \src "ls180.v:5115.160-5115.273" - cell $xor $xor$ls180.v:5115$877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:5115$876_Y - connect \Y $xor$ls180.v:5115$877_Y - end - attribute \src "ls180.v:5116.353-5116.425" - cell $xor $xor$ls180.v:5116$878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [33] - connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5116$878_Y - end - attribute \src "ls180.v:5116.200-5116.272" - cell $xor $xor$ls180.v:5116$879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [33] - connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5116$879_Y - end - attribute \src "ls180.v:5116.160-5116.273" - cell $xor $xor$ls180.v:5116$880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:5116$879_Y - connect \Y $xor$ls180.v:5116$880_Y - end - attribute \src "ls180.v:5117.353-5117.425" - cell $xor $xor$ls180.v:5117$881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [32] - connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5117$881_Y - end - attribute \src "ls180.v:5117.200-5117.272" - cell $xor $xor$ls180.v:5117$882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [32] - connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5117$882_Y - end - attribute \src "ls180.v:5117.160-5117.273" - cell $xor $xor$ls180.v:5117$883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:5117$882_Y - connect \Y $xor$ls180.v:5117$883_Y - end - attribute \src "ls180.v:5118.353-5118.425" - cell $xor $xor$ls180.v:5118$884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [31] - connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5118$884_Y - end - attribute \src "ls180.v:5118.200-5118.272" - cell $xor $xor$ls180.v:5118$885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [31] - connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5118$885_Y - end - attribute \src "ls180.v:5118.160-5118.273" - cell $xor $xor$ls180.v:5118$886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:5118$885_Y - connect \Y $xor$ls180.v:5118$886_Y - end - attribute \src "ls180.v:5119.354-5119.426" - cell $xor $xor$ls180.v:5119$887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [30] - connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5119$887_Y - end - attribute \src "ls180.v:5119.201-5119.273" - cell $xor $xor$ls180.v:5119$888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [30] - connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5119$888_Y - end - attribute \src "ls180.v:5119.161-5119.274" - cell $xor $xor$ls180.v:5119$889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:5119$888_Y - connect \Y $xor$ls180.v:5119$889_Y - end - attribute \src "ls180.v:5120.361-5120.434" - cell $xor $xor$ls180.v:5120$890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [29] - connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5120$890_Y - end - attribute \src "ls180.v:5120.205-5120.278" - cell $xor $xor$ls180.v:5120$891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [29] - connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5120$891_Y - end - attribute \src "ls180.v:5120.164-5120.279" - cell $xor $xor$ls180.v:5120$892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:5120$891_Y - connect \Y $xor$ls180.v:5120$892_Y - end - attribute \src "ls180.v:5121.361-5121.434" - cell $xor $xor$ls180.v:5121$893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [28] - connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5121$893_Y - end - attribute \src "ls180.v:5121.205-5121.278" - cell $xor $xor$ls180.v:5121$894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [28] - connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5121$894_Y - end - attribute \src "ls180.v:5121.164-5121.279" - cell $xor $xor$ls180.v:5121$895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:5121$894_Y - connect \Y $xor$ls180.v:5121$895_Y - end - attribute \src "ls180.v:5122.361-5122.434" - cell $xor $xor$ls180.v:5122$896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [27] - connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5122$896_Y - end - attribute \src "ls180.v:5122.205-5122.278" - cell $xor $xor$ls180.v:5122$897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [27] - connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5122$897_Y - end - attribute \src "ls180.v:5122.164-5122.279" - cell $xor $xor$ls180.v:5122$898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:5122$897_Y - connect \Y $xor$ls180.v:5122$898_Y - end - attribute \src "ls180.v:5123.361-5123.434" - cell $xor $xor$ls180.v:5123$899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [26] - connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5123$899_Y - end - attribute \src "ls180.v:5123.205-5123.278" - cell $xor $xor$ls180.v:5123$900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [26] - connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5123$900_Y - end - attribute \src "ls180.v:5123.164-5123.279" - cell $xor $xor$ls180.v:5123$901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:5123$900_Y - connect \Y $xor$ls180.v:5123$901_Y - end - attribute \src "ls180.v:5124.361-5124.434" - cell $xor $xor$ls180.v:5124$902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [25] - connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5124$902_Y - end - attribute \src "ls180.v:5124.205-5124.278" - cell $xor $xor$ls180.v:5124$903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [25] - connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5124$903_Y - end - attribute \src "ls180.v:5124.164-5124.279" - cell $xor $xor$ls180.v:5124$904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:5124$903_Y - connect \Y $xor$ls180.v:5124$904_Y - end - attribute \src "ls180.v:5125.361-5125.434" - cell $xor $xor$ls180.v:5125$905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [24] - connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5125$905_Y - end - attribute \src "ls180.v:5125.205-5125.278" - cell $xor $xor$ls180.v:5125$906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [24] - connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5125$906_Y - end - attribute \src "ls180.v:5125.164-5125.279" - cell $xor $xor$ls180.v:5125$907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:5125$906_Y - connect \Y $xor$ls180.v:5125$907_Y - end - attribute \src "ls180.v:5126.361-5126.434" - cell $xor $xor$ls180.v:5126$908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [23] - connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5126$908_Y - end - attribute \src "ls180.v:5126.205-5126.278" - cell $xor $xor$ls180.v:5126$909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [23] - connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5126$909_Y - end - attribute \src "ls180.v:5126.164-5126.279" - cell $xor $xor$ls180.v:5126$910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:5126$909_Y - connect \Y $xor$ls180.v:5126$910_Y - end - attribute \src "ls180.v:5127.361-5127.434" - cell $xor $xor$ls180.v:5127$911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [22] - connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5127$911_Y - end - attribute \src "ls180.v:5127.205-5127.278" - cell $xor $xor$ls180.v:5127$912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [22] - connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5127$912_Y - end - attribute \src "ls180.v:5127.164-5127.279" - cell $xor $xor$ls180.v:5127$913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:5127$912_Y - connect \Y $xor$ls180.v:5127$913_Y - end - attribute \src "ls180.v:5128.361-5128.434" - cell $xor $xor$ls180.v:5128$914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [21] - connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5128$914_Y - end - attribute \src "ls180.v:5128.205-5128.278" - cell $xor $xor$ls180.v:5128$915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [21] - connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5128$915_Y - end - attribute \src "ls180.v:5128.164-5128.279" - cell $xor $xor$ls180.v:5128$916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:5128$915_Y - connect \Y $xor$ls180.v:5128$916_Y - end - attribute \src "ls180.v:5129.361-5129.434" - cell $xor $xor$ls180.v:5129$917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [20] - connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5129$917_Y - end - attribute \src "ls180.v:5129.205-5129.278" - cell $xor $xor$ls180.v:5129$918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [20] - connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5129$918_Y - end - attribute \src "ls180.v:5129.164-5129.279" - cell $xor $xor$ls180.v:5129$919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:5129$918_Y - connect \Y $xor$ls180.v:5129$919_Y - end - attribute \src "ls180.v:5130.361-5130.434" - cell $xor $xor$ls180.v:5130$920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [19] - connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5130$920_Y - end - attribute \src "ls180.v:5130.205-5130.278" - cell $xor $xor$ls180.v:5130$921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [19] - connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5130$921_Y - end - attribute \src "ls180.v:5130.164-5130.279" - cell $xor $xor$ls180.v:5130$922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:5130$921_Y - connect \Y $xor$ls180.v:5130$922_Y - end - attribute \src "ls180.v:5131.361-5131.434" - cell $xor $xor$ls180.v:5131$923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [18] - connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5131$923_Y - end - attribute \src "ls180.v:5131.205-5131.278" - cell $xor $xor$ls180.v:5131$924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [18] - connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5131$924_Y - end - attribute \src "ls180.v:5131.164-5131.279" - cell $xor $xor$ls180.v:5131$925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:5131$924_Y - connect \Y $xor$ls180.v:5131$925_Y - end - attribute \src "ls180.v:5132.361-5132.434" - cell $xor $xor$ls180.v:5132$926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [17] - connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5132$926_Y - end - attribute \src "ls180.v:5132.205-5132.278" - cell $xor $xor$ls180.v:5132$927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [17] - connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5132$927_Y - end - attribute \src "ls180.v:5132.164-5132.279" - cell $xor $xor$ls180.v:5132$928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:5132$927_Y - connect \Y $xor$ls180.v:5132$928_Y - end - attribute \src "ls180.v:5133.361-5133.434" - cell $xor $xor$ls180.v:5133$929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [16] - connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5133$929_Y - end - attribute \src "ls180.v:5133.205-5133.278" - cell $xor $xor$ls180.v:5133$930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [16] - connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5133$930_Y - end - attribute \src "ls180.v:5133.164-5133.279" - cell $xor $xor$ls180.v:5133$931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:5133$930_Y - connect \Y $xor$ls180.v:5133$931_Y - end - attribute \src "ls180.v:5134.361-5134.434" - cell $xor $xor$ls180.v:5134$932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [15] - connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5134$932_Y - end - attribute \src "ls180.v:5134.205-5134.278" - cell $xor $xor$ls180.v:5134$933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [15] - connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5134$933_Y - end - attribute \src "ls180.v:5134.164-5134.279" - cell $xor $xor$ls180.v:5134$934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:5134$933_Y - connect \Y $xor$ls180.v:5134$934_Y - end - attribute \src "ls180.v:5135.361-5135.434" - cell $xor $xor$ls180.v:5135$935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [14] - connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5135$935_Y - end - attribute \src "ls180.v:5135.205-5135.278" - cell $xor $xor$ls180.v:5135$936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [14] - connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5135$936_Y - end - attribute \src "ls180.v:5135.164-5135.279" - cell $xor $xor$ls180.v:5135$937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:5135$936_Y - connect \Y $xor$ls180.v:5135$937_Y - end - attribute \src "ls180.v:5136.361-5136.434" - cell $xor $xor$ls180.v:5136$938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [13] - connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5136$938_Y - end - attribute \src "ls180.v:5136.205-5136.278" - cell $xor $xor$ls180.v:5136$939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [13] - connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5136$939_Y - end - attribute \src "ls180.v:5136.164-5136.279" - cell $xor $xor$ls180.v:5136$940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:5136$939_Y - connect \Y $xor$ls180.v:5136$940_Y - end - attribute \src "ls180.v:5137.361-5137.434" - cell $xor $xor$ls180.v:5137$941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [12] - connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5137$941_Y - end - attribute \src "ls180.v:5137.205-5137.278" - cell $xor $xor$ls180.v:5137$942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [12] - connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5137$942_Y - end - attribute \src "ls180.v:5137.164-5137.279" - cell $xor $xor$ls180.v:5137$943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:5137$942_Y - connect \Y $xor$ls180.v:5137$943_Y - end - attribute \src "ls180.v:5138.361-5138.434" - cell $xor $xor$ls180.v:5138$944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [11] - connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5138$944_Y - end - attribute \src "ls180.v:5138.205-5138.278" - cell $xor $xor$ls180.v:5138$945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [11] - connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5138$945_Y - end - attribute \src "ls180.v:5138.164-5138.279" - cell $xor $xor$ls180.v:5138$946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:5138$945_Y - connect \Y $xor$ls180.v:5138$946_Y - end - attribute \src "ls180.v:5139.361-5139.434" - cell $xor $xor$ls180.v:5139$947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [10] - connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5139$947_Y - end - attribute \src "ls180.v:5139.205-5139.278" - cell $xor $xor$ls180.v:5139$948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [10] - connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5139$948_Y - end - attribute \src "ls180.v:5139.164-5139.279" - cell $xor $xor$ls180.v:5139$949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:5139$948_Y - connect \Y $xor$ls180.v:5139$949_Y - end - attribute \src "ls180.v:5140.360-5140.432" - cell $xor $xor$ls180.v:5140$950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [9] - connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5140$950_Y - end - attribute \src "ls180.v:5140.205-5140.277" - cell $xor $xor$ls180.v:5140$951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [9] - connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5140$951_Y - end - attribute \src "ls180.v:5140.164-5140.278" - cell $xor $xor$ls180.v:5140$952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:5140$951_Y - connect \Y $xor$ls180.v:5140$952_Y - end - attribute \src "ls180.v:5141.360-5141.432" - cell $xor $xor$ls180.v:5141$953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [8] - connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5141$953_Y - end - attribute \src "ls180.v:5141.205-5141.277" - cell $xor $xor$ls180.v:5141$954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [8] - connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5141$954_Y - end - attribute \src "ls180.v:5141.164-5141.278" - cell $xor $xor$ls180.v:5141$955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:5141$954_Y - connect \Y $xor$ls180.v:5141$955_Y - end - attribute \src "ls180.v:5142.360-5142.432" - cell $xor $xor$ls180.v:5142$956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [7] - connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5142$956_Y - end - attribute \src "ls180.v:5142.205-5142.277" - cell $xor $xor$ls180.v:5142$957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [7] - connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5142$957_Y - end - attribute \src "ls180.v:5142.164-5142.278" - cell $xor $xor$ls180.v:5142$958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:5142$957_Y - connect \Y $xor$ls180.v:5142$958_Y - end - attribute \src "ls180.v:5143.360-5143.432" - cell $xor $xor$ls180.v:5143$959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [6] - connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5143$959_Y - end - attribute \src "ls180.v:5143.205-5143.277" - cell $xor $xor$ls180.v:5143$960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [6] - connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5143$960_Y - end - attribute \src "ls180.v:5143.164-5143.278" - cell $xor $xor$ls180.v:5143$961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:5143$960_Y - connect \Y $xor$ls180.v:5143$961_Y - end - attribute \src "ls180.v:5144.360-5144.432" - cell $xor $xor$ls180.v:5144$962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [5] - connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5144$962_Y - end - attribute \src "ls180.v:5144.205-5144.277" - cell $xor $xor$ls180.v:5144$963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [5] - connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5144$963_Y - end - attribute \src "ls180.v:5144.164-5144.278" - cell $xor $xor$ls180.v:5144$964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:5144$963_Y - connect \Y $xor$ls180.v:5144$964_Y - end - attribute \src "ls180.v:5145.360-5145.432" - cell $xor $xor$ls180.v:5145$965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [4] - connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5145$965_Y - end - attribute \src "ls180.v:5145.205-5145.277" - cell $xor $xor$ls180.v:5145$966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [4] - connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5145$966_Y - end - attribute \src "ls180.v:5145.164-5145.278" - cell $xor $xor$ls180.v:5145$967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:5145$966_Y - connect \Y $xor$ls180.v:5145$967_Y - end - attribute \src "ls180.v:5146.360-5146.432" - cell $xor $xor$ls180.v:5146$968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [3] - connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5146$968_Y - end - attribute \src "ls180.v:5146.205-5146.277" - cell $xor $xor$ls180.v:5146$969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [3] - connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5146$969_Y - end - attribute \src "ls180.v:5146.164-5146.278" - cell $xor $xor$ls180.v:5146$970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:5146$969_Y - connect \Y $xor$ls180.v:5146$970_Y - end - attribute \src "ls180.v:5147.360-5147.432" - cell $xor $xor$ls180.v:5147$971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [2] - connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5147$971_Y - end - attribute \src "ls180.v:5147.205-5147.277" - cell $xor $xor$ls180.v:5147$972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [2] - connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5147$972_Y - end - attribute \src "ls180.v:5147.164-5147.278" - cell $xor $xor$ls180.v:5147$973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:5147$972_Y - connect \Y $xor$ls180.v:5147$973_Y - end - attribute \src "ls180.v:5148.360-5148.432" - cell $xor $xor$ls180.v:5148$974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [1] - connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5148$974_Y - end - attribute \src "ls180.v:5148.205-5148.277" - cell $xor $xor$ls180.v:5148$975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [1] - connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5148$975_Y - end - attribute \src "ls180.v:5148.164-5148.278" - cell $xor $xor$ls180.v:5148$976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:5148$975_Y - connect \Y $xor$ls180.v:5148$976_Y - end - attribute \src "ls180.v:5149.360-5149.432" - cell $xor $xor$ls180.v:5149$977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [0] - connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5149$977_Y - end - attribute \src "ls180.v:5149.205-5149.277" - cell $xor $xor$ls180.v:5149$978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [0] - connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5149$978_Y - end - attribute \src "ls180.v:5149.164-5149.278" - cell $xor $xor$ls180.v:5149$979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:5149$978_Y - connect \Y $xor$ls180.v:5149$979_Y - end - attribute \src "ls180.v:5170.899-5170.983" - cell $xor $xor$ls180.v:5170$993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5170$993_Y - end - attribute \src "ls180.v:5170.634-5170.718" - cell $xor $xor$ls180.v:5170$994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5170$994_Y - end - attribute \src "ls180.v:5170.588-5170.719" - cell $xor $xor$ls180.v:5170$995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5170$994_Y - connect \Y $xor$ls180.v:5170$995_Y - end - attribute \src "ls180.v:5170.234-5170.318" - cell $xor $xor$ls180.v:5170$996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5170$996_Y - end - attribute \src "ls180.v:5170.187-5170.319" - cell $xor $xor$ls180.v:5170$997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5170$996_Y - connect \Y $xor$ls180.v:5170$997_Y - end - attribute \src "ls180.v:5171.588-5171.719" - cell $xor $xor$ls180.v:5171$1000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5171$999_Y - connect \Y $xor$ls180.v:5171$1000_Y - end - attribute \src "ls180.v:5171.234-5171.318" - cell $xor $xor$ls180.v:5171$1001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5171$1001_Y - end - attribute \src "ls180.v:5171.187-5171.319" - cell $xor $xor$ls180.v:5171$1002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5171$1001_Y - connect \Y $xor$ls180.v:5171$1002_Y - end - attribute \src "ls180.v:5171.899-5171.983" - cell $xor $xor$ls180.v:5171$998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5171$998_Y - end - attribute \src "ls180.v:5171.634-5171.718" - cell $xor $xor$ls180.v:5171$999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5171$999_Y - end - attribute \src "ls180.v:5180.899-5180.983" - cell $xor $xor$ls180.v:5180$1004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5180$1004_Y - end - attribute \src "ls180.v:5180.634-5180.718" - cell $xor $xor$ls180.v:5180$1005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5180$1005_Y - end - attribute \src "ls180.v:5180.588-5180.719" - cell $xor $xor$ls180.v:5180$1006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5180$1005_Y - connect \Y $xor$ls180.v:5180$1006_Y - end - attribute \src "ls180.v:5180.234-5180.318" - cell $xor $xor$ls180.v:5180$1007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5180$1007_Y - end - attribute \src "ls180.v:5180.187-5180.319" - cell $xor $xor$ls180.v:5180$1008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5180$1007_Y - connect \Y $xor$ls180.v:5180$1008_Y - end - attribute \src "ls180.v:5181.899-5181.983" - cell $xor $xor$ls180.v:5181$1009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5181$1009_Y - end - attribute \src "ls180.v:5181.634-5181.718" - cell $xor $xor$ls180.v:5181$1010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5181$1010_Y - end - attribute \src "ls180.v:5181.588-5181.719" - cell $xor $xor$ls180.v:5181$1011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5181$1010_Y - connect \Y $xor$ls180.v:5181$1011_Y - end - attribute \src "ls180.v:5181.234-5181.318" - cell $xor $xor$ls180.v:5181$1012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5181$1012_Y - end - attribute \src "ls180.v:5181.187-5181.319" - cell $xor $xor$ls180.v:5181$1013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5181$1012_Y - connect \Y $xor$ls180.v:5181$1013_Y - end - attribute \src "ls180.v:5190.899-5190.983" - cell $xor $xor$ls180.v:5190$1015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5190$1015_Y - end - attribute \src "ls180.v:5190.634-5190.718" - cell $xor $xor$ls180.v:5190$1016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5190$1016_Y - end - attribute \src "ls180.v:5190.588-5190.719" - cell $xor $xor$ls180.v:5190$1017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5190$1016_Y - connect \Y $xor$ls180.v:5190$1017_Y - end - attribute \src "ls180.v:5190.234-5190.318" - cell $xor $xor$ls180.v:5190$1018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5190$1018_Y - end - attribute \src "ls180.v:5190.187-5190.319" - cell $xor $xor$ls180.v:5190$1019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5190$1018_Y - connect \Y $xor$ls180.v:5190$1019_Y - end - attribute \src "ls180.v:5191.899-5191.983" - cell $xor $xor$ls180.v:5191$1020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5191$1020_Y - end - attribute \src "ls180.v:5191.634-5191.718" - cell $xor $xor$ls180.v:5191$1021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5191$1021_Y - end - attribute \src "ls180.v:5191.588-5191.719" - cell $xor $xor$ls180.v:5191$1022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5191$1021_Y - connect \Y $xor$ls180.v:5191$1022_Y - end - attribute \src "ls180.v:5191.234-5191.318" - cell $xor $xor$ls180.v:5191$1023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5191$1023_Y - end - attribute \src "ls180.v:5191.187-5191.319" - cell $xor $xor$ls180.v:5191$1024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5191$1023_Y - connect \Y $xor$ls180.v:5191$1024_Y - end - attribute \src "ls180.v:5200.899-5200.983" - cell $xor $xor$ls180.v:5200$1026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5200$1026_Y - end - attribute \src "ls180.v:5200.634-5200.718" - cell $xor $xor$ls180.v:5200$1027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5200$1027_Y - end - attribute \src "ls180.v:5200.588-5200.719" - cell $xor $xor$ls180.v:5200$1028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5200$1027_Y - connect \Y $xor$ls180.v:5200$1028_Y - end - attribute \src "ls180.v:5200.234-5200.318" - cell $xor $xor$ls180.v:5200$1029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5200$1029_Y - end - attribute \src "ls180.v:5200.187-5200.319" - cell $xor $xor$ls180.v:5200$1030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5200$1029_Y - connect \Y $xor$ls180.v:5200$1030_Y - end - attribute \src "ls180.v:5201.899-5201.983" - cell $xor $xor$ls180.v:5201$1031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5201$1031_Y - end - attribute \src "ls180.v:5201.634-5201.718" - cell $xor $xor$ls180.v:5201$1032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5201$1032_Y - end - attribute \src "ls180.v:5201.588-5201.719" - cell $xor $xor$ls180.v:5201$1033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5201$1032_Y - connect \Y $xor$ls180.v:5201$1033_Y - end - attribute \src "ls180.v:5201.234-5201.318" - cell $xor $xor$ls180.v:5201$1034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5201$1034_Y - end - attribute \src "ls180.v:5201.187-5201.319" - cell $xor $xor$ls180.v:5201$1035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5201$1034_Y - connect \Y $xor$ls180.v:5201$1035_Y - end - attribute \src "ls180.v:5352.879-5352.961" - cell $xor $xor$ls180.v:5352$1068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5352$1068_Y - end - attribute \src "ls180.v:5352.620-5352.702" - cell $xor $xor$ls180.v:5352$1069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5352$1069_Y - end - attribute \src "ls180.v:5352.575-5352.703" - cell $xor $xor$ls180.v:5352$1070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5352$1069_Y - connect \Y $xor$ls180.v:5352$1070_Y - end - attribute \src "ls180.v:5352.229-5352.311" - cell $xor $xor$ls180.v:5352$1071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5352$1071_Y - end - attribute \src "ls180.v:5352.183-5352.312" - cell $xor $xor$ls180.v:5352$1072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5352$1071_Y - connect \Y $xor$ls180.v:5352$1072_Y - end - attribute \src "ls180.v:5353.879-5353.961" - cell $xor $xor$ls180.v:5353$1073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5353$1073_Y - end - attribute \src "ls180.v:5353.620-5353.702" - cell $xor $xor$ls180.v:5353$1074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5353$1074_Y - end - attribute \src "ls180.v:5353.575-5353.703" - cell $xor $xor$ls180.v:5353$1075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5353$1074_Y - connect \Y $xor$ls180.v:5353$1075_Y - end - attribute \src "ls180.v:5353.229-5353.311" - cell $xor $xor$ls180.v:5353$1076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5353$1076_Y - end - attribute \src "ls180.v:5353.183-5353.312" - cell $xor $xor$ls180.v:5353$1077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5353$1076_Y - connect \Y $xor$ls180.v:5353$1077_Y - end - attribute \src "ls180.v:5362.879-5362.961" - cell $xor $xor$ls180.v:5362$1079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5362$1079_Y - end - attribute \src "ls180.v:5362.620-5362.702" - cell $xor $xor$ls180.v:5362$1080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5362$1080_Y - end - attribute \src "ls180.v:5362.575-5362.703" - cell $xor $xor$ls180.v:5362$1081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5362$1080_Y - connect \Y $xor$ls180.v:5362$1081_Y - end - attribute \src "ls180.v:5362.229-5362.311" - cell $xor $xor$ls180.v:5362$1082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5362$1082_Y - end - attribute \src "ls180.v:5362.183-5362.312" - cell $xor $xor$ls180.v:5362$1083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5362$1082_Y - connect \Y $xor$ls180.v:5362$1083_Y - end - attribute \src "ls180.v:5363.879-5363.961" - cell $xor $xor$ls180.v:5363$1084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5363$1084_Y - end - attribute \src "ls180.v:5363.620-5363.702" - cell $xor $xor$ls180.v:5363$1085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5363$1085_Y - end - attribute \src "ls180.v:5363.575-5363.703" - cell $xor $xor$ls180.v:5363$1086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5363$1085_Y - connect \Y $xor$ls180.v:5363$1086_Y - end - attribute \src "ls180.v:5363.229-5363.311" - cell $xor $xor$ls180.v:5363$1087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5363$1087_Y - end - attribute \src "ls180.v:5363.183-5363.312" - cell $xor $xor$ls180.v:5363$1088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5363$1087_Y - connect \Y $xor$ls180.v:5363$1088_Y - end - attribute \src "ls180.v:5372.879-5372.961" - cell $xor $xor$ls180.v:5372$1090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5372$1090_Y - end - attribute \src "ls180.v:5372.620-5372.702" - cell $xor $xor$ls180.v:5372$1091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5372$1091_Y - end - attribute \src "ls180.v:5372.575-5372.703" - cell $xor $xor$ls180.v:5372$1092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5372$1091_Y - connect \Y $xor$ls180.v:5372$1092_Y - end - attribute \src "ls180.v:5372.229-5372.311" - cell $xor $xor$ls180.v:5372$1093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5372$1093_Y - end - attribute \src "ls180.v:5372.183-5372.312" - cell $xor $xor$ls180.v:5372$1094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5372$1093_Y - connect \Y $xor$ls180.v:5372$1094_Y - end - attribute \src "ls180.v:5373.879-5373.961" - cell $xor $xor$ls180.v:5373$1095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5373$1095_Y - end - attribute \src "ls180.v:5373.620-5373.702" - cell $xor $xor$ls180.v:5373$1096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5373$1096_Y - end - attribute \src "ls180.v:5373.575-5373.703" - cell $xor $xor$ls180.v:5373$1097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5373$1096_Y - connect \Y $xor$ls180.v:5373$1097_Y - end - attribute \src "ls180.v:5373.229-5373.311" - cell $xor $xor$ls180.v:5373$1098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5373$1098_Y - end - attribute \src "ls180.v:5373.183-5373.312" - cell $xor $xor$ls180.v:5373$1099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5373$1098_Y - connect \Y $xor$ls180.v:5373$1099_Y - end - attribute \src "ls180.v:5382.879-5382.961" - cell $xor $xor$ls180.v:5382$1101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5382$1101_Y - end - attribute \src "ls180.v:5382.620-5382.702" - cell $xor $xor$ls180.v:5382$1102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5382$1102_Y - end - attribute \src "ls180.v:5382.575-5382.703" - cell $xor $xor$ls180.v:5382$1103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5382$1102_Y - connect \Y $xor$ls180.v:5382$1103_Y - end - attribute \src "ls180.v:5382.229-5382.311" - cell $xor $xor$ls180.v:5382$1104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5382$1104_Y - end - attribute \src "ls180.v:5382.183-5382.312" - cell $xor $xor$ls180.v:5382$1105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5382$1104_Y - connect \Y $xor$ls180.v:5382$1105_Y - end - attribute \src "ls180.v:5383.879-5383.961" - cell $xor $xor$ls180.v:5383$1106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5383$1106_Y - end - attribute \src "ls180.v:5383.620-5383.702" - cell $xor $xor$ls180.v:5383$1107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5383$1107_Y - end - attribute \src "ls180.v:5383.575-5383.703" - cell $xor $xor$ls180.v:5383$1108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5383$1107_Y - connect \Y $xor$ls180.v:5383$1108_Y - end - attribute \src "ls180.v:5383.229-5383.311" - cell $xor $xor$ls180.v:5383$1109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5383$1109_Y - end - attribute \src "ls180.v:5383.183-5383.312" - cell $xor $xor$ls180.v:5383$1110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5383$1109_Y - connect \Y $xor$ls180.v:5383$1110_Y - end - attribute \module_not_derived 1 - attribute \src "ls180.v:10606.13-11024.2" - cell \test_issuer \test_issuer - connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck - connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi - connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo - connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms - connect \busy_o \main_libresocsim_libresoc0 - connect \clk \sys_clk_1 - connect \clk_sel_i \main_libresocsim_libresoc_clk_sel - connect \core_bigendian_i 1'0 - connect \dbus__ack \main_libresocsim_libresoc_dbus_ack - connect \dbus__adr \main_libresocsim_libresoc_dbus_adr - connect \dbus__bte 1'0 - connect \dbus__cti 1'0 - connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc - connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r - connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w - connect \dbus__err \main_libresocsim_libresoc_dbus_err - connect \dbus__sel \main_libresocsim_libresoc_dbus_sel - connect \dbus__stb \main_libresocsim_libresoc_dbus_stb - connect \dbus__we \main_libresocsim_libresoc_dbus_we - connect \eint_0__core__i \eint [0] - connect \eint_0__pad__i \eint_1 [0] - connect \eint_1__core__i \eint [1] - connect \eint_1__pad__i \eint_1 [1] - connect \eint_2__core__i \eint [2] - connect \eint_2__pad__i \eint_1 [2] - connect \gpio_e10__core__i \gpio_i [10] - connect \gpio_e10__core__o \gpio_o [10] - connect \gpio_e10__core__oe \gpio_oe [10] - connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10] - connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10] - connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] - connect \gpio_e11__core__i \gpio_i [11] - connect \gpio_e11__core__o \gpio_o [11] - connect \gpio_e11__core__oe \gpio_oe [11] - connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11] - connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11] - connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] - connect \gpio_e12__core__i \gpio_i [12] - connect \gpio_e12__core__o \gpio_o [12] - connect \gpio_e12__core__oe \gpio_oe [12] - connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12] - connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12] - connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] - connect \gpio_e13__core__i \gpio_i [13] - connect \gpio_e13__core__o \gpio_o [13] - connect \gpio_e13__core__oe \gpio_oe [13] - connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13] - connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13] - connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] - connect \gpio_e14__core__i \gpio_i [14] - connect \gpio_e14__core__o \gpio_o [14] - connect \gpio_e14__core__oe \gpio_oe [14] - connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14] - connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14] - connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] - connect \gpio_e15__core__i \gpio_i [15] - connect \gpio_e15__core__o \gpio_o [15] - connect \gpio_e15__core__oe \gpio_oe [15] - connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15] - connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15] - connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] - connect \gpio_e8__core__i \gpio_i [8] - connect \gpio_e8__core__o \gpio_o [8] - connect \gpio_e8__core__oe \gpio_oe [8] - connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8] - connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8] - connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] - connect \gpio_e9__core__i \gpio_i [9] - connect \gpio_e9__core__o \gpio_o [9] - connect \gpio_e9__core__oe \gpio_oe [9] - connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9] - connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9] - connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] - connect \gpio_s0__core__i \gpio_i [0] - connect \gpio_s0__core__o \gpio_o [0] - connect \gpio_s0__core__oe \gpio_oe [0] - connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0] - connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0] - connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] - connect \gpio_s1__core__i \gpio_i [1] - connect \gpio_s1__core__o \gpio_o [1] - connect \gpio_s1__core__oe \gpio_oe [1] - connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1] - connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1] - connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] - connect \gpio_s2__core__i \gpio_i [2] - connect \gpio_s2__core__o \gpio_o [2] - connect \gpio_s2__core__oe \gpio_oe [2] - connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2] - connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2] - connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] - connect \gpio_s3__core__i \gpio_i [3] - connect \gpio_s3__core__o \gpio_o [3] - connect \gpio_s3__core__oe \gpio_oe [3] - connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3] - connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3] - connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] - connect \gpio_s4__core__i \gpio_i [4] - connect \gpio_s4__core__o \gpio_o [4] - connect \gpio_s4__core__oe \gpio_oe [4] - connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4] - connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4] - connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] - connect \gpio_s5__core__i \gpio_i [5] - connect \gpio_s5__core__o \gpio_o [5] - connect \gpio_s5__core__oe \gpio_oe [5] - connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5] - connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5] - connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] - connect \gpio_s6__core__i \gpio_i [6] - connect \gpio_s6__core__o \gpio_o [6] - connect \gpio_s6__core__oe \gpio_oe [6] - connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6] - connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6] - connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] - connect \gpio_s7__core__i \gpio_i [7] - connect \gpio_s7__core__o \gpio_o [7] - connect \gpio_s7__core__oe \gpio_oe [7] - connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7] - connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7] - connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] - connect \ibus__ack \main_libresocsim_libresoc_ibus_ack - connect \ibus__adr \main_libresocsim_libresoc_ibus_adr - connect \ibus__bte 1'0 - connect \ibus__cti 1'0 - connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc - connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r - connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w - connect \ibus__err \main_libresocsim_libresoc_ibus_err - connect \ibus__sel \main_libresocsim_libresoc_ibus_sel - connect \ibus__stb \main_libresocsim_libresoc_ibus_stb - connect \ibus__we \main_libresocsim_libresoc_ibus_we - connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack - connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr - connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc - connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r - connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w - connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err - connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel - connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb - connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we - connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack - connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr - connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc - connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r - connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w - connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err - connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel - connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb - connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we - connect \int_level_i \main_libresocsim_libresoc_interrupt - connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack - connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr - connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc - connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r - connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w - connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err - connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel - connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb - connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we - connect \memerr_o \main_libresocsim_libresoc1 - connect \mspi0_clk__core__o \spimaster_clk - connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - connect \mspi0_cs_n__core__o \spimaster_cs_n - connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - connect \mspi0_miso__core__i \spimaster_miso - connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - connect \mspi0_mosi__core__o \spimaster_mosi - connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - connect \mspi1_clk__core__o \spisdcard_clk - connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - connect \mspi1_cs_n__core__o \spisdcard_cs_n - connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - connect \mspi1_miso__core__i \spisdcard_miso - connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - connect \mspi1_mosi__core__o \spisdcard_mosi - connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - connect \mtwi_scl__core__o \i2c_scl - connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - connect \mtwi_sda__core__i \i2c_sda_i - connect \mtwi_sda__core__o \i2c_sda_o - connect \mtwi_sda__core__oe \i2c_sda_oe - connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - connect \pc_i 1'0 - connect \pc_i_ok 1'0 - connect \pc_o \main_libresocsim_libresoc2 - connect \pll_18_o \main_libresocsim_libresoc_pll_18_o - connect \pll_lck_o \main_libresocsim_libresoc_pll_lck_o - connect \pwm_0__core__o \pwm [0] - connect \pwm_0__pad__o \pwm_1 [0] - connect \pwm_1__core__o \pwm [1] - connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10706$3077_Y - connect \sd0_clk__core__o \sdcard_clk - connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - connect \sd0_cmd__core__i \sdcard_cmd_i - connect \sd0_cmd__core__o \sdcard_cmd_o - connect \sd0_cmd__core__oe \sdcard_cmd_oe - connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data0__core__i \sdcard_cmd_i - connect \sd0_data0__core__o \sdcard_cmd_o - connect \sd0_data0__core__oe \sdcard_cmd_oe - connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data1__core__i \sdcard_cmd_i - connect \sd0_data1__core__o \sdcard_cmd_o - connect \sd0_data1__core__oe \sdcard_cmd_oe - connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data2__core__i \sdcard_cmd_i - connect \sd0_data2__core__o \sdcard_cmd_o - connect \sd0_data2__core__oe \sdcard_cmd_oe - connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data3__core__i \sdcard_cmd_i - connect \sd0_data3__core__o \sdcard_cmd_o - connect \sd0_data3__core__oe \sdcard_cmd_oe - connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sdr_a_0__core__o \sdram_a [0] - connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] - connect \sdr_a_10__core__o \sdram_a [10] - connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10] - connect \sdr_a_11__core__o \sdram_a [11] - connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11] - connect \sdr_a_12__core__o \sdram_a [12] - connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12] - connect \sdr_a_1__core__o \sdram_a [1] - connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1] - connect \sdr_a_2__core__o \sdram_a [2] - connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2] - connect \sdr_a_3__core__o \sdram_a [3] - connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3] - connect \sdr_a_4__core__o \sdram_a [4] - connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4] - connect \sdr_a_5__core__o \sdram_a [5] - connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5] - connect \sdr_a_6__core__o \sdram_a [6] - connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6] - connect \sdr_a_7__core__o \sdram_a [7] - connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7] - connect \sdr_a_8__core__o \sdram_a [8] - connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8] - connect \sdr_a_9__core__o \sdram_a [9] - connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9] - connect \sdr_ba_0__core__o \sdram_ba [0] - connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] - connect \sdr_ba_1__core__o \sdram_ba [1] - connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] - connect \sdr_cas_n__core__o \sdram_cas_n - connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - connect \sdr_cke__core__o \sdram_cke - connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - connect \sdr_clock__core__o \sdram_clock - connect \sdr_clock__pad__o \sdram_clock_1 - connect \sdr_cs_n__core__o \sdram_cs_n - connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - connect \sdr_dm_0__core__o \sdram_dm [0] - connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] - connect \sdr_dm_1__core__i \sdram_dq_i [1] - connect \sdr_dm_1__core__o \sdram_dq_o [1] - connect \sdr_dm_1__core__oe \sdram_dq_oe - connect \sdr_dm_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] - connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] - connect \sdr_dm_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_0__core__i \sdram_dq_i [0] - connect \sdr_dq_0__core__o \sdram_dq_o [0] - connect \sdr_dq_0__core__oe \sdram_dq_oe - connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] - connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] - connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_10__core__i \sdram_dq_i [10] - connect \sdr_dq_10__core__o \sdram_dq_o [10] - connect \sdr_dq_10__core__oe \sdram_dq_oe - connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] - connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] - connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_11__core__i \sdram_dq_i [11] - connect \sdr_dq_11__core__o \sdram_dq_o [11] - connect \sdr_dq_11__core__oe \sdram_dq_oe - connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] - connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] - connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_12__core__i \sdram_dq_i [12] - connect \sdr_dq_12__core__o \sdram_dq_o [12] - connect \sdr_dq_12__core__oe \sdram_dq_oe - connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] - connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] - connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_13__core__i \sdram_dq_i [13] - connect \sdr_dq_13__core__o \sdram_dq_o [13] - connect \sdr_dq_13__core__oe \sdram_dq_oe - connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] - connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] - connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_14__core__i \sdram_dq_i [14] - connect \sdr_dq_14__core__o \sdram_dq_o [14] - connect \sdr_dq_14__core__oe \sdram_dq_oe - connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] - connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] - connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_15__core__i \sdram_dq_i [15] - connect \sdr_dq_15__core__o \sdram_dq_o [15] - connect \sdr_dq_15__core__oe \sdram_dq_oe - connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] - connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] - connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_1__core__i \sdram_dq_i [1] - connect \sdr_dq_1__core__o \sdram_dq_o [1] - connect \sdr_dq_1__core__oe \sdram_dq_oe - connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] - connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] - connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_2__core__i \sdram_dq_i [2] - connect \sdr_dq_2__core__o \sdram_dq_o [2] - connect \sdr_dq_2__core__oe \sdram_dq_oe - connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] - connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] - connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_3__core__i \sdram_dq_i [3] - connect \sdr_dq_3__core__o \sdram_dq_o [3] - connect \sdr_dq_3__core__oe \sdram_dq_oe - connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] - connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] - connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_4__core__i \sdram_dq_i [4] - connect \sdr_dq_4__core__o \sdram_dq_o [4] - connect \sdr_dq_4__core__oe \sdram_dq_oe - connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] - connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] - connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_5__core__i \sdram_dq_i [5] - connect \sdr_dq_5__core__o \sdram_dq_o [5] - connect \sdr_dq_5__core__oe \sdram_dq_oe - connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] - connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] - connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_6__core__i \sdram_dq_i [6] - connect \sdr_dq_6__core__o \sdram_dq_o [6] - connect \sdr_dq_6__core__oe \sdram_dq_oe - connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] - connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] - connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_7__core__i \sdram_dq_i [7] - connect \sdr_dq_7__core__o \sdram_dq_o [7] - connect \sdr_dq_7__core__oe \sdram_dq_oe - connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] - connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] - connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_8__core__i \sdram_dq_i [8] - connect \sdr_dq_8__core__o \sdram_dq_o [8] - connect \sdr_dq_8__core__oe \sdram_dq_oe - connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] - connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] - connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_9__core__i \sdram_dq_i [9] - connect \sdr_dq_9__core__o \sdram_dq_o [9] - connect \sdr_dq_9__core__oe \sdram_dq_oe - connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] - connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] - connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_ras_n__core__o \sdram_ras_n - connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - connect \sdr_we_n__core__o \sdram_we_n - connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - connect \sram4k_0_wb__ack \main_libresocsim_libresoc_interface0_ack - connect \sram4k_0_wb__adr \main_libresocsim_libresoc_interface0_adr - connect \sram4k_0_wb__bte \main_libresocsim_libresoc_interface0_bte - connect \sram4k_0_wb__cti \main_libresocsim_libresoc_interface0_cti - connect \sram4k_0_wb__cyc \main_libresocsim_libresoc_interface0_cyc - connect \sram4k_0_wb__dat_r \main_libresocsim_libresoc_interface0_dat_r - connect \sram4k_0_wb__dat_w \main_libresocsim_libresoc_interface0_dat_w - connect \sram4k_0_wb__err \main_libresocsim_libresoc_interface0_err - connect \sram4k_0_wb__sel \main_libresocsim_libresoc_interface0_sel - connect \sram4k_0_wb__stb \main_libresocsim_libresoc_interface0_stb - connect \sram4k_0_wb__we \main_libresocsim_libresoc_interface0_we - connect \sram4k_1_wb__ack \main_libresocsim_libresoc_interface1_ack - connect \sram4k_1_wb__adr \main_libresocsim_libresoc_interface1_adr - connect \sram4k_1_wb__bte \main_libresocsim_libresoc_interface1_bte - connect \sram4k_1_wb__cti \main_libresocsim_libresoc_interface1_cti - connect \sram4k_1_wb__cyc \main_libresocsim_libresoc_interface1_cyc - connect \sram4k_1_wb__dat_r \main_libresocsim_libresoc_interface1_dat_r - connect \sram4k_1_wb__dat_w \main_libresocsim_libresoc_interface1_dat_w - connect \sram4k_1_wb__err \main_libresocsim_libresoc_interface1_err - connect \sram4k_1_wb__sel \main_libresocsim_libresoc_interface1_sel - connect \sram4k_1_wb__stb \main_libresocsim_libresoc_interface1_stb - connect \sram4k_1_wb__we \main_libresocsim_libresoc_interface1_we - connect \sram4k_2_wb__ack \main_libresocsim_libresoc_interface2_ack - connect \sram4k_2_wb__adr \main_libresocsim_libresoc_interface2_adr - connect \sram4k_2_wb__bte \main_libresocsim_libresoc_interface2_bte - connect \sram4k_2_wb__cti \main_libresocsim_libresoc_interface2_cti - connect \sram4k_2_wb__cyc \main_libresocsim_libresoc_interface2_cyc - connect \sram4k_2_wb__dat_r \main_libresocsim_libresoc_interface2_dat_r - connect \sram4k_2_wb__dat_w \main_libresocsim_libresoc_interface2_dat_w - connect \sram4k_2_wb__err \main_libresocsim_libresoc_interface2_err - connect \sram4k_2_wb__sel \main_libresocsim_libresoc_interface2_sel - connect \sram4k_2_wb__stb \main_libresocsim_libresoc_interface2_stb - connect \sram4k_2_wb__we \main_libresocsim_libresoc_interface2_we - connect \sram4k_3_wb__ack \main_libresocsim_libresoc_interface3_ack - connect \sram4k_3_wb__adr \main_libresocsim_libresoc_interface3_adr - connect \sram4k_3_wb__bte \main_libresocsim_libresoc_interface3_bte - connect \sram4k_3_wb__cti \main_libresocsim_libresoc_interface3_cti - connect \sram4k_3_wb__cyc \main_libresocsim_libresoc_interface3_cyc - connect \sram4k_3_wb__dat_r \main_libresocsim_libresoc_interface3_dat_r - connect \sram4k_3_wb__dat_w \main_libresocsim_libresoc_interface3_dat_w - connect \sram4k_3_wb__err \main_libresocsim_libresoc_interface3_err - connect \sram4k_3_wb__sel \main_libresocsim_libresoc_interface3_sel - connect \sram4k_3_wb__stb \main_libresocsim_libresoc_interface3_stb - connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4086 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4087 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4088 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4089 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4090 - sync always - sync init - end - attribute \src "ls180.v:100.11-100.56" - process $proc$ls180.v:100$3144 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] - end - attribute \src "ls180.v:1009.5-1009.40" - process $proc$ls180.v:1009$3478 - assign { } { } - assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] - sync init - end - attribute \src "ls180.v:101.5-101.50" - process $proc$ls180.v:101$3145 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] - end - attribute \src "ls180.v:1010.5-1010.39" - process $proc$ls180.v:1010$3479 - assign { } { } - assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1018.5-1018.38" - process $proc$ls180.v:1018$3480 - assign { } { } - assign $1\main_uart_tx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] - end - attribute \src "ls180.v:102.5-102.50" - process $proc$ls180.v:102$3146 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] - end - attribute \src "ls180.v:1025.11-1025.42" - process $proc$ls180.v:1025$3481 - assign { } { } - assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] - end - attribute \src "ls180.v:1026.5-1026.37" - process $proc$ls180.v:1026$3482 - assign { } { } - assign $0\main_uart_tx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1027.11-1027.43" - process $proc$ls180.v:1027$3483 - assign { } { } - assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] - end - attribute \src "ls180.v:1028.11-1028.43" - process $proc$ls180.v:1028$3484 - assign { } { } - assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] - end - attribute \src "ls180.v:1029.11-1029.46" - process $proc$ls180.v:1029$3485 - assign { } { } - assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:10350.1-10368.4" - process $proc$ls180.v:10350$2891 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr[5:0] \main_libresocsim_adr - attribute \src "ls180.v:10351.2-10352.65" - switch \main_libresocsim_we [0] - attribute \src "ls180.v:10351.6-10351.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10353.2-10354.67" - switch \main_libresocsim_we [1] - attribute \src "ls180.v:10353.6-10353.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10355.2-10356.69" - switch \main_libresocsim_we [2] - attribute \src "ls180.v:10355.6-10355.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10357.2-10358.69" - switch \main_libresocsim_we [3] - attribute \src "ls180.v:10357.6-10357.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10359.2-10360.69" - switch \main_libresocsim_we [4] - attribute \src "ls180.v:10359.6-10359.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10361.2-10362.69" - switch \main_libresocsim_we [5] - attribute \src "ls180.v:10361.6-10361.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10363.2-10364.69" - switch \main_libresocsim_we [6] - attribute \src "ls180.v:10363.6-10363.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10365.2-10366.69" - switch \main_libresocsim_we [7] - attribute \src "ls180.v:10365.6-10365.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr $0\memadr[5:0] - update $memwr$\mem$ls180.v:10352$1_ADDR $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 - update $memwr$\mem$ls180.v:10352$1_DATA $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 - update $memwr$\mem$ls180.v:10352$1_EN $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 - update $memwr$\mem$ls180.v:10354$2_ADDR $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 - update $memwr$\mem$ls180.v:10354$2_DATA $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 - update $memwr$\mem$ls180.v:10354$2_EN $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 - update $memwr$\mem$ls180.v:10356$3_ADDR $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 - update $memwr$\mem$ls180.v:10356$3_DATA $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 - update $memwr$\mem$ls180.v:10356$3_EN $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 - update $memwr$\mem$ls180.v:10358$4_ADDR $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 - update $memwr$\mem$ls180.v:10358$4_DATA $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 - update $memwr$\mem$ls180.v:10358$4_EN $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 - update $memwr$\mem$ls180.v:10360$5_ADDR $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 - update $memwr$\mem$ls180.v:10360$5_DATA $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 - update $memwr$\mem$ls180.v:10360$5_EN $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 - update $memwr$\mem$ls180.v:10362$6_ADDR $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 - update $memwr$\mem$ls180.v:10362$6_DATA $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 - update $memwr$\mem$ls180.v:10362$6_EN $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 - update $memwr$\mem$ls180.v:10364$7_ADDR $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 - update $memwr$\mem$ls180.v:10364$7_DATA $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 - update $memwr$\mem$ls180.v:10364$7_EN $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 - update $memwr$\mem$ls180.v:10366$8_ADDR $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 - update $memwr$\mem$ls180.v:10366$8_DATA $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 - update $memwr$\mem$ls180.v:10366$8_EN $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 - end - attribute \src "ls180.v:10378.1-10396.4" - process $proc$ls180.v:10378$2917 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_1[5:0] \main_sram0_adr - attribute \src "ls180.v:10379.2-10380.55" - switch \main_sram0_we [0] - attribute \src "ls180.v:10379.6-10379.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } - assign $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10381.2-10382.57" - switch \main_sram0_we [1] - attribute \src "ls180.v:10381.6-10381.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10383.2-10384.59" - switch \main_sram0_we [2] - attribute \src "ls180.v:10383.6-10383.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10385.2-10386.59" - switch \main_sram0_we [3] - attribute \src "ls180.v:10385.6-10385.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10387.2-10388.59" - switch \main_sram0_we [4] - attribute \src "ls180.v:10387.6-10387.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10389.2-10390.59" - switch \main_sram0_we [5] - attribute \src "ls180.v:10389.6-10389.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10391.2-10392.59" - switch \main_sram0_we [6] - attribute \src "ls180.v:10391.6-10391.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10393.2-10394.59" - switch \main_sram0_we [7] - attribute \src "ls180.v:10393.6-10393.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_1 $0\memadr_1[5:0] - update $memwr$\mem_1$ls180.v:10380$9_ADDR $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 - update $memwr$\mem_1$ls180.v:10380$9_DATA $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 - update $memwr$\mem_1$ls180.v:10380$9_EN $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 - update $memwr$\mem_1$ls180.v:10382$10_ADDR $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 - update $memwr$\mem_1$ls180.v:10382$10_DATA $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 - update $memwr$\mem_1$ls180.v:10382$10_EN $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 - update $memwr$\mem_1$ls180.v:10384$11_ADDR $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 - update $memwr$\mem_1$ls180.v:10384$11_DATA $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 - update $memwr$\mem_1$ls180.v:10384$11_EN $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 - update $memwr$\mem_1$ls180.v:10386$12_ADDR $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 - update $memwr$\mem_1$ls180.v:10386$12_DATA $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 - update $memwr$\mem_1$ls180.v:10386$12_EN $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 - update $memwr$\mem_1$ls180.v:10388$13_ADDR $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 - update $memwr$\mem_1$ls180.v:10388$13_DATA $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 - update $memwr$\mem_1$ls180.v:10388$13_EN $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 - update $memwr$\mem_1$ls180.v:10390$14_ADDR $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 - update $memwr$\mem_1$ls180.v:10390$14_DATA $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 - update $memwr$\mem_1$ls180.v:10390$14_EN $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 - update $memwr$\mem_1$ls180.v:10392$15_ADDR $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 - update $memwr$\mem_1$ls180.v:10392$15_DATA $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 - update $memwr$\mem_1$ls180.v:10392$15_EN $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 - update $memwr$\mem_1$ls180.v:10394$16_ADDR $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 - update $memwr$\mem_1$ls180.v:10394$16_DATA $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 - update $memwr$\mem_1$ls180.v:10394$16_EN $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 - end - attribute \src "ls180.v:104.5-104.49" - process $proc$ls180.v:104$3147 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] - end - attribute \src "ls180.v:10406.1-10424.4" - process $proc$ls180.v:10406$2943 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_2[5:0] \main_sram1_adr - attribute \src "ls180.v:10407.2-10408.55" - switch \main_sram1_we [0] - attribute \src "ls180.v:10407.6-10407.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } - assign $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10409.2-10410.57" - switch \main_sram1_we [1] - attribute \src "ls180.v:10409.6-10409.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10411.2-10412.59" - switch \main_sram1_we [2] - attribute \src "ls180.v:10411.6-10411.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10413.2-10414.59" - switch \main_sram1_we [3] - attribute \src "ls180.v:10413.6-10413.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10415.2-10416.59" - switch \main_sram1_we [4] - attribute \src "ls180.v:10415.6-10415.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10417.2-10418.59" - switch \main_sram1_we [5] - attribute \src "ls180.v:10417.6-10417.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10419.2-10420.59" - switch \main_sram1_we [6] - attribute \src "ls180.v:10419.6-10419.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10421.2-10422.59" - switch \main_sram1_we [7] - attribute \src "ls180.v:10421.6-10421.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_2 $0\memadr_2[5:0] - update $memwr$\mem_2$ls180.v:10408$17_ADDR $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 - update $memwr$\mem_2$ls180.v:10408$17_DATA $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 - update $memwr$\mem_2$ls180.v:10408$17_EN $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 - update $memwr$\mem_2$ls180.v:10410$18_ADDR $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 - update $memwr$\mem_2$ls180.v:10410$18_DATA $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 - update $memwr$\mem_2$ls180.v:10410$18_EN $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 - update $memwr$\mem_2$ls180.v:10412$19_ADDR $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 - update $memwr$\mem_2$ls180.v:10412$19_DATA $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 - update $memwr$\mem_2$ls180.v:10412$19_EN $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 - update $memwr$\mem_2$ls180.v:10414$20_ADDR $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 - update $memwr$\mem_2$ls180.v:10414$20_DATA $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 - update $memwr$\mem_2$ls180.v:10414$20_EN $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 - update $memwr$\mem_2$ls180.v:10416$21_ADDR $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 - update $memwr$\mem_2$ls180.v:10416$21_DATA $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 - update $memwr$\mem_2$ls180.v:10416$21_EN $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 - update $memwr$\mem_2$ls180.v:10418$22_ADDR $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 - update $memwr$\mem_2$ls180.v:10418$22_DATA $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 - update $memwr$\mem_2$ls180.v:10418$22_EN $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 - update $memwr$\mem_2$ls180.v:10420$23_ADDR $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 - update $memwr$\mem_2$ls180.v:10420$23_DATA $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 - update $memwr$\mem_2$ls180.v:10420$23_EN $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 - update $memwr$\mem_2$ls180.v:10422$24_ADDR $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 - update $memwr$\mem_2$ls180.v:10422$24_DATA $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 - update $memwr$\mem_2$ls180.v:10422$24_EN $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 - end - attribute \src "ls180.v:10434.1-10452.4" - process $proc$ls180.v:10434$2969 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_3[5:0] \main_sram2_adr - attribute \src "ls180.v:10435.2-10436.55" - switch \main_sram2_we [0] - attribute \src "ls180.v:10435.6-10435.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } - assign $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10437.2-10438.57" - switch \main_sram2_we [1] - attribute \src "ls180.v:10437.6-10437.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10439.2-10440.59" - switch \main_sram2_we [2] - attribute \src "ls180.v:10439.6-10439.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10441.2-10442.59" - switch \main_sram2_we [3] - attribute \src "ls180.v:10441.6-10441.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10443.2-10444.59" - switch \main_sram2_we [4] - attribute \src "ls180.v:10443.6-10443.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10445.2-10446.59" - switch \main_sram2_we [5] - attribute \src "ls180.v:10445.6-10445.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10447.2-10448.59" - switch \main_sram2_we [6] - attribute \src "ls180.v:10447.6-10447.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10449.2-10450.59" - switch \main_sram2_we [7] - attribute \src "ls180.v:10449.6-10449.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_3 $0\memadr_3[5:0] - update $memwr$\mem_3$ls180.v:10436$25_ADDR $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 - update $memwr$\mem_3$ls180.v:10436$25_DATA $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 - update $memwr$\mem_3$ls180.v:10436$25_EN $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 - update $memwr$\mem_3$ls180.v:10438$26_ADDR $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 - update $memwr$\mem_3$ls180.v:10438$26_DATA $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 - update $memwr$\mem_3$ls180.v:10438$26_EN $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 - update $memwr$\mem_3$ls180.v:10440$27_ADDR $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 - update $memwr$\mem_3$ls180.v:10440$27_DATA $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 - update $memwr$\mem_3$ls180.v:10440$27_EN $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 - update $memwr$\mem_3$ls180.v:10442$28_ADDR $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 - update $memwr$\mem_3$ls180.v:10442$28_DATA $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 - update $memwr$\mem_3$ls180.v:10442$28_EN $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 - update $memwr$\mem_3$ls180.v:10444$29_ADDR $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 - update $memwr$\mem_3$ls180.v:10444$29_DATA $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 - update $memwr$\mem_3$ls180.v:10444$29_EN $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 - update $memwr$\mem_3$ls180.v:10446$30_ADDR $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 - update $memwr$\mem_3$ls180.v:10446$30_DATA $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 - update $memwr$\mem_3$ls180.v:10446$30_EN $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 - update $memwr$\mem_3$ls180.v:10448$31_ADDR $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 - update $memwr$\mem_3$ls180.v:10448$31_DATA $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 - update $memwr$\mem_3$ls180.v:10448$31_EN $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 - update $memwr$\mem_3$ls180.v:10450$32_ADDR $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 - update $memwr$\mem_3$ls180.v:10450$32_DATA $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 - update $memwr$\mem_3$ls180.v:10450$32_EN $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 - end - attribute \src "ls180.v:10462.1-10480.4" - process $proc$ls180.v:10462$2995 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_4[5:0] \main_sram3_adr - attribute \src "ls180.v:10463.2-10464.55" - switch \main_sram3_we [0] - attribute \src "ls180.v:10463.6-10463.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } - assign $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10465.2-10466.57" - switch \main_sram3_we [1] - attribute \src "ls180.v:10465.6-10465.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10467.2-10468.59" - switch \main_sram3_we [2] - attribute \src "ls180.v:10467.6-10467.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10469.2-10470.59" - switch \main_sram3_we [3] - attribute \src "ls180.v:10469.6-10469.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10471.2-10472.59" - switch \main_sram3_we [4] - attribute \src "ls180.v:10471.6-10471.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10473.2-10474.59" - switch \main_sram3_we [5] - attribute \src "ls180.v:10473.6-10473.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10475.2-10476.59" - switch \main_sram3_we [6] - attribute \src "ls180.v:10475.6-10475.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10477.2-10478.59" - switch \main_sram3_we [7] - attribute \src "ls180.v:10477.6-10477.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_4 $0\memadr_4[5:0] - update $memwr$\mem_4$ls180.v:10464$33_ADDR $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 - update $memwr$\mem_4$ls180.v:10464$33_DATA $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 - update $memwr$\mem_4$ls180.v:10464$33_EN $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 - update $memwr$\mem_4$ls180.v:10466$34_ADDR $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 - update $memwr$\mem_4$ls180.v:10466$34_DATA $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 - update $memwr$\mem_4$ls180.v:10466$34_EN $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 - update $memwr$\mem_4$ls180.v:10468$35_ADDR $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 - update $memwr$\mem_4$ls180.v:10468$35_DATA $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 - update $memwr$\mem_4$ls180.v:10468$35_EN $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 - update $memwr$\mem_4$ls180.v:10470$36_ADDR $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 - update $memwr$\mem_4$ls180.v:10470$36_DATA $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 - update $memwr$\mem_4$ls180.v:10470$36_EN $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 - update $memwr$\mem_4$ls180.v:10472$37_ADDR $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 - update $memwr$\mem_4$ls180.v:10472$37_DATA $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 - update $memwr$\mem_4$ls180.v:10472$37_EN $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 - update $memwr$\mem_4$ls180.v:10474$38_ADDR $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 - update $memwr$\mem_4$ls180.v:10474$38_DATA $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 - update $memwr$\mem_4$ls180.v:10474$38_EN $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 - update $memwr$\mem_4$ls180.v:10476$39_ADDR $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 - update $memwr$\mem_4$ls180.v:10476$39_DATA $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 - update $memwr$\mem_4$ls180.v:10476$39_EN $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 - update $memwr$\mem_4$ls180.v:10478$40_ADDR $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 - update $memwr$\mem_4$ls180.v:10478$40_DATA $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 - update $memwr$\mem_4$ls180.v:10478$40_EN $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 - end - attribute \src "ls180.v:10490.1-10494.4" - process $proc$ls180.v:10490$3021 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 3'xxx - assign $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10493$3025_DATA - attribute \src "ls180.v:10491.2-10492.129" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10491.6-10491.60" - case 1'1 - assign $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10492$41_ADDR $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 - update $memwr$\storage$ls180.v:10492$41_DATA $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 - update $memwr$\storage$ls180.v:10492$41_EN $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 - end - attribute \src "ls180.v:10496.1-10497.4" - process $proc$ls180.v:10496$3026 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10504.1-10508.4" - process $proc$ls180.v:10504$3028 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 3'xxx - assign $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10507$3032_DATA - attribute \src "ls180.v:10505.2-10506.131" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10505.6-10505.60" - case 1'1 - assign $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10506$42_ADDR $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 - update $memwr$\storage_1$ls180.v:10506$42_DATA $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 - update $memwr$\storage_1$ls180.v:10506$42_EN $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 - end - attribute \src "ls180.v:10510.1-10511.4" - process $proc$ls180.v:10510$3033 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10518.1-10522.4" - process $proc$ls180.v:10518$3035 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 3'xxx - assign $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10521$3039_DATA - attribute \src "ls180.v:10519.2-10520.131" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10519.6-10519.60" - case 1'1 - assign $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10520$43_ADDR $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 - update $memwr$\storage_2$ls180.v:10520$43_DATA $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 - update $memwr$\storage_2$ls180.v:10520$43_EN $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 - end - attribute \src "ls180.v:10524.1-10525.4" - process $proc$ls180.v:10524$3040 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10532.1-10536.4" - process $proc$ls180.v:10532$3042 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 3'xxx - assign $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10535$3046_DATA - attribute \src "ls180.v:10533.2-10534.131" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10533.6-10533.60" - case 1'1 - assign $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10534$44_ADDR $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 - update $memwr$\storage_3$ls180.v:10534$44_DATA $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 - update $memwr$\storage_3$ls180.v:10534$44_EN $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 - end - attribute \src "ls180.v:10538.1-10539.4" - process $proc$ls180.v:10538$3047 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10547.1-10551.4" - process $proc$ls180.v:10547$3049 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10550$3053_DATA - attribute \src "ls180.v:10548.2-10549.77" - switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10548.6-10548.33" - case 1'1 - assign $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10549$45_ADDR $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 - update $memwr$\storage_4$ls180.v:10549$45_DATA $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 - update $memwr$\storage_4$ls180.v:10549$45_EN $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 - end - attribute \src "ls180.v:1055.5-1055.38" - process $proc$ls180.v:1055$3486 - assign { } { } - assign $1\main_uart_rx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] - end - attribute \src "ls180.v:10553.1-10556.4" - process $proc$ls180.v:10553$3054 - assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10554.2-10555.55" - switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10554.6-10554.33" - case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10555$3055_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_5 $0\memdat_5[9:0] - end - attribute \src "ls180.v:10564.1-10568.4" - process $proc$ls180.v:10564$3056 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10567$3060_DATA - attribute \src "ls180.v:10565.2-10566.77" - switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10565.6-10565.33" - case 1'1 - assign $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10566$46_ADDR $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 - update $memwr$\storage_5$ls180.v:10566$46_DATA $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 - update $memwr$\storage_5$ls180.v:10566$46_EN $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 - end - attribute \src "ls180.v:10570.1-10573.4" - process $proc$ls180.v:10570$3061 - assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10571.2-10572.55" - switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10571.6-10571.33" - case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10572$3062_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_7 $0\memdat_7[9:0] - end - attribute \src "ls180.v:10580.1-10584.4" - process $proc$ls180.v:10580$3063 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10583$3067_DATA - attribute \src "ls180.v:10581.2-10582.85" - switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10581.6-10581.37" - case 1'1 - assign $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10582$47_ADDR $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 - update $memwr$\storage_6$ls180.v:10582$47_DATA $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 - update $memwr$\storage_6$ls180.v:10582$47_EN $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 - end - attribute \src "ls180.v:10586.1-10587.4" - process $proc$ls180.v:10586$3068 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10594.1-10598.4" - process $proc$ls180.v:10594$3070 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10597$3074_DATA - attribute \src "ls180.v:10595.2-10596.85" - switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10595.6-10595.37" - case 1'1 - assign $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10596$48_ADDR $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 - update $memwr$\storage_7$ls180.v:10596$48_DATA $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 - update $memwr$\storage_7$ls180.v:10596$48_EN $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 - end - attribute \src "ls180.v:10600.1-10601.4" - process $proc$ls180.v:10600$3075 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1062.11-1062.42" - process $proc$ls180.v:1062$3487 - assign { } { } - assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] - end - attribute \src "ls180.v:1063.5-1063.37" - process $proc$ls180.v:1063$3488 - assign { } { } - assign $0\main_uart_rx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1064.11-1064.43" - process $proc$ls180.v:1064$3489 - assign { } { } - assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] - end - attribute \src "ls180.v:1065.11-1065.43" - process $proc$ls180.v:1065$3490 - assign { } { } - assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] - end - attribute \src "ls180.v:1066.11-1066.46" - process $proc$ls180.v:1066$3491 - assign { } { } - assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:1081.5-1081.27" - process $proc$ls180.v:1081$3492 - assign { } { } - assign $0\main_uart_reset[0:0] 1'0 - sync always - update \main_uart_reset $0\main_uart_reset[0:0] - sync init - end - attribute \src "ls180.v:1082.12-1082.53" - process $proc$ls180.v:1082$3493 - assign { } { } - assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 - sync always - update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] - sync init - end - attribute \src "ls180.v:1083.12-1083.49" - process $proc$ls180.v:1083$3494 - assign { } { } - assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] - end - attribute \src "ls180.v:1084.12-1084.54" - process $proc$ls180.v:1084$3495 - assign { } { } - assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 - sync always - update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] - sync init - end - attribute \src "ls180.v:1088.12-1088.53" - process $proc$ls180.v:1088$3496 - assign { } { } - assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] - end - attribute \src "ls180.v:1089.5-1089.40" - process $proc$ls180.v:1089$3497 - assign { } { } - assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 - sync always - sync init - update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] - end - attribute \src "ls180.v:1090.12-1090.49" - process $proc$ls180.v:1090$3498 - assign { } { } - assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] - end - attribute \src "ls180.v:1092.12-1092.54" - process $proc$ls180.v:1092$3499 - assign { } { } - assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] - end - attribute \src "ls180.v:1093.5-1093.41" - process $proc$ls180.v:1093$3500 - assign { } { } - assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 - sync always - sync init - update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] - end - attribute \src "ls180.v:1099.5-1099.32" - process $proc$ls180.v:1099$3501 - assign { } { } - assign $1\main_spimaster2_done[0:0] 1'0 - sync always - sync init - update \main_spimaster2_done $1\main_spimaster2_done[0:0] - end - attribute \src "ls180.v:1100.5-1100.31" - process $proc$ls180.v:1100$3502 - assign { } { } - assign $1\main_spimaster3_irq[0:0] 1'0 - sync always - sync init - update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] - end - attribute \src "ls180.v:1102.11-1102.38" - process $proc$ls180.v:1102$3503 - assign { } { } - assign $1\main_spimaster5_miso[7:0] 8'00000000 - sync always - sync init - update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] - end - attribute \src "ls180.v:1105.12-1105.47" - process $proc$ls180.v:1105$3504 - assign { } { } - assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 - sync always - update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] - sync init - end - attribute \src "ls180.v:1106.5-1106.33" - process $proc$ls180.v:1106$3505 - assign { } { } - assign $1\main_spimaster9_start[0:0] 1'0 - sync always - sync init - update \main_spimaster9_start $1\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:1108.12-1108.44" - process $proc$ls180.v:1108$3506 - assign { } { } - assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] - end - attribute \src "ls180.v:1109.5-1109.31" - process $proc$ls180.v:1109$3507 - assign { } { } - assign $1\main_spimaster12_re[0:0] 1'0 - sync always - sync init - update \main_spimaster12_re $1\main_spimaster12_re[0:0] - end - attribute \src "ls180.v:1113.11-1113.42" - process $proc$ls180.v:1113$3508 - assign { } { } - assign $1\main_spimaster16_storage[7:0] 8'00000000 - sync always - sync init - update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] - end - attribute \src "ls180.v:1114.5-1114.31" - process $proc$ls180.v:1114$3509 - assign { } { } - assign $1\main_spimaster17_re[0:0] 1'0 - sync always - sync init - update \main_spimaster17_re $1\main_spimaster17_re[0:0] - end - attribute \src "ls180.v:1118.5-1118.36" - process $proc$ls180.v:1118$3510 - assign { } { } - assign $1\main_spimaster21_storage[0:0] 1'1 - sync always - sync init - update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] - end - attribute \src "ls180.v:1119.5-1119.31" - process $proc$ls180.v:1119$3511 - assign { } { } - assign $1\main_spimaster22_re[0:0] 1'0 - sync always - sync init - update \main_spimaster22_re $1\main_spimaster22_re[0:0] - end - attribute \src "ls180.v:1120.5-1120.36" - process $proc$ls180.v:1120$3512 - assign { } { } - assign $1\main_spimaster23_storage[0:0] 1'0 - sync always - sync init - update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] - end - attribute \src "ls180.v:1121.5-1121.31" - process $proc$ls180.v:1121$3513 - assign { } { } - assign $1\main_spimaster24_re[0:0] 1'0 - sync always - sync init - update \main_spimaster24_re $1\main_spimaster24_re[0:0] - end - attribute \src "ls180.v:1122.5-1122.39" - process $proc$ls180.v:1122$3514 - assign { } { } - assign $1\main_spimaster25_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] - end - attribute \src "ls180.v:1123.5-1123.38" - process $proc$ls180.v:1123$3515 - assign { } { } - assign $1\main_spimaster26_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] - end - attribute \src "ls180.v:1124.11-1124.40" - process $proc$ls180.v:1124$3516 - assign { } { } - assign $1\main_spimaster27_count[2:0] 3'000 - sync always - sync init - update \main_spimaster27_count $1\main_spimaster27_count[2:0] - end - attribute \src "ls180.v:1125.5-1125.39" - process $proc$ls180.v:1125$3517 - assign { } { } - assign $1\main_spimaster28_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] - end - attribute \src "ls180.v:1126.5-1126.39" - process $proc$ls180.v:1126$3518 - assign { } { } - assign $1\main_spimaster29_miso_latch[0:0] 1'0 - sync always - sync init - update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] - end - attribute \src "ls180.v:1127.12-1127.48" - process $proc$ls180.v:1127$3519 - assign { } { } - assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - sync always - sync init - update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] - end - attribute \src "ls180.v:1130.11-1130.44" - process $proc$ls180.v:1130$3520 - assign { } { } - assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 - sync always - sync init - update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] - end - attribute \src "ls180.v:1131.11-1131.43" - process $proc$ls180.v:1131$3521 - assign { } { } - assign $1\main_spimaster34_mosi_sel[2:0] 3'000 - sync always - sync init - update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] - end - attribute \src "ls180.v:1132.11-1132.44" - process $proc$ls180.v:1132$3522 - assign { } { } - assign $1\main_spimaster35_miso_data[7:0] 8'00000000 - sync always - sync init - update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] - end - attribute \src "ls180.v:1135.5-1135.32" - process $proc$ls180.v:1135$3523 - assign { } { } - assign $1\main_spisdcard_done0[0:0] 1'0 - sync always - sync init - update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] - end - attribute \src "ls180.v:1136.5-1136.30" - process $proc$ls180.v:1136$3524 - assign { } { } - assign $1\main_spisdcard_irq[0:0] 1'0 - sync always - sync init - update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] - end - attribute \src "ls180.v:1138.11-1138.37" - process $proc$ls180.v:1138$3525 - assign { } { } - assign $1\main_spisdcard_miso[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] - end - attribute \src "ls180.v:114.11-114.55" - process $proc$ls180.v:114$3148 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 - sync always - update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] - sync init - end - attribute \src "ls180.v:1142.5-1142.33" - process $proc$ls180.v:1142$3526 - assign { } { } - assign $1\main_spisdcard_start1[0:0] 1'0 - sync always - sync init - update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] - end - attribute \src "ls180.v:1144.12-1144.50" - process $proc$ls180.v:1144$3527 - assign { } { } - assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] - end - attribute \src "ls180.v:1145.5-1145.37" - process $proc$ls180.v:1145$3528 - assign { } { } - assign $1\main_spisdcard_control_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] - end - attribute \src "ls180.v:1149.11-1149.45" - process $proc$ls180.v:1149$3529 - assign { } { } - assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] - end - attribute \src "ls180.v:115.11-115.55" - process $proc$ls180.v:115$3149 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 - sync always - update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] - sync init - end - attribute \src "ls180.v:1150.5-1150.34" - process $proc$ls180.v:1150$3530 - assign { } { } - assign $1\main_spisdcard_mosi_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] - end - attribute \src "ls180.v:1154.5-1154.37" - process $proc$ls180.v:1154$3531 - assign { } { } - assign $1\main_spisdcard_cs_storage[0:0] 1'1 - sync always - sync init - update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] - end - attribute \src "ls180.v:1155.5-1155.32" - process $proc$ls180.v:1155$3532 - assign { } { } - assign $1\main_spisdcard_cs_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] - end - attribute \src "ls180.v:1156.5-1156.43" - process $proc$ls180.v:1156$3533 - assign { } { } - assign $1\main_spisdcard_loopback_storage[0:0] 1'0 - sync always - sync init - update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] - end - attribute \src "ls180.v:1157.5-1157.38" - process $proc$ls180.v:1157$3534 - assign { } { } - assign $1\main_spisdcard_loopback_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] - end - attribute \src "ls180.v:1158.5-1158.37" - process $proc$ls180.v:1158$3535 - assign { } { } - assign $1\main_spisdcard_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] - end - attribute \src "ls180.v:1159.5-1159.36" - process $proc$ls180.v:1159$3536 - assign { } { } - assign $1\main_spisdcard_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] - end - attribute \src "ls180.v:1160.11-1160.38" - process $proc$ls180.v:1160$3537 - assign { } { } - assign $1\main_spisdcard_count[2:0] 3'000 - sync always - sync init - update \main_spisdcard_count $1\main_spisdcard_count[2:0] - end - attribute \src "ls180.v:1161.5-1161.37" - process $proc$ls180.v:1161$3538 - assign { } { } - assign $1\main_spisdcard_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] - end - attribute \src "ls180.v:1162.5-1162.37" - process $proc$ls180.v:1162$3539 - assign { } { } - assign $1\main_spisdcard_miso_latch[0:0] 1'0 - sync always - sync init - update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] - end - attribute \src "ls180.v:1163.12-1163.47" - process $proc$ls180.v:1163$3540 - assign { } { } - assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - sync always - sync init - update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] - end - attribute \src "ls180.v:1166.11-1166.42" - process $proc$ls180.v:1166$3541 - assign { } { } - assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] - end - attribute \src "ls180.v:1167.11-1167.41" - process $proc$ls180.v:1167$3542 - assign { } { } - assign $1\main_spisdcard_mosi_sel[2:0] 3'000 - sync always - sync init - update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] - end - attribute \src "ls180.v:1168.11-1168.42" - process $proc$ls180.v:1168$3543 - assign { } { } - assign $1\main_spisdcard_miso_data[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] - end - attribute \src "ls180.v:1169.12-1169.45" - process $proc$ls180.v:1169$3544 - assign { } { } - assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 - sync always - sync init - update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] - end - attribute \src "ls180.v:1170.5-1170.30" - process $proc$ls180.v:1170$3545 - assign { } { } - assign $1\main_spimaster1_re[0:0] 1'0 - sync always - sync init - update \main_spimaster1_re $1\main_spimaster1_re[0:0] - end - attribute \src "ls180.v:1172.12-1172.30" - process $proc$ls180.v:1172$3546 - assign { } { } - assign $1\main_dummy[23:0] 24'000000000000000000000000 - sync always - sync init - update \main_dummy $1\main_dummy[23:0] - end - attribute \src "ls180.v:1176.12-1176.37" - process $proc$ls180.v:1176$3547 - assign { } { } - assign $1\main_pwm0_counter[31:0] 0 - sync always - sync init - update \main_pwm0_counter $1\main_pwm0_counter[31:0] - end - attribute \src "ls180.v:1177.5-1177.36" - process $proc$ls180.v:1177$3548 - assign { } { } - assign $1\main_pwm0_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] - end - attribute \src "ls180.v:1178.5-1178.31" - process $proc$ls180.v:1178$3549 - assign { } { } - assign $1\main_pwm0_enable_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] - end - attribute \src "ls180.v:1179.12-1179.43" - process $proc$ls180.v:1179$3550 - assign { } { } - assign $1\main_pwm0_width_storage[31:0] 0 - sync always - sync init - update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] - end - attribute \src "ls180.v:1180.5-1180.30" - process $proc$ls180.v:1180$3551 - assign { } { } - assign $1\main_pwm0_width_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] - end - attribute \src "ls180.v:1181.12-1181.44" - process $proc$ls180.v:1181$3552 - assign { } { } - assign $1\main_pwm0_period_storage[31:0] 0 - sync always - sync init - update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] - end - attribute \src "ls180.v:1182.5-1182.31" - process $proc$ls180.v:1182$3553 - assign { } { } - assign $1\main_pwm0_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] - end - attribute \src "ls180.v:1186.12-1186.37" - process $proc$ls180.v:1186$3554 - assign { } { } - assign $1\main_pwm1_counter[31:0] 0 - sync always - sync init - update \main_pwm1_counter $1\main_pwm1_counter[31:0] - end - attribute \src "ls180.v:1187.5-1187.36" - process $proc$ls180.v:1187$3555 - assign { } { } - assign $1\main_pwm1_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] - end - attribute \src "ls180.v:1188.5-1188.31" - process $proc$ls180.v:1188$3556 - assign { } { } - assign $1\main_pwm1_enable_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] - end - attribute \src "ls180.v:1189.12-1189.43" - process $proc$ls180.v:1189$3557 - assign { } { } - assign $1\main_pwm1_width_storage[31:0] 0 - sync always - sync init - update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] - end - attribute \src "ls180.v:1190.5-1190.30" - process $proc$ls180.v:1190$3558 - assign { } { } - assign $1\main_pwm1_width_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] - end - attribute \src "ls180.v:1191.12-1191.44" - process $proc$ls180.v:1191$3559 - assign { } { } - assign $1\main_pwm1_period_storage[31:0] 0 - sync always - sync init - update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] - end - attribute \src "ls180.v:1192.5-1192.31" - process $proc$ls180.v:1192$3560 - assign { } { } - assign $1\main_pwm1_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] - end - attribute \src "ls180.v:1196.11-1196.34" - process $proc$ls180.v:1196$3561 - assign { } { } - assign $1\main_i2c_storage[2:0] 3'000 - sync always - sync init - update \main_i2c_storage $1\main_i2c_storage[2:0] - end - attribute \src "ls180.v:1197.5-1197.23" - process $proc$ls180.v:1197$3562 - assign { } { } - assign $1\main_i2c_re[0:0] 1'0 - sync always - sync init - update \main_i2c_re $1\main_i2c_re[0:0] - end - attribute \src "ls180.v:1203.11-1203.46" - process $proc$ls180.v:1203$3563 - assign { } { } - assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 - sync always - sync init - update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] - end - attribute \src "ls180.v:1204.5-1204.33" - process $proc$ls180.v:1204$3564 - assign { } { } - assign $1\main_sdphy_clocker_re[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] - end - attribute \src "ls180.v:1206.5-1206.35" - process $proc$ls180.v:1206$3565 - assign { } { } - assign $1\main_sdphy_clocker_clk0[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] - end - attribute \src "ls180.v:1208.11-1208.41" - process $proc$ls180.v:1208$3566 - assign { } { } - assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 - sync always - sync init - update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] - end - attribute \src "ls180.v:1209.5-1209.35" - process $proc$ls180.v:1209$3567 - assign { } { } - assign $1\main_sdphy_clocker_clk1[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] - end - attribute \src "ls180.v:1210.5-1210.36" - process $proc$ls180.v:1210$3568 - assign { } { } - assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] - end - attribute \src "ls180.v:1214.5-1214.40" - process $proc$ls180.v:1214$3569 - assign { } { } - assign $0\main_sdphy_init_initialize_w[0:0] 1'0 - sync always - update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] - sync init - end - attribute \src "ls180.v:1219.5-1219.48" - process $proc$ls180.v:1219$3570 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1220.5-1220.50" - process $proc$ls180.v:1220$3571 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1221.5-1221.51" - process $proc$ls180.v:1221$3572 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1222.11-1222.57" - process $proc$ls180.v:1222$3573 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1223.5-1223.52" - process $proc$ls180.v:1223$3574 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1224.11-1224.39" - process $proc$ls180.v:1224$3575 - assign { } { } - assign $1\main_sdphy_init_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] - end - attribute \src "ls180.v:1229.5-1229.48" - process $proc$ls180.v:1229$3576 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1230.5-1230.50" - process $proc$ls180.v:1230$3577 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1231.5-1231.51" - process $proc$ls180.v:1231$3578 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1232.11-1232.57" - process $proc$ls180.v:1232$3579 - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1233.5-1233.52" - process $proc$ls180.v:1233$3580 - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1234.5-1234.38" - process $proc$ls180.v:1234$3581 - assign { } { } - assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] - end - attribute \src "ls180.v:1235.5-1235.38" - process $proc$ls180.v:1235$3582 - assign { } { } - assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] - end - attribute \src "ls180.v:1236.5-1236.37" - process $proc$ls180.v:1236$3583 - assign { } { } - assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] - end - attribute \src "ls180.v:1237.11-1237.51" - process $proc$ls180.v:1237$3584 - assign { } { } - assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1238.5-1238.32" - process $proc$ls180.v:1238$3585 - assign { } { } - assign $1\main_sdphy_cmdw_done[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] - end - attribute \src "ls180.v:1239.11-1239.39" - process $proc$ls180.v:1239$3586 - assign { } { } - assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] - end - attribute \src "ls180.v:1242.5-1242.49" - process $proc$ls180.v:1242$3587 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1243.5-1243.48" - process $proc$ls180.v:1243$3588 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1244.5-1244.55" - process $proc$ls180.v:1244$3589 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1246.5-1246.57" - process $proc$ls180.v:1246$3590 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1247.5-1247.58" - process $proc$ls180.v:1247$3591 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1249.11-1249.64" - process $proc$ls180.v:1249$3592 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1250.5-1250.59" - process $proc$ls180.v:1250$3593 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1252.5-1252.48" - process $proc$ls180.v:1252$3594 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1253.5-1253.50" - process $proc$ls180.v:1253$3595 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1254.5-1254.51" - process $proc$ls180.v:1254$3596 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1255.11-1255.57" - process $proc$ls180.v:1255$3597 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1256.5-1256.52" - process $proc$ls180.v:1256$3598 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1257.5-1257.38" - process $proc$ls180.v:1257$3599 - assign { } { } - assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] - end - attribute \src "ls180.v:1258.5-1258.38" - process $proc$ls180.v:1258$3600 - assign { } { } - assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] - end - attribute \src "ls180.v:1259.5-1259.37" - process $proc$ls180.v:1259$3601 - assign { } { } - assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] - end - attribute \src "ls180.v:1260.11-1260.53" - process $proc$ls180.v:1260$3602 - assign { } { } - assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] - end - attribute \src "ls180.v:1261.5-1261.40" - process $proc$ls180.v:1261$3603 - assign { } { } - assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] - end - attribute \src "ls180.v:1262.5-1262.40" - process $proc$ls180.v:1262$3604 - assign { } { } - assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] - end - attribute \src "ls180.v:1263.5-1263.39" - process $proc$ls180.v:1263$3605 - assign { } { } - assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] - end - attribute \src "ls180.v:1264.11-1264.53" - process $proc$ls180.v:1264$3606 - assign { } { } - assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] - end - attribute \src "ls180.v:1265.11-1265.55" - process $proc$ls180.v:1265$3607 - assign { } { } - assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - sync always - sync init - update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] - end - attribute \src "ls180.v:1266.12-1266.48" - process $proc$ls180.v:1266$3608 - assign { } { } - assign $1\main_sdphy_cmdr_timeout[31:0] 500000 - sync always - sync init - update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] - end - attribute \src "ls180.v:1267.11-1267.39" - process $proc$ls180.v:1267$3609 - assign { } { } - assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] - end - attribute \src "ls180.v:1269.5-1269.46" - process $proc$ls180.v:1269$3610 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1280.5-1280.53" - process $proc$ls180.v:1280$3611 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1285.5-1285.36" - process $proc$ls180.v:1285$3612 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] - end - attribute \src "ls180.v:1288.5-1288.53" - process $proc$ls180.v:1288$3613 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1289.5-1289.52" - process $proc$ls180.v:1289$3614 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1293.5-1293.55" - process $proc$ls180.v:1293$3615 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - end - attribute \src "ls180.v:1294.5-1294.54" - process $proc$ls180.v:1294$3616 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - end - attribute \src "ls180.v:1295.11-1295.68" - process $proc$ls180.v:1295$3617 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1296.11-1296.81" - process $proc$ls180.v:1296$3618 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1297.11-1297.54" - process $proc$ls180.v:1297$3619 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - end - attribute \src "ls180.v:1299.5-1299.53" - process $proc$ls180.v:1299$3620 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1310.5-1310.49" - process $proc$ls180.v:1310$3621 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1312.5-1312.49" - process $proc$ls180.v:1312$3622 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - end - attribute \src "ls180.v:1313.5-1313.48" - process $proc$ls180.v:1313$3623 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - end - attribute \src "ls180.v:1314.11-1314.62" - process $proc$ls180.v:1314$3624 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1315.5-1315.38" - process $proc$ls180.v:1315$3625 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] - end - attribute \src "ls180.v:1320.5-1320.49" - process $proc$ls180.v:1320$3626 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1321.5-1321.51" - process $proc$ls180.v:1321$3627 - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1322.5-1322.52" - process $proc$ls180.v:1322$3628 - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1323.11-1323.58" - process $proc$ls180.v:1323$3629 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1324.5-1324.53" - process $proc$ls180.v:1324$3630 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1325.5-1325.39" - process $proc$ls180.v:1325$3631 - assign { } { } - assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] - end - attribute \src "ls180.v:1326.5-1326.39" - process $proc$ls180.v:1326$3632 - assign { } { } - assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] - end - attribute \src "ls180.v:1327.5-1327.39" - process $proc$ls180.v:1327$3633 - assign { } { } - assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] - end - attribute \src "ls180.v:1328.5-1328.38" - process $proc$ls180.v:1328$3634 - assign { } { } - assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] - end - attribute \src "ls180.v:1329.11-1329.52" - process $proc$ls180.v:1329$3635 - assign { } { } - assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1330.5-1330.33" - process $proc$ls180.v:1330$3636 - assign { } { } - assign $1\main_sdphy_dataw_stop[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] - end - attribute \src "ls180.v:1331.11-1331.40" - process $proc$ls180.v:1331$3637 - assign { } { } - assign $1\main_sdphy_dataw_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] - end - attribute \src "ls180.v:1332.5-1332.50" - process $proc$ls180.v:1332$3638 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - sync init - end - attribute \src "ls180.v:1334.5-1334.50" - process $proc$ls180.v:1334$3639 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1335.5-1335.49" - process $proc$ls180.v:1335$3640 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1336.5-1336.56" - process $proc$ls180.v:1336$3641 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1337.5-1337.58" - process $proc$ls180.v:1337$3642 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - sync init - end - attribute \src "ls180.v:1338.5-1338.58" - process $proc$ls180.v:1338$3643 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1339.5-1339.59" - process $proc$ls180.v:1339$3644 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1340.11-1340.65" - process $proc$ls180.v:1340$3645 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - sync init - end - attribute \src "ls180.v:1341.11-1341.65" - process $proc$ls180.v:1341$3646 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1342.5-1342.60" - process $proc$ls180.v:1342$3647 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1343.5-1343.34" - process $proc$ls180.v:1343$3648 - assign { } { } - assign $1\main_sdphy_dataw_start[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] - end - attribute \src "ls180.v:1344.5-1344.34" - process $proc$ls180.v:1344$3649 - assign { } { } - assign $1\main_sdphy_dataw_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] - end - attribute \src "ls180.v:1345.5-1345.34" - process $proc$ls180.v:1345$3650 - assign { } { } - assign $1\main_sdphy_dataw_error[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] - end - attribute \src "ls180.v:1347.5-1347.47" - process $proc$ls180.v:1347$3651 - assign { } { } - assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1358.5-1358.54" - process $proc$ls180.v:1358$3652 - assign { } { } - assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1363.5-1363.37" - process $proc$ls180.v:1363$3653 - assign { } { } - assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] - end - attribute \src "ls180.v:1366.5-1366.54" - process $proc$ls180.v:1366$3654 - assign { } { } - assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1367.5-1367.53" - process $proc$ls180.v:1367$3655 - assign { } { } - assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1371.5-1371.56" - process $proc$ls180.v:1371$3656 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - end - attribute \src "ls180.v:1372.5-1372.55" - process $proc$ls180.v:1372$3657 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - end - attribute \src "ls180.v:1373.11-1373.69" - process $proc$ls180.v:1373$3658 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1374.11-1374.82" - process $proc$ls180.v:1374$3659 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1375.11-1375.55" - process $proc$ls180.v:1375$3660 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] - end - attribute \src "ls180.v:1377.5-1377.54" - process $proc$ls180.v:1377$3661 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1388.5-1388.50" - process $proc$ls180.v:1388$3662 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1390.5-1390.50" - process $proc$ls180.v:1390$3663 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - end - attribute \src "ls180.v:1391.5-1391.49" - process $proc$ls180.v:1391$3664 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - end - attribute \src "ls180.v:1392.11-1392.63" - process $proc$ls180.v:1392$3665 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1393.5-1393.39" - process $proc$ls180.v:1393$3666 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] - end - attribute \src "ls180.v:1396.5-1396.50" - process $proc$ls180.v:1396$3667 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1397.5-1397.49" - process $proc$ls180.v:1397$3668 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1398.5-1398.56" - process $proc$ls180.v:1398$3669 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1400.5-1400.58" - process $proc$ls180.v:1400$3670 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1401.5-1401.59" - process $proc$ls180.v:1401$3671 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1403.11-1403.65" - process $proc$ls180.v:1403$3672 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1404.5-1404.60" - process $proc$ls180.v:1404$3673 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1406.5-1406.49" - process $proc$ls180.v:1406$3674 - assign { } { } - assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1407.5-1407.51" - process $proc$ls180.v:1407$3675 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1408.5-1408.52" - process $proc$ls180.v:1408$3676 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1409.11-1409.58" - process $proc$ls180.v:1409$3677 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1410.5-1410.53" - process $proc$ls180.v:1410$3678 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1411.5-1411.39" - process $proc$ls180.v:1411$3679 - assign { } { } - assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] - end - attribute \src "ls180.v:1412.5-1412.39" - process $proc$ls180.v:1412$3680 - assign { } { } - assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] - end - attribute \src "ls180.v:1413.5-1413.38" - process $proc$ls180.v:1413$3681 - assign { } { } - assign $1\main_sdphy_datar_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] - end - attribute \src "ls180.v:1414.11-1414.61" - process $proc$ls180.v:1414$3682 - assign { } { } - assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] - end - attribute \src "ls180.v:1415.5-1415.41" - process $proc$ls180.v:1415$3683 - assign { } { } - assign $1\main_sdphy_datar_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] - end - attribute \src "ls180.v:1416.5-1416.41" - process $proc$ls180.v:1416$3684 - assign { } { } - assign $1\main_sdphy_datar_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] - end - attribute \src "ls180.v:1417.5-1417.41" - process $proc$ls180.v:1417$3685 - assign { } { } - assign $0\main_sdphy_datar_source_first[0:0] 1'0 - sync always - update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] - sync init - end - attribute \src "ls180.v:1418.5-1418.40" - process $proc$ls180.v:1418$3686 - assign { } { } - assign $1\main_sdphy_datar_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] - end - attribute \src "ls180.v:1419.11-1419.54" - process $proc$ls180.v:1419$3687 - assign { } { } - assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] - end - attribute \src "ls180.v:1420.11-1420.56" - process $proc$ls180.v:1420$3688 - assign { } { } - assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 - sync always - sync init - update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] - end - attribute \src "ls180.v:1421.5-1421.33" - process $proc$ls180.v:1421$3689 - assign { } { } - assign $1\main_sdphy_datar_stop[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] - end - attribute \src "ls180.v:1422.12-1422.49" - process $proc$ls180.v:1422$3690 - assign { } { } - assign $1\main_sdphy_datar_timeout[31:0] 500000 - sync always - sync init - update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] - end - attribute \src "ls180.v:1423.11-1423.41" - process $proc$ls180.v:1423$3691 - assign { } { } - assign $1\main_sdphy_datar_count[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] - end - attribute \src "ls180.v:1425.5-1425.48" - process $proc$ls180.v:1425$3692 - assign { } { } - assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1436.5-1436.55" - process $proc$ls180.v:1436$3693 - assign { } { } - assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] - end - attribute \src "ls180.v:1441.5-1441.38" - process $proc$ls180.v:1441$3694 - assign { } { } - assign $1\main_sdphy_datar_datar_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] - end - attribute \src "ls180.v:1444.5-1444.55" - process $proc$ls180.v:1444$3695 - assign { } { } - assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1445.5-1445.54" - process $proc$ls180.v:1445$3696 - assign { } { } - assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1449.5-1449.57" - process $proc$ls180.v:1449$3697 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] - end - attribute \src "ls180.v:1450.5-1450.56" - process $proc$ls180.v:1450$3698 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] - end - attribute \src "ls180.v:1451.11-1451.70" - process $proc$ls180.v:1451$3699 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1452.11-1452.83" - process $proc$ls180.v:1452$3700 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - end - attribute \src "ls180.v:1453.5-1453.50" - process $proc$ls180.v:1453$3701 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] - end - attribute \src "ls180.v:1455.5-1455.55" - process $proc$ls180.v:1455$3702 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1466.5-1466.51" - process $proc$ls180.v:1466$3703 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] - end - attribute \src "ls180.v:1468.5-1468.51" - process $proc$ls180.v:1468$3704 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] - end - attribute \src "ls180.v:1469.5-1469.50" - process $proc$ls180.v:1469$3705 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] - end - attribute \src "ls180.v:1470.11-1470.64" - process $proc$ls180.v:1470$3706 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1471.5-1471.40" - process $proc$ls180.v:1471$3707 - assign { } { } - assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] - end - attribute \src "ls180.v:1473.5-1473.35" - process $proc$ls180.v:1473$3708 - assign { } { } - assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 - sync always - sync init - update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] - end - attribute \src "ls180.v:1476.11-1476.42" - process $proc$ls180.v:1476$3709 - assign { } { } - assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 - sync always - sync init - update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] - end - attribute \src "ls180.v:1489.12-1489.52" - process $proc$ls180.v:1489$3710 - assign { } { } - assign $1\main_sdcore_cmd_argument_storage[31:0] 0 - sync always - sync init - update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] - end - attribute \src "ls180.v:1490.5-1490.39" - process $proc$ls180.v:1490$3711 - assign { } { } - assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] - end - attribute \src "ls180.v:1491.12-1491.51" - process $proc$ls180.v:1491$3712 - assign { } { } - assign $1\main_sdcore_cmd_command_storage[31:0] 0 - sync always - sync init - update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] - end - attribute \src "ls180.v:1492.5-1492.38" - process $proc$ls180.v:1492$3713 - assign { } { } - assign $1\main_sdcore_cmd_command_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] - end - attribute \src "ls180.v:1496.5-1496.34" - process $proc$ls180.v:1496$3714 - assign { } { } - assign $0\main_sdcore_cmd_send_w[0:0] 1'0 - sync always - update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] - sync init - end - attribute \src "ls180.v:1497.13-1497.53" - process $proc$ls180.v:1497$3715 - assign { } { } - assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] - end - attribute \src "ls180.v:1503.11-1503.51" - process $proc$ls180.v:1503$3716 - assign { } { } - assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 - sync always - sync init - update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] - end - attribute \src "ls180.v:1504.5-1504.39" - process $proc$ls180.v:1504$3717 - assign { } { } - assign $1\main_sdcore_block_length_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] - end - attribute \src "ls180.v:1505.12-1505.51" - process $proc$ls180.v:1505$3718 - assign { } { } - assign $1\main_sdcore_block_count_storage[31:0] 0 - sync always - sync init - update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] - end - attribute \src "ls180.v:1506.5-1506.38" - process $proc$ls180.v:1506$3719 - assign { } { } - assign $1\main_sdcore_block_count_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] - end - attribute \src "ls180.v:1507.11-1507.51" - process $proc$ls180.v:1507$3720 - assign { } { } - assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - sync always - sync init - update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - end - attribute \src "ls180.v:1549.11-1549.47" - process $proc$ls180.v:1549$3721 - assign { } { } - assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - sync always - sync init - update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:1553.5-1553.49" - process $proc$ls180.v:1553$3722 - assign { } { } - assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] - end - attribute \src "ls180.v:1557.5-1557.51" - process $proc$ls180.v:1557$3723 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] - end - attribute \src "ls180.v:1558.5-1558.51" - process $proc$ls180.v:1558$3724 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] - end - attribute \src "ls180.v:1559.5-1559.51" - process $proc$ls180.v:1559$3725 - assign { } { } - assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 - sync always - update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] - sync init - end - attribute \src "ls180.v:1560.5-1560.50" - process $proc$ls180.v:1560$3726 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] - end - attribute \src "ls180.v:1561.11-1561.64" - process $proc$ls180.v:1561$3727 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - end - attribute \src "ls180.v:1562.11-1562.48" - process $proc$ls180.v:1562$3728 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] - end - attribute \src "ls180.v:1563.12-1563.59" - process $proc$ls180.v:1563$3729 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1567.12-1567.55" - process $proc$ls180.v:1567$3730 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:1570.12-1570.59" - process $proc$ls180.v:1570$3731 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1574.12-1574.55" - process $proc$ls180.v:1574$3732 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:1577.12-1577.59" - process $proc$ls180.v:1577$3733 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1581.12-1581.55" - process $proc$ls180.v:1581$3734 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:1584.12-1584.59" - process $proc$ls180.v:1584$3735 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:1588.12-1588.55" - process $proc$ls180.v:1588$3736 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:1591.12-1591.54" - process $proc$ls180.v:1591$3737 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - end - attribute \src "ls180.v:1592.12-1592.54" - process $proc$ls180.v:1592$3738 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - end - attribute \src "ls180.v:1593.12-1593.54" - process $proc$ls180.v:1593$3739 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - end - attribute \src "ls180.v:1594.12-1594.54" - process $proc$ls180.v:1594$3740 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - end - attribute \src "ls180.v:1595.5-1595.48" - process $proc$ls180.v:1595$3741 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] - end - attribute \src "ls180.v:1596.5-1596.48" - process $proc$ls180.v:1596$3742 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] - end - attribute \src "ls180.v:1597.5-1597.48" - process $proc$ls180.v:1597$3743 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] - end - attribute \src "ls180.v:1598.5-1598.47" - process $proc$ls180.v:1598$3744 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] - end - attribute \src "ls180.v:1599.11-1599.61" - process $proc$ls180.v:1599$3745 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - end - attribute \src "ls180.v:1600.5-1600.50" - process $proc$ls180.v:1600$3746 - assign { } { } - assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] - end - attribute \src "ls180.v:1602.5-1602.50" - process $proc$ls180.v:1602$3747 - assign { } { } - assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 - sync always - update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] - sync init - end - attribute \src "ls180.v:1605.11-1605.47" - process $proc$ls180.v:1605$3748 - assign { } { } - assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] - end - attribute \src "ls180.v:1606.11-1606.47" - process $proc$ls180.v:1606$3749 - assign { } { } - assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - sync always - sync init - update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] - end - attribute \src "ls180.v:1607.12-1607.58" - process $proc$ls180.v:1607$3750 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1611.12-1611.54" - process $proc$ls180.v:1611$3751 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:1612.5-1612.46" - process $proc$ls180.v:1612$3752 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] - end - attribute \src "ls180.v:1614.12-1614.58" - process $proc$ls180.v:1614$3753 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1618.12-1618.54" - process $proc$ls180.v:1618$3754 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] - end - attribute \src "ls180.v:1619.5-1619.46" - process $proc$ls180.v:1619$3755 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] - end - attribute \src "ls180.v:1621.12-1621.58" - process $proc$ls180.v:1621$3756 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1625.12-1625.54" - process $proc$ls180.v:1625$3757 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] - end - attribute \src "ls180.v:1626.5-1626.46" - process $proc$ls180.v:1626$3758 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] - end - attribute \src "ls180.v:1628.12-1628.58" - process $proc$ls180.v:1628$3759 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:1632.12-1632.54" - process $proc$ls180.v:1632$3760 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] - end - attribute \src "ls180.v:1633.5-1633.46" - process $proc$ls180.v:1633$3761 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] - end - attribute \src "ls180.v:1635.12-1635.53" - process $proc$ls180.v:1635$3762 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] - end - attribute \src "ls180.v:1636.12-1636.53" - process $proc$ls180.v:1636$3763 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] - end - attribute \src "ls180.v:1637.12-1637.53" - process $proc$ls180.v:1637$3764 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] - end - attribute \src "ls180.v:1638.12-1638.53" - process $proc$ls180.v:1638$3765 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] - end - attribute \src "ls180.v:1639.5-1639.43" - process $proc$ls180.v:1639$3766 - assign { } { } - assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] - end - attribute \src "ls180.v:1640.12-1640.51" - process $proc$ls180.v:1640$3767 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] - end - attribute \src "ls180.v:1641.12-1641.51" - process $proc$ls180.v:1641$3768 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] - end - attribute \src "ls180.v:1642.12-1642.51" - process $proc$ls180.v:1642$3769 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] - end - attribute \src "ls180.v:1643.12-1643.51" - process $proc$ls180.v:1643$3770 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] - end - attribute \src "ls180.v:1645.11-1645.39" - process $proc$ls180.v:1645$3771 - assign { } { } - assign $1\main_sdcore_cmd_count[2:0] 3'000 - sync always - sync init - update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] - end - attribute \src "ls180.v:1646.5-1646.32" - process $proc$ls180.v:1646$3772 - assign { } { } - assign $1\main_sdcore_cmd_done[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] - end - attribute \src "ls180.v:1647.5-1647.33" - process $proc$ls180.v:1647$3773 - assign { } { } - assign $1\main_sdcore_cmd_error[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] - end - attribute \src "ls180.v:1648.5-1648.35" - process $proc$ls180.v:1648$3774 - assign { } { } - assign $1\main_sdcore_cmd_timeout[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] - end - attribute \src "ls180.v:1650.12-1650.42" - process $proc$ls180.v:1650$3775 - assign { } { } - assign $1\main_sdcore_data_count[31:0] 0 - sync always - sync init - update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] - end - attribute \src "ls180.v:1651.5-1651.33" - process $proc$ls180.v:1651$3776 - assign { } { } - assign $1\main_sdcore_data_done[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] - end - attribute \src "ls180.v:1652.5-1652.34" - process $proc$ls180.v:1652$3777 - assign { } { } - assign $1\main_sdcore_data_error[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] - end - attribute \src "ls180.v:1653.5-1653.36" - process $proc$ls180.v:1653$3778 - assign { } { } - assign $1\main_sdcore_data_timeout[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] - end - attribute \src "ls180.v:1662.11-1662.41" - process $proc$ls180.v:1662$3779 - assign { } { } - assign $0\main_interface0_bus_cti[2:0] 3'000 - sync always - update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1663.11-1663.41" - process $proc$ls180.v:1663$3780 - assign { } { } - assign $0\main_interface0_bus_bte[1:0] 2'00 - sync always - update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:1686.11-1686.45" - process $proc$ls180.v:1686$3781 - assign { } { } - assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 - sync always - sync init - update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] - end - attribute \src "ls180.v:1687.5-1687.41" - process $proc$ls180.v:1687$3782 - assign { } { } - assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 - sync always - update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1688.11-1688.47" - process $proc$ls180.v:1688$3783 - assign { } { } - assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] - end - attribute \src "ls180.v:1689.11-1689.47" - process $proc$ls180.v:1689$3784 - assign { } { } - assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] - end - attribute \src "ls180.v:1690.11-1690.50" - process $proc$ls180.v:1690$3785 - assign { } { } - assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:1710.5-1710.51" - process $proc$ls180.v:1710$3786 - assign { } { } - assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] - end - attribute \src "ls180.v:1711.5-1711.50" - process $proc$ls180.v:1711$3787 - assign { } { } - assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] - end - attribute \src "ls180.v:1712.12-1712.66" - process $proc$ls180.v:1712$3788 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] - end - attribute \src "ls180.v:1713.11-1713.77" - process $proc$ls180.v:1713$3789 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1714.11-1714.50" - process $proc$ls180.v:1714$3790 - assign { } { } - assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] - end - attribute \src "ls180.v:1716.5-1716.49" - process $proc$ls180.v:1716$3791 - assign { } { } - assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1722.5-1722.45" - process $proc$ls180.v:1722$3792 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] - end - attribute \src "ls180.v:1724.12-1724.62" - process $proc$ls180.v:1724$3793 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - sync always - sync init - update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] - end - attribute \src "ls180.v:1725.12-1725.60" - process $proc$ls180.v:1725$3794 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] - end - attribute \src "ls180.v:1727.5-1727.57" - process $proc$ls180.v:1727$3795 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - end - attribute \src "ls180.v:1731.12-1731.67" - process $proc$ls180.v:1731$3796 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - end - attribute \src "ls180.v:1732.5-1732.54" - process $proc$ls180.v:1732$3797 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - end - attribute \src "ls180.v:1733.12-1733.69" - process $proc$ls180.v:1733$3798 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - end - attribute \src "ls180.v:1734.5-1734.56" - process $proc$ls180.v:1734$3799 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - end - attribute \src "ls180.v:1735.5-1735.61" - process $proc$ls180.v:1735$3800 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - end - attribute \src "ls180.v:1736.5-1736.56" - process $proc$ls180.v:1736$3801 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - end - attribute \src "ls180.v:1737.5-1737.53" - process $proc$ls180.v:1737$3802 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - end - attribute \src "ls180.v:1739.5-1739.59" - process $proc$ls180.v:1739$3803 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - end - attribute \src "ls180.v:1740.5-1740.54" - process $proc$ls180.v:1740$3804 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - end - attribute \src "ls180.v:1742.12-1742.61" - process $proc$ls180.v:1742$3805 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - end - attribute \src "ls180.v:1745.12-1745.43" - process $proc$ls180.v:1745$3806 - assign { } { } - assign $1\main_interface1_bus_adr[31:0] 0 - sync always - sync init - update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] - end - attribute \src "ls180.v:1746.12-1746.45" - process $proc$ls180.v:1746$3807 - assign { } { } - assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] - sync init - end - attribute \src "ls180.v:1748.11-1748.41" - process $proc$ls180.v:1748$3808 - assign { } { } - assign $1\main_interface1_bus_sel[7:0] 8'00000000 - sync always - sync init - update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] - end - attribute \src "ls180.v:1749.5-1749.35" - process $proc$ls180.v:1749$3809 - assign { } { } - assign $1\main_interface1_bus_cyc[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] - end - attribute \src "ls180.v:1750.5-1750.35" - process $proc$ls180.v:1750$3810 - assign { } { } - assign $1\main_interface1_bus_stb[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] - end - attribute \src "ls180.v:1752.5-1752.34" - process $proc$ls180.v:1752$3811 - assign { } { } - assign $1\main_interface1_bus_we[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] - end - attribute \src "ls180.v:1753.11-1753.41" - process $proc$ls180.v:1753$3812 - assign { } { } - assign $0\main_interface1_bus_cti[2:0] 3'000 - sync always - update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1754.11-1754.41" - process $proc$ls180.v:1754$3813 - assign { } { } - assign $0\main_interface1_bus_bte[1:0] 2'00 - sync always - update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:1761.5-1761.43" - process $proc$ls180.v:1761$3814 - assign { } { } - assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] - end - attribute \src "ls180.v:1762.5-1762.43" - process $proc$ls180.v:1762$3815 - assign { } { } - assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] - end - attribute \src "ls180.v:1763.5-1763.42" - process $proc$ls180.v:1763$3816 - assign { } { } - assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] - end - attribute \src "ls180.v:1764.12-1764.61" - process $proc$ls180.v:1764$3817 - assign { } { } - assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] - end - attribute \src "ls180.v:1765.5-1765.45" - process $proc$ls180.v:1765$3818 - assign { } { } - assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] - end - attribute \src "ls180.v:1767.5-1767.45" - process $proc$ls180.v:1767$3819 - assign { } { } - assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 - sync always - update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] - sync init - end - attribute \src "ls180.v:1768.5-1768.44" - process $proc$ls180.v:1768$3820 - assign { } { } - assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] - end - attribute \src "ls180.v:1769.12-1769.60" - process $proc$ls180.v:1769$3821 - assign { } { } - assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] - end - attribute \src "ls180.v:1770.12-1770.45" - process $proc$ls180.v:1770$3822 - assign { } { } - assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] - end - attribute \src "ls180.v:1771.12-1771.53" - process $proc$ls180.v:1771$3823 - assign { } { } - assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] - end - attribute \src "ls180.v:1772.5-1772.40" - process $proc$ls180.v:1772$3824 - assign { } { } - assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] - end - attribute \src "ls180.v:1773.12-1773.55" - process $proc$ls180.v:1773$3825 - assign { } { } - assign $1\main_sdmem2block_dma_length_storage[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] - end - attribute \src "ls180.v:1774.5-1774.42" - process $proc$ls180.v:1774$3826 - assign { } { } - assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] - end - attribute \src "ls180.v:1775.5-1775.47" - process $proc$ls180.v:1775$3827 - assign { } { } - assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] - end - attribute \src "ls180.v:1776.5-1776.42" - process $proc$ls180.v:1776$3828 - assign { } { } - assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] - end - attribute \src "ls180.v:1777.5-1777.44" - process $proc$ls180.v:1777$3829 - assign { } { } - assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] - end - attribute \src "ls180.v:1779.5-1779.45" - process $proc$ls180.v:1779$3830 - assign { } { } - assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] - end - attribute \src "ls180.v:1780.5-1780.40" - process $proc$ls180.v:1780$3831 - assign { } { } - assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] - end - attribute \src "ls180.v:1784.12-1784.47" - process $proc$ls180.v:1784$3832 - assign { } { } - assign $1\main_sdmem2block_dma_offset[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] - end - attribute \src "ls180.v:1796.11-1796.64" - process $proc$ls180.v:1796$3833 - assign { } { } - assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1798.11-1798.48" - process $proc$ls180.v:1798$3834 - assign { } { } - assign $1\main_sdmem2block_converter_mux[2:0] 3'000 - sync always - sync init - update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] - end - attribute \src "ls180.v:1822.11-1822.45" - process $proc$ls180.v:1822$3835 - assign { } { } - assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 - sync always - sync init - update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] - end - attribute \src "ls180.v:1823.5-1823.41" - process $proc$ls180.v:1823$3836 - assign { } { } - assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 - sync always - update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1824.11-1824.47" - process $proc$ls180.v:1824$3837 - assign { } { } - assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] - end - attribute \src "ls180.v:1825.11-1825.47" - process $proc$ls180.v:1825$3838 - assign { } { } - assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] - end - attribute \src "ls180.v:1826.11-1826.50" - process $proc$ls180.v:1826$3839 - assign { } { } - assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:1839.5-1839.36" - process $proc$ls180.v:1839$3840 - assign { } { } - assign $1\builder_converter0_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_state $1\builder_converter0_state[0:0] - end - attribute \src "ls180.v:1840.5-1840.41" - process $proc$ls180.v:1840$3841 - assign { } { } - assign $1\builder_converter0_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] - end - attribute \src "ls180.v:1841.5-1841.57" - process $proc$ls180.v:1841$3842 - assign { } { } - assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 - sync always - sync init - update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] - end - attribute \src "ls180.v:1842.5-1842.60" - process $proc$ls180.v:1842$3843 - assign { } { } - assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:1843.5-1843.36" - process $proc$ls180.v:1843$3844 - assign { } { } - assign $1\builder_converter1_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_state $1\builder_converter1_state[0:0] - end - attribute \src "ls180.v:1844.5-1844.41" - process $proc$ls180.v:1844$3845 - assign { } { } - assign $1\builder_converter1_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] - end - attribute \src "ls180.v:1845.5-1845.57" - process $proc$ls180.v:1845$3846 - assign { } { } - assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 - sync always - sync init - update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] - end - attribute \src "ls180.v:1846.5-1846.60" - process $proc$ls180.v:1846$3847 - assign { } { } - assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] - end - attribute \src "ls180.v:1847.5-1847.36" - process $proc$ls180.v:1847$3848 - assign { } { } - assign $1\builder_converter2_state[0:0] 1'0 - sync always - sync init - update \builder_converter2_state $1\builder_converter2_state[0:0] - end - attribute \src "ls180.v:1848.5-1848.41" - process $proc$ls180.v:1848$3849 - assign { } { } - assign $1\builder_converter2_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] - end - attribute \src "ls180.v:1849.5-1849.60" - process $proc$ls180.v:1849$3850 - assign { } { } - assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - sync always - sync init - update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] - end - attribute \src "ls180.v:1850.5-1850.63" - process $proc$ls180.v:1850$3851 - assign { } { } - assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] - end - attribute \src "ls180.v:1851.11-1851.41" - process $proc$ls180.v:1851$3852 - assign { } { } - assign $1\builder_refresher_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_state $1\builder_refresher_state[1:0] - end - attribute \src "ls180.v:1852.11-1852.46" - process $proc$ls180.v:1852$3853 - assign { } { } - assign $1\builder_refresher_next_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:1853.11-1853.44" - process $proc$ls180.v:1853$3854 - assign { } { } - assign $1\builder_bankmachine0_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] - end - attribute \src "ls180.v:1854.11-1854.49" - process $proc$ls180.v:1854$3855 - assign { } { } - assign $1\builder_bankmachine0_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:1855.11-1855.44" - process $proc$ls180.v:1855$3856 - assign { } { } - assign $1\builder_bankmachine1_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] - end - attribute \src "ls180.v:1856.11-1856.49" - process $proc$ls180.v:1856$3857 - assign { } { } - assign $1\builder_bankmachine1_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:1857.11-1857.44" - process $proc$ls180.v:1857$3858 - assign { } { } - assign $1\builder_bankmachine2_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] - end - attribute \src "ls180.v:1858.11-1858.49" - process $proc$ls180.v:1858$3859 - assign { } { } - assign $1\builder_bankmachine2_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:1859.11-1859.44" - process $proc$ls180.v:1859$3860 - assign { } { } - assign $1\builder_bankmachine3_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] - end - attribute \src "ls180.v:1860.11-1860.49" - process $proc$ls180.v:1860$3861 - assign { } { } - assign $1\builder_bankmachine3_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:1861.11-1861.43" - process $proc$ls180.v:1861$3862 - assign { } { } - assign $1\builder_multiplexer_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] - end - attribute \src "ls180.v:1862.11-1862.48" - process $proc$ls180.v:1862$3863 - assign { } { } - assign $1\builder_multiplexer_next_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:1875.5-1875.27" - process $proc$ls180.v:1875$3864 - assign { } { } - assign $0\builder_locked0[0:0] 1'0 - sync always - update \builder_locked0 $0\builder_locked0[0:0] - sync init - end - attribute \src "ls180.v:1876.5-1876.27" - process $proc$ls180.v:1876$3865 - assign { } { } - assign $0\builder_locked1[0:0] 1'0 - sync always - update \builder_locked1 $0\builder_locked1[0:0] - sync init - end - attribute \src "ls180.v:1877.5-1877.27" - process $proc$ls180.v:1877$3866 - assign { } { } - assign $0\builder_locked2[0:0] 1'0 - sync always - update \builder_locked2 $0\builder_locked2[0:0] - sync init - end - attribute \src "ls180.v:1878.5-1878.27" - process $proc$ls180.v:1878$3867 - assign { } { } - assign $0\builder_locked3[0:0] 1'0 - sync always - update \builder_locked3 $0\builder_locked3[0:0] - sync init - end - attribute \src "ls180.v:1879.5-1879.42" - process $proc$ls180.v:1879$3868 - assign { } { } - assign $1\builder_new_master_wdata_ready[0:0] 1'0 - sync always - sync init - update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] - end - attribute \src "ls180.v:1880.5-1880.43" - process $proc$ls180.v:1880$3869 - assign { } { } - assign $1\builder_new_master_rdata_valid0[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] - end - attribute \src "ls180.v:1881.5-1881.43" - process $proc$ls180.v:1881$3870 - assign { } { } - assign $1\builder_new_master_rdata_valid1[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] - end - attribute \src "ls180.v:1882.5-1882.43" - process $proc$ls180.v:1882$3871 - assign { } { } - assign $1\builder_new_master_rdata_valid2[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] - end - attribute \src "ls180.v:1883.5-1883.43" - process $proc$ls180.v:1883$3872 - assign { } { } - assign $1\builder_new_master_rdata_valid3[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] - end - attribute \src "ls180.v:1884.5-1884.35" - process $proc$ls180.v:1884$3873 - assign { } { } - assign $1\builder_converter_state[0:0] 1'0 - sync always - sync init - update \builder_converter_state $1\builder_converter_state[0:0] - end - attribute \src "ls180.v:1885.5-1885.40" - process $proc$ls180.v:1885$3874 - assign { } { } - assign $1\builder_converter_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter_next_state $1\builder_converter_next_state[0:0] - end - attribute \src "ls180.v:1886.5-1886.55" - process $proc$ls180.v:1886$3875 - assign { } { } - assign $1\main_converter_counter_converter_next_value[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] - end - attribute \src "ls180.v:1887.5-1887.58" - process $proc$ls180.v:1887$3876 - assign { } { } - assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:1888.11-1888.42" - process $proc$ls180.v:1888$3877 - assign { } { } - assign $1\builder_spimaster0_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] - end - attribute \src "ls180.v:1889.11-1889.47" - process $proc$ls180.v:1889$3878 - assign { } { } - assign $1\builder_spimaster0_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] - end - attribute \src "ls180.v:1890.11-1890.62" - process $proc$ls180.v:1890$3879 - assign { } { } - assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - sync always - sync init - update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] - end - attribute \src "ls180.v:1891.5-1891.59" - process $proc$ls180.v:1891$3880 - assign { } { } - assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:1892.11-1892.42" - process $proc$ls180.v:1892$3881 - assign { } { } - assign $1\builder_spimaster1_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] - end - attribute \src "ls180.v:1893.11-1893.47" - process $proc$ls180.v:1893$3882 - assign { } { } - assign $1\builder_spimaster1_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] - end - attribute \src "ls180.v:1894.11-1894.60" - process $proc$ls180.v:1894$3883 - assign { } { } - assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - sync always - sync init - update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] - end - attribute \src "ls180.v:1895.5-1895.57" - process $proc$ls180.v:1895$3884 - assign { } { } - assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:1896.5-1896.41" - process $proc$ls180.v:1896$3885 - assign { } { } - assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] - end - attribute \src "ls180.v:1897.5-1897.46" - process $proc$ls180.v:1897$3886 - assign { } { } - assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] - end - attribute \src "ls180.v:1898.11-1898.66" - process $proc$ls180.v:1898$3887 - assign { } { } - assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - end - attribute \src "ls180.v:1899.5-1899.63" - process $proc$ls180.v:1899$3888 - assign { } { } - assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - end - attribute \src "ls180.v:1900.11-1900.47" - process $proc$ls180.v:1900$3889 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] - end - attribute \src "ls180.v:1901.11-1901.52" - process $proc$ls180.v:1901$3890 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] - end - attribute \src "ls180.v:1902.11-1902.66" - process $proc$ls180.v:1902$3891 - assign { } { } - assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - end - attribute \src "ls180.v:1903.5-1903.63" - process $proc$ls180.v:1903$3892 - assign { } { } - assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:1904.11-1904.47" - process $proc$ls180.v:1904$3893 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] - end - attribute \src "ls180.v:1905.11-1905.52" - process $proc$ls180.v:1905$3894 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] - end - attribute \src "ls180.v:1906.11-1906.67" - process $proc$ls180.v:1906$3895 - assign { } { } - assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - end - attribute \src "ls180.v:1907.5-1907.64" - process $proc$ls180.v:1907$3896 - assign { } { } - assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - end - attribute \src "ls180.v:1908.12-1908.71" - process $proc$ls180.v:1908$3897 - assign { } { } - assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - sync always - sync init - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - end - attribute \src "ls180.v:1909.5-1909.66" - process $proc$ls180.v:1909$3898 - assign { } { } - assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - end - attribute \src "ls180.v:1910.5-1910.66" - process $proc$ls180.v:1910$3899 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - end - attribute \src "ls180.v:1911.5-1911.69" - process $proc$ls180.v:1911$3900 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - end - attribute \src "ls180.v:1912.5-1912.41" - process $proc$ls180.v:1912$3901 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] - end - attribute \src "ls180.v:1913.5-1913.46" - process $proc$ls180.v:1913$3902 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] - end - attribute \src "ls180.v:1914.5-1914.66" - process $proc$ls180.v:1914$3903 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - end - attribute \src "ls180.v:1915.5-1915.69" - process $proc$ls180.v:1915$3904 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - end - attribute \src "ls180.v:1916.11-1916.41" - process $proc$ls180.v:1916$3905 - assign { } { } - assign $1\builder_sdphy_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] - end - attribute \src "ls180.v:1917.11-1917.46" - process $proc$ls180.v:1917$3906 - assign { } { } - assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] - end - attribute \src "ls180.v:1918.11-1918.61" - process $proc$ls180.v:1918$3907 - assign { } { } - assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - end - attribute \src "ls180.v:1919.5-1919.58" - process $proc$ls180.v:1919$3908 - assign { } { } - assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1920.11-1920.48" - process $proc$ls180.v:1920$3909 - assign { } { } - assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] - end - attribute \src "ls180.v:1921.11-1921.53" - process $proc$ls180.v:1921$3910 - assign { } { } - assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] - end - attribute \src "ls180.v:1922.11-1922.70" - process $proc$ls180.v:1922$3911 - assign { } { } - assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - end - attribute \src "ls180.v:1923.5-1923.66" - process $proc$ls180.v:1923$3912 - assign { } { } - assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - end - attribute \src "ls180.v:1924.12-1924.73" - process $proc$ls180.v:1924$3913 - assign { } { } - assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - sync always - sync init - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - end - attribute \src "ls180.v:1925.5-1925.68" - process $proc$ls180.v:1925$3914 - assign { } { } - assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - end - attribute \src "ls180.v:1926.5-1926.69" - process $proc$ls180.v:1926$3915 - assign { } { } - assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - end - attribute \src "ls180.v:1927.5-1927.72" - process $proc$ls180.v:1927$3916 - assign { } { } - assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:1928.5-1928.52" - process $proc$ls180.v:1928$3917 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] - end - attribute \src "ls180.v:1929.5-1929.57" - process $proc$ls180.v:1929$3918 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - end - attribute \src "ls180.v:1930.12-1930.93" - process $proc$ls180.v:1930$3919 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - end - attribute \src "ls180.v:1931.5-1931.88" - process $proc$ls180.v:1931$3920 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - end - attribute \src "ls180.v:1932.12-1932.93" - process $proc$ls180.v:1932$3921 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - end - attribute \src "ls180.v:1933.5-1933.88" - process $proc$ls180.v:1933$3922 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - end - attribute \src "ls180.v:1934.12-1934.93" - process $proc$ls180.v:1934$3923 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - end - attribute \src "ls180.v:1935.5-1935.88" - process $proc$ls180.v:1935$3924 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - end - attribute \src "ls180.v:1936.12-1936.93" - process $proc$ls180.v:1936$3925 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - end - attribute \src "ls180.v:1937.5-1937.88" - process $proc$ls180.v:1937$3926 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - end - attribute \src "ls180.v:1938.11-1938.87" - process $proc$ls180.v:1938$3927 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - end - attribute \src "ls180.v:1939.5-1939.84" - process $proc$ls180.v:1939$3928 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - end - attribute \src "ls180.v:1940.11-1940.42" - process $proc$ls180.v:1940$3929 - assign { } { } - assign $1\builder_sdcore_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] - end - attribute \src "ls180.v:1941.11-1941.47" - process $proc$ls180.v:1941$3930 - assign { } { } - assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] - end - attribute \src "ls180.v:1942.5-1942.55" - process $proc$ls180.v:1942$3931 - assign { } { } - assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - end - attribute \src "ls180.v:1943.5-1943.58" - process $proc$ls180.v:1943$3932 - assign { } { } - assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - end - attribute \src "ls180.v:1944.5-1944.56" - process $proc$ls180.v:1944$3933 - assign { } { } - assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - end - attribute \src "ls180.v:1945.5-1945.59" - process $proc$ls180.v:1945$3934 - assign { } { } - assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - end - attribute \src "ls180.v:1946.11-1946.62" - process $proc$ls180.v:1946$3935 - assign { } { } - assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - sync always - sync init - update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - end - attribute \src "ls180.v:1947.5-1947.59" - process $proc$ls180.v:1947$3936 - assign { } { } - assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - end - attribute \src "ls180.v:1948.12-1948.65" - process $proc$ls180.v:1948$3937 - assign { } { } - assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - sync always - sync init - update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - end - attribute \src "ls180.v:1949.5-1949.60" - process $proc$ls180.v:1949$3938 - assign { } { } - assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - end - attribute \src "ls180.v:1950.5-1950.56" - process $proc$ls180.v:1950$3939 - assign { } { } - assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - end - attribute \src "ls180.v:1951.5-1951.59" - process $proc$ls180.v:1951$3940 - assign { } { } - assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - end - attribute \src "ls180.v:1952.5-1952.58" - process $proc$ls180.v:1952$3941 - assign { } { } - assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - end - attribute \src "ls180.v:1953.5-1953.61" - process $proc$ls180.v:1953$3942 - assign { } { } - assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - end - attribute \src "ls180.v:1954.5-1954.57" - process $proc$ls180.v:1954$3943 - assign { } { } - assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - end - attribute \src "ls180.v:1955.5-1955.60" - process $proc$ls180.v:1955$3944 - assign { } { } - assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - end - attribute \src "ls180.v:1956.5-1956.59" - process $proc$ls180.v:1956$3945 - assign { } { } - assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - end - attribute \src "ls180.v:1957.5-1957.62" - process $proc$ls180.v:1957$3946 - assign { } { } - assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - end - attribute \src "ls180.v:1958.13-1958.76" - process $proc$ls180.v:1958$3947 - assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - end - attribute \src "ls180.v:1959.5-1959.69" - process $proc$ls180.v:1959$3948 - assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:1960.11-1960.46" - process $proc$ls180.v:1960$3949 - assign { } { } - assign $1\builder_sdblock2memdma_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] - end - attribute \src "ls180.v:1961.11-1961.51" - process $proc$ls180.v:1961$3950 - assign { } { } - assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] - end - attribute \src "ls180.v:1962.12-1962.87" - process $proc$ls180.v:1962$3951 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - end - attribute \src "ls180.v:1963.5-1963.82" - process $proc$ls180.v:1963$3952 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:1964.5-1964.44" - process $proc$ls180.v:1964$3953 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] - end - attribute \src "ls180.v:1965.5-1965.49" - process $proc$ls180.v:1965$3954 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] - end - attribute \src "ls180.v:1966.12-1966.75" - process $proc$ls180.v:1966$3955 - assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - end - attribute \src "ls180.v:1967.5-1967.70" - process $proc$ls180.v:1967$3956 - assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1968.11-1968.60" - process $proc$ls180.v:1968$3957 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] - end - attribute \src "ls180.v:1969.11-1969.65" - process $proc$ls180.v:1969$3958 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - end - attribute \src "ls180.v:1970.12-1970.87" - process $proc$ls180.v:1970$3959 - assign { } { } - assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - end - attribute \src "ls180.v:1971.5-1971.82" - process $proc$ls180.v:1971$3960 - assign { } { } - assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:1972.12-1972.43" - process $proc$ls180.v:1972$3961 - assign { } { } - assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] - end - attribute \src "ls180.v:1973.5-1973.34" - process $proc$ls180.v:1973$3962 - assign { } { } - assign $1\builder_libresocsim_we[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] - end - attribute \src "ls180.v:1974.11-1974.43" - process $proc$ls180.v:1974$3963 - assign { } { } - assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] - end - attribute \src "ls180.v:1976.12-1976.52" - process $proc$ls180.v:1976$3964 - assign { } { } - assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 - sync always - update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] - sync init - end - attribute \src "ls180.v:1977.12-1977.54" - process $proc$ls180.v:1977$3965 - assign { } { } - assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 - sync always - update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] - sync init - end - attribute \src "ls180.v:1978.12-1978.54" - process $proc$ls180.v:1978$3966 - assign { } { } - assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 - sync always - sync init - update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] - end - attribute \src "ls180.v:1979.11-1979.50" - process $proc$ls180.v:1979$3967 - assign { } { } - assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 - sync always - update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] - sync init - end - attribute \src "ls180.v:1980.5-1980.44" - process $proc$ls180.v:1980$3968 - assign { } { } - assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] - sync init - end - attribute \src "ls180.v:1981.5-1981.44" - process $proc$ls180.v:1981$3969 - assign { } { } - assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] - sync init - end - attribute \src "ls180.v:1982.5-1982.44" - process $proc$ls180.v:1982$3970 - assign { } { } - assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] - end - attribute \src "ls180.v:1983.5-1983.43" - process $proc$ls180.v:1983$3971 - assign { } { } - assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] - sync init - end - attribute \src "ls180.v:1986.12-1986.65" - process $proc$ls180.v:1986$3972 - assign { } { } - assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] - sync init - end - attribute \src "ls180.v:1990.5-1990.55" - process $proc$ls180.v:1990$3973 - assign { } { } - assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 - sync always - update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] - sync init - end - attribute \src "ls180.v:1994.5-1994.55" - process $proc$ls180.v:1994$3974 - assign { } { } - assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 - sync always - update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] - sync init - end - attribute \src "ls180.v:1997.12-1997.40" - process $proc$ls180.v:1997$3975 - assign { } { } - assign $1\builder_shared_dat_r[31:0] 0 - sync always - sync init - update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] - end - attribute \src "ls180.v:2001.5-2001.30" - process $proc$ls180.v:2001$3976 - assign { } { } - assign $1\builder_shared_ack[0:0] 1'0 - sync always - sync init - update \builder_shared_ack $1\builder_shared_ack[0:0] - end - attribute \src "ls180.v:2007.11-2007.31" - process $proc$ls180.v:2007$3977 - assign { } { } - assign $1\builder_grant[2:0] 3'000 - sync always - sync init - update \builder_grant $1\builder_grant[2:0] - end - attribute \src "ls180.v:2008.12-2008.37" - process $proc$ls180.v:2008$3978 - assign { } { } - assign $1\builder_slave_sel[12:0] 13'0000000000000 - sync always - sync init - update \builder_slave_sel $1\builder_slave_sel[12:0] - end - attribute \src "ls180.v:2009.12-2009.39" - process $proc$ls180.v:2009$3979 - assign { } { } - assign $1\builder_slave_sel_r[12:0] 13'0000000000000 - sync always - sync init - update \builder_slave_sel_r $1\builder_slave_sel_r[12:0] - end - attribute \src "ls180.v:2010.5-2010.25" - process $proc$ls180.v:2010$3980 - assign { } { } - assign $1\builder_error[0:0] 1'0 - sync always - sync init - update \builder_error $1\builder_error[0:0] - end - attribute \src "ls180.v:2013.12-2013.39" - process $proc$ls180.v:2013$3981 - assign { } { } - assign $1\builder_count[19:0] 20'11110100001001000000 - sync always - sync init - update \builder_count $1\builder_count[19:0] - end - attribute \src "ls180.v:2017.11-2017.51" - process $proc$ls180.v:2017$3982 - assign { } { } - assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2058.11-2058.51" - process $proc$ls180.v:2058$3983 - assign { } { } - assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2087.11-2087.51" - process $proc$ls180.v:2087$3984 - assign { } { } - assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:210.5-210.40" - process $proc$ls180.v:210$3150 - assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2100.11-2100.51" - process $proc$ls180.v:2100$3985 - assign { } { } - assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:214.5-214.40" - process $proc$ls180.v:214$3151 - assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 - sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:2141.11-2141.51" - process $proc$ls180.v:2141$3986 - assign { } { } - assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:217.11-217.37" - process $proc$ls180.v:217$3152 - assign { } { } - assign $1\main_libresocsim_we[7:0] 8'00000000 - sync always - sync init - update \main_libresocsim_we $1\main_libresocsim_we[7:0] - end - attribute \src "ls180.v:2182.11-2182.51" - process $proc$ls180.v:2182$3987 - assign { } { } - assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:219.12-219.49" - process $proc$ls180.v:219$3153 - assign { } { } - assign $1\main_libresocsim_load_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] - end - attribute \src "ls180.v:220.5-220.36" - process $proc$ls180.v:220$3154 - assign { } { } - assign $1\main_libresocsim_load_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] - end - attribute \src "ls180.v:221.12-221.51" - process $proc$ls180.v:221$3155 - assign { } { } - assign $1\main_libresocsim_reload_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] - end - attribute \src "ls180.v:222.5-222.38" - process $proc$ls180.v:222$3156 - assign { } { } - assign $1\main_libresocsim_reload_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] - end - attribute \src "ls180.v:223.5-223.39" - process $proc$ls180.v:223$3157 - assign { } { } - assign $1\main_libresocsim_en_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] - end - attribute \src "ls180.v:224.5-224.34" - process $proc$ls180.v:224$3158 - assign { } { } - assign $1\main_libresocsim_en_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] - end - attribute \src "ls180.v:2247.11-2247.51" - process $proc$ls180.v:2247$3988 - assign { } { } - assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:225.5-225.49" - process $proc$ls180.v:225$3159 - assign { } { } - assign $1\main_libresocsim_update_value_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] - end - attribute \src "ls180.v:226.5-226.44" - process $proc$ls180.v:226$3160 - assign { } { } - assign $1\main_libresocsim_update_value_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] - end - attribute \src "ls180.v:227.12-227.49" - process $proc$ls180.v:227$3161 - assign { } { } - assign $1\main_libresocsim_value_status[31:0] 0 - sync always - sync init - update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] - end - attribute \src "ls180.v:231.5-231.41" - process $proc$ls180.v:231$3162 - assign { } { } - assign $1\main_libresocsim_zero_pending[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] - end - attribute \src "ls180.v:233.5-233.39" - process $proc$ls180.v:233$3163 - assign { } { } - assign $1\main_libresocsim_zero_clear[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:234.5-234.45" - process $proc$ls180.v:234$3164 - assign { } { } - assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] - end - attribute \src "ls180.v:2380.11-2380.51" - process $proc$ls180.v:2380$3989 - assign { } { } - assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:243.5-243.49" - process $proc$ls180.v:243$3165 - assign { } { } - assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] - end - attribute \src "ls180.v:244.5-244.44" - process $proc$ls180.v:244$3166 - assign { } { } - assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] - end - attribute \src "ls180.v:245.12-245.42" - process $proc$ls180.v:245$3167 - assign { } { } - assign $1\main_libresocsim_value[31:0] 0 - sync always - sync init - update \main_libresocsim_value $1\main_libresocsim_value[31:0] - end - attribute \src "ls180.v:2461.11-2461.51" - process $proc$ls180.v:2461$3990 - assign { } { } - assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2478.11-2478.51" - process $proc$ls180.v:2478$3991 - assign { } { } - assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2519.11-2519.52" - process $proc$ls180.v:2519$3992 - assign { } { } - assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:252.5-252.39" - process $proc$ls180.v:252$3168 - assign { } { } - assign $1\main_interface0_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2552.11-2552.52" - process $proc$ls180.v:2552$3993 - assign { } { } - assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:256.5-256.39" - process $proc$ls180.v:256$3169 - assign { } { } - assign $0\main_interface0_ram_bus_err[0:0] 1'0 - sync always - update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:259.11-259.31" - process $proc$ls180.v:259$3170 - assign { } { } - assign $1\main_sram0_we[7:0] 8'00000000 - sync always - sync init - update \main_sram0_we $1\main_sram0_we[7:0] - end - attribute \src "ls180.v:2593.11-2593.52" - process $proc$ls180.v:2593$3994 - assign { } { } - assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2658.11-2658.52" - process $proc$ls180.v:2658$3995 - assign { } { } - assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:267.5-267.39" - process $proc$ls180.v:267$3171 - assign { } { } - assign $1\main_interface1_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2683.11-2683.52" - process $proc$ls180.v:2683$3996 - assign { } { } - assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2705.11-2705.31" - process $proc$ls180.v:2705$3997 - assign { } { } - assign $1\builder_state[1:0] 2'00 - sync always - sync init - update \builder_state $1\builder_state[1:0] - end - attribute \src "ls180.v:2706.11-2706.36" - process $proc$ls180.v:2706$3998 - assign { } { } - assign $1\builder_next_state[1:0] 2'00 - sync always - sync init - update \builder_next_state $1\builder_next_state[1:0] - end - attribute \src "ls180.v:2707.11-2707.55" - process $proc$ls180.v:2707$3999 - assign { } { } - assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] - end - attribute \src "ls180.v:2708.5-2708.52" - process $proc$ls180.v:2708$4000 - assign { } { } - assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - end - attribute \src "ls180.v:2709.12-2709.55" - process $proc$ls180.v:2709$4001 - assign { } { } - assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] - end - attribute \src "ls180.v:271.5-271.39" - process $proc$ls180.v:271$3172 - assign { } { } - assign $0\main_interface1_ram_bus_err[0:0] 1'0 - sync always - update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:2710.5-2710.50" - process $proc$ls180.v:2710$4002 - assign { } { } - assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] - end - attribute \src "ls180.v:2711.5-2711.46" - process $proc$ls180.v:2711$4003 - assign { } { } - assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] - end - attribute \src "ls180.v:2712.5-2712.49" - process $proc$ls180.v:2712$4004 - assign { } { } - assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] - end - attribute \src "ls180.v:2713.5-2713.41" - process $proc$ls180.v:2713$4005 - assign { } { } - assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] - end - attribute \src "ls180.v:2714.12-2714.49" - process $proc$ls180.v:2714$4006 - assign { } { } - assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:2715.11-2715.47" - process $proc$ls180.v:2715$4007 - assign { } { } - assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] - end - attribute \src "ls180.v:2716.5-2716.41" - process $proc$ls180.v:2716$4008 - assign { } { } - assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:2717.5-2717.41" - process $proc$ls180.v:2717$4009 - assign { } { } - assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:2718.5-2718.41" - process $proc$ls180.v:2718$4010 - assign { } { } - assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:2719.5-2719.39" - process $proc$ls180.v:2719$4011 - assign { } { } - assign $1\builder_comb_t_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] - end - attribute \src "ls180.v:2720.5-2720.39" - process $proc$ls180.v:2720$4012 - assign { } { } - assign $1\builder_comb_t_array_muxed1[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] - end - attribute \src "ls180.v:2721.5-2721.39" - process $proc$ls180.v:2721$4013 - assign { } { } - assign $1\builder_comb_t_array_muxed2[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] - end - attribute \src "ls180.v:2722.5-2722.41" - process $proc$ls180.v:2722$4014 - assign { } { } - assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:2723.12-2723.49" - process $proc$ls180.v:2723$4015 - assign { } { } - assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] - end - attribute \src "ls180.v:2724.11-2724.47" - process $proc$ls180.v:2724$4016 - assign { } { } - assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] - end - attribute \src "ls180.v:2725.5-2725.41" - process $proc$ls180.v:2725$4017 - assign { } { } - assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] - end - attribute \src "ls180.v:2726.5-2726.42" - process $proc$ls180.v:2726$4018 - assign { } { } - assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] - end - attribute \src "ls180.v:2727.5-2727.42" - process $proc$ls180.v:2727$4019 - assign { } { } - assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] - end - attribute \src "ls180.v:2728.5-2728.39" - process $proc$ls180.v:2728$4020 - assign { } { } - assign $1\builder_comb_t_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] - end - attribute \src "ls180.v:2729.5-2729.39" - process $proc$ls180.v:2729$4021 - assign { } { } - assign $1\builder_comb_t_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] - end - attribute \src "ls180.v:2730.5-2730.39" - process $proc$ls180.v:2730$4022 - assign { } { } - assign $1\builder_comb_t_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] - end - attribute \src "ls180.v:2731.12-2731.50" - process $proc$ls180.v:2731$4023 - assign { } { } - assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] - end - attribute \src "ls180.v:2732.5-2732.42" - process $proc$ls180.v:2732$4024 - assign { } { } - assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] - end - attribute \src "ls180.v:2733.5-2733.42" - process $proc$ls180.v:2733$4025 - assign { } { } - assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] - end - attribute \src "ls180.v:2734.12-2734.50" - process $proc$ls180.v:2734$4026 - assign { } { } - assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] - end - attribute \src "ls180.v:2735.5-2735.42" - process $proc$ls180.v:2735$4027 - assign { } { } - assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] - end - attribute \src "ls180.v:2736.5-2736.42" - process $proc$ls180.v:2736$4028 - assign { } { } - assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] - end - attribute \src "ls180.v:2737.12-2737.50" - process $proc$ls180.v:2737$4029 - assign { } { } - assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] - end - attribute \src "ls180.v:2738.5-2738.42" - process $proc$ls180.v:2738$4030 - assign { } { } - assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] - end - attribute \src "ls180.v:2739.5-2739.42" - process $proc$ls180.v:2739$4031 - assign { } { } - assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] - end - attribute \src "ls180.v:274.11-274.31" - process $proc$ls180.v:274$3173 - assign { } { } - assign $1\main_sram1_we[7:0] 8'00000000 - sync always - sync init - update \main_sram1_we $1\main_sram1_we[7:0] - end - attribute \src "ls180.v:2740.12-2740.50" - process $proc$ls180.v:2740$4032 - assign { } { } - assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] - end - attribute \src "ls180.v:2741.5-2741.42" - process $proc$ls180.v:2741$4033 - assign { } { } - assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] - end - attribute \src "ls180.v:2742.5-2742.42" - process $proc$ls180.v:2742$4034 - assign { } { } - assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] - end - attribute \src "ls180.v:2743.12-2743.50" - process $proc$ls180.v:2743$4035 - assign { } { } - assign $1\builder_comb_rhs_array_muxed24[31:0] 0 - sync always - sync init - update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] - end - attribute \src "ls180.v:2744.12-2744.50" - process $proc$ls180.v:2744$4036 - assign { } { } - assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] - end - attribute \src "ls180.v:2745.11-2745.48" - process $proc$ls180.v:2745$4037 - assign { } { } - assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 - sync always - sync init - update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] - end - attribute \src "ls180.v:2746.5-2746.42" - process $proc$ls180.v:2746$4038 - assign { } { } - assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] - end - attribute \src "ls180.v:2747.5-2747.42" - process $proc$ls180.v:2747$4039 - assign { } { } - assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] - end - attribute \src "ls180.v:2748.5-2748.42" - process $proc$ls180.v:2748$4040 - assign { } { } - assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] - end - attribute \src "ls180.v:2749.11-2749.48" - process $proc$ls180.v:2749$4041 - assign { } { } - assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 - sync always - sync init - update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] - end - attribute \src "ls180.v:2750.11-2750.48" - process $proc$ls180.v:2750$4042 - assign { } { } - assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] - end - attribute \src "ls180.v:2751.11-2751.47" - process $proc$ls180.v:2751$4043 - assign { } { } - assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 - sync always - sync init - update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] - end - attribute \src "ls180.v:2752.12-2752.49" - process $proc$ls180.v:2752$4044 - assign { } { } - assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - sync always - sync init - update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:2753.5-2753.41" - process $proc$ls180.v:2753$4045 - assign { } { } - assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] - end - attribute \src "ls180.v:2754.5-2754.41" - process $proc$ls180.v:2754$4046 - assign { } { } - assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:2755.5-2755.41" - process $proc$ls180.v:2755$4047 - assign { } { } - assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:2756.5-2756.41" - process $proc$ls180.v:2756$4048 - assign { } { } - assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:2757.5-2757.41" - process $proc$ls180.v:2757$4049 - assign { } { } - assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:2758.5-2758.39" - process $proc$ls180.v:2758$4050 - assign { } { } - assign $1\builder_sync_f_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] - end - attribute \src "ls180.v:2759.5-2759.39" - process $proc$ls180.v:2759$4051 - assign { } { } - assign $1\builder_sync_f_array_muxed1[0:0] 1'0 - sync always - sync init - update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] - end - attribute \src "ls180.v:2816.32-2816.66" - process $proc$ls180.v:2816$4052 - assign { } { } - assign $1\builder_multiregimpl0_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] - end - attribute \src "ls180.v:2817.32-2817.66" - process $proc$ls180.v:2817$4053 - assign { } { } - assign $1\builder_multiregimpl0_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] - end - attribute \src "ls180.v:2818.32-2818.66" - process $proc$ls180.v:2818$4054 - assign { } { } - assign $1\builder_multiregimpl1_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] - end - attribute \src "ls180.v:2819.32-2819.66" - process $proc$ls180.v:2819$4055 - assign { } { } - assign $1\builder_multiregimpl1_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] - end - attribute \src "ls180.v:282.5-282.39" - process $proc$ls180.v:282$3174 - assign { } { } - assign $1\main_interface2_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2820.32-2820.66" - process $proc$ls180.v:2820$4056 - assign { } { } - assign $1\builder_multiregimpl2_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] - end - attribute \src "ls180.v:2821.32-2821.66" - process $proc$ls180.v:2821$4057 - assign { } { } - assign $1\builder_multiregimpl2_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] - end - attribute \src "ls180.v:2822.32-2822.66" - process $proc$ls180.v:2822$4058 - assign { } { } - assign $1\builder_multiregimpl3_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] - end - attribute \src "ls180.v:2823.32-2823.66" - process $proc$ls180.v:2823$4059 - assign { } { } - assign $1\builder_multiregimpl3_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] - end - attribute \src "ls180.v:2824.32-2824.66" - process $proc$ls180.v:2824$4060 - assign { } { } - assign $1\builder_multiregimpl4_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] - end - attribute \src "ls180.v:2825.32-2825.66" - process $proc$ls180.v:2825$4061 - assign { } { } - assign $1\builder_multiregimpl4_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] - end - attribute \src "ls180.v:2826.32-2826.66" - process $proc$ls180.v:2826$4062 - assign { } { } - assign $1\builder_multiregimpl5_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] - end - attribute \src "ls180.v:2827.32-2827.66" - process $proc$ls180.v:2827$4063 - assign { } { } - assign $1\builder_multiregimpl5_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] - end - attribute \src "ls180.v:2828.32-2828.66" - process $proc$ls180.v:2828$4064 - assign { } { } - assign $1\builder_multiregimpl6_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] - end - attribute \src "ls180.v:2829.32-2829.66" - process $proc$ls180.v:2829$4065 - assign { } { } - assign $1\builder_multiregimpl6_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] - end - attribute \src "ls180.v:2830.32-2830.66" - process $proc$ls180.v:2830$4066 - assign { } { } - assign $1\builder_multiregimpl7_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] - end - attribute \src "ls180.v:2831.32-2831.66" - process $proc$ls180.v:2831$4067 - assign { } { } - assign $1\builder_multiregimpl7_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] - end - attribute \src "ls180.v:2832.32-2832.66" - process $proc$ls180.v:2832$4068 - assign { } { } - assign $1\builder_multiregimpl8_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] - end - attribute \src "ls180.v:2833.32-2833.66" - process $proc$ls180.v:2833$4069 - assign { } { } - assign $1\builder_multiregimpl8_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] - end - attribute \src "ls180.v:2834.32-2834.66" - process $proc$ls180.v:2834$4070 - assign { } { } - assign $1\builder_multiregimpl9_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] - end - attribute \src "ls180.v:2835.32-2835.66" - process $proc$ls180.v:2835$4071 - assign { } { } - assign $1\builder_multiregimpl9_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] - end - attribute \src "ls180.v:2836.32-2836.67" - process $proc$ls180.v:2836$4072 - assign { } { } - assign $1\builder_multiregimpl10_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] - end - attribute \src "ls180.v:2837.32-2837.67" - process $proc$ls180.v:2837$4073 - assign { } { } - assign $1\builder_multiregimpl10_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] - end - attribute \src "ls180.v:2838.32-2838.67" - process $proc$ls180.v:2838$4074 - assign { } { } - assign $1\builder_multiregimpl11_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] - end - attribute \src "ls180.v:2839.32-2839.67" - process $proc$ls180.v:2839$4075 - assign { } { } - assign $1\builder_multiregimpl11_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] - end - attribute \src "ls180.v:2840.32-2840.67" - process $proc$ls180.v:2840$4076 - assign { } { } - assign $1\builder_multiregimpl12_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] - end - attribute \src "ls180.v:2841.32-2841.67" - process $proc$ls180.v:2841$4077 - assign { } { } - assign $1\builder_multiregimpl12_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] - end - attribute \src "ls180.v:2842.32-2842.67" - process $proc$ls180.v:2842$4078 - assign { } { } - assign $1\builder_multiregimpl13_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] - end - attribute \src "ls180.v:2843.32-2843.67" - process $proc$ls180.v:2843$4079 - assign { } { } - assign $1\builder_multiregimpl13_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] - end - attribute \src "ls180.v:2844.32-2844.67" - process $proc$ls180.v:2844$4080 - assign { } { } - assign $1\builder_multiregimpl14_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] - end - attribute \src "ls180.v:2845.32-2845.67" - process $proc$ls180.v:2845$4081 - assign { } { } - assign $1\builder_multiregimpl14_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] - end - attribute \src "ls180.v:2846.32-2846.67" - process $proc$ls180.v:2846$4082 - assign { } { } - assign $1\builder_multiregimpl15_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] - end - attribute \src "ls180.v:2847.32-2847.67" - process $proc$ls180.v:2847$4083 - assign { } { } - assign $1\builder_multiregimpl15_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] - end - attribute \src "ls180.v:2848.32-2848.67" - process $proc$ls180.v:2848$4084 - assign { } { } - assign $1\builder_multiregimpl16_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] - end - attribute \src "ls180.v:2849.32-2849.67" - process $proc$ls180.v:2849$4085 - assign { } { } - assign $1\builder_multiregimpl16_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] - end - attribute \src "ls180.v:286.5-286.39" - process $proc$ls180.v:286$3175 - assign { } { } - assign $0\main_interface2_ram_bus_err[0:0] 1'0 - sync always - update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:2884.1-2889.4" - process $proc$ls180.v:2884$49 - assign { } { } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 - assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq - assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq - sync always - update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:289.11-289.31" - process $proc$ls180.v:289$3176 - assign { } { } - assign $1\main_sram2_we[7:0] 8'00000000 - sync always - sync init - update \main_sram2_we $1\main_sram2_we[7:0] - end - attribute \src "ls180.v:2891.1-2901.4" - process $proc$ls180.v:2891$51 - assign { } { } - assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 - attribute \src "ls180.v:2893.2-2900.9" - switch \main_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [63:32] - case - end - sync always - update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - end - attribute \src "ls180.v:2903.1-2949.4" - process $proc$ls180.v:2903$52 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_interface0_converted_interface_ack[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 - assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 - assign $0\main_converter0_skip[0:0] 1'0 - assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2915.2-2948.9" - switch \builder_converter0_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } - attribute \src "ls180.v:2918.4-2925.11" - switch \main_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] - case - end - attribute \src "ls180.v:2926.4-2939.7" - switch $and$ls180.v:2926$53_Y - attribute \src "ls180.v:2926.8-2926.91" - case 1'1 - assign $0\main_converter0_skip[0:0] $eq$ls180.v:2927$54_Y - assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we - assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2929$55_Y - assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2930$56_Y - attribute \src "ls180.v:2931.5-2938.8" - switch $or$ls180.v:2931$57_Y - attribute \src "ls180.v:2931.9-2931.72" - case 1'1 - assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2932$58_Y - assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2934.6-2937.9" - switch $eq$ls180.v:2934$59_Y - attribute \src "ls180.v:2934.10-2934.43" - case 1'1 - assign $0\main_interface0_converted_interface_ack[0:0] 1'1 - assign $0\builder_converter0_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2944.4-2946.7" - switch $and$ls180.v:2944$60_Y - attribute \src "ls180.v:2944.8-2944.91" - case 1'1 - assign $0\builder_converter0_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_xics_icp_adr $0\main_libresocsim_libresoc_xics_icp_adr[29:0] - update \main_libresocsim_libresoc_xics_icp_sel $0\main_libresocsim_libresoc_xics_icp_sel[3:0] - update \main_libresocsim_libresoc_xics_icp_cyc $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] - update \main_libresocsim_libresoc_xics_icp_stb $0\main_libresocsim_libresoc_xics_icp_stb[0:0] - update \main_libresocsim_libresoc_xics_icp_we $0\main_libresocsim_libresoc_xics_icp_we[0:0] - update \main_interface0_converted_interface_ack $0\main_interface0_converted_interface_ack[0:0] - update \main_converter0_skip $0\main_converter0_skip[0:0] - update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] - update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] - update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:2951.1-2961.4" - process $proc$ls180.v:2951$62 - assign { } { } - assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 - attribute \src "ls180.v:2953.2-2960.9" - switch \main_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [63:32] - case - end - sync always - update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] - end - attribute \src "ls180.v:2963.1-3009.4" - process $proc$ls180.v:2963$63 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 - assign $0\main_interface1_converted_interface_ack[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 - assign $0\main_converter1_skip[0:0] 1'0 - assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2975.2-3008.9" - switch \builder_converter1_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } - attribute \src "ls180.v:2978.4-2985.11" - switch \main_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] - case - end - attribute \src "ls180.v:2986.4-2999.7" - switch $and$ls180.v:2986$64_Y - attribute \src "ls180.v:2986.8-2986.91" - case 1'1 - assign $0\main_converter1_skip[0:0] $eq$ls180.v:2987$65_Y - assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we - assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2989$66_Y - assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2990$67_Y - attribute \src "ls180.v:2991.5-2998.8" - switch $or$ls180.v:2991$68_Y - attribute \src "ls180.v:2991.9-2991.72" - case 1'1 - assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2992$69_Y - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2994.6-2997.9" - switch $eq$ls180.v:2994$70_Y - attribute \src "ls180.v:2994.10-2994.43" - case 1'1 - assign $0\main_interface1_converted_interface_ack[0:0] 1'1 - assign $0\builder_converter1_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3004.4-3006.7" - switch $and$ls180.v:3004$71_Y - attribute \src "ls180.v:3004.8-3004.91" - case 1'1 - assign $0\builder_converter1_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_xics_ics_adr $0\main_libresocsim_libresoc_xics_ics_adr[29:0] - update \main_libresocsim_libresoc_xics_ics_sel $0\main_libresocsim_libresoc_xics_ics_sel[3:0] - update \main_libresocsim_libresoc_xics_ics_cyc $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] - update \main_libresocsim_libresoc_xics_ics_stb $0\main_libresocsim_libresoc_xics_ics_stb[0:0] - update \main_libresocsim_libresoc_xics_ics_we $0\main_libresocsim_libresoc_xics_ics_we[0:0] - update \main_interface1_converted_interface_ack $0\main_interface1_converted_interface_ack[0:0] - update \main_converter1_skip $0\main_converter1_skip[0:0] - update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] - update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] - update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] - end - attribute \src "ls180.v:297.5-297.39" - process $proc$ls180.v:297$3177 - assign { } { } - assign $1\main_interface3_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface3_ram_bus_ack $1\main_interface3_ram_bus_ack[0:0] - end - attribute \src "ls180.v:301.5-301.39" - process $proc$ls180.v:301$3178 - assign { } { } - assign $0\main_interface3_ram_bus_err[0:0] 1'0 - sync always - update \main_interface3_ram_bus_err $0\main_interface3_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:3011.1-3021.4" - process $proc$ls180.v:3011$73 - assign { } { } - assign $0\main_wb_sdram_dat_w[31:0] 0 - attribute \src "ls180.v:3013.2-3020.9" - switch \main_socbushandler_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [63:32] - case - end - sync always - update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] - end - attribute \src "ls180.v:3023.1-3069.4" - process $proc$ls180.v:3023$74 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_wb_sdram_we[0:0] 1'0 - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 - assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 - assign $0\main_wb_sdram_sel[3:0] 4'0000 - assign $0\main_wb_sdram_cyc[0:0] 1'0 - assign $0\main_wb_sdram_stb[0:0] 1'0 - assign $0\main_socbushandler_skip[0:0] 1'0 - assign { } { } - assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:3035.2-3068.9" - switch \builder_converter2_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } - attribute \src "ls180.v:3038.4-3045.11" - switch \main_socbushandler_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] - case - end - attribute \src "ls180.v:3046.4-3059.7" - switch $and$ls180.v:3046$75_Y - attribute \src "ls180.v:3046.8-3046.97" - case 1'1 - assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:3047$76_Y - assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we - assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:3049$77_Y - assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:3050$78_Y - attribute \src "ls180.v:3051.5-3058.8" - switch $or$ls180.v:3051$79_Y - attribute \src "ls180.v:3051.9-3051.54" - case 1'1 - assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:3052$80_Y - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3054.6-3057.9" - switch $eq$ls180.v:3054$81_Y - attribute \src "ls180.v:3054.10-3054.46" - case 1'1 - assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 - assign $0\builder_converter2_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3064.4-3066.7" - switch $and$ls180.v:3064$82_Y - attribute \src "ls180.v:3064.8-3064.97" - case 1'1 - assign $0\builder_converter2_next_state[0:0] 1'1 - case - end - end - sync always - update \main_wb_sdram_adr $0\main_wb_sdram_adr[29:0] - update \main_wb_sdram_sel $0\main_wb_sdram_sel[3:0] - update \main_wb_sdram_cyc $0\main_wb_sdram_cyc[0:0] - update \main_wb_sdram_stb $0\main_wb_sdram_stb[0:0] - update \main_wb_sdram_we $0\main_wb_sdram_we[0:0] - update \main_socbushandler_converted_interface_ack $0\main_socbushandler_converted_interface_ack[0:0] - update \main_socbushandler_skip $0\main_socbushandler_skip[0:0] - update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] - update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] - update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] - end - attribute \src "ls180.v:304.11-304.31" - process $proc$ls180.v:304$3179 - assign { } { } - assign $1\main_sram3_we[7:0] 8'00000000 - sync always - sync init - update \main_sram3_we $1\main_sram3_we[7:0] - end - attribute \src "ls180.v:3072.1-3082.4" - process $proc$ls180.v:3072$83 - assign { } { } - assign { } { } - assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3074$86_Y - assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3075$89_Y - assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3076$92_Y - assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3077$95_Y - assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3078$98_Y - assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3079$101_Y - assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3080$104_Y - assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3081$107_Y - sync always - update \main_libresocsim_we $0\main_libresocsim_we[7:0] - end - attribute \src "ls180.v:3088.1-3093.4" - process $proc$ls180.v:3088$109 - assign { } { } - assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:3090.2-3092.5" - switch $and$ls180.v:3090$110_Y - attribute \src "ls180.v:3090.6-3090.90" - case 1'1 - assign $0\main_libresocsim_zero_clear[0:0] 1'1 - case - end - sync always - update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:3097.1-3107.4" - process $proc$ls180.v:3097$112 - assign { } { } - assign { } { } - assign $0\main_sram0_we[7:0] [0] $and$ls180.v:3099$115_Y - assign $0\main_sram0_we[7:0] [1] $and$ls180.v:3100$118_Y - assign $0\main_sram0_we[7:0] [2] $and$ls180.v:3101$121_Y - assign $0\main_sram0_we[7:0] [3] $and$ls180.v:3102$124_Y - assign $0\main_sram0_we[7:0] [4] $and$ls180.v:3103$127_Y - assign $0\main_sram0_we[7:0] [5] $and$ls180.v:3104$130_Y - assign $0\main_sram0_we[7:0] [6] $and$ls180.v:3105$133_Y - assign $0\main_sram0_we[7:0] [7] $and$ls180.v:3106$136_Y - sync always - update \main_sram0_we $0\main_sram0_we[7:0] - end - attribute \src "ls180.v:3111.1-3121.4" - process $proc$ls180.v:3111$137 - assign { } { } - assign { } { } - assign $0\main_sram1_we[7:0] [0] $and$ls180.v:3113$140_Y - assign $0\main_sram1_we[7:0] [1] $and$ls180.v:3114$143_Y - assign $0\main_sram1_we[7:0] [2] $and$ls180.v:3115$146_Y - assign $0\main_sram1_we[7:0] [3] $and$ls180.v:3116$149_Y - assign $0\main_sram1_we[7:0] [4] $and$ls180.v:3117$152_Y - assign $0\main_sram1_we[7:0] [5] $and$ls180.v:3118$155_Y - assign $0\main_sram1_we[7:0] [6] $and$ls180.v:3119$158_Y - assign $0\main_sram1_we[7:0] [7] $and$ls180.v:3120$161_Y - sync always - update \main_sram1_we $0\main_sram1_we[7:0] - end - attribute \src "ls180.v:312.5-312.51" - process $proc$ls180.v:312$3180 - assign { } { } - assign $1\main_interface0_converted_interface_ack[0:0] 1'0 - sync always - sync init - update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] - end - attribute \src "ls180.v:3125.1-3135.4" - process $proc$ls180.v:3125$162 - assign { } { } - assign { } { } - assign $0\main_sram2_we[7:0] [0] $and$ls180.v:3127$165_Y - assign $0\main_sram2_we[7:0] [1] $and$ls180.v:3128$168_Y - assign $0\main_sram2_we[7:0] [2] $and$ls180.v:3129$171_Y - assign $0\main_sram2_we[7:0] [3] $and$ls180.v:3130$174_Y - assign $0\main_sram2_we[7:0] [4] $and$ls180.v:3131$177_Y - assign $0\main_sram2_we[7:0] [5] $and$ls180.v:3132$180_Y - assign $0\main_sram2_we[7:0] [6] $and$ls180.v:3133$183_Y - assign $0\main_sram2_we[7:0] [7] $and$ls180.v:3134$186_Y - sync always - update \main_sram2_we $0\main_sram2_we[7:0] - end - attribute \src "ls180.v:3139.1-3149.4" - process $proc$ls180.v:3139$187 - assign { } { } - assign { } { } - assign $0\main_sram3_we[7:0] [0] $and$ls180.v:3141$190_Y - assign $0\main_sram3_we[7:0] [1] $and$ls180.v:3142$193_Y - assign $0\main_sram3_we[7:0] [2] $and$ls180.v:3143$196_Y - assign $0\main_sram3_we[7:0] [3] $and$ls180.v:3144$199_Y - assign $0\main_sram3_we[7:0] [4] $and$ls180.v:3145$202_Y - assign $0\main_sram3_we[7:0] [5] $and$ls180.v:3146$205_Y - assign $0\main_sram3_we[7:0] [6] $and$ls180.v:3147$208_Y - assign $0\main_sram3_we[7:0] [7] $and$ls180.v:3148$211_Y - sync always - update \main_sram3_we $0\main_sram3_we[7:0] - end - attribute \src "ls180.v:316.5-316.51" - process $proc$ls180.v:316$3181 - assign { } { } - assign $0\main_interface0_converted_interface_err[0:0] 1'0 - sync always - update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] - sync init - end - attribute \src "ls180.v:317.5-317.32" - process $proc$ls180.v:317$3182 - assign { } { } - assign $1\main_converter0_skip[0:0] 1'0 - sync always - sync init - update \main_converter0_skip $1\main_converter0_skip[0:0] - end - attribute \src "ls180.v:318.5-318.35" - process $proc$ls180.v:318$3183 - assign { } { } - assign $1\main_converter0_counter[0:0] 1'0 - sync always - sync init - update \main_converter0_counter $1\main_converter0_counter[0:0] - end - attribute \src "ls180.v:3188.1-3242.4" - process $proc$ls180.v:3188$212 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_master_p0_bank[1:0] 2'00 - assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_master_p0_we_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cke[0:0] 1'0 - assign $0\main_sdram_master_p0_odt[0:0] 1'0 - assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 - assign $0\main_sdram_master_p0_act_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - attribute \src "ls180.v:3207.2-3241.5" - switch \main_sdram_sel - attribute \src "ls180.v:3207.6-3207.20" - case 1'1 - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en - assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3224.6-3224.10" - case - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en - assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - end - sync always - update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] - update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] - update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] - update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] - update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] - update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] - update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] - update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] - update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] - update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] - update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] - update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] - update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] - update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] - update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] - update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] - update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] - update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:320.12-320.41" - process $proc$ls180.v:320$3184 - assign { } { } - assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] - end - attribute \src "ls180.v:3246.1-3262.4" - process $proc$ls180.v:3246$213 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - attribute \src "ls180.v:3251.2-3261.5" - switch \main_sdram_command_issue_re - attribute \src "ls180.v:3251.6-3251.33" - case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3252$214_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3253$215_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3254$216_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3255$217_Y - attribute \src "ls180.v:3256.6-3256.10" - case - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - end - sync always - update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] - update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] - update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] - update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:327.5-327.51" - process $proc$ls180.v:327$3185 - assign { } { } - assign $1\main_interface1_converted_interface_ack[0:0] 1'0 - sync always - sync init - update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] - end - attribute \src "ls180.v:3305.1-3335.4" - process $proc$ls180.v:3305$226 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_cmd_last[0:0] 1'0 - assign $0\main_sdram_sequencer_start0[0:0] 1'0 - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3311.2-3334.9" - switch \builder_refresher_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3314.4-3317.7" - switch \main_sdram_cmd_ready - attribute \src "ls180.v:3314.8-3314.28" - case 1'1 - assign $0\main_sdram_sequencer_start0[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3321.4-3325.7" - switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3321.8-3321.34" - case 1'1 - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign $0\main_sdram_cmd_last[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3328.4-3332.7" - switch 1'1 - attribute \src "ls180.v:3328.8-3328.12" - case 1'1 - attribute \src "ls180.v:3329.5-3331.8" - switch \main_sdram_wants_refresh - attribute \src "ls180.v:3329.9-3329.33" - case 1'1 - assign $0\builder_refresher_next_state[1:0] 2'01 - case - end - case - end - end - sync always - update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] - update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] - update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] - update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:331.5-331.51" - process $proc$ls180.v:331$3186 - assign { } { } - assign $0\main_interface1_converted_interface_err[0:0] 1'0 - sync always - update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] - sync init - end - attribute \src "ls180.v:332.5-332.32" - process $proc$ls180.v:332$3187 - assign { } { } - assign $1\main_converter1_skip[0:0] 1'0 - sync always - sync init - update \main_converter1_skip $1\main_converter1_skip[0:0] - end - attribute \src "ls180.v:333.5-333.35" - process $proc$ls180.v:333$3188 - assign { } { } - assign $1\main_converter1_counter[0:0] 1'0 - sync always - sync init - update \main_converter1_counter $1\main_converter1_counter[0:0] - end - attribute \src "ls180.v:335.12-335.41" - process $proc$ls180.v:335$3189 - assign { } { } - assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] - end - attribute \src "ls180.v:3350.1-3357.4" - process $proc$ls180.v:3350$230 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3352.2-3356.5" - switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3352.6-3352.48" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3354.6-3354.10" - case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3355$232_Y - end - sync always - update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3361.1-3368.4" - process $proc$ls180.v:3361$239 - assign { } { } - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3363.2-3367.5" - switch $and$ls180.v:3363$240_Y - attribute \src "ls180.v:3363.6-3363.115" - case 1'1 - attribute \src "ls180.v:3364.3-3366.6" - switch $ne$ls180.v:3364$241_Y - attribute \src "ls180.v:3364.7-3364.143" - case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3365$242_Y - case - end - case - end - sync always - update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] - end - attribute \src "ls180.v:3383.1-3390.4" - process $proc$ls180.v:3383$243 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3385.2-3389.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3385.6-3385.58" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3386$244_Y - attribute \src "ls180.v:3387.6-3387.10" - case - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:339.5-339.24" - process $proc$ls180.v:339$3190 - assign { } { } - assign $1\main_int_rst[0:0] 1'1 - sync always - sync init - update \main_int_rst $1\main_int_rst[0:0] - end - attribute \src "ls180.v:3399.1-3492.4" - process $proc$ls180.v:3399$252 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3415.2-3491.9" - switch \builder_bankmachine0_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3417.4-3425.7" - switch $and$ls180.v:3417$253_Y - attribute \src "ls180.v:3417.8-3417.87" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3419.5-3421.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3419.9-3419.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3429.4-3431.7" - switch $and$ls180.v:3429$254_Y - attribute \src "ls180.v:3429.8-3429.87" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3435.4-3444.7" - switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3435.8-3435.44" - case 1'1 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3440.5-3442.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3440.9-3440.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3447.4-3449.7" - switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3447.8-3447.45" - case 1'1 - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3452.4-3454.7" - switch $not$ls180.v:3452$255_Y - attribute \src "ls180.v:3452.8-3452.46" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3463.4-3489.7" - switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3463.8-3463.43" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3465.8-3465.12" - case - attribute \src "ls180.v:3466.5-3488.8" - switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3466.9-3466.56" - case 1'1 - attribute \src "ls180.v:3467.6-3487.9" - switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3467.10-3467.44" - case 1'1 - attribute \src "ls180.v:3468.7-3484.10" - switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3468.11-3468.42" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3470.8-3477.11" - switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3470.12-3470.64" - case 1'1 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3474.12-3474.16" - case - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3479.8-3481.11" - switch $and$ls180.v:3479$256_Y - attribute \src "ls180.v:3479.12-3479.88" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3482.11-3482.15" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3485.10-3485.14" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] - update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] - update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] - update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] - update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:3507.1-3514.4" - process $proc$ls180.v:3507$260 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3509.2-3513.5" - switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3509.6-3509.48" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3511.6-3511.10" - case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3512$262_Y - end - sync always - update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3518.1-3525.4" - process $proc$ls180.v:3518$269 - assign { } { } - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3520.2-3524.5" - switch $and$ls180.v:3520$270_Y - attribute \src "ls180.v:3520.6-3520.115" - case 1'1 - attribute \src "ls180.v:3521.3-3523.6" - switch $ne$ls180.v:3521$271_Y - attribute \src "ls180.v:3521.7-3521.143" - case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3522$272_Y - case - end - case - end - sync always - update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:354.12-354.38" - process $proc$ls180.v:354$3191 - assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] - end - attribute \src "ls180.v:3540.1-3547.4" - process $proc$ls180.v:3540$273 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3542.2-3546.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3542.6-3542.58" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3543$274_Y - attribute \src "ls180.v:3544.6-3544.10" - case - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:355.5-355.36" - process $proc$ls180.v:355$3192 - assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:3556.1-3649.4" - process $proc$ls180.v:3556$282 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3572.2-3648.9" - switch \builder_bankmachine1_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3574.4-3582.7" - switch $and$ls180.v:3574$283_Y - attribute \src "ls180.v:3574.8-3574.87" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3576.5-3578.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3576.9-3576.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3586.4-3588.7" - switch $and$ls180.v:3586$284_Y - attribute \src "ls180.v:3586.8-3586.87" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3592.4-3601.7" - switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3592.8-3592.44" - case 1'1 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3597.5-3599.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3597.9-3597.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3604.4-3606.7" - switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3604.8-3604.45" - case 1'1 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3609.4-3611.7" - switch $not$ls180.v:3609$285_Y - attribute \src "ls180.v:3609.8-3609.46" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3620.4-3646.7" - switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3620.8-3620.43" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3622.8-3622.12" - case - attribute \src "ls180.v:3623.5-3645.8" - switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3623.9-3623.56" - case 1'1 - attribute \src "ls180.v:3624.6-3644.9" - switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3624.10-3624.44" - case 1'1 - attribute \src "ls180.v:3625.7-3641.10" - switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3625.11-3625.42" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3627.8-3634.11" - switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3627.12-3627.64" - case 1'1 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3631.12-3631.16" - case - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3636.8-3638.11" - switch $and$ls180.v:3636$286_Y - attribute \src "ls180.v:3636.12-3636.88" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3639.11-3639.15" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3642.10-3642.14" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] - update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] - update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] - update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] - update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:356.11-356.32" - process $proc$ls180.v:356$3193 - assign { } { } - assign $1\main_rddata_en[2:0] 3'000 - sync always - sync init - update \main_rddata_en $1\main_rddata_en[2:0] - end - attribute \src "ls180.v:359.5-359.36" - process $proc$ls180.v:359$3194 - assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] - end - attribute \src "ls180.v:360.5-360.35" - process $proc$ls180.v:360$3195 - assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] - end - attribute \src "ls180.v:361.5-361.36" - process $proc$ls180.v:361$3196 - assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] - end - attribute \src "ls180.v:362.5-362.35" - process $proc$ls180.v:362$3197 - assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:366.5-366.36" - process $proc$ls180.v:366$3198 - assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:3664.1-3671.4" - process $proc$ls180.v:3664$290 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3666.2-3670.5" - switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3666.6-3666.48" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3668.6-3668.10" - case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3669$292_Y - end - sync always - update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3675.1-3682.4" - process $proc$ls180.v:3675$299 - assign { } { } - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3677.2-3681.5" - switch $and$ls180.v:3677$300_Y - attribute \src "ls180.v:3677.6-3677.115" - case 1'1 - attribute \src "ls180.v:3678.3-3680.6" - switch $ne$ls180.v:3678$301_Y - attribute \src "ls180.v:3678.7-3678.143" - case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3679$302_Y - case - end - case - end - sync always - update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:3697.1-3704.4" - process $proc$ls180.v:3697$303 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3699.2-3703.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3699.6-3699.58" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3700$304_Y - attribute \src "ls180.v:3701.6-3701.10" - case - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:371.12-371.45" - process $proc$ls180.v:371$3199 - assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] - end - attribute \src "ls180.v:3713.1-3806.4" - process $proc$ls180.v:3713$312 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3729.2-3805.9" - switch \builder_bankmachine2_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3731.4-3739.7" - switch $and$ls180.v:3731$313_Y - attribute \src "ls180.v:3731.8-3731.87" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3733.5-3735.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3733.9-3733.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3743.4-3745.7" - switch $and$ls180.v:3743$314_Y - attribute \src "ls180.v:3743.8-3743.87" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3749.4-3758.7" - switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3749.8-3749.44" - case 1'1 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3754.5-3756.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3754.9-3754.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3761.4-3763.7" - switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3761.8-3761.45" - case 1'1 - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3766.4-3768.7" - switch $not$ls180.v:3766$315_Y - attribute \src "ls180.v:3766.8-3766.46" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine2_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3777.4-3803.7" - switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3777.8-3777.43" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3779.8-3779.12" - case - attribute \src "ls180.v:3780.5-3802.8" - switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3780.9-3780.56" - case 1'1 - attribute \src "ls180.v:3781.6-3801.9" - switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3781.10-3781.44" - case 1'1 - attribute \src "ls180.v:3782.7-3798.10" - switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3782.11-3782.42" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3784.8-3791.11" - switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3784.12-3784.64" - case 1'1 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3788.12-3788.16" - case - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3793.8-3795.11" - switch $and$ls180.v:3793$316_Y - attribute \src "ls180.v:3793.12-3793.88" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3796.11-3796.15" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3799.10-3799.14" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] - update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] - update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] - update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] - update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:372.5-372.43" - process $proc$ls180.v:372$3200 - assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:3821.1-3828.4" - process $proc$ls180.v:3821$320 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3823.2-3827.5" - switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3823.6-3823.48" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3825.6-3825.10" - case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3826$322_Y - end - sync always - update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3832.1-3839.4" - process $proc$ls180.v:3832$329 - assign { } { } - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3834.2-3838.5" - switch $and$ls180.v:3834$330_Y - attribute \src "ls180.v:3834.6-3834.115" - case 1'1 - attribute \src "ls180.v:3835.3-3837.6" - switch $ne$ls180.v:3835$331_Y - attribute \src "ls180.v:3835.7-3835.143" - case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3836$332_Y - case - end - case - end - sync always - update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:3854.1-3861.4" - process $proc$ls180.v:3854$333 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3856.2-3860.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3856.6-3856.58" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3857$334_Y - attribute \src "ls180.v:3858.6-3858.10" - case - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:387.12-387.46" - process $proc$ls180.v:387$3201 - assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:3870.1-3963.4" - process $proc$ls180.v:3870$342 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3886.2-3962.9" - switch \builder_bankmachine3_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3888.4-3896.7" - switch $and$ls180.v:3888$343_Y - attribute \src "ls180.v:3888.8-3888.87" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3890.5-3892.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3890.9-3890.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3900.4-3902.7" - switch $and$ls180.v:3900$344_Y - attribute \src "ls180.v:3900.8-3900.87" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3906.4-3915.7" - switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3906.8-3906.44" - case 1'1 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3911.5-3913.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3911.9-3911.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3918.4-3920.7" - switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3918.8-3918.45" - case 1'1 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3923.4-3925.7" - switch $not$ls180.v:3923$345_Y - attribute \src "ls180.v:3923.8-3923.46" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3934.4-3960.7" - switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3934.8-3934.43" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3936.8-3936.12" - case - attribute \src "ls180.v:3937.5-3959.8" - switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3937.9-3937.56" - case 1'1 - attribute \src "ls180.v:3938.6-3958.9" - switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3938.10-3938.44" - case 1'1 - attribute \src "ls180.v:3939.7-3955.10" - switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3939.11-3939.42" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3941.8-3948.11" - switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3941.12-3941.64" - case 1'1 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3945.12-3945.16" - case - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3950.8-3952.11" - switch $and$ls180.v:3950$346_Y - attribute \src "ls180.v:3950.12-3950.88" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3953.11-3953.15" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3956.10-3956.14" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] - update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] - update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] - update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] - update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:388.5-388.44" - process $proc$ls180.v:388$3202 - assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:389.12-389.48" - process $proc$ls180.v:389$3203 - assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] - end - attribute \src "ls180.v:390.11-390.43" - process $proc$ls180.v:390$3204 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:391.5-391.38" - process $proc$ls180.v:391$3205 - assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] - end - attribute \src "ls180.v:392.5-392.37" - process $proc$ls180.v:392$3206 - assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] - end - attribute \src "ls180.v:393.5-393.38" - process $proc$ls180.v:393$3207 - assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] - end - attribute \src "ls180.v:394.5-394.37" - process $proc$ls180.v:394$3208 - assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] - end - attribute \src "ls180.v:395.5-395.36" - process $proc$ls180.v:395$3209 - assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] - end - attribute \src "ls180.v:396.5-396.36" - process $proc$ls180.v:396$3210 - assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] - end - attribute \src "ls180.v:397.5-397.40" - process $proc$ls180.v:397$3211 - assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] - end - attribute \src "ls180.v:398.5-398.38" - process $proc$ls180.v:398$3212 - assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:3983.1-3989.4" - process $proc$ls180.v:3983$385 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3985$398_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3986$411_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3987$424_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3988$437_Y - sync always - update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] - end - attribute \src "ls180.v:399.12-399.47" - process $proc$ls180.v:399$3213 - assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] - end - attribute \src "ls180.v:3997.1-4002.4" - process $proc$ls180.v:3997$438 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3999.2-4001.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3999.6-3999.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:400.5-400.42" - process $proc$ls180.v:400$3214 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:4003.1-4008.4" - process $proc$ls180.v:4003$439 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:4005.2-4007.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:4005.6-4005.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:4009.1-4014.4" - process $proc$ls180.v:4009$440 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:4011.2-4013.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:4011.6-4011.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:401.11-401.50" - process $proc$ls180.v:401$3215 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] - end - attribute \src "ls180.v:4016.1-4022.4" - process $proc$ls180.v:4016$443 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:4018$456_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:4019$469_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:4020$482_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:4021$495_Y - sync always - update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] - end - attribute \src "ls180.v:402.5-402.42" - process $proc$ls180.v:402$3216 - assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:4030.1-4035.4" - process $proc$ls180.v:4030$496 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:4032.2-4034.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4032.6-4032.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:4036.1-4041.4" - process $proc$ls180.v:4036$497 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:4038.2-4040.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4038.6-4038.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:4042.1-4047.4" - process $proc$ls180.v:4042$498 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:4044.2-4046.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4044.6-4044.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] - end - attribute \src "ls180.v:4048.1-4056.4" - process $proc$ls180.v:4048$499 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4050.2-4052.5" - switch $and$ls180.v:4050$502_Y - attribute \src "ls180.v:4050.6-4050.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:4053.2-4055.5" - switch $and$ls180.v:4053$505_Y - attribute \src "ls180.v:4053.6-4053.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:4057.1-4065.4" - process $proc$ls180.v:4057$506 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4059.2-4061.5" - switch $and$ls180.v:4059$509_Y - attribute \src "ls180.v:4059.6-4059.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:4062.2-4064.5" - switch $and$ls180.v:4062$512_Y - attribute \src "ls180.v:4062.6-4062.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:4066.1-4074.4" - process $proc$ls180.v:4066$513 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4068.2-4070.5" - switch $and$ls180.v:4068$516_Y - attribute \src "ls180.v:4068.6-4068.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:4071.2-4073.5" - switch $and$ls180.v:4071$519_Y - attribute \src "ls180.v:4071.6-4071.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:4075.1-4083.4" - process $proc$ls180.v:4075$520 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4077.2-4079.5" - switch $and$ls180.v:4077$523_Y - attribute \src "ls180.v:4077.6-4077.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:4080.2-4082.5" - switch $and$ls180.v:4080$526_Y - attribute \src "ls180.v:4080.6-4080.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:4088.1-4160.4" - process $proc$ls180.v:4088$529 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_en1[0:0] 1'0 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 - assign $0\main_sdram_cmd_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdram_steerer_sel[1:0] 2'00 - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 - assign $0\main_sdram_en0[0:0] 1'0 - assign { } { } - assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed - assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:4100.2-4159.9" - switch \builder_multiplexer_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_en1[0:0] 1'1 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4104.4-4110.7" - switch 1'1 - attribute \src "ls180.v:4104.8-4104.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4105$536_Y - case - end - attribute \src "ls180.v:4112.4-4116.7" - switch \main_sdram_read_available - attribute \src "ls180.v:4112.8-4112.33" - case 1'1 - attribute \src "ls180.v:4113.5-4115.8" - switch $or$ls180.v:4113$538_Y - attribute \src "ls180.v:4113.9-4113.63" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'011 - case - end - case - end - attribute \src "ls180.v:4117.4-4119.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4117.8-4117.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_steerer_sel[1:0] 2'11 - assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:4124.4-4126.7" - switch \main_sdram_cmd_last - attribute \src "ls180.v:4124.8-4124.27" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:4129.4-4131.7" - switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:4129.8-4129.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_multiplexer_next_state[2:0] 3'101 - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_multiplexer_next_state[2:0] 3'001 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_en0[0:0] 1'1 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4142.4-4148.7" - switch 1'1 - attribute \src "ls180.v:4142.8-4142.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4143$545_Y - case - end - attribute \src "ls180.v:4150.4-4154.7" - switch \main_sdram_write_available - attribute \src "ls180.v:4150.8-4150.34" - case 1'1 - attribute \src "ls180.v:4151.5-4153.8" - switch $or$ls180.v:4151$547_Y - attribute \src "ls180.v:4151.9-4151.62" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'100 - case - end - case - end - attribute \src "ls180.v:4155.4-4157.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4155.8-4155.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - end - sync always - update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] - update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] - update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] - update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] - update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] - update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] - update \main_sdram_en0 $0\main_sdram_en0[0:0] - update \main_sdram_en1 $0\main_sdram_en1[0:0] - update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:409.11-409.36" - process $proc$ls180.v:409$3217 - assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 - sync always - sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] - end - attribute \src "ls180.v:410.5-410.25" - process $proc$ls180.v:410$3218 - assign { } { } - assign $1\main_sdram_re[0:0] 1'0 - sync always - sync init - update \main_sdram_re $1\main_sdram_re[0:0] - end - attribute \src "ls180.v:411.11-411.44" - process $proc$ls180.v:411$3219 - assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 - sync always - sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] - end - attribute \src "ls180.v:412.5-412.33" - process $proc$ls180.v:412$3220 - assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 - sync always - sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] - end - attribute \src "ls180.v:416.5-416.38" - process $proc$ls180.v:416$3221 - assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 - sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] - sync init - end - attribute \src "ls180.v:417.12-417.46" - process $proc$ls180.v:417$3222 - assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] - end - attribute \src "ls180.v:418.5-418.33" - process $proc$ls180.v:418$3223 - assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 - sync always - sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] - end - attribute \src "ls180.v:4184.1-4197.4" - process $proc$ls180.v:4184$676 - assign { } { } - assign { } { } - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:4187.2-4196.9" - switch \builder_new_master_wdata_ready - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data - assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - end - sync always - update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] - update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:419.11-419.45" - process $proc$ls180.v:419$3224 - assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 - sync always - sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] - end - attribute \src "ls180.v:420.5-420.34" - process $proc$ls180.v:420$3225 - assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 - sync always - sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] - end - attribute \src "ls180.v:4204.1-4214.4" - process $proc$ls180.v:4204$678 - assign { } { } - assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:4206.2-4213.9" - switch \main_converter_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] - case - end - sync always - update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] - end - attribute \src "ls180.v:421.12-421.45" - process $proc$ls180.v:421$3226 - assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] - end - attribute \src "ls180.v:4216.1-4262.4" - process $proc$ls180.v:4216$679 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_litedram_wb_sel[1:0] 2'00 - assign $0\main_litedram_wb_cyc[0:0] 1'0 - assign { } { } - assign $0\main_litedram_wb_stb[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 - assign $0\main_litedram_wb_we[0:0] 1'0 - assign $0\main_converter_skip[0:0] 1'0 - assign $0\main_wb_sdram_ack[0:0] 1'0 - assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4228.2-4261.9" - switch \builder_converter_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4231.4-4238.11" - switch \main_converter_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] - case - end - attribute \src "ls180.v:4239.4-4252.7" - switch $and$ls180.v:4239$680_Y - attribute \src "ls180.v:4239.8-4239.47" - case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4240$681_Y - assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4242$682_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4243$683_Y - attribute \src "ls180.v:4244.5-4251.8" - switch $or$ls180.v:4244$684_Y - attribute \src "ls180.v:4244.9-4244.53" - case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4245$685_Y - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4247.6-4250.9" - switch $eq$ls180.v:4247$686_Y - attribute \src "ls180.v:4247.10-4247.42" - case 1'1 - assign $0\main_wb_sdram_ack[0:0] 1'1 - assign $0\builder_converter_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4257.4-4259.7" - switch $and$ls180.v:4257$687_Y - attribute \src "ls180.v:4257.8-4257.47" - case 1'1 - assign $0\builder_converter_next_state[0:0] 1'1 - case - end - end - sync always - update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] - update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] - update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] - update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] - update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] - update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] - update \main_converter_skip $0\main_converter_skip[0:0] - update \builder_converter_next_state $0\builder_converter_next_state[0:0] - update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] - update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:422.5-422.32" - process $proc$ls180.v:422$3227 - assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 - sync always - sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] - end - attribute \src "ls180.v:423.12-423.37" - process $proc$ls180.v:423$3228 - assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_status $1\main_sdram_status[15:0] - end - attribute \src "ls180.v:4307.1-4312.4" - process $proc$ls180.v:4307$719 - assign { } { } - assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4309.2-4311.5" - switch $and$ls180.v:4309$720_Y - attribute \src "ls180.v:4309.6-4309.79" - case 1'1 - assign $0\main_uart_tx_clear[0:0] 1'1 - case - end - sync always - update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] - end - attribute \src "ls180.v:4313.1-4317.4" - process $proc$ls180.v:4313$721 - assign { } { } - assign { } { } - assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status - assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status - sync always - update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] - end - attribute \src "ls180.v:4318.1-4323.4" - process $proc$ls180.v:4318$722 - assign { } { } - assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4320.2-4322.5" - switch $and$ls180.v:4320$723_Y - attribute \src "ls180.v:4320.6-4320.79" - case 1'1 - assign $0\main_uart_rx_clear[0:0] 1'1 - case - end - sync always - update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] - end - attribute \src "ls180.v:4324.1-4328.4" - process $proc$ls180.v:4324$724 - assign { } { } - assign { } { } - assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending - assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending - sync always - update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] - end - attribute \src "ls180.v:4346.1-4353.4" - process $proc$ls180.v:4346$732 - assign { } { } - assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4348.2-4352.5" - switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4348.6-4348.31" - case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4349$733_Y - attribute \src "ls180.v:4350.6-4350.10" - case - assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce - end - sync always - update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:4376.1-4383.4" - process $proc$ls180.v:4376$743 - assign { } { } - assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4378.2-4382.5" - switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4378.6-4378.31" - case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4379$744_Y - attribute \src "ls180.v:4380.6-4380.10" - case - assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce - end - sync always - update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:4396.1-4400.4" - process $proc$ls180.v:4396$750 - assign { } { } - assign { } { } - assign { } { } - assign $0\gpio_o[15:0] \main_gpiotristateasic1_pads_o - sync always - update \gpio_o $0\gpio_o[15:0] - end - attribute \src "ls180.v:4401.1-4405.4" - process $proc$ls180.v:4401$751 - assign { } { } - assign { } { } - assign { } { } - assign $0\gpio_oe[15:0] \main_gpiotristateasic1_pads_oe - sync always - update \gpio_oe $0\gpio_oe[15:0] - end - attribute \src "ls180.v:4417.1-4465.4" - process $proc$ls180.v:4417$756 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 - assign $0\main_spimaster25_clk_enable[0:0] 1'0 - assign $0\main_spimaster26_cs_enable[0:0] 1'0 - assign $0\main_spimaster28_mosi_latch[0:0] 1'0 - assign $0\main_spimaster2_done[0:0] 1'0 - assign $0\main_spimaster29_miso_latch[0:0] 1'0 - assign $0\main_spimaster3_irq[0:0] 1'0 - assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4428.2-4464.9" - switch \builder_spimaster0_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4432.4-4435.7" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4432.8-4432.33" - case 1'1 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_spimaster25_clk_enable[0:0] 1'1 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4440.4-4446.7" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4440.8-4440.33" - case 1'1 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4441$757_Y - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4443.5-4445.8" - switch $eq$ls180.v:4443$759_Y - attribute \src "ls180.v:4443.9-4443.68" - case 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4450.4-4454.7" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:4450.8-4450.33" - case 1'1 - assign $0\main_spimaster29_miso_latch[0:0] 1'1 - assign $0\main_spimaster3_irq[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_spimaster2_done[0:0] 1'1 - attribute \src "ls180.v:4458.4-4462.7" - switch \main_spimaster0_start - attribute \src "ls180.v:4458.8-4458.29" - case 1'1 - assign $0\main_spimaster2_done[0:0] 1'0 - assign $0\main_spimaster28_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'01 - case - end - end - sync always - update \main_spimaster2_done $0\main_spimaster2_done[0:0] - update \main_spimaster3_irq $0\main_spimaster3_irq[0:0] - update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0] - update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0] - update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0] - update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0] - update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] - update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] - update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:4476.1-4524.4" - process $proc$ls180.v:4476$764 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_spisdcard_clk_enable[0:0] 1'0 - assign $0\main_spisdcard_cs_enable[0:0] 1'0 - assign $0\main_spisdcard_mosi_latch[0:0] 1'0 - assign $0\main_spisdcard_done0[0:0] 1'0 - assign $0\main_spisdcard_miso_latch[0:0] 1'0 - assign $0\main_spisdcard_irq[0:0] 1'0 - assign { } { } - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 - assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:4487.2-4523.9" - switch \builder_spimaster1_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4491.4-4494.7" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4491.8-4491.31" - case 1'1 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_spisdcard_clk_enable[0:0] 1'1 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4499.4-4505.7" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4499.8-4499.31" - case 1'1 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4500$765_Y - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4502.5-4504.8" - switch $eq$ls180.v:4502$767_Y - attribute \src "ls180.v:4502.9-4502.66" - case 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4509.4-4513.7" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:4509.8-4509.31" - case 1'1 - assign $0\main_spisdcard_miso_latch[0:0] 1'1 - assign $0\main_spisdcard_irq[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_spisdcard_done0[0:0] 1'1 - attribute \src "ls180.v:4517.4-4521.7" - switch \main_spisdcard_start0 - attribute \src "ls180.v:4517.8-4517.29" - case 1'1 - assign $0\main_spisdcard_done0[0:0] 1'0 - assign $0\main_spisdcard_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'01 - case - end - end - sync always - update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0] - update \main_spisdcard_irq $0\main_spisdcard_irq[0:0] - update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0] - update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0] - update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0] - update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0] - update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] - update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] - update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:453.12-453.46" - process $proc$ls180.v:453$3229 - assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] - end - attribute \src "ls180.v:454.11-454.47" - process $proc$ls180.v:454$3230 - assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 - sync always - sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:4556.1-4584.4" - process $proc$ls180.v:4556$789 - assign { } { } - assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4558.2-4583.9" - switch \main_sdphy_clocker_storage - attribute \src "ls180.v:0.0-0.0" - case 9'000000100 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] - attribute \src "ls180.v:0.0-0.0" - case 9'000001000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] - attribute \src "ls180.v:0.0-0.0" - case 9'000010000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] - attribute \src "ls180.v:0.0-0.0" - case 9'000100000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] - attribute \src "ls180.v:0.0-0.0" - case 9'001000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] - attribute \src "ls180.v:0.0-0.0" - case 9'010000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] - attribute \src "ls180.v:0.0-0.0" - case 9'100000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] - end - sync always - update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] - end - attribute \src "ls180.v:456.12-456.45" - process $proc$ls180.v:456$3231 - assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] - end - attribute \src "ls180.v:457.11-457.40" - process $proc$ls180.v:457$3232 - assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] - end - attribute \src "ls180.v:458.5-458.35" - process $proc$ls180.v:458$3233 - assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] - end - attribute \src "ls180.v:4586.1-4619.4" - process $proc$ls180.v:4586$792 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4596.2-4618.9" - switch \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4603.4-4609.7" - switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4603.8-4603.38" - case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4604$793_Y - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4606.5-4608.8" - switch $eq$ls180.v:4606$794_Y - attribute \src "ls180.v:4606.9-4606.41" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4614.4-4616.7" - switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4614.8-4614.37" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 - case - end - end - sync always - update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] - update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] - update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] - update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - end - attribute \src "ls180.v:459.5-459.34" - process $proc$ls180.v:459$3234 - assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] - end - attribute \src "ls180.v:460.5-460.35" - process $proc$ls180.v:460$3235 - assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] - end - attribute \src "ls180.v:461.5-461.34" - process $proc$ls180.v:461$3236 - assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] - end - attribute \src "ls180.v:4620.1-4696.4" - process $proc$ls180.v:4620$795 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_cmdw_done[0:0] 1'0 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4630.2-4695.9" - switch \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4634.4-4659.11" - switch \main_sdphy_cmdw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] - attribute \src "ls180.v:0.0-0.0" - case 8'00000010 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] - attribute \src "ls180.v:0.0-0.0" - case 8'00000011 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000100 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] - attribute \src "ls180.v:0.0-0.0" - case 8'00000101 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] - attribute \src "ls180.v:0.0-0.0" - case 8'00000110 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] - attribute \src "ls180.v:0.0-0.0" - case 8'00000111 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] - case - end - attribute \src "ls180.v:4660.4-4671.7" - switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4660.8-4660.38" - case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4661$796_Y - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4663.5-4670.8" - switch $eq$ls180.v:4663$797_Y - attribute \src "ls180.v:4663.9-4663.40" - case 1'1 - attribute \src "ls180.v:4664.6-4669.9" - switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4664.10-4664.35" - case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4666.10-4666.14" - case - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4677.4-4684.7" - switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4677.8-4677.38" - case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4678$798_Y - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4680.5-4683.8" - switch $eq$ls180.v:4680$799_Y - attribute \src "ls180.v:4680.9-4680.40" - case 1'1 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4689.4-4693.7" - switch $and$ls180.v:4689$800_Y - attribute \src "ls180.v:4689.8-4689.69" - case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4691.8-4691.12" - case - assign $0\main_sdphy_cmdw_done[0:0] 1'1 - end - end - sync always - update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] - update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] - update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:465.5-465.35" - process $proc$ls180.v:465$3237 - assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:467.5-467.39" - process $proc$ls180.v:467$3238 - assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:469.5-469.39" - process $proc$ls180.v:469$3239 - assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] - end - attribute \src "ls180.v:472.5-472.32" - process $proc$ls180.v:472$3240 - assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] - end - attribute \src "ls180.v:473.5-473.32" - process $proc$ls180.v:473$3241 - assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] - end - attribute \src "ls180.v:4730.1-4823.4" - process $proc$ls180.v:4730$809 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign { } { } - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4748.2-4822.9" - switch \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4756$810_Y - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4753.4-4755.7" - switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4753.8-4753.49" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:4758.4-4761.7" - switch $eq$ls180.v:4758$811_Y - attribute \src "ls180.v:4758.8-4758.41" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4767$813_Y - assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4784$816_Y - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4769.4-4783.7" - switch $and$ls180.v:4769$814_Y - attribute \src "ls180.v:4769.8-4769.69" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4771$815_Y - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4773.5-4782.8" - switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4773.9-4773.36" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4775.6-4781.9" - switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4775.10-4775.35" - case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4779.10-4779.14" - case - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - end - case - end - case - end - attribute \src "ls180.v:4786.4-4789.7" - switch $eq$ls180.v:4786$817_Y - attribute \src "ls180.v:4786.8-4786.41" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4795.4-4801.7" - switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4795.8-4795.38" - case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4796$818_Y - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4798.5-4800.8" - switch $eq$ls180.v:4798$819_Y - attribute \src "ls180.v:4798.9-4798.40" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 - assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4807.4-4809.7" - switch $and$ls180.v:4807$820_Y - attribute \src "ls180.v:4807.8-4807.69" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4816.4-4820.7" - switch $and$ls180.v:4816$822_Y - attribute \src "ls180.v:4816.8-4816.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 - case - end - end - sync always - update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] - update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] - update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] - update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] - update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] - update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - end - attribute \src "ls180.v:474.5-474.31" - process $proc$ls180.v:474$3242 - assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] - end - attribute \src "ls180.v:475.12-475.44" - process $proc$ls180.v:475$3243 - assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] - end - attribute \src "ls180.v:476.11-476.43" - process $proc$ls180.v:476$3244 - assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 - sync always - sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] - end - attribute \src "ls180.v:477.5-477.38" - process $proc$ls180.v:477$3245 - assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:478.5-478.38" - process $proc$ls180.v:478$3246 - assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:479.5-479.37" - process $proc$ls180.v:479$3247 - assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] - end - attribute \src "ls180.v:480.5-480.42" - process $proc$ls180.v:480$3248 - assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] - sync init - end - attribute \src "ls180.v:481.5-481.43" - process $proc$ls180.v:481$3249 - assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] - sync init - end - attribute \src "ls180.v:4857.1-4884.4" - process $proc$ls180.v:4857$830 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_dataw_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_error[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4865.2-4883.9" - switch \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4870.4-4874.7" - switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4870.8-4870.50" - case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4871$831_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4872$832_Y - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 - case - end - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:4877.4-4881.7" - switch \main_sdphy_dataw_start - attribute \src "ls180.v:4877.8-4877.30" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 - case - end - end - sync always - update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] - update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] - update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - end - attribute \src "ls180.v:487.11-487.44" - process $proc$ls180.v:487$3250 - assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 - sync always - sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] - end - attribute \src "ls180.v:4885.1-4957.4" - process $proc$ls180.v:4885$833 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_dataw_start[0:0] 1'0 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_stop[0:0] 1'0 - assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4896.2-4956.9" - switch \builder_sdphy_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4901.4-4903.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4901.8-4901.39" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4906$834_Y - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4909.4-4916.11" - switch \main_sdphy_dataw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] - case - end - attribute \src "ls180.v:4917.4-4929.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4917.8-4917.39" - case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4918$835_Y - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4920.5-4928.8" - switch $eq$ls180.v:4920$836_Y - attribute \src "ls180.v:4920.9-4920.41" - case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4923.6-4927.9" - switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4923.10-4923.36" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4925.10-4925.14" - case - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4935.4-4938.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4935.8-4935.39" - case 1'1 - assign $0\main_sdphy_dataw_start[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4942.4-4947.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4942.8-4942.39" - case 1'1 - attribute \src "ls180.v:4943.5-4946.8" - switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4943.9-4943.51" - case 1'1 - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4952.4-4954.7" - switch $and$ls180.v:4952$837_Y - attribute \src "ls180.v:4952.8-4952.71" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 - case - end - end - sync always - update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] - update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] - update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] - update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] - update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:489.5-489.38" - process $proc$ls180.v:489$3251 - assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 - sync always - sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] - end - attribute \src "ls180.v:490.5-490.38" - process $proc$ls180.v:490$3252 - assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] - end - attribute \src "ls180.v:491.5-491.39" - process $proc$ls180.v:491$3253 - assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] - end - attribute \src "ls180.v:494.5-494.38" - process $proc$ls180.v:494$3254 - assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] - end - attribute \src "ls180.v:495.11-495.46" - process $proc$ls180.v:495$3255 - assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 - sync always - sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] - end - attribute \src "ls180.v:496.5-496.38" - process $proc$ls180.v:496$3256 - assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] - end - attribute \src "ls180.v:4991.1-5092.4" - process $proc$ls180.v:4991$845 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_datar_stop[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_datar_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_datar_source_last[0:0] 1'0 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:5008.2-5091.9" - switch \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign { } { } - assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5018$847_Y - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:5015.4-5017.7" - switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:5015.8-5015.51" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:5020.4-5023.7" - switch $eq$ls180.v:5020$848_Y - attribute \src "ls180.v:5020.8-5020.42" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:5029$851_Y - assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5050$853_Y - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:5031.4-5049.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5031.8-5031.37" - case 1'1 - attribute \src "ls180.v:5032.5-5048.8" - switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:5032.9-5032.38" - case 1'1 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5034$852_Y - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5036.6-5045.9" - switch \main_sdphy_datar_source_last - attribute \src "ls180.v:5036.10-5036.38" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5038.7-5044.10" - switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:5038.11-5038.37" - case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:5042.11-5042.15" - case - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - end - case - end - attribute \src "ls180.v:5046.9-5046.13" - case - assign $0\main_sdphy_datar_stop[0:0] 1'1 - end - case - end - attribute \src "ls180.v:5052.4-5055.7" - switch $eq$ls180.v:5052$854_Y - attribute \src "ls180.v:5052.8-5052.42" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:5059.4-5065.7" - switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:5059.8-5059.39" - case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5060$855_Y - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5062.5-5064.8" - switch $eq$ls180.v:5062$856_Y - attribute \src "ls180.v:5062.9-5062.42" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_datar_source_valid[0:0] 1'1 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 - assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:5071.4-5073.7" - switch $and$ls180.v:5071$857_Y - attribute \src "ls180.v:5071.8-5071.71" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5078.4-5089.7" - switch $and$ls180.v:5078$858_Y - attribute \src "ls180.v:5078.8-5078.71" - case 1'1 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:5080.5-5088.8" - switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:5080.9-5080.40" - case 1'1 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 - case - end - case - end - end - sync always - update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] - update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] - update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] - update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] - update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] - update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] - update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] - update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] - update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:502.5-502.51" - process $proc$ls180.v:502$3257 - assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - end - attribute \src "ls180.v:503.5-503.51" - process $proc$ls180.v:503$3258 - assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - end - attribute \src "ls180.v:505.5-505.47" - process $proc$ls180.v:505$3259 - assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] - end - attribute \src "ls180.v:506.5-506.45" - process $proc$ls180.v:506$3260 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] - end - attribute \src "ls180.v:507.5-507.45" - process $proc$ls180.v:507$3261 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:508.12-508.57" - process $proc$ls180.v:508$3262 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:510.5-510.51" - process $proc$ls180.v:510$3263 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:511.5-511.51" - process $proc$ls180.v:511$3264 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:512.5-512.50" - process $proc$ls180.v:512$3265 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - end - attribute \src "ls180.v:513.5-513.54" - process $proc$ls180.v:513$3266 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:514.5-514.55" - process $proc$ls180.v:514$3267 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:515.5-515.56" - process $proc$ls180.v:515$3268 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:5150.1-5157.4" - process $proc$ls180.v:5150$980 - assign { } { } - assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:5152.2-5156.5" - switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:5152.6-5152.38" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:5154.6-5154.10" - case - assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 - end - sync always - update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:516.5-516.50" - process $proc$ls180.v:516$3269 - assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] - end - attribute \src "ls180.v:5172.1-5179.4" - process $proc$ls180.v:5172$1003 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5174.2-5178.5" - switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:5174.6-5174.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:5176.6-5176.10" - case - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:5182.1-5189.4" - process $proc$ls180.v:5182$1014 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5184.2-5188.5" - switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:5184.6-5184.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:5186.6-5186.10" - case - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:519.5-519.67" - process $proc$ls180.v:519$3270 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:5192.1-5199.4" - process $proc$ls180.v:5192$1025 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5194.2-5198.5" - switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:5194.6-5194.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:5196.6-5196.10" - case - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:520.5-520.66" - process $proc$ls180.v:520$3271 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:5202.1-5209.4" - process $proc$ls180.v:5202$1036 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5204.2-5208.5" - switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:5204.6-5204.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:5206.6-5206.10" - case - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:5210.1-5289.4" - process $proc$ls180.v:5210$1037 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:5227.2-5288.9" - switch \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:5231.4-5233.7" - switch $eq$ls180.v:5231$1038_Y - attribute \src "ls180.v:5231.8-5231.48" - case 1'1 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 - case - end - attribute \src "ls180.v:5234.4-5259.11" - switch \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } - case - end - attribute \src "ls180.v:5260.4-5267.7" - switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:5260.8-5260.47" - case 1'1 - attribute \src "ls180.v:5261.5-5266.8" - switch $eq$ls180.v:5261$1039_Y - attribute \src "ls180.v:5261.9-5261.49" - case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:5263.9-5263.13" - case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5264$1040_Y - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5282.4-5286.7" - switch $and$ls180.v:5282$1042_Y - attribute \src "ls180.v:5282.8-5282.128" - case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 - case - end - end - sync always - update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] - update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] - update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] - update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - end - attribute \src "ls180.v:5290.1-5295.4" - process $proc$ls180.v:5290$1043 - assign { } { } - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:5292.2-5294.5" - switch $and$ls180.v:5292$1050_Y - attribute \src "ls180.v:5292.6-5292.301" - case 1'1 - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 - case - end - sync always - update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] - end - attribute \src "ls180.v:5298.1-5305.4" - process $proc$ls180.v:5298$1052 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5300.2-5304.5" - switch $eq$ls180.v:5300$1053_Y - attribute \src "ls180.v:5300.6-5300.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5302.6-5302.10" - case - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] - end - attribute \src "ls180.v:5308.1-5315.4" - process $proc$ls180.v:5308$1055 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5310.2-5314.5" - switch $eq$ls180.v:5310$1056_Y - attribute \src "ls180.v:5310.6-5310.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5312.6-5312.10" - case - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] - end - attribute \src "ls180.v:5318.1-5325.4" - process $proc$ls180.v:5318$1058 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5320.2-5324.5" - switch $eq$ls180.v:5320$1059_Y - attribute \src "ls180.v:5320.6-5320.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5322.6-5322.10" - case - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] - end - attribute \src "ls180.v:5328.1-5335.4" - process $proc$ls180.v:5328$1061 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5330.2-5334.5" - switch $eq$ls180.v:5330$1062_Y - attribute \src "ls180.v:5330.6-5330.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5332.6-5332.10" - case - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] - end - attribute \src "ls180.v:5337.1-5342.4" - process $proc$ls180.v:5337$1063 - assign { } { } - assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5339.2-5341.5" - switch $and$ls180.v:5339$1065_Y - attribute \src "ls180.v:5339.6-5339.85" - case 1'1 - assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 - case - end - sync always - update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] - end - attribute \src "ls180.v:5343.1-5350.4" - process $proc$ls180.v:5343$1066 - assign { } { } - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5345.2-5349.5" - switch $lt$ls180.v:5345$1067_Y - attribute \src "ls180.v:5345.6-5345.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5347.6-5347.10" - case - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready - end - sync always - update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] - end - attribute \src "ls180.v:535.11-535.68" - process $proc$ls180.v:535$3272 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:5354.1-5361.4" - process $proc$ls180.v:5354$1078 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5356.2-5360.5" - switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5356.6-5356.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5358.6-5358.10" - case - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:536.5-536.64" - process $proc$ls180.v:536$3273 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:5364.1-5371.4" - process $proc$ls180.v:5364$1089 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5366.2-5370.5" - switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5366.6-5366.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5368.6-5368.10" - case - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] - end - attribute \src "ls180.v:537.11-537.70" - process $proc$ls180.v:537$3274 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:5374.1-5381.4" - process $proc$ls180.v:5374$1100 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5376.2-5380.5" - switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5376.6-5376.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5378.6-5378.10" - case - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] - end - attribute \src "ls180.v:538.11-538.70" - process $proc$ls180.v:538$3275 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:5384.1-5391.4" - process $proc$ls180.v:5384$1111 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5386.2-5390.5" - switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5386.6-5386.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5388.6-5388.10" - case - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] - end - attribute \src "ls180.v:539.11-539.73" - process $proc$ls180.v:539$3276 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:5392.1-5582.4" - process $proc$ls180.v:5392$1112 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - assign { } { } - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 - assign $0\main_sdphy_datar_sink_last[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 - assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 - assign $0\main_sdphy_datar_source_ready[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 - assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5433.2-5581.9" - switch \builder_sdcore_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5436.4-5456.11" - switch \main_sdcore_cmd_count - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5454$1113_Y - case - end - attribute \src "ls180.v:5457.4-5469.7" - switch $and$ls180.v:5457$1114_Y - attribute \src "ls180.v:5457.8-5457.65" - case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5458$1115_Y - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5460.5-5468.8" - switch $eq$ls180.v:5460$1116_Y - attribute \src "ls180.v:5460.9-5460.40" - case 1'1 - attribute \src "ls180.v:5461.6-5467.9" - switch $eq$ls180.v:5461$1117_Y - attribute \src "ls180.v:5461.10-5461.40" - case 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5465.10-5465.14" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5473$1118_Y - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5474.4-5478.7" - switch $eq$ls180.v:5474$1119_Y - attribute \src "ls180.v:5474.8-5474.38" - case 1'1 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5476.8-5476.12" - case - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 - end - attribute \src "ls180.v:5480.4-5501.7" - switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5480.8-5480.36" - case 1'1 - attribute \src "ls180.v:5481.5-5500.8" - switch $eq$ls180.v:5481$1120_Y - attribute \src "ls180.v:5481.9-5481.56" - case 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5485.9-5485.13" - case - attribute \src "ls180.v:5486.6-5499.9" - switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5486.10-5486.37" - case 1'1 - attribute \src "ls180.v:5487.7-5495.10" - switch $eq$ls180.v:5487$1121_Y - attribute \src "ls180.v:5487.11-5487.42" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5489.11-5489.15" - case - attribute \src "ls180.v:5490.8-5494.11" - switch $eq$ls180.v:5490$1122_Y - attribute \src "ls180.v:5490.12-5490.43" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5492.12-5492.16" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - end - end - attribute \src "ls180.v:5496.10-5496.14" - case - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready - assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first - assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last - assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data - assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5509.4-5515.7" - switch $and$ls180.v:5509$1124_Y - attribute \src "ls180.v:5509.8-5509.98" - case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5510$1125_Y - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5512.5-5514.8" - switch $eq$ls180.v:5512$1127_Y - attribute \src "ls180.v:5512.9-5512.77" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:5517.4-5522.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5517.8-5517.37" - case 1'1 - attribute \src "ls180.v:5518.5-5521.8" - switch $ne$ls180.v:5518$1128_Y - attribute \src "ls180.v:5518.9-5518.57" - case 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5527$1130_Y - attribute \src "ls180.v:5528.4-5554.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5528.8-5528.37" - case 1'1 - attribute \src "ls180.v:5529.5-5553.8" - switch $eq$ls180.v:5529$1131_Y - attribute \src "ls180.v:5529.9-5529.57" - case 1'1 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid - assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready - assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first - assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5535.6-5543.9" - switch $and$ls180.v:5535$1132_Y - attribute \src "ls180.v:5535.10-5535.72" - case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5536$1133_Y - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5538.7-5542.10" - switch $eq$ls180.v:5538$1135_Y - attribute \src "ls180.v:5538.11-5538.79" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5540.11-5540.15" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - end - case - end - attribute \src "ls180.v:5544.9-5544.13" - case - attribute \src "ls180.v:5545.6-5552.9" - switch $eq$ls180.v:5545$1136_Y - attribute \src "ls180.v:5545.10-5545.58" - case 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5565.4-5579.7" - switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5565.8-5565.31" - case 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 - case - end - end - sync always - update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] - update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] - update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] - update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] - update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] - update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] - update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] - update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] - update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] - update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] - update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] - update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] - update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] - update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] - update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] - update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] - update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] - update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] - update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] - update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] - update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:55.5-55.42" - process $proc$ls180.v:55$3126 - assign { } { } - assign $1\main_libresocsim_reset_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] - end - attribute \src "ls180.v:56.5-56.37" - process $proc$ls180.v:56$3127 - assign { } { } - assign $1\main_libresocsim_reset_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] - end - attribute \src "ls180.v:560.5-560.59" - process $proc$ls180.v:560$3277 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:5610.1-5617.4" - process $proc$ls180.v:5610$1137 - assign { } { } - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5612.2-5616.5" - switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5612.6-5612.35" - case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5613$1138_Y - attribute \src "ls180.v:5614.6-5614.10" - case - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce - end - sync always - update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:562.5-562.59" - process $proc$ls180.v:562$3278 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:563.5-563.58" - process $proc$ls180.v:563$3279 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:564.5-564.64" - process $proc$ls180.v:564$3280 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:5643.1-5682.4" - process $proc$ls180.v:5643$1148 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5653.2-5681.9" - switch \builder_sdblock2memdma_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid - assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5657$1149_Y - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5659.4-5670.7" - switch $and$ls180.v:5659$1150_Y - attribute \src "ls180.v:5659.8-5659.103" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5660$1151_Y - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5662.5-5669.8" - switch $eq$ls180.v:5662$1153_Y - attribute \src "ls180.v:5662.9-5662.106" - case 1'1 - attribute \src "ls180.v:5663.6-5668.9" - switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5663.10-5663.57" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5666.10-5666.14" - case - assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 - end - sync always - update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] - update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] - update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] - update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:565.12-565.74" - process $proc$ls180.v:565$3281 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:566.12-566.47" - process $proc$ls180.v:566$3282 - assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] - end - attribute \src "ls180.v:567.5-567.46" - process $proc$ls180.v:567$3283 - assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] - end - attribute \src "ls180.v:569.5-569.44" - process $proc$ls180.v:569$3284 - assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] - end - attribute \src "ls180.v:57.12-57.60" - process $proc$ls180.v:57$3128 - assign { } { } - assign $1\main_libresocsim_scratch_storage[31:0] 305419896 - sync always - sync init - update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] - end - attribute \src "ls180.v:570.5-570.45" - process $proc$ls180.v:570$3285 - assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] - end - attribute \src "ls180.v:5702.1-5739.4" - process $proc$ls180.v:5702$1155 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_interface1_bus_adr[31:0] 0 - assign { } { } - assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_interface1_bus_sel[7:0] 8'00000000 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - assign $0\main_interface1_bus_cyc[0:0] 1'0 - assign $0\main_interface1_bus_stb[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5716.2-5738.9" - switch \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last - assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5721.4-5724.7" - switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5721.8-5721.41" - case 1'1 - assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid - assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_interface1_bus_sel[7:0] 8'11111111 - assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5732.4-5736.7" - switch $and$ls180.v:5732$1156_Y - attribute \src "ls180.v:5732.8-5732.59" - case 1'1 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 - case - end - end - sync always - update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] - update \main_interface1_bus_sel $0\main_interface1_bus_sel[7:0] - update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] - update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] - update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] - update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] - update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] - update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] - update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[63:0] - update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:571.5-571.54" - process $proc$ls180.v:571$3286 - assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:573.32-573.76" - process $proc$ls180.v:573$3287 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - end - attribute \src "ls180.v:574.11-574.55" - process $proc$ls180.v:574$3288 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] - end - attribute \src "ls180.v:5740.1-5776.4" - process $proc$ls180.v:5740$1157 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign { } { } - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5749.2-5775.9" - switch \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5752$1159_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5753$1160_Y - attribute \src "ls180.v:5754.4-5765.7" - switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5754.8-5754.39" - case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5755$1161_Y - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5757.5-5764.8" - switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5757.9-5757.39" - case 1'1 - attribute \src "ls180.v:5758.6-5763.9" - switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5758.10-5758.43" - case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5761.10-5761.14" - case - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 - end - sync always - update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] - update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] - update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] - update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] - update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:576.32-576.75" - process $proc$ls180.v:576$3289 - assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:578.32-578.76" - process $proc$ls180.v:578$3290 - assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:5788.1-5816.4" - process $proc$ls180.v:5788$1167 - assign { } { } - assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5790.2-5815.9" - switch \main_sdmem2block_converter_mux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [63:56] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [55:48] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [47:40] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [39:32] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] - end - sync always - update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:58.5-58.39" - process $proc$ls180.v:58$3129 - assign { } { } - assign $1\main_libresocsim_scratch_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] - end - attribute \src "ls180.v:5830.1-5837.4" - process $proc$ls180.v:5830$1168 - assign { } { } - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5832.2-5836.5" - switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5832.6-5832.35" - case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5833$1169_Y - attribute \src "ls180.v:5834.6-5834.10" - case - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce - end - sync always - update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:584.5-584.51" - process $proc$ls180.v:584$3291 - assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - end - attribute \src "ls180.v:5845.1-5881.4" - process $proc$ls180.v:5845$1175 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 - assign { } { } - assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5856.2-5880.9" - switch \builder_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'10 - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } - assign $0\builder_next_state[1:0] 2'00 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5872.4-5878.7" - switch $and$ls180.v:5872$1176_Y - attribute \src "ls180.v:5872.8-5872.77" - case 1'1 - assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5875$1178_Y - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'01 - case - end - end - sync always - update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] - update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] - update \builder_next_state $0\builder_next_state[1:0] - update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] - update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] - update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] - update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] - update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] - end - attribute \src "ls180.v:585.5-585.51" - process $proc$ls180.v:585$3292 - assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - end - attribute \src "ls180.v:587.5-587.47" - process $proc$ls180.v:587$3293 - assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] - end - attribute \src "ls180.v:588.5-588.45" - process $proc$ls180.v:588$3294 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] - end - attribute \src "ls180.v:589.5-589.45" - process $proc$ls180.v:589$3295 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:590.12-590.57" - process $proc$ls180.v:590$3296 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:5906.1-5921.4" - process $proc$ls180.v:5906$1199 - assign { } { } - assign { } { } - assign $0\builder_slave_sel[12:0] [0] $eq$ls180.v:5908$1200_Y - assign $0\builder_slave_sel[12:0] [1] $eq$ls180.v:5909$1201_Y - assign $0\builder_slave_sel[12:0] [2] $eq$ls180.v:5910$1202_Y - assign $0\builder_slave_sel[12:0] [3] $eq$ls180.v:5911$1203_Y - assign $0\builder_slave_sel[12:0] [4] $eq$ls180.v:5912$1204_Y - assign $0\builder_slave_sel[12:0] [5] $eq$ls180.v:5913$1205_Y - assign $0\builder_slave_sel[12:0] [6] $eq$ls180.v:5914$1206_Y - assign $0\builder_slave_sel[12:0] [7] $eq$ls180.v:5915$1207_Y - assign $0\builder_slave_sel[12:0] [8] $eq$ls180.v:5916$1208_Y - assign $0\builder_slave_sel[12:0] [9] $eq$ls180.v:5917$1209_Y - assign $0\builder_slave_sel[12:0] [10] $eq$ls180.v:5918$1210_Y - assign $0\builder_slave_sel[12:0] [11] $eq$ls180.v:5919$1211_Y - assign $0\builder_slave_sel[12:0] [12] $eq$ls180.v:5920$1212_Y - sync always - update \builder_slave_sel $0\builder_slave_sel[12:0] - end - attribute \src "ls180.v:592.5-592.51" - process $proc$ls180.v:592$3297 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:593.5-593.51" - process $proc$ls180.v:593$3298 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:594.5-594.50" - process $proc$ls180.v:594$3299 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - end - attribute \src "ls180.v:595.5-595.54" - process $proc$ls180.v:595$3300 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:596.5-596.55" - process $proc$ls180.v:596$3301 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:597.5-597.56" - process $proc$ls180.v:597$3302 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:598.5-598.50" - process $proc$ls180.v:598$3303 - assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:601.5-601.67" - process $proc$ls180.v:601$3304 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:602.5-602.66" - process $proc$ls180.v:602$3305 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:6028.1-6039.4" - process $proc$ls180.v:6028$1241 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_error[0:0] 1'0 - assign $0\builder_shared_ack[0:0] $or$ls180.v:6032$1253_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:6033$1278_Y [31:0] - attribute \src "ls180.v:6034.2-6038.5" - switch \builder_done - attribute \src "ls180.v:6034.6-6034.18" - case 1'1 - assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 - assign $0\builder_shared_ack[0:0] 1'1 - assign $0\builder_error[0:0] 1'1 - case - end - sync always - update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] - update \builder_shared_ack $0\builder_shared_ack[0:0] - update \builder_error $0\builder_error[0:0] - end - attribute \src "ls180.v:617.11-617.68" - process $proc$ls180.v:617$3306 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:618.5-618.64" - process $proc$ls180.v:618$3307 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:619.11-619.70" - process $proc$ls180.v:619$3308 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:620.11-620.70" - process $proc$ls180.v:620$3309 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:621.11-621.73" - process $proc$ls180.v:621$3310 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:63.12-63.47" - process $proc$ls180.v:63$3130 - assign { } { } - assign $1\main_libresocsim_bus_errors[31:0] 0 - sync always - sync init - update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] - end - attribute \src "ls180.v:642.5-642.59" - process $proc$ls180.v:642$3311 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:644.5-644.59" - process $proc$ls180.v:644$3312 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:645.5-645.58" - process $proc$ls180.v:645$3313 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:646.5-646.64" - process $proc$ls180.v:646$3314 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:647.12-647.74" - process $proc$ls180.v:647$3315 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:648.12-648.47" - process $proc$ls180.v:648$3316 - assign { } { } - assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] - end - attribute \src "ls180.v:649.5-649.46" - process $proc$ls180.v:649$3317 - assign { } { } - assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] - end - attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$3131 - assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 - sync always - sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:651.5-651.44" - process $proc$ls180.v:651$3318 - assign { } { } - assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] - end - attribute \src "ls180.v:652.5-652.45" - process $proc$ls180.v:652$3319 - assign { } { } - assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] - end - attribute \src "ls180.v:653.5-653.54" - process $proc$ls180.v:653$3320 - assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:655.32-655.76" - process $proc$ls180.v:655$3321 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - end - attribute \src "ls180.v:6553.1-6558.4" - process $proc$ls180.v:6553$2152 - assign { } { } - assign $0\main_spimaster9_start[0:0] 1'0 - attribute \src "ls180.v:6555.2-6557.5" - switch \main_spimaster12_re - attribute \src "ls180.v:6555.6-6555.25" - case 1'1 - assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] - case - end - sync always - update \main_spimaster9_start $0\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:656.11-656.55" - process $proc$ls180.v:656$3322 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] - end - attribute \src "ls180.v:658.32-658.75" - process $proc$ls180.v:658$3323 - assign { } { } - assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:6599.1-6604.4" - process $proc$ls180.v:6599$2217 - assign { } { } - assign $0\main_spisdcard_start1[0:0] 1'0 - attribute \src "ls180.v:6601.2-6603.5" - switch \main_spisdcard_control_re - attribute \src "ls180.v:6601.6-6601.31" - case 1'1 - assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] - case - end - sync always - update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] - end - attribute \src "ls180.v:660.32-660.76" - process $proc$ls180.v:660$3324 - assign { } { } - assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:666.5-666.51" - process $proc$ls180.v:666$3325 - assign { } { } - assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - end - attribute \src "ls180.v:667.5-667.51" - process $proc$ls180.v:667$3326 - assign { } { } - assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - end - attribute \src "ls180.v:669.5-669.47" - process $proc$ls180.v:669$3327 - assign { } { } - assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] - end - attribute \src "ls180.v:670.5-670.45" - process $proc$ls180.v:670$3328 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] - end - attribute \src "ls180.v:671.5-671.45" - process $proc$ls180.v:671$3329 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:672.12-672.57" - process $proc$ls180.v:672$3330 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - end - attribute \src "ls180.v:674.5-674.51" - process $proc$ls180.v:674$3331 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:675.5-675.51" - process $proc$ls180.v:675$3332 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:676.5-676.50" - process $proc$ls180.v:676$3333 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - end - attribute \src "ls180.v:677.5-677.54" - process $proc$ls180.v:677$3334 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:678.5-678.55" - process $proc$ls180.v:678$3335 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:6788.1-6804.4" - process $proc$ls180.v:6788$2438 - assign { } { } - assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6790.2-6803.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] - end - sync always - update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] - end - attribute \src "ls180.v:679.5-679.56" - process $proc$ls180.v:679$3336 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:680.5-680.50" - process $proc$ls180.v:680$3337 - assign { } { } - assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:6805.1-6821.4" - process $proc$ls180.v:6805$2439 - assign { } { } - assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6807.2-6820.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a - end - sync always - update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:6822.1-6838.4" - process $proc$ls180.v:6822$2440 - assign { } { } - assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6824.2-6837.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba - end - sync always - update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] - end - attribute \src "ls180.v:683.5-683.67" - process $proc$ls180.v:683$3338 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:6839.1-6855.4" - process $proc$ls180.v:6839$2441 - assign { } { } - assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6841.2-6854.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read - end - sync always - update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:684.5-684.66" - process $proc$ls180.v:684$3339 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:6856.1-6872.4" - process $proc$ls180.v:6856$2442 - assign { } { } - assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6858.2-6871.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write - end - sync always - update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:6873.1-6889.4" - process $proc$ls180.v:6873$2443 - assign { } { } - assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6875.2-6888.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd - end - sync always - update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:6890.1-6906.4" - process $proc$ls180.v:6890$2444 - assign { } { } - assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6892.2-6905.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas - end - sync always - update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] - end - attribute \src "ls180.v:6907.1-6923.4" - process $proc$ls180.v:6907$2445 - assign { } { } - assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6909.2-6922.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras - end - sync always - update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] - end - attribute \src "ls180.v:6924.1-6940.4" - process $proc$ls180.v:6924$2446 - assign { } { } - assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6926.2-6939.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we - end - sync always - update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] - end - attribute \src "ls180.v:6941.1-6957.4" - process $proc$ls180.v:6941$2447 - assign { } { } - assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6943.2-6956.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] - end - sync always - update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:6958.1-6974.4" - process $proc$ls180.v:6958$2448 - assign { } { } - assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6960.2-6973.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a - end - sync always - update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] - end - attribute \src "ls180.v:6975.1-6991.4" - process $proc$ls180.v:6975$2449 - assign { } { } - assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6977.2-6990.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba - end - sync always - update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] - end - attribute \src "ls180.v:699.11-699.68" - process $proc$ls180.v:699$3340 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:6992.1-7008.4" - process $proc$ls180.v:6992$2450 - assign { } { } - assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6994.2-7007.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read - end - sync always - update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] - end - attribute \src "ls180.v:700.5-700.64" - process $proc$ls180.v:700$3341 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:7009.1-7025.4" - process $proc$ls180.v:7009$2451 - assign { } { } - assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:7011.2-7024.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write - end - sync always - update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] - end - attribute \src "ls180.v:701.11-701.70" - process $proc$ls180.v:701$3342 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:702.11-702.70" - process $proc$ls180.v:702$3343 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:7026.1-7042.4" - process $proc$ls180.v:7026$2452 - assign { } { } - assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:7028.2-7041.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd - end - sync always - update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] - end - attribute \src "ls180.v:703.11-703.73" - process $proc$ls180.v:703$3344 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:7043.1-7059.4" - process $proc$ls180.v:7043$2453 - assign { } { } - assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7045.2-7058.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas - end - sync always - update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] - end - attribute \src "ls180.v:7060.1-7076.4" - process $proc$ls180.v:7060$2454 - assign { } { } - assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7062.2-7075.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras - end - sync always - update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] - end - attribute \src "ls180.v:7077.1-7093.4" - process $proc$ls180.v:7077$2455 - assign { } { } - assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7079.2-7092.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we - end - sync always - update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] - end - attribute \src "ls180.v:7094.1-7101.4" - process $proc$ls180.v:7094$2456 - assign { } { } - assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7096.2-7100.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] - end - attribute \src "ls180.v:7102.1-7109.4" - process $proc$ls180.v:7102$2457 - assign { } { } - assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:7104.2-7108.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] - end - attribute \src "ls180.v:7110.1-7117.4" - process $proc$ls180.v:7110$2458 - assign { } { } - assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:7112.2-7116.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:7114$2471_Y - end - sync always - update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] - end - attribute \src "ls180.v:7118.1-7125.4" - process $proc$ls180.v:7118$2472 - assign { } { } - assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7120.2-7124.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] - end - attribute \src "ls180.v:7126.1-7133.4" - process $proc$ls180.v:7126$2473 - assign { } { } - assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:7128.2-7132.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] - end - attribute \src "ls180.v:7134.1-7141.4" - process $proc$ls180.v:7134$2474 - assign { } { } - assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:7136.2-7140.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7138$2487_Y - end - sync always - update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] - end - attribute \src "ls180.v:7142.1-7149.4" - process $proc$ls180.v:7142$2488 - assign { } { } - assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7144.2-7148.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] - end - attribute \src "ls180.v:7150.1-7157.4" - process $proc$ls180.v:7150$2489 - assign { } { } - assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:7152.2-7156.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] - end - attribute \src "ls180.v:7158.1-7165.4" - process $proc$ls180.v:7158$2490 - assign { } { } - assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:7160.2-7164.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7162$2503_Y - end - sync always - update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] - end - attribute \src "ls180.v:7166.1-7173.4" - process $proc$ls180.v:7166$2504 - assign { } { } - assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7168.2-7172.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] - end - attribute \src "ls180.v:7174.1-7181.4" - process $proc$ls180.v:7174$2505 - assign { } { } - assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:7176.2-7180.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] - end - attribute \src "ls180.v:7182.1-7189.4" - process $proc$ls180.v:7182$2506 - assign { } { } - assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:7184.2-7188.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7186$2519_Y - end - sync always - update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] - end - attribute \src "ls180.v:7190.1-7209.4" - process $proc$ls180.v:7190$2520 - assign { } { } - assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:7192.2-7208.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_ibus_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_dbus_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_jtag_wb_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr - end - sync always - update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] - end - attribute \src "ls180.v:7210.1-7229.4" - process $proc$ls180.v:7210$2521 - assign { } { } - assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "ls180.v:7212.2-7228.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface0_bus_dat_w - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface1_bus_dat_w - end - sync always - update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] - end - attribute \src "ls180.v:7230.1-7249.4" - process $proc$ls180.v:7230$2522 - assign { } { } - assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 - attribute \src "ls180.v:7232.2-7248.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_jtag_wb_sel - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface0_bus_sel - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface1_bus_sel - end - sync always - update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] - end - attribute \src "ls180.v:724.5-724.59" - process $proc$ls180.v:724$3345 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:7250.1-7269.4" - process $proc$ls180.v:7250$2523 - assign { } { } - assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:7252.2-7268.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_dbus_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_jtag_wb_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc - end - sync always - update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] - end - attribute \src "ls180.v:726.5-726.59" - process $proc$ls180.v:726$3346 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:727.5-727.58" - process $proc$ls180.v:727$3347 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:7270.1-7289.4" - process $proc$ls180.v:7270$2524 - assign { } { } - assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:7272.2-7288.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_jtag_wb_stb - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb - end - sync always - update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] - end - attribute \src "ls180.v:728.5-728.64" - process $proc$ls180.v:728$3348 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:729.12-729.74" - process $proc$ls180.v:729$3349 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:7290.1-7309.4" - process $proc$ls180.v:7290$2525 - assign { } { } - assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:7292.2-7308.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we - end - sync always - update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] - end - attribute \src "ls180.v:730.12-730.47" - process $proc$ls180.v:730$3350 - assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] - end - attribute \src "ls180.v:731.5-731.46" - process $proc$ls180.v:731$3351 - assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] - end - attribute \src "ls180.v:7310.1-7329.4" - process $proc$ls180.v:7310$2526 - assign { } { } - assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:7312.2-7328.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_ibus_cti - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_dbus_cti - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_jtag_wb_cti - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti - end - sync always - update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] - end - attribute \src "ls180.v:733.5-733.44" - process $proc$ls180.v:733$3352 - assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] - end - attribute \src "ls180.v:7330.1-7349.4" - process $proc$ls180.v:7330$2527 - assign { } { } - assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:7332.2-7348.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_ibus_bte - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_dbus_bte - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_jtag_wb_bte - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte - end - sync always - update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] - end - attribute \src "ls180.v:734.5-734.45" - process $proc$ls180.v:734$3353 - assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] - end - attribute \src "ls180.v:735.5-735.54" - process $proc$ls180.v:735$3354 - assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:7350.1-7366.4" - process $proc$ls180.v:7350$2528 - assign { } { } - assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7352.2-7365.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba - end - sync always - update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] - end - attribute \src "ls180.v:7367.1-7383.4" - process $proc$ls180.v:7367$2529 - assign { } { } - assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7369.2-7382.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a - end - sync always - update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:737.32-737.76" - process $proc$ls180.v:737$3355 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - end - attribute \src "ls180.v:738.11-738.55" - process $proc$ls180.v:738$3356 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] - end - attribute \src "ls180.v:7384.1-7400.4" - process $proc$ls180.v:7384$2530 - assign { } { } - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7386.2-7399.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7391$2532_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7394$2534_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7397$2536_Y - end - sync always - update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] - end - attribute \src "ls180.v:74.11-74.52" - process $proc$ls180.v:74$3132 - assign { } { } - assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 - sync always - update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] - sync init - end - attribute \src "ls180.v:740.32-740.75" - process $proc$ls180.v:740$3357 - assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:7401.1-7417.4" - process $proc$ls180.v:7401$2537 - assign { } { } - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7403.2-7416.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7408$2539_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7411$2541_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7414$2543_Y - end - sync always - update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:7418.1-7434.4" - process $proc$ls180.v:7418$2544 - assign { } { } - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7420.2-7433.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7425$2546_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7428$2548_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7431$2550_Y - end - sync always - update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:742.32-742.76" - process $proc$ls180.v:742$3358 - assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:7435.1-7451.4" - process $proc$ls180.v:7435$2551 - assign { } { } - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7437.2-7450.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7442$2553_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7445$2555_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7448$2557_Y - end - sync always - update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:7452.1-7468.4" - process $proc$ls180.v:7452$2558 - assign { } { } - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7454.2-7467.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7459$2560_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7462$2562_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7465$2564_Y - end - sync always - update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:7469.1-7497.4" - process $proc$ls180.v:7469$2565 - assign { } { } - assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7471.2-7496.9" - switch \main_spimaster34_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7] - end - sync always - update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] - end - attribute \src "ls180.v:748.5-748.51" - process $proc$ls180.v:748$3359 - assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - end - attribute \src "ls180.v:749.5-749.51" - process $proc$ls180.v:749$3360 - assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - end - attribute \src "ls180.v:7498.1-7526.4" - process $proc$ls180.v:7498$2566 - assign { } { } - assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7500.2-7525.9" - switch \main_spisdcard_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7] - end - sync always - update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] - end - attribute \src "ls180.v:75.11-75.52" - process $proc$ls180.v:75$3133 - assign { } { } - assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 - sync always - update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] - sync init - end - attribute \src "ls180.v:751.5-751.47" - process $proc$ls180.v:751$3361 - assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] - end - attribute \src "ls180.v:752.5-752.45" - process $proc$ls180.v:752$3362 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] - end - attribute \src "ls180.v:753.5-753.45" - process $proc$ls180.v:753$3363 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:754.12-754.57" - process $proc$ls180.v:754$3364 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:756.5-756.51" - process $proc$ls180.v:756$3365 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:757.5-757.51" - process $proc$ls180.v:757$3366 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:758.5-758.50" - process $proc$ls180.v:758$3367 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - end - attribute \src "ls180.v:7584.1-7594.4" - process $proc$ls180.v:7584$2567 - assign { } { } - assign $0\main_gpiotristateasic0_status[15:0] [15:8] 8'00000000 - assign $0\main_gpiotristateasic0_status[15:0] [0] \builder_multiregimpl1_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [1] \builder_multiregimpl2_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [2] \builder_multiregimpl3_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [3] \builder_multiregimpl4_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [4] \builder_multiregimpl5_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [5] \builder_multiregimpl6_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [6] \builder_multiregimpl7_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [7] \builder_multiregimpl8_regs1 - sync always - update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] - end - attribute \src "ls180.v:759.5-759.54" - process $proc$ls180.v:759$3368 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:7595.1-7605.4" - process $proc$ls180.v:7595$2568 - assign { } { } - assign $0\main_gpiotristateasic1_status[15:0] [7:0] 8'00000000 - assign $0\main_gpiotristateasic1_status[15:0] [8] \builder_multiregimpl9_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [9] \builder_multiregimpl10_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [10] \builder_multiregimpl11_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [11] \builder_multiregimpl12_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [12] \builder_multiregimpl13_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [13] \builder_multiregimpl14_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [14] \builder_multiregimpl15_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [15] \builder_multiregimpl16_regs1 - sync always - update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] - end - attribute \src "ls180.v:760.5-760.55" - process $proc$ls180.v:760$3369 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:761.5-761.56" - process $proc$ls180.v:761$3370 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:762.5-762.50" - process $proc$ls180.v:762$3371 - assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:7626.1-7628.4" - process $proc$ls180.v:7626$2569 - assign { } { } - assign $0\main_int_rst[0:0] \sys_rst - sync posedge \por_clk - update \main_int_rst $0\main_int_rst[0:0] - end - attribute \src "ls180.v:7630.1-7700.4" - process $proc$ls180.v:7630$2570 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] - assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] - assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] - assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] - assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] - assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] - assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] - assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] - assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] - assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] - assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] - assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] - assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] - assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] - assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] - assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n - assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n - assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n - assign $0\sdram_cke[0:0] \main_dfi_p0_cke - assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n - assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] - assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] - assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] - assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] - assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] - assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] - assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] - assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] - assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] - assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] - assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] - assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] - assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] - assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] - assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] - assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] - assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] - assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] - assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] - assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] - assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] - assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] - assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] - assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] - assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] - assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] - assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] - assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] - assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] - assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] - assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] - assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] - assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] - assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] - assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7687$2572_Y - assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe - assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o - assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i - assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe - assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] - assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] - assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] - assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] - assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] - assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] - assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] - assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] - sync posedge \sdrio_clk - update \sdram_a $0\sdram_a[12:0] - update \sdram_dq_o $0\sdram_dq_o[15:0] - update \sdram_dq_oe $0\sdram_dq_oe[0:0] - update \sdram_we_n $0\sdram_we_n[0:0] - update \sdram_ras_n $0\sdram_ras_n[0:0] - update \sdram_cas_n $0\sdram_cas_n[0:0] - update \sdram_cs_n $0\sdram_cs_n[0:0] - update \sdram_cke $0\sdram_cke[0:0] - update \sdram_ba $0\sdram_ba[1:0] - update \sdram_dm $0\sdram_dm[1:0] - update \sdram_clock $0\sdram_clock[0:0] - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] - update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] - update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] - update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] - end - attribute \src "ls180.v:765.5-765.67" - process $proc$ls180.v:765$3372 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:766.5-766.66" - process $proc$ls180.v:766$3373 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:7702.1-10346.4" - process $proc$ls180.v:7702$2573 - assign $0\pwm[1:0] \pwm - assign $0\spisdcard_clk[0:0] \spisdcard_clk - assign $0\spisdcard_mosi[0:0] \spisdcard_mosi - assign { } { } - assign $0\uart_tx[0:0] \uart_tx - assign $0\spimaster_clk[0:0] \spimaster_clk - assign $0\spimaster_mosi[0:0] \spimaster_mosi - assign { } { } - assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage - assign { } { } - assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage - assign { } { } - assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors - assign { } { } - assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage - assign { } { } - assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage - assign { } { } - assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage - assign { } { } - assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage - assign { } { } - assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status - assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending - assign { } { } - assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage - assign { } { } - assign $0\main_libresocsim_value[31:0] \main_libresocsim_value - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_converter0_counter[0:0] \main_converter0_counter - assign $0\main_converter0_dat_r[63:0] \main_converter0_dat_r - assign $0\main_converter1_counter[0:0] \main_converter1_counter - assign $0\main_converter1_dat_r[63:0] \main_converter1_dat_r - assign { } { } - assign { } { } - assign $0\main_sdram_storage[3:0] \main_sdram_storage - assign { } { } - assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage - assign { } { } - assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage - assign { } { } - assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage - assign { } { } - assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage - assign { } { } - assign $0\main_sdram_status[15:0] \main_sdram_status - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 - assign { } { } - assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count - assign { } { } - assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter - assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row - assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row - assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row - assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row - assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count - assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant - assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant - assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready - assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count - assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready - assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count - assign $0\main_sdram_time0[4:0] \main_sdram_time0 - assign $0\main_sdram_time1[3:0] \main_sdram_time1 - assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter - assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_dat_r - assign $0\main_converter_counter[0:0] \main_converter_counter - assign $0\main_converter_dat_r[31:0] \main_converter_dat_r - assign $0\main_cmd_consumed[0:0] \main_cmd_consumed - assign $0\main_wdata_consumed[0:0] \main_wdata_consumed - assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage - assign { } { } - assign { } { } - assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen - assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx - assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg - assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount - assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy - assign { } { } - assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data - assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen - assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx - assign { } { } - assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg - assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount - assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy - assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending - assign { } { } - assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending - assign { } { } - assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage - assign { } { } - assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable - assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 - assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce - assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume - assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable - assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 - assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce - assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume - assign $0\main_gpiotristateasic1_oe_storage[15:0] \main_gpiotristateasic1_oe_storage - assign { } { } - assign $0\main_gpiotristateasic1_out_storage[15:0] \main_gpiotristateasic1_out_storage - assign { } { } - assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso - assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage - assign { } { } - assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage - assign { } { } - assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage - assign { } { } - assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage - assign { } { } - assign $0\main_spimaster27_count[2:0] \main_spimaster27_count - assign { } { } - assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data - assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel - assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data - assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso - assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage - assign { } { } - assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage - assign { } { } - assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage - assign { } { } - assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage - assign { } { } - assign $0\main_spisdcard_count[2:0] \main_spisdcard_count - assign { } { } - assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data - assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel - assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data - assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage - assign { } { } - assign { } { } - assign $0\main_pwm0_counter[31:0] \main_pwm0_counter - assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage - assign { } { } - assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage - assign { } { } - assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage - assign { } { } - assign $0\main_pwm1_counter[31:0] \main_pwm1_counter - assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage - assign { } { } - assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage - assign { } { } - assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage - assign { } { } - assign $0\main_i2c_storage[2:0] \main_i2c_storage - assign { } { } - assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage - assign { } { } - assign { } { } - assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks - assign { } { } - assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count - assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count - assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout - assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count - assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid - assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first - assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last - assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset - assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count - assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid - assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first - assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last - assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data - assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset - assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout - assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count - assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count - assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid - assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first - assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last - assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data - assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset - assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage - assign { } { } - assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage - assign { } { } - assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status - assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage - assign { } { } - assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage - assign { } { } - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 - assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val - assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 - assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count - assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done - assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error - assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout - assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count - assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done - assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error - assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout - assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level - assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce - assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume - assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first - assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] \main_sdblock2mem_converter_source_payload_data - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] \main_sdblock2mem_converter_source_payload_valid_token_count - assign $0\main_sdblock2mem_converter_demux[2:0] \main_sdblock2mem_converter_demux - assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset - assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data - assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage - assign { } { } - assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage - assign { } { } - assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage - assign { } { } - assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage - assign { } { } - assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset - assign $0\main_sdmem2block_converter_mux[2:0] \main_sdmem2block_converter_mux - assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level - assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce - assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w - assign $0\builder_grant[2:0] \builder_grant - assign { } { } - assign $0\builder_count[19:0] \builder_count - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_dummy[23:0] [0] $or$ls180.v:7703$2574_Y - assign $0\main_dummy[23:0] [1] $or$ls180.v:7704$2575_Y - assign $0\main_dummy[23:0] [2] $or$ls180.v:7705$2576_Y - assign $0\main_dummy[23:0] [3] $or$ls180.v:7706$2577_Y - assign $0\main_dummy[23:0] [4] $or$ls180.v:7707$2578_Y - assign $0\main_dummy[23:0] [5] $or$ls180.v:7708$2579_Y - assign $0\main_dummy[23:0] [6] $or$ls180.v:7709$2580_Y - assign $0\main_dummy[23:0] [7] $or$ls180.v:7710$2581_Y - assign $0\main_dummy[23:0] [8] $or$ls180.v:7711$2582_Y - assign $0\main_dummy[23:0] [9] $or$ls180.v:7712$2583_Y - assign $0\main_dummy[23:0] [10] $or$ls180.v:7713$2584_Y - assign $0\main_dummy[23:0] [11] $or$ls180.v:7714$2585_Y - assign $0\main_dummy[23:0] [12] $or$ls180.v:7715$2586_Y - assign $0\main_dummy[23:0] [13] $or$ls180.v:7716$2587_Y - assign $0\main_dummy[23:0] [14] $or$ls180.v:7717$2588_Y - assign $0\main_dummy[23:0] [15] $or$ls180.v:7718$2589_Y - assign $0\main_dummy[23:0] [16] $or$ls180.v:7719$2590_Y - assign $0\main_dummy[23:0] [17] $or$ls180.v:7720$2591_Y - assign $0\main_dummy[23:0] [18] $or$ls180.v:7721$2592_Y - assign $0\main_dummy[23:0] [19] $or$ls180.v:7722$2593_Y - assign $0\main_dummy[23:0] [20] $or$ls180.v:7723$2594_Y - assign $0\main_dummy[23:0] [21] $or$ls180.v:7724$2595_Y - assign $0\main_dummy[23:0] [22] $or$ls180.v:7725$2596_Y - assign $0\main_dummy[23:0] [23] $or$ls180.v:7726$2597_Y - assign $0\builder_converter0_state[0:0] \builder_converter0_next_state - assign $0\builder_converter1_state[0:0] \builder_converter1_next_state - assign $0\builder_converter2_state[0:0] \builder_converter2_next_state - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger - assign $0\main_interface0_ram_bus_ack[0:0] 1'0 - assign $0\main_interface1_ram_bus_ack[0:0] 1'0 - assign $0\main_interface2_ram_bus_ack[0:0] 1'0 - assign $0\main_interface3_ram_bus_ack[0:0] 1'0 - assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } - assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\builder_refresher_state[1:0] \builder_refresher_next_state - assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state - assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state - assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state - assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 - assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 - assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8184$2706_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8185$2707_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8186$2708_Y - assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 - assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8220$2726_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8221$2738_Y - assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 - assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 - assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 - assign $0\builder_converter_state[0:0] \builder_converter_next_state - assign $0\main_uart_phy_sink_ready[0:0] 1'0 - assign $0\main_uart_phy_source_valid[0:0] 1'0 - assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx - assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger - assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8379$2784_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8388$2787_Y - assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8414$2789_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8423$2792_Y - assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state - assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 - assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 - assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state - assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state - assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state - assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state - assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state - assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state - assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state - assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state - assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state - assign $0\builder_state[1:0] \builder_next_state - assign $0\builder_slave_sel_r[12:0] \builder_slave_sel - assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re - assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re - assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_gpiotristateasic1_oe_re[0:0] \builder_csrbank1_oe0_re - assign $0\main_gpiotristateasic1_out_re[0:0] \builder_csrbank1_out0_re - assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re - assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re - assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re - assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re - assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re - assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re - assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re - assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re - assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re - assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re - assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re - assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re - assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re - assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re - assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re - assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re - assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re - assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re - assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re - assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re - assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re - assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re - assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re - assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re - assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re - assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re - assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re - assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re - assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re - assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re - assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re - assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re - assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re - assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re - assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re - assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re - assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re - assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re - assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx - assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 - assign $0\builder_multiregimpl1_regs0[0:0] \main_gpiotristateasic0_pads_i [0] - assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 - assign $0\builder_multiregimpl2_regs0[0:0] \main_gpiotristateasic0_pads_i [1] - assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 - assign $0\builder_multiregimpl3_regs0[0:0] \main_gpiotristateasic0_pads_i [2] - assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 - assign $0\builder_multiregimpl4_regs0[0:0] \main_gpiotristateasic0_pads_i [3] - assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 - assign $0\builder_multiregimpl5_regs0[0:0] \main_gpiotristateasic0_pads_i [4] - assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 - assign $0\builder_multiregimpl6_regs0[0:0] \main_gpiotristateasic0_pads_i [5] - assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 - assign $0\builder_multiregimpl7_regs0[0:0] \main_gpiotristateasic0_pads_i [6] - assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 - assign $0\builder_multiregimpl8_regs0[0:0] \main_gpiotristateasic0_pads_i [7] - assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 - assign $0\builder_multiregimpl9_regs0[0:0] \main_gpiotristateasic1_pads_i [8] - assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 - assign $0\builder_multiregimpl10_regs0[0:0] \main_gpiotristateasic1_pads_i [9] - assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 - assign $0\builder_multiregimpl11_regs0[0:0] \main_gpiotristateasic1_pads_i [10] - assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 - assign $0\builder_multiregimpl12_regs0[0:0] \main_gpiotristateasic1_pads_i [11] - assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 - assign $0\builder_multiregimpl13_regs0[0:0] \main_gpiotristateasic1_pads_i [12] - assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 - assign $0\builder_multiregimpl14_regs0[0:0] \main_gpiotristateasic1_pads_i [13] - assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 - assign $0\builder_multiregimpl15_regs0[0:0] \main_gpiotristateasic1_pads_i [14] - assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 - assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] - assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7727.2-7729.5" - switch $or$ls180.v:7727$2598_Y - attribute \src "ls180.v:7727.6-7727.69" - case 1'1 - assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r - case - end - attribute \src "ls180.v:7731.2-7733.5" - switch \main_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7731.6-7731.54" - case 1'1 - assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value - case - end - attribute \src "ls180.v:7734.2-7737.5" - switch \main_converter0_reset - attribute \src "ls180.v:7734.6-7734.27" - case 1'1 - assign $0\main_converter0_counter[0:0] 1'0 - assign $0\builder_converter0_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7738.2-7740.5" - switch $or$ls180.v:7738$2599_Y - attribute \src "ls180.v:7738.6-7738.69" - case 1'1 - assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r - case - end - attribute \src "ls180.v:7742.2-7744.5" - switch \main_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7742.6-7742.54" - case 1'1 - assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value - case - end - attribute \src "ls180.v:7745.2-7748.5" - switch \main_converter1_reset - attribute \src "ls180.v:7745.6-7745.27" - case 1'1 - assign $0\main_converter1_counter[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7749.2-7751.5" - switch $or$ls180.v:7749$2600_Y - attribute \src "ls180.v:7749.6-7749.51" - case 1'1 - assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r - case - end - attribute \src "ls180.v:7753.2-7755.5" - switch \main_socbushandler_counter_converter2_next_value_ce - attribute \src "ls180.v:7753.6-7753.57" - case 1'1 - assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value - case - end - attribute \src "ls180.v:7756.2-7759.5" - switch \main_socbushandler_reset - attribute \src "ls180.v:7756.6-7756.30" - case 1'1 - assign $0\main_socbushandler_counter[0:0] 1'0 - assign $0\builder_converter2_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7760.2-7764.5" - switch $ne$ls180.v:7760$2601_Y - attribute \src "ls180.v:7760.6-7760.53" - case 1'1 - attribute \src "ls180.v:7761.3-7763.6" - switch \main_libresocsim_bus_error - attribute \src "ls180.v:7761.7-7761.33" - case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7762$2602_Y - case - end - case - end - attribute \src "ls180.v:7766.2-7768.5" - switch $and$ls180.v:7766$2605_Y - attribute \src "ls180.v:7766.6-7766.103" - case 1'1 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7769.2-7777.5" - switch \main_libresocsim_en_storage - attribute \src "ls180.v:7769.6-7769.33" - case 1'1 - attribute \src "ls180.v:7770.3-7774.6" - switch $eq$ls180.v:7770$2606_Y - attribute \src "ls180.v:7770.7-7770.39" - case 1'1 - assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7772.7-7772.11" - case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7773$2607_Y - end - attribute \src "ls180.v:7775.6-7775.10" - case - assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage - end - attribute \src "ls180.v:7778.2-7780.5" - switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7778.6-7778.38" - case 1'1 - assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value - case - end - attribute \src "ls180.v:7781.2-7783.5" - switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7781.6-7781.33" - case 1'1 - assign $0\main_libresocsim_zero_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:7785.2-7787.5" - switch $and$ls180.v:7785$2609_Y - attribute \src "ls180.v:7785.6-7785.76" - case 1'1 - assign $0\main_libresocsim_zero_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:7789.2-7791.5" - switch $and$ls180.v:7789$2612_Y - attribute \src "ls180.v:7789.6-7789.100" - case 1'1 - assign $0\main_interface0_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7793.2-7795.5" - switch $and$ls180.v:7793$2615_Y - attribute \src "ls180.v:7793.6-7793.100" - case 1'1 - assign $0\main_interface1_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7797.2-7799.5" - switch $and$ls180.v:7797$2618_Y - attribute \src "ls180.v:7797.6-7797.100" - case 1'1 - assign $0\main_interface2_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7801.2-7803.5" - switch $and$ls180.v:7801$2621_Y - attribute \src "ls180.v:7801.6-7801.100" - case 1'1 - assign $0\main_interface3_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7806.2-7808.5" - switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7806.6-7806.37" - case 1'1 - assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata - case - end - attribute \src "ls180.v:7809.2-7813.5" - switch $and$ls180.v:7809$2623_Y - attribute \src "ls180.v:7809.6-7809.57" - case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7810$2624_Y - attribute \src "ls180.v:7811.6-7811.10" - case - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - end - attribute \src "ls180.v:7815.2-7821.5" - switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7815.6-7815.32" - case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7816$2625_Y - attribute \src "ls180.v:7817.3-7820.6" - switch $eq$ls180.v:7817$2626_Y - attribute \src "ls180.v:7817.7-7817.43" - case 1'1 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_postponer_req_o[0:0] 1'1 - case - end - case - end - attribute \src "ls180.v:7822.2-7830.5" - switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7822.6-7822.33" - case 1'1 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7824.6-7824.10" - case - attribute \src "ls180.v:7825.3-7829.6" - switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7825.7-7825.33" - case 1'1 - attribute \src "ls180.v:7826.4-7828.7" - switch $ne$ls180.v:7826$2627_Y - attribute \src "ls180.v:7826.8-7826.44" - case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7827$2628_Y - case - end - case - end - end - attribute \src "ls180.v:7837.2-7843.5" - switch $and$ls180.v:7837$2630_Y - attribute \src "ls180.v:7837.6-7837.76" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'1 - case - end - attribute \src "ls180.v:7844.2-7850.5" - switch $eq$ls180.v:7844$2631_Y - attribute \src "ls180.v:7844.6-7844.44" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - case - end - attribute \src "ls180.v:7851.2-7858.5" - switch $eq$ls180.v:7851$2632_Y - attribute \src "ls180.v:7851.6-7851.44" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'1 - case - end - attribute \src "ls180.v:7859.2-7869.5" - switch $eq$ls180.v:7859$2633_Y - attribute \src "ls180.v:7859.6-7859.44" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7861.6-7861.10" - case - attribute \src "ls180.v:7862.3-7868.6" - switch $ne$ls180.v:7862$2634_Y - attribute \src "ls180.v:7862.7-7862.45" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7863$2635_Y - attribute \src "ls180.v:7864.7-7864.11" - case - attribute \src "ls180.v:7865.4-7867.7" - switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7865.8-7865.35" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0001 - case - end - end - end - attribute \src "ls180.v:7871.2-7878.5" - switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7871.6-7871.39" - case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7873.6-7873.10" - case - attribute \src "ls180.v:7874.3-7877.6" - switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7874.7-7874.39" - case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7879.2-7881.5" - switch $and$ls180.v:7879$2638_Y - attribute \src "ls180.v:7879.6-7879.191" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7880$2639_Y - case - end - attribute \src "ls180.v:7882.2-7884.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7882.6-7882.58" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7883$2640_Y - case - end - attribute \src "ls180.v:7885.2-7893.5" - switch $and$ls180.v:7885$2643_Y - attribute \src "ls180.v:7885.6-7885.191" - case 1'1 - attribute \src "ls180.v:7886.3-7888.6" - switch $not$ls180.v:7886$2644_Y - attribute \src "ls180.v:7886.7-7886.62" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7887$2645_Y - case - end - attribute \src "ls180.v:7889.6-7889.10" - case - attribute \src "ls180.v:7890.3-7892.6" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7890.7-7890.59" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7891$2646_Y - case - end - end - attribute \src "ls180.v:7894.2-7900.5" - switch $or$ls180.v:7894$2648_Y - attribute \src "ls180.v:7894.6-7894.108" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7901.2-7915.5" - switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7901.6-7901.43" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7903.3-7907.6" - switch 1'0 - attribute \src "ls180.v:7905.7-7905.11" - case - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7908.6-7908.10" - case - attribute \src "ls180.v:7909.3-7914.6" - switch $not$ls180.v:7909$2649_Y - attribute \src "ls180.v:7909.7-7909.47" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7910$2650_Y - attribute \src "ls180.v:7911.4-7913.7" - switch $eq$ls180.v:7911$2651_Y - attribute \src "ls180.v:7911.8-7911.55" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7917.2-7924.5" - switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7917.6-7917.39" - case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7919.6-7919.10" - case - attribute \src "ls180.v:7920.3-7923.6" - switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7920.7-7920.39" - case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7925.2-7927.5" - switch $and$ls180.v:7925$2654_Y - attribute \src "ls180.v:7925.6-7925.191" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7926$2655_Y - case - end - attribute \src "ls180.v:7928.2-7930.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7928.6-7928.58" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7929$2656_Y - case - end - attribute \src "ls180.v:7931.2-7939.5" - switch $and$ls180.v:7931$2659_Y - attribute \src "ls180.v:7931.6-7931.191" - case 1'1 - attribute \src "ls180.v:7932.3-7934.6" - switch $not$ls180.v:7932$2660_Y - attribute \src "ls180.v:7932.7-7932.62" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7933$2661_Y - case - end - attribute \src "ls180.v:7935.6-7935.10" - case - attribute \src "ls180.v:7936.3-7938.6" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7936.7-7936.59" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7937$2662_Y - case - end - end - attribute \src "ls180.v:7940.2-7946.5" - switch $or$ls180.v:7940$2664_Y - attribute \src "ls180.v:7940.6-7940.108" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7947.2-7961.5" - switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7947.6-7947.43" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7949.3-7953.6" - switch 1'0 - attribute \src "ls180.v:7951.7-7951.11" - case - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7954.6-7954.10" - case - attribute \src "ls180.v:7955.3-7960.6" - switch $not$ls180.v:7955$2665_Y - attribute \src "ls180.v:7955.7-7955.47" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7956$2666_Y - attribute \src "ls180.v:7957.4-7959.7" - switch $eq$ls180.v:7957$2667_Y - attribute \src "ls180.v:7957.8-7957.55" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7963.2-7970.5" - switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7963.6-7963.39" - case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7965.6-7965.10" - case - attribute \src "ls180.v:7966.3-7969.6" - switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7966.7-7966.39" - case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7971.2-7973.5" - switch $and$ls180.v:7971$2670_Y - attribute \src "ls180.v:7971.6-7971.191" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7972$2671_Y - case - end - attribute \src "ls180.v:7974.2-7976.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7974.6-7974.58" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7975$2672_Y - case - end - attribute \src "ls180.v:7977.2-7985.5" - switch $and$ls180.v:7977$2675_Y - attribute \src "ls180.v:7977.6-7977.191" - case 1'1 - attribute \src "ls180.v:7978.3-7980.6" - switch $not$ls180.v:7978$2676_Y - attribute \src "ls180.v:7978.7-7978.62" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7979$2677_Y - case - end - attribute \src "ls180.v:7981.6-7981.10" - case - attribute \src "ls180.v:7982.3-7984.6" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7982.7-7982.59" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7983$2678_Y - case - end - end - attribute \src "ls180.v:7986.2-7992.5" - switch $or$ls180.v:7986$2680_Y - attribute \src "ls180.v:7986.6-7986.108" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7993.2-8007.5" - switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7993.6-7993.43" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7995.3-7999.6" - switch 1'0 - attribute \src "ls180.v:7997.7-7997.11" - case - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:8000.6-8000.10" - case - attribute \src "ls180.v:8001.3-8006.6" - switch $not$ls180.v:8001$2681_Y - attribute \src "ls180.v:8001.7-8001.47" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8002$2682_Y - attribute \src "ls180.v:8003.4-8005.7" - switch $eq$ls180.v:8003$2683_Y - attribute \src "ls180.v:8003.8-8003.55" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:8009.2-8016.5" - switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:8009.6-8009.39" - case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:8011.6-8011.10" - case - attribute \src "ls180.v:8012.3-8015.6" - switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:8012.7-8012.39" - case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:8017.2-8019.5" - switch $and$ls180.v:8017$2686_Y - attribute \src "ls180.v:8017.6-8017.191" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8018$2687_Y - case - end - attribute \src "ls180.v:8020.2-8022.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:8020.6-8020.58" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8021$2688_Y - case - end - attribute \src "ls180.v:8023.2-8031.5" - switch $and$ls180.v:8023$2691_Y - attribute \src "ls180.v:8023.6-8023.191" - case 1'1 - attribute \src "ls180.v:8024.3-8026.6" - switch $not$ls180.v:8024$2692_Y - attribute \src "ls180.v:8024.7-8024.62" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8025$2693_Y - case - end - attribute \src "ls180.v:8027.6-8027.10" - case - attribute \src "ls180.v:8028.3-8030.6" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:8028.7-8028.59" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8029$2694_Y - case - end - end - attribute \src "ls180.v:8032.2-8038.5" - switch $or$ls180.v:8032$2696_Y - attribute \src "ls180.v:8032.6-8032.108" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:8039.2-8053.5" - switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:8039.6-8039.43" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:8041.3-8045.6" - switch 1'0 - attribute \src "ls180.v:8043.7-8043.11" - case - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:8046.6-8046.10" - case - attribute \src "ls180.v:8047.3-8052.6" - switch $not$ls180.v:8047$2697_Y - attribute \src "ls180.v:8047.7-8047.47" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8048$2698_Y - attribute \src "ls180.v:8049.4-8051.7" - switch $eq$ls180.v:8049$2699_Y - attribute \src "ls180.v:8049.8-8049.55" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:8055.2-8061.5" - switch $not$ls180.v:8055$2700_Y - attribute \src "ls180.v:8055.6-8055.23" - case 1'1 - assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:8057.6-8057.10" - case - attribute \src "ls180.v:8058.3-8060.6" - switch $not$ls180.v:8058$2701_Y - attribute \src "ls180.v:8058.7-8058.30" - case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:8059$2702_Y - case - end - end - attribute \src "ls180.v:8062.2-8068.5" - switch $not$ls180.v:8062$2703_Y - attribute \src "ls180.v:8062.6-8062.23" - case 1'1 - assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:8064.6-8064.10" - case - attribute \src "ls180.v:8065.3-8067.6" - switch $not$ls180.v:8065$2704_Y - attribute \src "ls180.v:8065.7-8065.30" - case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:8066$2705_Y - case - end - end - attribute \src "ls180.v:8069.2-8124.5" - switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:8069.6-8069.30" - case 1'1 - attribute \src "ls180.v:8070.3-8123.10" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - attribute \src "ls180.v:8072.5-8082.8" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8072.9-8072.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:8074.9-8074.13" - case - attribute \src "ls180.v:8075.6-8081.9" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8075.10-8075.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:8077.10-8077.14" - case - attribute \src "ls180.v:8078.7-8080.10" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8078.11-8078.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'01 - attribute \src "ls180.v:8085.5-8095.8" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8085.9-8085.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:8087.9-8087.13" - case - attribute \src "ls180.v:8088.6-8094.9" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8088.10-8088.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:8090.10-8090.14" - case - attribute \src "ls180.v:8091.7-8093.10" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8091.11-8091.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - attribute \src "ls180.v:8098.5-8108.8" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8098.9-8098.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:8100.9-8100.13" - case - attribute \src "ls180.v:8101.6-8107.9" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8101.10-8101.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:8103.10-8103.14" - case - attribute \src "ls180.v:8104.7-8106.10" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8104.11-8104.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - attribute \src "ls180.v:8111.5-8121.8" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8111.9-8111.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:8113.9-8113.13" - case - attribute \src "ls180.v:8114.6-8120.9" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8114.10-8114.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:8116.10-8116.14" - case - attribute \src "ls180.v:8117.7-8119.10" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8117.11-8117.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - case - end - end - end - case - end - case - end - attribute \src "ls180.v:8125.2-8180.5" - switch \main_sdram_choose_req_ce - attribute \src "ls180.v:8125.6-8125.30" - case 1'1 - attribute \src "ls180.v:8126.3-8179.10" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - attribute \src "ls180.v:8128.5-8138.8" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8128.9-8128.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:8130.9-8130.13" - case - attribute \src "ls180.v:8131.6-8137.9" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8131.10-8131.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:8133.10-8133.14" - case - attribute \src "ls180.v:8134.7-8136.10" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8134.11-8134.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'01 - attribute \src "ls180.v:8141.5-8151.8" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8141.9-8141.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:8143.9-8143.13" - case - attribute \src "ls180.v:8144.6-8150.9" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8144.10-8144.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:8146.10-8146.14" - case - attribute \src "ls180.v:8147.7-8149.10" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8147.11-8147.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - attribute \src "ls180.v:8154.5-8164.8" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8154.9-8154.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:8156.9-8156.13" - case - attribute \src "ls180.v:8157.6-8163.9" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8157.10-8157.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:8159.10-8159.14" - case - attribute \src "ls180.v:8160.7-8162.10" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8160.11-8160.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - attribute \src "ls180.v:8167.5-8177.8" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8167.9-8167.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:8169.9-8169.13" - case - attribute \src "ls180.v:8170.6-8176.9" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8170.10-8170.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:8172.10-8172.14" - case - attribute \src "ls180.v:8173.7-8175.10" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8173.11-8173.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - case - end - end - end - case - end - case - end - attribute \src "ls180.v:8189.2-8203.5" - switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:8189.6-8189.30" - case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:8191.3-8195.6" - switch 1'1 - attribute \src "ls180.v:8191.7-8191.11" - case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:8196.6-8196.10" - case - attribute \src "ls180.v:8197.3-8202.6" - switch $not$ls180.v:8197$2709_Y - attribute \src "ls180.v:8197.7-8197.34" - case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8198$2710_Y - attribute \src "ls180.v:8199.4-8201.7" - switch $eq$ls180.v:8199$2711_Y - attribute \src "ls180.v:8199.8-8199.42" - case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:8204.2-8218.5" - switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:8204.6-8204.30" - case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:8206.3-8210.6" - switch 1'0 - attribute \src "ls180.v:8208.7-8208.11" - case - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:8211.6-8211.10" - case - attribute \src "ls180.v:8212.3-8217.6" - switch $not$ls180.v:8212$2712_Y - attribute \src "ls180.v:8212.7-8212.34" - case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8213$2713_Y - attribute \src "ls180.v:8214.4-8216.7" - switch $eq$ls180.v:8214$2714_Y - attribute \src "ls180.v:8214.8-8214.42" - case 1'1 - assign $0\main_sdram_twtrcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:8225.2-8227.5" - switch $or$ls180.v:8225$2739_Y - attribute \src "ls180.v:8225.6-8225.50" - case 1'1 - assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r - case - end - attribute \src "ls180.v:8229.2-8231.5" - switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:8229.6-8229.52" - case 1'1 - assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value - case - end - attribute \src "ls180.v:8232.2-8235.5" - switch \main_converter_reset - attribute \src "ls180.v:8232.6-8232.26" - case 1'1 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 - case - end - attribute \src "ls180.v:8236.2-8246.5" - switch \main_litedram_wb_ack - attribute \src "ls180.v:8236.6-8236.26" - case 1'1 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:8239.6-8239.10" - case - attribute \src "ls180.v:8240.3-8242.6" - switch $and$ls180.v:8240$2740_Y - attribute \src "ls180.v:8240.7-8240.50" - case 1'1 - assign $0\main_cmd_consumed[0:0] 1'1 - case - end - attribute \src "ls180.v:8243.3-8245.6" - switch $and$ls180.v:8243$2741_Y - attribute \src "ls180.v:8243.7-8243.54" - case 1'1 - assign $0\main_wdata_consumed[0:0] 1'1 - case - end - end - attribute \src "ls180.v:8248.2-8269.5" - switch $and$ls180.v:8248$2745_Y - attribute \src "ls180.v:8248.6-8248.91" - case 1'1 - assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data - assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 - assign $0\main_uart_phy_tx_busy[0:0] 1'1 - assign $0\uart_tx[0:0] 1'0 - attribute \src "ls180.v:8253.6-8253.10" - case - attribute \src "ls180.v:8254.3-8268.6" - switch $and$ls180.v:8254$2746_Y - attribute \src "ls180.v:8254.7-8254.60" - case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8255$2747_Y - attribute \src "ls180.v:8256.4-8267.7" - switch $eq$ls180.v:8256$2748_Y - attribute \src "ls180.v:8256.8-8256.43" - case 1'1 - assign $0\uart_tx[0:0] 1'1 - attribute \src "ls180.v:8258.8-8258.12" - case - attribute \src "ls180.v:8259.5-8266.8" - switch $eq$ls180.v:8259$2749_Y - attribute \src "ls180.v:8259.9-8259.44" - case 1'1 - assign $0\uart_tx[0:0] 1'1 - assign $0\main_uart_phy_tx_busy[0:0] 1'0 - assign $0\main_uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:8263.9-8263.13" - case - assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] - assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } - end - end - case - end - end - attribute \src "ls180.v:8270.2-8274.5" - switch \main_uart_phy_tx_busy - attribute \src "ls180.v:8270.6-8270.27" - case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8271$2750_Y - attribute \src "ls180.v:8272.6-8272.10" - case - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } - end - attribute \src "ls180.v:8277.2-8301.5" - switch $not$ls180.v:8277$2751_Y - attribute \src "ls180.v:8277.6-8277.30" - case 1'1 - attribute \src "ls180.v:8278.3-8281.6" - switch $and$ls180.v:8278$2753_Y - attribute \src "ls180.v:8278.7-8278.49" - case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 - case - end - attribute \src "ls180.v:8282.6-8282.10" - case - attribute \src "ls180.v:8283.3-8300.6" - switch \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:8283.7-8283.34" - case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8284$2754_Y - attribute \src "ls180.v:8285.4-8299.7" - switch $eq$ls180.v:8285$2755_Y - attribute \src "ls180.v:8285.8-8285.43" - case 1'1 - attribute \src "ls180.v:8286.5-8288.8" - switch \main_uart_phy_rx - attribute \src "ls180.v:8286.9-8286.25" - case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - case - end - attribute \src "ls180.v:8289.8-8289.12" - case - attribute \src "ls180.v:8290.5-8298.8" - switch $eq$ls180.v:8290$2756_Y - attribute \src "ls180.v:8290.9-8290.44" - case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:8292.6-8295.9" - switch \main_uart_phy_rx - attribute \src "ls180.v:8292.10-8292.26" - case 1'1 - assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg - assign $0\main_uart_phy_source_valid[0:0] 1'1 - case - end - attribute \src "ls180.v:8296.9-8296.13" - case - assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } - end - end - case - end - end - attribute \src "ls180.v:8302.2-8306.5" - switch \main_uart_phy_rx_busy - attribute \src "ls180.v:8302.6-8302.27" - case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8303$2757_Y - attribute \src "ls180.v:8304.6-8304.10" - case - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 - end - attribute \src "ls180.v:8307.2-8309.5" - switch \main_uart_tx_clear - attribute \src "ls180.v:8307.6-8307.24" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:8311.2-8313.5" - switch $and$ls180.v:8311$2759_Y - attribute \src "ls180.v:8311.6-8311.58" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:8314.2-8316.5" - switch \main_uart_rx_clear - attribute \src "ls180.v:8314.6-8314.24" - case 1'1 - assign $0\main_uart_rx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:8318.2-8320.5" - switch $and$ls180.v:8318$2761_Y - attribute \src "ls180.v:8318.6-8318.58" - case 1'1 - assign $0\main_uart_rx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:8321.2-8327.5" - switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:8321.6-8321.35" - case 1'1 - assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8323.6-8323.10" - case - attribute \src "ls180.v:8324.3-8326.6" - switch \main_uart_tx_fifo_re - attribute \src "ls180.v:8324.7-8324.27" - case 1'1 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8328.2-8330.5" - switch $and$ls180.v:8328$2764_Y - attribute \src "ls180.v:8328.6-8328.108" - case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8329$2765_Y - case - end - attribute \src "ls180.v:8331.2-8333.5" - switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8331.6-8331.31" - case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8332$2766_Y - case - end - attribute \src "ls180.v:8334.2-8342.5" - switch $and$ls180.v:8334$2769_Y - attribute \src "ls180.v:8334.6-8334.108" - case 1'1 - attribute \src "ls180.v:8335.3-8337.6" - switch $not$ls180.v:8335$2770_Y - attribute \src "ls180.v:8335.7-8335.35" - case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8336$2771_Y - case - end - attribute \src "ls180.v:8338.6-8338.10" - case - attribute \src "ls180.v:8339.3-8341.6" - switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8339.7-8339.32" - case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8340$2772_Y - case - end - end - attribute \src "ls180.v:8343.2-8349.5" - switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8343.6-8343.35" - case 1'1 - assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8345.6-8345.10" - case - attribute \src "ls180.v:8346.3-8348.6" - switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8346.7-8346.27" - case 1'1 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8350.2-8352.5" - switch $and$ls180.v:8350$2775_Y - attribute \src "ls180.v:8350.6-8350.108" - case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8351$2776_Y - case - end - attribute \src "ls180.v:8353.2-8355.5" - switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8353.6-8353.31" - case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8354$2777_Y - case - end - attribute \src "ls180.v:8356.2-8364.5" - switch $and$ls180.v:8356$2780_Y - attribute \src "ls180.v:8356.6-8356.108" - case 1'1 - attribute \src "ls180.v:8357.3-8359.6" - switch $not$ls180.v:8357$2781_Y - attribute \src "ls180.v:8357.7-8357.35" - case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8358$2782_Y - case - end - attribute \src "ls180.v:8360.6-8360.10" - case - attribute \src "ls180.v:8361.3-8363.6" - switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8361.7-8361.32" - case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8362$2783_Y - case - end - end - attribute \src "ls180.v:8365.2-8378.5" - switch \main_uart_reset - attribute \src "ls180.v:8365.6-8365.21" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'0 - assign $0\main_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_uart_rx_pending[0:0] 1'0 - assign $0\main_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - case - end - attribute \src "ls180.v:8380.2-8387.5" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8380.6-8380.31" - case 1'1 - assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable - attribute \src "ls180.v:8382.6-8382.10" - case - attribute \src "ls180.v:8383.3-8386.6" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8383.7-8383.32" - case 1'1 - assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - assign $0\spisdcard_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8389.2-8399.5" - switch \main_spimaster28_mosi_latch - attribute \src "ls180.v:8389.6-8389.33" - case 1'1 - assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi - assign $0\main_spimaster34_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8392.6-8392.10" - case - attribute \src "ls180.v:8393.3-8398.6" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8393.7-8393.32" - case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8397$2788_Y - attribute \src "ls180.v:8394.4-8396.7" - switch \main_spimaster26_cs_enable - attribute \src "ls180.v:8394.8-8394.34" - case 1'1 - assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 - case - end - case - end - end - attribute \src "ls180.v:8400.2-8406.5" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8400.6-8400.31" - case 1'1 - attribute \src "ls180.v:8401.3-8405.6" - switch \main_spimaster7_loopback - attribute \src "ls180.v:8401.7-8401.31" - case 1'1 - assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8403.7-8403.11" - case - assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } - end - case - end - attribute \src "ls180.v:8407.2-8409.5" - switch \main_spimaster29_miso_latch - attribute \src "ls180.v:8407.6-8407.33" - case 1'1 - assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data - case - end - attribute \src "ls180.v:8411.2-8413.5" - switch \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:8411.6-8411.53" - case 1'1 - assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value - case - end - attribute \src "ls180.v:8415.2-8422.5" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8415.6-8415.29" - case 1'1 - assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable - attribute \src "ls180.v:8417.6-8417.10" - case - attribute \src "ls180.v:8418.3-8421.6" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8418.7-8418.30" - case 1'1 - assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - assign $0\spimaster_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8424.2-8434.5" - switch \main_spisdcard_mosi_latch - attribute \src "ls180.v:8424.6-8424.31" - case 1'1 - assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi - assign $0\main_spisdcard_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8427.6-8427.10" - case - attribute \src "ls180.v:8428.3-8433.6" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8428.7-8428.30" - case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8432$2793_Y - attribute \src "ls180.v:8429.4-8431.7" - switch \main_spisdcard_cs_enable - attribute \src "ls180.v:8429.8-8429.32" - case 1'1 - assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 - case - end - case - end - end - attribute \src "ls180.v:8435.2-8441.5" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8435.6-8435.29" - case 1'1 - attribute \src "ls180.v:8436.3-8440.6" - switch \main_spisdcard_loopback - attribute \src "ls180.v:8436.7-8436.30" - case 1'1 - assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } - attribute \src "ls180.v:8438.7-8438.11" - case - assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } - end - case - end - attribute \src "ls180.v:8442.2-8444.5" - switch \main_spisdcard_miso_latch - attribute \src "ls180.v:8442.6-8442.31" - case 1'1 - assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data - case - end - attribute \src "ls180.v:8446.2-8448.5" - switch \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:8446.6-8446.51" - case 1'1 - assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value - case - end - attribute \src "ls180.v:8449.2-8462.5" - switch \main_pwm0_enable - attribute \src "ls180.v:8449.6-8449.22" - case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8450$2794_Y - attribute \src "ls180.v:8451.3-8455.6" - switch $lt$ls180.v:8451$2795_Y - attribute \src "ls180.v:8451.7-8451.44" - case 1'1 - assign $0\pwm[1:0] [0] 1'1 - attribute \src "ls180.v:8453.7-8453.11" - case - assign $0\pwm[1:0] [0] 1'0 - end - attribute \src "ls180.v:8456.3-8458.6" - switch $ge$ls180.v:8456$2797_Y - attribute \src "ls180.v:8456.7-8456.55" - case 1'1 - assign $0\main_pwm0_counter[31:0] 0 - case - end - attribute \src "ls180.v:8459.6-8459.10" - case - assign $0\main_pwm0_counter[31:0] 0 - assign $0\pwm[1:0] [0] 1'0 - end - attribute \src "ls180.v:8463.2-8476.5" - switch \main_pwm1_enable - attribute \src "ls180.v:8463.6-8463.22" - case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8464$2798_Y - attribute \src "ls180.v:8465.3-8469.6" - switch $lt$ls180.v:8465$2799_Y - attribute \src "ls180.v:8465.7-8465.44" - case 1'1 - assign $0\pwm[1:0] [1] 1'1 - attribute \src "ls180.v:8467.7-8467.11" - case - assign $0\pwm[1:0] [1] 1'0 - end - attribute \src "ls180.v:8470.3-8472.6" - switch $ge$ls180.v:8470$2801_Y - attribute \src "ls180.v:8470.7-8470.55" - case 1'1 - assign $0\main_pwm1_counter[31:0] 0 - case - end - attribute \src "ls180.v:8473.6-8473.10" - case - assign $0\main_pwm1_counter[31:0] 0 - assign $0\pwm[1:0] [1] 1'0 - end - attribute \src "ls180.v:8477.2-8479.5" - switch $not$ls180.v:8477$2802_Y - attribute \src "ls180.v:8477.6-8477.32" - case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8478$2803_Y - case - end - attribute \src "ls180.v:8483.2-8485.5" - switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8483.6-8483.57" - case 1'1 - assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value - case - end - attribute \src "ls180.v:8487.2-8489.5" - switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8487.6-8487.57" - case 1'1 - assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - case - end - attribute \src "ls180.v:8490.2-8492.5" - switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8490.6-8490.40" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8491$2804_Y - case - end - attribute \src "ls180.v:8493.2-8495.5" - switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8493.6-8493.49" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8496.2-8503.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8496.6-8496.46" - case 1'1 - attribute \src "ls180.v:8497.3-8502.6" - switch $or$ls180.v:8497$2806_Y - attribute \src "ls180.v:8497.7-8497.98" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8500.7-8500.11" - case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8501$2807_Y - end - case - end - attribute \src "ls180.v:8504.2-8517.5" - switch $and$ls180.v:8504$2808_Y - attribute \src "ls180.v:8504.6-8504.97" - case 1'1 - attribute \src "ls180.v:8505.3-8511.6" - switch $and$ls180.v:8505$2809_Y - attribute \src "ls180.v:8505.7-8505.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8508.7-8508.11" - case - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8512.6-8512.10" - case - attribute \src "ls180.v:8513.3-8516.6" - switch $and$ls180.v:8513$2810_Y - attribute \src "ls180.v:8513.7-8513.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8514$2811_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8515$2812_Y - case - end - end - attribute \src "ls180.v:8518.2-8545.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8518.6-8518.46" - case 1'1 - attribute \src "ls180.v:8519.3-8544.10" - switch \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8546.2-8548.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8546.6-8546.46" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8547$2813_Y - case - end - attribute \src "ls180.v:8549.2-8554.5" - switch $or$ls180.v:8549$2815_Y - attribute \src "ls180.v:8549.6-8549.88" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid - assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first - assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last - assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data - case - end - attribute \src "ls180.v:8555.2-8560.5" - switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8555.6-8555.32" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8562.2-8564.5" - switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8562.6-8562.58" - case 1'1 - assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - case - end - attribute \src "ls180.v:8565.2-8567.5" - switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8565.6-8565.60" - case 1'1 - assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - case - end - attribute \src "ls180.v:8568.2-8570.5" - switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8568.6-8568.63" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - case - end - attribute \src "ls180.v:8571.2-8573.5" - switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8571.6-8571.41" - case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8572$2816_Y - case - end - attribute \src "ls180.v:8574.2-8576.5" - switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8574.6-8574.50" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8577.2-8584.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8577.6-8577.47" - case 1'1 - attribute \src "ls180.v:8578.3-8583.6" - switch $or$ls180.v:8578$2818_Y - attribute \src "ls180.v:8578.7-8578.100" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8581.7-8581.11" - case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8582$2819_Y - end - case - end - attribute \src "ls180.v:8585.2-8598.5" - switch $and$ls180.v:8585$2820_Y - attribute \src "ls180.v:8585.6-8585.99" - case 1'1 - attribute \src "ls180.v:8586.3-8592.6" - switch $and$ls180.v:8586$2821_Y - attribute \src "ls180.v:8586.7-8586.96" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8589.7-8589.11" - case - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8593.6-8593.10" - case - attribute \src "ls180.v:8594.3-8597.6" - switch $and$ls180.v:8594$2822_Y - attribute \src "ls180.v:8594.7-8594.96" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8595$2823_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8596$2824_Y - case - end - end - attribute \src "ls180.v:8599.2-8626.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8599.6-8599.47" - case 1'1 - attribute \src "ls180.v:8600.3-8625.10" - switch \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8627.2-8629.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8627.6-8627.47" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8628$2825_Y - case - end - attribute \src "ls180.v:8630.2-8635.5" - switch $or$ls180.v:8630$2827_Y - attribute \src "ls180.v:8630.6-8630.90" - case 1'1 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid - assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first - assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last - assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data - case - end - attribute \src "ls180.v:8636.2-8641.5" - switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8636.6-8636.33" - case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8643.2-8645.5" - switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8643.6-8643.63" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - case - end - attribute \src "ls180.v:8647.2-8649.5" - switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8647.6-8647.52" - case 1'1 - assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value - case - end - attribute \src "ls180.v:8650.2-8652.5" - switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8650.6-8650.42" - case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8651$2828_Y - case - end - attribute \src "ls180.v:8653.2-8655.5" - switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8653.6-8653.51" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8656.2-8663.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8656.6-8656.48" - case 1'1 - attribute \src "ls180.v:8657.3-8662.6" - switch $or$ls180.v:8657$2830_Y - attribute \src "ls180.v:8657.7-8657.102" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8660.7-8660.11" - case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8661$2831_Y - end - case - end - attribute \src "ls180.v:8664.2-8677.5" - switch $and$ls180.v:8664$2832_Y - attribute \src "ls180.v:8664.6-8664.101" - case 1'1 - attribute \src "ls180.v:8665.3-8671.6" - switch $and$ls180.v:8665$2833_Y - attribute \src "ls180.v:8665.7-8665.98" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8668.7-8668.11" - case - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8672.6-8672.10" - case - attribute \src "ls180.v:8673.3-8676.6" - switch $and$ls180.v:8673$2834_Y - attribute \src "ls180.v:8673.7-8673.98" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8674$2835_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8675$2836_Y - case - end - end - attribute \src "ls180.v:8678.2-8687.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8678.6-8678.48" - case 1'1 - attribute \src "ls180.v:8679.3-8686.10" - switch \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8688.2-8690.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8688.6-8688.48" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8689$2837_Y - case - end - attribute \src "ls180.v:8691.2-8696.5" - switch $or$ls180.v:8691$2839_Y - attribute \src "ls180.v:8691.6-8691.92" - case 1'1 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid - assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first - assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last - assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data - case - end - attribute \src "ls180.v:8697.2-8702.5" - switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8697.6-8697.34" - case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8704.2-8706.5" - switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8704.6-8704.60" - case 1'1 - assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - case - end - attribute \src "ls180.v:8707.2-8709.5" - switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8707.6-8707.62" - case 1'1 - assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - case - end - attribute \src "ls180.v:8710.2-8712.5" - switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8710.6-8710.66" - case 1'1 - assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - case - end - attribute \src "ls180.v:8713.2-8719.5" - switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8713.6-8713.35" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8715.6-8715.10" - case - attribute \src "ls180.v:8716.3-8718.6" - switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8716.7-8716.39" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 - case - end - end - attribute \src "ls180.v:8720.2-8726.5" - switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8720.6-8720.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8722.6-8722.10" - case - attribute \src "ls180.v:8723.3-8725.6" - switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8723.7-8723.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:8727.2-8733.5" - switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8727.6-8727.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8729.6-8729.10" - case - attribute \src "ls180.v:8730.3-8732.6" - switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8730.7-8730.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:8734.2-8740.5" - switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8734.6-8734.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8736.6-8736.10" - case - attribute \src "ls180.v:8737.3-8739.6" - switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8737.7-8737.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:8741.2-8747.5" - switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8741.6-8741.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8743.6-8743.10" - case - attribute \src "ls180.v:8744.3-8746.6" - switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8744.7-8744.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:8749.2-8751.5" - switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8749.6-8749.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - case - end - attribute \src "ls180.v:8752.2-8754.5" - switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8752.6-8752.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - case - end - attribute \src "ls180.v:8755.2-8757.5" - switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8755.6-8755.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - case - end - attribute \src "ls180.v:8758.2-8760.5" - switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8758.6-8758.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - case - end - attribute \src "ls180.v:8761.2-8763.5" - switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8761.6-8761.78" - case 1'1 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - case - end - attribute \src "ls180.v:8764.2-8766.5" - switch $and$ls180.v:8764$2840_Y - attribute \src "ls180.v:8764.6-8764.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc - case - end - attribute \src "ls180.v:8767.2-8769.5" - switch $and$ls180.v:8767$2841_Y - attribute \src "ls180.v:8767.6-8767.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc - case - end - attribute \src "ls180.v:8770.2-8772.5" - switch $and$ls180.v:8770$2842_Y - attribute \src "ls180.v:8770.6-8770.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc - case - end - attribute \src "ls180.v:8773.2-8775.5" - switch $and$ls180.v:8773$2843_Y - attribute \src "ls180.v:8773.6-8773.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc - case - end - attribute \src "ls180.v:8776.2-8780.5" - switch $and$ls180.v:8776$2844_Y - attribute \src "ls180.v:8776.6-8776.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } - assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] - case - end - attribute \src "ls180.v:8781.2-8785.5" - switch $and$ls180.v:8781$2845_Y - attribute \src "ls180.v:8781.6-8781.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } - assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] - case - end - attribute \src "ls180.v:8786.2-8790.5" - switch $and$ls180.v:8786$2846_Y - attribute \src "ls180.v:8786.6-8786.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } - assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] - case - end - attribute \src "ls180.v:8791.2-8795.5" - switch $and$ls180.v:8791$2847_Y - attribute \src "ls180.v:8791.6-8791.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } - assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] - case - end - attribute \src "ls180.v:8796.2-8804.5" - switch $and$ls180.v:8796$2848_Y - attribute \src "ls180.v:8796.6-8796.83" - case 1'1 - attribute \src "ls180.v:8797.3-8803.6" - switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8797.7-8797.42" - case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8799.7-8799.11" - case - attribute \src "ls180.v:8800.4-8802.7" - switch $ne$ls180.v:8800$2849_Y - attribute \src "ls180.v:8800.8-8800.48" - case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8801$2850_Y - case - end - end - case - end - attribute \src "ls180.v:8805.2-8811.5" - switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8805.6-8805.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8807.6-8807.10" - case - attribute \src "ls180.v:8808.3-8810.6" - switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8808.7-8808.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:8812.2-8818.5" - switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8812.6-8812.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8814.6-8814.10" - case - attribute \src "ls180.v:8815.3-8817.6" - switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8815.7-8815.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:8819.2-8825.5" - switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8819.6-8819.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8821.6-8821.10" - case - attribute \src "ls180.v:8822.3-8824.6" - switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8822.7-8822.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:8826.2-8832.5" - switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8826.6-8826.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8828.6-8828.10" - case - attribute \src "ls180.v:8829.3-8831.6" - switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8829.7-8829.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:8834.2-8836.5" - switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8834.6-8834.52" - case 1'1 - assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 - case - end - attribute \src "ls180.v:8837.2-8839.5" - switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8837.6-8837.53" - case 1'1 - assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 - case - end - attribute \src "ls180.v:8840.2-8842.5" - switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8840.6-8840.53" - case 1'1 - assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 - case - end - attribute \src "ls180.v:8843.2-8845.5" - switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8843.6-8843.54" - case 1'1 - assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 - case - end - attribute \src "ls180.v:8846.2-8848.5" - switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8846.6-8846.53" - case 1'1 - assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 - case - end - attribute \src "ls180.v:8849.2-8851.5" - switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8849.6-8849.55" - case 1'1 - assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - case - end - attribute \src "ls180.v:8852.2-8854.5" - switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8852.6-8852.54" - case 1'1 - assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 - case - end - attribute \src "ls180.v:8855.2-8857.5" - switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8855.6-8855.56" - case 1'1 - assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 - case - end - attribute \src "ls180.v:8858.2-8860.5" - switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8858.6-8858.63" - case 1'1 - assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - case - end - attribute \src "ls180.v:8861.2-8863.5" - switch $and$ls180.v:8861$2853_Y - attribute \src "ls180.v:8861.6-8861.120" - case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8862$2854_Y - case - end - attribute \src "ls180.v:8864.2-8866.5" - switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8864.6-8864.35" - case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8865$2855_Y - case - end - attribute \src "ls180.v:8867.2-8875.5" - switch $and$ls180.v:8867$2858_Y - attribute \src "ls180.v:8867.6-8867.120" - case 1'1 - attribute \src "ls180.v:8868.3-8870.6" - switch $not$ls180.v:8868$2859_Y - attribute \src "ls180.v:8868.7-8868.39" - case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8869$2860_Y - case - end - attribute \src "ls180.v:8871.6-8871.10" - case - attribute \src "ls180.v:8872.3-8874.6" - switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8872.7-8872.36" - case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8873$2861_Y - case - end - end - attribute \src "ls180.v:8876.2-8878.5" - switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8876.6-8876.45" - case 1'1 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8879.2-8886.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8879.6-8879.42" - case 1'1 - attribute \src "ls180.v:8880.3-8885.6" - switch $or$ls180.v:8880$2863_Y - attribute \src "ls180.v:8880.7-8880.90" - case 1'1 - assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8883.7-8883.11" - case - assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8884$2864_Y - end - case - end - attribute \src "ls180.v:8887.2-8900.5" - switch $and$ls180.v:8887$2865_Y - attribute \src "ls180.v:8887.6-8887.89" - case 1'1 - attribute \src "ls180.v:8888.3-8894.6" - switch $and$ls180.v:8888$2866_Y - attribute \src "ls180.v:8888.7-8888.86" - case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first - assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8891.7-8891.11" - case - assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 - assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8895.6-8895.10" - case - attribute \src "ls180.v:8896.3-8899.6" - switch $and$ls180.v:8896$2867_Y - attribute \src "ls180.v:8896.7-8896.86" - case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8897$2868_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8898$2869_Y - case - end - end - attribute \src "ls180.v:8901.2-8928.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8901.6-8901.42" - case 1'1 - attribute \src "ls180.v:8902.3-8927.10" - switch \main_sdblock2mem_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [63:56] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [55:48] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [47:40] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [39:32] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [31:24] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [23:16] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [15:8] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [7:0] \main_sdblock2mem_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8929.2-8931.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8929.6-8929.42" - case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8930$2870_Y - case - end - attribute \src "ls180.v:8933.2-8935.5" - switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8933.6-8933.76" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - case - end - attribute \src "ls180.v:8936.2-8939.5" - switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8936.6-8936.46" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - case - end - attribute \src "ls180.v:8941.2-8943.5" - switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8941.6-8941.64" - case 1'1 - assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - case - end - attribute \src "ls180.v:8945.2-8947.5" - switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8945.6-8945.76" - case 1'1 - assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - case - end - attribute \src "ls180.v:8948.2-8951.5" - switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8948.6-8948.32" - case 1'1 - assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - case - end - attribute \src "ls180.v:8952.2-8958.5" - switch $and$ls180.v:8952$2871_Y - attribute \src "ls180.v:8952.6-8952.89" - case 1'1 - attribute \src "ls180.v:8953.3-8957.6" - switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8953.7-8953.38" - case 1'1 - assign $0\main_sdmem2block_converter_mux[2:0] 3'000 - attribute \src "ls180.v:8955.7-8955.11" - case - assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8956$2872_Y - end - case - end - attribute \src "ls180.v:8959.2-8961.5" - switch $and$ls180.v:8959$2875_Y - attribute \src "ls180.v:8959.6-8959.120" - case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8960$2876_Y - case - end - attribute \src "ls180.v:8962.2-8964.5" - switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8962.6-8962.35" - case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8963$2877_Y - case - end - attribute \src "ls180.v:8965.2-8973.5" - switch $and$ls180.v:8965$2880_Y - attribute \src "ls180.v:8965.6-8965.120" - case 1'1 - attribute \src "ls180.v:8966.3-8968.6" - switch $not$ls180.v:8966$2881_Y - attribute \src "ls180.v:8966.7-8966.39" - case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8967$2882_Y - case - end - attribute \src "ls180.v:8969.6-8969.10" - case - attribute \src "ls180.v:8970.3-8972.6" - switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8970.7-8970.36" - case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8971$2883_Y - case - end - end - attribute \src "ls180.v:8975.2-8977.5" - switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8975.6-8975.46" - case 1'1 - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 - case - end - attribute \src "ls180.v:8978.2-8980.5" - switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8978.6-8978.44" - case 1'1 - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 - case - end - attribute \src "ls180.v:8981.2-8983.5" - switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8981.6-8981.43" - case 1'1 - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 - case - end - attribute \src "ls180.v:8984.2-9080.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - attribute \src "ls180.v:8986.4-9002.7" - switch $not$ls180.v:8986$2884_Y - attribute \src "ls180.v:8986.8-8986.29" - case 1'1 - attribute \src "ls180.v:8987.5-9001.8" - switch \builder_request [1] - attribute \src "ls180.v:8987.9-8987.27" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8989.9-8989.13" - case - attribute \src "ls180.v:8990.6-9000.9" - switch \builder_request [2] - attribute \src "ls180.v:8990.10-8990.28" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8992.10-8992.14" - case - attribute \src "ls180.v:8993.7-8999.10" - switch \builder_request [3] - attribute \src "ls180.v:8993.11-8993.29" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8995.11-8995.15" - case - attribute \src "ls180.v:8996.8-8998.11" - switch \builder_request [4] - attribute \src "ls180.v:8996.12-8996.30" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'001 - attribute \src "ls180.v:9005.4-9021.7" - switch $not$ls180.v:9005$2885_Y - attribute \src "ls180.v:9005.8-9005.29" - case 1'1 - attribute \src "ls180.v:9006.5-9020.8" - switch \builder_request [2] - attribute \src "ls180.v:9006.9-9006.27" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:9008.9-9008.13" - case - attribute \src "ls180.v:9009.6-9019.9" - switch \builder_request [3] - attribute \src "ls180.v:9009.10-9009.28" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:9011.10-9011.14" - case - attribute \src "ls180.v:9012.7-9018.10" - switch \builder_request [4] - attribute \src "ls180.v:9012.11-9012.29" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9014.11-9014.15" - case - attribute \src "ls180.v:9015.8-9017.11" - switch \builder_request [0] - attribute \src "ls180.v:9015.12-9015.30" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - attribute \src "ls180.v:9024.4-9040.7" - switch $not$ls180.v:9024$2886_Y - attribute \src "ls180.v:9024.8-9024.29" - case 1'1 - attribute \src "ls180.v:9025.5-9039.8" - switch \builder_request [3] - attribute \src "ls180.v:9025.9-9025.27" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:9027.9-9027.13" - case - attribute \src "ls180.v:9028.6-9038.9" - switch \builder_request [4] - attribute \src "ls180.v:9028.10-9028.28" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9030.10-9030.14" - case - attribute \src "ls180.v:9031.7-9037.10" - switch \builder_request [0] - attribute \src "ls180.v:9031.11-9031.29" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9033.11-9033.15" - case - attribute \src "ls180.v:9034.8-9036.11" - switch \builder_request [1] - attribute \src "ls180.v:9034.12-9034.30" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:9043.4-9059.7" - switch $not$ls180.v:9043$2887_Y - attribute \src "ls180.v:9043.8-9043.29" - case 1'1 - attribute \src "ls180.v:9044.5-9058.8" - switch \builder_request [4] - attribute \src "ls180.v:9044.9-9044.27" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9046.9-9046.13" - case - attribute \src "ls180.v:9047.6-9057.9" - switch \builder_request [0] - attribute \src "ls180.v:9047.10-9047.28" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9049.10-9049.14" - case - attribute \src "ls180.v:9050.7-9056.10" - switch \builder_request [1] - attribute \src "ls180.v:9050.11-9050.29" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:9052.11-9052.15" - case - attribute \src "ls180.v:9053.8-9055.11" - switch \builder_request [2] - attribute \src "ls180.v:9053.12-9053.30" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - attribute \src "ls180.v:9062.4-9078.7" - switch $not$ls180.v:9062$2888_Y - attribute \src "ls180.v:9062.8-9062.29" - case 1'1 - attribute \src "ls180.v:9063.5-9077.8" - switch \builder_request [0] - attribute \src "ls180.v:9063.9-9063.27" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9065.9-9065.13" - case - attribute \src "ls180.v:9066.6-9076.9" - switch \builder_request [1] - attribute \src "ls180.v:9066.10-9066.28" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:9068.10-9068.14" - case - attribute \src "ls180.v:9069.7-9075.10" - switch \builder_request [2] - attribute \src "ls180.v:9069.11-9069.29" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:9071.11-9071.15" - case - attribute \src "ls180.v:9072.8-9074.11" - switch \builder_request [3] - attribute \src "ls180.v:9072.12-9072.30" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - case - end - end - end - end - case - end - case - end - attribute \src "ls180.v:9082.2-9088.5" - switch \builder_wait - attribute \src "ls180.v:9082.6-9082.18" - case 1'1 - attribute \src "ls180.v:9083.3-9085.6" - switch $not$ls180.v:9083$2889_Y - attribute \src "ls180.v:9083.7-9083.22" - case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:9084$2890_Y - case - end - attribute \src "ls180.v:9086.6-9086.10" - case - assign $0\builder_count[19:0] 20'11110100001001000000 - end - attribute \src "ls180.v:9090.2-9120.5" - switch \builder_csrbank0_sel - attribute \src "ls180.v:9090.6-9090.26" - case 1'1 - attribute \src "ls180.v:9091.3-9119.10" - switch \builder_interface0_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w - case - end - case - end - attribute \src "ls180.v:9121.2-9123.5" - switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:9121.6-9121.32" - case 1'1 - assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r - case - end - attribute \src "ls180.v:9125.2-9127.5" - switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:9125.6-9125.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r - case - end - attribute \src "ls180.v:9128.2-9130.5" - switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:9128.6-9128.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r - case - end - attribute \src "ls180.v:9131.2-9133.5" - switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:9131.6-9131.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r - case - end - attribute \src "ls180.v:9134.2-9136.5" - switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:9134.6-9134.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r - case - end - attribute \src "ls180.v:9139.2-9160.5" - switch \builder_csrbank1_sel - attribute \src "ls180.v:9139.6-9139.26" - case 1'1 - attribute \src "ls180.v:9140.3-9159.10" - switch \builder_interface1_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w - case - end - case - end - attribute \src "ls180.v:9161.2-9163.5" - switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:9161.6-9161.29" - case 1'1 - assign $0\main_gpiotristateasic1_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r - case - end - attribute \src "ls180.v:9164.2-9166.5" - switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:9164.6-9164.29" - case 1'1 - assign $0\main_gpiotristateasic1_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r - case - end - attribute \src "ls180.v:9168.2-9170.5" - switch \builder_csrbank1_out1_re - attribute \src "ls180.v:9168.6-9168.30" - case 1'1 - assign $0\main_gpiotristateasic1_out_storage[15:0] [15:8] \builder_csrbank1_out1_r - case - end - attribute \src "ls180.v:9171.2-9173.5" - switch \builder_csrbank1_out0_re - attribute \src "ls180.v:9171.6-9171.30" - case 1'1 - assign $0\main_gpiotristateasic1_out_storage[15:0] [7:0] \builder_csrbank1_out0_r - case - end - attribute \src "ls180.v:9176.2-9185.5" - switch \builder_csrbank2_sel - attribute \src "ls180.v:9176.6-9176.26" - case 1'1 - attribute \src "ls180.v:9177.3-9184.10" - switch \builder_interface2_bank_bus_adr [0] - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } - case - end - case - end - attribute \src "ls180.v:9186.2-9188.5" - switch \builder_csrbank2_w0_re - attribute \src "ls180.v:9186.6-9186.28" - case 1'1 - assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r - case - end - attribute \src "ls180.v:9191.2-9221.5" - switch \builder_csrbank3_sel - attribute \src "ls180.v:9191.6-9191.26" - case 1'1 - attribute \src "ls180.v:9192.3-9220.10" - switch \builder_interface3_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w - case - end - case - end - attribute \src "ls180.v:9222.2-9224.5" - switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:9222.6-9222.33" - case 1'1 - assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r - case - end - attribute \src "ls180.v:9226.2-9228.5" - switch \builder_csrbank3_width3_re - attribute \src "ls180.v:9226.6-9226.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r - case - end - attribute \src "ls180.v:9229.2-9231.5" - switch \builder_csrbank3_width2_re - attribute \src "ls180.v:9229.6-9229.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r - case - end - attribute \src "ls180.v:9232.2-9234.5" - switch \builder_csrbank3_width1_re - attribute \src "ls180.v:9232.6-9232.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r - case - end - attribute \src "ls180.v:9235.2-9237.5" - switch \builder_csrbank3_width0_re - attribute \src "ls180.v:9235.6-9235.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r - case - end - attribute \src "ls180.v:9239.2-9241.5" - switch \builder_csrbank3_period3_re - attribute \src "ls180.v:9239.6-9239.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r - case - end - attribute \src "ls180.v:9242.2-9244.5" - switch \builder_csrbank3_period2_re - attribute \src "ls180.v:9242.6-9242.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r - case - end - attribute \src "ls180.v:9245.2-9247.5" - switch \builder_csrbank3_period1_re - attribute \src "ls180.v:9245.6-9245.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r - case - end - attribute \src "ls180.v:9248.2-9250.5" - switch \builder_csrbank3_period0_re - attribute \src "ls180.v:9248.6-9248.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r - case - end - attribute \src "ls180.v:9253.2-9283.5" - switch \builder_csrbank4_sel - attribute \src "ls180.v:9253.6-9253.26" - case 1'1 - attribute \src "ls180.v:9254.3-9282.10" - switch \builder_interface4_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w - case - end - case - end - attribute \src "ls180.v:9284.2-9286.5" - switch \builder_csrbank4_enable0_re - attribute \src "ls180.v:9284.6-9284.33" - case 1'1 - assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r - case - end - attribute \src "ls180.v:9288.2-9290.5" - switch \builder_csrbank4_width3_re - attribute \src "ls180.v:9288.6-9288.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r - case - end - attribute \src "ls180.v:9291.2-9293.5" - switch \builder_csrbank4_width2_re - attribute \src "ls180.v:9291.6-9291.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r - case - end - attribute \src "ls180.v:9294.2-9296.5" - switch \builder_csrbank4_width1_re - attribute \src "ls180.v:9294.6-9294.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r - case - end - attribute \src "ls180.v:9297.2-9299.5" - switch \builder_csrbank4_width0_re - attribute \src "ls180.v:9297.6-9297.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r - case - end - attribute \src "ls180.v:9301.2-9303.5" - switch \builder_csrbank4_period3_re - attribute \src "ls180.v:9301.6-9301.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r - case - end - attribute \src "ls180.v:9304.2-9306.5" - switch \builder_csrbank4_period2_re - attribute \src "ls180.v:9304.6-9304.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r - case - end - attribute \src "ls180.v:9307.2-9309.5" - switch \builder_csrbank4_period1_re - attribute \src "ls180.v:9307.6-9307.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r - case - end - attribute \src "ls180.v:9310.2-9312.5" - switch \builder_csrbank4_period0_re - attribute \src "ls180.v:9310.6-9310.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r - case - end - attribute \src "ls180.v:9315.2-9363.5" - switch \builder_csrbank5_sel - attribute \src "ls180.v:9315.6-9315.26" - case 1'1 - attribute \src "ls180.v:9316.3-9362.10" - switch \builder_interface5_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 4'1010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } - case - end - case - end - attribute \src "ls180.v:9364.2-9366.5" - switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:9364.6-9364.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r - case - end - attribute \src "ls180.v:9367.2-9369.5" - switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:9367.6-9367.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r - case - end - attribute \src "ls180.v:9370.2-9372.5" - switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:9370.6-9370.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r - case - end - attribute \src "ls180.v:9373.2-9375.5" - switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:9373.6-9373.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r - case - end - attribute \src "ls180.v:9376.2-9378.5" - switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:9376.6-9376.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r - case - end - attribute \src "ls180.v:9379.2-9381.5" - switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:9379.6-9379.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r - case - end - attribute \src "ls180.v:9382.2-9384.5" - switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:9382.6-9382.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r - case - end - attribute \src "ls180.v:9385.2-9387.5" - switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:9385.6-9385.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r - case - end - attribute \src "ls180.v:9389.2-9391.5" - switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:9389.6-9389.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r - case - end - attribute \src "ls180.v:9392.2-9394.5" - switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:9392.6-9392.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r - case - end - attribute \src "ls180.v:9395.2-9397.5" - switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:9395.6-9395.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r - case - end - attribute \src "ls180.v:9398.2-9400.5" - switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:9398.6-9398.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r - case - end - attribute \src "ls180.v:9402.2-9404.5" - switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:9402.6-9402.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r - case - end - attribute \src "ls180.v:9406.2-9408.5" - switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:9406.6-9406.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r - case - end - attribute \src "ls180.v:9411.2-9513.5" - switch \builder_csrbank6_sel - attribute \src "ls180.v:9411.6-9411.26" - case 1'1 - attribute \src "ls180.v:9412.3-9512.10" - switch \builder_interface6_bank_bus_adr [5:0] - attribute \src "ls180.v:0.0-0.0" - case 6'000000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:0.0-0.0" - case 6'000100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:0.0-0.0" - case 6'001000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } - attribute \src "ls180.v:0.0-0.0" - case 6'001001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:0.0-0.0" - case 6'001010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:0.0-0.0" - case 6'001011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:0.0-0.0" - case 6'001100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:0.0-0.0" - case 6'001101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:0.0-0.0" - case 6'001110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:0.0-0.0" - case 6'001111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:0.0-0.0" - case 6'010000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:0.0-0.0" - case 6'010001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:0.0-0.0" - case 6'010010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:0.0-0.0" - case 6'010011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:0.0-0.0" - case 6'010100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:0.0-0.0" - case 6'010101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:0.0-0.0" - case 6'010110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:0.0-0.0" - case 6'010111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:0.0-0.0" - case 6'011000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w - attribute \src "ls180.v:0.0-0.0" - case 6'011110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w - attribute \src "ls180.v:0.0-0.0" - case 6'011111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w - attribute \src "ls180.v:0.0-0.0" - case 6'100000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w - case - end - case - end - attribute \src "ls180.v:9514.2-9516.5" - switch \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:9514.6-9514.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r - case - end - attribute \src "ls180.v:9517.2-9519.5" - switch \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:9517.6-9517.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r - case - end - attribute \src "ls180.v:9520.2-9522.5" - switch \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:9520.6-9520.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r - case - end - attribute \src "ls180.v:9523.2-9525.5" - switch \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:9523.6-9523.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r - case - end - attribute \src "ls180.v:9527.2-9529.5" - switch \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:9527.6-9527.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r - case - end - attribute \src "ls180.v:9530.2-9532.5" - switch \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:9530.6-9530.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r - case - end - attribute \src "ls180.v:9533.2-9535.5" - switch \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:9533.6-9533.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r - case - end - attribute \src "ls180.v:9536.2-9538.5" - switch \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:9536.6-9536.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r - case - end - attribute \src "ls180.v:9540.2-9542.5" - switch \builder_csrbank6_block_length1_re - attribute \src "ls180.v:9540.6-9540.39" - case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r - case - end - attribute \src "ls180.v:9543.2-9545.5" - switch \builder_csrbank6_block_length0_re - attribute \src "ls180.v:9543.6-9543.39" - case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r - case - end - attribute \src "ls180.v:9547.2-9549.5" - switch \builder_csrbank6_block_count3_re - attribute \src "ls180.v:9547.6-9547.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r - case - end - attribute \src "ls180.v:9550.2-9552.5" - switch \builder_csrbank6_block_count2_re - attribute \src "ls180.v:9550.6-9550.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r - case - end - attribute \src "ls180.v:9553.2-9555.5" - switch \builder_csrbank6_block_count1_re - attribute \src "ls180.v:9553.6-9553.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r - case - end - attribute \src "ls180.v:9556.2-9558.5" - switch \builder_csrbank6_block_count0_re - attribute \src "ls180.v:9556.6-9556.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r - case - end - attribute \src "ls180.v:9561.2-9621.5" - switch \builder_csrbank7_sel - attribute \src "ls180.v:9561.6-9561.26" - case 1'1 - attribute \src "ls180.v:9562.3-9620.10" - switch \builder_interface7_bank_bus_adr [4:0] - attribute \src "ls180.v:0.0-0.0" - case 5'00000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 5'00001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 5'00010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 5'00011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 5'00100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 5'01001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 5'01010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 5'01011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:0.0-0.0" - case 5'10000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:0.0-0.0" - case 5'10001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:0.0-0.0" - case 5'10010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w - case - end - case - end - attribute \src "ls180.v:9622.2-9624.5" - switch \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:9622.6-9622.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r - case - end - attribute \src "ls180.v:9625.2-9627.5" - switch \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:9625.6-9625.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r - case - end - attribute \src "ls180.v:9628.2-9630.5" - switch \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:9628.6-9628.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r - case - end - attribute \src "ls180.v:9631.2-9633.5" - switch \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:9631.6-9631.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r - case - end - attribute \src "ls180.v:9634.2-9636.5" - switch \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:9634.6-9634.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r - case - end - attribute \src "ls180.v:9637.2-9639.5" - switch \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:9637.6-9637.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r - case - end - attribute \src "ls180.v:9640.2-9642.5" - switch \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:9640.6-9640.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r - case - end - attribute \src "ls180.v:9643.2-9645.5" - switch \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:9643.6-9643.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r - case - end - attribute \src "ls180.v:9647.2-9649.5" - switch \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:9647.6-9647.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r - case - end - attribute \src "ls180.v:9650.2-9652.5" - switch \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:9650.6-9650.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r - case - end - attribute \src "ls180.v:9653.2-9655.5" - switch \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:9653.6-9653.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r - case - end - attribute \src "ls180.v:9656.2-9658.5" - switch \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:9656.6-9656.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r - case - end - attribute \src "ls180.v:9660.2-9662.5" - switch \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:9660.6-9660.37" - case 1'1 - assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r - case - end - attribute \src "ls180.v:9664.2-9666.5" - switch \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:9664.6-9664.35" - case 1'1 - assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r - case - end - attribute \src "ls180.v:9669.2-9684.5" - switch \builder_csrbank8_sel - attribute \src "ls180.v:9669.6-9669.26" - case 1'1 - attribute \src "ls180.v:9670.3-9683.10" - switch \builder_interface8_bank_bus_adr [1:0] - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } - case - end - case - end - attribute \src "ls180.v:9685.2-9687.5" - switch \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:9685.6-9685.42" - case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r - case - end - attribute \src "ls180.v:9688.2-9690.5" - switch \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:9688.6-9688.42" - case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r - case - end - attribute \src "ls180.v:9693.2-9726.5" - switch \builder_csrbank9_sel - attribute \src "ls180.v:9693.6-9693.26" - case 1'1 - attribute \src "ls180.v:9694.3-9725.10" - switch \builder_interface9_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w - case - end - case - end - attribute \src "ls180.v:9727.2-9729.5" - switch \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:9727.6-9727.39" - case 1'1 - assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r - case - end - attribute \src "ls180.v:9731.2-9733.5" - switch \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:9731.6-9731.43" - case 1'1 - assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r - case - end - attribute \src "ls180.v:9735.2-9737.5" - switch \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:9735.6-9735.43" - case 1'1 - assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r - case - end - attribute \src "ls180.v:9738.2-9740.5" - switch \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:9738.6-9738.43" - case 1'1 - assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r - case - end - attribute \src "ls180.v:9742.2-9744.5" - switch \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:9742.6-9742.44" - case 1'1 - assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r - case - end - attribute \src "ls180.v:9746.2-9748.5" - switch \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9746.6-9746.42" - case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r - case - end - attribute \src "ls180.v:9749.2-9751.5" - switch \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9749.6-9749.42" - case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r - case - end - attribute \src "ls180.v:9754.2-9778.5" - switch \builder_csrbank10_sel - attribute \src "ls180.v:9754.6-9754.27" - case 1'1 - attribute \src "ls180.v:9755.3-9777.10" - switch \builder_interface10_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } - case - end - case - end - attribute \src "ls180.v:9779.2-9781.5" - switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9779.6-9779.35" - case 1'1 - assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r - case - end - attribute \src "ls180.v:9782.2-9784.5" - switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9782.6-9782.35" - case 1'1 - assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r - case - end - attribute \src "ls180.v:9786.2-9788.5" - switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9786.6-9786.32" - case 1'1 - assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r - case - end - attribute \src "ls180.v:9790.2-9792.5" - switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9790.6-9790.30" - case 1'1 - assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r - case - end - attribute \src "ls180.v:9794.2-9796.5" - switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9794.6-9794.36" - case 1'1 - assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r - case - end - attribute \src "ls180.v:9799.2-9829.5" - switch \builder_csrbank11_sel - attribute \src "ls180.v:9799.6-9799.27" - case 1'1 - attribute \src "ls180.v:9800.3-9828.10" - switch \builder_interface11_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w - case - end - case - end - attribute \src "ls180.v:9830.2-9832.5" - switch \builder_csrbank11_control1_re - attribute \src "ls180.v:9830.6-9830.35" - case 1'1 - assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r - case - end - attribute \src "ls180.v:9833.2-9835.5" - switch \builder_csrbank11_control0_re - attribute \src "ls180.v:9833.6-9833.35" - case 1'1 - assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r - case - end - attribute \src "ls180.v:9837.2-9839.5" - switch \builder_csrbank11_mosi0_re - attribute \src "ls180.v:9837.6-9837.32" - case 1'1 - assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r - case - end - attribute \src "ls180.v:9841.2-9843.5" - switch \builder_csrbank11_cs0_re - attribute \src "ls180.v:9841.6-9841.30" - case 1'1 - assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r - case - end - attribute \src "ls180.v:9845.2-9847.5" - switch \builder_csrbank11_loopback0_re - attribute \src "ls180.v:9845.6-9845.36" - case 1'1 - assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r - case - end - attribute \src "ls180.v:9849.2-9851.5" - switch \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:9849.6-9849.39" - case 1'1 - assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r - case - end - attribute \src "ls180.v:9852.2-9854.5" - switch \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:9852.6-9852.39" - case 1'1 - assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r - case - end - attribute \src "ls180.v:9857.2-9911.5" - switch \builder_csrbank12_sel - attribute \src "ls180.v:9857.6-9857.27" - case 1'1 - attribute \src "ls180.v:9858.3-9910.10" - switch \builder_interface12_bank_bus_adr [4:0] - attribute \src "ls180.v:0.0-0.0" - case 5'00000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w - attribute \src "ls180.v:0.0-0.0" - case 5'00100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w - attribute \src "ls180.v:0.0-0.0" - case 5'01011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w - attribute \src "ls180.v:0.0-0.0" - case 5'01100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w - attribute \src "ls180.v:0.0-0.0" - case 5'01101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } - attribute \src "ls180.v:0.0-0.0" - case 5'10000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } - case - end - case - end - attribute \src "ls180.v:9912.2-9914.5" - switch \builder_csrbank12_load3_re - attribute \src "ls180.v:9912.6-9912.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r - case - end - attribute \src "ls180.v:9915.2-9917.5" - switch \builder_csrbank12_load2_re - attribute \src "ls180.v:9915.6-9915.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r - case - end - attribute \src "ls180.v:9918.2-9920.5" - switch \builder_csrbank12_load1_re - attribute \src "ls180.v:9918.6-9918.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r - case - end - attribute \src "ls180.v:9921.2-9923.5" - switch \builder_csrbank12_load0_re - attribute \src "ls180.v:9921.6-9921.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r - case - end - attribute \src "ls180.v:9925.2-9927.5" - switch \builder_csrbank12_reload3_re - attribute \src "ls180.v:9925.6-9925.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r - case - end - attribute \src "ls180.v:9928.2-9930.5" - switch \builder_csrbank12_reload2_re - attribute \src "ls180.v:9928.6-9928.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r - case - end - attribute \src "ls180.v:9931.2-9933.5" - switch \builder_csrbank12_reload1_re - attribute \src "ls180.v:9931.6-9931.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r - case - end - attribute \src "ls180.v:9934.2-9936.5" - switch \builder_csrbank12_reload0_re - attribute \src "ls180.v:9934.6-9934.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r - case - end - attribute \src "ls180.v:9938.2-9940.5" - switch \builder_csrbank12_en0_re - attribute \src "ls180.v:9938.6-9938.30" - case 1'1 - assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r - case - end - attribute \src "ls180.v:9942.2-9944.5" - switch \builder_csrbank12_update_value0_re - attribute \src "ls180.v:9942.6-9942.40" - case 1'1 - assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r - case - end - attribute \src "ls180.v:9946.2-9948.5" - switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9946.6-9946.37" - case 1'1 - assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r - case - end - attribute \src "ls180.v:9951.2-9978.5" - switch \builder_csrbank13_sel - attribute \src "ls180.v:9951.6-9951.27" - case 1'1 - attribute \src "ls180.v:9952.3-9977.10" - switch \builder_interface13_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } - case - end - case - end - attribute \src "ls180.v:9979.2-9981.5" - switch \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:9979.6-9979.37" - case 1'1 - assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r - case - end - attribute \src "ls180.v:9984.2-9999.5" - switch \builder_csrbank14_sel - attribute \src "ls180.v:9984.6-9984.27" - case 1'1 - attribute \src "ls180.v:9985.3-9998.10" - switch \builder_interface14_bank_bus_adr [1:0] - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w - case - end - case - end - attribute \src "ls180.v:10000.2-10002.5" - switch \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:10000.6-10000.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r - case - end - attribute \src "ls180.v:10003.2-10005.5" - switch \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:10003.6-10003.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r - case - end - attribute \src "ls180.v:10006.2-10008.5" - switch \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:10006.6-10006.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r - case - end - attribute \src "ls180.v:10009.2-10011.5" - switch \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:10009.6-10009.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r - case - end - attribute \src "ls180.v:10013.2-10311.5" - switch \sys_rst_1 - attribute \src "ls180.v:10013.6-10013.15" - case 1'1 - assign $0\main_libresocsim_reset_storage[0:0] 1'0 - assign $0\main_libresocsim_reset_re[0:0] 1'0 - assign $0\main_libresocsim_scratch_storage[31:0] 305419896 - assign $0\main_libresocsim_scratch_re[0:0] 1'0 - assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\pwm[1:0] 2'00 - assign $0\spisdcard_clk[0:0] 1'0 - assign $0\spisdcard_mosi[0:0] 1'0 - assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\uart_tx[0:0] 1'1 - assign $0\spimaster_clk[0:0] 1'0 - assign $0\spimaster_mosi[0:0] 1'0 - assign $0\spimaster_cs_n[0:0] 1'0 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_load_storage[31:0] 0 - assign $0\main_libresocsim_load_re[0:0] 1'0 - assign $0\main_libresocsim_reload_storage[31:0] 0 - assign $0\main_libresocsim_reload_re[0:0] 1'0 - assign $0\main_libresocsim_en_storage[0:0] 1'0 - assign $0\main_libresocsim_en_re[0:0] 1'0 - assign $0\main_libresocsim_update_value_storage[0:0] 1'0 - assign $0\main_libresocsim_update_value_re[0:0] 1'0 - assign $0\main_libresocsim_value_status[31:0] 0 - assign $0\main_libresocsim_zero_pending[0:0] 1'0 - assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 - assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 - assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 - assign $0\main_libresocsim_value[31:0] 0 - assign $0\main_interface0_ram_bus_ack[0:0] 1'0 - assign $0\main_interface1_ram_bus_ack[0:0] 1'0 - assign $0\main_interface2_ram_bus_ack[0:0] 1'0 - assign $0\main_interface3_ram_bus_ack[0:0] 1'0 - assign $0\main_converter0_counter[0:0] 1'0 - assign $0\main_converter1_counter[0:0] 1'0 - assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 - assign $0\main_rddata_en[2:0] 3'000 - assign $0\main_sdram_storage[3:0] 4'0001 - assign $0\main_sdram_re[0:0] 1'0 - assign $0\main_sdram_command_storage[5:0] 6'000000 - assign $0\main_sdram_command_re[0:0] 1'0 - assign $0\main_sdram_address_re[0:0] 1'0 - assign $0\main_sdram_baddress_re[0:0] 1'0 - assign $0\main_sdram_wrdata_re[0:0] 1'0 - assign $0\main_sdram_status[15:0] 16'0000000000000000 - assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 - assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - assign $0\main_sdram_tccdcon_ready[0:0] 1'0 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 - assign $0\main_sdram_twtrcon_count[2:0] 3'000 - assign $0\main_sdram_time0[4:0] 5'00000 - assign $0\main_sdram_time1[3:0] 4'0000 - assign $0\main_socbushandler_counter[0:0] 1'0 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - assign $0\main_uart_phy_storage[31:0] 9895604 - assign $0\main_uart_phy_re[0:0] 1'0 - assign $0\main_uart_phy_sink_ready[0:0] 1'0 - assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 - assign $0\main_uart_phy_tx_busy[0:0] 1'0 - assign $0\main_uart_phy_source_valid[0:0] 1'0 - assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 - assign $0\main_uart_phy_rx_r[0:0] 1'0 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - assign $0\main_uart_tx_pending[0:0] 1'0 - assign $0\main_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_uart_rx_pending[0:0] 1'0 - assign $0\main_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_uart_eventmanager_storage[1:0] 2'00 - assign $0\main_uart_eventmanager_re[0:0] 1'0 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - assign $0\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 - assign $0\main_gpiotristateasic1_oe_re[0:0] 1'0 - assign $0\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 - assign $0\main_gpiotristateasic1_out_re[0:0] 1'0 - assign $0\main_spimaster5_miso[7:0] 8'00000000 - assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 - assign $0\main_spimaster12_re[0:0] 1'0 - assign $0\main_spimaster17_re[0:0] 1'0 - assign $0\main_spimaster21_storage[0:0] 1'1 - assign $0\main_spimaster22_re[0:0] 1'0 - assign $0\main_spimaster23_storage[0:0] 1'0 - assign $0\main_spimaster24_re[0:0] 1'0 - assign $0\main_spimaster27_count[2:0] 3'000 - assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - assign $0\main_spimaster33_mosi_data[7:0] 8'00000000 - assign $0\main_spimaster34_mosi_sel[2:0] 3'000 - assign $0\main_spimaster35_miso_data[7:0] 8'00000000 - assign $0\main_spisdcard_miso[7:0] 8'00000000 - assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000 - assign $0\main_spisdcard_control_re[0:0] 1'0 - assign $0\main_spisdcard_mosi_re[0:0] 1'0 - assign $0\main_spisdcard_cs_storage[0:0] 1'1 - assign $0\main_spisdcard_cs_re[0:0] 1'0 - assign $0\main_spisdcard_loopback_storage[0:0] 1'0 - assign $0\main_spisdcard_loopback_re[0:0] 1'0 - assign $0\main_spisdcard_count[2:0] 3'000 - assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - assign $0\main_spisdcard_mosi_data[7:0] 8'00000000 - assign $0\main_spisdcard_mosi_sel[2:0] 3'000 - assign $0\main_spisdcard_miso_data[7:0] 8'00000000 - assign $0\main_spimaster1_storage[15:0] 16'0000000001111101 - assign $0\main_spimaster1_re[0:0] 1'0 - assign $0\main_dummy[23:0] 24'000000000000000000000000 - assign $0\main_pwm0_enable_storage[0:0] 1'0 - assign $0\main_pwm0_enable_re[0:0] 1'0 - assign $0\main_pwm0_width_re[0:0] 1'0 - assign $0\main_pwm0_period_re[0:0] 1'0 - assign $0\main_pwm1_enable_storage[0:0] 1'0 - assign $0\main_pwm1_enable_re[0:0] 1'0 - assign $0\main_pwm1_width_re[0:0] 1'0 - assign $0\main_pwm1_period_re[0:0] 1'0 - assign $0\main_i2c_storage[2:0] 3'000 - assign $0\main_i2c_re[0:0] 1'0 - assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 - assign $0\main_sdphy_clocker_re[0:0] 1'0 - assign $0\main_sdphy_clocker_clk0[0:0] 1'0 - assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 - assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 - assign $0\main_sdphy_init_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_timeout[31:0] 500000 - assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 - assign $0\main_sdphy_dataw_count[7:0] 8'00000000 - assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 - assign $0\main_sdphy_datar_timeout[31:0] 500000 - assign $0\main_sdphy_datar_count[9:0] 10'0000000000 - assign $0\main_sdphy_datar_datar_run[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 - assign $0\main_sdcore_cmd_argument_storage[31:0] 0 - assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 - assign $0\main_sdcore_cmd_command_storage[31:0] 0 - assign $0\main_sdcore_cmd_command_re[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 - assign $0\main_sdcore_block_length_re[0:0] 1'0 - assign $0\main_sdcore_block_count_storage[31:0] 0 - assign $0\main_sdcore_block_count_re[0:0] 1'0 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 - assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - assign $0\main_sdcore_cmd_count[2:0] 3'000 - assign $0\main_sdcore_cmd_done[0:0] 1'0 - assign $0\main_sdcore_cmd_error[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout[0:0] 1'0 - assign $0\main_sdcore_data_count[31:0] 0 - assign $0\main_sdcore_data_done[0:0] 1'0 - assign $0\main_sdcore_data_error[0:0] 1'0 - assign $0\main_sdcore_data_timeout[0:0] 1'0 - assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 - assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 - assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 - assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_length_storage[31:0] 0 - assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 - assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 - assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\main_sdmem2block_converter_mux[2:0] 3'000 - assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 - assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 - assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 - assign $0\builder_converter0_state[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - assign $0\builder_converter2_state[0:0] 1'0 - assign $0\builder_refresher_state[1:0] 2'00 - assign $0\builder_bankmachine0_state[2:0] 3'000 - assign $0\builder_bankmachine1_state[2:0] 3'000 - assign $0\builder_bankmachine2_state[2:0] 3'000 - assign $0\builder_bankmachine3_state[2:0] 3'000 - assign $0\builder_multiplexer_state[2:0] 3'000 - assign $0\builder_new_master_wdata_ready[0:0] 1'0 - assign $0\builder_new_master_rdata_valid0[0:0] 1'0 - assign $0\builder_new_master_rdata_valid1[0:0] 1'0 - assign $0\builder_new_master_rdata_valid2[0:0] 1'0 - assign $0\builder_new_master_rdata_valid3[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 - assign $0\builder_spimaster0_state[1:0] 2'00 - assign $0\builder_spimaster1_state[1:0] 2'00 - assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 - assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 - assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 - assign $0\builder_sdphy_fsm_state[2:0] 3'000 - assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - assign $0\builder_sdcore_fsm_state[2:0] 3'000 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - assign $0\builder_libresocsim_we[0:0] 1'0 - assign $0\builder_grant[2:0] 3'000 - assign $0\builder_slave_sel_r[12:0] 13'0000000000000 - assign $0\builder_count[19:0] 20'11110100001001000000 - assign $0\builder_state[1:0] 2'00 - case - end - sync posedge \sys_clk_1 - update \pwm $0\pwm[1:0] - update \spisdcard_clk $0\spisdcard_clk[0:0] - update \spisdcard_mosi $0\spisdcard_mosi[0:0] - update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] - update \uart_tx $0\uart_tx[0:0] - update \spimaster_clk $0\spimaster_clk[0:0] - update \spimaster_mosi $0\spimaster_mosi[0:0] - update \spimaster_cs_n $0\spimaster_cs_n[0:0] - update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] - update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] - update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] - update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] - update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] - update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] - update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] - update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] - update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] - update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] - update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] - update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] - update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] - update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] - update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] - update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] - update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] - update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] - update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] - update \main_libresocsim_value $0\main_libresocsim_value[31:0] - update \main_interface0_ram_bus_ack $0\main_interface0_ram_bus_ack[0:0] - update \main_interface1_ram_bus_ack $0\main_interface1_ram_bus_ack[0:0] - update \main_interface2_ram_bus_ack $0\main_interface2_ram_bus_ack[0:0] - update \main_interface3_ram_bus_ack $0\main_interface3_ram_bus_ack[0:0] - update \main_converter0_counter $0\main_converter0_counter[0:0] - update \main_converter0_dat_r $0\main_converter0_dat_r[63:0] - update \main_converter1_counter $0\main_converter1_counter[0:0] - update \main_converter1_dat_r $0\main_converter1_dat_r[63:0] - update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] - update \main_rddata_en $0\main_rddata_en[2:0] - update \main_sdram_storage $0\main_sdram_storage[3:0] - update \main_sdram_re $0\main_sdram_re[0:0] - update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] - update \main_sdram_command_re $0\main_sdram_command_re[0:0] - update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] - update \main_sdram_address_re $0\main_sdram_address_re[0:0] - update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] - update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] - update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] - update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] - update \main_sdram_status $0\main_sdram_status[15:0] - update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] - update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] - update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] - update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] - update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] - update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] - update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] - update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] - update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] - update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] - update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] - update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] - update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] - update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] - update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] - update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] - update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] - update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] - update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] - update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] - update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] - update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] - update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] - update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] - update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] - update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] - update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] - update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] - update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] - update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] - update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] - update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] - update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] - update \main_sdram_time0 $0\main_sdram_time0[4:0] - update \main_sdram_time1 $0\main_sdram_time1[3:0] - update \main_socbushandler_counter $0\main_socbushandler_counter[0:0] - update \main_socbushandler_dat_r $0\main_socbushandler_dat_r[63:0] - update \main_converter_counter $0\main_converter_counter[0:0] - update \main_converter_dat_r $0\main_converter_dat_r[31:0] - update \main_cmd_consumed $0\main_cmd_consumed[0:0] - update \main_wdata_consumed $0\main_wdata_consumed[0:0] - update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] - update \main_uart_phy_re $0\main_uart_phy_re[0:0] - update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] - update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] - update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] - update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] - update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] - update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] - update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] - update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] - update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] - update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] - update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] - update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] - update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] - update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] - update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] - update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] - update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] - update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] - update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] - update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] - update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] - update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] - update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] - update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] - update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] - update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] - update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] - update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] - update \main_gpiotristateasic1_oe_storage $0\main_gpiotristateasic1_oe_storage[15:0] - update \main_gpiotristateasic1_oe_re $0\main_gpiotristateasic1_oe_re[0:0] - update \main_gpiotristateasic1_out_storage $0\main_gpiotristateasic1_out_storage[15:0] - update \main_gpiotristateasic1_out_re $0\main_gpiotristateasic1_out_re[0:0] - update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] - update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] - update \main_spimaster12_re $0\main_spimaster12_re[0:0] - update \main_spimaster16_storage $0\main_spimaster16_storage[7:0] - update \main_spimaster17_re $0\main_spimaster17_re[0:0] - update \main_spimaster21_storage $0\main_spimaster21_storage[0:0] - update \main_spimaster22_re $0\main_spimaster22_re[0:0] - update \main_spimaster23_storage $0\main_spimaster23_storage[0:0] - update \main_spimaster24_re $0\main_spimaster24_re[0:0] - update \main_spimaster27_count $0\main_spimaster27_count[2:0] - update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0] - update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0] - update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0] - update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0] - update \main_spisdcard_miso $0\main_spisdcard_miso[7:0] - update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0] - update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0] - update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0] - update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0] - update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0] - update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0] - update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0] - update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0] - update \main_spisdcard_count $0\main_spisdcard_count[2:0] - update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0] - update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0] - update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0] - update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0] - update \main_spimaster1_storage $0\main_spimaster1_storage[15:0] - update \main_spimaster1_re $0\main_spimaster1_re[0:0] - update \main_dummy $0\main_dummy[23:0] - update \main_pwm0_counter $0\main_pwm0_counter[31:0] - update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] - update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] - update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] - update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] - update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] - update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] - update \main_pwm1_counter $0\main_pwm1_counter[31:0] - update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] - update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] - update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] - update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] - update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] - update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] - update \main_i2c_storage $0\main_i2c_storage[2:0] - update \main_i2c_re $0\main_i2c_re[0:0] - update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] - update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] - update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] - update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] - update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] - update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] - update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] - update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] - update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] - update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] - update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] - update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] - update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] - update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] - update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] - update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] - update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] - update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] - update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] - update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] - update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] - update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] - update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] - update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] - update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] - update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] - update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] - update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] - update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] - update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] - update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] - update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] - update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] - update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] - update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] - update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] - update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] - update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] - update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] - update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] - update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] - update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] - update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] - update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] - update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] - update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] - update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] - update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] - update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] - update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] - update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] - update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] - update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] - update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] - update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] - update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] - update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] - update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[63:0] - update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[2:0] - update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] - update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[63:0] - update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] - update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] - update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] - update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] - update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] - update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] - update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] - update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] - update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] - update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[2:0] - update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] - update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] - update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] - update \builder_converter0_state $0\builder_converter0_state[0:0] - update \builder_converter1_state $0\builder_converter1_state[0:0] - update \builder_converter2_state $0\builder_converter2_state[0:0] - update \builder_refresher_state $0\builder_refresher_state[1:0] - update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] - update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] - update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] - update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] - update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] - update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] - update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] - update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] - update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] - update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] - update \builder_converter_state $0\builder_converter_state[0:0] - update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] - update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] - update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] - update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] - update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] - update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] - update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] - update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] - update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] - update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] - update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] - update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] - update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] - update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] - update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] - update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] - update \builder_grant $0\builder_grant[2:0] - update \builder_slave_sel_r $0\builder_slave_sel_r[12:0] - update \builder_count $0\builder_count[19:0] - update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] - update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] - update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] - update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] - update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] - update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] - update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] - update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] - update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] - update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] - update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] - update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] - update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] - update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] - update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] - update \builder_state $0\builder_state[1:0] - update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] - update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] - update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] - update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] - update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] - update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] - update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] - update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] - update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] - update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] - update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] - update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] - update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] - update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] - update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] - update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] - update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] - update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] - update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] - update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] - update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] - update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] - update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] - update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] - update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] - update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] - update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] - update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] - update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] - update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] - update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] - update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] - update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] - update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] - end - attribute \src "ls180.v:781.11-781.68" - process $proc$ls180.v:781$3374 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:782.5-782.64" - process $proc$ls180.v:782$3375 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:783.11-783.70" - process $proc$ls180.v:783$3376 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:784.11-784.70" - process $proc$ls180.v:784$3377 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:785.11-785.73" - process $proc$ls180.v:785$3378 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:806.5-806.59" - process $proc$ls180.v:806$3379 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:808.5-808.59" - process $proc$ls180.v:808$3380 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:809.5-809.58" - process $proc$ls180.v:809$3381 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:810.5-810.64" - process $proc$ls180.v:810$3382 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:811.12-811.74" - process $proc$ls180.v:811$3383 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:812.12-812.47" - process $proc$ls180.v:812$3384 - assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] - end - attribute \src "ls180.v:813.5-813.46" - process $proc$ls180.v:813$3385 - assign { } { } - assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] - end - attribute \src "ls180.v:815.5-815.44" - process $proc$ls180.v:815$3386 - assign { } { } - assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] - end - attribute \src "ls180.v:816.5-816.45" - process $proc$ls180.v:816$3387 - assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] - end - attribute \src "ls180.v:817.5-817.54" - process $proc$ls180.v:817$3388 - assign { } { } - assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:819.32-819.76" - process $proc$ls180.v:819$3389 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - end - attribute \src "ls180.v:820.11-820.55" - process $proc$ls180.v:820$3390 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] - end - attribute \src "ls180.v:822.32-822.75" - process $proc$ls180.v:822$3391 - assign { } { } - assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:824.32-824.76" - process $proc$ls180.v:824$3392 - assign { } { } - assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:827.5-827.44" - process $proc$ls180.v:827$3393 - assign { } { } - assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] - sync init - end - attribute \src "ls180.v:828.5-828.45" - process $proc$ls180.v:828$3394 - assign { } { } - assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] - sync init - end - attribute \src "ls180.v:829.5-829.43" - process $proc$ls180.v:829$3395 - assign { } { } - assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] - sync init - end - attribute \src "ls180.v:830.5-830.48" - process $proc$ls180.v:830$3396 - assign { } { } - assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] - sync init - end - attribute \src "ls180.v:832.5-832.43" - process $proc$ls180.v:832$3397 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] - sync init - end - attribute \src "ls180.v:835.5-835.49" - process $proc$ls180.v:835$3398 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:836.5-836.49" - process $proc$ls180.v:836$3399 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:837.5-837.48" - process $proc$ls180.v:837$3400 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:841.11-841.46" - process $proc$ls180.v:841$3401 - assign { } { } - assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 - sync always - sync init - update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] - end - attribute \src "ls180.v:843.11-843.45" - process $proc$ls180.v:843$3402 - assign { } { } - assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 - sync always - sync init - update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] - end - attribute \src "ls180.v:845.5-845.44" - process $proc$ls180.v:845$3403 - assign { } { } - assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] - end - attribute \src "ls180.v:846.5-846.45" - process $proc$ls180.v:846$3404 - assign { } { } - assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] - end - attribute \src "ls180.v:848.5-848.48" - process $proc$ls180.v:848$3405 - assign { } { } - assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] - end - attribute \src "ls180.v:85.11-85.52" - process $proc$ls180.v:85$3134 - assign { } { } - assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 - sync always - update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] - sync init - end - attribute \src "ls180.v:850.5-850.43" - process $proc$ls180.v:850$3406 - assign { } { } - assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] - end - attribute \src "ls180.v:853.5-853.49" - process $proc$ls180.v:853$3407 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:854.5-854.49" - process $proc$ls180.v:854$3408 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:855.5-855.48" - process $proc$ls180.v:855$3409 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] - end - attribute \src "ls180.v:859.11-859.46" - process $proc$ls180.v:859$3410 - assign { } { } - assign $1\main_sdram_choose_req_valids[3:0] 4'0000 - sync always - sync init - update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] - end - attribute \src "ls180.v:86.11-86.52" - process $proc$ls180.v:86$3135 - assign { } { } - assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 - sync always - update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] - sync init - end - attribute \src "ls180.v:861.11-861.45" - process $proc$ls180.v:861$3411 - assign { } { } - assign $1\main_sdram_choose_req_grant[1:0] 2'00 - sync always - sync init - update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] - end - attribute \src "ls180.v:863.12-863.36" - process $proc$ls180.v:863$3412 - assign { } { } - assign $0\main_sdram_nop_a[12:0] 13'0000000000000 - sync always - update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] - sync init - end - attribute \src "ls180.v:864.11-864.35" - process $proc$ls180.v:864$3413 - assign { } { } - assign $0\main_sdram_nop_ba[1:0] 2'00 - sync always - update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] - sync init - end - attribute \src "ls180.v:865.11-865.40" - process $proc$ls180.v:865$3414 - assign { } { } - assign $1\main_sdram_steerer_sel[1:0] 2'00 - sync always - sync init - update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] - end - attribute \src "ls180.v:866.5-866.31" - process $proc$ls180.v:866$3415 - assign { } { } - assign $0\main_sdram_steerer0[0:0] 1'1 - sync always - update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] - sync init - end - attribute \src "ls180.v:867.5-867.31" - process $proc$ls180.v:867$3416 - assign { } { } - assign $0\main_sdram_steerer1[0:0] 1'1 - sync always - update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] - sync init - end - attribute \src "ls180.v:869.32-869.63" - process $proc$ls180.v:869$3417 - assign { } { } - assign $0\main_sdram_trrdcon_ready[0:0] 1'1 - sync always - update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] - sync init - end - attribute \src "ls180.v:871.32-871.63" - process $proc$ls180.v:871$3418 - assign { } { } - assign $0\main_sdram_tfawcon_ready[0:0] 1'1 - sync always - update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] - sync init - end - attribute \src "ls180.v:873.32-873.63" - process $proc$ls180.v:873$3419 - assign { } { } - assign $1\main_sdram_tccdcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] - end - attribute \src "ls180.v:874.5-874.36" - process $proc$ls180.v:874$3420 - assign { } { } - assign $1\main_sdram_tccdcon_count[0:0] 1'0 - sync always - sync init - update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] - end - attribute \src "ls180.v:876.32-876.63" - process $proc$ls180.v:876$3421 - assign { } { } - assign $1\main_sdram_twtrcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] - end - attribute \src "ls180.v:877.11-877.42" - process $proc$ls180.v:877$3422 - assign { } { } - assign $1\main_sdram_twtrcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] - end - attribute \src "ls180.v:88.12-88.58" - process $proc$ls180.v:88$3136 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] - end - attribute \src "ls180.v:880.5-880.26" - process $proc$ls180.v:880$3423 - assign { } { } - assign $1\main_sdram_en0[0:0] 1'0 - sync always - sync init - update \main_sdram_en0 $1\main_sdram_en0[0:0] - end - attribute \src "ls180.v:882.11-882.34" - process $proc$ls180.v:882$3424 - assign { } { } - assign $1\main_sdram_time0[4:0] 5'00000 - sync always - sync init - update \main_sdram_time0 $1\main_sdram_time0[4:0] - end - attribute \src "ls180.v:883.5-883.26" - process $proc$ls180.v:883$3425 - assign { } { } - assign $1\main_sdram_en1[0:0] 1'0 - sync always - sync init - update \main_sdram_en1 $1\main_sdram_en1[0:0] - end - attribute \src "ls180.v:885.11-885.34" - process $proc$ls180.v:885$3426 - assign { } { } - assign $1\main_sdram_time1[3:0] 4'0000 - sync always - sync init - update \main_sdram_time1 $1\main_sdram_time1[3:0] - end - attribute \src "ls180.v:89.12-89.60" - process $proc$ls180.v:89$3137 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - end - attribute \src "ls180.v:900.12-900.37" - process $proc$ls180.v:900$3427 - assign { } { } - assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] - end - attribute \src "ls180.v:901.12-901.39" - process $proc$ls180.v:901$3428 - assign { } { } - assign $1\main_wb_sdram_dat_w[31:0] 0 - sync always - sync init - update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] - end - attribute \src "ls180.v:903.11-903.35" - process $proc$ls180.v:903$3429 - assign { } { } - assign $1\main_wb_sdram_sel[3:0] 4'0000 - sync always - sync init - update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] - end - attribute \src "ls180.v:904.5-904.29" - process $proc$ls180.v:904$3430 - assign { } { } - assign $1\main_wb_sdram_cyc[0:0] 1'0 - sync always - sync init - update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] - end - attribute \src "ls180.v:905.5-905.29" - process $proc$ls180.v:905$3431 - assign { } { } - assign $1\main_wb_sdram_stb[0:0] 1'0 - sync always - sync init - update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] - end - attribute \src "ls180.v:906.5-906.29" - process $proc$ls180.v:906$3432 - assign { } { } - assign $1\main_wb_sdram_ack[0:0] 1'0 - sync always - sync init - update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] - end - attribute \src "ls180.v:907.5-907.28" - process $proc$ls180.v:907$3433 - assign { } { } - assign $1\main_wb_sdram_we[0:0] 1'0 - sync always - sync init - update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] - end - attribute \src "ls180.v:91.11-91.56" - process $proc$ls180.v:91$3138 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] - end - attribute \src "ls180.v:914.5-914.54" - process $proc$ls180.v:914$3434 - assign { } { } - assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 - sync always - sync init - update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] - end - attribute \src "ls180.v:918.5-918.54" - process $proc$ls180.v:918$3435 - assign { } { } - assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 - sync always - update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] - sync init - end - attribute \src "ls180.v:919.5-919.35" - process $proc$ls180.v:919$3436 - assign { } { } - assign $1\main_socbushandler_skip[0:0] 1'0 - sync always - sync init - update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] - end - attribute \src "ls180.v:92.5-92.50" - process $proc$ls180.v:92$3139 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] - end - attribute \src "ls180.v:920.5-920.38" - process $proc$ls180.v:920$3437 - assign { } { } - assign $1\main_socbushandler_counter[0:0] 1'0 - sync always - sync init - update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] - end - attribute \src "ls180.v:922.12-922.44" - process $proc$ls180.v:922$3438 - assign { } { } - assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] - end - attribute \src "ls180.v:923.12-923.40" - process $proc$ls180.v:923$3439 - assign { } { } - assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] - end - attribute \src "ls180.v:924.12-924.42" - process $proc$ls180.v:924$3440 - assign { } { } - assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - sync always - sync init - update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] - end - attribute \src "ls180.v:926.11-926.38" - process $proc$ls180.v:926$3441 - assign { } { } - assign $1\main_litedram_wb_sel[1:0] 2'00 - sync always - sync init - update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] - end - attribute \src "ls180.v:927.5-927.32" - process $proc$ls180.v:927$3442 - assign { } { } - assign $1\main_litedram_wb_cyc[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] - end - attribute \src "ls180.v:928.5-928.32" - process $proc$ls180.v:928$3443 - assign { } { } - assign $1\main_litedram_wb_stb[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] - end - attribute \src "ls180.v:93.5-93.50" - process $proc$ls180.v:93$3140 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] - end - attribute \src "ls180.v:930.5-930.31" - process $proc$ls180.v:930$3444 - assign { } { } - assign $1\main_litedram_wb_we[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] - end - attribute \src "ls180.v:931.5-931.31" - process $proc$ls180.v:931$3445 - assign { } { } - assign $1\main_converter_skip[0:0] 1'0 - sync always - sync init - update \main_converter_skip $1\main_converter_skip[0:0] - end - attribute \src "ls180.v:932.5-932.34" - process $proc$ls180.v:932$3446 - assign { } { } - assign $1\main_converter_counter[0:0] 1'0 - sync always - sync init - update \main_converter_counter $1\main_converter_counter[0:0] - end - attribute \src "ls180.v:934.12-934.40" - process $proc$ls180.v:934$3447 - assign { } { } - assign $1\main_converter_dat_r[31:0] 0 - sync always - sync init - update \main_converter_dat_r $1\main_converter_dat_r[31:0] - end - attribute \src "ls180.v:935.5-935.29" - process $proc$ls180.v:935$3448 - assign { } { } - assign $1\main_cmd_consumed[0:0] 1'0 - sync always - sync init - update \main_cmd_consumed $1\main_cmd_consumed[0:0] - end - attribute \src "ls180.v:936.5-936.31" - process $proc$ls180.v:936$3449 - assign { } { } - assign $1\main_wdata_consumed[0:0] 1'0 - sync always - sync init - update \main_wdata_consumed $1\main_wdata_consumed[0:0] - end - attribute \src "ls180.v:940.12-940.47" - process $proc$ls180.v:940$3450 - assign { } { } - assign $1\main_uart_phy_storage[31:0] 9895604 - sync always - sync init - update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] - end - attribute \src "ls180.v:941.5-941.28" - process $proc$ls180.v:941$3451 - assign { } { } - assign $1\main_uart_phy_re[0:0] 1'0 - sync always - sync init - update \main_uart_phy_re $1\main_uart_phy_re[0:0] - end - attribute \src "ls180.v:943.5-943.36" - process $proc$ls180.v:943$3452 - assign { } { } - assign $1\main_uart_phy_sink_ready[0:0] 1'0 - sync always - sync init - update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] - end - attribute \src "ls180.v:947.5-947.39" - process $proc$ls180.v:947$3453 - assign { } { } - assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 - sync always - sync init - update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] - end - attribute \src "ls180.v:948.12-948.54" - process $proc$ls180.v:948$3454 - assign { } { } - assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 - sync always - sync init - update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] - end - attribute \src "ls180.v:949.11-949.38" - process $proc$ls180.v:949$3455 - assign { } { } - assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 - sync always - sync init - update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] - end - attribute \src "ls180.v:95.5-95.49" - process $proc$ls180.v:95$3141 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] - end - attribute \src "ls180.v:950.11-950.43" - process $proc$ls180.v:950$3456 - assign { } { } - assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 - sync always - sync init - update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] - end - attribute \src "ls180.v:951.5-951.33" - process $proc$ls180.v:951$3457 - assign { } { } - assign $1\main_uart_phy_tx_busy[0:0] 1'0 - sync always - sync init - update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] - end - attribute \src "ls180.v:952.5-952.38" - process $proc$ls180.v:952$3458 - assign { } { } - assign $1\main_uart_phy_source_valid[0:0] 1'0 - sync always - sync init - update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] - end - attribute \src "ls180.v:954.5-954.38" - process $proc$ls180.v:954$3459 - assign { } { } - assign $0\main_uart_phy_source_first[0:0] 1'0 - sync always - update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] - sync init - end - attribute \src "ls180.v:955.5-955.37" - process $proc$ls180.v:955$3460 - assign { } { } - assign $0\main_uart_phy_source_last[0:0] 1'0 - sync always - update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] - sync init - end - attribute \src "ls180.v:956.11-956.51" - process $proc$ls180.v:956$3461 - assign { } { } - assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] - end - attribute \src "ls180.v:957.5-957.39" - process $proc$ls180.v:957$3462 - assign { } { } - assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 - sync always - sync init - update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] - end - attribute \src "ls180.v:958.12-958.54" - process $proc$ls180.v:958$3463 - assign { } { } - assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 - sync always - sync init - update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] - end - attribute \src "ls180.v:960.5-960.30" - process $proc$ls180.v:960$3464 - assign { } { } - assign $1\main_uart_phy_rx_r[0:0] 1'0 - sync always - sync init - update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] - end - attribute \src "ls180.v:961.11-961.38" - process $proc$ls180.v:961$3465 - assign { } { } - assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 - sync always - sync init - update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] - end - attribute \src "ls180.v:962.11-962.43" - process $proc$ls180.v:962$3466 - assign { } { } - assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 - sync always - sync init - update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] - end - attribute \src "ls180.v:963.5-963.33" - process $proc$ls180.v:963$3467 - assign { } { } - assign $1\main_uart_phy_rx_busy[0:0] 1'0 - sync always - sync init - update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] - end - attribute \src "ls180.v:97.12-97.58" - process $proc$ls180.v:97$3142 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] - end - attribute \src "ls180.v:974.5-974.32" - process $proc$ls180.v:974$3468 - assign { } { } - assign $1\main_uart_tx_pending[0:0] 1'0 - sync always - sync init - update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] - end - attribute \src "ls180.v:976.5-976.30" - process $proc$ls180.v:976$3469 - assign { } { } - assign $1\main_uart_tx_clear[0:0] 1'0 - sync always - sync init - update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] - end - attribute \src "ls180.v:977.5-977.36" - process $proc$ls180.v:977$3470 - assign { } { } - assign $1\main_uart_tx_old_trigger[0:0] 1'0 - sync always - sync init - update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] - end - attribute \src "ls180.v:979.5-979.32" - process $proc$ls180.v:979$3471 - assign { } { } - assign $1\main_uart_rx_pending[0:0] 1'0 - sync always - sync init - update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] - end - attribute \src "ls180.v:98.12-98.60" - process $proc$ls180.v:98$3143 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] - end - attribute \src "ls180.v:981.5-981.30" - process $proc$ls180.v:981$3472 - assign { } { } - assign $1\main_uart_rx_clear[0:0] 1'0 - sync always - sync init - update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] - end - attribute \src "ls180.v:982.5-982.36" - process $proc$ls180.v:982$3473 - assign { } { } - assign $1\main_uart_rx_old_trigger[0:0] 1'0 - sync always - sync init - update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] - end - attribute \src "ls180.v:986.11-986.49" - process $proc$ls180.v:986$3474 - assign { } { } - assign $1\main_uart_eventmanager_status_w[1:0] 2'00 - sync always - sync init - update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] - end - attribute \src "ls180.v:990.11-990.50" - process $proc$ls180.v:990$3475 - assign { } { } - assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 - sync always - sync init - update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] - end - attribute \src "ls180.v:991.11-991.48" - process $proc$ls180.v:991$3476 - assign { } { } - assign $1\main_uart_eventmanager_storage[1:0] 2'00 - sync always - sync init - update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] - end - attribute \src "ls180.v:992.5-992.37" - process $proc$ls180.v:992$3477 - assign { } { } - assign $1\main_uart_eventmanager_re[0:0] 1'0 - sync always - sync init - update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] - end - connect \main_libresocsim_libresoc_reset \main_libresocsim_reset - connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i - connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o - connect \sys_pll_lck_o \main_libresocsim_libresoc_pll_lck_o - connect \main_libresocsim_libresoc_jtag_tck \jtag_tck - connect \main_libresocsim_libresoc_jtag_tms \jtag_tms - connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi - connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo - connect \main_nc \nc - connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid - connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 - connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first - connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last - connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data - connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 - connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready - connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 - connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 - connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 - connect \main_libresocsim_bus_error \builder_error - connect \main_converter0_reset $not$ls180.v:2890$50_Y - connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } - connect \main_converter1_reset $not$ls180.v:2950$61_Y - connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } - connect \main_socbushandler_reset $not$ls180.v:3010$72_Y - connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } - connect \main_libresocsim_reset \main_libresocsim_reset_re - connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0] - connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r - connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:3086$108_Y - connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status - connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:3095$111_Y - connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger - connect \main_sram0_adr \main_interface0_ram_bus_adr [5:0] - connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r - connect \main_sram0_dat_w \main_interface0_ram_bus_dat_w - connect \main_sram1_adr \main_interface1_ram_bus_adr [5:0] - connect \main_interface1_ram_bus_dat_r \main_sram1_dat_r - connect \main_sram1_dat_w \main_interface1_ram_bus_dat_w - connect \main_sram2_adr \main_interface2_ram_bus_adr [5:0] - connect \main_interface2_ram_bus_dat_r \main_sram2_dat_r - connect \main_sram2_dat_w \main_interface2_ram_bus_dat_w - connect \main_sram3_adr \main_interface3_ram_bus_adr [5:0] - connect \main_interface3_ram_bus_dat_r \main_sram3_dat_r - connect \main_sram3_dat_w \main_interface3_ram_bus_dat_w - connect \sys_clk_1 \sys_clk - connect \por_clk \sys_clk - connect \sys_rst_1 \main_int_rst - connect \main_dfi_p0_address \main_sdram_master_p0_address - connect \main_dfi_p0_bank \main_sdram_master_p0_bank - connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n - connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n - connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n - connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n - connect \main_dfi_p0_cke \main_sdram_master_p0_cke - connect \main_dfi_p0_odt \main_sdram_master_p0_odt - connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n - connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n - connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata - connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en - connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask - connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en - connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata - connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid - connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address - connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank - connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n - connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n - connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n - connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n - connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke - connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt - connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n - connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n - connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata - connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en - connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask - connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en - connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata - connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid - connect \main_sdram_inti_p0_cke \main_sdram_cke - connect \main_sdram_inti_p0_odt \main_sdram_odt - connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n - connect \main_sdram_inti_p0_address \main_sdram_address_storage - connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3265$218_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3266$219_Y - connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage - connect \main_sdram_inti_p0_wrdata_mask 2'00 - connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid - connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready - connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we - connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr - connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock - connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready - connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid - connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid - connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready - connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we - connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr - connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock - connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready - connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid - connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid - connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready - connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we - connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr - connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock - connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready - connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid - connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid - connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready - connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we - connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr - connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock - connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready - connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3297$220_Y - connect \main_sdram_postponer_req_i \main_sdram_timer_done0 - connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3300$221_Y - connect \main_sdram_timer_done0 \main_sdram_timer_done1 - connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3303$223_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3304$225_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid - connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr - connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3346$227_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3347$228_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3348$229_Y - connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3358$234_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3359$236_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3360$238_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3392$246_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3393$247_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3396$248_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3397$249_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3398$251_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid - connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr - connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3503$257_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3504$258_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3505$259_Y - connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3515$264_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3516$266_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3517$268_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3549$276_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3550$277_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3553$278_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3554$279_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3555$281_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid - connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr - connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3660$287_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3661$288_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3662$289_Y - connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3672$294_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3673$296_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3674$298_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3706$306_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3707$307_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3710$308_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3711$309_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3712$311_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid - connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr - connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3817$317_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3818$318_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3819$319_Y - connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3829$324_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3830$326_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3831$328_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3863$336_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3864$337_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3867$338_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3868$339_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3869$341_Y - connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3965$352_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3966$358_Y - connect \main_sdram_ras_allowed $and$ls180.v:3967$359_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3968$362_Y - connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3970$364_Y - connect \main_sdram_read_available $or$ls180.v:3971$371_Y - connect \main_sdram_write_available $or$ls180.v:3972$378_Y - connect \main_sdram_max_time0 $eq$ls180.v:3973$379_Y - connect \main_sdram_max_time1 $eq$ls180.v:3974$380_Y - connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3979$383_Y - connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata - connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3982$384_Y - connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids - connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 - connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 - connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 - connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 - connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 - connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:4015$442_Y - connect \main_sdram_choose_req_request \main_sdram_choose_req_valids - connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 - connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 - connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 - connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 - connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 - connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:4084$528_Y - connect \main_sdram_dfi_p0_reset_n 1'1 - connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 - connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:4161$560_Y - connect \builder_roundrobin0_ce $and$ls180.v:4162$563_Y - connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 - connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 - connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:4166$576_Y - connect \builder_roundrobin1_ce $and$ls180.v:4167$579_Y - connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 - connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 - connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:4171$592_Y - connect \builder_roundrobin2_ce $and$ls180.v:4172$595_Y - connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 - connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 - connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:4176$608_Y - connect \builder_roundrobin3_ce $and$ls180.v:4177$611_Y - connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 - connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 - connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:4181$675_Y - connect \main_port_wdata_ready \builder_new_master_wdata_ready - connect \main_port_rdata_valid \builder_new_master_rdata_valid3 - connect \main_port_rdata_payload_data \main_sdram_interface_rdata - connect \builder_roundrobin0_grant 1'0 - connect \builder_roundrobin1_grant 1'0 - connect \builder_roundrobin2_grant 1'0 - connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:4203$677_Y - connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4263$688_Y [23:0] - connect \main_port_cmd_payload_we \main_litedram_wb_we - connect \main_port_wdata_payload_data \main_litedram_wb_dat_w - connect \main_port_wdata_payload_we \main_litedram_wb_sel - connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4268$689_Y - connect \main_port_cmd_last $not$ls180.v:4269$690_Y - connect \main_port_cmd_valid $and$ls180.v:4270$693_Y - connect \main_port_wdata_valid $and$ls180.v:4271$697_Y - connect \main_port_rdata_ready $and$ls180.v:4272$700_Y - connect \main_litedram_wb_ack $and$ls180.v:4273$705_Y - connect \main_ack_cmd $or$ls180.v:4274$707_Y - connect \main_ack_wdata $or$ls180.v:4275$709_Y - connect \main_ack_rdata $and$ls180.v:4276$710_Y - connect \main_uart_uart_sink_valid \main_uart_phy_source_valid - connect \main_uart_phy_source_ready \main_uart_uart_sink_ready - connect \main_uart_uart_sink_first \main_uart_phy_source_first - connect \main_uart_uart_sink_last \main_uart_phy_source_last - connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data - connect \main_uart_phy_sink_valid \main_uart_uart_source_valid - connect \main_uart_uart_source_ready \main_uart_phy_sink_ready - connect \main_uart_phy_sink_first \main_uart_uart_source_first - connect \main_uart_phy_sink_last \main_uart_uart_source_last - connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data - connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re - connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4289$711_Y - connect \main_uart_txempty_status $not$ls180.v:4290$712_Y - connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid - connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready - connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first - connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last - connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4296$713_Y - connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid - connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready - connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first - connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last - connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4302$714_Y - connect \main_uart_rxfull_status $not$ls180.v:4303$715_Y - connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4305$717_Y - connect \main_uart_rx_trigger $not$ls180.v:4306$718_Y - connect \main_uart_irq $or$ls180.v:4329$727_Y - connect \main_uart_tx_status \main_uart_tx_trigger - connect \main_uart_rx_status \main_uart_rx_trigger - connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } - connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout - connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable - connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid - connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first - connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last - connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data - connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable - connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first - connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last - connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data - connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4344$730_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4345$731_Y - connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4355$735_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4356$736_Y - connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume - connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r - connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4360$737_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4361$738_Y - connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } - connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout - connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable - connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid - connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first - connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last - connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data - connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable - connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first - connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last - connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data - connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4374$741_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4375$742_Y - connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4385$746_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4386$747_Y - connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume - connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r - connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4390$748_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4391$749_Y - connect \main_gpiotristateasic0_pads_i \gpio_i - connect \main_gpiotristateasic0_pads_oe \main_gpiotristateasic0_oe_storage - connect \main_gpiotristateasic0_pads_o \main_gpiotristateasic0_out_storage - connect \main_gpiotristateasic1_pads_i \gpio_i - connect \main_gpiotristateasic1_pads_oe \main_gpiotristateasic1_oe_storage - connect \main_gpiotristateasic1_pads_o \main_gpiotristateasic1_out_storage - connect \main_spimaster0_start \main_spimaster9_start - connect \main_spimaster1_length \main_spimaster10_length - connect \main_spimaster4_mosi \main_spimaster16_storage - connect \main_spimaster13_done \main_spimaster2_done - connect \main_spimaster18_status \main_spimaster5_miso - connect \main_spimaster6_cs \main_spimaster21_storage - connect \main_spimaster7_loopback \main_spimaster23_storage - connect \main_spimaster31_clk_rise $eq$ls180.v:4415$753_Y - connect \main_spimaster32_clk_fall $eq$ls180.v:4416$755_Y - connect \main_spisdcard_start0 \main_spisdcard_start1 - connect \main_spisdcard_length0 \main_spisdcard_length1 - connect \main_spisdcard_mosi \main_spisdcard_mosi_storage - connect \main_spisdcard_done1 \main_spisdcard_done0 - connect \main_spisdcard_miso_status \main_spisdcard_miso - connect \main_spisdcard_cs \main_spisdcard_cs_storage - connect \main_spisdcard_loopback \main_spisdcard_loopback_storage - connect \main_spisdcard_clk_rise $eq$ls180.v:4473$761_Y - connect \main_spisdcard_clk_fall $eq$ls180.v:4474$763_Y - connect \main_spisdcard_clk_divider0 \main_spimaster1_storage - connect \i2c_scl \main_i2c_scl - connect \i2c_sda_oe \main_i2c_oe - connect \i2c_sda_o \main_i2c_sda0 - connect \main_i2c_sda1 \i2c_sda_i - connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4530$771_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4531$775_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4532$779_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4533$783_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4534$787_Y - connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4555$788_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4585$791_Y - connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid - connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready - connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first - connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last - connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4708$801_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4709$803_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 - connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready - connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 - connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 - connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 - connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid - connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 - connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first - connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last - connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data - connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid - connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 - connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first - connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last - connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4726$805_Y - connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4728$806_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4729$808_Y - connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid - connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready - connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first - connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last - connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i - connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o - connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4835$823_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4836$824_Y - connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] - connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 - connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready - connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 - connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 - connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 - connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid - connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 - connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first - connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last - connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data - connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid - connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 - connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first - connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last - connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4853$826_Y - connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4855$827_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4856$829_Y - connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid - connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready - connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first - connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last - connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk - connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i - connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o - connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4969$838_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4970$839_Y - connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i - connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 - connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready - connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 - connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 - connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 - connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid - connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 - connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first - connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last - connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data - connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid - connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 - connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first - connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last - connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4987$841_Y - connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4989$842_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4990$844_Y - connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid - connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready - connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first - connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last - connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data - connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid - connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready - connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first - connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last - connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data - connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] - connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] - connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:5106$859_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } - connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } - connect \main_sdcore_crc7_inserter_clr 1'1 - connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5110$862_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5110$860_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5111$865_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5111$863_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5112$868_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5112$866_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5113$871_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5113$869_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5114$874_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5114$872_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5115$877_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5115$875_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5116$880_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5116$878_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5117$883_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5117$881_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5118$886_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5118$884_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5119$889_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5119$887_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5120$892_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5120$890_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5121$895_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5121$893_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5122$898_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5122$896_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5123$901_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5123$899_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5124$904_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5124$902_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5125$907_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5125$905_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5126$910_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5126$908_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5127$913_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5127$911_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5128$916_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5128$914_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5129$919_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5129$917_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5130$922_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5130$920_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5131$925_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5131$923_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5132$928_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5132$926_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5133$931_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5133$929_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5134$934_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5134$932_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5135$937_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5135$935_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5136$940_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5136$938_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5137$943_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5137$941_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5138$946_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5138$944_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5139$949_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5139$947_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5140$952_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5140$950_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5141$955_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5141$953_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5142$958_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5142$956_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5143$961_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5143$959_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5144$964_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5144$962_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5145$967_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5145$965_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5146$970_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5146$968_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5147$973_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5147$971_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5148$976_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5148$974_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5149$979_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5149$977_Y } - connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5159$982_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5160$983_Y - connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5162$985_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5163$986_Y - connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5165$988_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5166$989_Y - connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5168$991_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5169$992_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5170$997_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5170$995_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5170$993_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5171$1002_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5171$1000_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5171$998_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5180$1008_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5180$1006_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5180$1004_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5181$1013_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5181$1011_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5181$1009_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5190$1019_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5190$1017_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5190$1015_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5191$1024_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5191$1022_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5191$1020_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5200$1030_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5200$1028_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5200$1026_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5201$1035_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5201$1033_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5201$1031_Y } - connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5297$1051_Y - connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5307$1054_Y - connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5317$1057_Y - connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5327$1060_Y - connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val - connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5352$1072_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5352$1070_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5352$1068_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5353$1077_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5353$1075_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5353$1073_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5362$1083_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5362$1081_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5362$1079_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5363$1088_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5363$1086_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5363$1084_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5372$1094_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5372$1092_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5372$1090_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5373$1099_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5373$1097_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5373$1095_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5382$1105_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5382$1103_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5382$1101_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5383$1110_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5383$1108_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5383$1106_Y } - connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 - connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready - connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first - connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last - connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 - connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid - connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready - connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first - connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last - connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data - connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid - connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first - connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last - connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data - connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } - connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout - connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable - connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid - connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first - connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last - connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data - connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable - connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first - connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last - connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data - connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready - connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5619$1140_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5620$1141_Y - connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume - connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5623$1142_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5624$1143_Y - connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid - connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready - connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first - connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last - connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5630$1145_Y - connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5632$1146_Y - connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 - connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 - connect \main_interface0_bus_we 1'1 - connect \main_interface0_bus_sel 8'11111111 - connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address - connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] \main_sdblock2mem_sink_sink_payload_data1 [39:32] \main_sdblock2mem_sink_sink_payload_data1 [47:40] \main_sdblock2mem_sink_sink_payload_data1 [55:48] \main_sdblock2mem_sink_sink_payload_data1 [63:56] } - connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack - connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] - connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5642$1147_Y - connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid - connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready - connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first - connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last - connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data - connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 - connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready - connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 - connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 - connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 - connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid - connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 - connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first - connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last - connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data - connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] - connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } - connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5701$1154_Y - connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid - connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 - connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first - connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last - connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5782$1162_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5783$1163_Y - connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5785$1164_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5786$1165_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5787$1166_Y - connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last - connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } - connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout - connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable - connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid - connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first - connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last - connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data - connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable - connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first - connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last - connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data - connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready - connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5839$1171_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5840$1172_Y - connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume - connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5843$1173_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5844$1174_Y - connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] - connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] - connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] - connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 - connect \builder_shared_stb \builder_comb_rhs_array_muxed28 - connect \builder_shared_we \builder_comb_rhs_array_muxed29 - connect \builder_shared_cti \builder_comb_rhs_array_muxed30 - connect \builder_shared_bte \builder_comb_rhs_array_muxed31 - connect \main_libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5895$1180_Y - connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5896$1182_Y - connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5897$1184_Y - connect \main_interface0_bus_ack $and$ls180.v:5898$1186_Y - connect \main_interface1_bus_ack $and$ls180.v:5899$1188_Y - connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5900$1190_Y - connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5901$1192_Y - connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5902$1194_Y - connect \main_interface0_bus_err $and$ls180.v:5903$1196_Y - connect \main_interface1_bus_err $and$ls180.v:5904$1198_Y - connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } - connect \main_libresocsim_ram_bus_adr \builder_shared_adr - connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_ram_bus_stb \builder_shared_stb - connect \main_libresocsim_ram_bus_we \builder_shared_we - connect \main_libresocsim_ram_bus_cti \builder_shared_cti - connect \main_libresocsim_ram_bus_bte \builder_shared_bte - connect \main_interface0_ram_bus_adr \builder_shared_adr - connect \main_interface0_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface0_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface0_ram_bus_stb \builder_shared_stb - connect \main_interface0_ram_bus_we \builder_shared_we - connect \main_interface0_ram_bus_cti \builder_shared_cti - connect \main_interface0_ram_bus_bte \builder_shared_bte - connect \main_interface1_ram_bus_adr \builder_shared_adr - connect \main_interface1_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface1_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface1_ram_bus_stb \builder_shared_stb - connect \main_interface1_ram_bus_we \builder_shared_we - connect \main_interface1_ram_bus_cti \builder_shared_cti - connect \main_interface1_ram_bus_bte \builder_shared_bte - connect \main_interface2_ram_bus_adr \builder_shared_adr - connect \main_interface2_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface2_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface2_ram_bus_stb \builder_shared_stb - connect \main_interface2_ram_bus_we \builder_shared_we - connect \main_interface2_ram_bus_cti \builder_shared_cti - connect \main_interface2_ram_bus_bte \builder_shared_bte - connect \main_interface3_ram_bus_adr \builder_shared_adr - connect \main_interface3_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface3_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface3_ram_bus_stb \builder_shared_stb - connect \main_interface3_ram_bus_we \builder_shared_we - connect \main_interface3_ram_bus_cti \builder_shared_cti - connect \main_interface3_ram_bus_bte \builder_shared_bte - connect \main_interface0_converted_interface_adr \builder_shared_adr - connect \main_interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface0_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \main_interface0_converted_interface_stb \builder_shared_stb - connect \main_interface0_converted_interface_we \builder_shared_we - connect \main_interface0_converted_interface_cti \builder_shared_cti - connect \main_interface0_converted_interface_bte \builder_shared_bte - connect \main_interface1_converted_interface_adr \builder_shared_adr - connect \main_interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface1_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \main_interface1_converted_interface_stb \builder_shared_stb - connect \main_interface1_converted_interface_we \builder_shared_we - connect \main_interface1_converted_interface_cti \builder_shared_cti - connect \main_interface1_converted_interface_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface0_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface0_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface0_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface0_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface0_we \builder_shared_we - connect \main_libresocsim_libresoc_interface0_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface0_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface1_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface1_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface1_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface1_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface1_we \builder_shared_we - connect \main_libresocsim_libresoc_interface1_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface1_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface2_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface2_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface2_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface2_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface2_we \builder_shared_we - connect \main_libresocsim_libresoc_interface2_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface2_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface3_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface3_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface3_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface3_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface3_we \builder_shared_we - connect \main_libresocsim_libresoc_interface3_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface3_bte \builder_shared_bte - connect \main_socbushandler_converted_interface_adr \builder_shared_adr - connect \main_socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_socbushandler_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \main_socbushandler_converted_interface_stb \builder_shared_stb - connect \main_socbushandler_converted_interface_we \builder_shared_we - connect \main_socbushandler_converted_interface_cti \builder_shared_cti - connect \main_socbushandler_converted_interface_bte \builder_shared_bte - connect \builder_libresocsim_converted_interface_adr \builder_shared_adr - connect \builder_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \builder_libresocsim_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \builder_libresocsim_converted_interface_stb \builder_shared_stb - connect \builder_libresocsim_converted_interface_we \builder_shared_we - connect \builder_libresocsim_converted_interface_cti \builder_shared_cti - connect \builder_libresocsim_converted_interface_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:6013$1213_Y - connect \main_interface0_ram_bus_cyc $and$ls180.v:6014$1214_Y - connect \main_interface1_ram_bus_cyc $and$ls180.v:6015$1215_Y - connect \main_interface2_ram_bus_cyc $and$ls180.v:6016$1216_Y - connect \main_interface3_ram_bus_cyc $and$ls180.v:6017$1217_Y - connect \main_interface0_converted_interface_cyc $and$ls180.v:6018$1218_Y - connect \main_interface1_converted_interface_cyc $and$ls180.v:6019$1219_Y - connect \main_libresocsim_libresoc_interface0_cyc $and$ls180.v:6020$1220_Y - connect \main_libresocsim_libresoc_interface1_cyc $and$ls180.v:6021$1221_Y - connect \main_libresocsim_libresoc_interface2_cyc $and$ls180.v:6022$1222_Y - connect \main_libresocsim_libresoc_interface3_cyc $and$ls180.v:6023$1223_Y - connect \main_socbushandler_converted_interface_cyc $and$ls180.v:6024$1224_Y - connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:6025$1225_Y - connect \builder_shared_err $or$ls180.v:6026$1237_Y - connect \builder_wait $and$ls180.v:6027$1240_Y - connect \builder_done $eq$ls180.v:6040$1279_Y - connect \builder_csrbank0_sel $eq$ls180.v:6041$1280_Y - connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:6043$1283_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:6044$1287_Y - connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:6046$1290_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:6047$1294_Y - connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:6049$1297_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:6050$1301_Y - connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:6052$1304_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:6053$1308_Y - connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:6055$1311_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:6056$1315_Y - connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:6058$1318_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:6059$1322_Y - connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:6061$1325_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:6062$1329_Y - connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:6064$1332_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:6065$1336_Y - connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:6067$1339_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:6068$1343_Y - connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage - connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] - connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] - connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] - connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] - connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] - connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] - connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] - connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] - connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:6079$1344_Y - connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:6081$1347_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:6082$1351_Y - connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:6084$1354_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:6085$1358_Y - connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:6087$1361_Y - connect \builder_csrbank1_in1_we $and$ls180.v:6088$1365_Y - connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:6090$1368_Y - connect \builder_csrbank1_in0_we $and$ls180.v:6091$1372_Y - connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:6093$1375_Y - connect \builder_csrbank1_out1_we $and$ls180.v:6094$1379_Y - connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:6096$1382_Y - connect \builder_csrbank1_out0_we $and$ls180.v:6097$1386_Y - connect \builder_csrbank1_oe1_w \main_gpiotristateasic1_oe_storage [15:8] - connect \builder_csrbank1_oe0_w \main_gpiotristateasic1_oe_storage [7:0] - connect \builder_csrbank1_in1_w \main_gpiotristateasic1_status [15:8] - connect \builder_csrbank1_in0_w \main_gpiotristateasic1_status [7:0] - connect \main_gpiotristateasic1_we \builder_csrbank1_in0_we - connect \builder_csrbank1_out1_w \main_gpiotristateasic1_out_storage [15:8] - connect \builder_csrbank1_out0_w \main_gpiotristateasic1_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:6105$1387_Y - connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] - connect \builder_csrbank2_w0_re $and$ls180.v:6107$1390_Y - connect \builder_csrbank2_w0_we $and$ls180.v:6108$1394_Y - connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_r_re $and$ls180.v:6110$1397_Y - connect \builder_csrbank2_r_we $and$ls180.v:6111$1401_Y - connect \main_i2c_scl \main_i2c_storage [0] - connect \main_i2c_oe \main_i2c_storage [1] - connect \main_i2c_sda0 \main_i2c_storage [2] - connect \builder_csrbank2_w0_w \main_i2c_storage - connect \main_i2c_status \main_i2c_sda1 - connect \builder_csrbank2_r_w \main_i2c_status - connect \main_i2c_we \builder_csrbank2_r_we - connect \builder_csrbank3_sel $eq$ls180.v:6119$1402_Y - connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:6121$1405_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:6122$1409_Y - connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:6124$1412_Y - connect \builder_csrbank3_width3_we $and$ls180.v:6125$1416_Y - connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:6127$1419_Y - connect \builder_csrbank3_width2_we $and$ls180.v:6128$1423_Y - connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:6130$1426_Y - connect \builder_csrbank3_width1_we $and$ls180.v:6131$1430_Y - connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:6133$1433_Y - connect \builder_csrbank3_width0_we $and$ls180.v:6134$1437_Y - connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:6136$1440_Y - connect \builder_csrbank3_period3_we $and$ls180.v:6137$1444_Y - connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:6139$1447_Y - connect \builder_csrbank3_period2_we $and$ls180.v:6140$1451_Y - connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:6142$1454_Y - connect \builder_csrbank3_period1_we $and$ls180.v:6143$1458_Y - connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:6145$1461_Y - connect \builder_csrbank3_period0_we $and$ls180.v:6146$1465_Y - connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage - connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] - connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] - connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] - connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] - connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] - connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] - connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] - connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:6156$1466_Y - connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_enable0_re $and$ls180.v:6158$1469_Y - connect \builder_csrbank4_enable0_we $and$ls180.v:6159$1473_Y - connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width3_re $and$ls180.v:6161$1476_Y - connect \builder_csrbank4_width3_we $and$ls180.v:6162$1480_Y - connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width2_re $and$ls180.v:6164$1483_Y - connect \builder_csrbank4_width2_we $and$ls180.v:6165$1487_Y - connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width1_re $and$ls180.v:6167$1490_Y - connect \builder_csrbank4_width1_we $and$ls180.v:6168$1494_Y - connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width0_re $and$ls180.v:6170$1497_Y - connect \builder_csrbank4_width0_we $and$ls180.v:6171$1501_Y - connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period3_re $and$ls180.v:6173$1504_Y - connect \builder_csrbank4_period3_we $and$ls180.v:6174$1508_Y - connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period2_re $and$ls180.v:6176$1511_Y - connect \builder_csrbank4_period2_we $and$ls180.v:6177$1515_Y - connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period1_re $and$ls180.v:6179$1518_Y - connect \builder_csrbank4_period1_we $and$ls180.v:6180$1522_Y - connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period0_re $and$ls180.v:6182$1525_Y - connect \builder_csrbank4_period0_we $and$ls180.v:6183$1529_Y - connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage - connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] - connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] - connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] - connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] - connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] - connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] - connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] - connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:6193$1530_Y - connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:6195$1533_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:6196$1537_Y - connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:6198$1540_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:6199$1544_Y - connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:6201$1547_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:6202$1551_Y - connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:6204$1554_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:6205$1558_Y - connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:6207$1561_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:6208$1565_Y - connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:6210$1568_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:6211$1572_Y - connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:6213$1575_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:6214$1579_Y - connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:6216$1582_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:6217$1586_Y - connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:6219$1589_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:6220$1593_Y - connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:6222$1596_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:6223$1600_Y - connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:6225$1603_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:6226$1607_Y - connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:6228$1610_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:6229$1614_Y - connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6231$1617_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6232$1621_Y - connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:6234$1624_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:6235$1628_Y - connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6237$1631_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6238$1635_Y - connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] - connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] - connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] - connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] - connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] - connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] - connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] - connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] - connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] - connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] - connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] - connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] - connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status - connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we - connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank6_sel $eq$ls180.v:6255$1636_Y - connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6257$1639_Y - connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6258$1643_Y - connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6260$1646_Y - connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6261$1650_Y - connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6263$1653_Y - connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6264$1657_Y - connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6266$1660_Y - connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6267$1664_Y - connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6269$1667_Y - connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6270$1671_Y - connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6272$1674_Y - connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6273$1678_Y - connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6275$1681_Y - connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6276$1685_Y - connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6278$1688_Y - connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6279$1692_Y - connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:6281$1695_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:6282$1699_Y - connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6284$1702_Y - connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6285$1706_Y - connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6287$1709_Y - connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6288$1713_Y - connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6290$1716_Y - connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6291$1720_Y - connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6293$1723_Y - connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6294$1727_Y - connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6296$1730_Y - connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6297$1734_Y - connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6299$1737_Y - connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6300$1741_Y - connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6302$1744_Y - connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6303$1748_Y - connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6305$1751_Y - connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6306$1755_Y - connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6308$1758_Y - connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6309$1762_Y - connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6311$1765_Y - connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6312$1769_Y - connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6314$1772_Y - connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6315$1776_Y - connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6317$1779_Y - connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6318$1783_Y - connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6320$1786_Y - connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6321$1790_Y - connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6323$1793_Y - connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6324$1797_Y - connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6326$1800_Y - connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6327$1804_Y - connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6329$1807_Y - connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6330$1811_Y - connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_cmd_event_re $and$ls180.v:6332$1814_Y - connect \builder_csrbank6_cmd_event_we $and$ls180.v:6333$1818_Y - connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_data_event_re $and$ls180.v:6335$1821_Y - connect \builder_csrbank6_data_event_we $and$ls180.v:6336$1825_Y - connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] - connect \builder_csrbank6_block_length1_re $and$ls180.v:6338$1828_Y - connect \builder_csrbank6_block_length1_we $and$ls180.v:6339$1832_Y - connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_length0_re $and$ls180.v:6341$1835_Y - connect \builder_csrbank6_block_length0_we $and$ls180.v:6342$1839_Y - connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count3_re $and$ls180.v:6344$1842_Y - connect \builder_csrbank6_block_count3_we $and$ls180.v:6345$1846_Y - connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count2_re $and$ls180.v:6347$1849_Y - connect \builder_csrbank6_block_count2_we $and$ls180.v:6348$1853_Y - connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count1_re $and$ls180.v:6350$1856_Y - connect \builder_csrbank6_block_count1_we $and$ls180.v:6351$1860_Y - connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count0_re $and$ls180.v:6353$1863_Y - connect \builder_csrbank6_block_count0_we $and$ls180.v:6354$1867_Y - connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] - connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] - connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] - connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] - connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] - connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] - connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] - connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] - connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] - connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] - connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] - connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] - connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] - connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] - connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] - connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] - connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] - connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] - connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] - connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] - connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] - connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] - connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] - connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] - connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we - connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status - connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we - connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status - connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we - connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] - connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] - connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] - connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] - connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] - connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:6390$1868_Y - connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base7_re $and$ls180.v:6392$1871_Y - connect \builder_csrbank7_dma_base7_we $and$ls180.v:6393$1875_Y - connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base6_re $and$ls180.v:6395$1878_Y - connect \builder_csrbank7_dma_base6_we $and$ls180.v:6396$1882_Y - connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base5_re $and$ls180.v:6398$1885_Y - connect \builder_csrbank7_dma_base5_we $and$ls180.v:6399$1889_Y - connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base4_re $and$ls180.v:6401$1892_Y - connect \builder_csrbank7_dma_base4_we $and$ls180.v:6402$1896_Y - connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base3_re $and$ls180.v:6404$1899_Y - connect \builder_csrbank7_dma_base3_we $and$ls180.v:6405$1903_Y - connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base2_re $and$ls180.v:6407$1906_Y - connect \builder_csrbank7_dma_base2_we $and$ls180.v:6408$1910_Y - connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base1_re $and$ls180.v:6410$1913_Y - connect \builder_csrbank7_dma_base1_we $and$ls180.v:6411$1917_Y - connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base0_re $and$ls180.v:6413$1920_Y - connect \builder_csrbank7_dma_base0_we $and$ls180.v:6414$1924_Y - connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length3_re $and$ls180.v:6416$1927_Y - connect \builder_csrbank7_dma_length3_we $and$ls180.v:6417$1931_Y - connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length2_re $and$ls180.v:6419$1934_Y - connect \builder_csrbank7_dma_length2_we $and$ls180.v:6420$1938_Y - connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length1_re $and$ls180.v:6422$1941_Y - connect \builder_csrbank7_dma_length1_we $and$ls180.v:6423$1945_Y - connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length0_re $and$ls180.v:6425$1948_Y - connect \builder_csrbank7_dma_length0_we $and$ls180.v:6426$1952_Y - connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6428$1955_Y - connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6429$1959_Y - connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_done_re $and$ls180.v:6431$1962_Y - connect \builder_csrbank7_dma_done_we $and$ls180.v:6432$1966_Y - connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6434$1969_Y - connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6435$1973_Y - connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6437$1976_Y - connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6438$1980_Y - connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6440$1983_Y - connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6441$1987_Y - connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6443$1990_Y - connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6444$1994_Y - connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6446$1997_Y - connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6447$2001_Y - connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] - connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] - connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] - connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] - connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] - connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] - connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] - connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] - connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] - connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] - connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] - connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] - connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage - connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status - connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we - connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage - connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] - connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] - connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] - connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] - connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we - connect \builder_csrbank8_sel $eq$ls180.v:6469$2002_Y - connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_card_detect_re $and$ls180.v:6471$2005_Y - connect \builder_csrbank8_card_detect_we $and$ls180.v:6472$2009_Y - connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6474$2012_Y - connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6475$2016_Y - connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6477$2019_Y - connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6478$2023_Y - connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6480$2026_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6481$2030_Y - connect \builder_csrbank8_card_detect_w \main_sdphy_status - connect \main_sdphy_we \builder_csrbank8_card_detect_we - connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] - connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank9_sel $eq$ls180.v:6486$2031_Y - connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] - connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6488$2034_Y - connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6489$2038_Y - connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] - connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6491$2041_Y - connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6492$2045_Y - connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6494$2048_Y - connect \main_sdram_command_issue_we $and$ls180.v:6495$2052_Y - connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] - connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6497$2055_Y - connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6498$2059_Y - connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6500$2062_Y - connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6501$2066_Y - connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] - connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6503$2069_Y - connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6504$2073_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6506$2076_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6507$2080_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6509$2083_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6510$2087_Y - connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6512$2090_Y - connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6513$2094_Y - connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6515$2097_Y - connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6516$2101_Y - connect \main_sdram_sel \main_sdram_storage [0] - connect \main_sdram_cke \main_sdram_storage [1] - connect \main_sdram_odt \main_sdram_storage [2] - connect \main_sdram_reset_n \main_sdram_storage [3] - connect \builder_csrbank9_dfii_control0_w \main_sdram_storage - connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage - connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] - connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] - connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage - connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] - connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] - connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] - connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] - connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we - connect \builder_csrbank10_sel $eq$ls180.v:6531$2102_Y - connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6533$2105_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6534$2109_Y - connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6536$2112_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6537$2116_Y - connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6539$2119_Y - connect \builder_csrbank10_status_we $and$ls180.v:6540$2123_Y - connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6542$2126_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6543$2130_Y - connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6545$2133_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6546$2137_Y - connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6548$2140_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6549$2144_Y - connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6551$2147_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6552$2151_Y - connect \main_spimaster10_length \main_spimaster11_storage [15:8] - connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] - connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] - connect \main_spimaster14_status \main_spimaster13_done - connect \builder_csrbank10_status_w \main_spimaster14_status - connect \main_spimaster15_we \builder_csrbank10_status_we - connect \builder_csrbank10_mosi0_w \main_spimaster16_storage - connect \builder_csrbank10_miso_w \main_spimaster18_status - connect \main_spimaster19_we \builder_csrbank10_miso_we - connect \main_spimaster20_sel \main_spimaster21_storage - connect \builder_csrbank10_cs0_w \main_spimaster21_storage - connect \builder_csrbank10_loopback0_w \main_spimaster23_storage - connect \builder_csrbank11_sel $eq$ls180.v:6571$2153_Y - connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control1_re $and$ls180.v:6573$2156_Y - connect \builder_csrbank11_control1_we $and$ls180.v:6574$2160_Y - connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control0_re $and$ls180.v:6576$2163_Y - connect \builder_csrbank11_control0_we $and$ls180.v:6577$2167_Y - connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_status_re $and$ls180.v:6579$2170_Y - connect \builder_csrbank11_status_we $and$ls180.v:6580$2174_Y - connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_mosi0_re $and$ls180.v:6582$2177_Y - connect \builder_csrbank11_mosi0_we $and$ls180.v:6583$2181_Y - connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_miso_re $and$ls180.v:6585$2184_Y - connect \builder_csrbank11_miso_we $and$ls180.v:6586$2188_Y - connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_cs0_re $and$ls180.v:6588$2191_Y - connect \builder_csrbank11_cs0_we $and$ls180.v:6589$2195_Y - connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_loopback0_re $and$ls180.v:6591$2198_Y - connect \builder_csrbank11_loopback0_we $and$ls180.v:6592$2202_Y - connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6594$2205_Y - connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6595$2209_Y - connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6597$2212_Y - connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6598$2216_Y - connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] - connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] - connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] - connect \main_spisdcard_status_status \main_spisdcard_done1 - connect \builder_csrbank11_status_w \main_spisdcard_status_status - connect \main_spisdcard_status_we \builder_csrbank11_status_we - connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage - connect \builder_csrbank11_miso_w \main_spisdcard_miso_status - connect \main_spisdcard_miso_we \builder_csrbank11_miso_we - connect \main_spisdcard_sel \main_spisdcard_cs_storage - connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage - connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage - connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] - connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] - connect \builder_csrbank12_sel $eq$ls180.v:6619$2218_Y - connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load3_re $and$ls180.v:6621$2221_Y - connect \builder_csrbank12_load3_we $and$ls180.v:6622$2225_Y - connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load2_re $and$ls180.v:6624$2228_Y - connect \builder_csrbank12_load2_we $and$ls180.v:6625$2232_Y - connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load1_re $and$ls180.v:6627$2235_Y - connect \builder_csrbank12_load1_we $and$ls180.v:6628$2239_Y - connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load0_re $and$ls180.v:6630$2242_Y - connect \builder_csrbank12_load0_we $and$ls180.v:6631$2246_Y - connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload3_re $and$ls180.v:6633$2249_Y - connect \builder_csrbank12_reload3_we $and$ls180.v:6634$2253_Y - connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload2_re $and$ls180.v:6636$2256_Y - connect \builder_csrbank12_reload2_we $and$ls180.v:6637$2260_Y - connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload1_re $and$ls180.v:6639$2263_Y - connect \builder_csrbank12_reload1_we $and$ls180.v:6640$2267_Y - connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload0_re $and$ls180.v:6642$2270_Y - connect \builder_csrbank12_reload0_we $and$ls180.v:6643$2274_Y - connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_en0_re $and$ls180.v:6645$2277_Y - connect \builder_csrbank12_en0_we $and$ls180.v:6646$2281_Y - connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_update_value0_re $and$ls180.v:6648$2284_Y - connect \builder_csrbank12_update_value0_we $and$ls180.v:6649$2288_Y - connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value3_re $and$ls180.v:6651$2291_Y - connect \builder_csrbank12_value3_we $and$ls180.v:6652$2295_Y - connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value2_re $and$ls180.v:6654$2298_Y - connect \builder_csrbank12_value2_we $and$ls180.v:6655$2302_Y - connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value1_re $and$ls180.v:6657$2305_Y - connect \builder_csrbank12_value1_we $and$ls180.v:6658$2309_Y - connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value0_re $and$ls180.v:6660$2312_Y - connect \builder_csrbank12_value0_we $and$ls180.v:6661$2316_Y - connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6663$2319_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6664$2323_Y - connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6666$2326_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6667$2330_Y - connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6669$2333_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6670$2337_Y - connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] - connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] - connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] - connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] - connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] - connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] - connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] - connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] - connect \builder_csrbank12_en0_w \main_libresocsim_en_storage - connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage - connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] - connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] - connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] - connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] - connect \main_libresocsim_value_we \builder_csrbank12_value0_we - connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank13_sel $eq$ls180.v:6687$2338_Y - connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6689$2341_Y - connect \main_uart_rxtx_we $and$ls180.v:6690$2345_Y - connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txfull_re $and$ls180.v:6692$2348_Y - connect \builder_csrbank13_txfull_we $and$ls180.v:6693$2352_Y - connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxempty_re $and$ls180.v:6695$2355_Y - connect \builder_csrbank13_rxempty_we $and$ls180.v:6696$2359_Y - connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6698$2362_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6699$2366_Y - connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6701$2369_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6702$2373_Y - connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] - connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6704$2376_Y - connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6705$2380_Y - connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txempty_re $and$ls180.v:6707$2383_Y - connect \builder_csrbank13_txempty_we $and$ls180.v:6708$2387_Y - connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxfull_re $and$ls180.v:6710$2390_Y - connect \builder_csrbank13_rxfull_we $and$ls180.v:6711$2394_Y - connect \builder_csrbank13_txfull_w \main_uart_txfull_status - connect \main_uart_txfull_we \builder_csrbank13_txfull_we - connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status - connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we - connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage - connect \builder_csrbank13_txempty_w \main_uart_txempty_status - connect \main_uart_txempty_we \builder_csrbank13_txempty_we - connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status - connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we - connect \builder_csrbank14_sel $eq$ls180.v:6721$2395_Y - connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6723$2398_Y - connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6724$2402_Y - connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6726$2405_Y - connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6727$2409_Y - connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6729$2412_Y - connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6730$2416_Y - connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6732$2419_Y - connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6733$2423_Y - connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] - connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] - connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] - connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] - connect \builder_csr_interconnect_adr \builder_libresocsim_adr - connect \builder_csr_interconnect_we \builder_libresocsim_we - connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w - connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r - connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6787$2437_Y - connect \sdrio_clk \sys_clk_1 - connect \sdrio_clk_1 \sys_clk_1 - connect \sdrio_clk_2 \sys_clk_1 - connect \sdrio_clk_3 \sys_clk_1 - connect \sdrio_clk_4 \sys_clk_1 - connect \sdrio_clk_5 \sys_clk_1 - connect \sdrio_clk_6 \sys_clk_1 - connect \sdrio_clk_7 \sys_clk_1 - connect \sdrio_clk_8 \sys_clk_1 - connect \sdrio_clk_9 \sys_clk_1 - connect \sdrio_clk_10 \sys_clk_1 - connect \sdrio_clk_11 \sys_clk_1 - connect \sdrio_clk_12 \sys_clk_1 - connect \sdrio_clk_13 \sys_clk_1 - connect \sdrio_clk_14 \sys_clk_1 - connect \sdrio_clk_15 \sys_clk_1 - connect \sdrio_clk_16 \sys_clk_1 - connect \sdrio_clk_17 \sys_clk_1 - connect \sdrio_clk_18 \sys_clk_1 - connect \sdrio_clk_19 \sys_clk_1 - connect \sdrio_clk_20 \sys_clk_1 - connect \sdrio_clk_21 \sys_clk_1 - connect \sdrio_clk_22 \sys_clk_1 - connect \sdrio_clk_23 \sys_clk_1 - connect \sdrio_clk_24 \sys_clk_1 - connect \sdrio_clk_25 \sys_clk_1 - connect \sdrio_clk_26 \sys_clk_1 - connect \sdrio_clk_27 \sys_clk_1 - connect \sdrio_clk_28 \sys_clk_1 - connect \sdrio_clk_29 \sys_clk_1 - connect \sdrio_clk_30 \sys_clk_1 - connect \sdrio_clk_31 \sys_clk_1 - connect \sdrio_clk_32 \sys_clk_1 - connect \sdrio_clk_33 \sys_clk_1 - connect \sdrio_clk_34 \sys_clk_1 - connect \sdrio_clk_35 \sys_clk_1 - connect \sdrio_clk_36 \sys_clk_1 - connect \sdrio_clk_37 \sys_clk_1 - connect \sdrio_clk_38 \sys_clk_1 - connect \sdrio_clk_39 \sys_clk_1 - connect \sdrio_clk_40 \sys_clk_1 - connect \sdrio_clk_41 \sys_clk_1 - connect \sdrio_clk_42 \sys_clk_1 - connect \sdrio_clk_43 \sys_clk_1 - connect \sdrio_clk_44 \sys_clk_1 - connect \sdrio_clk_45 \sys_clk_1 - connect \sdrio_clk_46 \sys_clk_1 - connect \sdrio_clk_47 \sys_clk_1 - connect \sdrio_clk_48 \sys_clk_1 - connect \sdrio_clk_49 \sys_clk_1 - connect \sdrio_clk_50 \sys_clk_1 - connect \sdrio_clk_51 \sys_clk_1 - connect \sdrio_clk_52 \sys_clk_1 - connect \sdrio_clk_53 \sys_clk_1 - connect \sdrio_clk_54 \sys_clk_1 - connect \sdrio_clk_55 \sys_clk_1 - connect \main_uart_phy_rx \builder_multiregimpl0_regs1 - connect \main_pwm0_enable \main_pwm0_enable_storage - connect \main_pwm0_width \main_pwm0_width_storage - connect \main_pwm0_period \main_pwm0_period_storage - connect \main_pwm1_enable \main_pwm1_enable_storage - connect \main_pwm1_width \main_pwm1_width_storage - connect \main_pwm1_period \main_pwm1_period_storage - connect \sdrio_clk_56 \sys_clk_1 - connect \sdrio_clk_57 \sys_clk_1 - connect \sdrio_clk_58 \sys_clk_1 - connect \sdrio_clk_59 \sys_clk_1 - connect \sdrio_clk_60 \sys_clk_1 - connect \sdrio_clk_61 \sys_clk_1 - connect \sdrio_clk_62 \sys_clk_1 - connect \sdrio_clk_63 \sys_clk_1 - connect \sdrio_clk_64 \sys_clk_1 - connect \sdrio_clk_65 \sys_clk_1 - connect \sdrio_clk_66 \sys_clk_1 - connect \sdrio_clk_67 \sys_clk_1 - connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10370$2916_DATA - connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10398$2942_DATA - connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10426$2968_DATA - connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10454$2994_DATA - connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10482$3020_DATA - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10500$3027_DATA - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10514$3034_DATA - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10528$3041_DATA - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10542$3048_DATA - connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 - connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 - connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 - connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 - connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10590$3069_DATA - connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect 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$0\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $0\logical_op__is_signed$next[0:0]$6885 + attribute \src "libresoc.v:143692.3-143693.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $0\logical_op__oe__oe$next[0:0]$6886 + attribute \src "libresoc.v:143674.3-143675.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $0\logical_op__oe__ok$next[0:0]$6887 + attribute \src "libresoc.v:143676.3-143677.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $0\logical_op__output_carry$next[0:0]$6888 + attribute \src "libresoc.v:143688.3-143689.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $0\logical_op__rc__ok$next[0:0]$6889 + attribute \src "libresoc.v:143672.3-143673.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $0\logical_op__rc__rc$next[0:0]$6890 + attribute \src "libresoc.v:143670.3-143671.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $0\logical_op__write_cr0$next[0:0]$6891 + attribute \src "libresoc.v:143686.3-143687.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $0\logical_op__zero_a$next[0:0]$6892 + attribute \src "libresoc.v:143680.3-143681.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "libresoc.v:143820.3-143832.6" + wire width 2 $0\muxid$next[1:0]$6872 + attribute \src "libresoc.v:143698.3-143699.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:143875.3-143893.6" + wire width 64 $0\o$next[63:0]$6918 + attribute \src "libresoc.v:143658.3-143659.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:143875.3-143893.6" + wire $0\o_ok$next[0:0]$6919 + attribute \src "libresoc.v:143660.3-143661.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:143802.3-143819.6" + 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$1\logical_op__fn_unit$next[12:0]$6894 + attribute \src "libresoc.v:142901.14-142901.44" + wire width 13 $1\logical_op__fn_unit[12:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$6895 + attribute \src "libresoc.v:142938.14-142938.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $1\logical_op__imm_data__ok$next[0:0]$6896 + attribute \src "libresoc.v:142947.7-142947.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$6897 + attribute \src "libresoc.v:142960.13-142960.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire width 32 $1\logical_op__insn$next[31:0]$6898 + attribute \src "libresoc.v:142977.14-142977.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$6899 + attribute \src "libresoc.v:143060.13-143060.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $1\logical_op__invert_in$next[0:0]$6900 + attribute \src "libresoc.v:143217.7-143217.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $1\logical_op__invert_out$next[0:0]$6901 + attribute \src "libresoc.v:143226.7-143226.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $1\logical_op__is_32bit$next[0:0]$6902 + attribute \src "libresoc.v:143235.7-143235.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $1\logical_op__is_signed$next[0:0]$6903 + attribute \src "libresoc.v:143244.7-143244.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "libresoc.v:143833.3-143874.6" + wire $1\logical_op__oe__oe$next[0:0]$6904 + attribute \src "libresoc.v:143253.7-143253.32" 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:142579.7-142579.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute 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\enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute 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\enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 33 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 42 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 32 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len$60 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_logical_op__fn_unit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok$47 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute 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\input_logical_op__insn_type$22 + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect 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\main_logical_op__is_32bit + connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 + connect \logical_op__is_signed \main_logical_op__is_signed + connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 + connect \logical_op__oe__oe \main_logical_op__oe__oe + connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 + connect \logical_op__oe__ok \main_logical_op__oe__ok + connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 + connect \logical_op__output_carry \main_logical_op__output_carry + connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 + connect \logical_op__rc__ok \main_logical_op__rc__ok + connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 + connect \logical_op__rc__rc \main_logical_op__rc__rc + connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 + connect \logical_op__write_cr0 \main_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 + connect \logical_op__zero_a \main_logical_op__zero_a + connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$43 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_so \main_xer_so + connect \xer_so$20 \main_xer_so$62 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143794.10-143797.4" + cell \n$49 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143798.10-143801.4" + cell \p$48 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:142579.7-142579.20" + process $proc$libresoc.v:142579$6935 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:142588.13-142588.24" + process $proc$libresoc.v:142588$6936 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:142597.7-142597.21" + process $proc$libresoc.v:142597$6937 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:142878.13-142878.40" + process $proc$libresoc.v:142878$6938 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:142901.14-142901.44" + process $proc$libresoc.v:142901$6939 + assign { } { } + assign $1\logical_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:142938.14-142938.63" + process $proc$libresoc.v:142938$6940 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:142947.7-142947.38" + process $proc$libresoc.v:142947$6941 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:142960.13-142960.43" + process $proc$libresoc.v:142960$6942 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:142977.14-142977.38" + process $proc$libresoc.v:142977$6943 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] + end + attribute \src "libresoc.v:143060.13-143060.42" + process $proc$libresoc.v:143060$6944 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:143217.7-143217.35" + process $proc$libresoc.v:143217$6945 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:143226.7-143226.36" + process $proc$libresoc.v:143226$6946 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:143235.7-143235.34" + process $proc$libresoc.v:143235$6947 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:143244.7-143244.35" + process $proc$libresoc.v:143244$6948 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:143253.7-143253.32" + process $proc$libresoc.v:143253$6949 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:143262.7-143262.32" + process $proc$libresoc.v:143262$6950 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:143271.7-143271.38" + process $proc$libresoc.v:143271$6951 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:143280.7-143280.32" + process $proc$libresoc.v:143280$6952 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:143289.7-143289.32" + process $proc$libresoc.v:143289$6953 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:143298.7-143298.35" + process $proc$libresoc.v:143298$6954 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:143307.7-143307.32" + process $proc$libresoc.v:143307$6955 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:143588.13-143588.25" + process $proc$libresoc.v:143588$6956 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:143603.14-143603.38" + process $proc$libresoc.v:143603$6957 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:143610.7-143610.18" + process $proc$libresoc.v:143610$6958 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:143624.7-143624.20" + process $proc$libresoc.v:143624$6959 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:143633.7-143633.20" + process $proc$libresoc.v:143633$6960 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:143642.7-143642.23" + process $proc$libresoc.v:143642$6961 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:143650.3-143651.29" + process $proc$libresoc.v:143650$6841 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:143652.3-143653.35" + process $proc$libresoc.v:143652$6842 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:143654.3-143655.25" + process $proc$libresoc.v:143654$6843 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:143656.3-143657.31" + process $proc$libresoc.v:143656$6844 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:143658.3-143659.19" + process $proc$libresoc.v:143658$6845 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:143660.3-143661.25" + process $proc$libresoc.v:143660$6846 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:143662.3-143663.59" + process $proc$libresoc.v:143662$6847 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:143664.3-143665.55" + process $proc$libresoc.v:143664$6848 + assign { } { } + assign $0\logical_op__fn_unit[12:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:143666.3-143667.69" + process $proc$libresoc.v:143666$6849 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:143668.3-143669.65" + process $proc$libresoc.v:143668$6850 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:143670.3-143671.53" + process $proc$libresoc.v:143670$6851 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:143672.3-143673.53" + process $proc$libresoc.v:143672$6852 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:143674.3-143675.53" + process $proc$libresoc.v:143674$6853 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:143676.3-143677.53" + process $proc$libresoc.v:143676$6854 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:143678.3-143679.59" + process $proc$libresoc.v:143678$6855 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:143680.3-143681.53" + process $proc$libresoc.v:143680$6856 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:143682.3-143683.63" + process $proc$libresoc.v:143682$6857 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:143684.3-143685.61" + process $proc$libresoc.v:143684$6858 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:143686.3-143687.59" + process $proc$libresoc.v:143686$6859 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:143688.3-143689.65" + process $proc$libresoc.v:143688$6860 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:143690.3-143691.57" + process $proc$libresoc.v:143690$6861 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:143692.3-143693.59" + process $proc$libresoc.v:143692$6862 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:143694.3-143695.57" + process $proc$libresoc.v:143694$6863 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:143696.3-143697.49" + process $proc$libresoc.v:143696$6864 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] + end + attribute \src "libresoc.v:143698.3-143699.27" + process $proc$libresoc.v:143698$6865 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:143700.3-143701.29" + process $proc$libresoc.v:143700$6866 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:143802.3-143819.6" + process $proc$libresoc.v:143802$6867 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$6868 $2\r_busy$next[0:0]$6870 + attribute \src "libresoc.v:143803.5-143803.29" + switch \initial + attribute \src "libresoc.v:143803.9-143803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$6869 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$6869 1'0 + case + assign $1\r_busy$next[0:0]$6869 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$6870 1'0 + case + assign $2\r_busy$next[0:0]$6870 $1\r_busy$next[0:0]$6869 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$6868 + end + attribute \src "libresoc.v:143820.3-143832.6" + process $proc$libresoc.v:143820$6871 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$6872 $1\muxid$next[1:0]$6873 + attribute \src "libresoc.v:143821.5-143821.29" + switch \initial + attribute \src "libresoc.v:143821.9-143821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$6873 \muxid$66 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$6873 \muxid$66 + case + assign $1\muxid$next[1:0]$6873 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$6872 + end + attribute \src "libresoc.v:143833.3-143874.6" + process $proc$libresoc.v:143833$6874 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$6875 $1\logical_op__data_len$next[3:0]$6893 + assign $0\logical_op__fn_unit$next[12:0]$6876 $1\logical_op__fn_unit$next[12:0]$6894 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$6879 $1\logical_op__input_carry$next[1:0]$6897 + assign $0\logical_op__insn$next[31:0]$6880 $1\logical_op__insn$next[31:0]$6898 + assign $0\logical_op__insn_type$next[6:0]$6881 $1\logical_op__insn_type$next[6:0]$6899 + assign $0\logical_op__invert_in$next[0:0]$6882 $1\logical_op__invert_in$next[0:0]$6900 + assign $0\logical_op__invert_out$next[0:0]$6883 $1\logical_op__invert_out$next[0:0]$6901 + assign $0\logical_op__is_32bit$next[0:0]$6884 $1\logical_op__is_32bit$next[0:0]$6902 + assign $0\logical_op__is_signed$next[0:0]$6885 $1\logical_op__is_signed$next[0:0]$6903 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$6888 $1\logical_op__output_carry$next[0:0]$6906 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$6891 $1\logical_op__write_cr0$next[0:0]$6909 + assign $0\logical_op__zero_a$next[0:0]$6892 $1\logical_op__zero_a$next[0:0]$6910 + assign $0\logical_op__imm_data__data$next[63:0]$6877 $2\logical_op__imm_data__data$next[63:0]$6911 + assign $0\logical_op__imm_data__ok$next[0:0]$6878 $2\logical_op__imm_data__ok$next[0:0]$6912 + assign $0\logical_op__oe__oe$next[0:0]$6886 $2\logical_op__oe__oe$next[0:0]$6913 + assign $0\logical_op__oe__ok$next[0:0]$6887 $2\logical_op__oe__ok$next[0:0]$6914 + assign $0\logical_op__rc__ok$next[0:0]$6889 $2\logical_op__rc__ok$next[0:0]$6915 + assign $0\logical_op__rc__rc$next[0:0]$6890 $2\logical_op__rc__rc$next[0:0]$6916 + attribute \src "libresoc.v:143834.5-143834.29" + switch \initial + attribute \src "libresoc.v:143834.9-143834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$6898 $1\logical_op__data_len$next[3:0]$6893 $1\logical_op__is_signed$next[0:0]$6903 $1\logical_op__is_32bit$next[0:0]$6902 $1\logical_op__output_carry$next[0:0]$6906 $1\logical_op__write_cr0$next[0:0]$6909 $1\logical_op__invert_out$next[0:0]$6901 $1\logical_op__input_carry$next[1:0]$6897 $1\logical_op__zero_a$next[0:0]$6910 $1\logical_op__invert_in$next[0:0]$6900 $1\logical_op__oe__ok$next[0:0]$6905 $1\logical_op__oe__oe$next[0:0]$6904 $1\logical_op__rc__ok$next[0:0]$6907 $1\logical_op__rc__rc$next[0:0]$6908 $1\logical_op__imm_data__ok$next[0:0]$6896 $1\logical_op__imm_data__data$next[63:0]$6895 $1\logical_op__fn_unit$next[12:0]$6894 $1\logical_op__insn_type$next[6:0]$6899 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$6898 $1\logical_op__data_len$next[3:0]$6893 $1\logical_op__is_signed$next[0:0]$6903 $1\logical_op__is_32bit$next[0:0]$6902 $1\logical_op__output_carry$next[0:0]$6906 $1\logical_op__write_cr0$next[0:0]$6909 $1\logical_op__invert_out$next[0:0]$6901 $1\logical_op__input_carry$next[1:0]$6897 $1\logical_op__zero_a$next[0:0]$6910 $1\logical_op__invert_in$next[0:0]$6900 $1\logical_op__oe__ok$next[0:0]$6905 $1\logical_op__oe__oe$next[0:0]$6904 $1\logical_op__rc__ok$next[0:0]$6907 $1\logical_op__rc__rc$next[0:0]$6908 $1\logical_op__imm_data__ok$next[0:0]$6896 $1\logical_op__imm_data__data$next[63:0]$6895 $1\logical_op__fn_unit$next[12:0]$6894 $1\logical_op__insn_type$next[6:0]$6899 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + case + assign $1\logical_op__data_len$next[3:0]$6893 \logical_op__data_len + assign $1\logical_op__fn_unit$next[12:0]$6894 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6895 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6896 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6897 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6898 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6899 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6900 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6901 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6902 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6903 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6904 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6905 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6906 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6907 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6908 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6909 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6910 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$6911 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6912 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6916 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6915 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6913 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6914 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$6911 $1\logical_op__imm_data__data$next[63:0]$6895 + assign $2\logical_op__imm_data__ok$next[0:0]$6912 $1\logical_op__imm_data__ok$next[0:0]$6896 + assign $2\logical_op__oe__oe$next[0:0]$6913 $1\logical_op__oe__oe$next[0:0]$6904 + assign $2\logical_op__oe__ok$next[0:0]$6914 $1\logical_op__oe__ok$next[0:0]$6905 + assign $2\logical_op__rc__ok$next[0:0]$6915 $1\logical_op__rc__ok$next[0:0]$6907 + assign $2\logical_op__rc__rc$next[0:0]$6916 $1\logical_op__rc__rc$next[0:0]$6908 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6875 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$6876 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6877 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6878 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6879 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6880 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6881 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6882 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6883 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6884 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6885 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6886 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6887 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6888 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6889 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6890 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6891 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6892 + end + attribute \src "libresoc.v:143875.3-143893.6" + process $proc$libresoc.v:143875$6917 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$6918 $1\o$next[63:0]$6920 + assign { } { } + assign $0\o_ok$next[0:0]$6919 $2\o_ok$next[0:0]$6922 + attribute \src "libresoc.v:143876.5-143876.29" + switch \initial + attribute \src "libresoc.v:143876.9-143876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$6921 $1\o$next[63:0]$6920 } { \o_ok$86 \o$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$6921 $1\o$next[63:0]$6920 } { \o_ok$86 \o$85 } + case + assign $1\o$next[63:0]$6920 \o + assign $1\o_ok$next[0:0]$6921 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$6922 1'0 + case + assign $2\o_ok$next[0:0]$6922 $1\o_ok$next[0:0]$6921 + end + sync always + update \o$next $0\o$next[63:0]$6918 + update \o_ok$next $0\o_ok$next[0:0]$6919 + end + attribute \src "libresoc.v:143894.3-143912.6" + process $proc$libresoc.v:143894$6923 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$6924 $1\cr_a$next[3:0]$6926 + assign { } { } + assign $0\cr_a_ok$next[0:0]$6925 $2\cr_a_ok$next[0:0]$6928 + attribute \src "libresoc.v:143895.5-143895.29" + switch \initial + attribute \src "libresoc.v:143895.9-143895.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$6927 $1\cr_a$next[3:0]$6926 } { \cr_a_ok$88 \cr_a$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$6927 $1\cr_a$next[3:0]$6926 } { \cr_a_ok$88 \cr_a$87 } + case + assign $1\cr_a$next[3:0]$6926 \cr_a + assign $1\cr_a_ok$next[0:0]$6927 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$6928 1'0 + case + assign $2\cr_a_ok$next[0:0]$6928 $1\cr_a_ok$next[0:0]$6927 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$6924 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6925 + end + attribute \src "libresoc.v:143913.3-143931.6" + process $proc$libresoc.v:143913$6929 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$6930 $1\xer_so$next[0:0]$6932 + assign { } { } + assign $0\xer_so_ok$next[0:0]$6931 $2\xer_so_ok$next[0:0]$6934 + attribute \src "libresoc.v:143914.5-143914.29" + switch \initial + attribute \src "libresoc.v:143914.9-143914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$6933 $1\xer_so$next[0:0]$6932 } { \xer_so_ok$92 \xer_so$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$6933 $1\xer_so$next[0:0]$6932 } { \xer_so_ok$92 \xer_so$91 } + case + assign $1\xer_so$next[0:0]$6932 \xer_so + assign $1\xer_so_ok$next[0:0]$6933 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$6934 1'0 + case + assign $2\xer_so_ok$next[0:0]$6934 $1\xer_so_ok$next[0:0]$6933 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$6930 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6931 + end + connect \$64 $and$libresoc.v:143649$6840_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } + connect \muxid$66 \main_muxid$43 + connect \p_valid_i_p_ready_o \$64 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$63 \p_valid_i + connect \main_xer_so \input_xer_so$42 + connect \main_rb \input_rb$41 + connect \main_ra \input_ra$40 + connect { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in \main_logical_op__oe__ok \main_logical_op__oe__oe \main_logical_op__rc__ok \main_logical_op__rc__rc \main_logical_op__imm_data__ok \main_logical_op__imm_data__data \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:143959.1-144982.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" +attribute \generator "nMigen" +module \logical_pipe2 + attribute \src "libresoc.v:144949.3-144967.6" + wire width 4 $0\cr_a$22$next[3:0]$7067 + attribute \src "libresoc.v:144753.3-144754.33" + wire width 4 $0\cr_a$22[3:0]$6964 + attribute \src "libresoc.v:143971.13-143971.29" + wire width 4 $0\cr_a$22[3:0]$7074 + attribute \src "libresoc.v:144949.3-144967.6" + wire $0\cr_a_ok$23$next[0:0]$7068 + attribute \src "libresoc.v:144755.3-144756.39" + wire $0\cr_a_ok$23[0:0]$6966 + attribute \src "libresoc.v:143980.7-143980.26" + wire $0\cr_a_ok$23[0:0]$7076 + attribute \src "libresoc.v:143960.7-143960.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:144888.3-144929.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$7018 + attribute \src "libresoc.v:144793.3-144794.65" + wire width 4 $0\logical_op__data_len$18[3:0]$7004 + attribute \src "libresoc.v:143991.13-143991.45" + wire width 4 $0\logical_op__data_len$18[3:0]$7078 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 13 $0\logical_op__fn_unit$3$next[12:0]$7019 + attribute \src "libresoc.v:144763.3-144764.61" + wire width 13 $0\logical_op__fn_unit$3[12:0]$6974 + attribute \src "libresoc.v:144028.14-144028.48" + wire width 13 $0\logical_op__fn_unit$3[12:0]$7080 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7020 + attribute \src "libresoc.v:144765.3-144766.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6976 + attribute \src "libresoc.v:144051.14-144051.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$7082 + attribute \src "libresoc.v:144888.3-144929.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$7021 + attribute \src "libresoc.v:144767.3-144768.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6978 + attribute \src "libresoc.v:144060.7-144060.42" + wire $0\logical_op__imm_data__ok$5[0:0]$7084 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$7022 + attribute \src "libresoc.v:144781.3-144782.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$6992 + attribute \src "libresoc.v:144077.13-144077.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$7086 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$7023 + attribute \src "libresoc.v:144795.3-144796.57" + wire width 32 $0\logical_op__insn$19[31:0]$7006 + attribute \src "libresoc.v:144090.14-144090.43" + wire width 32 $0\logical_op__insn$19[31:0]$7088 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$7024 + attribute \src "libresoc.v:144761.3-144762.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6972 + attribute \src "libresoc.v:144247.13-144247.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$7090 + attribute \src "libresoc.v:144888.3-144929.6" + wire $0\logical_op__invert_in$10$next[0:0]$7025 + attribute \src "libresoc.v:144777.3-144778.67" + wire $0\logical_op__invert_in$10[0:0]$6988 + attribute \src "libresoc.v:144330.7-144330.40" + wire $0\logical_op__invert_in$10[0:0]$7092 + attribute \src "libresoc.v:144888.3-144929.6" + wire $0\logical_op__invert_out$13$next[0:0]$7026 + attribute \src "libresoc.v:144783.3-144784.69" + wire $0\logical_op__invert_out$13[0:0]$6994 + attribute \src "libresoc.v:144339.7-144339.41" + wire $0\logical_op__invert_out$13[0:0]$7094 + attribute \src "libresoc.v:144888.3-144929.6" + wire $0\logical_op__is_32bit$16$next[0:0]$7027 + attribute \src "libresoc.v:144789.3-144790.65" + wire $0\logical_op__is_32bit$16[0:0]$7000 + attribute \src "libresoc.v:144348.7-144348.39" + wire $0\logical_op__is_32bit$16[0:0]$7096 + attribute \src "libresoc.v:144888.3-144929.6" + wire $0\logical_op__is_signed$17$next[0:0]$7028 + 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$0\logical_op__output_carry$15[0:0]$7104 + attribute \src "libresoc.v:144888.3-144929.6" + wire $0\logical_op__rc__ok$7$next[0:0]$7032 + attribute \src "libresoc.v:144771.3-144772.59" + wire $0\logical_op__rc__ok$7[0:0]$6982 + attribute \src "libresoc.v:144395.7-144395.36" + wire $0\logical_op__rc__ok$7[0:0]$7106 + attribute \src "libresoc.v:144888.3-144929.6" + wire $0\logical_op__rc__rc$6$next[0:0]$7033 + attribute \src "libresoc.v:144769.3-144770.59" + wire $0\logical_op__rc__rc$6[0:0]$6980 + attribute \src "libresoc.v:144404.7-144404.36" + wire $0\logical_op__rc__rc$6[0:0]$7108 + attribute \src "libresoc.v:144888.3-144929.6" + wire $0\logical_op__write_cr0$14$next[0:0]$7034 + attribute \src "libresoc.v:144785.3-144786.67" + wire $0\logical_op__write_cr0$14[0:0]$6996 + attribute \src "libresoc.v:144411.7-144411.40" + wire $0\logical_op__write_cr0$14[0:0]$7110 + attribute \src "libresoc.v:144888.3-144929.6" + wire $0\logical_op__zero_a$11$next[0:0]$7035 + attribute \src "libresoc.v:144779.3-144780.61" + wire $0\logical_op__zero_a$11[0:0]$6990 + attribute \src "libresoc.v:144420.7-144420.37" + wire $0\logical_op__zero_a$11[0:0]$7112 + attribute \src "libresoc.v:144875.3-144887.6" + wire width 2 $0\muxid$1$next[1:0]$7015 + attribute \src "libresoc.v:144797.3-144798.33" + wire width 2 $0\muxid$1[1:0]$7008 + attribute \src "libresoc.v:144429.13-144429.29" + wire width 2 $0\muxid$1[1:0]$7114 + attribute \src "libresoc.v:144930.3-144948.6" + wire width 64 $0\o$20$next[63:0]$7061 + attribute \src "libresoc.v:144757.3-144758.27" + wire width 64 $0\o$20[63:0]$6968 + attribute \src "libresoc.v:144444.14-144444.43" + wire width 64 $0\o$20[63:0]$7116 + attribute \src "libresoc.v:144930.3-144948.6" + wire $0\o_ok$21$next[0:0]$7062 + attribute \src "libresoc.v:144759.3-144760.33" + wire $0\o_ok$21[0:0]$6970 + attribute \src "libresoc.v:144453.7-144453.23" + wire $0\o_ok$21[0:0]$7118 + attribute \src "libresoc.v:144857.3-144874.6" + wire $0\r_busy$next[0:0]$7011 + attribute \src "libresoc.v:144799.3-144800.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:144949.3-144967.6" + wire width 4 $1\cr_a$22$next[3:0]$7069 + attribute \src "libresoc.v:144949.3-144967.6" + wire $1\cr_a_ok$23$next[0:0]$7070 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$7036 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 13 $1\logical_op__fn_unit$3$next[12:0]$7037 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7038 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$7039 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$7040 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$7041 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$7042 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__invert_in$10$next[0:0]$7043 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__invert_out$13$next[0:0]$7044 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__is_32bit$16$next[0:0]$7045 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__is_signed$17$next[0:0]$7046 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__oe__oe$8$next[0:0]$7047 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__oe__ok$9$next[0:0]$7048 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__output_carry$15$next[0:0]$7049 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__rc__ok$7$next[0:0]$7050 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__rc__rc$6$next[0:0]$7051 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__write_cr0$14$next[0:0]$7052 + attribute \src "libresoc.v:144888.3-144929.6" + wire $1\logical_op__zero_a$11$next[0:0]$7053 + attribute \src "libresoc.v:144875.3-144887.6" + wire width 2 $1\muxid$1$next[1:0]$7016 + attribute \src "libresoc.v:144930.3-144948.6" + wire width 64 $1\o$20$next[63:0]$7063 + attribute \src "libresoc.v:144930.3-144948.6" + wire $1\o_ok$21$next[0:0]$7064 + attribute \src "libresoc.v:144857.3-144874.6" + wire $1\r_busy$next[0:0]$7012 + attribute \src "libresoc.v:144743.7-144743.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:144949.3-144967.6" + wire $2\cr_a_ok$23$next[0:0]$7071 + attribute \src "libresoc.v:144888.3-144929.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7054 + attribute \src "libresoc.v:144888.3-144929.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$7055 + attribute \src "libresoc.v:144888.3-144929.6" + wire $2\logical_op__oe__oe$8$next[0:0]$7056 + attribute \src "libresoc.v:144888.3-144929.6" + wire $2\logical_op__oe__ok$9$next[0:0]$7057 + attribute \src "libresoc.v:144888.3-144929.6" + wire $2\logical_op__rc__ok$7$next[0:0]$7058 + attribute \src "libresoc.v:144888.3-144929.6" + wire $2\logical_op__rc__rc$6$next[0:0]$7059 + attribute \src "libresoc.v:144930.3-144948.6" + wire $2\o_ok$21$next[0:0]$7065 + attribute \src "libresoc.v:144857.3-144874.6" + wire $2\r_busy$next[0:0]$7013 + attribute \src "libresoc.v:144752.18-144752.118" + wire $and$libresoc.v:144752$6962_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 54 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 52 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 53 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$73 + attribute \src "libresoc.v:143960.7-143960.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 33 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 42 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 32 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 30 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 29 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 50 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:144752$6962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$48 + connect \B \p_ready_o + connect \Y $and$libresoc.v:144752$6962_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144801.10-144804.4" + cell \n$53 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144805.15-144852.4" + cell \output$54 \output + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$45 + connect \cr_a_ok \output_cr_a_ok + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__data_len$18 \output_logical_op__data_len$41 + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 + connect \logical_op__insn \output_logical_op__insn + connect \logical_op__insn$19 \output_logical_op__insn$42 + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 + connect \logical_op__oe__ok \output_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 + connect \logical_op__rc__ok \output_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$24 + connect \o \output_o + connect \o$20 \output_o$43 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$44 + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144853.10-144856.4" + cell \p$52 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:143960.7-143960.20" + process $proc$libresoc.v:143960$7072 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143971.13-143971.29" + process $proc$libresoc.v:143971$7073 + assign { } { } + assign $0\cr_a$22[3:0]$7074 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$7074 + end + attribute \src "libresoc.v:143980.7-143980.26" + process $proc$libresoc.v:143980$7075 + assign { } { } + assign $0\cr_a_ok$23[0:0]$7076 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7076 + end + attribute \src "libresoc.v:143991.13-143991.45" + process $proc$libresoc.v:143991$7077 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$7078 4'0000 + sync always + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7078 + end + attribute \src "libresoc.v:144028.14-144028.48" + process $proc$libresoc.v:144028$7079 + assign { } { } + assign $0\logical_op__fn_unit$3[12:0]$7080 13'0000000000000 + sync always + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$7080 + end + attribute \src "libresoc.v:144051.14-144051.67" + process $proc$libresoc.v:144051$7081 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$7082 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7082 + end + attribute \src "libresoc.v:144060.7-144060.42" + process $proc$libresoc.v:144060$7083 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$7084 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7084 + end + attribute \src "libresoc.v:144077.13-144077.48" + process $proc$libresoc.v:144077$7085 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$7086 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7086 + end + attribute \src "libresoc.v:144090.14-144090.43" + process $proc$libresoc.v:144090$7087 + assign { } { } + assign $0\logical_op__insn$19[31:0]$7088 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7088 + end + attribute \src "libresoc.v:144247.13-144247.46" + process $proc$libresoc.v:144247$7089 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$7090 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7090 + end + attribute \src "libresoc.v:144330.7-144330.40" + process $proc$libresoc.v:144330$7091 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$7092 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7092 + end + attribute \src "libresoc.v:144339.7-144339.41" + process $proc$libresoc.v:144339$7093 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$7094 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7094 + end + attribute \src "libresoc.v:144348.7-144348.39" + process $proc$libresoc.v:144348$7095 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$7096 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7096 + end + attribute \src "libresoc.v:144357.7-144357.40" + process $proc$libresoc.v:144357$7097 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$7098 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7098 + end + attribute \src "libresoc.v:144368.7-144368.36" + process $proc$libresoc.v:144368$7099 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$7100 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7100 + end + attribute \src "libresoc.v:144377.7-144377.36" + process $proc$libresoc.v:144377$7101 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$7102 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7102 + end + attribute \src "libresoc.v:144384.7-144384.43" + process $proc$libresoc.v:144384$7103 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$7104 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7104 + end + attribute \src "libresoc.v:144395.7-144395.36" + process $proc$libresoc.v:144395$7105 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$7106 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7106 + end + attribute \src "libresoc.v:144404.7-144404.36" + process $proc$libresoc.v:144404$7107 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$7108 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7108 + end + attribute \src "libresoc.v:144411.7-144411.40" + process $proc$libresoc.v:144411$7109 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$7110 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7110 + end + attribute \src "libresoc.v:144420.7-144420.37" + process $proc$libresoc.v:144420$7111 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$7112 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7112 + end + attribute \src "libresoc.v:144429.13-144429.29" + process $proc$libresoc.v:144429$7113 + assign { } { } + assign $0\muxid$1[1:0]$7114 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7114 + end + attribute \src "libresoc.v:144444.14-144444.43" + process $proc$libresoc.v:144444$7115 + assign { } { } + assign $0\o$20[63:0]$7116 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$7116 + end + attribute \src "libresoc.v:144453.7-144453.23" + process $proc$libresoc.v:144453$7117 + assign { } { } + assign $0\o_ok$21[0:0]$7118 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$7118 + end + attribute \src "libresoc.v:144743.7-144743.20" + process $proc$libresoc.v:144743$7119 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:144753.3-144754.33" + process $proc$libresoc.v:144753$6963 + assign { } { } + assign $0\cr_a$22[3:0]$6964 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$6964 + end + attribute \src "libresoc.v:144755.3-144756.39" + process $proc$libresoc.v:144755$6965 + assign { } { } + assign $0\cr_a_ok$23[0:0]$6966 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6966 + end + attribute \src "libresoc.v:144757.3-144758.27" + process $proc$libresoc.v:144757$6967 + assign { } { } + assign $0\o$20[63:0]$6968 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$6968 + end + attribute \src "libresoc.v:144759.3-144760.33" + process $proc$libresoc.v:144759$6969 + assign { } { } + assign $0\o_ok$21[0:0]$6970 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$6970 + end + attribute \src "libresoc.v:144761.3-144762.65" + process $proc$libresoc.v:144761$6971 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$6972 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6972 + end + attribute \src "libresoc.v:144763.3-144764.61" + process $proc$libresoc.v:144763$6973 + assign { } { } + assign $0\logical_op__fn_unit$3[12:0]$6974 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$6974 + end + attribute \src "libresoc.v:144765.3-144766.75" + process $proc$libresoc.v:144765$6975 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$6976 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6976 + end + attribute \src "libresoc.v:144767.3-144768.71" + process $proc$libresoc.v:144767$6977 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$6978 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6978 + end + attribute \src "libresoc.v:144769.3-144770.59" + process $proc$libresoc.v:144769$6979 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$6980 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6980 + end + attribute \src "libresoc.v:144771.3-144772.59" + process $proc$libresoc.v:144771$6981 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$6982 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6982 + end + attribute \src "libresoc.v:144773.3-144774.59" + process $proc$libresoc.v:144773$6983 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$6984 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6984 + end + attribute \src "libresoc.v:144775.3-144776.59" + process $proc$libresoc.v:144775$6985 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$6986 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6986 + end + attribute \src "libresoc.v:144777.3-144778.67" + process $proc$libresoc.v:144777$6987 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$6988 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6988 + end + attribute \src "libresoc.v:144779.3-144780.61" + process $proc$libresoc.v:144779$6989 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$6990 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6990 + end + attribute \src "libresoc.v:144781.3-144782.71" + process $proc$libresoc.v:144781$6991 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$6992 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6992 + end + attribute \src "libresoc.v:144783.3-144784.69" + process $proc$libresoc.v:144783$6993 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$6994 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6994 + end + attribute \src "libresoc.v:144785.3-144786.67" + process $proc$libresoc.v:144785$6995 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$6996 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6996 + end + attribute \src "libresoc.v:144787.3-144788.73" + process $proc$libresoc.v:144787$6997 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$6998 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6998 + end + attribute \src "libresoc.v:144789.3-144790.65" + process $proc$libresoc.v:144789$6999 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$7000 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7000 + end + attribute \src "libresoc.v:144791.3-144792.67" + process $proc$libresoc.v:144791$7001 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$7002 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7002 + end + attribute \src "libresoc.v:144793.3-144794.65" + process $proc$libresoc.v:144793$7003 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$7004 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7004 + end + attribute \src "libresoc.v:144795.3-144796.57" + process $proc$libresoc.v:144795$7005 + assign { } { } + assign $0\logical_op__insn$19[31:0]$7006 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7006 + end + attribute \src "libresoc.v:144797.3-144798.33" + process $proc$libresoc.v:144797$7007 + assign { } { } + assign $0\muxid$1[1:0]$7008 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7008 + end + attribute \src "libresoc.v:144799.3-144800.29" + process $proc$libresoc.v:144799$7009 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:144857.3-144874.6" + process $proc$libresoc.v:144857$7010 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7011 $2\r_busy$next[0:0]$7013 + attribute \src "libresoc.v:144858.5-144858.29" + switch \initial + attribute \src "libresoc.v:144858.9-144858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7012 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7012 1'0 + case + assign $1\r_busy$next[0:0]$7012 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7013 1'0 + case + assign $2\r_busy$next[0:0]$7013 $1\r_busy$next[0:0]$7012 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7011 + end + attribute \src "libresoc.v:144875.3-144887.6" + process $proc$libresoc.v:144875$7014 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7015 $1\muxid$1$next[1:0]$7016 + attribute \src "libresoc.v:144876.5-144876.29" + switch \initial + attribute \src "libresoc.v:144876.9-144876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7016 \muxid$51 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7016 \muxid$51 + case + assign $1\muxid$1$next[1:0]$7016 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7015 + end + attribute \src "libresoc.v:144888.3-144929.6" + process $proc$libresoc.v:144888$7017 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$7018 $1\logical_op__data_len$18$next[3:0]$7036 + assign $0\logical_op__fn_unit$3$next[12:0]$7019 $1\logical_op__fn_unit$3$next[12:0]$7037 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$7022 $1\logical_op__input_carry$12$next[1:0]$7040 + assign $0\logical_op__insn$19$next[31:0]$7023 $1\logical_op__insn$19$next[31:0]$7041 + assign $0\logical_op__insn_type$2$next[6:0]$7024 $1\logical_op__insn_type$2$next[6:0]$7042 + assign $0\logical_op__invert_in$10$next[0:0]$7025 $1\logical_op__invert_in$10$next[0:0]$7043 + assign $0\logical_op__invert_out$13$next[0:0]$7026 $1\logical_op__invert_out$13$next[0:0]$7044 + assign $0\logical_op__is_32bit$16$next[0:0]$7027 $1\logical_op__is_32bit$16$next[0:0]$7045 + assign $0\logical_op__is_signed$17$next[0:0]$7028 $1\logical_op__is_signed$17$next[0:0]$7046 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$7031 $1\logical_op__output_carry$15$next[0:0]$7049 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$7034 $1\logical_op__write_cr0$14$next[0:0]$7052 + assign $0\logical_op__zero_a$11$next[0:0]$7035 $1\logical_op__zero_a$11$next[0:0]$7053 + assign $0\logical_op__imm_data__data$4$next[63:0]$7020 $2\logical_op__imm_data__data$4$next[63:0]$7054 + assign $0\logical_op__imm_data__ok$5$next[0:0]$7021 $2\logical_op__imm_data__ok$5$next[0:0]$7055 + assign $0\logical_op__oe__oe$8$next[0:0]$7029 $2\logical_op__oe__oe$8$next[0:0]$7056 + assign $0\logical_op__oe__ok$9$next[0:0]$7030 $2\logical_op__oe__ok$9$next[0:0]$7057 + assign $0\logical_op__rc__ok$7$next[0:0]$7032 $2\logical_op__rc__ok$7$next[0:0]$7058 + assign $0\logical_op__rc__rc$6$next[0:0]$7033 $2\logical_op__rc__rc$6$next[0:0]$7059 + attribute \src "libresoc.v:144889.5-144889.29" + switch \initial + attribute \src "libresoc.v:144889.9-144889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$7041 $1\logical_op__data_len$18$next[3:0]$7036 $1\logical_op__is_signed$17$next[0:0]$7046 $1\logical_op__is_32bit$16$next[0:0]$7045 $1\logical_op__output_carry$15$next[0:0]$7049 $1\logical_op__write_cr0$14$next[0:0]$7052 $1\logical_op__invert_out$13$next[0:0]$7044 $1\logical_op__input_carry$12$next[1:0]$7040 $1\logical_op__zero_a$11$next[0:0]$7053 $1\logical_op__invert_in$10$next[0:0]$7043 $1\logical_op__oe__ok$9$next[0:0]$7048 $1\logical_op__oe__oe$8$next[0:0]$7047 $1\logical_op__rc__ok$7$next[0:0]$7050 $1\logical_op__rc__rc$6$next[0:0]$7051 $1\logical_op__imm_data__ok$5$next[0:0]$7039 $1\logical_op__imm_data__data$4$next[63:0]$7038 $1\logical_op__fn_unit$3$next[12:0]$7037 $1\logical_op__insn_type$2$next[6:0]$7042 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$7041 $1\logical_op__data_len$18$next[3:0]$7036 $1\logical_op__is_signed$17$next[0:0]$7046 $1\logical_op__is_32bit$16$next[0:0]$7045 $1\logical_op__output_carry$15$next[0:0]$7049 $1\logical_op__write_cr0$14$next[0:0]$7052 $1\logical_op__invert_out$13$next[0:0]$7044 $1\logical_op__input_carry$12$next[1:0]$7040 $1\logical_op__zero_a$11$next[0:0]$7053 $1\logical_op__invert_in$10$next[0:0]$7043 $1\logical_op__oe__ok$9$next[0:0]$7048 $1\logical_op__oe__oe$8$next[0:0]$7047 $1\logical_op__rc__ok$7$next[0:0]$7050 $1\logical_op__rc__rc$6$next[0:0]$7051 $1\logical_op__imm_data__ok$5$next[0:0]$7039 $1\logical_op__imm_data__data$4$next[63:0]$7038 $1\logical_op__fn_unit$3$next[12:0]$7037 $1\logical_op__insn_type$2$next[6:0]$7042 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + case + assign $1\logical_op__data_len$18$next[3:0]$7036 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[12:0]$7037 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$7038 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$7039 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$7040 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$7041 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$7042 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$7043 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$7044 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$7045 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$7046 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$7047 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$7048 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$7049 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$7050 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$7051 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$7052 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$7053 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$7054 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7055 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$7059 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$7058 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$7056 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$7057 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$7054 $1\logical_op__imm_data__data$4$next[63:0]$7038 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7055 $1\logical_op__imm_data__ok$5$next[0:0]$7039 + assign $2\logical_op__oe__oe$8$next[0:0]$7056 $1\logical_op__oe__oe$8$next[0:0]$7047 + assign $2\logical_op__oe__ok$9$next[0:0]$7057 $1\logical_op__oe__ok$9$next[0:0]$7048 + assign $2\logical_op__rc__ok$7$next[0:0]$7058 $1\logical_op__rc__ok$7$next[0:0]$7050 + assign $2\logical_op__rc__rc$6$next[0:0]$7059 $1\logical_op__rc__rc$6$next[0:0]$7051 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7018 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$7019 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7020 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7021 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7022 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7023 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7024 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7025 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7026 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7027 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7028 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7029 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7030 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7031 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7032 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7033 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7034 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7035 + end + attribute \src "libresoc.v:144930.3-144948.6" + process $proc$libresoc.v:144930$7060 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$7061 $1\o$20$next[63:0]$7063 + assign { } { } + assign $0\o_ok$21$next[0:0]$7062 $2\o_ok$21$next[0:0]$7065 + attribute \src "libresoc.v:144931.5-144931.29" + switch \initial + attribute \src "libresoc.v:144931.9-144931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$7064 $1\o$20$next[63:0]$7063 } { \o_ok$71 \o$70 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$7064 $1\o$20$next[63:0]$7063 } { \o_ok$71 \o$70 } + case + assign $1\o$20$next[63:0]$7063 \o$20 + assign $1\o_ok$21$next[0:0]$7064 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$7065 1'0 + case + assign $2\o_ok$21$next[0:0]$7065 $1\o_ok$21$next[0:0]$7064 + end + sync always + update \o$20$next $0\o$20$next[63:0]$7061 + update \o_ok$21$next $0\o_ok$21$next[0:0]$7062 + end + attribute \src "libresoc.v:144949.3-144967.6" + process $proc$libresoc.v:144949$7066 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$22$next[3:0]$7067 $1\cr_a$22$next[3:0]$7069 + assign { } { } + assign $0\cr_a_ok$23$next[0:0]$7068 $2\cr_a_ok$23$next[0:0]$7071 + attribute \src "libresoc.v:144950.5-144950.29" + switch \initial + attribute \src "libresoc.v:144950.9-144950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$7070 $1\cr_a$22$next[3:0]$7069 } { \cr_a_ok$73 \cr_a$72 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$7070 $1\cr_a$22$next[3:0]$7069 } { \cr_a_ok$73 \cr_a$72 } + case + assign $1\cr_a$22$next[3:0]$7069 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$7070 \cr_a_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$23$next[0:0]$7071 1'0 + case + assign $2\cr_a_ok$23$next[0:0]$7071 $1\cr_a_ok$23$next[0:0]$7070 + end + sync always + update \cr_a$22$next $0\cr_a$22$next[3:0]$7067 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7068 + end + connect \$49 $and$libresoc.v:144752$6962_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } + connect { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } + connect \muxid$51 \output_muxid$24 + connect \p_valid_i_p_ready_o \$49 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$48 \p_valid_i + connect { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_muxid \muxid end -attribute \src "libresoc.v:149327.1-149385.10" +attribute \src "ls180.v:4.1-11026.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" -attribute \generator "nMigen" -module \lsd_l - attribute \src "libresoc.v:149328.7-149328.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:149373.3-149381.6" - wire $0\q_int$next[0:0]$7145 - attribute \src "libresoc.v:149371.3-149372.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:149373.3-149381.6" - wire $1\q_int$next[0:0]$7146 - attribute \src "libresoc.v:149350.7-149350.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:149363.17-149363.96" - wire $and$libresoc.v:149363$7135_Y - attribute \src "libresoc.v:149368.17-149368.96" - wire $and$libresoc.v:149368$7140_Y - attribute \src "libresoc.v:149365.18-149365.93" - wire $not$libresoc.v:149365$7137_Y - attribute \src "libresoc.v:149367.17-149367.92" - wire $not$libresoc.v:149367$7139_Y - attribute \src "libresoc.v:149370.17-149370.92" - wire $not$libresoc.v:149370$7142_Y - attribute \src "libresoc.v:149364.18-149364.98" - wire $or$libresoc.v:149364$7136_Y - attribute \src "libresoc.v:149366.18-149366.99" - wire $or$libresoc.v:149366$7138_Y - attribute \src "libresoc.v:149369.17-149369.97" - wire $or$libresoc.v:149369$7141_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:149328.7-149328.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:149363$7135 +module \ls180 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 + attribute \src "ls180.v:10490.1-10494.4" + wire width 3 $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 + attribute \src "ls180.v:10490.1-10494.4" + wire width 25 $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 + attribute \src "ls180.v:10490.1-10494.4" + wire width 25 $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 + attribute \src "ls180.v:10504.1-10508.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 + attribute \src "ls180.v:10504.1-10508.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 + attribute \src "ls180.v:10504.1-10508.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 + attribute \src "ls180.v:10518.1-10522.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 + attribute \src "ls180.v:10518.1-10522.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 + attribute \src "ls180.v:10518.1-10522.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 + attribute \src "ls180.v:10532.1-10536.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 + attribute \src "ls180.v:10532.1-10536.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 + attribute \src "ls180.v:10532.1-10536.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 + attribute \src "ls180.v:10547.1-10551.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 + attribute \src "ls180.v:10547.1-10551.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 + attribute \src "ls180.v:10547.1-10551.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 + attribute \src "ls180.v:10564.1-10568.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 + attribute \src "ls180.v:10564.1-10568.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 + attribute \src "ls180.v:10564.1-10568.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 + attribute \src "ls180.v:10580.1-10584.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 + attribute \src "ls180.v:10580.1-10584.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 + attribute \src "ls180.v:10580.1-10584.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 + attribute \src "ls180.v:10594.1-10598.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 + attribute \src "ls180.v:10594.1-10598.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 + attribute \src "ls180.v:10594.1-10598.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 + attribute \src "ls180.v:3399.1-3492.4" + wire width 3 $0\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:3556.1-3649.4" + wire width 3 $0\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:3713.1-3806.4" + wire width 3 $0\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:3870.1-3963.4" + wire width 3 $0\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:6788.1-6804.4" + wire $0\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:7009.1-7025.4" + wire $0\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:7026.1-7042.4" + wire $0\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:7094.1-7101.4" + wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:7102.1-7109.4" + wire $0\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:7110.1-7117.4" + wire $0\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:7118.1-7125.4" + wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:7126.1-7133.4" + wire $0\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:7134.1-7141.4" + wire $0\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:7142.1-7149.4" + wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:7150.1-7157.4" + wire $0\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:6805.1-6821.4" + wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7158.1-7165.4" + wire $0\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:7166.1-7173.4" + wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:7174.1-7181.4" + wire $0\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:7182.1-7189.4" + wire $0\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:7190.1-7209.4" + wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:7210.1-7229.4" + wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:7230.1-7249.4" + wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:7250.1-7269.4" + wire $0\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:7270.1-7289.4" + wire $0\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:7290.1-7309.4" + wire $0\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:6822.1-6838.4" + wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:7310.1-7329.4" + wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:7330.1-7349.4" + wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:6839.1-6855.4" + wire $0\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:6856.1-6872.4" + wire $0\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:6873.1-6889.4" + wire $0\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:6941.1-6957.4" + wire $0\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:6958.1-6974.4" + wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:6975.1-6991.4" + wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:6992.1-7008.4" + wire $0\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:6890.1-6906.4" + wire $0\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:6907.1-6923.4" + wire $0\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:6924.1-6940.4" + wire $0\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:7043.1-7059.4" + wire $0\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:7060.1-7076.4" + wire $0\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:7077.1-7093.4" + wire $0\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\builder_converter0_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_converter0_state[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\builder_converter1_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_converter1_state[0:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\builder_converter2_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_converter2_state[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\builder_converter_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_converter_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 20 $0\builder_count[19:0] + attribute \src "ls180.v:6028.1-6039.4" + wire $0\builder_error[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_grant[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 14 $0\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:5845.1-5881.4" + wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:5845.1-5881.4" + wire $0\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1990.5-1990.55" + wire $0\builder_libresocsim_converted_interface_ack[0:0] + attribute \src "ls180.v:1986.12-1986.65" + wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] + attribute \src "ls180.v:1994.5-1994.55" + wire $0\builder_libresocsim_converted_interface_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:5845.1-5881.4" + wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:5845.1-5881.4" + wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_libresocsim_we[0:0] + attribute \src "ls180.v:5845.1-5881.4" + wire $0\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:5845.1-5881.4" + wire $0\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:5845.1-5881.4" + wire $0\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1976.12-1976.52" + wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] + attribute \src "ls180.v:1980.5-1980.44" + wire $0\builder_libresocsim_wishbone_cyc[0:0] + attribute \src "ls180.v:5845.1-5881.4" + wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1977.12-1977.54" + wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] + attribute \src "ls180.v:1979.11-1979.50" + wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] + attribute \src "ls180.v:1981.5-1981.44" + wire $0\builder_libresocsim_wishbone_stb[0:0] + attribute \src "ls180.v:1983.5-1983.43" + wire $0\builder_libresocsim_wishbone_we[0:0] + attribute \src "ls180.v:1875.5-1875.27" + wire $0\builder_locked0[0:0] + attribute \src "ls180.v:1876.5-1876.27" + wire $0\builder_locked1[0:0] + attribute \src "ls180.v:1877.5-1877.27" + wire $0\builder_locked2[0:0] + attribute \src "ls180.v:1878.5-1878.27" + wire $0\builder_locked3[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire width 3 $0\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_multiplexer_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:5845.1-5881.4" + wire width 2 $0\builder_next_state[1:0] + attribute \src "ls180.v:3305.1-3335.4" + wire width 2 $0\builder_refresher_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_refresher_state[1:0] + attribute \src "ls180.v:5643.1-5682.4" + wire width 2 $0\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 3 $0\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:5740.1-5776.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:4885.1-4957.4" + wire width 3 $0\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:4730.1-4823.4" + wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:4620.1-4696.4" + wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:6028.1-6039.4" + wire $0\builder_shared_ack[0:0] + attribute \src "ls180.v:6028.1-6039.4" + wire width 32 $0\builder_shared_dat_r[31:0] + attribute \src "ls180.v:5906.1-5921.4" + wire width 13 $0\builder_slave_sel[12:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\builder_slave_sel_r[12:0] + attribute \src "ls180.v:4417.1-4465.4" + wire width 2 $0\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_spimaster0_state[1:0] + attribute \src "ls180.v:4476.1-4524.4" + wire width 2 $0\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_spimaster1_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_state[1:0] + attribute \src "ls180.v:7469.1-7497.4" + wire $0\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:7498.1-7526.4" + wire $0\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:7350.1-7366.4" + wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:7367.1-7383.4" + wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7384.1-7400.4" + wire $0\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:7401.1-7417.4" + wire $0\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:7418.1-7434.4" + wire $0\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:7435.1-7451.4" + wire $0\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:7452.1-7468.4" + wire $0\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:4396.1-4400.4" + wire width 16 $0\gpio_o[15:0] + attribute \src "ls180.v:4401.1-4405.4" + wire width 16 $0\gpio_oe[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_cmd_consumed[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_converter0_counter[0:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_converter0_dat_r[63:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_converter0_skip[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_converter1_counter[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_converter1_dat_r[63:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_converter1_skip[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_converter_counter[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_converter_dat_r[31:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_converter_skip[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 16 $0\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 24 $0\main_dummy[23:0] + attribute \src "ls180.v:1082.12-1082.53" + wire width 16 $0\main_gpiotristateasic0_oe_storage[15:0] + attribute \src "ls180.v:1084.12-1084.54" + wire width 16 $0\main_gpiotristateasic0_out_storage[15:0] + attribute \src "ls180.v:7584.1-7594.4" + wire width 16 $0\main_gpiotristateasic0_status[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_gpiotristateasic1_oe_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_gpiotristateasic1_oe_storage[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_gpiotristateasic1_out_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_gpiotristateasic1_out_storage[15:0] + attribute \src "ls180.v:7595.1-7605.4" + wire width 16 $0\main_gpiotristateasic1_status[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_i2c_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_i2c_storage[2:0] + attribute \src "ls180.v:7626.1-7628.4" + wire $0\main_int_rst[0:0] + attribute \src "ls180.v:1663.11-1663.41" + wire width 2 $0\main_interface0_bus_bte[1:0] + attribute \src "ls180.v:1662.11-1662.41" + wire width 3 $0\main_interface0_bus_cti[2:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:316.5-316.51" + wire $0\main_interface0_converted_interface_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_interface0_ram_bus_ack[0:0] + attribute \src "ls180.v:256.5-256.39" + wire $0\main_interface0_ram_bus_err[0:0] + attribute \src "ls180.v:5702.1-5739.4" + wire width 32 $0\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1754.11-1754.41" + wire width 2 $0\main_interface1_bus_bte[1:0] + attribute \src "ls180.v:1753.11-1753.41" + wire width 3 $0\main_interface1_bus_cti[2:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1746.12-1746.45" + wire width 64 $0\main_interface1_bus_dat_w[63:0] + attribute \src "ls180.v:5702.1-5739.4" + wire width 8 $0\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_interface1_bus_we[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:331.5-331.51" + wire $0\main_interface1_converted_interface_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_interface1_ram_bus_ack[0:0] + attribute \src "ls180.v:271.5-271.39" + wire $0\main_interface1_ram_bus_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_interface2_ram_bus_ack[0:0] + attribute \src "ls180.v:286.5-286.39" + wire $0\main_interface2_ram_bus_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_interface3_ram_bus_ack[0:0] + attribute \src "ls180.v:301.5-301.39" + wire $0\main_interface3_ram_bus_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:75.11-75.52" + wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] + attribute \src "ls180.v:74.11-74.52" + wire width 3 $0\main_libresocsim_libresoc_dbus_cti[2:0] + attribute \src "ls180.v:86.11-86.52" + wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] + attribute \src "ls180.v:85.11-85.52" + wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] + attribute \src "ls180.v:2884.1-2889.4" + wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:115.11-115.55" + wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + attribute \src "ls180.v:114.11-114.55" + wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + attribute \src "ls180.v:2903.1-2949.4" + wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:2891.1-2901.4" + wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:2903.1-2949.4" + wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:2951.1-2961.4" + wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:2963.1-3009.4" + wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:214.5-214.40" + wire $0\main_libresocsim_ram_bus_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_value[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:3072.1-3082.4" + wire width 8 $0\main_libresocsim_we[7:0] + attribute \src "ls180.v:3088.1-3093.4" + wire $0\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire width 30 $0\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:4204.1-4214.4" + wire width 16 $0\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:4216.1-4262.4" + wire width 2 $0\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_litedram_wb_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm0_counter[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm0_period_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm0_width_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm1_counter[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm1_period_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm1_width_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_rddata_en[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 6 $0\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1687.5-1687.41" + wire $0\main_sdblock2mem_fifo_replace[0:0] + attribute \src "ls180.v:5610.1-5617.4" + wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:5643.1-5682.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:5643.1-5682.4" + wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:5643.1-5682.4" + wire $0\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:5643.1-5682.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:5643.1-5682.4" + wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:5643.1-5682.4" + wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:5643.1-5682.4" + wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 10 $0\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 128 $0\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1496.5-1496.34" + wire $0\main_sdcore_cmd_send_w[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:5298.1-5305.4" + wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:5354.1-5361.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:5308.1-5315.4" + wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:5364.1-5371.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:5318.1-5325.4" + wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:5374.1-5381.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:5328.1-5335.4" + wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:5384.1-5391.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:5343.1-5350.4" + wire $0\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1602.5-1602.50" + wire $0\main_sdcore_crc16_checker_source_first[0:0] + attribute \src "ls180.v:5337.1-5342.4" + wire $0\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:5290.1-5295.4" + wire $0\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:5172.1-5179.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:5182.1-5189.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:5192.1-5199.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:5202.1-5209.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1559.5-1559.51" + wire $0\main_sdcore_crc16_inserter_source_first[0:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:5150.1-5157.4" + wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdcore_data_count[31:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_data_done[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_data_error[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:5788.1-5816.4" + wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:5702.1-5739.4" + wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:5740.1-5776.4" + wire $0\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:5740.1-5776.4" + wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:5740.1-5776.4" + wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:5740.1-5776.4" + wire $0\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:5740.1-5776.4" + wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:5740.1-5776.4" + wire $0\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1767.5-1767.45" + wire $0\main_sdmem2block_dma_source_first[0:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:5702.1-5739.4" + wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 6 $0\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1823.5-1823.41" + wire $0\main_sdmem2block_fifo_replace[0:0] + attribute \src "ls180.v:5830.1-5837.4" + wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:4556.1-4584.4" + wire $0\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 9 $0\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 9 $0\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1288.5-1288.53" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + attribute \src "ls180.v:1289.5-1289.52" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1269.5-1269.46" + wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:4730.1-4823.4" + wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1242.5-1242.49" + wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1243.5-1243.48" + wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1244.5-1244.55" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1246.5-1246.57" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1247.5-1247.58" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1249.11-1249.64" + wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1250.5-1250.59" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1255.11-1255.57" + wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1256.5-1256.52" + wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:4730.1-4823.4" + wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:4730.1-4823.4" + wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:4620.1-4696.4" + wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1232.11-1232.57" + wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1233.5-1233.52" + wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 10 $0\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:4991.1-5092.4" + wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1444.5-1444.55" + wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] + attribute \src "ls180.v:1445.5-1445.54" + wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1425.5-1425.48" + wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1396.5-1396.50" + wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1397.5-1397.49" + wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1398.5-1398.56" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1400.5-1400.58" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1401.5-1401.59" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1403.11-1403.65" + wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1404.5-1404.60" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1407.5-1407.51" + wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1408.5-1408.52" + wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1409.11-1409.58" + wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1410.5-1410.53" + wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1417.5-1417.41" + wire $0\main_sdphy_datar_source_first[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:4991.1-5092.4" + wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:4991.1-5092.4" + wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:4885.1-4957.4" + wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1366.5-1366.54" + wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + attribute \src "ls180.v:1367.5-1367.53" + wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1347.5-1347.47" + wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1334.5-1334.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1335.5-1335.49" + wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1336.5-1336.56" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1337.5-1337.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + attribute \src "ls180.v:1338.5-1338.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1339.5-1339.59" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1340.11-1340.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + attribute \src "ls180.v:1341.11-1341.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1342.5-1342.60" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:1332.5-1332.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1321.5-1321.51" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1322.5-1322.52" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4885.1-4957.4" + wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_init_count[7:0] + attribute \src "ls180.v:4586.1-4619.4" + wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1214.5-1214.40" + wire $0\main_sdphy_init_initialize_w[0:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4586.1-4619.4" + wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 4 $0\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_address_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_address_storage[12:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:3361.1-3368.4" + wire $0\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:536.5-536.64" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:519.5-519.67" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:520.5-520.66" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3383.1-3390.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3350.1-3357.4" + wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:4048.1-4056.4" + wire $0\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:578.32-578.76" + wire $0\main_sdram_bankmachine0_trascon_ready[0:0] + attribute \src "ls180.v:576.32-576.75" + wire $0\main_sdram_bankmachine0_trccon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:3518.1-3525.4" + wire $0\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:618.5-618.64" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:601.5-601.67" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:602.5-602.66" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3540.1-3547.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3507.1-3514.4" + wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:4057.1-4065.4" + wire $0\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:660.32-660.76" + wire $0\main_sdram_bankmachine1_trascon_ready[0:0] + attribute \src "ls180.v:658.32-658.75" + wire $0\main_sdram_bankmachine1_trccon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:3675.1-3682.4" + wire $0\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:700.5-700.64" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:683.5-683.67" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:684.5-684.66" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3697.1-3704.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3664.1-3671.4" + wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:4066.1-4074.4" + wire $0\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:742.32-742.76" + wire $0\main_sdram_bankmachine2_trascon_ready[0:0] + attribute \src "ls180.v:740.32-740.75" + wire $0\main_sdram_bankmachine2_trccon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:3832.1-3839.4" + wire $0\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:782.5-782.64" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:765.5-765.67" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:766.5-766.66" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3854.1-3861.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3821.1-3828.4" + wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:4075.1-4083.4" + wire $0\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:824.32-824.76" + wire $0\main_sdram_bankmachine3_trascon_ready[0:0] + attribute \src "ls180.v:822.32-822.75" + wire $0\main_sdram_bankmachine3_trccon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:3997.1-4002.4" + wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:4003.1-4008.4" + wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:4009.1-4014.4" + wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:832.5-832.43" + wire $0\main_sdram_choose_cmd_cmd_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:3983.1-3989.4" + wire width 4 $0\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:830.5-830.48" + wire $0\main_sdram_choose_cmd_want_activates[0:0] + attribute \src "ls180.v:829.5-829.43" + wire $0\main_sdram_choose_cmd_want_cmds[0:0] + attribute \src "ls180.v:827.5-827.44" + wire $0\main_sdram_choose_cmd_want_reads[0:0] + attribute \src "ls180.v:828.5-828.45" + wire $0\main_sdram_choose_cmd_want_writes[0:0] + attribute \src "ls180.v:4030.1-4035.4" + wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:4036.1-4041.4" + wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:4042.1-4047.4" + wire $0\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:4016.1-4022.4" + wire width 4 $0\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:3305.1-3335.4" + wire $0\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:480.5-480.42" + wire $0\main_sdram_cmd_payload_is_read[0:0] + attribute \src "ls180.v:481.5-481.43" + wire $0\main_sdram_cmd_payload_is_write[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:3305.1-3335.4" + wire $0\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:416.5-416.38" + wire $0\main_sdram_command_issue_w[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_command_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 6 $0\main_sdram_command_storage[5:0] + attribute \src "ls180.v:465.5-465.35" + wire $0\main_sdram_dfi_p0_act_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_en0[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_en1[0:0] + attribute \src "ls180.v:4184.1-4197.4" + wire width 16 $0\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:4184.1-4197.4" + wire width 2 $0\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:366.5-366.36" + wire $0\main_sdram_inti_p0_act_n[0:0] + attribute \src "ls180.v:3246.1-3262.4" + wire $0\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:3246.1-3262.4" + wire $0\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:3246.1-3262.4" + wire $0\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 16 $0\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:3246.1-3262.4" + wire $0\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 13 $0\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 2 $0\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 16 $0\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:863.12-863.36" + wire width 13 $0\main_sdram_nop_a[12:0] + attribute \src "ls180.v:864.11-864.35" + wire width 2 $0\main_sdram_nop_ba[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:3305.1-3335.4" + wire $0\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 16 $0\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdram_status[15:0] + attribute \src "ls180.v:866.5-866.31" + wire $0\main_sdram_steerer0[0:0] + attribute \src "ls180.v:867.5-867.31" + wire $0\main_sdram_steerer1[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire width 2 $0\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_storage[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:871.32-871.63" + wire $0\main_sdram_tfawcon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_sdram_time0[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_time1[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 10 $0\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:869.32-869.63" + wire $0\main_sdram_trrdcon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:918.5-918.54" + wire $0\main_socbushandler_converted_interface_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_socbushandler_counter[0:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_socbushandler_skip[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_spimaster11_storage[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster12_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spimaster16_storage[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster17_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster1_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_spimaster1_storage[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster21_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster22_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster23_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster24_re[0:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_spimaster27_count[2:0] + attribute \src "ls180.v:4417.1-4465.4" + wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster2_done[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster3_irq[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spimaster5_miso[7:0] + attribute \src "ls180.v:1105.12-1105.47" + wire width 16 $0\main_spimaster8_clk_divider[15:0] + attribute \src "ls180.v:6553.1-6558.4" + wire $0\main_spimaster9_start[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_spisdcard_count[2:0] + attribute \src "ls180.v:4476.1-4524.4" + wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_done0[0:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_irq[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spisdcard_miso[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:6599.1-6604.4" + wire $0\main_spisdcard_start1[0:0] + attribute \src "ls180.v:3097.1-3107.4" + wire width 8 $0\main_sram0_we[7:0] + attribute \src "ls180.v:3111.1-3121.4" + wire width 8 $0\main_sram1_we[7:0] + attribute \src "ls180.v:3125.1-3135.4" + wire width 8 $0\main_sram2_we[7:0] + attribute \src "ls180.v:3139.1-3149.4" + wire width 8 $0\main_sram3_we[7:0] + attribute \src "ls180.v:4324.1-4328.4" + wire width 2 $0\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:4313.1-4317.4" + wire width 2 $0\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:954.5-954.38" + wire $0\main_uart_phy_source_first[0:0] + attribute \src "ls180.v:955.5-955.37" + wire $0\main_uart_phy_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_uart_phy_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:1081.5-1081.27" + wire $0\main_uart_reset[0:0] + attribute \src "ls180.v:4318.1-4323.4" + wire $0\main_uart_rx_clear[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:1063.5-1063.37" + wire $0\main_uart_rx_fifo_replace[0:0] + attribute \src "ls180.v:4376.1-4383.4" + wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_rx_pending[0:0] + attribute \src "ls180.v:4307.1-4312.4" + wire $0\main_uart_tx_clear[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:1026.5-1026.37" + wire $0\main_uart_tx_fifo_replace[0:0] + attribute \src "ls180.v:1009.5-1009.40" + wire $0\main_uart_tx_fifo_sink_first[0:0] + attribute \src "ls180.v:1010.5-1010.39" + wire $0\main_uart_tx_fifo_sink_last[0:0] + attribute \src "ls180.v:4346.1-4353.4" + wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_tx_pending[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:3023.1-3069.4" + wire width 30 $0\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:3011.1-3021.4" + wire width 32 $0\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:3023.1-3069.4" + wire width 4 $0\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_wb_sdram_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_wdata_consumed[0:0] + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0\memadr[5:0] + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0\memadr_1[5:0] + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0\memadr_2[5:0] + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0\memadr_3[5:0] + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0\memadr_4[5:0] + attribute \src "ls180.v:10490.1-10494.4" + wire width 25 $0\memdat[24:0] + attribute \src "ls180.v:10504.1-10508.4" + wire width 25 $0\memdat_1[24:0] + attribute \src "ls180.v:10518.1-10522.4" + wire width 25 $0\memdat_2[24:0] + attribute \src "ls180.v:10532.1-10536.4" + wire width 25 $0\memdat_3[24:0] + attribute \src "ls180.v:10547.1-10551.4" + wire width 10 $0\memdat_4[9:0] + attribute \src "ls180.v:10553.1-10556.4" + wire width 10 $0\memdat_5[9:0] + attribute \src "ls180.v:10564.1-10568.4" + wire width 10 $0\memdat_6[9:0] + attribute \src "ls180.v:10570.1-10573.4" + wire width 10 $0\memdat_7[9:0] + attribute \src "ls180.v:10580.1-10584.4" + wire width 10 $0\memdat_8[9:0] + attribute \src "ls180.v:10594.1-10598.4" + wire width 10 $0\memdat_9[9:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\pwm[1:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdcard_clk[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdcard_cmd_o[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdcard_cmd_oe[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 4 $0\sdcard_data_o[3:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdcard_data_oe[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 13 $0\sdram_a[12:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 2 $0\sdram_ba[1:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_cas_n[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_cke[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_clock[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_cs_n[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 2 $0\sdram_dm[1:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 16 $0\sdram_dq_o[15:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_dq_oe[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_ras_n[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_we_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spimaster_clk[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spimaster_cs_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spimaster_mosi[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spisdcard_clk[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spisdcard_cs_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spisdcard_mosi[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\uart_tx[0:0] + attribute \src "ls180.v:1854.11-1854.49" + wire width 3 $1\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:1853.11-1853.44" + wire width 3 $1\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:1856.11-1856.49" + wire width 3 $1\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:1855.11-1855.44" + wire width 3 $1\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:1858.11-1858.49" + wire width 3 $1\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:1857.11-1857.44" + wire width 3 $1\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:1860.11-1860.49" + wire width 3 $1\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:1859.11-1859.44" + wire width 3 $1\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:2713.5-2713.41" + wire $1\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:2726.5-2726.42" + wire $1\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:2727.5-2727.42" + wire $1\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:2731.12-2731.50" + wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:2732.5-2732.42" + wire $1\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:2733.5-2733.42" + wire $1\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:2734.12-2734.50" + wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:2735.5-2735.42" + wire $1\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:2736.5-2736.42" + wire $1\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:2737.12-2737.50" + wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:2738.5-2738.42" + wire $1\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:2714.12-2714.49" + wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2739.5-2739.42" + wire $1\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:2740.12-2740.50" + wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:2741.5-2741.42" + wire $1\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:2742.5-2742.42" + wire $1\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:2743.12-2743.50" + wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:2744.12-2744.50" + wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:2745.11-2745.48" + wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:2746.5-2746.42" + wire $1\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:2747.5-2747.42" + wire $1\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:2748.5-2748.42" + wire $1\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:2715.11-2715.47" + wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:2749.11-2749.48" + wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:2750.11-2750.48" + wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:2716.5-2716.41" + wire $1\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2717.5-2717.41" + wire $1\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2718.5-2718.41" + wire $1\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2722.5-2722.41" + wire $1\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:2723.12-2723.49" + wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:2724.11-2724.47" + wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:2725.5-2725.41" + wire $1\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:2719.5-2719.39" + wire $1\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:2720.5-2720.39" + wire $1\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:2721.5-2721.39" + wire $1\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:2728.5-2728.39" + wire $1\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:2729.5-2729.39" + wire $1\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:2730.5-2730.39" + wire $1\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:1840.5-1840.41" + wire $1\builder_converter0_next_state[0:0] + attribute \src "ls180.v:1839.5-1839.36" + wire $1\builder_converter0_state[0:0] + attribute \src "ls180.v:1844.5-1844.41" + wire $1\builder_converter1_next_state[0:0] + attribute \src "ls180.v:1843.5-1843.36" + wire $1\builder_converter1_state[0:0] + attribute \src "ls180.v:1848.5-1848.41" + wire $1\builder_converter2_next_state[0:0] + attribute \src "ls180.v:1847.5-1847.36" + wire $1\builder_converter2_state[0:0] + attribute \src "ls180.v:1885.5-1885.40" + wire $1\builder_converter_next_state[0:0] + attribute \src "ls180.v:1884.5-1884.35" + wire $1\builder_converter_state[0:0] + attribute \src "ls180.v:2013.12-2013.39" + wire width 20 $1\builder_count[19:0] + attribute \src "ls180.v:2010.5-2010.25" + wire $1\builder_error[0:0] + attribute \src "ls180.v:2007.11-2007.31" + wire width 3 $1\builder_grant[2:0] + attribute \src "ls180.v:2017.11-2017.51" + wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2519.11-2519.52" + wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2552.11-2552.52" + wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2593.11-2593.52" + wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2658.11-2658.52" + wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2683.11-2683.52" + wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2058.11-2058.51" + wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2087.11-2087.51" + wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2100.11-2100.51" + wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2141.11-2141.51" + wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2182.11-2182.51" + wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2247.11-2247.51" + wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2380.11-2380.51" + wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2461.11-2461.51" + wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2478.11-2478.51" + wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1972.12-1972.43" + wire width 14 $1\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:2709.12-2709.55" + wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:2710.5-2710.50" + wire $1\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1974.11-1974.43" + wire width 8 $1\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:2707.11-2707.55" + wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:2708.5-2708.52" + wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:1973.5-1973.34" + wire $1\builder_libresocsim_we[0:0] + attribute \src "ls180.v:2711.5-2711.46" + wire $1\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:2712.5-2712.49" + wire $1\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:1982.5-1982.44" + wire $1\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1978.12-1978.54" + wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1862.11-1862.48" + wire width 3 $1\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:1861.11-1861.43" + wire width 3 $1\builder_multiplexer_state[2:0] + attribute \src "ls180.v:2816.32-2816.66" + wire $1\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:2817.32-2817.66" + wire $1\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:2836.32-2836.67" + wire $1\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:2837.32-2837.67" + wire $1\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:2838.32-2838.67" + wire $1\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:2839.32-2839.67" + wire $1\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:2840.32-2840.67" + wire $1\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:2841.32-2841.67" + wire $1\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:2842.32-2842.67" + wire $1\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:2843.32-2843.67" + wire $1\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:2844.32-2844.67" + wire $1\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:2845.32-2845.67" + wire $1\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:2846.32-2846.67" + wire $1\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:2847.32-2847.67" + wire $1\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:2848.32-2848.67" + wire $1\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:2849.32-2849.67" + wire $1\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:2818.32-2818.66" + wire $1\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:2819.32-2819.66" + wire $1\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:2820.32-2820.66" + wire $1\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:2821.32-2821.66" + wire $1\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:2822.32-2822.66" + wire $1\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:2823.32-2823.66" + wire $1\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:2824.32-2824.66" + wire $1\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:2825.32-2825.66" + wire $1\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:2826.32-2826.66" + wire $1\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:2827.32-2827.66" + wire $1\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:2828.32-2828.66" + wire $1\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:2829.32-2829.66" + wire $1\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:2830.32-2830.66" + wire $1\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:2831.32-2831.66" + wire $1\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:2832.32-2832.66" + wire $1\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:2833.32-2833.66" + wire $1\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:2834.32-2834.66" + wire $1\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:2835.32-2835.66" + wire $1\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:1880.5-1880.43" + wire $1\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:1881.5-1881.43" + wire $1\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:1882.5-1882.43" + wire $1\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:1883.5-1883.43" + wire $1\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:1879.5-1879.42" + wire $1\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:2706.11-2706.36" + wire width 2 $1\builder_next_state[1:0] + attribute \src "ls180.v:1852.11-1852.46" + wire width 2 $1\builder_refresher_next_state[1:0] + attribute \src "ls180.v:1851.11-1851.41" + wire width 2 $1\builder_refresher_state[1:0] + attribute \src "ls180.v:1961.11-1961.51" + wire width 2 $1\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:1960.11-1960.46" + wire width 2 $1\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:1929.5-1929.57" + wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:1928.5-1928.52" + wire $1\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:1941.11-1941.47" + wire width 3 $1\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:1940.11-1940.42" + wire width 3 $1\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:1965.5-1965.49" + wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:1964.5-1964.44" + wire $1\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:1969.11-1969.65" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:1968.11-1968.60" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:1917.11-1917.46" + wire width 3 $1\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:1916.11-1916.41" + wire width 3 $1\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:1905.11-1905.52" + wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:1904.11-1904.47" + wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:1901.11-1901.52" + wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:1900.11-1900.47" + wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:1913.5-1913.46" + wire $1\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:1912.5-1912.41" + wire $1\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:1921.11-1921.53" + wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:1920.11-1920.48" + wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:1897.5-1897.46" + wire $1\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:1896.5-1896.41" + wire $1\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:2001.5-2001.30" + wire $1\builder_shared_ack[0:0] + attribute \src "ls180.v:1997.12-1997.40" + wire width 32 $1\builder_shared_dat_r[31:0] + attribute \src "ls180.v:2008.12-2008.37" + wire width 13 $1\builder_slave_sel[12:0] + attribute \src "ls180.v:2009.12-2009.39" + wire width 13 $1\builder_slave_sel_r[12:0] + attribute \src "ls180.v:1889.11-1889.47" + wire width 2 $1\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:1888.11-1888.42" + wire width 2 $1\builder_spimaster0_state[1:0] + attribute \src "ls180.v:1893.11-1893.47" + wire width 2 $1\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:1892.11-1892.42" + wire width 2 $1\builder_spimaster1_state[1:0] + attribute \src "ls180.v:2705.11-2705.31" + wire width 2 $1\builder_state[1:0] + attribute \src "ls180.v:2758.5-2758.39" + wire $1\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:2759.5-2759.39" + wire $1\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:2751.11-2751.47" + wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:2752.12-2752.49" + wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2753.5-2753.41" + wire $1\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:2754.5-2754.41" + wire $1\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2755.5-2755.41" + wire $1\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2756.5-2756.41" + wire $1\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2757.5-2757.41" + wire $1\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:935.5-935.29" + wire $1\main_cmd_consumed[0:0] + attribute \src "ls180.v:318.5-318.35" + wire $1\main_converter0_counter[0:0] + attribute \src "ls180.v:1841.5-1841.57" + wire $1\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1842.5-1842.60" + wire $1\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:320.12-320.41" + wire width 64 $1\main_converter0_dat_r[63:0] + attribute \src "ls180.v:317.5-317.32" + wire $1\main_converter0_skip[0:0] + attribute \src "ls180.v:333.5-333.35" + wire $1\main_converter1_counter[0:0] + attribute \src "ls180.v:1845.5-1845.57" + wire $1\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1846.5-1846.60" + wire $1\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:335.12-335.41" + wire width 64 $1\main_converter1_dat_r[63:0] + attribute \src "ls180.v:332.5-332.32" + wire $1\main_converter1_skip[0:0] + attribute \src "ls180.v:932.5-932.34" + wire $1\main_converter_counter[0:0] + attribute \src "ls180.v:1886.5-1886.55" + wire $1\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:1887.5-1887.58" + wire $1\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:934.12-934.40" + wire width 32 $1\main_converter_dat_r[31:0] + attribute \src "ls180.v:931.5-931.31" + wire $1\main_converter_skip[0:0] + attribute \src "ls180.v:354.12-354.38" + wire width 16 $1\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:355.5-355.36" + wire $1\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:1172.12-1172.30" + wire width 24 $1\main_dummy[23:0] + attribute \src "ls180.v:1083.12-1083.49" + wire width 16 $1\main_gpiotristateasic0_status[15:0] + attribute \src "ls180.v:1089.5-1089.40" + wire $1\main_gpiotristateasic1_oe_re[0:0] + attribute \src "ls180.v:1088.12-1088.53" + wire width 16 $1\main_gpiotristateasic1_oe_storage[15:0] + attribute \src "ls180.v:1093.5-1093.41" + wire $1\main_gpiotristateasic1_out_re[0:0] + attribute \src "ls180.v:1092.12-1092.54" + wire width 16 $1\main_gpiotristateasic1_out_storage[15:0] + attribute \src "ls180.v:1090.12-1090.49" + wire width 16 $1\main_gpiotristateasic1_status[15:0] + attribute \src "ls180.v:1197.5-1197.23" + wire $1\main_i2c_re[0:0] + attribute \src "ls180.v:1196.11-1196.34" + wire width 3 $1\main_i2c_storage[2:0] + attribute \src "ls180.v:339.5-339.24" + wire $1\main_int_rst[0:0] + attribute \src "ls180.v:312.5-312.51" + wire $1\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:252.5-252.39" + wire $1\main_interface0_ram_bus_ack[0:0] + attribute \src "ls180.v:1745.12-1745.43" + wire width 32 $1\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1749.5-1749.35" + wire $1\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1748.11-1748.41" + wire width 8 $1\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:1750.5-1750.35" + wire $1\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:1752.5-1752.34" + wire $1\main_interface1_bus_we[0:0] + attribute \src "ls180.v:327.5-327.51" + wire $1\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:267.5-267.39" + wire $1\main_interface1_ram_bus_ack[0:0] + attribute \src "ls180.v:282.5-282.39" + wire $1\main_interface2_ram_bus_ack[0:0] + attribute \src "ls180.v:297.5-297.39" + wire $1\main_interface3_ram_bus_ack[0:0] + attribute \src "ls180.v:63.12-63.47" + wire width 32 $1\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:224.5-224.34" + wire $1\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:223.5-223.39" + wire $1\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:244.5-244.44" + wire $1\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:243.5-243.49" + wire $1\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:65.12-65.55" + wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:88.12-88.58" + wire width 30 $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:92.5-92.50" + wire $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:89.12-89.60" + wire width 32 $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:91.11-91.56" + wire width 4 $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:93.5-93.50" + wire $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:95.5-95.49" + wire $1\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:97.12-97.58" + wire width 30 $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:101.5-101.50" + wire $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:98.12-98.60" + wire width 32 $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:100.11-100.56" + wire width 4 $1\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:102.5-102.50" + wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:104.5-104.49" + wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:220.5-220.36" + wire $1\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:219.12-219.49" + wire width 32 $1\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:210.5-210.40" + wire $1\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:222.5-222.38" + wire $1\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:221.12-221.51" + wire width 32 $1\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:56.5-56.37" + wire $1\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:55.5-55.42" + wire $1\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:58.5-58.39" + wire $1\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:57.12-57.60" + wire width 32 $1\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:226.5-226.44" + wire $1\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:225.5-225.49" + wire $1\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:245.12-245.42" + wire width 32 $1\main_libresocsim_value[31:0] + attribute \src "ls180.v:227.12-227.49" + wire width 32 $1\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:217.11-217.37" + wire width 8 $1\main_libresocsim_we[7:0] + attribute \src "ls180.v:233.5-233.39" + wire $1\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:234.5-234.45" + wire $1\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:231.5-231.41" + wire $1\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:923.12-923.40" + wire width 30 $1\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:927.5-927.32" + wire $1\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:924.12-924.42" + wire width 16 $1\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:926.11-926.38" + wire width 2 $1\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:928.5-928.32" + wire $1\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:930.5-930.31" + wire $1\main_litedram_wb_we[0:0] + attribute \src "ls180.v:1176.12-1176.37" + wire width 32 $1\main_pwm0_counter[31:0] + attribute \src "ls180.v:1178.5-1178.31" + wire $1\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:1177.5-1177.36" + wire $1\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:1182.5-1182.31" + wire $1\main_pwm0_period_re[0:0] + attribute \src "ls180.v:1181.12-1181.44" + wire width 32 $1\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:1180.5-1180.30" + wire $1\main_pwm0_width_re[0:0] + attribute \src "ls180.v:1179.12-1179.43" + wire width 32 $1\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:1186.12-1186.37" + wire width 32 $1\main_pwm1_counter[31:0] + attribute \src "ls180.v:1188.5-1188.31" + wire $1\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:1187.5-1187.36" + wire $1\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:1192.5-1192.31" + wire $1\main_pwm1_period_re[0:0] + attribute \src "ls180.v:1191.12-1191.44" + wire width 32 $1\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:1190.5-1190.30" + wire $1\main_pwm1_width_re[0:0] + attribute \src "ls180.v:1189.12-1189.43" + wire width 32 $1\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:356.11-356.32" + wire width 3 $1\main_rddata_en[2:0] + attribute \src "ls180.v:1714.11-1714.50" + wire width 3 $1\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:1710.5-1710.51" + wire $1\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:1711.5-1711.50" + wire $1\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:1712.12-1712.66" + wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:1713.11-1713.77" + wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1716.5-1716.49" + wire $1\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:1689.11-1689.47" + wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:1686.11-1686.45" + wire width 6 $1\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:1688.11-1688.47" + wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1690.11-1690.50" + wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1724.12-1724.62" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:1725.12-1725.60" + wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:1722.5-1722.45" + wire $1\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:1732.5-1732.54" + wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:1731.12-1731.67" + wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:1736.5-1736.56" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:1735.5-1735.61" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:1734.5-1734.56" + wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:1733.12-1733.69" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:1740.5-1740.54" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:1739.5-1739.59" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:1742.12-1742.61" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:1962.12-1962.87" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:1963.5-1963.82" + wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:1727.5-1727.57" + wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:1737.5-1737.53" + wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:1506.5-1506.38" + wire $1\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:1505.12-1505.51" + wire width 32 $1\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:1504.5-1504.39" + wire $1\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:1503.11-1503.51" + wire width 10 $1\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:1490.5-1490.39" + wire $1\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:1489.12-1489.52" + wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:1492.5-1492.38" + wire $1\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:1491.12-1491.51" + wire width 32 $1\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:1645.11-1645.39" + wire width 3 $1\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:1946.11-1946.62" + wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:1947.5-1947.59" + wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:1646.5-1646.32" + wire $1\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:1942.5-1942.55" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:1943.5-1943.58" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:1647.5-1647.33" + wire $1\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:1950.5-1950.56" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:1951.5-1951.59" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:1497.13-1497.53" + wire width 128 $1\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:1958.13-1958.76" + wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:1959.5-1959.69" + wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1648.5-1648.35" + wire $1\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:1952.5-1952.58" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:1953.5-1953.61" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:1606.11-1606.47" + wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:1612.5-1612.46" + wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:1611.12-1611.54" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:1607.12-1607.58" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:1619.5-1619.46" + wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:1618.12-1618.54" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:1614.12-1614.58" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:1626.5-1626.46" + wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:1625.12-1625.54" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:1621.12-1621.58" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:1633.5-1633.46" + wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:1632.12-1632.54" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:1628.12-1628.58" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:1635.12-1635.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:1636.12-1636.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:1637.12-1637.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:1638.12-1638.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:1640.12-1640.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:1641.12-1641.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:1642.12-1642.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:1643.12-1643.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:1597.5-1597.48" + wire $1\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:1598.5-1598.47" + wire $1\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:1599.11-1599.61" + wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:1596.5-1596.48" + wire $1\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:1595.5-1595.48" + wire $1\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1600.5-1600.50" + wire $1\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:1605.11-1605.47" + wire width 8 $1\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:1639.5-1639.43" + wire $1\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:1562.11-1562.48" + wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:1938.11-1938.87" + wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:1939.5-1939.84" + wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:1567.12-1567.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:1563.12-1563.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:1574.12-1574.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:1570.12-1570.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:1581.12-1581.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:1577.12-1577.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:1588.12-1588.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:1584.12-1584.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:1591.12-1591.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:1930.12-1930.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:1931.5-1931.88" + wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:1592.12-1592.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:1932.12-1932.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:1933.5-1933.88" + wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:1593.12-1593.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:1934.12-1934.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:1935.5-1935.88" + wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:1594.12-1594.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:1936.12-1936.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:1937.5-1937.88" + wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:1553.5-1553.49" + wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1560.5-1560.50" + wire $1\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:1561.11-1561.64" + wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:1558.5-1558.51" + wire $1\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:1557.5-1557.51" + wire $1\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:1549.11-1549.47" + wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:1507.11-1507.51" + wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:1650.12-1650.42" + wire width 32 $1\main_sdcore_data_count[31:0] + attribute \src "ls180.v:1948.12-1948.65" + wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:1949.5-1949.60" + wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:1651.5-1651.33" + wire $1\main_sdcore_data_done[0:0] + attribute \src "ls180.v:1944.5-1944.56" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:1945.5-1945.59" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:1652.5-1652.34" + wire $1\main_sdcore_data_error[0:0] + attribute \src "ls180.v:1954.5-1954.57" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:1955.5-1955.60" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:1653.5-1653.36" + wire $1\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:1956.5-1956.59" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:1957.5-1957.62" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:1798.11-1798.48" + wire width 3 $1\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:1796.11-1796.64" + wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:1772.5-1772.40" + wire $1\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:1771.12-1771.53" + wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:1770.12-1770.45" + wire width 64 $1\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:1966.12-1966.75" + wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:1967.5-1967.70" + wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1777.5-1777.44" + wire $1\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:1776.5-1776.42" + wire $1\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:1775.5-1775.47" + wire $1\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:1774.5-1774.42" + wire $1\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:1773.12-1773.55" + wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:1780.5-1780.40" + wire $1\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:1779.5-1779.45" + wire $1\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:1784.12-1784.47" + wire width 32 $1\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:1970.12-1970.87" + wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:1971.5-1971.82" + wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:1763.5-1763.42" + wire $1\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:1764.12-1764.61" + wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:1762.5-1762.43" + wire $1\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:1761.5-1761.43" + wire $1\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1768.5-1768.44" + wire $1\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:1769.12-1769.60" + wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:1765.5-1765.45" + wire $1\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:1825.11-1825.47" + wire width 5 $1\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:1822.11-1822.45" + wire width 6 $1\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:1824.11-1824.47" + wire width 5 $1\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1826.11-1826.50" + wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1206.5-1206.35" + wire $1\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:1209.5-1209.35" + wire $1\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:1210.5-1210.36" + wire $1\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:1208.11-1208.41" + wire width 9 $1\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:1204.5-1204.33" + wire $1\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:1203.11-1203.46" + wire width 9 $1\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:1312.5-1312.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:1313.5-1313.48" + wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:1314.11-1314.62" + wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1310.5-1310.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:1297.11-1297.54" + wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1293.5-1293.55" + wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:1294.5-1294.54" + wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:1295.11-1295.68" + wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1296.11-1296.81" + wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1299.5-1299.53" + wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1315.5-1315.38" + wire $1\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:1910.5-1910.66" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:1911.5-1911.69" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:1285.5-1285.36" + wire $1\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:1280.5-1280.53" + wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:1267.11-1267.39" + wire width 8 $1\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:1906.11-1906.67" + wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:1907.5-1907.64" + wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1252.5-1252.48" + wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1253.5-1253.50" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1254.5-1254.51" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1259.5-1259.37" + wire $1\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:1260.11-1260.53" + wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:1258.5-1258.38" + wire $1\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:1257.5-1257.38" + wire $1\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:1263.5-1263.39" + wire $1\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:1264.11-1264.53" + wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:1265.11-1265.55" + wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:1262.5-1262.40" + wire $1\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:1261.5-1261.40" + wire $1\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:1266.12-1266.48" + wire width 32 $1\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:1908.12-1908.71" + wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:1909.5-1909.66" + wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:1239.11-1239.39" + wire width 8 $1\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:1902.11-1902.66" + wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:1903.5-1903.63" + wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:1238.5-1238.32" + wire $1\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:1229.5-1229.48" + wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1230.5-1230.50" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1231.5-1231.51" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1236.5-1236.37" + wire $1\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:1237.11-1237.51" + wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:1235.5-1235.38" + wire $1\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:1234.5-1234.38" + wire $1\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:1423.11-1423.41" + wire width 10 $1\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:1922.11-1922.70" + wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:1923.5-1923.66" + wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:1468.5-1468.51" + wire $1\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:1469.5-1469.50" + wire $1\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:1470.11-1470.64" + wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:1466.5-1466.51" + wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:1453.5-1453.50" + wire $1\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1449.5-1449.57" + wire $1\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:1450.5-1450.56" + wire $1\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:1451.11-1451.70" + wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:1452.11-1452.83" + wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:1455.5-1455.55" + wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1471.5-1471.40" + wire $1\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:1926.5-1926.69" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:1927.5-1927.72" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:1441.5-1441.38" + wire $1\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:1436.5-1436.55" + wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1406.5-1406.49" + wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1413.5-1413.38" + wire $1\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:1414.11-1414.61" + wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:1412.5-1412.39" + wire $1\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:1411.5-1411.39" + wire $1\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1418.5-1418.40" + wire $1\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:1419.11-1419.54" + wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:1420.11-1420.56" + wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:1416.5-1416.41" + wire $1\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:1415.5-1415.41" + wire $1\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:1421.5-1421.33" + wire $1\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:1422.12-1422.49" + wire width 32 $1\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:1924.12-1924.73" + wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:1925.5-1925.68" + wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:1331.11-1331.40" + wire width 8 $1\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:1918.11-1918.61" + wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:1919.5-1919.58" + wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1390.5-1390.50" + wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:1391.5-1391.49" + wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:1392.11-1392.63" + wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1388.5-1388.50" + wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:1375.11-1375.55" + wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1371.5-1371.56" + wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:1372.5-1372.55" + wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:1373.11-1373.69" + wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1374.11-1374.82" + wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1377.5-1377.54" + wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1393.5-1393.39" + wire $1\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:1914.5-1914.66" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:1915.5-1915.69" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:1363.5-1363.37" + wire $1\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:1358.5-1358.54" + wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:1345.5-1345.34" + wire $1\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1320.5-1320.49" + wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1323.11-1323.58" + wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1324.5-1324.53" + wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1327.5-1327.39" + wire $1\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:1328.5-1328.38" + wire $1\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:1329.11-1329.52" + wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:1326.5-1326.39" + wire $1\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:1325.5-1325.39" + wire $1\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:1343.5-1343.34" + wire $1\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:1330.5-1330.33" + wire $1\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:1344.5-1344.34" + wire $1\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:1224.11-1224.39" + wire width 8 $1\main_sdphy_init_count[7:0] + attribute \src "ls180.v:1898.11-1898.66" + wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:1899.5-1899.63" + wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1219.5-1219.48" + wire $1\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1220.5-1220.50" + wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1221.5-1221.51" + wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1222.11-1222.57" + wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1223.5-1223.52" + wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1473.5-1473.35" + wire $1\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:1476.11-1476.42" + wire width 4 $1\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:418.5-418.33" + wire $1\main_sdram_address_re[0:0] + attribute \src "ls180.v:417.12-417.46" + wire width 13 $1\main_sdram_address_storage[12:0] + attribute \src "ls180.v:420.5-420.34" + wire $1\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:419.11-419.45" + wire width 2 $1\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:516.5-516.50" + wire $1\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:538.11-538.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:535.11-535.68" + wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:537.11-537.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:539.11-539.73" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:562.5-562.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:563.5-563.58" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:565.12-565.74" + wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:564.5-564.64" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:560.5-560.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:508.12-508.57" + wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:510.5-510.51" + wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:513.5-513.54" + wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:514.5-514.55" + wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:515.5-515.56" + wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:511.5-511.51" + wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:512.5-512.50" + wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:507.5-507.45" + wire $1\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:506.5-506.45" + wire $1\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:505.5-505.47" + wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:503.5-503.51" + wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:502.5-502.51" + wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:566.12-566.47" + wire width 13 $1\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:570.5-570.45" + wire $1\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:571.5-571.54" + wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:569.5-569.44" + wire $1\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:567.5-567.46" + wire $1\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:574.11-574.55" + wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:573.32-573.76" + wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:598.5-598.50" + wire $1\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:620.11-620.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:617.11-617.68" + wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:619.11-619.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:621.11-621.73" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:644.5-644.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:645.5-645.58" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:647.12-647.74" + wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:646.5-646.64" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:642.5-642.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:590.12-590.57" + wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:592.5-592.51" + wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:595.5-595.54" + wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:596.5-596.55" + wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:597.5-597.56" + wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:593.5-593.51" + wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:594.5-594.50" + wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:589.5-589.45" + wire $1\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:588.5-588.45" + wire $1\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:587.5-587.47" + wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:585.5-585.51" + wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:584.5-584.51" + wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:648.12-648.47" + wire width 13 $1\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:652.5-652.45" + wire $1\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:653.5-653.54" + wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:651.5-651.44" + wire $1\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:649.5-649.46" + wire $1\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:656.11-656.55" + wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:655.32-655.76" + wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:680.5-680.50" + wire $1\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:702.11-702.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:699.11-699.68" + wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:701.11-701.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:703.11-703.73" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:726.5-726.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:727.5-727.58" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:729.12-729.74" + wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:728.5-728.64" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:724.5-724.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:672.12-672.57" + wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:674.5-674.51" + wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:677.5-677.54" + wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:678.5-678.55" + wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:679.5-679.56" + wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:675.5-675.51" + wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:676.5-676.50" + wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:671.5-671.45" + wire $1\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:670.5-670.45" + wire $1\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:669.5-669.47" + wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:667.5-667.51" + wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:666.5-666.51" + wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:730.12-730.47" + wire width 13 $1\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:734.5-734.45" + wire $1\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:735.5-735.54" + wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:733.5-733.44" + wire $1\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:731.5-731.46" + wire $1\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:738.11-738.55" + wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:737.32-737.76" + wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:762.5-762.50" + wire $1\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:784.11-784.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:781.11-781.68" + wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:783.11-783.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:785.11-785.73" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:808.5-808.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:809.5-809.58" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:811.12-811.74" + wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:810.5-810.64" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:806.5-806.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:754.12-754.57" + wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:756.5-756.51" + wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:759.5-759.54" + wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:760.5-760.55" + wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:761.5-761.56" + wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:757.5-757.51" + wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:758.5-758.50" + wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:753.5-753.45" + wire $1\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:752.5-752.45" + wire $1\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:751.5-751.47" + wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:749.5-749.51" + wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:748.5-748.51" + wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:812.12-812.47" + wire width 13 $1\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:816.5-816.45" + wire $1\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:817.5-817.54" + wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:815.5-815.44" + wire $1\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:813.5-813.46" + wire $1\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:820.11-820.55" + wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:819.32-819.76" + wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:835.5-835.49" + wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:836.5-836.49" + wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:837.5-837.48" + wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:843.11-843.45" + wire width 2 $1\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:841.11-841.46" + wire width 4 $1\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:853.5-853.49" + wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:854.5-854.49" + wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:855.5-855.48" + wire $1\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:850.5-850.43" + wire $1\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:861.11-861.45" + wire width 2 $1\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:859.11-859.46" + wire width 4 $1\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:848.5-848.48" + wire $1\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:845.5-845.44" + wire $1\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:846.5-846.45" + wire $1\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:474.5-474.31" + wire $1\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:475.12-475.44" + wire width 13 $1\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:476.11-476.43" + wire width 2 $1\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:477.5-477.38" + wire $1\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:478.5-478.38" + wire $1\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:479.5-479.37" + wire $1\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:473.5-473.32" + wire $1\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:472.5-472.32" + wire $1\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:412.5-412.33" + wire $1\main_sdram_command_re[0:0] + attribute \src "ls180.v:411.11-411.44" + wire width 6 $1\main_sdram_command_storage[5:0] + attribute \src "ls180.v:456.12-456.45" + wire width 13 $1\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:457.11-457.40" + wire width 2 $1\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:458.5-458.35" + wire $1\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:459.5-459.34" + wire $1\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:460.5-460.35" + wire $1\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:469.5-469.39" + wire $1\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:461.5-461.34" + wire $1\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:467.5-467.39" + wire $1\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:880.5-880.26" + wire $1\main_sdram_en0[0:0] + attribute \src "ls180.v:883.5-883.26" + wire $1\main_sdram_en1[0:0] + attribute \src "ls180.v:453.12-453.46" + wire width 16 $1\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:454.11-454.47" + wire width 2 $1\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:359.5-359.36" + wire $1\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:360.5-360.35" + wire $1\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:361.5-361.36" + wire $1\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:371.12-371.45" + wire width 16 $1\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:372.5-372.43" + wire $1\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:362.5-362.35" + wire $1\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:398.5-398.38" + wire $1\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:389.12-389.48" + wire width 13 $1\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:390.11-390.43" + wire width 2 $1\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:391.5-391.38" + wire $1\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:395.5-395.36" + wire $1\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:392.5-392.37" + wire $1\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:396.5-396.36" + wire $1\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:393.5-393.38" + wire $1\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:402.5-402.42" + wire $1\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:397.5-397.40" + wire $1\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:394.5-394.37" + wire $1\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:399.12-399.47" + wire width 16 $1\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:400.5-400.42" + wire $1\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:401.11-401.50" + wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:490.5-490.38" + wire $1\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:489.5-489.38" + wire $1\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:410.5-410.25" + wire $1\main_sdram_re[0:0] + attribute \src "ls180.v:496.5-496.38" + wire $1\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:495.11-495.46" + wire width 4 $1\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:494.5-494.38" + wire $1\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:491.5-491.39" + wire $1\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:387.12-387.46" + wire width 16 $1\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:388.5-388.44" + wire $1\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:423.12-423.37" + wire width 16 $1\main_sdram_status[15:0] + attribute \src "ls180.v:865.11-865.40" + wire width 2 $1\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:409.11-409.36" + wire width 4 $1\main_sdram_storage[3:0] + attribute \src "ls180.v:874.5-874.36" + wire $1\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:873.32-873.63" + wire $1\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:882.11-882.34" + wire width 5 $1\main_sdram_time0[4:0] + attribute \src "ls180.v:885.11-885.34" + wire width 4 $1\main_sdram_time1[3:0] + attribute \src "ls180.v:487.11-487.44" + wire width 10 $1\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:877.11-877.42" + wire width 3 $1\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:876.32-876.63" + wire $1\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:422.5-422.32" + wire $1\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:421.12-421.45" + wire width 16 $1\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:914.5-914.54" + wire $1\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:920.5-920.38" + wire $1\main_socbushandler_counter[0:0] + attribute \src "ls180.v:1849.5-1849.60" + wire $1\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1850.5-1850.63" + wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:922.12-922.44" + wire width 64 $1\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:919.5-919.35" + wire $1\main_socbushandler_skip[0:0] + attribute \src "ls180.v:1108.12-1108.44" + wire width 16 $1\main_spimaster11_storage[15:0] + attribute \src "ls180.v:1109.5-1109.31" + wire $1\main_spimaster12_re[0:0] + attribute \src "ls180.v:1113.11-1113.42" + wire width 8 $1\main_spimaster16_storage[7:0] + attribute \src "ls180.v:1114.5-1114.31" + wire $1\main_spimaster17_re[0:0] + attribute \src "ls180.v:1170.5-1170.30" + wire $1\main_spimaster1_re[0:0] + attribute \src "ls180.v:1169.12-1169.45" + wire width 16 $1\main_spimaster1_storage[15:0] + attribute \src "ls180.v:1118.5-1118.36" + wire $1\main_spimaster21_storage[0:0] + attribute \src "ls180.v:1119.5-1119.31" + wire $1\main_spimaster22_re[0:0] + attribute \src "ls180.v:1120.5-1120.36" + wire $1\main_spimaster23_storage[0:0] + attribute \src "ls180.v:1121.5-1121.31" + wire $1\main_spimaster24_re[0:0] + attribute \src "ls180.v:1122.5-1122.39" + wire $1\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:1123.5-1123.38" + wire $1\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:1124.11-1124.40" + wire width 3 $1\main_spimaster27_count[2:0] + attribute \src "ls180.v:1890.11-1890.62" + wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:1891.5-1891.59" + wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:1125.5-1125.39" + wire $1\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:1126.5-1126.39" + wire $1\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:1099.5-1099.32" + wire $1\main_spimaster2_done[0:0] + attribute \src "ls180.v:1127.12-1127.48" + wire width 16 $1\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:1130.11-1130.44" + wire width 8 $1\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:1131.11-1131.43" + wire width 3 $1\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:1132.11-1132.44" + wire width 8 $1\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:1100.5-1100.31" + wire $1\main_spimaster3_irq[0:0] + attribute \src "ls180.v:1102.11-1102.38" + wire width 8 $1\main_spimaster5_miso[7:0] + attribute \src "ls180.v:1106.5-1106.33" + wire $1\main_spimaster9_start[0:0] + attribute \src "ls180.v:1163.12-1163.47" + wire width 16 $1\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:1158.5-1158.37" + wire $1\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:1145.5-1145.37" + wire $1\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:1144.12-1144.50" + wire width 16 $1\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:1160.11-1160.38" + wire width 3 $1\main_spisdcard_count[2:0] + attribute \src "ls180.v:1894.11-1894.60" + wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:1895.5-1895.57" + wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:1159.5-1159.36" + wire $1\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:1155.5-1155.32" + wire $1\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:1154.5-1154.37" + wire $1\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:1135.5-1135.32" + wire $1\main_spisdcard_done0[0:0] + attribute \src "ls180.v:1136.5-1136.30" + wire $1\main_spisdcard_irq[0:0] + attribute \src "ls180.v:1157.5-1157.38" + wire $1\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:1156.5-1156.43" + wire $1\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:1138.11-1138.37" + wire width 8 $1\main_spisdcard_miso[7:0] + attribute \src "ls180.v:1168.11-1168.42" + wire width 8 $1\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:1162.5-1162.37" + wire $1\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:1166.11-1166.42" + wire width 8 $1\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:1161.5-1161.37" + wire $1\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:1150.5-1150.34" + wire $1\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:1167.11-1167.41" + wire width 3 $1\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:1149.11-1149.45" + wire width 8 $1\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:1142.5-1142.33" + wire $1\main_spisdcard_start1[0:0] + attribute \src "ls180.v:259.11-259.31" + wire width 8 $1\main_sram0_we[7:0] + attribute \src "ls180.v:274.11-274.31" + wire width 8 $1\main_sram1_we[7:0] + attribute \src "ls180.v:289.11-289.31" + wire width 8 $1\main_sram2_we[7:0] + attribute \src "ls180.v:304.11-304.31" + wire width 8 $1\main_sram3_we[7:0] + attribute \src "ls180.v:990.11-990.50" + wire width 2 $1\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:992.5-992.37" + wire $1\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:986.11-986.49" + wire width 2 $1\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:991.11-991.48" + wire width 2 $1\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:958.12-958.54" + wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:948.12-948.54" + wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:941.5-941.28" + wire $1\main_uart_phy_re[0:0] + attribute \src "ls180.v:962.11-962.43" + wire width 4 $1\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:963.5-963.33" + wire $1\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:960.5-960.30" + wire $1\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:961.11-961.38" + wire width 8 $1\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:943.5-943.36" + wire $1\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:956.11-956.51" + wire width 8 $1\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:952.5-952.38" + wire $1\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:940.12-940.47" + wire width 32 $1\main_uart_phy_storage[31:0] + attribute \src "ls180.v:950.11-950.43" + wire width 4 $1\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:951.5-951.33" + wire $1\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:949.11-949.38" + wire width 8 $1\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:957.5-957.39" + wire $1\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:947.5-947.39" + wire $1\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:981.5-981.30" + wire $1\main_uart_rx_clear[0:0] + attribute \src "ls180.v:1065.11-1065.43" + wire width 4 $1\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:1062.11-1062.42" + wire width 5 $1\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:1064.11-1064.43" + wire width 4 $1\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:1055.5-1055.38" + wire $1\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:1066.11-1066.46" + wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:982.5-982.36" + wire $1\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:979.5-979.32" + wire $1\main_uart_rx_pending[0:0] + attribute \src "ls180.v:976.5-976.30" + wire $1\main_uart_tx_clear[0:0] + attribute \src "ls180.v:1028.11-1028.43" + wire width 4 $1\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:1025.11-1025.42" + wire width 5 $1\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:1027.11-1027.43" + wire width 4 $1\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:1018.5-1018.38" + wire $1\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:1029.11-1029.46" + wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:977.5-977.36" + wire $1\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:974.5-974.32" + wire $1\main_uart_tx_pending[0:0] + attribute \src "ls180.v:906.5-906.29" + wire $1\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:900.12-900.37" + wire width 30 $1\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:904.5-904.29" + wire $1\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:901.12-901.39" + wire width 32 $1\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:903.11-903.35" + wire width 4 $1\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:905.5-905.29" + wire $1\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:907.5-907.28" + wire $1\main_wb_sdram_we[0:0] + attribute \src "ls180.v:936.5-936.31" + wire $1\main_wdata_consumed[0:0] + attribute \src "ls180.v:2932.56-2932.86" + wire $add$ls180.v:2932$58_Y + attribute \src "ls180.v:2992.56-2992.86" + wire $add$ls180.v:2992$69_Y + attribute \src "ls180.v:3052.59-3052.92" + wire $add$ls180.v:3052$80_Y + attribute \src "ls180.v:4245.54-4245.83" + wire $add$ls180.v:4245$685_Y + attribute \src "ls180.v:4345.36-4345.89" + wire width 5 $add$ls180.v:4345$731_Y + attribute \src "ls180.v:4375.36-4375.89" + wire width 5 $add$ls180.v:4375$742_Y + attribute \src "ls180.v:4441.54-4441.83" + wire width 3 $add$ls180.v:4441$757_Y + attribute \src "ls180.v:4500.52-4500.79" + wire width 3 $add$ls180.v:4500$765_Y + attribute \src "ls180.v:4604.58-4604.86" + wire width 8 $add$ls180.v:4604$793_Y + attribute \src "ls180.v:4661.58-4661.86" + wire width 8 $add$ls180.v:4661$796_Y + attribute \src "ls180.v:4678.58-4678.86" + wire width 8 $add$ls180.v:4678$798_Y + attribute \src "ls180.v:4771.59-4771.87" + wire width 8 $add$ls180.v:4771$815_Y + attribute \src "ls180.v:4796.59-4796.87" + wire width 8 $add$ls180.v:4796$818_Y + attribute \src "ls180.v:4918.53-4918.82" + wire width 8 $add$ls180.v:4918$835_Y + attribute \src "ls180.v:5029.65-5029.114" + wire width 10 $add$ls180.v:5029$849_Y + attribute \src "ls180.v:5034.62-5034.91" + wire width 10 $add$ls180.v:5034$852_Y + attribute \src "ls180.v:5060.61-5060.90" + wire width 10 $add$ls180.v:5060$855_Y + attribute \src "ls180.v:5264.80-5264.117" + wire width 3 $add$ls180.v:5264$1040_Y + attribute \src "ls180.v:5458.54-5458.82" + wire width 3 $add$ls180.v:5458$1115_Y + attribute \src "ls180.v:5510.55-5510.84" + wire width 32 $add$ls180.v:5510$1125_Y + attribute \src "ls180.v:5536.57-5536.86" + wire width 32 $add$ls180.v:5536$1133_Y + attribute \src "ls180.v:5657.51-5657.134" + wire width 32 $add$ls180.v:5657$1149_Y + attribute \src "ls180.v:5660.77-5660.125" + wire width 32 $add$ls180.v:5660$1151_Y + attribute \src "ls180.v:5753.50-5753.105" + wire width 32 $add$ls180.v:5753$1160_Y + attribute \src "ls180.v:5755.77-5755.111" + wire width 32 $add$ls180.v:5755$1161_Y + attribute \src "ls180.v:7762.36-7762.70" + wire width 32 $add$ls180.v:7762$2602_Y + attribute \src "ls180.v:7863.37-7863.72" + wire width 4 $add$ls180.v:7863$2635_Y + attribute \src "ls180.v:7880.60-7880.119" + wire width 3 $add$ls180.v:7880$2639_Y + attribute \src "ls180.v:7883.60-7883.119" + wire width 3 $add$ls180.v:7883$2640_Y + attribute \src "ls180.v:7887.59-7887.116" + wire width 4 $add$ls180.v:7887$2645_Y + attribute \src "ls180.v:7926.60-7926.119" + wire width 3 $add$ls180.v:7926$2655_Y + attribute \src "ls180.v:7929.60-7929.119" + wire width 3 $add$ls180.v:7929$2656_Y + attribute \src "ls180.v:7933.59-7933.116" + wire width 4 $add$ls180.v:7933$2661_Y + attribute \src "ls180.v:7972.60-7972.119" + wire width 3 $add$ls180.v:7972$2671_Y + attribute \src "ls180.v:7975.60-7975.119" + wire width 3 $add$ls180.v:7975$2672_Y + attribute \src "ls180.v:7979.59-7979.116" + wire width 4 $add$ls180.v:7979$2677_Y + attribute \src "ls180.v:8018.60-8018.119" + wire width 3 $add$ls180.v:8018$2687_Y + attribute \src "ls180.v:8021.60-8021.119" + wire width 3 $add$ls180.v:8021$2688_Y + attribute \src "ls180.v:8025.59-8025.116" + wire width 4 $add$ls180.v:8025$2693_Y + attribute \src "ls180.v:8255.34-8255.66" + wire width 4 $add$ls180.v:8255$2747_Y + attribute \src "ls180.v:8271.73-8271.131" + wire width 33 $add$ls180.v:8271$2750_Y + attribute \src "ls180.v:8284.34-8284.66" + wire width 4 $add$ls180.v:8284$2754_Y + attribute \src "ls180.v:8303.73-8303.131" + wire width 33 $add$ls180.v:8303$2757_Y + attribute \src "ls180.v:8329.33-8329.65" + wire width 4 $add$ls180.v:8329$2765_Y + attribute \src "ls180.v:8332.33-8332.65" + wire width 4 $add$ls180.v:8332$2766_Y + attribute \src "ls180.v:8336.33-8336.64" + wire width 5 $add$ls180.v:8336$2771_Y + attribute \src "ls180.v:8351.33-8351.65" + wire width 4 $add$ls180.v:8351$2776_Y + attribute \src "ls180.v:8354.33-8354.65" + wire width 4 $add$ls180.v:8354$2777_Y + attribute \src "ls180.v:8358.33-8358.64" + wire width 5 $add$ls180.v:8358$2782_Y + attribute \src "ls180.v:8379.35-8379.70" + wire width 16 $add$ls180.v:8379$2784_Y + attribute \src "ls180.v:8414.34-8414.68" + wire width 16 $add$ls180.v:8414$2789_Y + attribute \src "ls180.v:8450.25-8450.49" + wire width 32 $add$ls180.v:8450$2794_Y + attribute \src "ls180.v:8464.25-8464.49" + wire width 32 $add$ls180.v:8464$2798_Y + attribute \src "ls180.v:8478.31-8478.61" + wire width 9 $add$ls180.v:8478$2803_Y + attribute \src "ls180.v:8501.45-8501.88" + wire width 3 $add$ls180.v:8501$2807_Y + attribute \src "ls180.v:8547.71-8547.114" + wire width 4 $add$ls180.v:8547$2813_Y + attribute \src "ls180.v:8582.46-8582.90" + wire width 3 $add$ls180.v:8582$2819_Y + attribute \src "ls180.v:8628.72-8628.116" + wire width 4 $add$ls180.v:8628$2825_Y + attribute \src "ls180.v:8661.47-8661.92" + wire $add$ls180.v:8661$2831_Y + attribute \src "ls180.v:8689.73-8689.118" + wire width 2 $add$ls180.v:8689$2837_Y + attribute \src "ls180.v:8801.39-8801.75" + wire width 4 $add$ls180.v:8801$2850_Y + attribute \src "ls180.v:8862.37-8862.73" + wire width 5 $add$ls180.v:8862$2854_Y + attribute \src "ls180.v:8865.37-8865.73" + wire width 5 $add$ls180.v:8865$2855_Y + attribute \src "ls180.v:8869.36-8869.70" + wire width 6 $add$ls180.v:8869$2860_Y + attribute \src "ls180.v:8884.41-8884.80" + wire width 3 $add$ls180.v:8884$2864_Y + attribute \src "ls180.v:8930.67-8930.106" + wire width 4 $add$ls180.v:8930$2870_Y + attribute \src "ls180.v:8956.39-8956.76" + wire width 3 $add$ls180.v:8956$2872_Y + attribute \src "ls180.v:8960.37-8960.73" + wire width 5 $add$ls180.v:8960$2876_Y + attribute \src "ls180.v:8963.37-8963.73" + wire width 5 $add$ls180.v:8963$2877_Y + attribute \src "ls180.v:8967.36-8967.70" + wire width 6 $add$ls180.v:8967$2882_Y + attribute \src "ls180.v:2926.9-2926.90" + wire $and$ls180.v:2926$53_Y + attribute \src "ls180.v:2944.9-2944.90" + wire $and$ls180.v:2944$60_Y + attribute \src "ls180.v:2986.9-2986.90" + wire $and$ls180.v:2986$64_Y + attribute \src "ls180.v:3004.9-3004.90" + wire $and$ls180.v:3004$71_Y + attribute \src "ls180.v:3046.9-3046.96" + wire $and$ls180.v:3046$75_Y + attribute \src "ls180.v:3064.9-3064.96" + wire $and$ls180.v:3064$82_Y + attribute \src "ls180.v:3074.31-3074.90" + wire $and$ls180.v:3074$84_Y + attribute \src "ls180.v:3074.30-3074.121" + wire $and$ls180.v:3074$85_Y + attribute \src "ls180.v:3074.29-3074.156" + wire $and$ls180.v:3074$86_Y + attribute \src "ls180.v:3075.31-3075.90" + wire $and$ls180.v:3075$87_Y + attribute \src "ls180.v:3075.30-3075.121" + wire $and$ls180.v:3075$88_Y + attribute \src "ls180.v:3075.29-3075.156" + wire $and$ls180.v:3075$89_Y + attribute \src "ls180.v:3076.31-3076.90" + wire $and$ls180.v:3076$90_Y + attribute \src "ls180.v:3076.30-3076.121" + wire $and$ls180.v:3076$91_Y + attribute \src "ls180.v:3076.29-3076.156" + wire $and$ls180.v:3076$92_Y + attribute \src "ls180.v:3077.31-3077.90" + wire $and$ls180.v:3077$93_Y + attribute \src "ls180.v:3077.30-3077.121" + wire $and$ls180.v:3077$94_Y + attribute \src "ls180.v:3077.29-3077.156" + wire $and$ls180.v:3077$95_Y + attribute \src "ls180.v:3078.31-3078.90" + wire $and$ls180.v:3078$96_Y + attribute \src "ls180.v:3078.30-3078.121" + wire $and$ls180.v:3078$97_Y + attribute \src "ls180.v:3078.29-3078.156" + wire $and$ls180.v:3078$98_Y + attribute \src "ls180.v:3079.30-3079.121" + wire $and$ls180.v:3079$100_Y + attribute \src "ls180.v:3079.29-3079.156" + wire $and$ls180.v:3079$101_Y + attribute \src "ls180.v:3079.31-3079.90" + wire $and$ls180.v:3079$99_Y + attribute \src "ls180.v:3080.31-3080.90" + wire $and$ls180.v:3080$102_Y + attribute \src "ls180.v:3080.30-3080.121" + wire $and$ls180.v:3080$103_Y + attribute \src "ls180.v:3080.29-3080.156" + wire $and$ls180.v:3080$104_Y + attribute \src "ls180.v:3081.31-3081.90" + wire $and$ls180.v:3081$105_Y + attribute \src "ls180.v:3081.30-3081.121" + wire $and$ls180.v:3081$106_Y + attribute \src "ls180.v:3081.29-3081.156" + wire $and$ls180.v:3081$107_Y + attribute \src "ls180.v:3090.7-3090.89" + wire $and$ls180.v:3090$110_Y + attribute \src "ls180.v:3095.32-3095.111" + wire $and$ls180.v:3095$111_Y + attribute \src "ls180.v:3099.25-3099.82" + wire $and$ls180.v:3099$113_Y + attribute \src "ls180.v:3099.24-3099.112" + wire $and$ls180.v:3099$114_Y + attribute \src "ls180.v:3099.23-3099.146" + wire $and$ls180.v:3099$115_Y + attribute \src "ls180.v:3100.25-3100.82" + wire $and$ls180.v:3100$116_Y + attribute \src "ls180.v:3100.24-3100.112" + wire $and$ls180.v:3100$117_Y + attribute \src "ls180.v:3100.23-3100.146" + wire $and$ls180.v:3100$118_Y + attribute \src "ls180.v:3101.25-3101.82" + wire $and$ls180.v:3101$119_Y + attribute \src "ls180.v:3101.24-3101.112" + wire $and$ls180.v:3101$120_Y + attribute \src "ls180.v:3101.23-3101.146" + wire $and$ls180.v:3101$121_Y + attribute \src "ls180.v:3102.25-3102.82" + wire $and$ls180.v:3102$122_Y + attribute \src "ls180.v:3102.24-3102.112" + wire $and$ls180.v:3102$123_Y + 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"ls180.v:8888.8-8888.85" + wire $and$ls180.v:8888$2866_Y + attribute \src "ls180.v:8896.8-8896.85" + wire $and$ls180.v:8896$2867_Y + attribute \src "ls180.v:8952.7-8952.88" + wire $and$ls180.v:8952$2871_Y + attribute \src "ls180.v:8959.8-8959.83" + wire $and$ls180.v:8959$2873_Y + attribute \src "ls180.v:8959.7-8959.119" + wire $and$ls180.v:8959$2875_Y + attribute \src "ls180.v:8965.8-8965.83" + wire $and$ls180.v:8965$2878_Y + attribute \src "ls180.v:8965.7-8965.119" + wire $and$ls180.v:8965$2880_Y + attribute \src "ls180.v:2927.30-2927.76" + wire $eq$ls180.v:2927$54_Y + attribute \src "ls180.v:2934.11-2934.42" + wire $eq$ls180.v:2934$59_Y + attribute \src "ls180.v:2987.30-2987.76" + wire $eq$ls180.v:2987$65_Y + attribute \src "ls180.v:2994.11-2994.42" + wire $eq$ls180.v:2994$70_Y + attribute \src "ls180.v:3047.33-3047.58" + wire $eq$ls180.v:3047$76_Y + attribute \src "ls180.v:3054.11-3054.45" + wire $eq$ls180.v:3054$81_Y + attribute \src "ls180.v:3300.34-3300.65" + wire $eq$ls180.v:3300$221_Y + attribute \src "ls180.v:3304.68-3304.102" + wire $eq$ls180.v:3304$224_Y + attribute \src "ls180.v:3348.43-3348.134" + wire $eq$ls180.v:3348$229_Y + attribute \src "ls180.v:3365.47-3365.88" + wire $eq$ls180.v:3365$242_Y + attribute \src "ls180.v:3505.43-3505.134" + wire $eq$ls180.v:3505$259_Y + attribute \src "ls180.v:3522.47-3522.88" + wire $eq$ls180.v:3522$272_Y + attribute \src "ls180.v:3662.43-3662.134" + wire $eq$ls180.v:3662$289_Y + attribute \src "ls180.v:3679.47-3679.88" + wire $eq$ls180.v:3679$302_Y + attribute \src "ls180.v:3819.43-3819.134" + wire $eq$ls180.v:3819$319_Y + attribute \src "ls180.v:3836.47-3836.88" + wire $eq$ls180.v:3836$332_Y + attribute \src "ls180.v:3973.32-3973.56" + wire $eq$ls180.v:3973$379_Y + attribute \src "ls180.v:3974.32-3974.56" + wire $eq$ls180.v:3974$380_Y + attribute \src "ls180.v:3985.339-3985.418" + wire $eq$ls180.v:3985$394_Y + attribute \src "ls180.v:3985.423-3985.504" + wire $eq$ls180.v:3985$395_Y + attribute \src "ls180.v:3986.339-3986.418" + wire $eq$ls180.v:3986$407_Y + attribute \src "ls180.v:3986.423-3986.504" + wire $eq$ls180.v:3986$408_Y + attribute \src "ls180.v:3987.339-3987.418" + wire $eq$ls180.v:3987$420_Y + attribute \src "ls180.v:3987.423-3987.504" + wire $eq$ls180.v:3987$421_Y + attribute \src "ls180.v:3988.339-3988.418" + wire $eq$ls180.v:3988$433_Y + attribute \src "ls180.v:3988.423-3988.504" + wire $eq$ls180.v:3988$434_Y + attribute \src "ls180.v:4018.339-4018.418" + wire $eq$ls180.v:4018$452_Y + attribute \src "ls180.v:4018.423-4018.504" + wire $eq$ls180.v:4018$453_Y + attribute \src "ls180.v:4019.339-4019.418" + wire $eq$ls180.v:4019$465_Y + attribute \src "ls180.v:4019.423-4019.504" + wire $eq$ls180.v:4019$466_Y + attribute \src "ls180.v:4020.339-4020.418" + wire $eq$ls180.v:4020$478_Y + attribute \src "ls180.v:4020.423-4020.504" + wire $eq$ls180.v:4020$479_Y + attribute \src "ls180.v:4021.339-4021.418" + wire $eq$ls180.v:4021$491_Y + attribute \src "ls180.v:4021.423-4021.504" + wire $eq$ls180.v:4021$492_Y + attribute \src "ls180.v:4050.78-4050.113" + wire $eq$ls180.v:4050$501_Y + attribute \src "ls180.v:4053.78-4053.113" + wire $eq$ls180.v:4053$504_Y + attribute \src "ls180.v:4059.78-4059.113" + wire $eq$ls180.v:4059$508_Y + attribute \src "ls180.v:4062.78-4062.113" + wire $eq$ls180.v:4062$511_Y + attribute \src "ls180.v:4068.78-4068.113" + wire $eq$ls180.v:4068$515_Y + attribute \src "ls180.v:4071.78-4071.113" + wire $eq$ls180.v:4071$518_Y + attribute \src "ls180.v:4077.78-4077.113" + wire $eq$ls180.v:4077$522_Y + attribute \src "ls180.v:4080.78-4080.113" + wire $eq$ls180.v:4080$525_Y + attribute \src "ls180.v:4161.42-4161.82" + wire $eq$ls180.v:4161$548_Y + attribute \src "ls180.v:4161.145-4161.178" + wire $eq$ls180.v:4161$549_Y + attribute \src "ls180.v:4161.220-4161.253" + wire $eq$ls180.v:4161$552_Y + attribute \src "ls180.v:4161.295-4161.328" + wire $eq$ls180.v:4161$555_Y + attribute \src "ls180.v:4166.42-4166.82" + wire $eq$ls180.v:4166$564_Y + attribute \src "ls180.v:4166.145-4166.178" + wire $eq$ls180.v:4166$565_Y + attribute \src "ls180.v:4166.220-4166.253" + wire $eq$ls180.v:4166$568_Y + attribute \src "ls180.v:4166.295-4166.328" + wire $eq$ls180.v:4166$571_Y + attribute \src "ls180.v:4171.42-4171.82" + wire $eq$ls180.v:4171$580_Y + attribute \src "ls180.v:4171.145-4171.178" + wire $eq$ls180.v:4171$581_Y + attribute \src "ls180.v:4171.220-4171.253" + wire $eq$ls180.v:4171$584_Y + attribute \src "ls180.v:4171.295-4171.328" + wire $eq$ls180.v:4171$587_Y + attribute \src "ls180.v:4176.42-4176.82" + wire $eq$ls180.v:4176$596_Y + attribute \src "ls180.v:4176.145-4176.178" + wire $eq$ls180.v:4176$597_Y + attribute \src "ls180.v:4176.220-4176.253" + wire $eq$ls180.v:4176$600_Y + attribute \src "ls180.v:4176.295-4176.328" + wire $eq$ls180.v:4176$603_Y + attribute \src "ls180.v:4181.44-4181.77" + wire $eq$ls180.v:4181$612_Y + attribute \src "ls180.v:4181.83-4181.123" + wire $eq$ls180.v:4181$613_Y + attribute \src "ls180.v:4181.186-4181.219" + wire $eq$ls180.v:4181$614_Y + attribute \src "ls180.v:4181.261-4181.294" + wire $eq$ls180.v:4181$617_Y + attribute \src "ls180.v:4181.336-4181.369" + wire $eq$ls180.v:4181$620_Y + attribute \src "ls180.v:4181.418-4181.451" + wire $eq$ls180.v:4181$628_Y + attribute \src "ls180.v:4181.457-4181.497" + wire $eq$ls180.v:4181$629_Y + attribute \src "ls180.v:4181.560-4181.593" + wire $eq$ls180.v:4181$630_Y + attribute \src "ls180.v:4181.635-4181.668" + wire $eq$ls180.v:4181$633_Y + attribute \src "ls180.v:4181.710-4181.743" + wire $eq$ls180.v:4181$636_Y + attribute \src "ls180.v:4181.792-4181.825" + wire $eq$ls180.v:4181$644_Y + attribute \src "ls180.v:4181.831-4181.871" + wire $eq$ls180.v:4181$645_Y + attribute \src "ls180.v:4181.934-4181.967" + wire $eq$ls180.v:4181$646_Y + attribute \src "ls180.v:4181.1009-4181.1042" + wire $eq$ls180.v:4181$649_Y + attribute \src "ls180.v:4181.1084-4181.1117" + wire $eq$ls180.v:4181$652_Y + attribute \src "ls180.v:4181.1166-4181.1199" + wire $eq$ls180.v:4181$660_Y + attribute \src "ls180.v:4181.1205-4181.1245" + wire $eq$ls180.v:4181$661_Y + attribute \src "ls180.v:4181.1308-4181.1341" + wire $eq$ls180.v:4181$662_Y + attribute \src "ls180.v:4181.1383-4181.1416" + wire $eq$ls180.v:4181$665_Y + attribute \src "ls180.v:4181.1458-4181.1491" + wire $eq$ls180.v:4181$668_Y + attribute \src "ls180.v:4240.29-4240.57" + wire $eq$ls180.v:4240$681_Y + attribute \src "ls180.v:4247.11-4247.41" + wire $eq$ls180.v:4247$686_Y + attribute \src "ls180.v:4415.37-4415.111" + wire $eq$ls180.v:4415$753_Y + attribute \src "ls180.v:4416.37-4416.105" + wire $eq$ls180.v:4416$755_Y + attribute \src "ls180.v:4443.10-4443.67" + wire $eq$ls180.v:4443$759_Y + attribute \src "ls180.v:4473.35-4473.108" + wire $eq$ls180.v:4473$761_Y + attribute \src "ls180.v:4474.35-4474.102" + wire $eq$ls180.v:4474$763_Y + attribute \src "ls180.v:4502.10-4502.65" + wire $eq$ls180.v:4502$767_Y + attribute \src "ls180.v:4606.10-4606.40" + wire $eq$ls180.v:4606$794_Y + attribute \src "ls180.v:4663.10-4663.39" + wire $eq$ls180.v:4663$797_Y + attribute \src "ls180.v:4680.10-4680.39" + wire $eq$ls180.v:4680$799_Y + attribute \src "ls180.v:4708.38-4708.88" + wire $eq$ls180.v:4708$801_Y + attribute \src "ls180.v:4758.9-4758.40" + wire $eq$ls180.v:4758$811_Y + attribute \src "ls180.v:4767.36-4767.105" + wire $eq$ls180.v:4767$813_Y + attribute \src "ls180.v:4786.9-4786.40" + wire $eq$ls180.v:4786$817_Y + attribute \src "ls180.v:4798.10-4798.39" + wire $eq$ls180.v:4798$819_Y + attribute \src "ls180.v:4835.39-4835.94" + wire $eq$ls180.v:4835$823_Y + attribute \src "ls180.v:4872.32-4872.89" + wire $eq$ls180.v:4872$832_Y + attribute \src "ls180.v:4920.10-4920.40" + wire $eq$ls180.v:4920$836_Y + attribute \src "ls180.v:4969.40-4969.98" + wire $eq$ls180.v:4969$838_Y + attribute \src "ls180.v:5020.9-5020.41" + wire $eq$ls180.v:5020$848_Y + attribute \src "ls180.v:5029.37-5029.123" + wire $eq$ls180.v:5029$851_Y + attribute \src "ls180.v:5052.9-5052.41" + wire $eq$ls180.v:5052$854_Y + attribute \src "ls180.v:5062.10-5062.41" + wire $eq$ls180.v:5062$856_Y + attribute \src "ls180.v:5231.9-5231.47" + wire $eq$ls180.v:5231$1038_Y + attribute \src "ls180.v:5261.10-5261.48" + wire $eq$ls180.v:5261$1039_Y + attribute \src "ls180.v:5292.10-5292.78" + wire $eq$ls180.v:5292$1044_Y + attribute \src "ls180.v:5292.83-5292.151" + wire $eq$ls180.v:5292$1045_Y + attribute \src "ls180.v:5292.157-5292.225" + wire $eq$ls180.v:5292$1047_Y + attribute \src "ls180.v:5292.231-5292.299" + wire $eq$ls180.v:5292$1049_Y + attribute \src "ls180.v:5300.7-5300.44" + wire $eq$ls180.v:5300$1053_Y + attribute \src "ls180.v:5310.7-5310.44" + wire $eq$ls180.v:5310$1056_Y + attribute \src "ls180.v:5320.7-5320.44" + wire $eq$ls180.v:5320$1059_Y + attribute \src "ls180.v:5330.7-5330.44" + wire $eq$ls180.v:5330$1062_Y + attribute \src "ls180.v:5454.36-5454.64" + wire $eq$ls180.v:5454$1113_Y + attribute \src "ls180.v:5460.10-5460.39" + wire $eq$ls180.v:5460$1116_Y + attribute \src "ls180.v:5461.11-5461.39" + wire $eq$ls180.v:5461$1117_Y + attribute \src "ls180.v:5473.34-5473.63" + wire $eq$ls180.v:5473$1118_Y + attribute \src "ls180.v:5474.9-5474.37" + wire $eq$ls180.v:5474$1119_Y + attribute \src "ls180.v:5481.10-5481.55" + wire $eq$ls180.v:5481$1120_Y + attribute \src "ls180.v:5487.12-5487.41" + wire $eq$ls180.v:5487$1121_Y + attribute \src "ls180.v:5490.13-5490.42" + wire $eq$ls180.v:5490$1122_Y + attribute \src "ls180.v:5512.10-5512.76" + wire $eq$ls180.v:5512$1127_Y + attribute \src "ls180.v:5527.35-5527.101" + wire $eq$ls180.v:5527$1130_Y + attribute \src "ls180.v:5529.10-5529.56" + wire $eq$ls180.v:5529$1131_Y + attribute \src "ls180.v:5538.12-5538.78" + wire $eq$ls180.v:5538$1135_Y + attribute \src "ls180.v:5545.11-5545.57" + wire $eq$ls180.v:5545$1136_Y + attribute \src "ls180.v:5662.10-5662.105" + wire $eq$ls180.v:5662$1153_Y + attribute \src "ls180.v:5752.39-5752.106" + wire $eq$ls180.v:5752$1159_Y + attribute \src "ls180.v:5782.44-5782.82" + wire $eq$ls180.v:5782$1162_Y + attribute \src "ls180.v:5783.43-5783.81" + wire $eq$ls180.v:5783$1163_Y + attribute \src "ls180.v:5895.68-5895.89" + wire $eq$ls180.v:5895$1179_Y + attribute \src "ls180.v:5896.68-5896.89" + wire $eq$ls180.v:5896$1181_Y + attribute \src "ls180.v:5897.71-5897.92" + wire $eq$ls180.v:5897$1183_Y + attribute \src "ls180.v:5898.57-5898.78" + wire $eq$ls180.v:5898$1185_Y + attribute \src "ls180.v:5899.57-5899.78" + wire $eq$ls180.v:5899$1187_Y + attribute \src "ls180.v:5900.68-5900.89" + wire $eq$ls180.v:5900$1189_Y + attribute \src "ls180.v:5901.68-5901.89" + wire $eq$ls180.v:5901$1191_Y + attribute \src "ls180.v:5902.71-5902.92" + wire $eq$ls180.v:5902$1193_Y + attribute \src "ls180.v:5903.57-5903.78" + wire $eq$ls180.v:5903$1195_Y + attribute \src "ls180.v:5904.57-5904.78" + wire $eq$ls180.v:5904$1197_Y + attribute \src "ls180.v:5908.27-5908.59" + wire $eq$ls180.v:5908$1200_Y + attribute \src "ls180.v:5909.27-5909.59" + wire $eq$ls180.v:5909$1201_Y + attribute \src "ls180.v:5910.27-5910.59" + wire $eq$ls180.v:5910$1202_Y + attribute \src "ls180.v:5911.27-5911.59" + wire $eq$ls180.v:5911$1203_Y + attribute \src "ls180.v:5912.27-5912.59" + wire $eq$ls180.v:5912$1204_Y + attribute \src "ls180.v:5913.27-5913.68" + wire $eq$ls180.v:5913$1205_Y + attribute \src "ls180.v:5914.27-5914.65" + wire $eq$ls180.v:5914$1206_Y + attribute \src "ls180.v:5915.27-5915.59" + wire $eq$ls180.v:5915$1207_Y + attribute \src "ls180.v:5916.27-5916.59" + wire $eq$ls180.v:5916$1208_Y + attribute \src "ls180.v:5917.27-5917.59" + wire $eq$ls180.v:5917$1209_Y + attribute \src "ls180.v:5918.28-5918.60" + wire $eq$ls180.v:5918$1210_Y + attribute \src "ls180.v:5919.28-5919.62" + wire $eq$ls180.v:5919$1211_Y + attribute \src "ls180.v:5920.28-5920.66" + wire $eq$ls180.v:5920$1212_Y + attribute \src "ls180.v:6040.24-6040.45" + wire $eq$ls180.v:6040$1279_Y + attribute \src "ls180.v:6041.32-6041.77" + wire $eq$ls180.v:6041$1280_Y + attribute \src "ls180.v:6043.97-6043.141" + wire $eq$ls180.v:6043$1282_Y + attribute \src "ls180.v:6044.100-6044.144" + wire $eq$ls180.v:6044$1286_Y + attribute \src "ls180.v:6046.99-6046.143" + wire $eq$ls180.v:6046$1289_Y + attribute \src "ls180.v:6047.102-6047.146" + wire $eq$ls180.v:6047$1293_Y + attribute \src "ls180.v:6049.99-6049.143" + wire $eq$ls180.v:6049$1296_Y + attribute \src "ls180.v:6050.102-6050.146" + wire $eq$ls180.v:6050$1300_Y + attribute \src "ls180.v:6052.99-6052.143" + wire $eq$ls180.v:6052$1303_Y + attribute \src "ls180.v:6053.102-6053.146" + wire $eq$ls180.v:6053$1307_Y + attribute \src "ls180.v:6055.99-6055.143" + wire $eq$ls180.v:6055$1310_Y + attribute \src "ls180.v:6056.102-6056.146" + wire $eq$ls180.v:6056$1314_Y + attribute \src "ls180.v:6058.102-6058.146" + wire $eq$ls180.v:6058$1317_Y + attribute \src "ls180.v:6059.105-6059.149" + wire $eq$ls180.v:6059$1321_Y + attribute \src "ls180.v:6061.102-6061.146" + wire $eq$ls180.v:6061$1324_Y + attribute \src "ls180.v:6062.105-6062.149" + wire $eq$ls180.v:6062$1328_Y + attribute \src "ls180.v:6064.102-6064.146" + wire $eq$ls180.v:6064$1331_Y + attribute \src "ls180.v:6065.105-6065.149" + wire $eq$ls180.v:6065$1335_Y + attribute \src "ls180.v:6067.102-6067.146" + wire $eq$ls180.v:6067$1338_Y + attribute \src "ls180.v:6068.105-6068.149" + wire $eq$ls180.v:6068$1342_Y + attribute \src "ls180.v:6079.32-6079.77" + wire $eq$ls180.v:6079$1344_Y + attribute \src "ls180.v:6081.94-6081.138" + wire $eq$ls180.v:6081$1346_Y + attribute \src "ls180.v:6082.97-6082.141" + wire $eq$ls180.v:6082$1350_Y + attribute \src "ls180.v:6084.94-6084.138" + wire $eq$ls180.v:6084$1353_Y + attribute \src "ls180.v:6085.97-6085.141" + wire $eq$ls180.v:6085$1357_Y + attribute \src "ls180.v:6087.94-6087.138" + wire $eq$ls180.v:6087$1360_Y + attribute \src "ls180.v:6088.97-6088.141" + wire $eq$ls180.v:6088$1364_Y + attribute \src "ls180.v:6090.94-6090.138" + wire $eq$ls180.v:6090$1367_Y + attribute \src "ls180.v:6091.97-6091.141" + wire $eq$ls180.v:6091$1371_Y + attribute \src "ls180.v:6093.95-6093.139" + wire $eq$ls180.v:6093$1374_Y + attribute \src "ls180.v:6094.98-6094.142" + wire $eq$ls180.v:6094$1378_Y + attribute \src "ls180.v:6096.95-6096.139" + wire $eq$ls180.v:6096$1381_Y + attribute \src "ls180.v:6097.98-6097.142" + wire $eq$ls180.v:6097$1385_Y + attribute \src "ls180.v:6105.32-6105.78" + wire $eq$ls180.v:6105$1387_Y + attribute \src "ls180.v:6107.93-6107.135" + wire $eq$ls180.v:6107$1389_Y + attribute \src "ls180.v:6108.96-6108.138" + wire $eq$ls180.v:6108$1393_Y + attribute \src "ls180.v:6110.92-6110.134" + wire $eq$ls180.v:6110$1396_Y + attribute \src "ls180.v:6111.95-6111.137" + wire $eq$ls180.v:6111$1400_Y + attribute \src "ls180.v:6119.32-6119.78" + wire $eq$ls180.v:6119$1402_Y + attribute \src "ls180.v:6121.98-6121.142" + wire $eq$ls180.v:6121$1404_Y + attribute \src "ls180.v:6122.101-6122.145" + wire $eq$ls180.v:6122$1408_Y + attribute \src "ls180.v:6124.97-6124.141" + wire $eq$ls180.v:6124$1411_Y + attribute \src "ls180.v:6125.100-6125.144" + wire $eq$ls180.v:6125$1415_Y + attribute \src "ls180.v:6127.97-6127.141" + wire $eq$ls180.v:6127$1418_Y + attribute \src "ls180.v:6128.100-6128.144" + wire $eq$ls180.v:6128$1422_Y + attribute \src "ls180.v:6130.97-6130.141" + wire $eq$ls180.v:6130$1425_Y + attribute \src "ls180.v:6131.100-6131.144" + wire $eq$ls180.v:6131$1429_Y + attribute \src "ls180.v:6133.97-6133.141" + wire $eq$ls180.v:6133$1432_Y + attribute \src "ls180.v:6134.100-6134.144" + wire $eq$ls180.v:6134$1436_Y + attribute \src "ls180.v:6136.98-6136.142" + wire $eq$ls180.v:6136$1439_Y + attribute \src "ls180.v:6137.101-6137.145" + wire $eq$ls180.v:6137$1443_Y + attribute \src "ls180.v:6139.98-6139.142" + wire $eq$ls180.v:6139$1446_Y + attribute \src "ls180.v:6140.101-6140.145" + wire $eq$ls180.v:6140$1450_Y + attribute \src "ls180.v:6142.98-6142.142" + wire $eq$ls180.v:6142$1453_Y + attribute \src "ls180.v:6143.101-6143.145" + wire $eq$ls180.v:6143$1457_Y + attribute \src "ls180.v:6145.98-6145.142" + wire $eq$ls180.v:6145$1460_Y + attribute \src "ls180.v:6146.101-6146.145" + wire $eq$ls180.v:6146$1464_Y + attribute \src "ls180.v:6156.32-6156.78" + wire $eq$ls180.v:6156$1466_Y + attribute \src "ls180.v:6158.98-6158.142" + wire $eq$ls180.v:6158$1468_Y + attribute \src "ls180.v:6159.101-6159.145" + wire $eq$ls180.v:6159$1472_Y + attribute \src "ls180.v:6161.97-6161.141" + wire $eq$ls180.v:6161$1475_Y + attribute \src "ls180.v:6162.100-6162.144" + wire $eq$ls180.v:6162$1479_Y + attribute \src "ls180.v:6164.97-6164.141" + wire $eq$ls180.v:6164$1482_Y + attribute \src "ls180.v:6165.100-6165.144" + wire $eq$ls180.v:6165$1486_Y + attribute \src "ls180.v:6167.97-6167.141" + wire $eq$ls180.v:6167$1489_Y + attribute \src "ls180.v:6168.100-6168.144" + wire $eq$ls180.v:6168$1493_Y + attribute \src "ls180.v:6170.97-6170.141" + wire $eq$ls180.v:6170$1496_Y + attribute \src "ls180.v:6171.100-6171.144" + wire $eq$ls180.v:6171$1500_Y + attribute \src "ls180.v:6173.98-6173.142" + wire $eq$ls180.v:6173$1503_Y + attribute \src "ls180.v:6174.101-6174.145" + wire $eq$ls180.v:6174$1507_Y + attribute \src "ls180.v:6176.98-6176.142" + wire $eq$ls180.v:6176$1510_Y + attribute \src "ls180.v:6177.101-6177.145" + wire $eq$ls180.v:6177$1514_Y + attribute \src "ls180.v:6179.98-6179.142" + wire $eq$ls180.v:6179$1517_Y + attribute \src "ls180.v:6180.101-6180.145" + wire $eq$ls180.v:6180$1521_Y + attribute \src "ls180.v:6182.98-6182.142" + wire $eq$ls180.v:6182$1524_Y + attribute \src "ls180.v:6183.101-6183.145" + wire $eq$ls180.v:6183$1528_Y + attribute \src "ls180.v:6193.32-6193.78" + wire $eq$ls180.v:6193$1530_Y + attribute \src "ls180.v:6195.100-6195.144" + wire $eq$ls180.v:6195$1532_Y + attribute \src "ls180.v:6196.103-6196.147" + wire $eq$ls180.v:6196$1536_Y + attribute \src "ls180.v:6198.100-6198.144" + wire $eq$ls180.v:6198$1539_Y + attribute \src "ls180.v:6199.103-6199.147" + wire $eq$ls180.v:6199$1543_Y + attribute \src "ls180.v:6201.100-6201.144" + wire $eq$ls180.v:6201$1546_Y + attribute \src "ls180.v:6202.103-6202.147" + wire $eq$ls180.v:6202$1550_Y + attribute \src "ls180.v:6204.100-6204.144" + wire $eq$ls180.v:6204$1553_Y + attribute \src "ls180.v:6205.103-6205.147" + wire $eq$ls180.v:6205$1557_Y + attribute \src "ls180.v:6207.100-6207.144" + wire $eq$ls180.v:6207$1560_Y + attribute \src "ls180.v:6208.103-6208.147" + wire $eq$ls180.v:6208$1564_Y + attribute \src "ls180.v:6210.100-6210.144" + wire $eq$ls180.v:6210$1567_Y + attribute \src "ls180.v:6211.103-6211.147" + wire $eq$ls180.v:6211$1571_Y + attribute \src "ls180.v:6213.100-6213.144" + wire $eq$ls180.v:6213$1574_Y + attribute \src "ls180.v:6214.103-6214.147" + wire $eq$ls180.v:6214$1578_Y + attribute \src "ls180.v:6216.100-6216.144" + wire $eq$ls180.v:6216$1581_Y + attribute \src "ls180.v:6217.103-6217.147" + wire $eq$ls180.v:6217$1585_Y + attribute \src "ls180.v:6219.102-6219.146" + wire $eq$ls180.v:6219$1588_Y + attribute \src "ls180.v:6220.105-6220.149" + wire $eq$ls180.v:6220$1592_Y + attribute \src "ls180.v:6222.102-6222.146" + wire $eq$ls180.v:6222$1595_Y + attribute \src "ls180.v:6223.105-6223.149" + wire $eq$ls180.v:6223$1599_Y + attribute \src "ls180.v:6225.102-6225.147" + wire $eq$ls180.v:6225$1602_Y + attribute \src "ls180.v:6226.105-6226.150" + wire $eq$ls180.v:6226$1606_Y + attribute \src "ls180.v:6228.102-6228.147" + wire $eq$ls180.v:6228$1609_Y + attribute \src "ls180.v:6229.105-6229.150" + wire $eq$ls180.v:6229$1613_Y + attribute \src "ls180.v:6231.102-6231.147" + wire $eq$ls180.v:6231$1616_Y + attribute \src "ls180.v:6232.105-6232.150" + wire $eq$ls180.v:6232$1620_Y + attribute \src "ls180.v:6234.99-6234.144" + wire $eq$ls180.v:6234$1623_Y + attribute \src "ls180.v:6235.102-6235.147" + wire $eq$ls180.v:6235$1627_Y + attribute \src "ls180.v:6237.100-6237.145" + wire $eq$ls180.v:6237$1630_Y + attribute \src "ls180.v:6238.103-6238.148" + wire $eq$ls180.v:6238$1634_Y + attribute \src "ls180.v:6255.32-6255.78" + wire $eq$ls180.v:6255$1636_Y + attribute \src "ls180.v:6257.104-6257.148" + wire $eq$ls180.v:6257$1638_Y + attribute \src "ls180.v:6258.107-6258.151" + wire $eq$ls180.v:6258$1642_Y + attribute \src "ls180.v:6260.104-6260.148" + wire $eq$ls180.v:6260$1645_Y + attribute \src "ls180.v:6261.107-6261.151" + wire $eq$ls180.v:6261$1649_Y + attribute \src "ls180.v:6263.104-6263.148" + wire $eq$ls180.v:6263$1652_Y + attribute \src "ls180.v:6264.107-6264.151" + wire $eq$ls180.v:6264$1656_Y + attribute \src "ls180.v:6266.104-6266.148" + wire $eq$ls180.v:6266$1659_Y + attribute \src "ls180.v:6267.107-6267.151" + wire $eq$ls180.v:6267$1663_Y + attribute \src "ls180.v:6269.103-6269.147" + wire $eq$ls180.v:6269$1666_Y + attribute \src "ls180.v:6270.106-6270.150" + wire $eq$ls180.v:6270$1670_Y + attribute \src "ls180.v:6272.103-6272.147" + wire $eq$ls180.v:6272$1673_Y + attribute \src "ls180.v:6273.106-6273.150" + wire $eq$ls180.v:6273$1677_Y + attribute \src "ls180.v:6275.103-6275.147" + wire $eq$ls180.v:6275$1680_Y + attribute \src "ls180.v:6276.106-6276.150" + wire $eq$ls180.v:6276$1684_Y + attribute \src "ls180.v:6278.103-6278.147" + wire $eq$ls180.v:6278$1687_Y + attribute \src "ls180.v:6279.106-6279.150" + wire $eq$ls180.v:6279$1691_Y + attribute \src "ls180.v:6281.94-6281.138" + wire $eq$ls180.v:6281$1694_Y + attribute \src "ls180.v:6282.97-6282.141" + wire $eq$ls180.v:6282$1698_Y + attribute \src "ls180.v:6284.105-6284.149" + wire $eq$ls180.v:6284$1701_Y + attribute \src "ls180.v:6285.108-6285.152" + wire $eq$ls180.v:6285$1705_Y + attribute \src "ls180.v:6287.105-6287.150" + wire $eq$ls180.v:6287$1708_Y + attribute \src "ls180.v:6288.108-6288.153" + wire $eq$ls180.v:6288$1712_Y + attribute \src "ls180.v:6290.105-6290.150" + wire $eq$ls180.v:6290$1715_Y + attribute \src "ls180.v:6291.108-6291.153" + wire $eq$ls180.v:6291$1719_Y + attribute \src "ls180.v:6293.105-6293.150" + wire $eq$ls180.v:6293$1722_Y + attribute \src "ls180.v:6294.108-6294.153" + wire $eq$ls180.v:6294$1726_Y + attribute \src "ls180.v:6296.105-6296.150" + wire $eq$ls180.v:6296$1729_Y + attribute \src "ls180.v:6297.108-6297.153" + wire $eq$ls180.v:6297$1733_Y + attribute \src "ls180.v:6299.105-6299.150" + wire $eq$ls180.v:6299$1736_Y + attribute \src "ls180.v:6300.108-6300.153" + wire $eq$ls180.v:6300$1740_Y + attribute \src "ls180.v:6302.104-6302.149" + wire $eq$ls180.v:6302$1743_Y + attribute \src "ls180.v:6303.107-6303.152" + wire $eq$ls180.v:6303$1747_Y + attribute \src "ls180.v:6305.104-6305.149" + wire $eq$ls180.v:6305$1750_Y + attribute \src "ls180.v:6306.107-6306.152" + wire $eq$ls180.v:6306$1754_Y + attribute \src "ls180.v:6308.104-6308.149" + wire $eq$ls180.v:6308$1757_Y + attribute \src "ls180.v:6309.107-6309.152" + wire $eq$ls180.v:6309$1761_Y + attribute \src "ls180.v:6311.104-6311.149" + wire $eq$ls180.v:6311$1764_Y + attribute \src "ls180.v:6312.107-6312.152" + wire $eq$ls180.v:6312$1768_Y + attribute \src "ls180.v:6314.104-6314.149" + wire $eq$ls180.v:6314$1771_Y + attribute \src "ls180.v:6315.107-6315.152" + wire $eq$ls180.v:6315$1775_Y + attribute \src "ls180.v:6317.104-6317.149" + wire $eq$ls180.v:6317$1778_Y + attribute \src "ls180.v:6318.107-6318.152" + wire $eq$ls180.v:6318$1782_Y + attribute \src "ls180.v:6320.104-6320.149" + wire $eq$ls180.v:6320$1785_Y + attribute \src "ls180.v:6321.107-6321.152" + wire $eq$ls180.v:6321$1789_Y + attribute \src "ls180.v:6323.104-6323.149" + wire $eq$ls180.v:6323$1792_Y + attribute \src "ls180.v:6324.107-6324.152" + wire $eq$ls180.v:6324$1796_Y + attribute \src "ls180.v:6326.104-6326.149" + wire $eq$ls180.v:6326$1799_Y + attribute \src "ls180.v:6327.107-6327.152" + wire $eq$ls180.v:6327$1803_Y + attribute \src "ls180.v:6329.104-6329.149" + wire $eq$ls180.v:6329$1806_Y + attribute \src "ls180.v:6330.107-6330.152" + wire $eq$ls180.v:6330$1810_Y + attribute \src "ls180.v:6332.100-6332.145" + wire $eq$ls180.v:6332$1813_Y + attribute \src "ls180.v:6333.103-6333.148" + wire $eq$ls180.v:6333$1817_Y + attribute \src "ls180.v:6335.101-6335.146" + wire $eq$ls180.v:6335$1820_Y + attribute \src "ls180.v:6336.104-6336.149" + wire $eq$ls180.v:6336$1824_Y + attribute \src "ls180.v:6338.104-6338.149" + wire $eq$ls180.v:6338$1827_Y + attribute \src "ls180.v:6339.107-6339.152" + wire $eq$ls180.v:6339$1831_Y + attribute \src "ls180.v:6341.104-6341.149" + wire $eq$ls180.v:6341$1834_Y + attribute \src "ls180.v:6342.107-6342.152" + wire $eq$ls180.v:6342$1838_Y + attribute \src "ls180.v:6344.103-6344.148" + wire $eq$ls180.v:6344$1841_Y + attribute \src "ls180.v:6345.106-6345.151" + wire $eq$ls180.v:6345$1845_Y + attribute \src "ls180.v:6347.103-6347.148" + wire $eq$ls180.v:6347$1848_Y + attribute \src "ls180.v:6348.106-6348.151" + wire $eq$ls180.v:6348$1852_Y + attribute \src "ls180.v:6350.103-6350.148" + wire $eq$ls180.v:6350$1855_Y + attribute \src "ls180.v:6351.106-6351.151" + wire $eq$ls180.v:6351$1859_Y + attribute \src "ls180.v:6353.103-6353.148" + wire $eq$ls180.v:6353$1862_Y + attribute \src "ls180.v:6354.106-6354.151" + wire $eq$ls180.v:6354$1866_Y + attribute \src "ls180.v:6390.32-6390.78" + wire $eq$ls180.v:6390$1868_Y + attribute \src "ls180.v:6392.100-6392.144" + wire $eq$ls180.v:6392$1870_Y + attribute \src "ls180.v:6393.103-6393.147" + wire $eq$ls180.v:6393$1874_Y + attribute \src "ls180.v:6395.100-6395.144" + wire $eq$ls180.v:6395$1877_Y + attribute \src "ls180.v:6396.103-6396.147" + wire $eq$ls180.v:6396$1881_Y + attribute \src "ls180.v:6398.100-6398.144" + wire $eq$ls180.v:6398$1884_Y + attribute \src "ls180.v:6399.103-6399.147" + wire $eq$ls180.v:6399$1888_Y + attribute \src "ls180.v:6401.100-6401.144" + wire $eq$ls180.v:6401$1891_Y + attribute \src "ls180.v:6402.103-6402.147" + wire $eq$ls180.v:6402$1895_Y + attribute \src "ls180.v:6404.100-6404.144" + wire $eq$ls180.v:6404$1898_Y + attribute \src "ls180.v:6405.103-6405.147" + wire $eq$ls180.v:6405$1902_Y + attribute \src "ls180.v:6407.100-6407.144" + wire $eq$ls180.v:6407$1905_Y + attribute \src "ls180.v:6408.103-6408.147" + wire $eq$ls180.v:6408$1909_Y + attribute \src "ls180.v:6410.100-6410.144" + wire $eq$ls180.v:6410$1912_Y + attribute \src "ls180.v:6411.103-6411.147" + wire $eq$ls180.v:6411$1916_Y + attribute \src "ls180.v:6413.100-6413.144" + wire $eq$ls180.v:6413$1919_Y + attribute \src "ls180.v:6414.103-6414.147" + wire $eq$ls180.v:6414$1923_Y + attribute \src "ls180.v:6416.102-6416.146" + wire $eq$ls180.v:6416$1926_Y + attribute \src "ls180.v:6417.105-6417.149" + wire $eq$ls180.v:6417$1930_Y + attribute \src "ls180.v:6419.102-6419.146" + wire $eq$ls180.v:6419$1933_Y + attribute \src "ls180.v:6420.105-6420.149" + wire $eq$ls180.v:6420$1937_Y + attribute \src "ls180.v:6422.102-6422.147" + wire $eq$ls180.v:6422$1940_Y + attribute \src "ls180.v:6423.105-6423.150" + wire $eq$ls180.v:6423$1944_Y + attribute \src "ls180.v:6425.102-6425.147" + wire $eq$ls180.v:6425$1947_Y + attribute \src "ls180.v:6426.105-6426.150" + wire $eq$ls180.v:6426$1951_Y + attribute \src "ls180.v:6428.102-6428.147" + wire $eq$ls180.v:6428$1954_Y + attribute \src "ls180.v:6429.105-6429.150" + wire $eq$ls180.v:6429$1958_Y + attribute \src "ls180.v:6431.99-6431.144" + wire $eq$ls180.v:6431$1961_Y + attribute \src "ls180.v:6432.102-6432.147" + wire $eq$ls180.v:6432$1965_Y + attribute \src "ls180.v:6434.100-6434.145" + wire $eq$ls180.v:6434$1968_Y + attribute \src "ls180.v:6435.103-6435.148" + wire $eq$ls180.v:6435$1972_Y + attribute \src "ls180.v:6437.102-6437.147" + wire $eq$ls180.v:6437$1975_Y + attribute \src "ls180.v:6438.105-6438.150" + wire $eq$ls180.v:6438$1979_Y + attribute \src "ls180.v:6440.102-6440.147" + wire $eq$ls180.v:6440$1982_Y + attribute \src "ls180.v:6441.105-6441.150" + wire $eq$ls180.v:6441$1986_Y + attribute \src "ls180.v:6443.102-6443.147" + wire $eq$ls180.v:6443$1989_Y + attribute \src "ls180.v:6444.105-6444.150" + wire $eq$ls180.v:6444$1993_Y + attribute \src "ls180.v:6446.102-6446.147" + wire $eq$ls180.v:6446$1996_Y + attribute \src "ls180.v:6447.105-6447.150" + wire $eq$ls180.v:6447$2000_Y + attribute \src "ls180.v:6469.32-6469.78" + wire $eq$ls180.v:6469$2002_Y + attribute \src "ls180.v:6471.102-6471.146" + wire $eq$ls180.v:6471$2004_Y + attribute \src "ls180.v:6472.105-6472.149" + wire $eq$ls180.v:6472$2008_Y + attribute \src "ls180.v:6474.107-6474.151" + wire $eq$ls180.v:6474$2011_Y + attribute \src "ls180.v:6475.110-6475.154" + wire $eq$ls180.v:6475$2015_Y + attribute \src "ls180.v:6477.107-6477.151" + wire $eq$ls180.v:6477$2018_Y + attribute \src "ls180.v:6478.110-6478.154" + wire $eq$ls180.v:6478$2022_Y + attribute \src "ls180.v:6480.100-6480.144" + wire $eq$ls180.v:6480$2025_Y + attribute \src "ls180.v:6481.103-6481.147" + wire $eq$ls180.v:6481$2029_Y + attribute \src "ls180.v:6486.32-6486.77" + wire $eq$ls180.v:6486$2031_Y + attribute \src "ls180.v:6488.104-6488.148" + wire $eq$ls180.v:6488$2033_Y + attribute \src "ls180.v:6489.107-6489.151" + wire $eq$ls180.v:6489$2037_Y + attribute \src "ls180.v:6491.108-6491.152" + wire $eq$ls180.v:6491$2040_Y + attribute \src "ls180.v:6492.111-6492.155" + wire $eq$ls180.v:6492$2044_Y + attribute \src "ls180.v:6494.98-6494.142" + wire $eq$ls180.v:6494$2047_Y + attribute \src "ls180.v:6495.101-6495.145" + wire $eq$ls180.v:6495$2051_Y + attribute \src "ls180.v:6497.108-6497.152" + wire $eq$ls180.v:6497$2054_Y + attribute \src "ls180.v:6498.111-6498.155" + wire $eq$ls180.v:6498$2058_Y + attribute \src "ls180.v:6500.108-6500.152" + wire $eq$ls180.v:6500$2061_Y + attribute \src "ls180.v:6501.111-6501.155" + wire $eq$ls180.v:6501$2065_Y + attribute \src "ls180.v:6503.109-6503.153" + wire $eq$ls180.v:6503$2068_Y + attribute \src "ls180.v:6504.112-6504.156" + wire $eq$ls180.v:6504$2072_Y + attribute \src "ls180.v:6506.107-6506.151" + wire $eq$ls180.v:6506$2075_Y + attribute \src "ls180.v:6507.110-6507.154" + wire $eq$ls180.v:6507$2079_Y + attribute \src "ls180.v:6509.107-6509.151" + wire $eq$ls180.v:6509$2082_Y + attribute \src "ls180.v:6510.110-6510.154" + wire $eq$ls180.v:6510$2086_Y + attribute \src "ls180.v:6512.107-6512.151" + wire $eq$ls180.v:6512$2089_Y + attribute \src "ls180.v:6513.110-6513.154" + wire $eq$ls180.v:6513$2093_Y + attribute \src "ls180.v:6515.107-6515.151" + wire $eq$ls180.v:6515$2096_Y + attribute \src "ls180.v:6516.110-6516.154" + wire $eq$ls180.v:6516$2100_Y + attribute \src "ls180.v:6531.33-6531.79" + wire $eq$ls180.v:6531$2102_Y + attribute \src "ls180.v:6533.102-6533.147" + wire $eq$ls180.v:6533$2104_Y + attribute \src "ls180.v:6534.105-6534.150" + wire $eq$ls180.v:6534$2108_Y + attribute \src "ls180.v:6536.102-6536.147" + wire $eq$ls180.v:6536$2111_Y + attribute \src "ls180.v:6537.105-6537.150" + wire $eq$ls180.v:6537$2115_Y + attribute \src "ls180.v:6539.100-6539.145" + wire $eq$ls180.v:6539$2118_Y + attribute \src "ls180.v:6540.103-6540.148" + wire $eq$ls180.v:6540$2122_Y + attribute \src "ls180.v:6542.99-6542.144" + wire $eq$ls180.v:6542$2125_Y + attribute \src "ls180.v:6543.102-6543.147" + wire $eq$ls180.v:6543$2129_Y + attribute \src "ls180.v:6545.98-6545.143" + wire $eq$ls180.v:6545$2132_Y + attribute \src "ls180.v:6546.101-6546.146" + wire $eq$ls180.v:6546$2136_Y + attribute \src "ls180.v:6548.97-6548.142" + wire $eq$ls180.v:6548$2139_Y + attribute \src "ls180.v:6549.100-6549.145" + wire $eq$ls180.v:6549$2143_Y + attribute \src "ls180.v:6551.103-6551.148" + wire $eq$ls180.v:6551$2146_Y + attribute \src "ls180.v:6552.106-6552.151" + wire $eq$ls180.v:6552$2150_Y + attribute \src "ls180.v:6571.33-6571.79" + wire $eq$ls180.v:6571$2153_Y + attribute \src "ls180.v:6573.102-6573.147" + wire $eq$ls180.v:6573$2155_Y + attribute \src "ls180.v:6574.105-6574.150" + wire $eq$ls180.v:6574$2159_Y + attribute \src "ls180.v:6576.102-6576.147" + wire $eq$ls180.v:6576$2162_Y + attribute \src "ls180.v:6577.105-6577.150" + wire $eq$ls180.v:6577$2166_Y + attribute \src "ls180.v:6579.100-6579.145" + wire $eq$ls180.v:6579$2169_Y + attribute \src "ls180.v:6580.103-6580.148" + wire $eq$ls180.v:6580$2173_Y + attribute \src "ls180.v:6582.99-6582.144" + wire $eq$ls180.v:6582$2176_Y + attribute \src "ls180.v:6583.102-6583.147" + wire $eq$ls180.v:6583$2180_Y + attribute \src "ls180.v:6585.98-6585.143" + wire $eq$ls180.v:6585$2183_Y + attribute \src "ls180.v:6586.101-6586.146" + wire $eq$ls180.v:6586$2187_Y + attribute \src "ls180.v:6588.97-6588.142" + wire $eq$ls180.v:6588$2190_Y + attribute \src "ls180.v:6589.100-6589.145" + wire $eq$ls180.v:6589$2194_Y + attribute \src "ls180.v:6591.103-6591.148" + wire $eq$ls180.v:6591$2197_Y + attribute \src "ls180.v:6592.106-6592.151" + wire $eq$ls180.v:6592$2201_Y + attribute \src "ls180.v:6594.106-6594.151" + wire $eq$ls180.v:6594$2204_Y + attribute \src "ls180.v:6595.109-6595.154" + wire $eq$ls180.v:6595$2208_Y + attribute \src "ls180.v:6597.106-6597.151" + wire $eq$ls180.v:6597$2211_Y + attribute \src "ls180.v:6598.109-6598.154" + wire $eq$ls180.v:6598$2215_Y + attribute \src "ls180.v:6619.33-6619.79" + wire $eq$ls180.v:6619$2218_Y + attribute \src "ls180.v:6621.99-6621.144" + wire $eq$ls180.v:6621$2220_Y + attribute \src "ls180.v:6622.102-6622.147" + wire $eq$ls180.v:6622$2224_Y + attribute \src "ls180.v:6624.99-6624.144" + wire $eq$ls180.v:6624$2227_Y + attribute \src "ls180.v:6625.102-6625.147" + wire $eq$ls180.v:6625$2231_Y + attribute \src "ls180.v:6627.99-6627.144" + wire $eq$ls180.v:6627$2234_Y + attribute \src "ls180.v:6628.102-6628.147" + wire $eq$ls180.v:6628$2238_Y + attribute \src "ls180.v:6630.99-6630.144" + wire $eq$ls180.v:6630$2241_Y + attribute \src "ls180.v:6631.102-6631.147" + wire $eq$ls180.v:6631$2245_Y + attribute \src "ls180.v:6633.101-6633.146" + wire $eq$ls180.v:6633$2248_Y + attribute \src "ls180.v:6634.104-6634.149" + wire $eq$ls180.v:6634$2252_Y + attribute \src "ls180.v:6636.101-6636.146" + wire $eq$ls180.v:6636$2255_Y + attribute \src "ls180.v:6637.104-6637.149" + wire $eq$ls180.v:6637$2259_Y + attribute \src "ls180.v:6639.101-6639.146" + wire $eq$ls180.v:6639$2262_Y + attribute \src "ls180.v:6640.104-6640.149" + wire $eq$ls180.v:6640$2266_Y + attribute \src "ls180.v:6642.101-6642.146" + wire $eq$ls180.v:6642$2269_Y + attribute \src "ls180.v:6643.104-6643.149" + wire $eq$ls180.v:6643$2273_Y + attribute \src "ls180.v:6645.97-6645.142" + wire $eq$ls180.v:6645$2276_Y + attribute \src "ls180.v:6646.100-6646.145" + wire $eq$ls180.v:6646$2280_Y + attribute \src "ls180.v:6648.107-6648.152" + wire $eq$ls180.v:6648$2283_Y + attribute \src "ls180.v:6649.110-6649.155" + wire $eq$ls180.v:6649$2287_Y + attribute \src "ls180.v:6651.100-6651.146" + wire $eq$ls180.v:6651$2290_Y + attribute \src "ls180.v:6652.103-6652.149" + wire $eq$ls180.v:6652$2294_Y + attribute \src "ls180.v:6654.100-6654.146" + wire $eq$ls180.v:6654$2297_Y + attribute \src "ls180.v:6655.103-6655.149" + wire $eq$ls180.v:6655$2301_Y + attribute \src "ls180.v:6657.100-6657.146" + wire $eq$ls180.v:6657$2304_Y + attribute \src "ls180.v:6658.103-6658.149" + wire $eq$ls180.v:6658$2308_Y + attribute \src "ls180.v:6660.100-6660.146" + wire $eq$ls180.v:6660$2311_Y + attribute \src "ls180.v:6661.103-6661.149" + wire $eq$ls180.v:6661$2315_Y + attribute \src "ls180.v:6663.112-6663.158" + wire $eq$ls180.v:6663$2318_Y + attribute \src "ls180.v:6664.115-6664.161" + wire $eq$ls180.v:6664$2322_Y + attribute \src "ls180.v:6666.113-6666.159" + wire $eq$ls180.v:6666$2325_Y + attribute \src "ls180.v:6667.116-6667.162" + wire $eq$ls180.v:6667$2329_Y + attribute \src "ls180.v:6669.104-6669.150" + wire $eq$ls180.v:6669$2332_Y + attribute \src "ls180.v:6670.107-6670.153" + wire $eq$ls180.v:6670$2336_Y + attribute \src "ls180.v:6687.33-6687.79" + wire $eq$ls180.v:6687$2338_Y + attribute \src "ls180.v:6689.90-6689.135" + wire $eq$ls180.v:6689$2340_Y + attribute \src "ls180.v:6690.93-6690.138" + wire $eq$ls180.v:6690$2344_Y + attribute \src "ls180.v:6692.100-6692.145" + wire $eq$ls180.v:6692$2347_Y + attribute \src "ls180.v:6693.103-6693.148" + wire $eq$ls180.v:6693$2351_Y + attribute \src "ls180.v:6695.101-6695.146" + wire $eq$ls180.v:6695$2354_Y + attribute \src "ls180.v:6696.104-6696.149" + wire $eq$ls180.v:6696$2358_Y + attribute \src "ls180.v:6698.105-6698.150" + wire $eq$ls180.v:6698$2361_Y + attribute \src "ls180.v:6699.108-6699.153" + wire $eq$ls180.v:6699$2365_Y + attribute \src "ls180.v:6701.106-6701.151" + wire $eq$ls180.v:6701$2368_Y + attribute \src "ls180.v:6702.109-6702.154" + wire $eq$ls180.v:6702$2372_Y + attribute \src "ls180.v:6704.104-6704.149" + wire $eq$ls180.v:6704$2375_Y + attribute \src "ls180.v:6705.107-6705.152" + wire $eq$ls180.v:6705$2379_Y + attribute \src "ls180.v:6707.101-6707.146" + wire $eq$ls180.v:6707$2382_Y + attribute \src "ls180.v:6708.104-6708.149" + wire $eq$ls180.v:6708$2386_Y + attribute \src "ls180.v:6710.100-6710.145" + wire $eq$ls180.v:6710$2389_Y + attribute \src "ls180.v:6711.103-6711.148" + wire $eq$ls180.v:6711$2393_Y + attribute \src "ls180.v:6721.33-6721.79" + wire $eq$ls180.v:6721$2395_Y + attribute \src "ls180.v:6723.106-6723.151" + wire $eq$ls180.v:6723$2397_Y + attribute \src "ls180.v:6724.109-6724.154" + wire $eq$ls180.v:6724$2401_Y + attribute \src "ls180.v:6726.106-6726.151" + wire $eq$ls180.v:6726$2404_Y + attribute \src "ls180.v:6727.109-6727.154" + wire $eq$ls180.v:6727$2408_Y + attribute \src "ls180.v:6729.106-6729.151" + wire $eq$ls180.v:6729$2411_Y + attribute \src "ls180.v:6730.109-6730.154" + wire $eq$ls180.v:6730$2415_Y + attribute \src "ls180.v:6732.106-6732.151" + wire $eq$ls180.v:6732$2418_Y + attribute \src "ls180.v:6733.109-6733.154" + wire $eq$ls180.v:6733$2422_Y + attribute \src "ls180.v:7114.41-7114.81" + wire $eq$ls180.v:7114$2459_Y + attribute \src "ls180.v:7114.144-7114.177" + wire $eq$ls180.v:7114$2460_Y + attribute \src "ls180.v:7114.219-7114.252" + wire $eq$ls180.v:7114$2463_Y + attribute \src "ls180.v:7114.294-7114.327" + wire $eq$ls180.v:7114$2466_Y + attribute \src "ls180.v:7138.41-7138.81" + wire $eq$ls180.v:7138$2475_Y + attribute \src "ls180.v:7138.144-7138.177" + wire $eq$ls180.v:7138$2476_Y + attribute \src "ls180.v:7138.219-7138.252" + wire $eq$ls180.v:7138$2479_Y + attribute \src "ls180.v:7138.294-7138.327" + wire $eq$ls180.v:7138$2482_Y + attribute \src "ls180.v:7162.41-7162.81" + wire $eq$ls180.v:7162$2491_Y + attribute \src "ls180.v:7162.144-7162.177" + wire $eq$ls180.v:7162$2492_Y + attribute \src "ls180.v:7162.219-7162.252" + wire $eq$ls180.v:7162$2495_Y + attribute \src "ls180.v:7162.294-7162.327" + wire $eq$ls180.v:7162$2498_Y + attribute \src "ls180.v:7186.41-7186.81" + wire $eq$ls180.v:7186$2507_Y + attribute \src "ls180.v:7186.144-7186.177" + wire $eq$ls180.v:7186$2508_Y + attribute \src "ls180.v:7186.219-7186.252" + wire $eq$ls180.v:7186$2511_Y + attribute \src "ls180.v:7186.294-7186.327" + wire $eq$ls180.v:7186$2514_Y + attribute \src "ls180.v:7770.8-7770.38" + wire $eq$ls180.v:7770$2606_Y + attribute \src "ls180.v:7817.8-7817.42" + wire $eq$ls180.v:7817$2626_Y + attribute \src "ls180.v:7837.38-7837.74" + wire $eq$ls180.v:7837$2629_Y + attribute \src "ls180.v:7844.7-7844.43" + wire $eq$ls180.v:7844$2631_Y + attribute \src "ls180.v:7851.7-7851.43" + wire $eq$ls180.v:7851$2632_Y + attribute \src "ls180.v:7859.7-7859.43" + wire $eq$ls180.v:7859$2633_Y + attribute \src "ls180.v:7911.9-7911.54" + wire $eq$ls180.v:7911$2651_Y + attribute \src "ls180.v:7957.9-7957.54" + wire $eq$ls180.v:7957$2667_Y + attribute \src "ls180.v:8003.9-8003.54" + wire $eq$ls180.v:8003$2683_Y + attribute \src "ls180.v:8049.9-8049.54" + wire $eq$ls180.v:8049$2699_Y + attribute \src "ls180.v:8199.9-8199.41" + wire $eq$ls180.v:8199$2711_Y + attribute \src "ls180.v:8214.9-8214.41" + wire $eq$ls180.v:8214$2714_Y + attribute \src "ls180.v:8220.49-8220.82" + wire $eq$ls180.v:8220$2715_Y + attribute \src "ls180.v:8220.131-8220.164" + wire $eq$ls180.v:8220$2718_Y + attribute \src "ls180.v:8220.213-8220.246" + wire $eq$ls180.v:8220$2721_Y + attribute \src "ls180.v:8220.295-8220.328" + wire $eq$ls180.v:8220$2724_Y + attribute \src "ls180.v:8221.50-8221.83" + wire $eq$ls180.v:8221$2727_Y + attribute \src "ls180.v:8221.132-8221.165" + wire $eq$ls180.v:8221$2730_Y + attribute \src "ls180.v:8221.214-8221.247" + wire $eq$ls180.v:8221$2733_Y + attribute \src "ls180.v:8221.296-8221.329" + wire $eq$ls180.v:8221$2736_Y + attribute \src "ls180.v:8256.9-8256.42" + wire $eq$ls180.v:8256$2748_Y + attribute \src "ls180.v:8259.10-8259.43" + wire $eq$ls180.v:8259$2749_Y + attribute \src "ls180.v:8285.9-8285.42" + wire $eq$ls180.v:8285$2755_Y + attribute \src "ls180.v:8290.10-8290.43" + wire $eq$ls180.v:8290$2756_Y + attribute \src "ls180.v:8497.9-8497.53" + wire $eq$ls180.v:8497$2805_Y + attribute \src "ls180.v:8578.9-8578.54" + wire $eq$ls180.v:8578$2817_Y + attribute \src "ls180.v:8657.9-8657.55" + wire $eq$ls180.v:8657$2829_Y + attribute \src "ls180.v:8880.9-8880.49" + wire $eq$ls180.v:8880$2862_Y + attribute \src "ls180.v:8456.8-8456.54" + wire $ge$ls180.v:8456$2797_Y + attribute \src "ls180.v:8470.8-8470.54" + wire $ge$ls180.v:8470$2801_Y + attribute \src "ls180.v:5339.47-5339.83" + wire $gt$ls180.v:5339$1064_Y + attribute \src "ls180.v:5345.7-5345.43" + wire $lt$ls180.v:5345$1067_Y + attribute \src "ls180.v:8451.8-8451.43" + wire $lt$ls180.v:8451$2795_Y + attribute \src "ls180.v:8465.8-8465.43" + wire $lt$ls180.v:8465$2799_Y + attribute \src "ls180.v:10370.33-10370.36" + wire width 64 $memrd$\mem$ls180.v:10370$2916_DATA + attribute \src "ls180.v:10398.27-10398.32" + wire width 64 $memrd$\mem_1$ls180.v:10398$2942_DATA + attribute \src "ls180.v:10426.27-10426.32" + wire width 64 $memrd$\mem_2$ls180.v:10426$2968_DATA + attribute \src "ls180.v:10454.27-10454.32" + wire width 64 $memrd$\mem_3$ls180.v:10454$2994_DATA + attribute \src "ls180.v:10482.27-10482.32" + wire width 64 $memrd$\mem_4$ls180.v:10482$3020_DATA + attribute \src "ls180.v:10493.12-10493.19" + wire width 25 $memrd$\storage$ls180.v:10493$3025_DATA + attribute \src "ls180.v:10500.68-10500.75" + wire width 25 $memrd$\storage$ls180.v:10500$3027_DATA + attribute \src "ls180.v:10507.14-10507.23" + wire width 25 $memrd$\storage_1$ls180.v:10507$3032_DATA + attribute \src "ls180.v:10514.68-10514.77" + wire width 25 $memrd$\storage_1$ls180.v:10514$3034_DATA + attribute \src "ls180.v:10521.14-10521.23" + wire width 25 $memrd$\storage_2$ls180.v:10521$3039_DATA + attribute \src "ls180.v:10528.68-10528.77" + wire width 25 $memrd$\storage_2$ls180.v:10528$3041_DATA + attribute \src "ls180.v:10535.14-10535.23" + wire width 25 $memrd$\storage_3$ls180.v:10535$3046_DATA + attribute \src "ls180.v:10542.68-10542.77" + wire width 25 $memrd$\storage_3$ls180.v:10542$3048_DATA + attribute \src "ls180.v:10550.14-10550.23" + wire width 10 $memrd$\storage_4$ls180.v:10550$3053_DATA + attribute \src "ls180.v:10555.15-10555.24" + wire width 10 $memrd$\storage_4$ls180.v:10555$3055_DATA + attribute \src "ls180.v:10567.14-10567.23" + wire width 10 $memrd$\storage_5$ls180.v:10567$3060_DATA + attribute \src "ls180.v:10572.15-10572.24" + wire width 10 $memrd$\storage_5$ls180.v:10572$3062_DATA + attribute \src "ls180.v:10583.14-10583.23" + wire width 10 $memrd$\storage_6$ls180.v:10583$3067_DATA + attribute \src "ls180.v:10590.45-10590.54" + wire width 10 $memrd$\storage_6$ls180.v:10590$3069_DATA + attribute \src "ls180.v:10597.14-10597.23" + wire width 10 $memrd$\storage_7$ls180.v:10597$3074_DATA + attribute \src "ls180.v:10604.45-10604.54" + wire width 10 $memrd$\storage_7$ls180.v:10604$3076_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10352$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10352$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10352$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10354$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10354$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10354$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10356$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10356$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10356$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10358$4_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10358$4_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10358$4_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10360$5_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10360$5_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10360$5_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10362$6_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10362$6_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10362$6_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10364$7_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10364$7_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10364$7_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10366$8_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10366$8_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10366$8_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10380$9_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10380$9_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10380$9_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10382$10_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10382$10_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10382$10_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10384$11_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10384$11_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10384$11_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10386$12_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10386$12_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10386$12_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10388$13_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10388$13_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10388$13_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10390$14_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10390$14_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10390$14_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10392$15_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10392$15_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10392$15_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10394$16_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10394$16_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10394$16_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10408$17_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10408$17_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10408$17_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10410$18_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10410$18_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10410$18_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10412$19_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10412$19_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10412$19_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10414$20_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10414$20_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10414$20_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10416$21_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10416$21_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10416$21_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10418$22_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10418$22_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10418$22_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10420$23_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10420$23_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10420$23_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10422$24_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10422$24_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10422$24_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10436$25_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10436$25_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10436$25_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10438$26_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10438$26_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10438$26_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10440$27_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10440$27_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10440$27_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10442$28_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10442$28_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10442$28_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10444$29_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10444$29_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10444$29_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10446$30_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10446$30_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10446$30_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10448$31_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10448$31_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10448$31_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10450$32_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10450$32_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10450$32_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10464$33_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10464$33_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10464$33_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10466$34_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10466$34_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10466$34_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10468$35_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10468$35_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10468$35_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10470$36_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10470$36_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10470$36_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10472$37_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10472$37_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10472$37_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10474$38_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10474$38_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10474$38_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10476$39_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10476$39_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10476$39_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10478$40_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10478$40_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10478$40_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage$ls180.v:10492$41_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10492$41_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10492$41_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_1$ls180.v:10506$42_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10506$42_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10506$42_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_2$ls180.v:10520$43_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10520$43_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10520$43_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_3$ls180.v:10534$44_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10534$44_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10534$44_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_4$ls180.v:10549$45_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10549$45_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10549$45_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_5$ls180.v:10566$46_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10566$46_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10566$46_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_6$ls180.v:10582$47_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10582$47_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10582$47_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_7$ls180.v:10596$48_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10596$48_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10596$48_EN + attribute \src "ls180.v:3086.41-3086.71" + wire $ne$ls180.v:3086$108_Y + attribute \src "ls180.v:3303.70-3303.104" + wire $ne$ls180.v:3303$222_Y + attribute \src "ls180.v:3364.8-3364.142" + wire $ne$ls180.v:3364$241_Y + attribute \src "ls180.v:3396.75-3396.133" + wire $ne$ls180.v:3396$248_Y + attribute \src "ls180.v:3397.75-3397.133" + wire $ne$ls180.v:3397$249_Y + attribute \src "ls180.v:3521.8-3521.142" + wire $ne$ls180.v:3521$271_Y + attribute \src "ls180.v:3553.75-3553.133" + wire $ne$ls180.v:3553$278_Y + attribute \src "ls180.v:3554.75-3554.133" + wire $ne$ls180.v:3554$279_Y + attribute \src "ls180.v:3678.8-3678.142" + wire $ne$ls180.v:3678$301_Y + attribute \src "ls180.v:3710.75-3710.133" + wire $ne$ls180.v:3710$308_Y + attribute \src "ls180.v:3711.75-3711.133" + wire $ne$ls180.v:3711$309_Y + attribute \src "ls180.v:3835.8-3835.142" + wire $ne$ls180.v:3835$331_Y + attribute \src "ls180.v:3867.75-3867.133" + wire $ne$ls180.v:3867$338_Y + attribute \src "ls180.v:3868.75-3868.133" + wire $ne$ls180.v:3868$339_Y + attribute \src "ls180.v:4360.47-4360.80" + wire $ne$ls180.v:4360$737_Y + attribute \src "ls180.v:4361.47-4361.79" + wire $ne$ls180.v:4361$738_Y + attribute \src "ls180.v:4390.47-4390.80" + wire $ne$ls180.v:4390$748_Y + attribute \src "ls180.v:4391.47-4391.79" + wire $ne$ls180.v:4391$749_Y + attribute \src "ls180.v:4871.32-4871.89" + wire $ne$ls180.v:4871$831_Y + attribute \src "ls180.v:5518.10-5518.56" + wire $ne$ls180.v:5518$1128_Y + attribute \src "ls180.v:5623.51-5623.87" + wire $ne$ls180.v:5623$1142_Y + attribute \src "ls180.v:5624.51-5624.86" + wire $ne$ls180.v:5624$1143_Y + attribute \src "ls180.v:5843.51-5843.87" + wire $ne$ls180.v:5843$1173_Y + attribute \src "ls180.v:5844.51-5844.86" + wire $ne$ls180.v:5844$1174_Y + attribute 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"ls180.v:7723.21-7723.73" + wire $or$ls180.v:7723$2594_Y + attribute \src "ls180.v:7724.21-7724.73" + wire $or$ls180.v:7724$2595_Y + attribute \src "ls180.v:7725.21-7725.73" + wire $or$ls180.v:7725$2596_Y + attribute \src "ls180.v:7726.21-7726.73" + wire $or$ls180.v:7726$2597_Y + attribute \src "ls180.v:7727.7-7727.68" + wire $or$ls180.v:7727$2598_Y + attribute \src "ls180.v:7738.7-7738.68" + wire $or$ls180.v:7738$2599_Y + attribute \src "ls180.v:7749.7-7749.50" + wire $or$ls180.v:7749$2600_Y + attribute \src "ls180.v:7894.7-7894.107" + wire $or$ls180.v:7894$2648_Y + attribute \src "ls180.v:7940.7-7940.107" + wire $or$ls180.v:7940$2664_Y + attribute \src "ls180.v:7986.7-7986.107" + wire $or$ls180.v:7986$2680_Y + attribute \src "ls180.v:8032.7-8032.107" + wire $or$ls180.v:8032$2696_Y + attribute \src "ls180.v:8220.40-8220.125" + wire $or$ls180.v:8220$2717_Y + attribute \src "ls180.v:8220.39-8220.207" + wire $or$ls180.v:8220$2720_Y + attribute \src "ls180.v:8220.38-8220.289" + wire $or$ls180.v:8220$2723_Y + attribute \src "ls180.v:8220.37-8220.371" + wire $or$ls180.v:8220$2726_Y + attribute \src "ls180.v:8221.41-8221.126" + wire $or$ls180.v:8221$2729_Y + attribute \src "ls180.v:8221.40-8221.208" + wire $or$ls180.v:8221$2732_Y + attribute \src "ls180.v:8221.39-8221.290" + wire $or$ls180.v:8221$2735_Y + attribute \src "ls180.v:8221.38-8221.372" + wire $or$ls180.v:8221$2738_Y + attribute \src "ls180.v:8225.7-8225.49" + wire $or$ls180.v:8225$2739_Y + attribute \src "ls180.v:8388.21-8388.74" + wire $or$ls180.v:8388$2787_Y + attribute \src "ls180.v:8423.21-8423.71" + wire $or$ls180.v:8423$2792_Y + attribute \src "ls180.v:8491.32-8491.85" + wire $or$ls180.v:8491$2804_Y + attribute \src "ls180.v:8497.8-8497.97" + wire $or$ls180.v:8497$2806_Y + attribute \src "ls180.v:8514.52-8514.139" + wire $or$ls180.v:8514$2811_Y + attribute \src "ls180.v:8515.51-8515.136" + wire $or$ls180.v:8515$2812_Y + attribute \src "ls180.v:8549.7-8549.87" + wire $or$ls180.v:8549$2815_Y + attribute \src "ls180.v:8572.33-8572.88" + wire $or$ls180.v:8572$2816_Y + attribute \src "ls180.v:8578.8-8578.99" + wire $or$ls180.v:8578$2818_Y + attribute \src "ls180.v:8595.53-8595.142" + wire $or$ls180.v:8595$2823_Y + attribute \src "ls180.v:8596.52-8596.139" + wire $or$ls180.v:8596$2824_Y + attribute \src "ls180.v:8630.7-8630.89" + wire $or$ls180.v:8630$2827_Y + attribute \src "ls180.v:8651.34-8651.91" + wire $or$ls180.v:8651$2828_Y + attribute \src "ls180.v:8657.8-8657.101" + wire $or$ls180.v:8657$2830_Y + attribute \src "ls180.v:8674.54-8674.145" + wire $or$ls180.v:8674$2835_Y + attribute \src "ls180.v:8675.53-8675.142" + wire $or$ls180.v:8675$2836_Y + attribute \src "ls180.v:8691.7-8691.91" + wire $or$ls180.v:8691$2839_Y + attribute \src "ls180.v:8880.8-8880.89" + wire $or$ls180.v:8880$2863_Y + attribute \src "ls180.v:8897.48-8897.127" + wire $or$ls180.v:8897$2868_Y + attribute \src "ls180.v:8898.47-8898.124" + wire $or$ls180.v:8898$2869_Y + attribute \src "ls180.v:3355.46-3355.94" + wire width 13 $sshl$ls180.v:3355$231_Y + attribute \src "ls180.v:3512.46-3512.94" + wire width 13 $sshl$ls180.v:3512$261_Y + attribute \src "ls180.v:3669.46-3669.94" + wire width 13 $sshl$ls180.v:3669$291_Y + attribute \src "ls180.v:3826.46-3826.94" + wire width 13 $sshl$ls180.v:3826$321_Y + attribute \src "ls180.v:3386.63-3386.122" + wire width 3 $sub$ls180.v:3386$244_Y + attribute \src "ls180.v:3543.63-3543.122" + wire width 3 $sub$ls180.v:3543$274_Y + attribute \src "ls180.v:3700.63-3700.122" + wire width 3 $sub$ls180.v:3700$304_Y + attribute \src "ls180.v:3857.63-3857.122" + wire width 3 $sub$ls180.v:3857$334_Y + attribute \src "ls180.v:4263.38-4263.75" + wire width 31 $sub$ls180.v:4263$688_Y + attribute \src "ls180.v:4349.36-4349.68" + wire width 4 $sub$ls180.v:4349$733_Y + attribute \src "ls180.v:4379.36-4379.68" + wire width 4 $sub$ls180.v:4379$744_Y + attribute \src "ls180.v:4415.70-4415.110" + wire width 16 $sub$ls180.v:4415$752_Y + attribute \src "ls180.v:4416.70-4416.104" + wire width 16 $sub$ls180.v:4416$754_Y + attribute \src "ls180.v:4443.37-4443.66" + wire width 8 $sub$ls180.v:4443$758_Y + attribute \src "ls180.v:4473.67-4473.107" + wire width 16 $sub$ls180.v:4473$760_Y + attribute \src "ls180.v:4474.67-4474.101" + wire width 16 $sub$ls180.v:4474$762_Y + attribute \src "ls180.v:4502.35-4502.64" + wire width 8 $sub$ls180.v:4502$766_Y + attribute \src "ls180.v:4756.60-4756.90" + wire width 32 $sub$ls180.v:4756$810_Y + attribute \src "ls180.v:4767.62-4767.104" + wire width 8 $sub$ls180.v:4767$812_Y + attribute \src "ls180.v:4784.60-4784.90" + wire width 32 $sub$ls180.v:4784$816_Y + attribute \src "ls180.v:5013.62-5013.93" + wire width 32 $sub$ls180.v:5013$846_Y + attribute \src "ls180.v:5018.62-5018.93" + wire width 32 $sub$ls180.v:5018$847_Y + attribute \src "ls180.v:5029.64-5029.122" + wire width 10 $sub$ls180.v:5029$850_Y + attribute \src "ls180.v:5050.62-5050.93" + wire width 32 $sub$ls180.v:5050$853_Y + attribute \src "ls180.v:5512.37-5512.75" + wire width 32 $sub$ls180.v:5512$1126_Y + attribute \src "ls180.v:5527.62-5527.100" + wire width 32 $sub$ls180.v:5527$1129_Y + attribute \src "ls180.v:5538.39-5538.77" + wire width 32 $sub$ls180.v:5538$1134_Y + attribute \src "ls180.v:5613.40-5613.76" + wire width 5 $sub$ls180.v:5613$1138_Y + attribute \src "ls180.v:5662.56-5662.104" + wire width 32 $sub$ls180.v:5662$1152_Y + attribute \src "ls180.v:5752.71-5752.105" + wire width 32 $sub$ls180.v:5752$1158_Y + attribute \src "ls180.v:5833.40-5833.76" + wire width 5 $sub$ls180.v:5833$1169_Y + attribute \src "ls180.v:7773.31-7773.60" + wire width 32 $sub$ls180.v:7773$2607_Y + attribute \src "ls180.v:7810.31-7810.61" + wire width 10 $sub$ls180.v:7810$2624_Y + attribute \src "ls180.v:7816.34-7816.67" + wire $sub$ls180.v:7816$2625_Y + attribute \src "ls180.v:7827.36-7827.69" + wire $sub$ls180.v:7827$2628_Y + attribute \src "ls180.v:7891.59-7891.116" + wire width 4 $sub$ls180.v:7891$2646_Y + attribute \src "ls180.v:7910.46-7910.90" + wire width 3 $sub$ls180.v:7910$2650_Y + attribute \src "ls180.v:7937.59-7937.116" + wire width 4 $sub$ls180.v:7937$2662_Y + attribute \src "ls180.v:7956.46-7956.90" + wire width 3 $sub$ls180.v:7956$2666_Y + attribute \src "ls180.v:7983.59-7983.116" + wire width 4 $sub$ls180.v:7983$2678_Y + attribute \src "ls180.v:8002.46-8002.90" + wire width 3 $sub$ls180.v:8002$2682_Y + attribute \src "ls180.v:8029.59-8029.116" + wire width 4 $sub$ls180.v:8029$2694_Y + attribute \src "ls180.v:8048.46-8048.90" + wire width 3 $sub$ls180.v:8048$2698_Y + attribute \src "ls180.v:8059.25-8059.48" + wire width 5 $sub$ls180.v:8059$2702_Y + attribute \src "ls180.v:8066.25-8066.48" + wire width 4 $sub$ls180.v:8066$2705_Y + attribute \src "ls180.v:8198.33-8198.64" + wire $sub$ls180.v:8198$2710_Y + attribute \src "ls180.v:8213.33-8213.64" + wire width 3 $sub$ls180.v:8213$2713_Y + attribute \src "ls180.v:8340.33-8340.64" + wire width 5 $sub$ls180.v:8340$2772_Y + attribute \src "ls180.v:8362.33-8362.64" + wire width 5 $sub$ls180.v:8362$2783_Y + attribute \src "ls180.v:8397.34-8397.66" + wire width 3 $sub$ls180.v:8397$2788_Y + attribute \src "ls180.v:8432.32-8432.62" + wire width 3 $sub$ls180.v:8432$2793_Y + attribute \src "ls180.v:8456.30-8456.53" + wire width 32 $sub$ls180.v:8456$2796_Y + attribute \src "ls180.v:8470.30-8470.53" + wire width 32 $sub$ls180.v:8470$2800_Y + attribute \src "ls180.v:8873.36-8873.70" + wire width 6 $sub$ls180.v:8873$2861_Y + attribute \src "ls180.v:8971.36-8971.70" + wire width 6 $sub$ls180.v:8971$2883_Y + attribute \src "ls180.v:9084.22-9084.42" + wire width 20 $sub$ls180.v:9084$2890_Y + attribute \src "ls180.v:5110.353-5110.425" + wire $xor$ls180.v:5110$860_Y + attribute \src "ls180.v:5110.200-5110.272" + wire $xor$ls180.v:5110$861_Y + attribute \src "ls180.v:5110.160-5110.273" + wire $xor$ls180.v:5110$862_Y + attribute \src "ls180.v:5111.353-5111.425" + wire $xor$ls180.v:5111$863_Y + attribute \src "ls180.v:5111.200-5111.272" + wire $xor$ls180.v:5111$864_Y + attribute \src "ls180.v:5111.160-5111.273" + wire $xor$ls180.v:5111$865_Y + attribute \src "ls180.v:5112.353-5112.425" + wire $xor$ls180.v:5112$866_Y + attribute \src "ls180.v:5112.200-5112.272" + wire $xor$ls180.v:5112$867_Y + attribute \src "ls180.v:5112.160-5112.273" + wire $xor$ls180.v:5112$868_Y + attribute \src "ls180.v:5113.353-5113.425" + wire $xor$ls180.v:5113$869_Y + attribute \src "ls180.v:5113.200-5113.272" + wire $xor$ls180.v:5113$870_Y + attribute \src "ls180.v:5113.160-5113.273" + wire $xor$ls180.v:5113$871_Y + attribute \src "ls180.v:5114.353-5114.425" + wire $xor$ls180.v:5114$872_Y + attribute \src "ls180.v:5114.200-5114.272" + wire $xor$ls180.v:5114$873_Y + attribute \src "ls180.v:5114.160-5114.273" + wire $xor$ls180.v:5114$874_Y + attribute \src "ls180.v:5115.353-5115.425" + wire $xor$ls180.v:5115$875_Y + attribute \src "ls180.v:5115.200-5115.272" + wire $xor$ls180.v:5115$876_Y + attribute \src "ls180.v:5115.160-5115.273" + wire $xor$ls180.v:5115$877_Y + attribute \src "ls180.v:5116.353-5116.425" + wire $xor$ls180.v:5116$878_Y + attribute \src "ls180.v:5116.200-5116.272" + wire $xor$ls180.v:5116$879_Y + attribute \src "ls180.v:5116.160-5116.273" + wire $xor$ls180.v:5116$880_Y + attribute \src "ls180.v:5117.353-5117.425" + wire $xor$ls180.v:5117$881_Y + attribute \src "ls180.v:5117.200-5117.272" + wire $xor$ls180.v:5117$882_Y + attribute \src "ls180.v:5117.160-5117.273" + wire $xor$ls180.v:5117$883_Y + attribute \src "ls180.v:5118.353-5118.425" + wire $xor$ls180.v:5118$884_Y + attribute \src "ls180.v:5118.200-5118.272" + wire $xor$ls180.v:5118$885_Y + attribute \src "ls180.v:5118.160-5118.273" + wire $xor$ls180.v:5118$886_Y + attribute \src "ls180.v:5119.354-5119.426" + wire $xor$ls180.v:5119$887_Y + attribute \src "ls180.v:5119.201-5119.273" + wire $xor$ls180.v:5119$888_Y + attribute \src "ls180.v:5119.161-5119.274" + wire $xor$ls180.v:5119$889_Y + attribute \src "ls180.v:5120.361-5120.434" + wire $xor$ls180.v:5120$890_Y + attribute \src "ls180.v:5120.205-5120.278" + wire $xor$ls180.v:5120$891_Y + attribute \src "ls180.v:5120.164-5120.279" + wire $xor$ls180.v:5120$892_Y + attribute \src "ls180.v:5121.361-5121.434" + wire $xor$ls180.v:5121$893_Y + attribute \src "ls180.v:5121.205-5121.278" + wire $xor$ls180.v:5121$894_Y + attribute \src "ls180.v:5121.164-5121.279" + wire $xor$ls180.v:5121$895_Y + attribute \src "ls180.v:5122.361-5122.434" + wire $xor$ls180.v:5122$896_Y + attribute \src "ls180.v:5122.205-5122.278" + wire $xor$ls180.v:5122$897_Y + attribute \src "ls180.v:5122.164-5122.279" + wire $xor$ls180.v:5122$898_Y + attribute \src "ls180.v:5123.361-5123.434" + wire $xor$ls180.v:5123$899_Y + attribute \src "ls180.v:5123.205-5123.278" + wire $xor$ls180.v:5123$900_Y + attribute \src "ls180.v:5123.164-5123.279" + wire $xor$ls180.v:5123$901_Y + attribute \src "ls180.v:5124.361-5124.434" + wire $xor$ls180.v:5124$902_Y + attribute \src "ls180.v:5124.205-5124.278" + wire $xor$ls180.v:5124$903_Y + attribute \src "ls180.v:5124.164-5124.279" + wire $xor$ls180.v:5124$904_Y + attribute \src "ls180.v:5125.361-5125.434" + wire $xor$ls180.v:5125$905_Y + attribute \src "ls180.v:5125.205-5125.278" + wire $xor$ls180.v:5125$906_Y + attribute \src "ls180.v:5125.164-5125.279" + wire $xor$ls180.v:5125$907_Y + attribute \src "ls180.v:5126.361-5126.434" + wire $xor$ls180.v:5126$908_Y + attribute \src "ls180.v:5126.205-5126.278" + wire $xor$ls180.v:5126$909_Y + attribute \src "ls180.v:5126.164-5126.279" + wire $xor$ls180.v:5126$910_Y + attribute \src "ls180.v:5127.361-5127.434" + wire $xor$ls180.v:5127$911_Y + attribute \src "ls180.v:5127.205-5127.278" + wire $xor$ls180.v:5127$912_Y + attribute \src "ls180.v:5127.164-5127.279" + wire $xor$ls180.v:5127$913_Y + attribute \src "ls180.v:5128.361-5128.434" + wire $xor$ls180.v:5128$914_Y + attribute \src "ls180.v:5128.205-5128.278" + wire $xor$ls180.v:5128$915_Y + attribute \src "ls180.v:5128.164-5128.279" + wire $xor$ls180.v:5128$916_Y + attribute \src "ls180.v:5129.361-5129.434" + wire $xor$ls180.v:5129$917_Y + attribute \src "ls180.v:5129.205-5129.278" + wire $xor$ls180.v:5129$918_Y + attribute \src "ls180.v:5129.164-5129.279" + wire $xor$ls180.v:5129$919_Y + attribute \src "ls180.v:5130.361-5130.434" + wire $xor$ls180.v:5130$920_Y + attribute \src "ls180.v:5130.205-5130.278" + wire $xor$ls180.v:5130$921_Y + attribute \src "ls180.v:5130.164-5130.279" + wire $xor$ls180.v:5130$922_Y + attribute \src "ls180.v:5131.361-5131.434" + wire $xor$ls180.v:5131$923_Y + attribute \src "ls180.v:5131.205-5131.278" + wire $xor$ls180.v:5131$924_Y + attribute \src "ls180.v:5131.164-5131.279" + wire $xor$ls180.v:5131$925_Y + attribute \src "ls180.v:5132.361-5132.434" + wire $xor$ls180.v:5132$926_Y + attribute \src "ls180.v:5132.205-5132.278" + wire $xor$ls180.v:5132$927_Y + attribute \src "ls180.v:5132.164-5132.279" + wire $xor$ls180.v:5132$928_Y + attribute \src "ls180.v:5133.361-5133.434" + wire $xor$ls180.v:5133$929_Y + attribute \src "ls180.v:5133.205-5133.278" + wire $xor$ls180.v:5133$930_Y + attribute \src "ls180.v:5133.164-5133.279" + wire $xor$ls180.v:5133$931_Y + attribute \src "ls180.v:5134.361-5134.434" + wire $xor$ls180.v:5134$932_Y + attribute \src "ls180.v:5134.205-5134.278" + wire $xor$ls180.v:5134$933_Y + attribute \src "ls180.v:5134.164-5134.279" + wire $xor$ls180.v:5134$934_Y + attribute \src "ls180.v:5135.361-5135.434" + wire $xor$ls180.v:5135$935_Y + attribute \src "ls180.v:5135.205-5135.278" + wire $xor$ls180.v:5135$936_Y + attribute \src "ls180.v:5135.164-5135.279" + wire $xor$ls180.v:5135$937_Y + attribute \src "ls180.v:5136.361-5136.434" + wire $xor$ls180.v:5136$938_Y + attribute \src "ls180.v:5136.205-5136.278" + wire $xor$ls180.v:5136$939_Y + attribute \src "ls180.v:5136.164-5136.279" + wire $xor$ls180.v:5136$940_Y + attribute \src "ls180.v:5137.361-5137.434" + wire $xor$ls180.v:5137$941_Y + attribute \src "ls180.v:5137.205-5137.278" + wire $xor$ls180.v:5137$942_Y + attribute \src "ls180.v:5137.164-5137.279" + wire $xor$ls180.v:5137$943_Y + attribute \src "ls180.v:5138.361-5138.434" + wire $xor$ls180.v:5138$944_Y + attribute \src "ls180.v:5138.205-5138.278" + wire $xor$ls180.v:5138$945_Y + attribute \src "ls180.v:5138.164-5138.279" + wire $xor$ls180.v:5138$946_Y + attribute \src "ls180.v:5139.361-5139.434" + wire $xor$ls180.v:5139$947_Y + attribute \src "ls180.v:5139.205-5139.278" + wire $xor$ls180.v:5139$948_Y + attribute \src "ls180.v:5139.164-5139.279" + wire $xor$ls180.v:5139$949_Y + attribute \src "ls180.v:5140.360-5140.432" + wire $xor$ls180.v:5140$950_Y + attribute \src "ls180.v:5140.205-5140.277" + wire $xor$ls180.v:5140$951_Y + attribute \src "ls180.v:5140.164-5140.278" + wire $xor$ls180.v:5140$952_Y + attribute \src "ls180.v:5141.360-5141.432" + wire $xor$ls180.v:5141$953_Y + attribute \src "ls180.v:5141.205-5141.277" + wire $xor$ls180.v:5141$954_Y + attribute \src "ls180.v:5141.164-5141.278" + wire $xor$ls180.v:5141$955_Y + attribute \src "ls180.v:5142.360-5142.432" + wire $xor$ls180.v:5142$956_Y + attribute \src "ls180.v:5142.205-5142.277" + wire $xor$ls180.v:5142$957_Y + attribute \src "ls180.v:5142.164-5142.278" + wire $xor$ls180.v:5142$958_Y + attribute \src "ls180.v:5143.360-5143.432" + wire $xor$ls180.v:5143$959_Y + attribute \src "ls180.v:5143.205-5143.277" + wire $xor$ls180.v:5143$960_Y + attribute \src "ls180.v:5143.164-5143.278" + wire $xor$ls180.v:5143$961_Y + attribute \src "ls180.v:5144.360-5144.432" + wire $xor$ls180.v:5144$962_Y + attribute \src "ls180.v:5144.205-5144.277" + wire $xor$ls180.v:5144$963_Y + attribute \src "ls180.v:5144.164-5144.278" + wire $xor$ls180.v:5144$964_Y + attribute \src "ls180.v:5145.360-5145.432" + wire $xor$ls180.v:5145$965_Y + attribute \src "ls180.v:5145.205-5145.277" + wire $xor$ls180.v:5145$966_Y + attribute \src "ls180.v:5145.164-5145.278" + wire $xor$ls180.v:5145$967_Y + attribute \src "ls180.v:5146.360-5146.432" + wire $xor$ls180.v:5146$968_Y + attribute \src "ls180.v:5146.205-5146.277" + wire $xor$ls180.v:5146$969_Y + attribute \src "ls180.v:5146.164-5146.278" + wire $xor$ls180.v:5146$970_Y + attribute \src "ls180.v:5147.360-5147.432" + wire $xor$ls180.v:5147$971_Y + attribute \src "ls180.v:5147.205-5147.277" + wire $xor$ls180.v:5147$972_Y + attribute \src "ls180.v:5147.164-5147.278" + wire $xor$ls180.v:5147$973_Y + attribute \src "ls180.v:5148.360-5148.432" + wire $xor$ls180.v:5148$974_Y + attribute \src "ls180.v:5148.205-5148.277" + wire $xor$ls180.v:5148$975_Y + attribute \src "ls180.v:5148.164-5148.278" + wire $xor$ls180.v:5148$976_Y + attribute \src "ls180.v:5149.360-5149.432" + wire $xor$ls180.v:5149$977_Y + attribute \src "ls180.v:5149.205-5149.277" + wire $xor$ls180.v:5149$978_Y + attribute \src "ls180.v:5149.164-5149.278" + wire $xor$ls180.v:5149$979_Y + attribute \src "ls180.v:5170.899-5170.983" + wire $xor$ls180.v:5170$993_Y + attribute \src "ls180.v:5170.634-5170.718" + wire $xor$ls180.v:5170$994_Y + attribute \src "ls180.v:5170.588-5170.719" + wire $xor$ls180.v:5170$995_Y + attribute \src "ls180.v:5170.234-5170.318" + wire $xor$ls180.v:5170$996_Y + attribute \src "ls180.v:5170.187-5170.319" + wire $xor$ls180.v:5170$997_Y + attribute \src "ls180.v:5171.588-5171.719" + wire $xor$ls180.v:5171$1000_Y + attribute \src "ls180.v:5171.234-5171.318" + wire $xor$ls180.v:5171$1001_Y + attribute \src "ls180.v:5171.187-5171.319" + wire $xor$ls180.v:5171$1002_Y + attribute \src "ls180.v:5171.899-5171.983" + wire $xor$ls180.v:5171$998_Y + attribute \src "ls180.v:5171.634-5171.718" + wire $xor$ls180.v:5171$999_Y + attribute \src "ls180.v:5180.899-5180.983" + wire $xor$ls180.v:5180$1004_Y + attribute \src "ls180.v:5180.634-5180.718" + wire $xor$ls180.v:5180$1005_Y + attribute \src "ls180.v:5180.588-5180.719" + wire $xor$ls180.v:5180$1006_Y + attribute \src "ls180.v:5180.234-5180.318" + wire $xor$ls180.v:5180$1007_Y + attribute \src "ls180.v:5180.187-5180.319" + wire $xor$ls180.v:5180$1008_Y + attribute \src "ls180.v:5181.899-5181.983" + wire $xor$ls180.v:5181$1009_Y + attribute \src "ls180.v:5181.634-5181.718" + wire $xor$ls180.v:5181$1010_Y + attribute \src "ls180.v:5181.588-5181.719" + wire $xor$ls180.v:5181$1011_Y + attribute \src "ls180.v:5181.234-5181.318" + wire $xor$ls180.v:5181$1012_Y + attribute \src "ls180.v:5181.187-5181.319" + wire $xor$ls180.v:5181$1013_Y + attribute \src "ls180.v:5190.899-5190.983" + wire $xor$ls180.v:5190$1015_Y + attribute \src "ls180.v:5190.634-5190.718" + wire $xor$ls180.v:5190$1016_Y + attribute \src "ls180.v:5190.588-5190.719" + wire $xor$ls180.v:5190$1017_Y + attribute \src "ls180.v:5190.234-5190.318" + wire $xor$ls180.v:5190$1018_Y + attribute \src "ls180.v:5190.187-5190.319" + wire $xor$ls180.v:5190$1019_Y + attribute \src "ls180.v:5191.899-5191.983" + wire $xor$ls180.v:5191$1020_Y + attribute \src "ls180.v:5191.634-5191.718" + wire $xor$ls180.v:5191$1021_Y + attribute \src "ls180.v:5191.588-5191.719" + wire $xor$ls180.v:5191$1022_Y + attribute \src "ls180.v:5191.234-5191.318" + wire $xor$ls180.v:5191$1023_Y + attribute \src "ls180.v:5191.187-5191.319" + wire $xor$ls180.v:5191$1024_Y + attribute \src "ls180.v:5200.899-5200.983" + wire $xor$ls180.v:5200$1026_Y + attribute \src "ls180.v:5200.634-5200.718" + wire $xor$ls180.v:5200$1027_Y + attribute \src "ls180.v:5200.588-5200.719" + wire $xor$ls180.v:5200$1028_Y + attribute \src "ls180.v:5200.234-5200.318" + wire $xor$ls180.v:5200$1029_Y + attribute \src "ls180.v:5200.187-5200.319" + wire $xor$ls180.v:5200$1030_Y + attribute \src "ls180.v:5201.899-5201.983" + wire $xor$ls180.v:5201$1031_Y + attribute \src "ls180.v:5201.634-5201.718" + wire $xor$ls180.v:5201$1032_Y + attribute \src "ls180.v:5201.588-5201.719" + wire $xor$ls180.v:5201$1033_Y + attribute \src "ls180.v:5201.234-5201.318" + wire $xor$ls180.v:5201$1034_Y + attribute \src "ls180.v:5201.187-5201.319" + wire $xor$ls180.v:5201$1035_Y + attribute \src "ls180.v:5352.879-5352.961" + wire $xor$ls180.v:5352$1068_Y + attribute \src "ls180.v:5352.620-5352.702" + wire $xor$ls180.v:5352$1069_Y + attribute \src "ls180.v:5352.575-5352.703" + wire $xor$ls180.v:5352$1070_Y + attribute \src "ls180.v:5352.229-5352.311" + wire $xor$ls180.v:5352$1071_Y + attribute \src "ls180.v:5352.183-5352.312" + wire $xor$ls180.v:5352$1072_Y + attribute \src "ls180.v:5353.879-5353.961" + wire $xor$ls180.v:5353$1073_Y + attribute \src "ls180.v:5353.620-5353.702" + wire $xor$ls180.v:5353$1074_Y + attribute \src "ls180.v:5353.575-5353.703" + wire $xor$ls180.v:5353$1075_Y + attribute \src "ls180.v:5353.229-5353.311" + wire $xor$ls180.v:5353$1076_Y + attribute \src "ls180.v:5353.183-5353.312" + wire $xor$ls180.v:5353$1077_Y + attribute \src "ls180.v:5362.879-5362.961" + wire $xor$ls180.v:5362$1079_Y + attribute \src "ls180.v:5362.620-5362.702" + wire $xor$ls180.v:5362$1080_Y + attribute \src "ls180.v:5362.575-5362.703" + wire $xor$ls180.v:5362$1081_Y + attribute \src "ls180.v:5362.229-5362.311" + wire $xor$ls180.v:5362$1082_Y + attribute \src "ls180.v:5362.183-5362.312" + wire $xor$ls180.v:5362$1083_Y + attribute \src "ls180.v:5363.879-5363.961" + wire $xor$ls180.v:5363$1084_Y + attribute \src "ls180.v:5363.620-5363.702" + wire $xor$ls180.v:5363$1085_Y + attribute \src "ls180.v:5363.575-5363.703" + wire $xor$ls180.v:5363$1086_Y + attribute \src "ls180.v:5363.229-5363.311" + wire $xor$ls180.v:5363$1087_Y + attribute \src "ls180.v:5363.183-5363.312" + wire $xor$ls180.v:5363$1088_Y + attribute \src "ls180.v:5372.879-5372.961" + wire $xor$ls180.v:5372$1090_Y + attribute \src "ls180.v:5372.620-5372.702" + wire $xor$ls180.v:5372$1091_Y + attribute \src "ls180.v:5372.575-5372.703" + wire $xor$ls180.v:5372$1092_Y + attribute \src "ls180.v:5372.229-5372.311" + wire $xor$ls180.v:5372$1093_Y + attribute \src "ls180.v:5372.183-5372.312" + wire $xor$ls180.v:5372$1094_Y + attribute \src "ls180.v:5373.879-5373.961" + wire $xor$ls180.v:5373$1095_Y + attribute \src "ls180.v:5373.620-5373.702" + wire $xor$ls180.v:5373$1096_Y + attribute \src "ls180.v:5373.575-5373.703" + wire $xor$ls180.v:5373$1097_Y + attribute \src "ls180.v:5373.229-5373.311" + wire $xor$ls180.v:5373$1098_Y + attribute \src "ls180.v:5373.183-5373.312" + wire $xor$ls180.v:5373$1099_Y + attribute \src "ls180.v:5382.879-5382.961" + wire $xor$ls180.v:5382$1101_Y + attribute \src "ls180.v:5382.620-5382.702" + wire $xor$ls180.v:5382$1102_Y + attribute \src "ls180.v:5382.575-5382.703" + wire $xor$ls180.v:5382$1103_Y + attribute \src "ls180.v:5382.229-5382.311" + wire $xor$ls180.v:5382$1104_Y + attribute \src "ls180.v:5382.183-5382.312" + wire $xor$ls180.v:5382$1105_Y + attribute \src "ls180.v:5383.879-5383.961" + wire $xor$ls180.v:5383$1106_Y + attribute \src "ls180.v:5383.620-5383.702" + wire $xor$ls180.v:5383$1107_Y + attribute \src "ls180.v:5383.575-5383.703" + wire $xor$ls180.v:5383$1108_Y + attribute \src "ls180.v:5383.229-5383.311" + wire $xor$ls180.v:5383$1109_Y + attribute \src "ls180.v:5383.183-5383.312" + wire $xor$ls180.v:5383$1110_Y + attribute \src "ls180.v:1854.11-1854.42" + wire width 3 \builder_bankmachine0_next_state + attribute \src "ls180.v:1853.11-1853.37" + wire width 3 \builder_bankmachine0_state + attribute \src "ls180.v:1856.11-1856.42" + wire width 3 \builder_bankmachine1_next_state + attribute \src "ls180.v:1855.11-1855.37" + wire width 3 \builder_bankmachine1_state + attribute \src "ls180.v:1858.11-1858.42" + wire width 3 \builder_bankmachine2_next_state + attribute \src "ls180.v:1857.11-1857.37" + wire width 3 \builder_bankmachine2_state + attribute \src "ls180.v:1860.11-1860.42" + wire width 3 \builder_bankmachine3_next_state + attribute \src "ls180.v:1859.11-1859.37" + wire width 3 \builder_bankmachine3_state + attribute \src "ls180.v:2713.5-2713.34" + wire \builder_comb_rhs_array_muxed0 + attribute \src "ls180.v:2714.12-2714.41" + wire width 13 \builder_comb_rhs_array_muxed1 + attribute \src "ls180.v:2726.5-2726.35" + wire \builder_comb_rhs_array_muxed10 + attribute \src "ls180.v:2727.5-2727.35" + wire \builder_comb_rhs_array_muxed11 + attribute \src "ls180.v:2731.12-2731.42" + wire width 22 \builder_comb_rhs_array_muxed12 + attribute \src "ls180.v:2732.5-2732.35" + wire \builder_comb_rhs_array_muxed13 + attribute \src "ls180.v:2733.5-2733.35" + wire \builder_comb_rhs_array_muxed14 + attribute \src "ls180.v:2734.12-2734.42" + wire width 22 \builder_comb_rhs_array_muxed15 + attribute \src "ls180.v:2735.5-2735.35" + wire \builder_comb_rhs_array_muxed16 + attribute \src "ls180.v:2736.5-2736.35" + wire \builder_comb_rhs_array_muxed17 + attribute \src "ls180.v:2737.12-2737.42" + wire width 22 \builder_comb_rhs_array_muxed18 + attribute \src "ls180.v:2738.5-2738.35" + wire \builder_comb_rhs_array_muxed19 + attribute \src "ls180.v:2715.11-2715.40" + wire width 2 \builder_comb_rhs_array_muxed2 + attribute \src "ls180.v:2739.5-2739.35" + wire \builder_comb_rhs_array_muxed20 + attribute \src "ls180.v:2740.12-2740.42" + wire width 22 \builder_comb_rhs_array_muxed21 + attribute \src "ls180.v:2741.5-2741.35" + wire \builder_comb_rhs_array_muxed22 + attribute \src "ls180.v:2742.5-2742.35" + wire \builder_comb_rhs_array_muxed23 + attribute \src "ls180.v:2743.12-2743.42" + wire width 32 \builder_comb_rhs_array_muxed24 + attribute \src "ls180.v:2744.12-2744.42" + wire width 64 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2745.11-2745.41" + wire width 8 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2746.5-2746.35" + wire \builder_comb_rhs_array_muxed27 + attribute \src "ls180.v:2747.5-2747.35" + wire \builder_comb_rhs_array_muxed28 + attribute \src "ls180.v:2748.5-2748.35" + wire \builder_comb_rhs_array_muxed29 + attribute \src "ls180.v:2716.5-2716.34" + wire \builder_comb_rhs_array_muxed3 + attribute \src "ls180.v:2749.11-2749.41" + wire width 3 \builder_comb_rhs_array_muxed30 + attribute \src "ls180.v:2750.11-2750.41" + wire width 2 \builder_comb_rhs_array_muxed31 + attribute \src "ls180.v:2717.5-2717.34" + wire \builder_comb_rhs_array_muxed4 + attribute \src "ls180.v:2718.5-2718.34" + wire \builder_comb_rhs_array_muxed5 + attribute \src "ls180.v:2722.5-2722.34" + wire \builder_comb_rhs_array_muxed6 + attribute \src "ls180.v:2723.12-2723.41" + wire width 13 \builder_comb_rhs_array_muxed7 + attribute \src "ls180.v:2724.11-2724.40" + wire width 2 \builder_comb_rhs_array_muxed8 + attribute \src "ls180.v:2725.5-2725.34" + wire \builder_comb_rhs_array_muxed9 + attribute \src "ls180.v:2719.5-2719.32" + wire \builder_comb_t_array_muxed0 + attribute \src "ls180.v:2720.5-2720.32" + wire \builder_comb_t_array_muxed1 + attribute \src "ls180.v:2721.5-2721.32" + wire \builder_comb_t_array_muxed2 + attribute \src "ls180.v:2728.5-2728.32" + wire \builder_comb_t_array_muxed3 + attribute \src "ls180.v:2729.5-2729.32" + wire \builder_comb_t_array_muxed4 + attribute \src "ls180.v:2730.5-2730.32" + wire \builder_comb_t_array_muxed5 + attribute \src "ls180.v:1840.5-1840.34" + wire \builder_converter0_next_state + attribute \src "ls180.v:1839.5-1839.29" + wire \builder_converter0_state + attribute \src "ls180.v:1844.5-1844.34" + wire \builder_converter1_next_state + attribute \src "ls180.v:1843.5-1843.29" + wire \builder_converter1_state + attribute \src "ls180.v:1848.5-1848.34" + wire \builder_converter2_next_state + attribute \src "ls180.v:1847.5-1847.29" + wire \builder_converter2_state + attribute \src "ls180.v:1885.5-1885.33" + wire \builder_converter_next_state + attribute \src "ls180.v:1884.5-1884.28" + wire \builder_converter_state + attribute \src "ls180.v:2013.12-2013.25" + wire width 20 \builder_count + attribute \src "ls180.v:2701.13-2701.41" + wire width 14 \builder_csr_interconnect_adr + attribute \src "ls180.v:2704.12-2704.42" + wire width 8 \builder_csr_interconnect_dat_r + attribute \src "ls180.v:2703.12-2703.42" + wire width 8 \builder_csr_interconnect_dat_w + attribute \src "ls180.v:2702.6-2702.33" + wire \builder_csr_interconnect_we + attribute \src "ls180.v:2051.12-2051.42" + wire width 8 \builder_csrbank0_bus_errors0_r + attribute \src "ls180.v:2050.6-2050.37" + wire \builder_csrbank0_bus_errors0_re + attribute \src "ls180.v:2053.12-2053.42" + wire width 8 \builder_csrbank0_bus_errors0_w + attribute \src "ls180.v:2052.6-2052.37" + wire \builder_csrbank0_bus_errors0_we + attribute \src "ls180.v:2047.12-2047.42" + wire width 8 \builder_csrbank0_bus_errors1_r + attribute \src "ls180.v:2046.6-2046.37" + wire \builder_csrbank0_bus_errors1_re + attribute \src "ls180.v:2049.12-2049.42" + wire width 8 \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:2048.6-2048.37" + wire \builder_csrbank0_bus_errors1_we + attribute \src "ls180.v:2043.12-2043.42" + wire width 8 \builder_csrbank0_bus_errors2_r + attribute \src "ls180.v:2042.6-2042.37" + wire \builder_csrbank0_bus_errors2_re + attribute \src "ls180.v:2045.12-2045.42" + wire width 8 \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:2044.6-2044.37" + wire \builder_csrbank0_bus_errors2_we + attribute \src "ls180.v:2039.12-2039.42" + wire width 8 \builder_csrbank0_bus_errors3_r + attribute \src "ls180.v:2038.6-2038.37" + wire \builder_csrbank0_bus_errors3_re + attribute \src "ls180.v:2041.12-2041.42" + wire width 8 \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:2040.6-2040.37" + wire \builder_csrbank0_bus_errors3_we + attribute \src "ls180.v:2019.6-2019.31" + wire \builder_csrbank0_reset0_r + attribute \src "ls180.v:2018.6-2018.32" + wire \builder_csrbank0_reset0_re + attribute \src "ls180.v:2021.6-2021.31" + wire \builder_csrbank0_reset0_w + attribute \src "ls180.v:2020.6-2020.32" + wire \builder_csrbank0_reset0_we + attribute \src "ls180.v:2035.12-2035.39" + wire width 8 \builder_csrbank0_scratch0_r + attribute \src "ls180.v:2034.6-2034.34" + wire \builder_csrbank0_scratch0_re + attribute \src "ls180.v:2037.12-2037.39" + wire width 8 \builder_csrbank0_scratch0_w + attribute \src "ls180.v:2036.6-2036.34" + wire \builder_csrbank0_scratch0_we + attribute \src "ls180.v:2031.12-2031.39" + wire width 8 \builder_csrbank0_scratch1_r + attribute \src "ls180.v:2030.6-2030.34" + wire \builder_csrbank0_scratch1_re + attribute \src "ls180.v:2033.12-2033.39" + wire width 8 \builder_csrbank0_scratch1_w + attribute \src "ls180.v:2032.6-2032.34" + wire \builder_csrbank0_scratch1_we + attribute \src "ls180.v:2027.12-2027.39" + wire width 8 \builder_csrbank0_scratch2_r + attribute \src "ls180.v:2026.6-2026.34" + wire \builder_csrbank0_scratch2_re + attribute \src "ls180.v:2029.12-2029.39" + wire width 8 \builder_csrbank0_scratch2_w + attribute \src "ls180.v:2028.6-2028.34" + wire \builder_csrbank0_scratch2_we + attribute \src "ls180.v:2023.12-2023.39" + wire width 8 \builder_csrbank0_scratch3_r + attribute \src "ls180.v:2022.6-2022.34" + wire \builder_csrbank0_scratch3_re + attribute \src "ls180.v:2025.12-2025.39" + wire width 8 \builder_csrbank0_scratch3_w + attribute \src "ls180.v:2024.6-2024.34" + wire \builder_csrbank0_scratch3_we + attribute \src "ls180.v:2054.6-2054.26" + wire \builder_csrbank0_sel + attribute \src "ls180.v:2525.12-2525.40" + wire width 8 \builder_csrbank10_control0_r + attribute \src "ls180.v:2524.6-2524.35" + wire \builder_csrbank10_control0_re + attribute \src "ls180.v:2527.12-2527.40" + wire width 8 \builder_csrbank10_control0_w + attribute \src "ls180.v:2526.6-2526.35" + wire \builder_csrbank10_control0_we + attribute \src "ls180.v:2521.12-2521.40" + wire width 8 \builder_csrbank10_control1_r + attribute \src "ls180.v:2520.6-2520.35" + wire \builder_csrbank10_control1_re + attribute \src "ls180.v:2523.12-2523.40" + wire width 8 \builder_csrbank10_control1_w + attribute \src "ls180.v:2522.6-2522.35" + wire \builder_csrbank10_control1_we + attribute \src "ls180.v:2541.6-2541.29" + wire \builder_csrbank10_cs0_r + attribute \src "ls180.v:2540.6-2540.30" + wire \builder_csrbank10_cs0_re + attribute \src "ls180.v:2543.6-2543.29" + wire \builder_csrbank10_cs0_w + attribute \src "ls180.v:2542.6-2542.30" + wire \builder_csrbank10_cs0_we + attribute \src "ls180.v:2545.6-2545.35" + wire \builder_csrbank10_loopback0_r + attribute \src "ls180.v:2544.6-2544.36" + wire \builder_csrbank10_loopback0_re + attribute \src "ls180.v:2547.6-2547.35" + wire \builder_csrbank10_loopback0_w + attribute \src "ls180.v:2546.6-2546.36" + wire \builder_csrbank10_loopback0_we + attribute \src "ls180.v:2537.12-2537.36" + wire width 8 \builder_csrbank10_miso_r + attribute \src "ls180.v:2536.6-2536.31" + wire \builder_csrbank10_miso_re + attribute \src "ls180.v:2539.12-2539.36" + wire width 8 \builder_csrbank10_miso_w + attribute \src "ls180.v:2538.6-2538.31" + wire \builder_csrbank10_miso_we + attribute \src "ls180.v:2533.12-2533.37" + wire width 8 \builder_csrbank10_mosi0_r + attribute \src "ls180.v:2532.6-2532.32" + wire \builder_csrbank10_mosi0_re + attribute \src "ls180.v:2535.12-2535.37" + wire width 8 \builder_csrbank10_mosi0_w + attribute \src "ls180.v:2534.6-2534.32" + wire \builder_csrbank10_mosi0_we + attribute \src "ls180.v:2548.6-2548.27" + wire \builder_csrbank10_sel + attribute \src "ls180.v:2529.6-2529.32" + wire \builder_csrbank10_status_r + attribute \src "ls180.v:2528.6-2528.33" + wire \builder_csrbank10_status_re + attribute \src "ls180.v:2531.6-2531.32" + wire \builder_csrbank10_status_w + attribute \src "ls180.v:2530.6-2530.33" + wire \builder_csrbank10_status_we + attribute \src "ls180.v:2586.12-2586.44" + wire width 8 \builder_csrbank11_clk_divider0_r + attribute \src "ls180.v:2585.6-2585.39" + wire \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:2588.12-2588.44" + wire width 8 \builder_csrbank11_clk_divider0_w + attribute \src "ls180.v:2587.6-2587.39" + wire \builder_csrbank11_clk_divider0_we + attribute \src "ls180.v:2582.12-2582.44" + wire width 8 \builder_csrbank11_clk_divider1_r + attribute \src "ls180.v:2581.6-2581.39" + wire \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:2584.12-2584.44" + wire width 8 \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:2583.6-2583.39" + wire \builder_csrbank11_clk_divider1_we + attribute \src "ls180.v:2558.12-2558.40" + wire width 8 \builder_csrbank11_control0_r + attribute \src "ls180.v:2557.6-2557.35" + wire \builder_csrbank11_control0_re + attribute \src "ls180.v:2560.12-2560.40" + wire width 8 \builder_csrbank11_control0_w + attribute \src "ls180.v:2559.6-2559.35" + wire \builder_csrbank11_control0_we + attribute \src "ls180.v:2554.12-2554.40" + wire width 8 \builder_csrbank11_control1_r + attribute \src "ls180.v:2553.6-2553.35" + wire \builder_csrbank11_control1_re + attribute \src "ls180.v:2556.12-2556.40" + wire width 8 \builder_csrbank11_control1_w + attribute \src "ls180.v:2555.6-2555.35" + wire \builder_csrbank11_control1_we + attribute \src "ls180.v:2574.6-2574.29" + wire \builder_csrbank11_cs0_r + attribute \src "ls180.v:2573.6-2573.30" + wire \builder_csrbank11_cs0_re + attribute \src "ls180.v:2576.6-2576.29" + wire \builder_csrbank11_cs0_w + attribute \src "ls180.v:2575.6-2575.30" + wire \builder_csrbank11_cs0_we + attribute \src "ls180.v:2578.6-2578.35" + wire \builder_csrbank11_loopback0_r + attribute \src "ls180.v:2577.6-2577.36" + wire \builder_csrbank11_loopback0_re + attribute \src "ls180.v:2580.6-2580.35" + wire \builder_csrbank11_loopback0_w + attribute \src "ls180.v:2579.6-2579.36" + wire \builder_csrbank11_loopback0_we + attribute \src "ls180.v:2570.12-2570.36" + wire width 8 \builder_csrbank11_miso_r + attribute \src "ls180.v:2569.6-2569.31" + wire \builder_csrbank11_miso_re + attribute \src "ls180.v:2572.12-2572.36" + wire width 8 \builder_csrbank11_miso_w + attribute \src "ls180.v:2571.6-2571.31" + wire \builder_csrbank11_miso_we + attribute \src "ls180.v:2566.12-2566.37" + wire width 8 \builder_csrbank11_mosi0_r + attribute \src "ls180.v:2565.6-2565.32" + wire \builder_csrbank11_mosi0_re + attribute \src "ls180.v:2568.12-2568.37" + wire width 8 \builder_csrbank11_mosi0_w + attribute \src "ls180.v:2567.6-2567.32" + wire \builder_csrbank11_mosi0_we + attribute \src "ls180.v:2589.6-2589.27" + wire \builder_csrbank11_sel + attribute \src "ls180.v:2562.6-2562.32" + wire \builder_csrbank11_status_r + attribute \src "ls180.v:2561.6-2561.33" + wire \builder_csrbank11_status_re + attribute \src "ls180.v:2564.6-2564.32" + wire \builder_csrbank11_status_w + attribute \src "ls180.v:2563.6-2563.33" + wire \builder_csrbank11_status_we + attribute \src "ls180.v:2627.6-2627.29" + wire \builder_csrbank12_en0_r + attribute \src "ls180.v:2626.6-2626.30" + wire \builder_csrbank12_en0_re + attribute \src "ls180.v:2629.6-2629.29" + wire \builder_csrbank12_en0_w + attribute \src "ls180.v:2628.6-2628.30" + wire \builder_csrbank12_en0_we + attribute \src "ls180.v:2651.6-2651.36" + wire \builder_csrbank12_ev_enable0_r + attribute \src "ls180.v:2650.6-2650.37" + wire \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:2653.6-2653.36" + wire \builder_csrbank12_ev_enable0_w + attribute \src "ls180.v:2652.6-2652.37" + wire \builder_csrbank12_ev_enable0_we + attribute \src "ls180.v:2607.12-2607.37" + wire width 8 \builder_csrbank12_load0_r + attribute \src "ls180.v:2606.6-2606.32" + wire \builder_csrbank12_load0_re + attribute \src "ls180.v:2609.12-2609.37" + wire width 8 \builder_csrbank12_load0_w + attribute \src "ls180.v:2608.6-2608.32" + wire \builder_csrbank12_load0_we + attribute \src "ls180.v:2603.12-2603.37" + wire width 8 \builder_csrbank12_load1_r + attribute \src "ls180.v:2602.6-2602.32" + wire \builder_csrbank12_load1_re + attribute \src "ls180.v:2605.12-2605.37" + wire width 8 \builder_csrbank12_load1_w + attribute \src "ls180.v:2604.6-2604.32" + wire \builder_csrbank12_load1_we + attribute \src "ls180.v:2599.12-2599.37" + wire width 8 \builder_csrbank12_load2_r + attribute \src "ls180.v:2598.6-2598.32" + wire \builder_csrbank12_load2_re + attribute \src "ls180.v:2601.12-2601.37" + wire width 8 \builder_csrbank12_load2_w + attribute \src "ls180.v:2600.6-2600.32" + wire \builder_csrbank12_load2_we + attribute \src "ls180.v:2595.12-2595.37" + wire width 8 \builder_csrbank12_load3_r + attribute \src "ls180.v:2594.6-2594.32" + wire \builder_csrbank12_load3_re + attribute \src "ls180.v:2597.12-2597.37" + wire width 8 \builder_csrbank12_load3_w + attribute \src "ls180.v:2596.6-2596.32" + wire \builder_csrbank12_load3_we + attribute \src "ls180.v:2623.12-2623.39" + wire width 8 \builder_csrbank12_reload0_r + attribute \src "ls180.v:2622.6-2622.34" + wire \builder_csrbank12_reload0_re + attribute \src "ls180.v:2625.12-2625.39" + wire width 8 \builder_csrbank12_reload0_w + attribute \src "ls180.v:2624.6-2624.34" + wire \builder_csrbank12_reload0_we + attribute \src "ls180.v:2619.12-2619.39" + wire width 8 \builder_csrbank12_reload1_r + attribute \src "ls180.v:2618.6-2618.34" + wire \builder_csrbank12_reload1_re + attribute \src "ls180.v:2621.12-2621.39" + wire width 8 \builder_csrbank12_reload1_w + attribute \src "ls180.v:2620.6-2620.34" + wire \builder_csrbank12_reload1_we + attribute \src "ls180.v:2615.12-2615.39" + wire width 8 \builder_csrbank12_reload2_r + attribute \src "ls180.v:2614.6-2614.34" + wire \builder_csrbank12_reload2_re + attribute \src "ls180.v:2617.12-2617.39" + wire width 8 \builder_csrbank12_reload2_w + attribute \src "ls180.v:2616.6-2616.34" + wire \builder_csrbank12_reload2_we + attribute \src "ls180.v:2611.12-2611.39" + wire width 8 \builder_csrbank12_reload3_r + attribute \src "ls180.v:2610.6-2610.34" + wire \builder_csrbank12_reload3_re + attribute \src "ls180.v:2613.12-2613.39" + wire width 8 \builder_csrbank12_reload3_w + attribute \src "ls180.v:2612.6-2612.34" + wire \builder_csrbank12_reload3_we + attribute \src "ls180.v:2654.6-2654.27" + wire \builder_csrbank12_sel + attribute \src "ls180.v:2631.6-2631.39" + wire \builder_csrbank12_update_value0_r + attribute \src "ls180.v:2630.6-2630.40" + wire \builder_csrbank12_update_value0_re + attribute \src "ls180.v:2633.6-2633.39" + wire \builder_csrbank12_update_value0_w + attribute \src "ls180.v:2632.6-2632.40" + wire \builder_csrbank12_update_value0_we + attribute \src "ls180.v:2647.12-2647.38" + wire width 8 \builder_csrbank12_value0_r + attribute \src "ls180.v:2646.6-2646.33" + wire \builder_csrbank12_value0_re + attribute \src "ls180.v:2649.12-2649.38" + wire width 8 \builder_csrbank12_value0_w + attribute \src "ls180.v:2648.6-2648.33" + wire \builder_csrbank12_value0_we + attribute \src "ls180.v:2643.12-2643.38" + wire width 8 \builder_csrbank12_value1_r + attribute \src "ls180.v:2642.6-2642.33" + wire \builder_csrbank12_value1_re + attribute \src "ls180.v:2645.12-2645.38" + wire width 8 \builder_csrbank12_value1_w + attribute \src "ls180.v:2644.6-2644.33" + wire \builder_csrbank12_value1_we + attribute \src "ls180.v:2639.12-2639.38" + wire width 8 \builder_csrbank12_value2_r + attribute \src "ls180.v:2638.6-2638.33" + wire \builder_csrbank12_value2_re + attribute \src "ls180.v:2641.12-2641.38" + wire width 8 \builder_csrbank12_value2_w + attribute \src "ls180.v:2640.6-2640.33" + wire \builder_csrbank12_value2_we + attribute \src "ls180.v:2635.12-2635.38" + wire width 8 \builder_csrbank12_value3_r + attribute \src "ls180.v:2634.6-2634.33" + wire \builder_csrbank12_value3_re + attribute \src "ls180.v:2637.12-2637.38" + wire width 8 \builder_csrbank12_value3_w + attribute \src "ls180.v:2636.6-2636.33" + wire \builder_csrbank12_value3_we + attribute \src "ls180.v:2668.12-2668.42" + wire width 2 \builder_csrbank13_ev_enable0_r + attribute \src "ls180.v:2667.6-2667.37" + wire \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:2670.12-2670.42" + wire width 2 \builder_csrbank13_ev_enable0_w + attribute \src "ls180.v:2669.6-2669.37" + wire \builder_csrbank13_ev_enable0_we + attribute \src "ls180.v:2664.6-2664.33" + wire \builder_csrbank13_rxempty_r + attribute \src "ls180.v:2663.6-2663.34" + wire \builder_csrbank13_rxempty_re + attribute \src "ls180.v:2666.6-2666.33" + wire \builder_csrbank13_rxempty_w + attribute \src "ls180.v:2665.6-2665.34" + wire \builder_csrbank13_rxempty_we + attribute \src "ls180.v:2676.6-2676.32" + wire \builder_csrbank13_rxfull_r + attribute \src "ls180.v:2675.6-2675.33" + wire \builder_csrbank13_rxfull_re + attribute \src "ls180.v:2678.6-2678.32" + wire \builder_csrbank13_rxfull_w + attribute \src "ls180.v:2677.6-2677.33" + wire \builder_csrbank13_rxfull_we + attribute \src "ls180.v:2679.6-2679.27" + wire \builder_csrbank13_sel + attribute \src "ls180.v:2672.6-2672.33" + wire \builder_csrbank13_txempty_r + attribute \src "ls180.v:2671.6-2671.34" + wire \builder_csrbank13_txempty_re + attribute \src "ls180.v:2674.6-2674.33" + wire \builder_csrbank13_txempty_w + attribute \src "ls180.v:2673.6-2673.34" + wire \builder_csrbank13_txempty_we + attribute \src "ls180.v:2660.6-2660.32" + wire \builder_csrbank13_txfull_r + attribute \src "ls180.v:2659.6-2659.33" + wire \builder_csrbank13_txfull_re + attribute \src "ls180.v:2662.6-2662.32" + wire \builder_csrbank13_txfull_w + attribute \src "ls180.v:2661.6-2661.33" + wire \builder_csrbank13_txfull_we + attribute \src "ls180.v:2700.6-2700.27" + wire \builder_csrbank14_sel + attribute \src "ls180.v:2697.12-2697.44" + wire width 8 \builder_csrbank14_tuning_word0_r + attribute \src "ls180.v:2696.6-2696.39" + wire \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:2699.12-2699.44" + wire width 8 \builder_csrbank14_tuning_word0_w + attribute \src "ls180.v:2698.6-2698.39" + wire \builder_csrbank14_tuning_word0_we + attribute \src "ls180.v:2693.12-2693.44" + wire width 8 \builder_csrbank14_tuning_word1_r + attribute \src "ls180.v:2692.6-2692.39" + wire \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:2695.12-2695.44" + wire width 8 \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:2694.6-2694.39" + wire \builder_csrbank14_tuning_word1_we + attribute \src "ls180.v:2689.12-2689.44" + wire width 8 \builder_csrbank14_tuning_word2_r + attribute \src "ls180.v:2688.6-2688.39" + wire \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:2691.12-2691.44" + wire width 8 \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:2690.6-2690.39" + wire \builder_csrbank14_tuning_word2_we + attribute \src "ls180.v:2685.12-2685.44" + wire width 8 \builder_csrbank14_tuning_word3_r + attribute \src "ls180.v:2684.6-2684.39" + wire \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:2687.12-2687.44" + wire width 8 \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:2686.6-2686.39" + wire \builder_csrbank14_tuning_word3_we + attribute \src "ls180.v:2072.12-2072.34" + wire width 8 \builder_csrbank1_in0_r + attribute \src "ls180.v:2071.6-2071.29" + wire \builder_csrbank1_in0_re + attribute \src "ls180.v:2074.12-2074.34" + wire width 8 \builder_csrbank1_in0_w + attribute \src "ls180.v:2073.6-2073.29" + wire \builder_csrbank1_in0_we + attribute \src "ls180.v:2068.12-2068.34" + wire width 8 \builder_csrbank1_in1_r + attribute \src "ls180.v:2067.6-2067.29" + wire \builder_csrbank1_in1_re + attribute \src "ls180.v:2070.12-2070.34" + wire width 8 \builder_csrbank1_in1_w + attribute \src "ls180.v:2069.6-2069.29" + wire \builder_csrbank1_in1_we + attribute \src "ls180.v:2064.12-2064.34" + wire width 8 \builder_csrbank1_oe0_r + attribute \src "ls180.v:2063.6-2063.29" + wire \builder_csrbank1_oe0_re + attribute \src "ls180.v:2066.12-2066.34" + wire width 8 \builder_csrbank1_oe0_w + attribute \src "ls180.v:2065.6-2065.29" + wire \builder_csrbank1_oe0_we + attribute \src "ls180.v:2060.12-2060.34" + wire width 8 \builder_csrbank1_oe1_r + attribute \src "ls180.v:2059.6-2059.29" + wire \builder_csrbank1_oe1_re + attribute \src "ls180.v:2062.12-2062.34" + wire width 8 \builder_csrbank1_oe1_w + attribute \src "ls180.v:2061.6-2061.29" + wire \builder_csrbank1_oe1_we + attribute \src "ls180.v:2080.12-2080.35" + wire width 8 \builder_csrbank1_out0_r + attribute \src "ls180.v:2079.6-2079.30" + wire \builder_csrbank1_out0_re + attribute \src "ls180.v:2082.12-2082.35" + wire width 8 \builder_csrbank1_out0_w + attribute \src "ls180.v:2081.6-2081.30" + wire \builder_csrbank1_out0_we + attribute \src "ls180.v:2076.12-2076.35" + wire width 8 \builder_csrbank1_out1_r + attribute \src "ls180.v:2075.6-2075.30" + wire \builder_csrbank1_out1_re + attribute \src "ls180.v:2078.12-2078.35" + wire width 8 \builder_csrbank1_out1_w + attribute \src "ls180.v:2077.6-2077.30" + wire \builder_csrbank1_out1_we + attribute \src "ls180.v:2083.6-2083.26" + wire \builder_csrbank1_sel + attribute \src "ls180.v:2093.6-2093.26" + wire \builder_csrbank2_r_r + attribute \src "ls180.v:2092.6-2092.27" + wire \builder_csrbank2_r_re + attribute \src "ls180.v:2095.6-2095.26" + wire \builder_csrbank2_r_w + attribute \src "ls180.v:2094.6-2094.27" + wire \builder_csrbank2_r_we + attribute \src "ls180.v:2096.6-2096.26" + wire \builder_csrbank2_sel + attribute \src "ls180.v:2089.12-2089.33" + wire width 3 \builder_csrbank2_w0_r + attribute \src "ls180.v:2088.6-2088.28" + wire \builder_csrbank2_w0_re + attribute \src "ls180.v:2091.12-2091.33" + wire width 3 \builder_csrbank2_w0_w + attribute \src "ls180.v:2090.6-2090.28" + wire \builder_csrbank2_w0_we + attribute \src "ls180.v:2102.6-2102.32" + wire \builder_csrbank3_enable0_r + attribute \src "ls180.v:2101.6-2101.33" + wire \builder_csrbank3_enable0_re + attribute \src "ls180.v:2104.6-2104.32" + wire \builder_csrbank3_enable0_w + attribute \src "ls180.v:2103.6-2103.33" + wire \builder_csrbank3_enable0_we + attribute \src "ls180.v:2134.12-2134.38" + wire width 8 \builder_csrbank3_period0_r + attribute \src "ls180.v:2133.6-2133.33" + wire \builder_csrbank3_period0_re + attribute \src "ls180.v:2136.12-2136.38" + wire width 8 \builder_csrbank3_period0_w + attribute \src "ls180.v:2135.6-2135.33" + wire \builder_csrbank3_period0_we + attribute \src "ls180.v:2130.12-2130.38" + wire width 8 \builder_csrbank3_period1_r + attribute \src "ls180.v:2129.6-2129.33" + wire \builder_csrbank3_period1_re + attribute \src "ls180.v:2132.12-2132.38" + wire width 8 \builder_csrbank3_period1_w + attribute \src "ls180.v:2131.6-2131.33" + wire \builder_csrbank3_period1_we + attribute \src "ls180.v:2126.12-2126.38" + wire width 8 \builder_csrbank3_period2_r + attribute \src "ls180.v:2125.6-2125.33" + wire \builder_csrbank3_period2_re + attribute \src "ls180.v:2128.12-2128.38" + wire width 8 \builder_csrbank3_period2_w + attribute \src "ls180.v:2127.6-2127.33" + wire \builder_csrbank3_period2_we + attribute \src "ls180.v:2122.12-2122.38" + wire width 8 \builder_csrbank3_period3_r + attribute \src "ls180.v:2121.6-2121.33" + wire \builder_csrbank3_period3_re + attribute \src "ls180.v:2124.12-2124.38" + wire width 8 \builder_csrbank3_period3_w + attribute \src "ls180.v:2123.6-2123.33" + wire \builder_csrbank3_period3_we + attribute \src "ls180.v:2137.6-2137.26" + wire \builder_csrbank3_sel + attribute \src "ls180.v:2118.12-2118.37" + wire width 8 \builder_csrbank3_width0_r + attribute \src "ls180.v:2117.6-2117.32" + wire \builder_csrbank3_width0_re + attribute \src "ls180.v:2120.12-2120.37" + wire width 8 \builder_csrbank3_width0_w + attribute \src "ls180.v:2119.6-2119.32" + wire \builder_csrbank3_width0_we + attribute \src "ls180.v:2114.12-2114.37" + wire width 8 \builder_csrbank3_width1_r + attribute \src "ls180.v:2113.6-2113.32" + wire \builder_csrbank3_width1_re + attribute \src "ls180.v:2116.12-2116.37" + wire width 8 \builder_csrbank3_width1_w + attribute \src "ls180.v:2115.6-2115.32" + wire \builder_csrbank3_width1_we + attribute \src "ls180.v:2110.12-2110.37" + wire width 8 \builder_csrbank3_width2_r + attribute \src "ls180.v:2109.6-2109.32" + wire \builder_csrbank3_width2_re + attribute \src "ls180.v:2112.12-2112.37" + wire width 8 \builder_csrbank3_width2_w + attribute \src "ls180.v:2111.6-2111.32" + wire \builder_csrbank3_width2_we + attribute \src "ls180.v:2106.12-2106.37" + wire width 8 \builder_csrbank3_width3_r + attribute \src "ls180.v:2105.6-2105.32" + wire \builder_csrbank3_width3_re + attribute \src "ls180.v:2108.12-2108.37" + wire width 8 \builder_csrbank3_width3_w + attribute \src "ls180.v:2107.6-2107.32" + wire \builder_csrbank3_width3_we + attribute \src "ls180.v:2143.6-2143.32" + wire \builder_csrbank4_enable0_r + attribute \src "ls180.v:2142.6-2142.33" + wire \builder_csrbank4_enable0_re + attribute \src "ls180.v:2145.6-2145.32" + wire \builder_csrbank4_enable0_w + attribute \src "ls180.v:2144.6-2144.33" + wire \builder_csrbank4_enable0_we + attribute \src "ls180.v:2175.12-2175.38" + wire width 8 \builder_csrbank4_period0_r + attribute \src "ls180.v:2174.6-2174.33" + wire \builder_csrbank4_period0_re + attribute \src "ls180.v:2177.12-2177.38" + wire width 8 \builder_csrbank4_period0_w + attribute \src "ls180.v:2176.6-2176.33" + wire \builder_csrbank4_period0_we + attribute \src "ls180.v:2171.12-2171.38" + wire width 8 \builder_csrbank4_period1_r + attribute \src "ls180.v:2170.6-2170.33" + wire \builder_csrbank4_period1_re + attribute \src "ls180.v:2173.12-2173.38" + wire width 8 \builder_csrbank4_period1_w + attribute \src "ls180.v:2172.6-2172.33" + wire \builder_csrbank4_period1_we + attribute \src "ls180.v:2167.12-2167.38" + wire width 8 \builder_csrbank4_period2_r + attribute \src "ls180.v:2166.6-2166.33" + wire \builder_csrbank4_period2_re + attribute \src "ls180.v:2169.12-2169.38" + wire width 8 \builder_csrbank4_period2_w + attribute \src "ls180.v:2168.6-2168.33" + wire \builder_csrbank4_period2_we + attribute \src "ls180.v:2163.12-2163.38" + wire width 8 \builder_csrbank4_period3_r + attribute \src "ls180.v:2162.6-2162.33" + wire \builder_csrbank4_period3_re + attribute \src "ls180.v:2165.12-2165.38" + wire width 8 \builder_csrbank4_period3_w + attribute \src "ls180.v:2164.6-2164.33" + wire \builder_csrbank4_period3_we + attribute \src "ls180.v:2178.6-2178.26" + wire \builder_csrbank4_sel + attribute \src "ls180.v:2159.12-2159.37" + wire width 8 \builder_csrbank4_width0_r + attribute \src "ls180.v:2158.6-2158.32" + wire \builder_csrbank4_width0_re + attribute \src "ls180.v:2161.12-2161.37" + wire width 8 \builder_csrbank4_width0_w + attribute \src "ls180.v:2160.6-2160.32" + wire \builder_csrbank4_width0_we + attribute \src "ls180.v:2155.12-2155.37" + wire width 8 \builder_csrbank4_width1_r + attribute \src "ls180.v:2154.6-2154.32" + wire \builder_csrbank4_width1_re + attribute \src "ls180.v:2157.12-2157.37" + wire width 8 \builder_csrbank4_width1_w + attribute \src "ls180.v:2156.6-2156.32" + wire \builder_csrbank4_width1_we + attribute \src "ls180.v:2151.12-2151.37" + wire width 8 \builder_csrbank4_width2_r + attribute \src "ls180.v:2150.6-2150.32" + wire \builder_csrbank4_width2_re + attribute \src "ls180.v:2153.12-2153.37" + wire width 8 \builder_csrbank4_width2_w + attribute \src "ls180.v:2152.6-2152.32" + wire \builder_csrbank4_width2_we + attribute \src "ls180.v:2147.12-2147.37" + wire width 8 \builder_csrbank4_width3_r + attribute \src "ls180.v:2146.6-2146.32" + wire \builder_csrbank4_width3_re + attribute \src "ls180.v:2149.12-2149.37" + wire width 8 \builder_csrbank4_width3_w + attribute \src "ls180.v:2148.6-2148.32" + wire \builder_csrbank4_width3_we + attribute \src "ls180.v:2212.12-2212.40" + wire width 8 \builder_csrbank5_dma_base0_r + attribute \src "ls180.v:2211.6-2211.35" + wire \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:2214.12-2214.40" + wire width 8 \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:2213.6-2213.35" + wire \builder_csrbank5_dma_base0_we + attribute \src "ls180.v:2208.12-2208.40" + wire width 8 \builder_csrbank5_dma_base1_r + attribute \src "ls180.v:2207.6-2207.35" + wire \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:2210.12-2210.40" + wire width 8 \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:2209.6-2209.35" + wire \builder_csrbank5_dma_base1_we + attribute \src "ls180.v:2204.12-2204.40" + wire width 8 \builder_csrbank5_dma_base2_r + attribute \src "ls180.v:2203.6-2203.35" + wire \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:2206.12-2206.40" + wire width 8 \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:2205.6-2205.35" + wire \builder_csrbank5_dma_base2_we + attribute \src "ls180.v:2200.12-2200.40" + wire width 8 \builder_csrbank5_dma_base3_r + attribute \src "ls180.v:2199.6-2199.35" + wire \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:2202.12-2202.40" + wire width 8 \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:2201.6-2201.35" + wire \builder_csrbank5_dma_base3_we + attribute \src "ls180.v:2196.12-2196.40" + wire width 8 \builder_csrbank5_dma_base4_r + attribute \src "ls180.v:2195.6-2195.35" + wire \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:2198.12-2198.40" + wire width 8 \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:2197.6-2197.35" + wire \builder_csrbank5_dma_base4_we + attribute \src "ls180.v:2192.12-2192.40" + wire width 8 \builder_csrbank5_dma_base5_r + attribute \src "ls180.v:2191.6-2191.35" + wire \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:2194.12-2194.40" + wire width 8 \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:2193.6-2193.35" + wire \builder_csrbank5_dma_base5_we + attribute \src "ls180.v:2188.12-2188.40" + wire width 8 \builder_csrbank5_dma_base6_r + attribute \src "ls180.v:2187.6-2187.35" + wire \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:2190.12-2190.40" + wire width 8 \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:2189.6-2189.35" + wire \builder_csrbank5_dma_base6_we + attribute \src "ls180.v:2184.12-2184.40" + wire width 8 \builder_csrbank5_dma_base7_r + attribute \src "ls180.v:2183.6-2183.35" + wire \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:2186.12-2186.40" + wire width 8 \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:2185.6-2185.35" + wire \builder_csrbank5_dma_base7_we + attribute \src "ls180.v:2236.6-2236.33" + wire \builder_csrbank5_dma_done_r + attribute \src "ls180.v:2235.6-2235.34" + wire \builder_csrbank5_dma_done_re + attribute \src "ls180.v:2238.6-2238.33" + wire \builder_csrbank5_dma_done_w + attribute \src "ls180.v:2237.6-2237.34" + wire \builder_csrbank5_dma_done_we + attribute \src "ls180.v:2232.6-2232.36" + wire \builder_csrbank5_dma_enable0_r + attribute \src "ls180.v:2231.6-2231.37" + wire \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:2234.6-2234.36" + wire \builder_csrbank5_dma_enable0_w + attribute \src "ls180.v:2233.6-2233.37" + wire \builder_csrbank5_dma_enable0_we + attribute \src "ls180.v:2228.12-2228.42" + wire width 8 \builder_csrbank5_dma_length0_r + attribute \src "ls180.v:2227.6-2227.37" + wire \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:2230.12-2230.42" + wire width 8 \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:2229.6-2229.37" + wire \builder_csrbank5_dma_length0_we + attribute \src "ls180.v:2224.12-2224.42" + wire width 8 \builder_csrbank5_dma_length1_r + attribute \src "ls180.v:2223.6-2223.37" + wire \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:2226.12-2226.42" + wire width 8 \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:2225.6-2225.37" + wire \builder_csrbank5_dma_length1_we + attribute \src "ls180.v:2220.12-2220.42" + wire width 8 \builder_csrbank5_dma_length2_r + attribute \src "ls180.v:2219.6-2219.37" + wire \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:2222.12-2222.42" + wire width 8 \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:2221.6-2221.37" + wire \builder_csrbank5_dma_length2_we + attribute \src "ls180.v:2216.12-2216.42" + wire width 8 \builder_csrbank5_dma_length3_r + attribute \src "ls180.v:2215.6-2215.37" + wire \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:2218.12-2218.42" + wire width 8 \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:2217.6-2217.37" + wire \builder_csrbank5_dma_length3_we + attribute \src "ls180.v:2240.6-2240.34" + wire \builder_csrbank5_dma_loop0_r + attribute \src "ls180.v:2239.6-2239.35" + wire \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:2242.6-2242.34" + wire \builder_csrbank5_dma_loop0_w + attribute \src "ls180.v:2241.6-2241.35" + wire \builder_csrbank5_dma_loop0_we + attribute \src "ls180.v:2243.6-2243.26" + wire \builder_csrbank5_sel + attribute \src "ls180.v:2373.12-2373.43" + wire width 8 \builder_csrbank6_block_count0_r + attribute \src "ls180.v:2372.6-2372.38" + wire \builder_csrbank6_block_count0_re + attribute \src "ls180.v:2375.12-2375.43" + wire width 8 \builder_csrbank6_block_count0_w + attribute \src "ls180.v:2374.6-2374.38" + wire \builder_csrbank6_block_count0_we + attribute \src "ls180.v:2369.12-2369.43" + wire width 8 \builder_csrbank6_block_count1_r + attribute \src "ls180.v:2368.6-2368.38" + wire \builder_csrbank6_block_count1_re + attribute \src "ls180.v:2371.12-2371.43" + wire width 8 \builder_csrbank6_block_count1_w + attribute \src "ls180.v:2370.6-2370.38" + wire \builder_csrbank6_block_count1_we + attribute \src "ls180.v:2365.12-2365.43" + wire width 8 \builder_csrbank6_block_count2_r + attribute \src "ls180.v:2364.6-2364.38" + wire \builder_csrbank6_block_count2_re + attribute \src "ls180.v:2367.12-2367.43" + wire width 8 \builder_csrbank6_block_count2_w + attribute \src "ls180.v:2366.6-2366.38" + wire \builder_csrbank6_block_count2_we + attribute \src "ls180.v:2361.12-2361.43" + wire width 8 \builder_csrbank6_block_count3_r + attribute \src "ls180.v:2360.6-2360.38" + wire \builder_csrbank6_block_count3_re + attribute \src "ls180.v:2363.12-2363.43" + wire width 8 \builder_csrbank6_block_count3_w + attribute \src "ls180.v:2362.6-2362.38" + wire \builder_csrbank6_block_count3_we + attribute \src "ls180.v:2357.12-2357.44" + wire width 8 \builder_csrbank6_block_length0_r + attribute \src "ls180.v:2356.6-2356.39" + wire \builder_csrbank6_block_length0_re + attribute \src "ls180.v:2359.12-2359.44" + wire width 8 \builder_csrbank6_block_length0_w + attribute \src "ls180.v:2358.6-2358.39" + wire \builder_csrbank6_block_length0_we + attribute \src "ls180.v:2353.12-2353.44" + wire width 2 \builder_csrbank6_block_length1_r + attribute \src "ls180.v:2352.6-2352.39" + wire \builder_csrbank6_block_length1_re + attribute \src "ls180.v:2355.12-2355.44" + wire width 2 \builder_csrbank6_block_length1_w + attribute \src "ls180.v:2354.6-2354.39" + wire \builder_csrbank6_block_length1_we + attribute \src "ls180.v:2261.12-2261.44" + wire width 8 \builder_csrbank6_cmd_argument0_r + attribute \src "ls180.v:2260.6-2260.39" + wire \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:2263.12-2263.44" + wire width 8 \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:2262.6-2262.39" + wire \builder_csrbank6_cmd_argument0_we + attribute \src "ls180.v:2257.12-2257.44" + wire width 8 \builder_csrbank6_cmd_argument1_r + attribute \src "ls180.v:2256.6-2256.39" + wire \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:2259.12-2259.44" + wire width 8 \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:2258.6-2258.39" + wire \builder_csrbank6_cmd_argument1_we + attribute \src "ls180.v:2253.12-2253.44" + wire width 8 \builder_csrbank6_cmd_argument2_r + attribute \src "ls180.v:2252.6-2252.39" + wire \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:2255.12-2255.44" + wire width 8 \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:2254.6-2254.39" + wire \builder_csrbank6_cmd_argument2_we + attribute \src "ls180.v:2249.12-2249.44" + wire width 8 \builder_csrbank6_cmd_argument3_r + attribute \src "ls180.v:2248.6-2248.39" + wire \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:2251.12-2251.44" + wire width 8 \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:2250.6-2250.39" + wire \builder_csrbank6_cmd_argument3_we + attribute \src "ls180.v:2277.12-2277.43" + wire width 8 \builder_csrbank6_cmd_command0_r + attribute \src "ls180.v:2276.6-2276.38" + wire \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:2279.12-2279.43" + wire width 8 \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:2278.6-2278.38" + wire \builder_csrbank6_cmd_command0_we + attribute \src "ls180.v:2273.12-2273.43" + wire width 8 \builder_csrbank6_cmd_command1_r + attribute \src "ls180.v:2272.6-2272.38" + wire \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:2275.12-2275.43" + wire width 8 \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:2274.6-2274.38" + wire \builder_csrbank6_cmd_command1_we + attribute \src "ls180.v:2269.12-2269.43" + wire width 8 \builder_csrbank6_cmd_command2_r + attribute \src "ls180.v:2268.6-2268.38" + wire \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:2271.12-2271.43" + wire width 8 \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:2270.6-2270.38" + wire \builder_csrbank6_cmd_command2_we + attribute \src "ls180.v:2265.12-2265.43" + wire width 8 \builder_csrbank6_cmd_command3_r + attribute \src "ls180.v:2264.6-2264.38" + wire \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:2267.12-2267.43" + wire width 8 \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:2266.6-2266.38" + wire \builder_csrbank6_cmd_command3_we + attribute \src "ls180.v:2345.12-2345.40" + wire width 4 \builder_csrbank6_cmd_event_r + attribute \src "ls180.v:2344.6-2344.35" + wire \builder_csrbank6_cmd_event_re + attribute \src "ls180.v:2347.12-2347.40" + wire width 4 \builder_csrbank6_cmd_event_w + attribute \src "ls180.v:2346.6-2346.35" + wire \builder_csrbank6_cmd_event_we + attribute \src "ls180.v:2341.12-2341.44" + wire width 8 \builder_csrbank6_cmd_response0_r + attribute \src "ls180.v:2340.6-2340.39" + wire \builder_csrbank6_cmd_response0_re + attribute \src "ls180.v:2343.12-2343.44" + wire width 8 \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:2342.6-2342.39" + wire \builder_csrbank6_cmd_response0_we + attribute \src "ls180.v:2301.12-2301.45" + wire width 8 \builder_csrbank6_cmd_response10_r + attribute \src "ls180.v:2300.6-2300.40" + wire \builder_csrbank6_cmd_response10_re + attribute \src "ls180.v:2303.12-2303.45" + wire width 8 \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:2302.6-2302.40" + wire \builder_csrbank6_cmd_response10_we + attribute \src "ls180.v:2297.12-2297.45" + wire width 8 \builder_csrbank6_cmd_response11_r + attribute \src "ls180.v:2296.6-2296.40" + wire \builder_csrbank6_cmd_response11_re + attribute \src "ls180.v:2299.12-2299.45" + wire width 8 \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:2298.6-2298.40" + wire \builder_csrbank6_cmd_response11_we + attribute \src "ls180.v:2293.12-2293.45" + wire width 8 \builder_csrbank6_cmd_response12_r + attribute \src "ls180.v:2292.6-2292.40" + wire \builder_csrbank6_cmd_response12_re + attribute \src "ls180.v:2295.12-2295.45" + wire width 8 \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:2294.6-2294.40" + wire \builder_csrbank6_cmd_response12_we + attribute \src "ls180.v:2289.12-2289.45" + wire width 8 \builder_csrbank6_cmd_response13_r + attribute \src "ls180.v:2288.6-2288.40" + wire \builder_csrbank6_cmd_response13_re + attribute \src "ls180.v:2291.12-2291.45" + wire width 8 \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:2290.6-2290.40" + wire \builder_csrbank6_cmd_response13_we + attribute \src "ls180.v:2285.12-2285.45" + wire width 8 \builder_csrbank6_cmd_response14_r + attribute \src "ls180.v:2284.6-2284.40" + wire \builder_csrbank6_cmd_response14_re + attribute \src "ls180.v:2287.12-2287.45" + wire width 8 \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:2286.6-2286.40" + wire \builder_csrbank6_cmd_response14_we + attribute \src "ls180.v:2281.12-2281.45" + wire width 8 \builder_csrbank6_cmd_response15_r + attribute \src "ls180.v:2280.6-2280.40" + wire \builder_csrbank6_cmd_response15_re + attribute \src "ls180.v:2283.12-2283.45" + wire width 8 \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:2282.6-2282.40" + wire \builder_csrbank6_cmd_response15_we + attribute \src "ls180.v:2337.12-2337.44" + wire width 8 \builder_csrbank6_cmd_response1_r + attribute \src "ls180.v:2336.6-2336.39" + wire \builder_csrbank6_cmd_response1_re + attribute \src "ls180.v:2339.12-2339.44" + wire width 8 \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:2338.6-2338.39" + wire \builder_csrbank6_cmd_response1_we + attribute \src "ls180.v:2333.12-2333.44" + wire width 8 \builder_csrbank6_cmd_response2_r + attribute \src "ls180.v:2332.6-2332.39" + wire \builder_csrbank6_cmd_response2_re + attribute \src "ls180.v:2335.12-2335.44" + wire width 8 \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:2334.6-2334.39" + wire \builder_csrbank6_cmd_response2_we + attribute \src "ls180.v:2329.12-2329.44" + wire width 8 \builder_csrbank6_cmd_response3_r + attribute \src "ls180.v:2328.6-2328.39" + wire \builder_csrbank6_cmd_response3_re + attribute \src "ls180.v:2331.12-2331.44" + wire width 8 \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:2330.6-2330.39" + wire \builder_csrbank6_cmd_response3_we + attribute \src "ls180.v:2325.12-2325.44" + wire width 8 \builder_csrbank6_cmd_response4_r + attribute \src "ls180.v:2324.6-2324.39" + wire \builder_csrbank6_cmd_response4_re + attribute \src "ls180.v:2327.12-2327.44" + wire width 8 \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:2326.6-2326.39" + wire \builder_csrbank6_cmd_response4_we + attribute \src "ls180.v:2321.12-2321.44" + wire width 8 \builder_csrbank6_cmd_response5_r + attribute \src "ls180.v:2320.6-2320.39" + wire \builder_csrbank6_cmd_response5_re + attribute \src "ls180.v:2323.12-2323.44" + wire width 8 \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:2322.6-2322.39" + wire \builder_csrbank6_cmd_response5_we + attribute \src "ls180.v:2317.12-2317.44" + wire width 8 \builder_csrbank6_cmd_response6_r + attribute \src "ls180.v:2316.6-2316.39" + wire \builder_csrbank6_cmd_response6_re + attribute \src "ls180.v:2319.12-2319.44" + wire width 8 \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:2318.6-2318.39" + wire \builder_csrbank6_cmd_response6_we + attribute \src "ls180.v:2313.12-2313.44" + wire width 8 \builder_csrbank6_cmd_response7_r + attribute \src "ls180.v:2312.6-2312.39" + wire \builder_csrbank6_cmd_response7_re + attribute \src "ls180.v:2315.12-2315.44" + wire width 8 \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:2314.6-2314.39" + wire \builder_csrbank6_cmd_response7_we + attribute \src "ls180.v:2309.12-2309.44" + wire width 8 \builder_csrbank6_cmd_response8_r + attribute \src "ls180.v:2308.6-2308.39" + wire \builder_csrbank6_cmd_response8_re + attribute \src "ls180.v:2311.12-2311.44" + wire width 8 \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:2310.6-2310.39" + wire \builder_csrbank6_cmd_response8_we + attribute \src "ls180.v:2305.12-2305.44" + wire width 8 \builder_csrbank6_cmd_response9_r + attribute \src "ls180.v:2304.6-2304.39" + wire \builder_csrbank6_cmd_response9_re + attribute \src "ls180.v:2307.12-2307.44" + wire width 8 \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:2306.6-2306.39" + wire \builder_csrbank6_cmd_response9_we + attribute \src "ls180.v:2349.12-2349.41" + wire width 4 \builder_csrbank6_data_event_r + attribute \src "ls180.v:2348.6-2348.36" + wire \builder_csrbank6_data_event_re + attribute \src "ls180.v:2351.12-2351.41" + wire width 4 \builder_csrbank6_data_event_w + attribute \src "ls180.v:2350.6-2350.36" + wire \builder_csrbank6_data_event_we + attribute \src "ls180.v:2376.6-2376.26" + wire \builder_csrbank6_sel + attribute \src "ls180.v:2410.12-2410.40" + wire width 8 \builder_csrbank7_dma_base0_r + attribute \src "ls180.v:2409.6-2409.35" + wire \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:2412.12-2412.40" + wire width 8 \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:2411.6-2411.35" + wire \builder_csrbank7_dma_base0_we + attribute \src "ls180.v:2406.12-2406.40" + wire width 8 \builder_csrbank7_dma_base1_r + attribute \src "ls180.v:2405.6-2405.35" + wire \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:2408.12-2408.40" + wire width 8 \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:2407.6-2407.35" + wire \builder_csrbank7_dma_base1_we + attribute \src "ls180.v:2402.12-2402.40" + wire width 8 \builder_csrbank7_dma_base2_r + attribute \src "ls180.v:2401.6-2401.35" + wire \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:2404.12-2404.40" + wire width 8 \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:2403.6-2403.35" + wire \builder_csrbank7_dma_base2_we + attribute \src "ls180.v:2398.12-2398.40" + wire width 8 \builder_csrbank7_dma_base3_r + attribute \src "ls180.v:2397.6-2397.35" + wire \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:2400.12-2400.40" + wire width 8 \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:2399.6-2399.35" + wire \builder_csrbank7_dma_base3_we + attribute \src "ls180.v:2394.12-2394.40" + wire width 8 \builder_csrbank7_dma_base4_r + attribute \src "ls180.v:2393.6-2393.35" + wire \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:2396.12-2396.40" + wire width 8 \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:2395.6-2395.35" + wire \builder_csrbank7_dma_base4_we + attribute \src "ls180.v:2390.12-2390.40" + wire width 8 \builder_csrbank7_dma_base5_r + attribute \src "ls180.v:2389.6-2389.35" + wire \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:2392.12-2392.40" + wire width 8 \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:2391.6-2391.35" + wire \builder_csrbank7_dma_base5_we + attribute \src "ls180.v:2386.12-2386.40" + wire width 8 \builder_csrbank7_dma_base6_r + attribute \src "ls180.v:2385.6-2385.35" + wire \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:2388.12-2388.40" + wire width 8 \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:2387.6-2387.35" + wire \builder_csrbank7_dma_base6_we + attribute \src "ls180.v:2382.12-2382.40" + wire width 8 \builder_csrbank7_dma_base7_r + attribute \src "ls180.v:2381.6-2381.35" + wire \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:2384.12-2384.40" + wire width 8 \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:2383.6-2383.35" + wire \builder_csrbank7_dma_base7_we + attribute \src "ls180.v:2434.6-2434.33" + wire \builder_csrbank7_dma_done_r + attribute \src "ls180.v:2433.6-2433.34" + wire \builder_csrbank7_dma_done_re + attribute \src "ls180.v:2436.6-2436.33" + wire \builder_csrbank7_dma_done_w + attribute \src "ls180.v:2435.6-2435.34" + wire \builder_csrbank7_dma_done_we + attribute \src "ls180.v:2430.6-2430.36" + wire \builder_csrbank7_dma_enable0_r + attribute \src "ls180.v:2429.6-2429.37" + wire \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:2432.6-2432.36" + wire \builder_csrbank7_dma_enable0_w + attribute \src "ls180.v:2431.6-2431.37" + wire \builder_csrbank7_dma_enable0_we + attribute \src "ls180.v:2426.12-2426.42" + wire width 8 \builder_csrbank7_dma_length0_r + attribute \src "ls180.v:2425.6-2425.37" + wire \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:2428.12-2428.42" + wire width 8 \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:2427.6-2427.37" + wire \builder_csrbank7_dma_length0_we + attribute \src "ls180.v:2422.12-2422.42" + wire width 8 \builder_csrbank7_dma_length1_r + attribute \src "ls180.v:2421.6-2421.37" + wire \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:2424.12-2424.42" + wire width 8 \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:2423.6-2423.37" + wire \builder_csrbank7_dma_length1_we + attribute \src "ls180.v:2418.12-2418.42" + wire width 8 \builder_csrbank7_dma_length2_r + attribute \src "ls180.v:2417.6-2417.37" + wire \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:2420.12-2420.42" + wire width 8 \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:2419.6-2419.37" + wire \builder_csrbank7_dma_length2_we + attribute \src "ls180.v:2414.12-2414.42" + wire width 8 \builder_csrbank7_dma_length3_r + attribute \src "ls180.v:2413.6-2413.37" + wire \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:2416.12-2416.42" + wire width 8 \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:2415.6-2415.37" + wire \builder_csrbank7_dma_length3_we + attribute \src "ls180.v:2438.6-2438.34" + wire \builder_csrbank7_dma_loop0_r + attribute \src "ls180.v:2437.6-2437.35" + wire \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:2440.6-2440.34" + wire \builder_csrbank7_dma_loop0_w + attribute \src "ls180.v:2439.6-2439.35" + wire \builder_csrbank7_dma_loop0_we + attribute \src "ls180.v:2454.12-2454.42" + wire width 8 \builder_csrbank7_dma_offset0_r + attribute \src "ls180.v:2453.6-2453.37" + wire \builder_csrbank7_dma_offset0_re + attribute \src "ls180.v:2456.12-2456.42" + wire width 8 \builder_csrbank7_dma_offset0_w + attribute \src "ls180.v:2455.6-2455.37" + wire \builder_csrbank7_dma_offset0_we + attribute \src "ls180.v:2450.12-2450.42" + wire width 8 \builder_csrbank7_dma_offset1_r + attribute \src "ls180.v:2449.6-2449.37" + wire \builder_csrbank7_dma_offset1_re + attribute \src "ls180.v:2452.12-2452.42" + wire width 8 \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:2451.6-2451.37" + wire \builder_csrbank7_dma_offset1_we + attribute \src "ls180.v:2446.12-2446.42" + wire width 8 \builder_csrbank7_dma_offset2_r + attribute \src "ls180.v:2445.6-2445.37" + wire \builder_csrbank7_dma_offset2_re + attribute \src "ls180.v:2448.12-2448.42" + wire width 8 \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:2447.6-2447.37" + wire \builder_csrbank7_dma_offset2_we + attribute \src "ls180.v:2442.12-2442.42" + wire width 8 \builder_csrbank7_dma_offset3_r + attribute \src "ls180.v:2441.6-2441.37" + wire \builder_csrbank7_dma_offset3_re + attribute \src "ls180.v:2444.12-2444.42" + wire width 8 \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:2443.6-2443.37" + wire \builder_csrbank7_dma_offset3_we + attribute \src "ls180.v:2457.6-2457.26" + wire \builder_csrbank7_sel + attribute \src "ls180.v:2463.6-2463.36" + wire \builder_csrbank8_card_detect_r + attribute \src "ls180.v:2462.6-2462.37" + wire \builder_csrbank8_card_detect_re + attribute \src "ls180.v:2465.6-2465.36" + wire \builder_csrbank8_card_detect_w + attribute \src "ls180.v:2464.6-2464.37" + wire \builder_csrbank8_card_detect_we + attribute \src "ls180.v:2471.12-2471.47" + wire width 8 \builder_csrbank8_clocker_divider0_r + attribute \src "ls180.v:2470.6-2470.42" + wire \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:2473.12-2473.47" + wire width 8 \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:2472.6-2472.42" + wire \builder_csrbank8_clocker_divider0_we + attribute \src "ls180.v:2467.6-2467.41" + wire \builder_csrbank8_clocker_divider1_r + attribute \src "ls180.v:2466.6-2466.42" + wire \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:2469.6-2469.41" + wire \builder_csrbank8_clocker_divider1_w + attribute \src "ls180.v:2468.6-2468.42" + wire \builder_csrbank8_clocker_divider1_we + attribute \src "ls180.v:2474.6-2474.26" + wire \builder_csrbank8_sel + attribute \src "ls180.v:2480.12-2480.44" + wire width 4 \builder_csrbank9_dfii_control0_r + attribute \src "ls180.v:2479.6-2479.39" + wire \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:2482.12-2482.44" + wire width 4 \builder_csrbank9_dfii_control0_w + attribute \src "ls180.v:2481.6-2481.39" + wire \builder_csrbank9_dfii_control0_we + attribute \src "ls180.v:2492.12-2492.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_r + attribute \src "ls180.v:2491.6-2491.43" + wire \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:2494.12-2494.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:2493.6-2493.43" + wire \builder_csrbank9_dfii_pi0_address0_we + attribute \src "ls180.v:2488.12-2488.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_r + attribute \src "ls180.v:2487.6-2487.43" + wire \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:2490.12-2490.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_w + attribute \src "ls180.v:2489.6-2489.43" + wire \builder_csrbank9_dfii_pi0_address1_we + attribute \src "ls180.v:2496.12-2496.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r + attribute \src "ls180.v:2495.6-2495.44" + wire \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:2498.12-2498.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w + attribute \src "ls180.v:2497.6-2497.44" + wire \builder_csrbank9_dfii_pi0_baddress0_we + attribute \src "ls180.v:2484.12-2484.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_r + attribute \src "ls180.v:2483.6-2483.43" + wire \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:2486.12-2486.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_w + attribute \src "ls180.v:2485.6-2485.43" + wire \builder_csrbank9_dfii_pi0_command0_we + attribute \src "ls180.v:2512.12-2512.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r + attribute \src "ls180.v:2511.6-2511.42" + wire \builder_csrbank9_dfii_pi0_rddata0_re + attribute \src "ls180.v:2514.12-2514.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w + attribute \src "ls180.v:2513.6-2513.42" + wire \builder_csrbank9_dfii_pi0_rddata0_we + attribute \src "ls180.v:2508.12-2508.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r + attribute \src "ls180.v:2507.6-2507.42" + wire \builder_csrbank9_dfii_pi0_rddata1_re + attribute \src "ls180.v:2510.12-2510.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:2509.6-2509.42" + wire \builder_csrbank9_dfii_pi0_rddata1_we + attribute \src "ls180.v:2504.12-2504.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r + attribute \src "ls180.v:2503.6-2503.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:2506.12-2506.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:2505.6-2505.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_we + attribute \src "ls180.v:2500.12-2500.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r + attribute \src "ls180.v:2499.6-2499.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:2502.12-2502.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:2501.6-2501.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_we + attribute \src "ls180.v:2515.6-2515.26" + wire \builder_csrbank9_sel + attribute \src "ls180.v:2012.6-2012.18" + wire \builder_done + attribute \src "ls180.v:2010.5-2010.18" + wire \builder_error + attribute \src "ls180.v:2007.11-2007.24" + wire width 3 \builder_grant + attribute \src "ls180.v:2014.13-2014.44" + wire width 14 \builder_interface0_bank_bus_adr + attribute \src "ls180.v:2017.11-2017.44" + wire width 8 \builder_interface0_bank_bus_dat_r + attribute \src "ls180.v:2016.12-2016.45" + wire width 8 \builder_interface0_bank_bus_dat_w + attribute \src "ls180.v:2015.6-2015.36" + wire \builder_interface0_bank_bus_we + attribute \src "ls180.v:2516.13-2516.45" + wire width 14 \builder_interface10_bank_bus_adr + attribute \src "ls180.v:2519.11-2519.45" + wire width 8 \builder_interface10_bank_bus_dat_r + attribute \src "ls180.v:2518.12-2518.46" + wire width 8 \builder_interface10_bank_bus_dat_w + attribute \src "ls180.v:2517.6-2517.37" + wire \builder_interface10_bank_bus_we + attribute \src "ls180.v:2549.13-2549.45" + wire width 14 \builder_interface11_bank_bus_adr + attribute \src "ls180.v:2552.11-2552.45" + wire width 8 \builder_interface11_bank_bus_dat_r + attribute \src "ls180.v:2551.12-2551.46" + wire width 8 \builder_interface11_bank_bus_dat_w + attribute \src "ls180.v:2550.6-2550.37" + wire \builder_interface11_bank_bus_we + attribute \src "ls180.v:2590.13-2590.45" + wire width 14 \builder_interface12_bank_bus_adr + attribute \src "ls180.v:2593.11-2593.45" + wire width 8 \builder_interface12_bank_bus_dat_r + attribute \src "ls180.v:2592.12-2592.46" + wire width 8 \builder_interface12_bank_bus_dat_w + attribute \src "ls180.v:2591.6-2591.37" + wire \builder_interface12_bank_bus_we + attribute \src "ls180.v:2655.13-2655.45" + wire width 14 \builder_interface13_bank_bus_adr + attribute \src "ls180.v:2658.11-2658.45" + wire width 8 \builder_interface13_bank_bus_dat_r + attribute \src "ls180.v:2657.12-2657.46" + wire width 8 \builder_interface13_bank_bus_dat_w + attribute \src "ls180.v:2656.6-2656.37" + wire \builder_interface13_bank_bus_we + attribute \src "ls180.v:2680.13-2680.45" + wire width 14 \builder_interface14_bank_bus_adr + attribute \src "ls180.v:2683.11-2683.45" + wire width 8 \builder_interface14_bank_bus_dat_r + attribute \src "ls180.v:2682.12-2682.46" + wire width 8 \builder_interface14_bank_bus_dat_w + attribute \src "ls180.v:2681.6-2681.37" + wire \builder_interface14_bank_bus_we + attribute \src "ls180.v:2055.13-2055.44" + wire width 14 \builder_interface1_bank_bus_adr + attribute \src "ls180.v:2058.11-2058.44" + wire width 8 \builder_interface1_bank_bus_dat_r + attribute \src "ls180.v:2057.12-2057.45" + wire width 8 \builder_interface1_bank_bus_dat_w + attribute \src "ls180.v:2056.6-2056.36" + wire \builder_interface1_bank_bus_we + attribute \src "ls180.v:2084.13-2084.44" + wire width 14 \builder_interface2_bank_bus_adr + attribute \src "ls180.v:2087.11-2087.44" + wire width 8 \builder_interface2_bank_bus_dat_r + attribute \src "ls180.v:2086.12-2086.45" + wire width 8 \builder_interface2_bank_bus_dat_w + attribute \src "ls180.v:2085.6-2085.36" + wire \builder_interface2_bank_bus_we + attribute \src "ls180.v:2097.13-2097.44" + wire width 14 \builder_interface3_bank_bus_adr + attribute \src "ls180.v:2100.11-2100.44" + wire width 8 \builder_interface3_bank_bus_dat_r + attribute \src "ls180.v:2099.12-2099.45" + wire width 8 \builder_interface3_bank_bus_dat_w + attribute \src "ls180.v:2098.6-2098.36" + wire \builder_interface3_bank_bus_we + attribute \src "ls180.v:2138.13-2138.44" + wire width 14 \builder_interface4_bank_bus_adr + attribute \src "ls180.v:2141.11-2141.44" + wire width 8 \builder_interface4_bank_bus_dat_r + attribute \src "ls180.v:2140.12-2140.45" + wire width 8 \builder_interface4_bank_bus_dat_w + attribute \src "ls180.v:2139.6-2139.36" + wire \builder_interface4_bank_bus_we + attribute \src "ls180.v:2179.13-2179.44" + wire width 14 \builder_interface5_bank_bus_adr + attribute \src "ls180.v:2182.11-2182.44" + wire width 8 \builder_interface5_bank_bus_dat_r + attribute \src "ls180.v:2181.12-2181.45" + wire width 8 \builder_interface5_bank_bus_dat_w + attribute \src "ls180.v:2180.6-2180.36" + wire \builder_interface5_bank_bus_we + attribute \src "ls180.v:2244.13-2244.44" + wire width 14 \builder_interface6_bank_bus_adr + attribute \src "ls180.v:2247.11-2247.44" + wire width 8 \builder_interface6_bank_bus_dat_r + attribute \src "ls180.v:2246.12-2246.45" + wire width 8 \builder_interface6_bank_bus_dat_w + attribute \src "ls180.v:2245.6-2245.36" + wire \builder_interface6_bank_bus_we + attribute \src "ls180.v:2377.13-2377.44" + wire width 14 \builder_interface7_bank_bus_adr + attribute \src "ls180.v:2380.11-2380.44" + wire width 8 \builder_interface7_bank_bus_dat_r + attribute \src "ls180.v:2379.12-2379.45" + wire width 8 \builder_interface7_bank_bus_dat_w + attribute \src "ls180.v:2378.6-2378.36" + wire \builder_interface7_bank_bus_we + attribute \src "ls180.v:2458.13-2458.44" + wire width 14 \builder_interface8_bank_bus_adr + attribute \src "ls180.v:2461.11-2461.44" + wire width 8 \builder_interface8_bank_bus_dat_r + attribute \src "ls180.v:2460.12-2460.45" + wire width 8 \builder_interface8_bank_bus_dat_w + attribute \src "ls180.v:2459.6-2459.36" + wire \builder_interface8_bank_bus_we + attribute \src "ls180.v:2475.13-2475.44" + wire width 14 \builder_interface9_bank_bus_adr + attribute \src "ls180.v:2478.11-2478.44" + wire width 8 \builder_interface9_bank_bus_dat_r + attribute \src "ls180.v:2477.12-2477.45" + wire width 8 \builder_interface9_bank_bus_dat_w + attribute \src "ls180.v:2476.6-2476.36" + wire \builder_interface9_bank_bus_we + attribute \src "ls180.v:1972.12-1972.35" + wire width 14 \builder_libresocsim_adr + attribute \src "ls180.v:2709.12-2709.47" + wire width 14 \builder_libresocsim_adr_next_value1 + attribute \src "ls180.v:2710.5-2710.43" + wire \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:1990.5-1990.48" + wire \builder_libresocsim_converted_interface_ack + attribute \src "ls180.v:1984.13-1984.56" + wire width 30 \builder_libresocsim_converted_interface_adr + attribute \src "ls180.v:1993.12-1993.55" + wire width 2 \builder_libresocsim_converted_interface_bte + attribute \src "ls180.v:1992.12-1992.55" + wire width 3 \builder_libresocsim_converted_interface_cti + attribute \src "ls180.v:1988.6-1988.49" + wire \builder_libresocsim_converted_interface_cyc + attribute \src "ls180.v:1986.12-1986.57" + wire width 64 \builder_libresocsim_converted_interface_dat_r + attribute \src "ls180.v:1985.13-1985.58" + wire width 64 \builder_libresocsim_converted_interface_dat_w + attribute \src "ls180.v:1994.5-1994.48" + wire \builder_libresocsim_converted_interface_err + attribute \src "ls180.v:1987.12-1987.55" + wire width 8 \builder_libresocsim_converted_interface_sel + attribute \src "ls180.v:1989.6-1989.49" + wire \builder_libresocsim_converted_interface_stb + attribute \src "ls180.v:1991.6-1991.48" + wire \builder_libresocsim_converted_interface_we + attribute \src "ls180.v:1975.12-1975.37" + wire width 8 \builder_libresocsim_dat_r + attribute \src "ls180.v:1974.11-1974.36" + wire width 8 \builder_libresocsim_dat_w + attribute \src "ls180.v:2707.11-2707.48" + wire width 8 \builder_libresocsim_dat_w_next_value0 + attribute \src "ls180.v:2708.5-2708.45" + wire \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:1973.5-1973.27" + wire \builder_libresocsim_we + attribute \src "ls180.v:2711.5-2711.39" + wire \builder_libresocsim_we_next_value2 + attribute \src "ls180.v:2712.5-2712.42" + wire \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:1982.5-1982.37" + wire \builder_libresocsim_wishbone_ack + attribute \src "ls180.v:1976.12-1976.44" + wire width 30 \builder_libresocsim_wishbone_adr + attribute \src "ls180.v:1980.5-1980.37" + wire \builder_libresocsim_wishbone_cyc + attribute \src "ls180.v:1978.12-1978.46" + wire width 32 \builder_libresocsim_wishbone_dat_r + attribute \src "ls180.v:1977.12-1977.46" + wire width 32 \builder_libresocsim_wishbone_dat_w + attribute \src "ls180.v:1979.11-1979.43" + wire width 4 \builder_libresocsim_wishbone_sel + attribute \src "ls180.v:1981.5-1981.37" + wire \builder_libresocsim_wishbone_stb + attribute \src "ls180.v:1983.5-1983.36" + wire \builder_libresocsim_wishbone_we + attribute \src "ls180.v:1875.5-1875.20" + wire \builder_locked0 + attribute \src "ls180.v:1876.5-1876.20" + wire \builder_locked1 + attribute \src "ls180.v:1877.5-1877.20" + wire \builder_locked2 + attribute \src "ls180.v:1878.5-1878.20" + wire \builder_locked3 + attribute \src "ls180.v:1862.11-1862.41" + wire width 3 \builder_multiplexer_next_state + attribute \src "ls180.v:1861.11-1861.36" + wire width 3 \builder_multiplexer_state + attribute \no_retiming "true" + attribute \src "ls180.v:2816.32-2816.59" + wire \builder_multiregimpl0_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2817.32-2817.59" + wire \builder_multiregimpl0_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2836.32-2836.60" + wire \builder_multiregimpl10_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2837.32-2837.60" + wire \builder_multiregimpl10_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2838.32-2838.60" + wire \builder_multiregimpl11_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2839.32-2839.60" + wire \builder_multiregimpl11_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2840.32-2840.60" + wire \builder_multiregimpl12_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2841.32-2841.60" + wire \builder_multiregimpl12_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2842.32-2842.60" + wire \builder_multiregimpl13_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2843.32-2843.60" + wire \builder_multiregimpl13_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2844.32-2844.60" + wire \builder_multiregimpl14_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2845.32-2845.60" + wire \builder_multiregimpl14_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2846.32-2846.60" + wire \builder_multiregimpl15_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2847.32-2847.60" + wire \builder_multiregimpl15_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2848.32-2848.60" + wire \builder_multiregimpl16_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2849.32-2849.60" + wire \builder_multiregimpl16_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2818.32-2818.59" + wire \builder_multiregimpl1_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2819.32-2819.59" + wire \builder_multiregimpl1_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2820.32-2820.59" + wire \builder_multiregimpl2_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2821.32-2821.59" + wire \builder_multiregimpl2_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2822.32-2822.59" + wire \builder_multiregimpl3_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2823.32-2823.59" + wire \builder_multiregimpl3_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2824.32-2824.59" + wire \builder_multiregimpl4_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2825.32-2825.59" + wire \builder_multiregimpl4_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2826.32-2826.59" + wire \builder_multiregimpl5_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2827.32-2827.59" + wire \builder_multiregimpl5_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2828.32-2828.59" + wire \builder_multiregimpl6_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2829.32-2829.59" + wire \builder_multiregimpl6_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2830.32-2830.59" + wire \builder_multiregimpl7_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2831.32-2831.59" + wire \builder_multiregimpl7_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2832.32-2832.59" + wire \builder_multiregimpl8_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2833.32-2833.59" + wire \builder_multiregimpl8_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2834.32-2834.59" + wire \builder_multiregimpl9_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2835.32-2835.59" + wire \builder_multiregimpl9_regs1 + attribute \src "ls180.v:1880.5-1880.36" + wire \builder_new_master_rdata_valid0 + attribute \src "ls180.v:1881.5-1881.36" + wire \builder_new_master_rdata_valid1 + attribute \src "ls180.v:1882.5-1882.36" + wire \builder_new_master_rdata_valid2 + attribute \src "ls180.v:1883.5-1883.36" + wire \builder_new_master_rdata_valid3 + attribute \src "ls180.v:1879.5-1879.35" + wire \builder_new_master_wdata_ready + attribute \src "ls180.v:2706.11-2706.29" + wire width 2 \builder_next_state + attribute \src "ls180.v:1852.11-1852.39" + wire width 2 \builder_refresher_next_state + attribute \src "ls180.v:1851.11-1851.34" + wire width 2 \builder_refresher_state + attribute \src "ls180.v:2006.12-2006.27" + wire width 5 \builder_request + attribute \src "ls180.v:1865.6-1865.28" + wire \builder_roundrobin0_ce + attribute \src "ls180.v:1864.6-1864.31" + wire \builder_roundrobin0_grant + attribute \src "ls180.v:1863.6-1863.33" + wire \builder_roundrobin0_request + attribute \src "ls180.v:1868.6-1868.28" + wire \builder_roundrobin1_ce + attribute \src "ls180.v:1867.6-1867.31" + wire \builder_roundrobin1_grant + attribute \src "ls180.v:1866.6-1866.33" + wire \builder_roundrobin1_request + attribute \src "ls180.v:1871.6-1871.28" + wire \builder_roundrobin2_ce + attribute \src "ls180.v:1870.6-1870.31" + wire \builder_roundrobin2_grant + attribute \src "ls180.v:1869.6-1869.33" + wire \builder_roundrobin2_request + attribute \src "ls180.v:1874.6-1874.28" + wire \builder_roundrobin3_ce + attribute \src "ls180.v:1873.6-1873.31" + wire \builder_roundrobin3_grant + attribute \src "ls180.v:1872.6-1872.33" + wire \builder_roundrobin3_request + attribute \src "ls180.v:1961.11-1961.44" + wire width 2 \builder_sdblock2memdma_next_state + attribute \src "ls180.v:1960.11-1960.39" + wire width 2 \builder_sdblock2memdma_state + attribute \src "ls180.v:1929.5-1929.50" + wire \builder_sdcore_crcupstreaminserter_next_state + attribute \src "ls180.v:1928.5-1928.45" + wire \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:1941.11-1941.40" + wire width 3 \builder_sdcore_fsm_next_state + attribute \src "ls180.v:1940.11-1940.35" + wire width 3 \builder_sdcore_fsm_state + attribute \src "ls180.v:1965.5-1965.42" + wire \builder_sdmem2blockdma_fsm_next_state + attribute \src "ls180.v:1964.5-1964.37" + wire \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:1969.11-1969.58" + wire width 2 \builder_sdmem2blockdma_resetinserter_next_state + attribute \src "ls180.v:1968.11-1968.53" + wire width 2 \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:1917.11-1917.39" + wire width 3 \builder_sdphy_fsm_next_state + attribute \src "ls180.v:1916.11-1916.34" + wire width 3 \builder_sdphy_fsm_state + attribute \src "ls180.v:1905.11-1905.45" + wire width 3 \builder_sdphy_sdphycmdr_next_state + attribute \src "ls180.v:1904.11-1904.40" + wire width 3 \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:1901.11-1901.45" + wire width 2 \builder_sdphy_sdphycmdw_next_state + attribute \src "ls180.v:1900.11-1900.40" + wire width 2 \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:1913.5-1913.39" + wire \builder_sdphy_sdphycrcr_next_state + attribute \src "ls180.v:1912.5-1912.34" + wire \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:1921.11-1921.46" + wire width 3 \builder_sdphy_sdphydatar_next_state + attribute \src "ls180.v:1920.11-1920.41" + wire width 3 \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:1897.5-1897.39" + wire \builder_sdphy_sdphyinit_next_state + attribute \src "ls180.v:1896.5-1896.34" + wire \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:2001.5-2001.23" + wire \builder_shared_ack + attribute \src "ls180.v:1995.13-1995.31" + wire width 30 \builder_shared_adr + attribute \src "ls180.v:2004.12-2004.30" + wire width 2 \builder_shared_bte + attribute \src "ls180.v:2003.12-2003.30" + wire width 3 \builder_shared_cti + attribute \src "ls180.v:1999.6-1999.24" + wire \builder_shared_cyc + attribute \src "ls180.v:1997.12-1997.32" + wire width 32 \builder_shared_dat_r + attribute \src "ls180.v:1996.13-1996.33" + wire width 32 \builder_shared_dat_w + attribute \src "ls180.v:2005.6-2005.24" + wire \builder_shared_err + attribute \src "ls180.v:1998.12-1998.30" + wire width 4 \builder_shared_sel + attribute \src "ls180.v:2000.6-2000.24" + wire \builder_shared_stb + attribute \src "ls180.v:2002.6-2002.23" + wire \builder_shared_we + attribute \src "ls180.v:2008.12-2008.29" + wire width 13 \builder_slave_sel + attribute \src "ls180.v:2009.12-2009.31" + wire width 13 \builder_slave_sel_r + attribute \src "ls180.v:1889.11-1889.40" + wire width 2 \builder_spimaster0_next_state + attribute \src "ls180.v:1888.11-1888.35" + wire width 2 \builder_spimaster0_state + attribute \src "ls180.v:1893.11-1893.40" + wire width 2 \builder_spimaster1_next_state + attribute \src "ls180.v:1892.11-1892.35" + wire width 2 \builder_spimaster1_state + attribute \src "ls180.v:2705.11-2705.24" + wire width 2 \builder_state + attribute \src "ls180.v:2758.5-2758.32" + wire \builder_sync_f_array_muxed0 + attribute \src "ls180.v:2759.5-2759.32" + wire \builder_sync_f_array_muxed1 + attribute \src "ls180.v:2751.11-2751.40" + wire width 2 \builder_sync_rhs_array_muxed0 + attribute \src "ls180.v:2752.12-2752.41" + wire width 13 \builder_sync_rhs_array_muxed1 + attribute \src "ls180.v:2753.5-2753.34" + wire \builder_sync_rhs_array_muxed2 + attribute \src "ls180.v:2754.5-2754.34" + wire \builder_sync_rhs_array_muxed3 + attribute \src "ls180.v:2755.5-2755.34" + wire \builder_sync_rhs_array_muxed4 + attribute \src "ls180.v:2756.5-2756.34" + wire \builder_sync_rhs_array_muxed5 + attribute \src "ls180.v:2757.5-2757.34" + wire \builder_sync_rhs_array_muxed6 + attribute \src "ls180.v:2011.6-2011.18" + wire \builder_wait + attribute \src "ls180.v:30.19-30.23" + wire width 3 input 26 \eint + attribute \src "ls180.v:194.12-194.18" + wire width 3 \eint_1 + attribute \src "ls180.v:5.20-5.26" + wire width 16 input 1 \gpio_i + attribute \src "ls180.v:6.20-6.26" + wire width 16 output 2 \gpio_o + attribute \src "ls180.v:7.20-7.27" + wire width 16 output 3 \gpio_oe + attribute \src "ls180.v:8.14-8.21" + wire output 4 \i2c_scl + attribute \src "ls180.v:9.13-9.22" + wire input 5 \i2c_sda_i + attribute \src "ls180.v:10.14-10.23" + wire output 6 \i2c_sda_o + attribute \src "ls180.v:11.14-11.24" + wire output 7 \i2c_sda_oe + attribute \src "ls180.v:49.13-49.21" + wire input 45 \jtag_tck + attribute \src "ls180.v:50.13-50.21" + wire input 46 \jtag_tdi + attribute \src "ls180.v:51.14-51.22" + wire output 47 \jtag_tdo + attribute \src "ls180.v:48.13-48.21" + wire input 44 \jtag_tms + attribute \src "ls180.v:937.6-937.18" + wire \main_ack_cmd + attribute \src "ls180.v:939.6-939.20" + wire \main_ack_rdata + attribute \src "ls180.v:938.6-938.20" + wire \main_ack_wdata + attribute \src "ls180.v:935.5-935.22" + wire \main_cmd_consumed + attribute \src "ls180.v:318.5-318.28" + wire \main_converter0_counter + attribute \src "ls180.v:1841.5-1841.50" + wire \main_converter0_counter_converter0_next_value + attribute \src "ls180.v:1842.5-1842.53" + wire \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:320.12-320.33" + wire width 64 \main_converter0_dat_r + attribute \src "ls180.v:319.6-319.27" + wire \main_converter0_reset + attribute \src "ls180.v:317.5-317.25" + wire \main_converter0_skip + attribute \src "ls180.v:333.5-333.28" + wire \main_converter1_counter + attribute \src "ls180.v:1845.5-1845.50" + wire \main_converter1_counter_converter1_next_value + attribute \src "ls180.v:1846.5-1846.53" + wire \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:335.12-335.33" + wire width 64 \main_converter1_dat_r + attribute \src "ls180.v:334.6-334.27" + wire \main_converter1_reset + attribute \src "ls180.v:332.5-332.25" + wire \main_converter1_skip + attribute \src "ls180.v:932.5-932.27" + wire \main_converter_counter + attribute \src "ls180.v:1886.5-1886.48" + wire \main_converter_counter_converter_next_value + attribute \src "ls180.v:1887.5-1887.51" + wire \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:934.12-934.32" + wire width 32 \main_converter_dat_r + attribute \src "ls180.v:933.6-933.26" + wire \main_converter_reset + attribute \src "ls180.v:931.5-931.24" + wire \main_converter_skip + attribute \src "ls180.v:349.6-349.23" + wire \main_dfi_p0_act_n + attribute \src "ls180.v:340.13-340.32" + wire width 13 \main_dfi_p0_address + attribute \src "ls180.v:341.12-341.28" + wire width 2 \main_dfi_p0_bank + attribute \src "ls180.v:342.6-342.23" + wire \main_dfi_p0_cas_n + attribute \src "ls180.v:346.6-346.21" + wire \main_dfi_p0_cke + attribute \src "ls180.v:343.6-343.22" + wire \main_dfi_p0_cs_n + attribute \src "ls180.v:347.6-347.21" + wire \main_dfi_p0_odt + attribute \src "ls180.v:344.6-344.23" + wire \main_dfi_p0_ras_n + attribute \src "ls180.v:354.12-354.30" + wire width 16 \main_dfi_p0_rddata + attribute \src "ls180.v:353.6-353.27" + wire \main_dfi_p0_rddata_en + attribute \src "ls180.v:355.5-355.29" + wire \main_dfi_p0_rddata_valid + attribute \src "ls180.v:348.6-348.25" + wire \main_dfi_p0_reset_n + attribute \src "ls180.v:345.6-345.22" + wire \main_dfi_p0_we_n + attribute \src "ls180.v:350.13-350.31" + wire width 16 \main_dfi_p0_wrdata + attribute \src "ls180.v:351.6-351.27" + wire \main_dfi_p0_wrdata_en + attribute \src "ls180.v:352.12-352.35" + wire width 2 \main_dfi_p0_wrdata_mask + attribute \src "ls180.v:1172.12-1172.22" + wire width 24 \main_dummy + attribute \src "ls180.v:1082.12-1082.45" + wire width 16 \main_gpiotristateasic0_oe_storage + attribute \src "ls180.v:1084.12-1084.46" + wire width 16 \main_gpiotristateasic0_out_storage + attribute \src "ls180.v:1085.13-1085.42" + wire width 16 \main_gpiotristateasic0_pads_i + attribute \src "ls180.v:1086.13-1086.42" + wire width 16 \main_gpiotristateasic0_pads_o + attribute \src "ls180.v:1087.13-1087.43" + wire width 16 \main_gpiotristateasic0_pads_oe + attribute \src "ls180.v:1083.12-1083.41" + wire width 16 \main_gpiotristateasic0_status + attribute \src "ls180.v:1089.5-1089.33" + wire \main_gpiotristateasic1_oe_re + attribute \src "ls180.v:1088.12-1088.45" + wire width 16 \main_gpiotristateasic1_oe_storage + attribute \src "ls180.v:1093.5-1093.34" + wire \main_gpiotristateasic1_out_re + attribute \src "ls180.v:1092.12-1092.46" + wire width 16 \main_gpiotristateasic1_out_storage + attribute \src "ls180.v:1094.13-1094.42" + wire width 16 \main_gpiotristateasic1_pads_i + attribute \src "ls180.v:1095.13-1095.42" + wire width 16 \main_gpiotristateasic1_pads_o + attribute \src "ls180.v:1096.13-1096.43" + wire width 16 \main_gpiotristateasic1_pads_oe + attribute \src "ls180.v:1090.12-1090.41" + wire width 16 \main_gpiotristateasic1_status + attribute \src "ls180.v:1091.6-1091.31" + wire \main_gpiotristateasic1_we + attribute \src "ls180.v:1194.6-1194.17" + wire \main_i2c_oe + attribute \src "ls180.v:1197.5-1197.16" + wire \main_i2c_re + attribute \src "ls180.v:1193.6-1193.18" + wire \main_i2c_scl + attribute \src "ls180.v:1195.6-1195.19" + wire \main_i2c_sda0 + attribute \src "ls180.v:1198.6-1198.19" + wire \main_i2c_sda1 + attribute \src "ls180.v:1199.6-1199.21" + wire \main_i2c_status + attribute \src "ls180.v:1196.11-1196.27" + wire width 3 \main_i2c_storage + attribute \src "ls180.v:1200.6-1200.17" + wire \main_i2c_we + attribute \src "ls180.v:339.5-339.17" + wire \main_int_rst + attribute \src "ls180.v:1660.6-1660.29" + wire \main_interface0_bus_ack + attribute \src "ls180.v:1654.13-1654.36" + wire width 32 \main_interface0_bus_adr + attribute \src "ls180.v:1663.11-1663.34" + wire width 2 \main_interface0_bus_bte + attribute \src "ls180.v:1662.11-1662.34" + wire width 3 \main_interface0_bus_cti + attribute \src "ls180.v:1658.6-1658.29" + wire \main_interface0_bus_cyc + attribute \src "ls180.v:1656.13-1656.38" + wire width 64 \main_interface0_bus_dat_r + attribute \src "ls180.v:1655.13-1655.38" + wire width 64 \main_interface0_bus_dat_w + attribute \src "ls180.v:1664.6-1664.29" + wire \main_interface0_bus_err + attribute \src "ls180.v:1657.12-1657.35" + wire width 8 \main_interface0_bus_sel + attribute \src "ls180.v:1659.6-1659.29" + wire \main_interface0_bus_stb + attribute \src "ls180.v:1661.6-1661.28" + wire \main_interface0_bus_we + attribute \src "ls180.v:312.5-312.44" + wire \main_interface0_converted_interface_ack + attribute \src "ls180.v:306.13-306.52" + wire width 30 \main_interface0_converted_interface_adr + attribute \src "ls180.v:315.12-315.51" + wire width 2 \main_interface0_converted_interface_bte + attribute \src "ls180.v:314.12-314.51" + wire width 3 \main_interface0_converted_interface_cti + attribute \src "ls180.v:310.6-310.45" + wire \main_interface0_converted_interface_cyc + attribute \src "ls180.v:308.13-308.54" + wire width 64 \main_interface0_converted_interface_dat_r + attribute \src "ls180.v:307.13-307.54" + wire width 64 \main_interface0_converted_interface_dat_w + attribute \src "ls180.v:316.5-316.44" + wire \main_interface0_converted_interface_err + attribute \src "ls180.v:309.12-309.51" + wire width 8 \main_interface0_converted_interface_sel + attribute \src "ls180.v:311.6-311.45" + wire \main_interface0_converted_interface_stb + attribute \src "ls180.v:313.6-313.44" + wire \main_interface0_converted_interface_we + attribute \src "ls180.v:252.5-252.32" + wire \main_interface0_ram_bus_ack + attribute \src "ls180.v:246.13-246.40" + wire width 30 \main_interface0_ram_bus_adr + attribute \src "ls180.v:255.12-255.39" + wire width 2 \main_interface0_ram_bus_bte + attribute \src "ls180.v:254.12-254.39" + wire width 3 \main_interface0_ram_bus_cti + attribute \src "ls180.v:250.6-250.33" + wire \main_interface0_ram_bus_cyc + attribute \src "ls180.v:248.13-248.42" + wire width 64 \main_interface0_ram_bus_dat_r + attribute \src "ls180.v:247.13-247.42" + wire width 64 \main_interface0_ram_bus_dat_w + attribute \src "ls180.v:256.5-256.32" + wire \main_interface0_ram_bus_err + attribute \src "ls180.v:249.12-249.39" + wire width 8 \main_interface0_ram_bus_sel + attribute \src "ls180.v:251.6-251.33" + wire \main_interface0_ram_bus_stb + attribute \src "ls180.v:253.6-253.32" + wire \main_interface0_ram_bus_we + attribute \src "ls180.v:1751.6-1751.29" + wire \main_interface1_bus_ack + attribute \src "ls180.v:1745.12-1745.35" + wire width 32 \main_interface1_bus_adr + attribute \src "ls180.v:1754.11-1754.34" + wire width 2 \main_interface1_bus_bte + attribute \src "ls180.v:1753.11-1753.34" + wire width 3 \main_interface1_bus_cti + attribute \src "ls180.v:1749.5-1749.28" + wire \main_interface1_bus_cyc + attribute \src "ls180.v:1747.13-1747.38" + wire width 64 \main_interface1_bus_dat_r + attribute \src "ls180.v:1746.12-1746.37" + wire width 64 \main_interface1_bus_dat_w + attribute \src "ls180.v:1755.6-1755.29" + wire \main_interface1_bus_err + attribute \src "ls180.v:1748.11-1748.34" + wire width 8 \main_interface1_bus_sel + attribute \src "ls180.v:1750.5-1750.28" + wire \main_interface1_bus_stb + attribute \src "ls180.v:1752.5-1752.27" + wire \main_interface1_bus_we + attribute \src "ls180.v:327.5-327.44" + wire \main_interface1_converted_interface_ack + attribute \src "ls180.v:321.13-321.52" + wire width 30 \main_interface1_converted_interface_adr + attribute \src "ls180.v:330.12-330.51" + wire width 2 \main_interface1_converted_interface_bte + attribute \src "ls180.v:329.12-329.51" + wire width 3 \main_interface1_converted_interface_cti + attribute \src "ls180.v:325.6-325.45" + wire \main_interface1_converted_interface_cyc + attribute \src "ls180.v:323.13-323.54" + wire width 64 \main_interface1_converted_interface_dat_r + attribute \src "ls180.v:322.13-322.54" + wire width 64 \main_interface1_converted_interface_dat_w + attribute \src "ls180.v:331.5-331.44" + wire \main_interface1_converted_interface_err + attribute \src "ls180.v:324.12-324.51" + wire width 8 \main_interface1_converted_interface_sel + attribute \src "ls180.v:326.6-326.45" + wire \main_interface1_converted_interface_stb + attribute \src "ls180.v:328.6-328.44" + wire \main_interface1_converted_interface_we + attribute \src "ls180.v:267.5-267.32" + wire \main_interface1_ram_bus_ack + attribute \src "ls180.v:261.13-261.40" + wire width 30 \main_interface1_ram_bus_adr + attribute \src "ls180.v:270.12-270.39" + wire width 2 \main_interface1_ram_bus_bte + attribute \src "ls180.v:269.12-269.39" + wire width 3 \main_interface1_ram_bus_cti + attribute \src "ls180.v:265.6-265.33" + wire \main_interface1_ram_bus_cyc + attribute \src "ls180.v:263.13-263.42" + wire width 64 \main_interface1_ram_bus_dat_r + attribute \src "ls180.v:262.13-262.42" + wire width 64 \main_interface1_ram_bus_dat_w + attribute \src "ls180.v:271.5-271.32" + wire \main_interface1_ram_bus_err + attribute \src "ls180.v:264.12-264.39" + wire width 8 \main_interface1_ram_bus_sel + attribute \src "ls180.v:266.6-266.33" + wire \main_interface1_ram_bus_stb + attribute \src "ls180.v:268.6-268.32" + wire \main_interface1_ram_bus_we + attribute \src "ls180.v:282.5-282.32" + wire \main_interface2_ram_bus_ack + attribute \src "ls180.v:276.13-276.40" + wire width 30 \main_interface2_ram_bus_adr + attribute \src "ls180.v:285.12-285.39" + wire width 2 \main_interface2_ram_bus_bte + attribute \src "ls180.v:284.12-284.39" + wire width 3 \main_interface2_ram_bus_cti + attribute \src "ls180.v:280.6-280.33" + wire \main_interface2_ram_bus_cyc + attribute \src "ls180.v:278.13-278.42" + wire width 64 \main_interface2_ram_bus_dat_r + attribute \src "ls180.v:277.13-277.42" + wire width 64 \main_interface2_ram_bus_dat_w + attribute \src "ls180.v:286.5-286.32" + wire \main_interface2_ram_bus_err + attribute \src "ls180.v:279.12-279.39" + wire width 8 \main_interface2_ram_bus_sel + attribute \src "ls180.v:281.6-281.33" + wire \main_interface2_ram_bus_stb + attribute \src "ls180.v:283.6-283.32" + wire \main_interface2_ram_bus_we + attribute \src "ls180.v:297.5-297.32" + wire \main_interface3_ram_bus_ack + attribute \src "ls180.v:291.13-291.40" + wire width 30 \main_interface3_ram_bus_adr + attribute \src "ls180.v:300.12-300.39" + wire width 2 \main_interface3_ram_bus_bte + attribute \src "ls180.v:299.12-299.39" + wire width 3 \main_interface3_ram_bus_cti + attribute \src "ls180.v:295.6-295.33" + wire \main_interface3_ram_bus_cyc + attribute \src "ls180.v:293.13-293.42" + wire width 64 \main_interface3_ram_bus_dat_r + attribute \src "ls180.v:292.13-292.42" + wire width 64 \main_interface3_ram_bus_dat_w + attribute \src "ls180.v:301.5-301.32" + wire \main_interface3_ram_bus_err + attribute \src "ls180.v:294.12-294.39" + wire width 8 \main_interface3_ram_bus_sel + attribute \src "ls180.v:296.6-296.33" + wire \main_interface3_ram_bus_stb + attribute \src "ls180.v:298.6-298.32" + wire \main_interface3_ram_bus_we + attribute \src "ls180.v:215.12-215.32" + wire width 6 \main_libresocsim_adr + attribute \src "ls180.v:62.6-62.32" + wire \main_libresocsim_bus_error + attribute \src "ls180.v:63.12-63.39" + wire width 32 \main_libresocsim_bus_errors + attribute \src "ls180.v:59.13-59.47" + wire width 32 \main_libresocsim_bus_errors_status + attribute \src "ls180.v:60.6-60.36" + wire \main_libresocsim_bus_errors_we + attribute \src "ls180.v:216.13-216.35" + wire width 64 \main_libresocsim_dat_r + attribute \src "ls180.v:218.13-218.35" + wire width 64 \main_libresocsim_dat_w + attribute \src "ls180.v:224.5-224.27" + wire \main_libresocsim_en_re + attribute \src "ls180.v:223.5-223.32" + wire \main_libresocsim_en_storage + attribute \src "ls180.v:240.6-240.45" + wire \main_libresocsim_eventmanager_pending_r + attribute \src "ls180.v:239.6-239.46" + wire \main_libresocsim_eventmanager_pending_re + attribute \src "ls180.v:242.6-242.45" + wire \main_libresocsim_eventmanager_pending_w + attribute \src "ls180.v:241.6-241.46" + wire \main_libresocsim_eventmanager_pending_we + attribute \src "ls180.v:244.5-244.37" + wire \main_libresocsim_eventmanager_re + attribute \src "ls180.v:236.6-236.44" + wire \main_libresocsim_eventmanager_status_r + attribute \src "ls180.v:235.6-235.45" + wire \main_libresocsim_eventmanager_status_re + attribute \src "ls180.v:238.6-238.44" + wire \main_libresocsim_eventmanager_status_w + attribute \src "ls180.v:237.6-237.45" + wire \main_libresocsim_eventmanager_status_we + attribute \src "ls180.v:243.5-243.42" + wire \main_libresocsim_eventmanager_storage + attribute \src "ls180.v:229.6-229.26" + wire \main_libresocsim_irq + attribute \src "ls180.v:165.6-165.32" + wire \main_libresocsim_libresoc0 + attribute \src "ls180.v:166.6-166.32" + wire \main_libresocsim_libresoc1 + attribute \src "ls180.v:167.13-167.39" + wire width 64 \main_libresocsim_libresoc2 + attribute \src "ls180.v:169.12-169.45" + wire width 2 \main_libresocsim_libresoc_clk_sel + attribute \src "ls180.v:171.13-171.67" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i + attribute \src "ls180.v:172.13-172.67" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o + attribute \src "ls180.v:173.13-173.68" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe + attribute \src "ls180.v:174.6-174.61" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + attribute \src "ls180.v:175.6-175.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + attribute \src "ls180.v:176.6-176.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + attribute \src "ls180.v:177.6-177.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + attribute \src "ls180.v:195.6-195.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + attribute \src "ls180.v:196.6-196.66" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + attribute \src "ls180.v:197.6-197.66" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + attribute \src "ls180.v:198.6-198.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + attribute \src "ls180.v:182.13-182.68" + wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a + attribute \src "ls180.v:191.12-191.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba + attribute \src "ls180.v:188.6-188.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + attribute \src "ls180.v:190.6-190.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + attribute \src "ls180.v:189.6-189.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + attribute \src "ls180.v:192.12-192.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm + attribute \src "ls180.v:183.13-183.71" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i + attribute \src "ls180.v:184.13-184.71" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o + attribute \src "ls180.v:185.6-185.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + attribute \src "ls180.v:187.6-187.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + attribute \src "ls180.v:186.6-186.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + attribute \src "ls180.v:199.6-199.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + attribute \src "ls180.v:201.6-201.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + attribute \src "ls180.v:202.6-202.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + attribute \src "ls180.v:200.6-200.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + attribute \src "ls180.v:178.6-178.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + attribute \src "ls180.v:180.6-180.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + attribute \src "ls180.v:181.6-181.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + attribute \src "ls180.v:179.6-179.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + attribute \src "ls180.v:72.6-72.40" + wire \main_libresocsim_libresoc_dbus_ack + attribute \src "ls180.v:66.13-66.47" + wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:75.11-75.45" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:74.11-74.45" + wire width 3 \main_libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:70.6-70.40" + wire \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:68.13-68.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_r + attribute \src "ls180.v:67.13-67.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:76.6-76.40" + wire \main_libresocsim_libresoc_dbus_err + attribute \src "ls180.v:69.12-69.46" + wire width 8 \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:71.6-71.40" + wire \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:73.6-73.39" + wire \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:83.6-83.40" + wire \main_libresocsim_libresoc_ibus_ack + attribute \src "ls180.v:77.13-77.47" + wire width 29 \main_libresocsim_libresoc_ibus_adr + attribute \src "ls180.v:86.11-86.45" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:85.11-85.45" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:81.6-81.40" + wire \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:79.13-79.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_r + attribute \src "ls180.v:78.13-78.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:87.6-87.40" + wire \main_libresocsim_libresoc_ibus_err + attribute \src "ls180.v:80.12-80.46" + wire width 8 \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:82.6-82.40" + wire \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:84.6-84.39" + wire \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:123.6-123.46" + wire \main_libresocsim_libresoc_interface0_ack + attribute \src "ls180.v:117.13-117.53" + wire width 29 \main_libresocsim_libresoc_interface0_adr + attribute \src "ls180.v:126.12-126.52" + wire width 2 \main_libresocsim_libresoc_interface0_bte + attribute \src "ls180.v:125.12-125.52" + wire width 3 \main_libresocsim_libresoc_interface0_cti + attribute \src "ls180.v:121.6-121.46" + wire \main_libresocsim_libresoc_interface0_cyc + attribute \src "ls180.v:119.13-119.55" + wire width 64 \main_libresocsim_libresoc_interface0_dat_r + attribute \src "ls180.v:118.13-118.55" + wire width 64 \main_libresocsim_libresoc_interface0_dat_w + attribute \src "ls180.v:127.6-127.46" + wire \main_libresocsim_libresoc_interface0_err + attribute \src "ls180.v:120.12-120.52" + wire width 8 \main_libresocsim_libresoc_interface0_sel + attribute \src "ls180.v:122.6-122.46" + wire \main_libresocsim_libresoc_interface0_stb + attribute \src "ls180.v:124.6-124.45" + wire \main_libresocsim_libresoc_interface0_we + attribute \src "ls180.v:134.6-134.46" + wire \main_libresocsim_libresoc_interface1_ack + attribute \src "ls180.v:128.13-128.53" + wire width 29 \main_libresocsim_libresoc_interface1_adr + attribute \src "ls180.v:137.12-137.52" + wire width 2 \main_libresocsim_libresoc_interface1_bte + attribute \src "ls180.v:136.12-136.52" + wire width 3 \main_libresocsim_libresoc_interface1_cti + attribute \src "ls180.v:132.6-132.46" + wire \main_libresocsim_libresoc_interface1_cyc + attribute \src "ls180.v:130.13-130.55" + wire width 64 \main_libresocsim_libresoc_interface1_dat_r + attribute \src "ls180.v:129.13-129.55" + wire width 64 \main_libresocsim_libresoc_interface1_dat_w + attribute \src "ls180.v:138.6-138.46" + wire \main_libresocsim_libresoc_interface1_err + attribute \src "ls180.v:131.12-131.52" + wire width 8 \main_libresocsim_libresoc_interface1_sel + attribute \src "ls180.v:133.6-133.46" + wire \main_libresocsim_libresoc_interface1_stb + attribute \src "ls180.v:135.6-135.45" + wire \main_libresocsim_libresoc_interface1_we + attribute \src "ls180.v:145.6-145.46" + wire \main_libresocsim_libresoc_interface2_ack + attribute \src "ls180.v:139.13-139.53" + wire width 29 \main_libresocsim_libresoc_interface2_adr + attribute \src "ls180.v:148.12-148.52" + wire width 2 \main_libresocsim_libresoc_interface2_bte + attribute \src "ls180.v:147.12-147.52" + wire width 3 \main_libresocsim_libresoc_interface2_cti + attribute \src "ls180.v:143.6-143.46" + wire \main_libresocsim_libresoc_interface2_cyc + attribute \src "ls180.v:141.13-141.55" + wire width 64 \main_libresocsim_libresoc_interface2_dat_r + attribute \src "ls180.v:140.13-140.55" + wire width 64 \main_libresocsim_libresoc_interface2_dat_w + attribute \src "ls180.v:149.6-149.46" + wire \main_libresocsim_libresoc_interface2_err + attribute \src "ls180.v:142.12-142.52" + wire width 8 \main_libresocsim_libresoc_interface2_sel + attribute \src "ls180.v:144.6-144.46" + wire \main_libresocsim_libresoc_interface2_stb + attribute \src "ls180.v:146.6-146.45" + wire \main_libresocsim_libresoc_interface2_we + attribute \src "ls180.v:156.6-156.46" + wire \main_libresocsim_libresoc_interface3_ack + attribute \src "ls180.v:150.13-150.53" + wire width 29 \main_libresocsim_libresoc_interface3_adr + attribute \src "ls180.v:159.12-159.52" + wire width 2 \main_libresocsim_libresoc_interface3_bte + attribute \src "ls180.v:158.12-158.52" + wire width 3 \main_libresocsim_libresoc_interface3_cti + attribute \src "ls180.v:154.6-154.46" + wire \main_libresocsim_libresoc_interface3_cyc + attribute \src "ls180.v:152.13-152.55" + wire width 64 \main_libresocsim_libresoc_interface3_dat_r + attribute \src "ls180.v:151.13-151.55" + wire width 64 \main_libresocsim_libresoc_interface3_dat_w + attribute \src "ls180.v:160.6-160.46" + wire \main_libresocsim_libresoc_interface3_err + attribute \src "ls180.v:153.12-153.52" + wire width 8 \main_libresocsim_libresoc_interface3_sel + attribute \src "ls180.v:155.6-155.46" + wire \main_libresocsim_libresoc_interface3_stb + attribute \src "ls180.v:157.6-157.45" + wire \main_libresocsim_libresoc_interface3_we + attribute \src "ls180.v:65.12-65.47" + wire width 16 \main_libresocsim_libresoc_interrupt + attribute \src "ls180.v:161.6-161.40" + wire \main_libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:163.6-163.40" + wire \main_libresocsim_libresoc_jtag_tdi + attribute \src "ls180.v:164.6-164.40" + wire \main_libresocsim_libresoc_jtag_tdo + attribute \src "ls180.v:162.6-162.40" + wire \main_libresocsim_libresoc_jtag_tms + attribute \src "ls180.v:112.6-112.43" + wire \main_libresocsim_libresoc_jtag_wb_ack + attribute \src "ls180.v:106.13-106.50" + wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:115.11-115.48" + wire width 2 \main_libresocsim_libresoc_jtag_wb_bte + attribute \src "ls180.v:114.11-114.48" + wire width 3 \main_libresocsim_libresoc_jtag_wb_cti + attribute \src "ls180.v:110.6-110.43" + wire \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:108.13-108.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r + attribute \src "ls180.v:107.13-107.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:116.6-116.43" + wire \main_libresocsim_libresoc_jtag_wb_err + attribute \src "ls180.v:109.12-109.49" + wire width 8 \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:111.6-111.43" + wire \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:113.6-113.42" + wire \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:168.6-168.40" + wire \main_libresocsim_libresoc_pll_18_o + attribute \src "ls180.v:170.6-170.41" + wire \main_libresocsim_libresoc_pll_lck_o + attribute \src "ls180.v:64.6-64.37" + wire \main_libresocsim_libresoc_reset + attribute \src "ls180.v:94.6-94.44" + wire \main_libresocsim_libresoc_xics_icp_ack + attribute \src "ls180.v:88.12-88.50" + wire width 30 \main_libresocsim_libresoc_xics_icp_adr + attribute \src "ls180.v:92.5-92.43" + wire \main_libresocsim_libresoc_xics_icp_cyc + attribute \src "ls180.v:90.13-90.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r + attribute \src "ls180.v:89.12-89.52" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w + attribute \src "ls180.v:96.6-96.44" + wire \main_libresocsim_libresoc_xics_icp_err + attribute \src "ls180.v:91.11-91.49" + wire width 4 \main_libresocsim_libresoc_xics_icp_sel + attribute \src "ls180.v:93.5-93.43" + wire \main_libresocsim_libresoc_xics_icp_stb + attribute \src "ls180.v:95.5-95.42" + wire \main_libresocsim_libresoc_xics_icp_we + attribute \src "ls180.v:103.6-103.44" + wire \main_libresocsim_libresoc_xics_ics_ack + attribute \src "ls180.v:97.12-97.50" + wire width 30 \main_libresocsim_libresoc_xics_ics_adr + attribute \src "ls180.v:101.5-101.43" + wire \main_libresocsim_libresoc_xics_ics_cyc + attribute \src "ls180.v:99.13-99.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r + attribute \src "ls180.v:98.12-98.52" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w + attribute \src "ls180.v:105.6-105.44" + wire \main_libresocsim_libresoc_xics_ics_err + attribute \src "ls180.v:100.11-100.49" + wire width 4 \main_libresocsim_libresoc_xics_ics_sel + attribute \src "ls180.v:102.5-102.43" + wire \main_libresocsim_libresoc_xics_ics_stb + attribute \src "ls180.v:104.5-104.42" + wire \main_libresocsim_libresoc_xics_ics_we + attribute \src "ls180.v:220.5-220.29" + wire \main_libresocsim_load_re + attribute \src "ls180.v:219.12-219.41" + wire width 32 \main_libresocsim_load_storage + attribute \src "ls180.v:210.5-210.33" + wire \main_libresocsim_ram_bus_ack + attribute \src "ls180.v:204.13-204.41" + wire width 30 \main_libresocsim_ram_bus_adr + attribute \src "ls180.v:213.12-213.40" + wire width 2 \main_libresocsim_ram_bus_bte + attribute \src "ls180.v:212.12-212.40" + wire width 3 \main_libresocsim_ram_bus_cti + attribute \src "ls180.v:208.6-208.34" + wire \main_libresocsim_ram_bus_cyc + attribute \src "ls180.v:206.13-206.43" + wire width 64 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:205.13-205.43" + wire width 64 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:214.5-214.33" + wire \main_libresocsim_ram_bus_err + attribute \src "ls180.v:207.12-207.40" + wire width 8 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:209.6-209.34" + wire \main_libresocsim_ram_bus_stb + attribute \src "ls180.v:211.6-211.33" + wire \main_libresocsim_ram_bus_we + attribute \src "ls180.v:222.5-222.31" + wire \main_libresocsim_reload_re + attribute \src "ls180.v:221.12-221.43" + wire width 32 \main_libresocsim_reload_storage + attribute \src "ls180.v:61.6-61.28" + wire \main_libresocsim_reset + attribute \src "ls180.v:56.5-56.30" + wire \main_libresocsim_reset_re + attribute \src "ls180.v:55.5-55.35" + wire \main_libresocsim_reset_storage + attribute \src "ls180.v:58.5-58.32" + wire \main_libresocsim_scratch_re + attribute \src "ls180.v:57.12-57.44" + wire width 32 \main_libresocsim_scratch_storage + attribute \src "ls180.v:226.5-226.37" + wire \main_libresocsim_update_value_re + attribute \src "ls180.v:225.5-225.42" + wire \main_libresocsim_update_value_storage + attribute \src "ls180.v:245.12-245.34" + wire width 32 \main_libresocsim_value + attribute \src "ls180.v:227.12-227.41" + wire width 32 \main_libresocsim_value_status + attribute \src "ls180.v:228.6-228.31" + wire \main_libresocsim_value_we + attribute \src "ls180.v:217.11-217.30" + wire width 8 \main_libresocsim_we + attribute \src "ls180.v:233.5-233.32" + wire \main_libresocsim_zero_clear + attribute \src "ls180.v:234.5-234.38" + wire \main_libresocsim_zero_old_trigger + attribute \src "ls180.v:231.5-231.34" + wire \main_libresocsim_zero_pending + attribute \src "ls180.v:230.6-230.34" + wire \main_libresocsim_zero_status + attribute \src "ls180.v:232.6-232.35" + wire \main_libresocsim_zero_trigger + attribute \src "ls180.v:929.6-929.26" + wire \main_litedram_wb_ack + attribute \src "ls180.v:923.12-923.32" + wire width 30 \main_litedram_wb_adr + attribute \src "ls180.v:927.5-927.25" + wire \main_litedram_wb_cyc + attribute \src "ls180.v:925.13-925.35" + wire width 16 \main_litedram_wb_dat_r + attribute \src "ls180.v:924.12-924.34" + wire width 16 \main_litedram_wb_dat_w + attribute \src "ls180.v:926.11-926.31" + wire width 2 \main_litedram_wb_sel + attribute \src "ls180.v:928.5-928.25" + wire \main_litedram_wb_stb + attribute \src "ls180.v:930.5-930.24" + wire \main_litedram_wb_we + attribute \src "ls180.v:1171.13-1171.20" + wire width 24 \main_nc + attribute \src "ls180.v:890.6-890.24" + wire \main_port_cmd_last + attribute \src "ls180.v:892.13-892.39" + wire width 24 \main_port_cmd_payload_addr + attribute \src "ls180.v:891.6-891.30" + wire \main_port_cmd_payload_we + attribute \src "ls180.v:889.6-889.25" + wire \main_port_cmd_ready + attribute \src "ls180.v:888.6-888.25" + wire \main_port_cmd_valid + attribute \src "ls180.v:887.6-887.21" + wire \main_port_flush + attribute \src "ls180.v:899.13-899.41" + wire width 16 \main_port_rdata_payload_data + attribute \src "ls180.v:898.6-898.27" + wire \main_port_rdata_ready + attribute \src "ls180.v:897.6-897.27" + wire \main_port_rdata_valid + attribute \src "ls180.v:895.13-895.41" + wire width 16 \main_port_wdata_payload_data + attribute \src "ls180.v:896.12-896.38" + wire width 2 \main_port_wdata_payload_we + attribute \src "ls180.v:894.6-894.27" + wire \main_port_wdata_ready + attribute \src "ls180.v:893.6-893.27" + wire \main_port_wdata_valid + attribute \src "ls180.v:1176.12-1176.29" + wire width 32 \main_pwm0_counter + attribute \src "ls180.v:1173.6-1173.22" + wire \main_pwm0_enable + attribute \src "ls180.v:1178.5-1178.24" + wire \main_pwm0_enable_re + attribute \src "ls180.v:1177.5-1177.29" + wire \main_pwm0_enable_storage + attribute \src "ls180.v:1175.13-1175.29" + wire width 32 \main_pwm0_period + attribute \src "ls180.v:1182.5-1182.24" + wire \main_pwm0_period_re + attribute \src "ls180.v:1181.12-1181.36" + wire width 32 \main_pwm0_period_storage + attribute \src "ls180.v:1174.13-1174.28" + wire width 32 \main_pwm0_width + attribute \src "ls180.v:1180.5-1180.23" + wire \main_pwm0_width_re + attribute \src "ls180.v:1179.12-1179.35" + wire width 32 \main_pwm0_width_storage + attribute \src "ls180.v:1186.12-1186.29" + wire width 32 \main_pwm1_counter + attribute \src "ls180.v:1183.6-1183.22" + wire \main_pwm1_enable + attribute \src "ls180.v:1188.5-1188.24" + wire \main_pwm1_enable_re + attribute \src "ls180.v:1187.5-1187.29" + wire \main_pwm1_enable_storage + attribute \src "ls180.v:1185.13-1185.29" + wire width 32 \main_pwm1_period + attribute \src "ls180.v:1192.5-1192.24" + wire \main_pwm1_period_re + attribute \src "ls180.v:1191.12-1191.36" + wire width 32 \main_pwm1_period_storage + attribute \src "ls180.v:1184.13-1184.28" + wire width 32 \main_pwm1_width + attribute \src "ls180.v:1190.5-1190.23" + wire \main_pwm1_width_re + attribute \src "ls180.v:1189.12-1189.35" + wire width 32 \main_pwm1_width_storage + attribute \src "ls180.v:356.11-356.25" + wire width 3 \main_rddata_en + attribute \src "ls180.v:1714.11-1714.43" + wire width 3 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1715.6-1715.42" + wire \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:1705.6-1705.43" + wire \main_sdblock2mem_converter_sink_first + attribute \src "ls180.v:1706.6-1706.42" + wire \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:1707.12-1707.56" + wire width 8 \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:1704.6-1704.43" + wire \main_sdblock2mem_converter_sink_ready + attribute \src "ls180.v:1703.6-1703.43" + wire \main_sdblock2mem_converter_sink_valid + attribute \src "ls180.v:1710.5-1710.44" + wire \main_sdblock2mem_converter_source_first + attribute \src "ls180.v:1711.5-1711.43" + wire \main_sdblock2mem_converter_source_last + attribute \src "ls180.v:1712.12-1712.58" + wire width 64 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1713.11-1713.70" + wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1709.6-1709.45" + wire \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:1708.6-1708.45" + wire \main_sdblock2mem_converter_source_valid + attribute \src "ls180.v:1716.5-1716.42" + wire \main_sdblock2mem_converter_strobe_all + attribute \src "ls180.v:1689.11-1689.40" + wire width 5 \main_sdblock2mem_fifo_consume + attribute \src "ls180.v:1694.6-1694.35" + wire \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:1698.6-1698.41" + wire \main_sdblock2mem_fifo_fifo_in_first + attribute \src "ls180.v:1699.6-1699.40" + wire \main_sdblock2mem_fifo_fifo_in_last + attribute \src "ls180.v:1697.12-1697.54" + wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data + attribute \src "ls180.v:1701.6-1701.42" + wire \main_sdblock2mem_fifo_fifo_out_first + attribute \src "ls180.v:1702.6-1702.41" + wire \main_sdblock2mem_fifo_fifo_out_last + attribute \src "ls180.v:1700.12-1700.55" + wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data + attribute \src "ls180.v:1686.11-1686.38" + wire width 6 \main_sdblock2mem_fifo_level + attribute \src "ls180.v:1688.11-1688.40" + wire width 5 \main_sdblock2mem_fifo_produce + attribute \src "ls180.v:1695.12-1695.44" + wire width 5 \main_sdblock2mem_fifo_rdport_adr + attribute \src "ls180.v:1696.12-1696.46" + wire width 10 \main_sdblock2mem_fifo_rdport_dat_r + attribute \src "ls180.v:1687.5-1687.34" + wire \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:1672.6-1672.38" + wire \main_sdblock2mem_fifo_sink_first + attribute \src "ls180.v:1673.6-1673.37" + wire \main_sdblock2mem_fifo_sink_last + attribute \src "ls180.v:1674.12-1674.51" + wire width 8 \main_sdblock2mem_fifo_sink_payload_data + attribute \src "ls180.v:1671.6-1671.38" + wire \main_sdblock2mem_fifo_sink_ready + attribute \src "ls180.v:1670.6-1670.38" + wire \main_sdblock2mem_fifo_sink_valid + attribute \src "ls180.v:1677.6-1677.40" + wire \main_sdblock2mem_fifo_source_first + attribute \src "ls180.v:1678.6-1678.39" + wire \main_sdblock2mem_fifo_source_last + attribute \src "ls180.v:1679.12-1679.53" + wire width 8 \main_sdblock2mem_fifo_source_payload_data + attribute \src "ls180.v:1676.6-1676.40" + wire \main_sdblock2mem_fifo_source_ready + attribute \src "ls180.v:1675.6-1675.40" + wire \main_sdblock2mem_fifo_source_valid + attribute \src "ls180.v:1684.12-1684.46" + wire width 10 \main_sdblock2mem_fifo_syncfifo_din + attribute \src "ls180.v:1685.12-1685.47" + wire width 10 \main_sdblock2mem_fifo_syncfifo_dout + attribute \src "ls180.v:1682.6-1682.39" + wire \main_sdblock2mem_fifo_syncfifo_re + attribute \src "ls180.v:1683.6-1683.45" + wire \main_sdblock2mem_fifo_syncfifo_readable + attribute \src "ls180.v:1680.6-1680.39" + wire \main_sdblock2mem_fifo_syncfifo_we + attribute \src "ls180.v:1681.6-1681.45" + wire \main_sdblock2mem_fifo_syncfifo_writable + attribute \src "ls180.v:1690.11-1690.43" + wire width 5 \main_sdblock2mem_fifo_wrport_adr + attribute \src "ls180.v:1691.12-1691.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_r + attribute \src "ls180.v:1693.12-1693.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_w + attribute \src "ls180.v:1692.6-1692.37" + wire \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:1667.6-1667.38" + wire \main_sdblock2mem_sink_sink_first + attribute \src "ls180.v:1668.6-1668.37" + wire \main_sdblock2mem_sink_sink_last + attribute \src "ls180.v:1724.12-1724.54" + wire width 32 \main_sdblock2mem_sink_sink_payload_address + attribute \src "ls180.v:1669.12-1669.52" + wire width 8 \main_sdblock2mem_sink_sink_payload_data0 + attribute \src "ls180.v:1725.12-1725.52" + wire width 64 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1666.6-1666.39" + wire \main_sdblock2mem_sink_sink_ready0 + attribute \src "ls180.v:1723.6-1723.39" + wire \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:1665.6-1665.39" + wire \main_sdblock2mem_sink_sink_valid0 + attribute \src "ls180.v:1722.5-1722.38" + wire \main_sdblock2mem_sink_sink_valid1 + attribute \src "ls180.v:1719.6-1719.42" + wire \main_sdblock2mem_source_source_first + attribute \src "ls180.v:1720.6-1720.41" + wire \main_sdblock2mem_source_source_last + attribute \src "ls180.v:1721.13-1721.56" + wire width 64 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1718.6-1718.42" + wire \main_sdblock2mem_source_source_ready + attribute \src "ls180.v:1717.6-1717.42" + wire \main_sdblock2mem_source_source_valid + attribute \src "ls180.v:1741.13-1741.52" + wire width 32 \main_sdblock2mem_wishbonedmawriter_base + attribute \src "ls180.v:1732.5-1732.47" + wire \main_sdblock2mem_wishbonedmawriter_base_re + attribute \src "ls180.v:1731.12-1731.59" + wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage + attribute \src "ls180.v:1736.5-1736.49" + wire \main_sdblock2mem_wishbonedmawriter_enable_re + attribute \src "ls180.v:1735.5-1735.54" + wire \main_sdblock2mem_wishbonedmawriter_enable_storage + attribute \src "ls180.v:1743.13-1743.54" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length + attribute \src "ls180.v:1734.5-1734.49" + wire \main_sdblock2mem_wishbonedmawriter_length_re + attribute \src "ls180.v:1733.12-1733.61" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage + attribute \src "ls180.v:1740.5-1740.47" + wire \main_sdblock2mem_wishbonedmawriter_loop_re + attribute \src "ls180.v:1739.5-1739.52" + wire \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:1742.12-1742.53" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset + attribute \src "ls180.v:1962.12-1962.79" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + attribute \src "ls180.v:1963.5-1963.75" + wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:1744.6-1744.46" + wire \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:1728.6-1728.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_first + attribute \src "ls180.v:1729.6-1729.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_last + attribute \src "ls180.v:1730.13-1730.65" + wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1727.5-1727.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_ready + attribute \src "ls180.v:1726.6-1726.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_valid + attribute \src "ls180.v:1737.5-1737.46" + wire \main_sdblock2mem_wishbonedmawriter_status + attribute \src "ls180.v:1738.6-1738.43" + wire \main_sdblock2mem_wishbonedmawriter_we + attribute \src "ls180.v:1506.5-1506.31" + wire \main_sdcore_block_count_re + attribute \src "ls180.v:1505.12-1505.43" + wire width 32 \main_sdcore_block_count_storage + attribute \src "ls180.v:1504.5-1504.32" + wire \main_sdcore_block_length_re + attribute \src "ls180.v:1503.11-1503.43" + wire width 10 \main_sdcore_block_length_storage + attribute \src "ls180.v:1490.5-1490.32" + wire \main_sdcore_cmd_argument_re + attribute \src "ls180.v:1489.12-1489.44" + wire width 32 \main_sdcore_cmd_argument_storage + attribute \src "ls180.v:1492.5-1492.31" + wire \main_sdcore_cmd_command_re + attribute \src "ls180.v:1491.12-1491.43" + wire width 32 \main_sdcore_cmd_command_storage + attribute \src "ls180.v:1645.11-1645.32" + wire width 3 \main_sdcore_cmd_count + attribute \src "ls180.v:1946.11-1946.55" + wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 + attribute \src "ls180.v:1947.5-1947.52" + wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:1646.5-1646.25" + wire \main_sdcore_cmd_done + attribute \src "ls180.v:1942.5-1942.48" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 + attribute \src "ls180.v:1943.5-1943.51" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:1647.5-1647.26" + wire \main_sdcore_cmd_error + attribute \src "ls180.v:1950.5-1950.49" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 + attribute \src "ls180.v:1951.5-1951.52" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:1499.12-1499.40" + wire width 4 \main_sdcore_cmd_event_status + attribute \src "ls180.v:1500.6-1500.30" + wire \main_sdcore_cmd_event_we + attribute \src "ls180.v:1497.13-1497.44" + wire width 128 \main_sdcore_cmd_response_status + attribute \src "ls180.v:1958.13-1958.67" + wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + attribute \src "ls180.v:1959.5-1959.62" + wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:1498.6-1498.33" + wire \main_sdcore_cmd_response_we + attribute \src "ls180.v:1494.6-1494.28" + wire \main_sdcore_cmd_send_r + attribute \src "ls180.v:1493.6-1493.29" + wire \main_sdcore_cmd_send_re + attribute \src "ls180.v:1496.5-1496.27" + wire \main_sdcore_cmd_send_w + attribute \src "ls180.v:1495.6-1495.29" + wire \main_sdcore_cmd_send_we + attribute \src "ls180.v:1648.5-1648.28" + wire \main_sdcore_cmd_timeout + attribute \src "ls180.v:1952.5-1952.51" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + attribute \src "ls180.v:1953.5-1953.54" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:1644.12-1644.32" + wire width 2 \main_sdcore_cmd_type + attribute \src "ls180.v:1606.11-1606.40" + wire width 4 \main_sdcore_crc16_checker_cnt + attribute \src "ls180.v:1612.5-1612.39" + wire \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:1611.12-1611.46" + wire width 16 \main_sdcore_crc16_checker_crc0_crc + attribute \src "ls180.v:1607.12-1607.50" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 + attribute \src "ls180.v:1608.13-1608.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 + attribute \src "ls180.v:1609.13-1609.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:1613.6-1613.43" + wire \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:1610.12-1610.46" + wire width 2 \main_sdcore_crc16_checker_crc0_val + attribute \src "ls180.v:1619.5-1619.39" + wire \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:1618.12-1618.46" + wire width 16 \main_sdcore_crc16_checker_crc1_crc + attribute \src "ls180.v:1614.12-1614.50" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 + attribute \src "ls180.v:1615.13-1615.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 + attribute \src "ls180.v:1616.13-1616.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:1620.6-1620.43" + wire \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:1617.12-1617.46" + wire width 2 \main_sdcore_crc16_checker_crc1_val + attribute \src "ls180.v:1626.5-1626.39" + wire \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:1625.12-1625.46" + wire width 16 \main_sdcore_crc16_checker_crc2_crc + attribute \src "ls180.v:1621.12-1621.50" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 + attribute \src "ls180.v:1622.13-1622.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 + attribute \src "ls180.v:1623.13-1623.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:1627.6-1627.43" + wire \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:1624.12-1624.46" + wire width 2 \main_sdcore_crc16_checker_crc2_val + attribute \src "ls180.v:1633.5-1633.39" + wire \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:1632.12-1632.46" + wire width 16 \main_sdcore_crc16_checker_crc3_crc + attribute \src "ls180.v:1628.12-1628.50" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 + attribute \src "ls180.v:1629.13-1629.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 + attribute \src "ls180.v:1630.13-1630.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:1634.6-1634.43" + wire \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:1631.12-1631.46" + wire width 2 \main_sdcore_crc16_checker_crc3_val + attribute \src "ls180.v:1635.12-1635.45" + wire width 16 \main_sdcore_crc16_checker_crctmp0 + attribute \src "ls180.v:1636.12-1636.45" + wire width 16 \main_sdcore_crc16_checker_crctmp1 + attribute \src "ls180.v:1637.12-1637.45" + wire width 16 \main_sdcore_crc16_checker_crctmp2 + attribute \src "ls180.v:1638.12-1638.45" + wire width 16 \main_sdcore_crc16_checker_crctmp3 + attribute \src "ls180.v:1640.12-1640.43" + wire width 16 \main_sdcore_crc16_checker_fifo0 + attribute \src "ls180.v:1641.12-1641.43" + wire width 16 \main_sdcore_crc16_checker_fifo1 + attribute \src "ls180.v:1642.12-1642.43" + wire width 16 \main_sdcore_crc16_checker_fifo2 + attribute \src "ls180.v:1643.12-1643.43" + wire width 16 \main_sdcore_crc16_checker_fifo3 + attribute \src "ls180.v:1597.5-1597.41" + wire \main_sdcore_crc16_checker_sink_first + attribute \src "ls180.v:1598.5-1598.40" + wire \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:1599.11-1599.54" + wire width 8 \main_sdcore_crc16_checker_sink_payload_data + attribute \src "ls180.v:1596.5-1596.41" + wire \main_sdcore_crc16_checker_sink_ready + attribute \src "ls180.v:1595.5-1595.41" + wire \main_sdcore_crc16_checker_sink_valid + attribute \src "ls180.v:1602.5-1602.43" + wire \main_sdcore_crc16_checker_source_first + attribute \src "ls180.v:1603.6-1603.43" + wire \main_sdcore_crc16_checker_source_last + attribute \src "ls180.v:1604.12-1604.57" + wire width 8 \main_sdcore_crc16_checker_source_payload_data + attribute \src "ls180.v:1601.6-1601.44" + wire \main_sdcore_crc16_checker_source_ready + attribute \src "ls180.v:1600.5-1600.43" + wire \main_sdcore_crc16_checker_source_valid + attribute \src "ls180.v:1605.11-1605.40" + wire width 8 \main_sdcore_crc16_checker_val + attribute \src "ls180.v:1639.5-1639.36" + wire \main_sdcore_crc16_checker_valid + attribute \src "ls180.v:1562.11-1562.41" + wire width 3 \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:1938.11-1938.80" + wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + attribute \src "ls180.v:1939.5-1939.77" + wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:1568.6-1568.41" + wire \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:1567.12-1567.47" + wire width 16 \main_sdcore_crc16_inserter_crc0_crc + attribute \src "ls180.v:1563.12-1563.51" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 + attribute \src "ls180.v:1564.13-1564.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 + attribute \src "ls180.v:1565.13-1565.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:1569.6-1569.44" + wire \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:1566.12-1566.47" + wire width 2 \main_sdcore_crc16_inserter_crc0_val + attribute \src "ls180.v:1575.6-1575.41" + wire \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:1574.12-1574.47" + wire width 16 \main_sdcore_crc16_inserter_crc1_crc + attribute \src "ls180.v:1570.12-1570.51" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 + attribute \src "ls180.v:1571.13-1571.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 + attribute \src "ls180.v:1572.13-1572.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:1576.6-1576.44" + wire \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:1573.12-1573.47" + wire width 2 \main_sdcore_crc16_inserter_crc1_val + attribute \src "ls180.v:1582.6-1582.41" + wire \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:1581.12-1581.47" + wire width 16 \main_sdcore_crc16_inserter_crc2_crc + attribute \src "ls180.v:1577.12-1577.51" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 + attribute \src "ls180.v:1578.13-1578.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 + attribute \src "ls180.v:1579.13-1579.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:1583.6-1583.44" + wire \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:1580.12-1580.47" + wire width 2 \main_sdcore_crc16_inserter_crc2_val + attribute \src "ls180.v:1589.6-1589.41" + wire \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:1588.12-1588.47" + wire width 16 \main_sdcore_crc16_inserter_crc3_crc + attribute \src "ls180.v:1584.12-1584.51" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 + attribute \src "ls180.v:1585.13-1585.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 + attribute \src "ls180.v:1586.13-1586.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:1590.6-1590.44" + wire \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:1587.12-1587.47" + wire width 2 \main_sdcore_crc16_inserter_crc3_val + attribute \src "ls180.v:1591.12-1591.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp0 + attribute \src "ls180.v:1930.12-1930.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + attribute \src "ls180.v:1931.5-1931.81" + wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:1592.12-1592.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp1 + attribute \src "ls180.v:1932.12-1932.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + attribute \src "ls180.v:1933.5-1933.81" + wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:1593.12-1593.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp2 + attribute \src "ls180.v:1934.12-1934.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + attribute \src "ls180.v:1935.5-1935.81" + wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:1594.12-1594.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp3 + attribute \src "ls180.v:1936.12-1936.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + attribute \src "ls180.v:1937.5-1937.81" + wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:1554.6-1554.43" + wire \main_sdcore_crc16_inserter_sink_first + attribute \src "ls180.v:1555.6-1555.42" + wire \main_sdcore_crc16_inserter_sink_last + attribute \src "ls180.v:1556.12-1556.56" + wire width 8 \main_sdcore_crc16_inserter_sink_payload_data + attribute \src "ls180.v:1553.5-1553.42" + wire \main_sdcore_crc16_inserter_sink_ready + attribute \src "ls180.v:1552.6-1552.43" + wire \main_sdcore_crc16_inserter_sink_valid + attribute \src "ls180.v:1559.5-1559.44" + wire \main_sdcore_crc16_inserter_source_first + attribute \src "ls180.v:1560.5-1560.43" + wire \main_sdcore_crc16_inserter_source_last + attribute \src "ls180.v:1561.11-1561.57" + wire width 8 \main_sdcore_crc16_inserter_source_payload_data + attribute \src "ls180.v:1558.5-1558.44" + wire \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:1557.5-1557.44" + wire \main_sdcore_crc16_inserter_source_valid + attribute \src "ls180.v:1550.6-1550.35" + wire \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:1549.11-1549.40" + wire width 7 \main_sdcore_crc7_inserter_crc + attribute \src "ls180.v:1507.11-1507.44" + wire width 7 \main_sdcore_crc7_inserter_crcreg0 + attribute \src "ls180.v:1508.12-1508.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg1 + attribute \src "ls180.v:1517.12-1517.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg10 + attribute \src "ls180.v:1518.12-1518.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg11 + attribute \src "ls180.v:1519.12-1519.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg12 + attribute \src "ls180.v:1520.12-1520.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg13 + attribute \src "ls180.v:1521.12-1521.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg14 + attribute \src "ls180.v:1522.12-1522.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg15 + attribute \src "ls180.v:1523.12-1523.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg16 + attribute \src "ls180.v:1524.12-1524.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg17 + attribute \src "ls180.v:1525.12-1525.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg18 + attribute \src "ls180.v:1526.12-1526.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg19 + attribute \src "ls180.v:1509.12-1509.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg2 + attribute \src "ls180.v:1527.12-1527.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg20 + attribute \src "ls180.v:1528.12-1528.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg21 + attribute \src "ls180.v:1529.12-1529.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg22 + attribute \src "ls180.v:1530.12-1530.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg23 + attribute \src "ls180.v:1531.12-1531.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg24 + attribute \src "ls180.v:1532.12-1532.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg25 + attribute \src "ls180.v:1533.12-1533.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg26 + attribute \src "ls180.v:1534.12-1534.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg27 + attribute \src "ls180.v:1535.12-1535.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg28 + attribute \src "ls180.v:1536.12-1536.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg29 + attribute \src "ls180.v:1510.12-1510.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg3 + attribute \src "ls180.v:1537.12-1537.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg30 + attribute \src "ls180.v:1538.12-1538.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg31 + attribute \src "ls180.v:1539.12-1539.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg32 + attribute \src "ls180.v:1540.12-1540.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg33 + attribute \src "ls180.v:1541.12-1541.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg34 + attribute \src "ls180.v:1542.12-1542.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg35 + attribute \src "ls180.v:1543.12-1543.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg36 + attribute \src "ls180.v:1544.12-1544.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg37 + attribute \src "ls180.v:1545.12-1545.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg38 + attribute \src "ls180.v:1546.12-1546.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg39 + attribute \src "ls180.v:1511.12-1511.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg4 + attribute \src "ls180.v:1547.12-1547.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:1512.12-1512.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg5 + attribute \src "ls180.v:1513.12-1513.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg6 + attribute \src "ls180.v:1514.12-1514.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg7 + attribute \src "ls180.v:1515.12-1515.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg8 + attribute \src "ls180.v:1516.12-1516.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg9 + attribute \src "ls180.v:1551.6-1551.38" + wire \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:1548.13-1548.42" + wire width 40 \main_sdcore_crc7_inserter_val + attribute \src "ls180.v:1650.12-1650.34" + wire width 32 \main_sdcore_data_count + attribute \src "ls180.v:1948.12-1948.57" + wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 + attribute \src "ls180.v:1949.5-1949.53" + wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:1651.5-1651.26" + wire \main_sdcore_data_done + attribute \src "ls180.v:1944.5-1944.49" + wire \main_sdcore_data_done_sdcore_fsm_next_value1 + attribute \src "ls180.v:1945.5-1945.52" + wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:1652.5-1652.27" + wire \main_sdcore_data_error + attribute \src "ls180.v:1954.5-1954.50" + wire \main_sdcore_data_error_sdcore_fsm_next_value6 + attribute \src "ls180.v:1955.5-1955.53" + wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:1501.12-1501.41" + wire width 4 \main_sdcore_data_event_status + attribute \src "ls180.v:1502.6-1502.31" + wire \main_sdcore_data_event_we + attribute \src "ls180.v:1653.5-1653.29" + wire \main_sdcore_data_timeout + attribute \src "ls180.v:1956.5-1956.52" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 + attribute \src "ls180.v:1957.5-1957.55" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:1649.12-1649.33" + wire width 2 \main_sdcore_data_type + attribute \src "ls180.v:1481.6-1481.33" + wire \main_sdcore_sink_sink_first + attribute \src "ls180.v:1482.6-1482.32" + wire \main_sdcore_sink_sink_last + attribute \src "ls180.v:1483.12-1483.46" + wire width 8 \main_sdcore_sink_sink_payload_data + attribute \src "ls180.v:1480.6-1480.33" + wire \main_sdcore_sink_sink_ready + attribute \src "ls180.v:1479.6-1479.33" + wire \main_sdcore_sink_sink_valid + attribute \src "ls180.v:1486.6-1486.37" + wire \main_sdcore_source_source_first + attribute \src "ls180.v:1487.6-1487.36" + wire \main_sdcore_source_source_last + attribute \src "ls180.v:1488.12-1488.50" + wire width 8 \main_sdcore_source_source_payload_data + attribute \src "ls180.v:1485.6-1485.37" + wire \main_sdcore_source_source_ready + attribute \src "ls180.v:1484.6-1484.37" + wire \main_sdcore_source_source_valid + attribute \src "ls180.v:1799.6-1799.38" + wire \main_sdmem2block_converter_first + attribute \src "ls180.v:1800.6-1800.37" + wire \main_sdmem2block_converter_last + attribute \src "ls180.v:1798.11-1798.41" + wire width 3 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1789.6-1789.43" + wire \main_sdmem2block_converter_sink_first + attribute \src "ls180.v:1790.6-1790.42" + wire \main_sdmem2block_converter_sink_last + attribute \src "ls180.v:1791.13-1791.57" + wire width 64 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1788.6-1788.43" + wire \main_sdmem2block_converter_sink_ready + attribute \src "ls180.v:1787.6-1787.43" + wire \main_sdmem2block_converter_sink_valid + attribute \src "ls180.v:1794.6-1794.45" + wire \main_sdmem2block_converter_source_first + attribute \src "ls180.v:1795.6-1795.44" + wire \main_sdmem2block_converter_source_last + attribute \src "ls180.v:1796.11-1796.57" + wire width 8 \main_sdmem2block_converter_source_payload_data + attribute \src "ls180.v:1797.6-1797.65" + wire \main_sdmem2block_converter_source_payload_valid_token_count + attribute \src "ls180.v:1793.6-1793.45" + wire \main_sdmem2block_converter_source_ready + attribute \src "ls180.v:1792.6-1792.45" + wire \main_sdmem2block_converter_source_valid + attribute \src "ls180.v:1783.13-1783.38" + wire width 32 \main_sdmem2block_dma_base + attribute \src "ls180.v:1772.5-1772.33" + wire \main_sdmem2block_dma_base_re + attribute \src "ls180.v:1771.12-1771.45" + wire width 64 \main_sdmem2block_dma_base_storage + attribute \src "ls180.v:1770.12-1770.37" + wire width 64 \main_sdmem2block_dma_data + attribute \src "ls180.v:1966.12-1966.67" + wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1967.5-1967.63" + wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:1777.5-1777.37" + wire \main_sdmem2block_dma_done_status + attribute \src "ls180.v:1778.6-1778.34" + wire \main_sdmem2block_dma_done_we + attribute \src "ls180.v:1776.5-1776.35" + wire \main_sdmem2block_dma_enable_re + attribute \src "ls180.v:1775.5-1775.40" + wire \main_sdmem2block_dma_enable_storage + attribute \src "ls180.v:1785.13-1785.40" + wire width 32 \main_sdmem2block_dma_length + attribute \src "ls180.v:1774.5-1774.35" + wire \main_sdmem2block_dma_length_re + attribute \src "ls180.v:1773.12-1773.47" + wire width 32 \main_sdmem2block_dma_length_storage + attribute \src "ls180.v:1780.5-1780.33" + wire \main_sdmem2block_dma_loop_re + attribute \src "ls180.v:1779.5-1779.38" + wire \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:1784.12-1784.39" + wire width 32 \main_sdmem2block_dma_offset + attribute \src "ls180.v:1970.12-1970.79" + wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + attribute \src "ls180.v:1971.5-1971.75" + wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:1781.13-1781.47" + wire width 32 \main_sdmem2block_dma_offset_status + attribute \src "ls180.v:1782.6-1782.36" + wire \main_sdmem2block_dma_offset_we + attribute \src "ls180.v:1786.6-1786.32" + wire \main_sdmem2block_dma_reset + attribute \src "ls180.v:1763.5-1763.35" + wire \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:1764.12-1764.53" + wire width 32 \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:1762.5-1762.36" + wire \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:1761.5-1761.36" + wire \main_sdmem2block_dma_sink_valid + attribute \src "ls180.v:1767.5-1767.38" + wire \main_sdmem2block_dma_source_first + attribute \src "ls180.v:1768.5-1768.37" + wire \main_sdmem2block_dma_source_last + attribute \src "ls180.v:1769.12-1769.52" + wire width 64 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1766.6-1766.39" + wire \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:1765.5-1765.38" + wire \main_sdmem2block_dma_source_valid + attribute \src "ls180.v:1825.11-1825.40" + wire width 5 \main_sdmem2block_fifo_consume + attribute \src "ls180.v:1830.6-1830.35" + wire \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:1834.6-1834.41" + wire \main_sdmem2block_fifo_fifo_in_first + attribute \src "ls180.v:1835.6-1835.40" + wire \main_sdmem2block_fifo_fifo_in_last + attribute \src "ls180.v:1833.12-1833.54" + wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data + attribute \src "ls180.v:1837.6-1837.42" + wire \main_sdmem2block_fifo_fifo_out_first + attribute \src "ls180.v:1838.6-1838.41" + wire \main_sdmem2block_fifo_fifo_out_last + attribute \src "ls180.v:1836.12-1836.55" + wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data + attribute \src "ls180.v:1822.11-1822.38" + wire width 6 \main_sdmem2block_fifo_level + attribute \src "ls180.v:1824.11-1824.40" + wire width 5 \main_sdmem2block_fifo_produce + attribute \src "ls180.v:1831.12-1831.44" + wire width 5 \main_sdmem2block_fifo_rdport_adr + attribute \src "ls180.v:1832.12-1832.46" + wire width 10 \main_sdmem2block_fifo_rdport_dat_r + attribute \src "ls180.v:1823.5-1823.34" + wire \main_sdmem2block_fifo_replace + attribute \src "ls180.v:1808.6-1808.38" + wire \main_sdmem2block_fifo_sink_first + attribute \src "ls180.v:1809.6-1809.37" + wire \main_sdmem2block_fifo_sink_last + attribute \src "ls180.v:1810.12-1810.51" + wire width 8 \main_sdmem2block_fifo_sink_payload_data + attribute \src "ls180.v:1807.6-1807.38" + wire \main_sdmem2block_fifo_sink_ready + attribute \src "ls180.v:1806.6-1806.38" + wire \main_sdmem2block_fifo_sink_valid + attribute \src "ls180.v:1813.6-1813.40" + wire \main_sdmem2block_fifo_source_first + attribute \src "ls180.v:1814.6-1814.39" + wire \main_sdmem2block_fifo_source_last + attribute \src "ls180.v:1815.12-1815.53" + wire width 8 \main_sdmem2block_fifo_source_payload_data + attribute \src "ls180.v:1812.6-1812.40" + wire \main_sdmem2block_fifo_source_ready + attribute \src "ls180.v:1811.6-1811.40" + wire \main_sdmem2block_fifo_source_valid + attribute \src "ls180.v:1820.12-1820.46" + wire width 10 \main_sdmem2block_fifo_syncfifo_din + attribute \src "ls180.v:1821.12-1821.47" + wire width 10 \main_sdmem2block_fifo_syncfifo_dout + attribute \src "ls180.v:1818.6-1818.39" + wire \main_sdmem2block_fifo_syncfifo_re + attribute \src "ls180.v:1819.6-1819.45" + wire \main_sdmem2block_fifo_syncfifo_readable + attribute \src "ls180.v:1816.6-1816.39" + wire \main_sdmem2block_fifo_syncfifo_we + attribute \src "ls180.v:1817.6-1817.45" + wire \main_sdmem2block_fifo_syncfifo_writable + attribute \src "ls180.v:1826.11-1826.43" + wire width 5 \main_sdmem2block_fifo_wrport_adr + attribute \src "ls180.v:1827.12-1827.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_r + attribute \src "ls180.v:1829.12-1829.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_w + attribute \src "ls180.v:1828.6-1828.37" + wire \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:1758.6-1758.43" + wire \main_sdmem2block_source_source_first0 + attribute \src "ls180.v:1803.6-1803.43" + wire \main_sdmem2block_source_source_first1 + attribute \src "ls180.v:1759.6-1759.42" + wire \main_sdmem2block_source_source_last0 + attribute \src "ls180.v:1804.6-1804.42" + wire \main_sdmem2block_source_source_last1 + attribute \src "ls180.v:1760.12-1760.56" + wire width 8 \main_sdmem2block_source_source_payload_data0 + attribute \src "ls180.v:1805.12-1805.56" + wire width 8 \main_sdmem2block_source_source_payload_data1 + attribute \src "ls180.v:1757.6-1757.43" + wire \main_sdmem2block_source_source_ready0 + attribute \src "ls180.v:1802.6-1802.43" + wire \main_sdmem2block_source_source_ready1 + attribute \src "ls180.v:1756.6-1756.43" + wire \main_sdmem2block_source_source_valid0 + attribute \src "ls180.v:1801.6-1801.43" + wire \main_sdmem2block_source_source_valid1 + attribute \src "ls180.v:1207.6-1207.27" + wire \main_sdphy_clocker_ce + attribute \src "ls180.v:1206.5-1206.28" + wire \main_sdphy_clocker_clk0 + attribute \src "ls180.v:1209.5-1209.28" + wire \main_sdphy_clocker_clk1 + attribute \src "ls180.v:1210.5-1210.29" + wire \main_sdphy_clocker_clk_d + attribute \src "ls180.v:1208.11-1208.34" + wire width 9 \main_sdphy_clocker_clks + attribute \src "ls180.v:1204.5-1204.26" + wire \main_sdphy_clocker_re + attribute \src "ls180.v:1205.6-1205.29" + wire \main_sdphy_clocker_stop + attribute \src "ls180.v:1203.11-1203.37" + wire width 9 \main_sdphy_clocker_storage + attribute \src "ls180.v:1307.6-1307.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_first + attribute \src "ls180.v:1308.6-1308.40" + wire \main_sdphy_cmdr_cmdr_buf_sink_last + attribute \src "ls180.v:1309.12-1309.54" + wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data + attribute \src "ls180.v:1306.6-1306.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_ready + attribute \src "ls180.v:1305.6-1305.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_valid + attribute \src "ls180.v:1312.5-1312.42" + wire \main_sdphy_cmdr_cmdr_buf_source_first + attribute \src "ls180.v:1313.5-1313.41" + wire \main_sdphy_cmdr_cmdr_buf_source_last + attribute \src "ls180.v:1314.11-1314.55" + wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data + attribute \src "ls180.v:1311.6-1311.43" + wire \main_sdphy_cmdr_cmdr_buf_source_ready + attribute \src "ls180.v:1310.5-1310.42" + wire \main_sdphy_cmdr_cmdr_buf_source_valid + attribute \src "ls180.v:1297.11-1297.47" + wire width 3 \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:1298.6-1298.46" + wire \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:1288.5-1288.46" + wire \main_sdphy_cmdr_cmdr_converter_sink_first + attribute \src "ls180.v:1289.5-1289.45" + wire \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:1290.6-1290.54" + wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:1287.6-1287.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_ready + attribute \src "ls180.v:1286.6-1286.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_valid + attribute \src "ls180.v:1293.5-1293.48" + wire \main_sdphy_cmdr_cmdr_converter_source_first + attribute \src "ls180.v:1294.5-1294.47" + wire \main_sdphy_cmdr_cmdr_converter_source_last + attribute \src "ls180.v:1295.11-1295.61" + wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data + attribute \src "ls180.v:1296.11-1296.74" + wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1292.6-1292.49" + wire \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:1291.6-1291.49" + wire \main_sdphy_cmdr_cmdr_converter_source_valid + attribute \src "ls180.v:1299.5-1299.46" + wire \main_sdphy_cmdr_cmdr_converter_strobe_all + attribute \src "ls180.v:1270.6-1270.40" + wire \main_sdphy_cmdr_cmdr_pads_in_first + attribute \src "ls180.v:1271.6-1271.39" + wire \main_sdphy_cmdr_cmdr_pads_in_last + attribute \src "ls180.v:1272.6-1272.46" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk + attribute \src "ls180.v:1273.6-1273.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + attribute \src "ls180.v:1274.6-1274.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o + attribute \src "ls180.v:1275.6-1275.49" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1276.12-1276.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i + attribute \src "ls180.v:1277.12-1277.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o + attribute \src "ls180.v:1278.6-1278.50" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe + attribute \src "ls180.v:1269.5-1269.39" + wire \main_sdphy_cmdr_cmdr_pads_in_ready + attribute \src "ls180.v:1268.6-1268.40" + wire \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:1315.5-1315.31" + wire \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:1910.5-1910.59" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + attribute \src "ls180.v:1911.5-1911.62" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:1285.5-1285.29" + wire \main_sdphy_cmdr_cmdr_run + attribute \src "ls180.v:1281.6-1281.47" + wire \main_sdphy_cmdr_cmdr_source_source_first0 + attribute \src "ls180.v:1302.6-1302.47" + wire \main_sdphy_cmdr_cmdr_source_source_first1 + attribute \src "ls180.v:1282.6-1282.46" + wire \main_sdphy_cmdr_cmdr_source_source_last0 + attribute \src "ls180.v:1303.6-1303.46" + wire \main_sdphy_cmdr_cmdr_source_source_last1 + attribute \src "ls180.v:1283.12-1283.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 + attribute \src "ls180.v:1304.12-1304.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 + attribute \src "ls180.v:1280.5-1280.46" + wire \main_sdphy_cmdr_cmdr_source_source_ready0 + attribute \src "ls180.v:1301.6-1301.47" + wire \main_sdphy_cmdr_cmdr_source_source_ready1 + attribute \src "ls180.v:1279.6-1279.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:1300.6-1300.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid1 + attribute \src "ls180.v:1284.6-1284.32" + wire \main_sdphy_cmdr_cmdr_start + attribute \src "ls180.v:1267.11-1267.32" + wire width 8 \main_sdphy_cmdr_count + attribute \src "ls180.v:1906.11-1906.60" + wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + attribute \src "ls180.v:1907.5-1907.57" + wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:1242.5-1242.42" + wire \main_sdphy_cmdr_pads_in_pads_in_first + attribute \src "ls180.v:1243.5-1243.41" + wire \main_sdphy_cmdr_pads_in_pads_in_last + attribute \src "ls180.v:1244.5-1244.48" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1245.6-1245.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1246.5-1246.50" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1247.5-1247.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1248.12-1248.58" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1249.11-1249.57" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1250.5-1250.52" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1241.6-1241.43" + wire \main_sdphy_cmdr_pads_in_pads_in_ready + attribute \src "ls180.v:1240.6-1240.43" + wire \main_sdphy_cmdr_pads_in_pads_in_valid + attribute \src "ls180.v:1252.5-1252.41" + wire \main_sdphy_cmdr_pads_out_payload_clk + attribute \src "ls180.v:1253.5-1253.43" + wire \main_sdphy_cmdr_pads_out_payload_cmd_o + attribute \src "ls180.v:1254.5-1254.44" + wire \main_sdphy_cmdr_pads_out_payload_cmd_oe + attribute \src "ls180.v:1255.11-1255.50" + wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o + attribute \src "ls180.v:1256.5-1256.45" + wire \main_sdphy_cmdr_pads_out_payload_data_oe + attribute \src "ls180.v:1251.6-1251.36" + wire \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:1259.5-1259.30" + wire \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:1260.11-1260.46" + wire width 8 \main_sdphy_cmdr_sink_payload_length + attribute \src "ls180.v:1258.5-1258.31" + wire \main_sdphy_cmdr_sink_ready + attribute \src "ls180.v:1257.5-1257.31" + wire \main_sdphy_cmdr_sink_valid + attribute \src "ls180.v:1263.5-1263.32" + wire \main_sdphy_cmdr_source_last + attribute \src "ls180.v:1264.11-1264.46" + wire width 8 \main_sdphy_cmdr_source_payload_data + attribute \src "ls180.v:1265.11-1265.48" + wire width 3 \main_sdphy_cmdr_source_payload_status + attribute \src "ls180.v:1262.5-1262.33" + wire \main_sdphy_cmdr_source_ready + attribute \src "ls180.v:1261.5-1261.33" + wire \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:1266.12-1266.35" + wire width 32 \main_sdphy_cmdr_timeout + attribute \src "ls180.v:1908.12-1908.63" + wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + attribute \src "ls180.v:1909.5-1909.59" + wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:1239.11-1239.32" + wire width 8 \main_sdphy_cmdw_count + attribute \src "ls180.v:1902.11-1902.59" + wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + attribute \src "ls180.v:1903.5-1903.56" + wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:1238.5-1238.25" + wire \main_sdphy_cmdw_done + attribute \src "ls180.v:1226.6-1226.43" + wire \main_sdphy_cmdw_pads_in_payload_cmd_i + attribute \src "ls180.v:1227.12-1227.50" + wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i + attribute \src "ls180.v:1225.6-1225.35" + wire \main_sdphy_cmdw_pads_in_valid + attribute \src "ls180.v:1229.5-1229.41" + wire \main_sdphy_cmdw_pads_out_payload_clk + attribute \src "ls180.v:1230.5-1230.43" + wire \main_sdphy_cmdw_pads_out_payload_cmd_o + attribute \src "ls180.v:1231.5-1231.44" + wire \main_sdphy_cmdw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1232.11-1232.50" + wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o + attribute \src "ls180.v:1233.5-1233.45" + wire \main_sdphy_cmdw_pads_out_payload_data_oe + attribute \src "ls180.v:1228.6-1228.36" + wire \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:1236.5-1236.30" + wire \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:1237.11-1237.44" + wire width 8 \main_sdphy_cmdw_sink_payload_data + attribute \src "ls180.v:1235.5-1235.31" + wire \main_sdphy_cmdw_sink_ready + attribute \src "ls180.v:1234.5-1234.31" + wire \main_sdphy_cmdw_sink_valid + attribute \src "ls180.v:1423.11-1423.33" + wire width 10 \main_sdphy_datar_count + attribute \src "ls180.v:1922.11-1922.62" + wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + attribute \src "ls180.v:1923.5-1923.59" + wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:1463.6-1463.43" + wire \main_sdphy_datar_datar_buf_sink_first + attribute \src "ls180.v:1464.6-1464.42" + wire \main_sdphy_datar_datar_buf_sink_last + attribute \src "ls180.v:1465.12-1465.56" + wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data + attribute \src "ls180.v:1462.6-1462.43" + wire \main_sdphy_datar_datar_buf_sink_ready + attribute \src "ls180.v:1461.6-1461.43" + wire \main_sdphy_datar_datar_buf_sink_valid + attribute \src "ls180.v:1468.5-1468.44" + wire \main_sdphy_datar_datar_buf_source_first + attribute \src "ls180.v:1469.5-1469.43" + wire \main_sdphy_datar_datar_buf_source_last + attribute \src "ls180.v:1470.11-1470.57" + wire width 8 \main_sdphy_datar_datar_buf_source_payload_data + attribute \src "ls180.v:1467.6-1467.45" + wire \main_sdphy_datar_datar_buf_source_ready + attribute \src "ls180.v:1466.5-1466.44" + wire \main_sdphy_datar_datar_buf_source_valid + attribute \src "ls180.v:1453.5-1453.43" + wire \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:1454.6-1454.48" + wire \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:1444.5-1444.48" + wire \main_sdphy_datar_datar_converter_sink_first + attribute \src "ls180.v:1445.5-1445.47" + wire \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:1446.12-1446.62" + wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:1443.6-1443.49" + wire \main_sdphy_datar_datar_converter_sink_ready + attribute \src "ls180.v:1442.6-1442.49" + wire \main_sdphy_datar_datar_converter_sink_valid + attribute \src "ls180.v:1449.5-1449.50" + wire \main_sdphy_datar_datar_converter_source_first + attribute \src "ls180.v:1450.5-1450.49" + wire \main_sdphy_datar_datar_converter_source_last + attribute \src "ls180.v:1451.11-1451.63" + wire width 8 \main_sdphy_datar_datar_converter_source_payload_data + attribute \src "ls180.v:1452.11-1452.76" + wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count + attribute \src "ls180.v:1448.6-1448.51" + wire \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:1447.6-1447.51" + wire \main_sdphy_datar_datar_converter_source_valid + attribute \src "ls180.v:1455.5-1455.48" + wire \main_sdphy_datar_datar_converter_strobe_all + attribute \src "ls180.v:1426.6-1426.42" + wire \main_sdphy_datar_datar_pads_in_first + attribute \src "ls180.v:1427.6-1427.41" + wire \main_sdphy_datar_datar_pads_in_last + attribute \src "ls180.v:1428.6-1428.48" + wire \main_sdphy_datar_datar_pads_in_payload_clk + attribute \src "ls180.v:1429.6-1429.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_i + attribute \src "ls180.v:1430.6-1430.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_o + attribute \src "ls180.v:1431.6-1431.51" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe + attribute \src "ls180.v:1432.12-1432.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i + attribute \src "ls180.v:1433.12-1433.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o + attribute \src "ls180.v:1434.6-1434.52" + wire \main_sdphy_datar_datar_pads_in_payload_data_oe + attribute \src "ls180.v:1425.5-1425.41" + wire \main_sdphy_datar_datar_pads_in_ready + attribute \src "ls180.v:1424.6-1424.42" + wire \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:1471.5-1471.33" + wire \main_sdphy_datar_datar_reset + attribute \src "ls180.v:1926.5-1926.62" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + attribute \src "ls180.v:1927.5-1927.65" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:1441.5-1441.31" + wire \main_sdphy_datar_datar_run + attribute \src "ls180.v:1437.6-1437.49" + wire \main_sdphy_datar_datar_source_source_first0 + attribute \src "ls180.v:1458.6-1458.49" + wire \main_sdphy_datar_datar_source_source_first1 + attribute \src "ls180.v:1438.6-1438.48" + wire \main_sdphy_datar_datar_source_source_last0 + attribute \src "ls180.v:1459.6-1459.48" + wire \main_sdphy_datar_datar_source_source_last1 + attribute \src "ls180.v:1439.12-1439.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 + attribute \src "ls180.v:1460.12-1460.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 + attribute \src "ls180.v:1436.5-1436.48" + wire \main_sdphy_datar_datar_source_source_ready0 + attribute \src "ls180.v:1457.6-1457.49" + wire \main_sdphy_datar_datar_source_source_ready1 + attribute \src "ls180.v:1435.6-1435.49" + wire \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:1456.6-1456.49" + wire \main_sdphy_datar_datar_source_source_valid1 + attribute \src "ls180.v:1440.6-1440.34" + wire \main_sdphy_datar_datar_start + attribute \src "ls180.v:1396.5-1396.43" + wire \main_sdphy_datar_pads_in_pads_in_first + attribute \src "ls180.v:1397.5-1397.42" + wire \main_sdphy_datar_pads_in_pads_in_last + attribute \src "ls180.v:1398.5-1398.49" + wire \main_sdphy_datar_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1399.6-1399.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1400.5-1400.51" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1401.5-1401.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1402.12-1402.59" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1403.11-1403.58" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1404.5-1404.53" + wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1395.6-1395.44" + wire \main_sdphy_datar_pads_in_pads_in_ready + attribute \src "ls180.v:1394.6-1394.44" + wire \main_sdphy_datar_pads_in_pads_in_valid + attribute \src "ls180.v:1406.5-1406.42" + wire \main_sdphy_datar_pads_out_payload_clk + attribute \src "ls180.v:1407.5-1407.44" + wire \main_sdphy_datar_pads_out_payload_cmd_o + attribute \src "ls180.v:1408.5-1408.45" + wire \main_sdphy_datar_pads_out_payload_cmd_oe + attribute \src "ls180.v:1409.11-1409.51" + wire width 4 \main_sdphy_datar_pads_out_payload_data_o + attribute \src "ls180.v:1410.5-1410.46" + wire \main_sdphy_datar_pads_out_payload_data_oe + attribute \src "ls180.v:1405.6-1405.37" + wire \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:1413.5-1413.31" + wire \main_sdphy_datar_sink_last + attribute \src "ls180.v:1414.11-1414.53" + wire width 10 \main_sdphy_datar_sink_payload_block_length + attribute \src "ls180.v:1412.5-1412.32" + wire \main_sdphy_datar_sink_ready + attribute \src "ls180.v:1411.5-1411.32" + wire \main_sdphy_datar_sink_valid + attribute \src "ls180.v:1417.5-1417.34" + wire \main_sdphy_datar_source_first + attribute \src "ls180.v:1418.5-1418.33" + wire \main_sdphy_datar_source_last + attribute \src "ls180.v:1419.11-1419.47" + wire width 8 \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:1420.11-1420.49" + wire width 3 \main_sdphy_datar_source_payload_status + attribute \src "ls180.v:1416.5-1416.34" + wire \main_sdphy_datar_source_ready + attribute \src "ls180.v:1415.5-1415.34" + wire \main_sdphy_datar_source_valid + attribute \src "ls180.v:1421.5-1421.26" + wire \main_sdphy_datar_stop + attribute \src "ls180.v:1422.12-1422.36" + wire width 32 \main_sdphy_datar_timeout + attribute \src "ls180.v:1924.12-1924.65" + wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + attribute \src "ls180.v:1925.5-1925.61" + wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:1331.11-1331.33" + wire width 8 \main_sdphy_dataw_count + attribute \src "ls180.v:1918.11-1918.54" + wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value + attribute \src "ls180.v:1919.5-1919.51" + wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:1385.6-1385.42" + wire \main_sdphy_dataw_crcr_buf_sink_first + attribute \src "ls180.v:1386.6-1386.41" + wire \main_sdphy_dataw_crcr_buf_sink_last + attribute \src "ls180.v:1387.12-1387.55" + wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data + attribute \src "ls180.v:1384.6-1384.42" + wire \main_sdphy_dataw_crcr_buf_sink_ready + attribute \src "ls180.v:1383.6-1383.42" + wire \main_sdphy_dataw_crcr_buf_sink_valid + attribute \src "ls180.v:1390.5-1390.43" + wire \main_sdphy_dataw_crcr_buf_source_first + attribute \src "ls180.v:1391.5-1391.42" + wire \main_sdphy_dataw_crcr_buf_source_last + attribute \src "ls180.v:1392.11-1392.56" + wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data + attribute \src "ls180.v:1389.6-1389.44" + wire \main_sdphy_dataw_crcr_buf_source_ready + attribute \src "ls180.v:1388.5-1388.43" + wire \main_sdphy_dataw_crcr_buf_source_valid + attribute \src "ls180.v:1375.11-1375.48" + wire width 3 \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:1376.6-1376.47" + wire \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:1366.5-1366.47" + wire \main_sdphy_dataw_crcr_converter_sink_first + attribute \src "ls180.v:1367.5-1367.46" + wire \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:1368.6-1368.55" + wire \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:1365.6-1365.48" + wire \main_sdphy_dataw_crcr_converter_sink_ready + attribute \src "ls180.v:1364.6-1364.48" + wire \main_sdphy_dataw_crcr_converter_sink_valid + attribute \src "ls180.v:1371.5-1371.49" + wire \main_sdphy_dataw_crcr_converter_source_first + attribute \src "ls180.v:1372.5-1372.48" + wire \main_sdphy_dataw_crcr_converter_source_last + attribute \src "ls180.v:1373.11-1373.62" + wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data + attribute \src "ls180.v:1374.11-1374.75" + wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1370.6-1370.50" + wire \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:1369.6-1369.50" + wire \main_sdphy_dataw_crcr_converter_source_valid + attribute \src "ls180.v:1377.5-1377.47" + wire \main_sdphy_dataw_crcr_converter_strobe_all + attribute \src "ls180.v:1348.6-1348.41" + wire \main_sdphy_dataw_crcr_pads_in_first + attribute \src "ls180.v:1349.6-1349.40" + wire \main_sdphy_dataw_crcr_pads_in_last + attribute \src "ls180.v:1350.6-1350.47" + wire \main_sdphy_dataw_crcr_pads_in_payload_clk + attribute \src "ls180.v:1351.6-1351.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i + attribute \src "ls180.v:1352.6-1352.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o + attribute \src "ls180.v:1353.6-1353.50" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1354.12-1354.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i + attribute \src "ls180.v:1355.12-1355.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o + attribute \src "ls180.v:1356.6-1356.51" + wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe + attribute \src "ls180.v:1347.5-1347.40" + wire \main_sdphy_dataw_crcr_pads_in_ready + attribute \src "ls180.v:1346.6-1346.41" + wire \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:1393.5-1393.32" + wire \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:1914.5-1914.59" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + attribute \src "ls180.v:1915.5-1915.62" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:1363.5-1363.30" + wire \main_sdphy_dataw_crcr_run + attribute \src "ls180.v:1359.6-1359.48" + wire \main_sdphy_dataw_crcr_source_source_first0 + attribute \src "ls180.v:1380.6-1380.48" + wire \main_sdphy_dataw_crcr_source_source_first1 + attribute \src "ls180.v:1360.6-1360.47" + wire \main_sdphy_dataw_crcr_source_source_last0 + attribute \src "ls180.v:1381.6-1381.47" + wire \main_sdphy_dataw_crcr_source_source_last1 + attribute \src "ls180.v:1361.12-1361.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 + attribute \src "ls180.v:1382.12-1382.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 + attribute \src "ls180.v:1358.5-1358.47" + wire \main_sdphy_dataw_crcr_source_source_ready0 + attribute \src "ls180.v:1379.6-1379.48" + wire \main_sdphy_dataw_crcr_source_source_ready1 + attribute \src "ls180.v:1357.6-1357.48" + wire \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:1378.6-1378.48" + wire \main_sdphy_dataw_crcr_source_source_valid1 + attribute \src "ls180.v:1362.6-1362.33" + wire \main_sdphy_dataw_crcr_start + attribute \src "ls180.v:1345.5-1345.27" + wire \main_sdphy_dataw_error + attribute \src "ls180.v:1334.5-1334.43" + wire \main_sdphy_dataw_pads_in_pads_in_first + attribute \src "ls180.v:1335.5-1335.42" + wire \main_sdphy_dataw_pads_in_pads_in_last + attribute \src "ls180.v:1336.5-1336.49" + wire \main_sdphy_dataw_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1337.5-1337.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1338.5-1338.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1339.5-1339.52" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1340.11-1340.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1341.11-1341.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1342.5-1342.53" + wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1333.6-1333.44" + wire \main_sdphy_dataw_pads_in_pads_in_ready + attribute \src "ls180.v:1332.5-1332.43" + wire \main_sdphy_dataw_pads_in_pads_in_valid + attribute \src "ls180.v:1317.6-1317.44" + wire \main_sdphy_dataw_pads_in_payload_cmd_i + attribute \src "ls180.v:1318.12-1318.51" + wire width 4 \main_sdphy_dataw_pads_in_payload_data_i + attribute \src "ls180.v:1316.6-1316.36" + wire \main_sdphy_dataw_pads_in_valid + attribute \src "ls180.v:1320.5-1320.42" + wire \main_sdphy_dataw_pads_out_payload_clk + attribute \src "ls180.v:1321.5-1321.44" + wire \main_sdphy_dataw_pads_out_payload_cmd_o + attribute \src "ls180.v:1322.5-1322.45" + wire \main_sdphy_dataw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1323.11-1323.51" + wire width 4 \main_sdphy_dataw_pads_out_payload_data_o + attribute \src "ls180.v:1324.5-1324.46" + wire \main_sdphy_dataw_pads_out_payload_data_oe + attribute \src "ls180.v:1319.6-1319.37" + wire \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:1327.5-1327.32" + wire \main_sdphy_dataw_sink_first + attribute \src "ls180.v:1328.5-1328.31" + wire \main_sdphy_dataw_sink_last + attribute \src "ls180.v:1329.11-1329.45" + wire width 8 \main_sdphy_dataw_sink_payload_data + attribute \src "ls180.v:1326.5-1326.32" + wire \main_sdphy_dataw_sink_ready + attribute \src "ls180.v:1325.5-1325.32" + wire \main_sdphy_dataw_sink_valid + attribute \src "ls180.v:1343.5-1343.27" + wire \main_sdphy_dataw_start + attribute \src "ls180.v:1330.5-1330.26" + wire \main_sdphy_dataw_stop + attribute \src "ls180.v:1344.5-1344.27" + wire \main_sdphy_dataw_valid + attribute \src "ls180.v:1224.11-1224.32" + wire width 8 \main_sdphy_init_count + attribute \src "ls180.v:1898.11-1898.59" + wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value + attribute \src "ls180.v:1899.5-1899.56" + wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:1212.6-1212.34" + wire \main_sdphy_init_initialize_r + attribute \src "ls180.v:1211.6-1211.35" + wire \main_sdphy_init_initialize_re + attribute \src "ls180.v:1214.5-1214.33" + wire \main_sdphy_init_initialize_w + attribute \src "ls180.v:1213.6-1213.35" + wire \main_sdphy_init_initialize_we + attribute \src "ls180.v:1216.6-1216.43" + wire \main_sdphy_init_pads_in_payload_cmd_i + attribute \src "ls180.v:1217.12-1217.50" + wire width 4 \main_sdphy_init_pads_in_payload_data_i + attribute \src "ls180.v:1215.6-1215.35" + wire \main_sdphy_init_pads_in_valid + attribute \src "ls180.v:1219.5-1219.41" + wire \main_sdphy_init_pads_out_payload_clk + attribute \src "ls180.v:1220.5-1220.43" + wire \main_sdphy_init_pads_out_payload_cmd_o + attribute \src "ls180.v:1221.5-1221.44" + wire \main_sdphy_init_pads_out_payload_cmd_oe + attribute \src "ls180.v:1222.11-1222.50" + wire width 4 \main_sdphy_init_pads_out_payload_data_o + attribute \src "ls180.v:1223.5-1223.45" + wire \main_sdphy_init_pads_out_payload_data_oe + attribute \src "ls180.v:1218.6-1218.36" + wire \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:1472.6-1472.27" + wire \main_sdphy_sdpads_clk + attribute \src "ls180.v:1473.5-1473.28" + wire \main_sdphy_sdpads_cmd_i + attribute \src "ls180.v:1474.6-1474.29" + wire \main_sdphy_sdpads_cmd_o + attribute \src "ls180.v:1475.6-1475.30" + wire \main_sdphy_sdpads_cmd_oe + attribute \src "ls180.v:1476.11-1476.35" + wire width 4 \main_sdphy_sdpads_data_i + attribute \src "ls180.v:1477.12-1477.36" + wire width 4 \main_sdphy_sdpads_data_o + attribute \src "ls180.v:1478.6-1478.31" + wire \main_sdphy_sdpads_data_oe + attribute \src "ls180.v:1201.6-1201.23" + wire \main_sdphy_status + attribute \src "ls180.v:1202.6-1202.19" + wire \main_sdphy_we + attribute \src "ls180.v:418.5-418.26" + wire \main_sdram_address_re + attribute \src "ls180.v:417.12-417.38" + wire width 13 \main_sdram_address_storage + attribute \src "ls180.v:420.5-420.27" + wire \main_sdram_baddress_re + attribute \src "ls180.v:419.11-419.38" + wire width 2 \main_sdram_baddress_storage + attribute \src "ls180.v:516.5-516.43" + wire \main_sdram_bankmachine0_auto_precharge + attribute \src "ls180.v:538.11-538.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "ls180.v:543.6-543.58" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:548.6-548.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:549.6-549.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:547.13-547.78" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:546.6-546.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:552.6-552.65" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:553.6-553.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:551.13-551.79" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:550.6-550.70" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:535.11-535.61" + wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "ls180.v:537.11-537.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "ls180.v:544.12-544.67" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:545.13-545.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:536.5-536.57" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:519.5-519.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:520.5-520.59" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:522.13-522.75" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:521.6-521.66" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:518.6-518.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:517.6-517.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:525.6-525.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:526.6-526.62" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:528.13-528.77" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:527.6-527.68" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:524.6-524.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:523.6-523.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:533.13-533.71" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "ls180.v:534.13-534.72" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "ls180.v:531.6-531.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "ls180.v:532.6-532.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "ls180.v:529.6-529.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "ls180.v:530.6-530.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "ls180.v:539.11-539.66" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:540.13-540.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:542.13-542.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:541.6-541.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:556.6-556.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "ls180.v:557.6-557.50" + wire \main_sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "ls180.v:559.13-559.65" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:558.6-558.56" + wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "ls180.v:555.6-555.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:554.6-554.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "ls180.v:562.5-562.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_first + attribute \src "ls180.v:563.5-563.51" + wire \main_sdram_bankmachine0_cmd_buffer_source_last + attribute \src "ls180.v:565.12-565.66" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "ls180.v:564.5-564.57" + wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:561.6-561.53" + wire \main_sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "ls180.v:560.5-560.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:508.12-508.49" + wire width 13 \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:509.12-509.50" + wire width 2 \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:510.5-510.44" + wire \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:513.5-513.47" + wire \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:514.5-514.48" + wire \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:515.5-515.49" + wire \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:511.5-511.44" + wire \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:512.5-512.43" + wire \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:507.5-507.38" + wire \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:506.5-506.38" + wire \main_sdram_bankmachine0_cmd_valid + attribute \src "ls180.v:505.5-505.40" + wire \main_sdram_bankmachine0_refresh_gnt + attribute \src "ls180.v:504.6-504.41" + wire \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:500.13-500.45" + wire width 22 \main_sdram_bankmachine0_req_addr + attribute \src "ls180.v:501.6-501.38" + wire \main_sdram_bankmachine0_req_lock + attribute \src "ls180.v:503.5-503.44" + wire \main_sdram_bankmachine0_req_rdata_valid + attribute \src "ls180.v:498.6-498.39" + wire \main_sdram_bankmachine0_req_ready + attribute \src "ls180.v:497.6-497.39" + wire \main_sdram_bankmachine0_req_valid + attribute \src "ls180.v:502.5-502.44" + wire \main_sdram_bankmachine0_req_wdata_ready + attribute \src "ls180.v:499.6-499.36" + wire \main_sdram_bankmachine0_req_we + attribute \src "ls180.v:566.12-566.39" + wire width 13 \main_sdram_bankmachine0_row + attribute \src "ls180.v:570.5-570.38" + wire \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:571.5-571.47" + wire \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:568.6-568.37" + wire \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:569.5-569.37" + wire \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:567.5-567.39" + wire \main_sdram_bankmachine0_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:578.32-578.69" + wire \main_sdram_bankmachine0_trascon_ready + attribute \src "ls180.v:577.6-577.43" + wire \main_sdram_bankmachine0_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:576.32-576.68" + wire \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:575.6-575.42" + wire \main_sdram_bankmachine0_trccon_valid + attribute \src "ls180.v:574.11-574.48" + wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:573.32-573.69" + wire \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:572.6-572.43" + wire \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:598.5-598.43" + wire \main_sdram_bankmachine1_auto_precharge + attribute \src "ls180.v:620.11-620.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "ls180.v:625.6-625.58" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:630.6-630.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:631.6-631.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:629.13-629.78" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:628.6-628.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:634.6-634.65" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:635.6-635.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:633.13-633.79" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:632.6-632.70" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:617.11-617.61" + wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "ls180.v:619.11-619.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "ls180.v:626.12-626.67" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:627.13-627.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:618.5-618.57" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:601.5-601.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:602.5-602.59" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:604.13-604.75" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:603.6-603.66" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:600.6-600.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:599.6-599.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:607.6-607.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:608.6-608.62" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:610.13-610.77" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:609.6-609.68" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:606.6-606.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:605.6-605.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:615.13-615.71" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "ls180.v:616.13-616.72" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "ls180.v:613.6-613.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "ls180.v:614.6-614.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "ls180.v:611.6-611.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "ls180.v:612.6-612.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "ls180.v:621.11-621.66" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:622.13-622.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:624.13-624.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:623.6-623.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:638.6-638.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "ls180.v:639.6-639.50" + wire \main_sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "ls180.v:641.13-641.65" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:640.6-640.56" + wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "ls180.v:637.6-637.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:636.6-636.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "ls180.v:644.5-644.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_first + attribute \src "ls180.v:645.5-645.51" + wire \main_sdram_bankmachine1_cmd_buffer_source_last + attribute \src "ls180.v:647.12-647.66" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "ls180.v:646.5-646.57" + wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:643.6-643.53" + wire \main_sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "ls180.v:642.5-642.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:590.12-590.49" + wire width 13 \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:591.12-591.50" + wire width 2 \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:592.5-592.44" + wire \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:595.5-595.47" + wire \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:596.5-596.48" + wire \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:597.5-597.49" + wire \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:593.5-593.44" + wire \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:594.5-594.43" + wire \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:589.5-589.38" + wire \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:588.5-588.38" + wire \main_sdram_bankmachine1_cmd_valid + attribute \src "ls180.v:587.5-587.40" + wire \main_sdram_bankmachine1_refresh_gnt + attribute \src "ls180.v:586.6-586.41" + wire \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:582.13-582.45" + wire width 22 \main_sdram_bankmachine1_req_addr + attribute \src "ls180.v:583.6-583.38" + wire \main_sdram_bankmachine1_req_lock + attribute \src "ls180.v:585.5-585.44" + wire \main_sdram_bankmachine1_req_rdata_valid + attribute \src "ls180.v:580.6-580.39" + wire \main_sdram_bankmachine1_req_ready + attribute \src "ls180.v:579.6-579.39" + wire \main_sdram_bankmachine1_req_valid + attribute \src "ls180.v:584.5-584.44" + wire \main_sdram_bankmachine1_req_wdata_ready + attribute \src "ls180.v:581.6-581.36" + wire \main_sdram_bankmachine1_req_we + attribute \src "ls180.v:648.12-648.39" + wire width 13 \main_sdram_bankmachine1_row + attribute \src "ls180.v:652.5-652.38" + wire \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:653.5-653.47" + wire \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:650.6-650.37" + wire \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:651.5-651.37" + wire \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:649.5-649.39" + wire \main_sdram_bankmachine1_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:660.32-660.69" + wire \main_sdram_bankmachine1_trascon_ready + attribute \src "ls180.v:659.6-659.43" + wire \main_sdram_bankmachine1_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:658.32-658.68" + wire \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:657.6-657.42" + wire \main_sdram_bankmachine1_trccon_valid + attribute \src "ls180.v:656.11-656.48" + wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:655.32-655.69" + wire \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:654.6-654.43" + wire \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:680.5-680.43" + wire \main_sdram_bankmachine2_auto_precharge + attribute \src "ls180.v:702.11-702.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "ls180.v:707.6-707.58" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:712.6-712.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:713.6-713.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:711.13-711.78" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:710.6-710.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:716.6-716.65" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:717.6-717.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:715.13-715.79" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:714.6-714.70" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:699.11-699.61" + wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "ls180.v:701.11-701.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "ls180.v:708.12-708.67" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:709.13-709.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:700.5-700.57" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:683.5-683.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:684.5-684.59" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:686.13-686.75" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:685.6-685.66" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:682.6-682.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:681.6-681.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:689.6-689.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:690.6-690.62" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:692.13-692.77" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:691.6-691.68" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:688.6-688.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:687.6-687.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:697.13-697.71" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "ls180.v:698.13-698.72" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "ls180.v:695.6-695.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "ls180.v:696.6-696.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "ls180.v:693.6-693.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "ls180.v:694.6-694.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "ls180.v:703.11-703.66" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:704.13-704.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:706.13-706.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:705.6-705.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:720.6-720.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "ls180.v:721.6-721.50" + wire \main_sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "ls180.v:723.13-723.65" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:722.6-722.56" + wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "ls180.v:719.6-719.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:718.6-718.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "ls180.v:726.5-726.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_first + attribute \src "ls180.v:727.5-727.51" + wire \main_sdram_bankmachine2_cmd_buffer_source_last + attribute \src "ls180.v:729.12-729.66" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "ls180.v:728.5-728.57" + wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:725.6-725.53" + wire \main_sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "ls180.v:724.5-724.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:672.12-672.49" + wire width 13 \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:673.12-673.50" + wire width 2 \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:674.5-674.44" + wire \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:677.5-677.47" + wire \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:678.5-678.48" + wire \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:679.5-679.49" + wire \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:675.5-675.44" + wire \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:676.5-676.43" + wire \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:671.5-671.38" + wire \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:670.5-670.38" + wire \main_sdram_bankmachine2_cmd_valid + attribute \src "ls180.v:669.5-669.40" + wire \main_sdram_bankmachine2_refresh_gnt + attribute \src "ls180.v:668.6-668.41" + wire \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:664.13-664.45" + wire width 22 \main_sdram_bankmachine2_req_addr + attribute \src "ls180.v:665.6-665.38" + wire \main_sdram_bankmachine2_req_lock + attribute \src "ls180.v:667.5-667.44" + wire \main_sdram_bankmachine2_req_rdata_valid + attribute \src "ls180.v:662.6-662.39" + wire \main_sdram_bankmachine2_req_ready + attribute \src "ls180.v:661.6-661.39" + wire \main_sdram_bankmachine2_req_valid + attribute \src "ls180.v:666.5-666.44" + wire \main_sdram_bankmachine2_req_wdata_ready + attribute \src "ls180.v:663.6-663.36" + wire \main_sdram_bankmachine2_req_we + attribute \src "ls180.v:730.12-730.39" + wire width 13 \main_sdram_bankmachine2_row + attribute \src "ls180.v:734.5-734.38" + wire \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:735.5-735.47" + wire \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:732.6-732.37" + wire \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:733.5-733.37" + wire \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:731.5-731.39" + wire \main_sdram_bankmachine2_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:742.32-742.69" + wire \main_sdram_bankmachine2_trascon_ready + attribute \src "ls180.v:741.6-741.43" + wire \main_sdram_bankmachine2_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:740.32-740.68" + wire \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:739.6-739.42" + wire \main_sdram_bankmachine2_trccon_valid + attribute \src "ls180.v:738.11-738.48" + wire width 3 \main_sdram_bankmachine2_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:737.32-737.69" + wire \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:736.6-736.43" + wire \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:762.5-762.43" + wire \main_sdram_bankmachine3_auto_precharge + attribute \src "ls180.v:784.11-784.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "ls180.v:789.6-789.58" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:794.6-794.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:795.6-795.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:793.13-793.78" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:792.6-792.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:798.6-798.65" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:799.6-799.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:797.13-797.79" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:796.6-796.70" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:781.11-781.61" + wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "ls180.v:783.11-783.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "ls180.v:790.12-790.67" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:791.13-791.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:782.5-782.57" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:765.5-765.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:766.5-766.59" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:768.13-768.75" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:767.6-767.66" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:764.6-764.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:763.6-763.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:771.6-771.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:772.6-772.62" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:774.13-774.77" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:773.6-773.68" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:770.6-770.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:769.6-769.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:779.13-779.71" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "ls180.v:780.13-780.72" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "ls180.v:777.6-777.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "ls180.v:778.6-778.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "ls180.v:775.6-775.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "ls180.v:776.6-776.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "ls180.v:785.11-785.66" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:786.13-786.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:788.13-788.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:787.6-787.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:802.6-802.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "ls180.v:803.6-803.50" + wire \main_sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "ls180.v:805.13-805.65" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:804.6-804.56" + wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "ls180.v:801.6-801.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:800.6-800.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "ls180.v:808.5-808.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_first + attribute \src "ls180.v:809.5-809.51" + wire \main_sdram_bankmachine3_cmd_buffer_source_last + attribute \src "ls180.v:811.12-811.66" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "ls180.v:810.5-810.57" + wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:807.6-807.53" + wire \main_sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "ls180.v:806.5-806.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:754.12-754.49" + wire width 13 \main_sdram_bankmachine3_cmd_payload_a + attribute \src "ls180.v:755.12-755.50" + wire width 2 \main_sdram_bankmachine3_cmd_payload_ba + attribute \src "ls180.v:756.5-756.44" + wire \main_sdram_bankmachine3_cmd_payload_cas + attribute \src "ls180.v:759.5-759.47" + wire \main_sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "ls180.v:760.5-760.48" + wire \main_sdram_bankmachine3_cmd_payload_is_read + attribute \src "ls180.v:761.5-761.49" + wire \main_sdram_bankmachine3_cmd_payload_is_write + attribute \src "ls180.v:757.5-757.44" + wire \main_sdram_bankmachine3_cmd_payload_ras + attribute \src "ls180.v:758.5-758.43" + wire \main_sdram_bankmachine3_cmd_payload_we + attribute \src "ls180.v:753.5-753.38" + wire \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:752.5-752.38" + wire \main_sdram_bankmachine3_cmd_valid + attribute \src "ls180.v:751.5-751.40" + wire \main_sdram_bankmachine3_refresh_gnt + attribute \src "ls180.v:750.6-750.41" + wire \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:746.13-746.45" + wire width 22 \main_sdram_bankmachine3_req_addr + attribute \src "ls180.v:747.6-747.38" + wire \main_sdram_bankmachine3_req_lock + attribute \src "ls180.v:749.5-749.44" + wire \main_sdram_bankmachine3_req_rdata_valid + attribute \src "ls180.v:744.6-744.39" + wire \main_sdram_bankmachine3_req_ready + attribute \src "ls180.v:743.6-743.39" + wire \main_sdram_bankmachine3_req_valid + attribute \src "ls180.v:748.5-748.44" + wire \main_sdram_bankmachine3_req_wdata_ready + attribute \src "ls180.v:745.6-745.36" + wire \main_sdram_bankmachine3_req_we + attribute \src "ls180.v:812.12-812.39" + wire width 13 \main_sdram_bankmachine3_row + attribute \src "ls180.v:816.5-816.38" + wire \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:817.5-817.47" + wire \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:814.6-814.37" + wire \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:815.5-815.37" + wire \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:813.5-813.39" + wire \main_sdram_bankmachine3_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:824.32-824.69" + wire \main_sdram_bankmachine3_trascon_ready + attribute \src "ls180.v:823.6-823.43" + wire \main_sdram_bankmachine3_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:822.32-822.68" + wire \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:821.6-821.42" + wire \main_sdram_bankmachine3_trccon_valid + attribute \src "ls180.v:820.11-820.48" + wire width 3 \main_sdram_bankmachine3_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:819.32-819.69" + wire \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:818.6-818.43" + wire \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:826.6-826.28" + wire \main_sdram_cas_allowed + attribute \src "ls180.v:844.6-844.30" + wire \main_sdram_choose_cmd_ce + attribute \src "ls180.v:833.13-833.48" + wire width 13 \main_sdram_choose_cmd_cmd_payload_a + attribute \src "ls180.v:834.12-834.48" + wire width 2 \main_sdram_choose_cmd_cmd_payload_ba + attribute \src "ls180.v:835.5-835.42" + wire \main_sdram_choose_cmd_cmd_payload_cas + attribute \src "ls180.v:838.6-838.46" + wire \main_sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "ls180.v:839.6-839.47" + wire \main_sdram_choose_cmd_cmd_payload_is_read + attribute \src "ls180.v:840.6-840.48" + wire \main_sdram_choose_cmd_cmd_payload_is_write + attribute \src "ls180.v:836.5-836.42" + wire \main_sdram_choose_cmd_cmd_payload_ras + attribute \src "ls180.v:837.5-837.41" + wire \main_sdram_choose_cmd_cmd_payload_we + attribute \src "ls180.v:832.5-832.36" + wire \main_sdram_choose_cmd_cmd_ready + attribute \src "ls180.v:831.6-831.37" + wire \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:843.11-843.38" + wire width 2 \main_sdram_choose_cmd_grant + attribute \src "ls180.v:842.12-842.41" + wire width 4 \main_sdram_choose_cmd_request + attribute \src "ls180.v:841.11-841.39" + wire width 4 \main_sdram_choose_cmd_valids + attribute \src "ls180.v:830.5-830.41" + wire \main_sdram_choose_cmd_want_activates + attribute \src "ls180.v:829.5-829.36" + wire \main_sdram_choose_cmd_want_cmds + attribute \src "ls180.v:827.5-827.37" + wire \main_sdram_choose_cmd_want_reads + attribute \src "ls180.v:828.5-828.38" + wire \main_sdram_choose_cmd_want_writes + attribute \src "ls180.v:862.6-862.30" + wire \main_sdram_choose_req_ce + attribute \src "ls180.v:851.13-851.48" + wire width 13 \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:852.12-852.48" + wire width 2 \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:853.5-853.42" + wire \main_sdram_choose_req_cmd_payload_cas + attribute \src "ls180.v:856.6-856.46" + wire \main_sdram_choose_req_cmd_payload_is_cmd + attribute \src "ls180.v:857.6-857.47" + wire \main_sdram_choose_req_cmd_payload_is_read + attribute \src "ls180.v:858.6-858.48" + wire \main_sdram_choose_req_cmd_payload_is_write + attribute \src "ls180.v:854.5-854.42" + wire \main_sdram_choose_req_cmd_payload_ras + attribute \src "ls180.v:855.5-855.41" + wire \main_sdram_choose_req_cmd_payload_we + attribute \src "ls180.v:850.5-850.36" + wire \main_sdram_choose_req_cmd_ready + attribute \src "ls180.v:849.6-849.37" + wire \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:861.11-861.38" + wire width 2 \main_sdram_choose_req_grant + attribute \src "ls180.v:860.12-860.41" + wire width 4 \main_sdram_choose_req_request + attribute \src "ls180.v:859.11-859.39" + wire width 4 \main_sdram_choose_req_valids + attribute \src "ls180.v:848.5-848.41" + wire \main_sdram_choose_req_want_activates + attribute \src "ls180.v:847.6-847.37" + wire \main_sdram_choose_req_want_cmds + attribute \src "ls180.v:845.5-845.37" + wire \main_sdram_choose_req_want_reads + attribute \src "ls180.v:846.5-846.38" + wire \main_sdram_choose_req_want_writes + attribute \src "ls180.v:406.6-406.20" + wire \main_sdram_cke + attribute \src "ls180.v:474.5-474.24" + wire \main_sdram_cmd_last + attribute \src "ls180.v:475.12-475.36" + wire width 13 \main_sdram_cmd_payload_a + attribute \src "ls180.v:476.11-476.36" + wire width 2 \main_sdram_cmd_payload_ba + attribute \src "ls180.v:477.5-477.31" + wire \main_sdram_cmd_payload_cas + attribute \src "ls180.v:480.5-480.35" + wire \main_sdram_cmd_payload_is_read + attribute \src "ls180.v:481.5-481.36" + wire \main_sdram_cmd_payload_is_write + attribute \src "ls180.v:478.5-478.31" + wire \main_sdram_cmd_payload_ras + attribute \src "ls180.v:479.5-479.30" + wire \main_sdram_cmd_payload_we + attribute \src "ls180.v:473.5-473.25" + wire \main_sdram_cmd_ready + attribute \src "ls180.v:472.5-472.25" + wire \main_sdram_cmd_valid + attribute \src "ls180.v:414.6-414.32" + wire \main_sdram_command_issue_r + attribute \src "ls180.v:413.6-413.33" + wire \main_sdram_command_issue_re + attribute \src "ls180.v:416.5-416.31" + wire \main_sdram_command_issue_w + attribute \src "ls180.v:415.6-415.33" + wire \main_sdram_command_issue_we + attribute \src "ls180.v:412.5-412.26" + wire \main_sdram_command_re + attribute \src "ls180.v:411.11-411.37" + wire width 6 \main_sdram_command_storage + attribute \src "ls180.v:465.5-465.28" + wire \main_sdram_dfi_p0_act_n + attribute \src "ls180.v:456.12-456.37" + wire width 13 \main_sdram_dfi_p0_address + attribute \src "ls180.v:457.11-457.33" + wire width 2 \main_sdram_dfi_p0_bank + attribute \src "ls180.v:458.5-458.28" + wire \main_sdram_dfi_p0_cas_n + attribute \src "ls180.v:462.6-462.27" + wire \main_sdram_dfi_p0_cke + attribute \src "ls180.v:459.5-459.27" + wire \main_sdram_dfi_p0_cs_n + attribute \src "ls180.v:463.6-463.27" + wire \main_sdram_dfi_p0_odt + attribute \src "ls180.v:460.5-460.28" + wire \main_sdram_dfi_p0_ras_n + attribute \src "ls180.v:470.13-470.37" + wire width 16 \main_sdram_dfi_p0_rddata + attribute \src "ls180.v:469.5-469.32" + wire \main_sdram_dfi_p0_rddata_en + attribute \src "ls180.v:471.6-471.36" + wire \main_sdram_dfi_p0_rddata_valid + attribute \src "ls180.v:464.6-464.31" + wire \main_sdram_dfi_p0_reset_n + attribute \src "ls180.v:461.5-461.27" + wire \main_sdram_dfi_p0_we_n + attribute \src "ls180.v:466.13-466.37" + wire width 16 \main_sdram_dfi_p0_wrdata + attribute \src "ls180.v:467.5-467.32" + wire \main_sdram_dfi_p0_wrdata_en + attribute \src "ls180.v:468.12-468.41" + wire width 2 \main_sdram_dfi_p0_wrdata_mask + attribute \src "ls180.v:880.5-880.19" + wire \main_sdram_en0 + attribute \src "ls180.v:883.5-883.19" + wire \main_sdram_en1 + attribute \src "ls180.v:886.6-886.30" + wire \main_sdram_go_to_refresh + attribute \src "ls180.v:428.13-428.44" + wire width 22 \main_sdram_interface_bank0_addr + attribute \src "ls180.v:429.6-429.37" + wire \main_sdram_interface_bank0_lock + attribute \src "ls180.v:431.6-431.44" + wire \main_sdram_interface_bank0_rdata_valid + attribute \src "ls180.v:426.6-426.38" + wire \main_sdram_interface_bank0_ready + attribute \src "ls180.v:425.6-425.38" + wire \main_sdram_interface_bank0_valid + attribute \src "ls180.v:430.6-430.44" + wire \main_sdram_interface_bank0_wdata_ready + attribute \src "ls180.v:427.6-427.35" + wire \main_sdram_interface_bank0_we + attribute \src "ls180.v:435.13-435.44" + wire width 22 \main_sdram_interface_bank1_addr + attribute \src "ls180.v:436.6-436.37" + wire \main_sdram_interface_bank1_lock + attribute \src "ls180.v:438.6-438.44" + wire \main_sdram_interface_bank1_rdata_valid + attribute \src "ls180.v:433.6-433.38" + wire \main_sdram_interface_bank1_ready + attribute \src "ls180.v:432.6-432.38" + wire \main_sdram_interface_bank1_valid + attribute \src "ls180.v:437.6-437.44" + wire \main_sdram_interface_bank1_wdata_ready + attribute \src "ls180.v:434.6-434.35" + wire \main_sdram_interface_bank1_we + attribute \src "ls180.v:442.13-442.44" + wire width 22 \main_sdram_interface_bank2_addr + attribute \src "ls180.v:443.6-443.37" + wire \main_sdram_interface_bank2_lock + attribute \src "ls180.v:445.6-445.44" + wire \main_sdram_interface_bank2_rdata_valid + attribute \src "ls180.v:440.6-440.38" + wire \main_sdram_interface_bank2_ready + attribute \src "ls180.v:439.6-439.38" + wire \main_sdram_interface_bank2_valid + attribute \src "ls180.v:444.6-444.44" + wire \main_sdram_interface_bank2_wdata_ready + attribute \src "ls180.v:441.6-441.35" + wire \main_sdram_interface_bank2_we + attribute \src "ls180.v:449.13-449.44" + wire width 22 \main_sdram_interface_bank3_addr + attribute \src "ls180.v:450.6-450.37" + wire \main_sdram_interface_bank3_lock + attribute \src "ls180.v:452.6-452.44" + wire \main_sdram_interface_bank3_rdata_valid + attribute \src "ls180.v:447.6-447.38" + wire \main_sdram_interface_bank3_ready + attribute \src "ls180.v:446.6-446.38" + wire \main_sdram_interface_bank3_valid + attribute \src "ls180.v:451.6-451.44" + wire \main_sdram_interface_bank3_wdata_ready + attribute \src "ls180.v:448.6-448.35" + wire \main_sdram_interface_bank3_we + attribute \src "ls180.v:455.13-455.39" + wire width 16 \main_sdram_interface_rdata + attribute \src "ls180.v:453.12-453.38" + wire width 16 \main_sdram_interface_wdata + attribute \src "ls180.v:454.11-454.40" + wire width 2 \main_sdram_interface_wdata_we + attribute \src "ls180.v:366.5-366.29" + wire \main_sdram_inti_p0_act_n + attribute \src "ls180.v:357.13-357.39" + wire width 13 \main_sdram_inti_p0_address + attribute \src "ls180.v:358.12-358.35" + wire width 2 \main_sdram_inti_p0_bank + attribute \src "ls180.v:359.5-359.29" + wire \main_sdram_inti_p0_cas_n + attribute \src "ls180.v:363.6-363.28" + wire \main_sdram_inti_p0_cke + attribute \src "ls180.v:360.5-360.28" + wire \main_sdram_inti_p0_cs_n + attribute \src "ls180.v:364.6-364.28" + wire \main_sdram_inti_p0_odt + attribute \src "ls180.v:361.5-361.29" + wire \main_sdram_inti_p0_ras_n + attribute \src "ls180.v:371.12-371.37" + wire width 16 \main_sdram_inti_p0_rddata + attribute \src "ls180.v:370.6-370.34" + wire \main_sdram_inti_p0_rddata_en + attribute \src "ls180.v:372.5-372.36" + wire \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:365.6-365.32" + wire \main_sdram_inti_p0_reset_n + attribute \src "ls180.v:362.5-362.28" + wire \main_sdram_inti_p0_we_n + attribute \src "ls180.v:367.13-367.38" + wire width 16 \main_sdram_inti_p0_wrdata + attribute \src "ls180.v:368.6-368.34" + wire \main_sdram_inti_p0_wrdata_en + attribute \src "ls180.v:369.12-369.42" + wire width 2 \main_sdram_inti_p0_wrdata_mask + attribute \src "ls180.v:398.5-398.31" + wire \main_sdram_master_p0_act_n + attribute \src "ls180.v:389.12-389.40" + wire width 13 \main_sdram_master_p0_address + attribute \src "ls180.v:390.11-390.36" + wire width 2 \main_sdram_master_p0_bank + attribute \src "ls180.v:391.5-391.31" + wire \main_sdram_master_p0_cas_n + attribute \src "ls180.v:395.5-395.29" + wire \main_sdram_master_p0_cke + attribute \src "ls180.v:392.5-392.30" + wire \main_sdram_master_p0_cs_n + attribute \src "ls180.v:396.5-396.29" + wire \main_sdram_master_p0_odt + attribute \src "ls180.v:393.5-393.31" + wire \main_sdram_master_p0_ras_n + attribute \src "ls180.v:403.13-403.40" + wire width 16 \main_sdram_master_p0_rddata + attribute \src "ls180.v:402.5-402.35" + wire \main_sdram_master_p0_rddata_en + attribute \src "ls180.v:404.6-404.39" + wire \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:397.5-397.33" + wire \main_sdram_master_p0_reset_n + attribute \src "ls180.v:394.5-394.30" + wire \main_sdram_master_p0_we_n + attribute \src "ls180.v:399.12-399.39" + wire width 16 \main_sdram_master_p0_wrdata + attribute \src "ls180.v:400.5-400.35" + wire \main_sdram_master_p0_wrdata_en + attribute \src "ls180.v:401.11-401.43" + wire width 2 \main_sdram_master_p0_wrdata_mask + attribute \src "ls180.v:881.6-881.26" + wire \main_sdram_max_time0 + attribute \src "ls180.v:884.6-884.26" + wire \main_sdram_max_time1 + attribute \src "ls180.v:863.12-863.28" + wire width 13 \main_sdram_nop_a + attribute \src "ls180.v:864.11-864.28" + wire width 2 \main_sdram_nop_ba + attribute \src "ls180.v:407.6-407.20" + wire \main_sdram_odt + attribute \src "ls180.v:490.5-490.31" + wire \main_sdram_postponer_count + attribute \src "ls180.v:488.6-488.32" + wire \main_sdram_postponer_req_i + attribute \src "ls180.v:489.5-489.31" + wire \main_sdram_postponer_req_o + attribute \src "ls180.v:825.6-825.28" + wire \main_sdram_ras_allowed + attribute \src "ls180.v:410.5-410.18" + wire \main_sdram_re + attribute \src "ls180.v:878.6-878.31" + wire \main_sdram_read_available + attribute \src "ls180.v:408.6-408.24" + wire \main_sdram_reset_n + attribute \src "ls180.v:405.6-405.20" + wire \main_sdram_sel + attribute \src "ls180.v:496.5-496.31" + wire \main_sdram_sequencer_count + attribute \src "ls180.v:495.11-495.39" + wire width 4 \main_sdram_sequencer_counter + attribute \src "ls180.v:492.6-492.32" + wire \main_sdram_sequencer_done0 + attribute \src "ls180.v:494.5-494.31" + wire \main_sdram_sequencer_done1 + attribute \src "ls180.v:491.5-491.32" + wire \main_sdram_sequencer_start0 + attribute \src "ls180.v:493.6-493.33" + wire \main_sdram_sequencer_start1 + attribute \src "ls180.v:382.6-382.31" + wire \main_sdram_slave_p0_act_n + attribute \src "ls180.v:373.13-373.40" + wire width 13 \main_sdram_slave_p0_address + attribute \src "ls180.v:374.12-374.36" + wire width 2 \main_sdram_slave_p0_bank + attribute \src "ls180.v:375.6-375.31" + wire \main_sdram_slave_p0_cas_n + attribute \src "ls180.v:379.6-379.29" + wire \main_sdram_slave_p0_cke + attribute \src "ls180.v:376.6-376.30" + wire \main_sdram_slave_p0_cs_n + attribute \src "ls180.v:380.6-380.29" + wire \main_sdram_slave_p0_odt + attribute \src "ls180.v:377.6-377.31" + wire \main_sdram_slave_p0_ras_n + attribute \src "ls180.v:387.12-387.38" + wire width 16 \main_sdram_slave_p0_rddata + attribute \src "ls180.v:386.6-386.35" + wire \main_sdram_slave_p0_rddata_en + attribute \src "ls180.v:388.5-388.37" + wire \main_sdram_slave_p0_rddata_valid + attribute \src "ls180.v:381.6-381.33" + wire \main_sdram_slave_p0_reset_n + attribute \src "ls180.v:378.6-378.30" + wire \main_sdram_slave_p0_we_n + attribute \src "ls180.v:383.13-383.39" + wire width 16 \main_sdram_slave_p0_wrdata + attribute \src "ls180.v:384.6-384.35" + wire \main_sdram_slave_p0_wrdata_en + attribute \src "ls180.v:385.12-385.43" + wire width 2 \main_sdram_slave_p0_wrdata_mask + attribute \src "ls180.v:423.12-423.29" + wire width 16 \main_sdram_status + attribute \src "ls180.v:866.5-866.24" + wire \main_sdram_steerer0 + attribute \src "ls180.v:867.5-867.24" + wire \main_sdram_steerer1 + attribute \src "ls180.v:865.11-865.33" + wire width 2 \main_sdram_steerer_sel + attribute \src "ls180.v:409.11-409.29" + wire width 4 \main_sdram_storage + attribute \src "ls180.v:874.5-874.29" + wire \main_sdram_tccdcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:873.32-873.56" + wire \main_sdram_tccdcon_ready + attribute \src "ls180.v:872.6-872.30" + wire \main_sdram_tccdcon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:871.32-871.56" + wire \main_sdram_tfawcon_ready + attribute \src "ls180.v:870.6-870.30" + wire \main_sdram_tfawcon_valid + attribute \src "ls180.v:882.11-882.27" + wire width 5 \main_sdram_time0 + attribute \src "ls180.v:885.11-885.27" + wire width 4 \main_sdram_time1 + attribute \src "ls180.v:485.12-485.35" + wire width 10 \main_sdram_timer_count0 + attribute \src "ls180.v:487.11-487.34" + wire width 10 \main_sdram_timer_count1 + attribute \src "ls180.v:484.6-484.28" + wire \main_sdram_timer_done0 + attribute \src "ls180.v:486.6-486.28" + wire \main_sdram_timer_done1 + attribute \src "ls180.v:483.6-483.27" + wire \main_sdram_timer_wait + attribute \no_retiming "true" + attribute \src "ls180.v:869.32-869.56" + wire \main_sdram_trrdcon_ready + attribute \src "ls180.v:868.6-868.30" + wire \main_sdram_trrdcon_valid + attribute \src "ls180.v:877.11-877.35" + wire width 3 \main_sdram_twtrcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:876.32-876.56" + wire \main_sdram_twtrcon_ready + attribute \src "ls180.v:875.6-875.30" + wire \main_sdram_twtrcon_valid + attribute \src "ls180.v:482.6-482.30" + wire \main_sdram_wants_refresh + attribute \src "ls180.v:424.6-424.19" + wire \main_sdram_we + attribute \src "ls180.v:422.5-422.25" + wire \main_sdram_wrdata_re + attribute \src "ls180.v:421.12-421.37" + wire width 16 \main_sdram_wrdata_storage + attribute \src "ls180.v:879.6-879.32" + wire \main_sdram_write_available + attribute \src "ls180.v:914.5-914.47" + wire \main_socbushandler_converted_interface_ack + attribute \src "ls180.v:908.13-908.55" + wire width 30 \main_socbushandler_converted_interface_adr + attribute \src "ls180.v:917.12-917.54" + wire width 2 \main_socbushandler_converted_interface_bte + attribute \src "ls180.v:916.12-916.54" + wire width 3 \main_socbushandler_converted_interface_cti + attribute \src "ls180.v:912.6-912.48" + wire \main_socbushandler_converted_interface_cyc + attribute \src "ls180.v:910.13-910.57" + wire width 64 \main_socbushandler_converted_interface_dat_r + attribute \src "ls180.v:909.13-909.57" + wire width 64 \main_socbushandler_converted_interface_dat_w + attribute \src "ls180.v:918.5-918.47" + wire \main_socbushandler_converted_interface_err + attribute \src "ls180.v:911.12-911.54" + wire width 8 \main_socbushandler_converted_interface_sel + attribute \src "ls180.v:913.6-913.48" + wire \main_socbushandler_converted_interface_stb + attribute \src "ls180.v:915.6-915.47" + wire \main_socbushandler_converted_interface_we + attribute \src "ls180.v:920.5-920.31" + wire \main_socbushandler_counter + attribute \src "ls180.v:1849.5-1849.53" + wire \main_socbushandler_counter_converter2_next_value + attribute \src "ls180.v:1850.5-1850.56" + wire \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:922.12-922.36" + wire width 64 \main_socbushandler_dat_r + attribute \src "ls180.v:921.6-921.30" + wire \main_socbushandler_reset + attribute \src "ls180.v:919.5-919.28" + wire \main_socbushandler_skip + attribute \src "ls180.v:1097.6-1097.27" + wire \main_spimaster0_start + attribute \src "ls180.v:1107.12-1107.35" + wire width 8 \main_spimaster10_length + attribute \src "ls180.v:1108.12-1108.36" + wire width 16 \main_spimaster11_storage + attribute \src "ls180.v:1109.5-1109.24" + wire \main_spimaster12_re + attribute \src "ls180.v:1110.6-1110.27" + wire \main_spimaster13_done + attribute \src "ls180.v:1111.6-1111.29" + wire \main_spimaster14_status + attribute \src "ls180.v:1112.6-1112.25" + wire \main_spimaster15_we + attribute \src "ls180.v:1113.11-1113.35" + wire width 8 \main_spimaster16_storage + attribute \src "ls180.v:1114.5-1114.24" + wire \main_spimaster17_re + attribute \src "ls180.v:1115.12-1115.35" + wire width 8 \main_spimaster18_status + attribute \src "ls180.v:1116.6-1116.25" + wire \main_spimaster19_we + attribute \src "ls180.v:1098.12-1098.34" + wire width 8 \main_spimaster1_length + attribute \src "ls180.v:1170.5-1170.23" + wire \main_spimaster1_re + attribute \src "ls180.v:1169.12-1169.35" + wire width 16 \main_spimaster1_storage + attribute \src "ls180.v:1117.6-1117.26" + wire \main_spimaster20_sel + attribute \src "ls180.v:1118.5-1118.29" + wire \main_spimaster21_storage + attribute \src "ls180.v:1119.5-1119.24" + wire \main_spimaster22_re + attribute \src "ls180.v:1120.5-1120.29" + wire \main_spimaster23_storage + attribute \src "ls180.v:1121.5-1121.24" + wire \main_spimaster24_re + attribute \src "ls180.v:1122.5-1122.32" + wire \main_spimaster25_clk_enable + attribute \src "ls180.v:1123.5-1123.31" + wire \main_spimaster26_cs_enable + attribute \src "ls180.v:1124.11-1124.33" + wire width 3 \main_spimaster27_count + attribute \src "ls180.v:1890.11-1890.55" + wire width 3 \main_spimaster27_count_spimaster0_next_value + attribute \src "ls180.v:1891.5-1891.52" + wire \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:1125.5-1125.32" + wire \main_spimaster28_mosi_latch + attribute \src "ls180.v:1126.5-1126.32" + wire \main_spimaster29_miso_latch + attribute \src "ls180.v:1099.5-1099.25" + wire \main_spimaster2_done + attribute \src "ls180.v:1127.12-1127.40" + wire width 16 \main_spimaster30_clk_divider + attribute \src "ls180.v:1128.6-1128.31" + wire \main_spimaster31_clk_rise + attribute \src "ls180.v:1129.6-1129.31" + wire \main_spimaster32_clk_fall + attribute \src "ls180.v:1130.11-1130.37" + wire width 8 \main_spimaster33_mosi_data + attribute \src "ls180.v:1131.11-1131.36" + wire width 3 \main_spimaster34_mosi_sel + attribute \src "ls180.v:1132.11-1132.37" + wire width 8 \main_spimaster35_miso_data + attribute \src "ls180.v:1100.5-1100.24" + wire \main_spimaster3_irq + attribute \src "ls180.v:1101.12-1101.32" + wire width 8 \main_spimaster4_mosi + attribute \src "ls180.v:1102.11-1102.31" + wire width 8 \main_spimaster5_miso + attribute \src "ls180.v:1103.6-1103.24" + wire \main_spimaster6_cs + attribute \src "ls180.v:1104.6-1104.30" + wire \main_spimaster7_loopback + attribute \src "ls180.v:1105.12-1105.39" + wire width 16 \main_spimaster8_clk_divider + attribute \src "ls180.v:1106.5-1106.26" + wire \main_spimaster9_start + attribute \src "ls180.v:1141.13-1141.40" + wire width 16 \main_spisdcard_clk_divider0 + attribute \src "ls180.v:1163.12-1163.39" + wire width 16 \main_spisdcard_clk_divider1 + attribute \src "ls180.v:1158.5-1158.30" + wire \main_spisdcard_clk_enable + attribute \src "ls180.v:1165.6-1165.29" + wire \main_spisdcard_clk_fall + attribute \src "ls180.v:1164.6-1164.29" + wire \main_spisdcard_clk_rise + attribute \src "ls180.v:1145.5-1145.30" + wire \main_spisdcard_control_re + attribute \src "ls180.v:1144.12-1144.42" + wire width 16 \main_spisdcard_control_storage + attribute \src "ls180.v:1160.11-1160.31" + wire width 3 \main_spisdcard_count + attribute \src "ls180.v:1894.11-1894.53" + wire width 3 \main_spisdcard_count_spimaster1_next_value + attribute \src "ls180.v:1895.5-1895.50" + wire \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:1139.6-1139.23" + wire \main_spisdcard_cs + attribute \src "ls180.v:1159.5-1159.29" + wire \main_spisdcard_cs_enable + attribute \src "ls180.v:1155.5-1155.25" + wire \main_spisdcard_cs_re + attribute \src "ls180.v:1154.5-1154.30" + wire \main_spisdcard_cs_storage + attribute \src "ls180.v:1135.5-1135.25" + wire \main_spisdcard_done0 + attribute \src "ls180.v:1146.6-1146.26" + wire \main_spisdcard_done1 + attribute \src "ls180.v:1136.5-1136.23" + wire \main_spisdcard_irq + attribute \src "ls180.v:1134.12-1134.34" + wire width 8 \main_spisdcard_length0 + attribute \src "ls180.v:1143.12-1143.34" + wire width 8 \main_spisdcard_length1 + attribute \src "ls180.v:1140.6-1140.29" + wire \main_spisdcard_loopback + attribute \src "ls180.v:1157.5-1157.31" + wire \main_spisdcard_loopback_re + attribute \src "ls180.v:1156.5-1156.36" + wire \main_spisdcard_loopback_storage + attribute \src "ls180.v:1138.11-1138.30" + wire width 8 \main_spisdcard_miso + attribute \src "ls180.v:1168.11-1168.35" + wire width 8 \main_spisdcard_miso_data + attribute \src "ls180.v:1162.5-1162.30" + wire \main_spisdcard_miso_latch + attribute \src "ls180.v:1151.12-1151.38" + wire width 8 \main_spisdcard_miso_status + attribute \src "ls180.v:1152.6-1152.28" + wire \main_spisdcard_miso_we + attribute \src "ls180.v:1137.12-1137.31" + wire width 8 \main_spisdcard_mosi + attribute \src "ls180.v:1166.11-1166.35" + wire width 8 \main_spisdcard_mosi_data + attribute \src "ls180.v:1161.5-1161.30" + wire \main_spisdcard_mosi_latch + attribute \src "ls180.v:1150.5-1150.27" + wire \main_spisdcard_mosi_re + attribute \src "ls180.v:1167.11-1167.34" + wire width 3 \main_spisdcard_mosi_sel + attribute \src "ls180.v:1149.11-1149.38" + wire width 8 \main_spisdcard_mosi_storage + attribute \src "ls180.v:1153.6-1153.24" + wire \main_spisdcard_sel + attribute \src "ls180.v:1133.6-1133.27" + wire \main_spisdcard_start0 + attribute \src "ls180.v:1142.5-1142.26" + wire \main_spisdcard_start1 + attribute \src "ls180.v:1147.6-1147.34" + wire \main_spisdcard_status_status + attribute \src "ls180.v:1148.6-1148.30" + wire \main_spisdcard_status_we + attribute \src "ls180.v:257.12-257.26" + wire width 6 \main_sram0_adr + attribute \src "ls180.v:258.13-258.29" + wire width 64 \main_sram0_dat_r + attribute \src "ls180.v:260.13-260.29" + wire width 64 \main_sram0_dat_w + attribute \src "ls180.v:259.11-259.24" + wire width 8 \main_sram0_we + attribute \src "ls180.v:272.12-272.26" + wire width 6 \main_sram1_adr + attribute \src "ls180.v:273.13-273.29" + wire width 64 \main_sram1_dat_r + attribute \src "ls180.v:275.13-275.29" + wire width 64 \main_sram1_dat_w + attribute \src "ls180.v:274.11-274.24" + wire width 8 \main_sram1_we + attribute \src "ls180.v:287.12-287.26" + wire width 6 \main_sram2_adr + attribute \src "ls180.v:288.13-288.29" + wire width 64 \main_sram2_dat_r + attribute \src "ls180.v:290.13-290.29" + wire width 64 \main_sram2_dat_w + attribute \src "ls180.v:289.11-289.24" + wire width 8 \main_sram2_we + attribute \src "ls180.v:302.12-302.26" + wire width 6 \main_sram3_adr + attribute \src "ls180.v:303.13-303.29" + wire width 64 \main_sram3_dat_r + attribute \src "ls180.v:305.13-305.29" + wire width 64 \main_sram3_dat_w + attribute \src "ls180.v:304.11-304.24" + wire width 8 \main_sram3_we + attribute \src "ls180.v:988.12-988.44" + wire width 2 \main_uart_eventmanager_pending_r + attribute \src "ls180.v:987.6-987.39" + wire \main_uart_eventmanager_pending_re + attribute \src "ls180.v:990.11-990.43" + wire width 2 \main_uart_eventmanager_pending_w + attribute \src "ls180.v:989.6-989.39" + wire \main_uart_eventmanager_pending_we + attribute \src "ls180.v:992.5-992.30" + wire \main_uart_eventmanager_re + attribute \src "ls180.v:984.12-984.43" + wire width 2 \main_uart_eventmanager_status_r + attribute \src "ls180.v:983.6-983.38" + wire \main_uart_eventmanager_status_re + attribute \src "ls180.v:986.11-986.42" + wire width 2 \main_uart_eventmanager_status_w + attribute \src "ls180.v:985.6-985.38" + wire \main_uart_eventmanager_status_we + attribute \src "ls180.v:991.11-991.41" + wire width 2 \main_uart_eventmanager_storage + attribute \src "ls180.v:972.6-972.19" + wire \main_uart_irq + attribute \src "ls180.v:958.12-958.46" + wire width 32 \main_uart_phy_phase_accumulator_rx + attribute \src "ls180.v:948.12-948.46" + wire width 32 \main_uart_phy_phase_accumulator_tx + attribute \src "ls180.v:941.5-941.21" + wire \main_uart_phy_re + attribute \src "ls180.v:959.6-959.22" + wire \main_uart_phy_rx + attribute \src "ls180.v:962.11-962.36" + wire width 4 \main_uart_phy_rx_bitcount + attribute \src "ls180.v:963.5-963.26" + wire \main_uart_phy_rx_busy + attribute \src "ls180.v:960.5-960.23" + wire \main_uart_phy_rx_r + attribute \src "ls180.v:961.11-961.31" + wire width 8 \main_uart_phy_rx_reg + attribute \src "ls180.v:944.6-944.30" + wire \main_uart_phy_sink_first + attribute \src "ls180.v:945.6-945.29" + wire \main_uart_phy_sink_last + attribute \src "ls180.v:946.12-946.43" + wire width 8 \main_uart_phy_sink_payload_data + attribute \src "ls180.v:943.5-943.29" + wire \main_uart_phy_sink_ready + attribute \src "ls180.v:942.6-942.30" + wire \main_uart_phy_sink_valid + attribute \src "ls180.v:954.5-954.31" + wire \main_uart_phy_source_first + attribute \src "ls180.v:955.5-955.30" + wire \main_uart_phy_source_last + attribute \src "ls180.v:956.11-956.44" + wire width 8 \main_uart_phy_source_payload_data + attribute \src "ls180.v:953.6-953.32" + wire \main_uart_phy_source_ready + attribute \src "ls180.v:952.5-952.31" + wire \main_uart_phy_source_valid + attribute \src "ls180.v:940.12-940.33" + wire width 32 \main_uart_phy_storage + attribute \src "ls180.v:950.11-950.36" + wire width 4 \main_uart_phy_tx_bitcount + attribute \src "ls180.v:951.5-951.26" + wire \main_uart_phy_tx_busy + attribute \src "ls180.v:949.11-949.31" + wire width 8 \main_uart_phy_tx_reg + attribute \src "ls180.v:957.5-957.32" + wire \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:947.5-947.32" + wire \main_uart_phy_uart_clk_txen + attribute \src "ls180.v:1081.5-1081.20" + wire \main_uart_reset + attribute \src "ls180.v:981.5-981.23" + wire \main_uart_rx_clear + attribute \src "ls180.v:1065.11-1065.36" + wire width 4 \main_uart_rx_fifo_consume + attribute \src "ls180.v:1070.6-1070.31" + wire \main_uart_rx_fifo_do_read + attribute \src "ls180.v:1076.6-1076.37" + wire \main_uart_rx_fifo_fifo_in_first + attribute \src "ls180.v:1077.6-1077.36" + wire \main_uart_rx_fifo_fifo_in_last + attribute \src "ls180.v:1075.12-1075.50" + wire width 8 \main_uart_rx_fifo_fifo_in_payload_data + attribute \src "ls180.v:1079.6-1079.38" + wire \main_uart_rx_fifo_fifo_out_first + attribute \src "ls180.v:1080.6-1080.37" + wire \main_uart_rx_fifo_fifo_out_last + attribute \src "ls180.v:1078.12-1078.51" + wire width 8 \main_uart_rx_fifo_fifo_out_payload_data + attribute \src "ls180.v:1062.11-1062.35" + wire width 5 \main_uart_rx_fifo_level0 + attribute \src "ls180.v:1074.12-1074.36" + wire width 5 \main_uart_rx_fifo_level1 + attribute \src "ls180.v:1064.11-1064.36" + wire width 4 \main_uart_rx_fifo_produce + attribute \src "ls180.v:1071.12-1071.40" + wire width 4 \main_uart_rx_fifo_rdport_adr + attribute \src "ls180.v:1072.12-1072.42" + wire width 10 \main_uart_rx_fifo_rdport_dat_r + attribute \src "ls180.v:1073.6-1073.33" + wire \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:1054.6-1054.26" + wire \main_uart_rx_fifo_re + attribute \src "ls180.v:1055.5-1055.31" + wire \main_uart_rx_fifo_readable + attribute \src "ls180.v:1063.5-1063.30" + wire \main_uart_rx_fifo_replace + attribute \src "ls180.v:1046.6-1046.34" + wire \main_uart_rx_fifo_sink_first + attribute \src "ls180.v:1047.6-1047.33" + wire \main_uart_rx_fifo_sink_last + attribute \src "ls180.v:1048.12-1048.47" + wire width 8 \main_uart_rx_fifo_sink_payload_data + attribute \src "ls180.v:1045.6-1045.34" + wire \main_uart_rx_fifo_sink_ready + attribute \src "ls180.v:1044.6-1044.34" + wire \main_uart_rx_fifo_sink_valid + attribute \src "ls180.v:1051.6-1051.36" + wire \main_uart_rx_fifo_source_first + attribute \src "ls180.v:1052.6-1052.35" + wire \main_uart_rx_fifo_source_last + attribute \src "ls180.v:1053.12-1053.49" + wire width 8 \main_uart_rx_fifo_source_payload_data + attribute \src "ls180.v:1050.6-1050.36" + wire \main_uart_rx_fifo_source_ready + attribute \src "ls180.v:1049.6-1049.36" + wire \main_uart_rx_fifo_source_valid + attribute \src "ls180.v:1060.12-1060.42" + wire width 10 \main_uart_rx_fifo_syncfifo_din + attribute \src "ls180.v:1061.12-1061.43" + wire width 10 \main_uart_rx_fifo_syncfifo_dout + attribute \src "ls180.v:1058.6-1058.35" + wire \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:1059.6-1059.41" + wire \main_uart_rx_fifo_syncfifo_readable + attribute \src "ls180.v:1056.6-1056.35" + wire \main_uart_rx_fifo_syncfifo_we + attribute \src "ls180.v:1057.6-1057.41" + wire \main_uart_rx_fifo_syncfifo_writable + attribute \src "ls180.v:1066.11-1066.39" + wire width 4 \main_uart_rx_fifo_wrport_adr + attribute \src "ls180.v:1067.12-1067.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_r + attribute \src "ls180.v:1069.12-1069.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_w + attribute \src "ls180.v:1068.6-1068.33" + wire \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:982.5-982.29" + wire \main_uart_rx_old_trigger + attribute \src "ls180.v:979.5-979.25" + wire \main_uart_rx_pending + attribute \src "ls180.v:978.6-978.25" + wire \main_uart_rx_status + attribute \src "ls180.v:980.6-980.26" + wire \main_uart_rx_trigger + attribute \src "ls180.v:970.6-970.30" + wire \main_uart_rxempty_status + attribute \src "ls180.v:971.6-971.26" + wire \main_uart_rxempty_we + attribute \src "ls180.v:995.6-995.29" + wire \main_uart_rxfull_status + attribute \src "ls180.v:996.6-996.25" + wire \main_uart_rxfull_we + attribute \src "ls180.v:965.12-965.28" + wire width 8 \main_uart_rxtx_r + attribute \src "ls180.v:964.6-964.23" + wire \main_uart_rxtx_re + attribute \src "ls180.v:967.12-967.28" + wire width 8 \main_uart_rxtx_w + attribute \src "ls180.v:966.6-966.23" + wire \main_uart_rxtx_we + attribute \src "ls180.v:976.5-976.23" + wire \main_uart_tx_clear + attribute \src "ls180.v:1028.11-1028.36" + wire width 4 \main_uart_tx_fifo_consume + attribute \src "ls180.v:1033.6-1033.31" + wire \main_uart_tx_fifo_do_read + attribute \src "ls180.v:1039.6-1039.37" + wire \main_uart_tx_fifo_fifo_in_first + attribute \src "ls180.v:1040.6-1040.36" + wire \main_uart_tx_fifo_fifo_in_last + attribute \src "ls180.v:1038.12-1038.50" + wire width 8 \main_uart_tx_fifo_fifo_in_payload_data + attribute \src "ls180.v:1042.6-1042.38" + wire \main_uart_tx_fifo_fifo_out_first + attribute \src "ls180.v:1043.6-1043.37" + wire \main_uart_tx_fifo_fifo_out_last + attribute \src "ls180.v:1041.12-1041.51" + wire width 8 \main_uart_tx_fifo_fifo_out_payload_data + attribute \src "ls180.v:1025.11-1025.35" + wire width 5 \main_uart_tx_fifo_level0 + attribute \src "ls180.v:1037.12-1037.36" + wire width 5 \main_uart_tx_fifo_level1 + attribute \src "ls180.v:1027.11-1027.36" + wire width 4 \main_uart_tx_fifo_produce + attribute \src "ls180.v:1034.12-1034.40" + wire width 4 \main_uart_tx_fifo_rdport_adr + attribute \src "ls180.v:1035.12-1035.42" + wire width 10 \main_uart_tx_fifo_rdport_dat_r + attribute \src "ls180.v:1036.6-1036.33" + wire \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:1017.6-1017.26" + wire \main_uart_tx_fifo_re + attribute \src "ls180.v:1018.5-1018.31" + wire \main_uart_tx_fifo_readable + attribute \src "ls180.v:1026.5-1026.30" + wire \main_uart_tx_fifo_replace + attribute \src "ls180.v:1009.5-1009.33" + wire \main_uart_tx_fifo_sink_first + attribute \src "ls180.v:1010.5-1010.32" + wire \main_uart_tx_fifo_sink_last + attribute \src "ls180.v:1011.12-1011.47" + wire width 8 \main_uart_tx_fifo_sink_payload_data + attribute \src "ls180.v:1008.6-1008.34" + wire \main_uart_tx_fifo_sink_ready + attribute \src "ls180.v:1007.6-1007.34" + wire \main_uart_tx_fifo_sink_valid + attribute \src "ls180.v:1014.6-1014.36" + wire \main_uart_tx_fifo_source_first + attribute \src "ls180.v:1015.6-1015.35" + wire \main_uart_tx_fifo_source_last + attribute \src "ls180.v:1016.12-1016.49" + wire width 8 \main_uart_tx_fifo_source_payload_data + attribute \src "ls180.v:1013.6-1013.36" + wire \main_uart_tx_fifo_source_ready + attribute \src "ls180.v:1012.6-1012.36" + wire \main_uart_tx_fifo_source_valid + attribute \src "ls180.v:1023.12-1023.42" + wire width 10 \main_uart_tx_fifo_syncfifo_din + attribute \src "ls180.v:1024.12-1024.43" + wire width 10 \main_uart_tx_fifo_syncfifo_dout + attribute \src "ls180.v:1021.6-1021.35" + wire \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:1022.6-1022.41" + wire \main_uart_tx_fifo_syncfifo_readable + attribute \src "ls180.v:1019.6-1019.35" + wire \main_uart_tx_fifo_syncfifo_we + attribute \src "ls180.v:1020.6-1020.41" + wire \main_uart_tx_fifo_syncfifo_writable + attribute \src "ls180.v:1029.11-1029.39" + wire width 4 \main_uart_tx_fifo_wrport_adr + attribute \src "ls180.v:1030.12-1030.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_r + attribute \src "ls180.v:1032.12-1032.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_w + attribute \src "ls180.v:1031.6-1031.33" + wire \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:977.5-977.29" + wire \main_uart_tx_old_trigger + attribute \src "ls180.v:974.5-974.25" + wire \main_uart_tx_pending + attribute \src "ls180.v:973.6-973.25" + wire \main_uart_tx_status + attribute \src "ls180.v:975.6-975.26" + wire \main_uart_tx_trigger + attribute \src "ls180.v:993.6-993.30" + wire \main_uart_txempty_status + attribute \src "ls180.v:994.6-994.26" + wire \main_uart_txempty_we + attribute \src "ls180.v:968.6-968.29" + wire \main_uart_txfull_status + attribute \src "ls180.v:969.6-969.25" + wire \main_uart_txfull_we + attribute \src "ls180.v:999.6-999.31" + wire \main_uart_uart_sink_first + attribute \src "ls180.v:1000.6-1000.30" + wire \main_uart_uart_sink_last + attribute \src "ls180.v:1001.12-1001.44" + wire width 8 \main_uart_uart_sink_payload_data + attribute \src "ls180.v:998.6-998.31" + wire \main_uart_uart_sink_ready + attribute \src "ls180.v:997.6-997.31" + wire \main_uart_uart_sink_valid + attribute \src "ls180.v:1004.6-1004.33" + wire \main_uart_uart_source_first + attribute \src "ls180.v:1005.6-1005.32" + wire \main_uart_uart_source_last + attribute \src "ls180.v:1006.12-1006.46" + wire width 8 \main_uart_uart_source_payload_data + attribute \src "ls180.v:1003.6-1003.33" + wire \main_uart_uart_source_ready + attribute \src "ls180.v:1002.6-1002.33" + wire \main_uart_uart_source_valid + attribute \src "ls180.v:906.5-906.22" + wire \main_wb_sdram_ack + attribute \src "ls180.v:900.12-900.29" + wire width 30 \main_wb_sdram_adr + attribute \src "ls180.v:904.5-904.22" + wire \main_wb_sdram_cyc + attribute \src "ls180.v:902.13-902.32" + wire width 32 \main_wb_sdram_dat_r + attribute \src "ls180.v:901.12-901.31" + wire width 32 \main_wb_sdram_dat_w + attribute \src "ls180.v:903.11-903.28" + wire width 4 \main_wb_sdram_sel + attribute \src "ls180.v:905.5-905.22" + wire \main_wb_sdram_stb + attribute \src "ls180.v:907.5-907.21" + wire \main_wb_sdram_we + attribute \src "ls180.v:936.5-936.24" + wire \main_wdata_consumed + attribute \src "ls180.v:10349.11-10349.17" + wire width 6 \memadr + attribute \src "ls180.v:10377.11-10377.19" + wire width 6 \memadr_1 + attribute \src "ls180.v:10405.11-10405.19" + wire width 6 \memadr_2 + attribute \src "ls180.v:10433.11-10433.19" + wire width 6 \memadr_3 + attribute \src "ls180.v:10461.11-10461.19" + wire width 6 \memadr_4 + attribute \src "ls180.v:10489.12-10489.18" + wire width 25 \memdat + attribute \src "ls180.v:10503.12-10503.20" + wire width 25 \memdat_1 + attribute \src "ls180.v:10517.12-10517.20" + wire width 25 \memdat_2 + attribute \src "ls180.v:10531.12-10531.20" + wire width 25 \memdat_3 + attribute \src "ls180.v:10545.11-10545.19" + wire width 10 \memdat_4 + attribute \src "ls180.v:10546.11-10546.19" + wire width 10 \memdat_5 + attribute \src "ls180.v:10562.11-10562.19" + wire width 10 \memdat_6 + attribute \src "ls180.v:10563.11-10563.19" + wire width 10 \memdat_7 + attribute \src "ls180.v:10579.11-10579.19" + wire width 10 \memdat_8 + attribute \src "ls180.v:10593.11-10593.19" + wire width 10 \memdat_9 + attribute \src "ls180.v:52.20-52.22" + wire width 24 input 48 \nc + attribute \src "ls180.v:338.6-338.13" + wire \por_clk + attribute \src "ls180.v:42.19-42.22" + wire width 2 output 38 \pwm + attribute \src "ls180.v:203.12-203.17" + wire width 2 \pwm_1 + attribute \src "ls180.v:31.13-31.23" + wire output 27 \sdcard_clk + attribute \src "ls180.v:32.13-32.25" + wire input 28 \sdcard_cmd_i + attribute \src "ls180.v:33.13-33.25" + wire output 29 \sdcard_cmd_o + attribute \src "ls180.v:34.13-34.26" + wire output 30 \sdcard_cmd_oe + attribute \src "ls180.v:35.19-35.32" + wire width 4 input 31 \sdcard_data_i + attribute \src "ls180.v:36.19-36.32" + wire width 4 output 32 \sdcard_data_o + attribute \src "ls180.v:37.13-37.27" + wire output 33 \sdcard_data_oe + attribute \src "ls180.v:18.20-18.27" + wire width 13 output 14 \sdram_a + attribute \src "ls180.v:27.19-27.27" + wire width 2 output 23 \sdram_ba + attribute \src "ls180.v:24.13-24.24" + wire output 20 \sdram_cas_n + attribute \src "ls180.v:26.13-26.22" + wire output 22 \sdram_cke + attribute \src "ls180.v:29.13-29.24" + wire output 25 \sdram_clock + attribute \src "ls180.v:193.6-193.19" + wire \sdram_clock_1 + attribute \src "ls180.v:25.13-25.23" + wire output 21 \sdram_cs_n + attribute \src "ls180.v:28.19-28.27" + wire width 2 output 24 \sdram_dm + attribute \src "ls180.v:19.20-19.30" + wire width 16 input 15 \sdram_dq_i + attribute \src "ls180.v:20.20-20.30" + wire width 16 output 16 \sdram_dq_o + attribute \src "ls180.v:21.13-21.24" + wire output 17 \sdram_dq_oe + attribute \src "ls180.v:23.13-23.24" + wire output 19 \sdram_ras_n + attribute \src "ls180.v:22.13-22.23" + wire output 18 \sdram_we_n + attribute \src "ls180.v:2760.6-2760.15" + wire \sdrio_clk + attribute \src "ls180.v:2761.6-2761.17" + wire \sdrio_clk_1 + attribute \src "ls180.v:2770.6-2770.18" + wire \sdrio_clk_10 + attribute \src "ls180.v:2771.6-2771.18" + wire \sdrio_clk_11 + attribute \src "ls180.v:2772.6-2772.18" + wire \sdrio_clk_12 + attribute \src "ls180.v:2773.6-2773.18" + wire \sdrio_clk_13 + attribute \src "ls180.v:2774.6-2774.18" + wire \sdrio_clk_14 + attribute \src "ls180.v:2775.6-2775.18" + wire \sdrio_clk_15 + attribute \src "ls180.v:2776.6-2776.18" + wire \sdrio_clk_16 + attribute \src "ls180.v:2777.6-2777.18" + wire \sdrio_clk_17 + attribute \src "ls180.v:2778.6-2778.18" + wire \sdrio_clk_18 + attribute \src "ls180.v:2779.6-2779.18" + wire \sdrio_clk_19 + attribute \src "ls180.v:2762.6-2762.17" + wire \sdrio_clk_2 + attribute \src "ls180.v:2780.6-2780.18" + wire \sdrio_clk_20 + attribute \src "ls180.v:2781.6-2781.18" + wire \sdrio_clk_21 + attribute \src "ls180.v:2782.6-2782.18" + wire \sdrio_clk_22 + attribute \src "ls180.v:2783.6-2783.18" + wire \sdrio_clk_23 + attribute \src "ls180.v:2784.6-2784.18" + wire \sdrio_clk_24 + attribute \src "ls180.v:2785.6-2785.18" + wire \sdrio_clk_25 + attribute \src "ls180.v:2786.6-2786.18" + wire \sdrio_clk_26 + attribute \src "ls180.v:2787.6-2787.18" + wire \sdrio_clk_27 + attribute \src "ls180.v:2788.6-2788.18" + wire \sdrio_clk_28 + attribute \src "ls180.v:2789.6-2789.18" + wire \sdrio_clk_29 + attribute \src "ls180.v:2763.6-2763.17" + wire \sdrio_clk_3 + attribute \src "ls180.v:2790.6-2790.18" + wire \sdrio_clk_30 + attribute \src "ls180.v:2791.6-2791.18" + wire \sdrio_clk_31 + attribute \src "ls180.v:2792.6-2792.18" + wire \sdrio_clk_32 + attribute \src "ls180.v:2793.6-2793.18" + wire \sdrio_clk_33 + attribute \src "ls180.v:2794.6-2794.18" + wire \sdrio_clk_34 + attribute \src "ls180.v:2795.6-2795.18" + wire \sdrio_clk_35 + attribute \src "ls180.v:2796.6-2796.18" + wire \sdrio_clk_36 + attribute \src "ls180.v:2797.6-2797.18" + wire \sdrio_clk_37 + attribute \src "ls180.v:2798.6-2798.18" + wire \sdrio_clk_38 + attribute \src "ls180.v:2799.6-2799.18" + wire \sdrio_clk_39 + attribute \src "ls180.v:2764.6-2764.17" + wire \sdrio_clk_4 + attribute \src "ls180.v:2800.6-2800.18" + wire \sdrio_clk_40 + attribute \src "ls180.v:2801.6-2801.18" + wire \sdrio_clk_41 + attribute \src "ls180.v:2802.6-2802.18" + wire \sdrio_clk_42 + attribute \src "ls180.v:2803.6-2803.18" + wire \sdrio_clk_43 + attribute \src "ls180.v:2804.6-2804.18" + wire \sdrio_clk_44 + attribute \src "ls180.v:2805.6-2805.18" + wire \sdrio_clk_45 + attribute \src "ls180.v:2806.6-2806.18" + wire \sdrio_clk_46 + attribute \src "ls180.v:2807.6-2807.18" + wire \sdrio_clk_47 + attribute \src "ls180.v:2808.6-2808.18" + wire \sdrio_clk_48 + attribute \src "ls180.v:2809.6-2809.18" + wire \sdrio_clk_49 + attribute \src "ls180.v:2765.6-2765.17" + wire \sdrio_clk_5 + attribute \src "ls180.v:2810.6-2810.18" + wire \sdrio_clk_50 + attribute \src "ls180.v:2811.6-2811.18" + wire \sdrio_clk_51 + attribute \src "ls180.v:2812.6-2812.18" + wire \sdrio_clk_52 + attribute \src "ls180.v:2813.6-2813.18" + wire \sdrio_clk_53 + attribute \src "ls180.v:2814.6-2814.18" + wire \sdrio_clk_54 + attribute \src "ls180.v:2815.6-2815.18" + wire \sdrio_clk_55 + attribute \src "ls180.v:2850.6-2850.18" + wire \sdrio_clk_56 + attribute \src "ls180.v:2851.6-2851.18" + wire \sdrio_clk_57 + attribute \src "ls180.v:2852.6-2852.18" + wire \sdrio_clk_58 + attribute \src "ls180.v:2853.6-2853.18" + wire \sdrio_clk_59 + attribute \src "ls180.v:2766.6-2766.17" + wire \sdrio_clk_6 + attribute \src "ls180.v:2854.6-2854.18" + wire \sdrio_clk_60 + attribute \src "ls180.v:2855.6-2855.18" + wire \sdrio_clk_61 + attribute \src "ls180.v:2856.6-2856.18" + wire \sdrio_clk_62 + attribute \src "ls180.v:2857.6-2857.18" + wire \sdrio_clk_63 + attribute \src "ls180.v:2858.6-2858.18" + wire \sdrio_clk_64 + attribute \src "ls180.v:2859.6-2859.18" + wire \sdrio_clk_65 + attribute \src "ls180.v:2860.6-2860.18" + wire \sdrio_clk_66 + attribute \src "ls180.v:2861.6-2861.18" + wire \sdrio_clk_67 + attribute \src "ls180.v:2862.6-2862.18" + wire \sdrio_clk_68 + attribute \src "ls180.v:2767.6-2767.17" + wire \sdrio_clk_7 + attribute \src "ls180.v:2768.6-2768.17" + wire \sdrio_clk_8 + attribute \src "ls180.v:2769.6-2769.17" + wire \sdrio_clk_9 + attribute \src "ls180.v:38.13-38.26" + wire output 34 \spimaster_clk + attribute \src "ls180.v:40.13-40.27" + wire output 36 \spimaster_cs_n + attribute \src "ls180.v:41.13-41.27" + wire input 37 \spimaster_miso + attribute \src "ls180.v:39.13-39.27" + wire output 35 \spimaster_mosi + attribute \src "ls180.v:14.13-14.26" + wire output 10 \spisdcard_clk + attribute \src "ls180.v:16.13-16.27" + wire output 12 \spisdcard_cs_n + attribute \src "ls180.v:17.13-17.27" + wire input 13 \spisdcard_miso + attribute \src "ls180.v:15.13-15.27" + wire output 11 \spisdcard_mosi + attribute \src "ls180.v:43.13-43.20" + wire input 39 \sys_clk + attribute \src "ls180.v:336.6-336.15" + wire \sys_clk_1 + attribute \src "ls180.v:45.19-45.31" + wire width 2 input 41 \sys_clksel_i + attribute \src "ls180.v:46.14-46.26" + wire output 42 \sys_pll_18_o + attribute \src "ls180.v:47.14-47.27" + wire output 43 \sys_pll_lck_o + attribute \src "ls180.v:44.13-44.20" + wire input 40 \sys_rst + attribute \src "ls180.v:337.6-337.15" + wire \sys_rst_1 + attribute \src "ls180.v:13.13-13.20" + wire input 9 \uart_rx + attribute \src "ls180.v:12.13-12.20" + wire output 8 \uart_tx + attribute \src "ls180.v:10348.12-10348.15" + memory width 64 size 64 \mem + attribute \src "ls180.v:10376.12-10376.17" + memory width 64 size 64 \mem_1 + attribute \src "ls180.v:10404.12-10404.17" + memory width 64 size 64 \mem_2 + attribute \src "ls180.v:10432.12-10432.17" + memory width 64 size 64 \mem_3 + attribute \src "ls180.v:10460.12-10460.17" + memory width 64 size 64 \mem_4 + attribute \src "ls180.v:10488.12-10488.19" + memory width 25 size 8 \storage + attribute \src "ls180.v:10502.12-10502.21" + memory width 25 size 8 \storage_1 + attribute \src "ls180.v:10516.12-10516.21" + memory width 25 size 8 \storage_2 + attribute \src "ls180.v:10530.12-10530.21" + memory width 25 size 8 \storage_3 + attribute \src "ls180.v:10544.11-10544.20" + memory width 10 size 16 \storage_4 + attribute \src "ls180.v:10561.11-10561.20" + memory width 10 size 16 \storage_5 + attribute \src "ls180.v:10578.11-10578.20" + memory width 10 size 32 \storage_6 + attribute \src "ls180.v:10592.11-10592.20" + memory width 10 size 32 \storage_7 + attribute \src "ls180.v:2932.56-2932.86" + cell $add $add$ls180.v:2932$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_counter + connect \B 1'1 + connect \Y $add$ls180.v:2932$58_Y + end + attribute \src "ls180.v:2992.56-2992.86" + cell $add $add$ls180.v:2992$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_counter + connect \B 1'1 + connect \Y $add$ls180.v:2992$69_Y + end + attribute \src "ls180.v:3052.59-3052.92" + cell $add $add$ls180.v:3052$80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_counter + connect \B 1'1 + connect \Y $add$ls180.v:3052$80_Y + end + attribute \src "ls180.v:4245.54-4245.83" + cell $add $add$ls180.v:4245$685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $add$ls180.v:4245$685_Y + end + attribute \src "ls180.v:4345.36-4345.89" + cell $add $add$ls180.v:4345$731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B \main_uart_tx_fifo_readable + connect \Y $add$ls180.v:4345$731_Y + end + attribute \src "ls180.v:4375.36-4375.89" + cell $add $add$ls180.v:4375$742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B \main_uart_rx_fifo_readable + connect \Y $add$ls180.v:4375$742_Y + end + attribute \src "ls180.v:4441.54-4441.83" + cell $add $add$ls180.v:4441$757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spimaster27_count + connect \B 1'1 + connect \Y $add$ls180.v:4441$757_Y + end + attribute \src "ls180.v:4500.52-4500.79" + cell $add $add$ls180.v:4500$765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_count + connect \B 1'1 + connect \Y $add$ls180.v:4500$765_Y + end + attribute \src "ls180.v:4604.58-4604.86" + cell $add $add$ls180.v:4604$793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_init_count + connect \B 1'1 + connect \Y $add$ls180.v:4604$793_Y + end + attribute \src "ls180.v:4661.58-4661.86" + cell $add $add$ls180.v:4661$796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4661$796_Y + end + attribute \src "ls180.v:4678.58-4678.86" + cell $add $add$ls180.v:4678$798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4678$798_Y + end + attribute \src "ls180.v:4771.59-4771.87" + cell $add $add$ls180.v:4771$815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4771$815_Y + end + attribute \src "ls180.v:4796.59-4796.87" + cell $add $add$ls180.v:4796$818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4796$818_Y + end + attribute \src "ls180.v:4918.53-4918.82" + cell $add $add$ls180.v:4918$835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $add$ls180.v:4918$835_Y + end + attribute \src "ls180.v:5029.65-5029.114" + cell $add $add$ls180.v:5029$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_sink_payload_block_length + connect \B 4'1000 + connect \Y $add$ls180.v:5029$849_Y + end + attribute \src "ls180.v:5034.62-5034.91" + cell $add $add$ls180.v:5034$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:5034$852_Y + end + attribute \src "ls180.v:5060.61-5060.90" + cell $add $add$ls180.v:5060$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:5060$855_Y + end + attribute \src "ls180.v:5264.80-5264.117" + cell $add $add$ls180.v:5264$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 1'1 + connect \Y $add$ls180.v:5264$1040_Y + end + attribute \src "ls180.v:5458.54-5458.82" + cell $add $add$ls180.v:5458$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_cmd_count + connect \B 1'1 + connect \Y $add$ls180.v:5458$1115_Y + end + attribute \src "ls180.v:5510.55-5510.84" + cell $add $add$ls180.v:5510$1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5510$1125_Y + end + attribute \src "ls180.v:5536.57-5536.86" + cell $add $add$ls180.v:5536$1133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5536$1133_Y + end + attribute \src "ls180.v:5657.51-5657.134" + cell $add $add$ls180.v:5657$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_base + connect \B \main_sdblock2mem_wishbonedmawriter_offset + connect \Y $add$ls180.v:5657$1149_Y + end + attribute \src "ls180.v:5660.77-5660.125" + cell $add $add$ls180.v:5660$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B 1'1 + connect \Y $add$ls180.v:5660$1151_Y + end + attribute \src "ls180.v:5753.50-5753.105" + cell $add $add$ls180.v:5753$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_base + connect \B \main_sdmem2block_dma_offset + connect \Y $add$ls180.v:5753$1160_Y + end + attribute \src "ls180.v:5755.77-5755.111" + cell $add $add$ls180.v:5755$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_offset + connect \B 1'1 + connect \Y $add$ls180.v:5755$1161_Y + end + attribute \src "ls180.v:7762.36-7762.70" + cell $add $add$ls180.v:7762$2602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_bus_errors + connect \B 1'1 + connect \Y $add$ls180.v:7762$2602_Y + end + attribute \src "ls180.v:7863.37-7863.72" + cell $add $add$ls180.v:7863$2635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_sequencer_counter + connect \B 1'1 + connect \Y $add$ls180.v:7863$2635_Y + end + attribute \src "ls180.v:7880.60-7880.119" + cell $add $add$ls180.v:7880$2639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7880$2639_Y + end + attribute \src "ls180.v:7883.60-7883.119" + cell $add $add$ls180.v:7883$2640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7883$2640_Y + end + attribute \src "ls180.v:7887.59-7887.116" + cell $add $add$ls180.v:7887$2645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7887$2645_Y + end + attribute \src "ls180.v:7926.60-7926.119" + cell $add $add$ls180.v:7926$2655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7926$2655_Y + end + attribute \src "ls180.v:7929.60-7929.119" + cell $add $add$ls180.v:7929$2656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7929$2656_Y + end + attribute \src "ls180.v:7933.59-7933.116" + cell $add $add$ls180.v:7933$2661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7933$2661_Y + end + attribute \src "ls180.v:7972.60-7972.119" + cell $add $add$ls180.v:7972$2671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7972$2671_Y + end + attribute \src "ls180.v:7975.60-7975.119" + cell $add $add$ls180.v:7975$2672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7975$2672_Y + end + attribute \src "ls180.v:7979.59-7979.116" + cell $add $add$ls180.v:7979$2677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7979$2677_Y + end + attribute \src "ls180.v:8018.60-8018.119" + cell $add $add$ls180.v:8018$2687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:8018$2687_Y + end + attribute \src "ls180.v:8021.60-8021.119" + cell $add $add$ls180.v:8021$2688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:8021$2688_Y + end + attribute \src "ls180.v:8025.59-8025.116" + cell $add $add$ls180.v:8025$2693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:8025$2693_Y + end + attribute \src "ls180.v:8255.34-8255.66" + cell $add $add$ls180.v:8255$2747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_tx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:8255$2747_Y + end + attribute \src "ls180.v:8271.73-8271.131" + cell $add $add$ls180.v:8271$2750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_tx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:8271$2750_Y + end + attribute \src "ls180.v:8284.34-8284.66" + cell $add $add$ls180.v:8284$2754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:8284$2754_Y + end + attribute \src "ls180.v:8303.73-8303.131" + cell $add $add$ls180.v:8303$2757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_rx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:8303$2757_Y + end + attribute \src "ls180.v:8329.33-8329.65" + cell $add $add$ls180.v:8329$2765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8329$2765_Y + end + attribute \src "ls180.v:8332.33-8332.65" + cell $add $add$ls180.v:8332$2766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8332$2766_Y + end + attribute \src "ls180.v:8336.33-8336.64" + cell $add $add$ls180.v:8336$2771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8336$2771_Y + end + attribute \src "ls180.v:8351.33-8351.65" + cell $add $add$ls180.v:8351$2776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8351$2776_Y + end + attribute \src "ls180.v:8354.33-8354.65" + cell $add $add$ls180.v:8354$2777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8354$2777_Y + end + attribute \src "ls180.v:8358.33-8358.64" + cell $add $add$ls180.v:8358$2782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8358$2782_Y + end + attribute \src "ls180.v:8379.35-8379.70" + cell $add $add$ls180.v:8379$2784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster30_clk_divider + connect \B 1'1 + connect \Y $add$ls180.v:8379$2784_Y + end + attribute \src "ls180.v:8414.34-8414.68" + cell $add $add$ls180.v:8414$2789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8414$2789_Y + end + attribute \src "ls180.v:8450.25-8450.49" + cell $add $add$ls180.v:8450$2794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_counter + connect \B 1'1 + connect \Y $add$ls180.v:8450$2794_Y + end + attribute \src "ls180.v:8464.25-8464.49" + cell $add $add$ls180.v:8464$2798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_counter + connect \B 1'1 + connect \Y $add$ls180.v:8464$2798_Y + end + attribute \src "ls180.v:8478.31-8478.61" + cell $add $add$ls180.v:8478$2803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 9 + connect \A \main_sdphy_clocker_clks + connect \B 1'1 + connect \Y $add$ls180.v:8478$2803_Y + end + attribute \src "ls180.v:8501.45-8501.88" + cell $add $add$ls180.v:8501$2807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8501$2807_Y + end + attribute \src "ls180.v:8547.71-8547.114" + cell $add $add$ls180.v:8547$2813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8547$2813_Y + end + attribute \src "ls180.v:8582.46-8582.90" + cell $add $add$ls180.v:8582$2819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8582$2819_Y + end + attribute \src "ls180.v:8628.72-8628.116" + cell $add $add$ls180.v:8628$2825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8628$2825_Y + end + attribute \src "ls180.v:8661.47-8661.92" + cell $add $add$ls180.v:8661$2831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8661$2831_Y + end + attribute \src "ls180.v:8689.73-8689.118" + cell $add $add$ls180.v:8689$2837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8689$2837_Y + end + attribute \src "ls180.v:8801.39-8801.75" + cell $add $add$ls180.v:8801$2850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 1'1 + connect \Y $add$ls180.v:8801$2850_Y + end + attribute \src "ls180.v:8862.37-8862.73" + cell $add $add$ls180.v:8862$2854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8862$2854_Y + end + attribute \src "ls180.v:8865.37-8865.73" + cell $add $add$ls180.v:8865$2855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8865$2855_Y + end + attribute \src "ls180.v:8869.36-8869.70" + cell $add $add$ls180.v:8869$2860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8869$2860_Y + end + attribute \src "ls180.v:8884.41-8884.80" + cell $add $add$ls180.v:8884$2864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8884$2864_Y + end + attribute \src "ls180.v:8930.67-8930.106" + cell $add $add$ls180.v:8930$2870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8930$2870_Y + end + attribute \src "ls180.v:8956.39-8956.76" + cell $add $add$ls180.v:8956$2872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdmem2block_converter_mux + connect \B 1'1 + connect \Y $add$ls180.v:8956$2872_Y + end + attribute \src "ls180.v:8960.37-8960.73" + cell $add $add$ls180.v:8960$2876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8960$2876_Y + end + attribute \src "ls180.v:8963.37-8963.73" + cell $add $add$ls180.v:8963$2877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8963$2877_Y + end + attribute \src "ls180.v:8967.36-8967.70" + cell $add $add$ls180.v:8967$2882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8967$2882_Y + end + attribute \src "ls180.v:2926.9-2926.90" + cell $and $and$ls180.v:2926$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2926$53_Y + end + attribute \src "ls180.v:2944.9-2944.90" + cell $and $and$ls180.v:2944$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2944$60_Y + end + attribute \src "ls180.v:2986.9-2986.90" + cell $and $and$ls180.v:2986$64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:2986$64_Y + end + attribute \src "ls180.v:3004.9-3004.90" + cell $and $and$ls180.v:3004$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:3004$71_Y + end + attribute \src "ls180.v:3046.9-3046.96" + cell $and $and$ls180.v:3046$75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:3046$75_Y + end + attribute \src "ls180.v:3064.9-3064.96" + cell $and $and$ls180.v:3064$82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:3064$82_Y + end + attribute \src "ls180.v:3074.31-3074.90" + cell $and $and$ls180.v:3074$84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3074$84_Y + end + attribute \src "ls180.v:3074.30-3074.121" + cell $and $and$ls180.v:3074$85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3074$84_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3074$85_Y + end + attribute \src "ls180.v:3074.29-3074.156" + cell $and $and$ls180.v:3074$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3074$85_Y + connect \B \main_libresocsim_ram_bus_sel [0] + connect \Y $and$ls180.v:3074$86_Y + end + attribute \src "ls180.v:3075.31-3075.90" + cell $and $and$ls180.v:3075$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3075$87_Y + end + attribute \src "ls180.v:3075.30-3075.121" + cell $and $and$ls180.v:3075$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3075$87_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3075$88_Y + end + attribute \src "ls180.v:3075.29-3075.156" + cell $and $and$ls180.v:3075$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3075$88_Y + connect \B \main_libresocsim_ram_bus_sel [1] + connect \Y $and$ls180.v:3075$89_Y + end + attribute \src "ls180.v:3076.31-3076.90" + cell $and $and$ls180.v:3076$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3076$90_Y + end + attribute \src "ls180.v:3076.30-3076.121" + cell $and $and$ls180.v:3076$91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3076$90_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3076$91_Y + end + attribute \src "ls180.v:3076.29-3076.156" + cell $and $and$ls180.v:3076$92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3076$91_Y + connect \B \main_libresocsim_ram_bus_sel [2] + connect \Y $and$ls180.v:3076$92_Y + end + attribute \src "ls180.v:3077.31-3077.90" + cell $and $and$ls180.v:3077$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3077$93_Y + end + attribute \src "ls180.v:3077.30-3077.121" + cell $and $and$ls180.v:3077$94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3077$93_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3077$94_Y + end + attribute \src "ls180.v:3077.29-3077.156" + cell $and $and$ls180.v:3077$95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3077$94_Y + connect \B \main_libresocsim_ram_bus_sel [3] + connect \Y $and$ls180.v:3077$95_Y + end + attribute \src "ls180.v:3078.31-3078.90" + cell $and $and$ls180.v:3078$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3078$96_Y + end + attribute \src "ls180.v:3078.30-3078.121" + cell $and $and$ls180.v:3078$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3078$96_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3078$97_Y + end + attribute \src "ls180.v:3078.29-3078.156" + cell $and $and$ls180.v:3078$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3078$97_Y + connect \B \main_libresocsim_ram_bus_sel [4] + connect \Y $and$ls180.v:3078$98_Y + end + attribute \src "ls180.v:3079.30-3079.121" + cell $and $and$ls180.v:3079$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3079$99_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3079$100_Y + end + attribute \src "ls180.v:3079.29-3079.156" + cell $and $and$ls180.v:3079$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3079$100_Y + connect \B \main_libresocsim_ram_bus_sel [5] + connect \Y $and$ls180.v:3079$101_Y + end + attribute \src "ls180.v:3079.31-3079.90" + cell $and $and$ls180.v:3079$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3079$99_Y + end + attribute \src "ls180.v:3080.31-3080.90" + cell $and $and$ls180.v:3080$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3080$102_Y + end + attribute \src "ls180.v:3080.30-3080.121" + cell $and $and$ls180.v:3080$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3080$102_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3080$103_Y + end + attribute \src "ls180.v:3080.29-3080.156" + cell $and $and$ls180.v:3080$104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3080$103_Y + connect \B \main_libresocsim_ram_bus_sel [6] + connect \Y $and$ls180.v:3080$104_Y + end + attribute \src "ls180.v:3081.31-3081.90" + cell $and $and$ls180.v:3081$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3081$105_Y + end + attribute \src "ls180.v:3081.30-3081.121" + cell $and $and$ls180.v:3081$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3081$105_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3081$106_Y + end + attribute \src "ls180.v:3081.29-3081.156" + cell $and $and$ls180.v:3081$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3081$106_Y + connect \B \main_libresocsim_ram_bus_sel [7] + connect \Y $and$ls180.v:3081$107_Y + end + attribute \src "ls180.v:3090.7-3090.89" + cell $and $and$ls180.v:3090$110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_re + connect \B \main_libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:3090$110_Y + end + attribute \src "ls180.v:3095.32-3095.111" + cell $and $and$ls180.v:3095$111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_w + connect \B \main_libresocsim_eventmanager_storage + connect \Y $and$ls180.v:3095$111_Y + end + attribute \src "ls180.v:3099.25-3099.82" + cell $and $and$ls180.v:3099$113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3099$113_Y + end + attribute \src "ls180.v:3099.24-3099.112" + cell $and $and$ls180.v:3099$114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3099$113_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3099$114_Y + end + attribute \src "ls180.v:3099.23-3099.146" + cell $and $and$ls180.v:3099$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3099$114_Y + connect \B \main_interface0_ram_bus_sel [0] + connect \Y $and$ls180.v:3099$115_Y + end + attribute \src "ls180.v:3100.25-3100.82" + cell $and $and$ls180.v:3100$116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3100$116_Y + end + attribute \src "ls180.v:3100.24-3100.112" + cell $and $and$ls180.v:3100$117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3100$116_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3100$117_Y + end + attribute \src "ls180.v:3100.23-3100.146" + cell $and $and$ls180.v:3100$118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3100$117_Y + connect \B \main_interface0_ram_bus_sel [1] + connect \Y $and$ls180.v:3100$118_Y + end + attribute \src "ls180.v:3101.25-3101.82" + cell $and $and$ls180.v:3101$119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3101$119_Y + end + attribute \src "ls180.v:3101.24-3101.112" + cell $and $and$ls180.v:3101$120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3101$119_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3101$120_Y + end + attribute \src "ls180.v:3101.23-3101.146" + cell $and $and$ls180.v:3101$121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3101$120_Y + connect \B \main_interface0_ram_bus_sel [2] + connect \Y $and$ls180.v:3101$121_Y + end + attribute \src "ls180.v:3102.25-3102.82" + cell $and $and$ls180.v:3102$122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3102$122_Y + end + attribute \src "ls180.v:3102.24-3102.112" + cell $and $and$ls180.v:3102$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3102$122_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3102$123_Y + end + attribute \src "ls180.v:3102.23-3102.146" + cell $and $and$ls180.v:3102$124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3102$123_Y + connect \B \main_interface0_ram_bus_sel [3] + connect \Y $and$ls180.v:3102$124_Y + end + attribute \src "ls180.v:3103.25-3103.82" + cell $and $and$ls180.v:3103$125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3103$125_Y + end + attribute \src "ls180.v:3103.24-3103.112" + cell $and $and$ls180.v:3103$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3103$125_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3103$126_Y + end + attribute \src "ls180.v:3103.23-3103.146" + cell $and $and$ls180.v:3103$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3103$126_Y + connect \B \main_interface0_ram_bus_sel [4] + connect \Y $and$ls180.v:3103$127_Y + end + attribute \src "ls180.v:3104.25-3104.82" + cell $and $and$ls180.v:3104$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3104$128_Y + end + attribute \src "ls180.v:3104.24-3104.112" + cell $and $and$ls180.v:3104$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3104$128_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3104$129_Y + end + attribute \src "ls180.v:3104.23-3104.146" + cell $and $and$ls180.v:3104$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3104$129_Y + connect \B \main_interface0_ram_bus_sel [5] + connect \Y $and$ls180.v:3104$130_Y + end + attribute \src "ls180.v:3105.25-3105.82" + cell $and $and$ls180.v:3105$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3105$131_Y + end + attribute \src "ls180.v:3105.24-3105.112" + cell $and $and$ls180.v:3105$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3105$131_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3105$132_Y + end + attribute \src "ls180.v:3105.23-3105.146" + cell $and $and$ls180.v:3105$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3105$132_Y + connect \B \main_interface0_ram_bus_sel [6] + connect \Y $and$ls180.v:3105$133_Y + end + attribute \src "ls180.v:3106.25-3106.82" + cell $and $and$ls180.v:3106$134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3106$134_Y + end + attribute \src "ls180.v:3106.24-3106.112" + cell $and $and$ls180.v:3106$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3106$134_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3106$135_Y + end + attribute \src "ls180.v:3106.23-3106.146" + cell $and $and$ls180.v:3106$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3106$135_Y + connect \B \main_interface0_ram_bus_sel [7] + connect \Y $and$ls180.v:3106$136_Y + end + attribute \src "ls180.v:3113.25-3113.82" + cell $and $and$ls180.v:3113$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3113$138_Y + end + attribute \src "ls180.v:3113.24-3113.112" + cell $and $and$ls180.v:3113$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3113$138_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3113$139_Y + end + attribute \src "ls180.v:3113.23-3113.146" + cell $and $and$ls180.v:3113$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3113$139_Y + connect \B \main_interface1_ram_bus_sel [0] + connect \Y $and$ls180.v:3113$140_Y + end + attribute \src "ls180.v:3114.25-3114.82" + cell $and $and$ls180.v:3114$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3114$141_Y + end + attribute \src "ls180.v:3114.24-3114.112" + cell $and $and$ls180.v:3114$142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3114$141_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3114$142_Y + end + attribute \src "ls180.v:3114.23-3114.146" + cell $and $and$ls180.v:3114$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3114$142_Y + connect \B \main_interface1_ram_bus_sel [1] + connect \Y $and$ls180.v:3114$143_Y + end + attribute \src "ls180.v:3115.25-3115.82" + cell $and $and$ls180.v:3115$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3115$144_Y + end + attribute \src "ls180.v:3115.24-3115.112" + cell $and $and$ls180.v:3115$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3115$144_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3115$145_Y + end + attribute \src "ls180.v:3115.23-3115.146" + cell $and $and$ls180.v:3115$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3115$145_Y + connect \B \main_interface1_ram_bus_sel [2] + connect \Y $and$ls180.v:3115$146_Y + end + attribute \src "ls180.v:3116.25-3116.82" + cell $and $and$ls180.v:3116$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3116$147_Y + end + attribute \src "ls180.v:3116.24-3116.112" + cell $and $and$ls180.v:3116$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3116$147_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3116$148_Y + end + attribute \src "ls180.v:3116.23-3116.146" + cell $and $and$ls180.v:3116$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3116$148_Y + connect \B \main_interface1_ram_bus_sel [3] + connect \Y $and$ls180.v:3116$149_Y + end + attribute \src "ls180.v:3117.25-3117.82" + cell $and $and$ls180.v:3117$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3117$150_Y + end + attribute \src "ls180.v:3117.24-3117.112" + cell $and $and$ls180.v:3117$151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3117$150_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3117$151_Y + end + attribute \src "ls180.v:3117.23-3117.146" + cell $and $and$ls180.v:3117$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3117$151_Y + connect \B \main_interface1_ram_bus_sel [4] + connect \Y $and$ls180.v:3117$152_Y + end + attribute \src "ls180.v:3118.25-3118.82" + cell $and $and$ls180.v:3118$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3118$153_Y + end + attribute \src "ls180.v:3118.24-3118.112" + cell $and $and$ls180.v:3118$154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3118$153_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3118$154_Y + end + attribute \src "ls180.v:3118.23-3118.146" + cell $and $and$ls180.v:3118$155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3118$154_Y + connect \B \main_interface1_ram_bus_sel [5] + connect \Y $and$ls180.v:3118$155_Y + end + attribute \src "ls180.v:3119.25-3119.82" + cell $and $and$ls180.v:3119$156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3119$156_Y + end + attribute \src "ls180.v:3119.24-3119.112" + cell $and $and$ls180.v:3119$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3119$156_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3119$157_Y + end + attribute \src "ls180.v:3119.23-3119.146" + cell $and $and$ls180.v:3119$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3119$157_Y + connect \B \main_interface1_ram_bus_sel [6] + connect \Y $and$ls180.v:3119$158_Y + end + attribute \src "ls180.v:3120.25-3120.82" + cell $and $and$ls180.v:3120$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3120$159_Y + end + attribute \src "ls180.v:3120.24-3120.112" + cell $and $and$ls180.v:3120$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3120$159_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3120$160_Y + end + attribute \src "ls180.v:3120.23-3120.146" + cell $and $and$ls180.v:3120$161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3120$160_Y + connect \B \main_interface1_ram_bus_sel [7] + connect \Y $and$ls180.v:3120$161_Y + end + attribute \src "ls180.v:3127.25-3127.82" + cell $and $and$ls180.v:3127$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3127$163_Y + end + attribute \src "ls180.v:3127.24-3127.112" + cell $and $and$ls180.v:3127$164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3127$163_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3127$164_Y + end + attribute \src "ls180.v:3127.23-3127.146" + cell $and $and$ls180.v:3127$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3127$164_Y + connect \B \main_interface2_ram_bus_sel [0] + connect \Y $and$ls180.v:3127$165_Y + end + attribute \src "ls180.v:3128.25-3128.82" + cell $and $and$ls180.v:3128$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3128$166_Y + end + attribute \src "ls180.v:3128.24-3128.112" + cell $and $and$ls180.v:3128$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3128$166_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3128$167_Y + end + attribute \src "ls180.v:3128.23-3128.146" + cell $and $and$ls180.v:3128$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3128$167_Y + connect \B \main_interface2_ram_bus_sel [1] + connect \Y $and$ls180.v:3128$168_Y + end + attribute \src "ls180.v:3129.25-3129.82" + cell $and $and$ls180.v:3129$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3129$169_Y + end + attribute \src "ls180.v:3129.24-3129.112" + cell $and $and$ls180.v:3129$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3129$169_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3129$170_Y + end + attribute \src "ls180.v:3129.23-3129.146" + cell $and $and$ls180.v:3129$171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3129$170_Y + connect \B \main_interface2_ram_bus_sel [2] + connect \Y $and$ls180.v:3129$171_Y + end + attribute \src "ls180.v:3130.25-3130.82" + cell $and $and$ls180.v:3130$172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3130$172_Y + end + attribute \src "ls180.v:3130.24-3130.112" + cell $and $and$ls180.v:3130$173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3130$172_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3130$173_Y + end + attribute \src "ls180.v:3130.23-3130.146" + cell $and $and$ls180.v:3130$174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3130$173_Y + connect \B \main_interface2_ram_bus_sel [3] + connect \Y $and$ls180.v:3130$174_Y + end + attribute \src "ls180.v:3131.25-3131.82" + cell $and $and$ls180.v:3131$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3131$175_Y + end + attribute \src "ls180.v:3131.24-3131.112" + cell $and $and$ls180.v:3131$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3131$175_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3131$176_Y + end + attribute \src "ls180.v:3131.23-3131.146" + cell $and $and$ls180.v:3131$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3131$176_Y + connect \B \main_interface2_ram_bus_sel [4] + connect \Y $and$ls180.v:3131$177_Y + end + attribute \src "ls180.v:3132.25-3132.82" + cell $and $and$ls180.v:3132$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3132$178_Y + end + attribute \src "ls180.v:3132.24-3132.112" + cell $and $and$ls180.v:3132$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3132$178_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3132$179_Y + end + attribute \src "ls180.v:3132.23-3132.146" + cell $and $and$ls180.v:3132$180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3132$179_Y + connect \B \main_interface2_ram_bus_sel [5] + connect \Y $and$ls180.v:3132$180_Y + end + attribute \src "ls180.v:3133.25-3133.82" + cell $and $and$ls180.v:3133$181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3133$181_Y + end + attribute \src "ls180.v:3133.24-3133.112" + cell $and $and$ls180.v:3133$182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3133$181_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3133$182_Y + end + attribute \src "ls180.v:3133.23-3133.146" + cell $and $and$ls180.v:3133$183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3133$182_Y + connect \B \main_interface2_ram_bus_sel [6] + connect \Y $and$ls180.v:3133$183_Y + end + attribute \src "ls180.v:3134.25-3134.82" + cell $and $and$ls180.v:3134$184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3134$184_Y + end + attribute \src "ls180.v:3134.24-3134.112" + cell $and $and$ls180.v:3134$185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3134$184_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3134$185_Y + end + attribute \src "ls180.v:3134.23-3134.146" + cell $and $and$ls180.v:3134$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3134$185_Y + connect \B \main_interface2_ram_bus_sel [7] + connect \Y $and$ls180.v:3134$186_Y + end + attribute \src "ls180.v:3141.25-3141.82" + cell $and $and$ls180.v:3141$188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3141$188_Y + end + attribute \src "ls180.v:3141.24-3141.112" + cell $and $and$ls180.v:3141$189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3141$188_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3141$189_Y + end + attribute \src "ls180.v:3141.23-3141.146" + cell $and $and$ls180.v:3141$190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3141$189_Y + connect \B \main_interface3_ram_bus_sel [0] + connect \Y $and$ls180.v:3141$190_Y + end + attribute \src "ls180.v:3142.25-3142.82" + cell $and $and$ls180.v:3142$191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3142$191_Y + end + attribute \src "ls180.v:3142.24-3142.112" + cell $and $and$ls180.v:3142$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3142$191_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3142$192_Y + end + attribute \src "ls180.v:3142.23-3142.146" + cell $and $and$ls180.v:3142$193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3142$192_Y + connect \B \main_interface3_ram_bus_sel [1] + connect \Y $and$ls180.v:3142$193_Y + end + attribute \src "ls180.v:3143.25-3143.82" + cell $and $and$ls180.v:3143$194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3143$194_Y + end + attribute \src "ls180.v:3143.24-3143.112" + cell $and $and$ls180.v:3143$195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3143$194_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3143$195_Y + end + attribute \src "ls180.v:3143.23-3143.146" + cell $and $and$ls180.v:3143$196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3143$195_Y + connect \B \main_interface3_ram_bus_sel [2] + connect \Y $and$ls180.v:3143$196_Y + end + attribute \src "ls180.v:3144.25-3144.82" + cell $and $and$ls180.v:3144$197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3144$197_Y + end + attribute \src "ls180.v:3144.24-3144.112" + cell $and $and$ls180.v:3144$198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3144$197_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3144$198_Y + end + attribute \src "ls180.v:3144.23-3144.146" + cell $and $and$ls180.v:3144$199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3144$198_Y + connect \B \main_interface3_ram_bus_sel [3] + connect \Y $and$ls180.v:3144$199_Y + end + attribute \src "ls180.v:3145.25-3145.82" + cell $and $and$ls180.v:3145$200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3145$200_Y + end + attribute \src "ls180.v:3145.24-3145.112" + cell $and $and$ls180.v:3145$201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3145$200_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3145$201_Y + end + attribute \src "ls180.v:3145.23-3145.146" + cell $and $and$ls180.v:3145$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3145$201_Y + connect \B \main_interface3_ram_bus_sel [4] + connect \Y $and$ls180.v:3145$202_Y + end + attribute \src "ls180.v:3146.25-3146.82" + cell $and $and$ls180.v:3146$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3146$203_Y + end + attribute \src "ls180.v:3146.24-3146.112" + cell $and $and$ls180.v:3146$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3146$203_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3146$204_Y + end + attribute \src "ls180.v:3146.23-3146.146" + cell $and $and$ls180.v:3146$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3146$204_Y + connect \B \main_interface3_ram_bus_sel [5] + connect \Y $and$ls180.v:3146$205_Y + end + attribute \src "ls180.v:3147.25-3147.82" + cell $and $and$ls180.v:3147$206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3147$206_Y + end + attribute \src "ls180.v:3147.24-3147.112" + cell $and $and$ls180.v:3147$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3147$206_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3147$207_Y + end + attribute \src "ls180.v:3147.23-3147.146" + cell $and $and$ls180.v:3147$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3147$207_Y + connect \B \main_interface3_ram_bus_sel [6] + connect \Y $and$ls180.v:3147$208_Y + end + attribute \src "ls180.v:3148.25-3148.82" + cell $and $and$ls180.v:3148$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3148$209_Y + end + attribute \src "ls180.v:3148.24-3148.112" + cell $and $and$ls180.v:3148$210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3148$209_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3148$210_Y + end + attribute \src "ls180.v:3148.23-3148.146" + cell $and $and$ls180.v:3148$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3148$210_Y + connect \B \main_interface3_ram_bus_sel [7] + connect \Y $and$ls180.v:3148$211_Y + end + attribute \src "ls180.v:3265.40-3265.99" + cell $and $and$ls180.v:3265$218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [4] + connect \Y $and$ls180.v:3265$218_Y + end + attribute \src "ls180.v:3266.40-3266.99" + cell $and $and$ls180.v:3266$219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [5] + connect \Y $and$ls180.v:3266$219_Y + end + attribute \src "ls180.v:3304.38-3304.103" + cell $and $and$ls180.v:3304$225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_done1 + connect \B $eq$ls180.v:3304$224_Y + connect \Y $and$ls180.v:3304$225_Y + end + attribute \src "ls180.v:3358.50-3358.119" + cell $and $and$ls180.v:3358$233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3358$233_Y + end + attribute \src "ls180.v:3358.49-3358.167" + cell $and $and$ls180.v:3358$234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3358$233_Y + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3358$234_Y + end + attribute \src "ls180.v:3359.49-3359.118" + cell $and $and$ls180.v:3359$235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3359$235_Y + end + attribute \src "ls180.v:3359.48-3359.154" + cell $and $and$ls180.v:3359$236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3359$235_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3359$236_Y + end + attribute \src "ls180.v:3360.50-3360.119" + cell $and $and$ls180.v:3360$237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3360$237_Y + end + attribute \src "ls180.v:3360.49-3360.155" + cell $and $and$ls180.v:3360$238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3360$237_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3360$238_Y + end + attribute \src "ls180.v:3363.7-3363.114" + cell $and $and$ls180.v:3363$240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:3363$240_Y + end + attribute \src "ls180.v:3392.66-3392.246" + cell $and $and$ls180.v:3392$246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:3392$245_Y + connect \Y $and$ls180.v:3392$246_Y + end + attribute \src "ls180.v:3393.64-3393.187" + cell $and $and$ls180.v:3393$247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:3393$247_Y + end + attribute \src "ls180.v:3417.9-3417.86" + cell $and $and$ls180.v:3417$253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3417$253_Y + end + attribute \src "ls180.v:3429.9-3429.86" + cell $and $and$ls180.v:3429$254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3429$254_Y + end + attribute \src "ls180.v:3479.13-3479.87" + cell $and $and$ls180.v:3479$256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_ready + connect \B \main_sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:3479$256_Y + end + attribute \src "ls180.v:3515.50-3515.119" + cell $and $and$ls180.v:3515$263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3515$263_Y + end + attribute \src "ls180.v:3515.49-3515.167" + cell $and $and$ls180.v:3515$264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3515$263_Y + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3515$264_Y + end + attribute \src "ls180.v:3516.49-3516.118" + cell $and $and$ls180.v:3516$265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3516$265_Y + end + attribute \src "ls180.v:3516.48-3516.154" + cell $and $and$ls180.v:3516$266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3516$265_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3516$266_Y + end + attribute \src "ls180.v:3517.50-3517.119" + cell $and $and$ls180.v:3517$267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3517$267_Y + end + attribute \src "ls180.v:3517.49-3517.155" + cell $and $and$ls180.v:3517$268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3517$267_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3517$268_Y + end + attribute \src "ls180.v:3520.7-3520.114" + cell $and $and$ls180.v:3520$270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:3520$270_Y + end + attribute \src "ls180.v:3549.66-3549.246" + cell $and $and$ls180.v:3549$276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:3549$275_Y + connect \Y $and$ls180.v:3549$276_Y + end + attribute \src "ls180.v:3550.64-3550.187" + cell $and $and$ls180.v:3550$277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:3550$277_Y + end + attribute \src "ls180.v:3574.9-3574.86" + cell $and $and$ls180.v:3574$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3574$283_Y + end + attribute \src "ls180.v:3586.9-3586.86" + cell $and $and$ls180.v:3586$284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3586$284_Y + end + attribute \src "ls180.v:3636.13-3636.87" + cell $and $and$ls180.v:3636$286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_ready + connect \B \main_sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:3636$286_Y + end + attribute \src "ls180.v:3672.50-3672.119" + cell $and $and$ls180.v:3672$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3672$293_Y + end + attribute \src "ls180.v:3672.49-3672.167" + cell $and $and$ls180.v:3672$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3672$293_Y + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3672$294_Y + end + attribute \src "ls180.v:3673.49-3673.118" + cell $and $and$ls180.v:3673$295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3673$295_Y + end + attribute \src "ls180.v:3673.48-3673.154" + cell $and $and$ls180.v:3673$296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3673$295_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3673$296_Y + end + attribute \src "ls180.v:3674.50-3674.119" + cell $and $and$ls180.v:3674$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3674$297_Y + end + attribute \src "ls180.v:3674.49-3674.155" + cell $and $and$ls180.v:3674$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3674$297_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3674$298_Y + end + attribute \src "ls180.v:3677.7-3677.114" + cell $and $and$ls180.v:3677$300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:3677$300_Y + end + attribute \src "ls180.v:3706.66-3706.246" + cell $and $and$ls180.v:3706$306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:3706$305_Y + connect \Y $and$ls180.v:3706$306_Y + end + attribute \src "ls180.v:3707.64-3707.187" + cell $and $and$ls180.v:3707$307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:3707$307_Y + end + attribute \src "ls180.v:3731.9-3731.86" + cell $and $and$ls180.v:3731$313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3731$313_Y + end + attribute \src "ls180.v:3743.9-3743.86" + cell $and $and$ls180.v:3743$314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3743$314_Y + end + attribute \src "ls180.v:3793.13-3793.87" + cell $and $and$ls180.v:3793$316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_ready + connect \B \main_sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:3793$316_Y + end + attribute \src "ls180.v:3829.50-3829.119" + cell $and $and$ls180.v:3829$323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3829$323_Y + end + attribute \src "ls180.v:3829.49-3829.167" + cell $and $and$ls180.v:3829$324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3829$323_Y + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3829$324_Y + end + attribute \src "ls180.v:3830.49-3830.118" + cell $and $and$ls180.v:3830$325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3830$325_Y + end + attribute \src "ls180.v:3830.48-3830.154" + cell $and $and$ls180.v:3830$326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3830$325_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3830$326_Y + end + attribute \src "ls180.v:3831.50-3831.119" + cell $and $and$ls180.v:3831$327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3831$327_Y + end + attribute \src "ls180.v:3831.49-3831.155" + cell $and $and$ls180.v:3831$328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3831$327_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3831$328_Y + end + attribute \src "ls180.v:3834.7-3834.114" + cell $and $and$ls180.v:3834$330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:3834$330_Y + end + attribute \src "ls180.v:3863.66-3863.246" + cell $and $and$ls180.v:3863$336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:3863$335_Y + connect \Y $and$ls180.v:3863$336_Y + end + attribute \src "ls180.v:3864.64-3864.187" + cell $and $and$ls180.v:3864$337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:3864$337_Y + end + attribute \src "ls180.v:3888.9-3888.86" + cell $and $and$ls180.v:3888$343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3888$343_Y + end + attribute \src "ls180.v:3900.9-3900.86" + cell $and $and$ls180.v:3900$344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3900$344_Y + end + attribute \src "ls180.v:3950.13-3950.87" + cell $and $and$ls180.v:3950$346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_ready + connect \B \main_sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:3950$346_Y + end + attribute \src "ls180.v:3965.37-3965.102" + cell $and $and$ls180.v:3965$347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3965$347_Y + end + attribute \src "ls180.v:3965.108-3965.188" + cell $and $and$ls180.v:3965$349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3965$348_Y + connect \Y $and$ls180.v:3965$349_Y + end + attribute \src "ls180.v:3965.107-3965.231" + cell $and $and$ls180.v:3965$351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3965$349_Y + connect \B $not$ls180.v:3965$350_Y + connect \Y $and$ls180.v:3965$351_Y + end + attribute \src "ls180.v:3965.36-3965.232" + cell $and $and$ls180.v:3965$352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3965$347_Y + connect \B $and$ls180.v:3965$351_Y + connect \Y $and$ls180.v:3965$352_Y + end + attribute \src "ls180.v:3966.37-3966.102" + cell $and $and$ls180.v:3966$353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3966$353_Y + end + attribute \src "ls180.v:3966.108-3966.188" + cell $and $and$ls180.v:3966$355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3966$354_Y + connect \Y $and$ls180.v:3966$355_Y + end + attribute \src "ls180.v:3966.107-3966.231" + cell $and $and$ls180.v:3966$357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3966$355_Y + connect \B $not$ls180.v:3966$356_Y + connect \Y $and$ls180.v:3966$357_Y + end + attribute \src "ls180.v:3966.36-3966.232" + cell $and $and$ls180.v:3966$358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3966$353_Y + connect \B $and$ls180.v:3966$357_Y + connect \Y $and$ls180.v:3966$358_Y + end + attribute \src "ls180.v:3967.34-3967.85" + cell $and $and$ls180.v:3967$359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_trrdcon_ready + connect \B \main_sdram_tfawcon_ready + connect \Y $and$ls180.v:3967$359_Y + end + attribute \src "ls180.v:3968.37-3968.102" + cell $and $and$ls180.v:3968$360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3968$360_Y + end + attribute \src "ls180.v:3968.36-3968.194" + cell $and $and$ls180.v:3968$362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3968$360_Y + connect \B $or$ls180.v:3968$361_Y + connect \Y $and$ls180.v:3968$362_Y + end + attribute \src "ls180.v:3970.37-3970.102" + cell $and $and$ls180.v:3970$363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3970$363_Y + end + attribute \src "ls180.v:3970.36-3970.148" + cell $and $and$ls180.v:3970$364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3970$363_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:3970$364_Y + end + attribute \src "ls180.v:3971.40-3971.119" + cell $and $and$ls180.v:3971$365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:3971$365_Y + end + attribute \src "ls180.v:3971.124-3971.203" + cell $and $and$ls180.v:3971$366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:3971$366_Y + end + attribute \src "ls180.v:3971.209-3971.288" + cell $and $and$ls180.v:3971$368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:3971$368_Y + end + attribute \src "ls180.v:3971.294-3971.373" + cell $and $and$ls180.v:3971$370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:3971$370_Y + end + attribute \src "ls180.v:3972.41-3972.121" + cell $and $and$ls180.v:3972$372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3972$372_Y + end + attribute \src "ls180.v:3972.126-3972.206" + cell $and $and$ls180.v:3972$373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3972$373_Y + end + attribute \src "ls180.v:3972.212-3972.292" + cell $and $and$ls180.v:3972$375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3972$375_Y + end + attribute \src "ls180.v:3972.298-3972.378" + cell $and $and$ls180.v:3972$377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3972$377_Y + end + attribute \src "ls180.v:3979.38-3979.111" + cell $and $and$ls180.v:3979$381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_gnt + connect \B \main_sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:3979$381_Y + end + attribute \src "ls180.v:3979.37-3979.150" + cell $and $and$ls180.v:3979$382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3979$381_Y + connect \B \main_sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:3979$382_Y + end + attribute \src "ls180.v:3979.36-3979.189" + cell $and $and$ls180.v:3979$383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3979$382_Y + connect \B \main_sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:3979$383_Y + end + attribute \src "ls180.v:3985.77-3985.153" + cell $and $and$ls180.v:3985$386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3985$386_Y + end + attribute \src "ls180.v:3985.162-3985.246" + cell $and $and$ls180.v:3985$388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3985$387_Y + connect \Y $and$ls180.v:3985$388_Y + end + attribute \src "ls180.v:3985.161-3985.291" + cell $and $and$ls180.v:3985$390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3985$388_Y + connect \B $not$ls180.v:3985$389_Y + connect \Y $and$ls180.v:3985$390_Y + end + attribute \src "ls180.v:3985.76-3985.333" + cell $and $and$ls180.v:3985$393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3985$386_Y + connect \B $or$ls180.v:3985$392_Y + connect \Y $and$ls180.v:3985$393_Y + end + attribute \src "ls180.v:3985.338-3985.505" + cell $and $and$ls180.v:3985$396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3985$394_Y + connect \B $eq$ls180.v:3985$395_Y + connect \Y $and$ls180.v:3985$396_Y + end + attribute \src "ls180.v:3985.38-3985.507" + cell $and $and$ls180.v:3985$398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3985$397_Y + connect \Y $and$ls180.v:3985$398_Y + end + attribute \src "ls180.v:3986.77-3986.153" + cell $and $and$ls180.v:3986$399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3986$399_Y + end + attribute \src "ls180.v:3986.162-3986.246" + cell $and $and$ls180.v:3986$401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3986$400_Y + connect \Y $and$ls180.v:3986$401_Y + end + attribute \src "ls180.v:3986.161-3986.291" + cell $and $and$ls180.v:3986$403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3986$401_Y + connect \B $not$ls180.v:3986$402_Y + connect \Y $and$ls180.v:3986$403_Y + end + attribute \src "ls180.v:3986.76-3986.333" + cell $and $and$ls180.v:3986$406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3986$399_Y + connect \B $or$ls180.v:3986$405_Y + connect \Y $and$ls180.v:3986$406_Y + end + attribute \src "ls180.v:3986.338-3986.505" + cell $and $and$ls180.v:3986$409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3986$407_Y + connect \B $eq$ls180.v:3986$408_Y + connect \Y $and$ls180.v:3986$409_Y + end + attribute \src "ls180.v:3986.38-3986.507" + cell $and $and$ls180.v:3986$411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3986$410_Y + connect \Y $and$ls180.v:3986$411_Y + end + attribute \src "ls180.v:3987.77-3987.153" + cell $and $and$ls180.v:3987$412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3987$412_Y + end + attribute \src "ls180.v:3987.162-3987.246" + cell $and $and$ls180.v:3987$414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3987$413_Y + connect \Y $and$ls180.v:3987$414_Y + end + attribute \src "ls180.v:3987.161-3987.291" + cell $and $and$ls180.v:3987$416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3987$414_Y + connect \B $not$ls180.v:3987$415_Y + connect \Y $and$ls180.v:3987$416_Y + end + attribute \src "ls180.v:3987.76-3987.333" + cell $and $and$ls180.v:3987$419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3987$412_Y + connect \B $or$ls180.v:3987$418_Y + connect \Y $and$ls180.v:3987$419_Y + end + attribute \src "ls180.v:3987.338-3987.505" + cell $and $and$ls180.v:3987$422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3987$420_Y + connect \B $eq$ls180.v:3987$421_Y + connect \Y $and$ls180.v:3987$422_Y + end + attribute \src "ls180.v:3987.38-3987.507" + cell $and $and$ls180.v:3987$424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3987$423_Y + connect \Y $and$ls180.v:3987$424_Y + end + attribute \src "ls180.v:3988.77-3988.153" + cell $and $and$ls180.v:3988$425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3988$425_Y + end + attribute \src "ls180.v:3988.162-3988.246" + cell $and $and$ls180.v:3988$427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3988$426_Y + connect \Y $and$ls180.v:3988$427_Y + end + attribute \src "ls180.v:3988.161-3988.291" + cell $and $and$ls180.v:3988$429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$427_Y + connect \B $not$ls180.v:3988$428_Y + connect \Y $and$ls180.v:3988$429_Y + end + attribute \src "ls180.v:3988.76-3988.333" + cell $and $and$ls180.v:3988$432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$425_Y + connect \B $or$ls180.v:3988$431_Y + connect \Y $and$ls180.v:3988$432_Y + end + attribute \src "ls180.v:3988.338-3988.505" + cell $and $and$ls180.v:3988$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$433_Y + connect \B $eq$ls180.v:3988$434_Y + connect \Y $and$ls180.v:3988$435_Y + end + attribute \src "ls180.v:3988.38-3988.507" + cell $and $and$ls180.v:3988$437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3988$436_Y + connect \Y $and$ls180.v:3988$437_Y + end + attribute \src "ls180.v:4018.77-4018.153" + cell $and $and$ls180.v:4018$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:4018$444_Y + end + attribute \src "ls180.v:4018.162-4018.246" + cell $and $and$ls180.v:4018$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:4018$445_Y + connect \Y $and$ls180.v:4018$446_Y + end + attribute \src "ls180.v:4018.161-4018.291" + cell $and $and$ls180.v:4018$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4018$446_Y + connect \B $not$ls180.v:4018$447_Y + connect \Y $and$ls180.v:4018$448_Y + end + attribute \src "ls180.v:4018.76-4018.333" + cell $and $and$ls180.v:4018$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4018$444_Y + connect \B $or$ls180.v:4018$450_Y + connect \Y $and$ls180.v:4018$451_Y + end + attribute \src "ls180.v:4018.338-4018.505" + cell $and $and$ls180.v:4018$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4018$452_Y + connect \B $eq$ls180.v:4018$453_Y + connect \Y $and$ls180.v:4018$454_Y + end + attribute \src "ls180.v:4018.38-4018.507" + cell $and $and$ls180.v:4018$456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:4018$455_Y + connect \Y $and$ls180.v:4018$456_Y + end + attribute \src "ls180.v:4019.77-4019.153" + cell $and $and$ls180.v:4019$457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:4019$457_Y + end + attribute \src "ls180.v:4019.162-4019.246" + cell $and $and$ls180.v:4019$459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:4019$458_Y + connect \Y $and$ls180.v:4019$459_Y + end + attribute \src "ls180.v:4019.161-4019.291" + cell $and $and$ls180.v:4019$461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4019$459_Y + connect \B $not$ls180.v:4019$460_Y + connect \Y $and$ls180.v:4019$461_Y + end + attribute \src "ls180.v:4019.76-4019.333" + cell $and $and$ls180.v:4019$464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4019$457_Y + connect \B $or$ls180.v:4019$463_Y + connect \Y $and$ls180.v:4019$464_Y + end + attribute \src "ls180.v:4019.338-4019.505" + cell $and $and$ls180.v:4019$467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4019$465_Y + connect \B $eq$ls180.v:4019$466_Y + connect \Y $and$ls180.v:4019$467_Y + end + attribute \src "ls180.v:4019.38-4019.507" + cell $and $and$ls180.v:4019$469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:4019$468_Y + connect \Y $and$ls180.v:4019$469_Y + end + attribute \src "ls180.v:4020.77-4020.153" + cell $and $and$ls180.v:4020$470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:4020$470_Y + end + attribute \src "ls180.v:4020.162-4020.246" + cell $and $and$ls180.v:4020$472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:4020$471_Y + connect \Y $and$ls180.v:4020$472_Y + end + attribute \src "ls180.v:4020.161-4020.291" + cell $and $and$ls180.v:4020$474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4020$472_Y + connect \B $not$ls180.v:4020$473_Y + connect \Y $and$ls180.v:4020$474_Y + end + attribute \src "ls180.v:4020.76-4020.333" + cell $and $and$ls180.v:4020$477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4020$470_Y + connect \B $or$ls180.v:4020$476_Y + connect \Y $and$ls180.v:4020$477_Y + end + attribute \src "ls180.v:4020.338-4020.505" + cell $and $and$ls180.v:4020$480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4020$478_Y + connect \B $eq$ls180.v:4020$479_Y + connect \Y $and$ls180.v:4020$480_Y + end + attribute \src "ls180.v:4020.38-4020.507" + cell $and $and$ls180.v:4020$482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:4020$481_Y + connect \Y $and$ls180.v:4020$482_Y + end + attribute \src "ls180.v:4021.77-4021.153" + cell $and $and$ls180.v:4021$483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:4021$483_Y + end + attribute \src "ls180.v:4021.162-4021.246" + cell $and $and$ls180.v:4021$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:4021$484_Y + connect \Y $and$ls180.v:4021$485_Y + end + attribute \src "ls180.v:4021.161-4021.291" + cell $and $and$ls180.v:4021$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4021$485_Y + connect \B $not$ls180.v:4021$486_Y + connect \Y $and$ls180.v:4021$487_Y + end + attribute \src "ls180.v:4021.76-4021.333" + cell $and $and$ls180.v:4021$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4021$483_Y + connect \B $or$ls180.v:4021$489_Y + connect \Y $and$ls180.v:4021$490_Y + end + attribute \src "ls180.v:4021.338-4021.505" + cell $and $and$ls180.v:4021$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4021$491_Y + connect \B $eq$ls180.v:4021$492_Y + connect \Y $and$ls180.v:4021$493_Y + end + attribute \src "ls180.v:4021.38-4021.507" + cell $and $and$ls180.v:4021$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:4021$494_Y + connect \Y $and$ls180.v:4021$495_Y + end + attribute \src "ls180.v:4050.8-4050.73" + cell $and $and$ls180.v:4050$500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:4050$500_Y + end + attribute \src "ls180.v:4050.7-4050.114" + cell $and $and$ls180.v:4050$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4050$500_Y + connect \B $eq$ls180.v:4050$501_Y + connect \Y $and$ls180.v:4050$502_Y + end + attribute \src "ls180.v:4053.8-4053.73" + cell $and $and$ls180.v:4053$503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4053$503_Y + end + attribute \src "ls180.v:4053.7-4053.114" + cell $and $and$ls180.v:4053$505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4053$503_Y + connect \B $eq$ls180.v:4053$504_Y + connect \Y $and$ls180.v:4053$505_Y + end + attribute \src "ls180.v:4059.8-4059.73" + cell $and $and$ls180.v:4059$507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:4059$507_Y + end + attribute \src "ls180.v:4059.7-4059.114" + cell $and $and$ls180.v:4059$509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4059$507_Y + connect \B $eq$ls180.v:4059$508_Y + connect \Y $and$ls180.v:4059$509_Y + end + attribute \src "ls180.v:4062.8-4062.73" + cell $and $and$ls180.v:4062$510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4062$510_Y + end + attribute \src "ls180.v:4062.7-4062.114" + cell $and $and$ls180.v:4062$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4062$510_Y + connect \B $eq$ls180.v:4062$511_Y + connect \Y $and$ls180.v:4062$512_Y + end + attribute \src "ls180.v:4068.8-4068.73" + cell $and $and$ls180.v:4068$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:4068$514_Y + end + attribute \src "ls180.v:4068.7-4068.114" + cell $and $and$ls180.v:4068$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4068$514_Y + connect \B $eq$ls180.v:4068$515_Y + connect \Y $and$ls180.v:4068$516_Y + end + attribute \src "ls180.v:4071.8-4071.73" + cell $and $and$ls180.v:4071$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4071$517_Y + end + attribute \src "ls180.v:4071.7-4071.114" + cell $and $and$ls180.v:4071$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4071$517_Y + connect \B $eq$ls180.v:4071$518_Y + connect \Y $and$ls180.v:4071$519_Y + end + attribute \src "ls180.v:4077.8-4077.73" + cell $and $and$ls180.v:4077$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:4077$521_Y + end + attribute \src "ls180.v:4077.7-4077.114" + cell $and $and$ls180.v:4077$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4077$521_Y + connect \B $eq$ls180.v:4077$522_Y + connect \Y $and$ls180.v:4077$523_Y + end + attribute \src "ls180.v:4080.8-4080.73" + cell $and $and$ls180.v:4080$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4080$524_Y + end + attribute \src "ls180.v:4080.7-4080.114" + cell $and $and$ls180.v:4080$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4080$524_Y + connect \B $eq$ls180.v:4080$525_Y + connect \Y $and$ls180.v:4080$526_Y + end + attribute \src "ls180.v:4105.71-4105.151" + cell $and $and$ls180.v:4105$531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:4105$530_Y + connect \Y $and$ls180.v:4105$531_Y + end + attribute \src "ls180.v:4105.70-4105.194" + cell $and $and$ls180.v:4105$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4105$531_Y + connect \B $not$ls180.v:4105$532_Y + connect \Y $and$ls180.v:4105$533_Y + end + attribute \src "ls180.v:4105.41-4105.222" + cell $and $and$ls180.v:4105$536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:4105$535_Y + connect \Y $and$ls180.v:4105$536_Y + end + attribute \src "ls180.v:4143.71-4143.151" + cell $and $and$ls180.v:4143$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:4143$539_Y + connect \Y $and$ls180.v:4143$540_Y + end + attribute \src "ls180.v:4143.70-4143.194" + cell $and $and$ls180.v:4143$542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4143$540_Y + connect \B $not$ls180.v:4143$541_Y + connect \Y $and$ls180.v:4143$542_Y + end + attribute \src "ls180.v:4143.41-4143.222" + cell $and $and$ls180.v:4143$545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:4143$544_Y + connect \Y $and$ls180.v:4143$545_Y + end + attribute \src "ls180.v:4161.110-4161.179" + cell $and $and$ls180.v:4161$550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4161$549_Y + connect \Y $and$ls180.v:4161$550_Y + end + attribute \src "ls180.v:4161.185-4161.254" + cell $and $and$ls180.v:4161$553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4161$552_Y + connect \Y $and$ls180.v:4161$553_Y + end + attribute \src "ls180.v:4161.260-4161.329" + cell $and $and$ls180.v:4161$556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4161$555_Y + connect \Y $and$ls180.v:4161$556_Y + end + attribute \src "ls180.v:4161.41-4161.332" + cell $and $and$ls180.v:4161$559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4161$548_Y + connect \B $not$ls180.v:4161$558_Y + connect \Y $and$ls180.v:4161$559_Y + end + attribute \src "ls180.v:4161.40-4161.355" + cell $and $and$ls180.v:4161$560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4161$559_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4161$560_Y + end + attribute \src "ls180.v:4162.34-4162.106" + cell $and $and$ls180.v:4162$563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4162$561_Y + connect \B $not$ls180.v:4162$562_Y + connect \Y $and$ls180.v:4162$563_Y + end + attribute \src "ls180.v:4166.110-4166.179" + cell $and $and$ls180.v:4166$566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4166$565_Y + connect \Y $and$ls180.v:4166$566_Y + end + attribute \src "ls180.v:4166.185-4166.254" + cell $and $and$ls180.v:4166$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4166$568_Y + connect \Y $and$ls180.v:4166$569_Y + end + attribute \src "ls180.v:4166.260-4166.329" + cell $and $and$ls180.v:4166$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4166$571_Y + connect \Y $and$ls180.v:4166$572_Y + end + attribute \src "ls180.v:4166.41-4166.332" + cell $and $and$ls180.v:4166$575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4166$564_Y + connect \B $not$ls180.v:4166$574_Y + connect \Y $and$ls180.v:4166$575_Y + end + attribute \src "ls180.v:4166.40-4166.355" + cell $and $and$ls180.v:4166$576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4166$575_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4166$576_Y + end + attribute \src "ls180.v:4167.34-4167.106" + cell $and $and$ls180.v:4167$579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4167$577_Y + connect \B $not$ls180.v:4167$578_Y + connect \Y $and$ls180.v:4167$579_Y + end + attribute \src "ls180.v:4171.110-4171.179" + cell $and $and$ls180.v:4171$582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4171$581_Y + connect \Y $and$ls180.v:4171$582_Y + end + attribute \src "ls180.v:4171.185-4171.254" + cell $and $and$ls180.v:4171$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4171$584_Y + connect \Y $and$ls180.v:4171$585_Y + end + attribute \src "ls180.v:4171.260-4171.329" + cell $and $and$ls180.v:4171$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4171$587_Y + connect \Y $and$ls180.v:4171$588_Y + end + attribute \src "ls180.v:4171.41-4171.332" + cell $and $and$ls180.v:4171$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4171$580_Y + connect \B $not$ls180.v:4171$590_Y + connect \Y $and$ls180.v:4171$591_Y + end + attribute \src "ls180.v:4171.40-4171.355" + cell $and $and$ls180.v:4171$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4171$591_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4171$592_Y + end + attribute \src "ls180.v:4172.34-4172.106" + cell $and $and$ls180.v:4172$595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4172$593_Y + connect \B $not$ls180.v:4172$594_Y + connect \Y $and$ls180.v:4172$595_Y + end + attribute \src "ls180.v:4176.110-4176.179" + cell $and $and$ls180.v:4176$598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4176$597_Y + connect \Y $and$ls180.v:4176$598_Y + end + attribute \src "ls180.v:4176.185-4176.254" + cell $and $and$ls180.v:4176$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4176$600_Y + connect \Y $and$ls180.v:4176$601_Y + end + attribute \src "ls180.v:4176.260-4176.329" + cell $and $and$ls180.v:4176$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4176$603_Y + connect \Y $and$ls180.v:4176$604_Y + end + attribute \src "ls180.v:4176.41-4176.332" + cell $and $and$ls180.v:4176$607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4176$596_Y + connect \B $not$ls180.v:4176$606_Y + connect \Y $and$ls180.v:4176$607_Y + end + attribute \src "ls180.v:4176.40-4176.355" + cell $and $and$ls180.v:4176$608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4176$607_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4176$608_Y + end + attribute \src "ls180.v:4177.34-4177.106" + cell $and $and$ls180.v:4177$611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4177$609_Y + connect \B $not$ls180.v:4177$610_Y + connect \Y $and$ls180.v:4177$611_Y + end + attribute \src "ls180.v:4181.151-4181.220" + cell $and $and$ls180.v:4181$615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4181$614_Y + connect \Y $and$ls180.v:4181$615_Y + end + attribute \src "ls180.v:4181.226-4181.295" + cell $and $and$ls180.v:4181$618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4181$617_Y + connect \Y $and$ls180.v:4181$618_Y + end + attribute \src "ls180.v:4181.301-4181.370" + cell $and $and$ls180.v:4181$621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4181$620_Y + connect \Y $and$ls180.v:4181$621_Y + end + attribute \src "ls180.v:4181.82-4181.373" + cell $and $and$ls180.v:4181$624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$613_Y + connect \B $not$ls180.v:4181$623_Y + connect \Y $and$ls180.v:4181$624_Y + end + attribute \src "ls180.v:4181.43-4181.374" + cell $and $and$ls180.v:4181$625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$612_Y + connect \B $and$ls180.v:4181$624_Y + connect \Y $and$ls180.v:4181$625_Y + end + attribute \src "ls180.v:4181.42-4181.410" + cell $and $and$ls180.v:4181$626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4181$625_Y + connect \B \main_sdram_interface_bank0_ready + connect \Y $and$ls180.v:4181$626_Y + end + attribute \src "ls180.v:4181.525-4181.594" + cell $and $and$ls180.v:4181$631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4181$630_Y + connect \Y $and$ls180.v:4181$631_Y + end + attribute \src "ls180.v:4181.600-4181.669" + cell $and $and$ls180.v:4181$634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4181$633_Y + connect \Y $and$ls180.v:4181$634_Y + end + attribute \src "ls180.v:4181.675-4181.744" + cell $and $and$ls180.v:4181$637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4181$636_Y + connect \Y $and$ls180.v:4181$637_Y + end + attribute \src "ls180.v:4181.456-4181.747" + cell $and $and$ls180.v:4181$640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$629_Y + connect \B $not$ls180.v:4181$639_Y + connect \Y $and$ls180.v:4181$640_Y + end + attribute \src "ls180.v:4181.417-4181.748" + cell $and $and$ls180.v:4181$641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$628_Y + connect \B $and$ls180.v:4181$640_Y + connect \Y $and$ls180.v:4181$641_Y + end + attribute \src "ls180.v:4181.416-4181.784" + cell $and $and$ls180.v:4181$642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4181$641_Y + connect \B \main_sdram_interface_bank1_ready + connect \Y $and$ls180.v:4181$642_Y + end + attribute \src "ls180.v:4181.899-4181.968" + cell $and $and$ls180.v:4181$647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4181$646_Y + connect \Y $and$ls180.v:4181$647_Y + end + attribute \src "ls180.v:4181.974-4181.1043" + cell $and $and$ls180.v:4181$650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4181$649_Y + connect \Y $and$ls180.v:4181$650_Y + end + attribute \src "ls180.v:4181.1049-4181.1118" + cell $and $and$ls180.v:4181$653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4181$652_Y + connect \Y $and$ls180.v:4181$653_Y + end + attribute \src "ls180.v:4181.830-4181.1121" + cell $and $and$ls180.v:4181$656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$645_Y + connect \B $not$ls180.v:4181$655_Y + connect \Y $and$ls180.v:4181$656_Y + end + attribute \src "ls180.v:4181.791-4181.1122" + cell $and $and$ls180.v:4181$657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$644_Y + connect \B $and$ls180.v:4181$656_Y + connect \Y $and$ls180.v:4181$657_Y + end + attribute \src "ls180.v:4181.790-4181.1158" + cell $and $and$ls180.v:4181$658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4181$657_Y + connect \B \main_sdram_interface_bank2_ready + connect \Y $and$ls180.v:4181$658_Y + end + attribute \src "ls180.v:4181.1273-4181.1342" + cell $and $and$ls180.v:4181$663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4181$662_Y + connect \Y $and$ls180.v:4181$663_Y + end + attribute \src "ls180.v:4181.1348-4181.1417" + cell $and $and$ls180.v:4181$666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4181$665_Y + connect \Y $and$ls180.v:4181$666_Y + end + attribute \src "ls180.v:4181.1423-4181.1492" + cell $and $and$ls180.v:4181$669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4181$668_Y + connect \Y $and$ls180.v:4181$669_Y + end + attribute \src "ls180.v:4181.1204-4181.1495" + cell $and $and$ls180.v:4181$672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$661_Y + connect \B $not$ls180.v:4181$671_Y + connect \Y $and$ls180.v:4181$672_Y + end + attribute \src "ls180.v:4181.1165-4181.1496" + cell $and $and$ls180.v:4181$673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$660_Y + connect \B $and$ls180.v:4181$672_Y + connect \Y $and$ls180.v:4181$673_Y + end + attribute \src "ls180.v:4181.1164-4181.1532" + cell $and $and$ls180.v:4181$674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4181$673_Y + connect \B \main_sdram_interface_bank3_ready + connect \Y $and$ls180.v:4181$674_Y + end + attribute \src "ls180.v:4239.9-4239.46" + cell $and $and$ls180.v:4239$680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4239$680_Y + end + attribute \src "ls180.v:4257.9-4257.46" + cell $and $and$ls180.v:4257$687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4257$687_Y + end + attribute \src "ls180.v:4270.32-4270.75" + cell $and $and$ls180.v:4270$691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \B \main_litedram_wb_stb + connect \Y $and$ls180.v:4270$691_Y + end + attribute \src "ls180.v:4270.31-4270.99" + cell $and $and$ls180.v:4270$693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4270$691_Y + connect \B $not$ls180.v:4270$692_Y + connect \Y $and$ls180.v:4270$693_Y + end + attribute \src "ls180.v:4271.34-4271.102" + cell $and $and$ls180.v:4271$695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4271$694_Y + connect \B \main_port_cmd_payload_we + connect \Y $and$ls180.v:4271$695_Y + end + attribute \src "ls180.v:4271.33-4271.128" + cell $and $and$ls180.v:4271$697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4271$695_Y + connect \B $not$ls180.v:4271$696_Y + connect \Y $and$ls180.v:4271$697_Y + end + attribute \src "ls180.v:4272.33-4272.104" + cell $and $and$ls180.v:4272$700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4272$698_Y + connect \B $not$ls180.v:4272$699_Y + connect \Y $and$ls180.v:4272$700_Y + end + attribute \src "ls180.v:4273.49-4273.85" + cell $and $and$ls180.v:4273$701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \B \main_ack_wdata + connect \Y $and$ls180.v:4273$701_Y + end + attribute \src "ls180.v:4273.90-4273.129" + cell $and $and$ls180.v:4273$703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4273$702_Y + connect \B \main_ack_rdata + connect \Y $and$ls180.v:4273$703_Y + end + attribute \src "ls180.v:4273.32-4273.131" + cell $and $and$ls180.v:4273$705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ack_cmd + connect \B $or$ls180.v:4273$704_Y + connect \Y $and$ls180.v:4273$705_Y + end + attribute \src "ls180.v:4274.25-4274.66" + cell $and $and$ls180.v:4274$706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:4274$706_Y + end + attribute \src "ls180.v:4275.27-4275.72" + cell $and $and$ls180.v:4275$708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:4275$708_Y + end + attribute \src "ls180.v:4276.26-4276.71" + cell $and $and$ls180.v:4276$710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_rdata_valid + connect \B \main_port_rdata_ready + connect \Y $and$ls180.v:4276$710_Y + end + attribute \src "ls180.v:4305.64-4305.88" + cell $and $and$ls180.v:4305$716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \main_uart_rxtx_we + connect \Y $and$ls180.v:4305$716_Y + end + attribute \src "ls180.v:4309.7-4309.78" + cell $and $and$ls180.v:4309$720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [0] + connect \Y $and$ls180.v:4309$720_Y + end + attribute \src "ls180.v:4320.7-4320.78" + cell $and $and$ls180.v:4320$723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [1] + connect \Y $and$ls180.v:4320$723_Y + end + attribute \src "ls180.v:4329.26-4329.97" + cell $and $and$ls180.v:4329$725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [0] + connect \B \main_uart_eventmanager_storage [0] + connect \Y $and$ls180.v:4329$725_Y + end + attribute \src "ls180.v:4329.102-4329.173" + cell $and $and$ls180.v:4329$726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [1] + connect \B \main_uart_eventmanager_storage [1] + connect \Y $and$ls180.v:4329$726_Y + end + attribute \src "ls180.v:4344.41-4344.133" + cell $and $and$ls180.v:4344$730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B $or$ls180.v:4344$729_Y + connect \Y $and$ls180.v:4344$730_Y + end + attribute \src "ls180.v:4355.39-4355.136" + cell $and $and$ls180.v:4355$735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B $or$ls180.v:4355$734_Y + connect \Y $and$ls180.v:4355$735_Y + end + attribute \src "ls180.v:4356.37-4356.104" + cell $and $and$ls180.v:4356$736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B \main_uart_tx_fifo_syncfifo_re + connect \Y $and$ls180.v:4356$736_Y + end + attribute \src "ls180.v:4374.41-4374.133" + cell $and $and$ls180.v:4374$741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B $or$ls180.v:4374$740_Y + connect \Y $and$ls180.v:4374$741_Y + end + attribute \src "ls180.v:4385.39-4385.136" + cell $and $and$ls180.v:4385$746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B $or$ls180.v:4385$745_Y + connect \Y $and$ls180.v:4385$746_Y + end + attribute \src "ls180.v:4386.37-4386.104" + cell $and $and$ls180.v:4386$747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B \main_uart_rx_fifo_syncfifo_re + connect \Y $and$ls180.v:4386$747_Y + end + attribute \src "ls180.v:4585.33-4585.86" + cell $and $and$ls180.v:4585$791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk1 + connect \B $not$ls180.v:4585$790_Y + connect \Y $and$ls180.v:4585$791_Y + end + attribute \src "ls180.v:4689.9-4689.68" + cell $and $and$ls180.v:4689$800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_pads_out_ready + connect \Y $and$ls180.v:4689$800_Y + end + attribute \src "ls180.v:4709.53-4709.145" + cell $and $and$ls180.v:4709$803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_valid + connect \B $or$ls180.v:4709$802_Y + connect \Y $and$ls180.v:4709$803_Y + end + attribute \src "ls180.v:4728.52-4728.137" + cell $and $and$ls180.v:4728$806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:4728$806_Y + end + attribute \src "ls180.v:4769.9-4769.68" + cell $and $and$ls180.v:4769$814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4769$814_Y + end + attribute \src "ls180.v:4807.9-4807.68" + cell $and $and$ls180.v:4807$820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4807$820_Y + end + attribute \src "ls180.v:4816.10-4816.69" + cell $and $and$ls180.v:4816$821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_sink_valid + connect \B \main_sdphy_cmdr_pads_out_ready + connect \Y $and$ls180.v:4816$821_Y + end + attribute \src "ls180.v:4816.9-4816.93" + cell $and $and$ls180.v:4816$822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4816$821_Y + connect \B \main_sdphy_cmdw_done + connect \Y $and$ls180.v:4816$822_Y + end + attribute \src "ls180.v:4836.54-4836.117" + cell $and $and$ls180.v:4836$824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_valid + connect \B \main_sdphy_dataw_crcr_run + connect \Y $and$ls180.v:4836$824_Y + end + attribute \src "ls180.v:4855.53-4855.140" + cell $and $and$ls180.v:4855$827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:4855$827_Y + end + attribute \src "ls180.v:4952.9-4952.70" + cell $and $and$ls180.v:4952$837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_pads_out_ready + connect \Y $and$ls180.v:4952$837_Y + end + attribute \src "ls180.v:4970.55-4970.120" + cell $and $and$ls180.v:4970$839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_valid + connect \B \main_sdphy_datar_datar_run + connect \Y $and$ls180.v:4970$839_Y + end + attribute \src "ls180.v:4989.54-4989.143" + cell $and $and$ls180.v:4989$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:4989$842_Y + end + attribute \src "ls180.v:5071.9-5071.70" + cell $and $and$ls180.v:5071$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_valid + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:5071$857_Y + end + attribute \src "ls180.v:5078.9-5078.70" + cell $and $and$ls180.v:5078$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_sink_valid + connect \B \main_sdphy_datar_pads_out_ready + connect \Y $and$ls180.v:5078$858_Y + end + attribute \src "ls180.v:5159.48-5159.124" + cell $and $and$ls180.v:5159$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5159$981_Y + end + attribute \src "ls180.v:5159.47-5159.165" + cell $and $and$ls180.v:5159$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5159$981_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5159$982_Y + end + attribute \src "ls180.v:5160.50-5160.127" + cell $and $and$ls180.v:5160$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5160$983_Y + end + attribute \src "ls180.v:5162.48-5162.124" + cell $and $and$ls180.v:5162$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5162$984_Y + end + attribute \src "ls180.v:5162.47-5162.165" + cell $and $and$ls180.v:5162$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5162$984_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5162$985_Y + end + attribute \src "ls180.v:5163.50-5163.127" + cell $and $and$ls180.v:5163$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5163$986_Y + end + attribute \src "ls180.v:5165.48-5165.124" + cell $and $and$ls180.v:5165$987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5165$987_Y + end + attribute \src "ls180.v:5165.47-5165.165" + cell $and $and$ls180.v:5165$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5165$987_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5165$988_Y + end + attribute \src "ls180.v:5166.50-5166.127" + cell $and $and$ls180.v:5166$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5166$989_Y + end + attribute \src "ls180.v:5168.48-5168.124" + cell $and $and$ls180.v:5168$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5168$990_Y + end + attribute \src "ls180.v:5168.47-5168.165" + cell $and $and$ls180.v:5168$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5168$990_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5168$991_Y + end + attribute \src "ls180.v:5169.50-5169.127" + cell $and $and$ls180.v:5169$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5169$992_Y + end + attribute \src "ls180.v:5282.10-5282.86" + cell $and $and$ls180.v:5282$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_last + connect \Y $and$ls180.v:5282$1041_Y + end + attribute \src "ls180.v:5282.9-5282.127" + cell $and $and$ls180.v:5282$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5282$1041_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5282$1042_Y + end + attribute \src "ls180.v:5292.9-5292.152" + cell $and $and$ls180.v:5292$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:5292$1044_Y + connect \B $eq$ls180.v:5292$1045_Y + connect \Y $and$ls180.v:5292$1046_Y + end + attribute \src "ls180.v:5292.8-5292.226" + cell $and $and$ls180.v:5292$1048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5292$1046_Y + connect \B $eq$ls180.v:5292$1047_Y + connect \Y $and$ls180.v:5292$1048_Y + end + attribute \src "ls180.v:5292.7-5292.300" + cell $and $and$ls180.v:5292$1050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5292$1048_Y + connect \B $eq$ls180.v:5292$1049_Y + connect \Y $and$ls180.v:5292$1050_Y + end + attribute \src "ls180.v:5297.49-5297.124" + cell $and $and$ls180.v:5297$1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5297$1051_Y + end + attribute \src "ls180.v:5307.49-5307.124" + cell $and $and$ls180.v:5307$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5307$1054_Y + end + attribute \src "ls180.v:5317.49-5317.124" + cell $and $and$ls180.v:5317$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5317$1057_Y + end + attribute \src "ls180.v:5327.49-5327.124" + cell $and $and$ls180.v:5327$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5327$1060_Y + end + attribute \src "ls180.v:5339.7-5339.84" + cell $and $and$ls180.v:5339$1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B $gt$ls180.v:5339$1064_Y + connect \Y $and$ls180.v:5339$1065_Y + end + attribute \src "ls180.v:5457.9-5457.64" + cell $and $and$ls180.v:5457$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_sink_ready + connect \Y $and$ls180.v:5457$1114_Y + end + attribute \src "ls180.v:5509.10-5509.66" + cell $and $and$ls180.v:5509$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_sink_last + connect \Y $and$ls180.v:5509$1123_Y + end + attribute \src "ls180.v:5509.9-5509.97" + cell $and $and$ls180.v:5509$1124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5509$1123_Y + connect \B \main_sdphy_dataw_sink_ready + connect \Y $and$ls180.v:5509$1124_Y + end + attribute \src "ls180.v:5535.11-5535.71" + cell $and $and$ls180.v:5535$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_last + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:5535$1132_Y + end + attribute \src "ls180.v:5619.43-5619.152" + cell $and $and$ls180.v:5619$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B $or$ls180.v:5619$1139_Y + connect \Y $and$ls180.v:5619$1140_Y + end + attribute \src "ls180.v:5620.41-5620.116" + cell $and $and$ls180.v:5620$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_readable + connect \B \main_sdblock2mem_fifo_syncfifo_re + connect \Y $and$ls180.v:5620$1141_Y + end + attribute \src "ls180.v:5632.48-5632.125" + cell $and $and$ls180.v:5632$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:5632$1146_Y + end + attribute \src "ls180.v:5659.9-5659.102" + cell $and $and$ls180.v:5659$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid + connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \Y $and$ls180.v:5659$1150_Y + end + attribute \src "ls180.v:5732.9-5732.58" + cell $and $and$ls180.v:5732$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_bus_stb + connect \B \main_interface1_bus_ack + connect \Y $and$ls180.v:5732$1156_Y + end + attribute \src "ls180.v:5785.51-5785.123" + cell $and $and$ls180.v:5785$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_first + connect \B \main_sdmem2block_converter_first + connect \Y $and$ls180.v:5785$1164_Y + end + attribute \src "ls180.v:5786.50-5786.120" + cell $and $and$ls180.v:5786$1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_last + connect \B \main_sdmem2block_converter_last + connect \Y $and$ls180.v:5786$1165_Y + end + attribute \src "ls180.v:5787.49-5787.122" + cell $and $and$ls180.v:5787$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_last + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:5787$1166_Y + end + attribute \src "ls180.v:5839.43-5839.152" + cell $and $and$ls180.v:5839$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B $or$ls180.v:5839$1170_Y + connect \Y $and$ls180.v:5839$1171_Y + end + attribute \src "ls180.v:5840.41-5840.116" + cell $and $and$ls180.v:5840$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_readable + connect \B \main_sdmem2block_fifo_syncfifo_re + connect \Y $and$ls180.v:5840$1172_Y + end + attribute \src "ls180.v:5872.9-5872.76" + cell $and $and$ls180.v:5872$1176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_cyc + connect \B \builder_libresocsim_wishbone_stb + connect \Y $and$ls180.v:5872$1176_Y + end + attribute \src "ls180.v:5875.44-5875.120" + cell $and $and$ls180.v:5875$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_we + connect \B $ne$ls180.v:5875$1177_Y + connect \Y $and$ls180.v:5875$1178_Y + end + attribute \src "ls180.v:5895.46-5895.90" + cell $and $and$ls180.v:5895$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5895$1179_Y + connect \Y $and$ls180.v:5895$1180_Y + end + attribute \src "ls180.v:5896.46-5896.90" + cell $and $and$ls180.v:5896$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5896$1181_Y + connect \Y $and$ls180.v:5896$1182_Y + end + attribute \src "ls180.v:5897.49-5897.93" + cell $and $and$ls180.v:5897$1184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5897$1183_Y + connect \Y $and$ls180.v:5897$1184_Y + end + attribute \src "ls180.v:5898.35-5898.79" + cell $and $and$ls180.v:5898$1186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5898$1185_Y + connect \Y $and$ls180.v:5898$1186_Y + end + attribute \src "ls180.v:5899.35-5899.79" + cell $and $and$ls180.v:5899$1188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5899$1187_Y + connect \Y $and$ls180.v:5899$1188_Y + end + attribute \src "ls180.v:5900.46-5900.90" + cell $and $and$ls180.v:5900$1190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5900$1189_Y + connect \Y $and$ls180.v:5900$1190_Y + end + attribute \src "ls180.v:5901.46-5901.90" + cell $and $and$ls180.v:5901$1192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5901$1191_Y + connect \Y $and$ls180.v:5901$1192_Y + end + attribute \src "ls180.v:5902.49-5902.93" + cell $and $and$ls180.v:5902$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5902$1193_Y + connect \Y $and$ls180.v:5902$1194_Y + end + attribute \src "ls180.v:5903.35-5903.79" + cell $and $and$ls180.v:5903$1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5903$1195_Y + connect \Y $and$ls180.v:5903$1196_Y + end + attribute \src "ls180.v:5904.35-5904.79" + cell $and $and$ls180.v:5904$1198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5904$1197_Y + connect \Y $and$ls180.v:5904$1198_Y + end + attribute \src "ls180.v:6013.40-6013.81" + cell $and $and$ls180.v:6013$1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [0] + connect \Y $and$ls180.v:6013$1213_Y + end + attribute \src "ls180.v:6014.39-6014.80" + cell $and $and$ls180.v:6014$1214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [1] + connect \Y $and$ls180.v:6014$1214_Y + end + attribute \src "ls180.v:6015.39-6015.80" + cell $and $and$ls180.v:6015$1215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [2] + connect \Y $and$ls180.v:6015$1215_Y + end + attribute \src "ls180.v:6016.39-6016.80" + cell $and $and$ls180.v:6016$1216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [3] + connect \Y $and$ls180.v:6016$1216_Y + end + attribute \src "ls180.v:6017.39-6017.80" + cell $and $and$ls180.v:6017$1217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [4] + connect \Y $and$ls180.v:6017$1217_Y + end + attribute \src "ls180.v:6018.51-6018.92" + cell $and $and$ls180.v:6018$1218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [5] + connect \Y $and$ls180.v:6018$1218_Y + end + attribute \src "ls180.v:6019.51-6019.92" + cell $and $and$ls180.v:6019$1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [6] + connect \Y $and$ls180.v:6019$1219_Y + end + attribute \src "ls180.v:6020.52-6020.93" + cell $and $and$ls180.v:6020$1220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [7] + connect \Y $and$ls180.v:6020$1220_Y + end + attribute \src "ls180.v:6021.52-6021.93" + cell $and $and$ls180.v:6021$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [8] + connect \Y $and$ls180.v:6021$1221_Y + end + attribute \src "ls180.v:6022.52-6022.93" + cell $and $and$ls180.v:6022$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [9] + connect \Y $and$ls180.v:6022$1222_Y + end + attribute \src "ls180.v:6023.52-6023.94" + cell $and $and$ls180.v:6023$1223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [10] + connect \Y $and$ls180.v:6023$1223_Y + end + attribute \src "ls180.v:6024.54-6024.96" + cell $and $and$ls180.v:6024$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [11] + connect \Y $and$ls180.v:6024$1224_Y + end + attribute \src "ls180.v:6025.55-6025.97" + cell $and $and$ls180.v:6025$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [12] + connect \Y $and$ls180.v:6025$1225_Y + end + attribute \src "ls180.v:6027.25-6027.64" + cell $and $and$ls180.v:6027$1238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_stb + connect \B \builder_shared_cyc + connect \Y $and$ls180.v:6027$1238_Y + end + attribute \src "ls180.v:6027.24-6027.89" + cell $and $and$ls180.v:6027$1240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6027$1238_Y + connect \B $not$ls180.v:6027$1239_Y + connect \Y $and$ls180.v:6027$1240_Y + end + attribute \src "ls180.v:6033.39-6033.100" + cell $and $and$ls180.v:6033$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + connect \B \main_libresocsim_ram_bus_dat_r + connect \Y $and$ls180.v:6033$1254_Y + end + attribute \src "ls180.v:6033.105-6033.165" + cell $and $and$ls180.v:6033$1255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + connect \B \main_interface0_ram_bus_dat_r + connect \Y $and$ls180.v:6033$1255_Y + end + attribute \src "ls180.v:6033.171-6033.231" + cell $and $and$ls180.v:6033$1257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + connect \B \main_interface1_ram_bus_dat_r + connect \Y $and$ls180.v:6033$1257_Y + end + attribute \src "ls180.v:6033.237-6033.297" + cell $and $and$ls180.v:6033$1259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + connect \B \main_interface2_ram_bus_dat_r + connect \Y $and$ls180.v:6033$1259_Y + end + attribute \src "ls180.v:6033.303-6033.363" + cell $and $and$ls180.v:6033$1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \main_interface3_ram_bus_dat_r + connect \Y $and$ls180.v:6033$1261_Y + end + attribute \src "ls180.v:6033.369-6033.441" + cell $and $and$ls180.v:6033$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } + connect \B \main_interface0_converted_interface_dat_r + connect \Y $and$ls180.v:6033$1263_Y + end + attribute \src "ls180.v:6033.447-6033.519" + cell $and $and$ls180.v:6033$1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } + connect \B \main_interface1_converted_interface_dat_r + connect \Y $and$ls180.v:6033$1265_Y + end + attribute \src "ls180.v:6033.525-6033.598" + cell $and $and$ls180.v:6033$1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } + connect \B \main_libresocsim_libresoc_interface0_dat_r + connect \Y $and$ls180.v:6033$1267_Y + end + attribute \src "ls180.v:6033.604-6033.677" + cell $and $and$ls180.v:6033$1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] } + connect \B \main_libresocsim_libresoc_interface1_dat_r + connect \Y $and$ls180.v:6033$1269_Y + end + attribute \src "ls180.v:6033.683-6033.756" + cell $and $and$ls180.v:6033$1271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] } + connect \B \main_libresocsim_libresoc_interface2_dat_r + connect \Y $and$ls180.v:6033$1271_Y + end + attribute \src "ls180.v:6033.762-6033.836" + cell $and $and$ls180.v:6033$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] } + connect \B \main_libresocsim_libresoc_interface3_dat_r + connect \Y $and$ls180.v:6033$1273_Y + end + attribute \src "ls180.v:6033.842-6033.918" + cell $and $and$ls180.v:6033$1275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] } + connect \B \main_socbushandler_converted_interface_dat_r + connect \Y $and$ls180.v:6033$1275_Y + end + attribute \src "ls180.v:6033.924-6033.1001" + cell $and $and$ls180.v:6033$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] } + connect \B \builder_libresocsim_converted_interface_dat_r + connect \Y $and$ls180.v:6033$1277_Y + end + attribute \src "ls180.v:6043.39-6043.92" + cell $and $and$ls180.v:6043$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6043$1281_Y + end + attribute \src "ls180.v:6043.38-6043.142" + cell $and $and$ls180.v:6043$1283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6043$1281_Y + connect \B $eq$ls180.v:6043$1282_Y + connect \Y $and$ls180.v:6043$1283_Y + end + attribute \src "ls180.v:6044.39-6044.95" + cell $and $and$ls180.v:6044$1285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6044$1284_Y + connect \Y $and$ls180.v:6044$1285_Y + end + attribute \src "ls180.v:6044.38-6044.145" + cell $and $and$ls180.v:6044$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6044$1285_Y + connect \B $eq$ls180.v:6044$1286_Y + connect \Y $and$ls180.v:6044$1287_Y + end + attribute \src "ls180.v:6046.41-6046.94" + cell $and $and$ls180.v:6046$1288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6046$1288_Y + end + attribute \src "ls180.v:6046.40-6046.144" + cell $and $and$ls180.v:6046$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6046$1288_Y + connect \B $eq$ls180.v:6046$1289_Y + connect \Y $and$ls180.v:6046$1290_Y + end + attribute \src "ls180.v:6047.41-6047.97" + cell $and $and$ls180.v:6047$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6047$1291_Y + connect \Y $and$ls180.v:6047$1292_Y + end + attribute \src "ls180.v:6047.40-6047.147" + cell $and $and$ls180.v:6047$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6047$1292_Y + connect \B $eq$ls180.v:6047$1293_Y + connect \Y $and$ls180.v:6047$1294_Y + end + attribute \src "ls180.v:6049.41-6049.94" + cell $and $and$ls180.v:6049$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6049$1295_Y + end + attribute \src "ls180.v:6049.40-6049.144" + cell $and $and$ls180.v:6049$1297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6049$1295_Y + connect \B $eq$ls180.v:6049$1296_Y + connect \Y $and$ls180.v:6049$1297_Y + end + attribute \src "ls180.v:6050.41-6050.97" + cell $and $and$ls180.v:6050$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6050$1298_Y + connect \Y $and$ls180.v:6050$1299_Y + end + attribute \src "ls180.v:6050.40-6050.147" + cell $and $and$ls180.v:6050$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6050$1299_Y + connect \B $eq$ls180.v:6050$1300_Y + connect \Y $and$ls180.v:6050$1301_Y + end + attribute \src "ls180.v:6052.41-6052.94" + cell $and $and$ls180.v:6052$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6052$1302_Y + end + attribute \src "ls180.v:6052.40-6052.144" + cell $and $and$ls180.v:6052$1304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6052$1302_Y + connect \B $eq$ls180.v:6052$1303_Y + connect \Y $and$ls180.v:6052$1304_Y + end + attribute \src "ls180.v:6053.41-6053.97" + cell $and $and$ls180.v:6053$1306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6053$1305_Y + connect \Y $and$ls180.v:6053$1306_Y + end + attribute \src "ls180.v:6053.40-6053.147" + cell $and $and$ls180.v:6053$1308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6053$1306_Y + connect \B $eq$ls180.v:6053$1307_Y + connect \Y $and$ls180.v:6053$1308_Y + end + attribute \src "ls180.v:6055.41-6055.94" + cell $and $and$ls180.v:6055$1309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6055$1309_Y + end + attribute \src "ls180.v:6055.40-6055.144" + cell $and $and$ls180.v:6055$1311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6055$1309_Y + connect \B $eq$ls180.v:6055$1310_Y + connect \Y $and$ls180.v:6055$1311_Y + end + attribute \src "ls180.v:6056.41-6056.97" + cell $and $and$ls180.v:6056$1313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6056$1312_Y + connect \Y $and$ls180.v:6056$1313_Y + end + attribute \src "ls180.v:6056.40-6056.147" + cell $and $and$ls180.v:6056$1315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6056$1313_Y + connect \B $eq$ls180.v:6056$1314_Y + connect \Y $and$ls180.v:6056$1315_Y + end + attribute \src "ls180.v:6058.44-6058.97" + cell $and $and$ls180.v:6058$1316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6058$1316_Y + end + attribute \src "ls180.v:6058.43-6058.147" + cell $and $and$ls180.v:6058$1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6058$1316_Y + connect \B $eq$ls180.v:6058$1317_Y + connect \Y $and$ls180.v:6058$1318_Y + end + attribute \src "ls180.v:6059.44-6059.100" + cell $and $and$ls180.v:6059$1320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6059$1319_Y + connect \Y $and$ls180.v:6059$1320_Y + end + attribute \src "ls180.v:6059.43-6059.150" + cell $and $and$ls180.v:6059$1322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6059$1320_Y + connect \B $eq$ls180.v:6059$1321_Y + connect \Y $and$ls180.v:6059$1322_Y + end + attribute \src "ls180.v:6061.44-6061.97" + cell $and $and$ls180.v:6061$1323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6061$1323_Y + end + attribute \src "ls180.v:6061.43-6061.147" + cell $and $and$ls180.v:6061$1325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6061$1323_Y + connect \B $eq$ls180.v:6061$1324_Y + connect \Y $and$ls180.v:6061$1325_Y + end + attribute \src "ls180.v:6062.44-6062.100" + cell $and $and$ls180.v:6062$1327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6062$1326_Y + connect \Y $and$ls180.v:6062$1327_Y + end + attribute \src "ls180.v:6062.43-6062.150" + cell $and $and$ls180.v:6062$1329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6062$1327_Y + connect \B $eq$ls180.v:6062$1328_Y + connect \Y $and$ls180.v:6062$1329_Y + end + attribute \src "ls180.v:6064.44-6064.97" + cell $and $and$ls180.v:6064$1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6064$1330_Y + end + attribute \src "ls180.v:6064.43-6064.147" + cell $and $and$ls180.v:6064$1332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6064$1330_Y + connect \B $eq$ls180.v:6064$1331_Y + connect \Y $and$ls180.v:6064$1332_Y + end + attribute \src "ls180.v:6065.44-6065.100" + cell $and $and$ls180.v:6065$1334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6065$1333_Y + connect \Y $and$ls180.v:6065$1334_Y + end + attribute \src "ls180.v:6065.43-6065.150" + cell $and $and$ls180.v:6065$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6065$1334_Y + connect \B $eq$ls180.v:6065$1335_Y + connect \Y $and$ls180.v:6065$1336_Y + end + attribute \src "ls180.v:6067.44-6067.97" + cell $and $and$ls180.v:6067$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6067$1337_Y + end + attribute \src "ls180.v:6067.43-6067.147" + cell $and $and$ls180.v:6067$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6067$1337_Y + connect \B $eq$ls180.v:6067$1338_Y + connect \Y $and$ls180.v:6067$1339_Y + end + attribute \src "ls180.v:6068.44-6068.100" + cell $and $and$ls180.v:6068$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6068$1340_Y + connect \Y $and$ls180.v:6068$1341_Y + end + attribute \src "ls180.v:6068.43-6068.150" + cell $and $and$ls180.v:6068$1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6068$1341_Y + connect \B $eq$ls180.v:6068$1342_Y + connect \Y $and$ls180.v:6068$1343_Y + end + attribute \src "ls180.v:6081.36-6081.89" + cell $and $and$ls180.v:6081$1345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6081$1345_Y + end + attribute \src "ls180.v:6081.35-6081.139" + cell $and $and$ls180.v:6081$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6081$1345_Y + connect \B $eq$ls180.v:6081$1346_Y + connect \Y $and$ls180.v:6081$1347_Y + end + attribute \src "ls180.v:6082.36-6082.92" + cell $and $and$ls180.v:6082$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6082$1348_Y + connect \Y $and$ls180.v:6082$1349_Y + end + attribute \src "ls180.v:6082.35-6082.142" + cell $and $and$ls180.v:6082$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6082$1349_Y + connect \B $eq$ls180.v:6082$1350_Y + connect \Y $and$ls180.v:6082$1351_Y + end + attribute \src "ls180.v:6084.36-6084.89" + cell $and $and$ls180.v:6084$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6084$1352_Y + end + attribute \src "ls180.v:6084.35-6084.139" + cell $and $and$ls180.v:6084$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6084$1352_Y + connect \B $eq$ls180.v:6084$1353_Y + connect \Y $and$ls180.v:6084$1354_Y + end + attribute \src "ls180.v:6085.36-6085.92" + cell $and $and$ls180.v:6085$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6085$1355_Y + connect \Y $and$ls180.v:6085$1356_Y + end + attribute \src "ls180.v:6085.35-6085.142" + cell $and $and$ls180.v:6085$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6085$1356_Y + connect \B $eq$ls180.v:6085$1357_Y + connect \Y $and$ls180.v:6085$1358_Y + end + attribute \src "ls180.v:6087.36-6087.89" + cell $and $and$ls180.v:6087$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6087$1359_Y + end + attribute \src "ls180.v:6087.35-6087.139" + cell $and $and$ls180.v:6087$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6087$1359_Y + connect \B $eq$ls180.v:6087$1360_Y + connect \Y $and$ls180.v:6087$1361_Y + end + attribute \src "ls180.v:6088.36-6088.92" + cell $and $and$ls180.v:6088$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6088$1362_Y + connect \Y $and$ls180.v:6088$1363_Y + end + attribute \src "ls180.v:6088.35-6088.142" + cell $and $and$ls180.v:6088$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6088$1363_Y + connect \B $eq$ls180.v:6088$1364_Y + connect \Y $and$ls180.v:6088$1365_Y + end + attribute \src "ls180.v:6090.36-6090.89" + cell $and $and$ls180.v:6090$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6090$1366_Y + end + attribute \src "ls180.v:6090.35-6090.139" + cell $and $and$ls180.v:6090$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6090$1366_Y + connect \B $eq$ls180.v:6090$1367_Y + connect \Y $and$ls180.v:6090$1368_Y + end + attribute \src "ls180.v:6091.36-6091.92" + cell $and $and$ls180.v:6091$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6091$1369_Y + connect \Y $and$ls180.v:6091$1370_Y + end + attribute \src "ls180.v:6091.35-6091.142" + cell $and $and$ls180.v:6091$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6091$1370_Y + connect \B $eq$ls180.v:6091$1371_Y + connect \Y $and$ls180.v:6091$1372_Y + end + attribute \src "ls180.v:6093.37-6093.90" + cell $and $and$ls180.v:6093$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6093$1373_Y + end + attribute \src "ls180.v:6093.36-6093.140" + cell $and $and$ls180.v:6093$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6093$1373_Y + connect \B $eq$ls180.v:6093$1374_Y + connect \Y $and$ls180.v:6093$1375_Y + end + attribute \src "ls180.v:6094.37-6094.93" + cell $and $and$ls180.v:6094$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6094$1376_Y + connect \Y $and$ls180.v:6094$1377_Y + end + attribute \src "ls180.v:6094.36-6094.143" + cell $and $and$ls180.v:6094$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6094$1377_Y + connect \B $eq$ls180.v:6094$1378_Y + connect \Y $and$ls180.v:6094$1379_Y + end + attribute \src "ls180.v:6096.37-6096.90" + cell $and $and$ls180.v:6096$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6096$1380_Y + end + attribute \src "ls180.v:6096.36-6096.140" + cell $and $and$ls180.v:6096$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6096$1380_Y + connect \B $eq$ls180.v:6096$1381_Y + connect \Y $and$ls180.v:6096$1382_Y + end + attribute \src "ls180.v:6097.37-6097.93" + cell $and $and$ls180.v:6097$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6097$1383_Y + connect \Y $and$ls180.v:6097$1384_Y + end + attribute \src "ls180.v:6097.36-6097.143" + cell $and $and$ls180.v:6097$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6097$1384_Y + connect \B $eq$ls180.v:6097$1385_Y + connect \Y $and$ls180.v:6097$1386_Y + end + attribute \src "ls180.v:6107.35-6107.88" + cell $and $and$ls180.v:6107$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:6107$1388_Y + end + attribute \src "ls180.v:6107.34-6107.136" + cell $and $and$ls180.v:6107$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6107$1388_Y + connect \B $eq$ls180.v:6107$1389_Y + connect \Y $and$ls180.v:6107$1390_Y + end + attribute \src "ls180.v:6108.35-6108.91" + cell $and $and$ls180.v:6108$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:6108$1391_Y + connect \Y $and$ls180.v:6108$1392_Y + end + attribute \src "ls180.v:6108.34-6108.139" + cell $and $and$ls180.v:6108$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6108$1392_Y + connect \B $eq$ls180.v:6108$1393_Y + connect \Y $and$ls180.v:6108$1394_Y + end + attribute \src "ls180.v:6110.34-6110.87" + cell $and $and$ls180.v:6110$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:6110$1395_Y + end + attribute \src "ls180.v:6110.33-6110.135" + cell $and $and$ls180.v:6110$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6110$1395_Y + connect \B $eq$ls180.v:6110$1396_Y + connect \Y $and$ls180.v:6110$1397_Y + end + attribute \src "ls180.v:6111.34-6111.90" + cell $and $and$ls180.v:6111$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:6111$1398_Y + connect \Y $and$ls180.v:6111$1399_Y + end + attribute \src "ls180.v:6111.33-6111.138" + cell $and $and$ls180.v:6111$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6111$1399_Y + connect \B $eq$ls180.v:6111$1400_Y + connect \Y $and$ls180.v:6111$1401_Y + end + attribute \src "ls180.v:6121.40-6121.93" + cell $and $and$ls180.v:6121$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6121$1403_Y + end + attribute \src "ls180.v:6121.39-6121.143" + cell $and $and$ls180.v:6121$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6121$1403_Y + connect \B $eq$ls180.v:6121$1404_Y + connect \Y $and$ls180.v:6121$1405_Y + end + attribute \src "ls180.v:6122.40-6122.96" + cell $and $and$ls180.v:6122$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6122$1406_Y + connect \Y $and$ls180.v:6122$1407_Y + end + attribute \src "ls180.v:6122.39-6122.146" + cell $and $and$ls180.v:6122$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6122$1407_Y + connect \B $eq$ls180.v:6122$1408_Y + connect \Y $and$ls180.v:6122$1409_Y + end + attribute \src "ls180.v:6124.39-6124.92" + cell $and $and$ls180.v:6124$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6124$1410_Y + end + attribute \src "ls180.v:6124.38-6124.142" + cell $and $and$ls180.v:6124$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6124$1410_Y + connect \B $eq$ls180.v:6124$1411_Y + connect \Y $and$ls180.v:6124$1412_Y + end + attribute \src "ls180.v:6125.39-6125.95" + cell $and $and$ls180.v:6125$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6125$1413_Y + connect \Y $and$ls180.v:6125$1414_Y + end + attribute \src "ls180.v:6125.38-6125.145" + cell $and $and$ls180.v:6125$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6125$1414_Y + connect \B $eq$ls180.v:6125$1415_Y + connect \Y $and$ls180.v:6125$1416_Y + end + attribute \src "ls180.v:6127.39-6127.92" + cell $and $and$ls180.v:6127$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6127$1417_Y + end + attribute \src "ls180.v:6127.38-6127.142" + cell $and $and$ls180.v:6127$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6127$1417_Y + connect \B $eq$ls180.v:6127$1418_Y + connect \Y $and$ls180.v:6127$1419_Y + end + attribute \src "ls180.v:6128.39-6128.95" + cell $and $and$ls180.v:6128$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6128$1420_Y + connect \Y $and$ls180.v:6128$1421_Y + end + attribute \src "ls180.v:6128.38-6128.145" + cell $and $and$ls180.v:6128$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6128$1421_Y + connect \B $eq$ls180.v:6128$1422_Y + connect \Y $and$ls180.v:6128$1423_Y + end + attribute \src "ls180.v:6130.39-6130.92" + cell $and $and$ls180.v:6130$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6130$1424_Y + end + attribute \src "ls180.v:6130.38-6130.142" + cell $and $and$ls180.v:6130$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6130$1424_Y + connect \B $eq$ls180.v:6130$1425_Y + connect \Y $and$ls180.v:6130$1426_Y + end + attribute \src "ls180.v:6131.39-6131.95" + cell $and $and$ls180.v:6131$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6131$1427_Y + connect \Y $and$ls180.v:6131$1428_Y + end + attribute \src "ls180.v:6131.38-6131.145" + cell $and $and$ls180.v:6131$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6131$1428_Y + connect \B $eq$ls180.v:6131$1429_Y + connect \Y $and$ls180.v:6131$1430_Y + end + attribute \src "ls180.v:6133.39-6133.92" + cell $and $and$ls180.v:6133$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6133$1431_Y + end + attribute \src "ls180.v:6133.38-6133.142" + cell $and $and$ls180.v:6133$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6133$1431_Y + connect \B $eq$ls180.v:6133$1432_Y + connect \Y $and$ls180.v:6133$1433_Y + end + attribute \src "ls180.v:6134.39-6134.95" + cell $and $and$ls180.v:6134$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6134$1434_Y + connect \Y $and$ls180.v:6134$1435_Y + end + attribute \src "ls180.v:6134.38-6134.145" + cell $and $and$ls180.v:6134$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6134$1435_Y + connect \B $eq$ls180.v:6134$1436_Y + connect \Y $and$ls180.v:6134$1437_Y + end + attribute \src "ls180.v:6136.40-6136.93" + cell $and $and$ls180.v:6136$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6136$1438_Y + end + attribute \src "ls180.v:6136.39-6136.143" + cell $and $and$ls180.v:6136$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6136$1438_Y + connect \B $eq$ls180.v:6136$1439_Y + connect \Y $and$ls180.v:6136$1440_Y + end + attribute \src "ls180.v:6137.40-6137.96" + cell $and $and$ls180.v:6137$1442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6137$1441_Y + connect \Y $and$ls180.v:6137$1442_Y + end + attribute \src "ls180.v:6137.39-6137.146" + cell $and $and$ls180.v:6137$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6137$1442_Y + connect \B $eq$ls180.v:6137$1443_Y + connect \Y $and$ls180.v:6137$1444_Y + end + attribute \src "ls180.v:6139.40-6139.93" + cell $and $and$ls180.v:6139$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6139$1445_Y + end + attribute \src "ls180.v:6139.39-6139.143" + cell $and $and$ls180.v:6139$1447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6139$1445_Y + connect \B $eq$ls180.v:6139$1446_Y + connect \Y $and$ls180.v:6139$1447_Y + end + attribute \src "ls180.v:6140.40-6140.96" + cell $and $and$ls180.v:6140$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6140$1448_Y + connect \Y $and$ls180.v:6140$1449_Y + end + attribute \src "ls180.v:6140.39-6140.146" + cell $and $and$ls180.v:6140$1451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6140$1449_Y + connect \B $eq$ls180.v:6140$1450_Y + connect \Y $and$ls180.v:6140$1451_Y + end + attribute \src "ls180.v:6142.40-6142.93" + cell $and $and$ls180.v:6142$1452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6142$1452_Y + end + attribute \src "ls180.v:6142.39-6142.143" + cell $and $and$ls180.v:6142$1454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6142$1452_Y + connect \B $eq$ls180.v:6142$1453_Y + connect \Y $and$ls180.v:6142$1454_Y + end + attribute \src "ls180.v:6143.40-6143.96" + cell $and $and$ls180.v:6143$1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6143$1455_Y + connect \Y $and$ls180.v:6143$1456_Y + end + attribute \src "ls180.v:6143.39-6143.146" + cell $and $and$ls180.v:6143$1458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6143$1456_Y + connect \B $eq$ls180.v:6143$1457_Y + connect \Y $and$ls180.v:6143$1458_Y + end + attribute \src "ls180.v:6145.40-6145.93" + cell $and $and$ls180.v:6145$1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6145$1459_Y + end + attribute \src "ls180.v:6145.39-6145.143" + cell $and $and$ls180.v:6145$1461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6145$1459_Y + connect \B $eq$ls180.v:6145$1460_Y + connect \Y $and$ls180.v:6145$1461_Y + end + attribute \src "ls180.v:6146.40-6146.96" + cell $and $and$ls180.v:6146$1463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6146$1462_Y + connect \Y $and$ls180.v:6146$1463_Y + end + attribute \src "ls180.v:6146.39-6146.146" + cell $and $and$ls180.v:6146$1465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6146$1463_Y + connect \B $eq$ls180.v:6146$1464_Y + connect \Y $and$ls180.v:6146$1465_Y + end + attribute \src "ls180.v:6158.40-6158.93" + cell $and $and$ls180.v:6158$1467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6158$1467_Y + end + attribute \src "ls180.v:6158.39-6158.143" + cell $and $and$ls180.v:6158$1469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6158$1467_Y + connect \B $eq$ls180.v:6158$1468_Y + connect \Y $and$ls180.v:6158$1469_Y + end + attribute \src "ls180.v:6159.40-6159.96" + cell $and $and$ls180.v:6159$1471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6159$1470_Y + connect \Y $and$ls180.v:6159$1471_Y + end + attribute \src "ls180.v:6159.39-6159.146" + cell $and $and$ls180.v:6159$1473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6159$1471_Y + connect \B $eq$ls180.v:6159$1472_Y + connect \Y $and$ls180.v:6159$1473_Y + end + attribute \src "ls180.v:6161.39-6161.92" + cell $and $and$ls180.v:6161$1474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6161$1474_Y + end + attribute \src "ls180.v:6161.38-6161.142" + cell $and $and$ls180.v:6161$1476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6161$1474_Y + connect \B $eq$ls180.v:6161$1475_Y + connect \Y $and$ls180.v:6161$1476_Y + end + attribute \src "ls180.v:6162.39-6162.95" + cell $and $and$ls180.v:6162$1478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6162$1477_Y + connect \Y $and$ls180.v:6162$1478_Y + end + attribute \src "ls180.v:6162.38-6162.145" + cell $and $and$ls180.v:6162$1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6162$1478_Y + connect \B $eq$ls180.v:6162$1479_Y + connect \Y $and$ls180.v:6162$1480_Y + end + attribute \src "ls180.v:6164.39-6164.92" + cell $and $and$ls180.v:6164$1481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6164$1481_Y + end + attribute \src "ls180.v:6164.38-6164.142" + cell $and $and$ls180.v:6164$1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6164$1481_Y + connect \B $eq$ls180.v:6164$1482_Y + connect \Y $and$ls180.v:6164$1483_Y + end + attribute \src "ls180.v:6165.39-6165.95" + cell $and $and$ls180.v:6165$1485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6165$1484_Y + connect \Y $and$ls180.v:6165$1485_Y + end + attribute \src "ls180.v:6165.38-6165.145" + cell $and $and$ls180.v:6165$1487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6165$1485_Y + connect \B $eq$ls180.v:6165$1486_Y + connect \Y $and$ls180.v:6165$1487_Y + end + attribute \src "ls180.v:6167.39-6167.92" + cell $and $and$ls180.v:6167$1488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6167$1488_Y + end + attribute \src "ls180.v:6167.38-6167.142" + cell $and $and$ls180.v:6167$1490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6167$1488_Y + connect \B $eq$ls180.v:6167$1489_Y + connect \Y $and$ls180.v:6167$1490_Y + end + attribute \src "ls180.v:6168.39-6168.95" + cell $and $and$ls180.v:6168$1492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6168$1491_Y + connect \Y $and$ls180.v:6168$1492_Y + end + attribute \src "ls180.v:6168.38-6168.145" + cell $and $and$ls180.v:6168$1494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6168$1492_Y + connect \B $eq$ls180.v:6168$1493_Y + connect \Y $and$ls180.v:6168$1494_Y + end + attribute \src "ls180.v:6170.39-6170.92" + cell $and $and$ls180.v:6170$1495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6170$1495_Y + end + attribute \src "ls180.v:6170.38-6170.142" + cell $and $and$ls180.v:6170$1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6170$1495_Y + connect \B $eq$ls180.v:6170$1496_Y + connect \Y $and$ls180.v:6170$1497_Y + end + attribute \src "ls180.v:6171.39-6171.95" + cell $and $and$ls180.v:6171$1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6171$1498_Y + connect \Y $and$ls180.v:6171$1499_Y + end + attribute \src "ls180.v:6171.38-6171.145" + cell $and $and$ls180.v:6171$1501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6171$1499_Y + connect \B $eq$ls180.v:6171$1500_Y + connect \Y $and$ls180.v:6171$1501_Y + end + attribute \src "ls180.v:6173.40-6173.93" + cell $and $and$ls180.v:6173$1502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6173$1502_Y + end + attribute \src "ls180.v:6173.39-6173.143" + cell $and $and$ls180.v:6173$1504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6173$1502_Y + connect \B $eq$ls180.v:6173$1503_Y + connect \Y $and$ls180.v:6173$1504_Y + end + attribute \src "ls180.v:6174.40-6174.96" + cell $and $and$ls180.v:6174$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6174$1505_Y + connect \Y $and$ls180.v:6174$1506_Y + end + attribute \src "ls180.v:6174.39-6174.146" + cell $and $and$ls180.v:6174$1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6174$1506_Y + connect \B $eq$ls180.v:6174$1507_Y + connect \Y $and$ls180.v:6174$1508_Y + end + attribute \src "ls180.v:6176.40-6176.93" + cell $and $and$ls180.v:6176$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6176$1509_Y + end + attribute \src "ls180.v:6176.39-6176.143" + cell $and $and$ls180.v:6176$1511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6176$1509_Y + connect \B $eq$ls180.v:6176$1510_Y + connect \Y $and$ls180.v:6176$1511_Y + end + attribute \src "ls180.v:6177.40-6177.96" + cell $and $and$ls180.v:6177$1513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6177$1512_Y + connect \Y $and$ls180.v:6177$1513_Y + end + attribute \src "ls180.v:6177.39-6177.146" + cell $and $and$ls180.v:6177$1515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6177$1513_Y + connect \B $eq$ls180.v:6177$1514_Y + connect \Y $and$ls180.v:6177$1515_Y + end + attribute \src "ls180.v:6179.40-6179.93" + cell $and $and$ls180.v:6179$1516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6179$1516_Y + end + attribute \src "ls180.v:6179.39-6179.143" + cell $and $and$ls180.v:6179$1518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6179$1516_Y + connect \B $eq$ls180.v:6179$1517_Y + connect \Y $and$ls180.v:6179$1518_Y + end + attribute \src "ls180.v:6180.40-6180.96" + cell $and $and$ls180.v:6180$1520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6180$1519_Y + connect \Y $and$ls180.v:6180$1520_Y + end + attribute \src "ls180.v:6180.39-6180.146" + cell $and $and$ls180.v:6180$1522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6180$1520_Y + connect \B $eq$ls180.v:6180$1521_Y + connect \Y $and$ls180.v:6180$1522_Y + end + attribute \src "ls180.v:6182.40-6182.93" + cell $and $and$ls180.v:6182$1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6182$1523_Y + end + attribute \src "ls180.v:6182.39-6182.143" + cell $and $and$ls180.v:6182$1525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6182$1523_Y + connect \B $eq$ls180.v:6182$1524_Y + connect \Y $and$ls180.v:6182$1525_Y + end + attribute \src "ls180.v:6183.40-6183.96" + cell $and $and$ls180.v:6183$1527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6183$1526_Y + connect \Y $and$ls180.v:6183$1527_Y + end + attribute \src "ls180.v:6183.39-6183.146" + cell $and $and$ls180.v:6183$1529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6183$1527_Y + connect \B $eq$ls180.v:6183$1528_Y + connect \Y $and$ls180.v:6183$1529_Y + end + attribute \src "ls180.v:6195.42-6195.95" + cell $and $and$ls180.v:6195$1531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6195$1531_Y + end + attribute \src "ls180.v:6195.41-6195.145" + cell $and $and$ls180.v:6195$1533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6195$1531_Y + connect \B $eq$ls180.v:6195$1532_Y + connect \Y $and$ls180.v:6195$1533_Y + end + attribute \src "ls180.v:6196.42-6196.98" + cell $and $and$ls180.v:6196$1535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6196$1534_Y + connect \Y $and$ls180.v:6196$1535_Y + end + attribute \src "ls180.v:6196.41-6196.148" + cell $and $and$ls180.v:6196$1537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6196$1535_Y + connect \B $eq$ls180.v:6196$1536_Y + connect \Y $and$ls180.v:6196$1537_Y + end + attribute \src "ls180.v:6198.42-6198.95" + cell $and $and$ls180.v:6198$1538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6198$1538_Y + end + attribute \src "ls180.v:6198.41-6198.145" + cell $and $and$ls180.v:6198$1540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6198$1538_Y + connect \B $eq$ls180.v:6198$1539_Y + connect \Y $and$ls180.v:6198$1540_Y + end + attribute \src "ls180.v:6199.42-6199.98" + cell $and $and$ls180.v:6199$1542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6199$1541_Y + connect \Y $and$ls180.v:6199$1542_Y + end + attribute \src "ls180.v:6199.41-6199.148" + cell $and $and$ls180.v:6199$1544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6199$1542_Y + connect \B $eq$ls180.v:6199$1543_Y + connect \Y $and$ls180.v:6199$1544_Y + end + attribute \src "ls180.v:6201.42-6201.95" + cell $and $and$ls180.v:6201$1545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6201$1545_Y + end + attribute \src "ls180.v:6201.41-6201.145" + cell $and $and$ls180.v:6201$1547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6201$1545_Y + connect \B $eq$ls180.v:6201$1546_Y + connect \Y $and$ls180.v:6201$1547_Y + end + attribute \src "ls180.v:6202.42-6202.98" + cell $and $and$ls180.v:6202$1549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6202$1548_Y + connect \Y $and$ls180.v:6202$1549_Y + end + attribute \src "ls180.v:6202.41-6202.148" + cell $and $and$ls180.v:6202$1551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6202$1549_Y + connect \B $eq$ls180.v:6202$1550_Y + connect \Y $and$ls180.v:6202$1551_Y + end + attribute \src "ls180.v:6204.42-6204.95" + cell $and $and$ls180.v:6204$1552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6204$1552_Y + end + attribute \src "ls180.v:6204.41-6204.145" + cell $and $and$ls180.v:6204$1554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6204$1552_Y + connect \B $eq$ls180.v:6204$1553_Y + connect \Y $and$ls180.v:6204$1554_Y + end + attribute \src "ls180.v:6205.42-6205.98" + cell $and $and$ls180.v:6205$1556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6205$1555_Y + connect \Y $and$ls180.v:6205$1556_Y + end + attribute \src "ls180.v:6205.41-6205.148" + cell $and $and$ls180.v:6205$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6205$1556_Y + connect \B $eq$ls180.v:6205$1557_Y + connect \Y $and$ls180.v:6205$1558_Y + end + attribute \src "ls180.v:6207.42-6207.95" + cell $and $and$ls180.v:6207$1559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6207$1559_Y + end + attribute \src "ls180.v:6207.41-6207.145" + cell $and $and$ls180.v:6207$1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6207$1559_Y + connect \B $eq$ls180.v:6207$1560_Y + connect \Y $and$ls180.v:6207$1561_Y + end + attribute \src "ls180.v:6208.42-6208.98" + cell $and $and$ls180.v:6208$1563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6208$1562_Y + connect \Y $and$ls180.v:6208$1563_Y + end + attribute \src "ls180.v:6208.41-6208.148" + cell $and $and$ls180.v:6208$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6208$1563_Y + connect \B $eq$ls180.v:6208$1564_Y + connect \Y $and$ls180.v:6208$1565_Y + end + attribute \src "ls180.v:6210.42-6210.95" + cell $and $and$ls180.v:6210$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6210$1566_Y + end + attribute \src "ls180.v:6210.41-6210.145" + cell $and $and$ls180.v:6210$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6210$1566_Y + connect \B $eq$ls180.v:6210$1567_Y + connect \Y $and$ls180.v:6210$1568_Y + end + attribute \src "ls180.v:6211.42-6211.98" + cell $and $and$ls180.v:6211$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6211$1569_Y + connect \Y $and$ls180.v:6211$1570_Y + end + attribute \src "ls180.v:6211.41-6211.148" + cell $and $and$ls180.v:6211$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6211$1570_Y + connect \B $eq$ls180.v:6211$1571_Y + connect \Y $and$ls180.v:6211$1572_Y + end + attribute \src "ls180.v:6213.42-6213.95" + cell $and $and$ls180.v:6213$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6213$1573_Y + end + attribute \src "ls180.v:6213.41-6213.145" + cell $and $and$ls180.v:6213$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6213$1573_Y + connect \B $eq$ls180.v:6213$1574_Y + connect \Y $and$ls180.v:6213$1575_Y + end + attribute \src "ls180.v:6214.42-6214.98" + cell $and $and$ls180.v:6214$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6214$1576_Y + connect \Y $and$ls180.v:6214$1577_Y + end + attribute \src "ls180.v:6214.41-6214.148" + cell $and $and$ls180.v:6214$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6214$1577_Y + connect \B $eq$ls180.v:6214$1578_Y + connect \Y $and$ls180.v:6214$1579_Y + end + attribute \src "ls180.v:6216.42-6216.95" + cell $and $and$ls180.v:6216$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6216$1580_Y + end + attribute \src "ls180.v:6216.41-6216.145" + cell $and $and$ls180.v:6216$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6216$1580_Y + connect \B $eq$ls180.v:6216$1581_Y + connect \Y $and$ls180.v:6216$1582_Y + end + attribute \src "ls180.v:6217.42-6217.98" + cell $and $and$ls180.v:6217$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6217$1583_Y + connect \Y $and$ls180.v:6217$1584_Y + end + attribute \src "ls180.v:6217.41-6217.148" + cell $and $and$ls180.v:6217$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6217$1584_Y + connect \B $eq$ls180.v:6217$1585_Y + connect \Y $and$ls180.v:6217$1586_Y + end + attribute \src "ls180.v:6219.44-6219.97" + cell $and $and$ls180.v:6219$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6219$1587_Y + end + attribute \src "ls180.v:6219.43-6219.147" + cell $and $and$ls180.v:6219$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6219$1587_Y + connect \B $eq$ls180.v:6219$1588_Y + connect \Y $and$ls180.v:6219$1589_Y + end + attribute \src "ls180.v:6220.44-6220.100" + cell $and $and$ls180.v:6220$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6220$1590_Y + connect \Y $and$ls180.v:6220$1591_Y + end + attribute \src "ls180.v:6220.43-6220.150" + cell $and $and$ls180.v:6220$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6220$1591_Y + connect \B $eq$ls180.v:6220$1592_Y + connect \Y $and$ls180.v:6220$1593_Y + end + attribute \src "ls180.v:6222.44-6222.97" + cell $and $and$ls180.v:6222$1594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6222$1594_Y + end + attribute \src "ls180.v:6222.43-6222.147" + cell $and $and$ls180.v:6222$1596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6222$1594_Y + connect \B $eq$ls180.v:6222$1595_Y + connect \Y $and$ls180.v:6222$1596_Y + end + attribute \src "ls180.v:6223.44-6223.100" + cell $and $and$ls180.v:6223$1598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6223$1597_Y + connect \Y $and$ls180.v:6223$1598_Y + end + attribute \src "ls180.v:6223.43-6223.150" + cell $and $and$ls180.v:6223$1600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6223$1598_Y + connect \B $eq$ls180.v:6223$1599_Y + connect \Y $and$ls180.v:6223$1600_Y + end + attribute \src "ls180.v:6225.44-6225.97" + cell $and $and$ls180.v:6225$1601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6225$1601_Y + end + attribute \src "ls180.v:6225.43-6225.148" + cell $and $and$ls180.v:6225$1603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6225$1601_Y + connect \B $eq$ls180.v:6225$1602_Y + connect \Y $and$ls180.v:6225$1603_Y + end + attribute \src "ls180.v:6226.44-6226.100" + cell $and $and$ls180.v:6226$1605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6226$1604_Y + connect \Y $and$ls180.v:6226$1605_Y + end + attribute \src "ls180.v:6226.43-6226.151" + cell $and $and$ls180.v:6226$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6226$1605_Y + connect \B $eq$ls180.v:6226$1606_Y + connect \Y $and$ls180.v:6226$1607_Y + end + attribute \src "ls180.v:6228.44-6228.97" + cell $and $and$ls180.v:6228$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6228$1608_Y + end + attribute \src "ls180.v:6228.43-6228.148" + cell $and $and$ls180.v:6228$1610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6228$1608_Y + connect \B $eq$ls180.v:6228$1609_Y + connect \Y $and$ls180.v:6228$1610_Y + end + attribute \src "ls180.v:6229.44-6229.100" + cell $and $and$ls180.v:6229$1612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6229$1611_Y + connect \Y $and$ls180.v:6229$1612_Y + end + attribute \src "ls180.v:6229.43-6229.151" + cell $and $and$ls180.v:6229$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6229$1612_Y + connect \B $eq$ls180.v:6229$1613_Y + connect \Y $and$ls180.v:6229$1614_Y + end + attribute \src "ls180.v:6231.44-6231.97" + cell $and $and$ls180.v:6231$1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6231$1615_Y + end + attribute \src "ls180.v:6231.43-6231.148" + cell $and $and$ls180.v:6231$1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6231$1615_Y + connect \B $eq$ls180.v:6231$1616_Y + connect \Y $and$ls180.v:6231$1617_Y + end + attribute \src "ls180.v:6232.44-6232.100" + cell $and $and$ls180.v:6232$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6232$1618_Y + connect \Y $and$ls180.v:6232$1619_Y + end + attribute \src "ls180.v:6232.43-6232.151" + cell $and $and$ls180.v:6232$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6232$1619_Y + connect \B $eq$ls180.v:6232$1620_Y + connect \Y $and$ls180.v:6232$1621_Y + end + attribute \src "ls180.v:6234.41-6234.94" + cell $and $and$ls180.v:6234$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6234$1622_Y + end + attribute \src "ls180.v:6234.40-6234.145" + cell $and $and$ls180.v:6234$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6234$1622_Y + connect \B $eq$ls180.v:6234$1623_Y + connect \Y $and$ls180.v:6234$1624_Y + end + attribute \src "ls180.v:6235.41-6235.97" + cell $and $and$ls180.v:6235$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6235$1625_Y + connect \Y $and$ls180.v:6235$1626_Y + end + attribute \src "ls180.v:6235.40-6235.148" + cell $and $and$ls180.v:6235$1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6235$1626_Y + connect \B $eq$ls180.v:6235$1627_Y + connect \Y $and$ls180.v:6235$1628_Y + end + attribute \src "ls180.v:6237.42-6237.95" + cell $and $and$ls180.v:6237$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6237$1629_Y + end + attribute \src "ls180.v:6237.41-6237.146" + cell $and $and$ls180.v:6237$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6237$1629_Y + connect \B $eq$ls180.v:6237$1630_Y + connect \Y $and$ls180.v:6237$1631_Y + end + attribute \src "ls180.v:6238.42-6238.98" + cell $and $and$ls180.v:6238$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6238$1632_Y + connect \Y $and$ls180.v:6238$1633_Y + end + attribute \src "ls180.v:6238.41-6238.149" + cell $and $and$ls180.v:6238$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6238$1633_Y + connect \B $eq$ls180.v:6238$1634_Y + connect \Y $and$ls180.v:6238$1635_Y + end + attribute \src "ls180.v:6257.46-6257.99" + cell $and $and$ls180.v:6257$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6257$1637_Y + end + attribute \src "ls180.v:6257.45-6257.149" + cell $and $and$ls180.v:6257$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6257$1637_Y + connect \B $eq$ls180.v:6257$1638_Y + connect \Y $and$ls180.v:6257$1639_Y + end + attribute \src "ls180.v:6258.46-6258.102" + cell $and $and$ls180.v:6258$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6258$1640_Y + connect \Y $and$ls180.v:6258$1641_Y + end + attribute \src "ls180.v:6258.45-6258.152" + cell $and $and$ls180.v:6258$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6258$1641_Y + connect \B $eq$ls180.v:6258$1642_Y + connect \Y $and$ls180.v:6258$1643_Y + end + attribute \src "ls180.v:6260.46-6260.99" + cell $and $and$ls180.v:6260$1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6260$1644_Y + end + attribute \src "ls180.v:6260.45-6260.149" + cell $and $and$ls180.v:6260$1646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6260$1644_Y + connect \B $eq$ls180.v:6260$1645_Y + connect \Y $and$ls180.v:6260$1646_Y + end + attribute \src "ls180.v:6261.46-6261.102" + cell $and $and$ls180.v:6261$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6261$1647_Y + connect \Y $and$ls180.v:6261$1648_Y + end + attribute \src "ls180.v:6261.45-6261.152" + cell $and $and$ls180.v:6261$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6261$1648_Y + connect \B $eq$ls180.v:6261$1649_Y + connect \Y $and$ls180.v:6261$1650_Y + end + attribute \src "ls180.v:6263.46-6263.99" + cell $and $and$ls180.v:6263$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6263$1651_Y + end + attribute \src "ls180.v:6263.45-6263.149" + cell $and $and$ls180.v:6263$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6263$1651_Y + connect \B $eq$ls180.v:6263$1652_Y + connect \Y $and$ls180.v:6263$1653_Y + end + attribute \src "ls180.v:6264.46-6264.102" + cell $and $and$ls180.v:6264$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6264$1654_Y + connect \Y $and$ls180.v:6264$1655_Y + end + attribute \src "ls180.v:6264.45-6264.152" + cell $and $and$ls180.v:6264$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6264$1655_Y + connect \B $eq$ls180.v:6264$1656_Y + connect \Y $and$ls180.v:6264$1657_Y + end + attribute \src "ls180.v:6266.46-6266.99" + cell $and $and$ls180.v:6266$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6266$1658_Y + end + attribute \src "ls180.v:6266.45-6266.149" + cell $and $and$ls180.v:6266$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6266$1658_Y + connect \B $eq$ls180.v:6266$1659_Y + connect \Y $and$ls180.v:6266$1660_Y + end + attribute \src "ls180.v:6267.46-6267.102" + cell $and $and$ls180.v:6267$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6267$1661_Y + connect \Y $and$ls180.v:6267$1662_Y + end + attribute \src "ls180.v:6267.45-6267.152" + cell $and $and$ls180.v:6267$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6267$1662_Y + connect \B $eq$ls180.v:6267$1663_Y + connect \Y $and$ls180.v:6267$1664_Y + end + attribute \src "ls180.v:6269.45-6269.98" + cell $and $and$ls180.v:6269$1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6269$1665_Y + end + attribute \src "ls180.v:6269.44-6269.148" + cell $and $and$ls180.v:6269$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6269$1665_Y + connect \B $eq$ls180.v:6269$1666_Y + connect \Y $and$ls180.v:6269$1667_Y + end + attribute \src "ls180.v:6270.45-6270.101" + cell $and $and$ls180.v:6270$1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6270$1668_Y + connect \Y $and$ls180.v:6270$1669_Y + end + attribute \src "ls180.v:6270.44-6270.151" + cell $and $and$ls180.v:6270$1671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6270$1669_Y + connect \B $eq$ls180.v:6270$1670_Y + connect \Y $and$ls180.v:6270$1671_Y + end + attribute \src "ls180.v:6272.45-6272.98" + cell $and $and$ls180.v:6272$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6272$1672_Y + end + attribute \src "ls180.v:6272.44-6272.148" + cell $and $and$ls180.v:6272$1674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6272$1672_Y + connect \B $eq$ls180.v:6272$1673_Y + connect \Y $and$ls180.v:6272$1674_Y + end + attribute \src "ls180.v:6273.45-6273.101" + cell $and $and$ls180.v:6273$1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6273$1675_Y + connect \Y $and$ls180.v:6273$1676_Y + end + attribute \src "ls180.v:6273.44-6273.151" + cell $and $and$ls180.v:6273$1678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6273$1676_Y + connect \B $eq$ls180.v:6273$1677_Y + connect \Y $and$ls180.v:6273$1678_Y + end + attribute \src "ls180.v:6275.45-6275.98" + cell $and $and$ls180.v:6275$1679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6275$1679_Y + end + attribute \src "ls180.v:6275.44-6275.148" + cell $and $and$ls180.v:6275$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6275$1679_Y + connect \B $eq$ls180.v:6275$1680_Y + connect \Y $and$ls180.v:6275$1681_Y + end + attribute \src "ls180.v:6276.45-6276.101" + cell $and $and$ls180.v:6276$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6276$1682_Y + connect \Y $and$ls180.v:6276$1683_Y + end + attribute \src "ls180.v:6276.44-6276.151" + cell $and $and$ls180.v:6276$1685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6276$1683_Y + connect \B $eq$ls180.v:6276$1684_Y + connect \Y $and$ls180.v:6276$1685_Y + end + attribute \src "ls180.v:6278.45-6278.98" + cell $and $and$ls180.v:6278$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6278$1686_Y + end + attribute \src "ls180.v:6278.44-6278.148" + cell $and $and$ls180.v:6278$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6278$1686_Y + connect \B $eq$ls180.v:6278$1687_Y + connect \Y $and$ls180.v:6278$1688_Y + end + attribute \src "ls180.v:6279.45-6279.101" + cell $and $and$ls180.v:6279$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6279$1689_Y + connect \Y $and$ls180.v:6279$1690_Y + end + attribute \src "ls180.v:6279.44-6279.151" + cell $and $and$ls180.v:6279$1692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6279$1690_Y + connect \B $eq$ls180.v:6279$1691_Y + connect \Y $and$ls180.v:6279$1692_Y + end + attribute \src "ls180.v:6281.36-6281.89" + cell $and $and$ls180.v:6281$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6281$1693_Y + end + attribute \src "ls180.v:6281.35-6281.139" + cell $and $and$ls180.v:6281$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6281$1693_Y + connect \B $eq$ls180.v:6281$1694_Y + connect \Y $and$ls180.v:6281$1695_Y + end + attribute \src "ls180.v:6282.36-6282.92" + cell $and $and$ls180.v:6282$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6282$1696_Y + connect \Y $and$ls180.v:6282$1697_Y + end + attribute \src "ls180.v:6282.35-6282.142" + cell $and $and$ls180.v:6282$1699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6282$1697_Y + connect \B $eq$ls180.v:6282$1698_Y + connect \Y $and$ls180.v:6282$1699_Y + end + attribute \src "ls180.v:6284.47-6284.100" + cell $and $and$ls180.v:6284$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6284$1700_Y + end + attribute \src "ls180.v:6284.46-6284.150" + cell $and $and$ls180.v:6284$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6284$1700_Y + connect \B $eq$ls180.v:6284$1701_Y + connect \Y $and$ls180.v:6284$1702_Y + end + attribute \src "ls180.v:6285.47-6285.103" + cell $and $and$ls180.v:6285$1704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6285$1703_Y + connect \Y $and$ls180.v:6285$1704_Y + end + attribute \src "ls180.v:6285.46-6285.153" + cell $and $and$ls180.v:6285$1706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6285$1704_Y + connect \B $eq$ls180.v:6285$1705_Y + connect \Y $and$ls180.v:6285$1706_Y + end + attribute \src "ls180.v:6287.47-6287.100" + cell $and $and$ls180.v:6287$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6287$1707_Y + end + attribute \src "ls180.v:6287.46-6287.151" + cell $and $and$ls180.v:6287$1709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6287$1707_Y + connect \B $eq$ls180.v:6287$1708_Y + connect \Y $and$ls180.v:6287$1709_Y + end + attribute \src "ls180.v:6288.47-6288.103" + cell $and $and$ls180.v:6288$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6288$1710_Y + connect \Y $and$ls180.v:6288$1711_Y + end + attribute \src "ls180.v:6288.46-6288.154" + cell $and $and$ls180.v:6288$1713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6288$1711_Y + connect \B $eq$ls180.v:6288$1712_Y + connect \Y $and$ls180.v:6288$1713_Y + end + attribute \src "ls180.v:6290.47-6290.100" + cell $and $and$ls180.v:6290$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6290$1714_Y + end + attribute \src "ls180.v:6290.46-6290.151" + cell $and $and$ls180.v:6290$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6290$1714_Y + connect \B $eq$ls180.v:6290$1715_Y + connect \Y $and$ls180.v:6290$1716_Y + end + attribute \src "ls180.v:6291.47-6291.103" + cell $and $and$ls180.v:6291$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6291$1717_Y + connect \Y $and$ls180.v:6291$1718_Y + end + attribute \src "ls180.v:6291.46-6291.154" + cell $and $and$ls180.v:6291$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6291$1718_Y + connect \B $eq$ls180.v:6291$1719_Y + connect \Y $and$ls180.v:6291$1720_Y + end + attribute \src "ls180.v:6293.47-6293.100" + cell $and $and$ls180.v:6293$1721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6293$1721_Y + end + attribute \src "ls180.v:6293.46-6293.151" + cell $and $and$ls180.v:6293$1723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6293$1721_Y + connect \B $eq$ls180.v:6293$1722_Y + connect \Y $and$ls180.v:6293$1723_Y + end + attribute \src "ls180.v:6294.47-6294.103" + cell $and $and$ls180.v:6294$1725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6294$1724_Y + connect \Y $and$ls180.v:6294$1725_Y + end + attribute \src "ls180.v:6294.46-6294.154" + cell $and $and$ls180.v:6294$1727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6294$1725_Y + connect \B $eq$ls180.v:6294$1726_Y + connect \Y $and$ls180.v:6294$1727_Y + end + attribute \src "ls180.v:6296.47-6296.100" + cell $and $and$ls180.v:6296$1728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6296$1728_Y + end + attribute \src "ls180.v:6296.46-6296.151" + cell $and $and$ls180.v:6296$1730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6296$1728_Y + connect \B $eq$ls180.v:6296$1729_Y + connect \Y $and$ls180.v:6296$1730_Y + end + attribute \src "ls180.v:6297.47-6297.103" + cell $and $and$ls180.v:6297$1732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6297$1731_Y + connect \Y $and$ls180.v:6297$1732_Y + end + attribute \src "ls180.v:6297.46-6297.154" + cell $and $and$ls180.v:6297$1734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6297$1732_Y + connect \B $eq$ls180.v:6297$1733_Y + connect \Y $and$ls180.v:6297$1734_Y + end + attribute \src "ls180.v:6299.47-6299.100" + cell $and $and$ls180.v:6299$1735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6299$1735_Y + end + attribute \src "ls180.v:6299.46-6299.151" + cell $and $and$ls180.v:6299$1737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6299$1735_Y + connect \B $eq$ls180.v:6299$1736_Y + connect \Y $and$ls180.v:6299$1737_Y + end + attribute \src "ls180.v:6300.47-6300.103" + cell $and $and$ls180.v:6300$1739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6300$1738_Y + connect \Y $and$ls180.v:6300$1739_Y + end + attribute \src "ls180.v:6300.46-6300.154" + cell $and $and$ls180.v:6300$1741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6300$1739_Y + connect \B $eq$ls180.v:6300$1740_Y + connect \Y $and$ls180.v:6300$1741_Y + end + attribute \src "ls180.v:6302.46-6302.99" + cell $and $and$ls180.v:6302$1742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6302$1742_Y + end + attribute \src "ls180.v:6302.45-6302.150" + cell $and $and$ls180.v:6302$1744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6302$1742_Y + connect \B $eq$ls180.v:6302$1743_Y + connect \Y $and$ls180.v:6302$1744_Y + end + attribute \src "ls180.v:6303.46-6303.102" + cell $and $and$ls180.v:6303$1746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6303$1745_Y + connect \Y $and$ls180.v:6303$1746_Y + end + attribute \src "ls180.v:6303.45-6303.153" + cell $and $and$ls180.v:6303$1748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6303$1746_Y + connect \B $eq$ls180.v:6303$1747_Y + connect \Y $and$ls180.v:6303$1748_Y + end + attribute \src "ls180.v:6305.46-6305.99" + cell $and $and$ls180.v:6305$1749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6305$1749_Y + end + attribute \src "ls180.v:6305.45-6305.150" + cell $and $and$ls180.v:6305$1751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6305$1749_Y + connect \B $eq$ls180.v:6305$1750_Y + connect \Y $and$ls180.v:6305$1751_Y + end + attribute \src "ls180.v:6306.46-6306.102" + cell $and $and$ls180.v:6306$1753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6306$1752_Y + connect \Y $and$ls180.v:6306$1753_Y + end + attribute \src "ls180.v:6306.45-6306.153" + cell $and $and$ls180.v:6306$1755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6306$1753_Y + connect \B $eq$ls180.v:6306$1754_Y + connect \Y $and$ls180.v:6306$1755_Y + end + attribute \src "ls180.v:6308.46-6308.99" + cell $and $and$ls180.v:6308$1756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6308$1756_Y + end + attribute \src "ls180.v:6308.45-6308.150" + cell $and $and$ls180.v:6308$1758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6308$1756_Y + connect \B $eq$ls180.v:6308$1757_Y + connect \Y $and$ls180.v:6308$1758_Y + end + attribute \src "ls180.v:6309.46-6309.102" + cell $and $and$ls180.v:6309$1760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6309$1759_Y + connect \Y $and$ls180.v:6309$1760_Y + end + attribute \src "ls180.v:6309.45-6309.153" + cell $and $and$ls180.v:6309$1762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6309$1760_Y + connect \B $eq$ls180.v:6309$1761_Y + connect \Y $and$ls180.v:6309$1762_Y + end + attribute \src "ls180.v:6311.46-6311.99" + cell $and $and$ls180.v:6311$1763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6311$1763_Y + end + attribute \src "ls180.v:6311.45-6311.150" + cell $and $and$ls180.v:6311$1765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6311$1763_Y + connect \B $eq$ls180.v:6311$1764_Y + connect \Y $and$ls180.v:6311$1765_Y + end + attribute \src "ls180.v:6312.46-6312.102" + cell $and $and$ls180.v:6312$1767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6312$1766_Y + connect \Y $and$ls180.v:6312$1767_Y + end + attribute \src "ls180.v:6312.45-6312.153" + cell $and $and$ls180.v:6312$1769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6312$1767_Y + connect \B $eq$ls180.v:6312$1768_Y + connect \Y $and$ls180.v:6312$1769_Y + end + attribute \src "ls180.v:6314.46-6314.99" + cell $and $and$ls180.v:6314$1770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6314$1770_Y + end + attribute \src "ls180.v:6314.45-6314.150" + cell $and $and$ls180.v:6314$1772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6314$1770_Y + connect \B $eq$ls180.v:6314$1771_Y + connect \Y $and$ls180.v:6314$1772_Y + end + attribute \src "ls180.v:6315.46-6315.102" + cell $and $and$ls180.v:6315$1774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6315$1773_Y + connect \Y $and$ls180.v:6315$1774_Y + end + attribute \src "ls180.v:6315.45-6315.153" + cell $and $and$ls180.v:6315$1776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6315$1774_Y + connect \B $eq$ls180.v:6315$1775_Y + connect \Y $and$ls180.v:6315$1776_Y + end + attribute \src "ls180.v:6317.46-6317.99" + cell $and $and$ls180.v:6317$1777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6317$1777_Y + end + attribute \src "ls180.v:6317.45-6317.150" + cell $and $and$ls180.v:6317$1779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6317$1777_Y + connect \B $eq$ls180.v:6317$1778_Y + connect \Y $and$ls180.v:6317$1779_Y + end + attribute \src "ls180.v:6318.46-6318.102" + cell $and $and$ls180.v:6318$1781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6318$1780_Y + connect \Y $and$ls180.v:6318$1781_Y + end + attribute \src "ls180.v:6318.45-6318.153" + cell $and $and$ls180.v:6318$1783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6318$1781_Y + connect \B $eq$ls180.v:6318$1782_Y + connect \Y $and$ls180.v:6318$1783_Y + end + attribute \src "ls180.v:6320.46-6320.99" + cell $and $and$ls180.v:6320$1784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6320$1784_Y + end + attribute \src "ls180.v:6320.45-6320.150" + cell $and $and$ls180.v:6320$1786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6320$1784_Y + connect \B $eq$ls180.v:6320$1785_Y + connect \Y $and$ls180.v:6320$1786_Y + end + attribute \src "ls180.v:6321.46-6321.102" + cell $and $and$ls180.v:6321$1788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6321$1787_Y + connect \Y $and$ls180.v:6321$1788_Y + end + attribute \src "ls180.v:6321.45-6321.153" + cell $and $and$ls180.v:6321$1790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6321$1788_Y + connect \B $eq$ls180.v:6321$1789_Y + connect \Y $and$ls180.v:6321$1790_Y + end + attribute \src "ls180.v:6323.46-6323.99" + cell $and $and$ls180.v:6323$1791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6323$1791_Y + end + attribute \src "ls180.v:6323.45-6323.150" + cell $and $and$ls180.v:6323$1793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6323$1791_Y + connect \B $eq$ls180.v:6323$1792_Y + connect \Y $and$ls180.v:6323$1793_Y + end + attribute \src "ls180.v:6324.46-6324.102" + cell $and $and$ls180.v:6324$1795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6324$1794_Y + connect \Y $and$ls180.v:6324$1795_Y + end + attribute \src "ls180.v:6324.45-6324.153" + cell $and $and$ls180.v:6324$1797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6324$1795_Y + connect \B $eq$ls180.v:6324$1796_Y + connect \Y $and$ls180.v:6324$1797_Y + end + attribute \src "ls180.v:6326.46-6326.99" + cell $and $and$ls180.v:6326$1798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6326$1798_Y + end + attribute \src "ls180.v:6326.45-6326.150" + cell $and $and$ls180.v:6326$1800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6326$1798_Y + connect \B $eq$ls180.v:6326$1799_Y + connect \Y $and$ls180.v:6326$1800_Y + end + attribute \src "ls180.v:6327.46-6327.102" + cell $and $and$ls180.v:6327$1802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6327$1801_Y + connect \Y $and$ls180.v:6327$1802_Y + end + attribute \src "ls180.v:6327.45-6327.153" + cell $and $and$ls180.v:6327$1804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6327$1802_Y + connect \B $eq$ls180.v:6327$1803_Y + connect \Y $and$ls180.v:6327$1804_Y + end + attribute \src "ls180.v:6329.46-6329.99" + cell $and $and$ls180.v:6329$1805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6329$1805_Y + end + attribute \src "ls180.v:6329.45-6329.150" + cell $and $and$ls180.v:6329$1807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6329$1805_Y + connect \B $eq$ls180.v:6329$1806_Y + connect \Y $and$ls180.v:6329$1807_Y + end + attribute \src "ls180.v:6330.46-6330.102" + cell $and $and$ls180.v:6330$1809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6330$1808_Y + connect \Y $and$ls180.v:6330$1809_Y + end + attribute \src "ls180.v:6330.45-6330.153" + cell $and $and$ls180.v:6330$1811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6330$1809_Y + connect \B $eq$ls180.v:6330$1810_Y + connect \Y $and$ls180.v:6330$1811_Y + end + attribute \src "ls180.v:6332.42-6332.95" + cell $and $and$ls180.v:6332$1812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6332$1812_Y + end + attribute \src "ls180.v:6332.41-6332.146" + cell $and $and$ls180.v:6332$1814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6332$1812_Y + connect \B $eq$ls180.v:6332$1813_Y + connect \Y $and$ls180.v:6332$1814_Y + end + attribute \src "ls180.v:6333.42-6333.98" + cell $and $and$ls180.v:6333$1816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6333$1815_Y + connect \Y $and$ls180.v:6333$1816_Y + end + attribute \src "ls180.v:6333.41-6333.149" + cell $and $and$ls180.v:6333$1818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6333$1816_Y + connect \B $eq$ls180.v:6333$1817_Y + connect \Y $and$ls180.v:6333$1818_Y + end + attribute \src "ls180.v:6335.43-6335.96" + cell $and $and$ls180.v:6335$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6335$1819_Y + end + attribute \src "ls180.v:6335.42-6335.147" + cell $and $and$ls180.v:6335$1821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6335$1819_Y + connect \B $eq$ls180.v:6335$1820_Y + connect \Y $and$ls180.v:6335$1821_Y + end + attribute \src "ls180.v:6336.43-6336.99" + cell $and $and$ls180.v:6336$1823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6336$1822_Y + connect \Y $and$ls180.v:6336$1823_Y + end + attribute \src "ls180.v:6336.42-6336.150" + cell $and $and$ls180.v:6336$1825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6336$1823_Y + connect \B $eq$ls180.v:6336$1824_Y + connect \Y $and$ls180.v:6336$1825_Y + end + attribute \src "ls180.v:6338.46-6338.99" + cell $and $and$ls180.v:6338$1826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6338$1826_Y + end + attribute \src "ls180.v:6338.45-6338.150" + cell $and $and$ls180.v:6338$1828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6338$1826_Y + connect \B $eq$ls180.v:6338$1827_Y + connect \Y $and$ls180.v:6338$1828_Y + end + attribute \src "ls180.v:6339.46-6339.102" + cell $and $and$ls180.v:6339$1830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6339$1829_Y + connect \Y $and$ls180.v:6339$1830_Y + end + attribute \src "ls180.v:6339.45-6339.153" + cell $and $and$ls180.v:6339$1832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6339$1830_Y + connect \B $eq$ls180.v:6339$1831_Y + connect \Y $and$ls180.v:6339$1832_Y + end + attribute \src "ls180.v:6341.46-6341.99" + cell $and $and$ls180.v:6341$1833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6341$1833_Y + end + attribute \src "ls180.v:6341.45-6341.150" + cell $and $and$ls180.v:6341$1835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6341$1833_Y + connect \B $eq$ls180.v:6341$1834_Y + connect \Y $and$ls180.v:6341$1835_Y + end + attribute \src "ls180.v:6342.46-6342.102" + cell $and $and$ls180.v:6342$1837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6342$1836_Y + connect \Y $and$ls180.v:6342$1837_Y + end + attribute \src "ls180.v:6342.45-6342.153" + cell $and $and$ls180.v:6342$1839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6342$1837_Y + connect \B $eq$ls180.v:6342$1838_Y + connect \Y $and$ls180.v:6342$1839_Y + end + attribute \src "ls180.v:6344.45-6344.98" + cell $and $and$ls180.v:6344$1840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6344$1840_Y + end + attribute \src "ls180.v:6344.44-6344.149" + cell $and $and$ls180.v:6344$1842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6344$1840_Y + connect \B $eq$ls180.v:6344$1841_Y + connect \Y $and$ls180.v:6344$1842_Y + end + attribute \src "ls180.v:6345.45-6345.101" + cell $and $and$ls180.v:6345$1844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6345$1843_Y + connect \Y $and$ls180.v:6345$1844_Y + end + attribute \src "ls180.v:6345.44-6345.152" + cell $and $and$ls180.v:6345$1846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6345$1844_Y + connect \B $eq$ls180.v:6345$1845_Y + connect \Y $and$ls180.v:6345$1846_Y + end + attribute \src "ls180.v:6347.45-6347.98" + cell $and $and$ls180.v:6347$1847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6347$1847_Y + end + attribute \src "ls180.v:6347.44-6347.149" + cell $and $and$ls180.v:6347$1849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6347$1847_Y + connect \B $eq$ls180.v:6347$1848_Y + connect \Y $and$ls180.v:6347$1849_Y + end + attribute \src "ls180.v:6348.45-6348.101" + cell $and $and$ls180.v:6348$1851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6348$1850_Y + connect \Y $and$ls180.v:6348$1851_Y + end + attribute \src "ls180.v:6348.44-6348.152" + cell $and $and$ls180.v:6348$1853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6348$1851_Y + connect \B $eq$ls180.v:6348$1852_Y + connect \Y $and$ls180.v:6348$1853_Y + end + attribute \src "ls180.v:6350.45-6350.98" + cell $and $and$ls180.v:6350$1854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6350$1854_Y + end + attribute \src "ls180.v:6350.44-6350.149" + cell $and $and$ls180.v:6350$1856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6350$1854_Y + connect \B $eq$ls180.v:6350$1855_Y + connect \Y $and$ls180.v:6350$1856_Y + end + attribute \src "ls180.v:6351.45-6351.101" + cell $and $and$ls180.v:6351$1858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6351$1857_Y + connect \Y $and$ls180.v:6351$1858_Y + end + attribute \src "ls180.v:6351.44-6351.152" + cell $and $and$ls180.v:6351$1860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6351$1858_Y + connect \B $eq$ls180.v:6351$1859_Y + connect \Y $and$ls180.v:6351$1860_Y + end + attribute \src "ls180.v:6353.45-6353.98" + cell $and $and$ls180.v:6353$1861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6353$1861_Y + end + attribute \src "ls180.v:6353.44-6353.149" + cell $and $and$ls180.v:6353$1863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6353$1861_Y + connect \B $eq$ls180.v:6353$1862_Y + connect \Y $and$ls180.v:6353$1863_Y + end + attribute \src "ls180.v:6354.45-6354.101" + cell $and $and$ls180.v:6354$1865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6354$1864_Y + connect \Y $and$ls180.v:6354$1865_Y + end + attribute \src "ls180.v:6354.44-6354.152" + cell $and $and$ls180.v:6354$1867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6354$1865_Y + connect \B $eq$ls180.v:6354$1866_Y + connect \Y $and$ls180.v:6354$1867_Y + end + attribute \src "ls180.v:6392.42-6392.95" + cell $and $and$ls180.v:6392$1869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6392$1869_Y + end + attribute \src "ls180.v:6392.41-6392.145" + cell $and $and$ls180.v:6392$1871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6392$1869_Y + connect \B $eq$ls180.v:6392$1870_Y + connect \Y $and$ls180.v:6392$1871_Y + end + attribute \src "ls180.v:6393.42-6393.98" + cell $and $and$ls180.v:6393$1873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6393$1872_Y + connect \Y $and$ls180.v:6393$1873_Y + end + attribute \src "ls180.v:6393.41-6393.148" + cell $and $and$ls180.v:6393$1875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6393$1873_Y + connect \B $eq$ls180.v:6393$1874_Y + connect \Y $and$ls180.v:6393$1875_Y + end + attribute \src "ls180.v:6395.42-6395.95" + cell $and $and$ls180.v:6395$1876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6395$1876_Y + end + attribute \src "ls180.v:6395.41-6395.145" + cell $and $and$ls180.v:6395$1878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6395$1876_Y + connect \B $eq$ls180.v:6395$1877_Y + connect \Y $and$ls180.v:6395$1878_Y + end + attribute \src "ls180.v:6396.42-6396.98" + cell $and $and$ls180.v:6396$1880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6396$1879_Y + connect \Y $and$ls180.v:6396$1880_Y + end + attribute \src "ls180.v:6396.41-6396.148" + cell $and $and$ls180.v:6396$1882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6396$1880_Y + connect \B $eq$ls180.v:6396$1881_Y + connect \Y $and$ls180.v:6396$1882_Y + end + attribute \src "ls180.v:6398.42-6398.95" + cell $and $and$ls180.v:6398$1883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6398$1883_Y + end + attribute \src "ls180.v:6398.41-6398.145" + cell $and $and$ls180.v:6398$1885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6398$1883_Y + connect \B $eq$ls180.v:6398$1884_Y + connect \Y $and$ls180.v:6398$1885_Y + end + attribute \src "ls180.v:6399.42-6399.98" + cell $and $and$ls180.v:6399$1887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6399$1886_Y + connect \Y $and$ls180.v:6399$1887_Y + end + attribute \src "ls180.v:6399.41-6399.148" + cell $and $and$ls180.v:6399$1889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6399$1887_Y + connect \B $eq$ls180.v:6399$1888_Y + connect \Y $and$ls180.v:6399$1889_Y + end + attribute \src "ls180.v:6401.42-6401.95" + cell $and $and$ls180.v:6401$1890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6401$1890_Y + end + attribute \src "ls180.v:6401.41-6401.145" + cell $and $and$ls180.v:6401$1892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6401$1890_Y + connect \B $eq$ls180.v:6401$1891_Y + connect \Y $and$ls180.v:6401$1892_Y + end + attribute \src "ls180.v:6402.42-6402.98" + cell $and $and$ls180.v:6402$1894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6402$1893_Y + connect \Y $and$ls180.v:6402$1894_Y + end + attribute \src "ls180.v:6402.41-6402.148" + cell $and $and$ls180.v:6402$1896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6402$1894_Y + connect \B $eq$ls180.v:6402$1895_Y + connect \Y $and$ls180.v:6402$1896_Y + end + attribute \src "ls180.v:6404.42-6404.95" + cell $and $and$ls180.v:6404$1897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6404$1897_Y + end + attribute \src "ls180.v:6404.41-6404.145" + cell $and $and$ls180.v:6404$1899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6404$1897_Y + connect \B $eq$ls180.v:6404$1898_Y + connect \Y $and$ls180.v:6404$1899_Y + end + attribute \src "ls180.v:6405.42-6405.98" + cell $and $and$ls180.v:6405$1901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6405$1900_Y + connect \Y $and$ls180.v:6405$1901_Y + end + attribute \src "ls180.v:6405.41-6405.148" + cell $and $and$ls180.v:6405$1903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6405$1901_Y + connect \B $eq$ls180.v:6405$1902_Y + connect \Y $and$ls180.v:6405$1903_Y + end + attribute \src "ls180.v:6407.42-6407.95" + cell $and $and$ls180.v:6407$1904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6407$1904_Y + end + attribute \src "ls180.v:6407.41-6407.145" + cell $and $and$ls180.v:6407$1906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6407$1904_Y + connect \B $eq$ls180.v:6407$1905_Y + connect \Y $and$ls180.v:6407$1906_Y + end + attribute \src "ls180.v:6408.42-6408.98" + cell $and $and$ls180.v:6408$1908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6408$1907_Y + connect \Y $and$ls180.v:6408$1908_Y + end + attribute \src "ls180.v:6408.41-6408.148" + cell $and $and$ls180.v:6408$1910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6408$1908_Y + connect \B $eq$ls180.v:6408$1909_Y + connect \Y $and$ls180.v:6408$1910_Y + end + attribute \src "ls180.v:6410.42-6410.95" + cell $and $and$ls180.v:6410$1911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6410$1911_Y + end + attribute \src "ls180.v:6410.41-6410.145" + cell $and $and$ls180.v:6410$1913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6410$1911_Y + connect \B $eq$ls180.v:6410$1912_Y + connect \Y $and$ls180.v:6410$1913_Y + end + attribute \src "ls180.v:6411.42-6411.98" + cell $and $and$ls180.v:6411$1915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6411$1914_Y + connect \Y $and$ls180.v:6411$1915_Y + end + attribute \src "ls180.v:6411.41-6411.148" + cell $and $and$ls180.v:6411$1917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6411$1915_Y + connect \B $eq$ls180.v:6411$1916_Y + connect \Y $and$ls180.v:6411$1917_Y + end + attribute \src "ls180.v:6413.42-6413.95" + cell $and $and$ls180.v:6413$1918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6413$1918_Y + end + attribute \src "ls180.v:6413.41-6413.145" + cell $and $and$ls180.v:6413$1920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6413$1918_Y + connect \B $eq$ls180.v:6413$1919_Y + connect \Y $and$ls180.v:6413$1920_Y + end + attribute \src "ls180.v:6414.42-6414.98" + cell $and $and$ls180.v:6414$1922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6414$1921_Y + connect \Y $and$ls180.v:6414$1922_Y + end + attribute \src "ls180.v:6414.41-6414.148" + cell $and $and$ls180.v:6414$1924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6414$1922_Y + connect \B $eq$ls180.v:6414$1923_Y + connect \Y $and$ls180.v:6414$1924_Y + end + attribute \src "ls180.v:6416.44-6416.97" + cell $and $and$ls180.v:6416$1925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6416$1925_Y + end + attribute \src "ls180.v:6416.43-6416.147" + cell $and $and$ls180.v:6416$1927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6416$1925_Y + connect \B $eq$ls180.v:6416$1926_Y + connect \Y $and$ls180.v:6416$1927_Y + end + attribute \src "ls180.v:6417.44-6417.100" + cell $and $and$ls180.v:6417$1929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6417$1928_Y + connect \Y $and$ls180.v:6417$1929_Y + end + attribute \src "ls180.v:6417.43-6417.150" + cell $and $and$ls180.v:6417$1931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6417$1929_Y + connect \B $eq$ls180.v:6417$1930_Y + connect \Y $and$ls180.v:6417$1931_Y + end + attribute \src "ls180.v:6419.44-6419.97" + cell $and $and$ls180.v:6419$1932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6419$1932_Y + end + attribute \src "ls180.v:6419.43-6419.147" + cell $and $and$ls180.v:6419$1934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6419$1932_Y + connect \B $eq$ls180.v:6419$1933_Y + connect \Y $and$ls180.v:6419$1934_Y + end + attribute \src "ls180.v:6420.44-6420.100" + cell $and $and$ls180.v:6420$1936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6420$1935_Y + connect \Y $and$ls180.v:6420$1936_Y + end + attribute \src "ls180.v:6420.43-6420.150" + cell $and $and$ls180.v:6420$1938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6420$1936_Y + connect \B $eq$ls180.v:6420$1937_Y + connect \Y $and$ls180.v:6420$1938_Y + end + attribute \src "ls180.v:6422.44-6422.97" + cell $and $and$ls180.v:6422$1939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6422$1939_Y + end + attribute \src "ls180.v:6422.43-6422.148" + cell $and $and$ls180.v:6422$1941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6422$1939_Y + connect \B $eq$ls180.v:6422$1940_Y + connect \Y $and$ls180.v:6422$1941_Y + end + attribute \src "ls180.v:6423.44-6423.100" + cell $and $and$ls180.v:6423$1943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6423$1942_Y + connect \Y $and$ls180.v:6423$1943_Y + end + attribute \src "ls180.v:6423.43-6423.151" + cell $and $and$ls180.v:6423$1945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6423$1943_Y + connect \B $eq$ls180.v:6423$1944_Y + connect \Y $and$ls180.v:6423$1945_Y + end + attribute \src "ls180.v:6425.44-6425.97" + cell $and $and$ls180.v:6425$1946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6425$1946_Y + end + attribute \src "ls180.v:6425.43-6425.148" + cell $and $and$ls180.v:6425$1948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6425$1946_Y + connect \B $eq$ls180.v:6425$1947_Y + connect \Y $and$ls180.v:6425$1948_Y + end + attribute \src "ls180.v:6426.44-6426.100" + cell $and $and$ls180.v:6426$1950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6426$1949_Y + connect \Y $and$ls180.v:6426$1950_Y + end + attribute \src "ls180.v:6426.43-6426.151" + cell $and $and$ls180.v:6426$1952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6426$1950_Y + connect \B $eq$ls180.v:6426$1951_Y + connect \Y $and$ls180.v:6426$1952_Y + end + attribute \src "ls180.v:6428.44-6428.97" + cell $and $and$ls180.v:6428$1953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6428$1953_Y + end + attribute \src "ls180.v:6428.43-6428.148" + cell $and $and$ls180.v:6428$1955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6428$1953_Y + connect \B $eq$ls180.v:6428$1954_Y + connect \Y $and$ls180.v:6428$1955_Y + end + attribute \src "ls180.v:6429.44-6429.100" + cell $and $and$ls180.v:6429$1957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6429$1956_Y + connect \Y $and$ls180.v:6429$1957_Y + end + attribute \src "ls180.v:6429.43-6429.151" + cell $and $and$ls180.v:6429$1959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6429$1957_Y + connect \B $eq$ls180.v:6429$1958_Y + connect \Y $and$ls180.v:6429$1959_Y + end + attribute \src "ls180.v:6431.41-6431.94" + cell $and $and$ls180.v:6431$1960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6431$1960_Y + end + attribute \src "ls180.v:6431.40-6431.145" + cell $and $and$ls180.v:6431$1962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6431$1960_Y + connect \B $eq$ls180.v:6431$1961_Y + connect \Y $and$ls180.v:6431$1962_Y + end + attribute \src "ls180.v:6432.41-6432.97" + cell $and $and$ls180.v:6432$1964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6432$1963_Y + connect \Y $and$ls180.v:6432$1964_Y + end + attribute \src "ls180.v:6432.40-6432.148" + cell $and $and$ls180.v:6432$1966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6432$1964_Y + connect \B $eq$ls180.v:6432$1965_Y + connect \Y $and$ls180.v:6432$1966_Y + end + attribute \src "ls180.v:6434.42-6434.95" + cell $and $and$ls180.v:6434$1967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6434$1967_Y + end + attribute \src "ls180.v:6434.41-6434.146" + cell $and $and$ls180.v:6434$1969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6434$1967_Y + connect \B $eq$ls180.v:6434$1968_Y + connect \Y $and$ls180.v:6434$1969_Y + end + attribute \src "ls180.v:6435.42-6435.98" + cell $and $and$ls180.v:6435$1971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6435$1970_Y + connect \Y $and$ls180.v:6435$1971_Y + end + attribute \src "ls180.v:6435.41-6435.149" + cell $and $and$ls180.v:6435$1973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6435$1971_Y + connect \B $eq$ls180.v:6435$1972_Y + connect \Y $and$ls180.v:6435$1973_Y + end + attribute \src "ls180.v:6437.44-6437.97" + cell $and $and$ls180.v:6437$1974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6437$1974_Y + end + attribute \src "ls180.v:6437.43-6437.148" + cell $and $and$ls180.v:6437$1976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6437$1974_Y + connect \B $eq$ls180.v:6437$1975_Y + connect \Y $and$ls180.v:6437$1976_Y + end + attribute \src "ls180.v:6438.44-6438.100" + cell $and $and$ls180.v:6438$1978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6438$1977_Y + connect \Y $and$ls180.v:6438$1978_Y + end + attribute \src "ls180.v:6438.43-6438.151" + cell $and $and$ls180.v:6438$1980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6438$1978_Y + connect \B $eq$ls180.v:6438$1979_Y + connect \Y $and$ls180.v:6438$1980_Y + end + attribute \src "ls180.v:6440.44-6440.97" + cell $and $and$ls180.v:6440$1981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6440$1981_Y + end + attribute \src "ls180.v:6440.43-6440.148" + cell $and $and$ls180.v:6440$1983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6440$1981_Y + connect \B $eq$ls180.v:6440$1982_Y + connect \Y $and$ls180.v:6440$1983_Y + end + attribute \src "ls180.v:6441.44-6441.100" + cell $and $and$ls180.v:6441$1985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6441$1984_Y + connect \Y $and$ls180.v:6441$1985_Y + end + attribute \src "ls180.v:6441.43-6441.151" + cell $and $and$ls180.v:6441$1987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6441$1985_Y + connect \B $eq$ls180.v:6441$1986_Y + connect \Y $and$ls180.v:6441$1987_Y + end + attribute \src "ls180.v:6443.44-6443.97" + cell $and $and$ls180.v:6443$1988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6443$1988_Y + end + attribute \src "ls180.v:6443.43-6443.148" + cell $and $and$ls180.v:6443$1990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6443$1988_Y + connect \B $eq$ls180.v:6443$1989_Y + connect \Y $and$ls180.v:6443$1990_Y + end + attribute \src "ls180.v:6444.44-6444.100" + cell $and $and$ls180.v:6444$1992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6444$1991_Y + connect \Y $and$ls180.v:6444$1992_Y + end + attribute \src "ls180.v:6444.43-6444.151" + cell $and $and$ls180.v:6444$1994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6444$1992_Y + connect \B $eq$ls180.v:6444$1993_Y + connect \Y $and$ls180.v:6444$1994_Y + end + attribute \src "ls180.v:6446.44-6446.97" + cell $and $and$ls180.v:6446$1995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6446$1995_Y + end + attribute \src "ls180.v:6446.43-6446.148" + cell $and $and$ls180.v:6446$1997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6446$1995_Y + connect \B $eq$ls180.v:6446$1996_Y + connect \Y $and$ls180.v:6446$1997_Y + end + attribute \src "ls180.v:6447.44-6447.100" + cell $and $and$ls180.v:6447$1999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6447$1998_Y + connect \Y $and$ls180.v:6447$1999_Y + end + attribute \src "ls180.v:6447.43-6447.151" + cell $and $and$ls180.v:6447$2001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6447$1999_Y + connect \B $eq$ls180.v:6447$2000_Y + connect \Y $and$ls180.v:6447$2001_Y + end + attribute \src "ls180.v:6471.44-6471.97" + cell $and $and$ls180.v:6471$2003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6471$2003_Y + end + attribute \src "ls180.v:6471.43-6471.147" + cell $and $and$ls180.v:6471$2005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6471$2003_Y + connect \B $eq$ls180.v:6471$2004_Y + connect \Y $and$ls180.v:6471$2005_Y + end + attribute \src "ls180.v:6472.44-6472.100" + cell $and $and$ls180.v:6472$2007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6472$2006_Y + connect \Y $and$ls180.v:6472$2007_Y + end + attribute \src "ls180.v:6472.43-6472.150" + cell $and $and$ls180.v:6472$2009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6472$2007_Y + connect \B $eq$ls180.v:6472$2008_Y + connect \Y $and$ls180.v:6472$2009_Y + end + attribute \src "ls180.v:6474.49-6474.102" + cell $and $and$ls180.v:6474$2010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6474$2010_Y + end + attribute \src "ls180.v:6474.48-6474.152" + cell $and $and$ls180.v:6474$2012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6474$2010_Y + connect \B $eq$ls180.v:6474$2011_Y + connect \Y $and$ls180.v:6474$2012_Y + end + attribute \src "ls180.v:6475.49-6475.105" + cell $and $and$ls180.v:6475$2014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6475$2013_Y + connect \Y $and$ls180.v:6475$2014_Y + end + attribute \src "ls180.v:6475.48-6475.155" + cell $and $and$ls180.v:6475$2016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6475$2014_Y + connect \B $eq$ls180.v:6475$2015_Y + connect \Y $and$ls180.v:6475$2016_Y + end + attribute \src "ls180.v:6477.49-6477.102" + cell $and $and$ls180.v:6477$2017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6477$2017_Y + end + attribute \src "ls180.v:6477.48-6477.152" + cell $and $and$ls180.v:6477$2019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6477$2017_Y + connect \B $eq$ls180.v:6477$2018_Y + connect \Y $and$ls180.v:6477$2019_Y + end + attribute \src "ls180.v:6478.49-6478.105" + cell $and $and$ls180.v:6478$2021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6478$2020_Y + connect \Y $and$ls180.v:6478$2021_Y + end + attribute \src "ls180.v:6478.48-6478.155" + cell $and $and$ls180.v:6478$2023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6478$2021_Y + connect \B $eq$ls180.v:6478$2022_Y + connect \Y $and$ls180.v:6478$2023_Y + end + attribute \src "ls180.v:6480.42-6480.95" + cell $and $and$ls180.v:6480$2024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6480$2024_Y + end + attribute \src "ls180.v:6480.41-6480.145" + cell $and $and$ls180.v:6480$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6480$2024_Y + connect \B $eq$ls180.v:6480$2025_Y + connect \Y $and$ls180.v:6480$2026_Y + end + attribute \src "ls180.v:6481.42-6481.98" + cell $and $and$ls180.v:6481$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6481$2027_Y + connect \Y $and$ls180.v:6481$2028_Y + end + attribute \src "ls180.v:6481.41-6481.148" + cell $and $and$ls180.v:6481$2030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6481$2028_Y + connect \B $eq$ls180.v:6481$2029_Y + connect \Y $and$ls180.v:6481$2030_Y + end + attribute \src "ls180.v:6488.46-6488.99" + cell $and $and$ls180.v:6488$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6488$2032_Y + end + attribute \src "ls180.v:6488.45-6488.149" + cell $and $and$ls180.v:6488$2034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6488$2032_Y + connect \B $eq$ls180.v:6488$2033_Y + connect \Y $and$ls180.v:6488$2034_Y + end + attribute \src "ls180.v:6489.46-6489.102" + cell $and $and$ls180.v:6489$2036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6489$2035_Y + connect \Y $and$ls180.v:6489$2036_Y + end + attribute \src "ls180.v:6489.45-6489.152" + cell $and $and$ls180.v:6489$2038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6489$2036_Y + connect \B $eq$ls180.v:6489$2037_Y + connect \Y $and$ls180.v:6489$2038_Y + end + attribute \src "ls180.v:6491.50-6491.103" + cell $and $and$ls180.v:6491$2039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6491$2039_Y + end + attribute \src "ls180.v:6491.49-6491.153" + cell $and $and$ls180.v:6491$2041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6491$2039_Y + connect \B $eq$ls180.v:6491$2040_Y + connect \Y $and$ls180.v:6491$2041_Y + end + attribute \src "ls180.v:6492.50-6492.106" + cell $and $and$ls180.v:6492$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6492$2042_Y + connect \Y $and$ls180.v:6492$2043_Y + end + attribute \src "ls180.v:6492.49-6492.156" + cell $and $and$ls180.v:6492$2045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6492$2043_Y + connect \B $eq$ls180.v:6492$2044_Y + connect \Y $and$ls180.v:6492$2045_Y + end + attribute \src "ls180.v:6494.40-6494.93" + cell $and $and$ls180.v:6494$2046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6494$2046_Y + end + attribute \src "ls180.v:6494.39-6494.143" + cell $and $and$ls180.v:6494$2048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6494$2046_Y + connect \B $eq$ls180.v:6494$2047_Y + connect \Y $and$ls180.v:6494$2048_Y + end + attribute \src "ls180.v:6495.40-6495.96" + cell $and $and$ls180.v:6495$2050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6495$2049_Y + connect \Y $and$ls180.v:6495$2050_Y + end + attribute \src "ls180.v:6495.39-6495.146" + cell $and $and$ls180.v:6495$2052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6495$2050_Y + connect \B $eq$ls180.v:6495$2051_Y + connect \Y $and$ls180.v:6495$2052_Y + end + attribute \src "ls180.v:6497.50-6497.103" + cell $and $and$ls180.v:6497$2053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6497$2053_Y + end + attribute \src "ls180.v:6497.49-6497.153" + cell $and $and$ls180.v:6497$2055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6497$2053_Y + connect \B $eq$ls180.v:6497$2054_Y + connect \Y $and$ls180.v:6497$2055_Y + end + attribute \src "ls180.v:6498.50-6498.106" + cell $and $and$ls180.v:6498$2057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6498$2056_Y + connect \Y $and$ls180.v:6498$2057_Y + end + attribute \src "ls180.v:6498.49-6498.156" + cell $and $and$ls180.v:6498$2059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6498$2057_Y + connect \B $eq$ls180.v:6498$2058_Y + connect \Y $and$ls180.v:6498$2059_Y + end + attribute \src "ls180.v:6500.50-6500.103" + cell $and $and$ls180.v:6500$2060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6500$2060_Y + end + attribute \src "ls180.v:6500.49-6500.153" + cell $and $and$ls180.v:6500$2062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6500$2060_Y + connect \B $eq$ls180.v:6500$2061_Y + connect \Y $and$ls180.v:6500$2062_Y + end + attribute \src "ls180.v:6501.50-6501.106" + cell $and $and$ls180.v:6501$2064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6501$2063_Y + connect \Y $and$ls180.v:6501$2064_Y + end + attribute \src "ls180.v:6501.49-6501.156" + cell $and $and$ls180.v:6501$2066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6501$2064_Y + connect \B $eq$ls180.v:6501$2065_Y + connect \Y $and$ls180.v:6501$2066_Y + end + attribute \src "ls180.v:6503.51-6503.104" + cell $and $and$ls180.v:6503$2067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6503$2067_Y + end + attribute \src "ls180.v:6503.50-6503.154" + cell $and $and$ls180.v:6503$2069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6503$2067_Y + connect \B $eq$ls180.v:6503$2068_Y + connect \Y $and$ls180.v:6503$2069_Y + end + attribute \src "ls180.v:6504.51-6504.107" + cell $and $and$ls180.v:6504$2071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6504$2070_Y + connect \Y $and$ls180.v:6504$2071_Y + end + attribute \src "ls180.v:6504.50-6504.157" + cell $and $and$ls180.v:6504$2073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6504$2071_Y + connect \B $eq$ls180.v:6504$2072_Y + connect \Y $and$ls180.v:6504$2073_Y + end + attribute \src "ls180.v:6506.49-6506.102" + cell $and $and$ls180.v:6506$2074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6506$2074_Y + end + attribute \src "ls180.v:6506.48-6506.152" + cell $and $and$ls180.v:6506$2076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6506$2074_Y + connect \B $eq$ls180.v:6506$2075_Y + connect \Y $and$ls180.v:6506$2076_Y + end + attribute \src "ls180.v:6507.49-6507.105" + cell $and $and$ls180.v:6507$2078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6507$2077_Y + connect \Y $and$ls180.v:6507$2078_Y + end + attribute \src "ls180.v:6507.48-6507.155" + cell $and $and$ls180.v:6507$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6507$2078_Y + connect \B $eq$ls180.v:6507$2079_Y + connect \Y $and$ls180.v:6507$2080_Y + end + attribute \src "ls180.v:6509.49-6509.102" + cell $and $and$ls180.v:6509$2081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6509$2081_Y + end + attribute \src "ls180.v:6509.48-6509.152" + cell $and $and$ls180.v:6509$2083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6509$2081_Y + connect \B $eq$ls180.v:6509$2082_Y + connect \Y $and$ls180.v:6509$2083_Y + end + attribute \src "ls180.v:6510.49-6510.105" + cell $and $and$ls180.v:6510$2085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6510$2084_Y + connect \Y $and$ls180.v:6510$2085_Y + end + attribute \src "ls180.v:6510.48-6510.155" + cell $and $and$ls180.v:6510$2087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6510$2085_Y + connect \B $eq$ls180.v:6510$2086_Y + connect \Y $and$ls180.v:6510$2087_Y + end + attribute \src "ls180.v:6512.49-6512.102" + cell $and $and$ls180.v:6512$2088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6512$2088_Y + end + attribute \src "ls180.v:6512.48-6512.152" + cell $and $and$ls180.v:6512$2090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6512$2088_Y + connect \B $eq$ls180.v:6512$2089_Y + connect \Y $and$ls180.v:6512$2090_Y + end + attribute \src "ls180.v:6513.49-6513.105" + cell $and $and$ls180.v:6513$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6513$2091_Y + connect \Y $and$ls180.v:6513$2092_Y + end + attribute \src "ls180.v:6513.48-6513.155" + cell $and $and$ls180.v:6513$2094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6513$2092_Y + connect \B $eq$ls180.v:6513$2093_Y + connect \Y $and$ls180.v:6513$2094_Y + end + attribute \src "ls180.v:6515.49-6515.102" + cell $and $and$ls180.v:6515$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6515$2095_Y + end + attribute \src "ls180.v:6515.48-6515.152" + cell $and $and$ls180.v:6515$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6515$2095_Y + connect \B $eq$ls180.v:6515$2096_Y + connect \Y $and$ls180.v:6515$2097_Y + end + attribute \src "ls180.v:6516.49-6516.105" + cell $and $and$ls180.v:6516$2099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6516$2098_Y + connect \Y $and$ls180.v:6516$2099_Y + end + attribute \src "ls180.v:6516.48-6516.155" + cell $and $and$ls180.v:6516$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6516$2099_Y + connect \B $eq$ls180.v:6516$2100_Y + connect \Y $and$ls180.v:6516$2101_Y + end + attribute \src "ls180.v:6533.42-6533.97" + cell $and $and$ls180.v:6533$2103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6533$2103_Y + end + attribute \src "ls180.v:6533.41-6533.148" + cell $and $and$ls180.v:6533$2105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6533$2103_Y + connect \B $eq$ls180.v:6533$2104_Y + connect \Y $and$ls180.v:6533$2105_Y + end + attribute \src "ls180.v:6534.42-6534.100" + cell $and $and$ls180.v:6534$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6534$2106_Y + connect \Y $and$ls180.v:6534$2107_Y + end + attribute \src "ls180.v:6534.41-6534.151" + cell $and $and$ls180.v:6534$2109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6534$2107_Y + connect \B $eq$ls180.v:6534$2108_Y + connect \Y $and$ls180.v:6534$2109_Y + end + attribute \src "ls180.v:6536.42-6536.97" + cell $and $and$ls180.v:6536$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6536$2110_Y + end + attribute \src "ls180.v:6536.41-6536.148" + cell $and $and$ls180.v:6536$2112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6536$2110_Y + connect \B $eq$ls180.v:6536$2111_Y + connect \Y $and$ls180.v:6536$2112_Y + end + attribute \src "ls180.v:6537.42-6537.100" + cell $and $and$ls180.v:6537$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6537$2113_Y + connect \Y $and$ls180.v:6537$2114_Y + end + attribute \src "ls180.v:6537.41-6537.151" + cell $and $and$ls180.v:6537$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6537$2114_Y + connect \B $eq$ls180.v:6537$2115_Y + connect \Y $and$ls180.v:6537$2116_Y + end + attribute \src "ls180.v:6539.40-6539.95" + cell $and $and$ls180.v:6539$2117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6539$2117_Y + end + attribute \src "ls180.v:6539.39-6539.146" + cell $and $and$ls180.v:6539$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6539$2117_Y + connect \B $eq$ls180.v:6539$2118_Y + connect \Y $and$ls180.v:6539$2119_Y + end + attribute \src "ls180.v:6540.40-6540.98" + cell $and $and$ls180.v:6540$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6540$2120_Y + connect \Y $and$ls180.v:6540$2121_Y + end + attribute \src "ls180.v:6540.39-6540.149" + cell $and $and$ls180.v:6540$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6540$2121_Y + connect \B $eq$ls180.v:6540$2122_Y + connect \Y $and$ls180.v:6540$2123_Y + end + attribute \src "ls180.v:6542.39-6542.94" + cell $and $and$ls180.v:6542$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6542$2124_Y + end + attribute \src "ls180.v:6542.38-6542.145" + cell $and $and$ls180.v:6542$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6542$2124_Y + connect \B $eq$ls180.v:6542$2125_Y + connect \Y $and$ls180.v:6542$2126_Y + end + attribute \src "ls180.v:6543.39-6543.97" + cell $and $and$ls180.v:6543$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6543$2127_Y + connect \Y $and$ls180.v:6543$2128_Y + end + attribute \src "ls180.v:6543.38-6543.148" + cell $and $and$ls180.v:6543$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6543$2128_Y + connect \B $eq$ls180.v:6543$2129_Y + connect \Y $and$ls180.v:6543$2130_Y + end + attribute \src "ls180.v:6545.38-6545.93" + cell $and $and$ls180.v:6545$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6545$2131_Y + end + attribute \src "ls180.v:6545.37-6545.144" + cell $and $and$ls180.v:6545$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6545$2131_Y + connect \B $eq$ls180.v:6545$2132_Y + connect \Y $and$ls180.v:6545$2133_Y + end + attribute \src "ls180.v:6546.38-6546.96" + cell $and $and$ls180.v:6546$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6546$2134_Y + connect \Y $and$ls180.v:6546$2135_Y + end + attribute \src "ls180.v:6546.37-6546.147" + cell $and $and$ls180.v:6546$2137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6546$2135_Y + connect \B $eq$ls180.v:6546$2136_Y + connect \Y $and$ls180.v:6546$2137_Y + end + attribute \src "ls180.v:6548.37-6548.92" + cell $and $and$ls180.v:6548$2138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6548$2138_Y + end + attribute \src "ls180.v:6548.36-6548.143" + cell $and $and$ls180.v:6548$2140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6548$2138_Y + connect \B $eq$ls180.v:6548$2139_Y + connect \Y $and$ls180.v:6548$2140_Y + end + attribute \src "ls180.v:6549.37-6549.95" + cell $and $and$ls180.v:6549$2142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6549$2141_Y + connect \Y $and$ls180.v:6549$2142_Y + end + attribute \src "ls180.v:6549.36-6549.146" + cell $and $and$ls180.v:6549$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6549$2142_Y + connect \B $eq$ls180.v:6549$2143_Y + connect \Y $and$ls180.v:6549$2144_Y + end + attribute \src "ls180.v:6551.43-6551.98" + cell $and $and$ls180.v:6551$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6551$2145_Y + end + attribute \src "ls180.v:6551.42-6551.149" + cell $and $and$ls180.v:6551$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6551$2145_Y + connect \B $eq$ls180.v:6551$2146_Y + connect \Y $and$ls180.v:6551$2147_Y + end + attribute \src "ls180.v:6552.43-6552.101" + cell $and $and$ls180.v:6552$2149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6552$2148_Y + connect \Y $and$ls180.v:6552$2149_Y + end + attribute \src "ls180.v:6552.42-6552.152" + cell $and $and$ls180.v:6552$2151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6552$2149_Y + connect \B $eq$ls180.v:6552$2150_Y + connect \Y $and$ls180.v:6552$2151_Y + end + attribute \src "ls180.v:6573.42-6573.97" + cell $and $and$ls180.v:6573$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6573$2154_Y + end + attribute \src "ls180.v:6573.41-6573.148" + cell $and $and$ls180.v:6573$2156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6573$2154_Y + connect \B $eq$ls180.v:6573$2155_Y + connect \Y $and$ls180.v:6573$2156_Y + end + attribute \src "ls180.v:6574.42-6574.100" + cell $and $and$ls180.v:6574$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6574$2157_Y + connect \Y $and$ls180.v:6574$2158_Y + end + attribute \src "ls180.v:6574.41-6574.151" + cell $and $and$ls180.v:6574$2160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6574$2158_Y + connect \B $eq$ls180.v:6574$2159_Y + connect \Y $and$ls180.v:6574$2160_Y + end + attribute \src "ls180.v:6576.42-6576.97" + cell $and $and$ls180.v:6576$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6576$2161_Y + end + attribute \src "ls180.v:6576.41-6576.148" + cell $and $and$ls180.v:6576$2163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6576$2161_Y + connect \B $eq$ls180.v:6576$2162_Y + connect \Y $and$ls180.v:6576$2163_Y + end + attribute \src "ls180.v:6577.42-6577.100" + cell $and $and$ls180.v:6577$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6577$2164_Y + connect \Y $and$ls180.v:6577$2165_Y + end + attribute \src "ls180.v:6577.41-6577.151" + cell $and $and$ls180.v:6577$2167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6577$2165_Y + connect \B $eq$ls180.v:6577$2166_Y + connect \Y $and$ls180.v:6577$2167_Y + end + attribute \src "ls180.v:6579.40-6579.95" + cell $and $and$ls180.v:6579$2168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6579$2168_Y + end + attribute \src "ls180.v:6579.39-6579.146" + cell $and $and$ls180.v:6579$2170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6579$2168_Y + connect \B $eq$ls180.v:6579$2169_Y + connect \Y $and$ls180.v:6579$2170_Y + end + attribute \src "ls180.v:6580.40-6580.98" + cell $and $and$ls180.v:6580$2172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6580$2171_Y + connect \Y $and$ls180.v:6580$2172_Y + end + attribute \src "ls180.v:6580.39-6580.149" + cell $and $and$ls180.v:6580$2174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6580$2172_Y + connect \B $eq$ls180.v:6580$2173_Y + connect \Y $and$ls180.v:6580$2174_Y + end + attribute \src "ls180.v:6582.39-6582.94" + cell $and $and$ls180.v:6582$2175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6582$2175_Y + end + attribute \src "ls180.v:6582.38-6582.145" + cell $and $and$ls180.v:6582$2177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6582$2175_Y + connect \B $eq$ls180.v:6582$2176_Y + connect \Y $and$ls180.v:6582$2177_Y + end + attribute \src "ls180.v:6583.39-6583.97" + cell $and $and$ls180.v:6583$2179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6583$2178_Y + connect \Y $and$ls180.v:6583$2179_Y + end + attribute \src "ls180.v:6583.38-6583.148" + cell $and $and$ls180.v:6583$2181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6583$2179_Y + connect \B $eq$ls180.v:6583$2180_Y + connect \Y $and$ls180.v:6583$2181_Y + end + attribute \src "ls180.v:6585.38-6585.93" + cell $and $and$ls180.v:6585$2182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6585$2182_Y + end + attribute \src "ls180.v:6585.37-6585.144" + cell $and $and$ls180.v:6585$2184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6585$2182_Y + connect \B $eq$ls180.v:6585$2183_Y + connect \Y $and$ls180.v:6585$2184_Y + end + attribute \src "ls180.v:6586.38-6586.96" + cell $and $and$ls180.v:6586$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6586$2185_Y + connect \Y $and$ls180.v:6586$2186_Y + end + attribute \src "ls180.v:6586.37-6586.147" + cell $and $and$ls180.v:6586$2188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6586$2186_Y + connect \B $eq$ls180.v:6586$2187_Y + connect \Y $and$ls180.v:6586$2188_Y + end + attribute \src "ls180.v:6588.37-6588.92" + cell $and $and$ls180.v:6588$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6588$2189_Y + end + attribute \src "ls180.v:6588.36-6588.143" + cell $and $and$ls180.v:6588$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6588$2189_Y + connect \B $eq$ls180.v:6588$2190_Y + connect \Y $and$ls180.v:6588$2191_Y + end + attribute \src "ls180.v:6589.37-6589.95" + cell $and $and$ls180.v:6589$2193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6589$2192_Y + connect \Y $and$ls180.v:6589$2193_Y + end + attribute \src "ls180.v:6589.36-6589.146" + cell $and $and$ls180.v:6589$2195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6589$2193_Y + connect \B $eq$ls180.v:6589$2194_Y + connect \Y $and$ls180.v:6589$2195_Y + end + attribute \src "ls180.v:6591.43-6591.98" + cell $and $and$ls180.v:6591$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6591$2196_Y + end + attribute \src "ls180.v:6591.42-6591.149" + cell $and $and$ls180.v:6591$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6591$2196_Y + connect \B $eq$ls180.v:6591$2197_Y + connect \Y $and$ls180.v:6591$2198_Y + end + attribute \src "ls180.v:6592.43-6592.101" + cell $and $and$ls180.v:6592$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6592$2199_Y + connect \Y $and$ls180.v:6592$2200_Y + end + attribute \src "ls180.v:6592.42-6592.152" + cell $and $and$ls180.v:6592$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6592$2200_Y + connect \B $eq$ls180.v:6592$2201_Y + connect \Y $and$ls180.v:6592$2202_Y + end + attribute \src "ls180.v:6594.46-6594.101" + cell $and $and$ls180.v:6594$2203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6594$2203_Y + end + attribute \src "ls180.v:6594.45-6594.152" + cell $and $and$ls180.v:6594$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6594$2203_Y + connect \B $eq$ls180.v:6594$2204_Y + connect \Y $and$ls180.v:6594$2205_Y + end + attribute \src "ls180.v:6595.46-6595.104" + cell $and $and$ls180.v:6595$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6595$2206_Y + connect \Y $and$ls180.v:6595$2207_Y + end + attribute \src "ls180.v:6595.45-6595.155" + cell $and $and$ls180.v:6595$2209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6595$2207_Y + connect \B $eq$ls180.v:6595$2208_Y + connect \Y $and$ls180.v:6595$2209_Y + end + attribute \src "ls180.v:6597.46-6597.101" + cell $and $and$ls180.v:6597$2210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6597$2210_Y + end + attribute \src "ls180.v:6597.45-6597.152" + cell $and $and$ls180.v:6597$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6597$2210_Y + connect \B $eq$ls180.v:6597$2211_Y + connect \Y $and$ls180.v:6597$2212_Y + end + attribute \src "ls180.v:6598.46-6598.104" + cell $and $and$ls180.v:6598$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6598$2213_Y + connect \Y $and$ls180.v:6598$2214_Y + end + attribute \src "ls180.v:6598.45-6598.155" + cell $and $and$ls180.v:6598$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6598$2214_Y + connect \B $eq$ls180.v:6598$2215_Y + connect \Y $and$ls180.v:6598$2216_Y + end + attribute \src "ls180.v:6621.39-6621.94" + cell $and $and$ls180.v:6621$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6621$2219_Y + end + attribute \src "ls180.v:6621.38-6621.145" + cell $and $and$ls180.v:6621$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6621$2219_Y + connect \B $eq$ls180.v:6621$2220_Y + connect \Y $and$ls180.v:6621$2221_Y + end + attribute \src "ls180.v:6622.39-6622.97" + cell $and $and$ls180.v:6622$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6622$2222_Y + connect \Y $and$ls180.v:6622$2223_Y + end + attribute \src "ls180.v:6622.38-6622.148" + cell $and $and$ls180.v:6622$2225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6622$2223_Y + connect \B $eq$ls180.v:6622$2224_Y + connect \Y $and$ls180.v:6622$2225_Y + end + attribute \src "ls180.v:6624.39-6624.94" + cell $and $and$ls180.v:6624$2226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6624$2226_Y + end + attribute \src "ls180.v:6624.38-6624.145" + cell $and $and$ls180.v:6624$2228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6624$2226_Y + connect \B $eq$ls180.v:6624$2227_Y + connect \Y $and$ls180.v:6624$2228_Y + end + attribute \src "ls180.v:6625.39-6625.97" + cell $and $and$ls180.v:6625$2230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6625$2229_Y + connect \Y $and$ls180.v:6625$2230_Y + end + attribute \src "ls180.v:6625.38-6625.148" + cell $and $and$ls180.v:6625$2232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6625$2230_Y + connect \B $eq$ls180.v:6625$2231_Y + connect \Y $and$ls180.v:6625$2232_Y + end + attribute \src "ls180.v:6627.39-6627.94" + cell $and $and$ls180.v:6627$2233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6627$2233_Y + end + attribute \src "ls180.v:6627.38-6627.145" + cell $and $and$ls180.v:6627$2235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6627$2233_Y + connect \B $eq$ls180.v:6627$2234_Y + connect \Y $and$ls180.v:6627$2235_Y + end + attribute \src "ls180.v:6628.39-6628.97" + cell $and $and$ls180.v:6628$2237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6628$2236_Y + connect \Y $and$ls180.v:6628$2237_Y + end + attribute \src "ls180.v:6628.38-6628.148" + cell $and $and$ls180.v:6628$2239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6628$2237_Y + connect \B $eq$ls180.v:6628$2238_Y + connect \Y $and$ls180.v:6628$2239_Y + end + attribute \src "ls180.v:6630.39-6630.94" + cell $and $and$ls180.v:6630$2240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6630$2240_Y + end + attribute \src "ls180.v:6630.38-6630.145" + cell $and $and$ls180.v:6630$2242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6630$2240_Y + connect \B $eq$ls180.v:6630$2241_Y + connect \Y $and$ls180.v:6630$2242_Y + end + attribute \src "ls180.v:6631.39-6631.97" + cell $and $and$ls180.v:6631$2244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6631$2243_Y + connect \Y $and$ls180.v:6631$2244_Y + end + attribute \src "ls180.v:6631.38-6631.148" + cell $and $and$ls180.v:6631$2246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6631$2244_Y + connect \B $eq$ls180.v:6631$2245_Y + connect \Y $and$ls180.v:6631$2246_Y + end + attribute \src "ls180.v:6633.41-6633.96" + cell $and $and$ls180.v:6633$2247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6633$2247_Y + end + attribute \src "ls180.v:6633.40-6633.147" + cell $and $and$ls180.v:6633$2249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6633$2247_Y + connect \B $eq$ls180.v:6633$2248_Y + connect \Y $and$ls180.v:6633$2249_Y + end + attribute \src "ls180.v:6634.41-6634.99" + cell $and $and$ls180.v:6634$2251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6634$2250_Y + connect \Y $and$ls180.v:6634$2251_Y + end + attribute \src "ls180.v:6634.40-6634.150" + cell $and $and$ls180.v:6634$2253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6634$2251_Y + connect \B $eq$ls180.v:6634$2252_Y + connect \Y $and$ls180.v:6634$2253_Y + end + attribute \src "ls180.v:6636.41-6636.96" + cell $and $and$ls180.v:6636$2254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6636$2254_Y + end + attribute \src "ls180.v:6636.40-6636.147" + cell $and $and$ls180.v:6636$2256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6636$2254_Y + connect \B $eq$ls180.v:6636$2255_Y + connect \Y $and$ls180.v:6636$2256_Y + end + attribute \src "ls180.v:6637.41-6637.99" + cell $and $and$ls180.v:6637$2258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6637$2257_Y + connect \Y $and$ls180.v:6637$2258_Y + end + attribute \src "ls180.v:6637.40-6637.150" + cell $and $and$ls180.v:6637$2260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6637$2258_Y + connect \B $eq$ls180.v:6637$2259_Y + connect \Y $and$ls180.v:6637$2260_Y + end + attribute \src "ls180.v:6639.41-6639.96" + cell $and $and$ls180.v:6639$2261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6639$2261_Y + end + attribute \src "ls180.v:6639.40-6639.147" + cell $and $and$ls180.v:6639$2263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6639$2261_Y + connect \B $eq$ls180.v:6639$2262_Y + connect \Y $and$ls180.v:6639$2263_Y + end + attribute \src "ls180.v:6640.41-6640.99" + cell $and $and$ls180.v:6640$2265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6640$2264_Y + connect \Y $and$ls180.v:6640$2265_Y + end + attribute \src "ls180.v:6640.40-6640.150" + cell $and $and$ls180.v:6640$2267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6640$2265_Y + connect \B $eq$ls180.v:6640$2266_Y + connect \Y $and$ls180.v:6640$2267_Y + end + attribute \src "ls180.v:6642.41-6642.96" + cell $and $and$ls180.v:6642$2268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6642$2268_Y + end + attribute \src "ls180.v:6642.40-6642.147" + cell $and $and$ls180.v:6642$2270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6642$2268_Y + connect \B $eq$ls180.v:6642$2269_Y + connect \Y $and$ls180.v:6642$2270_Y + end + attribute \src "ls180.v:6643.41-6643.99" + cell $and $and$ls180.v:6643$2272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6643$2271_Y + connect \Y $and$ls180.v:6643$2272_Y + end + attribute \src "ls180.v:6643.40-6643.150" + cell $and $and$ls180.v:6643$2274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6643$2272_Y + connect \B $eq$ls180.v:6643$2273_Y + connect \Y $and$ls180.v:6643$2274_Y + end + attribute \src "ls180.v:6645.37-6645.92" + cell $and $and$ls180.v:6645$2275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6645$2275_Y + end + attribute \src "ls180.v:6645.36-6645.143" + cell $and $and$ls180.v:6645$2277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6645$2275_Y + connect \B $eq$ls180.v:6645$2276_Y + connect \Y $and$ls180.v:6645$2277_Y + end + attribute \src "ls180.v:6646.37-6646.95" + cell $and $and$ls180.v:6646$2279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6646$2278_Y + connect \Y $and$ls180.v:6646$2279_Y + end + attribute \src "ls180.v:6646.36-6646.146" + cell $and $and$ls180.v:6646$2281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6646$2279_Y + connect \B $eq$ls180.v:6646$2280_Y + connect \Y $and$ls180.v:6646$2281_Y + end + attribute \src "ls180.v:6648.47-6648.102" + cell $and $and$ls180.v:6648$2282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6648$2282_Y + end + attribute \src "ls180.v:6648.46-6648.153" + cell $and $and$ls180.v:6648$2284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6648$2282_Y + connect \B $eq$ls180.v:6648$2283_Y + connect \Y $and$ls180.v:6648$2284_Y + end + attribute \src "ls180.v:6649.47-6649.105" + cell $and $and$ls180.v:6649$2286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6649$2285_Y + connect \Y $and$ls180.v:6649$2286_Y + end + attribute \src "ls180.v:6649.46-6649.156" + cell $and $and$ls180.v:6649$2288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6649$2286_Y + connect \B $eq$ls180.v:6649$2287_Y + connect \Y $and$ls180.v:6649$2288_Y + end + attribute \src "ls180.v:6651.40-6651.95" + cell $and $and$ls180.v:6651$2289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6651$2289_Y + end + attribute \src "ls180.v:6651.39-6651.147" + cell $and $and$ls180.v:6651$2291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6651$2289_Y + connect \B $eq$ls180.v:6651$2290_Y + connect \Y $and$ls180.v:6651$2291_Y + end + attribute \src "ls180.v:6652.40-6652.98" + cell $and $and$ls180.v:6652$2293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6652$2292_Y + connect \Y $and$ls180.v:6652$2293_Y + end + attribute \src "ls180.v:6652.39-6652.150" + cell $and $and$ls180.v:6652$2295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6652$2293_Y + connect \B $eq$ls180.v:6652$2294_Y + connect \Y $and$ls180.v:6652$2295_Y + end + attribute \src "ls180.v:6654.40-6654.95" + cell $and $and$ls180.v:6654$2296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6654$2296_Y + end + attribute \src "ls180.v:6654.39-6654.147" + cell $and $and$ls180.v:6654$2298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6654$2296_Y + connect \B $eq$ls180.v:6654$2297_Y + connect \Y $and$ls180.v:6654$2298_Y + end + attribute \src "ls180.v:6655.40-6655.98" + cell $and $and$ls180.v:6655$2300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6655$2299_Y + connect \Y $and$ls180.v:6655$2300_Y + end + attribute \src "ls180.v:6655.39-6655.150" + cell $and $and$ls180.v:6655$2302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6655$2300_Y + connect \B $eq$ls180.v:6655$2301_Y + connect \Y $and$ls180.v:6655$2302_Y + end + attribute \src "ls180.v:6657.40-6657.95" + cell $and $and$ls180.v:6657$2303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6657$2303_Y + end + attribute \src "ls180.v:6657.39-6657.147" + cell $and $and$ls180.v:6657$2305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6657$2303_Y + connect \B $eq$ls180.v:6657$2304_Y + connect \Y $and$ls180.v:6657$2305_Y + end + attribute \src "ls180.v:6658.40-6658.98" + cell $and $and$ls180.v:6658$2307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6658$2306_Y + connect \Y $and$ls180.v:6658$2307_Y + end + attribute \src "ls180.v:6658.39-6658.150" + cell $and $and$ls180.v:6658$2309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6658$2307_Y + connect \B $eq$ls180.v:6658$2308_Y + connect \Y $and$ls180.v:6658$2309_Y + end + attribute \src "ls180.v:6660.40-6660.95" + cell $and $and$ls180.v:6660$2310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6660$2310_Y + end + attribute \src "ls180.v:6660.39-6660.147" + cell $and $and$ls180.v:6660$2312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6660$2310_Y + connect \B $eq$ls180.v:6660$2311_Y + connect \Y $and$ls180.v:6660$2312_Y + end + attribute \src "ls180.v:6661.40-6661.98" + cell $and $and$ls180.v:6661$2314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6661$2313_Y + connect \Y $and$ls180.v:6661$2314_Y + end + attribute \src "ls180.v:6661.39-6661.150" + cell $and $and$ls180.v:6661$2316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6661$2314_Y + connect \B $eq$ls180.v:6661$2315_Y + connect \Y $and$ls180.v:6661$2316_Y + end + attribute \src "ls180.v:6663.52-6663.107" + cell $and $and$ls180.v:6663$2317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6663$2317_Y + end + attribute \src "ls180.v:6663.51-6663.159" + cell $and $and$ls180.v:6663$2319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6663$2317_Y + connect \B $eq$ls180.v:6663$2318_Y + connect \Y $and$ls180.v:6663$2319_Y + end + attribute \src "ls180.v:6664.52-6664.110" + cell $and $and$ls180.v:6664$2321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6664$2320_Y + connect \Y $and$ls180.v:6664$2321_Y + end + attribute \src "ls180.v:6664.51-6664.162" + cell $and $and$ls180.v:6664$2323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6664$2321_Y + connect \B $eq$ls180.v:6664$2322_Y + connect \Y $and$ls180.v:6664$2323_Y + end + attribute \src "ls180.v:6666.53-6666.108" + cell $and $and$ls180.v:6666$2324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6666$2324_Y + end + attribute \src "ls180.v:6666.52-6666.160" + cell $and $and$ls180.v:6666$2326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6666$2324_Y + connect \B $eq$ls180.v:6666$2325_Y + connect \Y $and$ls180.v:6666$2326_Y + end + attribute \src "ls180.v:6667.53-6667.111" + cell $and $and$ls180.v:6667$2328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6667$2327_Y + connect \Y $and$ls180.v:6667$2328_Y + end + attribute \src "ls180.v:6667.52-6667.163" + cell $and $and$ls180.v:6667$2330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6667$2328_Y + connect \B $eq$ls180.v:6667$2329_Y + connect \Y $and$ls180.v:6667$2330_Y + end + attribute \src "ls180.v:6669.44-6669.99" + cell $and $and$ls180.v:6669$2331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6669$2331_Y + end + attribute \src "ls180.v:6669.43-6669.151" + cell $and $and$ls180.v:6669$2333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6669$2331_Y + connect \B $eq$ls180.v:6669$2332_Y + connect \Y $and$ls180.v:6669$2333_Y + end + attribute \src "ls180.v:6670.44-6670.102" + cell $and $and$ls180.v:6670$2335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6670$2334_Y + connect \Y $and$ls180.v:6670$2335_Y + end + attribute \src "ls180.v:6670.43-6670.154" + cell $and $and$ls180.v:6670$2337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6670$2335_Y + connect \B $eq$ls180.v:6670$2336_Y + connect \Y $and$ls180.v:6670$2337_Y + end + attribute \src "ls180.v:6689.30-6689.85" + cell $and $and$ls180.v:6689$2339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6689$2339_Y + end + attribute \src "ls180.v:6689.29-6689.136" + cell $and $and$ls180.v:6689$2341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6689$2339_Y + connect \B $eq$ls180.v:6689$2340_Y + connect \Y $and$ls180.v:6689$2341_Y + end + attribute \src "ls180.v:6690.30-6690.88" + cell $and $and$ls180.v:6690$2343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6690$2342_Y + connect \Y $and$ls180.v:6690$2343_Y + end + attribute \src "ls180.v:6690.29-6690.139" + cell $and $and$ls180.v:6690$2345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6690$2343_Y + connect \B $eq$ls180.v:6690$2344_Y + connect \Y $and$ls180.v:6690$2345_Y + end + attribute \src "ls180.v:6692.40-6692.95" + cell $and $and$ls180.v:6692$2346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6692$2346_Y + end + attribute \src "ls180.v:6692.39-6692.146" + cell $and $and$ls180.v:6692$2348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6692$2346_Y + connect \B $eq$ls180.v:6692$2347_Y + connect \Y $and$ls180.v:6692$2348_Y + end + attribute \src "ls180.v:6693.40-6693.98" + cell $and $and$ls180.v:6693$2350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6693$2349_Y + connect \Y $and$ls180.v:6693$2350_Y + end + attribute \src "ls180.v:6693.39-6693.149" + cell $and $and$ls180.v:6693$2352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6693$2350_Y + connect \B $eq$ls180.v:6693$2351_Y + connect \Y $and$ls180.v:6693$2352_Y + end + attribute \src "ls180.v:6695.41-6695.96" + cell $and $and$ls180.v:6695$2353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6695$2353_Y + end + attribute \src "ls180.v:6695.40-6695.147" + cell $and $and$ls180.v:6695$2355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6695$2353_Y + connect \B $eq$ls180.v:6695$2354_Y + connect \Y $and$ls180.v:6695$2355_Y + end + attribute \src "ls180.v:6696.41-6696.99" + cell $and $and$ls180.v:6696$2357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6696$2356_Y + connect \Y $and$ls180.v:6696$2357_Y + end + attribute \src "ls180.v:6696.40-6696.150" + cell $and $and$ls180.v:6696$2359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6696$2357_Y + connect \B $eq$ls180.v:6696$2358_Y + connect \Y $and$ls180.v:6696$2359_Y + end + attribute \src "ls180.v:6698.45-6698.100" + cell $and $and$ls180.v:6698$2360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6698$2360_Y + end + attribute \src "ls180.v:6698.44-6698.151" + cell $and $and$ls180.v:6698$2362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6698$2360_Y + connect \B $eq$ls180.v:6698$2361_Y + connect \Y $and$ls180.v:6698$2362_Y + end + attribute \src "ls180.v:6699.45-6699.103" + cell $and $and$ls180.v:6699$2364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6699$2363_Y + connect \Y $and$ls180.v:6699$2364_Y + end + attribute \src "ls180.v:6699.44-6699.154" + cell $and $and$ls180.v:6699$2366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6699$2364_Y + connect \B $eq$ls180.v:6699$2365_Y + connect \Y $and$ls180.v:6699$2366_Y + end + attribute \src "ls180.v:6701.46-6701.101" + cell $and $and$ls180.v:6701$2367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6701$2367_Y + end + attribute \src "ls180.v:6701.45-6701.152" + cell $and $and$ls180.v:6701$2369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6701$2367_Y + connect \B $eq$ls180.v:6701$2368_Y + connect \Y $and$ls180.v:6701$2369_Y + end + attribute \src "ls180.v:6702.46-6702.104" + cell $and $and$ls180.v:6702$2371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6702$2370_Y + connect \Y $and$ls180.v:6702$2371_Y + end + attribute \src "ls180.v:6702.45-6702.155" + cell $and $and$ls180.v:6702$2373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6702$2371_Y + connect \B $eq$ls180.v:6702$2372_Y + connect \Y $and$ls180.v:6702$2373_Y + end + attribute \src "ls180.v:6704.44-6704.99" + cell $and $and$ls180.v:6704$2374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6704$2374_Y + end + attribute \src "ls180.v:6704.43-6704.150" + cell $and $and$ls180.v:6704$2376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6704$2374_Y + connect \B $eq$ls180.v:6704$2375_Y + connect \Y $and$ls180.v:6704$2376_Y + end + attribute \src "ls180.v:6705.44-6705.102" + cell $and $and$ls180.v:6705$2378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6705$2377_Y + connect \Y $and$ls180.v:6705$2378_Y + end + attribute \src "ls180.v:6705.43-6705.153" + cell $and $and$ls180.v:6705$2380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6705$2378_Y + connect \B $eq$ls180.v:6705$2379_Y + connect \Y $and$ls180.v:6705$2380_Y + end + attribute \src "ls180.v:6707.41-6707.96" + cell $and $and$ls180.v:6707$2381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6707$2381_Y + end + attribute \src "ls180.v:6707.40-6707.147" + cell $and $and$ls180.v:6707$2383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6707$2381_Y + connect \B $eq$ls180.v:6707$2382_Y + connect \Y $and$ls180.v:6707$2383_Y + end + attribute \src "ls180.v:6708.41-6708.99" + cell $and $and$ls180.v:6708$2385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6708$2384_Y + connect \Y $and$ls180.v:6708$2385_Y + end + attribute \src "ls180.v:6708.40-6708.150" + cell $and $and$ls180.v:6708$2387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6708$2385_Y + connect \B $eq$ls180.v:6708$2386_Y + connect \Y $and$ls180.v:6708$2387_Y + end + attribute \src "ls180.v:6710.40-6710.95" + cell $and $and$ls180.v:6710$2388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6710$2388_Y + end + attribute \src "ls180.v:6710.39-6710.146" + cell $and $and$ls180.v:6710$2390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6710$2388_Y + connect \B $eq$ls180.v:6710$2389_Y + connect \Y $and$ls180.v:6710$2390_Y + end + attribute \src "ls180.v:6711.40-6711.98" + cell $and $and$ls180.v:6711$2392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6711$2391_Y + connect \Y $and$ls180.v:6711$2392_Y + end + attribute \src "ls180.v:6711.39-6711.149" + cell $and $and$ls180.v:6711$2394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6711$2392_Y + connect \B $eq$ls180.v:6711$2393_Y + connect \Y $and$ls180.v:6711$2394_Y + end + attribute \src "ls180.v:6723.46-6723.101" + cell $and $and$ls180.v:6723$2396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6723$2396_Y + end + attribute \src "ls180.v:6723.45-6723.152" + cell $and $and$ls180.v:6723$2398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6723$2396_Y + connect \B $eq$ls180.v:6723$2397_Y + connect \Y $and$ls180.v:6723$2398_Y + end + attribute \src "ls180.v:6724.46-6724.104" + cell $and $and$ls180.v:6724$2400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6724$2399_Y + connect \Y $and$ls180.v:6724$2400_Y + end + attribute \src "ls180.v:6724.45-6724.155" + cell $and $and$ls180.v:6724$2402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6724$2400_Y + connect \B $eq$ls180.v:6724$2401_Y + connect \Y $and$ls180.v:6724$2402_Y + end + attribute \src "ls180.v:6726.46-6726.101" + cell $and $and$ls180.v:6726$2403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6726$2403_Y + end + attribute \src "ls180.v:6726.45-6726.152" + cell $and $and$ls180.v:6726$2405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6726$2403_Y + connect \B $eq$ls180.v:6726$2404_Y + connect \Y $and$ls180.v:6726$2405_Y + end + attribute \src "ls180.v:6727.46-6727.104" + cell $and $and$ls180.v:6727$2407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6727$2406_Y + connect \Y $and$ls180.v:6727$2407_Y + end + attribute \src "ls180.v:6727.45-6727.155" + cell $and $and$ls180.v:6727$2409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6727$2407_Y + connect \B $eq$ls180.v:6727$2408_Y + connect \Y $and$ls180.v:6727$2409_Y + end + attribute \src "ls180.v:6729.46-6729.101" + cell $and $and$ls180.v:6729$2410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6729$2410_Y + end + attribute \src "ls180.v:6729.45-6729.152" + cell $and $and$ls180.v:6729$2412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6729$2410_Y + connect \B $eq$ls180.v:6729$2411_Y + connect \Y $and$ls180.v:6729$2412_Y + end + attribute \src "ls180.v:6730.46-6730.104" + cell $and $and$ls180.v:6730$2414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6730$2413_Y + connect \Y $and$ls180.v:6730$2414_Y + end + attribute \src "ls180.v:6730.45-6730.155" + cell $and $and$ls180.v:6730$2416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6730$2414_Y + connect \B $eq$ls180.v:6730$2415_Y + connect \Y $and$ls180.v:6730$2416_Y + end + attribute \src "ls180.v:6732.46-6732.101" + cell $and $and$ls180.v:6732$2417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6732$2417_Y + end + attribute \src "ls180.v:6732.45-6732.152" + cell $and $and$ls180.v:6732$2419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6732$2417_Y + connect \B $eq$ls180.v:6732$2418_Y + connect \Y $and$ls180.v:6732$2419_Y + end + attribute \src "ls180.v:6733.46-6733.104" + cell $and $and$ls180.v:6733$2421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6733$2420_Y + connect \Y $and$ls180.v:6733$2421_Y + end + attribute \src "ls180.v:6733.45-6733.155" + cell $and $and$ls180.v:6733$2423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6733$2421_Y + connect \B $eq$ls180.v:6733$2422_Y + connect \Y $and$ls180.v:6733$2423_Y + end + attribute \src "ls180.v:7114.109-7114.178" + cell $and $and$ls180.v:7114$2461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:7114$2460_Y + connect \Y $and$ls180.v:7114$2461_Y + end + attribute \src "ls180.v:7114.184-7114.253" + cell $and $and$ls180.v:7114$2464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:7114$2463_Y + connect \Y $and$ls180.v:7114$2464_Y + end + attribute \src "ls180.v:7114.259-7114.328" + cell $and $and$ls180.v:7114$2467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:7114$2466_Y + connect \Y $and$ls180.v:7114$2467_Y + end + attribute \src "ls180.v:7114.40-7114.331" + cell $and $and$ls180.v:7114$2470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7114$2459_Y + connect \B $not$ls180.v:7114$2469_Y + connect \Y $and$ls180.v:7114$2470_Y + end + attribute \src "ls180.v:7114.39-7114.354" + cell $and $and$ls180.v:7114$2471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7114$2470_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7114$2471_Y + end + attribute \src "ls180.v:7138.109-7138.178" + cell $and $and$ls180.v:7138$2477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:7138$2476_Y + connect \Y $and$ls180.v:7138$2477_Y + end + attribute \src "ls180.v:7138.184-7138.253" + cell $and $and$ls180.v:7138$2480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:7138$2479_Y + connect \Y $and$ls180.v:7138$2480_Y + end + attribute \src "ls180.v:7138.259-7138.328" + cell $and $and$ls180.v:7138$2483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:7138$2482_Y + connect \Y $and$ls180.v:7138$2483_Y + end + attribute \src "ls180.v:7138.40-7138.331" + cell $and $and$ls180.v:7138$2486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7138$2475_Y + connect \B $not$ls180.v:7138$2485_Y + connect \Y $and$ls180.v:7138$2486_Y + end + attribute \src "ls180.v:7138.39-7138.354" + cell $and $and$ls180.v:7138$2487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7138$2486_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7138$2487_Y + end + attribute \src "ls180.v:7162.109-7162.178" + cell $and $and$ls180.v:7162$2493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:7162$2492_Y + connect \Y $and$ls180.v:7162$2493_Y + end + attribute \src "ls180.v:7162.184-7162.253" + cell $and $and$ls180.v:7162$2496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:7162$2495_Y + connect \Y $and$ls180.v:7162$2496_Y + end + attribute \src "ls180.v:7162.259-7162.328" + cell $and $and$ls180.v:7162$2499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:7162$2498_Y + connect \Y $and$ls180.v:7162$2499_Y + end + attribute \src "ls180.v:7162.40-7162.331" + cell $and $and$ls180.v:7162$2502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7162$2491_Y + connect \B $not$ls180.v:7162$2501_Y + connect \Y $and$ls180.v:7162$2502_Y + end + attribute \src "ls180.v:7162.39-7162.354" + cell $and $and$ls180.v:7162$2503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7162$2502_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7162$2503_Y + end + attribute \src "ls180.v:7186.109-7186.178" + cell $and $and$ls180.v:7186$2509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:7186$2508_Y + connect \Y $and$ls180.v:7186$2509_Y + end + attribute \src "ls180.v:7186.184-7186.253" + cell $and $and$ls180.v:7186$2512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:7186$2511_Y + connect \Y $and$ls180.v:7186$2512_Y + end + attribute \src "ls180.v:7186.259-7186.328" + cell $and $and$ls180.v:7186$2515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:7186$2514_Y + connect \Y $and$ls180.v:7186$2515_Y + end + attribute \src "ls180.v:7186.40-7186.331" + cell $and $and$ls180.v:7186$2518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7186$2507_Y + connect \B $not$ls180.v:7186$2517_Y + connect \Y $and$ls180.v:7186$2518_Y + end + attribute \src "ls180.v:7186.39-7186.354" + cell $and $and$ls180.v:7186$2519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7186$2518_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7186$2519_Y + end + attribute \src "ls180.v:7391.39-7391.104" + cell $and $and$ls180.v:7391$2531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7391$2531_Y + end + attribute \src "ls180.v:7391.38-7391.145" + cell $and $and$ls180.v:7391$2532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7391$2531_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7391$2532_Y + end + attribute \src "ls180.v:7394.39-7394.104" + cell $and $and$ls180.v:7394$2533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7394$2533_Y + end + attribute \src "ls180.v:7394.38-7394.145" + cell $and $and$ls180.v:7394$2534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7394$2533_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7394$2534_Y + end + attribute \src "ls180.v:7397.39-7397.82" + cell $and $and$ls180.v:7397$2535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7397$2535_Y + end + attribute \src "ls180.v:7397.38-7397.112" + cell $and $and$ls180.v:7397$2536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7397$2535_Y + connect \B \main_sdram_cmd_payload_cas + connect \Y $and$ls180.v:7397$2536_Y + end + attribute \src "ls180.v:7408.39-7408.104" + cell $and $and$ls180.v:7408$2538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7408$2538_Y + end + attribute \src "ls180.v:7408.38-7408.145" + cell $and $and$ls180.v:7408$2539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7408$2538_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7408$2539_Y + end + attribute \src "ls180.v:7411.39-7411.104" + cell $and $and$ls180.v:7411$2540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7411$2540_Y + end + attribute \src "ls180.v:7411.38-7411.145" + cell $and $and$ls180.v:7411$2541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7411$2540_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7411$2541_Y + end + attribute \src "ls180.v:7414.39-7414.82" + cell $and $and$ls180.v:7414$2542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7414$2542_Y + end + attribute \src "ls180.v:7414.38-7414.112" + cell $and $and$ls180.v:7414$2543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7414$2542_Y + connect \B \main_sdram_cmd_payload_ras + connect \Y $and$ls180.v:7414$2543_Y + end + attribute \src "ls180.v:7425.39-7425.104" + cell $and $and$ls180.v:7425$2545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7425$2545_Y + end + attribute \src "ls180.v:7425.38-7425.144" + cell $and $and$ls180.v:7425$2546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7425$2545_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7425$2546_Y + end + attribute \src "ls180.v:7428.39-7428.104" + cell $and $and$ls180.v:7428$2547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7428$2547_Y + end + attribute \src "ls180.v:7428.38-7428.144" + cell $and $and$ls180.v:7428$2548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7428$2547_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7428$2548_Y + end + attribute \src "ls180.v:7431.39-7431.82" + cell $and $and$ls180.v:7431$2549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7431$2549_Y + end + attribute \src "ls180.v:7431.38-7431.111" + cell $and $and$ls180.v:7431$2550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7431$2549_Y + connect \B \main_sdram_cmd_payload_we + connect \Y $and$ls180.v:7431$2550_Y + end + attribute \src "ls180.v:7442.39-7442.104" + cell $and $and$ls180.v:7442$2552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7442$2552_Y + end + attribute \src "ls180.v:7442.38-7442.149" + cell $and $and$ls180.v:7442$2553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7442$2552_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7442$2553_Y + end + attribute \src "ls180.v:7445.39-7445.104" + cell $and $and$ls180.v:7445$2554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7445$2554_Y + end + attribute \src "ls180.v:7445.38-7445.149" + cell $and $and$ls180.v:7445$2555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7445$2554_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7445$2555_Y + end + attribute \src "ls180.v:7448.39-7448.82" + cell $and $and$ls180.v:7448$2556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7448$2556_Y + end + attribute \src "ls180.v:7448.38-7448.116" + cell $and $and$ls180.v:7448$2557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7448$2556_Y + connect \B \main_sdram_cmd_payload_is_read + connect \Y $and$ls180.v:7448$2557_Y + end + attribute \src "ls180.v:7459.39-7459.104" + cell $and $and$ls180.v:7459$2559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7459$2559_Y + end + attribute \src "ls180.v:7459.38-7459.150" + cell $and $and$ls180.v:7459$2560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7459$2559_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7459$2560_Y + end + attribute \src "ls180.v:7462.39-7462.104" + cell $and $and$ls180.v:7462$2561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7462$2561_Y + end + attribute \src "ls180.v:7462.38-7462.150" + cell $and $and$ls180.v:7462$2562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7462$2561_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7462$2562_Y + end + attribute \src "ls180.v:7465.39-7465.82" + cell $and $and$ls180.v:7465$2563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7465$2563_Y + end + attribute \src "ls180.v:7465.38-7465.117" + cell $and $and$ls180.v:7465$2564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7465$2563_Y + connect \B \main_sdram_cmd_payload_is_write + connect \Y $and$ls180.v:7465$2564_Y + end + attribute \src "ls180.v:7687.17-7687.67" + cell $and $and$ls180.v:7687$2572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7687$2571_Y + connect \B \main_sdphy_sdpads_clk + connect \Y $and$ls180.v:7687$2572_Y + end + attribute \src "ls180.v:7766.8-7766.67" + cell $and $and$ls180.v:7766$2603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:7766$2603_Y + end + attribute \src "ls180.v:7766.7-7766.102" + cell $and $and$ls180.v:7766$2605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7766$2603_Y + connect \B $not$ls180.v:7766$2604_Y + connect \Y $and$ls180.v:7766$2605_Y + end + attribute \src "ls180.v:7785.7-7785.75" + cell $and $and$ls180.v:7785$2609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7785$2608_Y + connect \B \main_libresocsim_zero_old_trigger + connect \Y $and$ls180.v:7785$2609_Y + end + attribute \src "ls180.v:7789.8-7789.65" + cell $and $and$ls180.v:7789$2610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:7789$2610_Y + end + attribute \src "ls180.v:7789.7-7789.99" + cell $and $and$ls180.v:7789$2612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7789$2610_Y + connect \B $not$ls180.v:7789$2611_Y + connect \Y $and$ls180.v:7789$2612_Y + end + attribute \src "ls180.v:7793.8-7793.65" + cell $and $and$ls180.v:7793$2613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:7793$2613_Y + end + attribute \src "ls180.v:7793.7-7793.99" + cell $and $and$ls180.v:7793$2615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7793$2613_Y + connect \B $not$ls180.v:7793$2614_Y + connect \Y $and$ls180.v:7793$2615_Y + end + attribute \src "ls180.v:7797.8-7797.65" + cell $and $and$ls180.v:7797$2616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:7797$2616_Y + end + attribute \src "ls180.v:7797.7-7797.99" + cell $and $and$ls180.v:7797$2618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7797$2616_Y + connect \B $not$ls180.v:7797$2617_Y + connect \Y $and$ls180.v:7797$2618_Y + end + attribute \src "ls180.v:7801.8-7801.65" + cell $and $and$ls180.v:7801$2619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:7801$2619_Y + end + attribute \src "ls180.v:7801.7-7801.99" + cell $and $and$ls180.v:7801$2621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7801$2619_Y + connect \B $not$ls180.v:7801$2620_Y + connect \Y $and$ls180.v:7801$2621_Y + end + attribute \src "ls180.v:7809.7-7809.56" + cell $and $and$ls180.v:7809$2623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_wait + connect \B $not$ls180.v:7809$2622_Y + connect \Y $and$ls180.v:7809$2623_Y + end + attribute \src "ls180.v:7837.7-7837.75" + cell $and $and$ls180.v:7837$2630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start1 + connect \B $eq$ls180.v:7837$2629_Y + connect \Y $and$ls180.v:7837$2630_Y + end + attribute \src "ls180.v:7879.8-7879.131" + cell $and $and$ls180.v:7879$2636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7879$2636_Y + end + attribute \src "ls180.v:7879.7-7879.190" + cell $and $and$ls180.v:7879$2638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7879$2636_Y + connect \B $not$ls180.v:7879$2637_Y + connect \Y $and$ls180.v:7879$2638_Y + end + attribute \src "ls180.v:7885.8-7885.131" + cell $and $and$ls180.v:7885$2641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7885$2641_Y + end + attribute \src "ls180.v:7885.7-7885.190" + cell $and $and$ls180.v:7885$2643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7885$2641_Y + connect \B $not$ls180.v:7885$2642_Y + connect \Y $and$ls180.v:7885$2643_Y + end + attribute \src "ls180.v:7925.8-7925.131" + cell $and $and$ls180.v:7925$2652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7925$2652_Y + end + attribute \src "ls180.v:7925.7-7925.190" + cell $and $and$ls180.v:7925$2654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7925$2652_Y + connect \B $not$ls180.v:7925$2653_Y + connect \Y $and$ls180.v:7925$2654_Y + end + attribute \src "ls180.v:7931.8-7931.131" + cell $and $and$ls180.v:7931$2657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7931$2657_Y + end + attribute \src "ls180.v:7931.7-7931.190" + cell $and $and$ls180.v:7931$2659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7931$2657_Y + connect \B $not$ls180.v:7931$2658_Y + connect \Y $and$ls180.v:7931$2659_Y + end + attribute \src "ls180.v:7971.8-7971.131" + cell $and $and$ls180.v:7971$2668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7971$2668_Y + end + attribute \src "ls180.v:7971.7-7971.190" + cell $and $and$ls180.v:7971$2670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7971$2668_Y + connect \B $not$ls180.v:7971$2669_Y + connect \Y $and$ls180.v:7971$2670_Y + end + attribute \src "ls180.v:7977.8-7977.131" + cell $and $and$ls180.v:7977$2673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7977$2673_Y + end + attribute \src "ls180.v:7977.7-7977.190" + cell $and $and$ls180.v:7977$2675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7977$2673_Y + connect \B $not$ls180.v:7977$2674_Y + connect \Y $and$ls180.v:7977$2675_Y + end + attribute \src "ls180.v:8017.8-8017.131" + cell $and $and$ls180.v:8017$2684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:8017$2684_Y + end + attribute \src "ls180.v:8017.7-8017.190" + cell $and $and$ls180.v:8017$2686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8017$2684_Y + connect \B $not$ls180.v:8017$2685_Y + connect \Y $and$ls180.v:8017$2686_Y + end + attribute \src "ls180.v:8023.8-8023.131" + cell $and $and$ls180.v:8023$2689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:8023$2689_Y + end + attribute \src "ls180.v:8023.7-8023.190" + cell $and $and$ls180.v:8023$2691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8023$2689_Y + connect \B $not$ls180.v:8023$2690_Y + connect \Y $and$ls180.v:8023$2691_Y + end + attribute \src "ls180.v:8220.48-8220.124" + cell $and $and$ls180.v:8220$2716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8220$2715_Y + connect \B \main_sdram_interface_bank0_wdata_ready + connect \Y $and$ls180.v:8220$2716_Y + end + attribute \src "ls180.v:8220.130-8220.206" + cell $and $and$ls180.v:8220$2719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8220$2718_Y + connect \B \main_sdram_interface_bank1_wdata_ready + connect \Y $and$ls180.v:8220$2719_Y + end + attribute \src "ls180.v:8220.212-8220.288" + cell $and $and$ls180.v:8220$2722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8220$2721_Y + connect \B \main_sdram_interface_bank2_wdata_ready + connect \Y $and$ls180.v:8220$2722_Y + end + attribute \src "ls180.v:8220.294-8220.370" + cell $and $and$ls180.v:8220$2725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8220$2724_Y + connect \B \main_sdram_interface_bank3_wdata_ready + connect \Y $and$ls180.v:8220$2725_Y + end + attribute \src "ls180.v:8221.49-8221.125" + cell $and $and$ls180.v:8221$2728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8221$2727_Y + connect \B \main_sdram_interface_bank0_rdata_valid + connect \Y $and$ls180.v:8221$2728_Y + end + attribute \src "ls180.v:8221.131-8221.207" + cell $and $and$ls180.v:8221$2731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8221$2730_Y + connect \B \main_sdram_interface_bank1_rdata_valid + connect \Y $and$ls180.v:8221$2731_Y + end + attribute \src "ls180.v:8221.213-8221.289" + cell $and $and$ls180.v:8221$2734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8221$2733_Y + connect \B \main_sdram_interface_bank2_rdata_valid + connect \Y $and$ls180.v:8221$2734_Y + end + attribute \src "ls180.v:8221.295-8221.371" + cell $and $and$ls180.v:8221$2737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8221$2736_Y + connect \B \main_sdram_interface_bank3_rdata_valid + connect \Y $and$ls180.v:8221$2737_Y + end + attribute \src "ls180.v:8240.8-8240.49" + cell $and $and$ls180.v:8240$2740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:8240$2740_Y + end + attribute \src "ls180.v:8243.8-8243.53" + cell $and $and$ls180.v:8243$2741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:8243$2741_Y + end + attribute \src "ls180.v:8248.8-8248.59" + cell $and $and$ls180.v:8248$2743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_valid + connect \B $not$ls180.v:8248$2742_Y + connect \Y $and$ls180.v:8248$2743_Y + end + attribute \src "ls180.v:8248.7-8248.90" + cell $and $and$ls180.v:8248$2745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8248$2743_Y + connect \B $not$ls180.v:8248$2744_Y + connect \Y $and$ls180.v:8248$2745_Y + end + attribute \src "ls180.v:8254.8-8254.59" + cell $and $and$ls180.v:8254$2746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_uart_clk_txen + connect \B \main_uart_phy_tx_busy + connect \Y $and$ls180.v:8254$2746_Y + end + attribute \src "ls180.v:8278.8-8278.48" + cell $and $and$ls180.v:8278$2753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8278$2752_Y + connect \B \main_uart_phy_rx_r + connect \Y $and$ls180.v:8278$2753_Y + end + attribute \src "ls180.v:8311.7-8311.57" + cell $and $and$ls180.v:8311$2759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8311$2758_Y + connect \B \main_uart_tx_old_trigger + connect \Y $and$ls180.v:8311$2759_Y + end + attribute \src "ls180.v:8318.7-8318.57" + cell $and $and$ls180.v:8318$2761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8318$2760_Y + connect \B \main_uart_rx_old_trigger + connect \Y $and$ls180.v:8318$2761_Y + end + attribute \src "ls180.v:8328.8-8328.75" + cell $and $and$ls180.v:8328$2762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8328$2762_Y + end + attribute \src "ls180.v:8328.7-8328.107" + cell $and $and$ls180.v:8328$2764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8328$2762_Y + connect \B $not$ls180.v:8328$2763_Y + connect \Y $and$ls180.v:8328$2764_Y + end + attribute \src "ls180.v:8334.8-8334.75" + cell $and $and$ls180.v:8334$2767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8334$2767_Y + end + attribute \src "ls180.v:8334.7-8334.107" + cell $and $and$ls180.v:8334$2769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8334$2767_Y + connect \B $not$ls180.v:8334$2768_Y + connect \Y $and$ls180.v:8334$2769_Y + end + attribute \src "ls180.v:8350.8-8350.75" + cell $and $and$ls180.v:8350$2773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8350$2773_Y + end + attribute \src "ls180.v:8350.7-8350.107" + cell $and $and$ls180.v:8350$2775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8350$2773_Y + connect \B $not$ls180.v:8350$2774_Y + connect \Y $and$ls180.v:8350$2775_Y + end + attribute \src "ls180.v:8356.8-8356.75" + cell $and $and$ls180.v:8356$2778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8356$2778_Y + end + attribute \src "ls180.v:8356.7-8356.107" + cell $and $and$ls180.v:8356$2780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8356$2778_Y + connect \B $not$ls180.v:8356$2779_Y + connect \Y $and$ls180.v:8356$2780_Y + end + attribute \src "ls180.v:8504.7-8504.96" + cell $and $and$ls180.v:8504$2808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_source_valid + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $and$ls180.v:8504$2808_Y + end + attribute \src "ls180.v:8505.8-8505.93" + cell $and $and$ls180.v:8505$2809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8505$2809_Y + end + attribute \src "ls180.v:8513.8-8513.93" + cell $and $and$ls180.v:8513$2810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8513$2810_Y + end + attribute \src "ls180.v:8585.7-8585.98" + cell $and $and$ls180.v:8585$2820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_source_valid + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $and$ls180.v:8585$2820_Y + end + attribute \src "ls180.v:8586.8-8586.95" + cell $and $and$ls180.v:8586$2821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8586$2821_Y + end + attribute \src "ls180.v:8594.8-8594.95" + cell $and $and$ls180.v:8594$2822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8594$2822_Y + end + attribute \src "ls180.v:8664.7-8664.100" + cell $and $and$ls180.v:8664$2832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_source_valid + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $and$ls180.v:8664$2832_Y + end + attribute \src "ls180.v:8665.8-8665.97" + cell $and $and$ls180.v:8665$2833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8665$2833_Y + end + attribute \src "ls180.v:8673.8-8673.97" + cell $and $and$ls180.v:8673$2834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8673$2834_Y + end + attribute \src "ls180.v:8764.7-8764.82" + cell $and $and$ls180.v:8764$2840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8764$2840_Y + end + attribute \src "ls180.v:8767.7-8767.82" + cell $and $and$ls180.v:8767$2841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8767$2841_Y + end + attribute \src "ls180.v:8770.7-8770.82" + cell $and $and$ls180.v:8770$2842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8770$2842_Y + end + attribute \src "ls180.v:8773.7-8773.82" + cell $and $and$ls180.v:8773$2843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8773$2843_Y + end + attribute \src "ls180.v:8776.7-8776.82" + cell $and $and$ls180.v:8776$2844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8776$2844_Y + end + attribute \src "ls180.v:8781.7-8781.82" + cell $and $and$ls180.v:8781$2845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8781$2845_Y + end + attribute \src "ls180.v:8786.7-8786.82" + cell $and $and$ls180.v:8786$2846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8786$2846_Y + end + attribute \src "ls180.v:8791.7-8791.82" + cell $and $and$ls180.v:8791$2847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8791$2847_Y + end + attribute \src "ls180.v:8796.7-8796.82" + cell $and $and$ls180.v:8796$2848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8796$2848_Y + end + attribute \src "ls180.v:8861.8-8861.83" + cell $and $and$ls180.v:8861$2851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8861$2851_Y + end + attribute \src "ls180.v:8861.7-8861.119" + cell $and $and$ls180.v:8861$2853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8861$2851_Y + connect \B $not$ls180.v:8861$2852_Y + connect \Y $and$ls180.v:8861$2853_Y + end + attribute \src "ls180.v:8867.8-8867.83" + cell $and $and$ls180.v:8867$2856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8867$2856_Y + end + attribute \src "ls180.v:8867.7-8867.119" + cell $and $and$ls180.v:8867$2858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8867$2856_Y + connect \B $not$ls180.v:8867$2857_Y + connect \Y $and$ls180.v:8867$2858_Y + end + attribute \src "ls180.v:8887.7-8887.88" + cell $and $and$ls180.v:8887$2865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_source_valid + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $and$ls180.v:8887$2865_Y + end + attribute \src "ls180.v:8888.8-8888.85" + cell $and $and$ls180.v:8888$2866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8888$2866_Y + end + attribute \src "ls180.v:8896.8-8896.85" + cell $and $and$ls180.v:8896$2867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8896$2867_Y + end + attribute \src "ls180.v:8952.7-8952.88" + cell $and $and$ls180.v:8952$2871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_source_valid + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:8952$2871_Y + end + attribute \src "ls180.v:8959.8-8959.83" + cell $and $and$ls180.v:8959$2873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8959$2873_Y + end + attribute \src "ls180.v:8959.7-8959.119" + cell $and $and$ls180.v:8959$2875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8959$2873_Y + connect \B $not$ls180.v:8959$2874_Y + connect \Y $and$ls180.v:8959$2875_Y + end + attribute \src "ls180.v:8965.8-8965.83" + cell $and $and$ls180.v:8965$2878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8965$2878_Y + end + attribute \src "ls180.v:8965.7-8965.119" + cell $and $and$ls180.v:8965$2880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8965$2878_Y + connect \B $not$ls180.v:8965$2879_Y + connect \Y $and$ls180.v:8965$2880_Y + end + attribute \src "ls180.v:2927.30-2927.76" + cell $eq $eq$ls180.v:2927$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_icp_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2927$54_Y + end + attribute \src "ls180.v:2934.11-2934.42" + cell $eq $eq$ls180.v:2934$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2934$59_Y + end + attribute \src "ls180.v:2987.30-2987.76" + cell $eq $eq$ls180.v:2987$65 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_ics_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2987$65_Y + end + attribute \src "ls180.v:2994.11-2994.42" + cell $eq $eq$ls180.v:2994$70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2994$70_Y + end + attribute \src "ls180.v:3047.33-3047.58" + cell $eq $eq$ls180.v:3047$76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_sel + connect \B 1'0 + connect \Y $eq$ls180.v:3047$76_Y + end + attribute \src "ls180.v:3054.11-3054.45" + cell $eq $eq$ls180.v:3054$81 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_counter + connect \B 1'1 + connect \Y $eq$ls180.v:3054$81_Y + end + attribute \src "ls180.v:3300.34-3300.65" + cell $eq $eq$ls180.v:3300$221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$ls180.v:3300$221_Y + end + attribute \src "ls180.v:3304.68-3304.102" + cell $eq $eq$ls180.v:3304$224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$ls180.v:3304$224_Y + end + attribute \src "ls180.v:3348.43-3348.134" + cell $eq $eq$ls180.v:3348$229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3348$229_Y + end + attribute \src "ls180.v:3365.47-3365.88" + cell $eq $eq$ls180.v:3365$242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3365$242_Y + end + attribute \src "ls180.v:3505.43-3505.134" + cell $eq $eq$ls180.v:3505$259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3505$259_Y + end + attribute \src "ls180.v:3522.47-3522.88" + cell $eq $eq$ls180.v:3522$272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3522$272_Y + end + attribute \src "ls180.v:3662.43-3662.134" + cell $eq $eq$ls180.v:3662$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3662$289_Y + end + attribute \src "ls180.v:3679.47-3679.88" + cell $eq $eq$ls180.v:3679$302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3679$302_Y + end + attribute \src "ls180.v:3819.43-3819.134" + cell $eq $eq$ls180.v:3819$319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3819$319_Y + end + attribute \src "ls180.v:3836.47-3836.88" + cell $eq $eq$ls180.v:3836$332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3836$332_Y + end + attribute \src "ls180.v:3973.32-3973.56" + cell $eq $eq$ls180.v:3973$379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time0 + connect \B 1'0 + connect \Y $eq$ls180.v:3973$379_Y + end + attribute \src "ls180.v:3974.32-3974.56" + cell $eq $eq$ls180.v:3974$380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time1 + connect \B 1'0 + connect \Y $eq$ls180.v:3974$380_Y + end + attribute \src "ls180.v:3985.339-3985.418" + cell $eq $eq$ls180.v:3985$394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3985$394_Y + end + attribute \src "ls180.v:3985.423-3985.504" + cell $eq $eq$ls180.v:3985$395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3985$395_Y + end + attribute \src "ls180.v:3986.339-3986.418" + cell $eq $eq$ls180.v:3986$407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3986$407_Y + end + attribute \src "ls180.v:3986.423-3986.504" + cell $eq $eq$ls180.v:3986$408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3986$408_Y + end + attribute \src "ls180.v:3987.339-3987.418" + cell $eq $eq$ls180.v:3987$420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3987$420_Y + end + attribute \src "ls180.v:3987.423-3987.504" + cell $eq $eq$ls180.v:3987$421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3987$421_Y + end + attribute \src "ls180.v:3988.339-3988.418" + cell $eq $eq$ls180.v:3988$433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3988$433_Y + end + attribute \src "ls180.v:3988.423-3988.504" + cell $eq $eq$ls180.v:3988$434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3988$434_Y + end + attribute \src "ls180.v:4018.339-4018.418" + cell $eq $eq$ls180.v:4018$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:4018$452_Y + end + attribute \src "ls180.v:4018.423-4018.504" + cell $eq $eq$ls180.v:4018$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:4018$453_Y + end + attribute \src "ls180.v:4019.339-4019.418" + cell $eq $eq$ls180.v:4019$465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:4019$465_Y + end + attribute \src "ls180.v:4019.423-4019.504" + cell $eq $eq$ls180.v:4019$466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:4019$466_Y + end + attribute \src "ls180.v:4020.339-4020.418" + cell $eq $eq$ls180.v:4020$478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:4020$478_Y + end + attribute \src "ls180.v:4020.423-4020.504" + cell $eq $eq$ls180.v:4020$479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:4020$479_Y + end + attribute \src "ls180.v:4021.339-4021.418" + cell $eq $eq$ls180.v:4021$491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:4021$491_Y + end + attribute \src "ls180.v:4021.423-4021.504" + cell $eq $eq$ls180.v:4021$492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:4021$492_Y + end + attribute \src "ls180.v:4050.78-4050.113" + cell $eq $eq$ls180.v:4050$501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4050$501_Y + end + attribute \src "ls180.v:4053.78-4053.113" + cell $eq $eq$ls180.v:4053$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4053$504_Y + end + attribute \src "ls180.v:4059.78-4059.113" + cell $eq $eq$ls180.v:4059$508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$ls180.v:4059$508_Y + end + attribute \src "ls180.v:4062.78-4062.113" + cell $eq $eq$ls180.v:4062$511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$ls180.v:4062$511_Y + end + attribute \src "ls180.v:4068.78-4068.113" + cell $eq $eq$ls180.v:4068$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$ls180.v:4068$515_Y + end + attribute \src "ls180.v:4071.78-4071.113" + cell $eq $eq$ls180.v:4071$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$ls180.v:4071$518_Y + end + attribute \src "ls180.v:4077.78-4077.113" + cell $eq $eq$ls180.v:4077$522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$ls180.v:4077$522_Y + end + attribute \src "ls180.v:4080.78-4080.113" + cell $eq $eq$ls180.v:4080$525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$ls180.v:4080$525_Y + end + attribute \src "ls180.v:4161.42-4161.82" + cell $eq $eq$ls180.v:4161$548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:4161$548_Y + end + attribute \src "ls180.v:4161.145-4161.178" + cell $eq $eq$ls180.v:4161$549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4161$549_Y + end + attribute \src "ls180.v:4161.220-4161.253" + cell $eq $eq$ls180.v:4161$552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4161$552_Y + end + attribute \src "ls180.v:4161.295-4161.328" + cell $eq $eq$ls180.v:4161$555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4161$555_Y + end + attribute \src "ls180.v:4166.42-4166.82" + cell $eq $eq$ls180.v:4166$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:4166$564_Y + end + attribute \src "ls180.v:4166.145-4166.178" + cell $eq $eq$ls180.v:4166$565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4166$565_Y + end + attribute \src "ls180.v:4166.220-4166.253" + cell $eq $eq$ls180.v:4166$568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4166$568_Y + end + attribute \src "ls180.v:4166.295-4166.328" + cell $eq $eq$ls180.v:4166$571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4166$571_Y + end + attribute \src "ls180.v:4171.42-4171.82" + cell $eq $eq$ls180.v:4171$580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:4171$580_Y + end + attribute \src "ls180.v:4171.145-4171.178" + cell $eq $eq$ls180.v:4171$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4171$581_Y + end + attribute \src "ls180.v:4171.220-4171.253" + cell $eq $eq$ls180.v:4171$584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4171$584_Y + end + attribute \src "ls180.v:4171.295-4171.328" + cell $eq $eq$ls180.v:4171$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4171$587_Y + end + attribute \src "ls180.v:4176.42-4176.82" + cell $eq $eq$ls180.v:4176$596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:4176$596_Y + end + attribute \src "ls180.v:4176.145-4176.178" + cell $eq $eq$ls180.v:4176$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4176$597_Y + end + attribute \src "ls180.v:4176.220-4176.253" + cell $eq $eq$ls180.v:4176$600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4176$600_Y + end + attribute \src "ls180.v:4176.295-4176.328" + cell $eq $eq$ls180.v:4176$603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4176$603_Y + end + attribute \src "ls180.v:4181.44-4181.77" + cell $eq $eq$ls180.v:4181$612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$612_Y + end + attribute \src "ls180.v:4181.83-4181.123" + cell $eq $eq$ls180.v:4181$613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:4181$613_Y + end + attribute \src "ls180.v:4181.186-4181.219" + cell $eq $eq$ls180.v:4181$614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$614_Y + end + attribute \src "ls180.v:4181.261-4181.294" + cell $eq $eq$ls180.v:4181$617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$617_Y + end + attribute \src "ls180.v:4181.336-4181.369" + cell $eq $eq$ls180.v:4181$620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$620_Y + end + attribute \src "ls180.v:4181.418-4181.451" + cell $eq $eq$ls180.v:4181$628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$628_Y + end + attribute \src "ls180.v:4181.457-4181.497" + cell $eq $eq$ls180.v:4181$629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:4181$629_Y + end + attribute \src "ls180.v:4181.560-4181.593" + cell $eq $eq$ls180.v:4181$630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$630_Y + end + attribute \src "ls180.v:4181.635-4181.668" + cell $eq $eq$ls180.v:4181$633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$633_Y + end + attribute \src "ls180.v:4181.710-4181.743" + cell $eq $eq$ls180.v:4181$636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$636_Y + end + attribute \src "ls180.v:4181.792-4181.825" + cell $eq $eq$ls180.v:4181$644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$644_Y + end + attribute \src "ls180.v:4181.831-4181.871" + cell $eq $eq$ls180.v:4181$645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:4181$645_Y + end + attribute \src "ls180.v:4181.934-4181.967" + cell $eq $eq$ls180.v:4181$646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$646_Y + end + attribute \src "ls180.v:4181.1009-4181.1042" + cell $eq $eq$ls180.v:4181$649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$649_Y + end + attribute \src "ls180.v:4181.1084-4181.1117" + cell $eq $eq$ls180.v:4181$652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$652_Y + end + attribute \src "ls180.v:4181.1166-4181.1199" + cell $eq $eq$ls180.v:4181$660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$660_Y + end + attribute \src "ls180.v:4181.1205-4181.1245" + cell $eq $eq$ls180.v:4181$661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:4181$661_Y + end + attribute \src "ls180.v:4181.1308-4181.1341" + cell $eq $eq$ls180.v:4181$662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$662_Y + end + attribute \src "ls180.v:4181.1383-4181.1416" + cell $eq $eq$ls180.v:4181$665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$665_Y + end + attribute \src "ls180.v:4181.1458-4181.1491" + cell $eq $eq$ls180.v:4181$668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$668_Y + end + attribute \src "ls180.v:4240.29-4240.57" + cell $eq $eq$ls180.v:4240$681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_sel + connect \B 1'0 + connect \Y $eq$ls180.v:4240$681_Y + end + attribute \src "ls180.v:4247.11-4247.41" + cell $eq $eq$ls180.v:4247$686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $eq$ls180.v:4247$686_Y + end + attribute \src "ls180.v:4415.37-4415.111" + cell $eq $eq$ls180.v:4415$753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4415$752_Y + connect \Y $eq$ls180.v:4415$753_Y + end + attribute \src "ls180.v:4416.37-4416.105" + cell $eq $eq$ls180.v:4416$755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4416$754_Y + connect \Y $eq$ls180.v:4416$755_Y + end + attribute \src "ls180.v:4443.10-4443.67" + cell $eq $eq$ls180.v:4443$759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spimaster27_count + connect \B $sub$ls180.v:4443$758_Y + connect \Y $eq$ls180.v:4443$759_Y + end + attribute \src "ls180.v:4473.35-4473.108" + cell $eq $eq$ls180.v:4473$761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4473$760_Y + connect \Y $eq$ls180.v:4473$761_Y + end + attribute \src "ls180.v:4474.35-4474.102" + cell $eq $eq$ls180.v:4474$763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4474$762_Y + connect \Y $eq$ls180.v:4474$763_Y + end + attribute \src "ls180.v:4502.10-4502.65" + cell $eq $eq$ls180.v:4502$767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_count + connect \B $sub$ls180.v:4502$766_Y + connect \Y $eq$ls180.v:4502$767_Y + end + attribute \src "ls180.v:4606.10-4606.40" + cell $eq $eq$ls180.v:4606$794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_count + connect \B 7'1001111 + connect \Y $eq$ls180.v:4606$794_Y + end + attribute \src "ls180.v:4663.10-4663.39" + cell $eq $eq$ls180.v:4663$797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4663$797_Y + end + attribute \src "ls180.v:4680.10-4680.39" + cell $eq $eq$ls180.v:4680$799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4680$799_Y + end + attribute \src "ls180.v:4708.38-4708.88" + cell $eq $eq$ls180.v:4708$801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \B 1'0 + connect \Y $eq$ls180.v:4708$801_Y + end + attribute \src "ls180.v:4758.9-4758.40" + cell $eq $eq$ls180.v:4758$811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4758$811_Y + end + attribute \src "ls180.v:4767.36-4767.105" + cell $eq $eq$ls180.v:4767$813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B $sub$ls180.v:4767$812_Y + connect \Y $eq$ls180.v:4767$813_Y + end + attribute \src "ls180.v:4786.9-4786.40" + cell $eq $eq$ls180.v:4786$817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4786$817_Y + end + attribute \src "ls180.v:4798.10-4798.39" + cell $eq $eq$ls180.v:4798$819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B 3'111 + connect \Y $eq$ls180.v:4798$819_Y + end + attribute \src "ls180.v:4835.39-4835.94" + cell $eq $eq$ls180.v:4835$823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \B 1'0 + connect \Y $eq$ls180.v:4835$823_Y + end + attribute \src "ls180.v:4872.32-4872.89" + cell $eq $eq$ls180.v:4872$832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $eq$ls180.v:4872$832_Y + end + attribute \src "ls180.v:4920.10-4920.40" + cell $eq $eq$ls180.v:4920$836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $eq$ls180.v:4920$836_Y + end + attribute \src "ls180.v:4969.40-4969.98" + cell $eq $eq$ls180.v:4969$838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_payload_data_i + connect \B 1'0 + connect \Y $eq$ls180.v:4969$838_Y + end + attribute \src "ls180.v:5020.9-5020.41" + cell $eq $eq$ls180.v:5020$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:5020$848_Y + end + attribute \src "ls180.v:5029.37-5029.123" + cell $eq $eq$ls180.v:5029$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B $sub$ls180.v:5029$850_Y + connect \Y $eq$ls180.v:5029$851_Y + end + attribute \src "ls180.v:5052.9-5052.41" + cell $eq $eq$ls180.v:5052$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:5052$854_Y + end + attribute \src "ls180.v:5062.10-5062.41" + cell $eq $eq$ls180.v:5062$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B 6'100111 + connect \Y $eq$ls180.v:5062$856_Y + end + attribute \src "ls180.v:5231.9-5231.47" + cell $eq $eq$ls180.v:5231$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5231$1038_Y + end + attribute \src "ls180.v:5261.10-5261.48" + cell $eq $eq$ls180.v:5261$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5261$1039_Y + end + attribute \src "ls180.v:5292.10-5292.78" + cell $eq $eq$ls180.v:5292$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo0 + connect \B \main_sdcore_crc16_checker_crctmp0 + connect \Y $eq$ls180.v:5292$1044_Y + end + attribute \src "ls180.v:5292.83-5292.151" + cell $eq $eq$ls180.v:5292$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo1 + connect \B \main_sdcore_crc16_checker_crctmp1 + connect \Y $eq$ls180.v:5292$1045_Y + end + attribute \src "ls180.v:5292.157-5292.225" + cell $eq $eq$ls180.v:5292$1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo2 + connect \B \main_sdcore_crc16_checker_crctmp2 + connect \Y $eq$ls180.v:5292$1047_Y + end + attribute \src "ls180.v:5292.231-5292.299" + cell $eq $eq$ls180.v:5292$1049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo3 + connect \B \main_sdcore_crc16_checker_crctmp3 + connect \Y $eq$ls180.v:5292$1049_Y + end + attribute \src "ls180.v:5300.7-5300.44" + cell $eq $eq$ls180.v:5300$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5300$1053_Y + end + attribute \src "ls180.v:5310.7-5310.44" + cell $eq $eq$ls180.v:5310$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5310$1056_Y + end + attribute \src "ls180.v:5320.7-5320.44" + cell $eq $eq$ls180.v:5320$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5320$1059_Y + end + attribute \src "ls180.v:5330.7-5330.44" + cell $eq $eq$ls180.v:5330$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5330$1062_Y + end + attribute \src "ls180.v:5454.36-5454.64" + cell $eq $eq$ls180.v:5454$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5454$1113_Y + end + attribute \src "ls180.v:5460.10-5460.39" + cell $eq $eq$ls180.v:5460$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_count + connect \B 3'101 + connect \Y $eq$ls180.v:5460$1116_Y + end + attribute \src "ls180.v:5461.11-5461.39" + cell $eq $eq$ls180.v:5461$1117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5461$1117_Y + end + attribute \src "ls180.v:5473.34-5473.63" + cell $eq $eq$ls180.v:5473$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'0 + connect \Y $eq$ls180.v:5473$1118_Y + end + attribute \src "ls180.v:5474.9-5474.37" + cell $eq $eq$ls180.v:5474$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 2'10 + connect \Y $eq$ls180.v:5474$1119_Y + end + attribute \src "ls180.v:5481.10-5481.55" + cell $eq $eq$ls180.v:5481$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5481$1120_Y + end + attribute \src "ls180.v:5487.12-5487.41" + cell $eq $eq$ls180.v:5487$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 2'10 + connect \Y $eq$ls180.v:5487$1121_Y + end + attribute \src "ls180.v:5490.13-5490.42" + cell $eq $eq$ls180.v:5490$1122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'1 + connect \Y $eq$ls180.v:5490$1122_Y + end + attribute \src "ls180.v:5512.10-5512.76" + cell $eq $eq$ls180.v:5512$1127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5512$1126_Y + connect \Y $eq$ls180.v:5512$1127_Y + end + attribute \src "ls180.v:5527.35-5527.101" + cell $eq $eq$ls180.v:5527$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5527$1129_Y + connect \Y $eq$ls180.v:5527$1130_Y + end + attribute \src "ls180.v:5529.10-5529.56" + cell $eq $eq$ls180.v:5529$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'0 + connect \Y $eq$ls180.v:5529$1131_Y + end + attribute \src "ls180.v:5538.12-5538.78" + cell $eq $eq$ls180.v:5538$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5538$1134_Y + connect \Y $eq$ls180.v:5538$1135_Y + end + attribute \src "ls180.v:5545.11-5545.57" + cell $eq $eq$ls180.v:5545$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5545$1136_Y + end + attribute \src "ls180.v:5662.10-5662.105" + cell $eq $eq$ls180.v:5662$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B $sub$ls180.v:5662$1152_Y + connect \Y $eq$ls180.v:5662$1153_Y + end + attribute \src "ls180.v:5752.39-5752.106" + cell $eq $eq$ls180.v:5752$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_offset + connect \B $sub$ls180.v:5752$1158_Y + connect \Y $eq$ls180.v:5752$1159_Y + end + attribute \src "ls180.v:5782.44-5782.82" + cell $eq $eq$ls180.v:5782$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 1'0 + connect \Y $eq$ls180.v:5782$1162_Y + end + attribute \src "ls180.v:5783.43-5783.81" + cell $eq $eq$ls180.v:5783$1163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 3'111 + connect \Y $eq$ls180.v:5783$1163_Y + end + attribute \src "ls180.v:5895.68-5895.89" + cell $eq $eq$ls180.v:5895$1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5895$1179_Y + end + attribute \src "ls180.v:5896.68-5896.89" + cell $eq $eq$ls180.v:5896$1181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5896$1181_Y + end + attribute \src "ls180.v:5897.71-5897.92" + cell $eq $eq$ls180.v:5897$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5897$1183_Y + end + attribute \src "ls180.v:5898.57-5898.78" + cell $eq $eq$ls180.v:5898$1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5898$1185_Y + end + attribute \src "ls180.v:5899.57-5899.78" + cell $eq $eq$ls180.v:5899$1187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5899$1187_Y + end + attribute \src "ls180.v:5900.68-5900.89" + cell $eq $eq$ls180.v:5900$1189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5900$1189_Y + end + attribute \src "ls180.v:5901.68-5901.89" + cell $eq $eq$ls180.v:5901$1191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5901$1191_Y + end + attribute \src "ls180.v:5902.71-5902.92" + cell $eq $eq$ls180.v:5902$1193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5902$1193_Y + end + attribute \src "ls180.v:5903.57-5903.78" + cell $eq $eq$ls180.v:5903$1195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5903$1195_Y + end + attribute \src "ls180.v:5904.57-5904.78" + cell $eq $eq$ls180.v:5904$1197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5904$1197_Y + end + attribute \src "ls180.v:5908.27-5908.59" + cell $eq $eq$ls180.v:5908$1200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 1'0 + connect \Y $eq$ls180.v:5908$1200_Y + end + attribute \src "ls180.v:5909.27-5909.59" + cell $eq $eq$ls180.v:5909$1201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 1'1 + connect \Y $eq$ls180.v:5909$1201_Y + end + attribute \src "ls180.v:5910.27-5910.59" + cell $eq $eq$ls180.v:5910$1202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 2'10 + connect \Y $eq$ls180.v:5910$1202_Y + end + attribute \src "ls180.v:5911.27-5911.59" + cell $eq $eq$ls180.v:5911$1203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 2'11 + connect \Y $eq$ls180.v:5911$1203_Y + end + attribute \src "ls180.v:5912.27-5912.59" + cell $eq $eq$ls180.v:5912$1204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 3'100 + connect \Y $eq$ls180.v:5912$1204_Y + end + attribute \src "ls180.v:5913.27-5913.68" + cell $eq $eq$ls180.v:5913$1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 28 + parameter \B_SIGNED 0 + parameter \B_WIDTH 27 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:2] + connect \B 27'110000000000000100000000000 + connect \Y $eq$ls180.v:5913$1205_Y + end + attribute \src "ls180.v:5914.27-5914.65" + cell $eq $eq$ls180.v:5914$1206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 20 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 20'11000000000000010001 + connect \Y $eq$ls180.v:5914$1206_Y + end + attribute \src "ls180.v:5915.27-5915.59" + cell $eq $eq$ls180.v:5915$1207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 1'1 + connect \Y $eq$ls180.v:5915$1207_Y + end + attribute \src "ls180.v:5916.27-5916.59" + cell $eq $eq$ls180.v:5916$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 2'10 + connect \Y $eq$ls180.v:5916$1208_Y + end + attribute \src "ls180.v:5917.27-5917.59" + cell $eq $eq$ls180.v:5917$1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 2'11 + connect \Y $eq$ls180.v:5917$1209_Y + end + attribute \src "ls180.v:5918.28-5918.60" + cell $eq $eq$ls180.v:5918$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 3'100 + connect \Y $eq$ls180.v:5918$1210_Y + end + attribute \src "ls180.v:5919.28-5919.62" + cell $eq $eq$ls180.v:5919$1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:22] + connect \B 7'1001000 + connect \Y $eq$ls180.v:5919$1211_Y + end + attribute \src "ls180.v:5920.28-5920.66" + cell $eq $eq$ls180.v:5920$1212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 17 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:13] + connect \B 16'1100000000000000 + connect \Y $eq$ls180.v:5920$1212_Y + end + attribute \src "ls180.v:6040.24-6040.45" + cell $eq $eq$ls180.v:6040$1279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_count + connect \B 1'0 + connect \Y $eq$ls180.v:6040$1279_Y + end + attribute \src "ls180.v:6041.32-6041.77" + cell $eq $eq$ls180.v:6041$1280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [13:8] + connect \B 1'0 + connect \Y $eq$ls180.v:6041$1280_Y + end + attribute \src "ls180.v:6043.97-6043.141" + cell $eq $eq$ls180.v:6043$1282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6043$1282_Y + end + attribute \src "ls180.v:6044.100-6044.144" + cell $eq $eq$ls180.v:6044$1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6044$1286_Y + end + attribute \src "ls180.v:6046.99-6046.143" + cell $eq $eq$ls180.v:6046$1289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6046$1289_Y + end + attribute \src "ls180.v:6047.102-6047.146" + cell $eq $eq$ls180.v:6047$1293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6047$1293_Y + end + attribute \src "ls180.v:6049.99-6049.143" + cell $eq $eq$ls180.v:6049$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6049$1296_Y + end + attribute \src "ls180.v:6050.102-6050.146" + cell $eq $eq$ls180.v:6050$1300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6050$1300_Y + end + attribute \src "ls180.v:6052.99-6052.143" + cell $eq $eq$ls180.v:6052$1303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6052$1303_Y + end + attribute \src "ls180.v:6053.102-6053.146" + cell $eq $eq$ls180.v:6053$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6053$1307_Y + end + attribute \src "ls180.v:6055.99-6055.143" + cell $eq $eq$ls180.v:6055$1310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6055$1310_Y + end + attribute \src "ls180.v:6056.102-6056.146" + cell $eq $eq$ls180.v:6056$1314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6056$1314_Y + end + attribute \src "ls180.v:6058.102-6058.146" + cell $eq $eq$ls180.v:6058$1317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6058$1317_Y + end + attribute \src "ls180.v:6059.105-6059.149" + cell $eq $eq$ls180.v:6059$1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6059$1321_Y + end + attribute \src "ls180.v:6061.102-6061.146" + cell $eq $eq$ls180.v:6061$1324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6061$1324_Y + end + attribute \src "ls180.v:6062.105-6062.149" + cell $eq $eq$ls180.v:6062$1328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6062$1328_Y + end + attribute \src "ls180.v:6064.102-6064.146" + cell $eq $eq$ls180.v:6064$1331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6064$1331_Y + end + attribute \src "ls180.v:6065.105-6065.149" + cell $eq $eq$ls180.v:6065$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6065$1335_Y + end + attribute \src "ls180.v:6067.102-6067.146" + cell $eq $eq$ls180.v:6067$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6067$1338_Y + end + attribute \src "ls180.v:6068.105-6068.149" + cell $eq $eq$ls180.v:6068$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6068$1342_Y + end + attribute \src "ls180.v:6079.32-6079.77" + cell $eq $eq$ls180.v:6079$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [13:8] + connect \B 3'110 + connect \Y $eq$ls180.v:6079$1344_Y + end + attribute \src "ls180.v:6081.94-6081.138" + cell $eq $eq$ls180.v:6081$1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6081$1346_Y + end + attribute \src "ls180.v:6082.97-6082.141" + cell $eq $eq$ls180.v:6082$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6082$1350_Y + end + attribute \src "ls180.v:6084.94-6084.138" + cell $eq $eq$ls180.v:6084$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6084$1353_Y + end + attribute \src "ls180.v:6085.97-6085.141" + cell $eq $eq$ls180.v:6085$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6085$1357_Y + end + attribute \src "ls180.v:6087.94-6087.138" + cell $eq $eq$ls180.v:6087$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6087$1360_Y + end + attribute \src "ls180.v:6088.97-6088.141" + cell $eq $eq$ls180.v:6088$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6088$1364_Y + end + attribute \src "ls180.v:6090.94-6090.138" + cell $eq $eq$ls180.v:6090$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6090$1367_Y + end + attribute \src "ls180.v:6091.97-6091.141" + cell $eq $eq$ls180.v:6091$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6091$1371_Y + end + attribute \src "ls180.v:6093.95-6093.139" + cell $eq $eq$ls180.v:6093$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6093$1374_Y + end + attribute \src "ls180.v:6094.98-6094.142" + cell $eq $eq$ls180.v:6094$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6094$1378_Y + end + attribute \src "ls180.v:6096.95-6096.139" + cell $eq $eq$ls180.v:6096$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6096$1381_Y + end + attribute \src "ls180.v:6097.98-6097.142" + cell $eq $eq$ls180.v:6097$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6097$1385_Y + end + attribute \src "ls180.v:6105.32-6105.78" + cell $eq $eq$ls180.v:6105$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [13:8] + connect \B 4'1100 + connect \Y $eq$ls180.v:6105$1387_Y + end + attribute \src "ls180.v:6107.93-6107.135" + cell $eq $eq$ls180.v:6107$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:6107$1389_Y + end + attribute \src "ls180.v:6108.96-6108.138" + cell $eq $eq$ls180.v:6108$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:6108$1393_Y + end + attribute \src "ls180.v:6110.92-6110.134" + cell $eq $eq$ls180.v:6110$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:6110$1396_Y + end + attribute \src "ls180.v:6111.95-6111.137" + cell $eq $eq$ls180.v:6111$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:6111$1400_Y + end + attribute \src "ls180.v:6119.32-6119.78" + cell $eq $eq$ls180.v:6119$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [13:8] + connect \B 4'1010 + connect \Y $eq$ls180.v:6119$1402_Y + end + attribute \src "ls180.v:6121.98-6121.142" + cell $eq $eq$ls180.v:6121$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6121$1404_Y + end + attribute \src "ls180.v:6122.101-6122.145" + cell $eq $eq$ls180.v:6122$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6122$1408_Y + end + attribute \src "ls180.v:6124.97-6124.141" + cell $eq $eq$ls180.v:6124$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6124$1411_Y + end + attribute \src "ls180.v:6125.100-6125.144" + cell $eq $eq$ls180.v:6125$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6125$1415_Y + end + attribute \src "ls180.v:6127.97-6127.141" + cell $eq $eq$ls180.v:6127$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6127$1418_Y + end + attribute \src "ls180.v:6128.100-6128.144" + cell $eq $eq$ls180.v:6128$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6128$1422_Y + end + attribute \src "ls180.v:6130.97-6130.141" + cell $eq $eq$ls180.v:6130$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6130$1425_Y + end + attribute \src "ls180.v:6131.100-6131.144" + cell $eq $eq$ls180.v:6131$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6131$1429_Y + end + attribute \src "ls180.v:6133.97-6133.141" + cell $eq $eq$ls180.v:6133$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6133$1432_Y + end + attribute \src "ls180.v:6134.100-6134.144" + cell $eq $eq$ls180.v:6134$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6134$1436_Y + end + attribute \src "ls180.v:6136.98-6136.142" + cell $eq $eq$ls180.v:6136$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6136$1439_Y + end + attribute \src "ls180.v:6137.101-6137.145" + cell $eq $eq$ls180.v:6137$1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6137$1443_Y + end + attribute \src "ls180.v:6139.98-6139.142" + cell $eq $eq$ls180.v:6139$1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6139$1446_Y + end + attribute \src "ls180.v:6140.101-6140.145" + cell $eq $eq$ls180.v:6140$1450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6140$1450_Y + end + attribute \src "ls180.v:6142.98-6142.142" + cell $eq $eq$ls180.v:6142$1453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6142$1453_Y + end + attribute \src "ls180.v:6143.101-6143.145" + cell $eq $eq$ls180.v:6143$1457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6143$1457_Y + end + attribute \src "ls180.v:6145.98-6145.142" + cell $eq $eq$ls180.v:6145$1460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6145$1460_Y + end + attribute \src "ls180.v:6146.101-6146.145" + cell $eq $eq$ls180.v:6146$1464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6146$1464_Y + end + attribute \src "ls180.v:6156.32-6156.78" + cell $eq $eq$ls180.v:6156$1466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [13:8] + connect \B 4'1011 + connect \Y $eq$ls180.v:6156$1466_Y + end + attribute \src "ls180.v:6158.98-6158.142" + cell $eq $eq$ls180.v:6158$1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6158$1468_Y + end + attribute \src "ls180.v:6159.101-6159.145" + cell $eq $eq$ls180.v:6159$1472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6159$1472_Y + end + attribute \src "ls180.v:6161.97-6161.141" + cell $eq $eq$ls180.v:6161$1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6161$1475_Y + end + attribute \src "ls180.v:6162.100-6162.144" + cell $eq $eq$ls180.v:6162$1479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6162$1479_Y + end + attribute \src "ls180.v:6164.97-6164.141" + cell $eq $eq$ls180.v:6164$1482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6164$1482_Y + end + attribute \src "ls180.v:6165.100-6165.144" + cell $eq $eq$ls180.v:6165$1486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6165$1486_Y + end + attribute \src "ls180.v:6167.97-6167.141" + cell $eq $eq$ls180.v:6167$1489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6167$1489_Y + end + attribute \src "ls180.v:6168.100-6168.144" + cell $eq $eq$ls180.v:6168$1493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6168$1493_Y + end + attribute \src "ls180.v:6170.97-6170.141" + cell $eq $eq$ls180.v:6170$1496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6170$1496_Y + end + attribute \src "ls180.v:6171.100-6171.144" + cell $eq $eq$ls180.v:6171$1500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6171$1500_Y + end + attribute \src "ls180.v:6173.98-6173.142" + cell $eq $eq$ls180.v:6173$1503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6173$1503_Y + end + attribute \src "ls180.v:6174.101-6174.145" + cell $eq $eq$ls180.v:6174$1507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6174$1507_Y + end + attribute \src "ls180.v:6176.98-6176.142" + cell $eq $eq$ls180.v:6176$1510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6176$1510_Y + end + attribute \src "ls180.v:6177.101-6177.145" + cell $eq $eq$ls180.v:6177$1514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6177$1514_Y + end + attribute \src "ls180.v:6179.98-6179.142" + cell $eq $eq$ls180.v:6179$1517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6179$1517_Y + end + attribute \src "ls180.v:6180.101-6180.145" + cell $eq $eq$ls180.v:6180$1521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6180$1521_Y + end + attribute \src "ls180.v:6182.98-6182.142" + cell $eq $eq$ls180.v:6182$1524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6182$1524_Y + end + attribute \src "ls180.v:6183.101-6183.145" + cell $eq $eq$ls180.v:6183$1528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6183$1528_Y + end + attribute \src "ls180.v:6193.32-6193.78" + cell $eq $eq$ls180.v:6193$1530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [13:8] + connect \B 4'1111 + connect \Y $eq$ls180.v:6193$1530_Y + end + attribute \src "ls180.v:6195.100-6195.144" + cell $eq $eq$ls180.v:6195$1532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6195$1532_Y + end + attribute \src "ls180.v:6196.103-6196.147" + cell $eq $eq$ls180.v:6196$1536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6196$1536_Y + end + attribute \src "ls180.v:6198.100-6198.144" + cell $eq $eq$ls180.v:6198$1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6198$1539_Y + end + attribute \src "ls180.v:6199.103-6199.147" + cell $eq $eq$ls180.v:6199$1543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6199$1543_Y + end + attribute \src "ls180.v:6201.100-6201.144" + cell $eq $eq$ls180.v:6201$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6201$1546_Y + end + attribute \src "ls180.v:6202.103-6202.147" + cell $eq $eq$ls180.v:6202$1550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6202$1550_Y + end + attribute \src "ls180.v:6204.100-6204.144" + cell $eq $eq$ls180.v:6204$1553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6204$1553_Y + end + attribute \src "ls180.v:6205.103-6205.147" + cell $eq $eq$ls180.v:6205$1557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6205$1557_Y + end + attribute \src "ls180.v:6207.100-6207.144" + cell $eq $eq$ls180.v:6207$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6207$1560_Y + end + attribute \src "ls180.v:6208.103-6208.147" + cell $eq $eq$ls180.v:6208$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6208$1564_Y + end + attribute \src "ls180.v:6210.100-6210.144" + cell $eq $eq$ls180.v:6210$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6210$1567_Y + end + attribute \src "ls180.v:6211.103-6211.147" + cell $eq $eq$ls180.v:6211$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6211$1571_Y + end + attribute \src "ls180.v:6213.100-6213.144" + cell $eq $eq$ls180.v:6213$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6213$1574_Y + end + attribute \src "ls180.v:6214.103-6214.147" + cell $eq $eq$ls180.v:6214$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6214$1578_Y + end + attribute \src "ls180.v:6216.100-6216.144" + cell $eq $eq$ls180.v:6216$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6216$1581_Y + end + attribute \src "ls180.v:6217.103-6217.147" + cell $eq $eq$ls180.v:6217$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6217$1585_Y + end + attribute \src "ls180.v:6219.102-6219.146" + cell $eq $eq$ls180.v:6219$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6219$1588_Y + end + attribute \src "ls180.v:6220.105-6220.149" + cell $eq $eq$ls180.v:6220$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6220$1592_Y + end + attribute \src "ls180.v:6222.102-6222.146" + cell $eq $eq$ls180.v:6222$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6222$1595_Y + end + attribute \src "ls180.v:6223.105-6223.149" + cell $eq $eq$ls180.v:6223$1599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6223$1599_Y + end + attribute \src "ls180.v:6225.102-6225.147" + cell $eq $eq$ls180.v:6225$1602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6225$1602_Y + end + attribute \src "ls180.v:6226.105-6226.150" + cell $eq $eq$ls180.v:6226$1606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6226$1606_Y + end + attribute \src "ls180.v:6228.102-6228.147" + cell $eq $eq$ls180.v:6228$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6228$1609_Y + end + attribute \src "ls180.v:6229.105-6229.150" + cell $eq $eq$ls180.v:6229$1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6229$1613_Y + end + attribute \src "ls180.v:6231.102-6231.147" + cell $eq $eq$ls180.v:6231$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6231$1616_Y + end + attribute \src "ls180.v:6232.105-6232.150" + cell $eq $eq$ls180.v:6232$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6232$1620_Y + end + attribute \src "ls180.v:6234.99-6234.144" + cell $eq $eq$ls180.v:6234$1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6234$1623_Y + end + attribute \src "ls180.v:6235.102-6235.147" + cell $eq $eq$ls180.v:6235$1627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6235$1627_Y + end + attribute \src "ls180.v:6237.100-6237.145" + cell $eq $eq$ls180.v:6237$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6237$1630_Y + end + attribute \src "ls180.v:6238.103-6238.148" + cell $eq $eq$ls180.v:6238$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6238$1634_Y + end + attribute \src "ls180.v:6255.32-6255.78" + cell $eq $eq$ls180.v:6255$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [13:8] + connect \B 4'1110 + connect \Y $eq$ls180.v:6255$1636_Y + end + attribute \src "ls180.v:6257.104-6257.148" + cell $eq $eq$ls180.v:6257$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6257$1638_Y + end + attribute \src "ls180.v:6258.107-6258.151" + cell $eq $eq$ls180.v:6258$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6258$1642_Y + end + attribute \src "ls180.v:6260.104-6260.148" + cell $eq $eq$ls180.v:6260$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6260$1645_Y + end + attribute \src "ls180.v:6261.107-6261.151" + cell $eq $eq$ls180.v:6261$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6261$1649_Y + end + attribute \src "ls180.v:6263.104-6263.148" + cell $eq $eq$ls180.v:6263$1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6263$1652_Y + end + attribute \src "ls180.v:6264.107-6264.151" + cell $eq $eq$ls180.v:6264$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6264$1656_Y + end + attribute \src "ls180.v:6266.104-6266.148" + cell $eq $eq$ls180.v:6266$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6266$1659_Y + end + attribute \src "ls180.v:6267.107-6267.151" + cell $eq $eq$ls180.v:6267$1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6267$1663_Y + end + attribute \src "ls180.v:6269.103-6269.147" + cell $eq $eq$ls180.v:6269$1666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6269$1666_Y + end + attribute \src "ls180.v:6270.106-6270.150" + cell $eq $eq$ls180.v:6270$1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6270$1670_Y + end + attribute \src "ls180.v:6272.103-6272.147" + cell $eq $eq$ls180.v:6272$1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6272$1673_Y + end + attribute \src "ls180.v:6273.106-6273.150" + cell $eq $eq$ls180.v:6273$1677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6273$1677_Y + end + attribute \src "ls180.v:6275.103-6275.147" + cell $eq $eq$ls180.v:6275$1680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6275$1680_Y + end + attribute \src "ls180.v:6276.106-6276.150" + cell $eq $eq$ls180.v:6276$1684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6276$1684_Y + end + attribute \src "ls180.v:6278.103-6278.147" + cell $eq $eq$ls180.v:6278$1687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6278$1687_Y + end + attribute \src "ls180.v:6279.106-6279.150" + cell $eq $eq$ls180.v:6279$1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6279$1691_Y + end + attribute \src "ls180.v:6281.94-6281.138" + cell $eq $eq$ls180.v:6281$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6281$1694_Y + end + attribute \src "ls180.v:6282.97-6282.141" + cell $eq $eq$ls180.v:6282$1698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6282$1698_Y + end + attribute \src "ls180.v:6284.105-6284.149" + cell $eq $eq$ls180.v:6284$1701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6284$1701_Y + end + attribute \src "ls180.v:6285.108-6285.152" + cell $eq $eq$ls180.v:6285$1705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6285$1705_Y + end + attribute \src "ls180.v:6287.105-6287.150" + cell $eq $eq$ls180.v:6287$1708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6287$1708_Y + end + attribute \src "ls180.v:6288.108-6288.153" + cell $eq $eq$ls180.v:6288$1712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6288$1712_Y + end + attribute \src "ls180.v:6290.105-6290.150" + cell $eq $eq$ls180.v:6290$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6290$1715_Y + end + attribute \src "ls180.v:6291.108-6291.153" + cell $eq $eq$ls180.v:6291$1719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6291$1719_Y + end + attribute \src "ls180.v:6293.105-6293.150" + cell $eq $eq$ls180.v:6293$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6293$1722_Y + end + attribute \src "ls180.v:6294.108-6294.153" + cell $eq $eq$ls180.v:6294$1726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6294$1726_Y + end + attribute \src "ls180.v:6296.105-6296.150" + cell $eq $eq$ls180.v:6296$1729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6296$1729_Y + end + attribute \src "ls180.v:6297.108-6297.153" + cell $eq $eq$ls180.v:6297$1733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6297$1733_Y + end + attribute \src "ls180.v:6299.105-6299.150" + cell $eq $eq$ls180.v:6299$1736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6299$1736_Y + end + attribute \src "ls180.v:6300.108-6300.153" + cell $eq $eq$ls180.v:6300$1740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6300$1740_Y + end + attribute \src "ls180.v:6302.104-6302.149" + cell $eq $eq$ls180.v:6302$1743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6302$1743_Y + end + attribute \src "ls180.v:6303.107-6303.152" + cell $eq $eq$ls180.v:6303$1747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6303$1747_Y + end + attribute \src "ls180.v:6305.104-6305.149" + cell $eq $eq$ls180.v:6305$1750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6305$1750_Y + end + attribute \src "ls180.v:6306.107-6306.152" + cell $eq $eq$ls180.v:6306$1754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6306$1754_Y + end + attribute \src "ls180.v:6308.104-6308.149" + cell $eq $eq$ls180.v:6308$1757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6308$1757_Y + end + attribute \src "ls180.v:6309.107-6309.152" + cell $eq $eq$ls180.v:6309$1761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6309$1761_Y + end + attribute \src "ls180.v:6311.104-6311.149" + cell $eq $eq$ls180.v:6311$1764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6311$1764_Y + end + attribute \src "ls180.v:6312.107-6312.152" + cell $eq $eq$ls180.v:6312$1768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6312$1768_Y + end + attribute \src "ls180.v:6314.104-6314.149" + cell $eq $eq$ls180.v:6314$1771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6314$1771_Y + end + attribute \src "ls180.v:6315.107-6315.152" + cell $eq $eq$ls180.v:6315$1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6315$1775_Y + end + attribute \src "ls180.v:6317.104-6317.149" + cell $eq $eq$ls180.v:6317$1778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6317$1778_Y + end + attribute \src "ls180.v:6318.107-6318.152" + cell $eq $eq$ls180.v:6318$1782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6318$1782_Y + end + attribute \src "ls180.v:6320.104-6320.149" + cell $eq $eq$ls180.v:6320$1785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6320$1785_Y + end + attribute \src "ls180.v:6321.107-6321.152" + cell $eq $eq$ls180.v:6321$1789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6321$1789_Y + end + attribute \src "ls180.v:6323.104-6323.149" + cell $eq $eq$ls180.v:6323$1792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6323$1792_Y + end + attribute \src "ls180.v:6324.107-6324.152" + cell $eq $eq$ls180.v:6324$1796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6324$1796_Y + end + attribute \src "ls180.v:6326.104-6326.149" + cell $eq $eq$ls180.v:6326$1799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6326$1799_Y + end + attribute \src "ls180.v:6327.107-6327.152" + cell $eq $eq$ls180.v:6327$1803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6327$1803_Y + end + attribute \src "ls180.v:6329.104-6329.149" + cell $eq $eq$ls180.v:6329$1806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6329$1806_Y + end + attribute \src "ls180.v:6330.107-6330.152" + cell $eq $eq$ls180.v:6330$1810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6330$1810_Y + end + attribute \src "ls180.v:6332.100-6332.145" + cell $eq $eq$ls180.v:6332$1813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6332$1813_Y + end + attribute \src "ls180.v:6333.103-6333.148" + cell $eq $eq$ls180.v:6333$1817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6333$1817_Y + end + attribute \src "ls180.v:6335.101-6335.146" + cell $eq $eq$ls180.v:6335$1820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6335$1820_Y + end + attribute \src "ls180.v:6336.104-6336.149" + cell $eq $eq$ls180.v:6336$1824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6336$1824_Y + end + attribute \src "ls180.v:6338.104-6338.149" + cell $eq $eq$ls180.v:6338$1827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6338$1827_Y + end + attribute \src "ls180.v:6339.107-6339.152" + cell $eq $eq$ls180.v:6339$1831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6339$1831_Y + end + attribute \src "ls180.v:6341.104-6341.149" + cell $eq $eq$ls180.v:6341$1834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6341$1834_Y + end + attribute \src "ls180.v:6342.107-6342.152" + cell $eq $eq$ls180.v:6342$1838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6342$1838_Y + end + attribute \src "ls180.v:6344.103-6344.148" + cell $eq $eq$ls180.v:6344$1841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6344$1841_Y + end + attribute \src "ls180.v:6345.106-6345.151" + cell $eq $eq$ls180.v:6345$1845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6345$1845_Y + end + attribute \src "ls180.v:6347.103-6347.148" + cell $eq $eq$ls180.v:6347$1848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6347$1848_Y + end + attribute \src "ls180.v:6348.106-6348.151" + cell $eq $eq$ls180.v:6348$1852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6348$1852_Y + end + attribute \src "ls180.v:6350.103-6350.148" + cell $eq $eq$ls180.v:6350$1855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6350$1855_Y + end + attribute \src "ls180.v:6351.106-6351.151" + cell $eq $eq$ls180.v:6351$1859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6351$1859_Y + end + attribute \src "ls180.v:6353.103-6353.148" + cell $eq $eq$ls180.v:6353$1862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6353$1862_Y + end + attribute \src "ls180.v:6354.106-6354.151" + cell $eq $eq$ls180.v:6354$1866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6354$1866_Y + end + attribute \src "ls180.v:6390.32-6390.78" + cell $eq $eq$ls180.v:6390$1868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [13:8] + connect \B 5'10000 + connect \Y $eq$ls180.v:6390$1868_Y + end + attribute \src "ls180.v:6392.100-6392.144" + cell $eq $eq$ls180.v:6392$1870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6392$1870_Y + end + attribute \src "ls180.v:6393.103-6393.147" + cell $eq $eq$ls180.v:6393$1874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6393$1874_Y + end + attribute \src "ls180.v:6395.100-6395.144" + cell $eq $eq$ls180.v:6395$1877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6395$1877_Y + end + attribute \src "ls180.v:6396.103-6396.147" + cell $eq $eq$ls180.v:6396$1881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6396$1881_Y + end + attribute \src "ls180.v:6398.100-6398.144" + cell $eq $eq$ls180.v:6398$1884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6398$1884_Y + end + attribute \src "ls180.v:6399.103-6399.147" + cell $eq $eq$ls180.v:6399$1888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6399$1888_Y + end + attribute \src "ls180.v:6401.100-6401.144" + cell $eq $eq$ls180.v:6401$1891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6401$1891_Y + end + attribute \src "ls180.v:6402.103-6402.147" + cell $eq $eq$ls180.v:6402$1895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6402$1895_Y + end + attribute \src "ls180.v:6404.100-6404.144" + cell $eq $eq$ls180.v:6404$1898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6404$1898_Y + end + attribute \src "ls180.v:6405.103-6405.147" + cell $eq $eq$ls180.v:6405$1902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6405$1902_Y + end + attribute \src "ls180.v:6407.100-6407.144" + cell $eq $eq$ls180.v:6407$1905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6407$1905_Y + end + attribute \src "ls180.v:6408.103-6408.147" + cell $eq $eq$ls180.v:6408$1909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6408$1909_Y + end + attribute \src "ls180.v:6410.100-6410.144" + cell $eq $eq$ls180.v:6410$1912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6410$1912_Y + end + attribute \src "ls180.v:6411.103-6411.147" + cell $eq $eq$ls180.v:6411$1916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6411$1916_Y + end + attribute \src "ls180.v:6413.100-6413.144" + cell $eq $eq$ls180.v:6413$1919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6413$1919_Y + end + attribute \src "ls180.v:6414.103-6414.147" + cell $eq $eq$ls180.v:6414$1923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6414$1923_Y + end + attribute \src "ls180.v:6416.102-6416.146" + cell $eq $eq$ls180.v:6416$1926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6416$1926_Y + end + attribute \src "ls180.v:6417.105-6417.149" + cell $eq $eq$ls180.v:6417$1930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6417$1930_Y + end + attribute \src "ls180.v:6419.102-6419.146" + cell $eq $eq$ls180.v:6419$1933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6419$1933_Y + end + attribute \src "ls180.v:6420.105-6420.149" + cell $eq $eq$ls180.v:6420$1937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6420$1937_Y + end + attribute \src "ls180.v:6422.102-6422.147" + cell $eq $eq$ls180.v:6422$1940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6422$1940_Y + end + attribute \src "ls180.v:6423.105-6423.150" + cell $eq $eq$ls180.v:6423$1944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6423$1944_Y + end + attribute \src "ls180.v:6425.102-6425.147" + cell $eq $eq$ls180.v:6425$1947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6425$1947_Y + end + attribute \src "ls180.v:6426.105-6426.150" + cell $eq $eq$ls180.v:6426$1951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6426$1951_Y + end + attribute \src "ls180.v:6428.102-6428.147" + cell $eq $eq$ls180.v:6428$1954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6428$1954_Y + end + attribute \src "ls180.v:6429.105-6429.150" + cell $eq $eq$ls180.v:6429$1958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6429$1958_Y + end + attribute \src "ls180.v:6431.99-6431.144" + cell $eq $eq$ls180.v:6431$1961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6431$1961_Y + end + attribute \src "ls180.v:6432.102-6432.147" + cell $eq $eq$ls180.v:6432$1965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6432$1965_Y + end + attribute \src "ls180.v:6434.100-6434.145" + cell $eq $eq$ls180.v:6434$1968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6434$1968_Y + end + attribute \src "ls180.v:6435.103-6435.148" + cell $eq $eq$ls180.v:6435$1972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6435$1972_Y + end + attribute \src "ls180.v:6437.102-6437.147" + cell $eq $eq$ls180.v:6437$1975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6437$1975_Y + end + attribute \src "ls180.v:6438.105-6438.150" + cell $eq $eq$ls180.v:6438$1979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6438$1979_Y + end + attribute \src "ls180.v:6440.102-6440.147" + cell $eq $eq$ls180.v:6440$1982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6440$1982_Y + end + attribute \src "ls180.v:6441.105-6441.150" + cell $eq $eq$ls180.v:6441$1986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6441$1986_Y + end + attribute \src "ls180.v:6443.102-6443.147" + cell $eq $eq$ls180.v:6443$1989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6443$1989_Y + end + attribute \src "ls180.v:6444.105-6444.150" + cell $eq $eq$ls180.v:6444$1993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6444$1993_Y + end + attribute \src "ls180.v:6446.102-6446.147" + cell $eq $eq$ls180.v:6446$1996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6446$1996_Y + end + attribute \src "ls180.v:6447.105-6447.150" + cell $eq $eq$ls180.v:6447$2000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6447$2000_Y + end + attribute \src "ls180.v:6469.32-6469.78" + cell $eq $eq$ls180.v:6469$2002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [13:8] + connect \B 4'1101 + connect \Y $eq$ls180.v:6469$2002_Y + end + attribute \src "ls180.v:6471.102-6471.146" + cell $eq $eq$ls180.v:6471$2004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6471$2004_Y + end + attribute \src "ls180.v:6472.105-6472.149" + cell $eq $eq$ls180.v:6472$2008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6472$2008_Y + end + attribute \src "ls180.v:6474.107-6474.151" + cell $eq $eq$ls180.v:6474$2011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6474$2011_Y + end + attribute \src "ls180.v:6475.110-6475.154" + cell $eq $eq$ls180.v:6475$2015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6475$2015_Y + end + attribute \src "ls180.v:6477.107-6477.151" + cell $eq $eq$ls180.v:6477$2018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6477$2018_Y + end + attribute \src "ls180.v:6478.110-6478.154" + cell $eq $eq$ls180.v:6478$2022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6478$2022_Y + end + attribute \src "ls180.v:6480.100-6480.144" + cell $eq $eq$ls180.v:6480$2025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6480$2025_Y + end + attribute \src "ls180.v:6481.103-6481.147" + cell $eq $eq$ls180.v:6481$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6481$2029_Y + end + attribute \src "ls180.v:6486.32-6486.77" + cell $eq $eq$ls180.v:6486$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [13:8] + connect \B 2'11 + connect \Y $eq$ls180.v:6486$2031_Y + end + attribute \src "ls180.v:6488.104-6488.148" + cell $eq $eq$ls180.v:6488$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6488$2033_Y + end + attribute \src "ls180.v:6489.107-6489.151" + cell $eq $eq$ls180.v:6489$2037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6489$2037_Y + end + attribute \src "ls180.v:6491.108-6491.152" + cell $eq $eq$ls180.v:6491$2040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6491$2040_Y + end + attribute \src "ls180.v:6492.111-6492.155" + cell $eq $eq$ls180.v:6492$2044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6492$2044_Y + end + attribute \src "ls180.v:6494.98-6494.142" + cell $eq $eq$ls180.v:6494$2047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6494$2047_Y + end + attribute \src "ls180.v:6495.101-6495.145" + cell $eq $eq$ls180.v:6495$2051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6495$2051_Y + end + attribute \src "ls180.v:6497.108-6497.152" + cell $eq $eq$ls180.v:6497$2054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6497$2054_Y + end + attribute \src "ls180.v:6498.111-6498.155" + cell $eq $eq$ls180.v:6498$2058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6498$2058_Y + end + attribute \src "ls180.v:6500.108-6500.152" + cell $eq $eq$ls180.v:6500$2061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6500$2061_Y + end + attribute \src "ls180.v:6501.111-6501.155" + cell $eq $eq$ls180.v:6501$2065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6501$2065_Y + end + attribute \src "ls180.v:6503.109-6503.153" + cell $eq $eq$ls180.v:6503$2068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6503$2068_Y + end + attribute \src "ls180.v:6504.112-6504.156" + cell $eq $eq$ls180.v:6504$2072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6504$2072_Y + end + attribute \src "ls180.v:6506.107-6506.151" + cell $eq $eq$ls180.v:6506$2075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6506$2075_Y + end + attribute \src "ls180.v:6507.110-6507.154" + cell $eq $eq$ls180.v:6507$2079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6507$2079_Y + end + attribute \src "ls180.v:6509.107-6509.151" + cell $eq $eq$ls180.v:6509$2082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6509$2082_Y + end + attribute \src "ls180.v:6510.110-6510.154" + cell $eq $eq$ls180.v:6510$2086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6510$2086_Y + end + attribute \src "ls180.v:6512.107-6512.151" + cell $eq $eq$ls180.v:6512$2089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6512$2089_Y + end + attribute \src "ls180.v:6513.110-6513.154" + cell $eq $eq$ls180.v:6513$2093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6513$2093_Y + end + attribute \src "ls180.v:6515.107-6515.151" + cell $eq $eq$ls180.v:6515$2096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6515$2096_Y + end + attribute \src "ls180.v:6516.110-6516.154" + cell $eq $eq$ls180.v:6516$2100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6516$2100_Y + end + attribute \src "ls180.v:6531.33-6531.79" + cell $eq $eq$ls180.v:6531$2102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [13:8] + connect \B 4'1000 + connect \Y $eq$ls180.v:6531$2102_Y + end + attribute \src "ls180.v:6533.102-6533.147" + cell $eq $eq$ls180.v:6533$2104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6533$2104_Y + end + attribute \src "ls180.v:6534.105-6534.150" + cell $eq $eq$ls180.v:6534$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6534$2108_Y + end + attribute \src "ls180.v:6536.102-6536.147" + cell $eq $eq$ls180.v:6536$2111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6536$2111_Y + end + attribute \src "ls180.v:6537.105-6537.150" + cell $eq $eq$ls180.v:6537$2115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6537$2115_Y + end + attribute \src "ls180.v:6539.100-6539.145" + cell $eq $eq$ls180.v:6539$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6539$2118_Y + end + attribute \src "ls180.v:6540.103-6540.148" + cell $eq $eq$ls180.v:6540$2122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6540$2122_Y + end + attribute \src "ls180.v:6542.99-6542.144" + cell $eq $eq$ls180.v:6542$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6542$2125_Y + end + attribute \src "ls180.v:6543.102-6543.147" + cell $eq $eq$ls180.v:6543$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6543$2129_Y + end + attribute \src "ls180.v:6545.98-6545.143" + cell $eq $eq$ls180.v:6545$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6545$2132_Y + end + attribute \src "ls180.v:6546.101-6546.146" + cell $eq $eq$ls180.v:6546$2136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6546$2136_Y + end + attribute \src "ls180.v:6548.97-6548.142" + cell $eq $eq$ls180.v:6548$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6548$2139_Y + end + attribute \src "ls180.v:6549.100-6549.145" + cell $eq $eq$ls180.v:6549$2143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6549$2143_Y + end + attribute \src "ls180.v:6551.103-6551.148" + cell $eq $eq$ls180.v:6551$2146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6551$2146_Y + end + attribute \src "ls180.v:6552.106-6552.151" + cell $eq $eq$ls180.v:6552$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6552$2150_Y + end + attribute \src "ls180.v:6571.33-6571.79" + cell $eq $eq$ls180.v:6571$2153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [13:8] + connect \B 4'1001 + connect \Y $eq$ls180.v:6571$2153_Y + end + attribute \src "ls180.v:6573.102-6573.147" + cell $eq $eq$ls180.v:6573$2155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6573$2155_Y + end + attribute \src "ls180.v:6574.105-6574.150" + cell $eq $eq$ls180.v:6574$2159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6574$2159_Y + end + attribute \src "ls180.v:6576.102-6576.147" + cell $eq $eq$ls180.v:6576$2162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6576$2162_Y + end + attribute \src "ls180.v:6577.105-6577.150" + cell $eq $eq$ls180.v:6577$2166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6577$2166_Y + end + attribute \src "ls180.v:6579.100-6579.145" + cell $eq $eq$ls180.v:6579$2169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6579$2169_Y + end + attribute \src "ls180.v:6580.103-6580.148" + cell $eq $eq$ls180.v:6580$2173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6580$2173_Y + end + attribute \src "ls180.v:6582.99-6582.144" + cell $eq $eq$ls180.v:6582$2176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6582$2176_Y + end + attribute \src "ls180.v:6583.102-6583.147" + cell $eq $eq$ls180.v:6583$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6583$2180_Y + end + attribute \src "ls180.v:6585.98-6585.143" + cell $eq $eq$ls180.v:6585$2183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6585$2183_Y + end + attribute \src "ls180.v:6586.101-6586.146" + cell $eq $eq$ls180.v:6586$2187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6586$2187_Y + end + attribute \src "ls180.v:6588.97-6588.142" + cell $eq $eq$ls180.v:6588$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6588$2190_Y + end + attribute \src "ls180.v:6589.100-6589.145" + cell $eq $eq$ls180.v:6589$2194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6589$2194_Y + end + attribute \src "ls180.v:6591.103-6591.148" + cell $eq $eq$ls180.v:6591$2197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6591$2197_Y + end + attribute \src "ls180.v:6592.106-6592.151" + cell $eq $eq$ls180.v:6592$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6592$2201_Y + end + attribute \src "ls180.v:6594.106-6594.151" + cell $eq $eq$ls180.v:6594$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6594$2204_Y + end + attribute \src "ls180.v:6595.109-6595.154" + cell $eq $eq$ls180.v:6595$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6595$2208_Y + end + attribute \src "ls180.v:6597.106-6597.151" + cell $eq $eq$ls180.v:6597$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6597$2211_Y + end + attribute \src "ls180.v:6598.109-6598.154" + cell $eq $eq$ls180.v:6598$2215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6598$2215_Y + end + attribute \src "ls180.v:6619.33-6619.79" + cell $eq $eq$ls180.v:6619$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [13:8] + connect \B 2'10 + connect \Y $eq$ls180.v:6619$2218_Y + end + attribute \src "ls180.v:6621.99-6621.144" + cell $eq $eq$ls180.v:6621$2220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6621$2220_Y + end + attribute \src "ls180.v:6622.102-6622.147" + cell $eq $eq$ls180.v:6622$2224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6622$2224_Y + end + attribute \src "ls180.v:6624.99-6624.144" + cell $eq $eq$ls180.v:6624$2227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6624$2227_Y + end + attribute \src "ls180.v:6625.102-6625.147" + cell $eq $eq$ls180.v:6625$2231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6625$2231_Y + end + attribute \src "ls180.v:6627.99-6627.144" + cell $eq $eq$ls180.v:6627$2234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6627$2234_Y + end + attribute \src "ls180.v:6628.102-6628.147" + cell $eq $eq$ls180.v:6628$2238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6628$2238_Y + end + attribute \src "ls180.v:6630.99-6630.144" + cell $eq $eq$ls180.v:6630$2241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6630$2241_Y + end + attribute \src "ls180.v:6631.102-6631.147" + cell $eq $eq$ls180.v:6631$2245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6631$2245_Y + end + attribute \src "ls180.v:6633.101-6633.146" + cell $eq $eq$ls180.v:6633$2248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6633$2248_Y + end + attribute \src "ls180.v:6634.104-6634.149" + cell $eq $eq$ls180.v:6634$2252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6634$2252_Y + end + attribute \src "ls180.v:6636.101-6636.146" + cell $eq $eq$ls180.v:6636$2255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6636$2255_Y + end + attribute \src "ls180.v:6637.104-6637.149" + cell $eq $eq$ls180.v:6637$2259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6637$2259_Y + end + attribute \src "ls180.v:6639.101-6639.146" + cell $eq $eq$ls180.v:6639$2262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6639$2262_Y + end + attribute \src "ls180.v:6640.104-6640.149" + cell $eq $eq$ls180.v:6640$2266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6640$2266_Y + end + attribute \src "ls180.v:6642.101-6642.146" + cell $eq $eq$ls180.v:6642$2269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6642$2269_Y + end + attribute \src "ls180.v:6643.104-6643.149" + cell $eq $eq$ls180.v:6643$2273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6643$2273_Y + end + attribute \src "ls180.v:6645.97-6645.142" + cell $eq $eq$ls180.v:6645$2276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6645$2276_Y + end + attribute \src "ls180.v:6646.100-6646.145" + cell $eq $eq$ls180.v:6646$2280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6646$2280_Y + end + attribute \src "ls180.v:6648.107-6648.152" + cell $eq $eq$ls180.v:6648$2283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6648$2283_Y + end + attribute \src "ls180.v:6649.110-6649.155" + cell $eq $eq$ls180.v:6649$2287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6649$2287_Y + end + attribute \src "ls180.v:6651.100-6651.146" + cell $eq $eq$ls180.v:6651$2290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6651$2290_Y + end + attribute \src "ls180.v:6652.103-6652.149" + cell $eq $eq$ls180.v:6652$2294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6652$2294_Y + end + attribute \src "ls180.v:6654.100-6654.146" + cell $eq $eq$ls180.v:6654$2297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6654$2297_Y + end + attribute \src "ls180.v:6655.103-6655.149" + cell $eq $eq$ls180.v:6655$2301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6655$2301_Y + end + attribute \src "ls180.v:6657.100-6657.146" + cell $eq $eq$ls180.v:6657$2304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6657$2304_Y + end + attribute \src "ls180.v:6658.103-6658.149" + cell $eq $eq$ls180.v:6658$2308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6658$2308_Y + end + attribute \src "ls180.v:6660.100-6660.146" + cell $eq $eq$ls180.v:6660$2311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6660$2311_Y + end + attribute \src "ls180.v:6661.103-6661.149" + cell $eq $eq$ls180.v:6661$2315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6661$2315_Y + end + attribute \src "ls180.v:6663.112-6663.158" + cell $eq $eq$ls180.v:6663$2318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6663$2318_Y + end + attribute \src "ls180.v:6664.115-6664.161" + cell $eq $eq$ls180.v:6664$2322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6664$2322_Y + end + attribute \src "ls180.v:6666.113-6666.159" + cell $eq $eq$ls180.v:6666$2325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6666$2325_Y + end + attribute \src "ls180.v:6667.116-6667.162" + cell $eq $eq$ls180.v:6667$2329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6667$2329_Y + end + attribute \src "ls180.v:6669.104-6669.150" + cell $eq $eq$ls180.v:6669$2332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6669$2332_Y + end + attribute \src "ls180.v:6670.107-6670.153" + cell $eq $eq$ls180.v:6670$2336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6670$2336_Y + end + attribute \src "ls180.v:6687.33-6687.79" + cell $eq $eq$ls180.v:6687$2338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [13:8] + connect \B 3'101 + connect \Y $eq$ls180.v:6687$2338_Y + end + attribute \src "ls180.v:6689.90-6689.135" + cell $eq $eq$ls180.v:6689$2340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6689$2340_Y + end + attribute \src "ls180.v:6690.93-6690.138" + cell $eq $eq$ls180.v:6690$2344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6690$2344_Y + end + attribute \src "ls180.v:6692.100-6692.145" + cell $eq $eq$ls180.v:6692$2347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6692$2347_Y + end + attribute \src "ls180.v:6693.103-6693.148" + cell $eq $eq$ls180.v:6693$2351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6693$2351_Y + end + attribute \src "ls180.v:6695.101-6695.146" + cell $eq $eq$ls180.v:6695$2354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6695$2354_Y + end + attribute \src "ls180.v:6696.104-6696.149" + cell $eq $eq$ls180.v:6696$2358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6696$2358_Y + end + attribute \src "ls180.v:6698.105-6698.150" + cell $eq $eq$ls180.v:6698$2361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6698$2361_Y + end + attribute \src "ls180.v:6699.108-6699.153" + cell $eq $eq$ls180.v:6699$2365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6699$2365_Y + end + attribute \src "ls180.v:6701.106-6701.151" + cell $eq $eq$ls180.v:6701$2368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6701$2368_Y + end + attribute \src "ls180.v:6702.109-6702.154" + cell $eq $eq$ls180.v:6702$2372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6702$2372_Y + end + attribute \src "ls180.v:6704.104-6704.149" + cell $eq $eq$ls180.v:6704$2375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6704$2375_Y + end + attribute \src "ls180.v:6705.107-6705.152" + cell $eq $eq$ls180.v:6705$2379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6705$2379_Y + end + attribute \src "ls180.v:6707.101-6707.146" + cell $eq $eq$ls180.v:6707$2382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6707$2382_Y + end + attribute \src "ls180.v:6708.104-6708.149" + cell $eq $eq$ls180.v:6708$2386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6708$2386_Y + end + attribute \src "ls180.v:6710.100-6710.145" + cell $eq $eq$ls180.v:6710$2389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6710$2389_Y + end + attribute \src "ls180.v:6711.103-6711.148" + cell $eq $eq$ls180.v:6711$2393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6711$2393_Y + end + attribute \src "ls180.v:6721.33-6721.79" + cell $eq $eq$ls180.v:6721$2395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [13:8] + connect \B 3'100 + connect \Y $eq$ls180.v:6721$2395_Y + end + attribute \src "ls180.v:6723.106-6723.151" + cell $eq $eq$ls180.v:6723$2397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6723$2397_Y + end + attribute \src "ls180.v:6724.109-6724.154" + cell $eq $eq$ls180.v:6724$2401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6724$2401_Y + end + attribute \src "ls180.v:6726.106-6726.151" + cell $eq $eq$ls180.v:6726$2404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6726$2404_Y + end + attribute \src "ls180.v:6727.109-6727.154" + cell $eq $eq$ls180.v:6727$2408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6727$2408_Y + end + attribute \src "ls180.v:6729.106-6729.151" + cell $eq $eq$ls180.v:6729$2411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6729$2411_Y + end + attribute \src "ls180.v:6730.109-6730.154" + cell $eq $eq$ls180.v:6730$2415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6730$2415_Y + end + attribute \src "ls180.v:6732.106-6732.151" + cell $eq $eq$ls180.v:6732$2418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6732$2418_Y + end + attribute \src "ls180.v:6733.109-6733.154" + cell $eq $eq$ls180.v:6733$2422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6733$2422_Y + end + attribute \src "ls180.v:7114.41-7114.81" + cell $eq $eq$ls180.v:7114$2459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:7114$2459_Y + end + attribute \src "ls180.v:7114.144-7114.177" + cell $eq $eq$ls180.v:7114$2460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7114$2460_Y + end + attribute \src "ls180.v:7114.219-7114.252" + cell $eq $eq$ls180.v:7114$2463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7114$2463_Y + end + attribute \src "ls180.v:7114.294-7114.327" + cell $eq $eq$ls180.v:7114$2466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7114$2466_Y + end + attribute \src "ls180.v:7138.41-7138.81" + cell $eq $eq$ls180.v:7138$2475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:7138$2475_Y + end + attribute \src "ls180.v:7138.144-7138.177" + cell $eq $eq$ls180.v:7138$2476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7138$2476_Y + end + attribute \src "ls180.v:7138.219-7138.252" + cell $eq $eq$ls180.v:7138$2479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7138$2479_Y + end + attribute \src "ls180.v:7138.294-7138.327" + cell $eq $eq$ls180.v:7138$2482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7138$2482_Y + end + attribute \src "ls180.v:7162.41-7162.81" + cell $eq $eq$ls180.v:7162$2491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:7162$2491_Y + end + attribute \src "ls180.v:7162.144-7162.177" + cell $eq $eq$ls180.v:7162$2492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7162$2492_Y + end + attribute \src "ls180.v:7162.219-7162.252" + cell $eq $eq$ls180.v:7162$2495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7162$2495_Y + end + attribute \src "ls180.v:7162.294-7162.327" + cell $eq $eq$ls180.v:7162$2498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7162$2498_Y + end + attribute \src "ls180.v:7186.41-7186.81" + cell $eq $eq$ls180.v:7186$2507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:7186$2507_Y + end + attribute \src "ls180.v:7186.144-7186.177" + cell $eq $eq$ls180.v:7186$2508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7186$2508_Y + end + attribute \src "ls180.v:7186.219-7186.252" + cell $eq $eq$ls180.v:7186$2511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7186$2511_Y + end + attribute \src "ls180.v:7186.294-7186.327" + cell $eq $eq$ls180.v:7186$2514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7186$2514_Y + end + attribute \src "ls180.v:7770.8-7770.38" + cell $eq $eq$ls180.v:7770$2606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $eq$ls180.v:7770$2606_Y + end + attribute \src "ls180.v:7817.8-7817.42" + cell $eq $eq$ls180.v:7817$2626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'0 + connect \Y $eq$ls180.v:7817$2626_Y + end + attribute \src "ls180.v:7837.38-7837.74" + cell $eq $eq$ls180.v:7837$2629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$ls180.v:7837$2629_Y + end + attribute \src "ls180.v:7844.7-7844.43" + cell $eq $eq$ls180.v:7844$2631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$ls180.v:7844$2631_Y + end + attribute \src "ls180.v:7851.7-7851.43" + cell $eq $eq$ls180.v:7851$2632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7851$2632_Y + end + attribute \src "ls180.v:7859.7-7859.43" + cell $eq $eq$ls180.v:7859$2633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7859$2633_Y + end + attribute \src "ls180.v:7911.9-7911.54" + cell $eq $eq$ls180.v:7911$2651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7911$2651_Y + end + attribute \src "ls180.v:7957.9-7957.54" + cell $eq $eq$ls180.v:7957$2667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7957$2667_Y + end + attribute \src "ls180.v:8003.9-8003.54" + cell $eq $eq$ls180.v:8003$2683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:8003$2683_Y + end + attribute \src "ls180.v:8049.9-8049.54" + cell $eq $eq$ls180.v:8049$2699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:8049$2699_Y + end + attribute \src "ls180.v:8199.9-8199.41" + cell $eq $eq$ls180.v:8199$2711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:8199$2711_Y + end + attribute \src "ls180.v:8214.9-8214.41" + cell $eq $eq$ls180.v:8214$2714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:8214$2714_Y + end + attribute \src "ls180.v:8220.49-8220.82" + cell $eq $eq$ls180.v:8220$2715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8220$2715_Y + end + attribute \src "ls180.v:8220.131-8220.164" + cell $eq $eq$ls180.v:8220$2718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8220$2718_Y + end + attribute \src "ls180.v:8220.213-8220.246" + cell $eq $eq$ls180.v:8220$2721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8220$2721_Y + end + attribute \src "ls180.v:8220.295-8220.328" + cell $eq $eq$ls180.v:8220$2724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8220$2724_Y + end + attribute \src "ls180.v:8221.50-8221.83" + cell $eq $eq$ls180.v:8221$2727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8221$2727_Y + end + attribute \src "ls180.v:8221.132-8221.165" + cell $eq $eq$ls180.v:8221$2730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8221$2730_Y + end + attribute \src "ls180.v:8221.214-8221.247" + cell $eq $eq$ls180.v:8221$2733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8221$2733_Y + end + attribute \src "ls180.v:8221.296-8221.329" + cell $eq $eq$ls180.v:8221$2736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8221$2736_Y + end + attribute \src "ls180.v:8256.9-8256.42" + cell $eq $eq$ls180.v:8256$2748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1000 + connect \Y $eq$ls180.v:8256$2748_Y + end + attribute \src "ls180.v:8259.10-8259.43" + cell $eq $eq$ls180.v:8259$2749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:8259$2749_Y + end + attribute \src "ls180.v:8285.9-8285.42" + cell $eq $eq$ls180.v:8285$2755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'0 + connect \Y $eq$ls180.v:8285$2755_Y + end + attribute \src "ls180.v:8290.10-8290.43" + cell $eq $eq$ls180.v:8290$2756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:8290$2756_Y + end + attribute \src "ls180.v:8497.9-8497.53" + cell $eq $eq$ls180.v:8497$2805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8497$2805_Y + end + attribute \src "ls180.v:8578.9-8578.54" + cell $eq $eq$ls180.v:8578$2817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8578$2817_Y + end + attribute \src "ls180.v:8657.9-8657.55" + cell $eq $eq$ls180.v:8657$2829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $eq$ls180.v:8657$2829_Y + end + attribute \src "ls180.v:8880.9-8880.49" + cell $eq $eq$ls180.v:8880$2862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8880$2862_Y + end + attribute \src "ls180.v:8456.8-8456.54" + cell $ge $ge$ls180.v:8456$2797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B $sub$ls180.v:8456$2796_Y + connect \Y $ge$ls180.v:8456$2797_Y + end + attribute \src "ls180.v:8470.8-8470.54" + cell $ge $ge$ls180.v:8470$2801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B $sub$ls180.v:8470$2800_Y + connect \Y $ge$ls180.v:8470$2801_Y + end + attribute \src "ls180.v:5339.47-5339.83" + cell $gt $gt$ls180.v:5339$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $gt$ls180.v:5339$1064_Y + end + attribute \src "ls180.v:5345.7-5345.43" + cell $lt $lt$ls180.v:5345$1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1000 + connect \Y $lt$ls180.v:5345$1067_Y + end + attribute \src "ls180.v:8451.8-8451.43" + cell $lt $lt$ls180.v:8451$2795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B \main_pwm0_width + connect \Y $lt$ls180.v:8451$2795_Y + end + attribute \src "ls180.v:8465.8-8465.43" + cell $lt $lt$ls180.v:8465$2799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B \main_pwm1_width + connect \Y $lt$ls180.v:8465$2799_Y + end + attribute \src "ls180.v:10370.33-10370.36" + cell $memrd $memrd$\mem$ls180.v:10370$2916 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$ls180.v:10370$2916_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10398.27-10398.32" + cell $memrd $memrd$\mem_1$ls180.v:10398$2942 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_1 + connect \CLK 1'x + connect \DATA $memrd$\mem_1$ls180.v:10398$2942_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10426.27-10426.32" + cell $memrd $memrd$\mem_2$ls180.v:10426$2968 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_2 + connect \CLK 1'x + connect \DATA $memrd$\mem_2$ls180.v:10426$2968_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10454.27-10454.32" + cell $memrd $memrd$\mem_3$ls180.v:10454$2994 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_3 + connect \CLK 1'x + connect \DATA $memrd$\mem_3$ls180.v:10454$2994_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10482.27-10482.32" + cell $memrd $memrd$\mem_4$ls180.v:10482$3020 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_4 + connect \CLK 1'x + connect \DATA $memrd$\mem_4$ls180.v:10482$3020_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10493.12-10493.19" + cell $memrd $memrd$\storage$ls180.v:10493$3025 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10493$3025_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10500.68-10500.75" + cell $memrd $memrd$\storage$ls180.v:10500$3027 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10500$3027_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10507.14-10507.23" + cell $memrd $memrd$\storage_1$ls180.v:10507$3032 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10507$3032_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10514.68-10514.77" + cell $memrd $memrd$\storage_1$ls180.v:10514$3034 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10514$3034_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10521.14-10521.23" + cell $memrd $memrd$\storage_2$ls180.v:10521$3039 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10521$3039_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10528.68-10528.77" + cell $memrd $memrd$\storage_2$ls180.v:10528$3041 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10528$3041_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10535.14-10535.23" + cell $memrd $memrd$\storage_3$ls180.v:10535$3046 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10535$3046_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10542.68-10542.77" + cell $memrd $memrd$\storage_3$ls180.v:10542$3048 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10542$3048_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10550.14-10550.23" + cell $memrd $memrd$\storage_4$ls180.v:10550$3053 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10550$3053_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10555.15-10555.24" + cell $memrd $memrd$\storage_4$ls180.v:10555$3055 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10555$3055_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10567.14-10567.23" + cell $memrd $memrd$\storage_5$ls180.v:10567$3060 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10567$3060_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10572.15-10572.24" + cell $memrd $memrd$\storage_5$ls180.v:10572$3062 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10572$3062_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10583.14-10583.23" + cell $memrd $memrd$\storage_6$ls180.v:10583$3067 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10583$3067_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10590.45-10590.54" + cell $memrd $memrd$\storage_6$ls180.v:10590$3069 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10590$3069_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10597.14-10597.23" + cell $memrd $memrd$\storage_7$ls180.v:10597$3074 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10597$3074_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10604.45-10604.54" + cell $memrd $memrd$\storage_7$ls180.v:10604$3076 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10604$3076_DATA + connect \EN 1'x + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3078 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3078 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10352$1_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10352$1_DATA + connect \EN $memwr$\mem$ls180.v:10352$1_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3079 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3079 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10354$2_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10354$2_DATA + connect \EN $memwr$\mem$ls180.v:10354$2_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3080 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3080 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10356$3_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10356$3_DATA + connect \EN $memwr$\mem$ls180.v:10356$3_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3081 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3081 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10358$4_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10358$4_DATA + connect \EN $memwr$\mem$ls180.v:10358$4_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3082 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3082 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10360$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10360$5_DATA + connect \EN $memwr$\mem$ls180.v:10360$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3083 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3083 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10362$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10362$6_DATA + connect \EN $memwr$\mem$ls180.v:10362$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3084 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3084 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10364$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10364$7_DATA + connect \EN $memwr$\mem$ls180.v:10364$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3085 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3085 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10366$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10366$8_DATA + connect \EN $memwr$\mem$ls180.v:10366$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3086 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3086 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10380$9_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10380$9_DATA + connect \EN $memwr$\mem_1$ls180.v:10380$9_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3087 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3087 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10382$10_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10382$10_DATA + connect \EN $memwr$\mem_1$ls180.v:10382$10_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3088 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3088 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10384$11_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10384$11_DATA + connect \EN $memwr$\mem_1$ls180.v:10384$11_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3089 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3089 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10386$12_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10386$12_DATA + connect \EN $memwr$\mem_1$ls180.v:10386$12_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3090 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3090 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10388$13_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10388$13_DATA + connect \EN $memwr$\mem_1$ls180.v:10388$13_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3091 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3091 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10390$14_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10390$14_DATA + connect \EN $memwr$\mem_1$ls180.v:10390$14_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3092 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3092 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10392$15_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10392$15_DATA + connect \EN $memwr$\mem_1$ls180.v:10392$15_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3093 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3093 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10394$16_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10394$16_DATA + connect \EN $memwr$\mem_1$ls180.v:10394$16_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3094 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3094 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10408$17_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10408$17_DATA + connect \EN $memwr$\mem_2$ls180.v:10408$17_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3095 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3095 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10410$18_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10410$18_DATA + connect \EN $memwr$\mem_2$ls180.v:10410$18_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3096 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3096 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10412$19_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10412$19_DATA + connect \EN $memwr$\mem_2$ls180.v:10412$19_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3097 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3097 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10414$20_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10414$20_DATA + connect \EN $memwr$\mem_2$ls180.v:10414$20_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3098 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3098 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10416$21_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10416$21_DATA + connect \EN $memwr$\mem_2$ls180.v:10416$21_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3099 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3099 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10418$22_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10418$22_DATA + connect \EN $memwr$\mem_2$ls180.v:10418$22_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3100 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3100 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10420$23_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10420$23_DATA + connect \EN $memwr$\mem_2$ls180.v:10420$23_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3101 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3101 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10422$24_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10422$24_DATA + connect \EN $memwr$\mem_2$ls180.v:10422$24_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3102 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3102 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10436$25_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10436$25_DATA + connect \EN $memwr$\mem_3$ls180.v:10436$25_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3103 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3103 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10438$26_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10438$26_DATA + connect \EN $memwr$\mem_3$ls180.v:10438$26_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3104 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3104 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10440$27_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10440$27_DATA + connect \EN $memwr$\mem_3$ls180.v:10440$27_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3105 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3105 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10442$28_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10442$28_DATA + connect \EN $memwr$\mem_3$ls180.v:10442$28_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3106 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3106 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10444$29_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10444$29_DATA + connect \EN $memwr$\mem_3$ls180.v:10444$29_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3107 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3107 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10446$30_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10446$30_DATA + connect \EN $memwr$\mem_3$ls180.v:10446$30_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3108 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3108 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10448$31_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10448$31_DATA + connect \EN $memwr$\mem_3$ls180.v:10448$31_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3109 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3109 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10450$32_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10450$32_DATA + connect \EN $memwr$\mem_3$ls180.v:10450$32_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3110 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3110 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10464$33_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10464$33_DATA + connect \EN $memwr$\mem_4$ls180.v:10464$33_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3111 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3111 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10466$34_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10466$34_DATA + connect \EN $memwr$\mem_4$ls180.v:10466$34_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3112 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3112 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10468$35_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10468$35_DATA + connect \EN $memwr$\mem_4$ls180.v:10468$35_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3113 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3113 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10470$36_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10470$36_DATA + connect \EN $memwr$\mem_4$ls180.v:10470$36_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3114 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3114 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10472$37_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10472$37_DATA + connect \EN $memwr$\mem_4$ls180.v:10472$37_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3115 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3115 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10474$38_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10474$38_DATA + connect \EN $memwr$\mem_4$ls180.v:10474$38_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3116 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3116 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10476$39_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10476$39_DATA + connect \EN $memwr$\mem_4$ls180.v:10476$39_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3117 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3117 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10478$40_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10478$40_DATA + connect \EN $memwr$\mem_4$ls180.v:10478$40_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$ls180.v:0$3118 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \PRIORITY 3118 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage$ls180.v:10492$41_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage$ls180.v:10492$41_DATA + connect \EN $memwr$\storage$ls180.v:10492$41_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_1$ls180.v:0$3119 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \PRIORITY 3119 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_1$ls180.v:10506$42_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_1$ls180.v:10506$42_DATA + connect \EN $memwr$\storage_1$ls180.v:10506$42_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_2$ls180.v:0$3120 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \PRIORITY 3120 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_2$ls180.v:10520$43_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_2$ls180.v:10520$43_DATA + connect \EN $memwr$\storage_2$ls180.v:10520$43_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_3$ls180.v:0$3121 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \PRIORITY 3121 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_3$ls180.v:10534$44_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_3$ls180.v:10534$44_DATA + connect \EN $memwr$\storage_3$ls180.v:10534$44_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_4$ls180.v:0$3122 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \PRIORITY 3122 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_4$ls180.v:10549$45_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_4$ls180.v:10549$45_DATA + connect \EN $memwr$\storage_4$ls180.v:10549$45_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_5$ls180.v:0$3123 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \PRIORITY 3123 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_5$ls180.v:10566$46_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_5$ls180.v:10566$46_DATA + connect \EN $memwr$\storage_5$ls180.v:10566$46_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_6$ls180.v:0$3124 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \PRIORITY 3124 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_6$ls180.v:10582$47_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_6$ls180.v:10582$47_DATA + connect \EN $memwr$\storage_6$ls180.v:10582$47_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_7$ls180.v:0$3125 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \PRIORITY 3125 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_7$ls180.v:10596$48_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_7$ls180.v:10596$48_DATA + connect \EN $memwr$\storage_7$ls180.v:10596$48_EN + end + attribute \src "ls180.v:3086.41-3086.71" + cell $ne $ne$ls180.v:3086$108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $ne$ls180.v:3086$108_Y + end + attribute \src "ls180.v:3303.70-3303.104" + cell $ne $ne$ls180.v:3303$222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:3303$222_Y + end + attribute \src "ls180.v:3364.8-3364.142" + cell $ne $ne$ls180.v:3364$241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3364$241_Y + end + attribute \src "ls180.v:3396.75-3396.133" + cell $ne $ne$ls180.v:3396$248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3396$248_Y + end + attribute \src "ls180.v:3397.75-3397.133" + cell $ne $ne$ls180.v:3397$249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3397$249_Y + end + attribute \src "ls180.v:3521.8-3521.142" + cell $ne $ne$ls180.v:3521$271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3521$271_Y + end + attribute \src "ls180.v:3553.75-3553.133" + cell $ne $ne$ls180.v:3553$278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3553$278_Y + end + attribute \src "ls180.v:3554.75-3554.133" + cell $ne $ne$ls180.v:3554$279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3554$279_Y + end + attribute \src "ls180.v:3678.8-3678.142" + cell $ne $ne$ls180.v:3678$301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3678$301_Y + end + attribute \src "ls180.v:3710.75-3710.133" + cell $ne $ne$ls180.v:3710$308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3710$308_Y + end + attribute \src "ls180.v:3711.75-3711.133" + cell $ne $ne$ls180.v:3711$309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3711$309_Y + end + attribute \src "ls180.v:3835.8-3835.142" + cell $ne $ne$ls180.v:3835$331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3835$331_Y + end + attribute \src "ls180.v:3867.75-3867.133" + cell $ne $ne$ls180.v:3867$338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3867$338_Y + end + attribute \src "ls180.v:3868.75-3868.133" + cell $ne $ne$ls180.v:3868$339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3868$339_Y + end + attribute \src "ls180.v:4360.47-4360.80" + cell $ne $ne$ls180.v:4360$737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4360$737_Y + end + attribute \src "ls180.v:4361.47-4361.79" + cell $ne $ne$ls180.v:4361$738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4361$738_Y + end + attribute \src "ls180.v:4390.47-4390.80" + cell $ne $ne$ls180.v:4390$748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4390$748_Y + end + attribute \src "ls180.v:4391.47-4391.79" + cell $ne $ne$ls180.v:4391$749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4391$749_Y + end + attribute \src "ls180.v:4871.32-4871.89" + cell $ne $ne$ls180.v:4871$831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $ne$ls180.v:4871$831_Y + end + attribute \src "ls180.v:5518.10-5518.56" + cell $ne $ne$ls180.v:5518$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 2'10 + connect \Y $ne$ls180.v:5518$1128_Y + end + attribute \src "ls180.v:5623.51-5623.87" + cell $ne $ne$ls180.v:5623$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5623$1142_Y + end + attribute \src "ls180.v:5624.51-5624.86" + cell $ne $ne$ls180.v:5624$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5624$1143_Y + end + attribute \src "ls180.v:5843.51-5843.87" + cell $ne $ne$ls180.v:5843$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5843$1173_Y + end + attribute \src "ls180.v:5844.51-5844.86" + cell $ne $ne$ls180.v:5844$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5844$1174_Y + end + attribute \src "ls180.v:5875.79-5875.119" + cell $ne $ne$ls180.v:5875$1177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$ls180.v:5875$1177_Y + end + attribute \src "ls180.v:7760.7-7760.52" + cell $ne $ne$ls180.v:7760$2601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$ls180.v:7760$2601_Y + end + attribute \src "ls180.v:7826.9-7826.43" + cell $ne $ne$ls180.v:7826$2627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:7826$2627_Y + end + attribute \src "ls180.v:7862.8-7862.44" + cell $ne $ne$ls180.v:7862$2634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$ls180.v:7862$2634_Y + end + attribute \src "ls180.v:8800.9-8800.47" + cell $ne $ne$ls180.v:8800$2849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1010 + connect \Y $ne$ls180.v:8800$2849_Y + end + attribute \src "ls180.v:2890.33-2890.73" + cell $not $not$ls180.v:2890$50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_converted_interface_cyc + connect \Y $not$ls180.v:2890$50_Y + end + attribute \src "ls180.v:2929.48-2929.69" + cell $not $not$ls180.v:2929$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2929$55_Y + end + attribute \src "ls180.v:2930.48-2930.69" + cell $not $not$ls180.v:2930$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2930$56_Y + end + attribute \src "ls180.v:2950.33-2950.73" + cell $not $not$ls180.v:2950$61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_converted_interface_cyc + connect \Y $not$ls180.v:2950$61_Y + end + attribute \src "ls180.v:2989.48-2989.69" + cell $not $not$ls180.v:2989$66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2989$66_Y + end + attribute \src "ls180.v:2990.48-2990.69" + cell $not $not$ls180.v:2990$67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2990$67_Y + end + attribute \src "ls180.v:3010.36-3010.79" + cell $not $not$ls180.v:3010$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_converted_interface_cyc + connect \Y $not$ls180.v:3010$72_Y + end + attribute \src "ls180.v:3049.27-3049.51" + cell $not $not$ls180.v:3049$77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:3049$77_Y + end + attribute \src "ls180.v:3050.27-3050.51" + cell $not $not$ls180.v:3050$78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:3050$78_Y + end + attribute \src "ls180.v:3252.34-3252.64" + cell $not $not$ls180.v:3252$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [0] + connect \Y $not$ls180.v:3252$214_Y + end + attribute \src "ls180.v:3253.31-3253.61" + cell $not $not$ls180.v:3253$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [1] + connect \Y $not$ls180.v:3253$215_Y + end + attribute \src "ls180.v:3254.32-3254.62" + cell $not $not$ls180.v:3254$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [2] + connect \Y $not$ls180.v:3254$216_Y + end + attribute \src "ls180.v:3255.32-3255.62" + cell $not $not$ls180.v:3255$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [3] + connect \Y $not$ls180.v:3255$217_Y + end + attribute \src "ls180.v:3297.33-3297.56" + cell $not $not$ls180.v:3297$220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:3297$220_Y + end + attribute \src "ls180.v:3398.58-3398.106" + cell $not $not$ls180.v:3398$250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:3398$250_Y + end + attribute \src "ls180.v:3452.9-3452.45" + cell $not $not$ls180.v:3452$255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_req + connect \Y $not$ls180.v:3452$255_Y + end + attribute \src "ls180.v:3555.58-3555.106" + cell $not $not$ls180.v:3555$280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:3555$280_Y + end + attribute \src "ls180.v:3609.9-3609.45" + cell $not $not$ls180.v:3609$285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_refresh_req + connect \Y $not$ls180.v:3609$285_Y + end + attribute \src "ls180.v:3712.58-3712.106" + cell $not $not$ls180.v:3712$310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:3712$310_Y + end + attribute \src "ls180.v:3766.9-3766.45" + cell $not $not$ls180.v:3766$315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_refresh_req + connect \Y $not$ls180.v:3766$315_Y + end + attribute \src "ls180.v:3869.58-3869.106" + cell $not $not$ls180.v:3869$340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:3869$340_Y + end + attribute \src "ls180.v:3923.9-3923.45" + cell $not $not$ls180.v:3923$345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_refresh_req + connect \Y $not$ls180.v:3923$345_Y + end + attribute \src "ls180.v:3965.149-3965.187" + cell $not $not$ls180.v:3965$348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3965$348_Y + end + attribute \src "ls180.v:3965.193-3965.230" + cell $not $not$ls180.v:3965$350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3965$350_Y + end + attribute \src "ls180.v:3966.149-3966.187" + cell $not $not$ls180.v:3966$354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3966$354_Y + end + attribute \src "ls180.v:3966.193-3966.230" + cell $not $not$ls180.v:3966$356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3966$356_Y + end + attribute \src "ls180.v:3982.43-3982.73" + cell $not $not$ls180.v:3982$384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \main_sdram_interface_wdata_we + connect \Y $not$ls180.v:3982$384_Y + end + attribute \src "ls180.v:3985.205-3985.245" + cell $not $not$ls180.v:3985$387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3985$387_Y + end + attribute \src "ls180.v:3985.251-3985.290" + cell $not $not$ls180.v:3985$389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3985$389_Y + end + attribute \src "ls180.v:3985.159-3985.292" + cell $not $not$ls180.v:3985$391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3985$390_Y + connect \Y $not$ls180.v:3985$391_Y + end + attribute \src "ls180.v:3986.205-3986.245" + cell $not $not$ls180.v:3986$400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3986$400_Y + end + attribute \src "ls180.v:3986.251-3986.290" + cell $not $not$ls180.v:3986$402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3986$402_Y + end + attribute \src "ls180.v:3986.159-3986.292" + cell $not $not$ls180.v:3986$404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3986$403_Y + connect \Y $not$ls180.v:3986$404_Y + end + attribute \src "ls180.v:3987.205-3987.245" + cell $not $not$ls180.v:3987$413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3987$413_Y + end + attribute \src "ls180.v:3987.251-3987.290" + cell $not $not$ls180.v:3987$415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3987$415_Y + end + attribute \src "ls180.v:3987.159-3987.292" + cell $not $not$ls180.v:3987$417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3987$416_Y + connect \Y $not$ls180.v:3987$417_Y + end + attribute \src "ls180.v:3988.205-3988.245" + cell $not $not$ls180.v:3988$426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3988$426_Y + end + attribute \src "ls180.v:3988.251-3988.290" + cell $not $not$ls180.v:3988$428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3988$428_Y + end + attribute \src "ls180.v:3988.159-3988.292" + cell $not $not$ls180.v:3988$430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$429_Y + connect \Y $not$ls180.v:3988$430_Y + end + attribute \src "ls180.v:4015.71-4015.103" + cell $not $not$ls180.v:4015$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \Y $not$ls180.v:4015$441_Y + end + attribute \src "ls180.v:4018.205-4018.245" + cell $not $not$ls180.v:4018$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:4018$445_Y + end + attribute \src "ls180.v:4018.251-4018.290" + cell $not $not$ls180.v:4018$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:4018$447_Y + end + attribute \src "ls180.v:4018.159-4018.292" + cell $not $not$ls180.v:4018$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4018$448_Y + connect \Y $not$ls180.v:4018$449_Y + end + attribute \src "ls180.v:4019.205-4019.245" + cell $not $not$ls180.v:4019$458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:4019$458_Y + end + attribute \src "ls180.v:4019.251-4019.290" + cell $not $not$ls180.v:4019$460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:4019$460_Y + end + attribute \src "ls180.v:4019.159-4019.292" + cell $not $not$ls180.v:4019$462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4019$461_Y + connect \Y $not$ls180.v:4019$462_Y + end + attribute \src "ls180.v:4020.205-4020.245" + cell $not $not$ls180.v:4020$471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:4020$471_Y + end + attribute \src "ls180.v:4020.251-4020.290" + cell $not $not$ls180.v:4020$473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:4020$473_Y + end + attribute \src "ls180.v:4020.159-4020.292" + cell $not $not$ls180.v:4020$475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4020$474_Y + connect \Y $not$ls180.v:4020$475_Y + end + attribute \src "ls180.v:4021.205-4021.245" + cell $not $not$ls180.v:4021$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:4021$484_Y + end + attribute \src "ls180.v:4021.251-4021.290" + cell $not $not$ls180.v:4021$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:4021$486_Y + end + attribute \src "ls180.v:4021.159-4021.292" + cell $not $not$ls180.v:4021$488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4021$487_Y + connect \Y $not$ls180.v:4021$488_Y + end + attribute \src "ls180.v:4084.71-4084.103" + cell $not $not$ls180.v:4084$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \Y $not$ls180.v:4084$527_Y + end + attribute \src "ls180.v:4105.112-4105.150" + cell $not $not$ls180.v:4105$530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:4105$530_Y + end + attribute \src "ls180.v:4105.156-4105.193" + cell $not $not$ls180.v:4105$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:4105$532_Y + end + attribute \src "ls180.v:4105.68-4105.195" + cell $not $not$ls180.v:4105$534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4105$533_Y + connect \Y $not$ls180.v:4105$534_Y + end + attribute \src "ls180.v:4113.11-4113.38" + cell $not $not$ls180.v:4113$537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_write_available + connect \Y $not$ls180.v:4113$537_Y + end + attribute \src "ls180.v:4143.112-4143.150" + cell $not $not$ls180.v:4143$539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:4143$539_Y + end + attribute \src "ls180.v:4143.156-4143.193" + cell $not $not$ls180.v:4143$541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:4143$541_Y + end + attribute \src "ls180.v:4143.68-4143.195" + cell $not $not$ls180.v:4143$543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4143$542_Y + connect \Y $not$ls180.v:4143$543_Y + end + attribute \src "ls180.v:4151.11-4151.37" + cell $not $not$ls180.v:4151$546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_read_available + connect \Y $not$ls180.v:4151$546_Y + end + attribute \src "ls180.v:4161.87-4161.331" + cell $not $not$ls180.v:4161$558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4161$557_Y + connect \Y $not$ls180.v:4161$558_Y + end + attribute \src "ls180.v:4162.35-4162.68" + cell $not $not$ls180.v:4162$561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_valid + connect \Y $not$ls180.v:4162$561_Y + end + attribute \src "ls180.v:4162.73-4162.105" + cell $not $not$ls180.v:4162$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \Y $not$ls180.v:4162$562_Y + end + attribute \src "ls180.v:4166.87-4166.331" + cell $not $not$ls180.v:4166$574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4166$573_Y + connect \Y $not$ls180.v:4166$574_Y + end + attribute \src "ls180.v:4167.35-4167.68" + cell $not $not$ls180.v:4167$577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_valid + connect \Y $not$ls180.v:4167$577_Y + end + attribute \src "ls180.v:4167.73-4167.105" + cell $not $not$ls180.v:4167$578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \Y $not$ls180.v:4167$578_Y + end + attribute \src "ls180.v:4171.87-4171.331" + cell $not $not$ls180.v:4171$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4171$589_Y + connect \Y $not$ls180.v:4171$590_Y + end + attribute \src "ls180.v:4172.35-4172.68" + cell $not $not$ls180.v:4172$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_valid + connect \Y $not$ls180.v:4172$593_Y + end + attribute \src "ls180.v:4172.73-4172.105" + cell $not $not$ls180.v:4172$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \Y $not$ls180.v:4172$594_Y + end + attribute \src "ls180.v:4176.87-4176.331" + cell $not $not$ls180.v:4176$606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4176$605_Y + connect \Y $not$ls180.v:4176$606_Y + end + attribute \src "ls180.v:4177.35-4177.68" + cell $not $not$ls180.v:4177$609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_valid + connect \Y $not$ls180.v:4177$609_Y + end + attribute \src "ls180.v:4177.73-4177.105" + cell $not $not$ls180.v:4177$610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \Y $not$ls180.v:4177$610_Y + end + attribute \src "ls180.v:4181.128-4181.372" + cell $not $not$ls180.v:4181$623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$622_Y + connect \Y $not$ls180.v:4181$623_Y + end + attribute \src "ls180.v:4181.502-4181.746" + cell $not $not$ls180.v:4181$639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$638_Y + connect \Y $not$ls180.v:4181$639_Y + end + attribute \src "ls180.v:4181.876-4181.1120" + cell $not $not$ls180.v:4181$655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$654_Y + connect \Y $not$ls180.v:4181$655_Y + end + attribute \src "ls180.v:4181.1250-4181.1494" + cell $not $not$ls180.v:4181$671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$670_Y + connect \Y $not$ls180.v:4181$671_Y + end + attribute \src "ls180.v:4203.32-4203.50" + cell $not $not$ls180.v:4203$677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_cyc + connect \Y $not$ls180.v:4203$677_Y + end + attribute \src "ls180.v:4242.30-4242.50" + cell $not $not$ls180.v:4242$682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4242$682_Y + end + attribute \src "ls180.v:4243.30-4243.50" + cell $not $not$ls180.v:4243$683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4243$683_Y + end + attribute \src "ls180.v:4268.27-4268.48" + cell $not $not$ls180.v:4268$689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \Y $not$ls180.v:4268$689_Y + end + attribute \src "ls180.v:4269.30-4269.50" + cell $not $not$ls180.v:4269$690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4269$690_Y + end + attribute \src "ls180.v:4270.80-4270.98" + cell $not $not$ls180.v:4270$692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cmd_consumed + connect \Y $not$ls180.v:4270$692_Y + end + attribute \src "ls180.v:4271.107-4271.127" + cell $not $not$ls180.v:4271$696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wdata_consumed + connect \Y $not$ls180.v:4271$696_Y + end + attribute \src "ls180.v:4272.78-4272.103" + cell $not $not$ls180.v:4272$699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_we + connect \Y $not$ls180.v:4272$699_Y + end + attribute \src "ls180.v:4273.91-4273.111" + cell $not $not$ls180.v:4273$702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4273$702_Y + end + attribute \src "ls180.v:4289.35-4289.64" + cell $not $not$ls180.v:4289$711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4289$711_Y + end + attribute \src "ls180.v:4290.36-4290.67" + cell $not $not$ls180.v:4290$712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_source_valid + connect \Y $not$ls180.v:4290$712_Y + end + attribute \src "ls180.v:4296.32-4296.61" + cell $not $not$ls180.v:4296$713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4296$713_Y + end + attribute \src "ls180.v:4302.36-4302.67" + cell $not $not$ls180.v:4302$714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4302$714_Y + end + attribute \src "ls180.v:4303.35-4303.64" + cell $not $not$ls180.v:4303$715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_sink_ready + connect \Y $not$ls180.v:4303$715_Y + end + attribute \src "ls180.v:4306.32-4306.63" + cell $not $not$ls180.v:4306$718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4306$718_Y + end + attribute \src "ls180.v:4344.81-4344.108" + cell $not $not$ls180.v:4344$728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_readable + connect \Y $not$ls180.v:4344$728_Y + end + attribute \src "ls180.v:4374.81-4374.108" + cell $not $not$ls180.v:4374$739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_readable + connect \Y $not$ls180.v:4374$739_Y + end + attribute \src "ls180.v:4585.60-4585.85" + cell $not $not$ls180.v:4585$790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk_d + connect \Y $not$ls180.v:4585$790_Y + end + attribute \src "ls180.v:4726.54-4726.96" + cell $not $not$ls180.v:4726$804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \Y $not$ls180.v:4726$804_Y + end + attribute \src "ls180.v:4729.48-4729.86" + cell $not $not$ls180.v:4729$807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:4729$807_Y + end + attribute \src "ls180.v:4853.55-4853.98" + cell $not $not$ls180.v:4853$825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_strobe_all + connect \Y $not$ls180.v:4853$825_Y + end + attribute \src "ls180.v:4856.49-4856.88" + cell $not $not$ls180.v:4856$828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:4856$828_Y + end + attribute \src "ls180.v:4906.30-4906.58" + cell $not $not$ls180.v:4906$834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \Y $not$ls180.v:4906$834_Y + end + attribute \src "ls180.v:4987.56-4987.100" + cell $not $not$ls180.v:4987$840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_strobe_all + connect \Y $not$ls180.v:4987$840_Y + end + attribute \src "ls180.v:4990.50-4990.90" + cell $not $not$ls180.v:4990$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:4990$843_Y + end + attribute \src "ls180.v:5106.42-5106.74" + cell $not $not$ls180.v:5106$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_valid + connect \Y $not$ls180.v:5106$859_Y + end + attribute \src "ls180.v:5630.50-5630.88" + cell $not $not$ls180.v:5630$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_strobe_all + connect \Y $not$ls180.v:5630$1144_Y + end + attribute \src "ls180.v:5642.52-5642.102" + cell $not $not$ls180.v:5642$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \Y $not$ls180.v:5642$1147_Y + end + attribute \src "ls180.v:5701.38-5701.74" + cell $not $not$ls180.v:5701$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_enable_storage + connect \Y $not$ls180.v:5701$1154_Y + end + attribute \src "ls180.v:6027.69-6027.88" + cell $not $not$ls180.v:6027$1239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \Y $not$ls180.v:6027$1239_Y + end + attribute \src "ls180.v:6044.63-6044.94" + cell $not $not$ls180.v:6044$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6044$1284_Y + end + attribute \src "ls180.v:6047.65-6047.96" + cell $not $not$ls180.v:6047$1291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6047$1291_Y + end + attribute \src "ls180.v:6050.65-6050.96" + cell $not $not$ls180.v:6050$1298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6050$1298_Y + end + attribute \src "ls180.v:6053.65-6053.96" + cell $not $not$ls180.v:6053$1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6053$1305_Y + end + attribute \src "ls180.v:6056.65-6056.96" + cell $not $not$ls180.v:6056$1312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6056$1312_Y + end + attribute \src "ls180.v:6059.68-6059.99" + cell $not $not$ls180.v:6059$1319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6059$1319_Y + end + attribute \src "ls180.v:6062.68-6062.99" + cell $not $not$ls180.v:6062$1326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6062$1326_Y + end + attribute \src "ls180.v:6065.68-6065.99" + cell $not $not$ls180.v:6065$1333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6065$1333_Y + end + attribute \src "ls180.v:6068.68-6068.99" + cell $not $not$ls180.v:6068$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6068$1340_Y + end + attribute \src "ls180.v:6082.60-6082.91" + cell $not $not$ls180.v:6082$1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6082$1348_Y + end + attribute \src "ls180.v:6085.60-6085.91" + cell $not $not$ls180.v:6085$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6085$1355_Y + end + attribute \src "ls180.v:6088.60-6088.91" + cell $not $not$ls180.v:6088$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6088$1362_Y + end + attribute \src "ls180.v:6091.60-6091.91" + cell $not $not$ls180.v:6091$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6091$1369_Y + end + attribute \src "ls180.v:6094.61-6094.92" + cell $not $not$ls180.v:6094$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6094$1376_Y + end + attribute \src "ls180.v:6097.61-6097.92" + cell $not $not$ls180.v:6097$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6097$1383_Y + end + attribute \src "ls180.v:6108.59-6108.90" + cell $not $not$ls180.v:6108$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:6108$1391_Y + end + attribute \src "ls180.v:6111.58-6111.89" + cell $not $not$ls180.v:6111$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:6111$1398_Y + end + attribute \src "ls180.v:6122.64-6122.95" + cell $not $not$ls180.v:6122$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6122$1406_Y + end + attribute \src "ls180.v:6125.63-6125.94" + cell $not $not$ls180.v:6125$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6125$1413_Y + end + attribute \src "ls180.v:6128.63-6128.94" + cell $not $not$ls180.v:6128$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6128$1420_Y + end + attribute \src "ls180.v:6131.63-6131.94" + cell $not $not$ls180.v:6131$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6131$1427_Y + end + attribute \src "ls180.v:6134.63-6134.94" + cell $not $not$ls180.v:6134$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6134$1434_Y + end + attribute \src "ls180.v:6137.64-6137.95" + cell $not $not$ls180.v:6137$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6137$1441_Y + end + attribute \src "ls180.v:6140.64-6140.95" + cell $not $not$ls180.v:6140$1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6140$1448_Y + end + attribute \src "ls180.v:6143.64-6143.95" + cell $not $not$ls180.v:6143$1455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6143$1455_Y + end + attribute \src "ls180.v:6146.64-6146.95" + cell $not $not$ls180.v:6146$1462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6146$1462_Y + end + attribute \src "ls180.v:6159.64-6159.95" + cell $not $not$ls180.v:6159$1470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6159$1470_Y + end + attribute \src "ls180.v:6162.63-6162.94" + cell $not $not$ls180.v:6162$1477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6162$1477_Y + end + attribute \src "ls180.v:6165.63-6165.94" + cell $not $not$ls180.v:6165$1484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6165$1484_Y + end + attribute \src "ls180.v:6168.63-6168.94" + cell $not $not$ls180.v:6168$1491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6168$1491_Y + end + attribute \src "ls180.v:6171.63-6171.94" + cell $not $not$ls180.v:6171$1498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6171$1498_Y + end + attribute \src "ls180.v:6174.64-6174.95" + cell $not $not$ls180.v:6174$1505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6174$1505_Y + end + attribute \src "ls180.v:6177.64-6177.95" + cell $not $not$ls180.v:6177$1512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6177$1512_Y + end + attribute \src "ls180.v:6180.64-6180.95" + cell $not $not$ls180.v:6180$1519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6180$1519_Y + end + attribute \src "ls180.v:6183.64-6183.95" + cell $not $not$ls180.v:6183$1526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6183$1526_Y + end + attribute \src "ls180.v:6196.66-6196.97" + cell $not $not$ls180.v:6196$1534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6196$1534_Y + end + attribute \src "ls180.v:6199.66-6199.97" + cell $not $not$ls180.v:6199$1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6199$1541_Y + end + attribute \src "ls180.v:6202.66-6202.97" + cell $not $not$ls180.v:6202$1548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6202$1548_Y + end + attribute \src "ls180.v:6205.66-6205.97" + cell $not $not$ls180.v:6205$1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6205$1555_Y + end + attribute \src "ls180.v:6208.66-6208.97" + cell $not $not$ls180.v:6208$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6208$1562_Y + end + attribute \src "ls180.v:6211.66-6211.97" + cell $not $not$ls180.v:6211$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6211$1569_Y + end + attribute \src "ls180.v:6214.66-6214.97" + cell $not $not$ls180.v:6214$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6214$1576_Y + end + attribute \src "ls180.v:6217.66-6217.97" + cell $not $not$ls180.v:6217$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6217$1583_Y + end + attribute \src "ls180.v:6220.68-6220.99" + cell $not $not$ls180.v:6220$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6220$1590_Y + end + attribute \src "ls180.v:6223.68-6223.99" + cell $not $not$ls180.v:6223$1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6223$1597_Y + end + attribute \src "ls180.v:6226.68-6226.99" + cell $not $not$ls180.v:6226$1604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6226$1604_Y + end + attribute \src "ls180.v:6229.68-6229.99" + cell $not $not$ls180.v:6229$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6229$1611_Y + end + attribute \src "ls180.v:6232.68-6232.99" + cell $not $not$ls180.v:6232$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6232$1618_Y + end + attribute \src "ls180.v:6235.65-6235.96" + cell $not $not$ls180.v:6235$1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6235$1625_Y + end + attribute \src "ls180.v:6238.66-6238.97" + cell $not $not$ls180.v:6238$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6238$1632_Y + end + attribute \src "ls180.v:6258.70-6258.101" + cell $not $not$ls180.v:6258$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6258$1640_Y + end + attribute \src "ls180.v:6261.70-6261.101" + cell $not $not$ls180.v:6261$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6261$1647_Y + end + attribute \src "ls180.v:6264.70-6264.101" + cell $not $not$ls180.v:6264$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6264$1654_Y + end + attribute \src "ls180.v:6267.70-6267.101" + cell $not $not$ls180.v:6267$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6267$1661_Y + end + attribute \src "ls180.v:6270.69-6270.100" + cell $not $not$ls180.v:6270$1668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6270$1668_Y + end + attribute \src "ls180.v:6273.69-6273.100" + cell $not $not$ls180.v:6273$1675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6273$1675_Y + end + attribute \src "ls180.v:6276.69-6276.100" + cell $not $not$ls180.v:6276$1682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6276$1682_Y + end + attribute \src "ls180.v:6279.69-6279.100" + cell $not $not$ls180.v:6279$1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6279$1689_Y + end + attribute \src "ls180.v:6282.60-6282.91" + cell $not $not$ls180.v:6282$1696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6282$1696_Y + end + attribute \src "ls180.v:6285.71-6285.102" + cell $not $not$ls180.v:6285$1703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6285$1703_Y + end + attribute \src "ls180.v:6288.71-6288.102" + cell $not $not$ls180.v:6288$1710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6288$1710_Y + end + attribute \src "ls180.v:6291.71-6291.102" + cell $not $not$ls180.v:6291$1717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6291$1717_Y + end + attribute \src "ls180.v:6294.71-6294.102" + cell $not $not$ls180.v:6294$1724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6294$1724_Y + end + attribute \src "ls180.v:6297.71-6297.102" + cell $not $not$ls180.v:6297$1731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6297$1731_Y + end + attribute \src "ls180.v:6300.71-6300.102" + cell $not $not$ls180.v:6300$1738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6300$1738_Y + end + attribute \src "ls180.v:6303.70-6303.101" + cell $not $not$ls180.v:6303$1745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6303$1745_Y + end + attribute \src "ls180.v:6306.70-6306.101" + cell $not $not$ls180.v:6306$1752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6306$1752_Y + end + attribute \src "ls180.v:6309.70-6309.101" + cell $not $not$ls180.v:6309$1759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6309$1759_Y + end + attribute \src "ls180.v:6312.70-6312.101" + cell $not $not$ls180.v:6312$1766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6312$1766_Y + end + attribute \src "ls180.v:6315.70-6315.101" + cell $not $not$ls180.v:6315$1773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6315$1773_Y + end + attribute \src "ls180.v:6318.70-6318.101" + cell $not $not$ls180.v:6318$1780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6318$1780_Y + end + attribute \src "ls180.v:6321.70-6321.101" + cell $not $not$ls180.v:6321$1787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6321$1787_Y + end + attribute \src "ls180.v:6324.70-6324.101" + cell $not $not$ls180.v:6324$1794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6324$1794_Y + end + attribute \src "ls180.v:6327.70-6327.101" + cell $not $not$ls180.v:6327$1801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6327$1801_Y + end + attribute \src "ls180.v:6330.70-6330.101" + cell $not $not$ls180.v:6330$1808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6330$1808_Y + end + attribute \src "ls180.v:6333.66-6333.97" + cell $not $not$ls180.v:6333$1815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6333$1815_Y + end + attribute \src "ls180.v:6336.67-6336.98" + cell $not $not$ls180.v:6336$1822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6336$1822_Y + end + attribute \src "ls180.v:6339.70-6339.101" + cell $not $not$ls180.v:6339$1829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6339$1829_Y + end + attribute \src "ls180.v:6342.70-6342.101" + cell $not $not$ls180.v:6342$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6342$1836_Y + end + attribute \src "ls180.v:6345.69-6345.100" + cell $not $not$ls180.v:6345$1843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6345$1843_Y + end + attribute \src "ls180.v:6348.69-6348.100" + cell $not $not$ls180.v:6348$1850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6348$1850_Y + end + attribute \src "ls180.v:6351.69-6351.100" + cell $not $not$ls180.v:6351$1857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6351$1857_Y + end + attribute \src "ls180.v:6354.69-6354.100" + cell $not $not$ls180.v:6354$1864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6354$1864_Y + end + attribute \src "ls180.v:6393.66-6393.97" + cell $not $not$ls180.v:6393$1872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6393$1872_Y + end + attribute \src "ls180.v:6396.66-6396.97" + cell $not $not$ls180.v:6396$1879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6396$1879_Y + end + attribute \src "ls180.v:6399.66-6399.97" + cell $not $not$ls180.v:6399$1886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6399$1886_Y + end + attribute \src "ls180.v:6402.66-6402.97" + cell $not $not$ls180.v:6402$1893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6402$1893_Y + end + attribute \src "ls180.v:6405.66-6405.97" + cell $not $not$ls180.v:6405$1900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6405$1900_Y + end + attribute \src "ls180.v:6408.66-6408.97" + cell $not $not$ls180.v:6408$1907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6408$1907_Y + end + attribute \src "ls180.v:6411.66-6411.97" + cell $not $not$ls180.v:6411$1914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6411$1914_Y + end + attribute \src "ls180.v:6414.66-6414.97" + cell $not $not$ls180.v:6414$1921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6414$1921_Y + end + attribute \src "ls180.v:6417.68-6417.99" + cell $not $not$ls180.v:6417$1928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6417$1928_Y + end + attribute \src "ls180.v:6420.68-6420.99" + cell $not $not$ls180.v:6420$1935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6420$1935_Y + end + attribute \src "ls180.v:6423.68-6423.99" + cell $not $not$ls180.v:6423$1942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6423$1942_Y + end + attribute \src "ls180.v:6426.68-6426.99" + cell $not $not$ls180.v:6426$1949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6426$1949_Y + end + attribute \src "ls180.v:6429.68-6429.99" + cell $not $not$ls180.v:6429$1956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6429$1956_Y + end + attribute \src "ls180.v:6432.65-6432.96" + cell $not $not$ls180.v:6432$1963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6432$1963_Y + end + attribute \src "ls180.v:6435.66-6435.97" + cell $not $not$ls180.v:6435$1970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6435$1970_Y + end + attribute \src "ls180.v:6438.68-6438.99" + cell $not $not$ls180.v:6438$1977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6438$1977_Y + end + attribute \src "ls180.v:6441.68-6441.99" + cell $not $not$ls180.v:6441$1984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6441$1984_Y + end + attribute \src "ls180.v:6444.68-6444.99" + cell $not $not$ls180.v:6444$1991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6444$1991_Y + end + attribute \src "ls180.v:6447.68-6447.99" + cell $not $not$ls180.v:6447$1998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6447$1998_Y + end + attribute \src "ls180.v:6472.68-6472.99" + cell $not $not$ls180.v:6472$2006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6472$2006_Y + end + attribute \src "ls180.v:6475.73-6475.104" + cell $not $not$ls180.v:6475$2013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6475$2013_Y + end + attribute \src "ls180.v:6478.73-6478.104" + cell $not $not$ls180.v:6478$2020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6478$2020_Y + end + attribute \src "ls180.v:6481.66-6481.97" + cell $not $not$ls180.v:6481$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6481$2027_Y + end + attribute \src "ls180.v:6489.70-6489.101" + cell $not $not$ls180.v:6489$2035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6489$2035_Y + end + attribute \src "ls180.v:6492.74-6492.105" + cell $not $not$ls180.v:6492$2042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6492$2042_Y + end + attribute \src "ls180.v:6495.64-6495.95" + cell $not $not$ls180.v:6495$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6495$2049_Y + end + attribute \src "ls180.v:6498.74-6498.105" + cell $not $not$ls180.v:6498$2056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6498$2056_Y + end + attribute \src "ls180.v:6501.74-6501.105" + cell $not $not$ls180.v:6501$2063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6501$2063_Y + end + attribute \src "ls180.v:6504.75-6504.106" + cell $not $not$ls180.v:6504$2070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6504$2070_Y + end + attribute \src "ls180.v:6507.73-6507.104" + cell $not $not$ls180.v:6507$2077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6507$2077_Y + end + attribute \src "ls180.v:6510.73-6510.104" + cell $not $not$ls180.v:6510$2084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6510$2084_Y + end + attribute \src "ls180.v:6513.73-6513.104" + cell $not $not$ls180.v:6513$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6513$2091_Y + end + attribute \src "ls180.v:6516.73-6516.104" + cell $not $not$ls180.v:6516$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6516$2098_Y + end + attribute \src "ls180.v:6534.67-6534.99" + cell $not $not$ls180.v:6534$2106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6534$2106_Y + end + attribute \src "ls180.v:6537.67-6537.99" + cell $not $not$ls180.v:6537$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6537$2113_Y + end + attribute \src "ls180.v:6540.65-6540.97" + cell $not $not$ls180.v:6540$2120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6540$2120_Y + end + attribute \src "ls180.v:6543.64-6543.96" + cell $not $not$ls180.v:6543$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6543$2127_Y + end + attribute \src "ls180.v:6546.63-6546.95" + cell $not $not$ls180.v:6546$2134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6546$2134_Y + end + attribute \src "ls180.v:6549.62-6549.94" + cell $not $not$ls180.v:6549$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6549$2141_Y + end + attribute \src "ls180.v:6552.68-6552.100" + cell $not $not$ls180.v:6552$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6552$2148_Y + end + attribute \src "ls180.v:6574.67-6574.99" + cell $not $not$ls180.v:6574$2157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6574$2157_Y + end + attribute \src "ls180.v:6577.67-6577.99" + cell $not $not$ls180.v:6577$2164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6577$2164_Y + end + attribute \src "ls180.v:6580.65-6580.97" + cell $not $not$ls180.v:6580$2171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6580$2171_Y + end + attribute \src "ls180.v:6583.64-6583.96" + cell $not $not$ls180.v:6583$2178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6583$2178_Y + end + attribute \src "ls180.v:6586.63-6586.95" + cell $not $not$ls180.v:6586$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6586$2185_Y + end + attribute \src "ls180.v:6589.62-6589.94" + cell $not $not$ls180.v:6589$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6589$2192_Y + end + attribute \src "ls180.v:6592.68-6592.100" + cell $not $not$ls180.v:6592$2199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6592$2199_Y + end + attribute \src "ls180.v:6595.71-6595.103" + cell $not $not$ls180.v:6595$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6595$2206_Y + end + attribute \src "ls180.v:6598.71-6598.103" + cell $not $not$ls180.v:6598$2213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6598$2213_Y + end + attribute \src "ls180.v:6622.64-6622.96" + cell $not $not$ls180.v:6622$2222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6622$2222_Y + end + attribute \src "ls180.v:6625.64-6625.96" + cell $not $not$ls180.v:6625$2229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6625$2229_Y + end + attribute \src "ls180.v:6628.64-6628.96" + cell $not $not$ls180.v:6628$2236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6628$2236_Y + end + attribute \src "ls180.v:6631.64-6631.96" + cell $not $not$ls180.v:6631$2243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6631$2243_Y + end + attribute \src "ls180.v:6634.66-6634.98" + cell $not $not$ls180.v:6634$2250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6634$2250_Y + end + attribute \src "ls180.v:6637.66-6637.98" + cell $not $not$ls180.v:6637$2257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6637$2257_Y + end + attribute \src "ls180.v:6640.66-6640.98" + cell $not $not$ls180.v:6640$2264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6640$2264_Y + end + attribute \src "ls180.v:6643.66-6643.98" + cell $not $not$ls180.v:6643$2271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6643$2271_Y + end + attribute \src "ls180.v:6646.62-6646.94" + cell $not $not$ls180.v:6646$2278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6646$2278_Y + end + attribute \src "ls180.v:6649.72-6649.104" + cell $not $not$ls180.v:6649$2285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6649$2285_Y + end + attribute \src "ls180.v:6652.65-6652.97" + cell $not $not$ls180.v:6652$2292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6652$2292_Y + end + attribute \src "ls180.v:6655.65-6655.97" + cell $not $not$ls180.v:6655$2299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6655$2299_Y + end + attribute \src "ls180.v:6658.65-6658.97" + cell $not $not$ls180.v:6658$2306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6658$2306_Y + end + attribute \src "ls180.v:6661.65-6661.97" + cell $not $not$ls180.v:6661$2313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6661$2313_Y + end + attribute \src "ls180.v:6664.77-6664.109" + cell $not $not$ls180.v:6664$2320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6664$2320_Y + end + attribute \src "ls180.v:6667.78-6667.110" + cell $not $not$ls180.v:6667$2327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6667$2327_Y + end + attribute \src "ls180.v:6670.69-6670.101" + cell $not $not$ls180.v:6670$2334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6670$2334_Y + end + attribute \src "ls180.v:6690.55-6690.87" + cell $not $not$ls180.v:6690$2342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6690$2342_Y + end + attribute \src "ls180.v:6693.65-6693.97" + cell $not $not$ls180.v:6693$2349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6693$2349_Y + end + attribute \src "ls180.v:6696.66-6696.98" + cell $not $not$ls180.v:6696$2356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6696$2356_Y + end + attribute \src "ls180.v:6699.70-6699.102" + cell $not $not$ls180.v:6699$2363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6699$2363_Y + end + attribute \src "ls180.v:6702.71-6702.103" + cell $not $not$ls180.v:6702$2370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6702$2370_Y + end + attribute \src "ls180.v:6705.69-6705.101" + cell $not $not$ls180.v:6705$2377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6705$2377_Y + end + attribute \src "ls180.v:6708.66-6708.98" + cell $not $not$ls180.v:6708$2384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6708$2384_Y + end + attribute \src "ls180.v:6711.65-6711.97" + cell $not $not$ls180.v:6711$2391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6711$2391_Y + end + attribute \src "ls180.v:6724.71-6724.103" + cell $not $not$ls180.v:6724$2399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6724$2399_Y + end + attribute \src "ls180.v:6727.71-6727.103" + cell $not $not$ls180.v:6727$2406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6727$2406_Y + end + attribute \src "ls180.v:6730.71-6730.103" + cell $not $not$ls180.v:6730$2413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6730$2413_Y + end + attribute \src "ls180.v:6733.71-6733.103" + cell $not $not$ls180.v:6733$2420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6733$2420_Y + end + attribute \src "ls180.v:7114.86-7114.330" + cell $not $not$ls180.v:7114$2469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7114$2468_Y + connect \Y $not$ls180.v:7114$2469_Y + end + attribute \src "ls180.v:7138.86-7138.330" + cell $not $not$ls180.v:7138$2485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7138$2484_Y + connect \Y $not$ls180.v:7138$2485_Y + end + attribute \src "ls180.v:7162.86-7162.330" + cell $not $not$ls180.v:7162$2501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7162$2500_Y + connect \Y $not$ls180.v:7162$2501_Y + end + attribute \src "ls180.v:7186.86-7186.330" + cell $not $not$ls180.v:7186$2517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7186$2516_Y + connect \Y $not$ls180.v:7186$2517_Y + end + attribute \src "ls180.v:7687.18-7687.42" + cell $not $not$ls180.v:7687$2571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk0 + connect \Y $not$ls180.v:7687$2571_Y + end + attribute \src "ls180.v:7766.72-7766.101" + cell $not $not$ls180.v:7766$2604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \Y $not$ls180.v:7766$2604_Y + end + attribute \src "ls180.v:7785.8-7785.38" + cell $not $not$ls180.v:7785$2608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_zero_trigger + connect \Y $not$ls180.v:7785$2608_Y + end + attribute \src "ls180.v:7789.70-7789.98" + cell $not $not$ls180.v:7789$2611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_ack + connect \Y $not$ls180.v:7789$2611_Y + end + attribute \src "ls180.v:7793.70-7793.98" + cell $not $not$ls180.v:7793$2614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_ack + connect \Y $not$ls180.v:7793$2614_Y + end + attribute \src "ls180.v:7797.70-7797.98" + cell $not $not$ls180.v:7797$2617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_ack + connect \Y $not$ls180.v:7797$2617_Y + end + attribute \src "ls180.v:7801.70-7801.98" + cell $not $not$ls180.v:7801$2620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_ack + connect \Y $not$ls180.v:7801$2620_Y + end + attribute \src "ls180.v:7809.32-7809.55" + cell $not $not$ls180.v:7809$2622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:7809$2622_Y + end + attribute \src "ls180.v:7879.136-7879.189" + cell $not $not$ls180.v:7879$2637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7879$2637_Y + end + attribute \src "ls180.v:7885.136-7885.189" + cell $not $not$ls180.v:7885$2642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7885$2642_Y + end + attribute \src "ls180.v:7886.8-7886.61" + cell $not $not$ls180.v:7886$2644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7886$2644_Y + end + attribute \src "ls180.v:7894.8-7894.56" + cell $not $not$ls180.v:7894$2647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:7894$2647_Y + end + attribute \src "ls180.v:7909.8-7909.46" + cell $not $not$ls180.v:7909$2649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \Y $not$ls180.v:7909$2649_Y + end + attribute \src "ls180.v:7925.136-7925.189" + cell $not $not$ls180.v:7925$2653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7925$2653_Y + end + attribute \src "ls180.v:7931.136-7931.189" + cell $not $not$ls180.v:7931$2658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7931$2658_Y + end + attribute \src "ls180.v:7932.8-7932.61" + cell $not $not$ls180.v:7932$2660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7932$2660_Y + end + attribute \src "ls180.v:7940.8-7940.56" + cell $not $not$ls180.v:7940$2663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:7940$2663_Y + end + attribute \src "ls180.v:7955.8-7955.46" + cell $not $not$ls180.v:7955$2665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \Y $not$ls180.v:7955$2665_Y + end + attribute \src "ls180.v:7971.136-7971.189" + cell $not $not$ls180.v:7971$2669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7971$2669_Y + end + attribute \src "ls180.v:7977.136-7977.189" + cell $not $not$ls180.v:7977$2674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7977$2674_Y + end + attribute \src "ls180.v:7978.8-7978.61" + cell $not $not$ls180.v:7978$2676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7978$2676_Y + end + attribute \src "ls180.v:7986.8-7986.56" + cell $not $not$ls180.v:7986$2679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:7986$2679_Y + end + attribute \src "ls180.v:8001.8-8001.46" + cell $not $not$ls180.v:8001$2681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \Y $not$ls180.v:8001$2681_Y + end + attribute \src "ls180.v:8017.136-8017.189" + cell $not $not$ls180.v:8017$2685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:8017$2685_Y + end + attribute \src "ls180.v:8023.136-8023.189" + cell $not $not$ls180.v:8023$2690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:8023$2690_Y + end + attribute \src "ls180.v:8024.8-8024.61" + cell $not $not$ls180.v:8024$2692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:8024$2692_Y + end + attribute \src "ls180.v:8032.8-8032.56" + cell $not $not$ls180.v:8032$2695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:8032$2695_Y + end + attribute \src "ls180.v:8047.8-8047.46" + cell $not $not$ls180.v:8047$2697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \Y $not$ls180.v:8047$2697_Y + end + attribute \src "ls180.v:8055.7-8055.22" + cell $not $not$ls180.v:8055$2700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en0 + connect \Y $not$ls180.v:8055$2700_Y + end + attribute \src "ls180.v:8058.8-8058.29" + cell $not $not$ls180.v:8058$2701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time0 + connect \Y $not$ls180.v:8058$2701_Y + end + attribute \src "ls180.v:8062.7-8062.22" + cell $not $not$ls180.v:8062$2703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en1 + connect \Y $not$ls180.v:8062$2703_Y + end + attribute \src "ls180.v:8065.8-8065.29" + cell $not $not$ls180.v:8065$2704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time1 + connect \Y $not$ls180.v:8065$2704_Y + end + attribute \src "ls180.v:8184.30-8184.60" + cell $not $not$ls180.v:8184$2706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed2 + connect \Y $not$ls180.v:8184$2706_Y + end + attribute \src "ls180.v:8185.30-8185.60" + cell $not $not$ls180.v:8185$2707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed3 + connect \Y $not$ls180.v:8185$2707_Y + end + attribute \src "ls180.v:8186.29-8186.59" + cell $not $not$ls180.v:8186$2708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed4 + connect \Y $not$ls180.v:8186$2708_Y + end + attribute \src "ls180.v:8197.8-8197.33" + cell $not $not$ls180.v:8197$2709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_ready + connect \Y $not$ls180.v:8197$2709_Y + end + attribute \src "ls180.v:8212.8-8212.33" + cell $not $not$ls180.v:8212$2712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_ready + connect \Y $not$ls180.v:8212$2712_Y + end + attribute \src "ls180.v:8248.36-8248.58" + cell $not $not$ls180.v:8248$2742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_busy + connect \Y $not$ls180.v:8248$2742_Y + end + attribute \src "ls180.v:8248.64-8248.89" + cell $not $not$ls180.v:8248$2744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_ready + connect \Y $not$ls180.v:8248$2744_Y + end + attribute \src "ls180.v:8277.7-8277.29" + cell $not $not$ls180.v:8277$2751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_busy + connect \Y $not$ls180.v:8277$2751_Y + end + attribute \src "ls180.v:8278.9-8278.26" + cell $not $not$ls180.v:8278$2752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx + connect \Y $not$ls180.v:8278$2752_Y + end + attribute \src "ls180.v:8311.8-8311.29" + cell $not $not$ls180.v:8311$2758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_trigger + connect \Y $not$ls180.v:8311$2758_Y + end + attribute \src "ls180.v:8318.8-8318.29" + cell $not $not$ls180.v:8318$2760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_trigger + connect \Y $not$ls180.v:8318$2760_Y + end + attribute \src "ls180.v:8328.80-8328.106" + cell $not $not$ls180.v:8328$2763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8328$2763_Y + end + attribute \src "ls180.v:8334.80-8334.106" + cell $not $not$ls180.v:8334$2768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8334$2768_Y + end + attribute \src "ls180.v:8335.8-8335.34" + cell $not $not$ls180.v:8335$2770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_do_read + connect \Y $not$ls180.v:8335$2770_Y + end + attribute \src "ls180.v:8350.80-8350.106" + cell $not $not$ls180.v:8350$2774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8350$2774_Y + end + attribute \src "ls180.v:8356.80-8356.106" + cell $not $not$ls180.v:8356$2779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8356$2779_Y + end + attribute \src "ls180.v:8357.8-8357.34" + cell $not $not$ls180.v:8357$2781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_do_read + connect \Y $not$ls180.v:8357$2781_Y + end + attribute \src "ls180.v:8388.22-8388.41" + cell $not $not$ls180.v:8388$2785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster6_cs + connect \Y $not$ls180.v:8388$2785_Y + end + attribute \src "ls180.v:8388.46-8388.73" + cell $not $not$ls180.v:8388$2786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster26_cs_enable + connect \Y $not$ls180.v:8388$2786_Y + end + attribute \src "ls180.v:8423.22-8423.40" + cell $not $not$ls180.v:8423$2790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_cs + connect \Y $not$ls180.v:8423$2790_Y + end + attribute \src "ls180.v:8423.45-8423.70" + cell $not $not$ls180.v:8423$2791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_cs_enable + connect \Y $not$ls180.v:8423$2791_Y + end + attribute \src "ls180.v:8477.7-8477.31" + cell $not $not$ls180.v:8477$2802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_stop + connect \Y $not$ls180.v:8477$2802_Y + end + attribute \src "ls180.v:8549.8-8549.46" + cell $not $not$ls180.v:8549$2814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:8549$2814_Y + end + attribute \src "ls180.v:8630.8-8630.47" + cell $not $not$ls180.v:8630$2826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:8630$2826_Y + end + attribute \src "ls180.v:8691.8-8691.48" + cell $not $not$ls180.v:8691$2838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:8691$2838_Y + end + attribute \src "ls180.v:8861.88-8861.118" + cell $not $not$ls180.v:8861$2852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8861$2852_Y + end + attribute \src "ls180.v:8867.88-8867.118" + cell $not $not$ls180.v:8867$2857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8867$2857_Y + end + attribute \src "ls180.v:8868.8-8868.38" + cell $not $not$ls180.v:8868$2859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_do_read + connect \Y $not$ls180.v:8868$2859_Y + end + attribute \src "ls180.v:8959.88-8959.118" + cell $not $not$ls180.v:8959$2874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8959$2874_Y + end + attribute \src "ls180.v:8965.88-8965.118" + cell $not $not$ls180.v:8965$2879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8965$2879_Y + end + attribute \src "ls180.v:8966.8-8966.38" + cell $not $not$ls180.v:8966$2881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_do_read + connect \Y $not$ls180.v:8966$2881_Y + end + attribute \src "ls180.v:8986.9-8986.28" + cell $not $not$ls180.v:8986$2884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [0] + connect \Y $not$ls180.v:8986$2884_Y + end + attribute \src "ls180.v:9005.9-9005.28" + cell $not $not$ls180.v:9005$2885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [1] + connect \Y $not$ls180.v:9005$2885_Y + end + attribute \src "ls180.v:9024.9-9024.28" + cell $not $not$ls180.v:9024$2886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [2] + connect \Y $not$ls180.v:9024$2886_Y + end + attribute \src "ls180.v:9043.9-9043.28" + cell $not $not$ls180.v:9043$2887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [3] + connect \Y $not$ls180.v:9043$2887_Y + end + attribute \src "ls180.v:9062.9-9062.28" + cell $not $not$ls180.v:9062$2888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [4] + connect \Y $not$ls180.v:9062$2888_Y + end + attribute \src "ls180.v:9083.8-9083.21" + cell $not $not$ls180.v:9083$2889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_done + connect \Y $not$ls180.v:9083$2889_Y + end + attribute \src "ls180.v:10706.8-10706.51" + cell $or $or$ls180.v:10706$3077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sys_rst_1 + connect \B \main_libresocsim_libresoc_reset + connect \Y $or$ls180.v:10706$3077_Y + end + attribute \src "ls180.v:2931.10-2931.71" + cell $or $or$ls180.v:2931$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:2931$57_Y + end + attribute \src "ls180.v:2991.10-2991.71" + cell $or $or$ls180.v:2991$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:2991$68_Y + end + attribute \src "ls180.v:3051.10-3051.53" + cell $or $or$ls180.v:3051$79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:3051$79_Y + end + attribute \src "ls180.v:3303.39-3303.105" + cell $or $or$ls180.v:3303$223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start0 + connect \B $ne$ls180.v:3303$222_Y + connect \Y $or$ls180.v:3303$223_Y + end + attribute \src "ls180.v:3346.59-3346.140" + cell $or $or$ls180.v:3346$227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_req_wdata_ready + connect \B \main_sdram_bankmachine0_req_rdata_valid + connect \Y $or$ls180.v:3346$227_Y + end + attribute \src "ls180.v:3347.44-3347.151" + cell $or $or$ls180.v:3347$228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$ls180.v:3347$228_Y + end + attribute \src "ls180.v:3355.45-3355.170" + cell $or $or$ls180.v:3355$232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3355$231_Y + connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3355$232_Y + end + attribute \src "ls180.v:3392.127-3392.245" + cell $or $or$ls180.v:3392$245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3392$245_Y + end + attribute \src "ls180.v:3398.57-3398.157" + cell $or $or$ls180.v:3398$251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3398$250_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:3398$251_Y + end + attribute \src "ls180.v:3503.59-3503.140" + cell $or $or$ls180.v:3503$257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_req_wdata_ready + connect \B \main_sdram_bankmachine1_req_rdata_valid + connect \Y $or$ls180.v:3503$257_Y + end + attribute \src "ls180.v:3504.44-3504.151" + cell $or $or$ls180.v:3504$258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$ls180.v:3504$258_Y + end + attribute \src "ls180.v:3512.45-3512.170" + cell $or $or$ls180.v:3512$262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3512$261_Y + connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3512$262_Y + end + attribute \src "ls180.v:3549.127-3549.245" + cell $or $or$ls180.v:3549$275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3549$275_Y + end + attribute \src "ls180.v:3555.57-3555.157" + cell $or $or$ls180.v:3555$281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3555$280_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:3555$281_Y + end + attribute \src "ls180.v:3660.59-3660.140" + cell $or $or$ls180.v:3660$287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_req_wdata_ready + connect \B \main_sdram_bankmachine2_req_rdata_valid + connect \Y $or$ls180.v:3660$287_Y + end + attribute \src "ls180.v:3661.44-3661.151" + cell $or $or$ls180.v:3661$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$ls180.v:3661$288_Y + end + attribute \src "ls180.v:3669.45-3669.170" + cell $or $or$ls180.v:3669$292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3669$291_Y + connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3669$292_Y + end + attribute \src "ls180.v:3706.127-3706.245" + cell $or $or$ls180.v:3706$305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3706$305_Y + end + attribute \src "ls180.v:3712.57-3712.157" + cell $or $or$ls180.v:3712$311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3712$310_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:3712$311_Y + end + attribute \src "ls180.v:3817.59-3817.140" + cell $or $or$ls180.v:3817$317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_req_wdata_ready + connect \B \main_sdram_bankmachine3_req_rdata_valid + connect \Y $or$ls180.v:3817$317_Y + end + attribute \src "ls180.v:3818.44-3818.151" + cell $or $or$ls180.v:3818$318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$ls180.v:3818$318_Y + end + attribute \src "ls180.v:3826.45-3826.170" + cell $or $or$ls180.v:3826$322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3826$321_Y + connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3826$322_Y + end + attribute \src "ls180.v:3863.127-3863.245" + cell $or $or$ls180.v:3863$335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3863$335_Y + end + attribute \src "ls180.v:3869.57-3869.157" + cell $or $or$ls180.v:3869$341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3869$340_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:3869$341_Y + end + attribute \src "ls180.v:3968.107-3968.193" + cell $or $or$ls180.v:3968$361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_is_write + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $or$ls180.v:3968$361_Y + end + attribute \src "ls180.v:3971.39-3971.204" + cell $or $or$ls180.v:3971$367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3971$365_Y + connect \B $and$ls180.v:3971$366_Y + connect \Y $or$ls180.v:3971$367_Y + end + attribute \src "ls180.v:3971.38-3971.289" + cell $or $or$ls180.v:3971$369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3971$367_Y + connect \B $and$ls180.v:3971$368_Y + connect \Y $or$ls180.v:3971$369_Y + end + attribute \src "ls180.v:3971.37-3971.374" + cell $or $or$ls180.v:3971$371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3971$369_Y + connect \B $and$ls180.v:3971$370_Y + connect \Y $or$ls180.v:3971$371_Y + end + attribute \src "ls180.v:3972.40-3972.207" + cell $or $or$ls180.v:3972$374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3972$372_Y + connect \B $and$ls180.v:3972$373_Y + connect \Y $or$ls180.v:3972$374_Y + end + attribute \src "ls180.v:3972.39-3972.293" + cell $or $or$ls180.v:3972$376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3972$374_Y + connect \B $and$ls180.v:3972$375_Y + connect \Y $or$ls180.v:3972$376_Y + end + attribute \src "ls180.v:3972.38-3972.379" + cell $or $or$ls180.v:3972$378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3972$376_Y + connect \B $and$ls180.v:3972$377_Y + connect \Y $or$ls180.v:3972$378_Y + end + attribute \src "ls180.v:3985.158-3985.332" + cell $or $or$ls180.v:3985$392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3985$391_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3985$392_Y + end + attribute \src "ls180.v:3985.75-3985.506" + cell $or $or$ls180.v:3985$397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3985$393_Y + connect \B $and$ls180.v:3985$396_Y + connect \Y $or$ls180.v:3985$397_Y + end + attribute \src "ls180.v:3986.158-3986.332" + cell $or $or$ls180.v:3986$405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3986$404_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3986$405_Y + end + attribute \src "ls180.v:3986.75-3986.506" + cell $or $or$ls180.v:3986$410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3986$406_Y + connect \B $and$ls180.v:3986$409_Y + connect \Y $or$ls180.v:3986$410_Y + end + attribute \src "ls180.v:3987.158-3987.332" + cell $or $or$ls180.v:3987$418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3987$417_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3987$418_Y + end + attribute \src "ls180.v:3987.75-3987.506" + cell $or $or$ls180.v:3987$423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3987$419_Y + connect \B $and$ls180.v:3987$422_Y + connect \Y $or$ls180.v:3987$423_Y + end + attribute \src "ls180.v:3988.158-3988.332" + cell $or $or$ls180.v:3988$431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3988$430_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3988$431_Y + end + attribute \src "ls180.v:3988.75-3988.506" + cell $or $or$ls180.v:3988$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$432_Y + connect \B $and$ls180.v:3988$435_Y + connect \Y $or$ls180.v:3988$436_Y + end + attribute \src "ls180.v:4015.36-4015.104" + cell $or $or$ls180.v:4015$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_ready + connect \B $not$ls180.v:4015$441_Y + connect \Y $or$ls180.v:4015$442_Y + end + attribute \src "ls180.v:4018.158-4018.332" + cell $or $or$ls180.v:4018$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4018$449_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:4018$450_Y + end + attribute \src "ls180.v:4018.75-4018.506" + cell $or $or$ls180.v:4018$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4018$451_Y + connect \B $and$ls180.v:4018$454_Y + connect \Y $or$ls180.v:4018$455_Y + end + attribute \src "ls180.v:4019.158-4019.332" + cell $or $or$ls180.v:4019$463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4019$462_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:4019$463_Y + end + attribute \src "ls180.v:4019.75-4019.506" + cell $or $or$ls180.v:4019$468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4019$464_Y + connect \B $and$ls180.v:4019$467_Y + connect \Y $or$ls180.v:4019$468_Y + end + attribute \src "ls180.v:4020.158-4020.332" + cell $or $or$ls180.v:4020$476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4020$475_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:4020$476_Y + end + attribute \src "ls180.v:4020.75-4020.506" + cell $or $or$ls180.v:4020$481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4020$477_Y + connect \B $and$ls180.v:4020$480_Y + connect \Y $or$ls180.v:4020$481_Y + end + attribute \src "ls180.v:4021.158-4021.332" + cell $or $or$ls180.v:4021$489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4021$488_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:4021$489_Y + end + attribute \src "ls180.v:4021.75-4021.506" + cell $or $or$ls180.v:4021$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4021$490_Y + connect \B $and$ls180.v:4021$493_Y + connect \Y $or$ls180.v:4021$494_Y + end + attribute \src "ls180.v:4084.36-4084.104" + cell $or $or$ls180.v:4084$528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_ready + connect \B $not$ls180.v:4084$527_Y + connect \Y $or$ls180.v:4084$528_Y + end + attribute \src "ls180.v:4105.67-4105.221" + cell $or $or$ls180.v:4105$535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4105$534_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:4105$535_Y + end + attribute \src "ls180.v:4113.10-4113.62" + cell $or $or$ls180.v:4113$538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4113$537_Y + connect \B \main_sdram_max_time1 + connect \Y $or$ls180.v:4113$538_Y + end + attribute \src "ls180.v:4143.67-4143.221" + cell $or $or$ls180.v:4143$544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4143$543_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:4143$544_Y + end + attribute \src "ls180.v:4151.10-4151.61" + cell $or $or$ls180.v:4151$547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4151$546_Y + connect \B \main_sdram_max_time0 + connect \Y $or$ls180.v:4151$547_Y + end + attribute \src "ls180.v:4161.91-4161.180" + cell $or $or$ls180.v:4161$551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:4161$550_Y + connect \Y $or$ls180.v:4161$551_Y + end + attribute \src "ls180.v:4161.90-4161.255" + cell $or $or$ls180.v:4161$554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4161$551_Y + connect \B $and$ls180.v:4161$553_Y + connect \Y $or$ls180.v:4161$554_Y + end + attribute \src "ls180.v:4161.89-4161.330" + cell $or $or$ls180.v:4161$557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4161$554_Y + connect \B $and$ls180.v:4161$556_Y + connect \Y $or$ls180.v:4161$557_Y + end + attribute \src "ls180.v:4166.91-4166.180" + cell $or $or$ls180.v:4166$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:4166$566_Y + connect \Y $or$ls180.v:4166$567_Y + end + attribute \src "ls180.v:4166.90-4166.255" + cell $or $or$ls180.v:4166$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4166$567_Y + connect \B $and$ls180.v:4166$569_Y + connect \Y $or$ls180.v:4166$570_Y + end + attribute \src "ls180.v:4166.89-4166.330" + cell $or $or$ls180.v:4166$573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4166$570_Y + connect \B $and$ls180.v:4166$572_Y + connect \Y $or$ls180.v:4166$573_Y + end + attribute \src "ls180.v:4171.91-4171.180" + cell $or $or$ls180.v:4171$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:4171$582_Y + connect \Y $or$ls180.v:4171$583_Y + end + attribute \src "ls180.v:4171.90-4171.255" + cell $or $or$ls180.v:4171$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4171$583_Y + connect \B $and$ls180.v:4171$585_Y + connect \Y $or$ls180.v:4171$586_Y + end + attribute \src "ls180.v:4171.89-4171.330" + cell $or $or$ls180.v:4171$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4171$586_Y + connect \B $and$ls180.v:4171$588_Y + connect \Y $or$ls180.v:4171$589_Y + end + attribute \src "ls180.v:4176.91-4176.180" + cell $or $or$ls180.v:4176$599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:4176$598_Y + connect \Y $or$ls180.v:4176$599_Y + end + attribute \src "ls180.v:4176.90-4176.255" + cell $or $or$ls180.v:4176$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4176$599_Y + connect \B $and$ls180.v:4176$601_Y + connect \Y $or$ls180.v:4176$602_Y + end + attribute \src "ls180.v:4176.89-4176.330" + cell $or $or$ls180.v:4176$605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4176$602_Y + connect \B $and$ls180.v:4176$604_Y + connect \Y $or$ls180.v:4176$605_Y + end + attribute \src "ls180.v:4181.132-4181.221" + cell $or $or$ls180.v:4181$616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:4181$615_Y + connect \Y $or$ls180.v:4181$616_Y + end + attribute \src "ls180.v:4181.131-4181.296" + cell $or $or$ls180.v:4181$619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$616_Y + connect \B $and$ls180.v:4181$618_Y + connect \Y $or$ls180.v:4181$619_Y + end + attribute \src "ls180.v:4181.130-4181.371" + cell $or $or$ls180.v:4181$622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$619_Y + connect \B $and$ls180.v:4181$621_Y + connect \Y $or$ls180.v:4181$622_Y + end + attribute \src "ls180.v:4181.34-4181.411" + cell $or $or$ls180.v:4181$627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:4181$626_Y + connect \Y $or$ls180.v:4181$627_Y + end + attribute \src "ls180.v:4181.506-4181.595" + cell $or $or$ls180.v:4181$632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:4181$631_Y + connect \Y $or$ls180.v:4181$632_Y + end + attribute \src "ls180.v:4181.505-4181.670" + cell $or $or$ls180.v:4181$635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$632_Y + connect \B $and$ls180.v:4181$634_Y + connect \Y $or$ls180.v:4181$635_Y + end + attribute \src "ls180.v:4181.504-4181.745" + cell $or $or$ls180.v:4181$638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$635_Y + connect \B $and$ls180.v:4181$637_Y + connect \Y $or$ls180.v:4181$638_Y + end + attribute \src "ls180.v:4181.33-4181.785" + cell $or $or$ls180.v:4181$643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$627_Y + connect \B $and$ls180.v:4181$642_Y + connect \Y $or$ls180.v:4181$643_Y + end + attribute \src "ls180.v:4181.880-4181.969" + cell $or $or$ls180.v:4181$648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:4181$647_Y + connect \Y $or$ls180.v:4181$648_Y + end + attribute \src "ls180.v:4181.879-4181.1044" + cell $or $or$ls180.v:4181$651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$648_Y + connect \B $and$ls180.v:4181$650_Y + connect \Y $or$ls180.v:4181$651_Y + end + attribute \src "ls180.v:4181.878-4181.1119" + cell $or $or$ls180.v:4181$654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$651_Y + connect \B $and$ls180.v:4181$653_Y + connect \Y $or$ls180.v:4181$654_Y + end + attribute \src "ls180.v:4181.32-4181.1159" + cell $or $or$ls180.v:4181$659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$643_Y + connect \B $and$ls180.v:4181$658_Y + connect \Y $or$ls180.v:4181$659_Y + end + attribute \src "ls180.v:4181.1254-4181.1343" + cell $or $or$ls180.v:4181$664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:4181$663_Y + connect \Y $or$ls180.v:4181$664_Y + end + attribute \src "ls180.v:4181.1253-4181.1418" + cell $or $or$ls180.v:4181$667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$664_Y + connect \B $and$ls180.v:4181$666_Y + connect \Y $or$ls180.v:4181$667_Y + end + attribute \src "ls180.v:4181.1252-4181.1493" + cell $or $or$ls180.v:4181$670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$667_Y + connect \B $and$ls180.v:4181$669_Y + connect \Y $or$ls180.v:4181$670_Y + end + attribute \src "ls180.v:4181.31-4181.1533" + cell $or $or$ls180.v:4181$675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$659_Y + connect \B $and$ls180.v:4181$674_Y + connect \Y $or$ls180.v:4181$675_Y + end + attribute \src "ls180.v:4244.10-4244.52" + cell $or $or$ls180.v:4244$684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:4244$684_Y + end + attribute \src "ls180.v:4271.35-4271.74" + cell $or $or$ls180.v:4271$694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4271$694_Y + end + attribute \src "ls180.v:4272.34-4272.73" + cell $or $or$ls180.v:4272$698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4272$698_Y + end + attribute \src "ls180.v:4273.48-4273.130" + cell $or $or$ls180.v:4273$704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4273$701_Y + connect \B $and$ls180.v:4273$703_Y + connect \Y $or$ls180.v:4273$704_Y + end + attribute \src "ls180.v:4274.24-4274.87" + cell $or $or$ls180.v:4274$707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4274$706_Y + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4274$707_Y + end + attribute \src "ls180.v:4275.26-4275.95" + cell $or $or$ls180.v:4275$709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4275$708_Y + connect \B \main_wdata_consumed + connect \Y $or$ls180.v:4275$709_Y + end + attribute \src "ls180.v:4305.42-4305.89" + cell $or $or$ls180.v:4305$717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_clear + connect \B $and$ls180.v:4305$716_Y + connect \Y $or$ls180.v:4305$717_Y + end + attribute \src "ls180.v:4329.25-4329.174" + cell $or $or$ls180.v:4329$727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4329$725_Y + connect \B $and$ls180.v:4329$726_Y + connect \Y $or$ls180.v:4329$727_Y + end + attribute \src "ls180.v:4344.80-4344.132" + cell $or $or$ls180.v:4344$729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4344$728_Y + connect \B \main_uart_tx_fifo_re + connect \Y $or$ls180.v:4344$729_Y + end + attribute \src "ls180.v:4355.72-4355.135" + cell $or $or$ls180.v:4355$734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_writable + connect \B \main_uart_tx_fifo_replace + connect \Y $or$ls180.v:4355$734_Y + end + attribute \src "ls180.v:4374.80-4374.132" + cell $or $or$ls180.v:4374$740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4374$739_Y + connect \B \main_uart_rx_fifo_re + connect \Y $or$ls180.v:4374$740_Y + end + attribute \src "ls180.v:4385.72-4385.135" + cell $or $or$ls180.v:4385$745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_writable + connect \B \main_uart_rx_fifo_replace + connect \Y $or$ls180.v:4385$745_Y + end + attribute \src "ls180.v:4530.36-4530.111" + cell $or $or$ls180.v:4530$768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_clk + connect \B \main_sdphy_cmdw_pads_out_payload_clk + connect \Y $or$ls180.v:4530$768_Y + end + attribute \src "ls180.v:4530.35-4530.151" + cell $or $or$ls180.v:4530$769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4530$768_Y + connect \B \main_sdphy_cmdr_pads_out_payload_clk + connect \Y $or$ls180.v:4530$769_Y + end + attribute \src "ls180.v:4530.34-4530.192" + cell $or $or$ls180.v:4530$770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4530$769_Y + connect \B \main_sdphy_dataw_pads_out_payload_clk + connect \Y $or$ls180.v:4530$770_Y + end + attribute \src "ls180.v:4530.33-4530.233" + cell $or $or$ls180.v:4530$771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4530$770_Y + connect \B \main_sdphy_datar_pads_out_payload_clk + connect \Y $or$ls180.v:4530$771_Y + end + attribute \src "ls180.v:4531.39-4531.120" + cell $or $or$ls180.v:4531$772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_oe + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4531$772_Y + end + attribute \src "ls180.v:4531.38-4531.163" + cell $or $or$ls180.v:4531$773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4531$772_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4531$773_Y + end + attribute \src "ls180.v:4531.37-4531.207" + cell $or $or$ls180.v:4531$774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4531$773_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4531$774_Y + end + attribute \src "ls180.v:4531.36-4531.251" + cell $or $or$ls180.v:4531$775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4531$774_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4531$775_Y + end + attribute \src "ls180.v:4532.38-4532.117" + cell $or $or$ls180.v:4532$776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_o + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4532$776_Y + end + attribute \src "ls180.v:4532.37-4532.159" + cell $or $or$ls180.v:4532$777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4532$776_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4532$777_Y + end + attribute \src "ls180.v:4532.36-4532.202" + cell $or $or$ls180.v:4532$778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4532$777_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4532$778_Y + end + attribute \src "ls180.v:4532.35-4532.245" + cell $or $or$ls180.v:4532$779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4532$778_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4532$779_Y + end + attribute \src "ls180.v:4533.40-4533.123" + cell $or $or$ls180.v:4533$780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_data_oe + connect \B \main_sdphy_cmdw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4533$780_Y + end + attribute \src "ls180.v:4533.39-4533.167" + cell $or $or$ls180.v:4533$781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4533$780_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_oe + connect \Y $or$ls180.v:4533$781_Y + end + attribute \src "ls180.v:4533.38-4533.212" + cell $or $or$ls180.v:4533$782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4533$781_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4533$782_Y + end + attribute \src "ls180.v:4533.37-4533.257" + cell $or $or$ls180.v:4533$783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4533$782_Y + connect \B \main_sdphy_datar_pads_out_payload_data_oe + connect \Y $or$ls180.v:4533$783_Y + end + attribute \src "ls180.v:4534.39-4534.120" + cell $or $or$ls180.v:4534$784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_init_pads_out_payload_data_o + connect \B \main_sdphy_cmdw_pads_out_payload_data_o + connect \Y $or$ls180.v:4534$784_Y + end + attribute \src "ls180.v:4534.38-4534.163" + cell $or $or$ls180.v:4534$785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4534$784_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_o + connect \Y $or$ls180.v:4534$785_Y + end + attribute \src "ls180.v:4534.37-4534.207" + cell $or $or$ls180.v:4534$786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4534$785_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_o + connect \Y $or$ls180.v:4534$786_Y + end + attribute \src "ls180.v:4534.36-4534.251" + cell $or $or$ls180.v:4534$787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4534$786_Y + connect \B \main_sdphy_datar_pads_out_payload_data_o + connect \Y $or$ls180.v:4534$787_Y + end + attribute \src "ls180.v:4555.35-4555.80" + cell $or $or$ls180.v:4555$788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_stop + connect \B \main_sdphy_datar_stop + connect \Y $or$ls180.v:4555$788_Y + end + attribute \src "ls180.v:4709.91-4709.144" + cell $or $or$ls180.v:4709$802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:4709$802_Y + end + attribute \src "ls180.v:4726.53-4726.143" + cell $or $or$ls180.v:4726$805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4726$804_Y + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $or$ls180.v:4726$805_Y + end + attribute \src "ls180.v:4729.47-4729.127" + cell $or $or$ls180.v:4729$808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4729$807_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:4729$808_Y + end + attribute \src "ls180.v:4853.54-4853.146" + cell $or $or$ls180.v:4853$826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4853$825_Y + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $or$ls180.v:4853$826_Y + end + attribute \src "ls180.v:4856.48-4856.130" + cell $or $or$ls180.v:4856$829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4856$828_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:4856$829_Y + end + attribute \src "ls180.v:4987.55-4987.149" + cell $or $or$ls180.v:4987$841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4987$840_Y + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $or$ls180.v:4987$841_Y + end + attribute \src "ls180.v:4990.49-4990.133" + cell $or $or$ls180.v:4990$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4990$843_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:4990$844_Y + end + attribute \src "ls180.v:5619.80-5619.151" + cell $or $or$ls180.v:5619$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_writable + connect \B \main_sdblock2mem_fifo_replace + connect \Y $or$ls180.v:5619$1139_Y + end + attribute \src "ls180.v:5630.49-5630.131" + cell $or $or$ls180.v:5630$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:5630$1144_Y + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $or$ls180.v:5630$1145_Y + end + attribute \src "ls180.v:5839.80-5839.151" + cell $or $or$ls180.v:5839$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_writable + connect \B \main_sdmem2block_fifo_replace + connect \Y $or$ls180.v:5839$1170_Y + end + attribute \src "ls180.v:6026.41-6026.99" + cell $or $or$ls180.v:6026$1226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_err + connect \B \main_interface0_ram_bus_err + connect \Y $or$ls180.v:6026$1226_Y + end + attribute \src "ls180.v:6026.40-6026.130" + cell $or $or$ls180.v:6026$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1226_Y + connect \B \main_interface1_ram_bus_err + connect \Y $or$ls180.v:6026$1227_Y + end + attribute \src "ls180.v:6026.39-6026.161" + cell $or $or$ls180.v:6026$1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1227_Y + connect \B \main_interface2_ram_bus_err + connect \Y $or$ls180.v:6026$1228_Y + end + attribute \src "ls180.v:6026.38-6026.192" + cell $or $or$ls180.v:6026$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1228_Y + connect \B \main_interface3_ram_bus_err + connect \Y $or$ls180.v:6026$1229_Y + end + attribute \src "ls180.v:6026.37-6026.235" + cell $or $or$ls180.v:6026$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1229_Y + connect \B \main_interface0_converted_interface_err + connect \Y $or$ls180.v:6026$1230_Y + end + attribute \src "ls180.v:6026.36-6026.278" + cell $or $or$ls180.v:6026$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1230_Y + connect \B \main_interface1_converted_interface_err + connect \Y $or$ls180.v:6026$1231_Y + end + attribute \src "ls180.v:6026.35-6026.322" + cell $or $or$ls180.v:6026$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1231_Y + connect \B \main_libresocsim_libresoc_interface0_err + connect \Y $or$ls180.v:6026$1232_Y + end + attribute \src "ls180.v:6026.34-6026.366" + cell $or $or$ls180.v:6026$1233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1232_Y + connect \B \main_libresocsim_libresoc_interface1_err + connect \Y $or$ls180.v:6026$1233_Y + end + attribute \src "ls180.v:6026.33-6026.410" + cell $or $or$ls180.v:6026$1234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1233_Y + connect \B \main_libresocsim_libresoc_interface2_err + connect \Y $or$ls180.v:6026$1234_Y + end + attribute \src "ls180.v:6026.32-6026.454" + cell $or $or$ls180.v:6026$1235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1234_Y + connect \B \main_libresocsim_libresoc_interface3_err + connect \Y $or$ls180.v:6026$1235_Y + end + attribute \src "ls180.v:6026.31-6026.500" + cell $or $or$ls180.v:6026$1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1235_Y + connect \B \main_socbushandler_converted_interface_err + connect \Y $or$ls180.v:6026$1236_Y + end + attribute \src "ls180.v:6026.30-6026.547" + cell $or $or$ls180.v:6026$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1236_Y + connect \B \builder_libresocsim_converted_interface_err + connect \Y $or$ls180.v:6026$1237_Y + end + attribute \src "ls180.v:6032.36-6032.94" + cell $or $or$ls180.v:6032$1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \B \main_interface0_ram_bus_ack + connect \Y $or$ls180.v:6032$1242_Y + end + attribute \src "ls180.v:6032.35-6032.125" + cell $or $or$ls180.v:6032$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1242_Y + connect \B \main_interface1_ram_bus_ack + connect \Y $or$ls180.v:6032$1243_Y + end + attribute \src "ls180.v:6032.34-6032.156" + cell $or $or$ls180.v:6032$1244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1243_Y + connect \B \main_interface2_ram_bus_ack + connect \Y $or$ls180.v:6032$1244_Y + end + attribute \src "ls180.v:6032.33-6032.187" + cell $or $or$ls180.v:6032$1245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1244_Y + connect \B \main_interface3_ram_bus_ack + connect \Y $or$ls180.v:6032$1245_Y + end + attribute \src "ls180.v:6032.32-6032.230" + cell $or $or$ls180.v:6032$1246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1245_Y + connect \B \main_interface0_converted_interface_ack + connect \Y $or$ls180.v:6032$1246_Y + end + attribute \src "ls180.v:6032.31-6032.273" + cell $or $or$ls180.v:6032$1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1246_Y + connect \B \main_interface1_converted_interface_ack + connect \Y $or$ls180.v:6032$1247_Y + end + attribute \src "ls180.v:6032.30-6032.317" + cell $or $or$ls180.v:6032$1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1247_Y + connect \B \main_libresocsim_libresoc_interface0_ack + connect \Y $or$ls180.v:6032$1248_Y + end + attribute \src "ls180.v:6032.29-6032.361" + cell $or $or$ls180.v:6032$1249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1248_Y + connect \B \main_libresocsim_libresoc_interface1_ack + connect \Y $or$ls180.v:6032$1249_Y + end + attribute \src "ls180.v:6032.28-6032.405" + cell $or $or$ls180.v:6032$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1249_Y + connect \B \main_libresocsim_libresoc_interface2_ack + connect \Y $or$ls180.v:6032$1250_Y + end + attribute \src "ls180.v:6032.27-6032.449" + cell $or $or$ls180.v:6032$1251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1250_Y + connect \B \main_libresocsim_libresoc_interface3_ack + connect \Y $or$ls180.v:6032$1251_Y + end + attribute \src "ls180.v:6032.26-6032.495" + cell $or $or$ls180.v:6032$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1251_Y + connect \B \main_socbushandler_converted_interface_ack + connect \Y $or$ls180.v:6032$1252_Y + end + attribute \src "ls180.v:6032.25-6032.542" + cell $or $or$ls180.v:6032$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1252_Y + connect \B \builder_libresocsim_converted_interface_ack + connect \Y $or$ls180.v:6032$1253_Y + end + attribute \src "ls180.v:6033.38-6033.166" + cell $or $or$ls180.v:6033$1256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $and$ls180.v:6033$1254_Y + connect \B $and$ls180.v:6033$1255_Y + connect \Y $or$ls180.v:6033$1256_Y + end + attribute \src "ls180.v:6033.37-6033.232" + cell $or $or$ls180.v:6033$1258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1256_Y + connect \B $and$ls180.v:6033$1257_Y + connect \Y $or$ls180.v:6033$1258_Y + end + attribute \src "ls180.v:6033.36-6033.298" + cell $or $or$ls180.v:6033$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1258_Y + connect \B $and$ls180.v:6033$1259_Y + connect \Y $or$ls180.v:6033$1260_Y + end + attribute \src "ls180.v:6033.35-6033.364" + cell $or $or$ls180.v:6033$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1260_Y + connect \B $and$ls180.v:6033$1261_Y + connect \Y $or$ls180.v:6033$1262_Y + end + attribute \src "ls180.v:6033.34-6033.442" + cell $or $or$ls180.v:6033$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1262_Y + connect \B $and$ls180.v:6033$1263_Y + connect \Y $or$ls180.v:6033$1264_Y + end + attribute \src "ls180.v:6033.33-6033.520" + cell $or $or$ls180.v:6033$1266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1264_Y + connect \B $and$ls180.v:6033$1265_Y + connect \Y $or$ls180.v:6033$1266_Y + end + attribute \src "ls180.v:6033.32-6033.599" + cell $or $or$ls180.v:6033$1268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1266_Y + connect \B $and$ls180.v:6033$1267_Y + connect \Y $or$ls180.v:6033$1268_Y + end + attribute \src "ls180.v:6033.31-6033.678" + cell $or $or$ls180.v:6033$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1268_Y + connect \B $and$ls180.v:6033$1269_Y + connect \Y $or$ls180.v:6033$1270_Y + end + attribute \src "ls180.v:6033.30-6033.757" + cell $or $or$ls180.v:6033$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1270_Y + connect \B $and$ls180.v:6033$1271_Y + connect \Y $or$ls180.v:6033$1272_Y + end + attribute \src "ls180.v:6033.29-6033.837" + cell $or $or$ls180.v:6033$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1272_Y + connect \B $and$ls180.v:6033$1273_Y + connect \Y $or$ls180.v:6033$1274_Y + end + attribute \src "ls180.v:6033.28-6033.919" + cell $or $or$ls180.v:6033$1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1274_Y + connect \B $and$ls180.v:6033$1275_Y + connect \Y $or$ls180.v:6033$1276_Y + end + attribute \src "ls180.v:6033.27-6033.1002" + cell $or $or$ls180.v:6033$1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1276_Y + connect \B $and$ls180.v:6033$1277_Y + connect \Y $or$ls180.v:6033$1278_Y + end + attribute \src "ls180.v:6787.55-6787.124" + cell $or $or$ls180.v:6787$2424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \builder_interface0_bank_bus_dat_r + connect \B \builder_interface1_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2424_Y + end + attribute \src "ls180.v:6787.54-6787.161" + cell $or $or$ls180.v:6787$2425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2424_Y + connect \B \builder_interface2_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2425_Y + end + attribute \src "ls180.v:6787.53-6787.198" + cell $or $or$ls180.v:6787$2426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2425_Y + connect \B \builder_interface3_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2426_Y + end + attribute \src "ls180.v:6787.52-6787.235" + cell $or $or$ls180.v:6787$2427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2426_Y + connect \B \builder_interface4_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2427_Y + end + attribute \src "ls180.v:6787.51-6787.272" + cell $or $or$ls180.v:6787$2428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2427_Y + connect \B \builder_interface5_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2428_Y + end + attribute \src "ls180.v:6787.50-6787.309" + cell $or $or$ls180.v:6787$2429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2428_Y + connect \B \builder_interface6_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2429_Y + end + attribute \src "ls180.v:6787.49-6787.346" + cell $or $or$ls180.v:6787$2430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2429_Y + connect \B \builder_interface7_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2430_Y + end + attribute \src "ls180.v:6787.48-6787.383" + cell $or $or$ls180.v:6787$2431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2430_Y + connect \B \builder_interface8_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2431_Y + end + attribute \src "ls180.v:6787.47-6787.420" + cell $or $or$ls180.v:6787$2432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2431_Y + connect \B \builder_interface9_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2432_Y + end + attribute \src "ls180.v:6787.46-6787.458" + cell $or $or$ls180.v:6787$2433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2432_Y + connect \B \builder_interface10_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2433_Y + end + attribute \src "ls180.v:6787.45-6787.496" + cell $or $or$ls180.v:6787$2434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2433_Y + connect \B \builder_interface11_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2434_Y + end + attribute \src "ls180.v:6787.44-6787.534" + cell $or $or$ls180.v:6787$2435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2434_Y + connect \B \builder_interface12_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2435_Y + end + attribute \src "ls180.v:6787.43-6787.572" + cell $or $or$ls180.v:6787$2436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2435_Y + connect \B \builder_interface13_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2436_Y + end + attribute \src "ls180.v:6787.42-6787.610" + cell $or $or$ls180.v:6787$2437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2436_Y + connect \B \builder_interface14_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2437_Y + end + attribute \src "ls180.v:7114.90-7114.179" + cell $or $or$ls180.v:7114$2462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:7114$2461_Y + connect \Y $or$ls180.v:7114$2462_Y + end + attribute \src "ls180.v:7114.89-7114.254" + cell $or $or$ls180.v:7114$2465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7114$2462_Y + connect \B $and$ls180.v:7114$2464_Y + connect \Y $or$ls180.v:7114$2465_Y + end + attribute \src "ls180.v:7114.88-7114.329" + cell $or $or$ls180.v:7114$2468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7114$2465_Y + connect \B $and$ls180.v:7114$2467_Y + connect \Y $or$ls180.v:7114$2468_Y + end + attribute \src "ls180.v:7138.90-7138.179" + cell $or $or$ls180.v:7138$2478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:7138$2477_Y + connect \Y $or$ls180.v:7138$2478_Y + end + attribute \src "ls180.v:7138.89-7138.254" + cell $or $or$ls180.v:7138$2481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7138$2478_Y + connect \B $and$ls180.v:7138$2480_Y + connect \Y $or$ls180.v:7138$2481_Y + end + attribute \src "ls180.v:7138.88-7138.329" + cell $or $or$ls180.v:7138$2484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7138$2481_Y + connect \B $and$ls180.v:7138$2483_Y + connect \Y $or$ls180.v:7138$2484_Y + end + attribute \src "ls180.v:7162.90-7162.179" + cell $or $or$ls180.v:7162$2494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:7162$2493_Y + connect \Y $or$ls180.v:7162$2494_Y + end + attribute \src "ls180.v:7162.89-7162.254" + cell $or $or$ls180.v:7162$2497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7162$2494_Y + connect \B $and$ls180.v:7162$2496_Y + connect \Y $or$ls180.v:7162$2497_Y + end + attribute \src "ls180.v:7162.88-7162.329" + cell $or $or$ls180.v:7162$2500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7162$2497_Y + connect \B $and$ls180.v:7162$2499_Y + connect \Y $or$ls180.v:7162$2500_Y + end + attribute \src "ls180.v:7186.90-7186.179" + cell $or $or$ls180.v:7186$2510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:7186$2509_Y + connect \Y $or$ls180.v:7186$2510_Y + end + attribute \src "ls180.v:7186.89-7186.254" + cell $or $or$ls180.v:7186$2513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7186$2510_Y + connect \B $and$ls180.v:7186$2512_Y + connect \Y $or$ls180.v:7186$2513_Y + end + attribute \src "ls180.v:7186.88-7186.329" + cell $or $or$ls180.v:7186$2516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7186$2513_Y + connect \B $and$ls180.v:7186$2515_Y + connect \Y $or$ls180.v:7186$2516_Y + end + attribute \src "ls180.v:7703.20-7703.71" + cell $or $or$ls180.v:7703$2574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [0] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7703$2574_Y + end + attribute \src "ls180.v:7704.20-7704.71" + cell $or $or$ls180.v:7704$2575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [1] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7704$2575_Y + end + attribute \src "ls180.v:7705.20-7705.71" + cell $or $or$ls180.v:7705$2576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [2] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7705$2576_Y + end + attribute \src "ls180.v:7706.20-7706.71" + cell $or $or$ls180.v:7706$2577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [3] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7706$2577_Y + end + attribute \src "ls180.v:7707.20-7707.71" + cell $or $or$ls180.v:7707$2578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [4] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7707$2578_Y + end + attribute \src "ls180.v:7708.20-7708.71" + cell $or $or$ls180.v:7708$2579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [5] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7708$2579_Y + end + attribute \src "ls180.v:7709.20-7709.71" + cell $or $or$ls180.v:7709$2580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [6] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7709$2580_Y + end + attribute \src "ls180.v:7710.20-7710.71" + cell $or $or$ls180.v:7710$2581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [7] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7710$2581_Y + end + attribute \src "ls180.v:7711.20-7711.71" + cell $or $or$ls180.v:7711$2582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [8] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7711$2582_Y + end + attribute \src "ls180.v:7712.20-7712.71" + cell $or $or$ls180.v:7712$2583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [9] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7712$2583_Y + end + attribute \src "ls180.v:7713.21-7713.73" + cell $or $or$ls180.v:7713$2584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [10] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7713$2584_Y + end + attribute \src "ls180.v:7714.21-7714.73" + cell $or $or$ls180.v:7714$2585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [11] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7714$2585_Y + end + attribute \src "ls180.v:7715.21-7715.73" + cell $or $or$ls180.v:7715$2586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [12] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7715$2586_Y + end + attribute \src "ls180.v:7716.21-7716.73" + cell $or $or$ls180.v:7716$2587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [13] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7716$2587_Y + end + attribute \src "ls180.v:7717.21-7717.73" + cell $or $or$ls180.v:7717$2588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [14] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7717$2588_Y + end + attribute \src "ls180.v:7718.21-7718.73" + cell $or $or$ls180.v:7718$2589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [15] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7718$2589_Y + end + attribute \src "ls180.v:7719.21-7719.73" + cell $or $or$ls180.v:7719$2590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [16] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7719$2590_Y + end + attribute \src "ls180.v:7720.21-7720.73" + cell $or $or$ls180.v:7720$2591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [17] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7720$2591_Y + end + attribute \src "ls180.v:7721.21-7721.73" + cell $or $or$ls180.v:7721$2592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [18] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7721$2592_Y + end + attribute \src "ls180.v:7722.21-7722.73" + cell $or $or$ls180.v:7722$2593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [19] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7722$2593_Y + end + attribute \src "ls180.v:7723.21-7723.73" + cell $or $or$ls180.v:7723$2594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [20] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7723$2594_Y + end + attribute \src "ls180.v:7724.21-7724.73" + cell $or $or$ls180.v:7724$2595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [21] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7724$2595_Y + end + attribute \src "ls180.v:7725.21-7725.73" + cell $or $or$ls180.v:7725$2596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [22] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7725$2596_Y + end + attribute \src "ls180.v:7726.21-7726.73" + cell $or $or$ls180.v:7726$2597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [23] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7726$2597_Y + end + attribute \src "ls180.v:7727.7-7727.68" + cell $or $or$ls180.v:7727$2598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:7727$2598_Y + end + attribute \src "ls180.v:7738.7-7738.68" + cell $or $or$ls180.v:7738$2599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:7738$2599_Y + end + attribute \src "ls180.v:7749.7-7749.50" + cell $or $or$ls180.v:7749$2600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:7749$2600_Y + end + attribute \src "ls180.v:7894.7-7894.107" + cell $or $or$ls180.v:7894$2648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7894$2647_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:7894$2648_Y + end + attribute \src "ls180.v:7940.7-7940.107" + cell $or $or$ls180.v:7940$2664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7940$2663_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:7940$2664_Y + end + attribute \src "ls180.v:7986.7-7986.107" + cell $or $or$ls180.v:7986$2680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7986$2679_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:7986$2680_Y + end + attribute \src "ls180.v:8032.7-8032.107" + cell $or $or$ls180.v:8032$2696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8032$2695_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:8032$2696_Y + end + attribute \src "ls180.v:8220.40-8220.125" + cell $or $or$ls180.v:8220$2717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:8220$2716_Y + connect \Y $or$ls180.v:8220$2717_Y + end + attribute \src "ls180.v:8220.39-8220.207" + cell $or $or$ls180.v:8220$2720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8220$2717_Y + connect \B $and$ls180.v:8220$2719_Y + connect \Y $or$ls180.v:8220$2720_Y + end + attribute \src "ls180.v:8220.38-8220.289" + cell $or $or$ls180.v:8220$2723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8220$2720_Y + connect \B $and$ls180.v:8220$2722_Y + connect \Y $or$ls180.v:8220$2723_Y + end + attribute \src "ls180.v:8220.37-8220.371" + cell $or $or$ls180.v:8220$2726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8220$2723_Y + connect \B $and$ls180.v:8220$2725_Y + connect \Y $or$ls180.v:8220$2726_Y + end + attribute \src "ls180.v:8221.41-8221.126" + cell $or $or$ls180.v:8221$2729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:8221$2728_Y + connect \Y $or$ls180.v:8221$2729_Y + end + attribute \src "ls180.v:8221.40-8221.208" + cell $or $or$ls180.v:8221$2732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8221$2729_Y + connect \B $and$ls180.v:8221$2731_Y + connect \Y $or$ls180.v:8221$2732_Y + end + attribute \src "ls180.v:8221.39-8221.290" + cell $or $or$ls180.v:8221$2735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8221$2732_Y + connect \B $and$ls180.v:8221$2734_Y + connect \Y $or$ls180.v:8221$2735_Y + end + attribute \src "ls180.v:8221.38-8221.372" + cell $or $or$ls180.v:8221$2738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8221$2735_Y + connect \B $and$ls180.v:8221$2737_Y + connect \Y $or$ls180.v:8221$2738_Y + end + attribute \src "ls180.v:8225.7-8225.49" + cell $or $or$ls180.v:8225$2739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:8225$2739_Y + end + attribute \src "ls180.v:8388.21-8388.74" + cell $or $or$ls180.v:8388$2787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8388$2785_Y + connect \B $not$ls180.v:8388$2786_Y + connect \Y $or$ls180.v:8388$2787_Y + end + attribute \src "ls180.v:8423.21-8423.71" + cell $or $or$ls180.v:8423$2792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8423$2790_Y + connect \B $not$ls180.v:8423$2791_Y + connect \Y $or$ls180.v:8423$2792_Y + end + attribute \src "ls180.v:8491.32-8491.85" + cell $or $or$ls180.v:8491$2804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:8491$2804_Y + end + attribute \src "ls180.v:8497.8-8497.97" + cell $or $or$ls180.v:8497$2806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8497$2805_Y + connect \B \main_sdphy_cmdr_cmdr_converter_sink_last + connect \Y $or$ls180.v:8497$2806_Y + end + attribute \src "ls180.v:8514.52-8514.139" + cell $or $or$ls180.v:8514$2811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_first + connect \B \main_sdphy_cmdr_cmdr_converter_source_first + connect \Y $or$ls180.v:8514$2811_Y + end + attribute \src "ls180.v:8515.51-8515.136" + cell $or $or$ls180.v:8515$2812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_last + connect \B \main_sdphy_cmdr_cmdr_converter_source_last + connect \Y $or$ls180.v:8515$2812_Y + end + attribute \src "ls180.v:8549.7-8549.87" + cell $or $or$ls180.v:8549$2815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8549$2814_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:8549$2815_Y + end + attribute \src "ls180.v:8572.33-8572.88" + cell $or $or$ls180.v:8572$2816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_start + connect \B \main_sdphy_dataw_crcr_run + connect \Y $or$ls180.v:8572$2816_Y + end + attribute \src "ls180.v:8578.8-8578.99" + cell $or $or$ls180.v:8578$2818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8578$2817_Y + connect \B \main_sdphy_dataw_crcr_converter_sink_last + connect \Y $or$ls180.v:8578$2818_Y + end + attribute \src "ls180.v:8595.53-8595.142" + cell $or $or$ls180.v:8595$2823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_first + connect \B \main_sdphy_dataw_crcr_converter_source_first + connect \Y $or$ls180.v:8595$2823_Y + end + attribute \src "ls180.v:8596.52-8596.139" + cell $or $or$ls180.v:8596$2824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_last + connect \B \main_sdphy_dataw_crcr_converter_source_last + connect \Y $or$ls180.v:8596$2824_Y + end + attribute \src "ls180.v:8630.7-8630.89" + cell $or $or$ls180.v:8630$2827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8630$2826_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:8630$2827_Y + end + attribute \src "ls180.v:8651.34-8651.91" + cell $or $or$ls180.v:8651$2828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_start + connect \B \main_sdphy_datar_datar_run + connect \Y $or$ls180.v:8651$2828_Y + end + attribute \src "ls180.v:8657.8-8657.101" + cell $or $or$ls180.v:8657$2830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8657$2829_Y + connect \B \main_sdphy_datar_datar_converter_sink_last + connect \Y $or$ls180.v:8657$2830_Y + end + attribute \src "ls180.v:8674.54-8674.145" + cell $or $or$ls180.v:8674$2835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_first + connect \B \main_sdphy_datar_datar_converter_source_first + connect \Y $or$ls180.v:8674$2835_Y + end + attribute \src "ls180.v:8675.53-8675.142" + cell $or $or$ls180.v:8675$2836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_last + connect \B \main_sdphy_datar_datar_converter_source_last + connect \Y $or$ls180.v:8675$2836_Y + end + attribute \src "ls180.v:8691.7-8691.91" + cell $or $or$ls180.v:8691$2839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8691$2838_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:8691$2839_Y + end + attribute \src "ls180.v:8880.8-8880.89" + cell $or $or$ls180.v:8880$2863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8880$2862_Y + connect \B \main_sdblock2mem_converter_sink_last + connect \Y $or$ls180.v:8880$2863_Y + end + attribute \src "ls180.v:8897.48-8897.127" + cell $or $or$ls180.v:8897$2868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_first + connect \B \main_sdblock2mem_converter_source_first + connect \Y $or$ls180.v:8897$2868_Y + end + attribute \src "ls180.v:8898.47-8898.124" + cell $or $or$ls180.v:8898$2869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_last + connect \B \main_sdblock2mem_converter_source_last + connect \Y $or$ls180.v:8898$2869_Y + end + attribute \src "ls180.v:3355.46-3355.94" + cell $sshl $sshl$ls180.v:3355$231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3355$231_Y + end + attribute \src "ls180.v:3512.46-3512.94" + cell $sshl $sshl$ls180.v:3512$261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3512$261_Y + end + attribute \src "ls180.v:3669.46-3669.94" + cell $sshl $sshl$ls180.v:3669$291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3669$291_Y + end + attribute \src "ls180.v:3826.46-3826.94" + cell $sshl $sshl$ls180.v:3826$321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3826$321_Y + end + attribute \src "ls180.v:3386.63-3386.122" + cell $sub $sub$ls180.v:3386$244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3386$244_Y + end + attribute \src "ls180.v:3543.63-3543.122" + cell $sub $sub$ls180.v:3543$274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3543$274_Y + end + attribute \src "ls180.v:3700.63-3700.122" + cell $sub $sub$ls180.v:3700$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3700$304_Y + end + attribute \src "ls180.v:3857.63-3857.122" + cell $sub $sub$ls180.v:3857$334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3857$334_Y + end + attribute \src "ls180.v:4263.38-4263.75" + cell $sub $sub$ls180.v:4263$688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 30 + parameter \B_SIGNED 0 + parameter \B_WIDTH 31 + parameter \Y_WIDTH 31 + connect \A \main_litedram_wb_adr + connect \B 31'1001000000000000000000000000000 + connect \Y $sub$ls180.v:4263$688_Y + end + attribute \src "ls180.v:4349.36-4349.68" + cell $sub $sub$ls180.v:4349$733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4349$733_Y + end + attribute \src "ls180.v:4379.36-4379.68" + cell $sub $sub$ls180.v:4379$744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4379$744_Y + end + attribute \src "ls180.v:4415.70-4415.110" + cell $sub $sub$ls180.v:4415$752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4415$752_Y + end + attribute \src "ls180.v:4416.70-4416.104" + cell $sub $sub$ls180.v:4416$754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider + connect \B 1'1 + connect \Y $sub$ls180.v:4416$754_Y + end + attribute \src "ls180.v:4443.37-4443.66" + cell $sub $sub$ls180.v:4443$758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spimaster1_length + connect \B 1'1 + connect \Y $sub$ls180.v:4443$758_Y + end + attribute \src "ls180.v:4473.67-4473.107" + cell $sub $sub$ls180.v:4473$760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4473$760_Y + end + attribute \src "ls180.v:4474.67-4474.101" + cell $sub $sub$ls180.v:4474$762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:4474$762_Y + end + attribute \src "ls180.v:4502.35-4502.64" + cell $sub $sub$ls180.v:4502$766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spisdcard_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:4502$766_Y + end + attribute \src "ls180.v:4756.60-4756.90" + cell $sub $sub$ls180.v:4756$810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4756$810_Y + end + attribute \src "ls180.v:4767.62-4767.104" + cell $sub $sub$ls180.v:4767$812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_sink_payload_length + connect \B 1'1 + connect \Y $sub$ls180.v:4767$812_Y + end + attribute \src "ls180.v:4784.60-4784.90" + cell $sub $sub$ls180.v:4784$816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4784$816_Y + end + attribute \src "ls180.v:5013.62-5013.93" + cell $sub $sub$ls180.v:5013$846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:5013$846_Y + end + attribute \src "ls180.v:5018.62-5018.93" + cell $sub $sub$ls180.v:5018$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:5018$847_Y + end + attribute \src "ls180.v:5029.64-5029.122" + cell $sub $sub$ls180.v:5029$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A $add$ls180.v:5029$849_Y + connect \B 1'1 + connect \Y $sub$ls180.v:5029$850_Y + end + attribute \src "ls180.v:5050.62-5050.93" + cell $sub $sub$ls180.v:5050$853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:5050$853_Y + end + attribute \src "ls180.v:5512.37-5512.75" + cell $sub $sub$ls180.v:5512$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5512$1126_Y + end + attribute \src "ls180.v:5527.62-5527.100" + cell $sub $sub$ls180.v:5527$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5527$1129_Y + end + attribute \src "ls180.v:5538.39-5538.77" + cell $sub $sub$ls180.v:5538$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5538$1134_Y + end + attribute \src "ls180.v:5613.40-5613.76" + cell $sub $sub$ls180.v:5613$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5613$1138_Y + end + attribute \src "ls180.v:5662.56-5662.104" + cell $sub $sub$ls180.v:5662$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_length + connect \B 1'1 + connect \Y $sub$ls180.v:5662$1152_Y + end + attribute \src "ls180.v:5752.71-5752.105" + cell $sub $sub$ls180.v:5752$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_length + connect \B 1'1 + connect \Y $sub$ls180.v:5752$1158_Y + end + attribute \src "ls180.v:5833.40-5833.76" + cell $sub $sub$ls180.v:5833$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5833$1169_Y + end + attribute \src "ls180.v:7773.31-7773.60" + cell $sub $sub$ls180.v:7773$2607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_value + connect \B 1'1 + connect \Y $sub$ls180.v:7773$2607_Y + end + attribute \src "ls180.v:7810.31-7810.61" + cell $sub $sub$ls180.v:7810$2624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$ls180.v:7810$2624_Y + end + attribute \src "ls180.v:7816.34-7816.67" + cell $sub $sub$ls180.v:7816$2625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7816$2625_Y + end + attribute \src "ls180.v:7827.36-7827.69" + cell $sub $sub$ls180.v:7827$2628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7827$2628_Y + end + attribute \src "ls180.v:7891.59-7891.116" + cell $sub $sub$ls180.v:7891$2646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7891$2646_Y + end + attribute \src "ls180.v:7910.46-7910.90" + cell $sub $sub$ls180.v:7910$2650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7910$2650_Y + end + attribute \src "ls180.v:7937.59-7937.116" + cell $sub $sub$ls180.v:7937$2662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7937$2662_Y + end + attribute \src "ls180.v:7956.46-7956.90" + cell $sub $sub$ls180.v:7956$2666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7956$2666_Y + end + attribute \src "ls180.v:7983.59-7983.116" + cell $sub $sub$ls180.v:7983$2678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7983$2678_Y + end + attribute \src "ls180.v:8002.46-8002.90" + cell $sub $sub$ls180.v:8002$2682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:8002$2682_Y + end + attribute \src "ls180.v:8029.59-8029.116" + cell $sub $sub$ls180.v:8029$2694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:8029$2694_Y + end + attribute \src "ls180.v:8048.46-8048.90" + cell $sub $sub$ls180.v:8048$2698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:8048$2698_Y + end + attribute \src "ls180.v:8059.25-8059.48" + cell $sub $sub$ls180.v:8059$2702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdram_time0 + connect \B 1'1 + connect \Y $sub$ls180.v:8059$2702_Y + end + attribute \src "ls180.v:8066.25-8066.48" + cell $sub $sub$ls180.v:8066$2705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_time1 + connect \B 1'1 + connect \Y $sub$ls180.v:8066$2705_Y + end + attribute \src "ls180.v:8198.33-8198.64" + cell $sub $sub$ls180.v:8198$2710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:8198$2710_Y + end + attribute \src "ls180.v:8213.33-8213.64" + cell $sub $sub$ls180.v:8213$2713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:8213$2713_Y + end + attribute \src "ls180.v:8340.33-8340.64" + cell $sub $sub$ls180.v:8340$2772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8340$2772_Y + end + attribute \src "ls180.v:8362.33-8362.64" + cell $sub $sub$ls180.v:8362$2783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8362$2783_Y + end + attribute \src "ls180.v:8397.34-8397.66" + cell $sub $sub$ls180.v:8397$2788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spimaster34_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8397$2788_Y + end + attribute \src "ls180.v:8432.32-8432.62" + cell $sub $sub$ls180.v:8432$2793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8432$2793_Y + end + attribute \src "ls180.v:8456.30-8456.53" + cell $sub $sub$ls180.v:8456$2796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_period + connect \B 1'1 + connect \Y $sub$ls180.v:8456$2796_Y + end + attribute \src "ls180.v:8470.30-8470.53" + cell $sub $sub$ls180.v:8470$2800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_period + connect \B 1'1 + connect \Y $sub$ls180.v:8470$2800_Y + end + attribute \src "ls180.v:8873.36-8873.70" + cell $sub $sub$ls180.v:8873$2861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8873$2861_Y + end + attribute \src "ls180.v:8971.36-8971.70" + cell $sub $sub$ls180.v:8971$2883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8971$2883_Y + end + attribute \src "ls180.v:9084.22-9084.42" + cell $sub $sub$ls180.v:9084$2890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 20 + connect \A \builder_count + connect \B 1'1 + connect \Y $sub$ls180.v:9084$2890_Y + end + attribute \src "ls180.v:5110.353-5110.425" + cell $xor $xor$ls180.v:5110$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:5110$860_Y + end + attribute \src "ls180.v:5110.200-5110.272" + cell $xor $xor$ls180.v:5110$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:5110$861_Y + end + attribute \src "ls180.v:5110.160-5110.273" + cell $xor $xor$ls180.v:5110$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg0 [2] + connect \B $xor$ls180.v:5110$861_Y + connect \Y $xor$ls180.v:5110$862_Y + end + attribute \src "ls180.v:5111.353-5111.425" + cell $xor $xor$ls180.v:5111$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:5111$863_Y + end + attribute \src "ls180.v:5111.200-5111.272" + cell $xor $xor$ls180.v:5111$864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:5111$864_Y + end + attribute \src "ls180.v:5111.160-5111.273" + cell $xor $xor$ls180.v:5111$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg1 [2] + connect \B $xor$ls180.v:5111$864_Y + connect \Y $xor$ls180.v:5111$865_Y + end + attribute \src "ls180.v:5112.353-5112.425" + cell $xor $xor$ls180.v:5112$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:5112$866_Y + end + attribute \src "ls180.v:5112.200-5112.272" + cell $xor $xor$ls180.v:5112$867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:5112$867_Y + end + attribute \src "ls180.v:5112.160-5112.273" + cell $xor $xor$ls180.v:5112$868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg2 [2] + connect \B $xor$ls180.v:5112$867_Y + connect \Y $xor$ls180.v:5112$868_Y + end + attribute \src "ls180.v:5113.353-5113.425" + cell $xor $xor$ls180.v:5113$869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:5113$869_Y + end + attribute \src "ls180.v:5113.200-5113.272" + cell $xor $xor$ls180.v:5113$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:5113$870_Y + end + attribute \src "ls180.v:5113.160-5113.273" + cell $xor $xor$ls180.v:5113$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg3 [2] + connect \B $xor$ls180.v:5113$870_Y + connect \Y $xor$ls180.v:5113$871_Y + end + attribute \src "ls180.v:5114.353-5114.425" + cell $xor $xor$ls180.v:5114$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:5114$872_Y + end + attribute \src "ls180.v:5114.200-5114.272" + cell $xor $xor$ls180.v:5114$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:5114$873_Y + end + attribute \src "ls180.v:5114.160-5114.273" + cell $xor $xor$ls180.v:5114$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg4 [2] + connect \B $xor$ls180.v:5114$873_Y + connect \Y $xor$ls180.v:5114$874_Y + end + attribute \src "ls180.v:5115.353-5115.425" + cell $xor $xor$ls180.v:5115$875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:5115$875_Y + end + attribute \src "ls180.v:5115.200-5115.272" + cell $xor $xor$ls180.v:5115$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:5115$876_Y + end + attribute \src "ls180.v:5115.160-5115.273" + cell $xor $xor$ls180.v:5115$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg5 [2] + connect \B $xor$ls180.v:5115$876_Y + connect \Y $xor$ls180.v:5115$877_Y + end + attribute \src "ls180.v:5116.353-5116.425" + cell $xor $xor$ls180.v:5116$878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:5116$878_Y + end + attribute \src "ls180.v:5116.200-5116.272" + cell $xor $xor$ls180.v:5116$879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:5116$879_Y + end + attribute \src "ls180.v:5116.160-5116.273" + cell $xor $xor$ls180.v:5116$880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg6 [2] + connect \B $xor$ls180.v:5116$879_Y + connect \Y $xor$ls180.v:5116$880_Y + end + attribute \src "ls180.v:5117.353-5117.425" + cell $xor $xor$ls180.v:5117$881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:5117$881_Y + end + attribute \src "ls180.v:5117.200-5117.272" + cell $xor $xor$ls180.v:5117$882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:5117$882_Y + end + attribute \src "ls180.v:5117.160-5117.273" + cell $xor $xor$ls180.v:5117$883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg7 [2] + connect \B $xor$ls180.v:5117$882_Y + connect \Y $xor$ls180.v:5117$883_Y + end + attribute \src "ls180.v:5118.353-5118.425" + cell $xor $xor$ls180.v:5118$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:5118$884_Y + end + attribute \src "ls180.v:5118.200-5118.272" + cell $xor $xor$ls180.v:5118$885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:5118$885_Y + end + attribute \src "ls180.v:5118.160-5118.273" + cell $xor $xor$ls180.v:5118$886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg8 [2] + connect \B $xor$ls180.v:5118$885_Y + connect \Y $xor$ls180.v:5118$886_Y + end + attribute \src "ls180.v:5119.354-5119.426" + cell $xor $xor$ls180.v:5119$887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:5119$887_Y + end + attribute \src "ls180.v:5119.201-5119.273" + cell $xor $xor$ls180.v:5119$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:5119$888_Y + end + attribute \src "ls180.v:5119.161-5119.274" + cell $xor $xor$ls180.v:5119$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg9 [2] + connect \B $xor$ls180.v:5119$888_Y + connect \Y $xor$ls180.v:5119$889_Y + end + attribute \src "ls180.v:5120.361-5120.434" + cell $xor $xor$ls180.v:5120$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:5120$890_Y + end + attribute \src "ls180.v:5120.205-5120.278" + cell $xor $xor$ls180.v:5120$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:5120$891_Y + end + attribute \src "ls180.v:5120.164-5120.279" + cell $xor $xor$ls180.v:5120$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg10 [2] + connect \B $xor$ls180.v:5120$891_Y + connect \Y $xor$ls180.v:5120$892_Y + end + attribute \src "ls180.v:5121.361-5121.434" + cell $xor $xor$ls180.v:5121$893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:5121$893_Y + end + attribute \src "ls180.v:5121.205-5121.278" + cell $xor $xor$ls180.v:5121$894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:5121$894_Y + end + attribute \src "ls180.v:5121.164-5121.279" + cell $xor $xor$ls180.v:5121$895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg11 [2] + connect \B $xor$ls180.v:5121$894_Y + connect \Y $xor$ls180.v:5121$895_Y + end + attribute \src "ls180.v:5122.361-5122.434" + cell $xor $xor$ls180.v:5122$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:5122$896_Y + end + attribute \src "ls180.v:5122.205-5122.278" + cell $xor $xor$ls180.v:5122$897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:5122$897_Y + end + attribute \src "ls180.v:5122.164-5122.279" + cell $xor $xor$ls180.v:5122$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg12 [2] + connect \B $xor$ls180.v:5122$897_Y + connect \Y $xor$ls180.v:5122$898_Y + end + attribute \src "ls180.v:5123.361-5123.434" + cell $xor $xor$ls180.v:5123$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:5123$899_Y + end + attribute \src "ls180.v:5123.205-5123.278" + cell $xor $xor$ls180.v:5123$900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:5123$900_Y + end + attribute \src "ls180.v:5123.164-5123.279" + cell $xor $xor$ls180.v:5123$901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg13 [2] + connect \B $xor$ls180.v:5123$900_Y + connect \Y $xor$ls180.v:5123$901_Y + end + attribute \src "ls180.v:5124.361-5124.434" + cell $xor $xor$ls180.v:5124$902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:5124$902_Y + end + attribute \src "ls180.v:5124.205-5124.278" + cell $xor $xor$ls180.v:5124$903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:5124$903_Y + end + attribute \src "ls180.v:5124.164-5124.279" + cell $xor $xor$ls180.v:5124$904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg14 [2] + connect \B $xor$ls180.v:5124$903_Y + connect \Y $xor$ls180.v:5124$904_Y + end + attribute \src "ls180.v:5125.361-5125.434" + cell $xor $xor$ls180.v:5125$905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:5125$905_Y + end + attribute \src "ls180.v:5125.205-5125.278" + cell $xor $xor$ls180.v:5125$906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:5125$906_Y + end + attribute \src "ls180.v:5125.164-5125.279" + cell $xor $xor$ls180.v:5125$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg15 [2] + connect \B $xor$ls180.v:5125$906_Y + connect \Y $xor$ls180.v:5125$907_Y + end + attribute \src "ls180.v:5126.361-5126.434" + cell $xor $xor$ls180.v:5126$908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:5126$908_Y + end + attribute \src "ls180.v:5126.205-5126.278" + cell $xor $xor$ls180.v:5126$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:5126$909_Y + end + attribute \src "ls180.v:5126.164-5126.279" + cell $xor $xor$ls180.v:5126$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg16 [2] + connect \B $xor$ls180.v:5126$909_Y + connect \Y $xor$ls180.v:5126$910_Y + end + attribute \src "ls180.v:5127.361-5127.434" + cell $xor $xor$ls180.v:5127$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:5127$911_Y + end + attribute \src "ls180.v:5127.205-5127.278" + cell $xor $xor$ls180.v:5127$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:5127$912_Y + end + attribute \src "ls180.v:5127.164-5127.279" + cell $xor $xor$ls180.v:5127$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg17 [2] + connect \B $xor$ls180.v:5127$912_Y + connect \Y $xor$ls180.v:5127$913_Y + end + attribute \src "ls180.v:5128.361-5128.434" + cell $xor $xor$ls180.v:5128$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:5128$914_Y + end + attribute \src "ls180.v:5128.205-5128.278" + cell $xor $xor$ls180.v:5128$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:5128$915_Y + end + attribute \src "ls180.v:5128.164-5128.279" + cell $xor $xor$ls180.v:5128$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg18 [2] + connect \B $xor$ls180.v:5128$915_Y + connect \Y $xor$ls180.v:5128$916_Y + end + attribute \src "ls180.v:5129.361-5129.434" + cell $xor $xor$ls180.v:5129$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:5129$917_Y + end + attribute \src "ls180.v:5129.205-5129.278" + cell $xor $xor$ls180.v:5129$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:5129$918_Y + end + attribute \src "ls180.v:5129.164-5129.279" + cell $xor $xor$ls180.v:5129$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg19 [2] + connect \B $xor$ls180.v:5129$918_Y + connect \Y $xor$ls180.v:5129$919_Y + end + attribute \src "ls180.v:5130.361-5130.434" + cell $xor $xor$ls180.v:5130$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:5130$920_Y + end + attribute \src "ls180.v:5130.205-5130.278" + cell $xor $xor$ls180.v:5130$921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:5130$921_Y + end + attribute \src "ls180.v:5130.164-5130.279" + cell $xor $xor$ls180.v:5130$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg20 [2] + connect \B $xor$ls180.v:5130$921_Y + connect \Y $xor$ls180.v:5130$922_Y + end + attribute \src "ls180.v:5131.361-5131.434" + cell $xor $xor$ls180.v:5131$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:5131$923_Y + end + attribute \src "ls180.v:5131.205-5131.278" + cell $xor $xor$ls180.v:5131$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:5131$924_Y + end + attribute \src "ls180.v:5131.164-5131.279" + cell $xor $xor$ls180.v:5131$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg21 [2] + connect \B $xor$ls180.v:5131$924_Y + connect \Y $xor$ls180.v:5131$925_Y + end + attribute \src "ls180.v:5132.361-5132.434" + cell $xor $xor$ls180.v:5132$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:5132$926_Y + end + attribute \src "ls180.v:5132.205-5132.278" + cell $xor $xor$ls180.v:5132$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:5132$927_Y + end + attribute \src "ls180.v:5132.164-5132.279" + cell $xor $xor$ls180.v:5132$928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg22 [2] + connect \B $xor$ls180.v:5132$927_Y + connect \Y $xor$ls180.v:5132$928_Y + end + attribute \src "ls180.v:5133.361-5133.434" + cell $xor $xor$ls180.v:5133$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:5133$929_Y + end + attribute \src "ls180.v:5133.205-5133.278" + cell $xor $xor$ls180.v:5133$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:5133$930_Y + end + attribute \src "ls180.v:5133.164-5133.279" + cell $xor $xor$ls180.v:5133$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg23 [2] + connect \B $xor$ls180.v:5133$930_Y + connect \Y $xor$ls180.v:5133$931_Y + end + attribute \src "ls180.v:5134.361-5134.434" + cell $xor $xor$ls180.v:5134$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:5134$932_Y + end + attribute \src "ls180.v:5134.205-5134.278" + cell $xor $xor$ls180.v:5134$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:5134$933_Y + end + attribute \src "ls180.v:5134.164-5134.279" + cell $xor $xor$ls180.v:5134$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg24 [2] + connect \B $xor$ls180.v:5134$933_Y + connect \Y $xor$ls180.v:5134$934_Y + end + attribute \src "ls180.v:5135.361-5135.434" + cell $xor $xor$ls180.v:5135$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:5135$935_Y + end + attribute \src "ls180.v:5135.205-5135.278" + cell $xor $xor$ls180.v:5135$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:5135$936_Y + end + attribute \src "ls180.v:5135.164-5135.279" + cell $xor $xor$ls180.v:5135$937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg25 [2] + connect \B $xor$ls180.v:5135$936_Y + connect \Y $xor$ls180.v:5135$937_Y + end + attribute \src "ls180.v:5136.361-5136.434" + cell $xor $xor$ls180.v:5136$938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:5136$938_Y + end + attribute \src "ls180.v:5136.205-5136.278" + cell $xor $xor$ls180.v:5136$939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:5136$939_Y + end + attribute \src "ls180.v:5136.164-5136.279" + cell $xor $xor$ls180.v:5136$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg26 [2] + connect \B $xor$ls180.v:5136$939_Y + connect \Y $xor$ls180.v:5136$940_Y + end + attribute \src "ls180.v:5137.361-5137.434" + cell $xor $xor$ls180.v:5137$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:5137$941_Y + end + attribute \src "ls180.v:5137.205-5137.278" + cell $xor $xor$ls180.v:5137$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:5137$942_Y + end + attribute \src "ls180.v:5137.164-5137.279" + cell $xor $xor$ls180.v:5137$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg27 [2] + connect \B $xor$ls180.v:5137$942_Y + connect \Y $xor$ls180.v:5137$943_Y + end + attribute \src "ls180.v:5138.361-5138.434" + cell $xor $xor$ls180.v:5138$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:5138$944_Y + end + attribute \src "ls180.v:5138.205-5138.278" + cell $xor $xor$ls180.v:5138$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:5138$945_Y + end + attribute \src "ls180.v:5138.164-5138.279" + cell $xor $xor$ls180.v:5138$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg28 [2] + connect \B $xor$ls180.v:5138$945_Y + connect \Y $xor$ls180.v:5138$946_Y + end + attribute \src "ls180.v:5139.361-5139.434" + cell $xor $xor$ls180.v:5139$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:5139$947_Y + end + attribute \src "ls180.v:5139.205-5139.278" + cell $xor $xor$ls180.v:5139$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:5139$948_Y + end + attribute \src "ls180.v:5139.164-5139.279" + cell $xor $xor$ls180.v:5139$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg29 [2] + connect \B $xor$ls180.v:5139$948_Y + connect \Y $xor$ls180.v:5139$949_Y + end + attribute \src "ls180.v:5140.360-5140.432" + cell $xor $xor$ls180.v:5140$950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:5140$950_Y + end + attribute \src "ls180.v:5140.205-5140.277" + cell $xor $xor$ls180.v:5140$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:5140$951_Y + end + attribute \src "ls180.v:5140.164-5140.278" + cell $xor $xor$ls180.v:5140$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg30 [2] + connect \B $xor$ls180.v:5140$951_Y + connect \Y $xor$ls180.v:5140$952_Y + end + attribute \src "ls180.v:5141.360-5141.432" + cell $xor $xor$ls180.v:5141$953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:5141$953_Y + end + attribute \src "ls180.v:5141.205-5141.277" + cell $xor $xor$ls180.v:5141$954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:5141$954_Y + end + attribute \src "ls180.v:5141.164-5141.278" + cell $xor $xor$ls180.v:5141$955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg31 [2] + connect \B $xor$ls180.v:5141$954_Y + connect \Y $xor$ls180.v:5141$955_Y + end + attribute \src "ls180.v:5142.360-5142.432" + cell $xor $xor$ls180.v:5142$956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:5142$956_Y + end + attribute \src "ls180.v:5142.205-5142.277" + cell $xor $xor$ls180.v:5142$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:5142$957_Y + end + attribute \src "ls180.v:5142.164-5142.278" + cell $xor $xor$ls180.v:5142$958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg32 [2] + connect \B $xor$ls180.v:5142$957_Y + connect \Y $xor$ls180.v:5142$958_Y + end + attribute \src "ls180.v:5143.360-5143.432" + cell $xor $xor$ls180.v:5143$959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:5143$959_Y + end + attribute \src "ls180.v:5143.205-5143.277" + cell $xor $xor$ls180.v:5143$960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:5143$960_Y + end + attribute \src "ls180.v:5143.164-5143.278" + cell $xor $xor$ls180.v:5143$961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg33 [2] + connect \B $xor$ls180.v:5143$960_Y + connect \Y $xor$ls180.v:5143$961_Y + end + attribute \src "ls180.v:5144.360-5144.432" + cell $xor $xor$ls180.v:5144$962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:5144$962_Y + end + attribute \src "ls180.v:5144.205-5144.277" + cell $xor $xor$ls180.v:5144$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:5144$963_Y + end + attribute \src "ls180.v:5144.164-5144.278" + cell $xor $xor$ls180.v:5144$964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg34 [2] + connect \B $xor$ls180.v:5144$963_Y + connect \Y $xor$ls180.v:5144$964_Y + end + attribute \src "ls180.v:5145.360-5145.432" + cell $xor $xor$ls180.v:5145$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:5145$965_Y + end + attribute \src "ls180.v:5145.205-5145.277" + cell $xor $xor$ls180.v:5145$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:5145$966_Y + end + attribute \src "ls180.v:5145.164-5145.278" + cell $xor $xor$ls180.v:5145$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg35 [2] + connect \B $xor$ls180.v:5145$966_Y + connect \Y $xor$ls180.v:5145$967_Y + end + attribute \src "ls180.v:5146.360-5146.432" + cell $xor $xor$ls180.v:5146$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:5146$968_Y + end + attribute \src "ls180.v:5146.205-5146.277" + cell $xor $xor$ls180.v:5146$969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:5146$969_Y + end + attribute \src "ls180.v:5146.164-5146.278" + cell $xor $xor$ls180.v:5146$970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg36 [2] + connect \B $xor$ls180.v:5146$969_Y + connect \Y $xor$ls180.v:5146$970_Y + end + attribute \src "ls180.v:5147.360-5147.432" + cell $xor $xor$ls180.v:5147$971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:5147$971_Y + end + attribute \src "ls180.v:5147.205-5147.277" + cell $xor $xor$ls180.v:5147$972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:5147$972_Y + end + attribute \src "ls180.v:5147.164-5147.278" + cell $xor $xor$ls180.v:5147$973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg37 [2] + connect \B $xor$ls180.v:5147$972_Y + connect \Y $xor$ls180.v:5147$973_Y + end + attribute \src "ls180.v:5148.360-5148.432" + cell $xor $xor$ls180.v:5148$974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:5148$974_Y + end + attribute \src "ls180.v:5148.205-5148.277" + cell $xor $xor$ls180.v:5148$975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:5148$975_Y + end + attribute \src "ls180.v:5148.164-5148.278" + cell $xor $xor$ls180.v:5148$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg38 [2] + connect \B $xor$ls180.v:5148$975_Y + connect \Y $xor$ls180.v:5148$976_Y + end + attribute \src "ls180.v:5149.360-5149.432" + cell $xor $xor$ls180.v:5149$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:5149$977_Y + end + attribute \src "ls180.v:5149.205-5149.277" + cell $xor $xor$ls180.v:5149$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:5149$978_Y + end + attribute \src "ls180.v:5149.164-5149.278" + cell $xor $xor$ls180.v:5149$979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg39 [2] + connect \B $xor$ls180.v:5149$978_Y + connect \Y $xor$ls180.v:5149$979_Y + end + attribute \src "ls180.v:5170.899-5170.983" + cell $xor $xor$ls180.v:5170$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5170$993_Y + end + attribute \src "ls180.v:5170.634-5170.718" + cell $xor $xor$ls180.v:5170$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5170$994_Y + end + attribute \src "ls180.v:5170.588-5170.719" + cell $xor $xor$ls180.v:5170$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5170$994_Y + connect \Y $xor$ls180.v:5170$995_Y + end + attribute \src "ls180.v:5170.234-5170.318" + cell $xor $xor$ls180.v:5170$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5170$996_Y + end + attribute \src "ls180.v:5170.187-5170.319" + cell $xor $xor$ls180.v:5170$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5170$996_Y + connect \Y $xor$ls180.v:5170$997_Y + end + attribute \src "ls180.v:5171.588-5171.719" + cell $xor $xor$ls180.v:5171$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5171$999_Y + connect \Y $xor$ls180.v:5171$1000_Y + end + attribute \src "ls180.v:5171.234-5171.318" + cell $xor $xor$ls180.v:5171$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5171$1001_Y + end + attribute \src "ls180.v:5171.187-5171.319" + cell $xor $xor$ls180.v:5171$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5171$1001_Y + connect \Y $xor$ls180.v:5171$1002_Y + end + attribute \src "ls180.v:5171.899-5171.983" + cell $xor $xor$ls180.v:5171$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5171$998_Y + end + attribute \src "ls180.v:5171.634-5171.718" + cell $xor $xor$ls180.v:5171$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5171$999_Y + end + attribute \src "ls180.v:5180.899-5180.983" + cell $xor $xor$ls180.v:5180$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5180$1004_Y + end + attribute \src "ls180.v:5180.634-5180.718" + cell $xor $xor$ls180.v:5180$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5180$1005_Y + end + attribute \src "ls180.v:5180.588-5180.719" + cell $xor $xor$ls180.v:5180$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5180$1005_Y + connect \Y $xor$ls180.v:5180$1006_Y + end + attribute \src "ls180.v:5180.234-5180.318" + cell $xor $xor$ls180.v:5180$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5180$1007_Y + end + attribute \src "ls180.v:5180.187-5180.319" + cell $xor $xor$ls180.v:5180$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5180$1007_Y + connect \Y $xor$ls180.v:5180$1008_Y + end + attribute \src "ls180.v:5181.899-5181.983" + cell $xor $xor$ls180.v:5181$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5181$1009_Y + end + attribute \src "ls180.v:5181.634-5181.718" + cell $xor $xor$ls180.v:5181$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5181$1010_Y + end + attribute \src "ls180.v:5181.588-5181.719" + cell $xor $xor$ls180.v:5181$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5181$1010_Y + connect \Y $xor$ls180.v:5181$1011_Y + end + attribute \src "ls180.v:5181.234-5181.318" + cell $xor $xor$ls180.v:5181$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5181$1012_Y + end + attribute \src "ls180.v:5181.187-5181.319" + cell $xor $xor$ls180.v:5181$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5181$1012_Y + connect \Y $xor$ls180.v:5181$1013_Y + end + attribute \src "ls180.v:5190.899-5190.983" + cell $xor $xor$ls180.v:5190$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:149363$7135_Y + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5190$1015_Y + end + attribute \src "ls180.v:5190.634-5190.718" + cell $xor $xor$ls180.v:5190$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5190$1016_Y + end + attribute \src "ls180.v:5190.588-5190.719" + cell $xor $xor$ls180.v:5190$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5190$1016_Y + connect \Y $xor$ls180.v:5190$1017_Y + end + attribute \src "ls180.v:5190.234-5190.318" + cell $xor $xor$ls180.v:5190$1018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5190$1018_Y + end + attribute \src "ls180.v:5190.187-5190.319" + cell $xor $xor$ls180.v:5190$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5190$1018_Y + connect \Y $xor$ls180.v:5190$1019_Y + end + attribute \src "ls180.v:5191.899-5191.983" + cell $xor $xor$ls180.v:5191$1020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5191$1020_Y + end + attribute \src "ls180.v:5191.634-5191.718" + cell $xor $xor$ls180.v:5191$1021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5191$1021_Y + end + attribute \src "ls180.v:5191.588-5191.719" + cell $xor $xor$ls180.v:5191$1022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5191$1021_Y + connect \Y $xor$ls180.v:5191$1022_Y + end + attribute \src "ls180.v:5191.234-5191.318" + cell $xor $xor$ls180.v:5191$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5191$1023_Y + end + attribute \src "ls180.v:5191.187-5191.319" + cell $xor $xor$ls180.v:5191$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5191$1023_Y + connect \Y $xor$ls180.v:5191$1024_Y + end + attribute \src "ls180.v:5200.899-5200.983" + cell $xor $xor$ls180.v:5200$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5200$1026_Y + end + attribute \src "ls180.v:5200.634-5200.718" + cell $xor $xor$ls180.v:5200$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5200$1027_Y + end + attribute \src "ls180.v:5200.588-5200.719" + cell $xor $xor$ls180.v:5200$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5200$1027_Y + connect \Y $xor$ls180.v:5200$1028_Y + end + attribute \src "ls180.v:5200.234-5200.318" + cell $xor $xor$ls180.v:5200$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5200$1029_Y + end + attribute \src "ls180.v:5200.187-5200.319" + cell $xor $xor$ls180.v:5200$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5200$1029_Y + connect \Y $xor$ls180.v:5200$1030_Y + end + attribute \src "ls180.v:5201.899-5201.983" + cell $xor $xor$ls180.v:5201$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5201$1031_Y + end + attribute \src "ls180.v:5201.634-5201.718" + cell $xor $xor$ls180.v:5201$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5201$1032_Y + end + attribute \src "ls180.v:5201.588-5201.719" + cell $xor $xor$ls180.v:5201$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5201$1032_Y + connect \Y $xor$ls180.v:5201$1033_Y + end + attribute \src "ls180.v:5201.234-5201.318" + cell $xor $xor$ls180.v:5201$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5201$1034_Y + end + attribute \src "ls180.v:5201.187-5201.319" + cell $xor $xor$ls180.v:5201$1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5201$1034_Y + connect \Y $xor$ls180.v:5201$1035_Y + end + attribute \src "ls180.v:5352.879-5352.961" + cell $xor $xor$ls180.v:5352$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5352$1068_Y + end + attribute \src "ls180.v:5352.620-5352.702" + cell $xor $xor$ls180.v:5352$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5352$1069_Y + end + attribute \src "ls180.v:5352.575-5352.703" + cell $xor $xor$ls180.v:5352$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5352$1069_Y + connect \Y $xor$ls180.v:5352$1070_Y + end + attribute \src "ls180.v:5352.229-5352.311" + cell $xor $xor$ls180.v:5352$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5352$1071_Y + end + attribute \src "ls180.v:5352.183-5352.312" + cell $xor $xor$ls180.v:5352$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5352$1071_Y + connect \Y $xor$ls180.v:5352$1072_Y + end + attribute \src "ls180.v:5353.879-5353.961" + cell $xor $xor$ls180.v:5353$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5353$1073_Y + end + attribute \src "ls180.v:5353.620-5353.702" + cell $xor $xor$ls180.v:5353$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5353$1074_Y + end + attribute \src "ls180.v:5353.575-5353.703" + cell $xor $xor$ls180.v:5353$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5353$1074_Y + connect \Y $xor$ls180.v:5353$1075_Y + end + attribute \src "ls180.v:5353.229-5353.311" + cell $xor $xor$ls180.v:5353$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5353$1076_Y + end + attribute \src "ls180.v:5353.183-5353.312" + cell $xor $xor$ls180.v:5353$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5353$1076_Y + connect \Y $xor$ls180.v:5353$1077_Y + end + attribute \src "ls180.v:5362.879-5362.961" + cell $xor $xor$ls180.v:5362$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5362$1079_Y + end + attribute \src "ls180.v:5362.620-5362.702" + cell $xor $xor$ls180.v:5362$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5362$1080_Y + end + attribute \src "ls180.v:5362.575-5362.703" + cell $xor $xor$ls180.v:5362$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5362$1080_Y + connect \Y $xor$ls180.v:5362$1081_Y + end + attribute \src "ls180.v:5362.229-5362.311" + cell $xor $xor$ls180.v:5362$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5362$1082_Y + end + attribute \src "ls180.v:5362.183-5362.312" + cell $xor $xor$ls180.v:5362$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5362$1082_Y + connect \Y $xor$ls180.v:5362$1083_Y + end + attribute \src "ls180.v:5363.879-5363.961" + cell $xor $xor$ls180.v:5363$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5363$1084_Y + end + attribute \src "ls180.v:5363.620-5363.702" + cell $xor $xor$ls180.v:5363$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5363$1085_Y + end + attribute \src "ls180.v:5363.575-5363.703" + cell $xor $xor$ls180.v:5363$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5363$1085_Y + connect \Y $xor$ls180.v:5363$1086_Y + end + attribute \src "ls180.v:5363.229-5363.311" + cell $xor $xor$ls180.v:5363$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5363$1087_Y + end + attribute \src "ls180.v:5363.183-5363.312" + cell $xor $xor$ls180.v:5363$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5363$1087_Y + connect \Y $xor$ls180.v:5363$1088_Y + end + attribute \src "ls180.v:5372.879-5372.961" + cell $xor $xor$ls180.v:5372$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5372$1090_Y + end + attribute \src "ls180.v:5372.620-5372.702" + cell $xor $xor$ls180.v:5372$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5372$1091_Y + end + attribute \src "ls180.v:5372.575-5372.703" + cell $xor $xor$ls180.v:5372$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5372$1091_Y + connect \Y $xor$ls180.v:5372$1092_Y + end + attribute \src "ls180.v:5372.229-5372.311" + cell $xor $xor$ls180.v:5372$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5372$1093_Y + end + attribute \src "ls180.v:5372.183-5372.312" + cell $xor $xor$ls180.v:5372$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5372$1093_Y + connect \Y $xor$ls180.v:5372$1094_Y + end + attribute \src "ls180.v:5373.879-5373.961" + cell $xor $xor$ls180.v:5373$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5373$1095_Y + end + attribute \src "ls180.v:5373.620-5373.702" + cell $xor $xor$ls180.v:5373$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5373$1096_Y + end + attribute \src "ls180.v:5373.575-5373.703" + cell $xor $xor$ls180.v:5373$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5373$1096_Y + connect \Y $xor$ls180.v:5373$1097_Y + end + attribute \src "ls180.v:5373.229-5373.311" + cell $xor $xor$ls180.v:5373$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5373$1098_Y + end + attribute \src "ls180.v:5373.183-5373.312" + cell $xor $xor$ls180.v:5373$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5373$1098_Y + connect \Y $xor$ls180.v:5373$1099_Y + end + attribute \src "ls180.v:5382.879-5382.961" + cell $xor $xor$ls180.v:5382$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5382$1101_Y + end + attribute \src "ls180.v:5382.620-5382.702" + cell $xor $xor$ls180.v:5382$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5382$1102_Y + end + attribute \src "ls180.v:5382.575-5382.703" + cell $xor $xor$ls180.v:5382$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5382$1102_Y + connect \Y $xor$ls180.v:5382$1103_Y + end + attribute \src "ls180.v:5382.229-5382.311" + cell $xor $xor$ls180.v:5382$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5382$1104_Y + end + attribute \src "ls180.v:5382.183-5382.312" + cell $xor $xor$ls180.v:5382$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5382$1104_Y + connect \Y $xor$ls180.v:5382$1105_Y + end + attribute \src "ls180.v:5383.879-5383.961" + cell $xor $xor$ls180.v:5383$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5383$1106_Y + end + attribute \src "ls180.v:5383.620-5383.702" + cell $xor $xor$ls180.v:5383$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5383$1107_Y + end + attribute \src "ls180.v:5383.575-5383.703" + cell $xor $xor$ls180.v:5383$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5383$1107_Y + connect \Y $xor$ls180.v:5383$1108_Y + end + attribute \src "ls180.v:5383.229-5383.311" + cell $xor $xor$ls180.v:5383$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5383$1109_Y + end + attribute \src "ls180.v:5383.183-5383.312" + cell $xor $xor$ls180.v:5383$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5383$1109_Y + connect \Y $xor$ls180.v:5383$1110_Y + end + attribute \module_not_derived 1 + attribute \src "ls180.v:10606.13-11024.2" + cell \test_issuer \test_issuer + connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck + connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi + connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo + connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms + connect \busy_o \main_libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \clk_sel_i \main_libresocsim_libresoc_clk_sel + connect \core_bigendian_i 1'0 + connect \dbus__ack \main_libresocsim_libresoc_dbus_ack + connect \dbus__adr \main_libresocsim_libresoc_dbus_adr + connect \dbus__bte 1'0 + connect \dbus__cti 1'0 + connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w + connect \dbus__err \main_libresocsim_libresoc_dbus_err + connect \dbus__sel \main_libresocsim_libresoc_dbus_sel + connect \dbus__stb \main_libresocsim_libresoc_dbus_stb + connect \dbus__we \main_libresocsim_libresoc_dbus_we + connect \eint_0__core__i \eint [0] + connect \eint_0__pad__i \eint_1 [0] + connect \eint_1__core__i \eint [1] + connect \eint_1__pad__i \eint_1 [1] + connect \eint_2__core__i \eint [2] + connect \eint_2__pad__i \eint_1 [2] + connect \gpio_e10__core__i \gpio_i [10] + connect \gpio_e10__core__o \gpio_o [10] + connect \gpio_e10__core__oe \gpio_oe [10] + connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10] + connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10] + connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] + connect \gpio_e11__core__i \gpio_i [11] + connect \gpio_e11__core__o \gpio_o [11] + connect \gpio_e11__core__oe \gpio_oe [11] + connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11] + connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11] + connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] + connect \gpio_e12__core__i \gpio_i [12] + connect \gpio_e12__core__o \gpio_o [12] + connect \gpio_e12__core__oe \gpio_oe [12] + connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12] + connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12] + connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] + connect \gpio_e13__core__i \gpio_i [13] + connect \gpio_e13__core__o \gpio_o [13] + connect \gpio_e13__core__oe \gpio_oe [13] + connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13] + connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13] + connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] + connect \gpio_e14__core__i \gpio_i [14] + connect \gpio_e14__core__o \gpio_o [14] + connect \gpio_e14__core__oe \gpio_oe [14] + connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14] + connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14] + connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] + connect \gpio_e15__core__i \gpio_i [15] + connect \gpio_e15__core__o \gpio_o [15] + connect \gpio_e15__core__oe \gpio_oe [15] + connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15] + connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15] + connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] + connect \gpio_e8__core__i \gpio_i [8] + connect \gpio_e8__core__o \gpio_o [8] + connect \gpio_e8__core__oe \gpio_oe [8] + connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8] + connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8] + connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] + connect \gpio_e9__core__i \gpio_i [9] + connect \gpio_e9__core__o \gpio_o [9] + connect \gpio_e9__core__oe \gpio_oe [9] + connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9] + connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9] + connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] + connect \gpio_s0__core__i \gpio_i [0] + connect \gpio_s0__core__o \gpio_o [0] + connect \gpio_s0__core__oe \gpio_oe [0] + connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0] + connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0] + connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] + connect \gpio_s1__core__i \gpio_i [1] + connect \gpio_s1__core__o \gpio_o [1] + connect \gpio_s1__core__oe \gpio_oe [1] + connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1] + connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1] + connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] + connect \gpio_s2__core__i \gpio_i [2] + connect \gpio_s2__core__o \gpio_o [2] + connect \gpio_s2__core__oe \gpio_oe [2] + connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2] + connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2] + connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] + connect \gpio_s3__core__i \gpio_i [3] + connect \gpio_s3__core__o \gpio_o [3] + connect \gpio_s3__core__oe \gpio_oe [3] + connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3] + connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3] + connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] + connect \gpio_s4__core__i \gpio_i [4] + connect \gpio_s4__core__o \gpio_o [4] + connect \gpio_s4__core__oe \gpio_oe [4] + connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4] + connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4] + connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] + connect \gpio_s5__core__i \gpio_i [5] + connect \gpio_s5__core__o \gpio_o [5] + connect \gpio_s5__core__oe \gpio_oe [5] + connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5] + connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5] + connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] + connect \gpio_s6__core__i \gpio_i [6] + connect \gpio_s6__core__o \gpio_o [6] + connect \gpio_s6__core__oe \gpio_oe [6] + connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6] + connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6] + connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] + connect \gpio_s7__core__i \gpio_i [7] + connect \gpio_s7__core__o \gpio_o [7] + connect \gpio_s7__core__oe \gpio_oe [7] + connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7] + connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7] + connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] + connect \ibus__ack \main_libresocsim_libresoc_ibus_ack + connect \ibus__adr \main_libresocsim_libresoc_ibus_adr + connect \ibus__bte 1'0 + connect \ibus__cti 1'0 + connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w + connect \ibus__err \main_libresocsim_libresoc_ibus_err + connect \ibus__sel \main_libresocsim_libresoc_ibus_sel + connect \ibus__stb \main_libresocsim_libresoc_ibus_stb + connect \ibus__we \main_libresocsim_libresoc_ibus_we + connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr + connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr + connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we + connect \int_level_i \main_libresocsim_libresoc_interrupt + connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack + connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr + connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc + connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r + connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w + connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err + connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel + connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb + connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we + connect \memerr_o \main_libresocsim_libresoc1 + connect \mspi0_clk__core__o \spimaster_clk + connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + connect \mspi0_cs_n__core__o \spimaster_cs_n + connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + connect \mspi0_miso__core__i \spimaster_miso + connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + connect \mspi0_mosi__core__o \spimaster_mosi + connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + connect \mspi1_clk__core__o \spisdcard_clk + connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + connect \mspi1_cs_n__core__o \spisdcard_cs_n + connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + connect \mspi1_miso__core__i \spisdcard_miso + connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + connect \mspi1_mosi__core__o \spisdcard_mosi + connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + connect \mtwi_scl__core__o \i2c_scl + connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + connect \mtwi_sda__core__i \i2c_sda_i + connect \mtwi_sda__core__o \i2c_sda_o + connect \mtwi_sda__core__oe \i2c_sda_oe + connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \pc_o \main_libresocsim_libresoc2 + connect \pll_18_o \main_libresocsim_libresoc_pll_18_o + connect \pll_lck_o \main_libresocsim_libresoc_pll_lck_o + connect \pwm_0__core__o \pwm [0] + connect \pwm_0__pad__o \pwm_1 [0] + connect \pwm_1__core__o \pwm [1] + connect \pwm_1__pad__o \pwm_1 [1] + connect \rst $or$ls180.v:10706$3077_Y + connect \sd0_clk__core__o \sdcard_clk + connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + connect \sd0_cmd__core__i \sdcard_cmd_i + connect \sd0_cmd__core__o \sdcard_cmd_o + connect \sd0_cmd__core__oe \sdcard_cmd_oe + connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data0__core__i \sdcard_cmd_i + connect \sd0_data0__core__o \sdcard_cmd_o + connect \sd0_data0__core__oe \sdcard_cmd_oe + connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data1__core__i \sdcard_cmd_i + connect \sd0_data1__core__o \sdcard_cmd_o + connect \sd0_data1__core__oe \sdcard_cmd_oe + connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data2__core__i \sdcard_cmd_i + connect \sd0_data2__core__o \sdcard_cmd_o + connect \sd0_data2__core__oe \sdcard_cmd_oe + connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data3__core__i \sdcard_cmd_i + connect \sd0_data3__core__o \sdcard_cmd_o + connect \sd0_data3__core__oe \sdcard_cmd_oe + connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sdr_a_0__core__o \sdram_a [0] + connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] + connect \sdr_a_10__core__o \sdram_a [10] + connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10] + connect \sdr_a_11__core__o \sdram_a [11] + connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11] + connect \sdr_a_12__core__o \sdram_a [12] + connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12] + connect \sdr_a_1__core__o \sdram_a [1] + connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1] + connect \sdr_a_2__core__o \sdram_a [2] + connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2] + connect \sdr_a_3__core__o \sdram_a [3] + connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3] + connect \sdr_a_4__core__o \sdram_a [4] + connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4] + connect \sdr_a_5__core__o \sdram_a [5] + connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5] + connect \sdr_a_6__core__o \sdram_a [6] + connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6] + connect \sdr_a_7__core__o \sdram_a [7] + connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7] + connect \sdr_a_8__core__o \sdram_a [8] + connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8] + connect \sdr_a_9__core__o \sdram_a [9] + connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9] + connect \sdr_ba_0__core__o \sdram_ba [0] + connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] + connect \sdr_ba_1__core__o \sdram_ba [1] + connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] + connect \sdr_cas_n__core__o \sdram_cas_n + connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + connect \sdr_cke__core__o \sdram_cke + connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + connect \sdr_clock__core__o \sdram_clock + connect \sdr_clock__pad__o \sdram_clock_1 + connect \sdr_cs_n__core__o \sdram_cs_n + connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + connect \sdr_dm_0__core__o \sdram_dm [0] + connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] + connect \sdr_dm_1__core__i \sdram_dq_i [1] + connect \sdr_dm_1__core__o \sdram_dq_o [1] + connect \sdr_dm_1__core__oe \sdram_dq_oe + connect \sdr_dm_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dm_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_0__core__i \sdram_dq_i [0] + connect \sdr_dq_0__core__o \sdram_dq_o [0] + connect \sdr_dq_0__core__oe \sdram_dq_oe + connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] + connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] + connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_10__core__i \sdram_dq_i [10] + connect \sdr_dq_10__core__o \sdram_dq_o [10] + connect \sdr_dq_10__core__oe \sdram_dq_oe + connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] + connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] + connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_11__core__i \sdram_dq_i [11] + connect \sdr_dq_11__core__o \sdram_dq_o [11] + connect \sdr_dq_11__core__oe \sdram_dq_oe + connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] + connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] + connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_12__core__i \sdram_dq_i [12] + connect \sdr_dq_12__core__o \sdram_dq_o [12] + connect \sdr_dq_12__core__oe \sdram_dq_oe + connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] + connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] + connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_13__core__i \sdram_dq_i [13] + connect \sdr_dq_13__core__o \sdram_dq_o [13] + connect \sdr_dq_13__core__oe \sdram_dq_oe + connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] + connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] + connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_14__core__i \sdram_dq_i [14] + connect \sdr_dq_14__core__o \sdram_dq_o [14] + connect \sdr_dq_14__core__oe \sdram_dq_oe + connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] + connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] + connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_15__core__i \sdram_dq_i [15] + connect \sdr_dq_15__core__o \sdram_dq_o [15] + connect \sdr_dq_15__core__oe \sdram_dq_oe + connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] + connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] + connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_1__core__i \sdram_dq_i [1] + connect \sdr_dq_1__core__o \sdram_dq_o [1] + connect \sdr_dq_1__core__oe \sdram_dq_oe + connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_2__core__i \sdram_dq_i [2] + connect \sdr_dq_2__core__o \sdram_dq_o [2] + connect \sdr_dq_2__core__oe \sdram_dq_oe + connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] + connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] + connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_3__core__i \sdram_dq_i [3] + connect \sdr_dq_3__core__o \sdram_dq_o [3] + connect \sdr_dq_3__core__oe \sdram_dq_oe + connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] + connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] + connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_4__core__i \sdram_dq_i [4] + connect \sdr_dq_4__core__o \sdram_dq_o [4] + connect \sdr_dq_4__core__oe \sdram_dq_oe + connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] + connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] + connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_5__core__i \sdram_dq_i [5] + connect \sdr_dq_5__core__o \sdram_dq_o [5] + connect \sdr_dq_5__core__oe \sdram_dq_oe + connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] + connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] + connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_6__core__i \sdram_dq_i [6] + connect \sdr_dq_6__core__o \sdram_dq_o [6] + connect \sdr_dq_6__core__oe \sdram_dq_oe + connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] + connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] + connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_7__core__i \sdram_dq_i [7] + connect \sdr_dq_7__core__o \sdram_dq_o [7] + connect \sdr_dq_7__core__oe \sdram_dq_oe + connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] + connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] + connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_8__core__i \sdram_dq_i [8] + connect \sdr_dq_8__core__o \sdram_dq_o [8] + connect \sdr_dq_8__core__oe \sdram_dq_oe + connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] + connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] + connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_9__core__i \sdram_dq_i [9] + connect \sdr_dq_9__core__o \sdram_dq_o [9] + connect \sdr_dq_9__core__oe \sdram_dq_oe + connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] + connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] + connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_ras_n__core__o \sdram_ras_n + connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + connect \sdr_we_n__core__o \sdram_we_n + connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + connect \sram4k_0_wb__ack \main_libresocsim_libresoc_interface0_ack + connect \sram4k_0_wb__adr \main_libresocsim_libresoc_interface0_adr + connect \sram4k_0_wb__bte \main_libresocsim_libresoc_interface0_bte + connect \sram4k_0_wb__cti \main_libresocsim_libresoc_interface0_cti + connect \sram4k_0_wb__cyc \main_libresocsim_libresoc_interface0_cyc + connect \sram4k_0_wb__dat_r \main_libresocsim_libresoc_interface0_dat_r + connect \sram4k_0_wb__dat_w \main_libresocsim_libresoc_interface0_dat_w + connect \sram4k_0_wb__err \main_libresocsim_libresoc_interface0_err + connect \sram4k_0_wb__sel \main_libresocsim_libresoc_interface0_sel + connect \sram4k_0_wb__stb \main_libresocsim_libresoc_interface0_stb + connect \sram4k_0_wb__we \main_libresocsim_libresoc_interface0_we + connect \sram4k_1_wb__ack \main_libresocsim_libresoc_interface1_ack + connect \sram4k_1_wb__adr \main_libresocsim_libresoc_interface1_adr + connect \sram4k_1_wb__bte \main_libresocsim_libresoc_interface1_bte + connect \sram4k_1_wb__cti \main_libresocsim_libresoc_interface1_cti + connect \sram4k_1_wb__cyc \main_libresocsim_libresoc_interface1_cyc + connect \sram4k_1_wb__dat_r \main_libresocsim_libresoc_interface1_dat_r + connect \sram4k_1_wb__dat_w \main_libresocsim_libresoc_interface1_dat_w + connect \sram4k_1_wb__err \main_libresocsim_libresoc_interface1_err + connect \sram4k_1_wb__sel \main_libresocsim_libresoc_interface1_sel + connect \sram4k_1_wb__stb \main_libresocsim_libresoc_interface1_stb + connect \sram4k_1_wb__we \main_libresocsim_libresoc_interface1_we + connect \sram4k_2_wb__ack \main_libresocsim_libresoc_interface2_ack + connect \sram4k_2_wb__adr \main_libresocsim_libresoc_interface2_adr + connect \sram4k_2_wb__bte \main_libresocsim_libresoc_interface2_bte + connect \sram4k_2_wb__cti \main_libresocsim_libresoc_interface2_cti + connect \sram4k_2_wb__cyc \main_libresocsim_libresoc_interface2_cyc + connect \sram4k_2_wb__dat_r \main_libresocsim_libresoc_interface2_dat_r + connect \sram4k_2_wb__dat_w \main_libresocsim_libresoc_interface2_dat_w + connect \sram4k_2_wb__err \main_libresocsim_libresoc_interface2_err + connect \sram4k_2_wb__sel \main_libresocsim_libresoc_interface2_sel + connect \sram4k_2_wb__stb \main_libresocsim_libresoc_interface2_stb + connect \sram4k_2_wb__we \main_libresocsim_libresoc_interface2_we + connect \sram4k_3_wb__ack \main_libresocsim_libresoc_interface3_ack + connect \sram4k_3_wb__adr \main_libresocsim_libresoc_interface3_adr + connect \sram4k_3_wb__bte \main_libresocsim_libresoc_interface3_bte + connect \sram4k_3_wb__cti \main_libresocsim_libresoc_interface3_cti + connect \sram4k_3_wb__cyc \main_libresocsim_libresoc_interface3_cyc + connect \sram4k_3_wb__dat_r \main_libresocsim_libresoc_interface3_dat_r + connect \sram4k_3_wb__dat_w \main_libresocsim_libresoc_interface3_dat_w + connect \sram4k_3_wb__err \main_libresocsim_libresoc_interface3_err + connect \sram4k_3_wb__sel \main_libresocsim_libresoc_interface3_sel + connect \sram4k_3_wb__stb \main_libresocsim_libresoc_interface3_stb + connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4086 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4087 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4088 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4089 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4090 + sync always + sync init + end + attribute \src "ls180.v:100.11-100.56" + process $proc$ls180.v:100$3144 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] + end + attribute \src "ls180.v:1009.5-1009.40" + process $proc$ls180.v:1009$3478 + assign { } { } + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] + sync init + end + attribute \src "ls180.v:101.5-101.50" + process $proc$ls180.v:101$3145 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + end + attribute \src "ls180.v:1010.5-1010.39" + process $proc$ls180.v:1010$3479 + assign { } { } + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1018.5-1018.38" + process $proc$ls180.v:1018$3480 + assign { } { } + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + end + attribute \src "ls180.v:102.5-102.50" + process $proc$ls180.v:102$3146 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + end + attribute \src "ls180.v:1025.11-1025.42" + process $proc$ls180.v:1025$3481 + assign { } { } + assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] + end + attribute \src "ls180.v:1026.5-1026.37" + process $proc$ls180.v:1026$3482 + assign { } { } + assign $0\main_uart_tx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1027.11-1027.43" + process $proc$ls180.v:1027$3483 + assign { } { } + assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] + end + attribute \src "ls180.v:1028.11-1028.43" + process $proc$ls180.v:1028$3484 + assign { } { } + assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] + end + attribute \src "ls180.v:1029.11-1029.46" + process $proc$ls180.v:1029$3485 + assign { } { } + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:10350.1-10368.4" + process $proc$ls180.v:10350$2891 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr[5:0] \main_libresocsim_adr + attribute \src "ls180.v:10351.2-10352.65" + switch \main_libresocsim_we [0] + attribute \src "ls180.v:10351.6-10351.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10353.2-10354.67" + switch \main_libresocsim_we [1] + attribute \src "ls180.v:10353.6-10353.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10355.2-10356.69" + switch \main_libresocsim_we [2] + attribute \src "ls180.v:10355.6-10355.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10357.2-10358.69" + switch \main_libresocsim_we [3] + attribute \src "ls180.v:10357.6-10357.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10359.2-10360.69" + switch \main_libresocsim_we [4] + attribute \src "ls180.v:10359.6-10359.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10361.2-10362.69" + switch \main_libresocsim_we [5] + attribute \src "ls180.v:10361.6-10361.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10363.2-10364.69" + switch \main_libresocsim_we [6] + attribute \src "ls180.v:10363.6-10363.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10365.2-10366.69" + switch \main_libresocsim_we [7] + attribute \src "ls180.v:10365.6-10365.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[5:0] + update $memwr$\mem$ls180.v:10352$1_ADDR $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 + update $memwr$\mem$ls180.v:10352$1_DATA $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 + update $memwr$\mem$ls180.v:10352$1_EN $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 + update $memwr$\mem$ls180.v:10354$2_ADDR $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 + update $memwr$\mem$ls180.v:10354$2_DATA $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 + update $memwr$\mem$ls180.v:10354$2_EN $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 + update $memwr$\mem$ls180.v:10356$3_ADDR $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 + update $memwr$\mem$ls180.v:10356$3_DATA $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 + update $memwr$\mem$ls180.v:10356$3_EN $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 + update $memwr$\mem$ls180.v:10358$4_ADDR $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 + update $memwr$\mem$ls180.v:10358$4_DATA $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 + update $memwr$\mem$ls180.v:10358$4_EN $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 + update $memwr$\mem$ls180.v:10360$5_ADDR $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 + update $memwr$\mem$ls180.v:10360$5_DATA $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 + update $memwr$\mem$ls180.v:10360$5_EN $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 + update $memwr$\mem$ls180.v:10362$6_ADDR $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 + update $memwr$\mem$ls180.v:10362$6_DATA $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 + update $memwr$\mem$ls180.v:10362$6_EN $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 + update $memwr$\mem$ls180.v:10364$7_ADDR $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 + update $memwr$\mem$ls180.v:10364$7_DATA $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 + update $memwr$\mem$ls180.v:10364$7_EN $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 + update $memwr$\mem$ls180.v:10366$8_ADDR $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 + update $memwr$\mem$ls180.v:10366$8_DATA $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 + update $memwr$\mem$ls180.v:10366$8_EN $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 + end + attribute \src "ls180.v:10378.1-10396.4" + process $proc$ls180.v:10378$2917 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_1[5:0] \main_sram0_adr + attribute \src "ls180.v:10379.2-10380.55" + switch \main_sram0_we [0] + attribute \src "ls180.v:10379.6-10379.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } + assign $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10381.2-10382.57" + switch \main_sram0_we [1] + attribute \src "ls180.v:10381.6-10381.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10383.2-10384.59" + switch \main_sram0_we [2] + attribute \src "ls180.v:10383.6-10383.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10385.2-10386.59" + switch \main_sram0_we [3] + attribute \src "ls180.v:10385.6-10385.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10387.2-10388.59" + switch \main_sram0_we [4] + attribute \src "ls180.v:10387.6-10387.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10389.2-10390.59" + switch \main_sram0_we [5] + attribute \src "ls180.v:10389.6-10389.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10391.2-10392.59" + switch \main_sram0_we [6] + attribute \src "ls180.v:10391.6-10391.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10393.2-10394.59" + switch \main_sram0_we [7] + attribute \src "ls180.v:10393.6-10393.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_1 $0\memadr_1[5:0] + update $memwr$\mem_1$ls180.v:10380$9_ADDR $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 + update $memwr$\mem_1$ls180.v:10380$9_DATA $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 + update $memwr$\mem_1$ls180.v:10380$9_EN $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 + update $memwr$\mem_1$ls180.v:10382$10_ADDR $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 + update $memwr$\mem_1$ls180.v:10382$10_DATA $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 + update $memwr$\mem_1$ls180.v:10382$10_EN $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 + update $memwr$\mem_1$ls180.v:10384$11_ADDR $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 + update $memwr$\mem_1$ls180.v:10384$11_DATA $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 + update $memwr$\mem_1$ls180.v:10384$11_EN $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 + update $memwr$\mem_1$ls180.v:10386$12_ADDR $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 + update $memwr$\mem_1$ls180.v:10386$12_DATA $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 + update $memwr$\mem_1$ls180.v:10386$12_EN $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 + update $memwr$\mem_1$ls180.v:10388$13_ADDR $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 + update $memwr$\mem_1$ls180.v:10388$13_DATA $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 + update $memwr$\mem_1$ls180.v:10388$13_EN $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 + update $memwr$\mem_1$ls180.v:10390$14_ADDR $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 + update $memwr$\mem_1$ls180.v:10390$14_DATA $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 + update $memwr$\mem_1$ls180.v:10390$14_EN $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 + update $memwr$\mem_1$ls180.v:10392$15_ADDR $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 + update $memwr$\mem_1$ls180.v:10392$15_DATA $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 + update $memwr$\mem_1$ls180.v:10392$15_EN $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 + update $memwr$\mem_1$ls180.v:10394$16_ADDR $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 + update $memwr$\mem_1$ls180.v:10394$16_DATA $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 + update $memwr$\mem_1$ls180.v:10394$16_EN $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 + end + attribute \src "ls180.v:104.5-104.49" + process $proc$ls180.v:104$3147 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] + end + attribute \src "ls180.v:10406.1-10424.4" + process $proc$ls180.v:10406$2943 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_2[5:0] \main_sram1_adr + attribute \src "ls180.v:10407.2-10408.55" + switch \main_sram1_we [0] + attribute \src "ls180.v:10407.6-10407.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } + assign $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10409.2-10410.57" + switch \main_sram1_we [1] + attribute \src "ls180.v:10409.6-10409.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10411.2-10412.59" + switch \main_sram1_we [2] + attribute \src "ls180.v:10411.6-10411.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10413.2-10414.59" + switch \main_sram1_we [3] + attribute \src "ls180.v:10413.6-10413.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10415.2-10416.59" + switch \main_sram1_we [4] + attribute \src "ls180.v:10415.6-10415.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10417.2-10418.59" + switch \main_sram1_we [5] + attribute \src "ls180.v:10417.6-10417.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10419.2-10420.59" + switch \main_sram1_we [6] + attribute \src "ls180.v:10419.6-10419.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10421.2-10422.59" + switch \main_sram1_we [7] + attribute \src "ls180.v:10421.6-10421.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_2 $0\memadr_2[5:0] + update $memwr$\mem_2$ls180.v:10408$17_ADDR $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 + update $memwr$\mem_2$ls180.v:10408$17_DATA $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 + update $memwr$\mem_2$ls180.v:10408$17_EN $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 + update $memwr$\mem_2$ls180.v:10410$18_ADDR $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 + update $memwr$\mem_2$ls180.v:10410$18_DATA $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 + update $memwr$\mem_2$ls180.v:10410$18_EN $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 + update $memwr$\mem_2$ls180.v:10412$19_ADDR $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 + update $memwr$\mem_2$ls180.v:10412$19_DATA $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 + update $memwr$\mem_2$ls180.v:10412$19_EN $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 + update $memwr$\mem_2$ls180.v:10414$20_ADDR $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 + update $memwr$\mem_2$ls180.v:10414$20_DATA $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 + update $memwr$\mem_2$ls180.v:10414$20_EN $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 + update $memwr$\mem_2$ls180.v:10416$21_ADDR $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 + update $memwr$\mem_2$ls180.v:10416$21_DATA $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 + update $memwr$\mem_2$ls180.v:10416$21_EN $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 + update $memwr$\mem_2$ls180.v:10418$22_ADDR $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 + update $memwr$\mem_2$ls180.v:10418$22_DATA $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 + update $memwr$\mem_2$ls180.v:10418$22_EN $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 + update $memwr$\mem_2$ls180.v:10420$23_ADDR $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 + update $memwr$\mem_2$ls180.v:10420$23_DATA $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 + update $memwr$\mem_2$ls180.v:10420$23_EN $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 + update $memwr$\mem_2$ls180.v:10422$24_ADDR $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 + update $memwr$\mem_2$ls180.v:10422$24_DATA $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 + update $memwr$\mem_2$ls180.v:10422$24_EN $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 + end + attribute \src "ls180.v:10434.1-10452.4" + process $proc$ls180.v:10434$2969 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_3[5:0] \main_sram2_adr + attribute \src "ls180.v:10435.2-10436.55" + switch \main_sram2_we [0] + attribute \src "ls180.v:10435.6-10435.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } + assign $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10437.2-10438.57" + switch \main_sram2_we [1] + attribute \src "ls180.v:10437.6-10437.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10439.2-10440.59" + switch \main_sram2_we [2] + attribute \src "ls180.v:10439.6-10439.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10441.2-10442.59" + switch \main_sram2_we [3] + attribute \src "ls180.v:10441.6-10441.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10443.2-10444.59" + switch \main_sram2_we [4] + attribute \src "ls180.v:10443.6-10443.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10445.2-10446.59" + switch \main_sram2_we [5] + attribute \src "ls180.v:10445.6-10445.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10447.2-10448.59" + switch \main_sram2_we [6] + attribute \src "ls180.v:10447.6-10447.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10449.2-10450.59" + switch \main_sram2_we [7] + attribute \src "ls180.v:10449.6-10449.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_3 $0\memadr_3[5:0] + update $memwr$\mem_3$ls180.v:10436$25_ADDR $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 + update $memwr$\mem_3$ls180.v:10436$25_DATA $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 + update $memwr$\mem_3$ls180.v:10436$25_EN $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 + update $memwr$\mem_3$ls180.v:10438$26_ADDR $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 + update $memwr$\mem_3$ls180.v:10438$26_DATA $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 + update $memwr$\mem_3$ls180.v:10438$26_EN $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 + update $memwr$\mem_3$ls180.v:10440$27_ADDR $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 + update $memwr$\mem_3$ls180.v:10440$27_DATA $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 + update $memwr$\mem_3$ls180.v:10440$27_EN $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 + update $memwr$\mem_3$ls180.v:10442$28_ADDR $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 + update $memwr$\mem_3$ls180.v:10442$28_DATA $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 + update $memwr$\mem_3$ls180.v:10442$28_EN $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 + update $memwr$\mem_3$ls180.v:10444$29_ADDR $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 + update $memwr$\mem_3$ls180.v:10444$29_DATA $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 + update $memwr$\mem_3$ls180.v:10444$29_EN $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 + update $memwr$\mem_3$ls180.v:10446$30_ADDR $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 + update $memwr$\mem_3$ls180.v:10446$30_DATA $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 + update $memwr$\mem_3$ls180.v:10446$30_EN $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 + update $memwr$\mem_3$ls180.v:10448$31_ADDR $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 + update $memwr$\mem_3$ls180.v:10448$31_DATA $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 + update $memwr$\mem_3$ls180.v:10448$31_EN $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 + update $memwr$\mem_3$ls180.v:10450$32_ADDR $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 + update $memwr$\mem_3$ls180.v:10450$32_DATA $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 + update $memwr$\mem_3$ls180.v:10450$32_EN $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 + end + attribute \src "ls180.v:10462.1-10480.4" + process $proc$ls180.v:10462$2995 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_4[5:0] \main_sram3_adr + attribute \src "ls180.v:10463.2-10464.55" + switch \main_sram3_we [0] + attribute \src "ls180.v:10463.6-10463.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } + assign $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10465.2-10466.57" + switch \main_sram3_we [1] + attribute \src "ls180.v:10465.6-10465.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10467.2-10468.59" + switch \main_sram3_we [2] + attribute \src "ls180.v:10467.6-10467.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10469.2-10470.59" + switch \main_sram3_we [3] + attribute \src "ls180.v:10469.6-10469.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10471.2-10472.59" + switch \main_sram3_we [4] + attribute \src "ls180.v:10471.6-10471.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10473.2-10474.59" + switch \main_sram3_we [5] + attribute \src "ls180.v:10473.6-10473.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10475.2-10476.59" + switch \main_sram3_we [6] + attribute \src "ls180.v:10475.6-10475.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10477.2-10478.59" + switch \main_sram3_we [7] + attribute \src "ls180.v:10477.6-10477.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_4 $0\memadr_4[5:0] + update $memwr$\mem_4$ls180.v:10464$33_ADDR $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 + update $memwr$\mem_4$ls180.v:10464$33_DATA $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 + update $memwr$\mem_4$ls180.v:10464$33_EN $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 + update $memwr$\mem_4$ls180.v:10466$34_ADDR $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 + update $memwr$\mem_4$ls180.v:10466$34_DATA $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 + update $memwr$\mem_4$ls180.v:10466$34_EN $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 + update $memwr$\mem_4$ls180.v:10468$35_ADDR $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 + update $memwr$\mem_4$ls180.v:10468$35_DATA $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 + update $memwr$\mem_4$ls180.v:10468$35_EN $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 + update $memwr$\mem_4$ls180.v:10470$36_ADDR $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 + update $memwr$\mem_4$ls180.v:10470$36_DATA $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 + update $memwr$\mem_4$ls180.v:10470$36_EN $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 + update $memwr$\mem_4$ls180.v:10472$37_ADDR $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 + update $memwr$\mem_4$ls180.v:10472$37_DATA $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 + update $memwr$\mem_4$ls180.v:10472$37_EN $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 + update $memwr$\mem_4$ls180.v:10474$38_ADDR $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 + update $memwr$\mem_4$ls180.v:10474$38_DATA $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 + update $memwr$\mem_4$ls180.v:10474$38_EN $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 + update $memwr$\mem_4$ls180.v:10476$39_ADDR $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 + update $memwr$\mem_4$ls180.v:10476$39_DATA $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 + update $memwr$\mem_4$ls180.v:10476$39_EN $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 + update $memwr$\mem_4$ls180.v:10478$40_ADDR $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 + update $memwr$\mem_4$ls180.v:10478$40_DATA $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 + update $memwr$\mem_4$ls180.v:10478$40_EN $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 + end + attribute \src "ls180.v:10490.1-10494.4" + process $proc$ls180.v:10490$3021 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 3'xxx + assign $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10493$3025_DATA + attribute \src "ls180.v:10491.2-10492.129" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10491.6-10491.60" + case 1'1 + assign $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:10492$41_ADDR $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 + update $memwr$\storage$ls180.v:10492$41_DATA $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 + update $memwr$\storage$ls180.v:10492$41_EN $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 + end + attribute \src "ls180.v:10496.1-10497.4" + process $proc$ls180.v:10496$3026 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10504.1-10508.4" + process $proc$ls180.v:10504$3028 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 3'xxx + assign $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10507$3032_DATA + attribute \src "ls180.v:10505.2-10506.131" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10505.6-10505.60" + case 1'1 + assign $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:10506$42_ADDR $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 + update $memwr$\storage_1$ls180.v:10506$42_DATA $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 + update $memwr$\storage_1$ls180.v:10506$42_EN $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 + end + attribute \src "ls180.v:10510.1-10511.4" + process $proc$ls180.v:10510$3033 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10518.1-10522.4" + process $proc$ls180.v:10518$3035 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 3'xxx + assign $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10521$3039_DATA + attribute \src "ls180.v:10519.2-10520.131" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10519.6-10519.60" + case 1'1 + assign $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[24:0] + update $memwr$\storage_2$ls180.v:10520$43_ADDR $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 + update $memwr$\storage_2$ls180.v:10520$43_DATA $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 + update $memwr$\storage_2$ls180.v:10520$43_EN $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 + end + attribute \src "ls180.v:10524.1-10525.4" + process $proc$ls180.v:10524$3040 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10532.1-10536.4" + process $proc$ls180.v:10532$3042 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 3'xxx + assign $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10535$3046_DATA + attribute \src "ls180.v:10533.2-10534.131" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10533.6-10533.60" + case 1'1 + assign $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[24:0] + update $memwr$\storage_3$ls180.v:10534$44_ADDR $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 + update $memwr$\storage_3$ls180.v:10534$44_DATA $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 + update $memwr$\storage_3$ls180.v:10534$44_EN $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 + end + attribute \src "ls180.v:10538.1-10539.4" + process $proc$ls180.v:10538$3047 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10547.1-10551.4" + process $proc$ls180.v:10547$3049 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10550$3053_DATA + attribute \src "ls180.v:10548.2-10549.77" + switch \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:10548.6-10548.33" + case 1'1 + assign $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[9:0] + update $memwr$\storage_4$ls180.v:10549$45_ADDR $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 + update $memwr$\storage_4$ls180.v:10549$45_DATA $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 + update $memwr$\storage_4$ls180.v:10549$45_EN $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 + end + attribute \src "ls180.v:1055.5-1055.38" + process $proc$ls180.v:1055$3486 + assign { } { } + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] + end + attribute \src "ls180.v:10553.1-10556.4" + process $proc$ls180.v:10553$3054 + assign $0\memdat_5[9:0] \memdat_5 + attribute \src "ls180.v:10554.2-10555.55" + switch \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:10554.6-10554.33" + case 1'1 + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10555$3055_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[9:0] + end + attribute \src "ls180.v:10564.1-10568.4" + process $proc$ls180.v:10564$3056 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10567$3060_DATA + attribute \src "ls180.v:10565.2-10566.77" + switch \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:10565.6-10565.33" + case 1'1 + assign $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[9:0] + update $memwr$\storage_5$ls180.v:10566$46_ADDR $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 + update $memwr$\storage_5$ls180.v:10566$46_DATA $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 + update $memwr$\storage_5$ls180.v:10566$46_EN $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 + end + attribute \src "ls180.v:10570.1-10573.4" + process $proc$ls180.v:10570$3061 + assign $0\memdat_7[9:0] \memdat_7 + attribute \src "ls180.v:10571.2-10572.55" + switch \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:10571.6-10571.33" + case 1'1 + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10572$3062_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[9:0] + end + attribute \src "ls180.v:10580.1-10584.4" + process $proc$ls180.v:10580$3063 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10583$3067_DATA + attribute \src "ls180.v:10581.2-10582.85" + switch \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:10581.6-10581.37" + case 1'1 + assign $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_8 $0\memdat_8[9:0] + update $memwr$\storage_6$ls180.v:10582$47_ADDR $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 + update $memwr$\storage_6$ls180.v:10582$47_DATA $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 + update $memwr$\storage_6$ls180.v:10582$47_EN $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 + end + attribute \src "ls180.v:10586.1-10587.4" + process $proc$ls180.v:10586$3068 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10594.1-10598.4" + process $proc$ls180.v:10594$3070 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10597$3074_DATA + attribute \src "ls180.v:10595.2-10596.85" + switch \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:10595.6-10595.37" + case 1'1 + assign $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_9 $0\memdat_9[9:0] + update $memwr$\storage_7$ls180.v:10596$48_ADDR $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 + update $memwr$\storage_7$ls180.v:10596$48_DATA $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 + update $memwr$\storage_7$ls180.v:10596$48_EN $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 + end + attribute \src "ls180.v:10600.1-10601.4" + process $proc$ls180.v:10600$3075 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1062.11-1062.42" + process $proc$ls180.v:1062$3487 + assign { } { } + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + end + attribute \src "ls180.v:1063.5-1063.37" + process $proc$ls180.v:1063$3488 + assign { } { } + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1064.11-1064.43" + process $proc$ls180.v:1064$3489 + assign { } { } + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] + end + attribute \src "ls180.v:1065.11-1065.43" + process $proc$ls180.v:1065$3490 + assign { } { } + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] + end + attribute \src "ls180.v:1066.11-1066.46" + process $proc$ls180.v:1066$3491 + assign { } { } + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:1081.5-1081.27" + process $proc$ls180.v:1081$3492 + assign { } { } + assign $0\main_uart_reset[0:0] 1'0 + sync always + update \main_uart_reset $0\main_uart_reset[0:0] + sync init + end + attribute \src "ls180.v:1082.12-1082.53" + process $proc$ls180.v:1082$3493 + assign { } { } + assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] + sync init + end + attribute \src "ls180.v:1083.12-1083.49" + process $proc$ls180.v:1083$3494 + assign { } { } + assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] + end + attribute \src "ls180.v:1084.12-1084.54" + process $proc$ls180.v:1084$3495 + assign { } { } + assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] + sync init + end + attribute \src "ls180.v:1088.12-1088.53" + process $proc$ls180.v:1088$3496 + assign { } { } + assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] + end + attribute \src "ls180.v:1089.5-1089.40" + process $proc$ls180.v:1089$3497 + assign { } { } + assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 + sync always + sync init + update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] + end + attribute \src "ls180.v:1090.12-1090.49" + process $proc$ls180.v:1090$3498 + assign { } { } + assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] + end + attribute \src "ls180.v:1092.12-1092.54" + process $proc$ls180.v:1092$3499 + assign { } { } + assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] + end + attribute \src "ls180.v:1093.5-1093.41" + process $proc$ls180.v:1093$3500 + assign { } { } + assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 + sync always + sync init + update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] + end + attribute \src "ls180.v:1099.5-1099.32" + process $proc$ls180.v:1099$3501 + assign { } { } + assign $1\main_spimaster2_done[0:0] 1'0 + sync always + sync init + update \main_spimaster2_done $1\main_spimaster2_done[0:0] + end + attribute \src "ls180.v:1100.5-1100.31" + process $proc$ls180.v:1100$3502 + assign { } { } + assign $1\main_spimaster3_irq[0:0] 1'0 + sync always + sync init + update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] + end + attribute \src "ls180.v:1102.11-1102.38" + process $proc$ls180.v:1102$3503 + assign { } { } + assign $1\main_spimaster5_miso[7:0] 8'00000000 + sync always + sync init + update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] + end + attribute \src "ls180.v:1105.12-1105.47" + process $proc$ls180.v:1105$3504 + assign { } { } + assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 + sync always + update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] + sync init + end + attribute \src "ls180.v:1106.5-1106.33" + process $proc$ls180.v:1106$3505 + assign { } { } + assign $1\main_spimaster9_start[0:0] 1'0 + sync always + sync init + update \main_spimaster9_start $1\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:1108.12-1108.44" + process $proc$ls180.v:1108$3506 + assign { } { } + assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] + end + attribute \src "ls180.v:1109.5-1109.31" + process $proc$ls180.v:1109$3507 + assign { } { } + assign $1\main_spimaster12_re[0:0] 1'0 + sync always + sync init + update \main_spimaster12_re $1\main_spimaster12_re[0:0] + end + attribute \src "ls180.v:1113.11-1113.42" + process $proc$ls180.v:1113$3508 + assign { } { } + assign $1\main_spimaster16_storage[7:0] 8'00000000 + sync always + sync init + update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] + end + attribute \src "ls180.v:1114.5-1114.31" + process $proc$ls180.v:1114$3509 + assign { } { } + assign $1\main_spimaster17_re[0:0] 1'0 + sync always + sync init + update \main_spimaster17_re $1\main_spimaster17_re[0:0] + end + attribute \src "ls180.v:1118.5-1118.36" + process $proc$ls180.v:1118$3510 + assign { } { } + assign $1\main_spimaster21_storage[0:0] 1'1 + sync always + sync init + update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] + end + attribute \src "ls180.v:1119.5-1119.31" + process $proc$ls180.v:1119$3511 + assign { } { } + assign $1\main_spimaster22_re[0:0] 1'0 + sync always + sync init + update \main_spimaster22_re $1\main_spimaster22_re[0:0] + end + attribute \src "ls180.v:1120.5-1120.36" + process $proc$ls180.v:1120$3512 + assign { } { } + assign $1\main_spimaster23_storage[0:0] 1'0 + sync always + sync init + update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] + end + attribute \src "ls180.v:1121.5-1121.31" + process $proc$ls180.v:1121$3513 + assign { } { } + assign $1\main_spimaster24_re[0:0] 1'0 + sync always + sync init + update \main_spimaster24_re $1\main_spimaster24_re[0:0] + end + attribute \src "ls180.v:1122.5-1122.39" + process $proc$ls180.v:1122$3514 + assign { } { } + assign $1\main_spimaster25_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] + end + attribute \src "ls180.v:1123.5-1123.38" + process $proc$ls180.v:1123$3515 + assign { } { } + assign $1\main_spimaster26_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] + end + attribute \src "ls180.v:1124.11-1124.40" + process $proc$ls180.v:1124$3516 + assign { } { } + assign $1\main_spimaster27_count[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count $1\main_spimaster27_count[2:0] + end + attribute \src "ls180.v:1125.5-1125.39" + process $proc$ls180.v:1125$3517 + assign { } { } + assign $1\main_spimaster28_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] + end + attribute \src "ls180.v:1126.5-1126.39" + process $proc$ls180.v:1126$3518 + assign { } { } + assign $1\main_spimaster29_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] + end + attribute \src "ls180.v:1127.12-1127.48" + process $proc$ls180.v:1127$3519 + assign { } { } + assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] + end + attribute \src "ls180.v:1130.11-1130.44" + process $proc$ls180.v:1130$3520 + assign { } { } + assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] + end + attribute \src "ls180.v:1131.11-1131.43" + process $proc$ls180.v:1131$3521 + assign { } { } + assign $1\main_spimaster34_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] + end + attribute \src "ls180.v:1132.11-1132.44" + process $proc$ls180.v:1132$3522 + assign { } { } + assign $1\main_spimaster35_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] + end + attribute \src "ls180.v:1135.5-1135.32" + process $proc$ls180.v:1135$3523 + assign { } { } + assign $1\main_spisdcard_done0[0:0] 1'0 + sync always + sync init + update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] + end + attribute \src "ls180.v:1136.5-1136.30" + process $proc$ls180.v:1136$3524 + assign { } { } + assign $1\main_spisdcard_irq[0:0] 1'0 + sync always + sync init + update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] + end + attribute \src "ls180.v:1138.11-1138.37" + process $proc$ls180.v:1138$3525 + assign { } { } + assign $1\main_spisdcard_miso[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] + end + attribute \src "ls180.v:114.11-114.55" + process $proc$ls180.v:114$3148 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + sync init + end + attribute \src "ls180.v:1142.5-1142.33" + process $proc$ls180.v:1142$3526 + assign { } { } + assign $1\main_spisdcard_start1[0:0] 1'0 + sync always + sync init + update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:1144.12-1144.50" + process $proc$ls180.v:1144$3527 + assign { } { } + assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] + end + attribute \src "ls180.v:1145.5-1145.37" + process $proc$ls180.v:1145$3528 + assign { } { } + assign $1\main_spisdcard_control_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] + end + attribute \src "ls180.v:1149.11-1149.45" + process $proc$ls180.v:1149$3529 + assign { } { } + assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] + end + attribute \src "ls180.v:115.11-115.55" + process $proc$ls180.v:115$3149 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + sync init + end + attribute \src "ls180.v:1150.5-1150.34" + process $proc$ls180.v:1150$3530 + assign { } { } + assign $1\main_spisdcard_mosi_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] + end + attribute \src "ls180.v:1154.5-1154.37" + process $proc$ls180.v:1154$3531 + assign { } { } + assign $1\main_spisdcard_cs_storage[0:0] 1'1 + sync always + sync init + update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] + end + attribute \src "ls180.v:1155.5-1155.32" + process $proc$ls180.v:1155$3532 + assign { } { } + assign $1\main_spisdcard_cs_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] + end + attribute \src "ls180.v:1156.5-1156.43" + process $proc$ls180.v:1156$3533 + assign { } { } + assign $1\main_spisdcard_loopback_storage[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] + end + attribute \src "ls180.v:1157.5-1157.38" + process $proc$ls180.v:1157$3534 + assign { } { } + assign $1\main_spisdcard_loopback_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] + end + attribute \src "ls180.v:1158.5-1158.37" + process $proc$ls180.v:1158$3535 + assign { } { } + assign $1\main_spisdcard_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] + end + attribute \src "ls180.v:1159.5-1159.36" + process $proc$ls180.v:1159$3536 + assign { } { } + assign $1\main_spisdcard_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] + end + attribute \src "ls180.v:1160.11-1160.38" + process $proc$ls180.v:1160$3537 + assign { } { } + assign $1\main_spisdcard_count[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count $1\main_spisdcard_count[2:0] + end + attribute \src "ls180.v:1161.5-1161.37" + process $proc$ls180.v:1161$3538 + assign { } { } + assign $1\main_spisdcard_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] + end + attribute \src "ls180.v:1162.5-1162.37" + process $proc$ls180.v:1162$3539 + assign { } { } + assign $1\main_spisdcard_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] + end + attribute \src "ls180.v:1163.12-1163.47" + process $proc$ls180.v:1163$3540 + assign { } { } + assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] + end + attribute \src "ls180.v:1166.11-1166.42" + process $proc$ls180.v:1166$3541 + assign { } { } + assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] + end + attribute \src "ls180.v:1167.11-1167.41" + process $proc$ls180.v:1167$3542 + assign { } { } + assign $1\main_spisdcard_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] + end + attribute \src "ls180.v:1168.11-1168.42" + process $proc$ls180.v:1168$3543 + assign { } { } + assign $1\main_spisdcard_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] + end + attribute \src "ls180.v:1169.12-1169.45" + process $proc$ls180.v:1169$3544 + assign { } { } + assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 + sync always + sync init + update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] + end + attribute \src "ls180.v:1170.5-1170.30" + process $proc$ls180.v:1170$3545 + assign { } { } + assign $1\main_spimaster1_re[0:0] 1'0 + sync always + sync init + update \main_spimaster1_re $1\main_spimaster1_re[0:0] + end + attribute \src "ls180.v:1172.12-1172.30" + process $proc$ls180.v:1172$3546 + assign { } { } + assign $1\main_dummy[23:0] 24'000000000000000000000000 + sync always + sync init + update \main_dummy $1\main_dummy[23:0] + end + attribute \src "ls180.v:1176.12-1176.37" + process $proc$ls180.v:1176$3547 + assign { } { } + assign $1\main_pwm0_counter[31:0] 0 + sync always + sync init + update \main_pwm0_counter $1\main_pwm0_counter[31:0] + end + attribute \src "ls180.v:1177.5-1177.36" + process $proc$ls180.v:1177$3548 + assign { } { } + assign $1\main_pwm0_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] + end + attribute \src "ls180.v:1178.5-1178.31" + process $proc$ls180.v:1178$3549 + assign { } { } + assign $1\main_pwm0_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] + end + attribute \src "ls180.v:1179.12-1179.43" + process $proc$ls180.v:1179$3550 + assign { } { } + assign $1\main_pwm0_width_storage[31:0] 0 + sync always + sync init + update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] + end + attribute \src "ls180.v:1180.5-1180.30" + process $proc$ls180.v:1180$3551 + assign { } { } + assign $1\main_pwm0_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + end + attribute \src "ls180.v:1181.12-1181.44" + process $proc$ls180.v:1181$3552 + assign { } { } + assign $1\main_pwm0_period_storage[31:0] 0 + sync always + sync init + update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] + end + attribute \src "ls180.v:1182.5-1182.31" + process $proc$ls180.v:1182$3553 + assign { } { } + assign $1\main_pwm0_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + end + attribute \src "ls180.v:1186.12-1186.37" + process $proc$ls180.v:1186$3554 + assign { } { } + assign $1\main_pwm1_counter[31:0] 0 + sync always + sync init + update \main_pwm1_counter $1\main_pwm1_counter[31:0] + end + attribute \src "ls180.v:1187.5-1187.36" + process $proc$ls180.v:1187$3555 + assign { } { } + assign $1\main_pwm1_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] + end + attribute \src "ls180.v:1188.5-1188.31" + process $proc$ls180.v:1188$3556 + assign { } { } + assign $1\main_pwm1_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] + end + attribute \src "ls180.v:1189.12-1189.43" + process $proc$ls180.v:1189$3557 + assign { } { } + assign $1\main_pwm1_width_storage[31:0] 0 + sync always + sync init + update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] + end + attribute \src "ls180.v:1190.5-1190.30" + process $proc$ls180.v:1190$3558 + assign { } { } + assign $1\main_pwm1_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] + end + attribute \src "ls180.v:1191.12-1191.44" + process $proc$ls180.v:1191$3559 + assign { } { } + assign $1\main_pwm1_period_storage[31:0] 0 + sync always + sync init + update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] + end + attribute \src "ls180.v:1192.5-1192.31" + process $proc$ls180.v:1192$3560 + assign { } { } + assign $1\main_pwm1_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] + end + attribute \src "ls180.v:1196.11-1196.34" + process $proc$ls180.v:1196$3561 + assign { } { } + assign $1\main_i2c_storage[2:0] 3'000 + sync always + sync init + update \main_i2c_storage $1\main_i2c_storage[2:0] + end + attribute \src "ls180.v:1197.5-1197.23" + process $proc$ls180.v:1197$3562 + assign { } { } + assign $1\main_i2c_re[0:0] 1'0 + sync always + sync init + update \main_i2c_re $1\main_i2c_re[0:0] + end + attribute \src "ls180.v:1203.11-1203.46" + process $proc$ls180.v:1203$3563 + assign { } { } + assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 + sync always + sync init + update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] + end + attribute \src "ls180.v:1204.5-1204.33" + process $proc$ls180.v:1204$3564 + assign { } { } + assign $1\main_sdphy_clocker_re[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] + end + attribute \src "ls180.v:1206.5-1206.35" + process $proc$ls180.v:1206$3565 + assign { } { } + assign $1\main_sdphy_clocker_clk0[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] + end + attribute \src "ls180.v:1208.11-1208.41" + process $proc$ls180.v:1208$3566 + assign { } { } + assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 + sync always + sync init + update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] + end + attribute \src "ls180.v:1209.5-1209.35" + process $proc$ls180.v:1209$3567 + assign { } { } + assign $1\main_sdphy_clocker_clk1[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:1210.5-1210.36" + process $proc$ls180.v:1210$3568 + assign { } { } + assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] + end + attribute \src "ls180.v:1214.5-1214.40" + process $proc$ls180.v:1214$3569 + assign { } { } + assign $0\main_sdphy_init_initialize_w[0:0] 1'0 + sync always + update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] + sync init + end + attribute \src "ls180.v:1219.5-1219.48" + process $proc$ls180.v:1219$3570 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1220.5-1220.50" + process $proc$ls180.v:1220$3571 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1221.5-1221.51" + process $proc$ls180.v:1221$3572 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1222.11-1222.57" + process $proc$ls180.v:1222$3573 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1223.5-1223.52" + process $proc$ls180.v:1223$3574 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1224.11-1224.39" + process $proc$ls180.v:1224$3575 + assign { } { } + assign $1\main_sdphy_init_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] + end + attribute \src "ls180.v:1229.5-1229.48" + process $proc$ls180.v:1229$3576 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1230.5-1230.50" + process $proc$ls180.v:1230$3577 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1231.5-1231.51" + process $proc$ls180.v:1231$3578 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1232.11-1232.57" + process $proc$ls180.v:1232$3579 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1233.5-1233.52" + process $proc$ls180.v:1233$3580 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1234.5-1234.38" + process $proc$ls180.v:1234$3581 + assign { } { } + assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] + end + attribute \src "ls180.v:1235.5-1235.38" + process $proc$ls180.v:1235$3582 + assign { } { } + assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] + end + attribute \src "ls180.v:1236.5-1236.37" + process $proc$ls180.v:1236$3583 + assign { } { } + assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] + end + attribute \src "ls180.v:1237.11-1237.51" + process $proc$ls180.v:1237$3584 + assign { } { } + assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1238.5-1238.32" + process $proc$ls180.v:1238$3585 + assign { } { } + assign $1\main_sdphy_cmdw_done[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] + end + attribute \src "ls180.v:1239.11-1239.39" + process $proc$ls180.v:1239$3586 + assign { } { } + assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] + end + attribute \src "ls180.v:1242.5-1242.49" + process $proc$ls180.v:1242$3587 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1243.5-1243.48" + process $proc$ls180.v:1243$3588 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1244.5-1244.55" + process $proc$ls180.v:1244$3589 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1246.5-1246.57" + process $proc$ls180.v:1246$3590 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1247.5-1247.58" + process $proc$ls180.v:1247$3591 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1249.11-1249.64" + process $proc$ls180.v:1249$3592 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1250.5-1250.59" + process $proc$ls180.v:1250$3593 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1252.5-1252.48" + process $proc$ls180.v:1252$3594 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1253.5-1253.50" + process $proc$ls180.v:1253$3595 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1254.5-1254.51" + process $proc$ls180.v:1254$3596 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1255.11-1255.57" + process $proc$ls180.v:1255$3597 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1256.5-1256.52" + process $proc$ls180.v:1256$3598 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1257.5-1257.38" + process $proc$ls180.v:1257$3599 + assign { } { } + assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] + end + attribute \src "ls180.v:1258.5-1258.38" + process $proc$ls180.v:1258$3600 + assign { } { } + assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] + end + attribute \src "ls180.v:1259.5-1259.37" + process $proc$ls180.v:1259$3601 + assign { } { } + assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] + end + attribute \src "ls180.v:1260.11-1260.53" + process $proc$ls180.v:1260$3602 + assign { } { } + assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] + end + attribute \src "ls180.v:1261.5-1261.40" + process $proc$ls180.v:1261$3603 + assign { } { } + assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] + end + attribute \src "ls180.v:1262.5-1262.40" + process $proc$ls180.v:1262$3604 + assign { } { } + assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] + end + attribute \src "ls180.v:1263.5-1263.39" + process $proc$ls180.v:1263$3605 + assign { } { } + assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] + end + attribute \src "ls180.v:1264.11-1264.53" + process $proc$ls180.v:1264$3606 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] + end + attribute \src "ls180.v:1265.11-1265.55" + process $proc$ls180.v:1265$3607 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] + end + attribute \src "ls180.v:1266.12-1266.48" + process $proc$ls180.v:1266$3608 + assign { } { } + assign $1\main_sdphy_cmdr_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] + end + attribute \src "ls180.v:1267.11-1267.39" + process $proc$ls180.v:1267$3609 + assign { } { } + assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] + end + attribute \src "ls180.v:1269.5-1269.46" + process $proc$ls180.v:1269$3610 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1280.5-1280.53" + process $proc$ls180.v:1280$3611 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1285.5-1285.36" + process $proc$ls180.v:1285$3612 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] + end + attribute \src "ls180.v:1288.5-1288.53" + process $proc$ls180.v:1288$3613 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1289.5-1289.52" + process $proc$ls180.v:1289$3614 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1293.5-1293.55" + process $proc$ls180.v:1293$3615 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + end + attribute \src "ls180.v:1294.5-1294.54" + process $proc$ls180.v:1294$3616 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + end + attribute \src "ls180.v:1295.11-1295.68" + process $proc$ls180.v:1295$3617 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1296.11-1296.81" + process $proc$ls180.v:1296$3618 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1297.11-1297.54" + process $proc$ls180.v:1297$3619 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + end + attribute \src "ls180.v:1299.5-1299.53" + process $proc$ls180.v:1299$3620 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1310.5-1310.49" + process $proc$ls180.v:1310$3621 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1312.5-1312.49" + process $proc$ls180.v:1312$3622 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + end + attribute \src "ls180.v:1313.5-1313.48" + process $proc$ls180.v:1313$3623 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + end + attribute \src "ls180.v:1314.11-1314.62" + process $proc$ls180.v:1314$3624 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1315.5-1315.38" + process $proc$ls180.v:1315$3625 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] + end + attribute \src "ls180.v:1320.5-1320.49" + process $proc$ls180.v:1320$3626 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1321.5-1321.51" + process $proc$ls180.v:1321$3627 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1322.5-1322.52" + process $proc$ls180.v:1322$3628 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1323.11-1323.58" + process $proc$ls180.v:1323$3629 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1324.5-1324.53" + process $proc$ls180.v:1324$3630 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1325.5-1325.39" + process $proc$ls180.v:1325$3631 + assign { } { } + assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] + end + attribute \src "ls180.v:1326.5-1326.39" + process $proc$ls180.v:1326$3632 + assign { } { } + assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] + end + attribute \src "ls180.v:1327.5-1327.39" + process $proc$ls180.v:1327$3633 + assign { } { } + assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] + end + attribute \src "ls180.v:1328.5-1328.38" + process $proc$ls180.v:1328$3634 + assign { } { } + assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] + end + attribute \src "ls180.v:1329.11-1329.52" + process $proc$ls180.v:1329$3635 + assign { } { } + assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1330.5-1330.33" + process $proc$ls180.v:1330$3636 + assign { } { } + assign $1\main_sdphy_dataw_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] + end + attribute \src "ls180.v:1331.11-1331.40" + process $proc$ls180.v:1331$3637 + assign { } { } + assign $1\main_sdphy_dataw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] + end + attribute \src "ls180.v:1332.5-1332.50" + process $proc$ls180.v:1332$3638 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + sync init + end + attribute \src "ls180.v:1334.5-1334.50" + process $proc$ls180.v:1334$3639 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1335.5-1335.49" + process $proc$ls180.v:1335$3640 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1336.5-1336.56" + process $proc$ls180.v:1336$3641 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1337.5-1337.58" + process $proc$ls180.v:1337$3642 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1338.5-1338.58" + process $proc$ls180.v:1338$3643 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1339.5-1339.59" + process $proc$ls180.v:1339$3644 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1340.11-1340.65" + process $proc$ls180.v:1340$3645 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + sync init + end + attribute \src "ls180.v:1341.11-1341.65" + process $proc$ls180.v:1341$3646 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1342.5-1342.60" + process $proc$ls180.v:1342$3647 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1343.5-1343.34" + process $proc$ls180.v:1343$3648 + assign { } { } + assign $1\main_sdphy_dataw_start[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] + end + attribute \src "ls180.v:1344.5-1344.34" + process $proc$ls180.v:1344$3649 + assign { } { } + assign $1\main_sdphy_dataw_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] + end + attribute \src "ls180.v:1345.5-1345.34" + process $proc$ls180.v:1345$3650 + assign { } { } + assign $1\main_sdphy_dataw_error[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] + end + attribute \src "ls180.v:1347.5-1347.47" + process $proc$ls180.v:1347$3651 + assign { } { } + assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1358.5-1358.54" + process $proc$ls180.v:1358$3652 + assign { } { } + assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1363.5-1363.37" + process $proc$ls180.v:1363$3653 + assign { } { } + assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] + end + attribute \src "ls180.v:1366.5-1366.54" + process $proc$ls180.v:1366$3654 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1367.5-1367.53" + process $proc$ls180.v:1367$3655 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1371.5-1371.56" + process $proc$ls180.v:1371$3656 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + end + attribute \src "ls180.v:1372.5-1372.55" + process $proc$ls180.v:1372$3657 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + end + attribute \src "ls180.v:1373.11-1373.69" + process $proc$ls180.v:1373$3658 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1374.11-1374.82" + process $proc$ls180.v:1374$3659 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1375.11-1375.55" + process $proc$ls180.v:1375$3660 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] + end + attribute \src "ls180.v:1377.5-1377.54" + process $proc$ls180.v:1377$3661 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1388.5-1388.50" + process $proc$ls180.v:1388$3662 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1390.5-1390.50" + process $proc$ls180.v:1390$3663 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + end + attribute \src "ls180.v:1391.5-1391.49" + process $proc$ls180.v:1391$3664 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + end + attribute \src "ls180.v:1392.11-1392.63" + process $proc$ls180.v:1392$3665 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1393.5-1393.39" + process $proc$ls180.v:1393$3666 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] + end + attribute \src "ls180.v:1396.5-1396.50" + process $proc$ls180.v:1396$3667 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1397.5-1397.49" + process $proc$ls180.v:1397$3668 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1398.5-1398.56" + process $proc$ls180.v:1398$3669 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1400.5-1400.58" + process $proc$ls180.v:1400$3670 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1401.5-1401.59" + process $proc$ls180.v:1401$3671 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1403.11-1403.65" + process $proc$ls180.v:1403$3672 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1404.5-1404.60" + process $proc$ls180.v:1404$3673 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1406.5-1406.49" + process $proc$ls180.v:1406$3674 + assign { } { } + assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1407.5-1407.51" + process $proc$ls180.v:1407$3675 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1408.5-1408.52" + process $proc$ls180.v:1408$3676 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1409.11-1409.58" + process $proc$ls180.v:1409$3677 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1410.5-1410.53" + process $proc$ls180.v:1410$3678 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1411.5-1411.39" + process $proc$ls180.v:1411$3679 + assign { } { } + assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] + end + attribute \src "ls180.v:1412.5-1412.39" + process $proc$ls180.v:1412$3680 + assign { } { } + assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] + end + attribute \src "ls180.v:1413.5-1413.38" + process $proc$ls180.v:1413$3681 + assign { } { } + assign $1\main_sdphy_datar_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] + end + attribute \src "ls180.v:1414.11-1414.61" + process $proc$ls180.v:1414$3682 + assign { } { } + assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] + end + attribute \src "ls180.v:1415.5-1415.41" + process $proc$ls180.v:1415$3683 + assign { } { } + assign $1\main_sdphy_datar_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] + end + attribute \src "ls180.v:1416.5-1416.41" + process $proc$ls180.v:1416$3684 + assign { } { } + assign $1\main_sdphy_datar_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] + end + attribute \src "ls180.v:1417.5-1417.41" + process $proc$ls180.v:1417$3685 + assign { } { } + assign $0\main_sdphy_datar_source_first[0:0] 1'0 + sync always + update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] + sync init + end + attribute \src "ls180.v:1418.5-1418.40" + process $proc$ls180.v:1418$3686 + assign { } { } + assign $1\main_sdphy_datar_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] + end + attribute \src "ls180.v:1419.11-1419.54" + process $proc$ls180.v:1419$3687 + assign { } { } + assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] + end + attribute \src "ls180.v:1420.11-1420.56" + process $proc$ls180.v:1420$3688 + assign { } { } + assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] + end + attribute \src "ls180.v:1421.5-1421.33" + process $proc$ls180.v:1421$3689 + assign { } { } + assign $1\main_sdphy_datar_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] + end + attribute \src "ls180.v:1422.12-1422.49" + process $proc$ls180.v:1422$3690 + assign { } { } + assign $1\main_sdphy_datar_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] + end + attribute \src "ls180.v:1423.11-1423.41" + process $proc$ls180.v:1423$3691 + assign { } { } + assign $1\main_sdphy_datar_count[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] + end + attribute \src "ls180.v:1425.5-1425.48" + process $proc$ls180.v:1425$3692 + assign { } { } + assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1436.5-1436.55" + process $proc$ls180.v:1436$3693 + assign { } { } + assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] + end + attribute \src "ls180.v:1441.5-1441.38" + process $proc$ls180.v:1441$3694 + assign { } { } + assign $1\main_sdphy_datar_datar_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] + end + attribute \src "ls180.v:1444.5-1444.55" + process $proc$ls180.v:1444$3695 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1445.5-1445.54" + process $proc$ls180.v:1445$3696 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1449.5-1449.57" + process $proc$ls180.v:1449$3697 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] + end + attribute \src "ls180.v:1450.5-1450.56" + process $proc$ls180.v:1450$3698 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] + end + attribute \src "ls180.v:1451.11-1451.70" + process $proc$ls180.v:1451$3699 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1452.11-1452.83" + process $proc$ls180.v:1452$3700 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + end + attribute \src "ls180.v:1453.5-1453.50" + process $proc$ls180.v:1453$3701 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] + end + attribute \src "ls180.v:1455.5-1455.55" + process $proc$ls180.v:1455$3702 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1466.5-1466.51" + process $proc$ls180.v:1466$3703 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] + end + attribute \src "ls180.v:1468.5-1468.51" + process $proc$ls180.v:1468$3704 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] + end + attribute \src "ls180.v:1469.5-1469.50" + process $proc$ls180.v:1469$3705 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] + end + attribute \src "ls180.v:1470.11-1470.64" + process $proc$ls180.v:1470$3706 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1471.5-1471.40" + process $proc$ls180.v:1471$3707 + assign { } { } + assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] + end + attribute \src "ls180.v:1473.5-1473.35" + process $proc$ls180.v:1473$3708 + assign { } { } + assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 + sync always + sync init + update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] + end + attribute \src "ls180.v:1476.11-1476.42" + process $proc$ls180.v:1476$3709 + assign { } { } + assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 + sync always + sync init + update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:1489.12-1489.52" + process $proc$ls180.v:1489$3710 + assign { } { } + assign $1\main_sdcore_cmd_argument_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] + end + attribute \src "ls180.v:1490.5-1490.39" + process $proc$ls180.v:1490$3711 + assign { } { } + assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] + end + attribute \src "ls180.v:1491.12-1491.51" + process $proc$ls180.v:1491$3712 + assign { } { } + assign $1\main_sdcore_cmd_command_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] + end + attribute \src "ls180.v:1492.5-1492.38" + process $proc$ls180.v:1492$3713 + assign { } { } + assign $1\main_sdcore_cmd_command_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] + end + attribute \src "ls180.v:1496.5-1496.34" + process $proc$ls180.v:1496$3714 + assign { } { } + assign $0\main_sdcore_cmd_send_w[0:0] 1'0 + sync always + update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] + sync init + end + attribute \src "ls180.v:1497.13-1497.53" + process $proc$ls180.v:1497$3715 + assign { } { } + assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] + end + attribute \src "ls180.v:1503.11-1503.51" + process $proc$ls180.v:1503$3716 + assign { } { } + assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 + sync always + sync init + update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] + end + attribute \src "ls180.v:1504.5-1504.39" + process $proc$ls180.v:1504$3717 + assign { } { } + assign $1\main_sdcore_block_length_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] + end + attribute \src "ls180.v:1505.12-1505.51" + process $proc$ls180.v:1505$3718 + assign { } { } + assign $1\main_sdcore_block_count_storage[31:0] 0 + sync always + sync init + update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] + end + attribute \src "ls180.v:1506.5-1506.38" + process $proc$ls180.v:1506$3719 + assign { } { } + assign $1\main_sdcore_block_count_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] + end + attribute \src "ls180.v:1507.11-1507.51" + process $proc$ls180.v:1507$3720 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + end + attribute \src "ls180.v:1549.11-1549.47" + process $proc$ls180.v:1549$3721 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:1553.5-1553.49" + process $proc$ls180.v:1553$3722 + assign { } { } + assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] + end + attribute \src "ls180.v:1557.5-1557.51" + process $proc$ls180.v:1557$3723 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] + end + attribute \src "ls180.v:1558.5-1558.51" + process $proc$ls180.v:1558$3724 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] + end + attribute \src "ls180.v:1559.5-1559.51" + process $proc$ls180.v:1559$3725 + assign { } { } + assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] + sync init + end + attribute \src "ls180.v:1560.5-1560.50" + process $proc$ls180.v:1560$3726 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] + end + attribute \src "ls180.v:1561.11-1561.64" + process $proc$ls180.v:1561$3727 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + end + attribute \src "ls180.v:1562.11-1562.48" + process $proc$ls180.v:1562$3728 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] + end + attribute \src "ls180.v:1563.12-1563.59" + process $proc$ls180.v:1563$3729 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1567.12-1567.55" + process $proc$ls180.v:1567$3730 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:1570.12-1570.59" + process $proc$ls180.v:1570$3731 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1574.12-1574.55" + process $proc$ls180.v:1574$3732 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:1577.12-1577.59" + process $proc$ls180.v:1577$3733 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1581.12-1581.55" + process $proc$ls180.v:1581$3734 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:1584.12-1584.59" + process $proc$ls180.v:1584$3735 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1588.12-1588.55" + process $proc$ls180.v:1588$3736 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:1591.12-1591.54" + process $proc$ls180.v:1591$3737 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + end + attribute \src "ls180.v:1592.12-1592.54" + process $proc$ls180.v:1592$3738 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + end + attribute \src "ls180.v:1593.12-1593.54" + process $proc$ls180.v:1593$3739 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + end + attribute \src "ls180.v:1594.12-1594.54" + process $proc$ls180.v:1594$3740 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + end + attribute \src "ls180.v:1595.5-1595.48" + process $proc$ls180.v:1595$3741 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] + end + attribute \src "ls180.v:1596.5-1596.48" + process $proc$ls180.v:1596$3742 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:1597.5-1597.48" + process $proc$ls180.v:1597$3743 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] + end + attribute \src "ls180.v:1598.5-1598.47" + process $proc$ls180.v:1598$3744 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] + end + attribute \src "ls180.v:1599.11-1599.61" + process $proc$ls180.v:1599$3745 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + end + attribute \src "ls180.v:1600.5-1600.50" + process $proc$ls180.v:1600$3746 + assign { } { } + assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:1602.5-1602.50" + process $proc$ls180.v:1602$3747 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] + sync init + end + attribute \src "ls180.v:1605.11-1605.47" + process $proc$ls180.v:1605$3748 + assign { } { } + assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] + end + attribute \src "ls180.v:1606.11-1606.47" + process $proc$ls180.v:1606$3749 + assign { } { } + assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + sync always + sync init + update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] + end + attribute \src "ls180.v:1607.12-1607.58" + process $proc$ls180.v:1607$3750 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1611.12-1611.54" + process $proc$ls180.v:1611$3751 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:1612.5-1612.46" + process $proc$ls180.v:1612$3752 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:1614.12-1614.58" + process $proc$ls180.v:1614$3753 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1618.12-1618.54" + process $proc$ls180.v:1618$3754 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:1619.5-1619.46" + process $proc$ls180.v:1619$3755 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:1621.12-1621.58" + process $proc$ls180.v:1621$3756 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1625.12-1625.54" + process $proc$ls180.v:1625$3757 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:1626.5-1626.46" + process $proc$ls180.v:1626$3758 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:1628.12-1628.58" + process $proc$ls180.v:1628$3759 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1632.12-1632.54" + process $proc$ls180.v:1632$3760 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:1633.5-1633.46" + process $proc$ls180.v:1633$3761 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:1635.12-1635.53" + process $proc$ls180.v:1635$3762 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] + end + attribute \src "ls180.v:1636.12-1636.53" + process $proc$ls180.v:1636$3763 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] + end + attribute \src "ls180.v:1637.12-1637.53" + process $proc$ls180.v:1637$3764 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] + end + attribute \src "ls180.v:1638.12-1638.53" + process $proc$ls180.v:1638$3765 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] + end + attribute \src "ls180.v:1639.5-1639.43" + process $proc$ls180.v:1639$3766 + assign { } { } + assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:1640.12-1640.51" + process $proc$ls180.v:1640$3767 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] + end + attribute \src "ls180.v:1641.12-1641.51" + process $proc$ls180.v:1641$3768 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] + end + attribute \src "ls180.v:1642.12-1642.51" + process $proc$ls180.v:1642$3769 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] + end + attribute \src "ls180.v:1643.12-1643.51" + process $proc$ls180.v:1643$3770 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] + end + attribute \src "ls180.v:1645.11-1645.39" + process $proc$ls180.v:1645$3771 + assign { } { } + assign $1\main_sdcore_cmd_count[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] + end + attribute \src "ls180.v:1646.5-1646.32" + process $proc$ls180.v:1646$3772 + assign { } { } + assign $1\main_sdcore_cmd_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] + end + attribute \src "ls180.v:1647.5-1647.33" + process $proc$ls180.v:1647$3773 + assign { } { } + assign $1\main_sdcore_cmd_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] + end + attribute \src "ls180.v:1648.5-1648.35" + process $proc$ls180.v:1648$3774 + assign { } { } + assign $1\main_sdcore_cmd_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] + end + attribute \src "ls180.v:1650.12-1650.42" + process $proc$ls180.v:1650$3775 + assign { } { } + assign $1\main_sdcore_data_count[31:0] 0 + sync always + sync init + update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] + end + attribute \src "ls180.v:1651.5-1651.33" + process $proc$ls180.v:1651$3776 + assign { } { } + assign $1\main_sdcore_data_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] + end + attribute \src "ls180.v:1652.5-1652.34" + process $proc$ls180.v:1652$3777 + assign { } { } + assign $1\main_sdcore_data_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] + end + attribute \src "ls180.v:1653.5-1653.36" + process $proc$ls180.v:1653$3778 + assign { } { } + assign $1\main_sdcore_data_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] + end + attribute \src "ls180.v:1662.11-1662.41" + process $proc$ls180.v:1662$3779 + assign { } { } + assign $0\main_interface0_bus_cti[2:0] 3'000 + sync always + update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1663.11-1663.41" + process $proc$ls180.v:1663$3780 + assign { } { } + assign $0\main_interface0_bus_bte[1:0] 2'00 + sync always + update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1686.11-1686.45" + process $proc$ls180.v:1686$3781 + assign { } { } + assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] + end + attribute \src "ls180.v:1687.5-1687.41" + process $proc$ls180.v:1687$3782 + assign { } { } + assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 + sync always + update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1688.11-1688.47" + process $proc$ls180.v:1688$3783 + assign { } { } + assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] + end + attribute \src "ls180.v:1689.11-1689.47" + process $proc$ls180.v:1689$3784 + assign { } { } + assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] + end + attribute \src "ls180.v:1690.11-1690.50" + process $proc$ls180.v:1690$3785 + assign { } { } + assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:1710.5-1710.51" + process $proc$ls180.v:1710$3786 + assign { } { } + assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] + end + attribute \src "ls180.v:1711.5-1711.50" + process $proc$ls180.v:1711$3787 + assign { } { } + assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] + end + attribute \src "ls180.v:1712.12-1712.66" + process $proc$ls180.v:1712$3788 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] + end + attribute \src "ls180.v:1713.11-1713.77" + process $proc$ls180.v:1713$3789 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1714.11-1714.50" + process $proc$ls180.v:1714$3790 + assign { } { } + assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] + end + attribute \src "ls180.v:1716.5-1716.49" + process $proc$ls180.v:1716$3791 + assign { } { } + assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1722.5-1722.45" + process $proc$ls180.v:1722$3792 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] + end + attribute \src "ls180.v:1724.12-1724.62" + process $proc$ls180.v:1724$3793 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] + end + attribute \src "ls180.v:1725.12-1725.60" + process $proc$ls180.v:1725$3794 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] + end + attribute \src "ls180.v:1727.5-1727.57" + process $proc$ls180.v:1727$3795 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + end + attribute \src "ls180.v:1731.12-1731.67" + process $proc$ls180.v:1731$3796 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + end + attribute \src "ls180.v:1732.5-1732.54" + process $proc$ls180.v:1732$3797 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + end + attribute \src "ls180.v:1733.12-1733.69" + process $proc$ls180.v:1733$3798 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + end + attribute \src "ls180.v:1734.5-1734.56" + process $proc$ls180.v:1734$3799 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + end + attribute \src "ls180.v:1735.5-1735.61" + process $proc$ls180.v:1735$3800 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + end + attribute \src "ls180.v:1736.5-1736.56" + process $proc$ls180.v:1736$3801 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + end + attribute \src "ls180.v:1737.5-1737.53" + process $proc$ls180.v:1737$3802 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + end + attribute \src "ls180.v:1739.5-1739.59" + process $proc$ls180.v:1739$3803 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + end + attribute \src "ls180.v:1740.5-1740.54" + process $proc$ls180.v:1740$3804 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + end + attribute \src "ls180.v:1742.12-1742.61" + process $proc$ls180.v:1742$3805 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + end + attribute \src "ls180.v:1745.12-1745.43" + process $proc$ls180.v:1745$3806 + assign { } { } + assign $1\main_interface1_bus_adr[31:0] 0 + sync always + sync init + update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] + end + attribute \src "ls180.v:1746.12-1746.45" + process $proc$ls180.v:1746$3807 + assign { } { } + assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] + sync init + end + attribute \src "ls180.v:1748.11-1748.41" + process $proc$ls180.v:1748$3808 + assign { } { } + assign $1\main_interface1_bus_sel[7:0] 8'00000000 + sync always + sync init + update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] + end + attribute \src "ls180.v:1749.5-1749.35" + process $proc$ls180.v:1749$3809 + assign { } { } + assign $1\main_interface1_bus_cyc[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] + end + attribute \src "ls180.v:1750.5-1750.35" + process $proc$ls180.v:1750$3810 + assign { } { } + assign $1\main_interface1_bus_stb[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] + end + attribute \src "ls180.v:1752.5-1752.34" + process $proc$ls180.v:1752$3811 + assign { } { } + assign $1\main_interface1_bus_we[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] + end + attribute \src "ls180.v:1753.11-1753.41" + process $proc$ls180.v:1753$3812 + assign { } { } + assign $0\main_interface1_bus_cti[2:0] 3'000 + sync always + update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1754.11-1754.41" + process $proc$ls180.v:1754$3813 + assign { } { } + assign $0\main_interface1_bus_bte[1:0] 2'00 + sync always + update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1761.5-1761.43" + process $proc$ls180.v:1761$3814 + assign { } { } + assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] + end + attribute \src "ls180.v:1762.5-1762.43" + process $proc$ls180.v:1762$3815 + assign { } { } + assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] + end + attribute \src "ls180.v:1763.5-1763.42" + process $proc$ls180.v:1763$3816 + assign { } { } + assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] + end + attribute \src "ls180.v:1764.12-1764.61" + process $proc$ls180.v:1764$3817 + assign { } { } + assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] + end + attribute \src "ls180.v:1765.5-1765.45" + process $proc$ls180.v:1765$3818 + assign { } { } + assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] + end + attribute \src "ls180.v:1767.5-1767.45" + process $proc$ls180.v:1767$3819 + assign { } { } + assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 + sync always + update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] + sync init + end + attribute \src "ls180.v:1768.5-1768.44" + process $proc$ls180.v:1768$3820 + assign { } { } + assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] + end + attribute \src "ls180.v:1769.12-1769.60" + process $proc$ls180.v:1769$3821 + assign { } { } + assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] + end + attribute \src "ls180.v:1770.12-1770.45" + process $proc$ls180.v:1770$3822 + assign { } { } + assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] + end + attribute \src "ls180.v:1771.12-1771.53" + process $proc$ls180.v:1771$3823 + assign { } { } + assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] + end + attribute \src "ls180.v:1772.5-1772.40" + process $proc$ls180.v:1772$3824 + assign { } { } + assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] + end + attribute \src "ls180.v:1773.12-1773.55" + process $proc$ls180.v:1773$3825 + assign { } { } + assign $1\main_sdmem2block_dma_length_storage[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] + end + attribute \src "ls180.v:1774.5-1774.42" + process $proc$ls180.v:1774$3826 + assign { } { } + assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] + end + attribute \src "ls180.v:1775.5-1775.47" + process $proc$ls180.v:1775$3827 + assign { } { } + assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] + end + attribute \src "ls180.v:1776.5-1776.42" + process $proc$ls180.v:1776$3828 + assign { } { } + assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] + end + attribute \src "ls180.v:1777.5-1777.44" + process $proc$ls180.v:1777$3829 + assign { } { } + assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] + end + attribute \src "ls180.v:1779.5-1779.45" + process $proc$ls180.v:1779$3830 + assign { } { } + assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] + end + attribute \src "ls180.v:1780.5-1780.40" + process $proc$ls180.v:1780$3831 + assign { } { } + assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] + end + attribute \src "ls180.v:1784.12-1784.47" + process $proc$ls180.v:1784$3832 + assign { } { } + assign $1\main_sdmem2block_dma_offset[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] + end + attribute \src "ls180.v:1796.11-1796.64" + process $proc$ls180.v:1796$3833 + assign { } { } + assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1798.11-1798.48" + process $proc$ls180.v:1798$3834 + assign { } { } + assign $1\main_sdmem2block_converter_mux[2:0] 3'000 + sync always + sync init + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] + end + attribute \src "ls180.v:1822.11-1822.45" + process $proc$ls180.v:1822$3835 + assign { } { } + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + end + attribute \src "ls180.v:1823.5-1823.41" + process $proc$ls180.v:1823$3836 + assign { } { } + assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 + sync always + update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1824.11-1824.47" + process $proc$ls180.v:1824$3837 + assign { } { } + assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] + end + attribute \src "ls180.v:1825.11-1825.47" + process $proc$ls180.v:1825$3838 + assign { } { } + assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] + end + attribute \src "ls180.v:1826.11-1826.50" + process $proc$ls180.v:1826$3839 + assign { } { } + assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:1839.5-1839.36" + process $proc$ls180.v:1839$3840 + assign { } { } + assign $1\builder_converter0_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_state $1\builder_converter0_state[0:0] + end + attribute \src "ls180.v:1840.5-1840.41" + process $proc$ls180.v:1840$3841 + assign { } { } + assign $1\builder_converter0_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] + end + attribute \src "ls180.v:1841.5-1841.57" + process $proc$ls180.v:1841$3842 + assign { } { } + assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 + sync always + sync init + update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] + end + attribute \src "ls180.v:1842.5-1842.60" + process $proc$ls180.v:1842$3843 + assign { } { } + assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:1843.5-1843.36" + process $proc$ls180.v:1843$3844 + assign { } { } + assign $1\builder_converter1_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_state $1\builder_converter1_state[0:0] + end + attribute \src "ls180.v:1844.5-1844.41" + process $proc$ls180.v:1844$3845 + assign { } { } + assign $1\builder_converter1_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] + end + attribute \src "ls180.v:1845.5-1845.57" + process $proc$ls180.v:1845$3846 + assign { } { } + assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 + sync always + sync init + update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] + end + attribute \src "ls180.v:1846.5-1846.60" + process $proc$ls180.v:1846$3847 + assign { } { } + assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:1847.5-1847.36" + process $proc$ls180.v:1847$3848 + assign { } { } + assign $1\builder_converter2_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_state $1\builder_converter2_state[0:0] + end + attribute \src "ls180.v:1848.5-1848.41" + process $proc$ls180.v:1848$3849 + assign { } { } + assign $1\builder_converter2_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] + end + attribute \src "ls180.v:1849.5-1849.60" + process $proc$ls180.v:1849$3850 + assign { } { } + assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] + end + attribute \src "ls180.v:1850.5-1850.63" + process $proc$ls180.v:1850$3851 + assign { } { } + assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:1851.11-1851.41" + process $proc$ls180.v:1851$3852 + assign { } { } + assign $1\builder_refresher_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_state $1\builder_refresher_state[1:0] + end + attribute \src "ls180.v:1852.11-1852.46" + process $proc$ls180.v:1852$3853 + assign { } { } + assign $1\builder_refresher_next_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:1853.11-1853.44" + process $proc$ls180.v:1853$3854 + assign { } { } + assign $1\builder_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] + end + attribute \src "ls180.v:1854.11-1854.49" + process $proc$ls180.v:1854$3855 + assign { } { } + assign $1\builder_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:1855.11-1855.44" + process $proc$ls180.v:1855$3856 + assign { } { } + assign $1\builder_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] + end + attribute \src "ls180.v:1856.11-1856.49" + process $proc$ls180.v:1856$3857 + assign { } { } + assign $1\builder_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:1857.11-1857.44" + process $proc$ls180.v:1857$3858 + assign { } { } + assign $1\builder_bankmachine2_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] + end + attribute \src "ls180.v:1858.11-1858.49" + process $proc$ls180.v:1858$3859 + assign { } { } + assign $1\builder_bankmachine2_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:1859.11-1859.44" + process $proc$ls180.v:1859$3860 + assign { } { } + assign $1\builder_bankmachine3_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] + end + attribute \src "ls180.v:1860.11-1860.49" + process $proc$ls180.v:1860$3861 + assign { } { } + assign $1\builder_bankmachine3_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:1861.11-1861.43" + process $proc$ls180.v:1861$3862 + assign { } { } + assign $1\builder_multiplexer_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] + end + attribute \src "ls180.v:1862.11-1862.48" + process $proc$ls180.v:1862$3863 + assign { } { } + assign $1\builder_multiplexer_next_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:1875.5-1875.27" + process $proc$ls180.v:1875$3864 + assign { } { } + assign $0\builder_locked0[0:0] 1'0 + sync always + update \builder_locked0 $0\builder_locked0[0:0] + sync init + end + attribute \src "ls180.v:1876.5-1876.27" + process $proc$ls180.v:1876$3865 + assign { } { } + assign $0\builder_locked1[0:0] 1'0 + sync always + update \builder_locked1 $0\builder_locked1[0:0] + sync init + end + attribute \src "ls180.v:1877.5-1877.27" + process $proc$ls180.v:1877$3866 + assign { } { } + assign $0\builder_locked2[0:0] 1'0 + sync always + update \builder_locked2 $0\builder_locked2[0:0] + sync init + end + attribute \src "ls180.v:1878.5-1878.27" + process $proc$ls180.v:1878$3867 + assign { } { } + assign $0\builder_locked3[0:0] 1'0 + sync always + update \builder_locked3 $0\builder_locked3[0:0] + sync init + end + attribute \src "ls180.v:1879.5-1879.42" + process $proc$ls180.v:1879$3868 + assign { } { } + assign $1\builder_new_master_wdata_ready[0:0] 1'0 + sync always + sync init + update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] + end + attribute \src "ls180.v:1880.5-1880.43" + process $proc$ls180.v:1880$3869 + assign { } { } + assign $1\builder_new_master_rdata_valid0[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] + end + attribute \src "ls180.v:1881.5-1881.43" + process $proc$ls180.v:1881$3870 + assign { } { } + assign $1\builder_new_master_rdata_valid1[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] + end + attribute \src "ls180.v:1882.5-1882.43" + process $proc$ls180.v:1882$3871 + assign { } { } + assign $1\builder_new_master_rdata_valid2[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] + end + attribute \src "ls180.v:1883.5-1883.43" + process $proc$ls180.v:1883$3872 + assign { } { } + assign $1\builder_new_master_rdata_valid3[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] + end + attribute \src "ls180.v:1884.5-1884.35" + process $proc$ls180.v:1884$3873 + assign { } { } + assign $1\builder_converter_state[0:0] 1'0 + sync always + sync init + update \builder_converter_state $1\builder_converter_state[0:0] + end + attribute \src "ls180.v:1885.5-1885.40" + process $proc$ls180.v:1885$3874 + assign { } { } + assign $1\builder_converter_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter_next_state $1\builder_converter_next_state[0:0] + end + attribute \src "ls180.v:1886.5-1886.55" + process $proc$ls180.v:1886$3875 + assign { } { } + assign $1\main_converter_counter_converter_next_value[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] + end + attribute \src "ls180.v:1887.5-1887.58" + process $proc$ls180.v:1887$3876 + assign { } { } + assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:1888.11-1888.42" + process $proc$ls180.v:1888$3877 + assign { } { } + assign $1\builder_spimaster0_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] + end + attribute \src "ls180.v:1889.11-1889.47" + process $proc$ls180.v:1889$3878 + assign { } { } + assign $1\builder_spimaster0_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] + end + attribute \src "ls180.v:1890.11-1890.62" + process $proc$ls180.v:1890$3879 + assign { } { } + assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] + end + attribute \src "ls180.v:1891.5-1891.59" + process $proc$ls180.v:1891$3880 + assign { } { } + assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:1892.11-1892.42" + process $proc$ls180.v:1892$3881 + assign { } { } + assign $1\builder_spimaster1_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] + end + attribute \src "ls180.v:1893.11-1893.47" + process $proc$ls180.v:1893$3882 + assign { } { } + assign $1\builder_spimaster1_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] + end + attribute \src "ls180.v:1894.11-1894.60" + process $proc$ls180.v:1894$3883 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] + end + attribute \src "ls180.v:1895.5-1895.57" + process $proc$ls180.v:1895$3884 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:1896.5-1896.41" + process $proc$ls180.v:1896$3885 + assign { } { } + assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] + end + attribute \src "ls180.v:1897.5-1897.46" + process $proc$ls180.v:1897$3886 + assign { } { } + assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] + end + attribute \src "ls180.v:1898.11-1898.66" + process $proc$ls180.v:1898$3887 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + end + attribute \src "ls180.v:1899.5-1899.63" + process $proc$ls180.v:1899$3888 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:1900.11-1900.47" + process $proc$ls180.v:1900$3889 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] + end + attribute \src "ls180.v:1901.11-1901.52" + process $proc$ls180.v:1901$3890 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] + end + attribute \src "ls180.v:1902.11-1902.66" + process $proc$ls180.v:1902$3891 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + end + attribute \src "ls180.v:1903.5-1903.63" + process $proc$ls180.v:1903$3892 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:1904.11-1904.47" + process $proc$ls180.v:1904$3893 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] + end + attribute \src "ls180.v:1905.11-1905.52" + process $proc$ls180.v:1905$3894 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] + end + attribute \src "ls180.v:1906.11-1906.67" + process $proc$ls180.v:1906$3895 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + end + attribute \src "ls180.v:1907.5-1907.64" + process $proc$ls180.v:1907$3896 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + end + attribute \src "ls180.v:1908.12-1908.71" + process $proc$ls180.v:1908$3897 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + end + attribute \src "ls180.v:1909.5-1909.66" + process $proc$ls180.v:1909$3898 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + end + attribute \src "ls180.v:1910.5-1910.66" + process $proc$ls180.v:1910$3899 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + end + attribute \src "ls180.v:1911.5-1911.69" + process $proc$ls180.v:1911$3900 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:1912.5-1912.41" + process $proc$ls180.v:1912$3901 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] + end + attribute \src "ls180.v:1913.5-1913.46" + process $proc$ls180.v:1913$3902 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] + end + attribute \src "ls180.v:1914.5-1914.66" + process $proc$ls180.v:1914$3903 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + end + attribute \src "ls180.v:1915.5-1915.69" + process $proc$ls180.v:1915$3904 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:1916.11-1916.41" + process $proc$ls180.v:1916$3905 + assign { } { } + assign $1\builder_sdphy_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] + end + attribute \src "ls180.v:1917.11-1917.46" + process $proc$ls180.v:1917$3906 + assign { } { } + assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] + end + attribute \src "ls180.v:1918.11-1918.61" + process $proc$ls180.v:1918$3907 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + end + attribute \src "ls180.v:1919.5-1919.58" + process $proc$ls180.v:1919$3908 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1920.11-1920.48" + process $proc$ls180.v:1920$3909 + assign { } { } + assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] + end + attribute \src "ls180.v:1921.11-1921.53" + process $proc$ls180.v:1921$3910 + assign { } { } + assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] + end + attribute \src "ls180.v:1922.11-1922.70" + process $proc$ls180.v:1922$3911 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + end + attribute \src "ls180.v:1923.5-1923.66" + process $proc$ls180.v:1923$3912 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + end + attribute \src "ls180.v:1924.12-1924.73" + process $proc$ls180.v:1924$3913 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + end + attribute \src "ls180.v:1925.5-1925.68" + process $proc$ls180.v:1925$3914 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + end + attribute \src "ls180.v:1926.5-1926.69" + process $proc$ls180.v:1926$3915 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + end + attribute \src "ls180.v:1927.5-1927.72" + process $proc$ls180.v:1927$3916 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:1928.5-1928.52" + process $proc$ls180.v:1928$3917 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] + end + attribute \src "ls180.v:1929.5-1929.57" + process $proc$ls180.v:1929$3918 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + end + attribute \src "ls180.v:1930.12-1930.93" + process $proc$ls180.v:1930$3919 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + end + attribute \src "ls180.v:1931.5-1931.88" + process $proc$ls180.v:1931$3920 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + end + attribute \src "ls180.v:1932.12-1932.93" + process $proc$ls180.v:1932$3921 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + end + attribute \src "ls180.v:1933.5-1933.88" + process $proc$ls180.v:1933$3922 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + end + attribute \src "ls180.v:1934.12-1934.93" + process $proc$ls180.v:1934$3923 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + end + attribute \src "ls180.v:1935.5-1935.88" + process $proc$ls180.v:1935$3924 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + end + attribute \src "ls180.v:1936.12-1936.93" + process $proc$ls180.v:1936$3925 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + end + attribute \src "ls180.v:1937.5-1937.88" + process $proc$ls180.v:1937$3926 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + end + attribute \src "ls180.v:1938.11-1938.87" + process $proc$ls180.v:1938$3927 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + end + attribute \src "ls180.v:1939.5-1939.84" + process $proc$ls180.v:1939$3928 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:1940.11-1940.42" + process $proc$ls180.v:1940$3929 + assign { } { } + assign $1\builder_sdcore_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] + end + attribute \src "ls180.v:1941.11-1941.47" + process $proc$ls180.v:1941$3930 + assign { } { } + assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] + end + attribute \src "ls180.v:1942.5-1942.55" + process $proc$ls180.v:1942$3931 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + end + attribute \src "ls180.v:1943.5-1943.58" + process $proc$ls180.v:1943$3932 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + end + attribute \src "ls180.v:1944.5-1944.56" + process $proc$ls180.v:1944$3933 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + end + attribute \src "ls180.v:1945.5-1945.59" + process $proc$ls180.v:1945$3934 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + end + attribute \src "ls180.v:1946.11-1946.62" + process $proc$ls180.v:1946$3935 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + end + attribute \src "ls180.v:1947.5-1947.59" + process $proc$ls180.v:1947$3936 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + end + attribute \src "ls180.v:1948.12-1948.65" + process $proc$ls180.v:1948$3937 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + end + attribute \src "ls180.v:1949.5-1949.60" + process $proc$ls180.v:1949$3938 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + end + attribute \src "ls180.v:1950.5-1950.56" + process $proc$ls180.v:1950$3939 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + end + attribute \src "ls180.v:1951.5-1951.59" + process $proc$ls180.v:1951$3940 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + end + attribute \src "ls180.v:1952.5-1952.58" + process $proc$ls180.v:1952$3941 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + end + attribute \src "ls180.v:1953.5-1953.61" + process $proc$ls180.v:1953$3942 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + end + attribute \src "ls180.v:1954.5-1954.57" + process $proc$ls180.v:1954$3943 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + end + attribute \src "ls180.v:1955.5-1955.60" + process $proc$ls180.v:1955$3944 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + end + attribute \src "ls180.v:1956.5-1956.59" + process $proc$ls180.v:1956$3945 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + end + attribute \src "ls180.v:1957.5-1957.62" + process $proc$ls180.v:1957$3946 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + end + attribute \src "ls180.v:1958.13-1958.76" + process $proc$ls180.v:1958$3947 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + end + attribute \src "ls180.v:1959.5-1959.69" + process $proc$ls180.v:1959$3948 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:1960.11-1960.46" + process $proc$ls180.v:1960$3949 + assign { } { } + assign $1\builder_sdblock2memdma_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] + end + attribute \src "ls180.v:1961.11-1961.51" + process $proc$ls180.v:1961$3950 + assign { } { } + assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] + end + attribute \src "ls180.v:1962.12-1962.87" + process $proc$ls180.v:1962$3951 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + end + attribute \src "ls180.v:1963.5-1963.82" + process $proc$ls180.v:1963$3952 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:1964.5-1964.44" + process $proc$ls180.v:1964$3953 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] + end + attribute \src "ls180.v:1965.5-1965.49" + process $proc$ls180.v:1965$3954 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] + end + attribute \src "ls180.v:1966.12-1966.75" + process $proc$ls180.v:1966$3955 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + end + attribute \src "ls180.v:1967.5-1967.70" + process $proc$ls180.v:1967$3956 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1968.11-1968.60" + process $proc$ls180.v:1968$3957 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] + end + attribute \src "ls180.v:1969.11-1969.65" + process $proc$ls180.v:1969$3958 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + end + attribute \src "ls180.v:1970.12-1970.87" + process $proc$ls180.v:1970$3959 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + end + attribute \src "ls180.v:1971.5-1971.82" + process $proc$ls180.v:1971$3960 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:1972.12-1972.43" + process $proc$ls180.v:1972$3961 + assign { } { } + assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] + end + attribute \src "ls180.v:1973.5-1973.34" + process $proc$ls180.v:1973$3962 + assign { } { } + assign $1\builder_libresocsim_we[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] + end + attribute \src "ls180.v:1974.11-1974.43" + process $proc$ls180.v:1974$3963 + assign { } { } + assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] + end + attribute \src "ls180.v:1976.12-1976.52" + process $proc$ls180.v:1976$3964 + assign { } { } + assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 + sync always + update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] + sync init + end + attribute \src "ls180.v:1977.12-1977.54" + process $proc$ls180.v:1977$3965 + assign { } { } + assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 + sync always + update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] + sync init + end + attribute \src "ls180.v:1978.12-1978.54" + process $proc$ls180.v:1978$3966 + assign { } { } + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + sync always + sync init + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] + end + attribute \src "ls180.v:1979.11-1979.50" + process $proc$ls180.v:1979$3967 + assign { } { } + assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 + sync always + update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] + sync init + end + attribute \src "ls180.v:1980.5-1980.44" + process $proc$ls180.v:1980$3968 + assign { } { } + assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] + sync init + end + attribute \src "ls180.v:1981.5-1981.44" + process $proc$ls180.v:1981$3969 + assign { } { } + assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] + sync init + end + attribute \src "ls180.v:1982.5-1982.44" + process $proc$ls180.v:1982$3970 + assign { } { } + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] + end + attribute \src "ls180.v:1983.5-1983.43" + process $proc$ls180.v:1983$3971 + assign { } { } + assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] + sync init + end + attribute \src "ls180.v:1986.12-1986.65" + process $proc$ls180.v:1986$3972 + assign { } { } + assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] + sync init + end + attribute \src "ls180.v:1990.5-1990.55" + process $proc$ls180.v:1990$3973 + assign { } { } + assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 + sync always + update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] + sync init + end + attribute \src "ls180.v:1994.5-1994.55" + process $proc$ls180.v:1994$3974 + assign { } { } + assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 + sync always + update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:1997.12-1997.40" + process $proc$ls180.v:1997$3975 + assign { } { } + assign $1\builder_shared_dat_r[31:0] 0 + sync always + sync init + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] + end + attribute \src "ls180.v:2001.5-2001.30" + process $proc$ls180.v:2001$3976 + assign { } { } + assign $1\builder_shared_ack[0:0] 1'0 + sync always + sync init + update \builder_shared_ack $1\builder_shared_ack[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:149368$7140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:149368$7140_Y + attribute \src "ls180.v:2007.11-2007.31" + process $proc$ls180.v:2007$3977 + assign { } { } + assign $1\builder_grant[2:0] 3'000 + sync always + sync init + update \builder_grant $1\builder_grant[2:0] + end + attribute \src "ls180.v:2008.12-2008.37" + process $proc$ls180.v:2008$3978 + assign { } { } + assign $1\builder_slave_sel[12:0] 13'0000000000000 + sync always + sync init + update \builder_slave_sel $1\builder_slave_sel[12:0] + end + attribute \src "ls180.v:2009.12-2009.39" + process $proc$ls180.v:2009$3979 + assign { } { } + assign $1\builder_slave_sel_r[12:0] 13'0000000000000 + sync always + sync init + update \builder_slave_sel_r $1\builder_slave_sel_r[12:0] + end + attribute \src "ls180.v:2010.5-2010.25" + process $proc$ls180.v:2010$3980 + assign { } { } + assign $1\builder_error[0:0] 1'0 + sync always + sync init + update \builder_error $1\builder_error[0:0] + end + attribute \src "ls180.v:2013.12-2013.39" + process $proc$ls180.v:2013$3981 + assign { } { } + assign $1\builder_count[19:0] 20'11110100001001000000 + sync always + sync init + update \builder_count $1\builder_count[19:0] + end + attribute \src "ls180.v:2017.11-2017.51" + process $proc$ls180.v:2017$3982 + assign { } { } + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2058.11-2058.51" + process $proc$ls180.v:2058$3983 + assign { } { } + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2087.11-2087.51" + process $proc$ls180.v:2087$3984 + assign { } { } + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:210.5-210.40" + process $proc$ls180.v:210$3150 + assign { } { } + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2100.11-2100.51" + process $proc$ls180.v:2100$3985 + assign { } { } + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:214.5-214.40" + process $proc$ls180.v:214$3151 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:2141.11-2141.51" + process $proc$ls180.v:2141$3986 + assign { } { } + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:217.11-217.37" + process $proc$ls180.v:217$3152 + assign { } { } + assign $1\main_libresocsim_we[7:0] 8'00000000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[7:0] + end + attribute \src "ls180.v:2182.11-2182.51" + process $proc$ls180.v:2182$3987 + assign { } { } + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:219.12-219.49" + process $proc$ls180.v:219$3153 + assign { } { } + assign $1\main_libresocsim_load_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + end + attribute \src "ls180.v:220.5-220.36" + process $proc$ls180.v:220$3154 + assign { } { } + assign $1\main_libresocsim_load_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + end + attribute \src "ls180.v:221.12-221.51" + process $proc$ls180.v:221$3155 + assign { } { } + assign $1\main_libresocsim_reload_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] + end + attribute \src "ls180.v:222.5-222.38" + process $proc$ls180.v:222$3156 + assign { } { } + assign $1\main_libresocsim_reload_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] + end + attribute \src "ls180.v:223.5-223.39" + process $proc$ls180.v:223$3157 + assign { } { } + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:224.5-224.34" + process $proc$ls180.v:224$3158 + assign { } { } + assign $1\main_libresocsim_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:2247.11-2247.51" + process $proc$ls180.v:2247$3988 + assign { } { } + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:225.5-225.49" + process $proc$ls180.v:225$3159 + assign { } { } + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] + end + attribute \src "ls180.v:226.5-226.44" + process $proc$ls180.v:226$3160 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:227.12-227.49" + process $proc$ls180.v:227$3161 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:231.5-231.41" + process $proc$ls180.v:231$3162 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:233.5-233.39" + process $proc$ls180.v:233$3163 + assign { } { } + assign $1\main_libresocsim_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:234.5-234.45" + process $proc$ls180.v:234$3164 + assign { } { } + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:2380.11-2380.51" + process $proc$ls180.v:2380$3989 + assign { } { } + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:243.5-243.49" + process $proc$ls180.v:243$3165 + assign { } { } + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + end + attribute \src "ls180.v:244.5-244.44" + process $proc$ls180.v:244$3166 + assign { } { } + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + end + attribute \src "ls180.v:245.12-245.42" + process $proc$ls180.v:245$3167 + assign { } { } + assign $1\main_libresocsim_value[31:0] 0 + sync always + sync init + update \main_libresocsim_value $1\main_libresocsim_value[31:0] + end + attribute \src "ls180.v:2461.11-2461.51" + process $proc$ls180.v:2461$3990 + assign { } { } + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2478.11-2478.51" + process $proc$ls180.v:2478$3991 + assign { } { } + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2519.11-2519.52" + process $proc$ls180.v:2519$3992 + assign { } { } + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:252.5-252.39" + process $proc$ls180.v:252$3168 + assign { } { } + assign $1\main_interface0_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2552.11-2552.52" + process $proc$ls180.v:2552$3993 + assign { } { } + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:256.5-256.39" + process $proc$ls180.v:256$3169 + assign { } { } + assign $0\main_interface0_ram_bus_err[0:0] 1'0 + sync always + update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:259.11-259.31" + process $proc$ls180.v:259$3170 + assign { } { } + assign $1\main_sram0_we[7:0] 8'00000000 + sync always + sync init + update \main_sram0_we $1\main_sram0_we[7:0] + end + attribute \src "ls180.v:2593.11-2593.52" + process $proc$ls180.v:2593$3994 + assign { } { } + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2658.11-2658.52" + process $proc$ls180.v:2658$3995 + assign { } { } + assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:267.5-267.39" + process $proc$ls180.v:267$3171 + assign { } { } + assign $1\main_interface1_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2683.11-2683.52" + process $proc$ls180.v:2683$3996 + assign { } { } + assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2705.11-2705.31" + process $proc$ls180.v:2705$3997 + assign { } { } + assign $1\builder_state[1:0] 2'00 + sync always + sync init + update \builder_state $1\builder_state[1:0] + end + attribute \src "ls180.v:2706.11-2706.36" + process $proc$ls180.v:2706$3998 + assign { } { } + assign $1\builder_next_state[1:0] 2'00 + sync always + sync init + update \builder_next_state $1\builder_next_state[1:0] + end + attribute \src "ls180.v:2707.11-2707.55" + process $proc$ls180.v:2707$3999 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] + end + attribute \src "ls180.v:2708.5-2708.52" + process $proc$ls180.v:2708$4000 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + end + attribute \src "ls180.v:2709.12-2709.55" + process $proc$ls180.v:2709$4001 + assign { } { } + assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] + end + attribute \src "ls180.v:271.5-271.39" + process $proc$ls180.v:271$3172 + assign { } { } + assign $0\main_interface1_ram_bus_err[0:0] 1'0 + sync always + update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:2710.5-2710.50" + process $proc$ls180.v:2710$4002 + assign { } { } + assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] + end + attribute \src "ls180.v:2711.5-2711.46" + process $proc$ls180.v:2711$4003 + assign { } { } + assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] + end + attribute \src "ls180.v:2712.5-2712.49" + process $proc$ls180.v:2712$4004 + assign { } { } + assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:2713.5-2713.41" + process $proc$ls180.v:2713$4005 + assign { } { } + assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:2714.12-2714.49" + process $proc$ls180.v:2714$4006 + assign { } { } + assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2715.11-2715.47" + process $proc$ls180.v:2715$4007 + assign { } { } + assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:2716.5-2716.41" + process $proc$ls180.v:2716$4008 + assign { } { } + assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2717.5-2717.41" + process $proc$ls180.v:2717$4009 + assign { } { } + assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2718.5-2718.41" + process $proc$ls180.v:2718$4010 + assign { } { } + assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2719.5-2719.39" + process $proc$ls180.v:2719$4011 + assign { } { } + assign $1\builder_comb_t_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:2720.5-2720.39" + process $proc$ls180.v:2720$4012 + assign { } { } + assign $1\builder_comb_t_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:2721.5-2721.39" + process $proc$ls180.v:2721$4013 + assign { } { } + assign $1\builder_comb_t_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:2722.5-2722.41" + process $proc$ls180.v:2722$4014 + assign { } { } + assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2723.12-2723.49" + process $proc$ls180.v:2723$4015 + assign { } { } + assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:2724.11-2724.47" + process $proc$ls180.v:2724$4016 + assign { } { } + assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:2725.5-2725.41" + process $proc$ls180.v:2725$4017 + assign { } { } + assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:2726.5-2726.42" + process $proc$ls180.v:2726$4018 + assign { } { } + assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:2727.5-2727.42" + process $proc$ls180.v:2727$4019 + assign { } { } + assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:2728.5-2728.39" + process $proc$ls180.v:2728$4020 + assign { } { } + assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:2729.5-2729.39" + process $proc$ls180.v:2729$4021 + assign { } { } + assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:2730.5-2730.39" + process $proc$ls180.v:2730$4022 + assign { } { } + assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:2731.12-2731.50" + process $proc$ls180.v:2731$4023 + assign { } { } + assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:2732.5-2732.42" + process $proc$ls180.v:2732$4024 + assign { } { } + assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:2733.5-2733.42" + process $proc$ls180.v:2733$4025 + assign { } { } + assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:2734.12-2734.50" + process $proc$ls180.v:2734$4026 + assign { } { } + assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:2735.5-2735.42" + process $proc$ls180.v:2735$4027 + assign { } { } + assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:2736.5-2736.42" + process $proc$ls180.v:2736$4028 + assign { } { } + assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:2737.12-2737.50" + process $proc$ls180.v:2737$4029 + assign { } { } + assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:2738.5-2738.42" + process $proc$ls180.v:2738$4030 + assign { } { } + assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:2739.5-2739.42" + process $proc$ls180.v:2739$4031 + assign { } { } + assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:274.11-274.31" + process $proc$ls180.v:274$3173 + assign { } { } + assign $1\main_sram1_we[7:0] 8'00000000 + sync always + sync init + update \main_sram1_we $1\main_sram1_we[7:0] + end + attribute \src "ls180.v:2740.12-2740.50" + process $proc$ls180.v:2740$4032 + assign { } { } + assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:2741.5-2741.42" + process $proc$ls180.v:2741$4033 + assign { } { } + assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:2742.5-2742.42" + process $proc$ls180.v:2742$4034 + assign { } { } + assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:2743.12-2743.50" + process $proc$ls180.v:2743$4035 + assign { } { } + assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:2744.12-2744.50" + process $proc$ls180.v:2744$4036 + assign { } { } + assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] + end + attribute \src "ls180.v:2745.11-2745.48" + process $proc$ls180.v:2745$4037 + assign { } { } + assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + sync always + sync init + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] + end + attribute \src "ls180.v:2746.5-2746.42" + process $proc$ls180.v:2746$4038 + assign { } { } + assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:2747.5-2747.42" + process $proc$ls180.v:2747$4039 + assign { } { } + assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:2748.5-2748.42" + process $proc$ls180.v:2748$4040 + assign { } { } + assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:2749.11-2749.48" + process $proc$ls180.v:2749$4041 + assign { } { } + assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + sync always + sync init + update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:2750.11-2750.48" + process $proc$ls180.v:2750$4042 + assign { } { } + assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:2751.11-2751.47" + process $proc$ls180.v:2751$4043 + assign { } { } + assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + sync always + sync init + update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:2752.12-2752.49" + process $proc$ls180.v:2752$4044 + assign { } { } + assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2753.5-2753.41" + process $proc$ls180.v:2753$4045 + assign { } { } + assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:2754.5-2754.41" + process $proc$ls180.v:2754$4046 + assign { } { } + assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2755.5-2755.41" + process $proc$ls180.v:2755$4047 + assign { } { } + assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2756.5-2756.41" + process $proc$ls180.v:2756$4048 + assign { } { } + assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2757.5-2757.41" + process $proc$ls180.v:2757$4049 + assign { } { } + assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2758.5-2758.39" + process $proc$ls180.v:2758$4050 + assign { } { } + assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:2759.5-2759.39" + process $proc$ls180.v:2759$4051 + assign { } { } + assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:2816.32-2816.66" + process $proc$ls180.v:2816$4052 + assign { } { } + assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + end + attribute \src "ls180.v:2817.32-2817.66" + process $proc$ls180.v:2817$4053 + assign { } { } + assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + end + attribute \src "ls180.v:2818.32-2818.66" + process $proc$ls180.v:2818$4054 + assign { } { } + assign $1\builder_multiregimpl1_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] + end + attribute \src "ls180.v:2819.32-2819.66" + process $proc$ls180.v:2819$4055 + assign { } { } + assign $1\builder_multiregimpl1_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] + end + attribute \src "ls180.v:282.5-282.39" + process $proc$ls180.v:282$3174 + assign { } { } + assign $1\main_interface2_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2820.32-2820.66" + process $proc$ls180.v:2820$4056 + assign { } { } + assign $1\builder_multiregimpl2_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] + end + attribute \src "ls180.v:2821.32-2821.66" + process $proc$ls180.v:2821$4057 + assign { } { } + assign $1\builder_multiregimpl2_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] + end + attribute \src "ls180.v:2822.32-2822.66" + process $proc$ls180.v:2822$4058 + assign { } { } + assign $1\builder_multiregimpl3_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] + end + attribute \src "ls180.v:2823.32-2823.66" + process $proc$ls180.v:2823$4059 + assign { } { } + assign $1\builder_multiregimpl3_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] + end + attribute \src "ls180.v:2824.32-2824.66" + process $proc$ls180.v:2824$4060 + assign { } { } + assign $1\builder_multiregimpl4_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] + end + attribute \src "ls180.v:2825.32-2825.66" + process $proc$ls180.v:2825$4061 + assign { } { } + assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + end + attribute \src "ls180.v:2826.32-2826.66" + process $proc$ls180.v:2826$4062 + assign { } { } + assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + end + attribute \src "ls180.v:2827.32-2827.66" + process $proc$ls180.v:2827$4063 + assign { } { } + assign $1\builder_multiregimpl5_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] + end + attribute \src "ls180.v:2828.32-2828.66" + process $proc$ls180.v:2828$4064 + assign { } { } + assign $1\builder_multiregimpl6_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] + end + attribute \src "ls180.v:2829.32-2829.66" + process $proc$ls180.v:2829$4065 + assign { } { } + assign $1\builder_multiregimpl6_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] + end + attribute \src "ls180.v:2830.32-2830.66" + process $proc$ls180.v:2830$4066 + assign { } { } + assign $1\builder_multiregimpl7_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] + end + attribute \src "ls180.v:2831.32-2831.66" + process $proc$ls180.v:2831$4067 + assign { } { } + assign $1\builder_multiregimpl7_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] + end + attribute \src "ls180.v:2832.32-2832.66" + process $proc$ls180.v:2832$4068 + assign { } { } + assign $1\builder_multiregimpl8_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] + end + attribute \src "ls180.v:2833.32-2833.66" + process $proc$ls180.v:2833$4069 + assign { } { } + assign $1\builder_multiregimpl8_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] + end + attribute \src "ls180.v:2834.32-2834.66" + process $proc$ls180.v:2834$4070 + assign { } { } + assign $1\builder_multiregimpl9_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] + end + attribute \src "ls180.v:2835.32-2835.66" + process $proc$ls180.v:2835$4071 + assign { } { } + assign $1\builder_multiregimpl9_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] + end + attribute \src "ls180.v:2836.32-2836.67" + process $proc$ls180.v:2836$4072 + assign { } { } + assign $1\builder_multiregimpl10_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] + end + attribute \src "ls180.v:2837.32-2837.67" + process $proc$ls180.v:2837$4073 + assign { } { } + assign $1\builder_multiregimpl10_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] + end + attribute \src "ls180.v:2838.32-2838.67" + process $proc$ls180.v:2838$4074 + assign { } { } + assign $1\builder_multiregimpl11_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] + end + attribute \src "ls180.v:2839.32-2839.67" + process $proc$ls180.v:2839$4075 + assign { } { } + assign $1\builder_multiregimpl11_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] + end + attribute \src "ls180.v:2840.32-2840.67" + process $proc$ls180.v:2840$4076 + assign { } { } + assign $1\builder_multiregimpl12_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] + end + attribute \src "ls180.v:2841.32-2841.67" + process $proc$ls180.v:2841$4077 + assign { } { } + assign $1\builder_multiregimpl12_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] + end + attribute \src "ls180.v:2842.32-2842.67" + process $proc$ls180.v:2842$4078 + assign { } { } + assign $1\builder_multiregimpl13_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:149365$7137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lsd - connect \Y $not$libresoc.v:149365$7137_Y + attribute \src "ls180.v:2843.32-2843.67" + process $proc$ls180.v:2843$4079 + assign { } { } + assign $1\builder_multiregimpl13_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:149367$7139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lsd - connect \Y $not$libresoc.v:149367$7139_Y + attribute \src "ls180.v:2844.32-2844.67" + process $proc$ls180.v:2844$4080 + assign { } { } + assign $1\builder_multiregimpl14_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:149370$7142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lsd - connect \Y $not$libresoc.v:149370$7142_Y + attribute \src "ls180.v:2845.32-2845.67" + process $proc$ls180.v:2845$4081 + assign { } { } + assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:149364$7136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_lsd - connect \Y $or$libresoc.v:149364$7136_Y + attribute \src "ls180.v:2846.32-2846.67" + process $proc$ls180.v:2846$4082 + assign { } { } + assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:149366$7138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lsd - connect \B \q_int - connect \Y $or$libresoc.v:149366$7138_Y + attribute \src "ls180.v:2847.32-2847.67" + process $proc$ls180.v:2847$4083 + assign { } { } + assign $1\builder_multiregimpl15_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:149369$7141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_lsd - connect \Y $or$libresoc.v:149369$7141_Y + attribute \src "ls180.v:2848.32-2848.67" + process $proc$ls180.v:2848$4084 + assign { } { } + assign $1\builder_multiregimpl16_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] end - attribute \src "libresoc.v:149328.7-149328.20" - process $proc$libresoc.v:149328$7147 + attribute \src "ls180.v:2849.32-2849.67" + process $proc$ls180.v:2849$4085 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\builder_multiregimpl16_regs1[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] end - attribute \src "libresoc.v:149350.7-149350.19" - process $proc$libresoc.v:149350$7148 + attribute \src "ls180.v:286.5-286.39" + process $proc$ls180.v:286$3175 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\main_interface2_ram_bus_err[0:0] 1'0 sync always + update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] sync init - update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:149371.3-149372.27" - process $proc$libresoc.v:149371$7143 + attribute \src "ls180.v:2884.1-2889.4" + process $proc$ls180.v:2884$49 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 + assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq + assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq + sync always + update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "libresoc.v:149373.3-149381.6" - process $proc$libresoc.v:149373$7144 + attribute \src "ls180.v:289.11-289.31" + process $proc$ls180.v:289$3176 assign { } { } + assign $1\main_sram2_we[7:0] 8'00000000 + sync always + sync init + update \main_sram2_we $1\main_sram2_we[7:0] + end + attribute \src "ls180.v:2891.1-2901.4" + process $proc$ls180.v:2891$51 assign { } { } - assign $0\q_int$next[0:0]$7145 $1\q_int$next[0:0]$7146 - attribute \src "libresoc.v:149374.5-149374.29" - switch \initial - attribute \src "libresoc.v:149374.9-149374.17" + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + attribute \src "ls180.v:2893.2-2900.9" + switch \main_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" case 1'1 + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [63:32] case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + end + attribute \src "ls180.v:2903.1-2949.4" + process $proc$ls180.v:2903$52 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_interface0_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + assign $0\main_converter0_skip[0:0] 1'0 + assign $0\builder_converter0_next_state[0:0] \builder_converter0_state + attribute \src "ls180.v:2915.2-2948.9" + switch \builder_converter0_state + attribute \src "ls180.v:0.0-0.0" case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$7146 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } + attribute \src "ls180.v:2918.4-2925.11" + switch \main_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] + case + end + attribute \src "ls180.v:2926.4-2939.7" + switch $and$ls180.v:2926$53_Y + attribute \src "ls180.v:2926.8-2926.91" + case 1'1 + assign $0\main_converter0_skip[0:0] $eq$ls180.v:2927$54_Y + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2929$55_Y + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2930$56_Y + attribute \src "ls180.v:2931.5-2938.8" + switch $or$ls180.v:2931$57_Y + attribute \src "ls180.v:2931.9-2931.72" + case 1'1 + assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2932$58_Y + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2934.6-2937.9" + switch $eq$ls180.v:2934$59_Y + attribute \src "ls180.v:2934.10-2934.43" + case 1'1 + assign $0\main_interface0_converted_interface_ack[0:0] 1'1 + assign $0\builder_converter0_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" case - assign $1\q_int$next[0:0]$7146 \$5 + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2944.4-2946.7" + switch $and$ls180.v:2944$60_Y + attribute \src "ls180.v:2944.8-2944.91" + case 1'1 + assign $0\builder_converter0_next_state[0:0] 1'1 + case + end end sync always - update \q_int$next $0\q_int$next[0:0]$7145 + update \main_libresocsim_libresoc_xics_icp_adr $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + update \main_libresocsim_libresoc_xics_icp_sel $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + update \main_libresocsim_libresoc_xics_icp_cyc $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + update \main_libresocsim_libresoc_xics_icp_stb $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + update \main_libresocsim_libresoc_xics_icp_we $0\main_libresocsim_libresoc_xics_icp_we[0:0] + update \main_interface0_converted_interface_ack $0\main_interface0_converted_interface_ack[0:0] + update \main_converter0_skip $0\main_converter0_skip[0:0] + update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] + update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] + update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] end - connect \$9 $and$libresoc.v:149363$7135_Y - connect \$11 $or$libresoc.v:149364$7136_Y - connect \$13 $not$libresoc.v:149365$7137_Y - connect \$15 $or$libresoc.v:149366$7138_Y - connect \$1 $not$libresoc.v:149367$7139_Y - connect \$3 $and$libresoc.v:149368$7140_Y - connect \$5 $or$libresoc.v:149369$7141_Y - connect \$7 $not$libresoc.v:149370$7142_Y - connect \qlq_lsd \$15 - connect \qn_lsd \$13 - connect \q_lsd \$11 -end -attribute \src "libresoc.v:149389.1-149923.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" -attribute \generator "nMigen" -module \lsmem - attribute \src "libresoc.v:149777.3-149802.6" - wire width 45 $0\dbus__adr$next[44:0]$7234 - attribute \src "libresoc.v:149627.3-149628.35" - wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:149637.3-149664.6" - wire $0\dbus__cyc$next[0:0]$7208 - attribute \src "libresoc.v:149635.3-149636.35" - wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:149829.3-149854.6" - wire width 64 $0\dbus__dat_w$next[63:0]$7244 - attribute \src "libresoc.v:149623.3-149624.39" - wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:149721.3-149751.6" - wire width 8 $0\dbus__sel$next[7:0]$7222 - attribute \src "libresoc.v:149631.3-149632.35" - wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:149665.3-149692.6" - wire $0\dbus__stb$next[0:0]$7214 - attribute \src "libresoc.v:149633.3-149634.35" - wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:149803.3-149828.6" - wire $0\dbus__we$next[0:0]$7239 - attribute \src "libresoc.v:149625.3-149626.33" - wire $0\dbus__we[0:0] - attribute \src "libresoc.v:149390.7-149390.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:149901.3-149920.6" - wire width 45 $0\m_badaddr_o$next[44:0]$7259 - attribute \src "libresoc.v:149617.3-149618.39" - wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:149703.3-149720.6" - wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:149752.3-149776.6" - wire width 64 $0\m_ld_data_o$next[63:0]$7228 - attribute \src "libresoc.v:149629.3-149630.39" - wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:149855.3-149877.6" - wire $0\m_load_err_o$next[0:0]$7249 - attribute \src "libresoc.v:149621.3-149622.41" - wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:149878.3-149900.6" - wire $0\m_store_err_o$next[0:0]$7254 - attribute \src "libresoc.v:149619.3-149620.43" - wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:149693.3-149702.6" - wire $0\x_busy_o[0:0] - attribute \src "libresoc.v:149777.3-149802.6" - wire width 45 $1\dbus__adr$next[44:0]$7235 - attribute \src "libresoc.v:149495.14-149495.42" - wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:149637.3-149664.6" - wire $1\dbus__cyc$next[0:0]$7209 - attribute \src "libresoc.v:149500.7-149500.23" - wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:149829.3-149854.6" - wire width 64 $1\dbus__dat_w$next[63:0]$7245 - attribute \src "libresoc.v:149507.14-149507.48" - wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:149721.3-149751.6" - wire width 8 $1\dbus__sel$next[7:0]$7223 - attribute \src "libresoc.v:149514.13-149514.30" - wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:149665.3-149692.6" - wire $1\dbus__stb$next[0:0]$7215 - attribute \src "libresoc.v:149519.7-149519.23" - wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:149803.3-149828.6" - wire $1\dbus__we$next[0:0]$7240 - attribute \src "libresoc.v:149524.7-149524.22" - wire $1\dbus__we[0:0] - attribute \src "libresoc.v:149901.3-149920.6" - wire width 45 $1\m_badaddr_o$next[44:0]$7260 - attribute \src "libresoc.v:149528.14-149528.44" - wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:149703.3-149720.6" - wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:149752.3-149776.6" - wire width 64 $1\m_ld_data_o$next[63:0]$7229 - attribute \src "libresoc.v:149535.14-149535.48" - wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:149855.3-149877.6" - wire $1\m_load_err_o$next[0:0]$7250 - attribute \src "libresoc.v:149539.7-149539.26" - wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:149878.3-149900.6" - wire $1\m_store_err_o$next[0:0]$7255 - attribute \src "libresoc.v:149545.7-149545.27" - wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:149693.3-149702.6" - wire $1\x_busy_o[0:0] - attribute \src "libresoc.v:149777.3-149802.6" - wire width 45 $2\dbus__adr$next[44:0]$7236 - attribute \src "libresoc.v:149637.3-149664.6" - wire $2\dbus__cyc$next[0:0]$7210 - attribute \src "libresoc.v:149829.3-149854.6" - wire width 64 $2\dbus__dat_w$next[63:0]$7246 - attribute \src "libresoc.v:149721.3-149751.6" - wire width 8 $2\dbus__sel$next[7:0]$7224 - attribute \src "libresoc.v:149665.3-149692.6" - wire $2\dbus__stb$next[0:0]$7216 - attribute \src "libresoc.v:149803.3-149828.6" - wire $2\dbus__we$next[0:0]$7241 - attribute \src "libresoc.v:149901.3-149920.6" - wire width 45 $2\m_badaddr_o$next[44:0]$7261 - attribute \src "libresoc.v:149703.3-149720.6" - wire $2\m_busy_o[0:0] - attribute \src "libresoc.v:149752.3-149776.6" - wire width 64 $2\m_ld_data_o$next[63:0]$7230 - attribute \src "libresoc.v:149855.3-149877.6" - wire $2\m_load_err_o$next[0:0]$7251 - attribute \src "libresoc.v:149878.3-149900.6" - wire $2\m_store_err_o$next[0:0]$7256 - attribute \src "libresoc.v:149777.3-149802.6" - wire width 45 $3\dbus__adr$next[44:0]$7237 - attribute \src "libresoc.v:149637.3-149664.6" - wire $3\dbus__cyc$next[0:0]$7211 - attribute \src "libresoc.v:149829.3-149854.6" - wire width 64 $3\dbus__dat_w$next[63:0]$7247 - attribute \src "libresoc.v:149721.3-149751.6" - wire width 8 $3\dbus__sel$next[7:0]$7225 - attribute \src "libresoc.v:149665.3-149692.6" - wire $3\dbus__stb$next[0:0]$7217 - attribute \src "libresoc.v:149803.3-149828.6" - wire $3\dbus__we$next[0:0]$7242 - attribute \src "libresoc.v:149901.3-149920.6" - wire width 45 $3\m_badaddr_o$next[44:0]$7262 - attribute \src "libresoc.v:149752.3-149776.6" - wire width 64 $3\m_ld_data_o$next[63:0]$7231 - attribute \src "libresoc.v:149855.3-149877.6" - wire $3\m_load_err_o$next[0:0]$7252 - attribute \src "libresoc.v:149878.3-149900.6" - wire $3\m_store_err_o$next[0:0]$7257 - attribute \src "libresoc.v:149637.3-149664.6" - wire $4\dbus__cyc$next[0:0]$7212 - attribute \src "libresoc.v:149721.3-149751.6" - wire width 8 $4\dbus__sel$next[7:0]$7226 - attribute \src "libresoc.v:149665.3-149692.6" - wire $4\dbus__stb$next[0:0]$7218 - attribute \src "libresoc.v:149752.3-149776.6" - wire width 64 $4\m_ld_data_o$next[63:0]$7232 - attribute \src "libresoc.v:149573.18-149573.116" - wire $and$libresoc.v:149573$7153_Y - attribute \src "libresoc.v:149576.18-149576.111" - wire $and$libresoc.v:149576$7156_Y - attribute \src "libresoc.v:149581.18-149581.116" - wire $and$libresoc.v:149581$7161_Y - attribute \src "libresoc.v:149583.18-149583.111" - wire $and$libresoc.v:149583$7163_Y - attribute \src "libresoc.v:149585.17-149585.114" - wire $and$libresoc.v:149585$7165_Y - attribute \src "libresoc.v:149589.18-149589.116" - wire $and$libresoc.v:149589$7169_Y - attribute \src "libresoc.v:149591.18-149591.111" - wire $and$libresoc.v:149591$7171_Y - attribute \src "libresoc.v:149597.18-149597.116" - wire $and$libresoc.v:149597$7177_Y - attribute \src "libresoc.v:149599.18-149599.111" - wire $and$libresoc.v:149599$7179_Y - attribute \src "libresoc.v:149601.18-149601.116" - wire $and$libresoc.v:149601$7181_Y - attribute \src "libresoc.v:149603.18-149603.111" - wire $and$libresoc.v:149603$7183_Y - attribute \src "libresoc.v:149605.18-149605.116" - wire $and$libresoc.v:149605$7185_Y - attribute \src "libresoc.v:149607.17-149607.108" - wire $and$libresoc.v:149607$7187_Y - attribute \src "libresoc.v:149608.18-149608.111" - wire $and$libresoc.v:149608$7188_Y - attribute \src "libresoc.v:149609.18-149609.120" - wire $and$libresoc.v:149609$7189_Y - attribute \src "libresoc.v:149612.18-149612.120" - wire $and$libresoc.v:149612$7192_Y - attribute \src "libresoc.v:149614.18-149614.120" - wire $and$libresoc.v:149614$7194_Y - attribute \src "libresoc.v:149570.18-149570.110" - wire $not$libresoc.v:149570$7150_Y - attribute \src "libresoc.v:149575.18-149575.110" - wire $not$libresoc.v:149575$7155_Y - attribute \src "libresoc.v:149578.18-149578.110" - wire $not$libresoc.v:149578$7158_Y - attribute \src "libresoc.v:149582.18-149582.110" - wire $not$libresoc.v:149582$7162_Y - attribute \src "libresoc.v:149586.18-149586.110" - wire $not$libresoc.v:149586$7166_Y - attribute \src "libresoc.v:149590.18-149590.110" - wire $not$libresoc.v:149590$7170_Y - attribute \src "libresoc.v:149593.18-149593.110" - wire $not$libresoc.v:149593$7173_Y - attribute \src "libresoc.v:149596.17-149596.109" - wire $not$libresoc.v:149596$7176_Y - attribute \src "libresoc.v:149598.18-149598.110" - wire $not$libresoc.v:149598$7178_Y - attribute \src "libresoc.v:149602.18-149602.110" - wire $not$libresoc.v:149602$7182_Y - attribute \src "libresoc.v:149606.18-149606.110" - wire $not$libresoc.v:149606$7186_Y - attribute \src "libresoc.v:149610.18-149610.110" - wire $not$libresoc.v:149610$7190_Y - attribute \src "libresoc.v:149611.18-149611.109" - wire $not$libresoc.v:149611$7191_Y - attribute \src "libresoc.v:149613.18-149613.110" - wire $not$libresoc.v:149613$7193_Y - attribute \src "libresoc.v:149615.18-149615.110" - wire $not$libresoc.v:149615$7195_Y - attribute \src "libresoc.v:149569.17-149569.119" - wire $or$libresoc.v:149569$7149_Y - attribute \src "libresoc.v:149571.18-149571.110" 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"/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 13 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 18 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 \dbus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 12 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire \dbus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 17 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 20 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 \dbus__dat_w$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 14 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 16 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 \dbus__sel$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 15 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire \dbus__stb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 19 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire \dbus__we$next - attribute \src "libresoc.v:149390.7-149390.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" - wire width 45 \m_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" - wire width 45 \m_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" - wire \m_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" - wire width 64 output 4 \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" - wire width 64 \m_ld_data_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" - wire \m_load_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" - wire \m_load_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:60" - wire \m_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" - wire \m_store_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" - wire \m_store_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" - wire input 9 \m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire input 11 \wb_dcache_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 48 input 3 \x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" - wire output 6 \x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" - wire input 7 \x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" - wire width 8 input 2 \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" - wire width 64 input 5 \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" - wire input 8 \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:56" - wire \x_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" - wire input 10 \x_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149573$7153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \x_valid_i - connect \Y $and$libresoc.v:149573$7153_Y + attribute \src "ls180.v:2951.1-2961.4" + process $proc$ls180.v:2951$62 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + attribute \src "ls180.v:2953.2-2960.9" + switch \main_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [63:32] + case + end + sync always + update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149576$7156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$17 - connect \B \$19 - connect \Y $and$libresoc.v:149576$7156_Y + attribute \src "ls180.v:2963.1-3009.4" + process $proc$ls180.v:2963$63 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + assign $0\main_interface1_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + assign $0\main_converter1_skip[0:0] 1'0 + assign $0\builder_converter1_next_state[0:0] \builder_converter1_state + attribute \src "ls180.v:2975.2-3008.9" + switch \builder_converter1_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } + attribute \src "ls180.v:2978.4-2985.11" + switch \main_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] + case + end + attribute \src "ls180.v:2986.4-2999.7" + switch $and$ls180.v:2986$64_Y + attribute \src "ls180.v:2986.8-2986.91" + case 1'1 + assign $0\main_converter1_skip[0:0] $eq$ls180.v:2987$65_Y + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2989$66_Y + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2990$67_Y + attribute \src "ls180.v:2991.5-2998.8" + switch $or$ls180.v:2991$68_Y + attribute \src "ls180.v:2991.9-2991.72" + case 1'1 + assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2992$69_Y + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2994.6-2997.9" + switch $eq$ls180.v:2994$70_Y + attribute \src "ls180.v:2994.10-2994.43" + case 1'1 + assign $0\main_interface1_converted_interface_ack[0:0] 1'1 + assign $0\builder_converter1_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3004.4-3006.7" + switch $and$ls180.v:3004$71_Y + attribute \src "ls180.v:3004.8-3004.91" + case 1'1 + assign $0\builder_converter1_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_xics_ics_adr $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + update \main_libresocsim_libresoc_xics_ics_sel $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + update \main_libresocsim_libresoc_xics_ics_cyc $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + update \main_libresocsim_libresoc_xics_ics_stb $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + update \main_libresocsim_libresoc_xics_ics_we $0\main_libresocsim_libresoc_xics_ics_we[0:0] + update \main_interface1_converted_interface_ack $0\main_interface1_converted_interface_ack[0:0] + update \main_converter1_skip $0\main_converter1_skip[0:0] + update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] + update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] + update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149581$7161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$29 - connect \B \x_valid_i - connect \Y $and$libresoc.v:149581$7161_Y + attribute \src "ls180.v:297.5-297.39" + process $proc$ls180.v:297$3177 + assign { } { } + assign $1\main_interface3_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface3_ram_bus_ack $1\main_interface3_ram_bus_ack[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149583$7163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$31 - connect \B \$33 - connect \Y $and$libresoc.v:149583$7163_Y + attribute \src "ls180.v:301.5-301.39" + process $proc$ls180.v:301$3178 + assign { } { } + assign $0\main_interface3_ram_bus_err[0:0] 1'0 + sync always + update \main_interface3_ram_bus_err $0\main_interface3_ram_bus_err[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149585$7165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \x_valid_i - connect \Y $and$libresoc.v:149585$7165_Y + attribute \src "ls180.v:3011.1-3021.4" + process $proc$ls180.v:3011$73 + assign { } { } + assign $0\main_wb_sdram_dat_w[31:0] 0 + attribute \src "ls180.v:3013.2-3020.9" + switch \main_socbushandler_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [63:32] + case + end + sync always + update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149589$7169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$43 - connect \B \x_valid_i - connect \Y $and$libresoc.v:149589$7169_Y + attribute \src "ls180.v:3023.1-3069.4" + process $proc$ls180.v:3023$74 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_wb_sdram_we[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 + assign $0\main_wb_sdram_sel[3:0] 4'0000 + assign $0\main_wb_sdram_cyc[0:0] 1'0 + assign $0\main_wb_sdram_stb[0:0] 1'0 + assign $0\main_socbushandler_skip[0:0] 1'0 + assign { } { } + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\builder_converter2_next_state[0:0] \builder_converter2_state + attribute \src "ls180.v:3035.2-3068.9" + switch \builder_converter2_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } + attribute \src "ls180.v:3038.4-3045.11" + switch \main_socbushandler_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] + case + end + attribute \src "ls180.v:3046.4-3059.7" + switch $and$ls180.v:3046$75_Y + attribute \src "ls180.v:3046.8-3046.97" + case 1'1 + assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:3047$76_Y + assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we + assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:3049$77_Y + assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:3050$78_Y + attribute \src "ls180.v:3051.5-3058.8" + switch $or$ls180.v:3051$79_Y + attribute \src "ls180.v:3051.9-3051.54" + case 1'1 + assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:3052$80_Y + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3054.6-3057.9" + switch $eq$ls180.v:3054$81_Y + attribute \src "ls180.v:3054.10-3054.46" + case 1'1 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 + assign $0\builder_converter2_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3064.4-3066.7" + switch $and$ls180.v:3064$82_Y + attribute \src "ls180.v:3064.8-3064.97" + case 1'1 + assign $0\builder_converter2_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_adr $0\main_wb_sdram_adr[29:0] + update \main_wb_sdram_sel $0\main_wb_sdram_sel[3:0] + update \main_wb_sdram_cyc $0\main_wb_sdram_cyc[0:0] + update \main_wb_sdram_stb $0\main_wb_sdram_stb[0:0] + update \main_wb_sdram_we $0\main_wb_sdram_we[0:0] + update \main_socbushandler_converted_interface_ack $0\main_socbushandler_converted_interface_ack[0:0] + update \main_socbushandler_skip $0\main_socbushandler_skip[0:0] + update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] + update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] + update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149591$7171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$45 - connect \B \$47 - connect \Y $and$libresoc.v:149591$7171_Y + attribute \src "ls180.v:304.11-304.31" + process $proc$ls180.v:304$3179 + assign { } { } + assign $1\main_sram3_we[7:0] 8'00000000 + sync always + sync init + update \main_sram3_we $1\main_sram3_we[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149597$7177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$57 - connect \B \x_valid_i - connect \Y $and$libresoc.v:149597$7177_Y + attribute \src "ls180.v:3072.1-3082.4" + process $proc$ls180.v:3072$83 + assign { } { } + assign { } { } + assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3074$86_Y + assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3075$89_Y + assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3076$92_Y + assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3077$95_Y + assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3078$98_Y + assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3079$101_Y + assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3080$104_Y + assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3081$107_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149599$7179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$59 - connect \B \$61 - connect \Y $and$libresoc.v:149599$7179_Y + attribute \src "ls180.v:3088.1-3093.4" + process $proc$ls180.v:3088$109 + assign { } { } + assign $0\main_libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:3090.2-3092.5" + switch $and$ls180.v:3090$110_Y + attribute \src "ls180.v:3090.6-3090.90" + case 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149601$7181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$65 - connect \B \x_valid_i - connect \Y $and$libresoc.v:149601$7181_Y + attribute \src "ls180.v:3097.1-3107.4" + process $proc$ls180.v:3097$112 + assign { } { } + assign { } { } + assign $0\main_sram0_we[7:0] [0] $and$ls180.v:3099$115_Y + assign $0\main_sram0_we[7:0] [1] $and$ls180.v:3100$118_Y + assign $0\main_sram0_we[7:0] [2] $and$ls180.v:3101$121_Y + assign $0\main_sram0_we[7:0] [3] $and$ls180.v:3102$124_Y + assign $0\main_sram0_we[7:0] [4] $and$ls180.v:3103$127_Y + assign $0\main_sram0_we[7:0] [5] $and$ls180.v:3104$130_Y + assign $0\main_sram0_we[7:0] [6] $and$ls180.v:3105$133_Y + assign $0\main_sram0_we[7:0] [7] $and$ls180.v:3106$136_Y + sync always + update \main_sram0_we $0\main_sram0_we[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149603$7183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$67 - connect \B \$69 - connect \Y $and$libresoc.v:149603$7183_Y + attribute \src "ls180.v:3111.1-3121.4" + process $proc$ls180.v:3111$137 + assign { } { } + assign { } { } + assign $0\main_sram1_we[7:0] [0] $and$ls180.v:3113$140_Y + assign $0\main_sram1_we[7:0] [1] $and$ls180.v:3114$143_Y + assign $0\main_sram1_we[7:0] [2] $and$ls180.v:3115$146_Y + assign $0\main_sram1_we[7:0] [3] $and$ls180.v:3116$149_Y + assign $0\main_sram1_we[7:0] [4] $and$ls180.v:3117$152_Y + assign $0\main_sram1_we[7:0] [5] $and$ls180.v:3118$155_Y + assign $0\main_sram1_we[7:0] [6] $and$ls180.v:3119$158_Y + assign $0\main_sram1_we[7:0] [7] $and$ls180.v:3120$161_Y + sync always + update \main_sram1_we $0\main_sram1_we[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149605$7185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$73 - connect \B \x_valid_i - connect \Y $and$libresoc.v:149605$7185_Y + attribute \src "ls180.v:312.5-312.51" + process $proc$ls180.v:312$3180 + assign { } { } + assign $1\main_interface0_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149607$7187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \$5 - connect \Y $and$libresoc.v:149607$7187_Y + attribute \src "ls180.v:3125.1-3135.4" + process $proc$ls180.v:3125$162 + assign { } { } + assign { } { } + assign $0\main_sram2_we[7:0] [0] $and$ls180.v:3127$165_Y + assign $0\main_sram2_we[7:0] [1] $and$ls180.v:3128$168_Y + assign $0\main_sram2_we[7:0] [2] $and$ls180.v:3129$171_Y + assign $0\main_sram2_we[7:0] [3] $and$ls180.v:3130$174_Y + assign $0\main_sram2_we[7:0] [4] $and$ls180.v:3131$177_Y + assign $0\main_sram2_we[7:0] [5] $and$ls180.v:3132$180_Y + assign $0\main_sram2_we[7:0] [6] $and$ls180.v:3133$183_Y + assign $0\main_sram2_we[7:0] [7] $and$ls180.v:3134$186_Y + sync always + update \main_sram2_we $0\main_sram2_we[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:149608$7188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$75 - connect \B \$77 - connect \Y $and$libresoc.v:149608$7188_Y + attribute \src "ls180.v:3139.1-3149.4" + process $proc$ls180.v:3139$187 + assign { } { } + assign { } { } + assign $0\main_sram3_we[7:0] [0] $and$ls180.v:3141$190_Y + assign $0\main_sram3_we[7:0] [1] $and$ls180.v:3142$193_Y + assign $0\main_sram3_we[7:0] [2] $and$ls180.v:3143$196_Y + assign $0\main_sram3_we[7:0] [3] $and$ls180.v:3144$199_Y + assign $0\main_sram3_we[7:0] [4] $and$ls180.v:3145$202_Y + assign $0\main_sram3_we[7:0] [5] $and$ls180.v:3146$205_Y + assign $0\main_sram3_we[7:0] [6] $and$ls180.v:3147$208_Y + assign $0\main_sram3_we[7:0] [7] $and$ls180.v:3148$211_Y + sync always + update \main_sram3_we $0\main_sram3_we[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:149609$7189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__cyc - connect \B \dbus__err - connect \Y $and$libresoc.v:149609$7189_Y + attribute \src "ls180.v:316.5-316.51" + process $proc$ls180.v:316$3181 + assign { } { } + assign $0\main_interface0_converted_interface_err[0:0] 1'0 + sync always + update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:149612$7192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__cyc - connect \B \dbus__err - connect \Y $and$libresoc.v:149612$7192_Y + attribute \src "ls180.v:317.5-317.32" + process $proc$ls180.v:317$3182 + assign { } { } + assign $1\main_converter0_skip[0:0] 1'0 + sync always + sync init + update \main_converter0_skip $1\main_converter0_skip[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:149614$7194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__cyc - connect \B \dbus__err - connect \Y $and$libresoc.v:149614$7194_Y + attribute \src "ls180.v:318.5-318.35" + process $proc$ls180.v:318$3183 + assign { } { } + assign $1\main_converter0_counter[0:0] 1'0 + sync always + sync init + update \main_converter0_counter $1\main_converter0_counter[0:0] + end + attribute \src "ls180.v:3188.1-3242.4" + process $proc$ls180.v:3188$212 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_master_p0_bank[1:0] 2'00 + assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_master_p0_we_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cke[0:0] 1'0 + assign $0\main_sdram_master_p0_odt[0:0] 1'0 + assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 + attribute \src "ls180.v:3207.2-3241.5" + switch \main_sdram_sel + attribute \src "ls180.v:3207.6-3207.20" + case 1'1 + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en + assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:3224.6-3224.10" + case + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en + assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + end + sync always + update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] + update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] + update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] + update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] + update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] + update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] + update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] + update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] + update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] + update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] + update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] + update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:320.12-320.41" + process $proc$ls180.v:320$3184 + assign { } { } + assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] + end + attribute \src "ls180.v:3246.1-3262.4" + process $proc$ls180.v:3246$213 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + attribute \src "ls180.v:3251.2-3261.5" + switch \main_sdram_command_issue_re + attribute \src "ls180.v:3251.6-3251.33" + case 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3252$214_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3253$215_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3254$216_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3255$217_Y + attribute \src "ls180.v:3256.6-3256.10" + case + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] + update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] + update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] + update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:149570$7150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $not$libresoc.v:149570$7150_Y + attribute \src "ls180.v:327.5-327.51" + process $proc$ls180.v:327$3185 + assign { } { } + assign $1\main_interface1_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:149575$7155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $not$libresoc.v:149575$7155_Y + attribute \src "ls180.v:3305.1-3335.4" + process $proc$ls180.v:3305$226 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_cmd_last[0:0] 1'0 + assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\builder_refresher_next_state[1:0] \builder_refresher_state + attribute \src "ls180.v:3311.2-3334.9" + switch \builder_refresher_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3314.4-3317.7" + switch \main_sdram_cmd_ready + attribute \src "ls180.v:3314.8-3314.28" + case 1'1 + assign $0\main_sdram_sequencer_start0[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3321.4-3325.7" + switch \main_sdram_sequencer_done0 + attribute \src "ls180.v:3321.8-3321.34" + case 1'1 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3328.4-3332.7" + switch 1'1 + attribute \src "ls180.v:3328.8-3328.12" + case 1'1 + attribute \src "ls180.v:3329.5-3331.8" + switch \main_sdram_wants_refresh + attribute \src "ls180.v:3329.9-3329.33" + case 1'1 + assign $0\builder_refresher_next_state[1:0] 2'01 + case + end + case + end + end + sync always + update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] + update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] + update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] + update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:149578$7158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $not$libresoc.v:149578$7158_Y + attribute \src "ls180.v:331.5-331.51" + process $proc$ls180.v:331$3186 + assign { } { } + assign $0\main_interface1_converted_interface_err[0:0] 1'0 + sync always + update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:149582$7162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $not$libresoc.v:149582$7162_Y + attribute \src "ls180.v:332.5-332.32" + process $proc$ls180.v:332$3187 + assign { } { } + assign $1\main_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_converter1_skip $1\main_converter1_skip[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:149586$7166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $not$libresoc.v:149586$7166_Y + attribute \src "ls180.v:333.5-333.35" + process $proc$ls180.v:333$3188 + assign { } { } + assign $1\main_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_converter1_counter $1\main_converter1_counter[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:149590$7170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $not$libresoc.v:149590$7170_Y + attribute \src "ls180.v:335.12-335.41" + process $proc$ls180.v:335$3189 + assign { } { } + assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:149593$7173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $not$libresoc.v:149593$7173_Y + attribute \src "ls180.v:3350.1-3357.4" + process $proc$ls180.v:3350$230 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3352.2-3356.5" + switch \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:3352.6-3352.48" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3354.6-3354.10" + case + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3355$232_Y + end + sync always + update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:149596$7176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $not$libresoc.v:149596$7176_Y + attribute \src "ls180.v:3361.1-3368.4" + process $proc$ls180.v:3361$239 + assign { } { } + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3363.2-3367.5" + switch $and$ls180.v:3363$240_Y + attribute \src "ls180.v:3363.6-3363.115" + case 1'1 + attribute \src "ls180.v:3364.3-3366.6" + switch $ne$ls180.v:3364$241_Y + attribute \src "ls180.v:3364.7-3364.143" + case 1'1 + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3365$242_Y + case + end + case + end + sync always + update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:149598$7178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $not$libresoc.v:149598$7178_Y + attribute \src "ls180.v:3383.1-3390.4" + process $proc$ls180.v:3383$243 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3385.2-3389.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3385.6-3385.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3386$244_Y + attribute \src "ls180.v:3387.6-3387.10" + case + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:149602$7182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $not$libresoc.v:149602$7182_Y + attribute \src "ls180.v:339.5-339.24" + process $proc$ls180.v:339$3190 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:149606$7186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $not$libresoc.v:149606$7186_Y + attribute \src "ls180.v:3399.1-3492.4" + process $proc$ls180.v:3399$252 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state + attribute \src "ls180.v:3415.2-3491.9" + switch \builder_bankmachine0_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3417.4-3425.7" + switch $and$ls180.v:3417$253_Y + attribute \src "ls180.v:3417.8-3417.87" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3419.5-3421.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3419.9-3419.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3429.4-3431.7" + switch $and$ls180.v:3429$254_Y + attribute \src "ls180.v:3429.8-3429.87" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3435.4-3444.7" + switch \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:3435.8-3435.44" + case 1'1 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3440.5-3442.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3440.9-3440.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3447.4-3449.7" + switch \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:3447.8-3447.45" + case 1'1 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3452.4-3454.7" + switch $not$ls180.v:3452$255_Y + attribute \src "ls180.v:3452.8-3452.46" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3463.4-3489.7" + switch \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:3463.8-3463.43" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'100 + attribute \src "ls180.v:3465.8-3465.12" + case + attribute \src "ls180.v:3466.5-3488.8" + switch \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:3466.9-3466.56" + case 1'1 + attribute \src "ls180.v:3467.6-3487.9" + switch \main_sdram_bankmachine0_row_opened + attribute \src "ls180.v:3467.10-3467.44" + case 1'1 + attribute \src "ls180.v:3468.7-3484.10" + switch \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:3468.11-3468.42" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3470.8-3477.11" + switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:3470.12-3470.64" + case 1'1 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3474.12-3474.16" + case + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3479.8-3481.11" + switch $and$ls180.v:3479$256_Y + attribute \src "ls180.v:3479.12-3479.88" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3482.11-3482.15" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3485.10-3485.14" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] + update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:149610$7190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_stall_i - connect \Y $not$libresoc.v:149610$7190_Y + attribute \src "ls180.v:3507.1-3514.4" + process $proc$ls180.v:3507$260 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3509.2-3513.5" + switch \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:3509.6-3509.48" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3511.6-3511.10" + case + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3512$262_Y + end + sync always + update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" - cell $not $not$libresoc.v:149611$7191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__we - connect \Y $not$libresoc.v:149611$7191_Y + attribute \src "ls180.v:3518.1-3525.4" + process $proc$ls180.v:3518$269 + assign { } { } + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3520.2-3524.5" + switch $and$ls180.v:3520$270_Y + attribute \src "ls180.v:3520.6-3520.115" + case 1'1 + attribute \src "ls180.v:3521.3-3523.6" + switch $ne$ls180.v:3521$271_Y + attribute \src "ls180.v:3521.7-3521.143" + case 1'1 + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3522$272_Y + case + end + case + end + sync always + update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:149613$7193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_stall_i - connect \Y $not$libresoc.v:149613$7193_Y + attribute \src "ls180.v:354.12-354.38" + process $proc$ls180.v:354$3191 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:149615$7195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_stall_i - connect \Y $not$libresoc.v:149615$7195_Y + attribute \src "ls180.v:3540.1-3547.4" + process $proc$ls180.v:3540$273 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3542.2-3546.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3542.6-3542.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3543$274_Y + attribute \src "ls180.v:3544.6-3544.10" + case + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:149569$7149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $or$libresoc.v:149569$7149_Y + attribute \src "ls180.v:355.5-355.36" + process $proc$ls180.v:355$3192 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:149571$7151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \$11 - connect \Y $or$libresoc.v:149571$7151_Y + attribute \src "ls180.v:3556.1-3649.4" + process $proc$ls180.v:3556$282 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state + attribute \src "ls180.v:3572.2-3648.9" + switch \builder_bankmachine1_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3574.4-3582.7" + switch $and$ls180.v:3574$283_Y + attribute \src "ls180.v:3574.8-3574.87" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3576.5-3578.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3576.9-3576.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3586.4-3588.7" + switch $and$ls180.v:3586$284_Y + attribute \src "ls180.v:3586.8-3586.87" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3592.4-3601.7" + switch \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:3592.8-3592.44" + case 1'1 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3597.5-3599.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3597.9-3597.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3604.4-3606.7" + switch \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:3604.8-3604.45" + case 1'1 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3609.4-3611.7" + switch $not$ls180.v:3609$285_Y + attribute \src "ls180.v:3609.8-3609.46" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3620.4-3646.7" + switch \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:3620.8-3620.43" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'100 + attribute \src "ls180.v:3622.8-3622.12" + case + attribute \src "ls180.v:3623.5-3645.8" + switch \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:3623.9-3623.56" + case 1'1 + attribute \src "ls180.v:3624.6-3644.9" + switch \main_sdram_bankmachine1_row_opened + attribute \src "ls180.v:3624.10-3624.44" + case 1'1 + attribute \src "ls180.v:3625.7-3641.10" + switch \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:3625.11-3625.42" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3627.8-3634.11" + switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:3627.12-3627.64" + case 1'1 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3631.12-3631.16" + case + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3636.8-3638.11" + switch $and$ls180.v:3636$286_Y + attribute \src "ls180.v:3636.12-3636.88" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3639.11-3639.15" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3642.10-3642.14" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] + update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:149572$7152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:149572$7152_Y + attribute \src "ls180.v:356.11-356.32" + process $proc$ls180.v:356$3193 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:149574$7154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:149574$7154_Y + attribute \src "ls180.v:359.5-359.36" + process $proc$ls180.v:359$3194 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:149577$7157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $or$libresoc.v:149577$7157_Y + attribute \src "ls180.v:360.5-360.35" + process $proc$ls180.v:360$3195 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:149579$7159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$23 - connect \B \$25 - connect \Y $or$libresoc.v:149579$7159_Y + attribute \src "ls180.v:361.5-361.36" + process $proc$ls180.v:361$3196 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:149580$7160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:149580$7160_Y + attribute \src "ls180.v:362.5-362.35" + process $proc$ls180.v:362$3197 + assign { } { } + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:149584$7164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $or$libresoc.v:149584$7164_Y + attribute \src "ls180.v:366.5-366.36" + process $proc$ls180.v:366$3198 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:149587$7167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$37 - connect \B \$39 - connect \Y $or$libresoc.v:149587$7167_Y + attribute \src "ls180.v:3664.1-3671.4" + process $proc$ls180.v:3664$290 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3666.2-3670.5" + switch \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:3666.6-3666.48" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3668.6-3668.10" + case + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3669$292_Y + end + sync always + update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:149588$7168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:149588$7168_Y + attribute \src "ls180.v:3675.1-3682.4" + process $proc$ls180.v:3675$299 + assign { } { } + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3677.2-3681.5" + switch $and$ls180.v:3677$300_Y + attribute \src "ls180.v:3677.6-3677.115" + case 1'1 + attribute \src "ls180.v:3678.3-3680.6" + switch $ne$ls180.v:3678$301_Y + attribute \src "ls180.v:3678.7-3678.143" + case 1'1 + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3679$302_Y + case + end + case + end + sync always + update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:149592$7172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $or$libresoc.v:149592$7172_Y + attribute \src "ls180.v:3697.1-3704.4" + process $proc$ls180.v:3697$303 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3699.2-3703.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3699.6-3699.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3700$304_Y + attribute \src "ls180.v:3701.6-3701.10" + case + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:149594$7174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$51 - connect \B \$53 - connect \Y $or$libresoc.v:149594$7174_Y + attribute \src "ls180.v:371.12-371.45" + process $proc$ls180.v:371$3199 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:149595$7175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:149595$7175_Y + attribute \src "ls180.v:3713.1-3806.4" + process $proc$ls180.v:3713$312 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state + attribute \src "ls180.v:3729.2-3805.9" + switch \builder_bankmachine2_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3731.4-3739.7" + switch $and$ls180.v:3731$313_Y + attribute \src "ls180.v:3731.8-3731.87" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3733.5-3735.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3733.9-3733.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3743.4-3745.7" + switch $and$ls180.v:3743$314_Y + attribute \src "ls180.v:3743.8-3743.87" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3749.4-3758.7" + switch \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:3749.8-3749.44" + case 1'1 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3754.5-3756.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3754.9-3754.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3761.4-3763.7" + switch \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:3761.8-3761.45" + case 1'1 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3766.4-3768.7" + switch $not$ls180.v:3766$315_Y + attribute \src "ls180.v:3766.8-3766.46" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3777.4-3803.7" + switch \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:3777.8-3777.43" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'100 + attribute \src "ls180.v:3779.8-3779.12" + case + attribute \src "ls180.v:3780.5-3802.8" + switch \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:3780.9-3780.56" + case 1'1 + attribute \src "ls180.v:3781.6-3801.9" + switch \main_sdram_bankmachine2_row_opened + attribute \src "ls180.v:3781.10-3781.44" + case 1'1 + attribute \src "ls180.v:3782.7-3798.10" + switch \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:3782.11-3782.42" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3784.8-3791.11" + switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:3784.12-3784.64" + case 1'1 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3788.12-3788.16" + case + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3793.8-3795.11" + switch $and$ls180.v:3793$316_Y + attribute \src "ls180.v:3793.12-3793.88" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3796.11-3796.15" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3799.10-3799.14" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:372.5-372.43" + process $proc$ls180.v:372$3200 + assign { } { } + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:149600$7180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:149600$7180_Y + attribute \src "ls180.v:3821.1-3828.4" + process $proc$ls180.v:3821$320 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3823.2-3827.5" + switch \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:3823.6-3823.48" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3825.6-3825.10" + case + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3826$322_Y + end + sync always + update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:149604$7184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:149604$7184_Y + attribute \src "ls180.v:3832.1-3839.4" + process $proc$ls180.v:3832$329 + assign { } { } + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3834.2-3838.5" + switch $and$ls180.v:3834$330_Y + attribute \src "ls180.v:3834.6-3834.115" + case 1'1 + attribute \src "ls180.v:3835.3-3837.6" + switch $ne$ls180.v:3835$331_Y + attribute \src "ls180.v:3835.7-3835.143" + case 1'1 + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3836$332_Y + case + end + case + end + sync always + update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - cell $or $or$libresoc.v:149616$7196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_load_err_o - connect \B \m_store_err_o - connect \Y $or$libresoc.v:149616$7196_Y + attribute \src "ls180.v:3854.1-3861.4" + process $proc$ls180.v:3854$333 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3856.2-3860.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3856.6-3856.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3857$334_Y + attribute \src "ls180.v:3858.6-3858.10" + case + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "libresoc.v:149390.7-149390.20" - process $proc$libresoc.v:149390$7263 + attribute \src "ls180.v:387.12-387.46" + process $proc$ls180.v:387$3201 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always - update \initial $0\initial[0:0] sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] end - attribute \src "libresoc.v:149495.14-149495.42" - process $proc$libresoc.v:149495$7264 + attribute \src "ls180.v:3870.1-3963.4" + process $proc$ls180.v:3870$342 assign { } { } - assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state + attribute \src "ls180.v:3886.2-3962.9" + switch \builder_bankmachine3_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3888.4-3896.7" + switch $and$ls180.v:3888$343_Y + attribute \src "ls180.v:3888.8-3888.87" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3890.5-3892.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3890.9-3890.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3900.4-3902.7" + switch $and$ls180.v:3900$344_Y + attribute \src "ls180.v:3900.8-3900.87" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3906.4-3915.7" + switch \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:3906.8-3906.44" + case 1'1 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3911.5-3913.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3911.9-3911.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3918.4-3920.7" + switch \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:3918.8-3918.45" + case 1'1 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3923.4-3925.7" + switch $not$ls180.v:3923$345_Y + attribute \src "ls180.v:3923.8-3923.46" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3934.4-3960.7" + switch \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:3934.8-3934.43" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'100 + attribute \src "ls180.v:3936.8-3936.12" + case + attribute \src "ls180.v:3937.5-3959.8" + switch \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:3937.9-3937.56" + case 1'1 + attribute \src "ls180.v:3938.6-3958.9" + switch \main_sdram_bankmachine3_row_opened + attribute \src "ls180.v:3938.10-3938.44" + case 1'1 + attribute \src "ls180.v:3939.7-3955.10" + switch \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:3939.11-3939.42" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3941.8-3948.11" + switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:3941.12-3941.64" + case 1'1 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3945.12-3945.16" + case + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3950.8-3952.11" + switch $and$ls180.v:3950$346_Y + attribute \src "ls180.v:3950.12-3950.88" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3953.11-3953.15" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3956.10-3956.14" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + end + case + end + end + end sync always - sync init - update \dbus__adr $1\dbus__adr[44:0] + update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] + update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] end - attribute \src "libresoc.v:149500.7-149500.23" - process $proc$libresoc.v:149500$7265 + attribute \src "ls180.v:388.5-388.44" + process $proc$ls180.v:388$3202 assign { } { } - assign $1\dbus__cyc[0:0] 1'0 + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 sync always sync init - update \dbus__cyc $1\dbus__cyc[0:0] + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] end - attribute \src "libresoc.v:149507.14-149507.48" - process $proc$libresoc.v:149507$7266 + attribute \src "ls180.v:389.12-389.48" + process $proc$ls180.v:389$3203 assign { } { } - assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 sync always sync init - update \dbus__dat_w $1\dbus__dat_w[63:0] + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] end - attribute \src "libresoc.v:149514.13-149514.30" - process $proc$libresoc.v:149514$7267 + attribute \src "ls180.v:390.11-390.43" + process $proc$ls180.v:390$3204 assign { } { } - assign $1\dbus__sel[7:0] 8'00000000 + assign $1\main_sdram_master_p0_bank[1:0] 2'00 sync always sync init - update \dbus__sel $1\dbus__sel[7:0] + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] end - attribute \src "libresoc.v:149519.7-149519.23" - process $proc$libresoc.v:149519$7268 + attribute \src "ls180.v:391.5-391.38" + process $proc$ls180.v:391$3205 assign { } { } - assign $1\dbus__stb[0:0] 1'0 + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 sync always sync init - update \dbus__stb $1\dbus__stb[0:0] + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] end - attribute \src "libresoc.v:149524.7-149524.22" - process $proc$libresoc.v:149524$7269 + attribute \src "ls180.v:392.5-392.37" + process $proc$ls180.v:392$3206 assign { } { } - assign $1\dbus__we[0:0] 1'0 + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 sync always sync init - update \dbus__we $1\dbus__we[0:0] + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] end - attribute \src "libresoc.v:149528.14-149528.44" - process $proc$libresoc.v:149528$7270 + attribute \src "ls180.v:393.5-393.38" + process $proc$ls180.v:393$3207 assign { } { } - assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 sync always sync init - update \m_badaddr_o $1\m_badaddr_o[44:0] + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] end - attribute \src "libresoc.v:149535.14-149535.48" - process $proc$libresoc.v:149535$7271 + attribute \src "ls180.v:394.5-394.37" + process $proc$ls180.v:394$3208 assign { } { } - assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 sync always sync init - update \m_ld_data_o $1\m_ld_data_o[63:0] + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] end - attribute \src "libresoc.v:149539.7-149539.26" - process $proc$libresoc.v:149539$7272 + attribute \src "ls180.v:395.5-395.36" + process $proc$ls180.v:395$3209 assign { } { } - assign $1\m_load_err_o[0:0] 1'0 + assign $1\main_sdram_master_p0_cke[0:0] 1'0 sync always sync init - update \m_load_err_o $1\m_load_err_o[0:0] + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] end - attribute \src "libresoc.v:149545.7-149545.27" - process $proc$libresoc.v:149545$7273 + attribute \src "ls180.v:396.5-396.36" + process $proc$ls180.v:396$3210 assign { } { } - assign $1\m_store_err_o[0:0] 1'0 + assign $1\main_sdram_master_p0_odt[0:0] 1'0 sync always sync init - update \m_store_err_o $1\m_store_err_o[0:0] + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] end - attribute \src "libresoc.v:149617.3-149618.39" - process $proc$libresoc.v:149617$7197 + attribute \src "ls180.v:397.5-397.40" + process $proc$ls180.v:397$3211 assign { } { } - assign $0\m_badaddr_o[44:0] \m_badaddr_o$next - sync posedge \coresync_clk - update \m_badaddr_o $0\m_badaddr_o[44:0] + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] end - attribute \src "libresoc.v:149619.3-149620.43" - process $proc$libresoc.v:149619$7198 + attribute \src "ls180.v:398.5-398.38" + process $proc$ls180.v:398$3212 assign { } { } - assign $0\m_store_err_o[0:0] \m_store_err_o$next - sync posedge \coresync_clk - update \m_store_err_o $0\m_store_err_o[0:0] + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] end - attribute \src "libresoc.v:149621.3-149622.41" - process $proc$libresoc.v:149621$7199 + attribute \src "ls180.v:3983.1-3989.4" + process $proc$ls180.v:3983$385 assign { } { } - assign $0\m_load_err_o[0:0] \m_load_err_o$next - sync posedge \coresync_clk - update \m_load_err_o $0\m_load_err_o[0:0] - end - attribute \src "libresoc.v:149623.3-149624.39" - process $proc$libresoc.v:149623$7200 assign { } { } - assign $0\dbus__dat_w[63:0] \dbus__dat_w$next - sync posedge \coresync_clk - update \dbus__dat_w $0\dbus__dat_w[63:0] + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3985$398_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3986$411_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3987$424_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3988$437_Y + sync always + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] end - attribute \src "libresoc.v:149625.3-149626.33" - process $proc$libresoc.v:149625$7201 + attribute \src "ls180.v:399.12-399.47" + process $proc$ls180.v:399$3213 assign { } { } - assign $0\dbus__we[0:0] \dbus__we$next - sync posedge \coresync_clk - update \dbus__we $0\dbus__we[0:0] + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] end - attribute \src "libresoc.v:149627.3-149628.35" - process $proc$libresoc.v:149627$7202 + attribute \src "ls180.v:3997.1-4002.4" + process $proc$ls180.v:3997$438 assign { } { } - assign $0\dbus__adr[44:0] \dbus__adr$next - sync posedge \coresync_clk - update \dbus__adr $0\dbus__adr[44:0] + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3999.2-4001.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3999.6-3999.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "libresoc.v:149629.3-149630.39" - process $proc$libresoc.v:149629$7203 + attribute \src "ls180.v:400.5-400.42" + process $proc$ls180.v:400$3214 assign { } { } - assign $0\m_ld_data_o[63:0] \m_ld_data_o$next - sync posedge \coresync_clk - update \m_ld_data_o $0\m_ld_data_o[63:0] + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] end - attribute \src "libresoc.v:149631.3-149632.35" - process $proc$libresoc.v:149631$7204 + attribute \src "ls180.v:4003.1-4008.4" + process $proc$ls180.v:4003$439 assign { } { } - assign $0\dbus__sel[7:0] \dbus__sel$next - sync posedge \coresync_clk - update \dbus__sel $0\dbus__sel[7:0] + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:4005.2-4007.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:4005.6-4005.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "libresoc.v:149633.3-149634.35" - process $proc$libresoc.v:149633$7205 + attribute \src "ls180.v:4009.1-4014.4" + process $proc$ls180.v:4009$440 assign { } { } - assign $0\dbus__stb[0:0] \dbus__stb$next - sync posedge \coresync_clk - update \dbus__stb $0\dbus__stb[0:0] + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:4011.2-4013.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:4011.6-4011.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "libresoc.v:149635.3-149636.35" - process $proc$libresoc.v:149635$7206 + attribute \src "ls180.v:401.11-401.50" + process $proc$ls180.v:401$3215 assign { } { } - assign $0\dbus__cyc[0:0] \dbus__cyc$next - sync posedge \coresync_clk - update \dbus__cyc $0\dbus__cyc[0:0] + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] end - attribute \src "libresoc.v:149637.3-149664.6" - process $proc$libresoc.v:149637$7207 + attribute \src "ls180.v:4016.1-4022.4" + process $proc$ls180.v:4016$443 + assign { } { } assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:4018$456_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:4019$469_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:4020$482_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:4021$495_Y + sync always + update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:402.5-402.42" + process $proc$ls180.v:402$3216 assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:4030.1-4035.4" + process $proc$ls180.v:4030$496 assign { } { } - assign $0\dbus__cyc$next[0:0]$7208 $4\dbus__cyc$next[0:0]$7212 - attribute \src "libresoc.v:149638.5-149638.29" - switch \initial - attribute \src "libresoc.v:149638.9-149638.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:4032.2-4034.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:4032.6-4032.37" case 1'1 - assign { } { } - assign $1\dbus__cyc$next[0:0]$7209 $2\dbus__cyc$next[0:0]$7210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$7 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\dbus__cyc$next[0:0]$7210 $3\dbus__cyc$next[0:0]$7211 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__cyc$next[0:0]$7211 1'0 - case - assign $3\dbus__cyc$next[0:0]$7211 \dbus__cyc - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__cyc$next[0:0]$7210 1'1 - case - assign $2\dbus__cyc$next[0:0]$7210 \dbus__cyc - end + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 case - assign $1\dbus__cyc$next[0:0]$7209 \dbus__cyc end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:4036.1-4041.4" + process $proc$ls180.v:4036$497 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:4038.2-4040.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:4038.6-4038.37" case 1'1 - assign { } { } - assign $4\dbus__cyc$next[0:0]$7212 1'0 + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 case - assign $4\dbus__cyc$next[0:0]$7212 $1\dbus__cyc$next[0:0]$7209 end sync always - update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7208 + update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "libresoc.v:149665.3-149692.6" - process $proc$libresoc.v:149665$7213 - assign { } { } - assign { } { } + attribute \src "ls180.v:4042.1-4047.4" + process $proc$ls180.v:4042$498 assign { } { } - assign $0\dbus__stb$next[0:0]$7214 $4\dbus__stb$next[0:0]$7218 - attribute \src "libresoc.v:149666.5-149666.29" - switch \initial - attribute \src "libresoc.v:149666.9-149666.17" + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:4044.2-4046.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:4044.6-4044.37" case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" + sync always + update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:4048.1-4056.4" + process $proc$ls180.v:4048$499 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:4050.2-4052.5" + switch $and$ls180.v:4050$502_Y + attribute \src "ls180.v:4050.6-4050.115" case 1'1 - assign { } { } - assign $1\dbus__stb$next[0:0]$7215 $2\dbus__stb$next[0:0]$7216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$21 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\dbus__stb$next[0:0]$7216 $3\dbus__stb$next[0:0]$7217 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__stb$next[0:0]$7217 1'0 - case - assign $3\dbus__stb$next[0:0]$7217 \dbus__stb - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__stb$next[0:0]$7216 1'1 - case - assign $2\dbus__stb$next[0:0]$7216 \dbus__stb - end + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case - assign $1\dbus__stb$next[0:0]$7215 \dbus__stb end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + attribute \src "ls180.v:4053.2-4055.5" + switch $and$ls180.v:4053$505_Y + attribute \src "ls180.v:4053.6-4053.115" case 1'1 - assign { } { } - assign $4\dbus__stb$next[0:0]$7218 1'0 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case - assign $4\dbus__stb$next[0:0]$7218 $1\dbus__stb$next[0:0]$7215 end sync always - update \dbus__stb$next $0\dbus__stb$next[0:0]$7214 + update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "libresoc.v:149693.3-149702.6" - process $proc$libresoc.v:149693$7219 - assign { } { } + attribute \src "ls180.v:4057.1-4065.4" + process $proc$ls180.v:4057$506 assign { } { } - assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] - attribute \src "libresoc.v:149694.5-149694.29" - switch \initial - attribute \src "libresoc.v:149694.9-149694.17" + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:4059.2-4061.5" + switch $and$ls180.v:4059$509_Y + attribute \src "ls180.v:4059.6-4059.115" case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" + attribute \src "ls180.v:4062.2-4064.5" + switch $and$ls180.v:4062$512_Y + attribute \src "ls180.v:4062.6-4062.115" case 1'1 - assign { } { } - assign $1\x_busy_o[0:0] \dbus__cyc + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case - assign $1\x_busy_o[0:0] 1'0 end sync always - update \x_busy_o $0\x_busy_o[0:0] + update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "libresoc.v:149703.3-149720.6" - process $proc$libresoc.v:149703$7220 - assign { } { } + attribute \src "ls180.v:4066.1-4074.4" + process $proc$ls180.v:4066$513 assign { } { } - assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:149704.5-149704.29" - switch \initial - attribute \src "libresoc.v:149704.9-149704.17" + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:4068.2-4070.5" + switch $and$ls180.v:4068$516_Y + attribute \src "ls180.v:4068.6-4068.115" case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" + attribute \src "ls180.v:4071.2-4073.5" + switch $and$ls180.v:4071$519_Y + attribute \src "ls180.v:4071.6-4071.115" case 1'1 - assign { } { } - assign $1\m_busy_o[0:0] $2\m_busy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - switch \$95 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\m_busy_o[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\m_busy_o[0:0] \dbus__cyc - end + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case - assign $1\m_busy_o[0:0] 1'0 end sync always - update \m_busy_o $0\m_busy_o[0:0] + update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "libresoc.v:149721.3-149751.6" - process $proc$libresoc.v:149721$7221 - assign { } { } - assign { } { } + attribute \src "ls180.v:4075.1-4083.4" + process $proc$ls180.v:4075$520 assign { } { } - assign $0\dbus__sel$next[7:0]$7222 $4\dbus__sel$next[7:0]$7226 - attribute \src "libresoc.v:149722.5-149722.29" - switch \initial - attribute \src "libresoc.v:149722.9-149722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:4077.2-4079.5" + switch $and$ls180.v:4077$523_Y + attribute \src "ls180.v:4077.6-4077.115" case 1'1 - assign { } { } - assign $1\dbus__sel$next[7:0]$7223 $2\dbus__sel$next[7:0]$7224 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$35 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\dbus__sel$next[7:0]$7224 $3\dbus__sel$next[7:0]$7225 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - switch \$41 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__sel$next[7:0]$7225 8'00000000 - case - assign $3\dbus__sel$next[7:0]$7225 \dbus__sel - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__sel$next[7:0]$7224 \x_mask_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbus__sel$next[7:0]$7224 8'00000000 - end + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case - assign $1\dbus__sel$next[7:0]$7223 \dbus__sel end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + attribute \src "ls180.v:4080.2-4082.5" + switch $and$ls180.v:4080$526_Y + attribute \src "ls180.v:4080.6-4080.115" case 1'1 - assign { } { } - assign $4\dbus__sel$next[7:0]$7226 8'00000000 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case - assign $4\dbus__sel$next[7:0]$7226 $1\dbus__sel$next[7:0]$7223 end sync always - update \dbus__sel$next $0\dbus__sel$next[7:0]$7222 + update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "libresoc.v:149752.3-149776.6" - process $proc$libresoc.v:149752$7227 + attribute \src "ls180.v:4088.1-4160.4" + process $proc$ls180.v:4088$529 assign { } { } assign { } { } assign { } { } - assign $0\m_ld_data_o$next[63:0]$7228 $4\m_ld_data_o$next[63:0]$7232 - attribute \src "libresoc.v:149753.5-149753.29" - switch \initial - attribute \src "libresoc.v:149753.9-149753.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\m_ld_data_o$next[63:0]$7229 $2\m_ld_data_o$next[63:0]$7230 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$49 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\m_ld_data_o$next[63:0]$7230 $3\m_ld_data_o$next[63:0]$7231 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - switch \$55 - attribute \src "libresoc.v:0.0-0.0" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_en1[0:0] 1'0 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $0\main_sdram_cmd_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_en0[0:0] 1'0 + assign { } { } + assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed + assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state + attribute \src "ls180.v:4100.2-4159.9" + switch \builder_multiplexer_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_en1[0:0] 1'1 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:4104.4-4110.7" + switch 1'1 + attribute \src "ls180.v:4104.8-4104.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4105$536_Y + case + end + attribute \src "ls180.v:4112.4-4116.7" + switch \main_sdram_read_available + attribute \src "ls180.v:4112.8-4112.33" + case 1'1 + attribute \src "ls180.v:4113.5-4115.8" + switch $or$ls180.v:4113$538_Y + attribute \src "ls180.v:4113.9-4113.63" case 1'1 - assign { } { } - assign $3\m_ld_data_o$next[63:0]$7231 \dbus__dat_r + assign $0\builder_multiplexer_next_state[2:0] 3'011 case - assign $3\m_ld_data_o$next[63:0]$7231 \m_ld_data_o end case - assign $2\m_ld_data_o$next[63:0]$7230 \m_ld_data_o end + attribute \src "ls180.v:4117.4-4119.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:4117.8-4117.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_steerer_sel[1:0] 2'11 + assign $0\main_sdram_cmd_ready[0:0] 1'1 + attribute \src "ls180.v:4124.4-4126.7" + switch \main_sdram_cmd_last + attribute \src "ls180.v:4124.8-4124.27" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:4129.4-4131.7" + switch \main_sdram_twtrcon_ready + attribute \src "ls180.v:4129.8-4129.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_multiplexer_next_state[2:0] 3'101 + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_multiplexer_next_state[2:0] 3'001 + attribute \src "ls180.v:0.0-0.0" case - assign $1\m_ld_data_o$next[63:0]$7229 \m_ld_data_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\m_ld_data_o$next[63:0]$7232 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $4\m_ld_data_o$next[63:0]$7232 $1\m_ld_data_o$next[63:0]$7229 + assign $0\main_sdram_en0[0:0] 1'1 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:4142.4-4148.7" + switch 1'1 + attribute \src "ls180.v:4142.8-4142.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4143$545_Y + case + end + attribute \src "ls180.v:4150.4-4154.7" + switch \main_sdram_write_available + attribute \src "ls180.v:4150.8-4150.34" + case 1'1 + attribute \src "ls180.v:4151.5-4153.8" + switch $or$ls180.v:4151$547_Y + attribute \src "ls180.v:4151.9-4151.62" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'100 + case + end + case + end + attribute \src "ls180.v:4155.4-4157.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:4155.8-4155.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end end sync always - update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7228 + update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] + update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] + update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] + update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] + update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] + update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] + update \main_sdram_en0 $0\main_sdram_en0[0:0] + update \main_sdram_en1 $0\main_sdram_en1[0:0] + update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:409.11-409.36" + process $proc$ls180.v:409$3217 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] end - attribute \src "libresoc.v:149777.3-149802.6" - process $proc$libresoc.v:149777$7233 + attribute \src "ls180.v:410.5-410.25" + process $proc$ls180.v:410$3218 assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:411.11-411.44" + process $proc$ls180.v:411$3219 assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:412.5-412.33" + process $proc$ls180.v:412$3220 assign { } { } - assign $0\dbus__adr$next[44:0]$7234 $3\dbus__adr$next[44:0]$7237 - attribute \src "libresoc.v:149778.5-149778.29" - switch \initial - attribute \src "libresoc.v:149778.9-149778.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbus__adr$next[44:0]$7235 $2\dbus__adr$next[44:0]$7236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$63 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $2\dbus__adr$next[44:0]$7236 \dbus__adr - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__adr$next[44:0]$7236 \x_addr_i [47:3] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbus__adr$next[44:0]$7236 45'000000000000000000000000000000000000000000000 - end - case - assign $1\dbus__adr$next[44:0]$7235 \dbus__adr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:416.5-416.38" + process $proc$ls180.v:416$3221 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "ls180.v:417.12-417.46" + process $proc$ls180.v:417$3222 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:418.5-418.33" + process $proc$ls180.v:418$3223 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:4184.1-4197.4" + process $proc$ls180.v:4184$676 + assign { } { } + assign { } { } + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + attribute \src "ls180.v:4187.2-4196.9" + switch \builder_new_master_wdata_ready + attribute \src "ls180.v:0.0-0.0" case 1'1 - assign { } { } - assign $3\dbus__adr$next[44:0]$7237 45'000000000000000000000000000000000000000000000 + assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data + assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we + attribute \src "ls180.v:0.0-0.0" case - assign $3\dbus__adr$next[44:0]$7237 $1\dbus__adr$next[44:0]$7235 + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 end sync always - update \dbus__adr$next $0\dbus__adr$next[44:0]$7234 + update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] + update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] end - attribute \src "libresoc.v:149803.3-149828.6" - process $proc$libresoc.v:149803$7238 + attribute \src "ls180.v:419.11-419.45" + process $proc$ls180.v:419$3224 assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:420.5-420.34" + process $proc$ls180.v:420$3225 assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:4204.1-4214.4" + process $proc$ls180.v:4204$678 assign { } { } - assign $0\dbus__we$next[0:0]$7239 $3\dbus__we$next[0:0]$7242 - attribute \src "libresoc.v:149804.5-149804.29" - switch \initial - attribute \src "libresoc.v:149804.9-149804.17" + assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "ls180.v:4206.2-4213.9" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + attribute \src "ls180.v:0.0-0.0" case 1'1 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" + sync always + update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:421.12-421.45" + process $proc$ls180.v:421$3226 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:4216.1-4262.4" + process $proc$ls180.v:4216$679 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_litedram_wb_sel[1:0] 2'00 + assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign { } { } + assign $0\main_litedram_wb_stb[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\main_litedram_wb_we[0:0] 1'0 + assign $0\main_converter_skip[0:0] 1'0 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\builder_converter_next_state[0:0] \builder_converter_state + attribute \src "ls180.v:4228.2-4261.9" + switch \builder_converter_state + attribute \src "ls180.v:0.0-0.0" case 1'1 - assign { } { } - assign $1\dbus__we$next[0:0]$7240 $2\dbus__we$next[0:0]$7241 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$71 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $2\dbus__we$next[0:0]$7241 \dbus__we - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__we$next[0:0]$7241 \x_st_i - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } + attribute \src "ls180.v:4231.4-4238.11" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + case + end + attribute \src "ls180.v:4239.4-4252.7" + switch $and$ls180.v:4239$680_Y + attribute \src "ls180.v:4239.8-4239.47" + case 1'1 + assign $0\main_converter_skip[0:0] $eq$ls180.v:4240$681_Y + assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4242$682_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4243$683_Y + attribute \src "ls180.v:4244.5-4251.8" + switch $or$ls180.v:4244$684_Y + attribute \src "ls180.v:4244.9-4244.53" + case 1'1 + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4245$685_Y + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4247.6-4250.9" + switch $eq$ls180.v:4247$686_Y + attribute \src "ls180.v:4247.10-4247.42" + case 1'1 + assign $0\main_wb_sdram_ack[0:0] 1'1 + assign $0\builder_converter_next_state[0:0] 1'0 + case + end + case + end case - assign { } { } - assign $2\dbus__we$next[0:0]$7241 1'0 end + attribute \src "ls180.v:0.0-0.0" case - assign $1\dbus__we$next[0:0]$7240 \dbus__we + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4257.4-4259.7" + switch $and$ls180.v:4257$687_Y + attribute \src "ls180.v:4257.8-4257.47" + case 1'1 + assign $0\builder_converter_next_state[0:0] 1'1 + case + end end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] + update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] + update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] + update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] + update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] + update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] + update \main_converter_skip $0\main_converter_skip[0:0] + update \builder_converter_next_state $0\builder_converter_next_state[0:0] + update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] + update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:422.5-422.32" + process $proc$ls180.v:422$3227 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:423.12-423.37" + process $proc$ls180.v:423$3228 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:4307.1-4312.4" + process $proc$ls180.v:4307$719 + assign { } { } + assign $0\main_uart_tx_clear[0:0] 1'0 + attribute \src "ls180.v:4309.2-4311.5" + switch $and$ls180.v:4309$720_Y + attribute \src "ls180.v:4309.6-4309.79" case 1'1 - assign { } { } - assign $3\dbus__we$next[0:0]$7242 1'0 + assign $0\main_uart_tx_clear[0:0] 1'1 case - assign $3\dbus__we$next[0:0]$7242 $1\dbus__we$next[0:0]$7240 end sync always - update \dbus__we$next $0\dbus__we$next[0:0]$7239 + update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] end - attribute \src "libresoc.v:149829.3-149854.6" - process $proc$libresoc.v:149829$7243 + attribute \src "ls180.v:4313.1-4317.4" + process $proc$ls180.v:4313$721 assign { } { } assign { } { } + assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status + assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status + sync always + update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:4318.1-4323.4" + process $proc$ls180.v:4318$722 assign { } { } - assign $0\dbus__dat_w$next[63:0]$7244 $3\dbus__dat_w$next[63:0]$7247 - attribute \src "libresoc.v:149830.5-149830.29" - switch \initial - attribute \src "libresoc.v:149830.9-149830.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbus__dat_w$next[63:0]$7245 $2\dbus__dat_w$next[63:0]$7246 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$79 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $2\dbus__dat_w$next[63:0]$7246 \dbus__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__dat_w$next[63:0]$7246 \x_st_data_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbus__dat_w$next[63:0]$7246 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\dbus__dat_w$next[63:0]$7245 \dbus__dat_w - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_uart_rx_clear[0:0] 1'0 + attribute \src "ls180.v:4320.2-4322.5" + switch $and$ls180.v:4320$723_Y + attribute \src "ls180.v:4320.6-4320.79" case 1'1 - assign { } { } - assign $3\dbus__dat_w$next[63:0]$7247 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_uart_rx_clear[0:0] 1'1 case - assign $3\dbus__dat_w$next[63:0]$7247 $1\dbus__dat_w$next[63:0]$7245 end sync always - update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7244 + update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] end - attribute \src "libresoc.v:149855.3-149877.6" - process $proc$libresoc.v:149855$7248 + attribute \src "ls180.v:4324.1-4328.4" + process $proc$ls180.v:4324$724 assign { } { } assign { } { } + assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending + assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending + sync always + update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:4346.1-4353.4" + process $proc$ls180.v:4346$732 assign { } { } - assign $0\m_load_err_o$next[0:0]$7249 $3\m_load_err_o$next[0:0]$7252 - attribute \src "libresoc.v:149856.5-149856.29" - switch \initial - attribute \src "libresoc.v:149856.9-149856.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4348.2-4352.5" + switch \main_uart_tx_fifo_replace + attribute \src "ls180.v:4348.6-4348.31" case 1'1 - assign { } { } - assign $1\m_load_err_o$next[0:0]$7250 $2\m_load_err_o$next[0:0]$7251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - switch { \$83 \$81 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\m_load_err_o$next[0:0]$7251 \$85 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\m_load_err_o$next[0:0]$7251 1'0 - case - assign $2\m_load_err_o$next[0:0]$7251 \m_load_err_o - end + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4349$733_Y + attribute \src "ls180.v:4350.6-4350.10" case - assign $1\m_load_err_o$next[0:0]$7250 \m_load_err_o + assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:4376.1-4383.4" + process $proc$ls180.v:4376$743 + assign { } { } + assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4378.2-4382.5" + switch \main_uart_rx_fifo_replace + attribute \src "ls180.v:4378.6-4378.31" case 1'1 - assign { } { } - assign $3\m_load_err_o$next[0:0]$7252 1'0 + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4379$744_Y + attribute \src "ls180.v:4380.6-4380.10" case - assign $3\m_load_err_o$next[0:0]$7252 $1\m_load_err_o$next[0:0]$7250 + assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce end sync always - update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7249 + update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "libresoc.v:149878.3-149900.6" - process $proc$libresoc.v:149878$7253 + attribute \src "ls180.v:4396.1-4400.4" + process $proc$ls180.v:4396$750 assign { } { } assign { } { } assign { } { } - assign $0\m_store_err_o$next[0:0]$7254 $3\m_store_err_o$next[0:0]$7257 - attribute \src "libresoc.v:149879.5-149879.29" - switch \initial - attribute \src "libresoc.v:149879.9-149879.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\m_store_err_o$next[0:0]$7255 $2\m_store_err_o$next[0:0]$7256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - switch { \$89 \$87 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\m_store_err_o$next[0:0]$7256 \dbus__we - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\m_store_err_o$next[0:0]$7256 1'0 - case - assign $2\m_store_err_o$next[0:0]$7256 \m_store_err_o - end - case - assign $1\m_store_err_o$next[0:0]$7255 \m_store_err_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\m_store_err_o$next[0:0]$7257 1'0 - case - assign $3\m_store_err_o$next[0:0]$7257 $1\m_store_err_o$next[0:0]$7255 - end + assign $0\gpio_o[15:0] \main_gpiotristateasic1_pads_o sync always - update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7254 + update \gpio_o $0\gpio_o[15:0] end - attribute \src "libresoc.v:149901.3-149920.6" - process $proc$libresoc.v:149901$7258 + attribute \src "ls180.v:4401.1-4405.4" + process $proc$ls180.v:4401$751 assign { } { } assign { } { } assign { } { } - assign $0\m_badaddr_o$next[44:0]$7259 $3\m_badaddr_o$next[44:0]$7262 - attribute \src "libresoc.v:149902.5-149902.29" - switch \initial - attribute \src "libresoc.v:149902.9-149902.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\m_badaddr_o$next[44:0]$7260 $2\m_badaddr_o$next[44:0]$7261 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - switch { \$93 \$91 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\m_badaddr_o$next[44:0]$7261 \dbus__adr + assign $0\gpio_oe[15:0] \main_gpiotristateasic1_pads_oe + sync always + update \gpio_oe $0\gpio_oe[15:0] + end + attribute \src "ls180.v:4417.1-4465.4" + process $proc$ls180.v:4417$756 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\main_spimaster25_clk_enable[0:0] 1'0 + assign $0\main_spimaster26_cs_enable[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'0 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster29_miso_latch[0:0] 1'0 + assign $0\main_spimaster3_irq[0:0] 1'0 + assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state + attribute \src "ls180.v:4428.2-4464.9" + switch \builder_spimaster0_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4432.4-4435.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4432.8-4432.33" + case 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spimaster25_clk_enable[0:0] 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4440.4-4446.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4440.8-4440.33" + case 1'1 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4441$757_Y + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4443.5-4445.8" + switch $eq$ls180.v:4443$759_Y + attribute \src "ls180.v:4443.9-4443.68" + case 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4450.4-4454.7" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:4450.8-4450.33" + case 1'1 + assign $0\main_spimaster29_miso_latch[0:0] 1'1 + assign $0\main_spimaster3_irq[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'00 case - assign $2\m_badaddr_o$next[44:0]$7261 \m_badaddr_o end + attribute \src "ls180.v:0.0-0.0" case - assign $1\m_badaddr_o$next[44:0]$7260 \m_badaddr_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\m_badaddr_o$next[44:0]$7262 45'000000000000000000000000000000000000000000000 - case - assign $3\m_badaddr_o$next[44:0]$7262 $1\m_badaddr_o$next[44:0]$7260 - end - sync always - update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7259 - end - connect \$9 $or$libresoc.v:149569$7149_Y - connect \$11 $not$libresoc.v:149570$7150_Y - connect \$13 $or$libresoc.v:149571$7151_Y - connect \$15 $or$libresoc.v:149572$7152_Y - connect \$17 $and$libresoc.v:149573$7153_Y - connect \$1 $or$libresoc.v:149574$7154_Y - connect \$19 $not$libresoc.v:149575$7155_Y - connect \$21 $and$libresoc.v:149576$7156_Y - connect \$23 $or$libresoc.v:149577$7157_Y - connect \$25 $not$libresoc.v:149578$7158_Y - connect \$27 $or$libresoc.v:149579$7159_Y - connect \$29 $or$libresoc.v:149580$7160_Y - connect \$31 $and$libresoc.v:149581$7161_Y - connect \$33 $not$libresoc.v:149582$7162_Y - connect \$35 $and$libresoc.v:149583$7163_Y - connect \$37 $or$libresoc.v:149584$7164_Y - connect \$3 $and$libresoc.v:149585$7165_Y - connect \$39 $not$libresoc.v:149586$7166_Y - connect \$41 $or$libresoc.v:149587$7167_Y - connect \$43 $or$libresoc.v:149588$7168_Y - connect \$45 $and$libresoc.v:149589$7169_Y - connect \$47 $not$libresoc.v:149590$7170_Y - connect \$49 $and$libresoc.v:149591$7171_Y - connect \$51 $or$libresoc.v:149592$7172_Y - connect \$53 $not$libresoc.v:149593$7173_Y - connect \$55 $or$libresoc.v:149594$7174_Y - connect \$57 $or$libresoc.v:149595$7175_Y - connect \$5 $not$libresoc.v:149596$7176_Y - connect \$59 $and$libresoc.v:149597$7177_Y - connect \$61 $not$libresoc.v:149598$7178_Y - connect \$63 $and$libresoc.v:149599$7179_Y - connect \$65 $or$libresoc.v:149600$7180_Y - connect \$67 $and$libresoc.v:149601$7181_Y - connect \$69 $not$libresoc.v:149602$7182_Y - connect \$71 $and$libresoc.v:149603$7183_Y - connect \$73 $or$libresoc.v:149604$7184_Y - connect \$75 $and$libresoc.v:149605$7185_Y - connect \$77 $not$libresoc.v:149606$7186_Y - connect \$7 $and$libresoc.v:149607$7187_Y - connect \$79 $and$libresoc.v:149608$7188_Y - connect \$81 $and$libresoc.v:149609$7189_Y - connect \$83 $not$libresoc.v:149610$7190_Y - connect \$85 $not$libresoc.v:149611$7191_Y - connect \$87 $and$libresoc.v:149612$7192_Y - connect \$89 $not$libresoc.v:149613$7193_Y - connect \$91 $and$libresoc.v:149614$7194_Y - connect \$93 $not$libresoc.v:149615$7195_Y - connect \$95 $or$libresoc.v:149616$7196_Y - connect \x_stall_i 1'0 - connect \m_stall_i 1'0 -end -attribute \src "libresoc.v:149927.1-150884.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" -attribute \generator "nMigen" -module \main - attribute \src "libresoc.v:150456.3-150478.6" - wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:150555.3-150581.6" - wire $0\a_lt[0:0] - attribute \src "libresoc.v:150836.3-150846.6" - wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:150806.3-150815.6" - wire width 66 $0\add_a[65:0] - attribute \src "libresoc.v:150816.3-150825.6" - wire width 66 $0\add_b[65:0] - attribute \src "libresoc.v:150826.3-150835.6" - wire width 66 $0\add_o[65:0] - attribute \src "libresoc.v:150694.3-150716.6" - wire width 64 $0\b_i[63:0] - attribute \src "libresoc.v:150680.3-150693.6" - wire width 2 $0\ca[1:0] - attribute \src "libresoc.v:150847.3-150857.6" - wire $0\carry_32[0:0] - attribute \src "libresoc.v:150858.3-150868.6" - wire $0\carry_64[0:0] - attribute \src "libresoc.v:150582.3-150607.6" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:150608.3-150622.6" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:150786.3-150805.6" - wire width 8 $0\eqs[7:0] - attribute \src "libresoc.v:149928.7-149928.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:150446.3-150455.6" - wire $0\is_32bit[0:0] - attribute \src "libresoc.v:150517.3-150535.6" - wire $0\msb_a[0:0] - attribute \src "libresoc.v:150536.3-150554.6" - wire $0\msb_b[0:0] - attribute \src "libresoc.v:150623.3-150660.6" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:150661.3-150679.6" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:150739.3-150752.6" - wire width 2 $0\ov[1:0] - attribute \src "libresoc.v:150775.3-150785.6" - wire width 8 $0\src1[7:0] - attribute \src "libresoc.v:150490.3-150516.6" - wire width 5 $0\tval[4:0] - attribute \src "libresoc.v:150717.3-150727.6" - wire width 2 $0\xer_ca$20[1:0]$7349 - attribute \src "libresoc.v:150728.3-150738.6" - wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:150753.3-150763.6" - wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:150764.3-150774.6" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:150479.3-150489.6" - wire $0\zerohi[0:0] - attribute \src "libresoc.v:150869.3-150879.6" - wire $0\zerolo[0:0] - attribute \src "libresoc.v:150456.3-150478.6" - wire width 64 $1\a_i[63:0] - attribute \src "libresoc.v:150555.3-150581.6" - wire $1\a_lt[0:0] - attribute \src "libresoc.v:150836.3-150846.6" - wire width 64 $1\a_n[63:0] - attribute \src "libresoc.v:150806.3-150815.6" - wire width 66 $1\add_a[65:0] - attribute \src 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\alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 36 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \alu_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \alu_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" - wire width 64 \b_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:150" - wire width 2 \ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" - wire \carry_32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" - wire \carry_64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 44 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 45 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire width 8 \eqs - attribute \src "libresoc.v:149928.7-149928.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" - wire \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:104" - wire \msb_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - wire \msb_b - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 42 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 43 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" - wire width 2 \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" - wire width 8 \src1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" - wire width 5 \tval - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 46 \xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 47 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 49 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 50 \xer_so$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" - wire \zerohi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" - wire \zerolo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" - cell $add $add$libresoc.v:150421$7310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 66 - parameter \B_SIGNED 0 - parameter \B_WIDTH 66 - parameter \Y_WIDTH 67 - connect \A \add_a - connect \B \add_b - connect \Y $add$libresoc.v:150421$7310_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:150395$7284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$113 - connect \B \$115 - connect \Y $and$libresoc.v:150395$7284_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:150399$7288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$121 - connect \B \$123 - connect \Y $and$libresoc.v:150399$7288_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:150432$7321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$69 - connect \Y $and$libresoc.v:150432$7321_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:150437$7326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$79 - connect \Y $and$libresoc.v:150437$7326_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:150440$7329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$85 - connect \Y $and$libresoc.v:150440$7329_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:150443$7332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$91 - connect \Y $and$libresoc.v:150443$7332_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:150386$7275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 1'1 - connect \Y $eq$libresoc.v:150386$7275_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - cell $eq $eq$libresoc.v:150387$7276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 2'10 - connect \Y $eq$libresoc.v:150387$7276_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - cell $eq $eq$libresoc.v:150388$7277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 3'100 - connect \Y $eq$libresoc.v:150388$7277_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:150400$7289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150400$7289_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:150401$7290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150401$7290_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:150402$7291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150402$7291_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:150403$7292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150403$7292_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:150404$7293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150404$7293_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:150405$7294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150405$7294_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:150406$7295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150406$7295_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:150407$7296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150407$7296_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - cell $eq $eq$libresoc.v:150408$7297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:150408$7297_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:150410$7299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:150410$7299_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:150411$7300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:150411$7300_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:150412$7301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $eq$libresoc.v:150412$7301_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:150413$7302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:150413$7302_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:150415$7304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $eq$libresoc.v:150415$7304_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:150416$7305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:150416$7305_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:150418$7307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $eq$libresoc.v:150418$7307_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:150419$7308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:150419$7308_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:150433$7322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_a - connect \B \msb_b - connect \Y $ne$libresoc.v:150433$7322_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:150444$7333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_a - connect \B \msb_b - connect \Y $ne$libresoc.v:150444$7333_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:150394$7283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$116 - connect \Y $not$libresoc.v:150394$7283_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:150398$7287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$124 - connect \Y $not$libresoc.v:150398$7287_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - cell $not $not$libresoc.v:150409$7298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn [21] - connect \Y $not$libresoc.v:150409$7298_Y + assign $0\main_spimaster2_done[0:0] 1'1 + attribute \src "ls180.v:4458.4-4462.7" + switch \main_spimaster0_start + attribute \src "ls180.v:4458.8-4458.29" + case 1'1 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spimaster2_done $0\main_spimaster2_done[0:0] + update \main_spimaster3_irq $0\main_spimaster3_irq[0:0] + update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0] + update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0] + update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0] + update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0] + update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] + update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] + update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$libresoc.v:150422$7311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $not$libresoc.v:150422$7311_Y + attribute \src "ls180.v:4476.1-4524.4" + process $proc$ls180.v:4476$764 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spisdcard_clk_enable[0:0] 1'0 + assign $0\main_spisdcard_cs_enable[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'0 + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_miso_latch[0:0] 1'0 + assign $0\main_spisdcard_irq[0:0] 1'0 + assign { } { } + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state + attribute \src "ls180.v:4487.2-4523.9" + switch \builder_spimaster1_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4491.4-4494.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4491.8-4491.31" + case 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spisdcard_clk_enable[0:0] 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4499.4-4505.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4499.8-4499.31" + case 1'1 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4500$765_Y + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4502.5-4504.8" + switch $eq$ls180.v:4502$767_Y + attribute \src "ls180.v:4502.9-4502.66" + case 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4509.4-4513.7" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:4509.8-4509.31" + case 1'1 + assign $0\main_spisdcard_miso_latch[0:0] 1'1 + assign $0\main_spisdcard_irq[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spisdcard_done0[0:0] 1'1 + attribute \src "ls180.v:4517.4-4521.7" + switch \main_spisdcard_start0 + attribute \src "ls180.v:4517.8-4517.29" + case 1'1 + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0] + update \main_spisdcard_irq $0\main_spisdcard_irq[0:0] + update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0] + update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0] + update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0] + update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0] + update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] + update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] + update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $not $not$libresoc.v:150427$7316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$58 - connect \Y $not$libresoc.v:150427$7316_Y + attribute \src "ls180.v:453.12-453.46" + process $proc$ls180.v:453$3229 + assign { } { } + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $not $not$libresoc.v:150430$7319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$64 - connect \Y $not$libresoc.v:150430$7319_Y + attribute \src "ls180.v:454.11-454.47" + process $proc$ls180.v:454$3230 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:150434$7323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_lt - connect \Y $not$libresoc.v:150434$7323_Y + attribute \src "ls180.v:4556.1-4584.4" + process $proc$ls180.v:4556$789 + assign { } { } + assign $0\main_sdphy_clocker_clk1[0:0] 1'0 + attribute \src "ls180.v:4558.2-4583.9" + switch \main_sdphy_clocker_storage + attribute \src "ls180.v:0.0-0.0" + case 9'000000100 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] + attribute \src "ls180.v:0.0-0.0" + case 9'000001000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] + attribute \src "ls180.v:0.0-0.0" + case 9'000010000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] + attribute \src "ls180.v:0.0-0.0" + case 9'000100000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] + attribute \src "ls180.v:0.0-0.0" + case 9'001000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] + attribute \src "ls180.v:0.0-0.0" + case 9'010000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] + attribute \src "ls180.v:0.0-0.0" + case 9'100000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] + end + sync always + update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:150435$7324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_lt - connect \Y $not$libresoc.v:150435$7324_Y + attribute \src "ls180.v:456.12-456.45" + process $proc$ls180.v:456$3231 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:150414$7303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$30 - connect \B \$32 - connect \Y $or$libresoc.v:150414$7303_Y + attribute \src "ls180.v:457.11-457.40" + process $proc$ls180.v:457$3232 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:150417$7306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$36 - connect \B \$38 - connect \Y $or$libresoc.v:150417$7306_Y + attribute \src "ls180.v:458.5-458.35" + process $proc$ls180.v:458$3233 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:150420$7309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$42 - connect \B \$44 - connect \Y $or$libresoc.v:150420$7309_Y + attribute \src "ls180.v:4586.1-4619.4" + process $proc$ls180.v:4586$792 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:4596.2-4618.9" + switch \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4603.4-4609.7" + switch \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:4603.8-4603.38" + case 1'1 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4604$793_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4606.5-4608.8" + switch $eq$ls180.v:4606$794_Y + attribute \src "ls180.v:4606.9-4606.41" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4614.4-4616.7" + switch \main_sdphy_init_initialize_re + attribute \src "ls180.v:4614.8-4614.37" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] + update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] + update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:150431$7320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $or$libresoc.v:150431$7320_Y + attribute \src "ls180.v:459.5-459.34" + process $proc$ls180.v:459$3234 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:150436$7325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $or$libresoc.v:150436$7325_Y + attribute \src "ls180.v:460.5-460.35" + process $proc$ls180.v:460$3235 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:150439$7328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $or$libresoc.v:150439$7328_Y + attribute \src "ls180.v:461.5-461.34" + process $proc$ls180.v:461$3236 + assign { } { } + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:150442$7331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $or$libresoc.v:150442$7331_Y + attribute \src "ls180.v:4620.1-4696.4" + process $proc$ls180.v:4620$795 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdw_done[0:0] 1'0 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:4630.2-4695.9" + switch \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + attribute \src "ls180.v:4634.4-4659.11" + switch \main_sdphy_cmdw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] + attribute \src "ls180.v:0.0-0.0" + case 8'00000010 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] + attribute \src "ls180.v:0.0-0.0" + case 8'00000011 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000100 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] + attribute \src "ls180.v:0.0-0.0" + case 8'00000101 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] + attribute \src "ls180.v:0.0-0.0" + case 8'00000110 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] + attribute \src "ls180.v:0.0-0.0" + case 8'00000111 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] + case + end + attribute \src "ls180.v:4660.4-4671.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4660.8-4660.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4661$796_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4663.5-4670.8" + switch $eq$ls180.v:4663$797_Y + attribute \src "ls180.v:4663.9-4663.40" + case 1'1 + attribute \src "ls180.v:4664.6-4669.9" + switch \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:4664.10-4664.35" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 + attribute \src "ls180.v:4666.10-4666.14" + case + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4677.4-4684.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4677.8-4677.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4678$798_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4680.5-4683.8" + switch $eq$ls180.v:4680$799_Y + attribute \src "ls180.v:4680.9-4680.40" + case 1'1 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4689.4-4693.7" + switch $and$ls180.v:4689$800_Y + attribute \src "ls180.v:4689.8-4689.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 + attribute \src "ls180.v:4691.8-4691.12" + case + assign $0\main_sdphy_cmdw_done[0:0] 1'1 + end + end + sync always + update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] + update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] + update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" - cell $reduce_or $reduce_or$libresoc.v:150385$7274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $reduce_or$libresoc.v:150385$7274_Y + attribute \src "ls180.v:465.5-465.35" + process $proc$ls180.v:465$3237 + assign { } { } + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" - cell $reduce_or $reduce_or$libresoc.v:150389$7278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $reduce_or$libresoc.v:150389$7278_Y + attribute \src "ls180.v:467.5-467.39" + process $proc$ls180.v:467$3238 + assign { } { } + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $reduce_or $reduce_or$libresoc.v:150426$7315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \$59 - connect \Y $reduce_or$libresoc.v:150426$7315_Y + attribute \src "ls180.v:469.5-469.39" + process $proc$ls180.v:469$3239 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $reduce_or $reduce_or$libresoc.v:150429$7318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \$65 - connect \Y $reduce_or$libresoc.v:150429$7318_Y + attribute \src "ls180.v:472.5-472.32" + process $proc$ls180.v:472$3240 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" - cell $mux $ternary$libresoc.v:150438$7327 - parameter \WIDTH 1 - connect \A \a_n [63] - connect \B \a_n [31] - connect \S \is_32bit - connect \Y $ternary$libresoc.v:150438$7327_Y + attribute \src "ls180.v:473.5-473.32" + process $proc$ls180.v:473$3241 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $mux $ternary$libresoc.v:150441$7330 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \is_32bit - connect \Y $ternary$libresoc.v:150441$7330_Y + attribute \src "ls180.v:4730.1-4823.4" + process $proc$ls180.v:4730$809 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign { } { } + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:4748.2-4822.9" + switch \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4756$810_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4753.4-4755.7" + switch \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:4753.8-4753.49" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4758.4-4761.7" + switch $eq$ls180.v:4758$811_Y + attribute \src "ls180.v:4758.8-4758.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4767$813_Y + assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4784$816_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4769.4-4783.7" + switch $and$ls180.v:4769$814_Y + attribute \src "ls180.v:4769.8-4769.69" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4771$815_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4773.5-4782.8" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:4773.9-4773.36" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4775.6-4781.9" + switch \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:4775.10-4775.35" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 + attribute \src "ls180.v:4779.10-4779.14" + case + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + end + case + end + case + end + attribute \src "ls180.v:4786.4-4789.7" + switch $eq$ls180.v:4786$817_Y + attribute \src "ls180.v:4786.8-4786.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4795.4-4801.7" + switch \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:4795.8-4795.38" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4796$818_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4798.5-4800.8" + switch $eq$ls180.v:4798$819_Y + attribute \src "ls180.v:4798.9-4798.40" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 + attribute \src "ls180.v:4807.4-4809.7" + switch $and$ls180.v:4807$820_Y + attribute \src "ls180.v:4807.8-4807.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4816.4-4820.7" + switch $and$ls180.v:4816$822_Y + attribute \src "ls180.v:4816.8-4816.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] + update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] + update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] + update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] + update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] + update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - cell $mux $ternary$libresoc.v:150445$7334 - parameter \WIDTH 1 - connect \A \carry_64 - connect \B \carry_32 - connect \S \is_32bit - connect \Y $ternary$libresoc.v:150445$7334_Y + attribute \src "ls180.v:474.5-474.31" + process $proc$ls180.v:474$3242 + assign { } { } + assign $1\main_sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:150390$7279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [32] - connect \B \b_i [32] - connect \Y $xor$libresoc.v:150390$7279_Y + attribute \src "ls180.v:475.12-475.44" + process $proc$ls180.v:475$3243 + assign { } { } + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:150391$7280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \add_o [33] - connect \B \$109 - connect \Y $xor$libresoc.v:150391$7280_Y + attribute \src "ls180.v:476.11-476.43" + process $proc$ls180.v:476$3244 + assign { } { } + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:150392$7281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ca [0] - connect \B \add_o [64] - connect \Y $xor$libresoc.v:150392$7281_Y + attribute \src "ls180.v:477.5-477.38" + process $proc$ls180.v:477$3245 + assign { } { } + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:150393$7282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [63] - connect \B \b_i [63] - connect \Y $xor$libresoc.v:150393$7282_Y + attribute \src "ls180.v:478.5-478.38" + process $proc$ls180.v:478$3246 + assign { } { } + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:150396$7285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ca [1] - connect \B \add_o [32] - connect \Y $xor$libresoc.v:150396$7285_Y + attribute \src "ls180.v:479.5-479.37" + process $proc$ls180.v:479$3247 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:150397$7286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [31] - connect \B \b_i [31] - connect \Y $xor$libresoc.v:150397$7286_Y + attribute \src "ls180.v:480.5-480.42" + process $proc$ls180.v:480$3248 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:150423$7312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \add_o [33] - connect \B \ra [32] - connect \Y $xor$libresoc.v:150423$7312_Y + attribute \src "ls180.v:481.5-481.43" + process $proc$ls180.v:481$3249 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:150424$7313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$53 - connect \B \rb [32] - connect \Y $xor$libresoc.v:150424$7313_Y + attribute \src "ls180.v:4857.1-4884.4" + process $proc$ls180.v:4857$830 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_dataw_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:4865.2-4883.9" + switch \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 + attribute \src "ls180.v:4870.4-4874.7" + switch \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:4870.8-4870.50" + case 1'1 + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4871$831_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4872$832_Y + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:4877.4-4881.7" + switch \main_sdphy_dataw_start + attribute \src "ls180.v:4877.8-4877.30" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] + update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] + update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $xor $xor$libresoc.v:150425$7314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \a_n [31:0] - connect \B \rb [31:0] - connect \Y $xor$libresoc.v:150425$7314_Y + attribute \src "ls180.v:487.11-487.44" + process $proc$ls180.v:487$3250 + assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $xor $xor$libresoc.v:150428$7317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \a_n [63:32] - connect \B \rb [63:32] - connect \Y $xor$libresoc.v:150428$7317_Y + attribute \src "ls180.v:4885.1-4957.4" + process $proc$ls180.v:4885$833 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_start[0:0] 1'0 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state + attribute \src "ls180.v:4896.2-4956.9" + switch \builder_sdphy_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + attribute \src "ls180.v:4901.4-4903.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4901.8-4901.39" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4906$834_Y + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + attribute \src "ls180.v:4909.4-4916.11" + switch \main_sdphy_dataw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] + case + end + attribute \src "ls180.v:4917.4-4929.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4917.8-4917.39" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4918$835_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4920.5-4928.8" + switch $eq$ls180.v:4920$836_Y + attribute \src "ls180.v:4920.9-4920.41" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4923.6-4927.9" + switch \main_sdphy_dataw_sink_last + attribute \src "ls180.v:4923.10-4923.36" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:4925.10-4925.14" + case + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4935.4-4938.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4935.8-4935.39" + case 1'1 + assign $0\main_sdphy_dataw_start[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4942.4-4947.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4942.8-4942.39" + case 1'1 + attribute \src "ls180.v:4943.5-4946.8" + switch \main_sdphy_dataw_pads_in_payload_data_i [0] + attribute \src "ls180.v:4943.9-4943.51" + case 1'1 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4952.4-4954.7" + switch $and$ls180.v:4952$837_Y + attribute \src "ls180.v:4952.8-4952.71" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] + update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] + update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] + update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "libresoc.v:149928.7-149928.20" - process $proc$libresoc.v:149928$7364 + attribute \src "ls180.v:489.5-489.38" + process $proc$ls180.v:489$3251 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\main_sdram_postponer_req_o[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] end - attribute \src "libresoc.v:150446.3-150455.6" - process $proc$libresoc.v:150446$7335 + attribute \src "ls180.v:490.5-490.38" + process $proc$ls180.v:490$3252 assign { } { } + assign $1\main_sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "ls180.v:491.5-491.39" + process $proc$ls180.v:491$3253 assign { } { } - assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:150447.5-150447.29" - switch \initial - attribute \src "libresoc.v:150447.9-150447.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - switch \$22 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\is_32bit[0:0] \$24 - case - assign $1\is_32bit[0:0] 1'0 - end + assign $1\main_sdram_sequencer_start0[0:0] 1'0 sync always - update \is_32bit $0\is_32bit[0:0] + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] end - attribute \src "libresoc.v:150456.3-150478.6" - process $proc$libresoc.v:150456$7336 + attribute \src "ls180.v:494.5-494.38" + process $proc$ls180.v:494$3254 assign { } { } - assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:150457.5-150457.29" - switch \initial - attribute \src "libresoc.v:150457.9-150457.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - switch { \is_32bit \$26 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\a_i[63:0] \ra - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\a_i[63:0] $2\a_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - switch \alu_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\a_i[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\a_i[63:0] { 32'00000000000000000000000000000000 \ra [31:0] } - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\a_i[63:0] \ra - end + assign $1\main_sdram_sequencer_done1[0:0] 1'0 sync always - update \a_i $0\a_i[63:0] + sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] end - attribute \src "libresoc.v:150479.3-150489.6" - process $proc$libresoc.v:150479$7337 + attribute \src "ls180.v:495.11-495.46" + process $proc$ls180.v:495$3255 assign { } { } + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + sync always + sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + end + attribute \src "ls180.v:496.5-496.38" + process $proc$ls180.v:496$3256 assign { } { } - assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:150480.5-150480.29" - switch \initial - attribute \src "libresoc.v:150480.9-150480.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\zerohi[0:0] \$63 - case - assign $1\zerohi[0:0] 1'0 - end + assign $1\main_sdram_sequencer_count[0:0] 1'0 sync always - update \zerohi $0\zerohi[0:0] + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] end - attribute \src "libresoc.v:150490.3-150516.6" - process $proc$libresoc.v:150490$7338 + attribute \src "ls180.v:4991.1-5092.4" + process $proc$ls180.v:4991$845 assign { } { } assign { } { } - assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:150491.5-150491.29" - switch \initial - attribute \src "libresoc.v:150491.9-150491.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:5008.2-5091.9" + switch \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 assign { } { } - assign $1\tval[4:0] $2\tval[4:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - switch \$71 - attribute \src "libresoc.v:0.0-0.0" + assign { } { } + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5018$847_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:5015.4-5017.7" + switch \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:5015.8-5015.51" case 1'1 - assign { $2\tval[4:0] [4:3] $2\tval[4:0] [1:0] } 4'0000 - assign $2\tval[4:0] [2] 1'1 - attribute \src "libresoc.v:0.0-0.0" + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 case - assign { } { } - assign $2\tval[4:0] $3\tval[4:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - switch \$73 - attribute \src "libresoc.v:0.0-0.0" + end + attribute \src "ls180.v:5020.4-5023.7" + switch $eq$ls180.v:5020$848_Y + attribute \src "ls180.v:5020.8-5020.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:5029$851_Y + assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5050$853_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:5031.4-5049.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5031.8-5031.37" + case 1'1 + attribute \src "ls180.v:5032.5-5048.8" + switch \main_sdphy_datar_source_ready + attribute \src "ls180.v:5032.9-5032.38" case 1'1 - assign { } { } - assign $3\tval[4:0] { \msb_a \msb_b 1'0 \msb_b \msb_a } - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5034$852_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5036.6-5045.9" + switch \main_sdphy_datar_source_last + attribute \src "ls180.v:5036.10-5036.38" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + attribute \src "ls180.v:5038.7-5044.10" + switch \main_sdphy_datar_sink_last + attribute \src "ls180.v:5038.11-5038.37" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 + attribute \src "ls180.v:5042.11-5042.15" + case + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + end + case + end + attribute \src "ls180.v:5046.9-5046.13" case - assign { } { } - assign $3\tval[4:0] { \a_lt \$77 1'0 \a_lt \$75 } + assign $0\main_sdphy_datar_stop[0:0] 1'1 end + case end - case - assign $1\tval[4:0] 5'00000 - end - sync always - update \tval $0\tval[4:0] - end - attribute \src "libresoc.v:150517.3-150535.6" - process $proc$libresoc.v:150517$7339 - assign { } { } - assign { } { } - assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:150518.5-150518.29" - switch \initial - attribute \src "libresoc.v:150518.9-150518.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\msb_a[0:0] $2\msb_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - switch \$81 - attribute \src "libresoc.v:0.0-0.0" + attribute \src "ls180.v:5052.4-5055.7" + switch $eq$ls180.v:5052$854_Y + attribute \src "ls180.v:5052.8-5052.42" case 1'1 - assign $2\msb_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 case - assign { } { } - assign $2\msb_a[0:0] \$83 end - case - assign $1\msb_a[0:0] 1'0 - end - sync always - update \msb_a $0\msb_a[0:0] - end - attribute \src "libresoc.v:150536.3-150554.6" - process $proc$libresoc.v:150536$7340 - assign { } { } - assign { } { } - assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:150537.5-150537.29" - switch \initial - attribute \src "libresoc.v:150537.9-150537.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\msb_b[0:0] $2\msb_b[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - switch \$87 - attribute \src "libresoc.v:0.0-0.0" + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:5059.4-5065.7" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:5059.8-5059.39" case 1'1 - assign $2\msb_b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5060$855_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5062.5-5064.8" + switch $eq$ls180.v:5062$856_Y + attribute \src "ls180.v:5062.9-5062.42" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end case - assign { } { } - assign $2\msb_b[0:0] \$89 end - case - assign $1\msb_b[0:0] 1'0 - end - sync always - update \msb_b $0\msb_b[0:0] - end - attribute \src "libresoc.v:150555.3-150581.6" - process $proc$libresoc.v:150555$7341 - assign { } { } - assign { } { } - assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:150556.5-150556.29" - switch \initial - attribute \src "libresoc.v:150556.9-150556.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\a_lt[0:0] $2\a_lt[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_source_valid[0:0] 1'1 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_datar_source_last[0:0] 1'1 + attribute \src "ls180.v:5071.4-5073.7" + switch $and$ls180.v:5071$857_Y + attribute \src "ls180.v:5071.8-5071.71" case 1'1 - assign $2\a_lt[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case - assign { } { } - assign $2\a_lt[0:0] $3\a_lt[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - switch \$95 - attribute \src "libresoc.v:0.0-0.0" + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5078.4-5089.7" + switch $and$ls180.v:5078$858_Y + attribute \src "ls180.v:5078.8-5078.71" + case 1'1 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:5080.5-5088.8" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:5080.9-5080.40" case 1'1 - assign $3\a_lt[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 case - assign { } { } - assign $3\a_lt[0:0] \$97 end + case end - case - assign $1\a_lt[0:0] 1'0 end sync always - update \a_lt $0\a_lt[0:0] + update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] + update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] + update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] + update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] + update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] + update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] + update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] + update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] + update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "libresoc.v:150582.3-150607.6" - process $proc$libresoc.v:150582$7342 + attribute \src "ls180.v:502.5-502.51" + process $proc$ls180.v:502$3257 assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:503.5-503.51" + process $proc$ls180.v:503$3258 assign { } { } - assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:150583.5-150583.29" - switch \initial - attribute \src "libresoc.v:150583.9-150583.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } - assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" - switch \alu_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a[3:2] \tval [4:3] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_a[3:2] \tval [1:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\cr_a[3:0] { 1'0 \$99 2'00 } - case - assign $1\cr_a[3:0] 4'0000 - end + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always - update \cr_a $0\cr_a[3:0] + sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] end - attribute \src "libresoc.v:150608.3-150622.6" - process $proc$libresoc.v:150608$7343 + attribute \src "ls180.v:505.5-505.47" + process $proc$ls180.v:505$3259 assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:506.5-506.45" + process $proc$ls180.v:506$3260 assign { } { } - assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:150609.5-150609.29" - switch \initial - attribute \src "libresoc.v:150609.9-150609.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\cr_a_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\cr_a_ok[0:0] 1'1 - case - assign $1\cr_a_ok[0:0] 1'0 - end + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 sync always - update \cr_a_ok $0\cr_a_ok[0:0] + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] end - attribute \src "libresoc.v:150623.3-150660.6" - process $proc$libresoc.v:150623$7344 + attribute \src "ls180.v:507.5-507.45" + process $proc$ls180.v:507$3261 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:508.12-508.57" + process $proc$ls180.v:508$3262 assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:150624.5-150624.29" - switch \initial - attribute \src "libresoc.v:150624.9-150624.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\o[63:0] \add_o [64:1] - attribute \src "libresoc.v:0.0-0.0" - case 7'0011111 - assign { } { } - assign { } { } - assign { } { } - assign $1\o[63:0] $4\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - switch \$101 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o[63:0] { \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7:0] } - case - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - switch \$103 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\o[63:0] { \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15:0] } - case - assign $3\o[63:0] $2\o[63:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - switch \$105 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\o[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } - case - assign $4\o[63:0] $3\o[63:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign $1\o[63:0] [63:1] 63'000000000000000000000000000000000000000000000000000000000000000 - assign $1\o[63:0] [0] \$107 - case - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 sync always - update \o $0\o[63:0] + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "libresoc.v:150661.3-150679.6" - process $proc$libresoc.v:150661$7345 + attribute \src "ls180.v:510.5-510.51" + process $proc$ls180.v:510$3263 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:511.5-511.51" + process $proc$ls180.v:511$3264 assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:150662.5-150662.29" - switch \initial - attribute \src "libresoc.v:150662.9-150662.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0011111 - assign { } { } - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\o_ok[0:0] 1'0 - case - assign $1\o_ok[0:0] 1'0 - end + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 sync always - update \o_ok $0\o_ok[0:0] + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] end - attribute \src "libresoc.v:150680.3-150693.6" - process $proc$libresoc.v:150680$7346 + attribute \src "ls180.v:512.5-512.50" + process $proc$ls180.v:512$3265 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:513.5-513.54" + process $proc$ls180.v:513$3266 assign { } { } - assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:150681.5-150681.29" - switch \initial - attribute \src "libresoc.v:150681.9-150681.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\ca[1:0] [0] \add_o [65] - assign $1\ca[1:0] [1] \$111 - case - assign $1\ca[1:0] 2'00 - end + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 sync always - update \ca $0\ca[1:0] + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] end - attribute \src "libresoc.v:150694.3-150716.6" - process $proc$libresoc.v:150694$7347 + attribute \src "ls180.v:514.5-514.55" + process $proc$ls180.v:514$3267 assign { } { } - assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:150695.5-150695.29" - switch \initial - attribute \src "libresoc.v:150695.9-150695.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - switch { \is_32bit \$28 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\b_i[63:0] \rb - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\b_i[63:0] $2\b_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - switch \alu_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\b_i[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\b_i[63:0] { 32'00000000000000000000000000000000 \rb [31:0] } - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\b_i[63:0] \rb - end + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 sync always - update \b_i $0\b_i[63:0] + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] end - attribute \src "libresoc.v:150717.3-150727.6" - process $proc$libresoc.v:150717$7348 + attribute \src "ls180.v:515.5-515.56" + process $proc$ls180.v:515$3268 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:5150.1-5157.4" + process $proc$ls180.v:5150$980 assign { } { } - assign $0\xer_ca$20[1:0]$7349 $1\xer_ca$20[1:0]$7350 - attribute \src "libresoc.v:150718.5-150718.29" - switch \initial - attribute \src "libresoc.v:150718.9-150718.17" + assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + attribute \src "ls180.v:5152.2-5156.5" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:5152.6-5152.38" case 1'1 + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:5154.6-5154.10" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ca$20[1:0]$7350 \ca - case - assign $1\xer_ca$20[1:0]$7350 2'00 + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 end sync always - update \xer_ca$20 $0\xer_ca$20[1:0]$7349 + update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "libresoc.v:150728.3-150738.6" - process $proc$libresoc.v:150728$7351 + attribute \src "ls180.v:516.5-516.50" + process $proc$ls180.v:516$3269 assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:5172.1-5179.4" + process $proc$ls180.v:5172$1003 assign { } { } - assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:150729.5-150729.29" - switch \initial - attribute \src "libresoc.v:150729.9-150729.17" + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5174.2-5178.5" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:5174.6-5174.44" case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:5176.6-5176.10" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'1 - case - assign $1\xer_ca_ok[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 end sync always - update \xer_ca_ok $0\xer_ca_ok[0:0] + update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "libresoc.v:150739.3-150752.6" - process $proc$libresoc.v:150739$7352 - assign { } { } + attribute \src "ls180.v:5182.1-5189.4" + process $proc$ls180.v:5182$1014 assign { } { } - assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:150740.5-150740.29" - switch \initial - attribute \src "libresoc.v:150740.9-150740.17" + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5184.2-5188.5" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:5184.6-5184.44" case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:5186.6-5186.10" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\ov[1:0] [0] \$119 - assign $1\ov[1:0] [1] \$127 - case - assign $1\ov[1:0] 2'00 + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 end sync always - update \ov $0\ov[1:0] + update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "libresoc.v:150753.3-150763.6" - process $proc$libresoc.v:150753$7353 + attribute \src "ls180.v:519.5-519.67" + process $proc$ls180.v:519$3270 assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:5192.1-5199.4" + process $proc$ls180.v:5192$1025 assign { } { } - assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:150754.5-150754.29" - switch \initial - attribute \src "libresoc.v:150754.9-150754.17" + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5194.2-5198.5" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:5194.6-5194.44" case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:5196.6-5196.10" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ov[1:0] \ov - case - assign $1\xer_ov[1:0] 2'00 + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 end sync always - update \xer_ov $0\xer_ov[1:0] + update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "libresoc.v:150764.3-150774.6" - process $proc$libresoc.v:150764$7354 + attribute \src "ls180.v:520.5-520.66" + process $proc$ls180.v:520$3271 assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:5202.1-5209.4" + process $proc$ls180.v:5202$1036 assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:150765.5-150765.29" - switch \initial - attribute \src "libresoc.v:150765.9-150765.17" + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5204.2-5208.5" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:5204.6-5204.44" case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:5206.6-5206.10" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 - case - assign $1\xer_ov_ok[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 end sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] + update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "libresoc.v:150775.3-150785.6" - process $proc$libresoc.v:150775$7355 + attribute \src "ls180.v:5210.1-5289.4" + process $proc$ls180.v:5210$1037 assign { } { } assign { } { } - assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:150776.5-150776.29" - switch \initial - attribute \src "libresoc.v:150776.9-150776.17" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:5227.2-5288.9" + switch \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:0.0-0.0" case 1'1 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 + attribute \src "ls180.v:5231.4-5233.7" + switch $eq$ls180.v:5231$1038_Y + attribute \src "ls180.v:5231.8-5231.48" + case 1'1 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 + case + end + attribute \src "ls180.v:5234.4-5259.11" + switch \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } + case + end + attribute \src "ls180.v:5260.4-5267.7" + switch \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:5260.8-5260.47" + case 1'1 + attribute \src "ls180.v:5261.5-5266.8" + switch $eq$ls180.v:5261$1039_Y + attribute \src "ls180.v:5261.9-5261.49" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + attribute \src "ls180.v:5263.9-5263.13" + case + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5264$1040_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + end + case + end + attribute \src "ls180.v:0.0-0.0" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\src1[7:0] \ra [7:0] - case - assign $1\src1[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5282.4-5286.7" + switch $and$ls180.v:5282$1042_Y + attribute \src "ls180.v:5282.8-5282.128" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + case + end end sync always - update \src1 $0\src1[7:0] + update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] + update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] + update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] + update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "libresoc.v:150786.3-150805.6" - process $proc$libresoc.v:150786$7356 - assign { } { } + attribute \src "ls180.v:5290.1-5295.4" + process $proc$ls180.v:5290$1043 assign { } { } - assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:150787.5-150787.29" - switch \initial - attribute \src "libresoc.v:150787.9-150787.17" + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 + attribute \src "ls180.v:5292.2-5294.5" + switch $and$ls180.v:5292$1050_Y + attribute \src "ls180.v:5292.6-5292.301" case 1'1 + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\eqs[7:0] [0] \$129 - assign $1\eqs[7:0] [1] \$131 - assign $1\eqs[7:0] [2] \$133 - assign $1\eqs[7:0] [3] \$135 - assign $1\eqs[7:0] [4] \$137 - assign $1\eqs[7:0] [5] \$139 - assign $1\eqs[7:0] [6] \$141 - assign $1\eqs[7:0] [7] \$143 - case - assign $1\eqs[7:0] 8'00000000 - end sync always - update \eqs $0\eqs[7:0] + update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "libresoc.v:150806.3-150815.6" - process $proc$libresoc.v:150806$7357 - assign { } { } + attribute \src "ls180.v:5298.1-5305.4" + process $proc$ls180.v:5298$1052 assign { } { } - assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:150807.5-150807.29" - switch \initial - attribute \src "libresoc.v:150807.9-150807.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - switch \$34 - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + attribute \src "ls180.v:5300.2-5304.5" + switch $eq$ls180.v:5300$1053_Y + attribute \src "ls180.v:5300.6-5300.45" case 1'1 - assign { } { } - assign $1\add_a[65:0] { 1'0 \a_i \xer_ca [0] } + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 + attribute \src "ls180.v:5302.6-5302.10" case - assign $1\add_a[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 end sync always - update \add_a $0\add_a[65:0] + update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "libresoc.v:150816.3-150825.6" - process $proc$libresoc.v:150816$7358 - assign { } { } + attribute \src "ls180.v:5308.1-5315.4" + process $proc$ls180.v:5308$1055 assign { } { } - assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:150817.5-150817.29" - switch \initial - attribute \src "libresoc.v:150817.9-150817.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - switch \$40 - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + attribute \src "ls180.v:5310.2-5314.5" + switch $eq$ls180.v:5310$1056_Y + attribute \src "ls180.v:5310.6-5310.45" case 1'1 - assign { } { } - assign $1\add_b[65:0] { 1'0 \b_i 1'1 } + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 + attribute \src "ls180.v:5312.6-5312.10" case - assign $1\add_b[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 end sync always - update \add_b $0\add_b[65:0] + update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "libresoc.v:150826.3-150835.6" - process $proc$libresoc.v:150826$7359 - assign { } { } + attribute \src "ls180.v:5318.1-5325.4" + process $proc$ls180.v:5318$1058 assign { } { } - assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:150827.5-150827.29" - switch \initial - attribute \src "libresoc.v:150827.9-150827.17" + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + attribute \src "ls180.v:5320.2-5324.5" + switch $eq$ls180.v:5320$1059_Y + attribute \src "ls180.v:5320.6-5320.45" case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 + attribute \src "ls180.v:5322.6-5322.10" case + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - switch \$46 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:5328.1-5335.4" + process $proc$ls180.v:5328$1061 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + attribute \src "ls180.v:5330.2-5334.5" + switch $eq$ls180.v:5330$1062_Y + attribute \src "ls180.v:5330.6-5330.45" case 1'1 - assign { } { } - assign $1\add_o[65:0] \$48 [65:0] + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 + attribute \src "ls180.v:5332.6-5332.10" case - assign $1\add_o[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 end sync always - update \add_o $0\add_o[65:0] + update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "libresoc.v:150836.3-150846.6" - process $proc$libresoc.v:150836$7360 - assign { } { } + attribute \src "ls180.v:5337.1-5342.4" + process $proc$ls180.v:5337$1063 assign { } { } - assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:150837.5-150837.29" - switch \initial - attribute \src "libresoc.v:150837.9-150837.17" + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + attribute \src "ls180.v:5339.2-5341.5" + switch $and$ls180.v:5339$1065_Y + attribute \src "ls180.v:5339.6-5339.85" case 1'1 + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\a_n[63:0] \$51 - case - assign $1\a_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end sync always - update \a_n $0\a_n[63:0] + update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "libresoc.v:150847.3-150857.6" - process $proc$libresoc.v:150847$7361 - assign { } { } + attribute \src "ls180.v:5343.1-5350.4" + process $proc$ls180.v:5343$1066 assign { } { } - assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "libresoc.v:150848.5-150848.29" - switch \initial - attribute \src "libresoc.v:150848.9-150848.17" + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + attribute \src "ls180.v:5345.2-5349.5" + switch $lt$ls180.v:5345$1067_Y + attribute \src "ls180.v:5345.6-5345.44" case 1'1 + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 + attribute \src "ls180.v:5347.6-5347.10" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\carry_32[0:0] \$55 - case - assign $1\carry_32[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready end sync always - update \carry_32 $0\carry_32[0:0] + update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "libresoc.v:150858.3-150868.6" - process $proc$libresoc.v:150858$7362 + attribute \src "ls180.v:535.11-535.68" + process $proc$ls180.v:535$3272 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:5354.1-5361.4" + process $proc$ls180.v:5354$1078 assign { } { } - assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "libresoc.v:150859.5-150859.29" - switch \initial - attribute \src "libresoc.v:150859.9-150859.17" + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5356.2-5360.5" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:5356.6-5356.43" case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:5358.6-5358.10" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\carry_64[0:0] \add_o [65] - case - assign $1\carry_64[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 end sync always - update \carry_64 $0\carry_64[0:0] + update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "libresoc.v:150869.3-150879.6" - process $proc$libresoc.v:150869$7363 + attribute \src "ls180.v:536.5-536.64" + process $proc$ls180.v:536$3273 assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:5364.1-5371.4" + process $proc$ls180.v:5364$1089 assign { } { } - assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "libresoc.v:150870.5-150870.29" - switch \initial - attribute \src "libresoc.v:150870.9-150870.17" + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5366.2-5370.5" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:5366.6-5366.43" case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:5368.6-5368.10" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\zerolo[0:0] \$57 - case - assign $1\zerolo[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 end sync always - update \zerolo $0\zerolo[0:0] - end - connect \$99 $reduce_or$libresoc.v:150385$7274_Y - connect \$101 $eq$libresoc.v:150386$7275_Y - connect \$103 $eq$libresoc.v:150387$7276_Y - connect \$105 $eq$libresoc.v:150388$7277_Y - connect \$107 $reduce_or$libresoc.v:150389$7278_Y - connect \$109 $xor$libresoc.v:150390$7279_Y - connect \$111 $xor$libresoc.v:150391$7280_Y - connect \$113 $xor$libresoc.v:150392$7281_Y - connect \$116 $xor$libresoc.v:150393$7282_Y - connect \$115 $not$libresoc.v:150394$7283_Y - connect \$119 $and$libresoc.v:150395$7284_Y - connect \$121 $xor$libresoc.v:150396$7285_Y - connect \$124 $xor$libresoc.v:150397$7286_Y - connect \$123 $not$libresoc.v:150398$7287_Y - connect \$127 $and$libresoc.v:150399$7288_Y - connect \$129 $eq$libresoc.v:150400$7289_Y - connect \$131 $eq$libresoc.v:150401$7290_Y - connect \$133 $eq$libresoc.v:150402$7291_Y - connect \$135 $eq$libresoc.v:150403$7292_Y - connect \$137 $eq$libresoc.v:150404$7293_Y - connect \$139 $eq$libresoc.v:150405$7294_Y - connect \$141 $eq$libresoc.v:150406$7295_Y - connect \$143 $eq$libresoc.v:150407$7296_Y - connect \$22 $eq$libresoc.v:150408$7297_Y - connect \$24 $not$libresoc.v:150409$7298_Y - connect \$26 $eq$libresoc.v:150410$7299_Y - connect \$28 $eq$libresoc.v:150411$7300_Y - connect \$30 $eq$libresoc.v:150412$7301_Y - connect \$32 $eq$libresoc.v:150413$7302_Y - connect \$34 $or$libresoc.v:150414$7303_Y - connect \$36 $eq$libresoc.v:150415$7304_Y - connect \$38 $eq$libresoc.v:150416$7305_Y - connect \$40 $or$libresoc.v:150417$7306_Y - connect \$42 $eq$libresoc.v:150418$7307_Y - connect \$44 $eq$libresoc.v:150419$7308_Y - connect \$46 $or$libresoc.v:150420$7309_Y - connect \$49 $add$libresoc.v:150421$7310_Y - connect \$51 $not$libresoc.v:150422$7311_Y - connect \$53 $xor$libresoc.v:150423$7312_Y - connect \$55 $xor$libresoc.v:150424$7313_Y - connect \$59 $xor$libresoc.v:150425$7314_Y - connect \$58 $reduce_or$libresoc.v:150426$7315_Y - connect \$57 $not$libresoc.v:150427$7316_Y - connect \$65 $xor$libresoc.v:150428$7317_Y - connect \$64 $reduce_or$libresoc.v:150429$7318_Y - connect \$63 $not$libresoc.v:150430$7319_Y - connect \$69 $or$libresoc.v:150431$7320_Y - connect \$71 $and$libresoc.v:150432$7321_Y - connect \$73 $ne$libresoc.v:150433$7322_Y - connect \$75 $not$libresoc.v:150434$7323_Y - connect \$77 $not$libresoc.v:150435$7324_Y - connect \$79 $or$libresoc.v:150436$7325_Y - connect \$81 $and$libresoc.v:150437$7326_Y - connect \$83 $ternary$libresoc.v:150438$7327_Y - connect \$85 $or$libresoc.v:150439$7328_Y - connect \$87 $and$libresoc.v:150440$7329_Y - connect \$89 $ternary$libresoc.v:150441$7330_Y - connect \$91 $or$libresoc.v:150442$7331_Y - connect \$93 $and$libresoc.v:150443$7332_Y - connect \$95 $ne$libresoc.v:150444$7333_Y - connect \$97 $ternary$libresoc.v:150445$7334_Y - connect \$48 \$49 - connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$21 \xer_so -end -attribute \src "libresoc.v:150888.1-151298.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" -attribute \generator "nMigen" -module \main$114 - attribute \src "libresoc.v:150889.7-150889.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:151250.3-151280.6" - wire width 4 $0\mode[3:0] - attribute \src "libresoc.v:151215.3-151249.6" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:151250.3-151280.6" - wire width 4 $1\mode[3:0] - attribute \src "libresoc.v:151215.3-151249.6" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:150889.7-150889.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" - wire width 5 \mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:48" - wire \mb_extra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:47" - wire width 5 \me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" - wire width 4 \mode - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 40 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 41 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" - wire \rotator_arith - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" - wire \rotator_carry_out_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" - wire \rotator_clear_left - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" - wire \rotator_clear_right - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" - wire \rotator_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - wire width 5 \rotator_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" - wire \rotator_mb_extra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" - wire width 5 \rotator_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" - wire width 64 \rotator_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" - wire width 64 \rotator_result_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" - wire \rotator_right_shift - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" - wire width 64 \rotator_rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" - wire width 7 \rotator_shift - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" - wire \rotator_sign_ext_rs - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 24 \sr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \sr_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \sr_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \sr_op__input_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 17 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 39 \sr_op__insn$18 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \sr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \sr_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \sr_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \sr_op__output_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__output_cr$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \sr_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \sr_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \sr_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 43 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 42 \xer_so$19 - attribute \module_not_derived 1 - attribute \src "libresoc.v:151199.11-151214.4" - cell \rotator \rotator - connect \arith \rotator_arith - connect \carry_out_o \rotator_carry_out_o - connect \clear_left \rotator_clear_left - connect \clear_right \rotator_clear_right - connect \is_32bit \rotator_is_32bit - connect \mb \rotator_mb - connect \mb_extra \rotator_mb_extra - connect \me \rotator_me - connect \ra \rotator_ra - connect \result_o \rotator_result_o - connect \right_shift \rotator_right_shift - connect \rs \rotator_rs - connect \shift \rotator_shift - connect \sign_ext_rs \rotator_sign_ext_rs + update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "libresoc.v:150889.7-150889.20" - process $proc$libresoc.v:150889$7367 + attribute \src "ls180.v:537.11-537.70" + process $proc$ls180.v:537$3274 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 sync always - update \initial $0\initial[0:0] sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end - attribute \src "libresoc.v:151215.3-151249.6" - process $proc$libresoc.v:151215$7365 - assign { } { } + attribute \src "ls180.v:5374.1-5381.4" + process $proc$ls180.v:5374$1100 assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:151216.5-151216.29" - switch \initial - attribute \src "libresoc.v:151216.9-151216.17" + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5376.2-5380.5" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:5376.6-5376.43" case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:5378.6-5378.10" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" - switch \sr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111100 - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0111101 - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0111000 - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0111001 - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0111010 - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0100000 - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\o_ok[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 end sync always - update \o_ok $0\o_ok[0:0] + update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "libresoc.v:151250.3-151280.6" - process $proc$libresoc.v:151250$7366 + attribute \src "ls180.v:538.11-538.70" + process $proc$ls180.v:538$3275 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:5384.1-5391.4" + process $proc$ls180.v:5384$1111 assign { } { } - assign $0\mode[3:0] $1\mode[3:0] - attribute \src "libresoc.v:151251.5-151251.29" - switch \initial - attribute \src "libresoc.v:151251.9-151251.17" + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5386.2-5390.5" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:5386.6-5386.43" case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:5388.6-5388.10" case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" - switch \sr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111100 - assign { } { } - assign $1\mode[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0111101 - assign { } { } - assign $1\mode[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 7'0111000 - assign { } { } - assign $1\mode[3:0] 4'0110 - attribute \src "libresoc.v:0.0-0.0" - case 7'0111001 - assign { } { } - assign $1\mode[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 7'0111010 - assign { } { } - assign $1\mode[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 7'0100000 - assign { } { } - assign $1\mode[3:0] 4'1000 - case - assign $1\mode[3:0] 4'0000 + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 end sync always - update \mode $0\mode[3:0] - end - connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$19 \xer_so - connect \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } - connect \o \rotator_result_o - connect { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode - connect \rotator_arith \sr_op__is_signed - connect \rotator_is_32bit \sr_op__is_32bit - connect \rotator_shift \rb [6:0] - connect \rotator_ra \ra - connect \rotator_rs \rc - connect \rotator_mb_extra \mb_extra - connect \rotator_mb \mb - connect \rotator_me \me - connect \mb_extra \sr_op__insn [5] - connect \me \sr_op__insn [5:1] - connect \mb \sr_op__insn [10:6] -end -attribute \src "libresoc.v:151302.1-151834.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" -attribute \generator "nMigen" -module \main$22 - attribute \src "libresoc.v:151741.3-151764.6" - wire $0\bc_taken[0:0] - attribute \src "libresoc.v:151620.3-151631.6" - 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output 25 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 26 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:151604$7370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \br_imm_addr - connect \B \br_op__cia - connect \Y $add$libresoc.v:151604$7370_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:151619$7386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \br_op__cia - connect \B 3'100 - connect \Y $add$libresoc.v:151619$7386_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:151611$7377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ctr_zero_bo1 - connect \B \$29 - connect \Y $and$libresoc.v:151611$7377_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:151612$7378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ctr_zero_bo1 - connect \B \cr_bit - connect \Y $and$libresoc.v:151612$7378_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:151618$7385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \br_op__insn [10] - connect \B \$44 - connect \Y $and$libresoc.v:151618$7385_Y + update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:151602$7368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \br_op__insn_type - connect \B 7'0001000 - connect \Y $eq$libresoc.v:151602$7368_Y + attribute \src "ls180.v:539.11-539.73" + process $proc$ls180.v:539$3276 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:151605$7371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_bit - connect \B \bo [3] - connect \Y $eq$libresoc.v:151605$7371_Y + attribute \src "ls180.v:5392.1-5582.4" + process $proc$ls180.v:5392$1112 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign { } { } + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 + assign $0\main_sdphy_datar_sink_last[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 + assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state + attribute \src "ls180.v:5433.2-5581.9" + switch \builder_sdcore_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 + attribute \src "ls180.v:5436.4-5456.11" + switch \main_sdcore_cmd_count + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5454$1113_Y + case + end + attribute \src "ls180.v:5457.4-5469.7" + switch $and$ls180.v:5457$1114_Y + attribute \src "ls180.v:5457.8-5457.65" + case 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5458$1115_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + attribute \src "ls180.v:5460.5-5468.8" + switch $eq$ls180.v:5460$1116_Y + attribute \src "ls180.v:5460.9-5460.40" + case 1'1 + attribute \src "ls180.v:5461.6-5467.9" + switch $eq$ls180.v:5461$1117_Y + attribute \src "ls180.v:5461.10-5461.40" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5465.10-5465.14" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5473$1118_Y + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 + attribute \src "ls180.v:5474.4-5478.7" + switch $eq$ls180.v:5474$1119_Y + attribute \src "ls180.v:5474.8-5474.38" + case 1'1 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 + attribute \src "ls180.v:5476.8-5476.12" + case + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 + end + attribute \src "ls180.v:5480.4-5501.7" + switch \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:5480.8-5480.36" + case 1'1 + attribute \src "ls180.v:5481.5-5500.8" + switch $eq$ls180.v:5481$1120_Y + attribute \src "ls180.v:5481.9-5481.56" + case 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5485.9-5485.13" + case + attribute \src "ls180.v:5486.6-5499.9" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:5486.10-5486.37" + case 1'1 + attribute \src "ls180.v:5487.7-5495.10" + switch $eq$ls180.v:5487$1121_Y + attribute \src "ls180.v:5487.11-5487.42" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:5489.11-5489.15" + case + attribute \src "ls180.v:5490.8-5494.11" + switch $eq$ls180.v:5490$1122_Y + attribute \src "ls180.v:5490.12-5490.43" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + attribute \src "ls180.v:5492.12-5492.16" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + end + end + attribute \src "ls180.v:5496.10-5496.14" + case + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready + assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first + assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last + assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + attribute \src "ls180.v:5509.4-5515.7" + switch $and$ls180.v:5509$1124_Y + attribute \src "ls180.v:5509.8-5509.98" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5510$1125_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5512.5-5514.8" + switch $eq$ls180.v:5512$1127_Y + attribute \src "ls180.v:5512.9-5512.77" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:5517.4-5522.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5517.8-5517.37" + case 1'1 + attribute \src "ls180.v:5518.5-5521.8" + switch $ne$ls180.v:5518$1128_Y + attribute \src "ls180.v:5518.9-5518.57" + case 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5527$1130_Y + attribute \src "ls180.v:5528.4-5554.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5528.8-5528.37" + case 1'1 + attribute \src "ls180.v:5529.5-5553.8" + switch $eq$ls180.v:5529$1131_Y + attribute \src "ls180.v:5529.9-5529.57" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid + assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready + assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first + assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:5535.6-5543.9" + switch $and$ls180.v:5535$1132_Y + attribute \src "ls180.v:5535.10-5535.72" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5536$1133_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5538.7-5542.10" + switch $eq$ls180.v:5538$1135_Y + attribute \src "ls180.v:5538.11-5538.79" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5540.11-5540.15" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + end + case + end + attribute \src "ls180.v:5544.9-5544.13" + case + attribute \src "ls180.v:5545.6-5552.9" + switch $eq$ls180.v:5545$1136_Y + attribute \src "ls180.v:5545.10-5545.58" + case 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5565.4-5579.7" + switch \main_sdcore_cmd_send_re + attribute \src "ls180.v:5565.8-5565.31" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] + update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] + update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] + update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] + update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] + update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] + update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] + update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] + update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] + update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] + update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] + update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] + update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] + update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] + update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] + update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] + update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] + update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] + update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] + update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:151607$7373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4:3] - connect \B 1'0 - connect \Y $eq$libresoc.v:151607$7373_Y + attribute \src "ls180.v:55.5-55.42" + process $proc$ls180.v:55$3126 + assign { } { } + assign $1\main_libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:151608$7374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4:3] - connect \B 1'1 - connect \Y $eq$libresoc.v:151608$7374_Y + attribute \src "ls180.v:56.5-56.37" + process $proc$ls180.v:56$3127 + assign { } { } + assign $1\main_libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:151609$7375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4] - connect \B 1'1 - connect \Y $eq$libresoc.v:151609$7375_Y + attribute \src "ls180.v:560.5-560.59" + process $proc$ls180.v:560$3277 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:151614$7380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:151614$7380_Y + attribute \src "ls180.v:5610.1-5617.4" + process $proc$ls180.v:5610$1137 + assign { } { } + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5612.2-5616.5" + switch \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:5612.6-5612.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5613$1138_Y + attribute \src "ls180.v:5614.6-5614.10" + case + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce + end + sync always + update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:151610$7376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_bit - connect \Y $not$libresoc.v:151610$7376_Y + attribute \src "ls180.v:562.5-562.59" + process $proc$ls180.v:562$3278 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:151617$7384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:151617$7384_Y + attribute \src "ls180.v:563.5-563.58" + process $proc$ls180.v:563$3279 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:151603$7369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \br_op__insn [1] - connect \B \$12 - connect \Y $or$libresoc.v:151603$7369_Y + attribute \src "ls180.v:564.5-564.64" + process $proc$ls180.v:564$3280 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:151606$7372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$19 - connect \B \bo [4] - connect \Y $or$libresoc.v:151606$7372_Y + attribute \src "ls180.v:5643.1-5682.4" + process $proc$ls180.v:5643$1148 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state + attribute \src "ls180.v:5653.2-5681.9" + switch \builder_sdblock2memdma_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5657$1149_Y + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:5659.4-5670.7" + switch $and$ls180.v:5659$1150_Y + attribute \src "ls180.v:5659.8-5659.103" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5660$1151_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5662.5-5669.8" + switch $eq$ls180.v:5662$1153_Y + attribute \src "ls180.v:5662.9-5662.106" + case 1'1 + attribute \src "ls180.v:5663.6-5668.9" + switch \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:5663.10-5663.57" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5666.10-5666.14" + case + assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 + end + sync always + update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] + update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] + update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:151614$7381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:151614$7380_Y - connect \Y $pos$libresoc.v:151614$7381_Y + attribute \src "ls180.v:565.12-565.74" + process $proc$ls180.v:565$3281 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:151615$7382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:151615$7382_Y + attribute \src "ls180.v:566.12-566.47" + process $proc$ls180.v:566$3282 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:151613$7379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \fast1 - connect \B 1'1 - connect \Y $sub$libresoc.v:151613$7379_Y + attribute \src "ls180.v:567.5-567.46" + process $proc$ls180.v:567$3283 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:151616$7383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [1] - connect \B \$40 - connect \Y $xor$libresoc.v:151616$7383_Y + attribute \src "ls180.v:569.5-569.44" + process $proc$ls180.v:569$3284 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] end - attribute \src "libresoc.v:151303.7-151303.20" - process $proc$libresoc.v:151303$7404 + attribute \src "ls180.v:57.12-57.60" + process $proc$ls180.v:57$3128 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 sync always - update \initial $0\initial[0:0] sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] end - attribute \src "libresoc.v:151620.3-151631.6" - process $proc$libresoc.v:151620$7387 + attribute \src "ls180.v:570.5-570.45" + process $proc$ls180.v:570$3285 assign { } { } - assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:151621.5-151621.29" - switch \initial - attribute \src "libresoc.v:151621.9-151621.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - switch \$14 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\br_addr[63:0] \br_imm_addr - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\br_addr[63:0] \$16 [63:0] - end + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 sync always - update \br_addr $0\br_addr[63:0] + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] end - attribute \src "libresoc.v:151632.3-151658.6" - process $proc$libresoc.v:151632$7388 + attribute \src "ls180.v:5702.1-5739.4" + process $proc$ls180.v:5702$1155 assign { } { } assign { } { } - assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:151633.5-151633.29" - switch \initial - attribute \src "libresoc.v:151633.9-151633.17" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_interface1_bus_adr[31:0] 0 + assign { } { } + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_interface1_bus_sel[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + assign $0\main_interface1_bus_cyc[0:0] 1'0 + assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:5716.2-5738.9" + switch \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:0.0-0.0" case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000110 - assign { } { } - assign $1\br_imm_addr[63:0] { \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25:2] 2'00 } - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign $1\br_imm_addr[63:0] { \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15:2] 2'00 } - attribute \src "libresoc.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign $1\br_imm_addr[63:0] $2\br_imm_addr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - switch \$46 - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last + assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5721.4-5724.7" + switch \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:5721.8-5721.41" case 1'1 - assign { } { } - assign $2\br_imm_addr[63:0] { \fast1 [63:2] 2'00 } - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 case - assign { } { } - assign $2\br_imm_addr[63:0] { \fast2 [63:2] 2'00 } end + attribute \src "ls180.v:0.0-0.0" case - assign $1\br_imm_addr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_interface1_bus_sel[7:0] 8'11111111 + assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:5732.4-5736.7" + switch $and$ls180.v:5732$1156_Y + attribute \src "ls180.v:5732.8-5732.59" + case 1'1 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + case + end end sync always - update \br_imm_addr $0\br_imm_addr[63:0] + update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[7:0] + update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] + update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] + update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] + update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] + update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] + update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[63:0] + update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "libresoc.v:151659.3-151677.6" - process $proc$libresoc.v:151659$7389 + attribute \src "ls180.v:571.5-571.54" + process $proc$ls180.v:571$3286 assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:573.32-573.76" + process $proc$ls180.v:573$3287 assign { } { } - assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:151660.5-151660.29" - switch \initial - attribute \src "libresoc.v:151660.9-151660.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000110 - assign { } { } - assign $1\br_taken[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign $1\br_taken[0:0] \bc_taken - attribute \src "libresoc.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign $1\br_taken[0:0] \bc_taken - case - assign $1\br_taken[0:0] 1'0 - end + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always - update \br_taken $0\br_taken[0:0] + sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] end - attribute \src "libresoc.v:151678.3-151692.6" - process $proc$libresoc.v:151678$7390 + attribute \src "ls180.v:574.11-574.55" + process $proc$ls180.v:574$3288 assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:5740.1-5776.4" + process $proc$ls180.v:5740$1157 assign { } { } - assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:151679.5-151679.29" - switch \initial - attribute \src "libresoc.v:151679.9-151679.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign $1\fast1_ok[0:0] \ctr_write - attribute \src "libresoc.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign $1\fast1_ok[0:0] \ctr_write + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign { } { } + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:5749.2-5775.9" + switch \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5752$1159_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5753$1160_Y + attribute \src "ls180.v:5754.4-5765.7" + switch \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:5754.8-5754.39" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5755$1161_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5757.5-5764.8" + switch \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:5757.9-5757.39" + case 1'1 + attribute \src "ls180.v:5758.6-5763.9" + switch \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:5758.10-5758.43" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5761.10-5761.14" + case + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" case - assign $1\fast1_ok[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 end sync always - update \fast1_ok $0\fast1_ok[0:0] + update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] + update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] + update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] + update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] + update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "libresoc.v:151693.3-151702.6" - process $proc$libresoc.v:151693$7391 + attribute \src "ls180.v:576.32-576.75" + process $proc$ls180.v:576$3289 assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:578.32-578.76" + process $proc$ls180.v:578$3290 assign { } { } - assign $0\fast2$11[63:0]$7392 $1\fast2$11[63:0]$7393 - attribute \src "libresoc.v:151694.5-151694.29" - switch \initial - attribute \src "libresoc.v:151694.9-151694.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" - switch \br_op__lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fast2$11[63:0]$7393 \$48 [63:0] + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:5788.1-5816.4" + process $proc$ls180.v:5788$1167 + assign { } { } + assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + attribute \src "ls180.v:5790.2-5815.9" + switch \main_sdmem2block_converter_mux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [63:56] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [55:48] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [47:40] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [39:32] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] + attribute \src "ls180.v:0.0-0.0" case - assign $1\fast2$11[63:0]$7393 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] end sync always - update \fast2$11 $0\fast2$11[63:0]$7392 + update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "libresoc.v:151703.3-151712.6" - process $proc$libresoc.v:151703$7394 + attribute \src "ls180.v:58.5-58.39" + process $proc$ls180.v:58$3129 assign { } { } + assign $1\main_libresocsim_scratch_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + end + attribute \src "ls180.v:5830.1-5837.4" + process $proc$ls180.v:5830$1168 assign { } { } - assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:151704.5-151704.29" - switch \initial - attribute \src "libresoc.v:151704.9-151704.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" - switch \br_op__lk - attribute \src "libresoc.v:0.0-0.0" + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5832.2-5836.5" + switch \main_sdmem2block_fifo_replace + attribute \src "ls180.v:5832.6-5832.35" case 1'1 - assign { } { } - assign $1\fast2_ok[0:0] 1'1 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5833$1169_Y + attribute \src "ls180.v:5834.6-5834.10" case - assign $1\fast2_ok[0:0] 1'0 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce end sync always - update \fast2_ok $0\fast2_ok[0:0] + update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "libresoc.v:151713.3-151727.6" - process $proc$libresoc.v:151713$7395 + attribute \src "ls180.v:584.5-584.51" + process $proc$ls180.v:584$3291 assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:5845.1-5881.4" + process $proc$ls180.v:5845$1175 assign { } { } - assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:151714.5-151714.29" - switch \initial - attribute \src "libresoc.v:151714.9-151714.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - switch \bi - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cr_bit[0:0] \cr_a [3] - attribute \src "libresoc.v:0.0-0.0" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign { } { } + assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\builder_next_state[1:0] \builder_state + attribute \src "ls180.v:5856.2-5880.9" + switch \builder_state + attribute \src "ls180.v:0.0-0.0" case 2'01 - assign { } { } - assign $1\cr_bit[0:0] \cr_a [2] - attribute \src "libresoc.v:0.0-0.0" + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'10 + attribute \src "ls180.v:0.0-0.0" case 2'10 - assign { } { } - assign $1\cr_bit[0:0] \cr_a [1] - attribute \src "libresoc.v:0.0-0.0" - case 2'-- - assign { } { } - assign $1\cr_bit[0:0] \cr_a [0] + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } + assign $0\builder_next_state[1:0] 2'00 + attribute \src "ls180.v:0.0-0.0" case - assign $1\cr_bit[0:0] 1'0 + assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5872.4-5878.7" + switch $and$ls180.v:5872$1176_Y + attribute \src "ls180.v:5872.8-5872.77" + case 1'1 + assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5875$1178_Y + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'01 + case + end end sync always - update \cr_bit $0\cr_bit[0:0] + update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] + update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] + update \builder_next_state $0\builder_next_state[1:0] + update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] + update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] + update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] + update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] + update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "libresoc.v:151728.3-151740.6" - process $proc$libresoc.v:151728$7396 + attribute \src "ls180.v:585.5-585.51" + process $proc$ls180.v:585$3292 assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:587.5-587.47" + process $proc$ls180.v:587$3293 assign { } { } - assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:151729.5-151729.29" - switch \initial - attribute \src "libresoc.v:151729.9-151729.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\ctr_write[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_write[0:0] 1'1 - end + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always - update \ctr_write $0\ctr_write[0:0] + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] end - attribute \src "libresoc.v:151741.3-151764.6" - process $proc$libresoc.v:151741$7397 + attribute \src "ls180.v:588.5-588.45" + process $proc$ls180.v:588$3294 assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:589.5-589.45" + process $proc$ls180.v:589$3295 assign { } { } - assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:151742.5-151742.29" - switch \initial - attribute \src "libresoc.v:151742.9-151742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\bc_taken[0:0] \$21 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\bc_taken[0:0] $2\bc_taken[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - switch { \$27 \$25 \$23 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\bc_taken[0:0] \$31 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\bc_taken[0:0] \$33 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\bc_taken[0:0] \ctr_zero_bo1 - case - assign $2\bc_taken[0:0] 1'0 - end - end + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 sync always - update \bc_taken $0\bc_taken[0:0] + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "libresoc.v:151765.3-151777.6" - process $proc$libresoc.v:151765$7398 + attribute \src "ls180.v:590.12-590.57" + process $proc$ls180.v:590$3296 assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:5906.1-5921.4" + process $proc$ls180.v:5906$1199 assign { } { } - assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:151766.5-151766.29" - switch \initial - attribute \src "libresoc.v:151766.9-151766.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\ctr_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_n[63:0] \$35 [63:0] - end + assign { } { } + assign $0\builder_slave_sel[12:0] [0] $eq$ls180.v:5908$1200_Y + assign $0\builder_slave_sel[12:0] [1] $eq$ls180.v:5909$1201_Y + assign $0\builder_slave_sel[12:0] [2] $eq$ls180.v:5910$1202_Y + assign $0\builder_slave_sel[12:0] [3] $eq$ls180.v:5911$1203_Y + assign $0\builder_slave_sel[12:0] [4] $eq$ls180.v:5912$1204_Y + assign $0\builder_slave_sel[12:0] [5] $eq$ls180.v:5913$1205_Y + assign $0\builder_slave_sel[12:0] [6] $eq$ls180.v:5914$1206_Y + assign $0\builder_slave_sel[12:0] [7] $eq$ls180.v:5915$1207_Y + assign $0\builder_slave_sel[12:0] [8] $eq$ls180.v:5916$1208_Y + assign $0\builder_slave_sel[12:0] [9] $eq$ls180.v:5917$1209_Y + assign $0\builder_slave_sel[12:0] [10] $eq$ls180.v:5918$1210_Y + assign $0\builder_slave_sel[12:0] [11] $eq$ls180.v:5919$1211_Y + assign $0\builder_slave_sel[12:0] [12] $eq$ls180.v:5920$1212_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[12:0] + end + attribute \src "ls180.v:592.5-592.51" + process $proc$ls180.v:592$3297 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:593.5-593.51" + process $proc$ls180.v:593$3298 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:594.5-594.50" + process $proc$ls180.v:594$3299 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:595.5-595.54" + process $proc$ls180.v:595$3300 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:596.5-596.55" + process $proc$ls180.v:596$3301 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always - update \ctr_n $0\ctr_n[63:0] + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] end - attribute \src "libresoc.v:151778.3-151790.6" - process $proc$libresoc.v:151778$7399 + attribute \src "ls180.v:597.5-597.56" + process $proc$ls180.v:597$3302 assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:598.5-598.50" + process $proc$ls180.v:598$3303 assign { } { } - assign $0\fast1$10[63:0]$7400 $1\fast1$10[63:0]$7401 - attribute \src "libresoc.v:151779.5-151779.29" - switch \initial - attribute \src "libresoc.v:151779.9-151779.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\fast1$10[63:0]$7401 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\fast1$10[63:0]$7401 \ctr_n - end + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 sync always - update \fast1$10 $0\fast1$10[63:0]$7400 + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "libresoc.v:151791.3-151811.6" - process $proc$libresoc.v:151791$7402 + attribute \src "ls180.v:601.5-601.67" + process $proc$ls180.v:601$3304 assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:602.5-602.66" + process $proc$ls180.v:602$3305 assign { } { } - assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:151792.5-151792.29" - switch \initial - attribute \src "libresoc.v:151792.9-151792.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\ctr_m[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_m[63:0] $2\ctr_m[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" - switch \br_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ctr_m[63:0] \$38 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\ctr_m[63:0] \fast1 - end - end + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always - update \ctr_m $0\ctr_m[63:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init end - attribute \src "libresoc.v:151812.3-151824.6" - process $proc$libresoc.v:151812$7403 + attribute \src "ls180.v:6028.1-6039.4" + process $proc$ls180.v:6028$1241 assign { } { } assign { } { } - assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:151813.5-151813.29" - switch \initial - attribute \src "libresoc.v:151813.9-151813.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign $0\builder_shared_ack[0:0] $or$ls180.v:6032$1253_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:6033$1278_Y [31:0] + attribute \src "ls180.v:6034.2-6038.5" + switch \builder_done + attribute \src "ls180.v:6034.6-6034.18" case 1'1 - assign $1\ctr_zero_bo1[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" + assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\builder_shared_ack[0:0] 1'1 + assign $0\builder_error[0:0] 1'1 case - assign { } { } - assign $1\ctr_zero_bo1[0:0] \$42 end sync always - update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] - end - connect \$12 $eq$libresoc.v:151602$7368_Y - connect \$14 $or$libresoc.v:151603$7369_Y - connect \$17 $add$libresoc.v:151604$7370_Y - connect \$19 $eq$libresoc.v:151605$7371_Y - connect \$21 $or$libresoc.v:151606$7372_Y - connect \$23 $eq$libresoc.v:151607$7373_Y - connect \$25 $eq$libresoc.v:151608$7374_Y - connect \$27 $eq$libresoc.v:151609$7375_Y - connect \$29 $not$libresoc.v:151610$7376_Y - connect \$31 $and$libresoc.v:151611$7377_Y - connect \$33 $and$libresoc.v:151612$7378_Y - connect \$36 $sub$libresoc.v:151613$7379_Y - connect \$38 $pos$libresoc.v:151614$7381_Y - connect \$40 $reduce_or$libresoc.v:151615$7382_Y - connect \$42 $xor$libresoc.v:151616$7383_Y - connect \$44 $not$libresoc.v:151617$7384_Y - connect \$46 $and$libresoc.v:151618$7385_Y - connect \$49 $add$libresoc.v:151619$7386_Y - connect \$16 \$17 - connect \$35 \$36 - connect \$48 \$49 - connect { \br_op__is_32bit$9 \br_op__lk$8 \br_op__imm_data__ok$7 \br_op__imm_data__data$6 \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - connect \muxid$1 \muxid - connect \nia_ok \br_taken - connect \nia \br_addr - connect \bi \br_op__insn [17:16] - connect \bo \br_op__insn [25:21] -end -attribute \src "libresoc.v:151838.1-152784.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" -attribute \generator "nMigen" -module \main$38 - attribute \src "libresoc.v:152749.3-152760.6" - wire width 64 $0\a[63:0] - attribute \src "libresoc.v:152247.3-152258.6" - wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:152761.3-152772.6" - wire width 64 $0\b[63:0] - attribute \src "libresoc.v:152530.3-152541.6" - wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:152323.3-152354.6" - wire width 64 $0\fast1$11[63:0]$7450 - attribute \src "libresoc.v:152355.3-152386.6" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:152387.3-152469.6" - wire width 64 $0\fast2$12[63:0]$7455 - attribute \src "libresoc.v:152470.3-152501.6" - wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:151839.7-151839.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:152542.3-152710.6" - wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:152542.3-152710.6" - wire $0\msr_ok[0:0] - attribute \src "libresoc.v:152259.3-152290.6" - wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:152291.3-152322.6" - wire $0\nia_ok[0:0] - attribute \src "libresoc.v:152711.3-152729.6" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:152730.3-152748.6" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:152502.3-152529.6" - wire $0\trapexc_$signal$60[0:0]$7469 - attribute \src "libresoc.v:152502.3-152529.6" - wire $0\trapexc_$signal$61[0:0]$7470 - attribute \src "libresoc.v:152502.3-152529.6" - wire $0\trapexc_$signal$62[0:0]$7471 - attribute \src "libresoc.v:152502.3-152529.6" - wire $0\trapexc_$signal$67[0:0]$7472 - attribute \src "libresoc.v:152502.3-152529.6" - wire $0\trapexc_$signal$68[0:0]$7473 - attribute \src "libresoc.v:152502.3-152529.6" - wire $0\trapexc_$signal$69[0:0]$7474 - attribute \src "libresoc.v:152502.3-152529.6" - wire $0\trapexc_$signal$70[0:0]$7475 - attribute \src "libresoc.v:152502.3-152529.6" - wire $0\trapexc_$signal[0:0]$7468 - attribute \src "libresoc.v:152387.3-152469.6" - wire $10\fast2$12[19:19]$7465 - attribute \src "libresoc.v:152542.3-152710.6" - wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:152542.3-152710.6" - wire $11\msr[15:15] - attribute \src "libresoc.v:152542.3-152710.6" - wire $12\msr[12:12] - attribute \src "libresoc.v:152542.3-152710.6" - wire $13\msr[60:60] - attribute \src "libresoc.v:152542.3-152710.6" - wire $14\msr[12:12] - attribute \src "libresoc.v:152542.3-152710.6" - wire $15\msr[12:12] - attribute \src "libresoc.v:152542.3-152710.6" - wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:152542.3-152710.6" - wire $17\msr[15:15] - attribute \src "libresoc.v:152542.3-152710.6" - wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:152749.3-152760.6" - wire width 64 $1\a[63:0] - attribute \src "libresoc.v:152247.3-152258.6" - wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:152761.3-152772.6" - wire width 64 $1\b[63:0] - attribute \src "libresoc.v:152530.3-152541.6" - wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:152323.3-152354.6" - wire width 64 $1\fast1$11[63:0]$7451 - attribute \src "libresoc.v:152355.3-152386.6" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:152387.3-152469.6" - wire width 64 $1\fast2$12[63:0]$7456 - attribute \src "libresoc.v:152470.3-152501.6" - wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:152542.3-152710.6" - wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:152542.3-152710.6" - wire $1\msr_ok[0:0] - attribute \src "libresoc.v:152259.3-152290.6" - wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:152291.3-152322.6" - wire $1\nia_ok[0:0] - attribute \src "libresoc.v:152711.3-152729.6" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:152730.3-152748.6" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:152502.3-152529.6" - wire $1\trapexc_$signal$60[0:0]$7477 - attribute \src "libresoc.v:152502.3-152529.6" - wire $1\trapexc_$signal$61[0:0]$7478 - attribute \src "libresoc.v:152502.3-152529.6" - wire $1\trapexc_$signal$62[0:0]$7479 - attribute \src "libresoc.v:152502.3-152529.6" - wire $1\trapexc_$signal$67[0:0]$7480 - attribute \src "libresoc.v:152502.3-152529.6" - wire $1\trapexc_$signal$68[0:0]$7481 - attribute \src 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"libresoc.v:152542.3-152710.6" - wire width 47 $7\msr[59:13] - attribute \src "libresoc.v:152387.3-152469.6" - wire $8\fast2$12[28:28]$7463 - attribute \src "libresoc.v:152542.3-152710.6" - wire width 3 $8\msr[63:61] - attribute \src "libresoc.v:152387.3-152469.6" - wire $9\fast2$12[30:30]$7464 - attribute \src "libresoc.v:152542.3-152710.6" - wire width 3 $9\msr[34:32] - attribute \src "libresoc.v:152223.18-152223.113" - wire width 65 $add$libresoc.v:152223$7421_Y - attribute \src "libresoc.v:152217.18-152217.108" - wire width 5 $and$libresoc.v:152217$7414_Y - attribute \src "libresoc.v:152225.18-152225.118" - wire width 8 $and$libresoc.v:152225$7423_Y - attribute \src "libresoc.v:152227.18-152227.118" - wire width 8 $and$libresoc.v:152227$7425_Y - attribute \src "libresoc.v:152229.18-152229.118" - wire width 8 $and$libresoc.v:152229$7427_Y - attribute \src "libresoc.v:152231.18-152231.119" - wire width 8 $and$libresoc.v:152231$7429_Y - attribute \src "libresoc.v:152233.18-152233.119" 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$extend$libresoc.v:152210$7405_Y - attribute \src "libresoc.v:152211.18-152211.95" - wire width 64 $extend$libresoc.v:152211$7407_Y - attribute \src "libresoc.v:152222.18-152222.100" - wire width 64 $extend$libresoc.v:152222$7419_Y - attribute \src "libresoc.v:152237.18-152237.109" - wire width 65 $extend$libresoc.v:152237$7435_Y - attribute \src "libresoc.v:152213.18-152213.121" - wire $gt$libresoc.v:152213$7410_Y - attribute \src "libresoc.v:152215.18-152215.99" - wire $gt$libresoc.v:152215$7412_Y - attribute \src "libresoc.v:152212.18-152212.121" - wire $lt$libresoc.v:152212$7409_Y - attribute \src "libresoc.v:152214.18-152214.99" - wire $lt$libresoc.v:152214$7411_Y - attribute \src "libresoc.v:152242.18-152242.112" - wire $not$libresoc.v:152242$7441_Y - attribute \src "libresoc.v:152243.18-152243.112" - wire $not$libresoc.v:152243$7442_Y - attribute \src "libresoc.v:152220.18-152220.106" - wire $or$libresoc.v:152220$7417_Y - attribute \src "libresoc.v:152210.18-152210.95" - wire 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"/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" - wire \gt_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" - wire \gt_u - attribute \src "libresoc.v:151839.7-151839.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" - wire \lt_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" - wire \lt_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 32 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 33 \msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 34 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 14 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 30 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 31 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 24 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 25 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - wire \should_trap - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134" - wire width 5 \to - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" - wire width 5 \trap_bits - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \trap_op__cia$6 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \trap_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 16 \trap_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 17 \trap_op__insn$4 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute 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attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 15 \trap_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \trap_op__is_32bit$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 9 \trap_op__ldst_exc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 23 \trap_op__ldst_exc$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 18 \trap_op__msr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 8 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 22 \trap_op__trapaddr$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 7 \trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 21 \trap_op__traptype$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \trapexc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \trapexc_$signal$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \trapexc_$signal$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \trapexc_$signal$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \trapexc_$signal$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \trapexc_$signal$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \trapexc_$signal$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \trapexc_$signal$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" - cell $add $add$libresoc.v:152223$7421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \trap_op__cia - connect \B 3'100 - connect \Y $add$libresoc.v:152223$7421_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $and $and$libresoc.v:152217$7414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \trap_bits - connect \B \to - connect \Y $and$libresoc.v:152217$7414_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - cell $and $and$libresoc.v:152225$7423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 8 - connect \A \trap_op__traptype - connect \B 2'10 - connect \Y $and$libresoc.v:152225$7423_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - cell $and $and$libresoc.v:152227$7425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \trap_op__traptype - connect \B 1'1 - connect \Y $and$libresoc.v:152227$7425_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - cell $and $and$libresoc.v:152229$7427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \trap_op__traptype - connect \B 4'1000 - connect \Y $and$libresoc.v:152229$7427_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:152231$7429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A \trap_op__traptype - connect \B 7'1000000 - connect \Y $and$libresoc.v:152231$7429_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - cell $and $and$libresoc.v:152233$7431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \trap_op__traptype - connect \B 8'10000000 - connect \Y $and$libresoc.v:152233$7431_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:152235$7433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A \trap_op__traptype - connect \B 7'1000000 - connect \Y $and$libresoc.v:152235$7433_Y + update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] + update \builder_shared_ack $0\builder_shared_ack[0:0] + update \builder_error $0\builder_error[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $and $and$libresoc.v:152241$7440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$79 - connect \B \$81 - connect \Y $and$libresoc.v:152241$7440_Y + attribute \src "ls180.v:617.11-617.68" + process $proc$ls180.v:617$3306 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $and $and$libresoc.v:152246$7445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$89 - connect \B \$91 - connect \Y $and$libresoc.v:152246$7445_Y + attribute \src "ls180.v:618.5-618.64" + process $proc$ls180.v:618$3307 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" - cell $eq $eq$libresoc.v:152216$7413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $eq$libresoc.v:152216$7413_Y + attribute \src "ls180.v:619.11-619.70" + process $proc$ls180.v:619$3308 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - cell $eq $eq$libresoc.v:152224$7422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \trap_op__traptype - connect \B 1'0 - connect \Y $eq$libresoc.v:152224$7422_Y + attribute \src "ls180.v:620.11-620.70" + process $proc$ls180.v:620$3309 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - cell $eq $eq$libresoc.v:152238$7437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \trap_op__insn_type - connect \B 7'1001000 - connect \Y $eq$libresoc.v:152238$7437_Y + attribute \src "ls180.v:621.11-621.73" + process $proc$ls180.v:621$3310 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" - cell $eq $eq$libresoc.v:152239$7438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [34:32] - connect \B 3'010 - connect \Y $eq$libresoc.v:152239$7438_Y + attribute \src "ls180.v:63.12-63.47" + process $proc$ls180.v:63$3130 + assign { } { } + assign $1\main_libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $eq $eq$libresoc.v:152240$7439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ra [34:32] - connect \B 3'000 - connect \Y $eq$libresoc.v:152240$7439_Y + attribute \src "ls180.v:642.5-642.59" + process $proc$ls180.v:642$3311 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - cell $eq $eq$libresoc.v:152244$7443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [34:32] - connect \B 3'010 - connect \Y $eq$libresoc.v:152244$7443_Y + attribute \src "ls180.v:644.5-644.59" + process $proc$ls180.v:644$3312 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $eq $eq$libresoc.v:152245$7444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \fast2 [34:32] - connect \B 3'000 - connect \Y $eq$libresoc.v:152245$7444_Y + attribute \src "ls180.v:645.5-645.58" + process $proc$ls180.v:645$3313 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:152210$7405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \ra [31:0] - connect \Y $extend$libresoc.v:152210$7405_Y + attribute \src "ls180.v:646.5-646.64" + process $proc$ls180.v:646$3314 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:152211$7407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \rb [31:0] - connect \Y $extend$libresoc.v:152211$7407_Y + attribute \src "ls180.v:647.12-647.74" + process $proc$ls180.v:647$3315 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $extend$libresoc.v:152222$7419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \Y_WIDTH 64 - connect \A \$36 - connect \Y $extend$libresoc.v:152222$7419_Y + attribute \src "ls180.v:648.12-648.47" + process $proc$ls180.v:648$3316 + assign { } { } + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:152237$7435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \trap_op__msr - connect \Y $extend$libresoc.v:152237$7435_Y + attribute \src "ls180.v:649.5-649.46" + process $proc$ls180.v:649$3317 + assign { } { } + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $gt $gt$libresoc.v:152213$7410 - parameter \A_SIGNED 1 - parameter \A_WIDTH 64 - parameter \B_SIGNED 1 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a_s - connect \B \b_s - connect \Y $gt$libresoc.v:152213$7410_Y + attribute \src "ls180.v:65.12-65.55" + process $proc$ls180.v:65$3131 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $gt $gt$libresoc.v:152215$7412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $gt$libresoc.v:152215$7412_Y + attribute \src "ls180.v:651.5-651.44" + process $proc$ls180.v:651$3318 + assign { } { } + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $lt $lt$libresoc.v:152212$7409 - parameter \A_SIGNED 1 - parameter \A_WIDTH 64 - parameter \B_SIGNED 1 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a_s - connect \B \b_s - connect \Y $lt$libresoc.v:152212$7409_Y + attribute \src "ls180.v:652.5-652.45" + process $proc$ls180.v:652$3319 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $lt $lt$libresoc.v:152214$7411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $lt$libresoc.v:152214$7411_Y + attribute \src "ls180.v:653.5-653.54" + process $proc$ls180.v:653$3320 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - cell $not $not$libresoc.v:152242$7441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [60] - connect \Y $not$libresoc.v:152242$7441_Y + attribute \src "ls180.v:655.32-655.76" + process $proc$ls180.v:655$3321 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $not $not$libresoc.v:152243$7442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \trap_op__insn [9] - connect \Y $not$libresoc.v:152243$7442_Y + attribute \src "ls180.v:6553.1-6558.4" + process $proc$ls180.v:6553$2152 + assign { } { } + assign $0\main_spimaster9_start[0:0] 1'0 + attribute \src "ls180.v:6555.2-6557.5" + switch \main_spimaster12_re + attribute \src "ls180.v:6555.6-6555.25" + case 1'1 + assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] + case + end + sync always + update \main_spimaster9_start $0\main_spimaster9_start[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $or $or$libresoc.v:152220$7417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \B \$31 - connect \Y $or$libresoc.v:152220$7417_Y + attribute \src "ls180.v:656.11-656.55" + process $proc$ls180.v:656$3322 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:152210$7406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:152210$7405_Y - connect \Y $pos$libresoc.v:152210$7406_Y + attribute \src "ls180.v:658.32-658.75" + process $proc$ls180.v:658$3323 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:152211$7408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:152211$7407_Y - connect \Y $pos$libresoc.v:152211$7408_Y + attribute \src "ls180.v:6599.1-6604.4" + process $proc$ls180.v:6599$2217 + assign { } { } + assign $0\main_spisdcard_start1[0:0] 1'0 + attribute \src "ls180.v:6601.2-6603.5" + switch \main_spisdcard_control_re + attribute \src "ls180.v:6601.6-6601.31" + case 1'1 + assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] + case + end + sync always + update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $pos$libresoc.v:152222$7420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:152222$7419_Y - connect \Y $pos$libresoc.v:152222$7420_Y + attribute \src "ls180.v:660.32-660.76" + process $proc$ls180.v:660$3324 + assign { } { } + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:152237$7436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152237$7435_Y - connect \Y $pos$libresoc.v:152237$7436_Y + attribute \src "ls180.v:666.5-666.51" + process $proc$ls180.v:666$3325 + assign { } { } + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:152218$7415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $reduce_or$libresoc.v:152218$7415_Y + attribute \src "ls180.v:667.5-667.51" + process $proc$ls180.v:667$3326 + assign { } { } + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:152219$7416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \trap_op__traptype - connect \Y $reduce_or$libresoc.v:152219$7416_Y + attribute \src "ls180.v:669.5-669.47" + process $proc$ls180.v:669$3327 + assign { } { } + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:152226$7424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$45 - connect \Y $reduce_or$libresoc.v:152226$7424_Y + attribute \src "ls180.v:670.5-670.45" + process $proc$ls180.v:670$3328 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:152228$7426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$49 - connect \Y $reduce_or$libresoc.v:152228$7426_Y + attribute \src "ls180.v:671.5-671.45" + process $proc$ls180.v:671$3329 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:152230$7428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$53 - connect \Y $reduce_or$libresoc.v:152230$7428_Y + attribute \src "ls180.v:672.12-672.57" + process $proc$ls180.v:672$3330 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:152232$7430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$57 - connect \Y $reduce_or$libresoc.v:152232$7430_Y + attribute \src "ls180.v:674.5-674.51" + process $proc$ls180.v:674$3331 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:152234$7432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$64 - connect \Y $reduce_or$libresoc.v:152234$7432_Y + attribute \src "ls180.v:675.5-675.51" + process $proc$ls180.v:675$3332 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:152236$7434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$72 - connect \Y $reduce_or$libresoc.v:152236$7434_Y + attribute \src "ls180.v:676.5-676.50" + process $proc$ls180.v:676$3333 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $sshl $sshl$libresoc.v:152221$7418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 20 - connect \A \trap_op__trapaddr - connect \B 3'100 - connect \Y $sshl$libresoc.v:152221$7418_Y + attribute \src "ls180.v:677.5-677.54" + process $proc$ls180.v:677$3334 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] end - attribute \src "libresoc.v:151839.7-151839.20" - process $proc$libresoc.v:151839$7506 + attribute \src "ls180.v:678.5-678.55" + process $proc$ls180.v:678$3335 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] end - attribute \src "libresoc.v:152247.3-152258.6" - process $proc$libresoc.v:152247$7446 + attribute \src "ls180.v:6788.1-6804.4" + process $proc$ls180.v:6788$2438 assign { } { } - assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:152248.5-152248.29" - switch \initial - attribute \src "libresoc.v:152248.9-152248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" - switch \trap_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a_s[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } - attribute \src "libresoc.v:0.0-0.0" + assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6790.2-6803.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + attribute \src "ls180.v:0.0-0.0" case - assign { } { } - assign $1\a_s[63:0] \ra + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] end sync always - update \a_s $0\a_s[63:0] + update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "libresoc.v:152259.3-152290.6" - process $proc$libresoc.v:152259$7447 + attribute \src "ls180.v:679.5-679.56" + process $proc$ls180.v:679$3336 assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:680.5-680.50" + process $proc$ls180.v:680$3337 assign { } { } - assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:152260.5-152260.29" - switch \initial - attribute \src "libresoc.v:152260.9-152260.17" - case 1'1 + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:6805.1-6821.4" + process $proc$ls180.v:6805$2439 + assign { } { } + assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:6807.2-6820.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\nia[63:0] $2\nia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\nia[63:0] \$35 - case - assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\nia[63:0] { \fast1 [63:2] 2'00 } - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000110000000000 + sync always + update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:6822.1-6838.4" + process $proc$ls180.v:6822$2440 + assign { } { } + assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 + attribute \src "ls180.v:6824.2-6837.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" case - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba end sync always - update \nia $0\nia[63:0] + update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "libresoc.v:152291.3-152322.6" - process $proc$libresoc.v:152291$7448 + attribute \src "ls180.v:683.5-683.67" + process $proc$ls180.v:683$3338 assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:6839.1-6855.4" + process $proc$ls180.v:6839$2441 assign { } { } - assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:152292.5-152292.29" - switch \initial - attribute \src "libresoc.v:152292.9-152292.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\nia_ok[0:0] $2\nia_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\nia_ok[0:0] 1'1 - case - assign $2\nia_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\nia_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\nia_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\nia_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\nia_ok[0:0] 1'1 + assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6841.2-6854.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" case - assign $1\nia_ok[0:0] 1'0 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read end sync always - update \nia_ok $0\nia_ok[0:0] + update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "libresoc.v:152323.3-152354.6" - process $proc$libresoc.v:152323$7449 + attribute \src "ls180.v:684.5-684.66" + process $proc$ls180.v:684$3339 assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6856.1-6872.4" + process $proc$ls180.v:6856$2442 assign { } { } - assign $0\fast1$11[63:0]$7450 $1\fast1$11[63:0]$7451 - attribute \src "libresoc.v:152324.5-152324.29" - switch \initial - attribute \src "libresoc.v:152324.9-152324.17" - case 1'1 + assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6858.2-6871.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast1$11[63:0]$7451 $2\fast1$11[63:0]$7452 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast1$11[63:0]$7452 \trap_op__cia - case - assign $2\fast1$11[63:0]$7452 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast1$11[63:0]$7451 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\fast1$11[63:0]$7451 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign $1\fast1$11[63:0]$7451 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\fast1$11[63:0]$7451 \$39 [63:0] + sync always + update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:6873.1-6889.4" + process $proc$ls180.v:6873$2443 + assign { } { } + assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6875.2-6888.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" case - assign $1\fast1$11[63:0]$7451 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd end sync always - update \fast1$11 $0\fast1$11[63:0]$7450 + update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "libresoc.v:152355.3-152386.6" - process $proc$libresoc.v:152355$7453 - assign { } { } + attribute \src "ls180.v:6890.1-6906.4" + process $proc$ls180.v:6890$2444 assign { } { } - assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:152356.5-152356.29" - switch \initial - attribute \src "libresoc.v:152356.9-152356.17" - case 1'1 + assign $0\builder_comb_t_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6892.2-6905.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast1_ok[0:0] 1'1 - case - assign $2\fast1_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast1_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\fast1_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign $1\fast1_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\fast1_ok[0:0] 1'1 + sync always + update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:6907.1-6923.4" + process $proc$ls180.v:6907$2445 + assign { } { } + assign $0\builder_comb_t_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:6909.2-6922.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" case - assign $1\fast1_ok[0:0] 1'0 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras end sync always - update \fast1_ok $0\fast1_ok[0:0] + update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] end - attribute \src "libresoc.v:152387.3-152469.6" - process $proc$libresoc.v:152387$7454 - assign { } { } + attribute \src "ls180.v:6924.1-6940.4" + process $proc$ls180.v:6924$2446 assign { } { } - assign $0\fast2$12[63:0]$7455 $1\fast2$12[63:0]$7456 - attribute \src "libresoc.v:152388.5-152388.29" - switch \initial - attribute \src "libresoc.v:152388.9-152388.17" - case 1'1 + assign $0\builder_comb_t_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:6926.2-6939.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast2$12[63:0]$7456 $2\fast2$12[63:0]$7457 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { $2\fast2$12[63:0]$7457 [29] $2\fast2$12[63:0]$7457 [27] $2\fast2$12[63:0]$7457 [21] } 3'000 - assign $2\fast2$12[63:0]$7457 [15:0] \trap_op__msr [15:0] - assign $2\fast2$12[63:0]$7457 [26:22] \trap_op__msr [26:22] - assign $2\fast2$12[63:0]$7457 [63:31] \trap_op__msr [63:31] - assign $2\fast2$12[63:0]$7457 [17] $3\fast2$12[17:17]$7458 - assign { } { } - assign $2\fast2$12[63:0]$7457 [20] $5\fast2$12[20:20]$7460 - assign $2\fast2$12[63:0]$7457 [16] $6\fast2$12[16:16]$7461 - assign $2\fast2$12[63:0]$7457 [18] $7\fast2$12[19:18]$7462 [0] - assign $2\fast2$12[63:0]$7457 [28] $8\fast2$12[28:28]$7463 - assign $2\fast2$12[63:0]$7457 [30] $9\fast2$12[30:30]$7464 - assign $2\fast2$12[63:0]$7457 [19] $10\fast2$12[19:19]$7465 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - switch \$42 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fast2$12[17:17]$7458 1'1 - case - assign $3\fast2$12[17:17]$7458 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - switch \$44 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fast2$12[18:18]$7459 1'1 - case - assign $4\fast2$12[18:18]$7459 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - switch \$48 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fast2$12[20:20]$7460 1'1 - case - assign $5\fast2$12[20:20]$7460 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - switch \$52 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\fast2$12[16:16]$7461 1'1 - case - assign $6\fast2$12[16:16]$7461 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - switch \$56 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign $9\fast2$12[30:30]$7464 \trapexc_$signal - assign $8\fast2$12[28:28]$7463 \trapexc_$signal$60 - assign $7\fast2$12[19:18]$7462 [1] \trapexc_$signal$61 - assign $7\fast2$12[19:18]$7462 [0] \trapexc_$signal$62 - case - assign $7\fast2$12[19:18]$7462 { 1'0 $4\fast2$12[18:18]$7459 } - assign $8\fast2$12[28:28]$7463 1'0 - assign $9\fast2$12[30:30]$7464 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - switch \$63 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\fast2$12[19:19]$7465 1'1 - case - assign $10\fast2$12[19:19]$7465 $7\fast2$12[19:18]$7462 [1] - end - case - assign $2\fast2$12[63:0]$7457 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast2$12[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\fast2$12[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign $1\fast2$12[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign { $1\fast2$12[63:0]$7456 [30:27] $1\fast2$12[63:0]$7456 [21:16] } 10'0000000000 - assign $1\fast2$12[63:0]$7456 [15:0] \trap_op__msr [15:0] - assign $1\fast2$12[63:0]$7456 [26:22] \trap_op__msr [26:22] - assign $1\fast2$12[63:0]$7456 [63:31] \trap_op__msr [63:31] + sync always + update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:6941.1-6957.4" + process $proc$ls180.v:6941$2447 + assign { } { } + assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:6943.2-6956.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + attribute \src "ls180.v:0.0-0.0" case - assign $1\fast2$12[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] end sync always - update \fast2$12 $0\fast2$12[63:0]$7455 + update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "libresoc.v:152470.3-152501.6" - process $proc$libresoc.v:152470$7466 - assign { } { } + attribute \src "ls180.v:6958.1-6974.4" + process $proc$ls180.v:6958$2448 assign { } { } - assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:152471.5-152471.29" - switch \initial - attribute \src "libresoc.v:152471.9-152471.17" - case 1'1 + assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "ls180.v:6960.2-6973.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast2_ok[0:0] 1'1 - case - assign $2\fast2_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast2_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\fast2_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign $1\fast2_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\fast2_ok[0:0] 1'1 + sync always + update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:6975.1-6991.4" + process $proc$ls180.v:6975$2449 + assign { } { } + assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 + attribute \src "ls180.v:6977.2-6990.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" case - assign $1\fast2_ok[0:0] 1'0 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba end sync always - update \fast2_ok $0\fast2_ok[0:0] + update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "libresoc.v:152502.3-152529.6" - process $proc$libresoc.v:152502$7467 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:699.11-699.68" + process $proc$ls180.v:699$3340 assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:6992.1-7008.4" + process $proc$ls180.v:6992$2450 assign { } { } + assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 + attribute \src "ls180.v:6994.2-7007.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:700.5-700.64" + process $proc$ls180.v:700$3341 assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:7009.1-7025.4" + process $proc$ls180.v:7009$2451 assign { } { } + assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 + attribute \src "ls180.v:7011.2-7024.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:701.11-701.70" + process $proc$ls180.v:701$3342 assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:702.11-702.70" + process $proc$ls180.v:702$3343 assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:7026.1-7042.4" + process $proc$ls180.v:7026$2452 assign { } { } + assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 + attribute \src "ls180.v:7028.2-7041.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:703.11-703.73" + process $proc$ls180.v:703$3344 assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:7043.1-7059.4" + process $proc$ls180.v:7043$2453 assign { } { } + assign $0\builder_comb_t_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:7045.2-7058.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:7060.1-7076.4" + process $proc$ls180.v:7060$2454 assign { } { } + assign $0\builder_comb_t_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:7062.2-7075.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:7077.1-7093.4" + process $proc$ls180.v:7077$2455 assign { } { } - assign $0\trapexc_$signal[0:0]$7468 $1\trapexc_$signal[0:0]$7476 - assign $0\trapexc_$signal$60[0:0]$7469 $1\trapexc_$signal$60[0:0]$7477 - assign $0\trapexc_$signal$61[0:0]$7470 $1\trapexc_$signal$61[0:0]$7478 - assign $0\trapexc_$signal$62[0:0]$7471 $1\trapexc_$signal$62[0:0]$7479 - assign $0\trapexc_$signal$67[0:0]$7472 $1\trapexc_$signal$67[0:0]$7480 - assign $0\trapexc_$signal$68[0:0]$7473 $1\trapexc_$signal$68[0:0]$7481 - assign $0\trapexc_$signal$69[0:0]$7474 $1\trapexc_$signal$69[0:0]$7482 - assign $0\trapexc_$signal$70[0:0]$7475 $1\trapexc_$signal$70[0:0]$7483 - attribute \src "libresoc.v:152503.5-152503.29" - switch \initial - attribute \src "libresoc.v:152503.9-152503.17" - case 1'1 + assign $0\builder_comb_t_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:7079.2-7092.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\trapexc_$signal[0:0]$7476 $2\trapexc_$signal[0:0]$7484 - assign $1\trapexc_$signal$60[0:0]$7477 $2\trapexc_$signal$60[0:0]$7485 - assign $1\trapexc_$signal$61[0:0]$7478 $2\trapexc_$signal$61[0:0]$7486 - assign $1\trapexc_$signal$62[0:0]$7479 $2\trapexc_$signal$62[0:0]$7487 - assign $1\trapexc_$signal$67[0:0]$7480 $2\trapexc_$signal$67[0:0]$7488 - assign $1\trapexc_$signal$68[0:0]$7481 $2\trapexc_$signal$68[0:0]$7489 - assign $1\trapexc_$signal$69[0:0]$7482 $2\trapexc_$signal$69[0:0]$7490 - assign $1\trapexc_$signal$70[0:0]$7483 $2\trapexc_$signal$70[0:0]$7491 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\trapexc_$signal[0:0]$7484 $3\trapexc_$signal[0:0]$7492 - assign $2\trapexc_$signal$60[0:0]$7485 $3\trapexc_$signal$60[0:0]$7493 - assign $2\trapexc_$signal$61[0:0]$7486 $3\trapexc_$signal$61[0:0]$7494 - assign $2\trapexc_$signal$62[0:0]$7487 $3\trapexc_$signal$62[0:0]$7495 - assign $2\trapexc_$signal$67[0:0]$7488 $3\trapexc_$signal$67[0:0]$7496 - assign $2\trapexc_$signal$68[0:0]$7489 $3\trapexc_$signal$68[0:0]$7497 - assign $2\trapexc_$signal$69[0:0]$7490 $3\trapexc_$signal$69[0:0]$7498 - assign $2\trapexc_$signal$70[0:0]$7491 $3\trapexc_$signal$70[0:0]$7499 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - switch \$71 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\trapexc_$signal$70[0:0]$7499 $3\trapexc_$signal$62[0:0]$7495 $3\trapexc_$signal$60[0:0]$7493 $3\trapexc_$signal$61[0:0]$7494 $3\trapexc_$signal[0:0]$7492 $3\trapexc_$signal$69[0:0]$7498 $3\trapexc_$signal$68[0:0]$7497 $3\trapexc_$signal$67[0:0]$7496 } \trap_op__ldst_exc - case - assign $3\trapexc_$signal[0:0]$7492 1'0 - assign $3\trapexc_$signal$60[0:0]$7493 1'0 - assign $3\trapexc_$signal$61[0:0]$7494 1'0 - assign $3\trapexc_$signal$62[0:0]$7495 1'0 - assign $3\trapexc_$signal$67[0:0]$7496 1'0 - assign $3\trapexc_$signal$68[0:0]$7497 1'0 - assign $3\trapexc_$signal$69[0:0]$7498 1'0 - assign $3\trapexc_$signal$70[0:0]$7499 1'0 - end - case - assign $2\trapexc_$signal[0:0]$7484 1'0 - assign $2\trapexc_$signal$60[0:0]$7485 1'0 - assign $2\trapexc_$signal$61[0:0]$7486 1'0 - assign $2\trapexc_$signal$62[0:0]$7487 1'0 - assign $2\trapexc_$signal$67[0:0]$7488 1'0 - assign $2\trapexc_$signal$68[0:0]$7489 1'0 - assign $2\trapexc_$signal$69[0:0]$7490 1'0 - assign $2\trapexc_$signal$70[0:0]$7491 1'0 - end - case - assign $1\trapexc_$signal[0:0]$7476 1'0 - assign $1\trapexc_$signal$60[0:0]$7477 1'0 - assign $1\trapexc_$signal$61[0:0]$7478 1'0 - assign $1\trapexc_$signal$62[0:0]$7479 1'0 - assign $1\trapexc_$signal$67[0:0]$7480 1'0 - assign $1\trapexc_$signal$68[0:0]$7481 1'0 - assign $1\trapexc_$signal$69[0:0]$7482 1'0 - assign $1\trapexc_$signal$70[0:0]$7483 1'0 - end - sync always - update \trapexc_$signal $0\trapexc_$signal[0:0]$7468 - update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7469 - update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7470 - update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7471 - update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7472 - update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7473 - update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7474 - update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7475 - end - attribute \src "libresoc.v:152530.3-152541.6" - process $proc$libresoc.v:152530$7500 + sync always + update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:7094.1-7101.4" + process $proc$ls180.v:7094$2456 assign { } { } - assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:152531.5-152531.29" - switch \initial - attribute \src "libresoc.v:152531.9-152531.17" - case 1'1 + assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7096.2-7100.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" - switch \trap_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } - attribute \src "libresoc.v:0.0-0.0" + sync always + update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:7102.1-7109.4" + process $proc$ls180.v:7102$2457 + assign { } { } + assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 + attribute \src "ls180.v:7104.2-7108.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" case - assign { } { } - assign $1\b_s[63:0] \rb + assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we end sync always - update \b_s $0\b_s[63:0] + update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "libresoc.v:152542.3-152710.6" - process $proc$libresoc.v:152542$7501 + attribute \src "ls180.v:7110.1-7117.4" + process $proc$ls180.v:7110$2458 assign { } { } + assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 + attribute \src "ls180.v:7112.2-7116.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:7114$2471_Y + end + sync always + update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:7118.1-7125.4" + process $proc$ls180.v:7118$2472 assign { } { } + assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7120.2-7124.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:7126.1-7133.4" + process $proc$ls180.v:7126$2473 assign { } { } + assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 + attribute \src "ls180.v:7128.2-7132.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:7134.1-7141.4" + process $proc$ls180.v:7134$2474 assign { } { } - assign $0\msr[63:0] $1\msr[63:0] - assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:152543.5-152543.29" - switch \initial - attribute \src "libresoc.v:152543.9-152543.17" - case 1'1 + assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 + attribute \src "ls180.v:7136.2-7140.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7138$2487_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign { } { } - assign $1\msr[63:0] $2\msr[63:0] - assign $1\msr_ok[0:0] $2\msr_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\msr[63:0] [62:59] $2\msr[63:0] [57:33] $2\msr[63:0] [31:26] $2\msr[63:0] [24] $2\msr[63:0] [22:16] $2\msr[63:0] [12] $2\msr[63:0] [7:6] $2\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } - assign $2\msr[63:0] [63] 1'1 - assign $2\msr[63:0] [15] 1'0 - assign $2\msr[63:0] [14] 1'0 - assign $2\msr[63:0] [5] 1'0 - assign $2\msr[63:0] [4] 1'0 - assign $2\msr[63:0] [1] 1'0 - assign $2\msr[63:0] [0] 1'1 - assign $2\msr[63:0] [11] 1'0 - assign $2\msr[63:0] [8] 1'0 - assign $2\msr[63:0] [23] 1'0 - assign $2\msr[63:0] [32] 1'0 - assign $2\msr[63:0] [25] 1'0 - assign $2\msr[63:0] [13] 1'0 - assign $2\msr[63:0] [3] 1'0 - assign $2\msr[63:0] [10] 1'0 - assign $2\msr[63:0] [9] 1'0 - assign $2\msr[63:0] [58] 1'0 - assign $2\msr_ok[0:0] 1'1 - case - assign $2\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\msr_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign { } { } - assign { } { } - assign $1\msr[63:0] [0] \$75 [0] - assign $1\msr[63:0] [11:1] $3\msr[11:1] - assign $1\msr[63:0] [59:13] $4\msr[59:13] - assign $1\msr[63:0] [63:61] $5\msr[63:61] - assign $1\msr[63:0] [12] $12\msr[12:12] - assign $1\msr[63:0] [60] $13\msr[60:60] - assign $1\msr_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" - switch \trap_op__insn [21] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $3\msr[11:1] [10:1] \$75 [11:2] - assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$75 [59:16] \$75 [14:13] } - assign $5\msr[63:61] \$75 [63:61] - assign $3\msr[11:1] [0] \ra [1] - assign $4\msr[59:13] [2] \ra [15] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { $3\msr[11:1] [10:5] $3\msr[11:1] [2:0] } { $6\msr[11:1] [10:5] $6\msr[11:1] [2:0] } - assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { $7\msr[59:13] [46:3] $7\msr[59:13] [1:0] } - assign $5\msr[63:61] $8\msr[63:61] - assign $3\msr[11:1] [4:3] $10\msr[5:4] - assign $4\msr[59:13] [2] $11\msr[15:15] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - switch \$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign $6\msr[11:1] \ra [11:1] - assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } - assign $8\msr[63:61] \ra [63:61] - assign $7\msr[59:13] [21:19] $9\msr[34:32] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - switch \$83 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\msr[34:32] \trap_op__msr [34:32] - case - assign $9\msr[34:32] \ra [34:32] - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $7\msr[59:13] [46:19] \$75 [59:32] - assign $8\msr[63:61] \$75 [63:61] - assign $6\msr[11:1] \ra [11:1] - assign $7\msr[59:13] [18:0] \ra [31:13] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" - switch $7\msr[59:13] [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $11\msr[15:15] 1'1 - assign $10\msr[5:4] [1] 1'1 - assign $10\msr[5:4] [0] 1'1 - case - assign $10\msr[5:4] $6\msr[11:1] [4:3] - assign $11\msr[15:15] $7\msr[59:13] [2] - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - switch \$85 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $13\msr[60:60] \trap_op__msr [60] - assign $12\msr[12:12] \trap_op__msr [12] - case - assign $12\msr[12:12] \$75 [12] - assign $13\msr[60:60] \$75 [60] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\msr_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { $1\msr[63:0] [30:27] $1\msr[63:0] [21:16] } 10'0000000000 - assign { } { } - assign { $1\msr[63:0] [14:13] $1\msr[63:0] [11:6] $1\msr[63:0] [3:0] } { \fast2 [14:13] \fast2 [11:6] \fast2 [3:0] } - assign $1\msr[63:0] [26:22] \fast2 [26:22] - assign { $1\msr[63:0] [63:35] $1\msr[63:0] [31] } { \fast2 [63:35] \fast2 [31] } - assign $1\msr[63:0] [12] $14\msr[12:12] - assign $1\msr[63:0] [5:4] $16\msr[5:4] - assign $1\msr[63:0] [15] $17\msr[15:15] - assign $1\msr[63:0] [34:32] $18\msr[34:32] - assign $1\msr_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - switch \$87 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $14\msr[12:12] $15\msr[12:12] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" - switch \trap_op__msr [60] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $15\msr[12:12] \fast2 [12] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $15\msr[12:12] \trap_op__msr [12] - end - case - assign $14\msr[12:12] \fast2 [12] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" - switch \fast2 [14] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $17\msr[15:15] 1'1 - assign $16\msr[5:4] [1] 1'1 - assign $16\msr[5:4] [0] 1'1 - case - assign $16\msr[5:4] \fast2 [5:4] - assign $17\msr[15:15] \fast2 [15] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $18\msr[34:32] \trap_op__msr [34:32] - case - assign $18\msr[34:32] \fast2 [34:32] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign { } { } - assign { $1\msr[63:0] [62:59] $1\msr[63:0] [57:33] $1\msr[63:0] [31:26] $1\msr[63:0] [24] $1\msr[63:0] [22:16] $1\msr[63:0] [12] $1\msr[63:0] [7:6] $1\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } - assign $1\msr[63:0] [63] 1'1 - assign $1\msr[63:0] [15] 1'0 - assign $1\msr[63:0] [14] 1'0 - assign $1\msr[63:0] [5] 1'0 - assign $1\msr[63:0] [4] 1'0 - assign $1\msr[63:0] [1] 1'0 - assign $1\msr[63:0] [0] 1'1 - assign $1\msr[63:0] [11] 1'0 - assign $1\msr[63:0] [8] 1'0 - assign $1\msr[63:0] [23] 1'0 - assign $1\msr[63:0] [32] 1'0 - assign $1\msr[63:0] [25] 1'0 - assign $1\msr[63:0] [13] 1'0 - assign $1\msr[63:0] [3] 1'0 - assign $1\msr[63:0] [10] 1'0 - assign $1\msr[63:0] [9] 1'0 - assign $1\msr[63:0] [58] 1'0 - assign $1\msr_ok[0:0] 1'1 + sync always + update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:7142.1-7149.4" + process $proc$ls180.v:7142$2488 + assign { } { } + assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7144.2-7148.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" case - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\msr_ok[0:0] 1'0 + assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:7150.1-7157.4" + process $proc$ls180.v:7150$2489 + assign { } { } + assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 + attribute \src "ls180.v:7152.2-7156.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we end sync always - update \msr $0\msr[63:0] - update \msr_ok $0\msr_ok[0:0] + update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "libresoc.v:152711.3-152729.6" - process $proc$libresoc.v:152711$7502 - assign { } { } + attribute \src "ls180.v:7158.1-7165.4" + process $proc$ls180.v:7158$2490 assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:152712.5-152712.29" - switch \initial - attribute \src "libresoc.v:152712.9-152712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign { } { } - assign $1\o[63:0] \trap_op__msr + assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 + attribute \src "ls180.v:7160.2-7164.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" case - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7162$2503_Y end sync always - update \o $0\o[63:0] + update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "libresoc.v:152730.3-152748.6" - process $proc$libresoc.v:152730$7503 - assign { } { } + attribute \src "ls180.v:7166.1-7173.4" + process $proc$ls180.v:7166$2504 assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:152731.5-152731.29" - switch \initial - attribute \src "libresoc.v:152731.9-152731.17" - case 1'1 + assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7168.2-7172.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign $1\o_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\o_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign { } { } - assign $1\o_ok[0:0] 1'1 + sync always + update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:7174.1-7181.4" + process $proc$ls180.v:7174$2505 + assign { } { } + assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 + attribute \src "ls180.v:7176.2-7180.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" case - assign $1\o_ok[0:0] 1'0 + assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we end sync always - update \o_ok $0\o_ok[0:0] + update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "libresoc.v:152749.3-152760.6" - process $proc$libresoc.v:152749$7504 + attribute \src "ls180.v:7182.1-7189.4" + process $proc$ls180.v:7182$2506 assign { } { } - assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:152750.5-152750.29" - switch \initial - attribute \src "libresoc.v:152750.9-152750.17" - case 1'1 + assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 + attribute \src "ls180.v:7184.2-7188.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7186$2519_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" - switch \trap_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[63:0] \$13 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:7190.1-7209.4" + process $proc$ls180.v:7190$2520 + assign { } { } + assign $0\builder_comb_rhs_array_muxed24[31:0] 0 + attribute \src "ls180.v:7192.2-7208.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_ibus_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_dbus_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_jtag_wb_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr + attribute \src "ls180.v:0.0-0.0" case - assign { } { } - assign $1\a[63:0] \ra + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr end sync always - update \a $0\a[63:0] + update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "libresoc.v:152761.3-152772.6" - process $proc$libresoc.v:152761$7505 + attribute \src "ls180.v:7210.1-7229.4" + process $proc$ls180.v:7210$2521 assign { } { } - assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:152762.5-152762.29" - switch \initial - attribute \src "libresoc.v:152762.9-152762.17" - case 1'1 + assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "ls180.v:7212.2-7228.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface0_bus_dat_w + attribute \src "ls180.v:0.0-0.0" case + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface1_bus_dat_w end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" - switch \trap_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\b[63:0] \$15 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] + end + attribute \src "ls180.v:7230.1-7249.4" + process $proc$ls180.v:7230$2522 + assign { } { } + assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + attribute \src "ls180.v:7232.2-7248.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface0_bus_sel + attribute \src "ls180.v:0.0-0.0" case - assign { } { } - assign $1\b[63:0] \rb + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface1_bus_sel end sync always - update \b $0\b[63:0] - end - connect \$13 $pos$libresoc.v:152210$7406_Y - connect \$15 $pos$libresoc.v:152211$7408_Y - connect \$17 $lt$libresoc.v:152212$7409_Y - connect \$19 $gt$libresoc.v:152213$7410_Y - connect \$21 $lt$libresoc.v:152214$7411_Y - connect \$23 $gt$libresoc.v:152215$7412_Y - connect \$25 $eq$libresoc.v:152216$7413_Y - connect \$28 $and$libresoc.v:152217$7414_Y - connect \$27 $reduce_or$libresoc.v:152218$7415_Y - connect \$31 $reduce_or$libresoc.v:152219$7416_Y - connect \$33 $or$libresoc.v:152220$7417_Y - connect \$36 $sshl$libresoc.v:152221$7418_Y - connect \$35 $pos$libresoc.v:152222$7420_Y - connect \$40 $add$libresoc.v:152223$7421_Y - connect \$42 $eq$libresoc.v:152224$7422_Y - connect \$45 $and$libresoc.v:152225$7423_Y - connect \$44 $reduce_or$libresoc.v:152226$7424_Y - connect \$49 $and$libresoc.v:152227$7425_Y - connect \$48 $reduce_or$libresoc.v:152228$7426_Y - connect \$53 $and$libresoc.v:152229$7427_Y - connect \$52 $reduce_or$libresoc.v:152230$7428_Y - connect \$57 $and$libresoc.v:152231$7429_Y - connect \$56 $reduce_or$libresoc.v:152232$7430_Y - connect \$64 $and$libresoc.v:152233$7431_Y - connect \$63 $reduce_or$libresoc.v:152234$7432_Y - connect \$72 $and$libresoc.v:152235$7433_Y - connect \$71 $reduce_or$libresoc.v:152236$7434_Y - connect \$75 $pos$libresoc.v:152237$7436_Y - connect \$77 $eq$libresoc.v:152238$7437_Y - connect \$79 $eq$libresoc.v:152239$7438_Y - connect \$81 $eq$libresoc.v:152240$7439_Y - connect \$83 $and$libresoc.v:152241$7440_Y - connect \$85 $not$libresoc.v:152242$7441_Y - connect \$87 $not$libresoc.v:152243$7442_Y - connect \$89 $eq$libresoc.v:152244$7443_Y - connect \$91 $eq$libresoc.v:152245$7444_Y - connect \$93 $and$libresoc.v:152246$7445_Y - connect \$39 \$40 - connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \muxid$1 \muxid - connect \should_trap \$33 - connect \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } - connect \equal \$25 - connect \gt_u \$23 - connect \lt_u \$21 - connect \gt_s \$19 - connect \lt_s \$17 - connect \to \trap_op__insn [25:21] -end -attribute \src "libresoc.v:152788.1-153533.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" -attribute \generator "nMigen" -module \main$51 - attribute \src "libresoc.v:153500.3-153510.6" - wire width 32 $0\a32[31:0] - attribute \src "libresoc.v:153445.3-153455.6" - wire width 64 $0\b[63:0] - attribute \src "libresoc.v:153423.3-153433.6" - wire width 64 $0\bpermd_rb[63:0] - attribute \src "libresoc.v:153412.3-153422.6" - wire width 64 $0\bpermd_rs[63:0] - attribute \src "libresoc.v:153401.3-153411.6" - wire width 64 $0\clz_sig_in[63:0] - attribute \src "libresoc.v:153511.3-153529.6" - wire width 64 $0\cntz_i[63:0] - attribute \src "libresoc.v:153489.3-153499.6" - wire $0\count_right[0:0] - attribute \src "libresoc.v:152789.7-152789.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:153346.3-153400.6" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:153346.3-153400.6" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:153467.3-153477.6" - wire $0\par0[0:0] - attribute \src "libresoc.v:153478.3-153488.6" - wire $0\par1[0:0] - attribute \src "libresoc.v:153434.3-153444.6" - wire width 64 $0\popcount_a[63:0] - attribute \src "libresoc.v:153456.3-153466.6" - wire width 64 $0\popcount_data_len[63:0] - attribute \src "libresoc.v:153500.3-153510.6" - wire width 32 $1\a32[31:0] - attribute \src "libresoc.v:153445.3-153455.6" - wire width 64 $1\b[63:0] - attribute \src "libresoc.v:153423.3-153433.6" - wire width 64 $1\bpermd_rb[63:0] - attribute \src "libresoc.v:153412.3-153422.6" - wire width 64 $1\bpermd_rs[63:0] - attribute \src "libresoc.v:153401.3-153411.6" - wire width 64 $1\clz_sig_in[63:0] - attribute \src "libresoc.v:153511.3-153529.6" - wire width 64 $1\cntz_i[63:0] - attribute \src "libresoc.v:153489.3-153499.6" - wire $1\count_right[0:0] - attribute \src "libresoc.v:153346.3-153400.6" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:153346.3-153400.6" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:153467.3-153477.6" - wire $1\par0[0:0] - attribute \src "libresoc.v:153478.3-153488.6" - wire $1\par1[0:0] - attribute \src "libresoc.v:153434.3-153444.6" - wire width 64 $1\popcount_a[63:0] - attribute \src "libresoc.v:153456.3-153466.6" - wire width 64 $1\popcount_data_len[63:0] - attribute \src "libresoc.v:153511.3-153529.6" - wire width 64 $2\cntz_i[63:0] - attribute \src "libresoc.v:153346.3-153400.6" - wire width 64 $2\o[63:0] - attribute \src "libresoc.v:153293.18-153293.103" - wire width 64 $and$libresoc.v:153293$7553_Y - attribute \src "libresoc.v:153252.18-153252.118" - wire $eq$libresoc.v:153252$7507_Y - attribute \src "libresoc.v:153253.19-153253.119" - wire $eq$libresoc.v:153253$7508_Y - attribute \src "libresoc.v:153254.19-153254.119" - wire $eq$libresoc.v:153254$7509_Y - attribute \src "libresoc.v:153255.19-153255.119" - wire $eq$libresoc.v:153255$7510_Y - attribute \src "libresoc.v:153256.19-153256.119" - wire $eq$libresoc.v:153256$7511_Y - attribute \src "libresoc.v:153257.19-153257.119" - wire $eq$libresoc.v:153257$7512_Y - attribute \src "libresoc.v:153258.19-153258.119" - wire $eq$libresoc.v:153258$7513_Y - attribute \src "libresoc.v:153259.19-153259.119" - wire $eq$libresoc.v:153259$7514_Y - attribute \src "libresoc.v:153260.19-153260.119" - wire $eq$libresoc.v:153260$7515_Y - attribute \src "libresoc.v:153261.19-153261.119" - wire $eq$libresoc.v:153261$7516_Y - attribute \src "libresoc.v:153262.19-153262.119" - wire $eq$libresoc.v:153262$7517_Y - attribute \src "libresoc.v:153263.19-153263.119" - wire $eq$libresoc.v:153263$7518_Y - attribute \src "libresoc.v:153264.19-153264.119" - wire $eq$libresoc.v:153264$7519_Y - attribute \src "libresoc.v:153265.19-153265.119" - wire $eq$libresoc.v:153265$7520_Y - attribute \src "libresoc.v:153266.19-153266.119" - wire $eq$libresoc.v:153266$7521_Y - attribute \src "libresoc.v:153267.19-153267.119" - wire $eq$libresoc.v:153267$7522_Y - attribute \src "libresoc.v:153268.19-153268.119" - wire $eq$libresoc.v:153268$7523_Y - attribute \src "libresoc.v:153269.19-153269.119" - wire $eq$libresoc.v:153269$7524_Y - attribute \src "libresoc.v:153270.19-153270.119" - wire $eq$libresoc.v:153270$7525_Y - attribute \src "libresoc.v:153271.19-153271.119" - wire $eq$libresoc.v:153271$7526_Y - attribute \src "libresoc.v:153272.19-153272.119" - wire $eq$libresoc.v:153272$7527_Y - attribute \src "libresoc.v:153273.19-153273.119" - wire $eq$libresoc.v:153273$7528_Y - attribute \src "libresoc.v:153274.19-153274.119" - wire $eq$libresoc.v:153274$7529_Y - attribute \src "libresoc.v:153275.19-153275.119" - wire $eq$libresoc.v:153275$7530_Y - attribute \src "libresoc.v:153276.19-153276.119" - wire $eq$libresoc.v:153276$7531_Y - attribute \src "libresoc.v:153277.19-153277.119" - wire $eq$libresoc.v:153277$7532_Y - attribute \src "libresoc.v:153278.19-153278.119" - wire $eq$libresoc.v:153278$7533_Y - attribute \src "libresoc.v:153279.19-153279.119" - wire $eq$libresoc.v:153279$7534_Y - attribute \src "libresoc.v:153280.19-153280.128" - wire $eq$libresoc.v:153280$7535_Y - attribute \src "libresoc.v:153296.18-153296.114" - wire $eq$libresoc.v:153296$7556_Y - attribute \src "libresoc.v:153297.18-153297.114" - wire $eq$libresoc.v:153297$7557_Y - attribute \src "libresoc.v:153298.18-153298.114" - wire $eq$libresoc.v:153298$7558_Y - attribute \src "libresoc.v:153299.18-153299.114" - wire $eq$libresoc.v:153299$7559_Y - attribute \src "libresoc.v:153300.18-153300.114" - wire $eq$libresoc.v:153300$7560_Y - attribute \src "libresoc.v:153301.18-153301.114" - wire $eq$libresoc.v:153301$7561_Y - attribute \src "libresoc.v:153302.18-153302.114" - wire $eq$libresoc.v:153302$7562_Y - attribute \src "libresoc.v:153303.18-153303.114" - wire $eq$libresoc.v:153303$7563_Y - attribute \src "libresoc.v:153304.18-153304.116" - wire $eq$libresoc.v:153304$7564_Y - attribute \src "libresoc.v:153305.18-153305.116" - wire $eq$libresoc.v:153305$7565_Y - attribute \src "libresoc.v:153306.18-153306.116" - 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\enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 41 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 42 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" - wire \par0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" - wire \par1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" - wire width 64 \popcount_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" - wire width 64 \popcount_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" - wire width 64 \popcount_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 43 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:153293$7553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $and$libresoc.v:153293$7553_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153252$7507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:153252$7507_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153253$7508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:153253$7508_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153254$7509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:153254$7509_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153255$7510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:153255$7510_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153256$7511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:153256$7511_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153257$7512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:153257$7512_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153258$7513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:153258$7513_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153259$7514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:153259$7514_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153260$7515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:153260$7515_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153261$7516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:153261$7516_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153262$7517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:153262$7517_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153263$7518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:153263$7518_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153264$7519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:153264$7519_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153265$7520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:153265$7520_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153266$7521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:153266$7521_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153267$7522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:153267$7522_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153268$7523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:153268$7523_Y + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153269$7524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:153269$7524_Y + attribute \src "ls180.v:724.5-724.59" + process $proc$ls180.v:724$3345 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153270$7525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:153270$7525_Y + attribute \src "ls180.v:7250.1-7269.4" + process $proc$ls180.v:7250$2523 + assign { } { } + assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 + attribute \src "ls180.v:7252.2-7268.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc + end + sync always + update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153271$7526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:153271$7526_Y + attribute \src "ls180.v:726.5-726.59" + process $proc$ls180.v:726$3346 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153272$7527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:153272$7527_Y + attribute \src "ls180.v:727.5-727.58" + process $proc$ls180.v:727$3347 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153273$7528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:153273$7528_Y + attribute \src "ls180.v:7270.1-7289.4" + process $proc$ls180.v:7270$2524 + assign { } { } + assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 + attribute \src "ls180.v:7272.2-7288.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb + end + sync always + update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153274$7529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:153274$7529_Y + attribute \src "ls180.v:728.5-728.64" + process $proc$ls180.v:728$3348 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153275$7530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:153275$7530_Y + attribute \src "ls180.v:729.12-729.74" + process $proc$ls180.v:729$3349 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153276$7531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:153276$7531_Y + attribute \src "ls180.v:7290.1-7309.4" + process $proc$ls180.v:7290$2525 + assign { } { } + assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 + attribute \src "ls180.v:7292.2-7308.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we + end + sync always + update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153277$7532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:153277$7532_Y + attribute \src "ls180.v:730.12-730.47" + process $proc$ls180.v:730$3350 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153278$7533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:153278$7533_Y + attribute \src "ls180.v:731.5-731.46" + process $proc$ls180.v:731$3351 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153279$7534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:153279$7534_Y + attribute \src "ls180.v:7310.1-7329.4" + process $proc$ls180.v:7310$2526 + assign { } { } + assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 + attribute \src "ls180.v:7312.2-7328.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_jtag_wb_cti + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti + end + sync always + update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:153280$7535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__data_len [3] - connect \B 1'1 - connect \Y $eq$libresoc.v:153280$7535_Y + attribute \src "ls180.v:733.5-733.44" + process $proc$ls180.v:733$3352 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153296$7556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:153296$7556_Y + attribute \src "ls180.v:7330.1-7349.4" + process $proc$ls180.v:7330$2527 + assign { } { } + assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 + attribute \src "ls180.v:7332.2-7348.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_jtag_wb_bte + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte + end + sync always + update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153297$7557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:153297$7557_Y + attribute \src "ls180.v:734.5-734.45" + process $proc$ls180.v:734$3353 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153298$7558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:153298$7558_Y + attribute \src "ls180.v:735.5-735.54" + process $proc$ls180.v:735$3354 + assign { } { } + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153299$7559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:153299$7559_Y + attribute \src "ls180.v:7350.1-7366.4" + process $proc$ls180.v:7350$2528 + assign { } { } + assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 + attribute \src "ls180.v:7352.2-7365.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + end + sync always + update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153300$7560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:153300$7560_Y + attribute \src "ls180.v:7367.1-7383.4" + process $proc$ls180.v:7367$2529 + assign { } { } + assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:7369.2-7382.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + end + sync always + update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153301$7561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:153301$7561_Y + attribute \src "ls180.v:737.32-737.76" + process $proc$ls180.v:737$3355 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153302$7562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:153302$7562_Y + attribute \src "ls180.v:738.11-738.55" + process $proc$ls180.v:738$3356 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153303$7563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:153303$7563_Y + attribute \src "ls180.v:7384.1-7400.4" + process $proc$ls180.v:7384$2530 + assign { } { } + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:7386.2-7399.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7391$2532_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7394$2534_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7397$2536_Y + end + sync always + update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153304$7564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:153304$7564_Y + attribute \src "ls180.v:74.11-74.52" + process $proc$ls180.v:74$3132 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153305$7565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:153305$7565_Y + attribute \src "ls180.v:740.32-740.75" + process $proc$ls180.v:740$3357 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153306$7566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:153306$7566_Y + attribute \src "ls180.v:7401.1-7417.4" + process $proc$ls180.v:7401$2537 + assign { } { } + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:7403.2-7416.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7408$2539_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7411$2541_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7414$2543_Y + end + sync always + update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153307$7567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:153307$7567_Y + attribute \src "ls180.v:7418.1-7434.4" + process $proc$ls180.v:7418$2544 + assign { } { } + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:7420.2-7433.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7425$2546_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7428$2548_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7431$2550_Y + end + sync always + update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153308$7568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:153308$7568_Y + attribute \src "ls180.v:742.32-742.76" + process $proc$ls180.v:742$3358 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153309$7569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:153309$7569_Y + attribute \src "ls180.v:7435.1-7451.4" + process $proc$ls180.v:7435$2551 + assign { } { } + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:7437.2-7450.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7442$2553_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7445$2555_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7448$2557_Y + end + sync always + update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153310$7570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:153310$7570_Y + attribute \src "ls180.v:7452.1-7468.4" + process $proc$ls180.v:7452$2558 + assign { } { } + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:7454.2-7467.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7459$2560_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7462$2562_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7465$2564_Y + end + sync always + update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153311$7571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:153311$7571_Y + attribute \src "ls180.v:7469.1-7497.4" + process $proc$ls180.v:7469$2565 + assign { } { } + assign $0\builder_sync_f_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:7471.2-7496.9" + switch \main_spimaster34_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153312$7572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:153312$7572_Y + attribute \src "ls180.v:748.5-748.51" + process $proc$ls180.v:748$3359 + assign { } { } + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153313$7573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:153313$7573_Y + attribute \src "ls180.v:749.5-749.51" + process $proc$ls180.v:749$3360 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153314$7574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:153314$7574_Y + attribute \src "ls180.v:7498.1-7526.4" + process $proc$ls180.v:7498$2566 + assign { } { } + assign $0\builder_sync_f_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:7500.2-7525.9" + switch \main_spisdcard_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153315$7575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:153315$7575_Y + attribute \src "ls180.v:75.11-75.52" + process $proc$ls180.v:75$3133 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153316$7576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:153316$7576_Y + attribute \src "ls180.v:751.5-751.47" + process $proc$ls180.v:751$3361 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153317$7577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:153317$7577_Y + attribute \src "ls180.v:752.5-752.45" + process $proc$ls180.v:752$3362 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153318$7578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:153318$7578_Y + attribute \src "ls180.v:753.5-753.45" + process $proc$ls180.v:753$3363 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153319$7579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:153319$7579_Y + attribute \src "ls180.v:754.12-754.57" + process $proc$ls180.v:754$3364 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153320$7580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:153320$7580_Y + attribute \src "ls180.v:756.5-756.51" + process $proc$ls180.v:756$3365 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153321$7581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:153321$7581_Y + attribute \src "ls180.v:757.5-757.51" + process $proc$ls180.v:757$3366 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153322$7582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:153322$7582_Y + attribute \src "ls180.v:758.5-758.50" + process $proc$ls180.v:758$3367 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153323$7583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:153323$7583_Y + attribute \src "ls180.v:7584.1-7594.4" + process $proc$ls180.v:7584$2567 + assign { } { } + assign $0\main_gpiotristateasic0_status[15:0] [15:8] 8'00000000 + assign $0\main_gpiotristateasic0_status[15:0] [0] \builder_multiregimpl1_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [1] \builder_multiregimpl2_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [2] \builder_multiregimpl3_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [3] \builder_multiregimpl4_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [4] \builder_multiregimpl5_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [5] \builder_multiregimpl6_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [6] \builder_multiregimpl7_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [7] \builder_multiregimpl8_regs1 + sync always + update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153324$7584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:153324$7584_Y + attribute \src "ls180.v:759.5-759.54" + process $proc$ls180.v:759$3368 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153325$7585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:153325$7585_Y + attribute \src "ls180.v:7595.1-7605.4" + process $proc$ls180.v:7595$2568 + assign { } { } + assign $0\main_gpiotristateasic1_status[15:0] [7:0] 8'00000000 + assign $0\main_gpiotristateasic1_status[15:0] [8] \builder_multiregimpl9_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [9] \builder_multiregimpl10_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [10] \builder_multiregimpl11_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [11] \builder_multiregimpl12_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [12] \builder_multiregimpl13_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [13] \builder_multiregimpl14_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [14] \builder_multiregimpl15_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [15] \builder_multiregimpl16_regs1 + sync always + update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153326$7586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:153326$7586_Y + attribute \src "ls180.v:760.5-760.55" + process $proc$ls180.v:760$3369 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153327$7587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:153327$7587_Y + attribute \src "ls180.v:761.5-761.56" + process $proc$ls180.v:761$3370 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153328$7588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:153328$7588_Y + attribute \src "ls180.v:762.5-762.50" + process $proc$ls180.v:762$3371 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153329$7589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:153329$7589_Y + attribute \src "ls180.v:7626.1-7628.4" + process $proc$ls180.v:7626$2569 + assign { } { } + assign $0\main_int_rst[0:0] \sys_rst + sync posedge \por_clk + update \main_int_rst $0\main_int_rst[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153330$7590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:153330$7590_Y + attribute \src "ls180.v:7630.1-7700.4" + process $proc$ls180.v:7630$2570 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] + assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] + assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] + assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] + assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] + assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] + assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] + assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] + assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] + assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] + assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] + assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] + assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] + assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] + assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] + assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n + assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n + assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n + assign $0\sdram_cke[0:0] \main_dfi_p0_cke + assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n + assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] + assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] + assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] + assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] + assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] + assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] + assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] + assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] + assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] + assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] + assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] + assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] + assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] + assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] + assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] + assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] + assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] + assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] + assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] + assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] + assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] + assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] + assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] + assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] + assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] + assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] + assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] + assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] + assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] + assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] + assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] + assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] + assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] + assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] + assign $0\sdram_clock[0:0] \sys_clk_1 + assign $0\sdcard_clk[0:0] $and$ls180.v:7687$2572_Y + assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe + assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o + assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i + assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe + assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] + assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] + assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] + assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] + assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] + assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] + assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] + assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] + sync posedge \sdrio_clk + update \sdram_a $0\sdram_a[12:0] + update \sdram_dq_o $0\sdram_dq_o[15:0] + update \sdram_dq_oe $0\sdram_dq_oe[0:0] + update \sdram_we_n $0\sdram_we_n[0:0] + update \sdram_ras_n $0\sdram_ras_n[0:0] + update \sdram_cas_n $0\sdram_cas_n[0:0] + update \sdram_cs_n $0\sdram_cs_n[0:0] + update \sdram_cke $0\sdram_cke[0:0] + update \sdram_ba $0\sdram_ba[1:0] + update \sdram_dm $0\sdram_dm[1:0] + update \sdram_clock $0\sdram_clock[0:0] + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] + update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] + update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] + update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:153331$7591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:153331$7591_Y + attribute \src "ls180.v:765.5-765.67" + process $proc$ls180.v:765$3372 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:153282$7537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 64 - connect \A \$158 - connect \Y $extend$libresoc.v:153282$7537_Y + attribute \src "ls180.v:766.5-766.66" + process $proc$ls180.v:766$3373 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:7702.1-10346.4" + process $proc$ls180.v:7702$2573 + assign $0\uart_tx[0:0] \uart_tx + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } + assign $0\spimaster_clk[0:0] \spimaster_clk + assign $0\spimaster_mosi[0:0] \spimaster_mosi + assign { } { } + assign $0\pwm[1:0] \pwm + assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage + assign { } { } + assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage + assign { } { } + assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors + assign { } { } + assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage + assign { } { } + assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage + assign { } { } + assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage + assign { } { } + assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage + assign { } { } + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status + assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending + assign { } { } + assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage + assign { } { } + assign $0\main_libresocsim_value[31:0] \main_libresocsim_value + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_converter0_counter[0:0] \main_converter0_counter + assign $0\main_converter0_dat_r[63:0] \main_converter0_dat_r + assign $0\main_converter1_counter[0:0] \main_converter1_counter + assign $0\main_converter1_dat_r[63:0] \main_converter1_dat_r + assign { } { } + assign { } { } + assign $0\main_sdram_storage[3:0] \main_sdram_storage + assign { } { } + assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage + assign { } { } + assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage + assign { } { } + assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage + assign { } { } + assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage + assign { } { } + assign $0\main_sdram_status[15:0] \main_sdram_status + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 + assign { } { } + assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count + assign { } { } + assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter + assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row + assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row + assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row + assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row + assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count + assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant + assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant + assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready + assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count + assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready + assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count + assign $0\main_sdram_time0[4:0] \main_sdram_time0 + assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_dat_r + assign $0\main_converter_counter[0:0] \main_converter_counter + assign $0\main_converter_dat_r[31:0] \main_converter_dat_r + assign $0\main_cmd_consumed[0:0] \main_cmd_consumed + assign $0\main_wdata_consumed[0:0] \main_wdata_consumed + assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage + assign { } { } + assign { } { } + assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen + assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg + assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount + assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy + assign { } { } + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data + assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen + assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx + assign { } { } + assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount + assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy + assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending + assign { } { } + assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending + assign { } { } + assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage + assign { } { } + assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable + assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 + assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce + assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume + assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable + assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 + assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce + assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume + assign $0\main_gpiotristateasic1_oe_storage[15:0] \main_gpiotristateasic1_oe_storage + assign { } { } + assign $0\main_gpiotristateasic1_out_storage[15:0] \main_gpiotristateasic1_out_storage + assign { } { } + assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso + assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage + assign { } { } + assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage + assign { } { } + assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage + assign { } { } + assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage + assign { } { } + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count + assign { } { } + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data + assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel + assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso + assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage + assign { } { } + assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage + assign { } { } + assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage + assign { } { } + assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage + assign { } { } + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count + assign { } { } + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data + assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel + assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data + assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage + assign { } { } + assign { } { } + assign $0\main_pwm0_counter[31:0] \main_pwm0_counter + assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage + assign { } { } + assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage + assign { } { } + assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage + assign { } { } + assign $0\main_pwm1_counter[31:0] \main_pwm1_counter + assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage + assign { } { } + assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage + assign { } { } + assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage + assign { } { } + assign $0\main_i2c_storage[2:0] \main_i2c_storage + assign { } { } + assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage + assign { } { } + assign { } { } + assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks + assign { } { } + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count + assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count + assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count + assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count + assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset + assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage + assign { } { } + assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage + assign { } { } + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status + assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage + assign { } { } + assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage + assign { } { } + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 + assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val + assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout + assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level + assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce + assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[2:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage + assign { } { } + assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage + assign { } { } + assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage + assign { } { } + assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage + assign { } { } + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset + assign $0\main_sdmem2block_converter_mux[2:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level + assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce + assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w + assign $0\builder_grant[2:0] \builder_grant + assign { } { } + assign $0\builder_count[19:0] \builder_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_dummy[23:0] [0] $or$ls180.v:7703$2574_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7704$2575_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7705$2576_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7706$2577_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7707$2578_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7708$2579_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7709$2580_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7710$2581_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7711$2582_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7712$2583_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7713$2584_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7714$2585_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7715$2586_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7716$2587_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7717$2588_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7718$2589_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7719$2590_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7720$2591_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7721$2592_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7722$2593_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7723$2594_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7724$2595_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7725$2596_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7726$2597_Y + assign $0\builder_converter0_state[0:0] \builder_converter0_next_state + assign $0\builder_converter1_state[0:0] \builder_converter1_next_state + assign $0\builder_converter2_state[0:0] \builder_converter2_next_state + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger + assign $0\main_interface0_ram_bus_ack[0:0] 1'0 + assign $0\main_interface1_ram_bus_ack[0:0] 1'0 + assign $0\main_interface2_ram_bus_ack[0:0] 1'0 + assign $0\main_interface3_ram_bus_ack[0:0] 1'0 + assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } + assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\builder_refresher_state[1:0] \builder_refresher_next_state + assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state + assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state + assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state + assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 + assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8184$2706_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8185$2707_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8186$2708_Y + assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 + assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8220$2726_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8221$2738_Y + assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 + assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 + assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 + assign $0\builder_converter_state[0:0] \builder_converter_next_state + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx + assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger + assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8379$2784_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8388$2787_Y + assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8414$2789_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8423$2792_Y + assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state + assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 + assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 + assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state + assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state + assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state + assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state + assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state + assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state + assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state + assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state + assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state + assign $0\builder_state[1:0] \builder_next_state + assign $0\builder_slave_sel_r[12:0] \builder_slave_sel + assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re + assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re + assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_gpiotristateasic1_oe_re[0:0] \builder_csrbank1_oe0_re + assign $0\main_gpiotristateasic1_out_re[0:0] \builder_csrbank1_out0_re + assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re + assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re + assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re + assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re + assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re + assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re + assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re + assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re + assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re + assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re + assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re + assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re + assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re + assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re + assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re + assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re + assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re + assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re + assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re + assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re + assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re + assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re + assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re + assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re + assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re + assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re + assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re + assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re + assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re + assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re + assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re + assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re + assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re + assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re + assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re + assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re + assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re + assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re + assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx + assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 + assign $0\builder_multiregimpl1_regs0[0:0] \main_gpiotristateasic0_pads_i [0] + assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 + assign $0\builder_multiregimpl2_regs0[0:0] \main_gpiotristateasic0_pads_i [1] + assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 + assign $0\builder_multiregimpl3_regs0[0:0] \main_gpiotristateasic0_pads_i [2] + assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 + assign $0\builder_multiregimpl4_regs0[0:0] \main_gpiotristateasic0_pads_i [3] + assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 + assign $0\builder_multiregimpl5_regs0[0:0] \main_gpiotristateasic0_pads_i [4] + assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 + assign $0\builder_multiregimpl6_regs0[0:0] \main_gpiotristateasic0_pads_i [5] + assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 + assign $0\builder_multiregimpl7_regs0[0:0] \main_gpiotristateasic0_pads_i [6] + assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 + assign $0\builder_multiregimpl8_regs0[0:0] \main_gpiotristateasic0_pads_i [7] + assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 + assign $0\builder_multiregimpl9_regs0[0:0] \main_gpiotristateasic1_pads_i [8] + assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 + assign $0\builder_multiregimpl10_regs0[0:0] \main_gpiotristateasic1_pads_i [9] + assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 + assign $0\builder_multiregimpl11_regs0[0:0] \main_gpiotristateasic1_pads_i [10] + assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 + assign $0\builder_multiregimpl12_regs0[0:0] \main_gpiotristateasic1_pads_i [11] + assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 + assign $0\builder_multiregimpl13_regs0[0:0] \main_gpiotristateasic1_pads_i [12] + assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 + assign $0\builder_multiregimpl14_regs0[0:0] \main_gpiotristateasic1_pads_i [13] + assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 + assign $0\builder_multiregimpl15_regs0[0:0] \main_gpiotristateasic1_pads_i [14] + assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 + assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] + assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 + attribute \src "ls180.v:7727.2-7729.5" + switch $or$ls180.v:7727$2598_Y + attribute \src "ls180.v:7727.6-7727.69" + case 1'1 + assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r + case + end + attribute \src "ls180.v:7731.2-7733.5" + switch \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7731.6-7731.54" + case 1'1 + assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value + case + end + attribute \src "ls180.v:7734.2-7737.5" + switch \main_converter0_reset + attribute \src "ls180.v:7734.6-7734.27" + case 1'1 + assign $0\main_converter0_counter[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7738.2-7740.5" + switch $or$ls180.v:7738$2599_Y + attribute \src "ls180.v:7738.6-7738.69" + case 1'1 + assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r + case + end + attribute \src "ls180.v:7742.2-7744.5" + switch \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7742.6-7742.54" + case 1'1 + assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value + case + end + attribute \src "ls180.v:7745.2-7748.5" + switch \main_converter1_reset + attribute \src "ls180.v:7745.6-7745.27" + case 1'1 + assign $0\main_converter1_counter[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7749.2-7751.5" + switch $or$ls180.v:7749$2600_Y + attribute \src "ls180.v:7749.6-7749.51" + case 1'1 + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r + case + end + attribute \src "ls180.v:7753.2-7755.5" + switch \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:7753.6-7753.57" + case 1'1 + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value + case + end + attribute \src "ls180.v:7756.2-7759.5" + switch \main_socbushandler_reset + attribute \src "ls180.v:7756.6-7756.30" + case 1'1 + assign $0\main_socbushandler_counter[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7760.2-7764.5" + switch $ne$ls180.v:7760$2601_Y + attribute \src "ls180.v:7760.6-7760.53" + case 1'1 + attribute \src "ls180.v:7761.3-7763.6" + switch \main_libresocsim_bus_error + attribute \src "ls180.v:7761.7-7761.33" + case 1'1 + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7762$2602_Y + case + end + case + end + attribute \src "ls180.v:7766.2-7768.5" + switch $and$ls180.v:7766$2605_Y + attribute \src "ls180.v:7766.6-7766.103" + case 1'1 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7769.2-7777.5" + switch \main_libresocsim_en_storage + attribute \src "ls180.v:7769.6-7769.33" + case 1'1 + attribute \src "ls180.v:7770.3-7774.6" + switch $eq$ls180.v:7770$2606_Y + attribute \src "ls180.v:7770.7-7770.39" + case 1'1 + assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage + attribute \src "ls180.v:7772.7-7772.11" + case + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7773$2607_Y + end + attribute \src "ls180.v:7775.6-7775.10" + case + assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage + end + attribute \src "ls180.v:7778.2-7780.5" + switch \main_libresocsim_update_value_re + attribute \src "ls180.v:7778.6-7778.38" + case 1'1 + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value + case + end + attribute \src "ls180.v:7781.2-7783.5" + switch \main_libresocsim_zero_clear + attribute \src "ls180.v:7781.6-7781.33" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7785.2-7787.5" + switch $and$ls180.v:7785$2609_Y + attribute \src "ls180.v:7785.6-7785.76" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7789.2-7791.5" + switch $and$ls180.v:7789$2612_Y + attribute \src "ls180.v:7789.6-7789.100" + case 1'1 + assign $0\main_interface0_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7793.2-7795.5" + switch $and$ls180.v:7793$2615_Y + attribute \src "ls180.v:7793.6-7793.100" + case 1'1 + assign $0\main_interface1_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7797.2-7799.5" + switch $and$ls180.v:7797$2618_Y + attribute \src "ls180.v:7797.6-7797.100" + case 1'1 + assign $0\main_interface2_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7801.2-7803.5" + switch $and$ls180.v:7801$2621_Y + attribute \src "ls180.v:7801.6-7801.100" + case 1'1 + assign $0\main_interface3_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7806.2-7808.5" + switch \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:7806.6-7806.37" + case 1'1 + assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata + case + end + attribute \src "ls180.v:7809.2-7813.5" + switch $and$ls180.v:7809$2623_Y + attribute \src "ls180.v:7809.6-7809.57" + case 1'1 + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7810$2624_Y + attribute \src "ls180.v:7811.6-7811.10" + case + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + end + attribute \src "ls180.v:7815.2-7821.5" + switch \main_sdram_postponer_req_i + attribute \src "ls180.v:7815.6-7815.32" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7816$2625_Y + attribute \src "ls180.v:7817.3-7820.6" + switch $eq$ls180.v:7817$2626_Y + attribute \src "ls180.v:7817.7-7817.43" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_postponer_req_o[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:7822.2-7830.5" + switch \main_sdram_sequencer_start0 + attribute \src "ls180.v:7822.6-7822.33" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + attribute \src "ls180.v:7824.6-7824.10" + case + attribute \src "ls180.v:7825.3-7829.6" + switch \main_sdram_sequencer_done1 + attribute \src "ls180.v:7825.7-7825.33" + case 1'1 + attribute \src "ls180.v:7826.4-7828.7" + switch $ne$ls180.v:7826$2627_Y + attribute \src "ls180.v:7826.8-7826.44" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7827$2628_Y + case + end + case + end + end + attribute \src "ls180.v:7837.2-7843.5" + switch $and$ls180.v:7837$2630_Y + attribute \src "ls180.v:7837.6-7837.76" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + case + end + attribute \src "ls180.v:7844.2-7850.5" + switch $eq$ls180.v:7844$2631_Y + attribute \src "ls180.v:7844.6-7844.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + case + end + attribute \src "ls180.v:7851.2-7858.5" + switch $eq$ls180.v:7851$2632_Y + attribute \src "ls180.v:7851.6-7851.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'1 + case + end + attribute \src "ls180.v:7859.2-7869.5" + switch $eq$ls180.v:7859$2633_Y + attribute \src "ls180.v:7859.6-7859.44" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + attribute \src "ls180.v:7861.6-7861.10" + case + attribute \src "ls180.v:7862.3-7868.6" + switch $ne$ls180.v:7862$2634_Y + attribute \src "ls180.v:7862.7-7862.45" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7863$2635_Y + attribute \src "ls180.v:7864.7-7864.11" + case + attribute \src "ls180.v:7865.4-7867.7" + switch \main_sdram_sequencer_start1 + attribute \src "ls180.v:7865.8-7865.35" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + case + end + end + end + attribute \src "ls180.v:7871.2-7878.5" + switch \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:7871.6-7871.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "ls180.v:7873.6-7873.10" + case + attribute \src "ls180.v:7874.3-7877.6" + switch \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:7874.7-7874.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7879.2-7881.5" + switch $and$ls180.v:7879$2638_Y + attribute \src "ls180.v:7879.6-7879.191" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7880$2639_Y + case + end + attribute \src "ls180.v:7882.2-7884.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7882.6-7882.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7883$2640_Y + case + end + attribute \src "ls180.v:7885.2-7893.5" + switch $and$ls180.v:7885$2643_Y + attribute \src "ls180.v:7885.6-7885.191" + case 1'1 + attribute \src "ls180.v:7886.3-7888.6" + switch $not$ls180.v:7886$2644_Y + attribute \src "ls180.v:7886.7-7886.62" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7887$2645_Y + case + end + attribute \src "ls180.v:7889.6-7889.10" + case + attribute \src "ls180.v:7890.3-7892.6" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7890.7-7890.59" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7891$2646_Y + case + end + end + attribute \src "ls180.v:7894.2-7900.5" + switch $or$ls180.v:7894$2648_Y + attribute \src "ls180.v:7894.6-7894.108" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7901.2-7915.5" + switch \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:7901.6-7901.43" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7903.3-7907.6" + switch 1'0 + attribute \src "ls180.v:7905.7-7905.11" + case + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7908.6-7908.10" + case + attribute \src "ls180.v:7909.3-7914.6" + switch $not$ls180.v:7909$2649_Y + attribute \src "ls180.v:7909.7-7909.47" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7910$2650_Y + attribute \src "ls180.v:7911.4-7913.7" + switch $eq$ls180.v:7911$2651_Y + attribute \src "ls180.v:7911.8-7911.55" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7917.2-7924.5" + switch \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:7917.6-7917.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "ls180.v:7919.6-7919.10" + case + attribute \src "ls180.v:7920.3-7923.6" + switch \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:7920.7-7920.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7925.2-7927.5" + switch $and$ls180.v:7925$2654_Y + attribute \src "ls180.v:7925.6-7925.191" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7926$2655_Y + case + end + attribute \src "ls180.v:7928.2-7930.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7928.6-7928.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7929$2656_Y + case + end + attribute \src "ls180.v:7931.2-7939.5" + switch $and$ls180.v:7931$2659_Y + attribute \src "ls180.v:7931.6-7931.191" + case 1'1 + attribute \src "ls180.v:7932.3-7934.6" + switch $not$ls180.v:7932$2660_Y + attribute \src "ls180.v:7932.7-7932.62" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7933$2661_Y + case + end + attribute \src "ls180.v:7935.6-7935.10" + case + attribute \src "ls180.v:7936.3-7938.6" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7936.7-7936.59" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7937$2662_Y + case + end + end + attribute \src "ls180.v:7940.2-7946.5" + switch $or$ls180.v:7940$2664_Y + attribute \src "ls180.v:7940.6-7940.108" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7947.2-7961.5" + switch \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:7947.6-7947.43" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7949.3-7953.6" + switch 1'0 + attribute \src "ls180.v:7951.7-7951.11" + case + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7954.6-7954.10" + case + attribute \src "ls180.v:7955.3-7960.6" + switch $not$ls180.v:7955$2665_Y + attribute \src "ls180.v:7955.7-7955.47" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7956$2666_Y + attribute \src "ls180.v:7957.4-7959.7" + switch $eq$ls180.v:7957$2667_Y + attribute \src "ls180.v:7957.8-7957.55" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7963.2-7970.5" + switch \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:7963.6-7963.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "ls180.v:7965.6-7965.10" + case + attribute \src "ls180.v:7966.3-7969.6" + switch \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:7966.7-7966.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7971.2-7973.5" + switch $and$ls180.v:7971$2670_Y + attribute \src "ls180.v:7971.6-7971.191" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7972$2671_Y + case + end + attribute \src "ls180.v:7974.2-7976.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7974.6-7974.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7975$2672_Y + case + end + attribute \src "ls180.v:7977.2-7985.5" + switch $and$ls180.v:7977$2675_Y + attribute \src "ls180.v:7977.6-7977.191" + case 1'1 + attribute \src "ls180.v:7978.3-7980.6" + switch $not$ls180.v:7978$2676_Y + attribute \src "ls180.v:7978.7-7978.62" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7979$2677_Y + case + end + attribute \src "ls180.v:7981.6-7981.10" + case + attribute \src "ls180.v:7982.3-7984.6" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7982.7-7982.59" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7983$2678_Y + case + end + end + attribute \src "ls180.v:7986.2-7992.5" + switch $or$ls180.v:7986$2680_Y + attribute \src "ls180.v:7986.6-7986.108" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7993.2-8007.5" + switch \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:7993.6-7993.43" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7995.3-7999.6" + switch 1'0 + attribute \src "ls180.v:7997.7-7997.11" + case + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:8000.6-8000.10" + case + attribute \src "ls180.v:8001.3-8006.6" + switch $not$ls180.v:8001$2681_Y + attribute \src "ls180.v:8001.7-8001.47" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8002$2682_Y + attribute \src "ls180.v:8003.4-8005.7" + switch $eq$ls180.v:8003$2683_Y + attribute \src "ls180.v:8003.8-8003.55" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:8009.2-8016.5" + switch \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:8009.6-8009.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "ls180.v:8011.6-8011.10" + case + attribute \src "ls180.v:8012.3-8015.6" + switch \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:8012.7-8012.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:8017.2-8019.5" + switch $and$ls180.v:8017$2686_Y + attribute \src "ls180.v:8017.6-8017.191" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8018$2687_Y + case + end + attribute \src "ls180.v:8020.2-8022.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:8020.6-8020.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8021$2688_Y + case + end + attribute \src "ls180.v:8023.2-8031.5" + switch $and$ls180.v:8023$2691_Y + attribute \src "ls180.v:8023.6-8023.191" + case 1'1 + attribute \src "ls180.v:8024.3-8026.6" + switch $not$ls180.v:8024$2692_Y + attribute \src "ls180.v:8024.7-8024.62" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8025$2693_Y + case + end + attribute \src "ls180.v:8027.6-8027.10" + case + attribute \src "ls180.v:8028.3-8030.6" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:8028.7-8028.59" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8029$2694_Y + case + end + end + attribute \src "ls180.v:8032.2-8038.5" + switch $or$ls180.v:8032$2696_Y + attribute \src "ls180.v:8032.6-8032.108" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:8039.2-8053.5" + switch \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:8039.6-8039.43" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:8041.3-8045.6" + switch 1'0 + attribute \src "ls180.v:8043.7-8043.11" + case + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:8046.6-8046.10" + case + attribute \src "ls180.v:8047.3-8052.6" + switch $not$ls180.v:8047$2697_Y + attribute \src "ls180.v:8047.7-8047.47" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8048$2698_Y + attribute \src "ls180.v:8049.4-8051.7" + switch $eq$ls180.v:8049$2699_Y + attribute \src "ls180.v:8049.8-8049.55" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:8055.2-8061.5" + switch $not$ls180.v:8055$2700_Y + attribute \src "ls180.v:8055.6-8055.23" + case 1'1 + assign $0\main_sdram_time0[4:0] 5'11111 + attribute \src "ls180.v:8057.6-8057.10" + case + attribute \src "ls180.v:8058.3-8060.6" + switch $not$ls180.v:8058$2701_Y + attribute \src "ls180.v:8058.7-8058.30" + case 1'1 + assign $0\main_sdram_time0[4:0] $sub$ls180.v:8059$2702_Y + case + end + end + attribute \src "ls180.v:8062.2-8068.5" + switch $not$ls180.v:8062$2703_Y + attribute \src "ls180.v:8062.6-8062.23" + case 1'1 + assign $0\main_sdram_time1[3:0] 4'1111 + attribute \src "ls180.v:8064.6-8064.10" + case + attribute \src "ls180.v:8065.3-8067.6" + switch $not$ls180.v:8065$2704_Y + attribute \src "ls180.v:8065.7-8065.30" + case 1'1 + assign $0\main_sdram_time1[3:0] $sub$ls180.v:8066$2705_Y + case + end + end + attribute \src "ls180.v:8069.2-8124.5" + switch \main_sdram_choose_cmd_ce + attribute \src "ls180.v:8069.6-8069.30" + case 1'1 + attribute \src "ls180.v:8070.3-8123.10" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:8072.5-8082.8" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:8072.9-8072.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:8074.9-8074.13" + case + attribute \src "ls180.v:8075.6-8081.9" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:8075.10-8075.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:8077.10-8077.14" + case + attribute \src "ls180.v:8078.7-8080.10" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:8078.11-8078.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:8085.5-8095.8" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:8085.9-8085.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:8087.9-8087.13" + case + attribute \src "ls180.v:8088.6-8094.9" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:8088.10-8088.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:8090.10-8090.14" + case + attribute \src "ls180.v:8091.7-8093.10" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:8091.11-8091.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:8098.5-8108.8" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:8098.9-8098.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:8100.9-8100.13" + case + attribute \src "ls180.v:8101.6-8107.9" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:8101.10-8101.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:8103.10-8103.14" + case + attribute \src "ls180.v:8104.7-8106.10" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:8104.11-8104.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:8111.5-8121.8" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:8111.9-8111.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:8113.9-8113.13" + case + attribute \src "ls180.v:8114.6-8120.9" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:8114.10-8114.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:8116.10-8116.14" + case + attribute \src "ls180.v:8117.7-8119.10" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:8117.11-8117.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:8125.2-8180.5" + switch \main_sdram_choose_req_ce + attribute \src "ls180.v:8125.6-8125.30" + case 1'1 + attribute \src "ls180.v:8126.3-8179.10" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:8128.5-8138.8" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:8128.9-8128.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:8130.9-8130.13" + case + attribute \src "ls180.v:8131.6-8137.9" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:8131.10-8131.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:8133.10-8133.14" + case + attribute \src "ls180.v:8134.7-8136.10" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:8134.11-8134.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:8141.5-8151.8" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:8141.9-8141.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:8143.9-8143.13" + case + attribute \src "ls180.v:8144.6-8150.9" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:8144.10-8144.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:8146.10-8146.14" + case + attribute \src "ls180.v:8147.7-8149.10" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:8147.11-8147.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:8154.5-8164.8" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:8154.9-8154.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:8156.9-8156.13" + case + attribute \src "ls180.v:8157.6-8163.9" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:8157.10-8157.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:8159.10-8159.14" + case + attribute \src "ls180.v:8160.7-8162.10" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:8160.11-8160.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:8167.5-8177.8" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:8167.9-8167.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:8169.9-8169.13" + case + attribute \src "ls180.v:8170.6-8176.9" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:8170.10-8170.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:8172.10-8172.14" + case + attribute \src "ls180.v:8173.7-8175.10" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:8173.11-8173.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:8189.2-8203.5" + switch \main_sdram_tccdcon_valid + attribute \src "ls180.v:8189.6-8189.30" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + attribute \src "ls180.v:8191.3-8195.6" + switch 1'1 + attribute \src "ls180.v:8191.7-8191.11" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:8196.6-8196.10" + case + attribute \src "ls180.v:8197.3-8202.6" + switch $not$ls180.v:8197$2709_Y + attribute \src "ls180.v:8197.7-8197.34" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8198$2710_Y + attribute \src "ls180.v:8199.4-8201.7" + switch $eq$ls180.v:8199$2711_Y + attribute \src "ls180.v:8199.8-8199.42" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:8204.2-8218.5" + switch \main_sdram_twtrcon_valid + attribute \src "ls180.v:8204.6-8204.30" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] 3'100 + attribute \src "ls180.v:8206.3-8210.6" + switch 1'0 + attribute \src "ls180.v:8208.7-8208.11" + case + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:8211.6-8211.10" + case + attribute \src "ls180.v:8212.3-8217.6" + switch $not$ls180.v:8212$2712_Y + attribute \src "ls180.v:8212.7-8212.34" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8213$2713_Y + attribute \src "ls180.v:8214.4-8216.7" + switch $eq$ls180.v:8214$2714_Y + attribute \src "ls180.v:8214.8-8214.42" + case 1'1 + assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:8225.2-8227.5" + switch $or$ls180.v:8225$2739_Y + attribute \src "ls180.v:8225.6-8225.50" + case 1'1 + assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + case + end + attribute \src "ls180.v:8229.2-8231.5" + switch \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:8229.6-8229.52" + case 1'1 + assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + case + end + attribute \src "ls180.v:8232.2-8235.5" + switch \main_converter_reset + attribute \src "ls180.v:8232.6-8232.26" + case 1'1 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + case + end + attribute \src "ls180.v:8236.2-8246.5" + switch \main_litedram_wb_ack + attribute \src "ls180.v:8236.6-8236.26" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + attribute \src "ls180.v:8239.6-8239.10" + case + attribute \src "ls180.v:8240.3-8242.6" + switch $and$ls180.v:8240$2740_Y + attribute \src "ls180.v:8240.7-8240.50" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'1 + case + end + attribute \src "ls180.v:8243.3-8245.6" + switch $and$ls180.v:8243$2741_Y + attribute \src "ls180.v:8243.7-8243.54" + case 1'1 + assign $0\main_wdata_consumed[0:0] 1'1 + case + end + end + attribute \src "ls180.v:8248.2-8269.5" + switch $and$ls180.v:8248$2745_Y + attribute \src "ls180.v:8248.6-8248.91" + case 1'1 + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data + assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 + assign $0\main_uart_phy_tx_busy[0:0] 1'1 + assign $0\uart_tx[0:0] 1'0 + attribute \src "ls180.v:8253.6-8253.10" + case + attribute \src "ls180.v:8254.3-8268.6" + switch $and$ls180.v:8254$2746_Y + attribute \src "ls180.v:8254.7-8254.60" + case 1'1 + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8255$2747_Y + attribute \src "ls180.v:8256.4-8267.7" + switch $eq$ls180.v:8256$2748_Y + attribute \src "ls180.v:8256.8-8256.43" + case 1'1 + assign $0\uart_tx[0:0] 1'1 + attribute \src "ls180.v:8258.8-8258.12" + case + attribute \src "ls180.v:8259.5-8266.8" + switch $eq$ls180.v:8259$2749_Y + attribute \src "ls180.v:8259.9-8259.44" + case 1'1 + assign $0\uart_tx[0:0] 1'1 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'1 + attribute \src "ls180.v:8263.9-8263.13" + case + assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] + assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:8270.2-8274.5" + switch \main_uart_phy_tx_busy + attribute \src "ls180.v:8270.6-8270.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8271$2750_Y + attribute \src "ls180.v:8272.6-8272.10" + case + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } + end + attribute \src "ls180.v:8277.2-8301.5" + switch $not$ls180.v:8277$2751_Y + attribute \src "ls180.v:8277.6-8277.30" + case 1'1 + attribute \src "ls180.v:8278.3-8281.6" + switch $and$ls180.v:8278$2753_Y + attribute \src "ls180.v:8278.7-8278.49" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 + case + end + attribute \src "ls180.v:8282.6-8282.10" + case + attribute \src "ls180.v:8283.3-8300.6" + switch \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:8283.7-8283.34" + case 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8284$2754_Y + attribute \src "ls180.v:8285.4-8299.7" + switch $eq$ls180.v:8285$2755_Y + attribute \src "ls180.v:8285.8-8285.43" + case 1'1 + attribute \src "ls180.v:8286.5-8288.8" + switch \main_uart_phy_rx + attribute \src "ls180.v:8286.9-8286.25" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + case + end + attribute \src "ls180.v:8289.8-8289.12" + case + attribute \src "ls180.v:8290.5-8298.8" + switch $eq$ls180.v:8290$2756_Y + attribute \src "ls180.v:8290.9-8290.44" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + attribute \src "ls180.v:8292.6-8295.9" + switch \main_uart_phy_rx + attribute \src "ls180.v:8292.10-8292.26" + case 1'1 + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_source_valid[0:0] 1'1 + case + end + attribute \src "ls180.v:8296.9-8296.13" + case + assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:8302.2-8306.5" + switch \main_uart_phy_rx_busy + attribute \src "ls180.v:8302.6-8302.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8303$2757_Y + attribute \src "ls180.v:8304.6-8304.10" + case + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 + end + attribute \src "ls180.v:8307.2-8309.5" + switch \main_uart_tx_clear + attribute \src "ls180.v:8307.6-8307.24" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8311.2-8313.5" + switch $and$ls180.v:8311$2759_Y + attribute \src "ls180.v:8311.6-8311.58" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8314.2-8316.5" + switch \main_uart_rx_clear + attribute \src "ls180.v:8314.6-8314.24" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8318.2-8320.5" + switch $and$ls180.v:8318$2761_Y + attribute \src "ls180.v:8318.6-8318.58" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8321.2-8327.5" + switch \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:8321.6-8321.35" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8323.6-8323.10" + case + attribute \src "ls180.v:8324.3-8326.6" + switch \main_uart_tx_fifo_re + attribute \src "ls180.v:8324.7-8324.27" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8328.2-8330.5" + switch $and$ls180.v:8328$2764_Y + attribute \src "ls180.v:8328.6-8328.108" + case 1'1 + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8329$2765_Y + case + end + attribute \src "ls180.v:8331.2-8333.5" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8331.6-8331.31" + case 1'1 + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8332$2766_Y + case + end + attribute \src "ls180.v:8334.2-8342.5" + switch $and$ls180.v:8334$2769_Y + attribute \src "ls180.v:8334.6-8334.108" + case 1'1 + attribute \src "ls180.v:8335.3-8337.6" + switch $not$ls180.v:8335$2770_Y + attribute \src "ls180.v:8335.7-8335.35" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8336$2771_Y + case + end + attribute \src "ls180.v:8338.6-8338.10" + case + attribute \src "ls180.v:8339.3-8341.6" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8339.7-8339.32" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8340$2772_Y + case + end + end + attribute \src "ls180.v:8343.2-8349.5" + switch \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:8343.6-8343.35" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8345.6-8345.10" + case + attribute \src "ls180.v:8346.3-8348.6" + switch \main_uart_rx_fifo_re + attribute \src "ls180.v:8346.7-8346.27" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8350.2-8352.5" + switch $and$ls180.v:8350$2775_Y + attribute \src "ls180.v:8350.6-8350.108" + case 1'1 + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8351$2776_Y + case + end + attribute \src "ls180.v:8353.2-8355.5" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8353.6-8353.31" + case 1'1 + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8354$2777_Y + case + end + attribute \src "ls180.v:8356.2-8364.5" + switch $and$ls180.v:8356$2780_Y + attribute \src "ls180.v:8356.6-8356.108" + case 1'1 + attribute \src "ls180.v:8357.3-8359.6" + switch $not$ls180.v:8357$2781_Y + attribute \src "ls180.v:8357.7-8357.35" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8358$2782_Y + case + end + attribute \src "ls180.v:8360.6-8360.10" + case + attribute \src "ls180.v:8361.3-8363.6" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8361.7-8361.32" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8362$2783_Y + case + end + end + attribute \src "ls180.v:8365.2-8378.5" + switch \main_uart_reset + attribute \src "ls180.v:8365.6-8365.21" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + case + end + attribute \src "ls180.v:8380.2-8387.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8380.6-8380.31" + case 1'1 + assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable + attribute \src "ls180.v:8382.6-8382.10" + case + attribute \src "ls180.v:8383.3-8386.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8383.7-8383.32" + case 1'1 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\spisdcard_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8389.2-8399.5" + switch \main_spimaster28_mosi_latch + attribute \src "ls180.v:8389.6-8389.33" + case 1'1 + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi + assign $0\main_spimaster34_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8392.6-8392.10" + case + attribute \src "ls180.v:8393.3-8398.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8393.7-8393.32" + case 1'1 + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8397$2788_Y + attribute \src "ls180.v:8394.4-8396.7" + switch \main_spimaster26_cs_enable + attribute \src "ls180.v:8394.8-8394.34" + case 1'1 + assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 + case + end + case + end + end + attribute \src "ls180.v:8400.2-8406.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8400.6-8400.31" + case 1'1 + attribute \src "ls180.v:8401.3-8405.6" + switch \main_spimaster7_loopback + attribute \src "ls180.v:8401.7-8401.31" + case 1'1 + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } + attribute \src "ls180.v:8403.7-8403.11" + case + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } + end + case + end + attribute \src "ls180.v:8407.2-8409.5" + switch \main_spimaster29_miso_latch + attribute \src "ls180.v:8407.6-8407.33" + case 1'1 + assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data + case + end + attribute \src "ls180.v:8411.2-8413.5" + switch \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:8411.6-8411.53" + case 1'1 + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value + case + end + attribute \src "ls180.v:8415.2-8422.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8415.6-8415.29" + case 1'1 + assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable + attribute \src "ls180.v:8417.6-8417.10" + case + attribute \src "ls180.v:8418.3-8421.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8418.7-8418.30" + case 1'1 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\spimaster_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8424.2-8434.5" + switch \main_spisdcard_mosi_latch + attribute \src "ls180.v:8424.6-8424.31" + case 1'1 + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi + assign $0\main_spisdcard_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8427.6-8427.10" + case + attribute \src "ls180.v:8428.3-8433.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8428.7-8428.30" + case 1'1 + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8432$2793_Y + attribute \src "ls180.v:8429.4-8431.7" + switch \main_spisdcard_cs_enable + attribute \src "ls180.v:8429.8-8429.32" + case 1'1 + assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 + case + end + case + end + end + attribute \src "ls180.v:8435.2-8441.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8435.6-8435.29" + case 1'1 + attribute \src "ls180.v:8436.3-8440.6" + switch \main_spisdcard_loopback + attribute \src "ls180.v:8436.7-8436.30" + case 1'1 + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } + attribute \src "ls180.v:8438.7-8438.11" + case + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } + end + case + end + attribute \src "ls180.v:8442.2-8444.5" + switch \main_spisdcard_miso_latch + attribute \src "ls180.v:8442.6-8442.31" + case 1'1 + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data + case + end + attribute \src "ls180.v:8446.2-8448.5" + switch \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:8446.6-8446.51" + case 1'1 + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value + case + end + attribute \src "ls180.v:8449.2-8462.5" + switch \main_pwm0_enable + attribute \src "ls180.v:8449.6-8449.22" + case 1'1 + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8450$2794_Y + attribute \src "ls180.v:8451.3-8455.6" + switch $lt$ls180.v:8451$2795_Y + attribute \src "ls180.v:8451.7-8451.44" + case 1'1 + assign $0\pwm[1:0] [0] 1'1 + attribute \src "ls180.v:8453.7-8453.11" + case + assign $0\pwm[1:0] [0] 1'0 + end + attribute \src "ls180.v:8456.3-8458.6" + switch $ge$ls180.v:8456$2797_Y + attribute \src "ls180.v:8456.7-8456.55" + case 1'1 + assign $0\main_pwm0_counter[31:0] 0 + case + end + attribute \src "ls180.v:8459.6-8459.10" + case + assign $0\main_pwm0_counter[31:0] 0 + assign $0\pwm[1:0] [0] 1'0 + end + attribute \src "ls180.v:8463.2-8476.5" + switch \main_pwm1_enable + attribute \src "ls180.v:8463.6-8463.22" + case 1'1 + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8464$2798_Y + attribute \src "ls180.v:8465.3-8469.6" + switch $lt$ls180.v:8465$2799_Y + attribute \src "ls180.v:8465.7-8465.44" + case 1'1 + assign $0\pwm[1:0] [1] 1'1 + attribute \src "ls180.v:8467.7-8467.11" + case + assign $0\pwm[1:0] [1] 1'0 + end + attribute \src "ls180.v:8470.3-8472.6" + switch $ge$ls180.v:8470$2801_Y + attribute \src "ls180.v:8470.7-8470.55" + case 1'1 + assign $0\main_pwm1_counter[31:0] 0 + case + end + attribute \src "ls180.v:8473.6-8473.10" + case + assign $0\main_pwm1_counter[31:0] 0 + assign $0\pwm[1:0] [1] 1'0 + end + attribute \src "ls180.v:8477.2-8479.5" + switch $not$ls180.v:8477$2802_Y + attribute \src "ls180.v:8477.6-8477.32" + case 1'1 + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8478$2803_Y + case + end + attribute \src "ls180.v:8483.2-8485.5" + switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:8483.6-8483.57" + case 1'1 + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value + case + end + attribute \src "ls180.v:8487.2-8489.5" + switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:8487.6-8487.57" + case 1'1 + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + case + end + attribute \src "ls180.v:8490.2-8492.5" + switch \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:8490.6-8490.40" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8491$2804_Y + case + end + attribute \src "ls180.v:8493.2-8495.5" + switch \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:8493.6-8493.49" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8496.2-8503.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8496.6-8496.46" + case 1'1 + attribute \src "ls180.v:8497.3-8502.6" + switch $or$ls180.v:8497$2806_Y + attribute \src "ls180.v:8497.7-8497.98" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8500.7-8500.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8501$2807_Y + end + case + end + attribute \src "ls180.v:8504.2-8517.5" + switch $and$ls180.v:8504$2808_Y + attribute \src "ls180.v:8504.6-8504.97" + case 1'1 + attribute \src "ls180.v:8505.3-8511.6" + switch $and$ls180.v:8505$2809_Y + attribute \src "ls180.v:8505.7-8505.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:8508.7-8508.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8512.6-8512.10" + case + attribute \src "ls180.v:8513.3-8516.6" + switch $and$ls180.v:8513$2810_Y + attribute \src "ls180.v:8513.7-8513.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8514$2811_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8515$2812_Y + case + end + end + attribute \src "ls180.v:8518.2-8545.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8518.6-8518.46" + case 1'1 + attribute \src "ls180.v:8519.3-8544.10" + switch \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8546.2-8548.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8546.6-8546.46" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8547$2813_Y + case + end + attribute \src "ls180.v:8549.2-8554.5" + switch $or$ls180.v:8549$2815_Y + attribute \src "ls180.v:8549.6-8549.88" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8555.2-8560.5" + switch \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:8555.6-8555.32" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8562.2-8564.5" + switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:8562.6-8562.58" + case 1'1 + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + case + end + attribute \src "ls180.v:8565.2-8567.5" + switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:8565.6-8565.60" + case 1'1 + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + case + end + attribute \src "ls180.v:8568.2-8570.5" + switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:8568.6-8568.63" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + case + end + attribute \src "ls180.v:8571.2-8573.5" + switch \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:8571.6-8571.41" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8572$2816_Y + case + end + attribute \src "ls180.v:8574.2-8576.5" + switch \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:8574.6-8574.50" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8577.2-8584.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8577.6-8577.47" + case 1'1 + attribute \src "ls180.v:8578.3-8583.6" + switch $or$ls180.v:8578$2818_Y + attribute \src "ls180.v:8578.7-8578.100" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8581.7-8581.11" + case + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8582$2819_Y + end + case + end + attribute \src "ls180.v:8585.2-8598.5" + switch $and$ls180.v:8585$2820_Y + attribute \src "ls180.v:8585.6-8585.99" + case 1'1 + attribute \src "ls180.v:8586.3-8592.6" + switch $and$ls180.v:8586$2821_Y + attribute \src "ls180.v:8586.7-8586.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:8589.7-8589.11" + case + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8593.6-8593.10" + case + attribute \src "ls180.v:8594.3-8597.6" + switch $and$ls180.v:8594$2822_Y + attribute \src "ls180.v:8594.7-8594.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8595$2823_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8596$2824_Y + case + end + end + attribute \src "ls180.v:8599.2-8626.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8599.6-8599.47" + case 1'1 + attribute \src "ls180.v:8600.3-8625.10" + switch \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8627.2-8629.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8627.6-8627.47" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8628$2825_Y + case + end + attribute \src "ls180.v:8630.2-8635.5" + switch $or$ls180.v:8630$2827_Y + attribute \src "ls180.v:8630.6-8630.90" + case 1'1 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8636.2-8641.5" + switch \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:8636.6-8636.33" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8643.2-8645.5" + switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:8643.6-8643.63" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + case + end + attribute \src "ls180.v:8647.2-8649.5" + switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:8647.6-8647.52" + case 1'1 + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value + case + end + attribute \src "ls180.v:8650.2-8652.5" + switch \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:8650.6-8650.42" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8651$2828_Y + case + end + attribute \src "ls180.v:8653.2-8655.5" + switch \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:8653.6-8653.51" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8656.2-8663.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8656.6-8656.48" + case 1'1 + attribute \src "ls180.v:8657.3-8662.6" + switch $or$ls180.v:8657$2830_Y + attribute \src "ls180.v:8657.7-8657.102" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8660.7-8660.11" + case + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8661$2831_Y + end + case + end + attribute \src "ls180.v:8664.2-8677.5" + switch $and$ls180.v:8664$2832_Y + attribute \src "ls180.v:8664.6-8664.101" + case 1'1 + attribute \src "ls180.v:8665.3-8671.6" + switch $and$ls180.v:8665$2833_Y + attribute \src "ls180.v:8665.7-8665.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:8668.7-8668.11" + case + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8672.6-8672.10" + case + attribute \src "ls180.v:8673.3-8676.6" + switch $and$ls180.v:8673$2834_Y + attribute \src "ls180.v:8673.7-8673.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8674$2835_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8675$2836_Y + case + end + end + attribute \src "ls180.v:8678.2-8687.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8678.6-8678.48" + case 1'1 + attribute \src "ls180.v:8679.3-8686.10" + switch \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8688.2-8690.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8688.6-8688.48" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8689$2837_Y + case + end + attribute \src "ls180.v:8691.2-8696.5" + switch $or$ls180.v:8691$2839_Y + attribute \src "ls180.v:8691.6-8691.92" + case 1'1 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data + case + end + attribute \src "ls180.v:8697.2-8702.5" + switch \main_sdphy_datar_datar_reset + attribute \src "ls180.v:8697.6-8697.34" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8704.2-8706.5" + switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:8704.6-8704.60" + case 1'1 + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + case + end + attribute \src "ls180.v:8707.2-8709.5" + switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:8707.6-8707.62" + case 1'1 + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + case + end + attribute \src "ls180.v:8710.2-8712.5" + switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:8710.6-8710.66" + case 1'1 + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + case + end + attribute \src "ls180.v:8713.2-8719.5" + switch \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:8713.6-8713.35" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + attribute \src "ls180.v:8715.6-8715.10" + case + attribute \src "ls180.v:8716.3-8718.6" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:8716.7-8716.39" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 + case + end + end + attribute \src "ls180.v:8720.2-8726.5" + switch \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:8720.6-8720.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8722.6-8722.10" + case + attribute \src "ls180.v:8723.3-8725.6" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:8723.7-8723.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8727.2-8733.5" + switch \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:8727.6-8727.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8729.6-8729.10" + case + attribute \src "ls180.v:8730.3-8732.6" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:8730.7-8730.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8734.2-8740.5" + switch \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:8734.6-8734.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8736.6-8736.10" + case + attribute \src "ls180.v:8737.3-8739.6" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:8737.7-8737.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8741.2-8747.5" + switch \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:8741.6-8741.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8743.6-8743.10" + case + attribute \src "ls180.v:8744.3-8746.6" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:8744.7-8744.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8749.2-8751.5" + switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:8749.6-8749.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + case + end + attribute \src "ls180.v:8752.2-8754.5" + switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:8752.6-8752.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + case + end + attribute \src "ls180.v:8755.2-8757.5" + switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:8755.6-8755.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + case + end + attribute \src "ls180.v:8758.2-8760.5" + switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:8758.6-8758.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + case + end + attribute \src "ls180.v:8761.2-8763.5" + switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:8761.6-8761.78" + case 1'1 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + case + end + attribute \src "ls180.v:8764.2-8766.5" + switch $and$ls180.v:8764$2840_Y + attribute \src "ls180.v:8764.6-8764.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc + case + end + attribute \src "ls180.v:8767.2-8769.5" + switch $and$ls180.v:8767$2841_Y + attribute \src "ls180.v:8767.6-8767.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc + case + end + attribute \src "ls180.v:8770.2-8772.5" + switch $and$ls180.v:8770$2842_Y + attribute \src "ls180.v:8770.6-8770.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc + case + end + attribute \src "ls180.v:8773.2-8775.5" + switch $and$ls180.v:8773$2843_Y + attribute \src "ls180.v:8773.6-8773.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + case + end + attribute \src "ls180.v:8776.2-8780.5" + switch $and$ls180.v:8776$2844_Y + attribute \src "ls180.v:8776.6-8776.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } + assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] + case + end + attribute \src "ls180.v:8781.2-8785.5" + switch $and$ls180.v:8781$2845_Y + attribute \src "ls180.v:8781.6-8781.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } + assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] + case + end + attribute \src "ls180.v:8786.2-8790.5" + switch $and$ls180.v:8786$2846_Y + attribute \src "ls180.v:8786.6-8786.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } + assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] + case + end + attribute \src "ls180.v:8791.2-8795.5" + switch $and$ls180.v:8791$2847_Y + attribute \src "ls180.v:8791.6-8791.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } + assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] + case + end + attribute \src "ls180.v:8796.2-8804.5" + switch $and$ls180.v:8796$2848_Y + attribute \src "ls180.v:8796.6-8796.83" + case 1'1 + attribute \src "ls180.v:8797.3-8803.6" + switch \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:8797.7-8797.42" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + attribute \src "ls180.v:8799.7-8799.11" + case + attribute \src "ls180.v:8800.4-8802.7" + switch $ne$ls180.v:8800$2849_Y + attribute \src "ls180.v:8800.8-8800.48" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8801$2850_Y + case + end + end + case + end + attribute \src "ls180.v:8805.2-8811.5" + switch \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:8805.6-8805.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8807.6-8807.10" + case + attribute \src "ls180.v:8808.3-8810.6" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:8808.7-8808.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8812.2-8818.5" + switch \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:8812.6-8812.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8814.6-8814.10" + case + attribute \src "ls180.v:8815.3-8817.6" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:8815.7-8815.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8819.2-8825.5" + switch \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:8819.6-8819.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8821.6-8821.10" + case + attribute \src "ls180.v:8822.3-8824.6" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:8822.7-8822.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8826.2-8832.5" + switch \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:8826.6-8826.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8828.6-8828.10" + case + attribute \src "ls180.v:8829.3-8831.6" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:8829.7-8829.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8834.2-8836.5" + switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:8834.6-8834.52" + case 1'1 + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 + case + end + attribute \src "ls180.v:8837.2-8839.5" + switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:8837.6-8837.53" + case 1'1 + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 + case + end + attribute \src "ls180.v:8840.2-8842.5" + switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:8840.6-8840.53" + case 1'1 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 + case + end + attribute \src "ls180.v:8843.2-8845.5" + switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:8843.6-8843.54" + case 1'1 + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 + case + end + attribute \src "ls180.v:8846.2-8848.5" + switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:8846.6-8846.53" + case 1'1 + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 + case + end + attribute \src "ls180.v:8849.2-8851.5" + switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:8849.6-8849.55" + case 1'1 + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + case + end + attribute \src "ls180.v:8852.2-8854.5" + switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:8852.6-8852.54" + case 1'1 + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 + case + end + attribute \src "ls180.v:8855.2-8857.5" + switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:8855.6-8855.56" + case 1'1 + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 + case + end + attribute \src "ls180.v:8858.2-8860.5" + switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:8858.6-8858.63" + case 1'1 + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + case + end + attribute \src "ls180.v:8861.2-8863.5" + switch $and$ls180.v:8861$2853_Y + attribute \src "ls180.v:8861.6-8861.120" + case 1'1 + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8862$2854_Y + case + end + attribute \src "ls180.v:8864.2-8866.5" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8864.6-8864.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8865$2855_Y + case + end + attribute \src "ls180.v:8867.2-8875.5" + switch $and$ls180.v:8867$2858_Y + attribute \src "ls180.v:8867.6-8867.120" + case 1'1 + attribute \src "ls180.v:8868.3-8870.6" + switch $not$ls180.v:8868$2859_Y + attribute \src "ls180.v:8868.7-8868.39" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8869$2860_Y + case + end + attribute \src "ls180.v:8871.6-8871.10" + case + attribute \src "ls180.v:8872.3-8874.6" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8872.7-8872.36" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8873$2861_Y + case + end + end + attribute \src "ls180.v:8876.2-8878.5" + switch \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:8876.6-8876.45" + case 1'1 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8879.2-8886.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8879.6-8879.42" + case 1'1 + attribute \src "ls180.v:8880.3-8885.6" + switch $or$ls180.v:8880$2863_Y + attribute \src "ls180.v:8880.7-8880.90" + case 1'1 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8883.7-8883.11" + case + assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8884$2864_Y + end + case + end + attribute \src "ls180.v:8887.2-8900.5" + switch $and$ls180.v:8887$2865_Y + attribute \src "ls180.v:8887.6-8887.89" + case 1'1 + attribute \src "ls180.v:8888.3-8894.6" + switch $and$ls180.v:8888$2866_Y + attribute \src "ls180.v:8888.7-8888.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:8891.7-8891.11" + case + assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 + assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8895.6-8895.10" + case + attribute \src "ls180.v:8896.3-8899.6" + switch $and$ls180.v:8896$2867_Y + attribute \src "ls180.v:8896.7-8896.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8897$2868_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8898$2869_Y + case + end + end + attribute \src "ls180.v:8901.2-8928.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8901.6-8901.42" + case 1'1 + attribute \src "ls180.v:8902.3-8927.10" + switch \main_sdblock2mem_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [63:56] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [55:48] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [47:40] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [39:32] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8929.2-8931.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8929.6-8929.42" + case 1'1 + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8930$2870_Y + case + end + attribute \src "ls180.v:8933.2-8935.5" + switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:8933.6-8933.76" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + case + end + attribute \src "ls180.v:8936.2-8939.5" + switch \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:8936.6-8936.46" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8941.2-8943.5" + switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:8941.6-8941.64" + case 1'1 + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + case + end + attribute \src "ls180.v:8945.2-8947.5" + switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:8945.6-8945.76" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + case + end + attribute \src "ls180.v:8948.2-8951.5" + switch \main_sdmem2block_dma_reset + attribute \src "ls180.v:8948.6-8948.32" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8952.2-8958.5" + switch $and$ls180.v:8952$2871_Y + attribute \src "ls180.v:8952.6-8952.89" + case 1'1 + attribute \src "ls180.v:8953.3-8957.6" + switch \main_sdmem2block_converter_last + attribute \src "ls180.v:8953.7-8953.38" + case 1'1 + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 + attribute \src "ls180.v:8955.7-8955.11" + case + assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8956$2872_Y + end + case + end + attribute \src "ls180.v:8959.2-8961.5" + switch $and$ls180.v:8959$2875_Y + attribute \src "ls180.v:8959.6-8959.120" + case 1'1 + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8960$2876_Y + case + end + attribute \src "ls180.v:8962.2-8964.5" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8962.6-8962.35" + case 1'1 + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8963$2877_Y + case + end + attribute \src "ls180.v:8965.2-8973.5" + switch $and$ls180.v:8965$2880_Y + attribute \src "ls180.v:8965.6-8965.120" + case 1'1 + attribute \src "ls180.v:8966.3-8968.6" + switch $not$ls180.v:8966$2881_Y + attribute \src "ls180.v:8966.7-8966.39" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8967$2882_Y + case + end + attribute \src "ls180.v:8969.6-8969.10" + case + attribute \src "ls180.v:8970.3-8972.6" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8970.7-8970.36" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8971$2883_Y + case + end + end + attribute \src "ls180.v:8975.2-8977.5" + switch \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:8975.6-8975.46" + case 1'1 + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 + case + end + attribute \src "ls180.v:8978.2-8980.5" + switch \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:8978.6-8978.44" + case 1'1 + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 + case + end + attribute \src "ls180.v:8981.2-8983.5" + switch \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:8981.6-8981.43" + case 1'1 + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 + case + end + attribute \src "ls180.v:8984.2-9080.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + attribute \src "ls180.v:8986.4-9002.7" + switch $not$ls180.v:8986$2884_Y + attribute \src "ls180.v:8986.8-8986.29" + case 1'1 + attribute \src "ls180.v:8987.5-9001.8" + switch \builder_request [1] + attribute \src "ls180.v:8987.9-8987.27" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8989.9-8989.13" + case + attribute \src "ls180.v:8990.6-9000.9" + switch \builder_request [2] + attribute \src "ls180.v:8990.10-8990.28" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8992.10-8992.14" + case + attribute \src "ls180.v:8993.7-8999.10" + switch \builder_request [3] + attribute \src "ls180.v:8993.11-8993.29" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8995.11-8995.15" + case + attribute \src "ls180.v:8996.8-8998.11" + switch \builder_request [4] + attribute \src "ls180.v:8996.12-8996.30" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'001 + attribute \src "ls180.v:9005.4-9021.7" + switch $not$ls180.v:9005$2885_Y + attribute \src "ls180.v:9005.8-9005.29" + case 1'1 + attribute \src "ls180.v:9006.5-9020.8" + switch \builder_request [2] + attribute \src "ls180.v:9006.9-9006.27" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:9008.9-9008.13" + case + attribute \src "ls180.v:9009.6-9019.9" + switch \builder_request [3] + attribute \src "ls180.v:9009.10-9009.28" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:9011.10-9011.14" + case + attribute \src "ls180.v:9012.7-9018.10" + switch \builder_request [4] + attribute \src "ls180.v:9012.11-9012.29" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:9014.11-9014.15" + case + attribute \src "ls180.v:9015.8-9017.11" + switch \builder_request [0] + attribute \src "ls180.v:9015.12-9015.30" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + attribute \src "ls180.v:9024.4-9040.7" + switch $not$ls180.v:9024$2886_Y + attribute \src "ls180.v:9024.8-9024.29" + case 1'1 + attribute \src "ls180.v:9025.5-9039.8" + switch \builder_request [3] + attribute \src "ls180.v:9025.9-9025.27" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:9027.9-9027.13" + case + attribute \src "ls180.v:9028.6-9038.9" + switch \builder_request [4] + attribute \src "ls180.v:9028.10-9028.28" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:9030.10-9030.14" + case + attribute \src "ls180.v:9031.7-9037.10" + switch \builder_request [0] + attribute \src "ls180.v:9031.11-9031.29" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:9033.11-9033.15" + case + attribute \src "ls180.v:9034.8-9036.11" + switch \builder_request [1] + attribute \src "ls180.v:9034.12-9034.30" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:9043.4-9059.7" + switch $not$ls180.v:9043$2887_Y + attribute \src "ls180.v:9043.8-9043.29" + case 1'1 + attribute \src "ls180.v:9044.5-9058.8" + switch \builder_request [4] + attribute \src "ls180.v:9044.9-9044.27" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:9046.9-9046.13" + case + attribute \src "ls180.v:9047.6-9057.9" + switch \builder_request [0] + attribute \src "ls180.v:9047.10-9047.28" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:9049.10-9049.14" + case + attribute \src "ls180.v:9050.7-9056.10" + switch \builder_request [1] + attribute \src "ls180.v:9050.11-9050.29" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:9052.11-9052.15" + case + attribute \src "ls180.v:9053.8-9055.11" + switch \builder_request [2] + attribute \src "ls180.v:9053.12-9053.30" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + attribute \src "ls180.v:9062.4-9078.7" + switch $not$ls180.v:9062$2888_Y + attribute \src "ls180.v:9062.8-9062.29" + case 1'1 + attribute \src "ls180.v:9063.5-9077.8" + switch \builder_request [0] + attribute \src "ls180.v:9063.9-9063.27" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:9065.9-9065.13" + case + attribute \src "ls180.v:9066.6-9076.9" + switch \builder_request [1] + attribute \src "ls180.v:9066.10-9066.28" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:9068.10-9068.14" + case + attribute \src "ls180.v:9069.7-9075.10" + switch \builder_request [2] + attribute \src "ls180.v:9069.11-9069.29" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:9071.11-9071.15" + case + attribute \src "ls180.v:9072.8-9074.11" + switch \builder_request [3] + attribute \src "ls180.v:9072.12-9072.30" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + case + end + end + end + end + case + end + case + end + attribute \src "ls180.v:9082.2-9088.5" + switch \builder_wait + attribute \src "ls180.v:9082.6-9082.18" + case 1'1 + attribute \src "ls180.v:9083.3-9085.6" + switch $not$ls180.v:9083$2889_Y + attribute \src "ls180.v:9083.7-9083.22" + case 1'1 + assign $0\builder_count[19:0] $sub$ls180.v:9084$2890_Y + case + end + attribute \src "ls180.v:9086.6-9086.10" + case + assign $0\builder_count[19:0] 20'11110100001001000000 + end + attribute \src "ls180.v:9090.2-9120.5" + switch \builder_csrbank0_sel + attribute \src "ls180.v:9090.6-9090.26" + case 1'1 + attribute \src "ls180.v:9091.3-9119.10" + switch \builder_interface0_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w + case + end + case + end + attribute \src "ls180.v:9121.2-9123.5" + switch \builder_csrbank0_reset0_re + attribute \src "ls180.v:9121.6-9121.32" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r + case + end + attribute \src "ls180.v:9125.2-9127.5" + switch \builder_csrbank0_scratch3_re + attribute \src "ls180.v:9125.6-9125.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r + case + end + attribute \src "ls180.v:9128.2-9130.5" + switch \builder_csrbank0_scratch2_re + attribute \src "ls180.v:9128.6-9128.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r + case + end + attribute \src "ls180.v:9131.2-9133.5" + switch \builder_csrbank0_scratch1_re + attribute \src "ls180.v:9131.6-9131.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r + case + end + attribute \src "ls180.v:9134.2-9136.5" + switch \builder_csrbank0_scratch0_re + attribute \src "ls180.v:9134.6-9134.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r + case + end + attribute \src "ls180.v:9139.2-9160.5" + switch \builder_csrbank1_sel + attribute \src "ls180.v:9139.6-9139.26" + case 1'1 + attribute \src "ls180.v:9140.3-9159.10" + switch \builder_interface1_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w + case + end + case + end + attribute \src "ls180.v:9161.2-9163.5" + switch \builder_csrbank1_oe1_re + attribute \src "ls180.v:9161.6-9161.29" + case 1'1 + assign $0\main_gpiotristateasic1_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r + case + end + attribute \src "ls180.v:9164.2-9166.5" + switch \builder_csrbank1_oe0_re + attribute \src "ls180.v:9164.6-9164.29" + case 1'1 + assign $0\main_gpiotristateasic1_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r + case + end + attribute \src "ls180.v:9168.2-9170.5" + switch \builder_csrbank1_out1_re + attribute \src "ls180.v:9168.6-9168.30" + case 1'1 + assign $0\main_gpiotristateasic1_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + case + end + attribute \src "ls180.v:9171.2-9173.5" + switch \builder_csrbank1_out0_re + attribute \src "ls180.v:9171.6-9171.30" + case 1'1 + assign $0\main_gpiotristateasic1_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + case + end + attribute \src "ls180.v:9176.2-9185.5" + switch \builder_csrbank2_sel + attribute \src "ls180.v:9176.6-9176.26" + case 1'1 + attribute \src "ls180.v:9177.3-9184.10" + switch \builder_interface2_bank_bus_adr [0] + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } + case + end + case + end + attribute \src "ls180.v:9186.2-9188.5" + switch \builder_csrbank2_w0_re + attribute \src "ls180.v:9186.6-9186.28" + case 1'1 + assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r + case + end + attribute \src "ls180.v:9191.2-9221.5" + switch \builder_csrbank3_sel + attribute \src "ls180.v:9191.6-9191.26" + case 1'1 + attribute \src "ls180.v:9192.3-9220.10" + switch \builder_interface3_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w + case + end + case + end + attribute \src "ls180.v:9222.2-9224.5" + switch \builder_csrbank3_enable0_re + attribute \src "ls180.v:9222.6-9222.33" + case 1'1 + assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r + case + end + attribute \src "ls180.v:9226.2-9228.5" + switch \builder_csrbank3_width3_re + attribute \src "ls180.v:9226.6-9226.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r + case + end + attribute \src "ls180.v:9229.2-9231.5" + switch \builder_csrbank3_width2_re + attribute \src "ls180.v:9229.6-9229.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r + case + end + attribute \src "ls180.v:9232.2-9234.5" + switch \builder_csrbank3_width1_re + attribute \src "ls180.v:9232.6-9232.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r + case + end + attribute \src "ls180.v:9235.2-9237.5" + switch \builder_csrbank3_width0_re + attribute \src "ls180.v:9235.6-9235.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r + case + end + attribute \src "ls180.v:9239.2-9241.5" + switch \builder_csrbank3_period3_re + attribute \src "ls180.v:9239.6-9239.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r + case + end + attribute \src "ls180.v:9242.2-9244.5" + switch \builder_csrbank3_period2_re + attribute \src "ls180.v:9242.6-9242.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r + case + end + attribute \src "ls180.v:9245.2-9247.5" + switch \builder_csrbank3_period1_re + attribute \src "ls180.v:9245.6-9245.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r + case + end + attribute \src "ls180.v:9248.2-9250.5" + switch \builder_csrbank3_period0_re + attribute \src "ls180.v:9248.6-9248.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r + case + end + attribute \src "ls180.v:9253.2-9283.5" + switch \builder_csrbank4_sel + attribute \src "ls180.v:9253.6-9253.26" + case 1'1 + attribute \src "ls180.v:9254.3-9282.10" + switch \builder_interface4_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w + case + end + case + end + attribute \src "ls180.v:9284.2-9286.5" + switch \builder_csrbank4_enable0_re + attribute \src "ls180.v:9284.6-9284.33" + case 1'1 + assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r + case + end + attribute \src "ls180.v:9288.2-9290.5" + switch \builder_csrbank4_width3_re + attribute \src "ls180.v:9288.6-9288.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r + case + end + attribute \src "ls180.v:9291.2-9293.5" + switch \builder_csrbank4_width2_re + attribute \src "ls180.v:9291.6-9291.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r + case + end + attribute \src "ls180.v:9294.2-9296.5" + switch \builder_csrbank4_width1_re + attribute \src "ls180.v:9294.6-9294.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r + case + end + attribute \src "ls180.v:9297.2-9299.5" + switch \builder_csrbank4_width0_re + attribute \src "ls180.v:9297.6-9297.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r + case + end + attribute \src "ls180.v:9301.2-9303.5" + switch \builder_csrbank4_period3_re + attribute \src "ls180.v:9301.6-9301.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r + case + end + attribute \src "ls180.v:9304.2-9306.5" + switch \builder_csrbank4_period2_re + attribute \src "ls180.v:9304.6-9304.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r + case + end + attribute \src "ls180.v:9307.2-9309.5" + switch \builder_csrbank4_period1_re + attribute \src "ls180.v:9307.6-9307.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r + case + end + attribute \src "ls180.v:9310.2-9312.5" + switch \builder_csrbank4_period0_re + attribute \src "ls180.v:9310.6-9310.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r + case + end + attribute \src "ls180.v:9315.2-9363.5" + switch \builder_csrbank5_sel + attribute \src "ls180.v:9315.6-9315.26" + case 1'1 + attribute \src "ls180.v:9316.3-9362.10" + switch \builder_interface5_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 4'1010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } + case + end + case + end + attribute \src "ls180.v:9364.2-9366.5" + switch \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:9364.6-9364.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r + case + end + attribute \src "ls180.v:9367.2-9369.5" + switch \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:9367.6-9367.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r + case + end + attribute \src "ls180.v:9370.2-9372.5" + switch \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:9370.6-9370.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r + case + end + attribute \src "ls180.v:9373.2-9375.5" + switch \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:9373.6-9373.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r + case + end + attribute \src "ls180.v:9376.2-9378.5" + switch \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:9376.6-9376.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r + case + end + attribute \src "ls180.v:9379.2-9381.5" + switch \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:9379.6-9379.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r + case + end + attribute \src "ls180.v:9382.2-9384.5" + switch \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:9382.6-9382.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r + case + end + attribute \src "ls180.v:9385.2-9387.5" + switch \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:9385.6-9385.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r + case + end + attribute \src "ls180.v:9389.2-9391.5" + switch \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:9389.6-9389.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r + case + end + attribute \src "ls180.v:9392.2-9394.5" + switch \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:9392.6-9392.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r + case + end + attribute \src "ls180.v:9395.2-9397.5" + switch \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:9395.6-9395.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r + case + end + attribute \src "ls180.v:9398.2-9400.5" + switch \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:9398.6-9398.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r + case + end + attribute \src "ls180.v:9402.2-9404.5" + switch \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:9402.6-9402.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r + case + end + attribute \src "ls180.v:9406.2-9408.5" + switch \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:9406.6-9406.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r + case + end + attribute \src "ls180.v:9411.2-9513.5" + switch \builder_csrbank6_sel + attribute \src "ls180.v:9411.6-9411.26" + case 1'1 + attribute \src "ls180.v:9412.3-9512.10" + switch \builder_interface6_bank_bus_adr [5:0] + attribute \src "ls180.v:0.0-0.0" + case 6'000000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:0.0-0.0" + case 6'000100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:0.0-0.0" + case 6'001000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } + attribute \src "ls180.v:0.0-0.0" + case 6'001001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:0.0-0.0" + case 6'001010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:0.0-0.0" + case 6'001011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:0.0-0.0" + case 6'001100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:0.0-0.0" + case 6'001101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:0.0-0.0" + case 6'001110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:0.0-0.0" + case 6'001111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:0.0-0.0" + case 6'010000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:0.0-0.0" + case 6'010001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:0.0-0.0" + case 6'010010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:0.0-0.0" + case 6'010011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:0.0-0.0" + case 6'010100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:0.0-0.0" + case 6'010101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:0.0-0.0" + case 6'010110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:0.0-0.0" + case 6'010111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:0.0-0.0" + case 6'011000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w + attribute \src "ls180.v:0.0-0.0" + case 6'011110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w + attribute \src "ls180.v:0.0-0.0" + case 6'011111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w + attribute \src "ls180.v:0.0-0.0" + case 6'100000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w + case + end + case + end + attribute \src "ls180.v:9514.2-9516.5" + switch \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:9514.6-9514.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r + case + end + attribute \src "ls180.v:9517.2-9519.5" + switch \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:9517.6-9517.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r + case + end + attribute \src "ls180.v:9520.2-9522.5" + switch \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:9520.6-9520.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r + case + end + attribute \src "ls180.v:9523.2-9525.5" + switch \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:9523.6-9523.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r + case + end + attribute \src "ls180.v:9527.2-9529.5" + switch \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:9527.6-9527.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r + case + end + attribute \src "ls180.v:9530.2-9532.5" + switch \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:9530.6-9530.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r + case + end + attribute \src "ls180.v:9533.2-9535.5" + switch \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:9533.6-9533.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r + case + end + attribute \src "ls180.v:9536.2-9538.5" + switch \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:9536.6-9536.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r + case + end + attribute \src "ls180.v:9540.2-9542.5" + switch \builder_csrbank6_block_length1_re + attribute \src "ls180.v:9540.6-9540.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r + case + end + attribute \src "ls180.v:9543.2-9545.5" + switch \builder_csrbank6_block_length0_re + attribute \src "ls180.v:9543.6-9543.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r + case + end + attribute \src "ls180.v:9547.2-9549.5" + switch \builder_csrbank6_block_count3_re + attribute \src "ls180.v:9547.6-9547.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r + case + end + attribute \src "ls180.v:9550.2-9552.5" + switch \builder_csrbank6_block_count2_re + attribute \src "ls180.v:9550.6-9550.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r + case + end + attribute \src "ls180.v:9553.2-9555.5" + switch \builder_csrbank6_block_count1_re + attribute \src "ls180.v:9553.6-9553.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r + case + end + attribute \src "ls180.v:9556.2-9558.5" + switch \builder_csrbank6_block_count0_re + attribute \src "ls180.v:9556.6-9556.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r + case + end + attribute \src "ls180.v:9561.2-9621.5" + switch \builder_csrbank7_sel + attribute \src "ls180.v:9561.6-9561.26" + case 1'1 + attribute \src "ls180.v:9562.3-9620.10" + switch \builder_interface7_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:0.0-0.0" + case 5'10001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:0.0-0.0" + case 5'10010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w + case + end + case + end + attribute \src "ls180.v:9622.2-9624.5" + switch \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:9622.6-9622.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r + case + end + attribute \src "ls180.v:9625.2-9627.5" + switch \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:9625.6-9625.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r + case + end + attribute \src "ls180.v:9628.2-9630.5" + switch \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:9628.6-9628.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r + case + end + attribute \src "ls180.v:9631.2-9633.5" + switch \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:9631.6-9631.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r + case + end + attribute \src "ls180.v:9634.2-9636.5" + switch \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:9634.6-9634.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r + case + end + attribute \src "ls180.v:9637.2-9639.5" + switch \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:9637.6-9637.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r + case + end + attribute \src "ls180.v:9640.2-9642.5" + switch \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:9640.6-9640.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r + case + end + attribute \src "ls180.v:9643.2-9645.5" + switch \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:9643.6-9643.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r + case + end + attribute \src "ls180.v:9647.2-9649.5" + switch \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:9647.6-9647.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r + case + end + attribute \src "ls180.v:9650.2-9652.5" + switch \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:9650.6-9650.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r + case + end + attribute \src "ls180.v:9653.2-9655.5" + switch \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:9653.6-9653.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r + case + end + attribute \src "ls180.v:9656.2-9658.5" + switch \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:9656.6-9656.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r + case + end + attribute \src "ls180.v:9660.2-9662.5" + switch \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:9660.6-9660.37" + case 1'1 + assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r + case + end + attribute \src "ls180.v:9664.2-9666.5" + switch \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:9664.6-9664.35" + case 1'1 + assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r + case + end + attribute \src "ls180.v:9669.2-9684.5" + switch \builder_csrbank8_sel + attribute \src "ls180.v:9669.6-9669.26" + case 1'1 + attribute \src "ls180.v:9670.3-9683.10" + switch \builder_interface8_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + case + end + case + end + attribute \src "ls180.v:9685.2-9687.5" + switch \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:9685.6-9685.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r + case + end + attribute \src "ls180.v:9688.2-9690.5" + switch \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:9688.6-9688.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r + case + end + attribute \src "ls180.v:9693.2-9726.5" + switch \builder_csrbank9_sel + attribute \src "ls180.v:9693.6-9693.26" + case 1'1 + attribute \src "ls180.v:9694.3-9725.10" + switch \builder_interface9_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w + case + end + case + end + attribute \src "ls180.v:9727.2-9729.5" + switch \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:9727.6-9727.39" + case 1'1 + assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r + case + end + attribute \src "ls180.v:9731.2-9733.5" + switch \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:9731.6-9731.43" + case 1'1 + assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r + case + end + attribute \src "ls180.v:9735.2-9737.5" + switch \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:9735.6-9735.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r + case + end + attribute \src "ls180.v:9738.2-9740.5" + switch \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:9738.6-9738.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r + case + end + attribute \src "ls180.v:9742.2-9744.5" + switch \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:9742.6-9742.44" + case 1'1 + assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r + case + end + attribute \src "ls180.v:9746.2-9748.5" + switch \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:9746.6-9746.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r + case + end + attribute \src "ls180.v:9749.2-9751.5" + switch \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:9749.6-9749.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r + case + end + attribute \src "ls180.v:9754.2-9778.5" + switch \builder_csrbank10_sel + attribute \src "ls180.v:9754.6-9754.27" + case 1'1 + attribute \src "ls180.v:9755.3-9777.10" + switch \builder_interface10_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + case + end + case + end + attribute \src "ls180.v:9779.2-9781.5" + switch \builder_csrbank10_control1_re + attribute \src "ls180.v:9779.6-9779.35" + case 1'1 + assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r + case + end + attribute \src "ls180.v:9782.2-9784.5" + switch \builder_csrbank10_control0_re + attribute \src "ls180.v:9782.6-9782.35" + case 1'1 + assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r + case + end + attribute \src "ls180.v:9786.2-9788.5" + switch \builder_csrbank10_mosi0_re + attribute \src "ls180.v:9786.6-9786.32" + case 1'1 + assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r + case + end + attribute \src "ls180.v:9790.2-9792.5" + switch \builder_csrbank10_cs0_re + attribute \src "ls180.v:9790.6-9790.30" + case 1'1 + assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r + case + end + attribute \src "ls180.v:9794.2-9796.5" + switch \builder_csrbank10_loopback0_re + attribute \src "ls180.v:9794.6-9794.36" + case 1'1 + assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r + case + end + attribute \src "ls180.v:9799.2-9829.5" + switch \builder_csrbank11_sel + attribute \src "ls180.v:9799.6-9799.27" + case 1'1 + attribute \src "ls180.v:9800.3-9828.10" + switch \builder_interface11_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w + case + end + case + end + attribute \src "ls180.v:9830.2-9832.5" + switch \builder_csrbank11_control1_re + attribute \src "ls180.v:9830.6-9830.35" + case 1'1 + assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r + case + end + attribute \src "ls180.v:9833.2-9835.5" + switch \builder_csrbank11_control0_re + attribute \src "ls180.v:9833.6-9833.35" + case 1'1 + assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r + case + end + attribute \src "ls180.v:9837.2-9839.5" + switch \builder_csrbank11_mosi0_re + attribute \src "ls180.v:9837.6-9837.32" + case 1'1 + assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r + case + end + attribute \src "ls180.v:9841.2-9843.5" + switch \builder_csrbank11_cs0_re + attribute \src "ls180.v:9841.6-9841.30" + case 1'1 + assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r + case + end + attribute \src "ls180.v:9845.2-9847.5" + switch \builder_csrbank11_loopback0_re + attribute \src "ls180.v:9845.6-9845.36" + case 1'1 + assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r + case + end + attribute \src "ls180.v:9849.2-9851.5" + switch \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:9849.6-9849.39" + case 1'1 + assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r + case + end + attribute \src "ls180.v:9852.2-9854.5" + switch \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:9852.6-9852.39" + case 1'1 + assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r + case + end + attribute \src "ls180.v:9857.2-9911.5" + switch \builder_csrbank12_sel + attribute \src "ls180.v:9857.6-9857.27" + case 1'1 + attribute \src "ls180.v:9858.3-9910.10" + switch \builder_interface12_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } + case + end + case + end + attribute \src "ls180.v:9912.2-9914.5" + switch \builder_csrbank12_load3_re + attribute \src "ls180.v:9912.6-9912.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r + case + end + attribute \src "ls180.v:9915.2-9917.5" + switch \builder_csrbank12_load2_re + attribute \src "ls180.v:9915.6-9915.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r + case + end + attribute \src "ls180.v:9918.2-9920.5" + switch \builder_csrbank12_load1_re + attribute \src "ls180.v:9918.6-9918.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r + case + end + attribute \src "ls180.v:9921.2-9923.5" + switch \builder_csrbank12_load0_re + attribute \src "ls180.v:9921.6-9921.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r + case + end + attribute \src "ls180.v:9925.2-9927.5" + switch \builder_csrbank12_reload3_re + attribute \src "ls180.v:9925.6-9925.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r + case + end + attribute \src "ls180.v:9928.2-9930.5" + switch \builder_csrbank12_reload2_re + attribute \src "ls180.v:9928.6-9928.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r + case + end + attribute \src "ls180.v:9931.2-9933.5" + switch \builder_csrbank12_reload1_re + attribute \src "ls180.v:9931.6-9931.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r + case + end + attribute \src "ls180.v:9934.2-9936.5" + switch \builder_csrbank12_reload0_re + attribute \src "ls180.v:9934.6-9934.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r + case + end + attribute \src "ls180.v:9938.2-9940.5" + switch \builder_csrbank12_en0_re + attribute \src "ls180.v:9938.6-9938.30" + case 1'1 + assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r + case + end + attribute \src "ls180.v:9942.2-9944.5" + switch \builder_csrbank12_update_value0_re + attribute \src "ls180.v:9942.6-9942.40" + case 1'1 + assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r + case + end + attribute \src "ls180.v:9946.2-9948.5" + switch \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:9946.6-9946.37" + case 1'1 + assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r + case + end + attribute \src "ls180.v:9951.2-9978.5" + switch \builder_csrbank13_sel + attribute \src "ls180.v:9951.6-9951.27" + case 1'1 + attribute \src "ls180.v:9952.3-9977.10" + switch \builder_interface13_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } + case + end + case + end + attribute \src "ls180.v:9979.2-9981.5" + switch \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:9979.6-9979.37" + case 1'1 + assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r + case + end + attribute \src "ls180.v:9984.2-9999.5" + switch \builder_csrbank14_sel + attribute \src "ls180.v:9984.6-9984.27" + case 1'1 + attribute \src "ls180.v:9985.3-9998.10" + switch \builder_interface14_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w + case + end + case + end + attribute \src "ls180.v:10000.2-10002.5" + switch \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:10000.6-10000.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r + case + end + attribute \src "ls180.v:10003.2-10005.5" + switch \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:10003.6-10003.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r + case + end + attribute \src "ls180.v:10006.2-10008.5" + switch \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:10006.6-10006.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r + case + end + attribute \src "ls180.v:10009.2-10011.5" + switch \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:10009.6-10009.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r + case + end + attribute \src "ls180.v:10013.2-10311.5" + switch \sys_rst_1 + attribute \src "ls180.v:10013.6-10013.15" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] 1'0 + assign $0\main_libresocsim_reset_re[0:0] 1'0 + assign $0\main_libresocsim_scratch_storage[31:0] 305419896 + assign $0\main_libresocsim_scratch_re[0:0] 1'0 + assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\uart_tx[0:0] 1'1 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\spimaster_clk[0:0] 1'0 + assign $0\spimaster_mosi[0:0] 1'0 + assign $0\spimaster_cs_n[0:0] 1'0 + assign $0\pwm[1:0] 2'00 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_load_storage[31:0] 0 + assign $0\main_libresocsim_load_re[0:0] 1'0 + assign $0\main_libresocsim_reload_storage[31:0] 0 + assign $0\main_libresocsim_reload_re[0:0] 1'0 + assign $0\main_libresocsim_en_storage[0:0] 1'0 + assign $0\main_libresocsim_en_re[0:0] 1'0 + assign $0\main_libresocsim_update_value_storage[0:0] 1'0 + assign $0\main_libresocsim_update_value_re[0:0] 1'0 + assign $0\main_libresocsim_value_status[31:0] 0 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $0\main_libresocsim_value[31:0] 0 + assign $0\main_interface0_ram_bus_ack[0:0] 1'0 + assign $0\main_interface1_ram_bus_ack[0:0] 1'0 + assign $0\main_interface2_ram_bus_ack[0:0] 1'0 + assign $0\main_interface3_ram_bus_ack[0:0] 1'0 + assign $0\main_converter0_counter[0:0] 1'0 + assign $0\main_converter1_counter[0:0] 1'0 + assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $0\main_rddata_en[2:0] 3'000 + assign $0\main_sdram_storage[3:0] 4'0001 + assign $0\main_sdram_re[0:0] 1'0 + assign $0\main_sdram_command_storage[5:0] 6'000000 + assign $0\main_sdram_command_re[0:0] 1'0 + assign $0\main_sdram_address_re[0:0] 1'0 + assign $0\main_sdram_baddress_re[0:0] 1'0 + assign $0\main_sdram_wrdata_re[0:0] 1'0 + assign $0\main_sdram_status[15:0] 16'0000000000000000 + assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\main_sdram_tccdcon_ready[0:0] 1'0 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\main_sdram_twtrcon_count[2:0] 3'000 + assign $0\main_sdram_time0[4:0] 5'00000 + assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_socbushandler_counter[0:0] 1'0 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + assign $0\main_uart_phy_storage[31:0] 9895604 + assign $0\main_uart_phy_re[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] 1'0 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_eventmanager_storage[1:0] 2'00 + assign $0\main_uart_eventmanager_re[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + assign $0\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 + assign $0\main_gpiotristateasic1_oe_re[0:0] 1'0 + assign $0\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 + assign $0\main_gpiotristateasic1_out_re[0:0] 1'0 + assign $0\main_spimaster5_miso[7:0] 8'00000000 + assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 + assign $0\main_spimaster12_re[0:0] 1'0 + assign $0\main_spimaster17_re[0:0] 1'0 + assign $0\main_spimaster21_storage[0:0] 1'1 + assign $0\main_spimaster22_re[0:0] 1'0 + assign $0\main_spimaster23_storage[0:0] 1'0 + assign $0\main_spimaster24_re[0:0] 1'0 + assign $0\main_spimaster27_count[2:0] 3'000 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\main_spimaster33_mosi_data[7:0] 8'00000000 + assign $0\main_spimaster34_mosi_sel[2:0] 3'000 + assign $0\main_spimaster35_miso_data[7:0] 8'00000000 + assign $0\main_spisdcard_miso[7:0] 8'00000000 + assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000 + assign $0\main_spisdcard_control_re[0:0] 1'0 + assign $0\main_spisdcard_mosi_re[0:0] 1'0 + assign $0\main_spisdcard_cs_storage[0:0] 1'1 + assign $0\main_spisdcard_cs_re[0:0] 1'0 + assign $0\main_spisdcard_loopback_storage[0:0] 1'0 + assign $0\main_spisdcard_loopback_re[0:0] 1'0 + assign $0\main_spisdcard_count[2:0] 3'000 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\main_spisdcard_mosi_data[7:0] 8'00000000 + assign $0\main_spisdcard_mosi_sel[2:0] 3'000 + assign $0\main_spisdcard_miso_data[7:0] 8'00000000 + assign $0\main_spimaster1_storage[15:0] 16'0000000001111101 + assign $0\main_spimaster1_re[0:0] 1'0 + assign $0\main_dummy[23:0] 24'000000000000000000000000 + assign $0\main_pwm0_enable_storage[0:0] 1'0 + assign $0\main_pwm0_enable_re[0:0] 1'0 + assign $0\main_pwm0_width_re[0:0] 1'0 + assign $0\main_pwm0_period_re[0:0] 1'0 + assign $0\main_pwm1_enable_storage[0:0] 1'0 + assign $0\main_pwm1_enable_re[0:0] 1'0 + assign $0\main_pwm1_width_re[0:0] 1'0 + assign $0\main_pwm1_period_re[0:0] 1'0 + assign $0\main_i2c_storage[2:0] 3'000 + assign $0\main_i2c_re[0:0] 1'0 + assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 + assign $0\main_sdphy_clocker_re[0:0] 1'0 + assign $0\main_sdphy_clocker_clk0[0:0] 1'0 + assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 + assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 + assign $0\main_sdphy_init_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_timeout[31:0] 500000 + assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + assign $0\main_sdphy_dataw_count[7:0] 8'00000000 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 + assign $0\main_sdphy_datar_timeout[31:0] 500000 + assign $0\main_sdphy_datar_count[9:0] 10'0000000000 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 + assign $0\main_sdcore_cmd_argument_storage[31:0] 0 + assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 + assign $0\main_sdcore_cmd_command_storage[31:0] 0 + assign $0\main_sdcore_cmd_command_re[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 + assign $0\main_sdcore_block_length_re[0:0] 1'0 + assign $0\main_sdcore_block_count_storage[31:0] 0 + assign $0\main_sdcore_block_count_re[0:0] 1'0 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + assign $0\main_sdcore_cmd_count[2:0] 3'000 + assign $0\main_sdcore_cmd_done[0:0] 1'0 + assign $0\main_sdcore_cmd_error[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout[0:0] 1'0 + assign $0\main_sdcore_data_count[31:0] 0 + assign $0\main_sdcore_data_done[0:0] 1'0 + assign $0\main_sdcore_data_error[0:0] 1'0 + assign $0\main_sdcore_data_timeout[0:0] 1'0 + assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 + assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 + assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_length_storage[31:0] 0 + assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 + assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 + assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 + assign $0\builder_converter0_state[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + assign $0\builder_refresher_state[1:0] 2'00 + assign $0\builder_bankmachine0_state[2:0] 3'000 + assign $0\builder_bankmachine1_state[2:0] 3'000 + assign $0\builder_bankmachine2_state[2:0] 3'000 + assign $0\builder_bankmachine3_state[2:0] 3'000 + assign $0\builder_multiplexer_state[2:0] 3'000 + assign $0\builder_new_master_wdata_ready[0:0] 1'0 + assign $0\builder_new_master_rdata_valid0[0:0] 1'0 + assign $0\builder_new_master_rdata_valid1[0:0] 1'0 + assign $0\builder_new_master_rdata_valid2[0:0] 1'0 + assign $0\builder_new_master_rdata_valid3[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + assign $0\builder_spimaster0_state[1:0] 2'00 + assign $0\builder_spimaster1_state[1:0] 2'00 + assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 + assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 + assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 + assign $0\builder_sdphy_fsm_state[2:0] 3'000 + assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + assign $0\builder_sdcore_fsm_state[2:0] 3'000 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + assign $0\builder_libresocsim_we[0:0] 1'0 + assign $0\builder_grant[2:0] 3'000 + assign $0\builder_slave_sel_r[12:0] 13'0000000000000 + assign $0\builder_count[19:0] 20'11110100001001000000 + assign $0\builder_state[1:0] 2'00 + case + end + sync posedge \sys_clk_1 + update \uart_tx $0\uart_tx[0:0] + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \spimaster_clk $0\spimaster_clk[0:0] + update \spimaster_mosi $0\spimaster_mosi[0:0] + update \spimaster_cs_n $0\spimaster_cs_n[0:0] + update \pwm $0\pwm[1:0] + update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] + update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] + update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] + update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] + update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] + update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] + update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] + update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] + update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] + update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] + update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] + update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] + update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] + update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] + update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] + update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] + update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] + update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] + update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] + update \main_libresocsim_value $0\main_libresocsim_value[31:0] + update \main_interface0_ram_bus_ack $0\main_interface0_ram_bus_ack[0:0] + update \main_interface1_ram_bus_ack $0\main_interface1_ram_bus_ack[0:0] + update \main_interface2_ram_bus_ack $0\main_interface2_ram_bus_ack[0:0] + update \main_interface3_ram_bus_ack $0\main_interface3_ram_bus_ack[0:0] + update \main_converter0_counter $0\main_converter0_counter[0:0] + update \main_converter0_dat_r $0\main_converter0_dat_r[63:0] + update \main_converter1_counter $0\main_converter1_counter[0:0] + update \main_converter1_dat_r $0\main_converter1_dat_r[63:0] + update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] + update \main_rddata_en $0\main_rddata_en[2:0] + update \main_sdram_storage $0\main_sdram_storage[3:0] + update \main_sdram_re $0\main_sdram_re[0:0] + update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] + update \main_sdram_command_re $0\main_sdram_command_re[0:0] + update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] + update \main_sdram_address_re $0\main_sdram_address_re[0:0] + update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] + update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] + update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] + update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] + update \main_sdram_status $0\main_sdram_status[15:0] + update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] + update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] + update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] + update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] + update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] + update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] + update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] + update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] + update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] + update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] + update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] + update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] + update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] + update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] + update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] + update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] + update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] + update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] + update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] + update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] + update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] + update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] + update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] + update \main_sdram_time0 $0\main_sdram_time0[4:0] + update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_socbushandler_counter $0\main_socbushandler_counter[0:0] + update \main_socbushandler_dat_r $0\main_socbushandler_dat_r[63:0] + update \main_converter_counter $0\main_converter_counter[0:0] + update \main_converter_dat_r $0\main_converter_dat_r[31:0] + update \main_cmd_consumed $0\main_cmd_consumed[0:0] + update \main_wdata_consumed $0\main_wdata_consumed[0:0] + update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] + update \main_uart_phy_re $0\main_uart_phy_re[0:0] + update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] + update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] + update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] + update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] + update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] + update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] + update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] + update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] + update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] + update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] + update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] + update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] + update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] + update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] + update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] + update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] + update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] + update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] + update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] + update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] + update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] + update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] + update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] + update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] + update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] + update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] + update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] + update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] + update \main_gpiotristateasic1_oe_storage $0\main_gpiotristateasic1_oe_storage[15:0] + update \main_gpiotristateasic1_oe_re $0\main_gpiotristateasic1_oe_re[0:0] + update \main_gpiotristateasic1_out_storage $0\main_gpiotristateasic1_out_storage[15:0] + update \main_gpiotristateasic1_out_re $0\main_gpiotristateasic1_out_re[0:0] + update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] + update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] + update \main_spimaster12_re $0\main_spimaster12_re[0:0] + update \main_spimaster16_storage $0\main_spimaster16_storage[7:0] + update \main_spimaster17_re $0\main_spimaster17_re[0:0] + update \main_spimaster21_storage $0\main_spimaster21_storage[0:0] + update \main_spimaster22_re $0\main_spimaster22_re[0:0] + update \main_spimaster23_storage $0\main_spimaster23_storage[0:0] + update \main_spimaster24_re $0\main_spimaster24_re[0:0] + update \main_spimaster27_count $0\main_spimaster27_count[2:0] + update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0] + update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0] + update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0] + update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0] + update \main_spisdcard_miso $0\main_spisdcard_miso[7:0] + update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0] + update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0] + update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0] + update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0] + update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0] + update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0] + update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0] + update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0] + update \main_spisdcard_count $0\main_spisdcard_count[2:0] + update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0] + update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0] + update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0] + update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0] + update \main_spimaster1_storage $0\main_spimaster1_storage[15:0] + update \main_spimaster1_re $0\main_spimaster1_re[0:0] + update \main_dummy $0\main_dummy[23:0] + update \main_pwm0_counter $0\main_pwm0_counter[31:0] + update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] + update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] + update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] + update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] + update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] + update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] + update \main_pwm1_counter $0\main_pwm1_counter[31:0] + update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] + update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] + update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] + update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] + update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] + update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] + update \main_i2c_storage $0\main_i2c_storage[2:0] + update \main_i2c_re $0\main_i2c_re[0:0] + update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] + update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] + update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] + update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] + update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] + update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] + update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] + update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] + update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] + update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] + update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] + update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] + update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] + update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] + update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] + update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] + update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] + update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] + update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] + update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] + update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] + update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] + update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] + update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] + update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] + update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] + update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] + update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] + update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] + update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] + update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] + update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] + update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] + update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] + update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] + update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] + update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] + update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] + update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] + update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] + update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] + update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] + update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] + update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] + update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] + update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] + update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] + update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] + update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] + update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] + update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] + update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] + update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] + update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] + update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] + update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] + update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[63:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[2:0] + update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] + update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[63:0] + update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] + update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] + update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] + update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] + update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] + update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] + update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] + update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] + update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[2:0] + update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] + update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] + update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] + update \builder_converter0_state $0\builder_converter0_state[0:0] + update \builder_converter1_state $0\builder_converter1_state[0:0] + update \builder_converter2_state $0\builder_converter2_state[0:0] + update \builder_refresher_state $0\builder_refresher_state[1:0] + update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] + update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] + update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] + update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] + update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] + update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] + update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] + update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] + update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] + update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] + update \builder_converter_state $0\builder_converter_state[0:0] + update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] + update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] + update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] + update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] + update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] + update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] + update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] + update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] + update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] + update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] + update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] + update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] + update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] + update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] + update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] + update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] + update \builder_grant $0\builder_grant[2:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[12:0] + update \builder_count $0\builder_count[19:0] + update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] + update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] + update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] + update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] + update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] + update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] + update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] + update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] + update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] + update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] + update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] + update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] + update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] + update \builder_state $0\builder_state[1:0] + update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] + update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] + update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] + update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] + update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] + update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] + update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] + update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] + update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] + update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] + update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] + update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] + update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] + update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] + update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] + update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] + update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] + update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] + update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] + update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] + update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] + update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] + update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] + update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] + update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] + update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] + update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] + update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] + update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] + update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] + update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] + update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] + update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] + update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $extend$libresoc.v:153284$7540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A \clz_lz - connect \Y $extend$libresoc.v:153284$7540_Y + attribute \src "ls180.v:781.11-781.68" + process $proc$ls180.v:781$3374 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:153286$7543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A \$166 - connect \Y $extend$libresoc.v:153286$7543_Y + attribute \src "ls180.v:782.5-782.64" + process $proc$ls180.v:782$3375 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:153287$7545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 64 - connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:153287$7545_Y + attribute \src "ls180.v:783.11-783.70" + process $proc$ls180.v:783$3376 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:153291$7550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \$176 - connect \Y $extend$libresoc.v:153291$7550_Y + attribute \src "ls180.v:784.11-784.70" + process $proc$ls180.v:784$3377 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:153294$7554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $or$libresoc.v:153294$7554_Y + attribute \src "ls180.v:785.11-785.73" + process $proc$ls180.v:785$3378 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:153282$7538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:153282$7537_Y - connect \Y $pos$libresoc.v:153282$7538_Y + attribute \src "ls180.v:806.5-806.59" + process $proc$ls180.v:806$3379 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $pos$libresoc.v:153284$7541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:153284$7540_Y - connect \Y $pos$libresoc.v:153284$7541_Y + attribute \src "ls180.v:808.5-808.59" + process $proc$ls180.v:808$3380 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:153286$7544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:153286$7543_Y - connect \Y $pos$libresoc.v:153286$7544_Y + attribute \src "ls180.v:809.5-809.58" + process $proc$ls180.v:809$3381 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:153287$7546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:153287$7545_Y - connect \Y $pos$libresoc.v:153287$7546_Y + attribute \src "ls180.v:810.5-810.64" + process $proc$ls180.v:810$3382 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:153291$7551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:153291$7550_Y - connect \Y $pos$libresoc.v:153291$7551_Y + attribute \src "ls180.v:811.12-811.74" + process $proc$ls180.v:811$3383 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:153288$7547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:153288$7547_Y + attribute \src "ls180.v:812.12-812.47" + process $proc$ls180.v:812$3384 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:153289$7548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:153289$7548_Y + attribute \src "ls180.v:813.5-813.46" + process $proc$ls180.v:813$3385 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:153283$7539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 8 - connect \A \clz_lz - connect \B 6'100000 - connect \Y $sub$libresoc.v:153283$7539_Y + attribute \src "ls180.v:815.5-815.44" + process $proc$ls180.v:815$3386 + assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:153285$7542 - parameter \WIDTH 8 - connect \A \$164 - connect \B \$162 - connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:153285$7542_Y + attribute \src "ls180.v:816.5-816.45" + process $proc$ls180.v:816$3387 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:153290$7549 - parameter \WIDTH 32 - connect \A \a32 - connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } - connect \S \count_right - connect \Y $ternary$libresoc.v:153290$7549_Y + attribute \src "ls180.v:817.5-817.54" + process $proc$ls180.v:817$3388 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:153292$7552 - parameter \WIDTH 64 - connect \A \ra - connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } - connect \S \count_right - connect \Y $ternary$libresoc.v:153292$7552_Y + attribute \src "ls180.v:819.32-819.76" + process $proc$ls180.v:819$3389 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:153281$7536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \par0 - connect \B \par1 - connect \Y $xor$libresoc.v:153281$7536_Y + attribute \src "ls180.v:820.11-820.55" + process $proc$ls180.v:820$3390 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:153295$7555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $xor$libresoc.v:153295$7555_Y + attribute \src "ls180.v:822.32-822.75" + process $proc$ls180.v:822$3391 + assign { } { } + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + sync init end - attribute \module_not_derived 1 - attribute \src "libresoc.v:153332.10-153336.4" - cell \bpermd \bpermd - connect \ra \bpermd_ra - connect \rb \bpermd_rb - connect \rs \bpermd_rs + attribute \src "ls180.v:824.32-824.76" + process $proc$ls180.v:824$3392 + assign { } { } + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] + sync init end - attribute \module_not_derived 1 - attribute \src "libresoc.v:153337.7-153340.4" - cell \clz \clz - connect \lz \clz_lz - connect \sig_in \clz_sig_in + attribute \src "ls180.v:827.5-827.44" + process $proc$ls180.v:827$3393 + assign { } { } + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + sync init end - attribute \module_not_derived 1 - attribute \src "libresoc.v:153341.12-153345.4" - cell \popcount \popcount - connect \a \popcount_a - connect \data_len \popcount_data_len - connect \o \popcount_o + attribute \src "ls180.v:828.5-828.45" + process $proc$ls180.v:828$3394 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init end - attribute \src "libresoc.v:152789.7-152789.20" - process $proc$libresoc.v:152789$7604 + attribute \src "ls180.v:829.5-829.43" + process $proc$ls180.v:829$3395 assign { } { } - assign $0\initial[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 sync always - update \initial $0\initial[0:0] + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] sync init end - attribute \src "libresoc.v:153346.3-153400.6" - process $proc$libresoc.v:153346$7592 + attribute \src "ls180.v:830.5-830.48" + process $proc$ls180.v:830$3396 assign { } { } + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + sync init + end + attribute \src "ls180.v:832.5-832.43" + process $proc$ls180.v:832$3397 assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "ls180.v:835.5-835.49" + process $proc$ls180.v:835$3398 assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:836.5-836.49" + process $proc$ls180.v:836$3399 assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:153347.5-153347.29" - switch \initial - attribute \src "libresoc.v:153347.9-153347.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000100 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$21 - attribute \src "libresoc.v:0.0-0.0" - case 7'0110101 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$23 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000011 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$25 - attribute \src "libresoc.v:0.0-0.0" - case 7'0001011 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] { \$139 \$141 \$143 \$145 \$147 \$149 \$151 \$153 \$123 \$125 \$127 \$129 \$131 \$133 \$135 \$137 \$107 \$109 \$111 \$113 \$115 \$117 \$119 \$121 \$91 \$93 \$95 \$97 \$99 \$101 \$103 \$105 \$75 \$77 \$79 \$81 \$83 \$85 \$87 \$89 \$59 \$61 \$63 \$65 \$67 \$69 \$71 \$73 \$43 \$45 \$47 \$49 \$51 \$53 \$55 \$57 \$27 \$29 \$31 \$33 \$35 \$37 \$39 \$41 } - attribute \src "libresoc.v:0.0-0.0" - case 7'0110110 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \popcount_o - attribute \src "libresoc.v:0.0-0.0" - case 7'0110111 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] $2\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - switch \$155 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o[63:0] \$157 - attribute \src "libresoc.v:0.0-0.0" - case - assign { $2\o[63:0] [63:33] $2\o[63:0] [31:1] } 62'00000000000000000000000000000000000000000000000000000000000000 - assign $2\o[63:0] [0] \par0 - assign $2\o[63:0] [32] \par1 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0001110 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$161 - attribute \src "libresoc.v:0.0-0.0" - case 7'0001001 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \bpermd_ra - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\o_ok[0:0] 1'0 - end + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 sync always - update \o_ok $0\o_ok[0:0] - update \o $0\o[63:0] + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "libresoc.v:153401.3-153411.6" - process $proc$libresoc.v:153401$7593 + attribute \src "ls180.v:837.5-837.48" + process $proc$ls180.v:837$3400 assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:841.11-841.46" + process $proc$ls180.v:841$3401 assign { } { } - assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:153402.5-153402.29" - switch \initial - attribute \src "libresoc.v:153402.9-153402.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001110 - assign { } { } - assign $1\clz_sig_in[63:0] \cntz_i - case - assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 sync always - update \clz_sig_in $0\clz_sig_in[63:0] + sync init + update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end - attribute \src "libresoc.v:153412.3-153422.6" - process $proc$libresoc.v:153412$7594 + attribute \src "ls180.v:843.11-843.45" + process $proc$ls180.v:843$3402 assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + end + attribute \src "ls180.v:845.5-845.44" + process $proc$ls180.v:845$3403 assign { } { } - assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:153413.5-153413.29" - switch \initial - attribute \src "libresoc.v:153413.9-153413.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001001 - assign { } { } - assign $1\bpermd_rs[63:0] \ra - case - assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 sync always - update \bpermd_rs $0\bpermd_rs[63:0] + sync init + update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end - attribute \src "libresoc.v:153423.3-153433.6" - process $proc$libresoc.v:153423$7595 + attribute \src "ls180.v:846.5-846.45" + process $proc$ls180.v:846$3404 assign { } { } + assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] + end + attribute \src "ls180.v:848.5-848.48" + process $proc$ls180.v:848$3405 assign { } { } - assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:153424.5-153424.29" - switch \initial - attribute \src "libresoc.v:153424.9-153424.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001001 - assign { } { } - assign $1\bpermd_rb[63:0] \rb - case - assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 sync always - update \bpermd_rb $0\bpermd_rb[63:0] + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end - attribute \src "libresoc.v:153434.3-153444.6" - process $proc$libresoc.v:153434$7596 + attribute \src "ls180.v:85.11-85.52" + process $proc$ls180.v:85$3134 assign { } { } + assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] + sync init + end + attribute \src "ls180.v:850.5-850.43" + process $proc$ls180.v:850$3406 assign { } { } - assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:153435.5-153435.29" - switch \initial - attribute \src "libresoc.v:153435.9-153435.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110110 - assign { } { } - assign $1\popcount_a[63:0] \ra - case - assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 sync always - update \popcount_a $0\popcount_a[63:0] + sync init + update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end - attribute \src "libresoc.v:153445.3-153455.6" - process $proc$libresoc.v:153445$7597 + attribute \src "ls180.v:853.5-853.49" + process $proc$ls180.v:853$3407 assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:854.5-854.49" + process $proc$ls180.v:854$3408 assign { } { } - assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:153446.5-153446.29" - switch \initial - attribute \src "libresoc.v:153446.9-153446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110110 - assign { } { } - assign $1\b[63:0] \rb - case - assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always - update \b $0\b[63:0] + sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "libresoc.v:153456.3-153466.6" - process $proc$libresoc.v:153456$7598 + attribute \src "ls180.v:855.5-855.48" + process $proc$ls180.v:855$3409 assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:859.11-859.46" + process $proc$ls180.v:859$3410 assign { } { } - assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "libresoc.v:153457.5-153457.29" - switch \initial - attribute \src "libresoc.v:153457.9-153457.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110110 - assign { } { } - assign $1\popcount_data_len[63:0] \$169 - case - assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always - update \popcount_data_len $0\popcount_data_len[63:0] + sync init + update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end - attribute \src "libresoc.v:153467.3-153477.6" - process $proc$libresoc.v:153467$7599 + attribute \src "ls180.v:86.11-86.52" + process $proc$ls180.v:86$3135 assign { } { } + assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] + sync init + end + attribute \src "ls180.v:861.11-861.45" + process $proc$ls180.v:861$3411 assign { } { } - assign $0\par0[0:0] $1\par0[0:0] - attribute \src "libresoc.v:153468.5-153468.29" - switch \initial - attribute \src "libresoc.v:153468.9-153468.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110111 - assign { } { } - assign $1\par0[0:0] \$171 - case - assign $1\par0[0:0] 1'0 - end + assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always - update \par0 $0\par0[0:0] + sync init + update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end - attribute \src "libresoc.v:153478.3-153488.6" - process $proc$libresoc.v:153478$7600 + attribute \src "ls180.v:863.12-863.36" + process $proc$ls180.v:863$3412 assign { } { } + assign $0\main_sdram_nop_a[12:0] 13'0000000000000 + sync always + update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] + sync init + end + attribute \src "ls180.v:864.11-864.35" + process $proc$ls180.v:864$3413 assign { } { } - assign $0\par1[0:0] $1\par1[0:0] - attribute \src "libresoc.v:153479.5-153479.29" - switch \initial - attribute \src "libresoc.v:153479.9-153479.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110111 - assign { } { } - assign $1\par1[0:0] \$173 - case - assign $1\par1[0:0] 1'0 - end + assign $0\main_sdram_nop_ba[1:0] 2'00 sync always - update \par1 $0\par1[0:0] + update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] + sync init end - attribute \src "libresoc.v:153489.3-153499.6" - process $proc$libresoc.v:153489$7601 + attribute \src "ls180.v:865.11-865.40" + process $proc$ls180.v:865$3414 assign { } { } + assign $1\main_sdram_steerer_sel[1:0] 2'00 + sync always + sync init + update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] + end + attribute \src "ls180.v:866.5-866.31" + process $proc$ls180.v:866$3415 assign { } { } - assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "libresoc.v:153490.5-153490.29" - switch \initial - attribute \src "libresoc.v:153490.9-153490.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001110 - assign { } { } - assign $1\count_right[0:0] \logical_op__insn [10] - case - assign $1\count_right[0:0] 1'0 - end + assign $0\main_sdram_steerer0[0:0] 1'1 sync always - update \count_right $0\count_right[0:0] + update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] + sync init end - attribute \src "libresoc.v:153500.3-153510.6" - process $proc$libresoc.v:153500$7602 + attribute \src "ls180.v:867.5-867.31" + process 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\enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \cr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 11 \cr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 6 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 32 output 16 \full_cr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 17 \full_cr_ok - attribute \src "libresoc.v:153538.7-153538.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" - wire width 4 \lut - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 20 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 10 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 14 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 15 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 4 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 5 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:153811$7611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \full_cr - connect \Y $extend$libresoc.v:153811$7611_Y + attribute \src "ls180.v:874.5-874.36" + process $proc$ls180.v:874$3420 + assign { } { } + assign $1\main_sdram_tccdcon_count[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:153813$7614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \$27 - connect \Y $extend$libresoc.v:153813$7614_Y + attribute \src "ls180.v:876.32-876.63" + process $proc$ls180.v:876$3421 + assign { } { } + assign $1\main_sdram_twtrcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:153814$7616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A \cr_a - connect \Y $extend$libresoc.v:153814$7616_Y + attribute \src "ls180.v:877.11-877.42" + process $proc$ls180.v:877$3422 + assign { } { } + assign $1\main_sdram_twtrcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:153811$7612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:153811$7611_Y - connect \Y $pos$libresoc.v:153811$7612_Y + attribute \src "ls180.v:88.12-88.58" + process $proc$ls180.v:88$3136 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:153813$7615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:153813$7614_Y - connect \Y $pos$libresoc.v:153813$7615_Y + attribute \src "ls180.v:880.5-880.26" + process $proc$ls180.v:880$3423 + assign { } { } + assign $1\main_sdram_en0[0:0] 1'0 + sync always + sync init + update \main_sdram_en0 $1\main_sdram_en0[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:153814$7617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:153814$7616_Y - connect \Y $pos$libresoc.v:153814$7617_Y + attribute \src "ls180.v:882.11-882.34" + process $proc$ls180.v:882$3424 + assign { } { } + assign $1\main_sdram_time0[4:0] 5'00000 + sync always + sync init + update \main_sdram_time0 $1\main_sdram_time0[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:153805$7605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:153805$7605_Y + attribute \src "ls180.v:883.5-883.26" + process $proc$ls180.v:883$3425 + assign { } { } + assign $1\main_sdram_en1[0:0] 1'0 + sync always + sync init + update \main_sdram_en1 $1\main_sdram_en1[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:153806$7606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:153806$7606_Y + attribute \src "ls180.v:885.11-885.34" + process $proc$ls180.v:885$3426 + assign { } { } + assign $1\main_sdram_time1[3:0] 4'0000 + sync always + sync init + update \main_sdram_time1 $1\main_sdram_time1[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:153807$7607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:153807$7607_Y + attribute \src "ls180.v:89.12-89.60" + process $proc$ls180.v:89$3137 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:153808$7608 - parameter \WIDTH 1 - connect \A \lut [1] - connect \B \lut [3] - connect \S \bit_a - connect \Y $ternary$libresoc.v:153808$7608_Y + attribute \src "ls180.v:900.12-900.37" + process $proc$ls180.v:900$3427 + assign { } { } + assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:153809$7609 - parameter \WIDTH 1 - connect \A \lut [0] - connect \B \lut [2] - connect \S \bit_a - connect \Y $ternary$libresoc.v:153809$7609_Y + attribute \src "ls180.v:901.12-901.39" + process $proc$ls180.v:901$3428 + assign { } { } + assign $1\main_wb_sdram_dat_w[31:0] 0 + sync always + sync init + update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:153810$7610 - parameter \WIDTH 1 - connect \A \$20 - connect \B \$18 - connect \S \bit_b - connect \Y $ternary$libresoc.v:153810$7610_Y + attribute \src "ls180.v:903.11-903.35" + process $proc$ls180.v:903$3429 + assign { } { } + assign $1\main_wb_sdram_sel[3:0] 4'0000 + sync always + sync init + update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:153812$7613 - parameter \WIDTH 64 - connect \A \rb - connect \B \ra - connect \S \cr_bit - connect \Y $ternary$libresoc.v:153812$7613_Y + attribute \src "ls180.v:904.5-904.29" + process $proc$ls180.v:904$3430 + assign { } { } + assign $1\main_wb_sdram_cyc[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] end - attribute \src "libresoc.v:153538.7-153538.20" - process $proc$libresoc.v:153538$7636 + attribute \src "ls180.v:905.5-905.29" + process $proc$ls180.v:905$3431 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\main_wb_sdram_stb[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] end - attribute \src "libresoc.v:153815.3-153849.6" - process $proc$libresoc.v:153815$7618 + attribute \src "ls180.v:906.5-906.29" + process $proc$ls180.v:906$3432 assign { } { } + assign $1\main_wb_sdram_ack[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] + end + attribute \src "ls180.v:907.5-907.28" + process $proc$ls180.v:907$3433 assign { } { } + assign $1\main_wb_sdram_we[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] + end + attribute \src "ls180.v:91.11-91.56" + process $proc$ls180.v:91$3138 assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + end + attribute \src "ls180.v:914.5-914.54" + process $proc$ls180.v:914$3434 assign { } { } - assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - assign $0\cr_a$6[3:0]$7619 $1\cr_a$6[3:0]$7620 - attribute \src "libresoc.v:153816.5-153816.29" - switch \initial - attribute \src "libresoc.v:153816.9-153816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0101010 - assign { } { } - assign { } { } - assign $1\cr_a$6[3:0]$7620 \$7 [3:0] - assign $1\cr_a_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign { } { } - assign { } { } - assign $1\cr_a$6[3:0]$7620 $2\cr_a$6[3:0]$7621 - assign $1\cr_a_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" - switch \bt - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign $2\cr_a$6[3:0]$7621 [3:1] \cr_c [3:1] - assign $2\cr_a$6[3:0]$7621 [0] \bit_o - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { $2\cr_a$6[3:0]$7621 [3:2] $2\cr_a$6[3:0]$7621 [0] } { \cr_c [3:2] \cr_c [0] } - assign $2\cr_a$6[3:0]$7621 [1] \bit_o - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { $2\cr_a$6[3:0]$7621 [3] $2\cr_a$6[3:0]$7621 [1:0] } { \cr_c [3] \cr_c [1:0] } - assign $2\cr_a$6[3:0]$7621 [2] \bit_o - attribute \src "libresoc.v:0.0-0.0" - case 2'-- - assign $2\cr_a$6[3:0]$7621 [2:0] \cr_c [2:0] - assign $2\cr_a$6[3:0]$7621 [3] \bit_o - case - assign $2\cr_a$6[3:0]$7621 \cr_c - end - case - assign $1\cr_a_ok[0:0] 1'0 - assign $1\cr_a$6[3:0]$7620 4'0000 - end + assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 sync always - update \cr_a_ok $0\cr_a_ok[0:0] - update \cr_a$6 $0\cr_a$6[3:0]$7619 + sync init + update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] end - attribute \src "libresoc.v:153850.3-153860.6" - process $proc$libresoc.v:153850$7622 + attribute \src "ls180.v:918.5-918.54" + process $proc$ls180.v:918$3435 assign { } { } + assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 + sync always + update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:919.5-919.35" + process $proc$ls180.v:919$3436 assign { } { } - assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:153851.5-153851.29" - switch \initial - attribute \src "libresoc.v:153851.9-153851.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110000 - assign { } { } - assign $1\full_cr_ok[0:0] 1'1 - case - assign $1\full_cr_ok[0:0] 1'0 - end + assign $1\main_socbushandler_skip[0:0] 1'0 sync always - update \full_cr_ok $0\full_cr_ok[0:0] + sync init + update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] end - attribute \src "libresoc.v:153861.3-153902.6" - process $proc$libresoc.v:153861$7623 + attribute \src "ls180.v:92.5-92.50" + process $proc$ls180.v:92$3139 assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + end + attribute \src "ls180.v:920.5-920.38" + process $proc$ls180.v:920$3437 assign { } { } + assign $1\main_socbushandler_counter[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] + end + attribute \src "ls180.v:922.12-922.44" + process $proc$ls180.v:922$3438 assign { } { } + assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] + end + attribute \src "ls180.v:923.12-923.40" + process $proc$ls180.v:923$3439 assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:153862.5-153862.29" - switch \initial - attribute \src "libresoc.v:153862.9-153862.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0101101 - assign { } { } - assign { } { } - assign $1\o[63:0] \$24 - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0100011 - assign { } { } - assign { } { } - assign $1\o[63:0] \$26 [63:0] - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0111011 - assign { } { } - assign { } { } - assign $1\o[63:0] $2\o[63:0] - assign $1\o_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" - switch { \cr_a [2] \cr_a [3] } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\o[63:0] 64'1111111111111111111111111111111111111111111111111111111111111111 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000001 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\o_ok[0:0] 1'0 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always - update \o_ok $0\o_ok[0:0] - update \o $0\o[63:0] + sync init + update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end - attribute \src "libresoc.v:153903.3-153913.6" - process $proc$libresoc.v:153903$7624 + attribute \src "ls180.v:924.12-924.42" + process $proc$ls180.v:924$3440 assign { } { } + assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + sync always + sync init + update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:926.11-926.38" + process $proc$ls180.v:926$3441 assign { } { } - assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:153904.5-153904.29" - switch \initial - attribute \src "libresoc.v:153904.9-153904.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0100011 - assign { } { } - assign $1\BC[1:0] \cr_op__insn [7:6] - case - assign $1\BC[1:0] 2'00 - end + assign $1\main_litedram_wb_sel[1:0] 2'00 sync always - update \BC $0\BC[1:0] + sync init + update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end - attribute \src "libresoc.v:153914.3-153934.6" - process $proc$libresoc.v:153914$7625 + attribute \src "ls180.v:927.5-927.32" + process $proc$ls180.v:927$3442 assign { } { } + assign $1\main_litedram_wb_cyc[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] + end + attribute \src "ls180.v:928.5-928.32" + process $proc$ls180.v:928$3443 assign { } { } - assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:153915.5-153915.29" - switch \initial - attribute \src "libresoc.v:153915.9-153915.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0100011 - assign { } { } - assign $1\cr_bit[0:0] $2\cr_bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" - switch \BC - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $2\cr_bit[0:0] \cr_a [3] - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $2\cr_bit[0:0] \cr_a [2] - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\cr_bit[0:0] \cr_a [1] - attribute \src "libresoc.v:0.0-0.0" - case 2'-- - assign { } { } - assign $2\cr_bit[0:0] \cr_a [0] - case - assign $2\cr_bit[0:0] 1'0 - end - case - assign $1\cr_bit[0:0] 1'0 - end + assign $1\main_litedram_wb_stb[0:0] 1'0 sync always - update \cr_bit $0\cr_bit[0:0] + sync init + update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "libresoc.v:153935.3-153945.6" - process $proc$libresoc.v:153935$7626 + attribute \src "ls180.v:93.5-93.50" + process $proc$ls180.v:93$3140 assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + end + attribute \src "ls180.v:930.5-930.31" + process $proc$ls180.v:930$3444 assign { } { } - assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:153936.5-153936.29" - switch \initial - attribute \src "libresoc.v:153936.9-153936.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\lut[3:0] \cr_op__insn [9:6] - case - assign $1\lut[3:0] 4'0000 - end + assign $1\main_litedram_wb_we[0:0] 1'0 sync always - update \lut $0\lut[3:0] + sync init + update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "libresoc.v:153946.3-153956.6" - process $proc$libresoc.v:153946$7627 + attribute \src "ls180.v:931.5-931.31" + process $proc$ls180.v:931$3445 assign { } { } + assign $1\main_converter_skip[0:0] 1'0 + sync always + sync init + update \main_converter_skip $1\main_converter_skip[0:0] + end + attribute \src "ls180.v:932.5-932.34" + process $proc$ls180.v:932$3446 assign { } { } - assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:153947.5-153947.29" - switch \initial - attribute \src "libresoc.v:153947.9-153947.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bt[1:0] \$9 [1:0] - case - assign $1\bt[1:0] 2'00 - end + assign $1\main_converter_counter[0:0] 1'0 sync always - update \bt $0\bt[1:0] + sync init + update \main_converter_counter $1\main_converter_counter[0:0] end - attribute \src "libresoc.v:153957.3-153967.6" - process $proc$libresoc.v:153957$7628 + attribute \src "ls180.v:934.12-934.40" + process $proc$ls180.v:934$3447 assign { } { } + assign $1\main_converter_dat_r[31:0] 0 + sync always + sync init + update \main_converter_dat_r $1\main_converter_dat_r[31:0] + end + attribute \src "ls180.v:935.5-935.29" + process $proc$ls180.v:935$3448 assign { } { } - assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:153958.5-153958.29" - switch \initial - attribute \src "libresoc.v:153958.9-153958.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\ba[1:0] \$12 [1:0] - case - assign $1\ba[1:0] 2'00 - end + assign $1\main_cmd_consumed[0:0] 1'0 sync always - update \ba $0\ba[1:0] + sync init + update \main_cmd_consumed $1\main_cmd_consumed[0:0] end - attribute \src "libresoc.v:153968.3-153978.6" - process $proc$libresoc.v:153968$7629 + attribute \src "ls180.v:936.5-936.31" + process $proc$ls180.v:936$3449 assign { } { } + assign $1\main_wdata_consumed[0:0] 1'0 + sync always + sync init + update \main_wdata_consumed $1\main_wdata_consumed[0:0] + end + attribute \src "ls180.v:940.12-940.47" + process $proc$ls180.v:940$3450 assign { } { } - assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:153969.5-153969.29" - switch \initial - attribute \src "libresoc.v:153969.9-153969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bb[1:0] \$15 [1:0] - case - assign $1\bb[1:0] 2'00 - end + assign $1\main_uart_phy_storage[31:0] 9895604 sync always - update \bb $0\bb[1:0] + sync init + update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] end - attribute \src "libresoc.v:153979.3-153999.6" - process $proc$libresoc.v:153979$7630 + attribute \src "ls180.v:941.5-941.28" + process $proc$ls180.v:941$3451 assign { } { } + assign $1\main_uart_phy_re[0:0] 1'0 + sync always + sync init + update \main_uart_phy_re $1\main_uart_phy_re[0:0] + end + attribute \src "ls180.v:943.5-943.36" + process $proc$ls180.v:943$3452 assign { } { } - assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:153980.5-153980.29" - switch \initial - attribute \src "libresoc.v:153980.9-153980.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bit_a[0:0] $2\bit_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" - switch \ba - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $2\bit_a[0:0] \cr_a [0] - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $2\bit_a[0:0] \cr_a [1] - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\bit_a[0:0] \cr_a [2] - attribute \src "libresoc.v:0.0-0.0" - case 2'-- - assign { } { } - assign $2\bit_a[0:0] \cr_a [3] - case - assign $2\bit_a[0:0] 1'0 - end - case - assign $1\bit_a[0:0] 1'0 - end + assign $1\main_uart_phy_sink_ready[0:0] 1'0 sync always - update \bit_a $0\bit_a[0:0] + sync init + update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] end - attribute \src "libresoc.v:154000.3-154020.6" - process $proc$libresoc.v:154000$7631 + attribute \src "ls180.v:947.5-947.39" + process $proc$ls180.v:947$3453 assign { } { } + assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 + sync always + sync init + update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] + end + attribute \src "ls180.v:948.12-948.54" + process $proc$ls180.v:948$3454 assign { } { } - assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:154001.5-154001.29" - switch \initial - attribute \src "libresoc.v:154001.9-154001.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bit_b[0:0] $2\bit_b[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" - switch \bb - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $2\bit_b[0:0] \cr_b [0] - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $2\bit_b[0:0] \cr_b [1] - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\bit_b[0:0] \cr_b [2] - attribute \src "libresoc.v:0.0-0.0" - case 2'-- - assign { } { } - assign $2\bit_b[0:0] \cr_b [3] - case - assign $2\bit_b[0:0] 1'0 - end - case - assign $1\bit_b[0:0] 1'0 - end + assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 sync always - update \bit_b $0\bit_b[0:0] + sync init + update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] end - attribute \src "libresoc.v:154021.3-154031.6" - process $proc$libresoc.v:154021$7632 + attribute \src "ls180.v:949.11-949.38" + process $proc$ls180.v:949$3455 assign { } { } + assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] + end + attribute \src "ls180.v:95.5-95.49" + process $proc$ls180.v:95$3141 assign { } { } - assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:154022.5-154022.29" - switch \initial - attribute \src "libresoc.v:154022.9-154022.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bit_o[0:0] \$22 - case - assign $1\bit_o[0:0] 1'0 - end + assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 sync always - update \bit_o $0\bit_o[0:0] + sync init + update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] end - attribute \src "libresoc.v:154032.3-154042.6" - process $proc$libresoc.v:154032$7633 + attribute \src "ls180.v:950.11-950.43" + process $proc$ls180.v:950$3456 assign { } { } + assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] + end + attribute \src "ls180.v:951.5-951.33" + process $proc$ls180.v:951$3457 assign { } { } - assign $0\full_cr$5[31:0]$7634 $1\full_cr$5[31:0]$7635 - attribute \src "libresoc.v:154033.5-154033.29" - switch \initial - attribute \src "libresoc.v:154033.9-154033.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110000 - assign { } { } - assign $1\full_cr$5[31:0]$7635 \ra [31:0] - case - assign $1\full_cr$5[31:0]$7635 0 - end + assign $1\main_uart_phy_tx_busy[0:0] 1'0 sync always - update \full_cr$5 $0\full_cr$5[31:0]$7634 + sync init + update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] end - connect \$10 $sub$libresoc.v:153805$7605_Y - connect \$13 $sub$libresoc.v:153806$7606_Y - connect \$16 $sub$libresoc.v:153807$7607_Y - connect \$18 $ternary$libresoc.v:153808$7608_Y - connect \$20 $ternary$libresoc.v:153809$7609_Y - connect \$22 $ternary$libresoc.v:153810$7610_Y - connect \$24 $pos$libresoc.v:153811$7612_Y - connect \$27 $ternary$libresoc.v:153812$7613_Y - connect \$26 $pos$libresoc.v:153813$7615_Y - connect \$7 $pos$libresoc.v:153814$7617_Y - connect \$9 \$10 - connect \$12 \$13 - connect \$15 \$16 - connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - connect \muxid$1 \muxid + attribute \src "ls180.v:952.5-952.38" + process $proc$ls180.v:952$3458 + assign { } { } + assign $1\main_uart_phy_source_valid[0:0] 1'0 + sync always + sync init + update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] + end + attribute \src "ls180.v:954.5-954.38" + process $proc$ls180.v:954$3459 + assign { } { } + assign $0\main_uart_phy_source_first[0:0] 1'0 + sync always + update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] + sync init + end + attribute \src "ls180.v:955.5-955.37" + process $proc$ls180.v:955$3460 + assign { } { } + assign $0\main_uart_phy_source_last[0:0] 1'0 + sync always + update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] + sync init + end + attribute \src "ls180.v:956.11-956.51" + process $proc$ls180.v:956$3461 + assign { } { } + assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] + end + attribute \src "ls180.v:957.5-957.39" + process $proc$ls180.v:957$3462 + assign { } { } + assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 + sync always + sync init + update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] + end + attribute \src "ls180.v:958.12-958.54" + process $proc$ls180.v:958$3463 + assign { } { } + assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 + sync always + sync init + update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] + end + attribute \src "ls180.v:960.5-960.30" + process $proc$ls180.v:960$3464 + assign { } { } + assign $1\main_uart_phy_rx_r[0:0] 1'0 + sync always + sync init + update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] + end + attribute \src "ls180.v:961.11-961.38" + process $proc$ls180.v:961$3465 + assign { } { } + assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] + end + attribute \src "ls180.v:962.11-962.43" + process $proc$ls180.v:962$3466 + assign { } { } + assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] + end + attribute \src "ls180.v:963.5-963.33" + process $proc$ls180.v:963$3467 + assign { } { } + assign $1\main_uart_phy_rx_busy[0:0] 1'0 + sync always + sync init + update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] + end + attribute \src "ls180.v:97.12-97.58" + process $proc$ls180.v:97$3142 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + end + attribute \src "ls180.v:974.5-974.32" + process $proc$ls180.v:974$3468 + assign { } { } + assign $1\main_uart_tx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] + end + attribute \src "ls180.v:976.5-976.30" + process $proc$ls180.v:976$3469 + assign { } { } + assign $1\main_uart_tx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:977.5-977.36" + process $proc$ls180.v:977$3470 + assign { } { } + assign $1\main_uart_tx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] + end + attribute \src "ls180.v:979.5-979.32" + process $proc$ls180.v:979$3471 + assign { } { } + assign $1\main_uart_rx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] + end + attribute \src "ls180.v:98.12-98.60" + process $proc$ls180.v:98$3143 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + end + attribute \src "ls180.v:981.5-981.30" + process $proc$ls180.v:981$3472 + assign { } { } + assign $1\main_uart_rx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:982.5-982.36" + process $proc$ls180.v:982$3473 + assign { } { } + assign $1\main_uart_rx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] + end + attribute \src "ls180.v:986.11-986.49" + process $proc$ls180.v:986$3474 + assign { } { } + assign $1\main_uart_eventmanager_status_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:990.11-990.50" + process $proc$ls180.v:990$3475 + assign { } { } + assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:991.11-991.48" + process $proc$ls180.v:991$3476 + assign { } { } + assign $1\main_uart_eventmanager_storage[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] + end + attribute \src "ls180.v:992.5-992.37" + process $proc$ls180.v:992$3477 + assign { } { } + assign $1\main_uart_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] + end + connect \main_libresocsim_libresoc_reset \main_libresocsim_reset + connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i + connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o + connect \sys_pll_lck_o \main_libresocsim_libresoc_pll_lck_o + connect \main_libresocsim_libresoc_jtag_tck \jtag_tck + connect \main_libresocsim_libresoc_jtag_tms \jtag_tms + connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi + connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo + connect \main_nc \nc + connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid + connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 + connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first + connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last + connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data + connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 + connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready + connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 + connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 + connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 + connect \main_libresocsim_bus_error \builder_error + connect \main_converter0_reset $not$ls180.v:2890$50_Y + connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } + connect \main_converter1_reset $not$ls180.v:2950$61_Y + connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } + connect \main_socbushandler_reset $not$ls180.v:3010$72_Y + connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } + connect \main_libresocsim_reset \main_libresocsim_reset_re + connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0] + connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r + connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w + connect \main_libresocsim_zero_trigger $ne$ls180.v:3086$108_Y + connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status + connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending + connect \main_libresocsim_irq $and$ls180.v:3095$111_Y + connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger + connect \main_sram0_adr \main_interface0_ram_bus_adr [5:0] + connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r + connect \main_sram0_dat_w \main_interface0_ram_bus_dat_w + connect \main_sram1_adr \main_interface1_ram_bus_adr [5:0] + connect \main_interface1_ram_bus_dat_r \main_sram1_dat_r + connect \main_sram1_dat_w \main_interface1_ram_bus_dat_w + connect \main_sram2_adr \main_interface2_ram_bus_adr [5:0] + connect \main_interface2_ram_bus_dat_r \main_sram2_dat_r + connect \main_sram2_dat_w \main_interface2_ram_bus_dat_w + connect \main_sram3_adr \main_interface3_ram_bus_adr [5:0] + connect \main_interface3_ram_bus_dat_r \main_sram3_dat_r + connect \main_sram3_dat_w \main_interface3_ram_bus_dat_w + connect \sys_clk_1 \sys_clk + connect \por_clk \sys_clk + connect \sys_rst_1 \main_int_rst + connect \main_dfi_p0_address \main_sdram_master_p0_address + connect \main_dfi_p0_bank \main_sdram_master_p0_bank + connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n + connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n + connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n + connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n + connect \main_dfi_p0_cke \main_sdram_master_p0_cke + connect \main_dfi_p0_odt \main_sdram_master_p0_odt + connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n + connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n + connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata + connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en + connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask + connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en + connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata + connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid + connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address + connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank + connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n + connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n + connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n + connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n + connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke + connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt + connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n + connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n + connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata + connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en + connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask + connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en + connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata + connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid + connect \main_sdram_inti_p0_cke \main_sdram_cke + connect \main_sdram_inti_p0_odt \main_sdram_odt + connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n + connect \main_sdram_inti_p0_address \main_sdram_address_storage + connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3265$218_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3266$219_Y + connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage + connect \main_sdram_inti_p0_wrdata_mask 2'00 + connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid + connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready + connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we + connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr + connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock + connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready + connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid + connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid + connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready + connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we + connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr + connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock + connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready + connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid + connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid + connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready + connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we + connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr + connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock + connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready + connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid + connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid + connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready + connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we + connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr + connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock + connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready + connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid + connect \main_sdram_timer_wait $not$ls180.v:3297$220_Y + connect \main_sdram_postponer_req_i \main_sdram_timer_done0 + connect \main_sdram_wants_refresh \main_sdram_postponer_req_o + connect \main_sdram_timer_done1 $eq$ls180.v:3300$221_Y + connect \main_sdram_timer_done0 \main_sdram_timer_done1 + connect \main_sdram_timer_count0 \main_sdram_timer_count1 + connect \main_sdram_sequencer_start1 $or$ls180.v:3303$223_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3304$225_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid + connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr + connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3346$227_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3347$228_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3348$229_Y + connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3358$234_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3359$236_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3360$238_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3392$246_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3393$247_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3396$248_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3397$249_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3398$251_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid + connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr + connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3503$257_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3504$258_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3505$259_Y + connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3515$264_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3516$266_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3517$268_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3549$276_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3550$277_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3553$278_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3554$279_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3555$281_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid + connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr + connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3660$287_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3661$288_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3662$289_Y + connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3672$294_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3673$296_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3674$298_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3706$306_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3707$307_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3710$308_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3711$309_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3712$311_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid + connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr + connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3817$317_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3818$318_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3819$319_Y + connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3829$324_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3830$326_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3831$328_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3863$336_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3864$337_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3867$338_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3868$339_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3869$341_Y + connect \main_sdram_choose_req_want_cmds 1'1 + connect \main_sdram_trrdcon_valid $and$ls180.v:3965$352_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3966$358_Y + connect \main_sdram_ras_allowed $and$ls180.v:3967$359_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3968$362_Y + connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready + connect \main_sdram_twtrcon_valid $and$ls180.v:3970$364_Y + connect \main_sdram_read_available $or$ls180.v:3971$371_Y + connect \main_sdram_write_available $or$ls180.v:3972$378_Y + connect \main_sdram_max_time0 $eq$ls180.v:3973$379_Y + connect \main_sdram_max_time1 $eq$ls180.v:3974$380_Y + connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid + connect \main_sdram_go_to_refresh $and$ls180.v:3979$383_Y + connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata + connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3982$384_Y + connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids + connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 + connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 + connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 + connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 + connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 + connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 + connect \main_sdram_choose_cmd_ce $or$ls180.v:4015$442_Y + connect \main_sdram_choose_req_request \main_sdram_choose_req_valids + connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 + connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 + connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 + connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 + connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 + connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 + connect \main_sdram_choose_req_ce $or$ls180.v:4084$528_Y + connect \main_sdram_dfi_p0_reset_n 1'1 + connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 + connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 + connect \builder_roundrobin0_request $and$ls180.v:4161$560_Y + connect \builder_roundrobin0_ce $and$ls180.v:4162$563_Y + connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 + connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 + connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 + connect \builder_roundrobin1_request $and$ls180.v:4166$576_Y + connect \builder_roundrobin1_ce $and$ls180.v:4167$579_Y + connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 + connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 + connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 + connect \builder_roundrobin2_request $and$ls180.v:4171$592_Y + connect \builder_roundrobin2_ce $and$ls180.v:4172$595_Y + connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 + connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 + connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 + connect \builder_roundrobin3_request $and$ls180.v:4176$608_Y + connect \builder_roundrobin3_ce $and$ls180.v:4177$611_Y + connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 + connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 + connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 + connect \main_port_cmd_ready $or$ls180.v:4181$675_Y + connect \main_port_wdata_ready \builder_new_master_wdata_ready + connect \main_port_rdata_valid \builder_new_master_rdata_valid3 + connect \main_port_rdata_payload_data \main_sdram_interface_rdata + connect \builder_roundrobin0_grant 1'0 + connect \builder_roundrobin1_grant 1'0 + connect \builder_roundrobin2_grant 1'0 + connect \builder_roundrobin3_grant 1'0 + connect \main_converter_reset $not$ls180.v:4203$677_Y + connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } + connect \main_port_cmd_payload_addr $sub$ls180.v:4263$688_Y [23:0] + connect \main_port_cmd_payload_we \main_litedram_wb_we + connect \main_port_wdata_payload_data \main_litedram_wb_dat_w + connect \main_port_wdata_payload_we \main_litedram_wb_sel + connect \main_litedram_wb_dat_r \main_port_rdata_payload_data + connect \main_port_flush $not$ls180.v:4268$689_Y + connect \main_port_cmd_last $not$ls180.v:4269$690_Y + connect \main_port_cmd_valid $and$ls180.v:4270$693_Y + connect \main_port_wdata_valid $and$ls180.v:4271$697_Y + connect \main_port_rdata_ready $and$ls180.v:4272$700_Y + connect \main_litedram_wb_ack $and$ls180.v:4273$705_Y + connect \main_ack_cmd $or$ls180.v:4274$707_Y + connect \main_ack_wdata $or$ls180.v:4275$709_Y + connect \main_ack_rdata $and$ls180.v:4276$710_Y + connect \main_uart_uart_sink_valid \main_uart_phy_source_valid + connect \main_uart_phy_source_ready \main_uart_uart_sink_ready + connect \main_uart_uart_sink_first \main_uart_phy_source_first + connect \main_uart_uart_sink_last \main_uart_phy_source_last + connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data + connect \main_uart_phy_sink_valid \main_uart_uart_source_valid + connect \main_uart_uart_source_ready \main_uart_phy_sink_ready + connect \main_uart_phy_sink_first \main_uart_uart_source_first + connect \main_uart_phy_sink_last \main_uart_uart_source_last + connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data + connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re + connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r + connect \main_uart_txfull_status $not$ls180.v:4289$711_Y + connect \main_uart_txempty_status $not$ls180.v:4290$712_Y + connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid + connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready + connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first + connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last + connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data + connect \main_uart_tx_trigger $not$ls180.v:4296$713_Y + connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid + connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready + connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first + connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last + connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data + connect \main_uart_rxempty_status $not$ls180.v:4302$714_Y + connect \main_uart_rxfull_status $not$ls180.v:4303$715_Y + connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4305$717_Y + connect \main_uart_rx_trigger $not$ls180.v:4306$718_Y + connect \main_uart_irq $or$ls180.v:4329$727_Y + connect \main_uart_tx_status \main_uart_tx_trigger + connect \main_uart_rx_status \main_uart_rx_trigger + connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } + connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout + connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable + connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid + connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first + connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last + connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data + connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable + connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first + connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last + connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data + connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4344$730_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4345$731_Y + connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4355$735_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4356$736_Y + connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume + connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r + connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4360$737_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4361$738_Y + connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } + connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout + connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable + connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid + connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first + connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last + connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data + connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable + connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first + connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last + connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data + connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4374$741_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4375$742_Y + connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4385$746_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4386$747_Y + connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume + connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r + connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4390$748_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4391$749_Y + connect \main_gpiotristateasic0_pads_i \gpio_i + connect \main_gpiotristateasic0_pads_oe \main_gpiotristateasic0_oe_storage + connect \main_gpiotristateasic0_pads_o \main_gpiotristateasic0_out_storage + connect \main_gpiotristateasic1_pads_i \gpio_i + connect \main_gpiotristateasic1_pads_oe \main_gpiotristateasic1_oe_storage + connect \main_gpiotristateasic1_pads_o \main_gpiotristateasic1_out_storage + connect \main_spimaster0_start \main_spimaster9_start + connect \main_spimaster1_length \main_spimaster10_length + connect \main_spimaster4_mosi \main_spimaster16_storage + connect \main_spimaster13_done \main_spimaster2_done + connect \main_spimaster18_status \main_spimaster5_miso + connect \main_spimaster6_cs \main_spimaster21_storage + connect \main_spimaster7_loopback \main_spimaster23_storage + connect \main_spimaster31_clk_rise $eq$ls180.v:4415$753_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4416$755_Y + connect \main_spisdcard_start0 \main_spisdcard_start1 + connect \main_spisdcard_length0 \main_spisdcard_length1 + connect \main_spisdcard_mosi \main_spisdcard_mosi_storage + connect \main_spisdcard_done1 \main_spisdcard_done0 + connect \main_spisdcard_miso_status \main_spisdcard_miso + connect \main_spisdcard_cs \main_spisdcard_cs_storage + connect \main_spisdcard_loopback \main_spisdcard_loopback_storage + connect \main_spisdcard_clk_rise $eq$ls180.v:4473$761_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4474$763_Y + connect \main_spisdcard_clk_divider0 \main_spimaster1_storage + connect \i2c_scl \main_i2c_scl + connect \i2c_sda_oe \main_i2c_oe + connect \i2c_sda_o \main_i2c_sda0 + connect \main_i2c_sda1 \i2c_sda_i + connect \main_sdphy_status 1'0 + connect \main_sdphy_sdpads_clk $or$ls180.v:4530$771_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4531$775_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4532$779_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4533$783_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4534$787_Y + connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_clocker_stop $or$ls180.v:4555$788_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4585$791_Y + connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid + connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready + connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first + connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last + connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4708$801_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4709$803_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 + connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready + connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 + connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 + connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 + connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid + connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 + connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data + connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid + connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 + connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4726$805_Y + connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4728$806_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4729$808_Y + connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid + connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready + connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first + connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last + connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i + connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o + connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4835$823_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4836$824_Y + connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 + connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready + connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 + connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 + connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 + connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid + connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 + connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first + connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data + connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid + connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 + connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first + connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4853$826_Y + connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4855$827_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4856$829_Y + connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid + connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready + connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first + connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last + connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk + connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i + connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o + connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe + connect \main_sdphy_datar_datar_start $eq$ls180.v:4969$838_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4970$839_Y + connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i + connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 + connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready + connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 + connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 + connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 + connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid + connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 + connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first + connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last + connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data + connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid + connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 + connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first + connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last + connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4987$841_Y + connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4989$842_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4990$844_Y + connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid + connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready + connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first + connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last + connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data + connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid + connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready + connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first + connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last + connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data + connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] + connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] + connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } + connect \main_sdcore_data_event_status { $not$ls180.v:5106$859_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } + connect \main_sdcore_crc7_inserter_clr 1'1 + connect \main_sdcore_crc7_inserter_enable 1'1 + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5110$862_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5110$860_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5111$865_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5111$863_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5112$868_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5112$866_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5113$871_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5113$869_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5114$874_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5114$872_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5115$877_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5115$875_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5116$880_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5116$878_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5117$883_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5117$881_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5118$886_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5118$884_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5119$889_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5119$887_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5120$892_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5120$890_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5121$895_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5121$893_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5122$898_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5122$896_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5123$901_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5123$899_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5124$904_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5124$902_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5125$907_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5125$905_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5126$910_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5126$908_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5127$913_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5127$911_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5128$916_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5128$914_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5129$919_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5129$917_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5130$922_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5130$920_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5131$925_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5131$923_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5132$928_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5132$926_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5133$931_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5133$929_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5134$934_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5134$932_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5135$937_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5135$935_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5136$940_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5136$938_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5137$943_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5137$941_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5138$946_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5138$944_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5139$949_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5139$947_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5140$952_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5140$950_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5141$955_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5141$953_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5142$958_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5142$956_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5143$961_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5143$959_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5144$964_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5144$962_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5145$967_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5145$965_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5146$970_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5146$968_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5147$973_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5147$971_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5148$976_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5148$974_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5149$979_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5149$977_Y } + connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5159$982_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5160$983_Y + connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5162$985_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5163$986_Y + connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5165$988_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5166$989_Y + connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5168$991_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5169$992_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5170$997_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5170$995_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5170$993_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5171$1002_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5171$1000_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5171$998_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5180$1008_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5180$1006_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5180$1004_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5181$1013_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5181$1011_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5181$1009_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5190$1019_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5190$1017_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5190$1015_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5191$1024_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5191$1022_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5191$1020_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5200$1030_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5200$1028_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5200$1026_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5201$1035_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5201$1033_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5201$1031_Y } + connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5297$1051_Y + connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5307$1054_Y + connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5317$1057_Y + connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5327$1060_Y + connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val + connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5352$1072_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5352$1070_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5352$1068_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5353$1077_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5353$1075_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5353$1073_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5362$1083_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5362$1081_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5362$1079_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5363$1088_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5363$1086_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5363$1084_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5372$1094_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5372$1092_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5372$1090_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5373$1099_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5373$1097_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5373$1095_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5382$1105_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5382$1103_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5382$1101_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5383$1110_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5383$1108_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5383$1106_Y } + connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 + connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready + connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first + connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last + connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 + connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid + connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready + connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first + connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last + connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data + connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid + connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first + connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last + connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data + connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } + connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout + connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable + connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid + connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first + connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last + connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data + connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable + connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first + connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last + connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data + connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready + connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5619$1140_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5620$1141_Y + connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume + connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5623$1142_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5624$1143_Y + connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid + connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready + connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first + connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last + connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5630$1145_Y + connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5632$1146_Y + connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_we 1'1 + connect \main_interface0_bus_sel 8'11111111 + connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] \main_sdblock2mem_sink_sink_payload_data1 [39:32] \main_sdblock2mem_sink_sink_payload_data1 [47:40] \main_sdblock2mem_sink_sink_payload_data1 [55:48] \main_sdblock2mem_sink_sink_payload_data1 [63:56] } + connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] + connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5642$1147_Y + connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid + connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready + connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first + connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last + connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data + connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 + connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready + connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 + connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 + connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 + connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid + connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 + connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first + connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last + connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] + connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } + connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset + connect \main_sdmem2block_dma_reset $not$ls180.v:5701$1154_Y + connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid + connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 + connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first + connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last + connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data + connect \main_sdmem2block_converter_first $eq$ls180.v:5782$1162_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5783$1163_Y + connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid + connect \main_sdmem2block_converter_source_first $and$ls180.v:5785$1164_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5786$1165_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5787$1166_Y + connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last + connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } + connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout + connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable + connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid + connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first + connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last + connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data + connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable + connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first + connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last + connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data + connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready + connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5839$1171_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5840$1172_Y + connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume + connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5843$1173_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5844$1174_Y + connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] + connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 + connect \builder_shared_stb \builder_comb_rhs_array_muxed28 + connect \builder_shared_we \builder_comb_rhs_array_muxed29 + connect \builder_shared_cti \builder_comb_rhs_array_muxed30 + connect \builder_shared_bte \builder_comb_rhs_array_muxed31 + connect \main_libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5895$1180_Y + connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5896$1182_Y + connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5897$1184_Y + connect \main_interface0_bus_ack $and$ls180.v:5898$1186_Y + connect \main_interface1_bus_ack $and$ls180.v:5899$1188_Y + connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5900$1190_Y + connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5901$1192_Y + connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5902$1194_Y + connect \main_interface0_bus_err $and$ls180.v:5903$1196_Y + connect \main_interface1_bus_err $and$ls180.v:5904$1198_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } + connect \main_libresocsim_ram_bus_adr \builder_shared_adr + connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_ram_bus_stb \builder_shared_stb + connect \main_libresocsim_ram_bus_we \builder_shared_we + connect \main_libresocsim_ram_bus_cti \builder_shared_cti + connect \main_libresocsim_ram_bus_bte \builder_shared_bte + connect \main_interface0_ram_bus_adr \builder_shared_adr + connect \main_interface0_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface0_ram_bus_stb \builder_shared_stb + connect \main_interface0_ram_bus_we \builder_shared_we + connect \main_interface0_ram_bus_cti \builder_shared_cti + connect \main_interface0_ram_bus_bte \builder_shared_bte + connect \main_interface1_ram_bus_adr \builder_shared_adr + connect \main_interface1_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface1_ram_bus_stb \builder_shared_stb + connect \main_interface1_ram_bus_we \builder_shared_we + connect \main_interface1_ram_bus_cti \builder_shared_cti + connect \main_interface1_ram_bus_bte \builder_shared_bte + connect \main_interface2_ram_bus_adr \builder_shared_adr + connect \main_interface2_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface2_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface2_ram_bus_stb \builder_shared_stb + connect \main_interface2_ram_bus_we \builder_shared_we + connect \main_interface2_ram_bus_cti \builder_shared_cti + connect \main_interface2_ram_bus_bte \builder_shared_bte + connect \main_interface3_ram_bus_adr \builder_shared_adr + connect \main_interface3_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface3_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface3_ram_bus_stb \builder_shared_stb + connect \main_interface3_ram_bus_we \builder_shared_we + connect \main_interface3_ram_bus_cti \builder_shared_cti + connect \main_interface3_ram_bus_bte \builder_shared_bte + connect \main_interface0_converted_interface_adr \builder_shared_adr + connect \main_interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface0_converted_interface_stb \builder_shared_stb + connect \main_interface0_converted_interface_we \builder_shared_we + connect \main_interface0_converted_interface_cti \builder_shared_cti + connect \main_interface0_converted_interface_bte \builder_shared_bte + connect \main_interface1_converted_interface_adr \builder_shared_adr + connect \main_interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface1_converted_interface_stb \builder_shared_stb + connect \main_interface1_converted_interface_we \builder_shared_we + connect \main_interface1_converted_interface_cti \builder_shared_cti + connect \main_interface1_converted_interface_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface0_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface0_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface0_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface0_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface0_we \builder_shared_we + connect \main_libresocsim_libresoc_interface0_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface0_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface1_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface1_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface1_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface1_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface1_we \builder_shared_we + connect \main_libresocsim_libresoc_interface1_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface1_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface2_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface2_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface2_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface2_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface2_we \builder_shared_we + connect \main_libresocsim_libresoc_interface2_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface2_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface3_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface3_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface3_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface3_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface3_we \builder_shared_we + connect \main_libresocsim_libresoc_interface3_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface3_bte \builder_shared_bte + connect \main_socbushandler_converted_interface_adr \builder_shared_adr + connect \main_socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_socbushandler_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_socbushandler_converted_interface_stb \builder_shared_stb + connect \main_socbushandler_converted_interface_we \builder_shared_we + connect \main_socbushandler_converted_interface_cti \builder_shared_cti + connect \main_socbushandler_converted_interface_bte \builder_shared_bte + connect \builder_libresocsim_converted_interface_adr \builder_shared_adr + connect \builder_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \builder_libresocsim_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \builder_libresocsim_converted_interface_stb \builder_shared_stb + connect \builder_libresocsim_converted_interface_we \builder_shared_we + connect \builder_libresocsim_converted_interface_cti \builder_shared_cti + connect \builder_libresocsim_converted_interface_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:6013$1213_Y + connect \main_interface0_ram_bus_cyc $and$ls180.v:6014$1214_Y + connect \main_interface1_ram_bus_cyc $and$ls180.v:6015$1215_Y + connect \main_interface2_ram_bus_cyc $and$ls180.v:6016$1216_Y + connect \main_interface3_ram_bus_cyc $and$ls180.v:6017$1217_Y + connect \main_interface0_converted_interface_cyc $and$ls180.v:6018$1218_Y + connect \main_interface1_converted_interface_cyc $and$ls180.v:6019$1219_Y + connect \main_libresocsim_libresoc_interface0_cyc $and$ls180.v:6020$1220_Y + connect \main_libresocsim_libresoc_interface1_cyc $and$ls180.v:6021$1221_Y + connect \main_libresocsim_libresoc_interface2_cyc $and$ls180.v:6022$1222_Y + connect \main_libresocsim_libresoc_interface3_cyc $and$ls180.v:6023$1223_Y + connect \main_socbushandler_converted_interface_cyc $and$ls180.v:6024$1224_Y + connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:6025$1225_Y + connect \builder_shared_err $or$ls180.v:6026$1237_Y + connect \builder_wait $and$ls180.v:6027$1240_Y + connect \builder_done $eq$ls180.v:6040$1279_Y + connect \builder_csrbank0_sel $eq$ls180.v:6041$1280_Y + connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] + connect \builder_csrbank0_reset0_re $and$ls180.v:6043$1283_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:6044$1287_Y + connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch3_re $and$ls180.v:6046$1290_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:6047$1294_Y + connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch2_re $and$ls180.v:6049$1297_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:6050$1301_Y + connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch1_re $and$ls180.v:6052$1304_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:6053$1308_Y + connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch0_re $and$ls180.v:6055$1311_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:6056$1315_Y + connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:6058$1318_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:6059$1322_Y + connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:6061$1325_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:6062$1329_Y + connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:6064$1332_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:6065$1336_Y + connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:6067$1339_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:6068$1343_Y + connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage + connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] + connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] + connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] + connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] + connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] + connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] + connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] + connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] + connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we + connect \builder_csrbank1_sel $eq$ls180.v:6079$1344_Y + connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe1_re $and$ls180.v:6081$1347_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:6082$1351_Y + connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe0_re $and$ls180.v:6084$1354_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:6085$1358_Y + connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in1_re $and$ls180.v:6087$1361_Y + connect \builder_csrbank1_in1_we $and$ls180.v:6088$1365_Y + connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in0_re $and$ls180.v:6090$1368_Y + connect \builder_csrbank1_in0_we $and$ls180.v:6091$1372_Y + connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out1_re $and$ls180.v:6093$1375_Y + connect \builder_csrbank1_out1_we $and$ls180.v:6094$1379_Y + connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out0_re $and$ls180.v:6096$1382_Y + connect \builder_csrbank1_out0_we $and$ls180.v:6097$1386_Y + connect \builder_csrbank1_oe1_w \main_gpiotristateasic1_oe_storage [15:8] + connect \builder_csrbank1_oe0_w \main_gpiotristateasic1_oe_storage [7:0] + connect \builder_csrbank1_in1_w \main_gpiotristateasic1_status [15:8] + connect \builder_csrbank1_in0_w \main_gpiotristateasic1_status [7:0] + connect \main_gpiotristateasic1_we \builder_csrbank1_in0_we + connect \builder_csrbank1_out1_w \main_gpiotristateasic1_out_storage [15:8] + connect \builder_csrbank1_out0_w \main_gpiotristateasic1_out_storage [7:0] + connect \builder_csrbank2_sel $eq$ls180.v:6105$1387_Y + connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] + connect \builder_csrbank2_w0_re $and$ls180.v:6107$1390_Y + connect \builder_csrbank2_w0_we $and$ls180.v:6108$1394_Y + connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] + connect \builder_csrbank2_r_re $and$ls180.v:6110$1397_Y + connect \builder_csrbank2_r_we $and$ls180.v:6111$1401_Y + connect \main_i2c_scl \main_i2c_storage [0] + connect \main_i2c_oe \main_i2c_storage [1] + connect \main_i2c_sda0 \main_i2c_storage [2] + connect \builder_csrbank2_w0_w \main_i2c_storage + connect \main_i2c_status \main_i2c_sda1 + connect \builder_csrbank2_r_w \main_i2c_status + connect \main_i2c_we \builder_csrbank2_r_we + connect \builder_csrbank3_sel $eq$ls180.v:6119$1402_Y + connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_enable0_re $and$ls180.v:6121$1405_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:6122$1409_Y + connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width3_re $and$ls180.v:6124$1412_Y + connect \builder_csrbank3_width3_we $and$ls180.v:6125$1416_Y + connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width2_re $and$ls180.v:6127$1419_Y + connect \builder_csrbank3_width2_we $and$ls180.v:6128$1423_Y + connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width1_re $and$ls180.v:6130$1426_Y + connect \builder_csrbank3_width1_we $and$ls180.v:6131$1430_Y + connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width0_re $and$ls180.v:6133$1433_Y + connect \builder_csrbank3_width0_we $and$ls180.v:6134$1437_Y + connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period3_re $and$ls180.v:6136$1440_Y + connect \builder_csrbank3_period3_we $and$ls180.v:6137$1444_Y + connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period2_re $and$ls180.v:6139$1447_Y + connect \builder_csrbank3_period2_we $and$ls180.v:6140$1451_Y + connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period1_re $and$ls180.v:6142$1454_Y + connect \builder_csrbank3_period1_we $and$ls180.v:6143$1458_Y + connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period0_re $and$ls180.v:6145$1461_Y + connect \builder_csrbank3_period0_we $and$ls180.v:6146$1465_Y + connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage + connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] + connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] + connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] + connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] + connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] + connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] + connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] + connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] + connect \builder_csrbank4_sel $eq$ls180.v:6156$1466_Y + connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_enable0_re $and$ls180.v:6158$1469_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:6159$1473_Y + connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width3_re $and$ls180.v:6161$1476_Y + connect \builder_csrbank4_width3_we $and$ls180.v:6162$1480_Y + connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width2_re $and$ls180.v:6164$1483_Y + connect \builder_csrbank4_width2_we $and$ls180.v:6165$1487_Y + connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width1_re $and$ls180.v:6167$1490_Y + connect \builder_csrbank4_width1_we $and$ls180.v:6168$1494_Y + connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width0_re $and$ls180.v:6170$1497_Y + connect \builder_csrbank4_width0_we $and$ls180.v:6171$1501_Y + connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period3_re $and$ls180.v:6173$1504_Y + connect \builder_csrbank4_period3_we $and$ls180.v:6174$1508_Y + connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period2_re $and$ls180.v:6176$1511_Y + connect \builder_csrbank4_period2_we $and$ls180.v:6177$1515_Y + connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period1_re $and$ls180.v:6179$1518_Y + connect \builder_csrbank4_period1_we $and$ls180.v:6180$1522_Y + connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period0_re $and$ls180.v:6182$1525_Y + connect \builder_csrbank4_period0_we $and$ls180.v:6183$1529_Y + connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage + connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] + connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] + connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] + connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] + connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] + connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] + connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] + connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] + connect \builder_csrbank5_sel $eq$ls180.v:6193$1530_Y + connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base7_re $and$ls180.v:6195$1533_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:6196$1537_Y + connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base6_re $and$ls180.v:6198$1540_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:6199$1544_Y + connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base5_re $and$ls180.v:6201$1547_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:6202$1551_Y + connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base4_re $and$ls180.v:6204$1554_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:6205$1558_Y + connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base3_re $and$ls180.v:6207$1561_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:6208$1565_Y + connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base2_re $and$ls180.v:6210$1568_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:6211$1572_Y + connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base1_re $and$ls180.v:6213$1575_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:6214$1579_Y + connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base0_re $and$ls180.v:6216$1582_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:6217$1586_Y + connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length3_re $and$ls180.v:6219$1589_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:6220$1593_Y + connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length2_re $and$ls180.v:6222$1596_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:6223$1600_Y + connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length1_re $and$ls180.v:6225$1603_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:6226$1607_Y + connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length0_re $and$ls180.v:6228$1610_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:6229$1614_Y + connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6231$1617_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6232$1621_Y + connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_done_re $and$ls180.v:6234$1624_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:6235$1628_Y + connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6237$1631_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6238$1635_Y + connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] + connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] + connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] + connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] + connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] + connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] + connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] + connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] + connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] + connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] + connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] + connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] + connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status + connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we + connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage + connect \builder_csrbank6_sel $eq$ls180.v:6255$1636_Y + connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6257$1639_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6258$1643_Y + connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6260$1646_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6261$1650_Y + connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6263$1653_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6264$1657_Y + connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6266$1660_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6267$1664_Y + connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6269$1667_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6270$1671_Y + connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6272$1674_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6273$1678_Y + connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6275$1681_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6276$1685_Y + connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6278$1688_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6279$1692_Y + connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] + connect \main_sdcore_cmd_send_re $and$ls180.v:6281$1695_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6282$1699_Y + connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6284$1702_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6285$1706_Y + connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6287$1709_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6288$1713_Y + connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6290$1716_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6291$1720_Y + connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6293$1723_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6294$1727_Y + connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6296$1730_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6297$1734_Y + connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6299$1737_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6300$1741_Y + connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6302$1744_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6303$1748_Y + connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6305$1751_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6306$1755_Y + connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6308$1758_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6309$1762_Y + connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6311$1765_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6312$1769_Y + connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6314$1772_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6315$1776_Y + connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6317$1779_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6318$1783_Y + connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6320$1786_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6321$1790_Y + connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6323$1793_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6324$1797_Y + connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6326$1800_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6327$1804_Y + connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6329$1807_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6330$1811_Y + connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6332$1814_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6333$1818_Y + connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_data_event_re $and$ls180.v:6335$1821_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6336$1825_Y + connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] + connect \builder_csrbank6_block_length1_re $and$ls180.v:6338$1828_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6339$1832_Y + connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_length0_re $and$ls180.v:6341$1835_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6342$1839_Y + connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count3_re $and$ls180.v:6344$1842_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6345$1846_Y + connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count2_re $and$ls180.v:6347$1849_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6348$1853_Y + connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count1_re $and$ls180.v:6350$1856_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6351$1860_Y + connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count0_re $and$ls180.v:6353$1863_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6354$1867_Y + connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] + connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] + connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] + connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] + connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] + connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] + connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] + connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] + connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] + connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] + connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] + connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] + connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] + connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] + connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] + connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] + connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] + connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] + connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] + connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] + connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] + connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] + connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] + connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] + connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we + connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status + connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we + connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status + connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we + connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] + connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] + connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] + connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] + connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] + connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] + connect \builder_csrbank7_sel $eq$ls180.v:6390$1868_Y + connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6392$1871_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6393$1875_Y + connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6395$1878_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6396$1882_Y + connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6398$1885_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6399$1889_Y + connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6401$1892_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6402$1896_Y + connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6404$1899_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6405$1903_Y + connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6407$1906_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6408$1910_Y + connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6410$1913_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6411$1917_Y + connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6413$1920_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6414$1924_Y + connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6416$1927_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6417$1931_Y + connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6419$1934_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6420$1938_Y + connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6422$1941_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6423$1945_Y + connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6425$1948_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6426$1952_Y + connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6428$1955_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6429$1959_Y + connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_done_re $and$ls180.v:6431$1962_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6432$1966_Y + connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6434$1969_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6435$1973_Y + connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6437$1976_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6438$1980_Y + connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6440$1983_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6441$1987_Y + connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6443$1990_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6444$1994_Y + connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6446$1997_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6447$2001_Y + connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] + connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] + connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] + connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] + connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] + connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] + connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] + connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] + connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] + connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] + connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] + connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] + connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage + connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status + connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we + connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage + connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] + connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] + connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] + connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] + connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we + connect \builder_csrbank8_sel $eq$ls180.v:6469$2002_Y + connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_card_detect_re $and$ls180.v:6471$2005_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6472$2009_Y + connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6474$2012_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6475$2016_Y + connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6477$2019_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6478$2023_Y + connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] + connect \main_sdphy_init_initialize_re $and$ls180.v:6480$2026_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6481$2030_Y + connect \builder_csrbank8_card_detect_w \main_sdphy_status + connect \main_sdphy_we \builder_csrbank8_card_detect_we + connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] + connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] + connect \builder_csrbank9_sel $eq$ls180.v:6486$2031_Y + connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6488$2034_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6489$2038_Y + connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6491$2041_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6492$2045_Y + connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] + connect \main_sdram_command_issue_re $and$ls180.v:6494$2048_Y + connect \main_sdram_command_issue_we $and$ls180.v:6495$2052_Y + connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6497$2055_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6498$2059_Y + connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6500$2062_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6501$2066_Y + connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6503$2069_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6504$2073_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6506$2076_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6507$2080_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6509$2083_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6510$2087_Y + connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6512$2090_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6513$2094_Y + connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6515$2097_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6516$2101_Y + connect \main_sdram_sel \main_sdram_storage [0] + connect \main_sdram_cke \main_sdram_storage [1] + connect \main_sdram_odt \main_sdram_storage [2] + connect \main_sdram_reset_n \main_sdram_storage [3] + connect \builder_csrbank9_dfii_control0_w \main_sdram_storage + connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage + connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] + connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] + connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage + connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] + connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] + connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] + connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] + connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we + connect \builder_csrbank10_sel $eq$ls180.v:6531$2102_Y + connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control1_re $and$ls180.v:6533$2105_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6534$2109_Y + connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control0_re $and$ls180.v:6536$2112_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6537$2116_Y + connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_status_re $and$ls180.v:6539$2119_Y + connect \builder_csrbank10_status_we $and$ls180.v:6540$2123_Y + connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_mosi0_re $and$ls180.v:6542$2126_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6543$2130_Y + connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_miso_re $and$ls180.v:6545$2133_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6546$2137_Y + connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_cs0_re $and$ls180.v:6548$2140_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6549$2144_Y + connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_loopback0_re $and$ls180.v:6551$2147_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6552$2151_Y + connect \main_spimaster10_length \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] + connect \main_spimaster14_status \main_spimaster13_done + connect \builder_csrbank10_status_w \main_spimaster14_status + connect \main_spimaster15_we \builder_csrbank10_status_we + connect \builder_csrbank10_mosi0_w \main_spimaster16_storage + connect \builder_csrbank10_miso_w \main_spimaster18_status + connect \main_spimaster19_we \builder_csrbank10_miso_we + connect \main_spimaster20_sel \main_spimaster21_storage + connect \builder_csrbank10_cs0_w \main_spimaster21_storage + connect \builder_csrbank10_loopback0_w \main_spimaster23_storage + connect \builder_csrbank11_sel $eq$ls180.v:6571$2153_Y + connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control1_re $and$ls180.v:6573$2156_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6574$2160_Y + connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control0_re $and$ls180.v:6576$2163_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6577$2167_Y + connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_status_re $and$ls180.v:6579$2170_Y + connect \builder_csrbank11_status_we $and$ls180.v:6580$2174_Y + connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_mosi0_re $and$ls180.v:6582$2177_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6583$2181_Y + connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_miso_re $and$ls180.v:6585$2184_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6586$2188_Y + connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_cs0_re $and$ls180.v:6588$2191_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6589$2195_Y + connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_loopback0_re $and$ls180.v:6591$2198_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6592$2202_Y + connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6594$2205_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6595$2209_Y + connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6597$2212_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6598$2216_Y + connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] + connect \main_spisdcard_status_status \main_spisdcard_done1 + connect \builder_csrbank11_status_w \main_spisdcard_status_status + connect \main_spisdcard_status_we \builder_csrbank11_status_we + connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage + connect \builder_csrbank11_miso_w \main_spisdcard_miso_status + connect \main_spisdcard_miso_we \builder_csrbank11_miso_we + connect \main_spisdcard_sel \main_spisdcard_cs_storage + connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage + connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage + connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] + connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] + connect \builder_csrbank12_sel $eq$ls180.v:6619$2218_Y + connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load3_re $and$ls180.v:6621$2221_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6622$2225_Y + connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load2_re $and$ls180.v:6624$2228_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6625$2232_Y + connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load1_re $and$ls180.v:6627$2235_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6628$2239_Y + connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load0_re $and$ls180.v:6630$2242_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6631$2246_Y + connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload3_re $and$ls180.v:6633$2249_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6634$2253_Y + connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload2_re $and$ls180.v:6636$2256_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6637$2260_Y + connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload1_re $and$ls180.v:6639$2263_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6640$2267_Y + connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload0_re $and$ls180.v:6642$2270_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6643$2274_Y + connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_en0_re $and$ls180.v:6645$2277_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6646$2281_Y + connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_update_value0_re $and$ls180.v:6648$2284_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6649$2288_Y + connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value3_re $and$ls180.v:6651$2291_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6652$2295_Y + connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value2_re $and$ls180.v:6654$2298_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6655$2302_Y + connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value1_re $and$ls180.v:6657$2305_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6658$2309_Y + connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value0_re $and$ls180.v:6660$2312_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6661$2316_Y + connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6663$2319_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6664$2323_Y + connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6666$2326_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6667$2330_Y + connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6669$2333_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6670$2337_Y + connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] + connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] + connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] + connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] + connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] + connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] + connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] + connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] + connect \builder_csrbank12_en0_w \main_libresocsim_en_storage + connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage + connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] + connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] + connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] + connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] + connect \main_libresocsim_value_we \builder_csrbank12_value0_we + connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage + connect \builder_csrbank13_sel $eq$ls180.v:6687$2338_Y + connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w + connect \main_uart_rxtx_re $and$ls180.v:6689$2341_Y + connect \main_uart_rxtx_we $and$ls180.v:6690$2345_Y + connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txfull_re $and$ls180.v:6692$2348_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6693$2352_Y + connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxempty_re $and$ls180.v:6695$2355_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6696$2359_Y + connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_status_re $and$ls180.v:6698$2362_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6699$2366_Y + connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_pending_re $and$ls180.v:6701$2369_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6702$2373_Y + connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6704$2376_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6705$2380_Y + connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txempty_re $and$ls180.v:6707$2383_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6708$2387_Y + connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxfull_re $and$ls180.v:6710$2390_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6711$2394_Y + connect \builder_csrbank13_txfull_w \main_uart_txfull_status + connect \main_uart_txfull_we \builder_csrbank13_txfull_we + connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status + connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we + connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage + connect \builder_csrbank13_txempty_w \main_uart_txempty_status + connect \main_uart_txempty_we \builder_csrbank13_txempty_we + connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status + connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we + connect \builder_csrbank14_sel $eq$ls180.v:6721$2395_Y + connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6723$2398_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6724$2402_Y + connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6726$2405_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6727$2409_Y + connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6729$2412_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6730$2416_Y + connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6732$2419_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6733$2423_Y + connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] + connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] + connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] + connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] + connect \builder_csr_interconnect_adr \builder_libresocsim_adr + connect \builder_csr_interconnect_we \builder_libresocsim_we + connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w + connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r + connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_csr_interconnect_dat_r $or$ls180.v:6787$2437_Y + connect \sdrio_clk \sys_clk_1 + connect \sdrio_clk_1 \sys_clk_1 + connect \sdrio_clk_2 \sys_clk_1 + connect \sdrio_clk_3 \sys_clk_1 + connect \sdrio_clk_4 \sys_clk_1 + connect \sdrio_clk_5 \sys_clk_1 + connect \sdrio_clk_6 \sys_clk_1 + connect \sdrio_clk_7 \sys_clk_1 + connect \sdrio_clk_8 \sys_clk_1 + connect \sdrio_clk_9 \sys_clk_1 + connect \sdrio_clk_10 \sys_clk_1 + connect \sdrio_clk_11 \sys_clk_1 + connect \sdrio_clk_12 \sys_clk_1 + connect \sdrio_clk_13 \sys_clk_1 + connect \sdrio_clk_14 \sys_clk_1 + connect \sdrio_clk_15 \sys_clk_1 + connect \sdrio_clk_16 \sys_clk_1 + connect \sdrio_clk_17 \sys_clk_1 + connect \sdrio_clk_18 \sys_clk_1 + connect \sdrio_clk_19 \sys_clk_1 + connect \sdrio_clk_20 \sys_clk_1 + connect \sdrio_clk_21 \sys_clk_1 + connect \sdrio_clk_22 \sys_clk_1 + connect \sdrio_clk_23 \sys_clk_1 + connect \sdrio_clk_24 \sys_clk_1 + connect \sdrio_clk_25 \sys_clk_1 + connect \sdrio_clk_26 \sys_clk_1 + connect \sdrio_clk_27 \sys_clk_1 + connect \sdrio_clk_28 \sys_clk_1 + connect \sdrio_clk_29 \sys_clk_1 + connect \sdrio_clk_30 \sys_clk_1 + connect \sdrio_clk_31 \sys_clk_1 + connect \sdrio_clk_32 \sys_clk_1 + connect \sdrio_clk_33 \sys_clk_1 + connect \sdrio_clk_34 \sys_clk_1 + connect \sdrio_clk_35 \sys_clk_1 + connect \sdrio_clk_36 \sys_clk_1 + connect \sdrio_clk_37 \sys_clk_1 + connect \sdrio_clk_38 \sys_clk_1 + connect \sdrio_clk_39 \sys_clk_1 + connect \sdrio_clk_40 \sys_clk_1 + connect \sdrio_clk_41 \sys_clk_1 + connect \sdrio_clk_42 \sys_clk_1 + connect \sdrio_clk_43 \sys_clk_1 + connect \sdrio_clk_44 \sys_clk_1 + connect \sdrio_clk_45 \sys_clk_1 + connect \sdrio_clk_46 \sys_clk_1 + connect \sdrio_clk_47 \sys_clk_1 + connect \sdrio_clk_48 \sys_clk_1 + connect \sdrio_clk_49 \sys_clk_1 + connect \sdrio_clk_50 \sys_clk_1 + connect \sdrio_clk_51 \sys_clk_1 + connect \sdrio_clk_52 \sys_clk_1 + connect \sdrio_clk_53 \sys_clk_1 + connect \sdrio_clk_54 \sys_clk_1 + connect \sdrio_clk_55 \sys_clk_1 + connect \main_uart_phy_rx \builder_multiregimpl0_regs1 + connect \main_pwm0_enable \main_pwm0_enable_storage + connect \main_pwm0_width \main_pwm0_width_storage + connect \main_pwm0_period \main_pwm0_period_storage + connect \main_pwm1_enable \main_pwm1_enable_storage + connect \main_pwm1_width \main_pwm1_width_storage + connect \main_pwm1_period \main_pwm1_period_storage + connect \sdrio_clk_56 \sys_clk_1 + connect \sdrio_clk_57 \sys_clk_1 + connect \sdrio_clk_58 \sys_clk_1 + connect \sdrio_clk_59 \sys_clk_1 + connect \sdrio_clk_60 \sys_clk_1 + connect \sdrio_clk_61 \sys_clk_1 + connect \sdrio_clk_62 \sys_clk_1 + connect \sdrio_clk_63 \sys_clk_1 + connect \sdrio_clk_64 \sys_clk_1 + connect \sdrio_clk_65 \sys_clk_1 + connect \sdrio_clk_66 \sys_clk_1 + connect \sdrio_clk_67 \sys_clk_1 + connect \sdrio_clk_68 \sys_clk_1 + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10370$2916_DATA + connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10398$2942_DATA + connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10426$2968_DATA + connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10454$2994_DATA + connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10482$3020_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10500$3027_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10514$3034_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10528$3041_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10542$3048_DATA + connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 + connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 + connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 + connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 + connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10590$3069_DATA + connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10604$3076_DATA end -attribute \src "libresoc.v:154052.1-155209.10" +attribute \src "libresoc.v:144986.1-145044.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" -module \mul0 - attribute \src "libresoc.v:154780.3-154781.25" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:154778.3-154779.40" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:155121.3-155129.6" - wire $0\alu_l_r_alu$next[0:0]$7842 - attribute \src "libresoc.v:154706.3-154707.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire width 13 $0\alu_mul0_mul_op__fn_unit$next[12:0]$7767 - attribute \src "libresoc.v:154734.3-154735.65" - wire width 13 $0\alu_mul0_mul_op__fn_unit[12:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 - attribute \src "libresoc.v:154736.3-154737.79" - wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 - attribute \src "libresoc.v:154738.3-154739.75" - wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7770 - attribute \src "libresoc.v:154754.3-154755.59" - wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7771 - attribute \src "libresoc.v:154732.3-154733.69" - wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7772 - attribute \src "libresoc.v:154750.3-154751.67" - wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7773 - attribute \src "libresoc.v:154752.3-154753.69" - wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7774 - attribute \src "libresoc.v:154744.3-154745.63" - wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7775 - attribute \src "libresoc.v:154746.3-154747.63" - wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7776 - attribute \src "libresoc.v:154742.3-154743.63" - wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7777 - attribute \src "libresoc.v:154740.3-154741.63" - wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7778 - attribute \src "libresoc.v:154748.3-154749.69" - wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:155112.3-155120.6" - wire $0\alui_l_r_alui$next[0:0]$7839 - attribute \src "libresoc.v:154708.3-154709.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:154994.3-155015.6" - wire width 64 $0\data_r0__o$next[63:0]$7798 - attribute \src "libresoc.v:154728.3-154729.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:154994.3-155015.6" - wire $0\data_r0__o_ok$next[0:0]$7799 - attribute \src "libresoc.v:154730.3-154731.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:155016.3-155037.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$7806 - attribute \src "libresoc.v:154724.3-154725.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:155016.3-155037.6" - wire $0\data_r1__cr_a_ok$next[0:0]$7807 - attribute \src "libresoc.v:154726.3-154727.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:155038.3-155059.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$7814 - attribute \src "libresoc.v:154720.3-154721.47" - wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:155038.3-155059.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$7815 - attribute \src "libresoc.v:154722.3-154723.53" - wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:155060.3-155081.6" - wire $0\data_r3__xer_so$next[0:0]$7822 - attribute \src "libresoc.v:154716.3-154717.47" - wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:155060.3-155081.6" - wire $0\data_r3__xer_so_ok$next[0:0]$7823 - attribute \src "libresoc.v:154718.3-154719.53" - wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:155130.3-155139.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:155140.3-155149.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:155150.3-155159.6" - wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:155160.3-155169.6" - wire $0\dest4_o[0:0] - attribute \src "libresoc.v:154053.7-154053.20" +module \lsd_l + attribute \src "libresoc.v:144987.7-144987.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154916.3-154924.6" - wire $0\opc_l_r_opc$next[0:0]$7752 - attribute \src "libresoc.v:154764.3-154765.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:154907.3-154915.6" - wire $0\opc_l_s_opc$next[0:0]$7749 - attribute \src "libresoc.v:154766.3-154767.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:155170.3-155178.6" - wire width 4 $0\prev_wr_go$next[3:0]$7849 - attribute \src "libresoc.v:154776.3-154777.37" - wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:154861.3-154870.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:154952.3-154960.6" - wire width 4 $0\req_l_r_req$next[3:0]$7764 - attribute \src "libresoc.v:154756.3-154757.39" - wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:154943.3-154951.6" - wire width 4 $0\req_l_s_req$next[3:0]$7761 - attribute \src "libresoc.v:154758.3-154759.39" - wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:154880.3-154888.6" - wire $0\rok_l_r_rdok$next[0:0]$7740 - attribute \src "libresoc.v:154772.3-154773.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:154871.3-154879.6" - wire $0\rok_l_s_rdok$next[0:0]$7737 - attribute \src "libresoc.v:154774.3-154775.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:154898.3-154906.6" - wire $0\rst_l_r_rst$next[0:0]$7746 - attribute \src "libresoc.v:154768.3-154769.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:154889.3-154897.6" - wire $0\rst_l_s_rst$next[0:0]$7743 - attribute \src "libresoc.v:154770.3-154771.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:154934.3-154942.6" - wire width 3 $0\src_l_r_src$next[2:0]$7758 - attribute \src "libresoc.v:154760.3-154761.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:154925.3-154933.6" - wire width 3 $0\src_l_s_src$next[2:0]$7755 - attribute \src "libresoc.v:154762.3-154763.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:155082.3-155091.6" - wire width 64 $0\src_r0$next[63:0]$7830 - attribute \src "libresoc.v:154714.3-154715.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:155092.3-155101.6" - wire width 64 $0\src_r1$next[63:0]$7833 - attribute \src "libresoc.v:154712.3-154713.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:155102.3-155111.6" - wire $0\src_r2$next[0:0]$7836 - attribute \src "libresoc.v:154710.3-154711.29" - wire $0\src_r2[0:0] - attribute \src "libresoc.v:154177.7-154177.24" - wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:154187.7-154187.26" - wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:155121.3-155129.6" - wire $1\alu_l_r_alu$next[0:0]$7843 - attribute \src "libresoc.v:154195.7-154195.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire width 13 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7779 - attribute \src "libresoc.v:154217.14-154217.49" - wire width 13 $1\alu_mul0_mul_op__fn_unit[12:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7780 - attribute \src "libresoc.v:154221.14-154221.68" - wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7781 - attribute \src "libresoc.v:154225.7-154225.43" - wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7782 - attribute \src "libresoc.v:154229.14-154229.43" - wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7783 - attribute \src "libresoc.v:154307.13-154307.47" - wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7784 - attribute \src "libresoc.v:154311.7-154311.39" - wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7785 - attribute \src "libresoc.v:154315.7-154315.40" - wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:154961.3-154993.6" - wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7786 - attribute \src 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$not$libresoc.v:145026$7124_Y + attribute \src "libresoc.v:145029.17-145029.92" + wire $not$libresoc.v:145029$7127_Y + attribute \src "libresoc.v:145023.18-145023.98" + wire $or$libresoc.v:145023$7121_Y + attribute \src "libresoc.v:145025.18-145025.99" + wire $or$libresoc.v:145025$7123_Y + attribute \src "libresoc.v:145028.17-145028.97" + wire $or$libresoc.v:145028$7126_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:144987.7-144987.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 22 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \opc_l_s_opc$next - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 3 \oper_i_alu_mul0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \oper_i_alu_mul0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_mul0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 13 \oper_i_alu_mul0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \oper_i_alu_mul0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_alu_mul0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_mul0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_mul0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_mul0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_mul0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_mul0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_mul0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 4 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 4 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire width 4 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire width 4 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire width 4 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 4 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 19 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 20 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 21 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire width 3 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \src_l_r_src + wire output 4 \q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire width 3 \src_l_s_src + wire input 3 \r_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" - wire \src_r2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 30 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:154646$7637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$96 - connect \B \$98 - connect \Y $and$libresoc.v:154646$7637_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:154647$7638 + wire input 2 \s_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:145022$7120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:154647$7638_Y + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:145022$7120_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:154648$7639 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:145027$7125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:154648$7639_Y + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:145027$7125_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:154649$7640 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:145024$7122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:154649$7640_Y + connect \A \q_lsd + connect \Y $not$libresoc.v:145024$7122_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:154650$7641 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:145026$7124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:154650$7641_Y + connect \A \r_lsd + connect \Y $not$libresoc.v:145026$7124_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:154651$7642 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:145029$7127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$2 - connect \B \$4 - connect \Y $and$libresoc.v:154651$7642_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:154652$7643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \req_l_q_req - connect \B { \$102 \$104 \$106 \$108 } - connect \Y $and$libresoc.v:154652$7643_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:154653$7644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$110 - connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:154653$7644_Y + connect \A \r_lsd + connect \Y $not$libresoc.v:145029$7127_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:154654$7645 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:145023$7121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:154654$7645_Y + connect \A \$9 + connect \B \s_lsd + connect \Y $or$libresoc.v:145023$7121_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:154655$7646 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:145025$7123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:154655$7646_Y + connect \A \q_lsd + connect \B \q_int + connect \Y $or$libresoc.v:145025$7123_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:154656$7647 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:145028$7126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:154656$7647_Y + connect \A \$3 + connect \B \s_lsd + connect \Y $or$libresoc.v:145028$7126_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:154657$7648 + attribute \src "libresoc.v:144987.7-144987.20" + process $proc$libresoc.v:144987$7132 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:145009.7-145009.19" + process $proc$libresoc.v:145009$7133 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:145030.3-145031.27" + process $proc$libresoc.v:145030$7128 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:145032.3-145040.6" + process $proc$libresoc.v:145032$7129 + assign { } { } + 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"/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 21 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 13 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 18 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 \dbus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 12 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire \dbus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 17 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 20 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 \dbus__dat_w$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 14 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 16 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 \dbus__sel$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 15 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire \dbus__stb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 19 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire \dbus__we$next + attribute \src "libresoc.v:145049.7-145049.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" + wire width 45 \m_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" + wire width 45 \m_badaddr_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" + wire \m_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" + wire width 64 output 4 \m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" + wire width 64 \m_ld_data_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" + wire \m_load_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" + wire \m_load_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:60" + wire \m_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" + wire \m_store_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" + wire \m_store_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" + wire input 9 \m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" + wire input 11 \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire width 48 input 3 \x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" + wire output 6 \x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" + wire input 7 \x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" + wire width 8 input 2 \x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire width 64 input 5 \x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" + wire input 8 \x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:56" + wire \x_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" + wire input 10 \x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145232$7138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:154657$7648_Y + connect \A \$15 + connect \B \x_valid_i + connect \Y $and$libresoc.v:145232$7138_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:154659$7650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145235$7141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B \$12 - connect \Y $and$libresoc.v:154659$7650_Y + connect \A \$17 + connect \B \$19 + connect \Y $and$libresoc.v:145235$7141_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:154661$7652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145240$7146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B \$16 - connect \Y $and$libresoc.v:154661$7652_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:154662$7653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:154662$7653_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:154664$7655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__rel_o - connect \B \$24 - connect \Y $and$libresoc.v:154664$7655_Y + connect \A \$29 + connect \B \x_valid_i + connect \Y $and$libresoc.v:145240$7146_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:154667$7658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145242$7148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:154667$7658_Y + connect \A \$31 + connect \B \$33 + connect \Y $and$libresoc.v:145242$7148_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:154668$7659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145244$7150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \$22 - connect \Y $and$libresoc.v:154668$7659_Y + connect \A \$1 + connect \B \x_valid_i + connect \Y $and$libresoc.v:145244$7150_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:154673$7664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145248$7154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B \$38 - connect \Y $and$libresoc.v:154673$7664_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:154674$7665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:154674$7665_Y + connect \A \$43 + connect \B \x_valid_i + connect \Y $and$libresoc.v:145248$7154_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:154676$7667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145250$7156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$40 - connect \B \$44 - connect \Y $and$libresoc.v:154676$7667_Y + connect \A \$45 + connect \B \$47 + connect \Y $and$libresoc.v:145250$7156_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:154678$7669 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145256$7162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$48 - connect \B \alu_mul0_n_ready_i - connect \Y $and$libresoc.v:154678$7669_Y + connect \A \$57 + connect \B \x_valid_i + connect \Y $and$libresoc.v:145256$7162_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:154679$7670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145258$7164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$50 - connect \B \alu_mul0_n_valid_o - connect \Y $and$libresoc.v:154679$7670_Y + connect \A \$59 + connect \B \$61 + connect \Y $and$libresoc.v:145258$7164_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:154680$7671 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145260$7166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$52 - connect \B \cu_busy_o - connect \Y $and$libresoc.v:154680$7671_Y + connect \A \$65 + connect \B \x_valid_i + connect \Y $and$libresoc.v:145260$7166_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:154686$7677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145262$7168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_mul0_n_valid_o - connect \B \cu_busy_o - connect \Y $and$libresoc.v:154686$7677_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:154687$7678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:154687$7678_Y + connect \A \$67 + connect \B \$69 + connect \Y $and$libresoc.v:145262$7168_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:154689$7680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145264$7170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:154689$7680_Y + connect \A \$73 + connect \B \x_valid_i + connect \Y $and$libresoc.v:145264$7170_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:154690$7681 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145266$7172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:154690$7681_Y + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:145266$7172_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:154691$7682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $and $and$libresoc.v:145267$7173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \xer_ov_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:154691$7682_Y + connect \A \$75 + connect \B \$77 + connect \Y $and$libresoc.v:145267$7173_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:154692$7683 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + cell $and $and$libresoc.v:145268$7174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \xer_so_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:154692$7683_Y + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $and$libresoc.v:145268$7174_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:154699$7690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + cell $and $and$libresoc.v:145271$7177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_mul0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:154699$7690_Y + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $and$libresoc.v:145271$7177_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:154701$7692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + cell $and $and$libresoc.v:145273$7179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_mul0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:154701$7692_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:154702$7693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:154702$7693_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:154704$7695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$92 - connect \B { 1'1 \$94 1'1 } - connect \Y $and$libresoc.v:154704$7695_Y + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $and$libresoc.v:145273$7179_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:154675$7666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:145229$7135 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$42 - connect \B 1'0 - connect \Y $eq$libresoc.v:154675$7666_Y + connect \A \m_valid_i + connect \Y $not$libresoc.v:145229$7135_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:154677$7668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:145234$7140 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$libresoc.v:154677$7668_Y + connect \A \x_stall_i + connect \Y $not$libresoc.v:145234$7140_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:154658$7649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:145237$7143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$libresoc.v:154658$7649_Y + connect \A \m_valid_i + connect \Y $not$libresoc.v:145237$7143_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:154660$7651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:145241$7147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$libresoc.v:154660$7651_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:154663$7654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:154663$7654_Y + connect \A \x_stall_i + connect \Y $not$libresoc.v:145241$7147_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:154666$7657 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:145245$7151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$23 - connect \Y $not$libresoc.v:154666$7657_Y + connect \A \m_valid_i + connect \Y $not$libresoc.v:145245$7151_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:154672$7663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:145249$7155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_mul0_n_ready_i - connect \Y $not$libresoc.v:154672$7663_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:154683$7674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:154683$7674_Y + connect \A \x_stall_i + connect \Y $not$libresoc.v:145249$7155_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:154703$7694 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:145252$7158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$libresoc.v:154703$7694_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:154705$7696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:154705$7696_Y + connect \A \m_valid_i + connect \Y $not$libresoc.v:145252$7158_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:154671$7662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:145255$7161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$32 - connect \B \$34 - connect \Y $or$libresoc.v:154671$7662_Y + connect \A \x_stall_i + connect \Y $not$libresoc.v:145255$7161_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:154681$7672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:145257$7163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:154681$7672_Y + connect \A \x_stall_i + connect \Y $not$libresoc.v:145257$7163_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:154682$7673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:145261$7167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:154682$7673_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:154684$7675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:154684$7675_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:154685$7676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:154685$7676_Y + connect \A \x_stall_i + connect \Y $not$libresoc.v:145261$7167_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:154688$7679 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:145265$7171 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$libresoc.v:154688$7679_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:145265$7171_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:154694$7685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:145269$7175 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$5 - connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:154694$7685_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$libresoc.v:145269$7175_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:154700$7691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" + cell $not $not$libresoc.v:145270$7176 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$7 - connect \Y $reduce_and$libresoc.v:154700$7691_Y + connect \A \dbus__we + connect \Y $not$libresoc.v:145270$7176_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:154665$7656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:145272$7178 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $reduce_or$libresoc.v:154665$7656_Y + connect \A \m_stall_i + connect \Y $not$libresoc.v:145272$7178_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:154669$7660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:145274$7180 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:154669$7660_Y + connect \A \m_stall_i + connect \Y $not$libresoc.v:145274$7180_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:154670$7661 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:145228$7134 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:154670$7661_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:154693$7684 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:154693$7684_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:154695$7686 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_mul0_mul_op__imm_data__data - connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:154695$7686_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:154696$7687 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:154696$7687_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:154697$7688 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$libresoc.v:154697$7688_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:154698$7689 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:154698$7689_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154782.15-154788.4" - cell \alu_l$107 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154789.12-154819.4" - cell \alu_mul0 \alu_mul0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_mul0_cr_a - connect \cr_a_ok \cr_a_ok - connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit - connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data - connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok - connect \mul_op__insn \alu_mul0_mul_op__insn - connect \mul_op__insn_type \alu_mul0_mul_op__insn_type - connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit - connect \mul_op__is_signed \alu_mul0_mul_op__is_signed - connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe - connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok - connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok - connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc - connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 - connect \n_ready_i \alu_mul0_n_ready_i - connect \n_valid_o \alu_mul0_n_valid_o - connect \o \alu_mul0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_mul0_p_ready_o - connect \p_valid_i \alu_mul0_p_valid_i - connect \ra \alu_mul0_ra - connect \rb \alu_mul0_rb - connect \xer_ov \alu_mul0_xer_ov - connect \xer_ov_ok \xer_ov_ok - connect \xer_so \alu_mul0_xer_so - connect \xer_so$1 \alu_mul0_xer_so$1 - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154820.16-154826.4" - cell \alui_l$106 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154827.15-154833.4" - cell \opc_l$102 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154834.15-154840.4" - cell \req_l$103 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154841.15-154847.4" - cell \rok_l$105 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154848.15-154853.4" - cell \rst_l$104 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154854.15-154860.4" - cell \src_l$101 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "libresoc.v:154053.7-154053.20" - process $proc$libresoc.v:154053$7851 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:154177.7-154177.24" - process $proc$libresoc.v:154177$7852 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:154187.7-154187.26" - process $proc$libresoc.v:154187$7853 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:154195.7-154195.25" - process $proc$libresoc.v:154195$7854 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:154217.14-154217.49" - process $proc$libresoc.v:154217$7855 - assign { } { } - assign $1\alu_mul0_mul_op__fn_unit[12:0] 13'0000000000000 - sync always - sync init - update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[12:0] - end - attribute \src "libresoc.v:154221.14-154221.68" - process $proc$libresoc.v:154221$7856 - assign { } { } - assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:154225.7-154225.43" - process $proc$libresoc.v:154225$7857 - assign { } { } - assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:154229.14-154229.43" - process $proc$libresoc.v:154229$7858 - assign { } { } - assign $1\alu_mul0_mul_op__insn[31:0] 0 - sync always - sync init - update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] - end - attribute \src "libresoc.v:154307.13-154307.47" - process $proc$libresoc.v:154307$7859 - assign { } { } - assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] - end - attribute \src "libresoc.v:154311.7-154311.39" - process $proc$libresoc.v:154311$7860 - assign { } { } - assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] - end - attribute \src "libresoc.v:154315.7-154315.40" - process $proc$libresoc.v:154315$7861 - assign { } { } - assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] - end - attribute \src "libresoc.v:154319.7-154319.37" - process $proc$libresoc.v:154319$7862 - assign { } { } - assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] - end - attribute \src "libresoc.v:154323.7-154323.37" - process $proc$libresoc.v:154323$7863 - assign { } { } - assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:145228$7134_Y end - attribute \src "libresoc.v:154327.7-154327.37" - process $proc$libresoc.v:154327$7864 - assign { } { } - assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:145230$7136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \$11 + connect \Y $or$libresoc.v:145230$7136_Y end - attribute \src "libresoc.v:154331.7-154331.37" - process $proc$libresoc.v:154331$7865 - assign { } { } - assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:145231$7137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:145231$7137_Y end - attribute \src "libresoc.v:154335.7-154335.40" - process $proc$libresoc.v:154335$7866 - assign { } { } - assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:145233$7139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:145233$7139_Y end - attribute \src "libresoc.v:154365.7-154365.27" - process $proc$libresoc.v:154365$7867 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:145236$7142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:145236$7142_Y end - attribute \src "libresoc.v:154399.14-154399.47" - process $proc$libresoc.v:154399$7868 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:145238$7144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:145238$7144_Y end - attribute \src "libresoc.v:154403.7-154403.27" - process $proc$libresoc.v:154403$7869 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:145239$7145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:145239$7145_Y end - attribute \src "libresoc.v:154407.13-154407.33" - process $proc$libresoc.v:154407$7870 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:145243$7149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:145243$7149_Y end - attribute \src "libresoc.v:154411.7-154411.30" - process $proc$libresoc.v:154411$7871 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:145246$7152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:145246$7152_Y end - attribute \src "libresoc.v:154415.13-154415.35" - process $proc$libresoc.v:154415$7872 - assign { } { } - assign $1\data_r2__xer_ov[1:0] 2'00 - sync always - sync init - update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:145247$7153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:145247$7153_Y end - attribute \src "libresoc.v:154419.7-154419.32" - process $proc$libresoc.v:154419$7873 - assign { } { } - assign $1\data_r2__xer_ov_ok[0:0] 1'0 - sync always - sync init - update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:145251$7157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:145251$7157_Y end - attribute \src "libresoc.v:154423.7-154423.29" - process $proc$libresoc.v:154423$7874 - assign { } { } - assign $1\data_r3__xer_so[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so $1\data_r3__xer_so[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:145253$7159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \$53 + connect \Y $or$libresoc.v:145253$7159_Y end - attribute \src "libresoc.v:154427.7-154427.32" - process $proc$libresoc.v:154427$7875 - assign { } { } - assign $1\data_r3__xer_so_ok[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:145254$7160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:145254$7160_Y end - attribute \src "libresoc.v:154447.7-154447.25" - process $proc$libresoc.v:154447$7876 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:145259$7165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:145259$7165_Y end - attribute \src "libresoc.v:154451.7-154451.25" - process $proc$libresoc.v:154451$7877 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:145263$7169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:145263$7169_Y end - attribute \src "libresoc.v:154567.13-154567.30" - process $proc$libresoc.v:154567$7878 - assign { } { } - assign $1\prev_wr_go[3:0] 4'0000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + cell $or $or$libresoc.v:145275$7181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_load_err_o + connect \B \m_store_err_o + connect \Y $or$libresoc.v:145275$7181_Y end - attribute \src "libresoc.v:154575.13-154575.31" - process $proc$libresoc.v:154575$7879 + attribute \src "libresoc.v:145049.7-145049.20" + process $proc$libresoc.v:145049$7248 assign { } { } - assign $1\req_l_r_req[3:0] 4'1111 + assign $0\initial[0:0] 1'0 sync always + update \initial $0\initial[0:0] sync init - update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:154579.13-154579.31" - process $proc$libresoc.v:154579$7880 + attribute \src "libresoc.v:145154.14-145154.42" + process $proc$libresoc.v:145154$7249 assign { } { } - assign $1\req_l_s_req[3:0] 4'0000 + assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init - update \req_l_s_req $1\req_l_s_req[3:0] + update \dbus__adr $1\dbus__adr[44:0] end - attribute \src "libresoc.v:154591.7-154591.26" - process $proc$libresoc.v:154591$7881 + attribute \src "libresoc.v:145159.7-145159.23" + process $proc$libresoc.v:145159$7250 assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 + assign $1\dbus__cyc[0:0] 1'0 sync always sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + update \dbus__cyc $1\dbus__cyc[0:0] end - attribute \src "libresoc.v:154595.7-154595.26" - process $proc$libresoc.v:154595$7882 + attribute \src "libresoc.v:145166.14-145166.48" + process $proc$libresoc.v:145166$7251 assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 + assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + update \dbus__dat_w $1\dbus__dat_w[63:0] end - attribute \src "libresoc.v:154599.7-154599.25" - process $proc$libresoc.v:154599$7883 + attribute \src "libresoc.v:145173.13-145173.30" + process $proc$libresoc.v:145173$7252 assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 + assign $1\dbus__sel[7:0] 8'00000000 sync always sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] + update \dbus__sel $1\dbus__sel[7:0] end - attribute \src "libresoc.v:154603.7-154603.25" - process $proc$libresoc.v:154603$7884 + attribute \src "libresoc.v:145178.7-145178.23" + process $proc$libresoc.v:145178$7253 assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 + assign $1\dbus__stb[0:0] 1'0 sync always sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] + update \dbus__stb $1\dbus__stb[0:0] end - attribute \src "libresoc.v:154617.13-154617.31" - process $proc$libresoc.v:154617$7885 + attribute \src "libresoc.v:145183.7-145183.22" + process $proc$libresoc.v:145183$7254 assign { } { } - assign $1\src_l_r_src[2:0] 3'111 + assign $1\dbus__we[0:0] 1'0 sync always sync init - update \src_l_r_src $1\src_l_r_src[2:0] + update \dbus__we $1\dbus__we[0:0] end - attribute \src "libresoc.v:154621.13-154621.31" - process $proc$libresoc.v:154621$7886 + attribute \src "libresoc.v:145187.14-145187.44" + process $proc$libresoc.v:145187$7255 assign { } { } - assign $1\src_l_s_src[2:0] 3'000 + assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init - update \src_l_s_src $1\src_l_s_src[2:0] + update \m_badaddr_o $1\m_badaddr_o[44:0] end - attribute \src "libresoc.v:154627.14-154627.43" - process $proc$libresoc.v:154627$7887 + attribute \src "libresoc.v:145194.14-145194.48" + process $proc$libresoc.v:145194$7256 assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \src_r0 $1\src_r0[63:0] + update \m_ld_data_o $1\m_ld_data_o[63:0] end - attribute \src "libresoc.v:154631.14-154631.43" - process $proc$libresoc.v:154631$7888 + attribute \src "libresoc.v:145198.7-145198.26" + process $proc$libresoc.v:145198$7257 assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\m_load_err_o[0:0] 1'0 sync always sync init - update \src_r1 $1\src_r1[63:0] + update \m_load_err_o $1\m_load_err_o[0:0] end - attribute \src "libresoc.v:154635.7-154635.20" - process $proc$libresoc.v:154635$7889 + attribute \src "libresoc.v:145204.7-145204.27" + process $proc$libresoc.v:145204$7258 assign { } { } - assign $1\src_r2[0:0] 1'0 + assign $1\m_store_err_o[0:0] 1'0 sync always sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "libresoc.v:154706.3-154707.39" - process $proc$libresoc.v:154706$7697 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:154708.3-154709.43" - process $proc$libresoc.v:154708$7698 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:154710.3-154711.29" - process $proc$libresoc.v:154710$7699 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "libresoc.v:154712.3-154713.29" - process $proc$libresoc.v:154712$7700 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:154714.3-154715.29" - process $proc$libresoc.v:154714$7701 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:154716.3-154717.47" - process $proc$libresoc.v:154716$7702 - assign { } { } - assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next - sync posedge \coresync_clk - update \data_r3__xer_so $0\data_r3__xer_so[0:0] - end - attribute \src "libresoc.v:154718.3-154719.53" - process $proc$libresoc.v:154718$7703 - assign { } { } - assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next - sync posedge \coresync_clk - update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] - end - attribute \src "libresoc.v:154720.3-154721.47" - process $proc$libresoc.v:154720$7704 - assign { } { } - assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next - sync posedge \coresync_clk - update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] - end - attribute \src "libresoc.v:154722.3-154723.53" - process $proc$libresoc.v:154722$7705 - assign { } { } - assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next - sync posedge \coresync_clk - update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:154724.3-154725.43" - process $proc$libresoc.v:154724$7706 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:154726.3-154727.49" - process $proc$libresoc.v:154726$7707 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:154728.3-154729.37" - process $proc$libresoc.v:154728$7708 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "libresoc.v:154730.3-154731.43" - process $proc$libresoc.v:154730$7709 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:154732.3-154733.69" - process $proc$libresoc.v:154732$7710 - assign { } { } - assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] - end - attribute \src "libresoc.v:154734.3-154735.65" - process $proc$libresoc.v:154734$7711 - assign { } { } - assign $0\alu_mul0_mul_op__fn_unit[12:0] \alu_mul0_mul_op__fn_unit$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[12:0] - end - attribute \src "libresoc.v:154736.3-154737.79" - process $proc$libresoc.v:154736$7712 - assign { } { } - assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:154738.3-154739.75" - process $proc$libresoc.v:154738$7713 - assign { } { } - assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:154740.3-154741.63" - process $proc$libresoc.v:154740$7714 - assign { } { } - assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] - end - attribute \src "libresoc.v:154742.3-154743.63" - process $proc$libresoc.v:154742$7715 - assign { } { } - assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] - end - attribute \src "libresoc.v:154744.3-154745.63" - process $proc$libresoc.v:154744$7716 - assign { } { } - assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] - end - attribute \src "libresoc.v:154746.3-154747.63" - process $proc$libresoc.v:154746$7717 - assign { } { } - assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] - end - attribute \src "libresoc.v:154748.3-154749.69" - process $proc$libresoc.v:154748$7718 - assign { } { } - assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] - end - attribute \src "libresoc.v:154750.3-154751.67" - process $proc$libresoc.v:154750$7719 - assign { } { } - assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] - end - attribute \src "libresoc.v:154752.3-154753.69" - process $proc$libresoc.v:154752$7720 - assign { } { } - assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] - end - attribute \src "libresoc.v:154754.3-154755.59" - process $proc$libresoc.v:154754$7721 - assign { } { } - assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] - end - attribute \src "libresoc.v:154756.3-154757.39" - process $proc$libresoc.v:154756$7722 - assign { } { } - assign $0\req_l_r_req[3:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[3:0] - end - attribute \src "libresoc.v:154758.3-154759.39" - process $proc$libresoc.v:154758$7723 - assign { } { } - assign $0\req_l_s_req[3:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[3:0] - end - attribute \src "libresoc.v:154760.3-154761.39" - process $proc$libresoc.v:154760$7724 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] + update \m_store_err_o $1\m_store_err_o[0:0] end - attribute \src "libresoc.v:154762.3-154763.39" - process $proc$libresoc.v:154762$7725 + attribute \src "libresoc.v:145276.3-145277.39" + process $proc$libresoc.v:145276$7182 assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next + assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] + update \m_badaddr_o $0\m_badaddr_o[44:0] end - attribute \src "libresoc.v:154764.3-154765.39" - process $proc$libresoc.v:154764$7726 + attribute \src "libresoc.v:145278.3-145279.43" + process $proc$libresoc.v:145278$7183 assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] + update \m_store_err_o $0\m_store_err_o[0:0] end - attribute \src "libresoc.v:154766.3-154767.39" - process $proc$libresoc.v:154766$7727 + attribute \src "libresoc.v:145280.3-145281.41" + process $proc$libresoc.v:145280$7184 assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] + update \m_load_err_o $0\m_load_err_o[0:0] end - attribute \src "libresoc.v:154768.3-154769.39" - process $proc$libresoc.v:154768$7728 + attribute \src "libresoc.v:145282.3-145283.39" + process $proc$libresoc.v:145282$7185 assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] + update \dbus__dat_w $0\dbus__dat_w[63:0] end - attribute \src "libresoc.v:154770.3-154771.39" - process $proc$libresoc.v:154770$7729 + attribute \src "libresoc.v:145284.3-145285.33" + process $proc$libresoc.v:145284$7186 assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] + update \dbus__we $0\dbus__we[0:0] end - attribute \src "libresoc.v:154772.3-154773.41" - process $proc$libresoc.v:154772$7730 + attribute \src "libresoc.v:145286.3-145287.35" + process $proc$libresoc.v:145286$7187 assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + update \dbus__adr $0\dbus__adr[44:0] end - attribute \src "libresoc.v:154774.3-154775.41" - process $proc$libresoc.v:154774$7731 + attribute \src "libresoc.v:145288.3-145289.39" + process $proc$libresoc.v:145288$7188 assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + update \m_ld_data_o $0\m_ld_data_o[63:0] end - attribute \src "libresoc.v:154776.3-154777.37" - process $proc$libresoc.v:154776$7732 + attribute \src "libresoc.v:145290.3-145291.35" + process $proc$libresoc.v:145290$7189 assign { } { } - assign $0\prev_wr_go[3:0] \prev_wr_go$next + assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[3:0] + update \dbus__sel $0\dbus__sel[7:0] end - attribute \src "libresoc.v:154778.3-154779.40" - process $proc$libresoc.v:154778$7733 + attribute \src "libresoc.v:145292.3-145293.35" + process $proc$libresoc.v:145292$7190 assign { } { } - assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o + assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] + update \dbus__stb $0\dbus__stb[0:0] end - attribute \src "libresoc.v:154780.3-154781.25" - process $proc$libresoc.v:154780$7734 + attribute \src "libresoc.v:145294.3-145295.35" + process $proc$libresoc.v:145294$7191 assign { } { } - assign $0\all_rd_dly[0:0] \$10 + assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] + update \dbus__cyc $0\dbus__cyc[0:0] end - attribute \src "libresoc.v:154861.3-154870.6" - process $proc$libresoc.v:154861$7735 + attribute \src "libresoc.v:145296.3-145323.6" + process $proc$libresoc.v:145296$7192 assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:154862.5-154862.29" - switch \initial - attribute \src "libresoc.v:154862.9-154862.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$54 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$46 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "libresoc.v:154871.3-154879.6" - process $proc$libresoc.v:154871$7736 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$7737 $1\rok_l_s_rdok$next[0:0]$7738 - attribute \src "libresoc.v:154872.5-154872.29" + assign $0\dbus__cyc$next[0:0]$7193 $4\dbus__cyc$next[0:0]$7197 + attribute \src "libresoc.v:145297.5-145297.29" switch \initial - attribute \src "libresoc.v:154872.9-154872.17" + attribute \src "libresoc.v:145297.9-145297.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$7738 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$7738 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7737 - end - attribute \src "libresoc.v:154880.3-154888.6" - process $proc$libresoc.v:154880$7739 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$7740 $1\rok_l_r_rdok$next[0:0]$7741 - attribute \src "libresoc.v:154881.5-154881.29" - switch \initial - attribute \src "libresoc.v:154881.9-154881.17" - case 1'1 + assign $1\dbus__cyc$next[0:0]$7194 $2\dbus__cyc$next[0:0]$7195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$7 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__cyc$next[0:0]$7195 $3\dbus__cyc$next[0:0]$7196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__cyc$next[0:0]$7196 1'0 + case + assign $3\dbus__cyc$next[0:0]$7196 \dbus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__cyc$next[0:0]$7195 1'1 + case + assign $2\dbus__cyc$next[0:0]$7195 \dbus__cyc + end case + assign $1\dbus__cyc$next[0:0]$7194 \dbus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$7741 1'1 + assign $4\dbus__cyc$next[0:0]$7197 1'0 case - assign $1\rok_l_r_rdok$next[0:0]$7741 \$64 + assign $4\dbus__cyc$next[0:0]$7197 $1\dbus__cyc$next[0:0]$7194 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7740 + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7193 end - attribute \src "libresoc.v:154889.3-154897.6" - process $proc$libresoc.v:154889$7742 - assign { } { } + attribute \src "libresoc.v:145324.3-145351.6" + process $proc$libresoc.v:145324$7198 assign { } { } - assign $0\rst_l_s_rst$next[0:0]$7743 $1\rst_l_s_rst$next[0:0]$7744 - attribute \src "libresoc.v:154890.5-154890.29" - switch \initial - attribute \src "libresoc.v:154890.9-154890.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$7744 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$7744 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7743 - end - attribute \src "libresoc.v:154898.3-154906.6" - process $proc$libresoc.v:154898$7745 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$7746 $1\rst_l_r_rst$next[0:0]$7747 - attribute \src "libresoc.v:154899.5-154899.29" + assign $0\dbus__stb$next[0:0]$7199 $4\dbus__stb$next[0:0]$7203 + attribute \src "libresoc.v:145325.5-145325.29" switch \initial - attribute \src "libresoc.v:154899.9-154899.17" + attribute \src "libresoc.v:145325.9-145325.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$7747 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$7747 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7746 - end - attribute \src "libresoc.v:154907.3-154915.6" - process $proc$libresoc.v:154907$7748 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$7749 $1\opc_l_s_opc$next[0:0]$7750 - attribute \src "libresoc.v:154908.5-154908.29" - switch \initial - attribute \src "libresoc.v:154908.9-154908.17" - case 1'1 + assign $1\dbus__stb$next[0:0]$7200 $2\dbus__stb$next[0:0]$7201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$21 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__stb$next[0:0]$7201 $3\dbus__stb$next[0:0]$7202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__stb$next[0:0]$7202 1'0 + case + assign $3\dbus__stb$next[0:0]$7202 \dbus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__stb$next[0:0]$7201 1'1 + case + assign $2\dbus__stb$next[0:0]$7201 \dbus__stb + end case + assign $1\dbus__stb$next[0:0]$7200 \dbus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$7750 1'0 + assign $4\dbus__stb$next[0:0]$7203 1'0 case - assign $1\opc_l_s_opc$next[0:0]$7750 \cu_issue_i + assign $4\dbus__stb$next[0:0]$7203 $1\dbus__stb$next[0:0]$7200 end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7749 + update \dbus__stb$next $0\dbus__stb$next[0:0]$7199 end - attribute \src "libresoc.v:154916.3-154924.6" - process $proc$libresoc.v:154916$7751 + attribute \src "libresoc.v:145352.3-145361.6" + process $proc$libresoc.v:145352$7204 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$7752 $1\opc_l_r_opc$next[0:0]$7753 - attribute \src "libresoc.v:154917.5-154917.29" + assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] + attribute \src "libresoc.v:145353.5-145353.29" switch \initial - attribute \src "libresoc.v:154917.9-154917.17" + attribute \src "libresoc.v:145353.9-145353.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$7753 1'1 + assign $1\x_busy_o[0:0] \dbus__cyc case - assign $1\opc_l_r_opc$next[0:0]$7753 \req_done + assign $1\x_busy_o[0:0] 1'0 end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7752 + update \x_busy_o $0\x_busy_o[0:0] end - attribute \src "libresoc.v:154925.3-154933.6" - process $proc$libresoc.v:154925$7754 + attribute \src "libresoc.v:145362.3-145379.6" + process $proc$libresoc.v:145362$7205 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$7755 $1\src_l_s_src$next[2:0]$7756 - attribute \src "libresoc.v:154926.5-154926.29" + assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] + attribute \src "libresoc.v:145363.5-145363.29" switch \initial - attribute \src "libresoc.v:154926.9-154926.17" + attribute \src "libresoc.v:145363.9-145363.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$7756 3'000 + assign $1\m_busy_o[0:0] $2\m_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\m_busy_o[0:0] \dbus__cyc + end case - assign $1\src_l_s_src$next[2:0]$7756 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\m_busy_o[0:0] 1'0 end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7755 + update \m_busy_o $0\m_busy_o[0:0] end - attribute \src "libresoc.v:154934.3-154942.6" - process $proc$libresoc.v:154934$7757 - assign { } { } + attribute \src "libresoc.v:145380.3-145410.6" + process $proc$libresoc.v:145380$7206 assign { } { } - assign $0\src_l_r_src$next[2:0]$7758 $1\src_l_r_src$next[2:0]$7759 - attribute \src "libresoc.v:154935.5-154935.29" - switch \initial - attribute \src "libresoc.v:154935.9-154935.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$7759 3'111 - case - assign $1\src_l_r_src$next[2:0]$7759 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7758 - end - attribute \src "libresoc.v:154943.3-154951.6" - process $proc$libresoc.v:154943$7760 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$7761 $1\req_l_s_req$next[3:0]$7762 - attribute \src "libresoc.v:154944.5-154944.29" + assign $0\dbus__sel$next[7:0]$7207 $4\dbus__sel$next[7:0]$7211 + attribute \src "libresoc.v:145381.5-145381.29" switch \initial - attribute \src "libresoc.v:154944.9-154944.17" + attribute \src "libresoc.v:145381.9-145381.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$7762 4'0000 - case - assign $1\req_l_s_req$next[3:0]$7762 \$66 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7761 - end - attribute \src "libresoc.v:154952.3-154960.6" - process $proc$libresoc.v:154952$7763 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[3:0]$7764 $1\req_l_r_req$next[3:0]$7765 - attribute \src "libresoc.v:154953.5-154953.29" - switch \initial - attribute \src "libresoc.v:154953.9-154953.17" - case 1'1 + assign $1\dbus__sel$next[7:0]$7208 $2\dbus__sel$next[7:0]$7209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$35 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__sel$next[7:0]$7209 $3\dbus__sel$next[7:0]$7210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__sel$next[7:0]$7210 8'00000000 + case + assign $3\dbus__sel$next[7:0]$7210 \dbus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__sel$next[7:0]$7209 \x_mask_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__sel$next[7:0]$7209 8'00000000 + end case + assign $1\dbus__sel$next[7:0]$7208 \dbus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$7765 4'1111 + assign $4\dbus__sel$next[7:0]$7211 8'00000000 case - assign $1\req_l_r_req$next[3:0]$7765 \$68 + assign $4\dbus__sel$next[7:0]$7211 $1\dbus__sel$next[7:0]$7208 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7764 + update \dbus__sel$next $0\dbus__sel$next[7:0]$7207 end - attribute \src "libresoc.v:154961.3-154993.6" - process $proc$libresoc.v:154961$7766 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_mul0_mul_op__fn_unit$next[12:0]$7767 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7779 - assign { } { } - assign { } { } - assign $0\alu_mul0_mul_op__insn$next[31:0]$7770 $1\alu_mul0_mul_op__insn$next[31:0]$7782 - assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7771 $1\alu_mul0_mul_op__insn_type$next[6:0]$7783 - assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7772 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7784 - assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7773 $1\alu_mul0_mul_op__is_signed$next[0:0]$7785 + attribute \src "libresoc.v:145411.3-145435.6" + process $proc$libresoc.v:145411$7212 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7778 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7790 - assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7791 - assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7792 - assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7774 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7793 - assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7775 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7794 - assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7776 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7795 - assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7777 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7796 - attribute \src "libresoc.v:154962.5-154962.29" + assign $0\m_ld_data_o$next[63:0]$7213 $4\m_ld_data_o$next[63:0]$7217 + attribute \src "libresoc.v:145412.5-145412.29" switch \initial - attribute \src "libresoc.v:154962.9-154962.17" + attribute \src "libresoc.v:145412.9-145412.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_mul0_mul_op__insn$next[31:0]$7782 $1\alu_mul0_mul_op__is_signed$next[0:0]$7785 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7784 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7790 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7787 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7786 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7788 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7789 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7781 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7780 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7779 $1\alu_mul0_mul_op__insn_type$next[6:0]$7783 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + assign $1\m_ld_data_o$next[63:0]$7214 $2\m_ld_data_o$next[63:0]$7215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$49 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_ld_data_o$next[63:0]$7215 $3\m_ld_data_o$next[63:0]$7216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_ld_data_o$next[63:0]$7216 \dbus__dat_r + case + assign $3\m_ld_data_o$next[63:0]$7216 \m_ld_data_o + end + case + assign $2\m_ld_data_o$next[63:0]$7215 \m_ld_data_o + end case - assign $1\alu_mul0_mul_op__fn_unit$next[12:0]$7779 \alu_mul0_mul_op__fn_unit - assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7780 \alu_mul0_mul_op__imm_data__data - assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7781 \alu_mul0_mul_op__imm_data__ok - assign $1\alu_mul0_mul_op__insn$next[31:0]$7782 \alu_mul0_mul_op__insn - assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7783 \alu_mul0_mul_op__insn_type - assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7784 \alu_mul0_mul_op__is_32bit - assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7785 \alu_mul0_mul_op__is_signed - assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7786 \alu_mul0_mul_op__oe__oe - assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7787 \alu_mul0_mul_op__oe__ok - assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7788 \alu_mul0_mul_op__rc__ok - assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7789 \alu_mul0_mul_op__rc__rc - assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7790 \alu_mul0_mul_op__write_cr0 + assign $1\m_ld_data_o$next[63:0]$7214 \m_ld_data_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7791 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7792 1'0 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7796 1'0 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7795 1'0 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7793 1'0 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7794 1'0 + assign $4\m_ld_data_o$next[63:0]$7217 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7791 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7780 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7792 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7781 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7793 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7786 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7794 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7787 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7795 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7788 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7796 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7789 + assign $4\m_ld_data_o$next[63:0]$7217 $1\m_ld_data_o$next[63:0]$7214 end sync always - update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[12:0]$7767 - update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 - update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 - update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7770 - update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7771 - update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7772 - update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7773 - update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7774 - update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7775 - update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7776 - update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7777 - update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7778 + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7213 end - attribute \src "libresoc.v:154994.3-155015.6" - process $proc$libresoc.v:154994$7797 - assign { } { } + attribute \src "libresoc.v:145436.3-145461.6" + process $proc$libresoc.v:145436$7218 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$7798 $2\data_r0__o$next[63:0]$7802 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$7799 $3\data_r0__o_ok$next[0:0]$7804 - attribute \src "libresoc.v:154995.5-154995.29" + assign $0\dbus__adr$next[44:0]$7219 $3\dbus__adr$next[44:0]$7222 + attribute \src "libresoc.v:145437.5-145437.29" switch \initial - attribute \src "libresoc.v:154995.9-154995.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:145437.9-145437.17" case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$7801 $1\data_r0__o$next[63:0]$7800 } { \o_ok \alu_mul0_o } case - assign $1\data_r0__o$next[63:0]$7800 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$7801 \data_r0__o_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$7803 $2\data_r0__o$next[63:0]$7802 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbus__adr$next[44:0]$7220 $2\dbus__adr$next[44:0]$7221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$63 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__adr$next[44:0]$7221 \dbus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__adr$next[44:0]$7221 \x_addr_i [47:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__adr$next[44:0]$7221 45'000000000000000000000000000000000000000000000 + end case - assign $2\data_r0__o$next[63:0]$7802 $1\data_r0__o$next[63:0]$7800 - assign $2\data_r0__o_ok$next[0:0]$7803 $1\data_r0__o_ok$next[0:0]$7801 + assign $1\dbus__adr$next[44:0]$7220 \dbus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$7804 1'0 + assign $3\dbus__adr$next[44:0]$7222 45'000000000000000000000000000000000000000000000 case - assign $3\data_r0__o_ok$next[0:0]$7804 $2\data_r0__o_ok$next[0:0]$7803 + assign $3\dbus__adr$next[44:0]$7222 $1\dbus__adr$next[44:0]$7220 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$7798 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7799 + update \dbus__adr$next $0\dbus__adr$next[44:0]$7219 end - attribute \src "libresoc.v:155016.3-155037.6" - process $proc$libresoc.v:155016$7805 - assign { } { } + attribute \src "libresoc.v:145462.3-145487.6" + process $proc$libresoc.v:145462$7223 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$7806 $2\data_r1__cr_a$next[3:0]$7810 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$7807 $3\data_r1__cr_a_ok$next[0:0]$7812 - attribute \src "libresoc.v:155017.5-155017.29" + assign $0\dbus__we$next[0:0]$7224 $3\dbus__we$next[0:0]$7227 + attribute \src "libresoc.v:145463.5-145463.29" switch \initial - attribute \src "libresoc.v:155017.9-155017.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:145463.9-145463.17" case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$7809 $1\data_r1__cr_a$next[3:0]$7808 } { \cr_a_ok \alu_mul0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$7808 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$7809 \data_r1__cr_a_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$7811 $2\data_r1__cr_a$next[3:0]$7810 } 5'00000 + assign $1\dbus__we$next[0:0]$7225 $2\dbus__we$next[0:0]$7226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$71 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__we$next[0:0]$7226 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__we$next[0:0]$7226 \x_st_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__we$next[0:0]$7226 1'0 + end case - assign $2\data_r1__cr_a$next[3:0]$7810 $1\data_r1__cr_a$next[3:0]$7808 - assign $2\data_r1__cr_a_ok$next[0:0]$7811 $1\data_r1__cr_a_ok$next[0:0]$7809 + assign $1\dbus__we$next[0:0]$7225 \dbus__we end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$7812 1'0 + assign $3\dbus__we$next[0:0]$7227 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$7812 $2\data_r1__cr_a_ok$next[0:0]$7811 + assign $3\dbus__we$next[0:0]$7227 $1\dbus__we$next[0:0]$7225 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7806 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7807 + update \dbus__we$next $0\dbus__we$next[0:0]$7224 end - attribute \src "libresoc.v:155038.3-155059.6" - process $proc$libresoc.v:155038$7813 - assign { } { } + attribute \src "libresoc.v:145488.3-145513.6" + process $proc$libresoc.v:145488$7228 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$7814 $2\data_r2__xer_ov$next[1:0]$7818 - assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$7815 $3\data_r2__xer_ov_ok$next[0:0]$7820 - attribute \src "libresoc.v:155039.5-155039.29" + assign $0\dbus__dat_w$next[63:0]$7229 $3\dbus__dat_w$next[63:0]$7232 + attribute \src "libresoc.v:145489.5-145489.29" switch \initial - attribute \src "libresoc.v:155039.9-155039.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:145489.9-145489.17" case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$7817 $1\data_r2__xer_ov$next[1:0]$7816 } { \xer_ov_ok \alu_mul0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$7816 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$7817 \data_r2__xer_ov_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$7819 $2\data_r2__xer_ov$next[1:0]$7818 } 3'000 + assign $1\dbus__dat_w$next[63:0]$7230 $2\dbus__dat_w$next[63:0]$7231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$79 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__dat_w$next[63:0]$7231 \dbus__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__dat_w$next[63:0]$7231 \x_st_data_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__dat_w$next[63:0]$7231 64'0000000000000000000000000000000000000000000000000000000000000000 + end case - assign $2\data_r2__xer_ov$next[1:0]$7818 $1\data_r2__xer_ov$next[1:0]$7816 - assign $2\data_r2__xer_ov_ok$next[0:0]$7819 $1\data_r2__xer_ov_ok$next[0:0]$7817 + assign $1\dbus__dat_w$next[63:0]$7230 \dbus__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$7820 1'0 + assign $3\dbus__dat_w$next[63:0]$7232 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\data_r2__xer_ov_ok$next[0:0]$7820 $2\data_r2__xer_ov_ok$next[0:0]$7819 + assign $3\dbus__dat_w$next[63:0]$7232 $1\dbus__dat_w$next[63:0]$7230 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7814 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7815 + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7229 end - attribute \src "libresoc.v:155060.3-155081.6" - process $proc$libresoc.v:155060$7821 - assign { } { } + attribute \src "libresoc.v:145514.3-145536.6" + process $proc$libresoc.v:145514$7233 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\data_r3__xer_so$next[0:0]$7822 $2\data_r3__xer_so$next[0:0]$7826 - assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$7823 $3\data_r3__xer_so_ok$next[0:0]$7828 - attribute \src "libresoc.v:155061.5-155061.29" + assign $0\m_load_err_o$next[0:0]$7234 $3\m_load_err_o$next[0:0]$7237 + attribute \src "libresoc.v:145515.5-145515.29" switch \initial - attribute \src "libresoc.v:155061.9-155061.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:145515.9-145515.17" case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$7825 $1\data_r3__xer_so$next[0:0]$7824 } { \xer_so_ok \alu_mul0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$7824 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$7825 \data_r3__xer_so_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$7827 $2\data_r3__xer_so$next[0:0]$7826 } 2'00 + assign $1\m_load_err_o$next[0:0]$7235 $2\m_load_err_o$next[0:0]$7236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_load_err_o$next[0:0]$7236 \$85 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\m_load_err_o$next[0:0]$7236 1'0 + case + assign $2\m_load_err_o$next[0:0]$7236 \m_load_err_o + end case - assign $2\data_r3__xer_so$next[0:0]$7826 $1\data_r3__xer_so$next[0:0]$7824 - assign $2\data_r3__xer_so_ok$next[0:0]$7827 $1\data_r3__xer_so_ok$next[0:0]$7825 + assign $1\m_load_err_o$next[0:0]$7235 \m_load_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$7828 1'0 - case - assign $3\data_r3__xer_so_ok$next[0:0]$7828 $2\data_r3__xer_so_ok$next[0:0]$7827 - end - sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7822 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7823 - end - attribute \src "libresoc.v:155082.3-155091.6" - process $proc$libresoc.v:155082$7829 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$7830 $1\src_r0$next[63:0]$7831 - attribute \src "libresoc.v:155083.5-155083.29" - switch \initial - attribute \src "libresoc.v:155083.9-155083.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \src_l_q_src [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$7831 \src1_i - case - assign $1\src_r0$next[63:0]$7831 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$7830 - end - attribute \src "libresoc.v:155092.3-155101.6" - process $proc$libresoc.v:155092$7832 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$7833 $1\src_r1$next[63:0]$7834 - attribute \src "libresoc.v:155093.5-155093.29" - switch \initial - attribute \src "libresoc.v:155093.9-155093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \src_sel - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$7834 \src_or_imm + assign $3\m_load_err_o$next[0:0]$7237 1'0 case - assign $1\src_r1$next[63:0]$7834 \src_r1 + assign $3\m_load_err_o$next[0:0]$7237 $1\m_load_err_o$next[0:0]$7235 end sync always - update \src_r1$next $0\src_r1$next[63:0]$7833 + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7234 end - attribute \src "libresoc.v:155102.3-155111.6" - process $proc$libresoc.v:155102$7835 + attribute \src "libresoc.v:145537.3-145559.6" + process $proc$libresoc.v:145537$7238 assign { } { } - assign { } { } - assign $0\src_r2$next[0:0]$7836 $1\src_r2$next[0:0]$7837 - attribute \src "libresoc.v:155103.5-155103.29" - switch \initial - attribute \src "libresoc.v:155103.9-155103.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" - switch \src_l_q_src [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[0:0]$7837 \src3_i - case - assign $1\src_r2$next[0:0]$7837 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[0:0]$7836 - end - attribute \src "libresoc.v:155112.3-155120.6" - process $proc$libresoc.v:155112$7838 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$7839 $1\alui_l_r_alui$next[0:0]$7840 - attribute \src "libresoc.v:155113.5-155113.29" + assign $0\m_store_err_o$next[0:0]$7239 $3\m_store_err_o$next[0:0]$7242 + attribute \src "libresoc.v:145538.5-145538.29" switch \initial - attribute \src "libresoc.v:155113.9-155113.17" + attribute \src "libresoc.v:145538.9-145538.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$7840 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$7840 \$88 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7839 - end - attribute \src "libresoc.v:155121.3-155129.6" - process $proc$libresoc.v:155121$7841 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$7842 $1\alu_l_r_alu$next[0:0]$7843 - attribute \src "libresoc.v:155122.5-155122.29" - switch \initial - attribute \src "libresoc.v:155122.9-155122.17" - case 1'1 + assign $1\m_store_err_o$next[0:0]$7240 $2\m_store_err_o$next[0:0]$7241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$89 \$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_store_err_o$next[0:0]$7241 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\m_store_err_o$next[0:0]$7241 1'0 + case + assign $2\m_store_err_o$next[0:0]$7241 \m_store_err_o + end case + assign $1\m_store_err_o$next[0:0]$7240 \m_store_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$7843 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$7843 \$90 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7842 - end - attribute \src "libresoc.v:155130.3-155139.6" - process $proc$libresoc.v:155130$7844 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:155131.5-155131.29" - switch \initial - attribute \src "libresoc.v:155131.9-155131.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$114 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:155140.3-155149.6" - process $proc$libresoc.v:155140$7845 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:155141.5-155141.29" - switch \initial - attribute \src "libresoc.v:155141.9-155141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$116 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a + assign $3\m_store_err_o$next[0:0]$7242 1'0 case - assign $1\dest2_o[3:0] 4'0000 + assign $3\m_store_err_o$next[0:0]$7242 $1\m_store_err_o$next[0:0]$7240 end sync always - update \dest2_o $0\dest2_o[3:0] + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7239 end - attribute \src "libresoc.v:155150.3-155159.6" - process $proc$libresoc.v:155150$7846 + attribute \src "libresoc.v:145560.3-145579.6" + process $proc$libresoc.v:145560$7243 assign { } { } - assign { } { } - assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:155151.5-155151.29" - switch \initial - attribute \src "libresoc.v:155151.9-155151.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$118 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[1:0] \data_r2__xer_ov - case - assign $1\dest3_o[1:0] 2'00 - end - sync always - update \dest3_o $0\dest3_o[1:0] - end - attribute \src "libresoc.v:155160.3-155169.6" - process $proc$libresoc.v:155160$7847 assign { } { } assign { } { } - assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:155161.5-155161.29" + assign $0\m_badaddr_o$next[44:0]$7244 $3\m_badaddr_o$next[44:0]$7247 + attribute \src "libresoc.v:145561.5-145561.29" switch \initial - attribute \src "libresoc.v:155161.9-155161.17" + attribute \src "libresoc.v:145561.9-145561.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dest4_o[0:0] \data_r3__xer_so - case - assign $1\dest4_o[0:0] 1'0 - end - sync always - update \dest4_o $0\dest4_o[0:0] - end - attribute \src "libresoc.v:155170.3-155178.6" - process $proc$libresoc.v:155170$7848 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[3:0]$7849 $1\prev_wr_go$next[3:0]$7850 - attribute \src "libresoc.v:155171.5-155171.29" - switch \initial - attribute \src "libresoc.v:155171.9-155171.17" - case 1'1 + assign $1\m_badaddr_o$next[44:0]$7245 $2\m_badaddr_o$next[44:0]$7246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$93 \$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_badaddr_o$next[44:0]$7246 \dbus__adr + case + assign $2\m_badaddr_o$next[44:0]$7246 \m_badaddr_o + end case + assign $1\m_badaddr_o$next[44:0]$7245 \m_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$7850 4'0000 - case - assign $1\prev_wr_go$next[3:0]$7850 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7849 - end - connect \$100 $and$libresoc.v:154646$7637_Y - connect \$102 $and$libresoc.v:154647$7638_Y - connect \$104 $and$libresoc.v:154648$7639_Y - connect \$106 $and$libresoc.v:154649$7640_Y - connect \$108 $and$libresoc.v:154650$7641_Y - connect \$10 $and$libresoc.v:154651$7642_Y - connect \$110 $and$libresoc.v:154652$7643_Y - connect \$112 $and$libresoc.v:154653$7644_Y - connect \$114 $and$libresoc.v:154654$7645_Y - connect \$116 $and$libresoc.v:154655$7646_Y - connect \$118 $and$libresoc.v:154656$7647_Y - connect \$120 $and$libresoc.v:154657$7648_Y - connect \$12 $not$libresoc.v:154658$7649_Y - connect \$14 $and$libresoc.v:154659$7650_Y - connect \$16 $not$libresoc.v:154660$7651_Y - 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- connect \$5 $not$libresoc.v:154683$7674_Y - connect \$60 $or$libresoc.v:154684$7675_Y - connect \$62 $or$libresoc.v:154685$7676_Y - connect \$64 $and$libresoc.v:154686$7677_Y - connect \$66 $and$libresoc.v:154687$7678_Y - connect \$68 $or$libresoc.v:154688$7679_Y - connect \$70 $and$libresoc.v:154689$7680_Y - connect \$72 $and$libresoc.v:154690$7681_Y - connect \$74 $and$libresoc.v:154691$7682_Y - connect \$76 $and$libresoc.v:154692$7683_Y - connect \$78 $ternary$libresoc.v:154693$7684_Y - connect \$7 $or$libresoc.v:154694$7685_Y - connect \$80 $ternary$libresoc.v:154695$7686_Y - connect \$82 $ternary$libresoc.v:154696$7687_Y - connect \$84 $ternary$libresoc.v:154697$7688_Y - connect \$86 $ternary$libresoc.v:154698$7689_Y - connect \$88 $and$libresoc.v:154699$7690_Y - connect \$4 $reduce_and$libresoc.v:154700$7691_Y - connect \$90 $and$libresoc.v:154701$7692_Y - connect \$92 $and$libresoc.v:154702$7693_Y - connect \$94 $not$libresoc.v:154703$7694_Y - connect \$96 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$or$libresoc.v:145243$7149_Y + connect \$3 $and$libresoc.v:145244$7150_Y + connect \$39 $not$libresoc.v:145245$7151_Y + connect \$41 $or$libresoc.v:145246$7152_Y + connect \$43 $or$libresoc.v:145247$7153_Y + connect \$45 $and$libresoc.v:145248$7154_Y + connect \$47 $not$libresoc.v:145249$7155_Y + connect \$49 $and$libresoc.v:145250$7156_Y + connect \$51 $or$libresoc.v:145251$7157_Y + connect \$53 $not$libresoc.v:145252$7158_Y + connect \$55 $or$libresoc.v:145253$7159_Y + connect \$57 $or$libresoc.v:145254$7160_Y + connect \$5 $not$libresoc.v:145255$7161_Y + connect \$59 $and$libresoc.v:145256$7162_Y + connect \$61 $not$libresoc.v:145257$7163_Y + connect \$63 $and$libresoc.v:145258$7164_Y + connect \$65 $or$libresoc.v:145259$7165_Y + connect \$67 $and$libresoc.v:145260$7166_Y + connect \$69 $not$libresoc.v:145261$7167_Y + connect \$71 $and$libresoc.v:145262$7168_Y + connect \$73 $or$libresoc.v:145263$7169_Y + connect \$75 $and$libresoc.v:145264$7170_Y + connect \$77 $not$libresoc.v:145265$7171_Y + connect \$7 $and$libresoc.v:145266$7172_Y + connect \$79 $and$libresoc.v:145267$7173_Y + connect \$81 $and$libresoc.v:145268$7174_Y + connect \$83 $not$libresoc.v:145269$7175_Y + connect \$85 $not$libresoc.v:145270$7176_Y + connect \$87 $and$libresoc.v:145271$7177_Y + connect \$89 $not$libresoc.v:145272$7178_Y + connect \$91 $and$libresoc.v:145273$7179_Y + connect \$93 $not$libresoc.v:145274$7180_Y + connect \$95 $or$libresoc.v:145275$7181_Y + connect \x_stall_i 1'0 + connect \m_stall_i 1'0 end -attribute \src "libresoc.v:155213.1-155542.10" +attribute \src "libresoc.v:145586.1-146543.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" -module \mul1 - attribute \src "libresoc.v:155509.18-155509.116" - wire $and$libresoc.v:155509$7891_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -322594,7 +305868,7 @@ module \mul1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \mul_op__fn_unit + wire width 13 input 2 \alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -322610,19 +305884,31 @@ module \mul1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 18 \mul_op__fn_unit$3 + wire width 13 output 25 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data + wire width 64 input 3 \alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__data$4 + wire width 64 output 26 \alu_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \mul_op__imm_data__ok + wire input 4 \alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \mul_op__imm_data__ok$5 + wire output 27 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 28 \mul_op__insn$13 + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -322698,7 +305984,7 @@ module \mul1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type + wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -322774,1390 +306060,1665 @@ module \mul1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \mul_op__insn_type$2 + wire width 7 output 24 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__is_32bit + wire input 9 \alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \mul_op__is_32bit$11 + wire output 32 \alu_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__is_signed + wire input 11 \alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__is_signed$12 + wire output 34 \alu_op__invert_out$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \mul_op__oe__oe + wire input 15 \alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__oe__oe$8 + wire output 38 \alu_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__oe__ok + wire input 16 \alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \mul_op__oe__ok$9 + wire output 39 \alu_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \mul_op__rc__ok + wire input 7 \alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 22 \mul_op__rc__ok$7 + wire output 30 \alu_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc + wire input 8 \alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \mul_op__rc__rc$6 + wire output 31 \alu_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 + wire input 14 \alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \mul_op__write_cr0$10 + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" + wire width 64 \b_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:150" + wire width 2 \ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" + wire \carry_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" + wire \carry_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 44 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 8 \eqs + attribute \src "libresoc.v:145587.7-145587.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:104" + wire \msb_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + wire \msb_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 34 \muxid + wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire output 32 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire output 33 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 29 \ra$14 + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 42 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" + wire width 2 \ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 30 \rb$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" - wire \sign32_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" - wire \sign32_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" - wire \sign_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" - wire \sign_b + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" + wire width 8 \src1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" + wire width 5 \tval attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 15 \xer_so + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 46 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 31 \xer_so$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$libresoc.v:155509$7891 + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 50 \xer_so$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" + wire \zerohi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" + wire \zerolo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" + cell $add $add$libresoc.v:146080$7295 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 66 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$17 - connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:155509$7891_Y + parameter \B_WIDTH 66 + parameter \Y_WIDTH 67 + connect \A \add_a + connect \B \add_b + connect \Y $add$libresoc.v:146080$7295_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $and$libresoc.v:155511$7893 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $and $and$libresoc.v:146054$7269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$21 - connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:155511$7893_Y + connect \A \$113 + connect \B \$115 + connect \Y $and$libresoc.v:146054$7269_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $and$libresoc.v:155512$7894 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $and $and$libresoc.v:146058$7273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [31] - connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:155512$7894_Y + connect \A \$121 + connect \B \$123 + connect \Y $and$libresoc.v:146058$7273_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $and$libresoc.v:155513$7895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:146091$7306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rb [31] - connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:155513$7895_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $pos $extend$libresoc.v:155516$7898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $extend$libresoc.v:155516$7898_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:155517$7900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $extend$libresoc.v:155517$7900_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $pos $extend$libresoc.v:155519$7903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $extend$libresoc.v:155519$7903_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:155520$7905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $extend$libresoc.v:155520$7905_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $neg$libresoc.v:155516$7899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:155516$7898_Y - connect \Y $neg$libresoc.v:155516$7899_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $neg$libresoc.v:155519$7904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:155519$7903_Y - connect \Y $neg$libresoc.v:155519$7904_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:155517$7901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:155517$7900_Y - connect \Y $pos$libresoc.v:155517$7901_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:155520$7906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:155520$7905_Y - connect \Y $pos$libresoc.v:155520$7906_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $ternary$libresoc.v:155508$7890 - parameter \WIDTH 1 - connect \A \ra [63] - connect \B \ra [31] - connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:155508$7890_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $ternary$libresoc.v:155510$7892 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:155510$7892_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $ternary$libresoc.v:155518$7902 - parameter \WIDTH 65 - connect \A \$36 - connect \B \$34 - connect \S \sign_a - connect \Y $ternary$libresoc.v:155518$7902_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $ternary$libresoc.v:155521$7907 - parameter \WIDTH 65 - connect \A \$43 - connect \B \$41 - connect \S \sign_b - connect \Y $ternary$libresoc.v:155521$7907_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:155522$7908 - parameter \WIDTH 32 - connect \A \abs_a [63:32] - connect \B 0 - connect \S \is_32bit - connect \Y $ternary$libresoc.v:155522$7908_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:155523$7909 - parameter \WIDTH 32 - connect \A \abs_b [63:32] - connect \B 0 - connect \S \is_32bit - connect \Y $ternary$libresoc.v:155523$7909_Y + connect \A \zerolo + connect \B \$69 + connect \Y $and$libresoc.v:146091$7306_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $xor$libresoc.v:155514$7896 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:146096$7311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sign_a - connect \B \sign_b - connect \Y $xor$libresoc.v:155514$7896_Y + connect \A \zerolo + connect \B \$79 + connect \Y $and$libresoc.v:146096$7311_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $xor$libresoc.v:155515$7897 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $and $and$libresoc.v:146099$7314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sign32_a - connect \B \sign32_b - connect \Y $xor$libresoc.v:155515$7897_Y - end - connect \$17 $ternary$libresoc.v:155508$7890_Y - connect \$19 $and$libresoc.v:155509$7891_Y - connect \$21 $ternary$libresoc.v:155510$7892_Y - connect \$23 $and$libresoc.v:155511$7893_Y - connect \$25 $and$libresoc.v:155512$7894_Y - connect \$27 $and$libresoc.v:155513$7895_Y - connect \$29 $xor$libresoc.v:155514$7896_Y - connect \$31 $xor$libresoc.v:155515$7897_Y - connect \$34 $neg$libresoc.v:155516$7899_Y - connect \$36 $pos$libresoc.v:155517$7901_Y - connect \$38 $ternary$libresoc.v:155518$7902_Y - connect \$41 $neg$libresoc.v:155519$7904_Y - connect \$43 $pos$libresoc.v:155520$7906_Y - connect \$45 $ternary$libresoc.v:155521$7907_Y - connect \$47 $ternary$libresoc.v:155522$7908_Y - connect \$49 $ternary$libresoc.v:155523$7909_Y - connect \$33 \$38 - connect \$40 \$45 - connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$16 \xer_so - connect \rb$15 [63:32] \$49 - connect \rb$15 [31:0] \abs_b [31:0] - connect \ra$14 [63:32] \$47 - connect \ra$14 [31:0] \abs_a [31:0] - connect \abs_b \$45 [63:0] - connect \abs_a \$38 [63:0] - connect \neg_res32 \$31 - connect \neg_res \$29 - connect \sign32_b \$27 - connect \sign32_a \$25 - connect \sign_b \$23 - connect \sign_a \$19 - connect \is_32bit \mul_op__is_32bit -end -attribute \src "libresoc.v:155546.1-155805.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" -attribute \generator "nMigen" -module \mul2 - attribute \src "libresoc.v:155798.18-155798.98" - wire width 129 $extend$libresoc.v:155798$7911_Y - attribute \src "libresoc.v:155797.18-155797.99" - wire width 128 $mul$libresoc.v:155797$7910_Y - attribute \src "libresoc.v:155798.18-155798.98" - wire width 129 $pos$libresoc.v:155798$7912_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - wire width 129 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - wire width 128 \$18 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \$39 - attribute \src "libresoc.v:155810.7-155810.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" - wire \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" - wire width 129 \mul_o - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 18 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 28 \mul_op__insn$13 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 22 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" - wire \mul_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 35 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire input 15 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 input 13 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 29 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 30 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 31 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 14 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 33 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 34 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:156099$7921 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$91 + connect \Y $and$libresoc.v:146102$7317_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + cell $eq $eq$libresoc.v:146045$7260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 1'1 + connect \Y $eq$libresoc.v:146045$7260_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" + cell $eq $eq$libresoc.v:146046$7261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 2'10 + connect \Y $eq$libresoc.v:146046$7261_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" + cell $eq $eq$libresoc.v:146047$7262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 3'100 + connect \Y $eq$libresoc.v:146047$7262_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:146059$7274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:146059$7274_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:146060$7275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:146060$7275_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:146061$7276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:146061$7276_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:146062$7277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:146062$7277_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:146063$7278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:146063$7278_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:146064$7279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:146064$7279_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:146065$7280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:146065$7280_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" + cell $eq $eq$libresoc.v:146066$7281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:146066$7281_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" + cell $eq $eq$libresoc.v:146067$7282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:146067$7282_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + cell $eq $eq$libresoc.v:146069$7284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:146069$7284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + cell $eq $eq$libresoc.v:146070$7285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:146070$7285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" + cell $eq $eq$libresoc.v:146071$7286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$libresoc.v:146071$7286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $eq $eq$libresoc.v:146072$7287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:146072$7287_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" + cell $eq $eq$libresoc.v:146074$7289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$libresoc.v:146074$7289_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $eq $eq$libresoc.v:146075$7290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:146075$7290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" + cell $eq $eq$libresoc.v:146077$7292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$libresoc.v:146077$7292_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $eq $eq$libresoc.v:146078$7293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:146078$7293_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + cell $ne $ne$libresoc.v:146092$7307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$23 - connect \B \$25 - connect \Y $and$libresoc.v:156099$7921_Y + connect \A \msb_a + connect \B \msb_b + connect \Y $ne$libresoc.v:146092$7307_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:156103$7925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + cell $ne $ne$libresoc.v:146103$7318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$31 - connect \B \$33 - connect \Y $and$libresoc.v:156103$7925_Y + connect \A \msb_a + connect \B \msb_b + connect \Y $ne$libresoc.v:146103$7318_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:156093$7913 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $not $not$libresoc.v:146053$7268 parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 130 - connect \A \o - connect \Y $extend$libresoc.v:156093$7913_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$116 + connect \Y $not$libresoc.v:146053$7268_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:156094$7915 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $not $not$libresoc.v:146057$7272 parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 130 - connect \A \o - connect \Y $extend$libresoc.v:156094$7915_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$124 + connect \Y $not$libresoc.v:146057$7272_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:156104$7926 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" + cell $not $not$libresoc.v:146068$7283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \xer_so - connect \Y $extend$libresoc.v:156104$7926_Y + parameter \Y_WIDTH 1 + connect \A \alu_op__insn [21] + connect \Y $not$libresoc.v:146068$7283_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:156093$7914 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $not $not$libresoc.v:146081$7296 parameter \A_SIGNED 0 - parameter \A_WIDTH 130 - parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:156093$7913_Y - connect \Y $neg$libresoc.v:156093$7914_Y + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:146081$7296_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:156098$7920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $not $not$libresoc.v:146086$7301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $not$libresoc.v:156098$7920_Y + connect \A \$58 + connect \Y $not$libresoc.v:146086$7301_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:156102$7924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $not $not$libresoc.v:146089$7304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$34 - connect \Y $not$libresoc.v:156102$7924_Y + connect \A \$64 + connect \Y $not$libresoc.v:146089$7304_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:156094$7916 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" + cell $not $not$libresoc.v:146093$7308 parameter \A_SIGNED 0 - parameter \A_WIDTH 130 - parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:156094$7915_Y - connect \Y $pos$libresoc.v:156094$7916_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_lt + connect \Y $not$libresoc.v:146093$7308_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:156104$7927 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" + cell $not $not$libresoc.v:146094$7309 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:156104$7926_Y - connect \Y $pos$libresoc.v:156104$7927_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_lt + connect \Y $not$libresoc.v:146094$7309_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:156097$7919 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $or $or$libresoc.v:146073$7288 parameter \A_SIGNED 0 - parameter \A_WIDTH 33 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:156097$7919_Y + connect \A \$30 + connect \B \$32 + connect \Y $or$libresoc.v:146073$7288_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:156101$7923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $or $or$libresoc.v:146076$7291 parameter \A_SIGNED 0 - parameter \A_WIDTH 65 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:156101$7923_Y + connect \A \$36 + connect \B \$38 + connect \Y $or$libresoc.v:146076$7291_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:156096$7918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $or $or$libresoc.v:146079$7294 parameter \A_SIGNED 0 - parameter \A_WIDTH 33 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:156096$7918_Y + connect \A \$42 + connect \B \$44 + connect \Y $or$libresoc.v:146079$7294_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:156100$7922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:146090$7305 parameter \A_SIGNED 0 - parameter \A_WIDTH 65 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:156100$7922_Y + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:146090$7305_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:156095$7917 - parameter \WIDTH 130 - connect \A \$19 - connect \B \$17 - connect \S \neg_res - connect \Y $ternary$libresoc.v:156095$7917_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:146095$7310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:146095$7310_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:146098$7313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:146098$7313_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $or $or$libresoc.v:146101$7316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$libresoc.v:146101$7316_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" + cell $reduce_or $reduce_or$libresoc.v:146044$7259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $reduce_or$libresoc.v:146044$7259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" + cell $reduce_or $reduce_or$libresoc.v:146048$7263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $reduce_or$libresoc.v:146048$7263_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $reduce_or $reduce_or$libresoc.v:146085$7300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \Y $reduce_or$libresoc.v:146085$7300_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $reduce_or $reduce_or$libresoc.v:146088$7303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \Y $reduce_or$libresoc.v:146088$7303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" + cell $mux $ternary$libresoc.v:146097$7312 + parameter \WIDTH 1 + connect \A \a_n [63] + connect \B \a_n [31] + connect \S \is_32bit + connect \Y $ternary$libresoc.v:146097$7312_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" + cell $mux $ternary$libresoc.v:146100$7315 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \is_32bit + connect \Y $ternary$libresoc.v:146100$7315_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" + cell $mux $ternary$libresoc.v:146104$7319 + parameter \WIDTH 1 + connect \A \carry_64 + connect \B \carry_32 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:146104$7319_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + cell $xor $xor$libresoc.v:146049$7264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [32] + connect \B \b_i [32] + connect \Y $xor$libresoc.v:146049$7264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + cell $xor $xor$libresoc.v:146050$7265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \$109 + connect \Y $xor$libresoc.v:146050$7265_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:146051$7266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [0] + connect \B \add_o [64] + connect \Y $xor$libresoc.v:146051$7266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:146052$7267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [63] + connect \B \b_i [63] + connect \Y $xor$libresoc.v:146052$7267_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:146055$7270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [1] + connect \B \add_o [32] + connect \Y $xor$libresoc.v:146055$7270_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:146056$7271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [31] + connect \B \b_i [31] + connect \Y $xor$libresoc.v:146056$7271_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:146082$7297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \ra [32] + connect \Y $xor$libresoc.v:146082$7297_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:146083$7298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \rb [32] + connect \Y $xor$libresoc.v:146083$7298_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $xor $xor$libresoc.v:146084$7299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [31:0] + connect \B \rb [31:0] + connect \Y $xor$libresoc.v:146084$7299_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $xor $xor$libresoc.v:146087$7302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [63:32] + connect \B \rb [63:32] + connect \Y $xor$libresoc.v:146087$7302_Y end - attribute \src "libresoc.v:155810.7-155810.20" - process $proc$libresoc.v:155810$7935 + attribute \src "libresoc.v:145587.7-145587.20" + process $proc$libresoc.v:145587$7349 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:156105.3-156123.6" - process $proc$libresoc.v:156105$7928 + attribute \src "libresoc.v:146105.3-146114.6" + process $proc$libresoc.v:146105$7320 assign { } { } assign { } { } - assign $0\o$14[63:0]$7929 $1\o$14[63:0]$7930 - attribute \src "libresoc.v:156106.5-156106.29" + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + attribute \src "libresoc.v:146106.5-146106.29" switch \initial - attribute \src "libresoc.v:156106.9-156106.17" + attribute \src "libresoc.v:146106.9-146106.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" + switch \$22 attribute \src "libresoc.v:0.0-0.0" - case 7'0110100 + case 1'1 assign { } { } - assign $1\o$14[63:0]$7930 { \mul_o [63:32] \mul_o [63:32] } + assign $1\is_32bit[0:0] \$24 + case + assign $1\is_32bit[0:0] 1'0 + end + sync always + update \is_32bit $0\is_32bit[0:0] + end + attribute \src "libresoc.v:146115.3-146137.6" + process $proc$libresoc.v:146115$7321 + assign { } { } + assign $0\a_i[63:0] $1\a_i[63:0] + attribute \src "libresoc.v:146116.5-146116.29" + switch \initial + attribute \src "libresoc.v:146116.9-146116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch { \is_32bit \$26 } attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 + case 2'-1 assign { } { } - assign $1\o$14[63:0]$7930 \mul_o [127:64] + assign $1\a_i[63:0] \ra attribute \src "libresoc.v:0.0-0.0" - case 7'0110010 + case 2'1- + assign { } { } + assign $1\a_i[63:0] $2\a_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a_i[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\a_i[63:0] { 32'00000000000000000000000000000000 \ra [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a_i[63:0] \ra + end + sync always + update \a_i $0\a_i[63:0] + end + attribute \src "libresoc.v:146138.3-146148.6" + process $proc$libresoc.v:146138$7322 + assign { } { } + assign { } { } + assign $0\zerohi[0:0] $1\zerohi[0:0] + attribute \src "libresoc.v:146139.5-146139.29" + switch \initial + attribute \src "libresoc.v:146139.9-146139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\zerohi[0:0] \$63 + case + assign $1\zerohi[0:0] 1'0 + end + sync always + update \zerohi $0\zerohi[0:0] + end + attribute \src "libresoc.v:146149.3-146175.6" + process $proc$libresoc.v:146149$7323 + assign { } { } + assign { } { } + assign $0\tval[4:0] $1\tval[4:0] + attribute \src "libresoc.v:146150.5-146150.29" + switch \initial + attribute \src "libresoc.v:146150.9-146150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\tval[4:0] $2\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { $2\tval[4:0] [4:3] $2\tval[4:0] [1:0] } 4'0000 + assign $2\tval[4:0] [2] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\tval[4:0] $3\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\tval[4:0] { \msb_a \msb_b 1'0 \msb_b \msb_a } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\tval[4:0] { \a_lt \$77 1'0 \a_lt \$75 } + end + end + case + assign $1\tval[4:0] 5'00000 + end + sync always + update \tval $0\tval[4:0] + end + attribute \src "libresoc.v:146176.3-146194.6" + process $proc$libresoc.v:146176$7324 + assign { } { } + assign { } { } + assign $0\msb_a[0:0] $1\msb_a[0:0] + attribute \src "libresoc.v:146177.5-146177.29" + switch \initial + attribute \src "libresoc.v:146177.9-146177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_a[0:0] $2\msb_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\msb_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\msb_a[0:0] \$83 + end + case + assign $1\msb_a[0:0] 1'0 + end + sync always + update \msb_a $0\msb_a[0:0] + end + attribute \src "libresoc.v:146195.3-146213.6" + process $proc$libresoc.v:146195$7325 + assign { } { } + assign { } { } + assign $0\msb_b[0:0] $1\msb_b[0:0] + attribute \src "libresoc.v:146196.5-146196.29" + switch \initial + attribute \src "libresoc.v:146196.9-146196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_b[0:0] $2\msb_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\msb_b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\msb_b[0:0] \$89 + end + case + assign $1\msb_b[0:0] 1'0 + end + sync always + update \msb_b $0\msb_b[0:0] + end + attribute \src "libresoc.v:146214.3-146240.6" + process $proc$libresoc.v:146214$7326 + assign { } { } + assign { } { } + assign $0\a_lt[0:0] $1\a_lt[0:0] + attribute \src "libresoc.v:146215.5-146215.29" + switch \initial + attribute \src "libresoc.v:146215.9-146215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\a_lt[0:0] $2\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\a_lt[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\a_lt[0:0] $3\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\a_lt[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\a_lt[0:0] \$97 + end + end + case + assign $1\a_lt[0:0] 1'0 + end + sync always + update \a_lt $0\a_lt[0:0] + end + attribute \src "libresoc.v:146241.3-146266.6" + process $proc$libresoc.v:146241$7327 + assign { } { } + assign { } { } + assign $0\cr_a[3:0] $1\cr_a[3:0] + attribute \src "libresoc.v:146242.5-146242.29" + switch \initial + attribute \src "libresoc.v:146242.9-146242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } + assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a[3:2] \tval [4:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_a[3:2] \tval [1:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a[3:0] { 1'0 \$99 2'00 } + case + assign $1\cr_a[3:0] 4'0000 + end + sync always + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:146267.3-146281.6" + process $proc$libresoc.v:146267$7328 + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + attribute \src "libresoc.v:146268.5-146268.29" + switch \initial + attribute \src "libresoc.v:146268.9-146268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + case + assign $1\cr_a_ok[0:0] 1'0 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:146282.3-146319.6" + process $proc$libresoc.v:146282$7329 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:146283.5-146283.29" + switch \initial + attribute \src "libresoc.v:146283.9-146283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o[63:0] \add_o [64:1] + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign { } { } assign { } { } - assign $1\o$14[63:0]$7930 \mul_o [63:0] + assign $1\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] { \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7:0] } + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] { \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15:0] } + case + assign $3\o[63:0] $2\o[63:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + case + assign $4\o[63:0] $3\o[63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign $1\o[63:0] [63:1] 63'000000000000000000000000000000000000000000000000000000000000000 + assign $1\o[63:0] [0] \$107 case - assign $1\o$14[63:0]$7930 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \o$14 $0\o$14[63:0]$7929 + update \o $0\o[63:0] end - attribute \src "libresoc.v:156124.3-156142.6" - process $proc$libresoc.v:156124$7931 + attribute \src "libresoc.v:146320.3-146338.6" + process $proc$libresoc.v:146320$7330 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:156125.5-156125.29" + attribute \src "libresoc.v:146321.5-146321.29" switch \initial - attribute \src "libresoc.v:156125.9-156125.17" + attribute \src "libresoc.v:146321.9-146321.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 7'0110100 + case 7'0000010 assign { } { } assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 + case 7'0011111 assign { } { } assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 7'0110010 + case 7'0001100 + assign { } { } + assign $1\o_ok[0:0] 1'0 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:146339.3-146352.6" + process $proc$libresoc.v:146339$7331 + assign { } { } + assign { } { } + assign $0\ca[1:0] $1\ca[1:0] + attribute \src "libresoc.v:146340.5-146340.29" + switch \initial + attribute \src "libresoc.v:146340.9-146340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ca[1:0] [0] \add_o [65] + assign $1\ca[1:0] [1] \$111 + case + assign $1\ca[1:0] 2'00 + end + sync always + update \ca $0\ca[1:0] + end + attribute \src "libresoc.v:146353.3-146375.6" + process $proc$libresoc.v:146353$7332 + assign { } { } + assign $0\b_i[63:0] $1\b_i[63:0] + attribute \src "libresoc.v:146354.5-146354.29" + switch \initial + attribute \src "libresoc.v:146354.9-146354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch { \is_32bit \$28 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\b_i[63:0] \rb + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\b_i[63:0] $2\b_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\b_i[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\b_i[63:0] { 32'00000000000000000000000000000000 \rb [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b_i[63:0] \rb + end + sync always + update \b_i $0\b_i[63:0] + end + attribute \src "libresoc.v:146376.3-146386.6" + process $proc$libresoc.v:146376$7333 + assign { } { } + assign { } { } + assign $0\xer_ca$20[1:0]$7334 $1\xer_ca$20[1:0]$7335 + attribute \src "libresoc.v:146377.5-146377.29" + switch \initial + attribute \src "libresoc.v:146377.9-146377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca$20[1:0]$7335 \ca + case + assign $1\xer_ca$20[1:0]$7335 2'00 + end + sync always + update \xer_ca$20 $0\xer_ca$20[1:0]$7334 + end + attribute \src "libresoc.v:146387.3-146397.6" + process $proc$libresoc.v:146387$7336 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:146388.5-146388.29" + switch \initial + attribute \src "libresoc.v:146388.9-146388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'1 + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:146398.3-146411.6" + process $proc$libresoc.v:146398$7337 + assign { } { } + assign { } { } + assign $0\ov[1:0] $1\ov[1:0] + attribute \src "libresoc.v:146399.5-146399.29" + switch \initial + attribute \src "libresoc.v:146399.9-146399.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ov[1:0] [0] \$119 + assign $1\ov[1:0] [1] \$127 + case + assign $1\ov[1:0] 2'00 + end + sync always + update \ov $0\ov[1:0] + end + attribute \src "libresoc.v:146412.3-146422.6" + process $proc$libresoc.v:146412$7338 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "libresoc.v:146413.5-146413.29" + switch \initial + attribute \src "libresoc.v:146413.9-146413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov[1:0] \ov + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:146423.3-146433.6" + process $proc$libresoc.v:146423$7339 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:146424.5-146424.29" + switch \initial + attribute \src "libresoc.v:146424.9-146424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:146434.3-146444.6" + process $proc$libresoc.v:146434$7340 + assign { } { } + assign { } { } + assign $0\src1[7:0] $1\src1[7:0] + attribute \src "libresoc.v:146435.5-146435.29" + switch \initial + attribute \src "libresoc.v:146435.9-146435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\src1[7:0] \ra [7:0] + case + assign $1\src1[7:0] 8'00000000 + end + sync always + update \src1 $0\src1[7:0] + end + attribute \src "libresoc.v:146445.3-146464.6" + process $proc$libresoc.v:146445$7341 + assign { } { } + assign { } { } + assign $0\eqs[7:0] $1\eqs[7:0] + attribute \src "libresoc.v:146446.5-146446.29" + switch \initial + attribute \src "libresoc.v:146446.9-146446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\eqs[7:0] [0] \$129 + assign $1\eqs[7:0] [1] \$131 + assign $1\eqs[7:0] [2] \$133 + assign $1\eqs[7:0] [3] \$135 + assign $1\eqs[7:0] [4] \$137 + assign $1\eqs[7:0] [5] \$139 + assign $1\eqs[7:0] [6] \$141 + assign $1\eqs[7:0] [7] \$143 + case + assign $1\eqs[7:0] 8'00000000 + end + sync always + update \eqs $0\eqs[7:0] + end + attribute \src "libresoc.v:146465.3-146474.6" + process $proc$libresoc.v:146465$7342 + assign { } { } + assign { } { } + assign $0\add_a[65:0] $1\add_a[65:0] + attribute \src "libresoc.v:146466.5-146466.29" + switch \initial + attribute \src "libresoc.v:146466.9-146466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_a[65:0] { 1'0 \a_i \xer_ca [0] } + case + assign $1\add_a[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_a $0\add_a[65:0] + end + attribute \src "libresoc.v:146475.3-146484.6" + process $proc$libresoc.v:146475$7343 + assign { } { } + assign { } { } + assign $0\add_b[65:0] $1\add_b[65:0] + attribute \src "libresoc.v:146476.5-146476.29" + switch \initial + attribute \src "libresoc.v:146476.9-146476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_b[65:0] { 1'0 \b_i 1'1 } + case + assign $1\add_b[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_b $0\add_b[65:0] + end + attribute \src "libresoc.v:146485.3-146494.6" + process $proc$libresoc.v:146485$7344 + assign { } { } + assign { } { } + assign $0\add_o[65:0] $1\add_o[65:0] + attribute \src "libresoc.v:146486.5-146486.29" + switch \initial + attribute \src "libresoc.v:146486.9-146486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_o[65:0] \$48 [65:0] + case + assign $1\add_o[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_o $0\add_o[65:0] + end + attribute \src "libresoc.v:146495.3-146505.6" + process $proc$libresoc.v:146495$7345 + assign { } { } + assign { } { } + assign $0\a_n[63:0] $1\a_n[63:0] + attribute \src "libresoc.v:146496.5-146496.29" + switch \initial + attribute \src "libresoc.v:146496.9-146496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 assign { } { } - assign $1\o_ok[0:0] 1'1 + assign $1\a_n[63:0] \$51 case - assign $1\o_ok[0:0] 1'0 + assign $1\a_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \o_ok $0\o_ok[0:0] + update \a_n $0\a_n[63:0] end - attribute \src "libresoc.v:156143.3-156161.6" - process $proc$libresoc.v:156143$7932 + attribute \src "libresoc.v:146506.3-146516.6" + process $proc$libresoc.v:146506$7346 assign { } { } assign { } { } - assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:156144.5-156144.29" + assign $0\carry_32[0:0] $1\carry_32[0:0] + attribute \src "libresoc.v:146507.5-146507.29" switch \initial - attribute \src "libresoc.v:156144.9-156144.17" + attribute \src "libresoc.v:146507.9-146507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 7'0110010 + case 7'0001010 assign { } { } - assign $1\mul_ov[0:0] $2\mul_ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" - switch \is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\mul_ov[0:0] \$29 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\mul_ov[0:0] \$37 - end + assign $1\carry_32[0:0] \$55 case - assign $1\mul_ov[0:0] 1'0 + assign $1\carry_32[0:0] 1'0 end sync always - update \mul_ov $0\mul_ov[0:0] + update \carry_32 $0\carry_32[0:0] end - attribute \src "libresoc.v:156162.3-156172.6" - process $proc$libresoc.v:156162$7933 + attribute \src "libresoc.v:146517.3-146527.6" + process $proc$libresoc.v:146517$7347 assign { } { } assign { } { } - assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:156163.5-156163.29" + assign $0\carry_64[0:0] $1\carry_64[0:0] + attribute \src "libresoc.v:146518.5-146518.29" switch \initial - attribute \src "libresoc.v:156163.9-156163.17" + attribute \src "libresoc.v:146518.9-146518.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 7'0110010 + case 7'0001010 assign { } { } - assign $1\xer_ov[1:0] { \mul_ov \mul_ov } + assign $1\carry_64[0:0] \add_o [65] case - assign $1\xer_ov[1:0] 2'00 + assign $1\carry_64[0:0] 1'0 end sync always - update \xer_ov $0\xer_ov[1:0] + update \carry_64 $0\carry_64[0:0] end - attribute \src "libresoc.v:156173.3-156183.6" - process $proc$libresoc.v:156173$7934 + attribute \src "libresoc.v:146528.3-146538.6" + process $proc$libresoc.v:146528$7348 assign { } { } assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:156174.5-156174.29" + assign $0\zerolo[0:0] $1\zerolo[0:0] + attribute \src "libresoc.v:146529.5-146529.29" switch \initial - attribute \src "libresoc.v:156174.9-156174.17" + attribute \src "libresoc.v:146529.9-146529.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 7'0110010 + case 7'0001010 assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 + assign $1\zerolo[0:0] \$57 case - assign $1\xer_ov_ok[0:0] 1'0 + assign $1\zerolo[0:0] 1'0 end sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] + update \zerolo $0\zerolo[0:0] end - connect \$17 $neg$libresoc.v:156093$7914_Y - connect \$19 $pos$libresoc.v:156094$7916_Y - connect \$21 $ternary$libresoc.v:156095$7917_Y - connect \$23 $reduce_or$libresoc.v:156096$7918_Y - connect \$26 $reduce_and$libresoc.v:156097$7919_Y - connect \$25 $not$libresoc.v:156098$7920_Y - connect \$29 $and$libresoc.v:156099$7921_Y - connect \$31 $reduce_or$libresoc.v:156100$7922_Y - connect \$34 $reduce_and$libresoc.v:156101$7923_Y - connect \$33 $not$libresoc.v:156102$7924_Y - connect \$37 $and$libresoc.v:156103$7925_Y - connect \$39 $pos$libresoc.v:156104$7927_Y - connect \$16 \$21 - connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \$99 $reduce_or$libresoc.v:146044$7259_Y + connect \$101 $eq$libresoc.v:146045$7260_Y + connect \$103 $eq$libresoc.v:146046$7261_Y + connect \$105 $eq$libresoc.v:146047$7262_Y + connect \$107 $reduce_or$libresoc.v:146048$7263_Y + connect \$109 $xor$libresoc.v:146049$7264_Y + connect \$111 $xor$libresoc.v:146050$7265_Y + connect \$113 $xor$libresoc.v:146051$7266_Y + connect \$116 $xor$libresoc.v:146052$7267_Y + connect \$115 $not$libresoc.v:146053$7268_Y + connect \$119 $and$libresoc.v:146054$7269_Y + connect \$121 $xor$libresoc.v:146055$7270_Y + connect \$124 $xor$libresoc.v:146056$7271_Y + connect \$123 $not$libresoc.v:146057$7272_Y + connect \$127 $and$libresoc.v:146058$7273_Y + connect \$129 $eq$libresoc.v:146059$7274_Y + connect \$131 $eq$libresoc.v:146060$7275_Y + connect \$133 $eq$libresoc.v:146061$7276_Y + connect \$135 $eq$libresoc.v:146062$7277_Y + connect \$137 $eq$libresoc.v:146063$7278_Y + connect \$139 $eq$libresoc.v:146064$7279_Y + connect \$141 $eq$libresoc.v:146065$7280_Y + connect \$143 $eq$libresoc.v:146066$7281_Y + connect \$22 $eq$libresoc.v:146067$7282_Y + connect \$24 $not$libresoc.v:146068$7283_Y + connect \$26 $eq$libresoc.v:146069$7284_Y + connect \$28 $eq$libresoc.v:146070$7285_Y + connect \$30 $eq$libresoc.v:146071$7286_Y + connect \$32 $eq$libresoc.v:146072$7287_Y + connect \$34 $or$libresoc.v:146073$7288_Y + connect \$36 $eq$libresoc.v:146074$7289_Y + connect \$38 $eq$libresoc.v:146075$7290_Y + connect \$40 $or$libresoc.v:146076$7291_Y + connect \$42 $eq$libresoc.v:146077$7292_Y + connect \$44 $eq$libresoc.v:146078$7293_Y + connect \$46 $or$libresoc.v:146079$7294_Y + connect \$49 $add$libresoc.v:146080$7295_Y + connect \$51 $not$libresoc.v:146081$7296_Y + connect \$53 $xor$libresoc.v:146082$7297_Y + connect \$55 $xor$libresoc.v:146083$7298_Y + connect \$59 $xor$libresoc.v:146084$7299_Y + connect \$58 $reduce_or$libresoc.v:146085$7300_Y + connect \$57 $not$libresoc.v:146086$7301_Y + connect \$65 $xor$libresoc.v:146087$7302_Y + connect \$64 $reduce_or$libresoc.v:146088$7303_Y + connect \$63 $not$libresoc.v:146089$7304_Y + connect \$69 $or$libresoc.v:146090$7305_Y + connect \$71 $and$libresoc.v:146091$7306_Y + connect \$73 $ne$libresoc.v:146092$7307_Y + connect \$75 $not$libresoc.v:146093$7308_Y + connect \$77 $not$libresoc.v:146094$7309_Y + connect \$79 $or$libresoc.v:146095$7310_Y + connect \$81 $and$libresoc.v:146096$7311_Y + connect \$83 $ternary$libresoc.v:146097$7312_Y + connect \$85 $or$libresoc.v:146098$7313_Y + connect \$87 $and$libresoc.v:146099$7314_Y + connect \$89 $ternary$libresoc.v:146100$7315_Y + connect \$91 $or$libresoc.v:146101$7316_Y + connect \$93 $and$libresoc.v:146102$7317_Y + connect \$95 $ne$libresoc.v:146103$7318_Y + connect \$97 $ternary$libresoc.v:146104$7319_Y + connect \$48 \$49 + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid - connect { \xer_so_ok \xer_so$15 } \$39 - connect \mul_o \$21 [128:0] - connect \is_32bit \mul_op__is_32bit + connect \xer_so$21 \xer_so end -attribute \src "libresoc.v:156194.1-157397.10" +attribute \src "libresoc.v:146547.1-146957.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" -module \mul_pipe1 - attribute \src "libresoc.v:156195.7-156195.20" +module \main$114 + attribute \src "libresoc.v:146548.7-146548.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire width 13 $0\mul_op__fn_unit$next[12:0]$7964 - attribute \src "libresoc.v:157139.3-157140.47" - wire width 13 $0\mul_op__fn_unit[12:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire width 64 $0\mul_op__imm_data__data$next[63:0]$7965 - attribute \src "libresoc.v:157141.3-157142.61" - wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $0\mul_op__imm_data__ok$next[0:0]$7966 - attribute \src "libresoc.v:157143.3-157144.57" - wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire width 32 $0\mul_op__insn$next[31:0]$7967 - attribute \src "libresoc.v:157159.3-157160.41" - wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire width 7 $0\mul_op__insn_type$next[6:0]$7968 - attribute \src "libresoc.v:157137.3-157138.51" - wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $0\mul_op__is_32bit$next[0:0]$7969 - attribute \src "libresoc.v:157155.3-157156.49" - wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $0\mul_op__is_signed$next[0:0]$7970 - attribute \src "libresoc.v:157157.3-157158.51" - wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $0\mul_op__oe__oe$next[0:0]$7971 - attribute \src "libresoc.v:157149.3-157150.45" - wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $0\mul_op__oe__ok$next[0:0]$7972 - attribute \src "libresoc.v:157151.3-157152.45" - wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $0\mul_op__rc__ok$next[0:0]$7973 - attribute \src "libresoc.v:157147.3-157148.45" - wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $0\mul_op__rc__rc$next[0:0]$7974 - attribute \src "libresoc.v:157145.3-157146.45" - wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $0\mul_op__write_cr0$next[0:0]$7975 - attribute \src "libresoc.v:157153.3-157154.51" - wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:157261.3-157273.6" - wire width 2 $0\muxid$next[1:0]$7961 - attribute \src "libresoc.v:157161.3-157162.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:157349.3-157361.6" - wire $0\neg_res$next[0:0]$8004 - attribute \src "libresoc.v:157362.3-157374.6" - wire $0\neg_res32$next[0:0]$8007 - attribute \src "libresoc.v:157127.3-157128.35" - wire $0\neg_res32[0:0] - attribute \src "libresoc.v:157129.3-157130.31" - wire $0\neg_res[0:0] - attribute \src "libresoc.v:157243.3-157260.6" - wire $0\r_busy$next[0:0]$7957 - attribute \src "libresoc.v:157163.3-157164.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:157310.3-157322.6" - wire width 64 $0\ra$next[63:0]$7995 - attribute \src "libresoc.v:157135.3-157136.21" - wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:157323.3-157335.6" - wire width 64 $0\rb$next[63:0]$7998 - attribute \src "libresoc.v:157133.3-157134.21" - wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:157336.3-157348.6" - wire $0\xer_so$next[0:0]$8001 - attribute \src "libresoc.v:157131.3-157132.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire width 13 $1\mul_op__fn_unit$next[12:0]$7976 - attribute \src "libresoc.v:156702.14-156702.40" - wire width 13 $1\mul_op__fn_unit[12:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire width 64 $1\mul_op__imm_data__data$next[63:0]$7977 - attribute \src "libresoc.v:156739.14-156739.59" - wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $1\mul_op__imm_data__ok$next[0:0]$7978 - attribute \src "libresoc.v:156748.7-156748.34" - wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire width 32 $1\mul_op__insn$next[31:0]$7979 - attribute \src "libresoc.v:156757.14-156757.34" - wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire width 7 $1\mul_op__insn_type$next[6:0]$7980 - attribute \src "libresoc.v:156840.13-156840.38" - wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $1\mul_op__is_32bit$next[0:0]$7981 - attribute \src "libresoc.v:156997.7-156997.30" - wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $1\mul_op__is_signed$next[0:0]$7982 - attribute \src "libresoc.v:157006.7-157006.31" - wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $1\mul_op__oe__oe$next[0:0]$7983 - attribute \src "libresoc.v:157015.7-157015.28" - wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $1\mul_op__oe__ok$next[0:0]$7984 - attribute \src "libresoc.v:157024.7-157024.28" - wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $1\mul_op__rc__ok$next[0:0]$7985 - attribute \src "libresoc.v:157033.7-157033.28" - wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $1\mul_op__rc__rc$next[0:0]$7986 - attribute \src "libresoc.v:157042.7-157042.28" - wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire $1\mul_op__write_cr0$next[0:0]$7987 - attribute \src "libresoc.v:157051.7-157051.31" - wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:157261.3-157273.6" - wire width 2 $1\muxid$next[1:0]$7962 - attribute \src "libresoc.v:157060.13-157060.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:157349.3-157361.6" - wire $1\neg_res$next[0:0]$8005 - attribute \src "libresoc.v:157362.3-157374.6" - wire $1\neg_res32$next[0:0]$8008 - attribute \src "libresoc.v:157082.7-157082.23" - wire $1\neg_res32[0:0] - attribute \src "libresoc.v:157075.7-157075.21" - wire $1\neg_res[0:0] - attribute \src "libresoc.v:157243.3-157260.6" - wire $1\r_busy$next[0:0]$7958 - attribute \src "libresoc.v:157096.7-157096.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:157310.3-157322.6" - wire width 64 $1\ra$next[63:0]$7996 - attribute \src "libresoc.v:157101.14-157101.39" - wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:157323.3-157335.6" - wire width 64 $1\rb$next[63:0]$7999 - attribute \src "libresoc.v:157110.14-157110.39" - wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:157336.3-157348.6" - wire $1\xer_so$next[0:0]$8002 - attribute \src "libresoc.v:157119.7-157119.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:157274.3-157309.6" - wire width 64 $2\mul_op__imm_data__data$next[63:0]$7988 - attribute \src "libresoc.v:157274.3-157309.6" - wire $2\mul_op__imm_data__ok$next[0:0]$7989 - attribute \src "libresoc.v:157274.3-157309.6" - wire $2\mul_op__oe__oe$next[0:0]$7990 - attribute \src "libresoc.v:157274.3-157309.6" - wire $2\mul_op__oe__ok$next[0:0]$7991 - attribute \src "libresoc.v:157274.3-157309.6" - wire $2\mul_op__rc__ok$next[0:0]$7992 - attribute \src "libresoc.v:157274.3-157309.6" - wire $2\mul_op__rc__rc$next[0:0]$7993 - attribute \src "libresoc.v:157243.3-157260.6" - wire $2\r_busy$next[0:0]$7959 - attribute \src "libresoc.v:157126.18-157126.118" - wire $and$libresoc.v:157126$7936_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:156195.7-156195.15" + attribute \src "libresoc.v:146909.3-146939.6" + wire width 4 $0\mode[3:0] + attribute \src "libresoc.v:146874.3-146908.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:146909.3-146939.6" + wire width 4 $1\mode[3:0] + attribute \src "libresoc.v:146874.3-146908.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:146548.7-146548.15" wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" + wire width 5 \mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:48" + wire \mb_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:47" + wire width 5 \me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" + wire width 4 \mode + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 40 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 41 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" + wire \rotator_arith + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" + wire \rotator_carry_out_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" + wire \rotator_clear_left + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" + wire \rotator_clear_right + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" + wire \rotator_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + wire width 5 \rotator_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" + wire \rotator_mb_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" + wire width 5 \rotator_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" + wire width 64 \rotator_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" + wire width 64 \rotator_result_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" + wire \rotator_right_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" + wire width 64 \rotator_rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" + wire width 7 \rotator_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" + wire \rotator_sign_ext_rs attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -324173,7 +307734,7 @@ module \mul_pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_mul_op__fn_unit + wire width 13 input 2 \sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -324189,19 +307750,35 @@ module \mul_pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_mul_op__fn_unit$19 + wire width 13 output 24 \sr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_mul_op__imm_data__data + wire width 64 input 3 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_mul_op__imm_data__data$20 + wire width 64 output 25 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__imm_data__ok + wire input 4 \sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__imm_data__ok$21 + wire output 26 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_mul_op__insn + wire width 2 input 11 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_mul_op__insn$29 + wire width 2 output 33 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 39 \sr_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -324277,7 +307854,7 @@ module \mul_pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_mul_op__insn_type + wire width 7 input 1 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -324353,51 +307930,338 @@ module \mul_pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_mul_op__insn_type$18 + wire width 7 output 23 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_32bit + wire input 10 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_32bit$27 + wire output 32 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_signed + wire input 15 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_signed$28 + wire output 37 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__oe + wire input 16 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__oe$24 + wire output 38 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__ok + wire input 7 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__ok$25 + wire output 29 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__ok + wire input 8 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__ok$23 + wire output 30 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__rc + wire input 12 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__rc$22 + wire output 34 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__write_cr0 + wire input 14 \sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__write_cr0$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \input_muxid$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so + wire output 36 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 43 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$32 + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \xer_so$19 + attribute \module_not_derived 1 + attribute \src "libresoc.v:146858.11-146873.4" + cell \rotator \rotator + connect \arith \rotator_arith + connect \carry_out_o \rotator_carry_out_o + connect \clear_left \rotator_clear_left + connect \clear_right \rotator_clear_right + connect \is_32bit \rotator_is_32bit + connect \mb \rotator_mb + connect \mb_extra \rotator_mb_extra + connect \me \rotator_me + connect \ra \rotator_ra + connect \result_o \rotator_result_o + connect \right_shift \rotator_right_shift + connect \rs \rotator_rs + connect \shift \rotator_shift + connect \sign_ext_rs \rotator_sign_ext_rs + end + attribute \src "libresoc.v:146548.7-146548.20" + process $proc$libresoc.v:146548$7352 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:146874.3-146908.6" + process $proc$libresoc.v:146874$7350 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:146875.5-146875.29" + switch \initial + attribute \src "libresoc.v:146875.9-146875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" + switch \sr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111100 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111101 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111000 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111001 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111010 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100000 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:146909.3-146939.6" + process $proc$libresoc.v:146909$7351 + assign { } { } + assign { } { } + assign $0\mode[3:0] $1\mode[3:0] + attribute \src "libresoc.v:146910.5-146910.29" + switch \initial + attribute \src "libresoc.v:146910.9-146910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" + switch \sr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111100 + assign { } { } + assign $1\mode[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111101 + assign { } { } + assign $1\mode[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111000 + assign { } { } + assign $1\mode[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111001 + assign { } { } + assign $1\mode[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111010 + assign { } { } + assign $1\mode[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100000 + assign { } { } + assign $1\mode[3:0] 4'1000 + case + assign $1\mode[3:0] 4'0000 + end + sync always + update \mode $0\mode[3:0] + end + connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$19 \xer_so + connect \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } + connect \o \rotator_result_o + connect { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode + connect \rotator_arith \sr_op__is_signed + connect \rotator_is_32bit \sr_op__is_32bit + connect \rotator_shift \rb [6:0] + connect \rotator_ra \ra + connect \rotator_rs \rc + connect \rotator_mb_extra \mb_extra + connect \rotator_mb \mb + connect \rotator_me \me + connect \mb_extra \sr_op__insn [5] + connect \me \sr_op__insn [5:1] + connect \mb \sr_op__insn [10:6] +end +attribute \src "libresoc.v:146961.1-147493.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" +attribute \generator "nMigen" +module \main$22 + attribute \src "libresoc.v:147400.3-147423.6" + wire $0\bc_taken[0:0] + attribute \src "libresoc.v:147279.3-147290.6" + wire width 64 $0\br_addr[63:0] + attribute \src "libresoc.v:147291.3-147317.6" + wire width 64 $0\br_imm_addr[63:0] + attribute \src "libresoc.v:147318.3-147336.6" + wire $0\br_taken[0:0] + attribute \src "libresoc.v:147372.3-147386.6" + wire $0\cr_bit[0:0] + attribute \src "libresoc.v:147450.3-147470.6" + wire width 64 $0\ctr_m[63:0] + attribute \src "libresoc.v:147424.3-147436.6" + wire width 64 $0\ctr_n[63:0] + attribute \src "libresoc.v:147387.3-147399.6" + wire $0\ctr_write[0:0] + attribute \src "libresoc.v:147471.3-147483.6" + wire $0\ctr_zero_bo1[0:0] + attribute \src "libresoc.v:147437.3-147449.6" + wire width 64 $0\fast1$10[63:0]$7385 + attribute \src "libresoc.v:147337.3-147351.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:147352.3-147361.6" + wire width 64 $0\fast2$11[63:0]$7377 + attribute \src "libresoc.v:147362.3-147371.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:146962.7-146962.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:147400.3-147423.6" + wire $1\bc_taken[0:0] + attribute \src "libresoc.v:147279.3-147290.6" + wire width 64 $1\br_addr[63:0] + attribute \src "libresoc.v:147291.3-147317.6" + wire width 64 $1\br_imm_addr[63:0] + attribute \src "libresoc.v:147318.3-147336.6" + wire $1\br_taken[0:0] + attribute \src "libresoc.v:147372.3-147386.6" + wire $1\cr_bit[0:0] + attribute \src "libresoc.v:147450.3-147470.6" + wire width 64 $1\ctr_m[63:0] + attribute \src "libresoc.v:147424.3-147436.6" + wire width 64 $1\ctr_n[63:0] + attribute \src "libresoc.v:147387.3-147399.6" + wire $1\ctr_write[0:0] + attribute \src "libresoc.v:147471.3-147483.6" + wire $1\ctr_zero_bo1[0:0] + attribute \src "libresoc.v:147437.3-147449.6" + wire width 64 $1\fast1$10[63:0]$7386 + attribute \src "libresoc.v:147337.3-147351.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:147352.3-147361.6" + wire width 64 $1\fast2$11[63:0]$7378 + attribute \src "libresoc.v:147362.3-147371.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:147400.3-147423.6" + wire $2\bc_taken[0:0] + attribute \src "libresoc.v:147291.3-147317.6" + wire width 64 $2\br_imm_addr[63:0] + attribute \src "libresoc.v:147450.3-147470.6" + wire width 64 $2\ctr_m[63:0] + attribute \src "libresoc.v:147263.18-147263.119" + wire width 65 $add$libresoc.v:147263$7355_Y + attribute \src "libresoc.v:147278.18-147278.113" + wire width 65 $add$libresoc.v:147278$7371_Y + attribute \src "libresoc.v:147270.18-147270.115" + wire $and$libresoc.v:147270$7362_Y + attribute \src "libresoc.v:147271.18-147271.117" + wire $and$libresoc.v:147271$7363_Y + attribute \src "libresoc.v:147277.18-147277.118" + wire $and$libresoc.v:147277$7370_Y + attribute \src "libresoc.v:147261.18-147261.120" + wire $eq$libresoc.v:147261$7353_Y + attribute \src "libresoc.v:147264.18-147264.111" + wire $eq$libresoc.v:147264$7356_Y + attribute \src "libresoc.v:147266.18-147266.111" + wire $eq$libresoc.v:147266$7358_Y + attribute \src "libresoc.v:147267.18-147267.111" + wire $eq$libresoc.v:147267$7359_Y + attribute \src "libresoc.v:147268.18-147268.109" + wire $eq$libresoc.v:147268$7360_Y + attribute \src "libresoc.v:147273.18-147273.98" + wire width 64 $extend$libresoc.v:147273$7365_Y + attribute \src "libresoc.v:147269.18-147269.104" + wire $not$libresoc.v:147269$7361_Y + attribute \src "libresoc.v:147276.18-147276.112" + wire $not$libresoc.v:147276$7369_Y + attribute \src "libresoc.v:147262.18-147262.116" + wire $or$libresoc.v:147262$7354_Y + attribute \src "libresoc.v:147265.18-147265.109" + wire $or$libresoc.v:147265$7357_Y + attribute \src "libresoc.v:147273.18-147273.98" + wire width 64 $pos$libresoc.v:147273$7366_Y + attribute \src "libresoc.v:147274.18-147274.103" + wire $reduce_or$libresoc.v:147274$7367_Y + attribute \src "libresoc.v:147272.18-147272.108" + wire width 65 $sub$libresoc.v:147272$7364_Y + attribute \src "libresoc.v:147275.18-147275.108" + wire $xor$libresoc.v:147275$7368_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + wire width 65 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + wire width 65 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + wire width 65 \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + wire width 65 \$36 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 64 \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" + wire width 65 \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" + wire width 65 \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:119" + wire \bc_taken + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" + wire width 2 \bi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:105" + wire width 5 \bo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" + wire width 64 \br_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87" + wire width 64 \br_imm_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 1 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 13 \br_op__cia$2 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -324413,7 +308277,7 @@ module \mul_pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul1_mul_op__fn_unit + wire width 13 input 3 \br_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -324429,19 +308293,19 @@ module \mul_pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul1_mul_op__fn_unit$35 + wire width 13 output 15 \br_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul1_mul_op__imm_data__data + wire width 64 input 5 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul1_mul_op__imm_data__data$36 + wire width 64 output 17 \br_op__imm_data__data$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__imm_data__ok + wire input 6 \br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__imm_data__ok$37 + wire output 18 \br_op__imm_data__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul1_mul_op__insn + wire width 32 input 4 \br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul1_mul_op__insn$45 + wire width 32 output 16 \br_op__insn$5 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -324517,7 +308381,7 @@ module \mul_pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul1_mul_op__insn_type + wire width 7 input 2 \br_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -324593,71 +308457,1070 @@ module \mul_pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul1_mul_op__insn_type$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__is_32bit$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__is_signed$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__oe__oe$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__oe__ok$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__rc__ok + wire width 7 output 14 \br_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__rc__ok$39 + wire input 8 \br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__rc__rc + wire output 20 \br_op__is_32bit$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__rc__rc$38 + wire input 7 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__write_cr0 + wire output 19 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" + wire \br_taken + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" + wire \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" + wire width 64 \ctr_m + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" + wire width 64 \ctr_n + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" + wire \ctr_write + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + wire \ctr_zero_bo1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 21 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \fast2_ok + attribute \src "libresoc.v:146962.7-146962.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 27 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 12 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 25 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + cell $add $add$libresoc.v:147263$7355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \br_imm_addr + connect \B \br_op__cia + connect \Y $add$libresoc.v:147263$7355_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" + cell $add $add$libresoc.v:147278$7371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \br_op__cia + connect \B 3'100 + connect \Y $add$libresoc.v:147278$7371_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $and $and$libresoc.v:147270$7362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \$29 + connect \Y $and$libresoc.v:147270$7362_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" + cell $and $and$libresoc.v:147271$7363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \cr_bit + connect \Y $and$libresoc.v:147271$7363_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $and $and$libresoc.v:147277$7370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [10] + connect \B \$44 + connect \Y $and$libresoc.v:147277$7370_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $eq $eq$libresoc.v:147261$7353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \br_op__insn_type + connect \B 7'0001000 + connect \Y $eq$libresoc.v:147261$7353_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $eq $eq$libresoc.v:147264$7356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \B \bo [3] + connect \Y $eq$libresoc.v:147264$7356_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + cell $eq $eq$libresoc.v:147266$7358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'0 + connect \Y $eq$libresoc.v:147266$7358_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" + cell $eq $eq$libresoc.v:147267$7359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'1 + connect \Y $eq$libresoc.v:147267$7359_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + cell $eq $eq$libresoc.v:147268$7360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:147268$7360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:147273$7365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \fast1 [31:0] + connect \Y $extend$libresoc.v:147273$7365_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $not $not$libresoc.v:147269$7361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \Y $not$libresoc.v:147269$7361_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $not $not$libresoc.v:147276$7369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [6] + connect \Y $not$libresoc.v:147276$7369_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $or $or$libresoc.v:147262$7354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [1] + connect \B \$12 + connect \Y $or$libresoc.v:147262$7354_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $or $or$libresoc.v:147265$7357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \bo [4] + connect \Y $or$libresoc.v:147265$7357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:147273$7366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:147273$7365_Y + connect \Y $pos$libresoc.v:147273$7366_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $reduce_or $reduce_or$libresoc.v:147274$7367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \ctr_n + connect \Y $reduce_or$libresoc.v:147274$7367_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + cell $sub $sub$libresoc.v:147272$7364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \fast1 + connect \B 1'1 + connect \Y $sub$libresoc.v:147272$7364_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $xor $xor$libresoc.v:147275$7368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [1] + connect \B \$40 + connect \Y $xor$libresoc.v:147275$7368_Y + end + attribute \src "libresoc.v:146962.7-146962.20" + process $proc$libresoc.v:146962$7389 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:147279.3-147290.6" + process $proc$libresoc.v:147279$7372 + assign { } { } + assign $0\br_addr[63:0] $1\br_addr[63:0] + attribute \src "libresoc.v:147280.5-147280.29" + switch \initial + attribute \src "libresoc.v:147280.9-147280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + switch \$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\br_addr[63:0] \br_imm_addr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\br_addr[63:0] \$16 [63:0] + end + sync always + update \br_addr $0\br_addr[63:0] + end + attribute \src "libresoc.v:147291.3-147317.6" + process $proc$libresoc.v:147291$7373 + assign { } { } + assign { } { } + assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] + attribute \src "libresoc.v:147292.5-147292.29" + switch \initial + attribute \src "libresoc.v:147292.9-147292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_imm_addr[63:0] $2\br_imm_addr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\br_imm_addr[63:0] { \fast1 [63:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\br_imm_addr[63:0] { \fast2 [63:2] 2'00 } + end + case + assign $1\br_imm_addr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \br_imm_addr $0\br_imm_addr[63:0] + end + attribute \src "libresoc.v:147318.3-147336.6" + process $proc$libresoc.v:147318$7374 + assign { } { } + assign { } { } + assign $0\br_taken[0:0] $1\br_taken[0:0] + attribute \src "libresoc.v:147319.5-147319.29" + switch \initial + attribute \src "libresoc.v:147319.9-147319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_taken[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + case + assign $1\br_taken[0:0] 1'0 + end + sync always + update \br_taken $0\br_taken[0:0] + end + attribute \src "libresoc.v:147337.3-147351.6" + process $proc$libresoc.v:147337$7375 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:147338.5-147338.29" + switch \initial + attribute \src "libresoc.v:147338.9-147338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:147352.3-147361.6" + process $proc$libresoc.v:147352$7376 + assign { } { } + assign { } { } + assign $0\fast2$11[63:0]$7377 $1\fast2$11[63:0]$7378 + attribute \src "libresoc.v:147353.5-147353.29" + switch \initial + attribute \src "libresoc.v:147353.9-147353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2$11[63:0]$7378 \$48 [63:0] + case + assign $1\fast2$11[63:0]$7378 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$11 $0\fast2$11[63:0]$7377 + end + attribute \src "libresoc.v:147362.3-147371.6" + process $proc$libresoc.v:147362$7379 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "libresoc.v:147363.5-147363.29" + switch \initial + attribute \src "libresoc.v:147363.9-147363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:147372.3-147386.6" + process $proc$libresoc.v:147372$7380 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "libresoc.v:147373.5-147373.29" + switch \initial + attribute \src "libresoc.v:147373.9-147373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" + switch \bi + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [3] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $1\cr_bit[0:0] \cr_a [0] + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "libresoc.v:147387.3-147399.6" + process $proc$libresoc.v:147387$7381 + assign { } { } + assign { } { } + assign $0\ctr_write[0:0] $1\ctr_write[0:0] + attribute \src "libresoc.v:147388.5-147388.29" + switch \initial + attribute \src "libresoc.v:147388.9-147388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_write[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_write[0:0] 1'1 + end + sync always + update \ctr_write $0\ctr_write[0:0] + end + attribute \src "libresoc.v:147400.3-147423.6" + process $proc$libresoc.v:147400$7382 + assign { } { } + assign { } { } + assign $0\bc_taken[0:0] $1\bc_taken[0:0] + attribute \src "libresoc.v:147401.5-147401.29" + switch \initial + attribute \src "libresoc.v:147401.9-147401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\bc_taken[0:0] \$21 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\bc_taken[0:0] $2\bc_taken[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + switch { \$27 \$25 \$23 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\bc_taken[0:0] \$31 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\bc_taken[0:0] \$33 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\bc_taken[0:0] \ctr_zero_bo1 + case + assign $2\bc_taken[0:0] 1'0 + end + end + sync always + update \bc_taken $0\bc_taken[0:0] + end + attribute \src "libresoc.v:147424.3-147436.6" + process $proc$libresoc.v:147424$7383 + assign { } { } + assign { } { } + assign $0\ctr_n[63:0] $1\ctr_n[63:0] + attribute \src "libresoc.v:147425.5-147425.29" + switch \initial + attribute \src "libresoc.v:147425.9-147425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_n[63:0] \$35 [63:0] + end + sync always + update \ctr_n $0\ctr_n[63:0] + end + attribute \src "libresoc.v:147437.3-147449.6" + process $proc$libresoc.v:147437$7384 + assign { } { } + assign { } { } + assign $0\fast1$10[63:0]$7385 $1\fast1$10[63:0]$7386 + attribute \src "libresoc.v:147438.5-147438.29" + switch \initial + attribute \src "libresoc.v:147438.9-147438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\fast1$10[63:0]$7386 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\fast1$10[63:0]$7386 \ctr_n + end + sync always + update \fast1$10 $0\fast1$10[63:0]$7385 + end + attribute \src "libresoc.v:147450.3-147470.6" + process $proc$libresoc.v:147450$7387 + assign { } { } + assign { } { } + assign $0\ctr_m[63:0] $1\ctr_m[63:0] + attribute \src "libresoc.v:147451.5-147451.29" + switch \initial + attribute \src "libresoc.v:147451.9-147451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_m[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_m[63:0] $2\ctr_m[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" + switch \br_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ctr_m[63:0] \$38 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ctr_m[63:0] \fast1 + end + end + sync always + update \ctr_m $0\ctr_m[63:0] + end + attribute \src "libresoc.v:147471.3-147483.6" + process $proc$libresoc.v:147471$7388 + assign { } { } + assign { } { } + assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] + attribute \src "libresoc.v:147472.5-147472.29" + switch \initial + attribute \src "libresoc.v:147472.9-147472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_zero_bo1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_zero_bo1[0:0] \$42 + end + sync always + update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] + end + connect \$12 $eq$libresoc.v:147261$7353_Y + connect \$14 $or$libresoc.v:147262$7354_Y + connect \$17 $add$libresoc.v:147263$7355_Y + connect \$19 $eq$libresoc.v:147264$7356_Y + connect \$21 $or$libresoc.v:147265$7357_Y + connect \$23 $eq$libresoc.v:147266$7358_Y + connect \$25 $eq$libresoc.v:147267$7359_Y + connect \$27 $eq$libresoc.v:147268$7360_Y + connect \$29 $not$libresoc.v:147269$7361_Y + connect \$31 $and$libresoc.v:147270$7362_Y + connect \$33 $and$libresoc.v:147271$7363_Y + connect \$36 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"/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" + wire width 64 \a_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:142" + wire width 64 \b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:139" + wire width 64 \b_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161" + wire \equal attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul1_rb + wire width 64 input 12 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 26 \fast1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul1_rb$47 + wire width 64 input 13 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 28 \fast2$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" + wire \gt_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" + wire \gt_u + attribute \src "libresoc.v:147498.7-147498.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" + wire \lt_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" + wire \lt_u + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 32 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 34 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 14 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 30 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul1_xer_so + wire width 64 input 10 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul1_xer_so$48 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" + wire width 64 input 11 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + wire \should_trap + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134" + wire width 5 \to + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + wire width 5 \trap_bits attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \mul_op__fn_unit + wire width 64 input 5 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \trap_op__cia$6 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -324673,7 +309536,7 @@ module \mul_pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 26 \mul_op__fn_unit$3 + wire width 13 input 2 \trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -324689,109 +309552,11 @@ module \mul_pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 27 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 28 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 16 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 36 \mul_op__insn$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$64 + wire width 13 output 16 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 32 input 3 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \mul_op__insn_type + wire width 32 output 17 \trap_op__insn$4 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -324867,7 +309632,7 @@ module \mul_pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 25 \mul_op__insn_type$2 + wire width 7 input 1 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -324943,597 +309708,821 @@ module \mul_pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 34 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 35 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 31 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 32 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$58 + wire width 7 output 15 \trap_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 30 \mul_op__rc__ok$7 + wire input 6 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$next + wire output 20 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \mul_op__rc__rc + wire width 8 input 9 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$57 + wire width 8 output 23 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 29 \mul_op__rc__rc$6 + wire width 64 input 4 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$next + wire width 64 output 18 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \mul_op__write_cr0 + wire width 13 input 8 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 33 \mul_op__write_cr0$10 + wire width 13 output 22 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$61 + wire width 8 input 7 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire output 20 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \neg_res$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \neg_res$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire output 21 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \neg_res32$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \neg_res32$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 23 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 22 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 17 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 37 \ra$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 18 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 38 \rb$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 39 \xer_so$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:157126$7936 + wire width 8 output 21 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" + cell $add $add$libresoc.v:147882$7406 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$49 - connect \B \p_ready_o - connect \Y $and$libresoc.v:157126$7936_Y + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \trap_op__cia + connect \B 3'100 + connect \Y $add$libresoc.v:147882$7406_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:157165.14-157198.4" - cell \input$95 \input - connect \mul_op__fn_unit \input_mul_op__fn_unit - connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 - connect \mul_op__imm_data__data \input_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 - connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 - connect \mul_op__insn \input_mul_op__insn - connect \mul_op__insn$13 \input_mul_op__insn$29 - connect \mul_op__insn_type \input_mul_op__insn_type - connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 - connect \mul_op__is_32bit \input_mul_op__is_32bit - connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 - connect \mul_op__is_signed \input_mul_op__is_signed - connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 - connect \mul_op__oe__oe \input_mul_op__oe__oe - connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 - connect \mul_op__oe__ok \input_mul_op__oe__ok - connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 - connect \mul_op__rc__ok \input_mul_op__rc__ok - connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 - connect \mul_op__rc__rc \input_mul_op__rc__rc - connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 - connect \mul_op__write_cr0 \input_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$17 - connect \ra \input_ra - connect \ra$14 \input_ra$30 - connect \rb \input_rb - connect \rb$15 \input_rb$31 - connect \xer_so \input_xer_so - connect \xer_so$16 \input_xer_so$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $and $and$libresoc.v:147876$7399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \trap_bits + connect \B \to + connect \Y $and$libresoc.v:147876$7399_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:157199.8-157234.4" - cell \mul1 \mul1 - connect \mul_op__fn_unit \mul1_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 - connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 - connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 - connect \mul_op__insn \mul1_mul_op__insn - connect \mul_op__insn$13 \mul1_mul_op__insn$45 - connect \mul_op__insn_type \mul1_mul_op__insn_type - connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 - connect \mul_op__is_32bit \mul1_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 - connect \mul_op__is_signed \mul1_mul_op__is_signed - connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 - connect \mul_op__oe__oe \mul1_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 - connect \mul_op__oe__ok \mul1_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 - connect \mul_op__rc__ok \mul1_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 - connect \mul_op__rc__rc \mul1_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 - connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 - connect \muxid \mul1_muxid - connect \muxid$1 \mul1_muxid$33 - connect \neg_res \mul1_neg_res - connect \neg_res32 \mul1_neg_res32 - connect \ra \mul1_ra - connect \ra$14 \mul1_ra$46 - connect \rb \mul1_rb - connect \rb$15 \mul1_rb$47 - connect \xer_so \mul1_xer_so - connect \xer_so$16 \mul1_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" + cell $and $and$libresoc.v:147884$7408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 2'10 + connect \Y $and$libresoc.v:147884$7408_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:157235.10-157238.4" - cell \n$94 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + cell $and $and$libresoc.v:147886$7410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 1'1 + connect \Y $and$libresoc.v:147886$7410_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:157239.10-157242.4" - cell \p$93 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" + cell $and $and$libresoc.v:147888$7412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 4'1000 + connect \Y $and$libresoc.v:147888$7412_Y end - attribute \src "libresoc.v:156195.7-156195.20" - process $proc$libresoc.v:156195$8009 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + cell $and $and$libresoc.v:147890$7414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$libresoc.v:147890$7414_Y end - attribute \src "libresoc.v:156702.14-156702.40" - process $proc$libresoc.v:156702$8010 - assign { } { } - assign $1\mul_op__fn_unit[12:0] 13'0000000000000 - sync always - sync init - update \mul_op__fn_unit $1\mul_op__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + cell $and $and$libresoc.v:147892$7416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 8'10000000 + connect \Y $and$libresoc.v:147892$7416_Y end - attribute \src "libresoc.v:156739.14-156739.59" - process $proc$libresoc.v:156739$8011 - assign { } { } - assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + cell $and $and$libresoc.v:147894$7418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$libresoc.v:147894$7418_Y end - attribute \src "libresoc.v:156748.7-156748.34" - process $proc$libresoc.v:156748$8012 - assign { } { } - assign $1\mul_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $and $and$libresoc.v:147900$7425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \B \$81 + connect \Y $and$libresoc.v:147900$7425_Y end - attribute \src "libresoc.v:156757.14-156757.34" - process $proc$libresoc.v:156757$8013 - assign { } { } - assign $1\mul_op__insn[31:0] 0 - sync always - sync init - update \mul_op__insn $1\mul_op__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + cell $and $and$libresoc.v:147905$7430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$89 + connect \B \$91 + connect \Y $and$libresoc.v:147905$7430_Y end - attribute \src "libresoc.v:156840.13-156840.38" - process $proc$libresoc.v:156840$8014 - assign { } { } - assign $1\mul_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \mul_op__insn_type $1\mul_op__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" + cell $eq $eq$libresoc.v:147875$7398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $eq$libresoc.v:147875$7398_Y end - attribute \src "libresoc.v:156997.7-156997.30" - process $proc$libresoc.v:156997$8015 - assign { } { } - assign $1\mul_op__is_32bit[0:0] 1'0 - sync always - sync init - update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" + cell $eq $eq$libresoc.v:147883$7407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \B 1'0 + connect \Y $eq$libresoc.v:147883$7407_Y end - attribute \src "libresoc.v:157006.7-157006.31" - process $proc$libresoc.v:157006$8016 - assign { } { } - assign $1\mul_op__is_signed[0:0] 1'0 - sync always - sync init - update \mul_op__is_signed $1\mul_op__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" + cell $eq $eq$libresoc.v:147897$7422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn_type + connect \B 7'1001000 + connect \Y $eq$libresoc.v:147897$7422_Y end - attribute \src "libresoc.v:157015.7-157015.28" - process $proc$libresoc.v:157015$8017 - assign { } { } - assign $1\mul_op__oe__oe[0:0] 1'0 - sync always - sync init - update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" + cell $eq $eq$libresoc.v:147898$7423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$libresoc.v:147898$7423_Y end - attribute \src "libresoc.v:157024.7-157024.28" - process $proc$libresoc.v:157024$8018 - assign { } { } - assign $1\mul_op__oe__ok[0:0] 1'0 - sync always - sync init - update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $eq $eq$libresoc.v:147899$7424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ra [34:32] + connect \B 3'000 + connect \Y $eq$libresoc.v:147899$7424_Y end - attribute \src "libresoc.v:157033.7-157033.28" - process $proc$libresoc.v:157033$8019 - assign { } { } - assign $1\mul_op__rc__ok[0:0] 1'0 - sync always - sync init - update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" + cell $eq $eq$libresoc.v:147903$7428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$libresoc.v:147903$7428_Y end - attribute \src "libresoc.v:157042.7-157042.28" - process $proc$libresoc.v:157042$8020 - assign { } { } - assign $1\mul_op__rc__rc[0:0] 1'0 - sync always - sync init - update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + cell $eq $eq$libresoc.v:147904$7429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fast2 [34:32] + connect \B 3'000 + connect \Y $eq$libresoc.v:147904$7429_Y end - attribute \src "libresoc.v:157051.7-157051.31" - process $proc$libresoc.v:157051$8021 - assign { } { } - assign $1\mul_op__write_cr0[0:0] 1'0 - sync always - sync init - update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:147869$7390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \ra [31:0] + connect \Y $extend$libresoc.v:147869$7390_Y end - attribute \src "libresoc.v:157060.13-157060.25" - process $proc$libresoc.v:157060$8022 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:147870$7392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \rb [31:0] + connect \Y $extend$libresoc.v:147870$7392_Y end - attribute \src "libresoc.v:157075.7-157075.21" - process $proc$libresoc.v:157075$8023 - assign { } { } - assign $1\neg_res[0:0] 1'0 - sync always - sync init - update \neg_res $1\neg_res[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $pos $extend$libresoc.v:147881$7404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \Y_WIDTH 64 + connect \A \$36 + connect \Y $extend$libresoc.v:147881$7404_Y end - attribute \src "libresoc.v:157082.7-157082.23" - process $proc$libresoc.v:157082$8024 - assign { } { } - assign $1\neg_res32[0:0] 1'0 - sync always - sync init - update \neg_res32 $1\neg_res32[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$libresoc.v:147896$7420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \trap_op__msr + connect \Y $extend$libresoc.v:147896$7420_Y end - attribute \src "libresoc.v:157096.7-157096.20" - process $proc$libresoc.v:157096$8025 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" + cell $gt $gt$libresoc.v:147872$7395 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $gt$libresoc.v:147872$7395_Y end - attribute \src "libresoc.v:157101.14-157101.39" - process $proc$libresoc.v:157101$8026 - assign { } { } - assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ra $1\ra[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" + cell $gt $gt$libresoc.v:147874$7397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $gt$libresoc.v:147874$7397_Y end - attribute \src "libresoc.v:157110.14-157110.39" - process $proc$libresoc.v:157110$8027 - assign { } { } - assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \rb $1\rb[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + cell $lt $lt$libresoc.v:147871$7394 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $lt$libresoc.v:147871$7394_Y end - attribute \src "libresoc.v:157119.7-157119.20" - process $proc$libresoc.v:157119$8028 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" + cell $lt $lt$libresoc.v:147873$7396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $lt$libresoc.v:147873$7396_Y end - attribute \src "libresoc.v:157127.3-157128.35" - process $proc$libresoc.v:157127$7937 - assign { } { } - assign $0\neg_res32[0:0] \neg_res32$next - sync posedge \coresync_clk - update \neg_res32 $0\neg_res32[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + cell $not $not$libresoc.v:147901$7426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [60] + connect \Y $not$libresoc.v:147901$7426_Y end - attribute \src "libresoc.v:157129.3-157130.31" - process $proc$libresoc.v:157129$7938 - assign { } { } - assign $0\neg_res[0:0] \neg_res$next - sync posedge \coresync_clk - update \neg_res $0\neg_res[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + cell $not $not$libresoc.v:147902$7427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn [9] + connect \Y $not$libresoc.v:147902$7427_Y end - attribute \src "libresoc.v:157131.3-157132.29" - process $proc$libresoc.v:157131$7939 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $or $or$libresoc.v:147879$7402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \B \$31 + connect \Y $or$libresoc.v:147879$7402_Y end - attribute \src "libresoc.v:157133.3-157134.21" - process $proc$libresoc.v:157133$7940 - assign { } { } - assign $0\rb[63:0] \rb$next - sync posedge \coresync_clk - update \rb $0\rb[63:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:147869$7391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:147869$7390_Y + connect \Y $pos$libresoc.v:147869$7391_Y end - attribute \src "libresoc.v:157135.3-157136.21" - process $proc$libresoc.v:157135$7941 - assign { } { } - assign $0\ra[63:0] \ra$next - sync posedge \coresync_clk - update \ra $0\ra[63:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:147870$7393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:147870$7392_Y + connect \Y $pos$libresoc.v:147870$7393_Y end - attribute \src "libresoc.v:157137.3-157138.51" - process $proc$libresoc.v:157137$7942 - assign { } { } - assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next - sync posedge \coresync_clk - update \mul_op__insn_type $0\mul_op__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $pos $pos$libresoc.v:147881$7405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:147881$7404_Y + connect \Y $pos$libresoc.v:147881$7405_Y end - attribute \src "libresoc.v:157139.3-157140.47" - process $proc$libresoc.v:157139$7943 - assign { } { } - assign $0\mul_op__fn_unit[12:0] \mul_op__fn_unit$next - sync posedge \coresync_clk - update \mul_op__fn_unit $0\mul_op__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$libresoc.v:147896$7421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:147896$7420_Y + connect \Y $pos$libresoc.v:147896$7421_Y end - attribute \src "libresoc.v:157141.3-157142.61" - process $proc$libresoc.v:157141$7944 - assign { } { } - assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next - sync posedge \coresync_clk - update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $reduce_or $reduce_or$libresoc.v:147877$7400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $reduce_or$libresoc.v:147877$7400_Y end - attribute \src "libresoc.v:157143.3-157144.57" - process $proc$libresoc.v:157143$7945 - assign { } { } - assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next - sync posedge \coresync_clk - update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $reduce_or $reduce_or$libresoc.v:147878$7401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \Y $reduce_or$libresoc.v:147878$7401_Y end - attribute \src "libresoc.v:157145.3-157146.45" - process $proc$libresoc.v:157145$7946 - assign { } { } - assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next - sync posedge \coresync_clk - update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:147885$7409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$45 + connect \Y $reduce_or$libresoc.v:147885$7409_Y end - attribute \src "libresoc.v:157147.3-157148.45" - process $proc$libresoc.v:157147$7947 - assign { } { } - assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next - sync posedge \coresync_clk - update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:147887$7411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \Y $reduce_or$libresoc.v:147887$7411_Y end - attribute \src "libresoc.v:157149.3-157150.45" - process $proc$libresoc.v:157149$7948 - assign { } { } - assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next - sync posedge \coresync_clk - update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:147889$7413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \Y $reduce_or$libresoc.v:147889$7413_Y end - attribute \src "libresoc.v:157151.3-157152.45" - process $proc$libresoc.v:157151$7949 - assign { } { } - assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next - sync posedge \coresync_clk - update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:147891$7415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$57 + connect \Y $reduce_or$libresoc.v:147891$7415_Y end - attribute \src "libresoc.v:157153.3-157154.51" - process $proc$libresoc.v:157153$7950 - assign { } { } - assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next - sync posedge \coresync_clk - update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:147893$7417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$64 + connect \Y $reduce_or$libresoc.v:147893$7417_Y end - attribute \src "libresoc.v:157155.3-157156.49" - process $proc$libresoc.v:157155$7951 - assign { } { } - assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next - sync posedge \coresync_clk - update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:147895$7419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$72 + connect \Y $reduce_or$libresoc.v:147895$7419_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $sshl $sshl$libresoc.v:147880$7403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 20 + connect \A \trap_op__trapaddr + connect \B 3'100 + connect \Y $sshl$libresoc.v:147880$7403_Y end - attribute \src "libresoc.v:157157.3-157158.51" - process $proc$libresoc.v:157157$7952 + attribute \src "libresoc.v:147498.7-147498.20" + process $proc$libresoc.v:147498$7491 assign { } { } - assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next - sync posedge \coresync_clk - update \mul_op__is_signed $0\mul_op__is_signed[0:0] + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:157159.3-157160.41" - process $proc$libresoc.v:157159$7953 + attribute \src "libresoc.v:147906.3-147917.6" + process $proc$libresoc.v:147906$7431 assign { } { } - assign $0\mul_op__insn[31:0] \mul_op__insn$next - sync posedge \coresync_clk - update \mul_op__insn $0\mul_op__insn[31:0] + assign $0\a_s[63:0] $1\a_s[63:0] + attribute \src "libresoc.v:147907.5-147907.29" + switch \initial + attribute \src "libresoc.v:147907.9-147907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_s[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a_s[63:0] \ra + end + sync always + update \a_s $0\a_s[63:0] end - attribute \src "libresoc.v:157161.3-157162.27" - process $proc$libresoc.v:157161$7954 + attribute \src "libresoc.v:147918.3-147949.6" + process $proc$libresoc.v:147918$7432 assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:157163.3-157164.29" - process $proc$libresoc.v:157163$7955 assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + assign $0\nia[63:0] $1\nia[63:0] + attribute \src "libresoc.v:147919.5-147919.29" + switch \initial + attribute \src "libresoc.v:147919.9-147919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia[63:0] $2\nia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia[63:0] \$35 + case + assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia[63:0] { \fast1 [63:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000110000000000 + case + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \nia $0\nia[63:0] end - attribute \src "libresoc.v:157243.3-157260.6" - process $proc$libresoc.v:157243$7956 - assign { } { } + attribute \src "libresoc.v:147950.3-147981.6" + process $proc$libresoc.v:147950$7433 assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7957 $2\r_busy$next[0:0]$7959 - attribute \src "libresoc.v:157244.5-157244.29" + assign $0\nia_ok[0:0] $1\nia_ok[0:0] + attribute \src "libresoc.v:147951.5-147951.29" switch \initial - attribute \src "libresoc.v:157244.9-157244.17" + attribute \src "libresoc.v:147951.9-147951.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 7'0111111 assign { } { } - assign $1\r_busy$next[0:0]$7958 1'1 + assign $1\nia_ok[0:0] $2\nia_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok[0:0] 1'1 + case + assign $2\nia_ok[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'1001000 , 7'1001010 + assign $1\nia_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\nia_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 assign { } { } - assign $1\r_busy$next[0:0]$7958 1'0 - case - assign $1\r_busy$next[0:0]$7958 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\nia_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 7'1001001 assign { } { } - assign $2\r_busy$next[0:0]$7959 1'0 + assign $1\nia_ok[0:0] 1'1 case - assign $2\r_busy$next[0:0]$7959 $1\r_busy$next[0:0]$7958 + assign $1\nia_ok[0:0] 1'0 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7957 + update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:157261.3-157273.6" - process $proc$libresoc.v:157261$7960 + attribute \src "libresoc.v:147982.3-148013.6" + process $proc$libresoc.v:147982$7434 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$7961 $1\muxid$next[1:0]$7962 - attribute \src "libresoc.v:157262.5-157262.29" + assign $0\fast1$11[63:0]$7435 $1\fast1$11[63:0]$7436 + attribute \src "libresoc.v:147983.5-147983.29" switch \initial - attribute \src "libresoc.v:157262.9-157262.17" + attribute \src "libresoc.v:147983.9-147983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 7'0111111 assign { } { } - assign $1\muxid$next[1:0]$7962 \muxid$52 + assign $1\fast1$11[63:0]$7436 $2\fast1$11[63:0]$7437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1$11[63:0]$7437 \trap_op__cia + case + assign $2\fast1$11[63:0]$7437 64'0000000000000000000000000000000000000000000000000000000000000000 + end attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'1001000 , 7'1001010 + assign $1\fast1$11[63:0]$7436 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast1$11[63:0]$7436 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast1$11[63:0]$7436 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 assign { } { } - assign $1\muxid$next[1:0]$7962 \muxid$52 + assign $1\fast1$11[63:0]$7436 \$39 [63:0] case - assign $1\muxid$next[1:0]$7962 \muxid + assign $1\fast1$11[63:0]$7436 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \muxid$next $0\muxid$next[1:0]$7961 + update \fast1$11 $0\fast1$11[63:0]$7435 end - attribute \src "libresoc.v:157274.3-157309.6" - process $proc$libresoc.v:157274$7963 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:148014.3-148045.6" + process $proc$libresoc.v:148014$7438 assign { } { } assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:148015.5-148015.29" + switch \initial + attribute \src "libresoc.v:148015.9-148015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1_ok[0:0] 1'1 + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:148046.3-148128.6" + process $proc$libresoc.v:148046$7439 assign { } { } assign { } { } + assign $0\fast2$12[63:0]$7440 $1\fast2$12[63:0]$7441 + attribute \src "libresoc.v:148047.5-148047.29" + switch \initial + attribute \src "libresoc.v:148047.9-148047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2$12[63:0]$7441 $2\fast2$12[63:0]$7442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { $2\fast2$12[63:0]$7442 [29] $2\fast2$12[63:0]$7442 [27] $2\fast2$12[63:0]$7442 [21] } 3'000 + assign $2\fast2$12[63:0]$7442 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7442 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7442 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7442 [17] $3\fast2$12[17:17]$7443 + assign { } { } + assign $2\fast2$12[63:0]$7442 [20] $5\fast2$12[20:20]$7445 + assign $2\fast2$12[63:0]$7442 [16] $6\fast2$12[16:16]$7446 + assign $2\fast2$12[63:0]$7442 [18] $7\fast2$12[19:18]$7447 [0] + assign $2\fast2$12[63:0]$7442 [28] $8\fast2$12[28:28]$7448 + assign $2\fast2$12[63:0]$7442 [30] $9\fast2$12[30:30]$7449 + assign $2\fast2$12[63:0]$7442 [19] $10\fast2$12[19:19]$7450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fast2$12[17:17]$7443 1'1 + case + assign $3\fast2$12[17:17]$7443 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fast2$12[18:18]$7444 1'1 + case + assign $4\fast2$12[18:18]$7444 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fast2$12[20:20]$7445 1'1 + case + assign $5\fast2$12[20:20]$7445 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" + switch \$52 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fast2$12[16:16]$7446 1'1 + case + assign $6\fast2$12[16:16]$7446 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + switch \$56 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $9\fast2$12[30:30]$7449 \trapexc_$signal + assign $8\fast2$12[28:28]$7448 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7447 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7447 [0] \trapexc_$signal$62 + case + assign $7\fast2$12[19:18]$7447 { 1'0 $4\fast2$12[18:18]$7444 } + assign $8\fast2$12[28:28]$7448 1'0 + assign $9\fast2$12[30:30]$7449 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fast2$12[19:19]$7450 1'1 + case + assign $10\fast2$12[19:19]$7450 $7\fast2$12[19:18]$7447 [1] + end + case + assign $2\fast2$12[63:0]$7442 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2$12[63:0]$7441 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast2$12[63:0]$7441 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast2$12[63:0]$7441 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { $1\fast2$12[63:0]$7441 [30:27] $1\fast2$12[63:0]$7441 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7441 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7441 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7441 [63:31] \trap_op__msr [63:31] + case + assign $1\fast2$12[63:0]$7441 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$12 $0\fast2$12[63:0]$7440 + end + attribute \src "libresoc.v:148129.3-148160.6" + process $proc$libresoc.v:148129$7451 assign { } { } assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "libresoc.v:148130.5-148130.29" + switch \initial + attribute \src "libresoc.v:148130.9-148130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok[0:0] 1'1 + case + assign $2\fast2_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:148161.3-148188.6" + process $proc$libresoc.v:148161$7452 assign { } { } assign { } { } assign { } { } @@ -325544,53 +310533,30 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$next[12:0]$7964 $1\mul_op__fn_unit$next[12:0]$7976 assign { } { } assign { } { } - assign $0\mul_op__insn$next[31:0]$7967 $1\mul_op__insn$next[31:0]$7979 - assign $0\mul_op__insn_type$next[6:0]$7968 $1\mul_op__insn_type$next[6:0]$7980 - assign $0\mul_op__is_32bit$next[0:0]$7969 $1\mul_op__is_32bit$next[0:0]$7981 - assign $0\mul_op__is_signed$next[0:0]$7970 $1\mul_op__is_signed$next[0:0]$7982 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$next[0:0]$7975 $1\mul_op__write_cr0$next[0:0]$7987 - assign $0\mul_op__imm_data__data$next[63:0]$7965 $2\mul_op__imm_data__data$next[63:0]$7988 - assign $0\mul_op__imm_data__ok$next[0:0]$7966 $2\mul_op__imm_data__ok$next[0:0]$7989 - assign $0\mul_op__oe__oe$next[0:0]$7971 $2\mul_op__oe__oe$next[0:0]$7990 - assign $0\mul_op__oe__ok$next[0:0]$7972 $2\mul_op__oe__ok$next[0:0]$7991 - assign $0\mul_op__rc__ok$next[0:0]$7973 $2\mul_op__rc__ok$next[0:0]$7992 - assign $0\mul_op__rc__rc$next[0:0]$7974 $2\mul_op__rc__rc$next[0:0]$7993 - attribute \src "libresoc.v:157275.5-157275.29" + assign $0\trapexc_$signal[0:0]$7453 $1\trapexc_$signal[0:0]$7461 + assign $0\trapexc_$signal$60[0:0]$7454 $1\trapexc_$signal$60[0:0]$7462 + assign $0\trapexc_$signal$61[0:0]$7455 $1\trapexc_$signal$61[0:0]$7463 + assign $0\trapexc_$signal$62[0:0]$7456 $1\trapexc_$signal$62[0:0]$7464 + assign $0\trapexc_$signal$67[0:0]$7457 $1\trapexc_$signal$67[0:0]$7465 + assign $0\trapexc_$signal$68[0:0]$7458 $1\trapexc_$signal$68[0:0]$7466 + assign $0\trapexc_$signal$69[0:0]$7459 $1\trapexc_$signal$69[0:0]$7467 + assign $0\trapexc_$signal$70[0:0]$7460 $1\trapexc_$signal$70[0:0]$7468 + attribute \src "libresoc.v:148162.5-148162.29" switch \initial - attribute \src "libresoc.v:157275.9-157275.17" + attribute \src "libresoc.v:148162.9-148162.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$next[31:0]$7979 $1\mul_op__is_signed$next[0:0]$7982 $1\mul_op__is_32bit$next[0:0]$7981 $1\mul_op__write_cr0$next[0:0]$7987 $1\mul_op__oe__ok$next[0:0]$7984 $1\mul_op__oe__oe$next[0:0]$7983 $1\mul_op__rc__ok$next[0:0]$7985 $1\mul_op__rc__rc$next[0:0]$7986 $1\mul_op__imm_data__ok$next[0:0]$7978 $1\mul_op__imm_data__data$next[63:0]$7977 $1\mul_op__fn_unit$next[12:0]$7976 $1\mul_op__insn_type$next[6:0]$7980 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } + case 7'0111111 assign { } { } assign { } { } assign { } { } @@ -325599,655 +310565,907 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7979 $1\mul_op__is_signed$next[0:0]$7982 $1\mul_op__is_32bit$next[0:0]$7981 $1\mul_op__write_cr0$next[0:0]$7987 $1\mul_op__oe__ok$next[0:0]$7984 $1\mul_op__oe__oe$next[0:0]$7983 $1\mul_op__rc__ok$next[0:0]$7985 $1\mul_op__rc__rc$next[0:0]$7986 $1\mul_op__imm_data__ok$next[0:0]$7978 $1\mul_op__imm_data__data$next[63:0]$7977 $1\mul_op__fn_unit$next[12:0]$7976 $1\mul_op__insn_type$next[6:0]$7980 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign $1\trapexc_$signal[0:0]$7461 $2\trapexc_$signal[0:0]$7469 + assign $1\trapexc_$signal$60[0:0]$7462 $2\trapexc_$signal$60[0:0]$7470 + assign $1\trapexc_$signal$61[0:0]$7463 $2\trapexc_$signal$61[0:0]$7471 + assign $1\trapexc_$signal$62[0:0]$7464 $2\trapexc_$signal$62[0:0]$7472 + assign $1\trapexc_$signal$67[0:0]$7465 $2\trapexc_$signal$67[0:0]$7473 + assign $1\trapexc_$signal$68[0:0]$7466 $2\trapexc_$signal$68[0:0]$7474 + assign $1\trapexc_$signal$69[0:0]$7467 $2\trapexc_$signal$69[0:0]$7475 + assign $1\trapexc_$signal$70[0:0]$7468 $2\trapexc_$signal$70[0:0]$7476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\trapexc_$signal[0:0]$7469 $3\trapexc_$signal[0:0]$7477 + assign $2\trapexc_$signal$60[0:0]$7470 $3\trapexc_$signal$60[0:0]$7478 + assign $2\trapexc_$signal$61[0:0]$7471 $3\trapexc_$signal$61[0:0]$7479 + assign $2\trapexc_$signal$62[0:0]$7472 $3\trapexc_$signal$62[0:0]$7480 + assign $2\trapexc_$signal$67[0:0]$7473 $3\trapexc_$signal$67[0:0]$7481 + assign $2\trapexc_$signal$68[0:0]$7474 $3\trapexc_$signal$68[0:0]$7482 + assign $2\trapexc_$signal$69[0:0]$7475 $3\trapexc_$signal$69[0:0]$7483 + assign $2\trapexc_$signal$70[0:0]$7476 $3\trapexc_$signal$70[0:0]$7484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\trapexc_$signal$70[0:0]$7484 $3\trapexc_$signal$62[0:0]$7480 $3\trapexc_$signal$60[0:0]$7478 $3\trapexc_$signal$61[0:0]$7479 $3\trapexc_$signal[0:0]$7477 $3\trapexc_$signal$69[0:0]$7483 $3\trapexc_$signal$68[0:0]$7482 $3\trapexc_$signal$67[0:0]$7481 } \trap_op__ldst_exc + case + assign $3\trapexc_$signal[0:0]$7477 1'0 + assign $3\trapexc_$signal$60[0:0]$7478 1'0 + assign $3\trapexc_$signal$61[0:0]$7479 1'0 + assign $3\trapexc_$signal$62[0:0]$7480 1'0 + assign $3\trapexc_$signal$67[0:0]$7481 1'0 + assign $3\trapexc_$signal$68[0:0]$7482 1'0 + assign $3\trapexc_$signal$69[0:0]$7483 1'0 + assign $3\trapexc_$signal$70[0:0]$7484 1'0 + end + case + assign $2\trapexc_$signal[0:0]$7469 1'0 + assign $2\trapexc_$signal$60[0:0]$7470 1'0 + assign $2\trapexc_$signal$61[0:0]$7471 1'0 + assign $2\trapexc_$signal$62[0:0]$7472 1'0 + assign $2\trapexc_$signal$67[0:0]$7473 1'0 + assign $2\trapexc_$signal$68[0:0]$7474 1'0 + assign $2\trapexc_$signal$69[0:0]$7475 1'0 + assign $2\trapexc_$signal$70[0:0]$7476 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7461 1'0 + assign $1\trapexc_$signal$60[0:0]$7462 1'0 + assign $1\trapexc_$signal$61[0:0]$7463 1'0 + assign $1\trapexc_$signal$62[0:0]$7464 1'0 + assign $1\trapexc_$signal$67[0:0]$7465 1'0 + assign $1\trapexc_$signal$68[0:0]$7466 1'0 + assign $1\trapexc_$signal$69[0:0]$7467 1'0 + assign $1\trapexc_$signal$70[0:0]$7468 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7453 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7454 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7455 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7456 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7457 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7458 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7459 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7460 + end + attribute \src "libresoc.v:148189.3-148200.6" + process $proc$libresoc.v:148189$7485 + assign { } { } + assign $0\b_s[63:0] $1\b_s[63:0] + attribute \src "libresoc.v:148190.5-148190.29" + switch \initial + attribute \src "libresoc.v:148190.9-148190.17" + case 1'1 case - assign $1\mul_op__fn_unit$next[12:0]$7976 \mul_op__fn_unit - assign $1\mul_op__imm_data__data$next[63:0]$7977 \mul_op__imm_data__data - assign $1\mul_op__imm_data__ok$next[0:0]$7978 \mul_op__imm_data__ok - assign $1\mul_op__insn$next[31:0]$7979 \mul_op__insn - assign $1\mul_op__insn_type$next[6:0]$7980 \mul_op__insn_type - assign $1\mul_op__is_32bit$next[0:0]$7981 \mul_op__is_32bit - assign $1\mul_op__is_signed$next[0:0]$7982 \mul_op__is_signed - assign $1\mul_op__oe__oe$next[0:0]$7983 \mul_op__oe__oe - assign $1\mul_op__oe__ok$next[0:0]$7984 \mul_op__oe__ok - assign $1\mul_op__rc__ok$next[0:0]$7985 \mul_op__rc__ok - assign $1\mul_op__rc__rc$next[0:0]$7986 \mul_op__rc__rc - assign $1\mul_op__write_cr0$next[0:0]$7987 \mul_op__write_cr0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\mul_op__imm_data__data$next[63:0]$7988 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$next[0:0]$7989 1'0 - assign $2\mul_op__rc__rc$next[0:0]$7993 1'0 - assign $2\mul_op__rc__ok$next[0:0]$7992 1'0 - assign $2\mul_op__oe__oe$next[0:0]$7990 1'0 - assign $2\mul_op__oe__ok$next[0:0]$7991 1'0 + assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" case - assign $2\mul_op__imm_data__data$next[63:0]$7988 $1\mul_op__imm_data__data$next[63:0]$7977 - assign $2\mul_op__imm_data__ok$next[0:0]$7989 $1\mul_op__imm_data__ok$next[0:0]$7978 - assign $2\mul_op__oe__oe$next[0:0]$7990 $1\mul_op__oe__oe$next[0:0]$7983 - assign $2\mul_op__oe__ok$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7984 - assign $2\mul_op__rc__ok$next[0:0]$7992 $1\mul_op__rc__ok$next[0:0]$7985 - assign $2\mul_op__rc__rc$next[0:0]$7993 $1\mul_op__rc__rc$next[0:0]$7986 + assign { } { } + assign $1\b_s[63:0] \rb end sync always - update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[12:0]$7964 - update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7965 - update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7966 - update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7967 - update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7968 - update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7969 - update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7970 - update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7971 - update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7972 - update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7973 - update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7974 - update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7975 + update \b_s $0\b_s[63:0] end - attribute \src "libresoc.v:157310.3-157322.6" - process $proc$libresoc.v:157310$7994 + attribute \src "libresoc.v:148201.3-148369.6" + process $proc$libresoc.v:148201$7486 + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\ra$next[63:0]$7995 $1\ra$next[63:0]$7996 - attribute \src "libresoc.v:157311.5-157311.29" + assign $0\msr[63:0] $1\msr[63:0] + assign $0\msr_ok[0:0] $1\msr_ok[0:0] + attribute \src "libresoc.v:148202.5-148202.29" switch \initial - attribute \src "libresoc.v:157311.9-157311.17" + attribute \src "libresoc.v:148202.9-148202.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 7'0111111 assign { } { } - assign $1\ra$next[63:0]$7996 \ra$65 + assign { } { } + assign $1\msr[63:0] $2\msr[63:0] + assign $1\msr_ok[0:0] $2\msr_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\msr[63:0] [62:59] $2\msr[63:0] [57:33] $2\msr[63:0] [31:26] $2\msr[63:0] [24] $2\msr[63:0] [22:16] $2\msr[63:0] [12] $2\msr[63:0] [7:6] $2\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $2\msr[63:0] [63] 1'1 + assign $2\msr[63:0] [15] 1'0 + assign $2\msr[63:0] [14] 1'0 + assign $2\msr[63:0] [5] 1'0 + assign $2\msr[63:0] [4] 1'0 + assign $2\msr[63:0] [1] 1'0 + assign $2\msr[63:0] [0] 1'1 + assign $2\msr[63:0] [11] 1'0 + assign $2\msr[63:0] [8] 1'0 + assign $2\msr[63:0] [23] 1'0 + assign $2\msr[63:0] [32] 1'0 + assign $2\msr[63:0] [25] 1'0 + assign $2\msr[63:0] [13] 1'0 + assign $2\msr[63:0] [3] 1'0 + assign $2\msr[63:0] [10] 1'0 + assign $2\msr[63:0] [9] 1'0 + assign $2\msr[63:0] [58] 1'0 + assign $2\msr_ok[0:0] 1'1 + case + assign $2\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr_ok[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'1001000 , 7'1001010 + assign { } { } + assign { } { } + assign $1\msr[63:0] [0] \$75 [0] + assign $1\msr[63:0] [11:1] $3\msr[11:1] + assign $1\msr[63:0] [59:13] $4\msr[59:13] + assign $1\msr[63:0] [63:61] $5\msr[63:61] + assign $1\msr[63:0] [12] $12\msr[12:12] + assign $1\msr[63:0] [60] $13\msr[60:60] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" + switch \trap_op__insn [21] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\msr[11:1] [10:1] \$75 [11:2] + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$75 [59:16] \$75 [14:13] } + assign $5\msr[63:61] \$75 [63:61] + assign $3\msr[11:1] [0] \ra [1] + assign $4\msr[59:13] [2] \ra [15] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { $3\msr[11:1] [10:5] $3\msr[11:1] [2:0] } { $6\msr[11:1] [10:5] $6\msr[11:1] [2:0] } + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { $7\msr[59:13] [46:3] $7\msr[59:13] [1:0] } + assign $5\msr[63:61] $8\msr[63:61] + assign $3\msr[11:1] [4:3] $10\msr[5:4] + assign $4\msr[59:13] [2] $11\msr[15:15] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $6\msr[11:1] \ra [11:1] + assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } + assign $8\msr[63:61] \ra [63:61] + assign $7\msr[59:13] [21:19] $9\msr[34:32] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\msr[34:32] \trap_op__msr [34:32] + case + assign $9\msr[34:32] \ra [34:32] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $7\msr[59:13] [46:19] \$75 [59:32] + assign $8\msr[63:61] \$75 [63:61] + assign $6\msr[11:1] \ra [11:1] + assign $7\msr[59:13] [18:0] \ra [31:13] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" + switch $7\msr[59:13] [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $11\msr[15:15] 1'1 + assign $10\msr[5:4] [1] 1'1 + assign $10\msr[5:4] [0] 1'1 + case + assign $10\msr[5:4] $6\msr[11:1] [4:3] + assign $11\msr[15:15] $7\msr[59:13] [2] + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $13\msr[60:60] \trap_op__msr [60] + assign $12\msr[12:12] \trap_op__msr [12] + case + assign $12\msr[12:12] \$75 [12] + assign $13\msr[60:60] \$75 [60] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { $1\msr[63:0] [30:27] $1\msr[63:0] [21:16] } 10'0000000000 + assign { } { } + assign { $1\msr[63:0] [14:13] $1\msr[63:0] [11:6] $1\msr[63:0] [3:0] } { \fast2 [14:13] \fast2 [11:6] \fast2 [3:0] } + assign $1\msr[63:0] [26:22] \fast2 [26:22] + assign { $1\msr[63:0] [63:35] $1\msr[63:0] [31] } { \fast2 [63:35] \fast2 [31] } + assign $1\msr[63:0] [12] $14\msr[12:12] + assign $1\msr[63:0] [5:4] $16\msr[5:4] + assign $1\msr[63:0] [15] $17\msr[15:15] + assign $1\msr[63:0] [34:32] $18\msr[34:32] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\msr[12:12] $15\msr[12:12] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" + switch \trap_op__msr [60] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\msr[12:12] \fast2 [12] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $15\msr[12:12] \trap_op__msr [12] + end + case + assign $14\msr[12:12] \fast2 [12] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" + switch \fast2 [14] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $17\msr[15:15] 1'1 + assign $16\msr[5:4] [1] 1'1 + assign $16\msr[5:4] [0] 1'1 + case + assign $16\msr[5:4] \fast2 [5:4] + assign $17\msr[15:15] \fast2 [15] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\msr[34:32] \trap_op__msr [34:32] + case + assign $18\msr[34:32] \fast2 [34:32] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 assign { } { } - assign $1\ra$next[63:0]$7996 \ra$65 + assign { } { } + assign { $1\msr[63:0] [62:59] $1\msr[63:0] [57:33] $1\msr[63:0] [31:26] $1\msr[63:0] [24] $1\msr[63:0] [22:16] $1\msr[63:0] [12] $1\msr[63:0] [7:6] $1\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $1\msr[63:0] [63] 1'1 + assign $1\msr[63:0] [15] 1'0 + assign $1\msr[63:0] [14] 1'0 + assign $1\msr[63:0] [5] 1'0 + assign $1\msr[63:0] [4] 1'0 + assign $1\msr[63:0] [1] 1'0 + assign $1\msr[63:0] [0] 1'1 + assign $1\msr[63:0] [11] 1'0 + assign $1\msr[63:0] [8] 1'0 + assign $1\msr[63:0] [23] 1'0 + assign $1\msr[63:0] [32] 1'0 + assign $1\msr[63:0] [25] 1'0 + assign $1\msr[63:0] [13] 1'0 + assign $1\msr[63:0] [3] 1'0 + assign $1\msr[63:0] [10] 1'0 + assign $1\msr[63:0] [9] 1'0 + assign $1\msr[63:0] [58] 1'0 + assign $1\msr_ok[0:0] 1'1 case - assign $1\ra$next[63:0]$7996 \ra + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 end sync always - update \ra$next $0\ra$next[63:0]$7995 + update \msr $0\msr[63:0] + update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:157323.3-157335.6" - process $proc$libresoc.v:157323$7997 + attribute \src "libresoc.v:148370.3-148388.6" + process $proc$libresoc.v:148370$7487 assign { } { } assign { } { } - assign $0\rb$next[63:0]$7998 $1\rb$next[63:0]$7999 - attribute \src "libresoc.v:157324.5-157324.29" + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:148371.5-148371.29" switch \initial - attribute \src "libresoc.v:157324.9-157324.17" + attribute \src "libresoc.v:148371.9-148371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\rb$next[63:0]$7999 \rb$66 + case 7'0111111 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'1001000 , 7'1001010 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 assign { } { } - assign $1\rb$next[63:0]$7999 \rb$66 + assign $1\o[63:0] \trap_op__msr case - assign $1\rb$next[63:0]$7999 \rb + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \rb$next $0\rb$next[63:0]$7998 + update \o $0\o[63:0] end - attribute \src "libresoc.v:157336.3-157348.6" - process $proc$libresoc.v:157336$8000 + attribute \src "libresoc.v:148389.3-148407.6" + process $proc$libresoc.v:148389$7488 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$8001 $1\xer_so$next[0:0]$8002 - attribute \src "libresoc.v:157337.5-157337.29" + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:148390.5-148390.29" switch \initial - attribute \src "libresoc.v:157337.9-157337.17" + attribute \src "libresoc.v:148390.9-148390.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\xer_so$next[0:0]$8002 \xer_so$67 + case 7'0111111 + assign $1\o_ok[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'1001000 , 7'1001010 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 assign { } { } - assign $1\xer_so$next[0:0]$8002 \xer_so$67 + assign $1\o_ok[0:0] 1'1 case - assign $1\xer_so$next[0:0]$8002 \xer_so + assign $1\o_ok[0:0] 1'0 end sync always - update \xer_so$next $0\xer_so$next[0:0]$8001 + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:157349.3-157361.6" - process $proc$libresoc.v:157349$8003 + attribute \src "libresoc.v:148408.3-148419.6" + process $proc$libresoc.v:148408$7489 assign { } { } - assign { } { } - assign $0\neg_res$next[0:0]$8004 $1\neg_res$next[0:0]$8005 - attribute \src "libresoc.v:157350.5-157350.29" + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:148409.5-148409.29" switch \initial - attribute \src "libresoc.v:157350.9-157350.17" + attribute \src "libresoc.v:148409.9-148409.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\neg_res$next[0:0]$8005 \neg_res$68 + assign $1\a[63:0] \$13 attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\neg_res$next[0:0]$8005 \neg_res$68 case - assign $1\neg_res$next[0:0]$8005 \neg_res + assign { } { } + assign $1\a[63:0] \ra end sync always - update \neg_res$next $0\neg_res$next[0:0]$8004 + update \a $0\a[63:0] end - attribute \src "libresoc.v:157362.3-157374.6" - process $proc$libresoc.v:157362$8006 + attribute \src "libresoc.v:148420.3-148431.6" + process $proc$libresoc.v:148420$7490 assign { } { } - assign { } { } - assign $0\neg_res32$next[0:0]$8007 $1\neg_res32$next[0:0]$8008 - attribute \src "libresoc.v:157363.5-157363.29" + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:148421.5-148421.29" switch \initial - attribute \src "libresoc.v:157363.9-157363.17" + attribute \src "libresoc.v:148421.9-148421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\neg_res32$next[0:0]$8008 \neg_res32$69 + assign $1\b[63:0] \$15 attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\neg_res32$next[0:0]$8008 \neg_res32$69 case - assign $1\neg_res32$next[0:0]$8008 \neg_res32 + assign { } { } + assign $1\b[63:0] \rb end sync always - update \neg_res32$next $0\neg_res32$next[0:0]$8007 + update \b $0\b[63:0] end - connect \$50 $and$libresoc.v:157126$7936_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \neg_res32$69 \mul1_neg_res32 - connect \neg_res$68 \mul1_neg_res - connect \xer_so$67 \mul1_xer_so$48 - connect \rb$66 \mul1_rb$47 - connect \ra$65 \mul1_ra$46 - connect { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } - connect \muxid$52 \mul1_muxid$33 - connect \p_valid_i_p_ready_o \$50 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$49 \p_valid_i - connect \mul1_xer_so \input_xer_so$32 - connect \mul1_rb \input_rb$31 - connect \mul1_ra \input_ra$30 - connect { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } - connect \mul1_muxid \input_muxid$17 - connect \input_xer_so \xer_so$16 - connect \input_rb \rb$15 - connect \input_ra \ra$14 - connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } - connect \input_muxid \muxid$1 + connect \$13 $pos$libresoc.v:147869$7391_Y + connect \$15 $pos$libresoc.v:147870$7393_Y + connect \$17 $lt$libresoc.v:147871$7394_Y + connect \$19 $gt$libresoc.v:147872$7395_Y + connect \$21 $lt$libresoc.v:147873$7396_Y + connect \$23 $gt$libresoc.v:147874$7397_Y + connect \$25 $eq$libresoc.v:147875$7398_Y + connect \$28 $and$libresoc.v:147876$7399_Y + connect \$27 $reduce_or$libresoc.v:147877$7400_Y + connect \$31 $reduce_or$libresoc.v:147878$7401_Y + connect \$33 $or$libresoc.v:147879$7402_Y + connect \$36 $sshl$libresoc.v:147880$7403_Y + connect \$35 $pos$libresoc.v:147881$7405_Y + connect \$40 $add$libresoc.v:147882$7406_Y + connect \$42 $eq$libresoc.v:147883$7407_Y + connect \$45 $and$libresoc.v:147884$7408_Y + connect \$44 $reduce_or$libresoc.v:147885$7409_Y + connect \$49 $and$libresoc.v:147886$7410_Y + connect \$48 $reduce_or$libresoc.v:147887$7411_Y + connect \$53 $and$libresoc.v:147888$7412_Y + connect \$52 $reduce_or$libresoc.v:147889$7413_Y + connect \$57 $and$libresoc.v:147890$7414_Y + connect \$56 $reduce_or$libresoc.v:147891$7415_Y + connect \$64 $and$libresoc.v:147892$7416_Y + connect \$63 $reduce_or$libresoc.v:147893$7417_Y + connect \$72 $and$libresoc.v:147894$7418_Y + connect \$71 $reduce_or$libresoc.v:147895$7419_Y + connect \$75 $pos$libresoc.v:147896$7421_Y + connect \$77 $eq$libresoc.v:147897$7422_Y + connect \$79 $eq$libresoc.v:147898$7423_Y + connect \$81 $eq$libresoc.v:147899$7424_Y + connect \$83 $and$libresoc.v:147900$7425_Y + connect \$85 $not$libresoc.v:147901$7426_Y + connect \$87 $not$libresoc.v:147902$7427_Y + connect \$89 $eq$libresoc.v:147903$7428_Y + connect \$91 $eq$libresoc.v:147904$7429_Y + connect \$93 $and$libresoc.v:147905$7430_Y + connect \$39 \$40 + connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \muxid$1 \muxid + connect \should_trap \$33 + connect \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } + connect \equal \$25 + connect \gt_u \$23 + connect \lt_u \$21 + connect \gt_s \$19 + connect \lt_s \$17 + connect \to \trap_op__insn [25:21] end -attribute \src "libresoc.v:157401.1-158311.10" +attribute \src "libresoc.v:148447.1-149192.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" -module \mul_pipe2 - attribute \src "libresoc.v:157402.7-157402.20" +module \main$51 + attribute \src "libresoc.v:149159.3-149169.6" + wire width 32 $0\a32[31:0] + attribute \src "libresoc.v:149104.3-149114.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:149082.3-149092.6" + wire width 64 $0\bpermd_rb[63:0] + attribute \src "libresoc.v:149071.3-149081.6" + wire width 64 $0\bpermd_rs[63:0] + attribute \src "libresoc.v:149060.3-149070.6" + wire width 64 $0\clz_sig_in[63:0] + attribute \src "libresoc.v:149170.3-149188.6" + wire width 64 $0\cntz_i[63:0] + attribute \src "libresoc.v:149148.3-149158.6" + wire $0\count_right[0:0] + attribute \src "libresoc.v:148448.7-148448.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158205.3-158240.6" - wire width 13 $0\mul_op__fn_unit$3$next[12:0]$8072 - attribute \src "libresoc.v:158103.3-158104.53" - wire width 13 $0\mul_op__fn_unit$3[12:0]$8040 - attribute \src "libresoc.v:157687.14-157687.44" - wire width 13 $0\mul_op__fn_unit$3[12:0]$8116 - attribute \src "libresoc.v:158205.3-158240.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8073 - attribute \src "libresoc.v:158105.3-158106.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8042 - attribute \src "libresoc.v:157712.14-157712.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8118 - attribute \src "libresoc.v:158205.3-158240.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8074 - attribute \src "libresoc.v:158107.3-158108.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8044 - attribute \src "libresoc.v:157721.7-157721.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8120 - attribute \src "libresoc.v:158205.3-158240.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8075 - attribute \src "libresoc.v:158123.3-158124.49" - wire width 32 $0\mul_op__insn$13[31:0]$8060 - attribute \src "libresoc.v:157728.14-157728.39" - wire width 32 $0\mul_op__insn$13[31:0]$8122 - attribute \src "libresoc.v:158205.3-158240.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8076 - attribute \src "libresoc.v:158101.3-158102.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$8038 - attribute \src "libresoc.v:157885.13-157885.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8124 - attribute \src "libresoc.v:158205.3-158240.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8077 - attribute \src "libresoc.v:158119.3-158120.57" - wire $0\mul_op__is_32bit$11[0:0]$8056 - attribute \src "libresoc.v:157968.7-157968.35" - wire $0\mul_op__is_32bit$11[0:0]$8126 - attribute \src "libresoc.v:158205.3-158240.6" - wire $0\mul_op__is_signed$12$next[0:0]$8078 - attribute \src "libresoc.v:158121.3-158122.59" - wire $0\mul_op__is_signed$12[0:0]$8058 - attribute \src "libresoc.v:157977.7-157977.36" - wire $0\mul_op__is_signed$12[0:0]$8128 - attribute \src "libresoc.v:158205.3-158240.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8079 - attribute \src "libresoc.v:158113.3-158114.51" - wire $0\mul_op__oe__oe$8[0:0]$8050 - attribute \src "libresoc.v:157988.7-157988.32" - wire $0\mul_op__oe__oe$8[0:0]$8130 - attribute \src "libresoc.v:158205.3-158240.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8080 - attribute \src "libresoc.v:158115.3-158116.51" - wire $0\mul_op__oe__ok$9[0:0]$8052 - attribute \src "libresoc.v:157997.7-157997.32" - wire $0\mul_op__oe__ok$9[0:0]$8132 - attribute \src "libresoc.v:158205.3-158240.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8081 - attribute \src "libresoc.v:158111.3-158112.51" - wire $0\mul_op__rc__ok$7[0:0]$8048 - attribute \src "libresoc.v:158006.7-158006.32" - wire $0\mul_op__rc__ok$7[0:0]$8134 - attribute \src "libresoc.v:158205.3-158240.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8082 - attribute \src "libresoc.v:158109.3-158110.51" - wire $0\mul_op__rc__rc$6[0:0]$8046 - attribute \src "libresoc.v:158015.7-158015.32" - wire $0\mul_op__rc__rc$6[0:0]$8136 - attribute \src "libresoc.v:158205.3-158240.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8083 - attribute \src "libresoc.v:158117.3-158118.59" - wire $0\mul_op__write_cr0$10[0:0]$8054 - attribute \src "libresoc.v:158022.7-158022.36" - wire $0\mul_op__write_cr0$10[0:0]$8138 - attribute \src "libresoc.v:158192.3-158204.6" - wire width 2 $0\muxid$1$next[1:0]$8069 - attribute \src "libresoc.v:158125.3-158126.33" - wire width 2 $0\muxid$1[1:0]$8062 - attribute \src "libresoc.v:158031.13-158031.29" - wire width 2 $0\muxid$1[1:0]$8140 - attribute \src "libresoc.v:158267.3-158279.6" - wire $0\neg_res$15$next[0:0]$8109 - attribute \src "libresoc.v:158095.3-158096.39" - wire $0\neg_res$15[0:0]$8033 - attribute \src "libresoc.v:158046.7-158046.26" - wire $0\neg_res$15[0:0]$8142 - attribute \src "libresoc.v:158280.3-158292.6" - wire $0\neg_res32$16$next[0:0]$8112 - attribute \src "libresoc.v:158093.3-158094.43" - wire $0\neg_res32$16[0:0]$8031 - attribute \src "libresoc.v:158055.7-158055.28" - wire $0\neg_res32$16[0:0]$8144 - attribute \src "libresoc.v:158241.3-158253.6" - wire width 129 $0\o$next[128:0]$8103 - attribute \src "libresoc.v:158099.3-158100.19" - wire width 129 $0\o[128:0] - attribute \src "libresoc.v:158174.3-158191.6" - wire $0\r_busy$next[0:0]$8065 - attribute \src "libresoc.v:158127.3-158128.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:158254.3-158266.6" - wire $0\xer_so$14$next[0:0]$8106 - attribute \src "libresoc.v:158097.3-158098.37" - wire $0\xer_so$14[0:0]$8035 - attribute \src "libresoc.v:158087.7-158087.25" - wire $0\xer_so$14[0:0]$8148 - attribute \src "libresoc.v:158205.3-158240.6" - wire width 13 $1\mul_op__fn_unit$3$next[12:0]$8084 - attribute \src "libresoc.v:158205.3-158240.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8085 - attribute \src "libresoc.v:158205.3-158240.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8086 - attribute \src "libresoc.v:158205.3-158240.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8087 - attribute \src "libresoc.v:158205.3-158240.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8088 - attribute \src "libresoc.v:158205.3-158240.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8089 - attribute \src "libresoc.v:158205.3-158240.6" - wire $1\mul_op__is_signed$12$next[0:0]$8090 - attribute \src "libresoc.v:158205.3-158240.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8091 - attribute \src "libresoc.v:158205.3-158240.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8092 - attribute \src "libresoc.v:158205.3-158240.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8093 - attribute \src "libresoc.v:158205.3-158240.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8094 - attribute \src "libresoc.v:158205.3-158240.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8095 - attribute \src "libresoc.v:158192.3-158204.6" - wire width 2 $1\muxid$1$next[1:0]$8070 - attribute \src "libresoc.v:158267.3-158279.6" - wire $1\neg_res$15$next[0:0]$8110 - attribute \src "libresoc.v:158280.3-158292.6" - wire $1\neg_res32$16$next[0:0]$8113 - attribute \src "libresoc.v:158241.3-158253.6" - wire width 129 $1\o$next[128:0]$8104 - attribute \src "libresoc.v:158062.15-158062.57" - wire width 129 $1\o[128:0] - attribute \src "libresoc.v:158174.3-158191.6" - wire $1\r_busy$next[0:0]$8066 - attribute \src "libresoc.v:158076.7-158076.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:158254.3-158266.6" - wire $1\xer_so$14$next[0:0]$8107 - attribute \src "libresoc.v:158205.3-158240.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8096 - attribute \src "libresoc.v:158205.3-158240.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8097 - attribute \src "libresoc.v:158205.3-158240.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8098 - attribute \src "libresoc.v:158205.3-158240.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8099 - attribute \src "libresoc.v:158205.3-158240.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8100 - attribute \src "libresoc.v:158205.3-158240.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8101 - attribute \src "libresoc.v:158174.3-158191.6" - wire $2\r_busy$next[0:0]$8067 - attribute \src "libresoc.v:158092.18-158092.118" - wire $and$libresoc.v:158092$8029_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:157402.7-157402.15" - wire \initial - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul2_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul2_mul_op__fn_unit$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul2_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul2_mul_op__imm_data__data$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__imm_data__ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul2_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul2_mul_op__insn$29 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28" + wire width 64 \b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" + wire width 64 \bpermd_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" + wire width 64 \bpermd_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" + wire width 64 \bpermd_rs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" + wire width 7 \clz_lz + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" + wire width 64 \clz_sig_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" + wire width 64 \cntz_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" + wire \count_right + attribute \src "libresoc.v:148448.7-148448.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__write_cr0$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \mul2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \mul2_muxid$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \mul2_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \mul2_neg_res$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \mul2_neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \mul2_neg_res32$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul2_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul2_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul2_xer_so$30 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \mul_op__fn_unit + wire width 4 output 39 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -326263,9 +311481,7 @@ module \mul_pipe2 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 26 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$3$next + wire width 13 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -326281,107 +311497,31 @@ module \mul_pipe2 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 27 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__imm_data__ok + wire width 13 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$40 + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \mul_op__imm_data__ok$5 + wire width 64 output 25 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$5$next + wire input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \mul_op__insn + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 36 \mul_op__insn$13 + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$13$next + wire width 2 output 33 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$48 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \mul_op__insn_type + wire width 32 output 40 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -326457,9 +311597,7 @@ module \mul_pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 25 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$2$next + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -326535,1022 +311673,1576 @@ module \mul_pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \mul_op__is_signed$12 + wire width 7 output 23 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$12$next + wire input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$47 + wire output 31 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__oe__oe + wire input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$43 + wire output 34 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \mul_op__oe__oe$8 + wire input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$8$next + wire output 37 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \mul_op__oe__ok + wire input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$44 + wire output 38 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \mul_op__oe__ok$9 + wire input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$9$next + wire output 29 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__rc__ok + wire input 8 \logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$42 + wire output 30 \logical_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \mul_op__rc__ok$7 + wire input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$7$next + wire output 36 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__rc__rc + wire input 6 \logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$41 + wire output 28 \logical_op__rc__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \mul_op__rc__rc$6 + wire input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$6$next + wire output 27 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \mul_op__write_cr0 + wire input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \mul_op__write_cr0$10 + wire output 35 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$10$next + wire input 10 \logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 24 \muxid$1 + wire output 32 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$1$next + wire width 2 input 44 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 23 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 22 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire input 20 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire output 39 \neg_res$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \neg_res$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \neg_res$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire input 21 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire output 40 \neg_res32$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \neg_res32$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \neg_res32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 output 37 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 19 \xer_so + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 41 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" + wire \par0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" + wire \par1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" + wire width 64 \popcount_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" + wire width 64 \popcount_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" + wire width 64 \popcount_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 38 \xer_so$14 + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$14$next + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:158092$8029 + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" + cell $and $and$libresoc.v:148952$7538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $and$libresoc.v:148952$7538_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148911$7492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:148911$7492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148912$7493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:148912$7493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148913$7494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:148913$7494_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148914$7495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:148914$7495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148915$7496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:148915$7496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148916$7497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:148916$7497_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148917$7498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:148917$7498_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148918$7499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:148918$7499_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148919$7500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:148919$7500_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148920$7501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:148920$7501_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148921$7502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:148921$7502_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148922$7503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:148922$7503_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148923$7504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:148923$7504_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148924$7505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:148924$7505_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148925$7506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:148925$7506_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148926$7507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:148926$7507_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148927$7508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:148927$7508_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148928$7509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:148928$7509_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148929$7510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:148929$7510_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148930$7511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:148930$7511_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148931$7512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:148931$7512_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148932$7513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:148932$7513_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148933$7514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:148933$7514_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148934$7515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:148934$7515_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148935$7516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:148935$7516_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148936$7517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:148936$7517_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148937$7518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:148937$7518_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148938$7519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:148938$7519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + cell $eq $eq$libresoc.v:148939$7520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$33 - connect \B \p_ready_o - connect \Y $and$libresoc.v:158092$8029_Y + connect \A \logical_op__data_len [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:148939$7520_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:158129.8-158165.4" - cell \mul2 \mul2 - connect \mul_op__fn_unit \mul2_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 - connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 - connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 - connect \mul_op__insn \mul2_mul_op__insn - connect \mul_op__insn$13 \mul2_mul_op__insn$29 - connect \mul_op__insn_type \mul2_mul_op__insn_type - connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 - connect \mul_op__is_32bit \mul2_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 - connect \mul_op__is_signed \mul2_mul_op__is_signed - connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 - connect \mul_op__oe__oe \mul2_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 - connect \mul_op__oe__ok \mul2_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 - connect \mul_op__rc__ok \mul2_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 - connect \mul_op__rc__rc \mul2_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 - connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 - connect \muxid \mul2_muxid - connect \muxid$1 \mul2_muxid$17 - connect \neg_res \mul2_neg_res - connect \neg_res$15 \mul2_neg_res$31 - connect \neg_res32 \mul2_neg_res32 - connect \neg_res32$16 \mul2_neg_res32$32 - connect \o \mul2_o - connect \ra \mul2_ra - connect \rb \mul2_rb - connect \xer_so \mul2_xer_so - connect \xer_so$14 \mul2_xer_so$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148955$7541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:148955$7541_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:158166.10-158169.4" - cell \n$97 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148956$7542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:148956$7542_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:158170.10-158173.4" - cell \p$96 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148957$7543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:148957$7543_Y end - attribute \src "libresoc.v:157402.7-157402.20" - process $proc$libresoc.v:157402$8114 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148958$7544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:148958$7544_Y end - attribute \src "libresoc.v:157687.14-157687.44" - process $proc$libresoc.v:157687$8115 - assign { } { } - assign $0\mul_op__fn_unit$3[12:0]$8116 13'0000000000000 - sync always - sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148959$7545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:148959$7545_Y end - attribute \src "libresoc.v:157712.14-157712.63" - process $proc$libresoc.v:157712$8117 - assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8118 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148960$7546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:148960$7546_Y end - attribute \src "libresoc.v:157721.7-157721.38" - process $proc$libresoc.v:157721$8119 - assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8120 1'0 - sync always - sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148961$7547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:148961$7547_Y end - attribute \src "libresoc.v:157728.14-157728.39" - process $proc$libresoc.v:157728$8121 - assign { } { } - assign $0\mul_op__insn$13[31:0]$8122 0 - sync always - sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148962$7548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:148962$7548_Y end - attribute \src "libresoc.v:157885.13-157885.42" - process $proc$libresoc.v:157885$8123 - assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8124 7'0000000 - sync always - sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148963$7549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:148963$7549_Y end - attribute \src "libresoc.v:157968.7-157968.35" - process $proc$libresoc.v:157968$8125 - assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8126 1'0 - sync always - sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148964$7550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:148964$7550_Y end - attribute \src "libresoc.v:157977.7-157977.36" - process $proc$libresoc.v:157977$8127 - assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8128 1'0 - sync always - sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148965$7551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:148965$7551_Y end - attribute \src "libresoc.v:157988.7-157988.32" - process $proc$libresoc.v:157988$8129 - assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8130 1'0 - sync always - sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148966$7552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:148966$7552_Y end - attribute \src "libresoc.v:157997.7-157997.32" - process $proc$libresoc.v:157997$8131 - assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8132 1'0 - sync always - sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148967$7553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:148967$7553_Y end - attribute \src "libresoc.v:158006.7-158006.32" - process $proc$libresoc.v:158006$8133 - assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8134 1'0 - sync always - sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148968$7554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:148968$7554_Y end - attribute \src "libresoc.v:158015.7-158015.32" - process $proc$libresoc.v:158015$8135 - assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8136 1'0 - sync always - sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148969$7555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:148969$7555_Y end - attribute \src "libresoc.v:158022.7-158022.36" - process $proc$libresoc.v:158022$8137 - assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8138 1'0 - sync always - sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148970$7556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:148970$7556_Y end - attribute \src "libresoc.v:158031.13-158031.29" - process $proc$libresoc.v:158031$8139 - assign { } { } - assign $0\muxid$1[1:0]$8140 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148971$7557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:148971$7557_Y end - attribute \src "libresoc.v:158046.7-158046.26" - process $proc$libresoc.v:158046$8141 - assign { } { } - assign $0\neg_res$15[0:0]$8142 1'0 - sync always - sync init - update \neg_res$15 $0\neg_res$15[0:0]$8142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148972$7558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:148972$7558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148973$7559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:148973$7559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148974$7560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:148974$7560_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148975$7561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:148975$7561_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148976$7562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:148976$7562_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148977$7563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:148977$7563_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148978$7564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:148978$7564_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148979$7565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:148979$7565_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148980$7566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:148980$7566_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148981$7567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:148981$7567_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148982$7568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:148982$7568_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148983$7569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:148983$7569_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148984$7570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:148984$7570_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148985$7571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:148985$7571_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148986$7572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:148986$7572_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148987$7573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:148987$7573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148988$7574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:148988$7574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148989$7575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:148989$7575_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:148990$7576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:148990$7576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $extend$libresoc.v:148941$7522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 64 + connect \A \$158 + connect \Y $extend$libresoc.v:148941$7522_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" + cell $pos $extend$libresoc.v:148943$7525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \Y $extend$libresoc.v:148943$7525_Y end - attribute \src "libresoc.v:158055.7-158055.28" - process $proc$libresoc.v:158055$8143 - assign { } { } - assign $0\neg_res32$16[0:0]$8144 1'0 - sync always - sync init - update \neg_res32$16 $0\neg_res32$16[0:0]$8144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $extend$libresoc.v:148945$7528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \$166 + connect \Y $extend$libresoc.v:148945$7528_Y end - attribute \src "libresoc.v:158062.15-158062.57" - process $proc$libresoc.v:158062$8145 - assign { } { } - assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[128:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$libresoc.v:148946$7530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 64 + connect \A \logical_op__data_len + connect \Y $extend$libresoc.v:148946$7530_Y end - attribute \src "libresoc.v:158076.7-158076.20" - process $proc$libresoc.v:158076$8146 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $extend$libresoc.v:148950$7535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$176 + connect \Y $extend$libresoc.v:148950$7535_Y end - attribute \src "libresoc.v:158087.7-158087.25" - process $proc$libresoc.v:158087$8147 - assign { } { } - assign $0\xer_so$14[0:0]$8148 1'0 - sync always - sync init - update \xer_so$14 $0\xer_so$14[0:0]$8148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" + cell $or $or$libresoc.v:148953$7539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $or$libresoc.v:148953$7539_Y end - attribute \src "libresoc.v:158093.3-158094.43" - process $proc$libresoc.v:158093$8030 - assign { } { } - assign $0\neg_res32$16[0:0]$8031 \neg_res32$16$next - sync posedge \coresync_clk - update \neg_res32$16 $0\neg_res32$16[0:0]$8031 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $pos$libresoc.v:148941$7523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:148941$7522_Y + connect \Y $pos$libresoc.v:148941$7523_Y end - attribute \src "libresoc.v:158095.3-158096.39" - process $proc$libresoc.v:158095$8032 - assign { } { } - assign $0\neg_res$15[0:0]$8033 \neg_res$15$next - sync posedge \coresync_clk - update \neg_res$15 $0\neg_res$15[0:0]$8033 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" + cell $pos $pos$libresoc.v:148943$7526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:148943$7525_Y + connect \Y $pos$libresoc.v:148943$7526_Y end - attribute \src "libresoc.v:158097.3-158098.37" - process $proc$libresoc.v:158097$8034 - assign { } { } - assign $0\xer_so$14[0:0]$8035 \xer_so$14$next - sync posedge \coresync_clk - update \xer_so$14 $0\xer_so$14[0:0]$8035 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $pos$libresoc.v:148945$7529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:148945$7528_Y + connect \Y $pos$libresoc.v:148945$7529_Y end - attribute \src "libresoc.v:158099.3-158100.19" - process $proc$libresoc.v:158099$8036 - assign { } { } - assign $0\o[128:0] \o$next - sync posedge \coresync_clk - update \o $0\o[128:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$libresoc.v:148946$7531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:148946$7530_Y + connect \Y $pos$libresoc.v:148946$7531_Y end - attribute \src "libresoc.v:158101.3-158102.57" - process $proc$libresoc.v:158101$8037 - assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8038 \mul_op__insn_type$2$next - sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $pos$libresoc.v:148950$7536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:148950$7535_Y + connect \Y $pos$libresoc.v:148950$7536_Y end - attribute \src "libresoc.v:158103.3-158104.53" - process $proc$libresoc.v:158103$8039 - assign { } { } - assign $0\mul_op__fn_unit$3[12:0]$8040 \mul_op__fn_unit$3$next - sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" + cell $reduce_xor $reduce_xor$libresoc.v:148947$7532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } + connect \Y $reduce_xor$libresoc.v:148947$7532_Y end - attribute \src "libresoc.v:158105.3-158106.67" - process $proc$libresoc.v:158105$8041 - assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8042 \mul_op__imm_data__data$4$next - sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" + cell $reduce_xor $reduce_xor$libresoc.v:148948$7533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } + connect \Y $reduce_xor$libresoc.v:148948$7533_Y end - attribute \src "libresoc.v:158107.3-158108.63" - process $proc$libresoc.v:158107$8043 - assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8044 \mul_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $sub $sub$libresoc.v:148942$7524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \B 6'100000 + connect \Y $sub$libresoc.v:148942$7524_Y end - attribute \src "libresoc.v:158109.3-158110.51" - process $proc$libresoc.v:158109$8045 - assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8046 \mul_op__rc__rc$6$next - sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8046 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $mux $ternary$libresoc.v:148944$7527 + parameter \WIDTH 8 + connect \A \$164 + connect \B \$162 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:148944$7527_Y end - attribute \src "libresoc.v:158111.3-158112.51" - process $proc$libresoc.v:158111$8047 - assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8048 \mul_op__rc__ok$7$next - sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8048 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $mux $ternary$libresoc.v:148949$7534 + parameter \WIDTH 32 + connect \A \a32 + connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } + connect \S \count_right + connect \Y $ternary$libresoc.v:148949$7534_Y end - attribute \src "libresoc.v:158113.3-158114.51" - process $proc$libresoc.v:158113$8049 - assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8050 \mul_op__oe__oe$8$next - sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8050 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" + cell $mux $ternary$libresoc.v:148951$7537 + parameter \WIDTH 64 + connect \A \ra + connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } + connect \S \count_right + connect \Y $ternary$libresoc.v:148951$7537_Y end - attribute \src "libresoc.v:158115.3-158116.51" - process $proc$libresoc.v:158115$8051 - assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8052 \mul_op__oe__ok$9$next - sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8052 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $xor $xor$libresoc.v:148940$7521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \par0 + connect \B \par1 + connect \Y $xor$libresoc.v:148940$7521_Y end - attribute \src "libresoc.v:158117.3-158118.59" - process $proc$libresoc.v:158117$8053 - assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8054 \mul_op__write_cr0$10$next - sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8054 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" + cell $xor $xor$libresoc.v:148954$7540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $xor$libresoc.v:148954$7540_Y end - attribute \src "libresoc.v:158119.3-158120.57" - process $proc$libresoc.v:158119$8055 - assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8056 \mul_op__is_32bit$11$next - sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8056 + attribute \module_not_derived 1 + attribute \src "libresoc.v:148991.10-148995.4" + cell \bpermd \bpermd + connect \ra \bpermd_ra + connect \rb \bpermd_rb + connect \rs \bpermd_rs end - attribute \src "libresoc.v:158121.3-158122.59" - process $proc$libresoc.v:158121$8057 - assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8058 \mul_op__is_signed$12$next - sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8058 + attribute \module_not_derived 1 + attribute \src "libresoc.v:148996.7-148999.4" + cell \clz \clz + connect \lz \clz_lz + connect \sig_in \clz_sig_in end - attribute \src "libresoc.v:158123.3-158124.49" - process $proc$libresoc.v:158123$8059 - assign { } { } - assign $0\mul_op__insn$13[31:0]$8060 \mul_op__insn$13$next - sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8060 + attribute \module_not_derived 1 + attribute \src "libresoc.v:149000.12-149004.4" + cell \popcount \popcount + connect \a \popcount_a + connect \data_len \popcount_data_len + connect \o \popcount_o end - attribute \src "libresoc.v:158125.3-158126.33" - process $proc$libresoc.v:158125$8061 + attribute \src "libresoc.v:148448.7-148448.20" + process $proc$libresoc.v:148448$7589 assign { } { } - assign $0\muxid$1[1:0]$8062 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8062 + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:158127.3-158128.29" - process $proc$libresoc.v:158127$8063 + attribute \src "libresoc.v:149005.3-149059.6" + process $proc$libresoc.v:149005$7577 assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:158174.3-158191.6" - process $proc$libresoc.v:158174$8064 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8065 $2\r_busy$next[0:0]$8067 - attribute \src "libresoc.v:158175.5-158175.29" + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:149006.5-149006.29" switch \initial - attribute \src "libresoc.v:158175.9-158175.17" + attribute \src "libresoc.v:149006.9-149006.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 7'0000100 + assign $1\o_ok[0:0] 1'1 assign { } { } - assign $1\r_busy$next[0:0]$8066 1'1 + assign $1\o[63:0] \$21 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'0110101 + assign $1\o_ok[0:0] 1'1 assign { } { } - assign $1\r_busy$next[0:0]$8066 1'0 - case - assign $1\r_busy$next[0:0]$8066 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\o[63:0] \$23 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 7'1000011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$25 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] { \$139 \$141 \$143 \$145 \$147 \$149 \$151 \$153 \$123 \$125 \$127 \$129 \$131 \$133 \$135 \$137 \$107 \$109 \$111 \$113 \$115 \$117 \$119 \$121 \$91 \$93 \$95 \$97 \$99 \$101 \$103 \$105 \$75 \$77 \$79 \$81 \$83 \$85 \$87 \$89 \$59 \$61 \$63 \$65 \$67 \$69 \$71 \$73 \$43 \$45 \$47 \$49 \$51 \$53 \$55 \$57 \$27 \$29 \$31 \$33 \$35 \$37 \$39 \$41 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \popcount_o + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + switch \$155 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] \$157 + attribute \src "libresoc.v:0.0-0.0" + case + assign { $2\o[63:0] [63:33] $2\o[63:0] [31:1] } 62'00000000000000000000000000000000000000000000000000000000000000 + assign $2\o[63:0] [0] \par0 + assign $2\o[63:0] [32] \par1 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$161 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign $1\o_ok[0:0] 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8067 1'0 + assign $1\o[63:0] \bpermd_ra + attribute \src "libresoc.v:0.0-0.0" case - assign $2\r_busy$next[0:0]$8067 $1\r_busy$next[0:0]$8066 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o_ok[0:0] 1'0 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8065 + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] end - attribute \src "libresoc.v:158192.3-158204.6" - process $proc$libresoc.v:158192$8068 + attribute \src "libresoc.v:149060.3-149070.6" + process $proc$libresoc.v:149060$7578 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8069 $1\muxid$1$next[1:0]$8070 - attribute \src "libresoc.v:158193.5-158193.29" + assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] + attribute \src "libresoc.v:149061.5-149061.29" switch \initial - attribute \src "libresoc.v:158193.9-158193.17" + attribute \src "libresoc.v:149061.9-149061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$8070 \muxid$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'0001110 assign { } { } - assign $1\muxid$1$next[1:0]$8070 \muxid$36 + assign $1\clz_sig_in[63:0] \cntz_i case - assign $1\muxid$1$next[1:0]$8070 \muxid$1 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8069 + update \clz_sig_in $0\clz_sig_in[63:0] end - attribute \src "libresoc.v:158205.3-158240.6" - process $proc$libresoc.v:158205$8071 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:149071.3-149081.6" + process $proc$libresoc.v:149071$7579 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__fn_unit$3$next[12:0]$8072 $1\mul_op__fn_unit$3$next[12:0]$8084 - assign { } { } - assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8075 $1\mul_op__insn$13$next[31:0]$8087 - assign $0\mul_op__insn_type$2$next[6:0]$8076 $1\mul_op__insn_type$2$next[6:0]$8088 - assign $0\mul_op__is_32bit$11$next[0:0]$8077 $1\mul_op__is_32bit$11$next[0:0]$8089 - assign $0\mul_op__is_signed$12$next[0:0]$8078 $1\mul_op__is_signed$12$next[0:0]$8090 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8083 $1\mul_op__write_cr0$10$next[0:0]$8095 - assign $0\mul_op__imm_data__data$4$next[63:0]$8073 $2\mul_op__imm_data__data$4$next[63:0]$8096 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8074 $2\mul_op__imm_data__ok$5$next[0:0]$8097 - assign $0\mul_op__oe__oe$8$next[0:0]$8079 $2\mul_op__oe__oe$8$next[0:0]$8098 - assign $0\mul_op__oe__ok$9$next[0:0]$8080 $2\mul_op__oe__ok$9$next[0:0]$8099 - assign $0\mul_op__rc__ok$7$next[0:0]$8081 $2\mul_op__rc__ok$7$next[0:0]$8100 - assign $0\mul_op__rc__rc$6$next[0:0]$8082 $2\mul_op__rc__rc$6$next[0:0]$8101 - attribute \src "libresoc.v:158206.5-158206.29" + assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] + attribute \src "libresoc.v:149072.5-149072.29" switch \initial - attribute \src "libresoc.v:158206.9-158206.17" + attribute \src "libresoc.v:149072.9-149072.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8087 $1\mul_op__is_signed$12$next[0:0]$8090 $1\mul_op__is_32bit$11$next[0:0]$8089 $1\mul_op__write_cr0$10$next[0:0]$8095 $1\mul_op__oe__ok$9$next[0:0]$8092 $1\mul_op__oe__oe$8$next[0:0]$8091 $1\mul_op__rc__ok$7$next[0:0]$8093 $1\mul_op__rc__rc$6$next[0:0]$8094 $1\mul_op__imm_data__ok$5$next[0:0]$8086 $1\mul_op__imm_data__data$4$next[63:0]$8085 $1\mul_op__fn_unit$3$next[12:0]$8084 $1\mul_op__insn_type$2$next[6:0]$8088 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + case 7'0001001 assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8087 $1\mul_op__is_signed$12$next[0:0]$8090 $1\mul_op__is_32bit$11$next[0:0]$8089 $1\mul_op__write_cr0$10$next[0:0]$8095 $1\mul_op__oe__ok$9$next[0:0]$8092 $1\mul_op__oe__oe$8$next[0:0]$8091 $1\mul_op__rc__ok$7$next[0:0]$8093 $1\mul_op__rc__rc$6$next[0:0]$8094 $1\mul_op__imm_data__ok$5$next[0:0]$8086 $1\mul_op__imm_data__data$4$next[63:0]$8085 $1\mul_op__fn_unit$3$next[12:0]$8084 $1\mul_op__insn_type$2$next[6:0]$8088 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign $1\bpermd_rs[63:0] \ra case - assign $1\mul_op__fn_unit$3$next[12:0]$8084 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8085 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8086 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8087 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8088 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8089 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8090 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8091 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8092 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8093 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8094 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8095 \mul_op__write_cr0$10 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \bpermd_rs $0\bpermd_rs[63:0] + end + attribute \src "libresoc.v:149082.3-149092.6" + process $proc$libresoc.v:149082$7580 + assign { } { } + assign { } { } + assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] + attribute \src "libresoc.v:149083.5-149083.29" + switch \initial + attribute \src "libresoc.v:149083.9-149083.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8096 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8097 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8101 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8100 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8098 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8099 1'0 + assign $1\bpermd_rb[63:0] \rb case - assign $2\mul_op__imm_data__data$4$next[63:0]$8096 $1\mul_op__imm_data__data$4$next[63:0]$8085 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8097 $1\mul_op__imm_data__ok$5$next[0:0]$8086 - assign $2\mul_op__oe__oe$8$next[0:0]$8098 $1\mul_op__oe__oe$8$next[0:0]$8091 - assign $2\mul_op__oe__ok$9$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8092 - assign $2\mul_op__rc__ok$7$next[0:0]$8100 $1\mul_op__rc__ok$7$next[0:0]$8093 - assign $2\mul_op__rc__rc$6$next[0:0]$8101 $1\mul_op__rc__rc$6$next[0:0]$8094 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$8072 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8073 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8074 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8075 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8076 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8077 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8078 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8079 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8080 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8081 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8082 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8083 + update \bpermd_rb $0\bpermd_rb[63:0] end - attribute \src "libresoc.v:158241.3-158253.6" - process $proc$libresoc.v:158241$8102 + attribute \src "libresoc.v:149093.3-149103.6" + process $proc$libresoc.v:149093$7581 assign { } { } assign { } { } - assign $0\o$next[128:0]$8103 $1\o$next[128:0]$8104 - attribute \src "libresoc.v:158242.5-158242.29" + assign $0\popcount_a[63:0] $1\popcount_a[63:0] + attribute \src "libresoc.v:149094.5-149094.29" switch \initial - attribute \src "libresoc.v:158242.9-158242.17" + attribute \src "libresoc.v:149094.9-149094.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 7'0110110 assign { } { } - assign $1\o$next[128:0]$8104 \o$49 + assign $1\popcount_a[63:0] \ra + case + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_a $0\popcount_a[63:0] + end + attribute \src "libresoc.v:149104.3-149114.6" + process $proc$libresoc.v:149104$7582 + assign { } { } + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:149105.5-149105.29" + switch \initial + attribute \src "libresoc.v:149105.9-149105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'0110110 assign { } { } - assign $1\o$next[128:0]$8104 \o$49 + assign $1\b[63:0] \rb case - assign $1\o$next[128:0]$8104 \o + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \o$next $0\o$next[128:0]$8103 + update \b $0\b[63:0] end - attribute \src "libresoc.v:158254.3-158266.6" - process $proc$libresoc.v:158254$8105 + attribute \src "libresoc.v:149115.3-149125.6" + process $proc$libresoc.v:149115$7583 assign { } { } assign { } { } - assign $0\xer_so$14$next[0:0]$8106 $1\xer_so$14$next[0:0]$8107 - attribute \src "libresoc.v:158255.5-158255.29" + assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] + attribute \src "libresoc.v:149116.5-149116.29" switch \initial - attribute \src "libresoc.v:158255.9-158255.17" + attribute \src "libresoc.v:149116.9-149116.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 7'0110110 assign { } { } - assign $1\xer_so$14$next[0:0]$8107 \xer_so$50 + assign $1\popcount_data_len[63:0] \$169 + case + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_data_len $0\popcount_data_len[63:0] + end + attribute \src "libresoc.v:149126.3-149136.6" + process $proc$libresoc.v:149126$7584 + assign { } { } + assign { } { } + assign $0\par0[0:0] $1\par0[0:0] + attribute \src "libresoc.v:149127.5-149127.29" + switch \initial + attribute \src "libresoc.v:149127.9-149127.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'0110111 assign { } { } - assign $1\xer_so$14$next[0:0]$8107 \xer_so$50 + assign $1\par0[0:0] \$171 case - assign $1\xer_so$14$next[0:0]$8107 \xer_so$14 + assign $1\par0[0:0] 1'0 end sync always - update \xer_so$14$next $0\xer_so$14$next[0:0]$8106 + update \par0 $0\par0[0:0] end - attribute \src "libresoc.v:158267.3-158279.6" - process $proc$libresoc.v:158267$8108 + attribute \src "libresoc.v:149137.3-149147.6" + process $proc$libresoc.v:149137$7585 assign { } { } assign { } { } - assign $0\neg_res$15$next[0:0]$8109 $1\neg_res$15$next[0:0]$8110 - attribute \src "libresoc.v:158268.5-158268.29" + assign $0\par1[0:0] $1\par1[0:0] + attribute \src "libresoc.v:149138.5-149138.29" switch \initial - attribute \src "libresoc.v:158268.9-158268.17" + attribute \src "libresoc.v:149138.9-149138.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 7'0110111 assign { } { } - assign $1\neg_res$15$next[0:0]$8110 \neg_res$51 + assign $1\par1[0:0] \$173 + case + assign $1\par1[0:0] 1'0 + end + sync always + update \par1 $0\par1[0:0] + end + attribute \src "libresoc.v:149148.3-149158.6" + process $proc$libresoc.v:149148$7586 + assign { } { } + assign { } { } + assign $0\count_right[0:0] $1\count_right[0:0] + attribute \src "libresoc.v:149149.5-149149.29" + switch \initial + attribute \src "libresoc.v:149149.9-149149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'0001110 assign { } { } - assign $1\neg_res$15$next[0:0]$8110 \neg_res$51 + assign $1\count_right[0:0] \logical_op__insn [10] case - assign $1\neg_res$15$next[0:0]$8110 \neg_res$15 + assign $1\count_right[0:0] 1'0 end sync always - update \neg_res$15$next $0\neg_res$15$next[0:0]$8109 + update \count_right $0\count_right[0:0] end - attribute \src "libresoc.v:158280.3-158292.6" - process $proc$libresoc.v:158280$8111 + attribute \src "libresoc.v:149159.3-149169.6" + process $proc$libresoc.v:149159$7587 assign { } { } assign { } { } - assign $0\neg_res32$16$next[0:0]$8112 $1\neg_res32$16$next[0:0]$8113 - attribute \src "libresoc.v:158281.5-158281.29" + assign $0\a32[31:0] $1\a32[31:0] + attribute \src "libresoc.v:149160.5-149160.29" switch \initial - attribute \src "libresoc.v:158281.9-158281.17" + attribute \src "libresoc.v:149160.9-149160.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 7'0001110 assign { } { } - assign $1\neg_res32$16$next[0:0]$8113 \neg_res32$52 + assign $1\a32[31:0] \ra [31:0] + case + assign $1\a32[31:0] 0 + end + sync always + update \a32 $0\a32[31:0] + end + attribute \src "libresoc.v:149170.3-149188.6" + process $proc$libresoc.v:149170$7588 + assign { } { } + assign { } { } + assign $0\cntz_i[63:0] $1\cntz_i[63:0] + attribute \src "libresoc.v:149171.5-149171.29" + switch \initial + attribute \src "libresoc.v:149171.9-149171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'0001110 assign { } { } - assign $1\neg_res32$16$next[0:0]$8113 \neg_res32$52 + assign $1\cntz_i[63:0] $2\cntz_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cntz_i[63:0] \$175 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cntz_i[63:0] \$179 + end case - assign $1\neg_res32$16$next[0:0]$8113 \neg_res32$16 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8112 + update \cntz_i $0\cntz_i[63:0] end - connect \$34 $and$libresoc.v:158092$8029_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \neg_res32$52 \mul2_neg_res32$32 - connect \neg_res$51 \mul2_neg_res$31 - connect \xer_so$50 \mul2_xer_so$30 - connect \o$49 \mul2_o - connect { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } - connect \muxid$36 \mul2_muxid$17 - connect \p_valid_i_p_ready_o \$34 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$33 \p_valid_i - connect \mul2_neg_res32 \neg_res32 - connect \mul2_neg_res \neg_res - connect \mul2_xer_so \xer_so - connect \mul2_rb \rb - connect \mul2_ra \ra - connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \mul2_muxid \muxid + connect \$99 $eq$libresoc.v:148911$7492_Y + connect \$101 $eq$libresoc.v:148912$7493_Y + connect \$103 $eq$libresoc.v:148913$7494_Y + connect \$105 $eq$libresoc.v:148914$7495_Y + connect \$107 $eq$libresoc.v:148915$7496_Y + connect \$109 $eq$libresoc.v:148916$7497_Y + connect \$111 $eq$libresoc.v:148917$7498_Y + connect \$113 $eq$libresoc.v:148918$7499_Y + connect \$115 $eq$libresoc.v:148919$7500_Y + connect \$117 $eq$libresoc.v:148920$7501_Y + connect \$119 $eq$libresoc.v:148921$7502_Y + connect \$121 $eq$libresoc.v:148922$7503_Y + connect \$123 $eq$libresoc.v:148923$7504_Y + connect \$125 $eq$libresoc.v:148924$7505_Y + connect \$127 $eq$libresoc.v:148925$7506_Y + connect \$129 $eq$libresoc.v:148926$7507_Y + connect \$131 $eq$libresoc.v:148927$7508_Y + connect \$133 $eq$libresoc.v:148928$7509_Y + connect \$135 $eq$libresoc.v:148929$7510_Y + connect \$137 $eq$libresoc.v:148930$7511_Y + connect \$139 $eq$libresoc.v:148931$7512_Y + connect \$141 $eq$libresoc.v:148932$7513_Y + connect \$143 $eq$libresoc.v:148933$7514_Y + connect \$145 $eq$libresoc.v:148934$7515_Y + connect \$147 $eq$libresoc.v:148935$7516_Y + connect \$149 $eq$libresoc.v:148936$7517_Y + connect \$151 $eq$libresoc.v:148937$7518_Y + connect \$153 $eq$libresoc.v:148938$7519_Y + connect \$155 $eq$libresoc.v:148939$7520_Y + connect \$158 $xor$libresoc.v:148940$7521_Y + connect \$157 $pos$libresoc.v:148941$7523_Y + connect \$162 $sub$libresoc.v:148942$7524_Y + connect \$164 $pos$libresoc.v:148943$7526_Y + connect \$166 $ternary$libresoc.v:148944$7527_Y + connect \$161 $pos$libresoc.v:148945$7529_Y + connect \$169 $pos$libresoc.v:148946$7531_Y + connect \$171 $reduce_xor$libresoc.v:148947$7532_Y + connect \$173 $reduce_xor$libresoc.v:148948$7533_Y + connect \$176 $ternary$libresoc.v:148949$7534_Y + connect \$175 $pos$libresoc.v:148950$7536_Y + connect \$179 $ternary$libresoc.v:148951$7537_Y + connect \$21 $and$libresoc.v:148952$7538_Y + connect \$23 $or$libresoc.v:148953$7539_Y + connect \$25 $xor$libresoc.v:148954$7540_Y + connect \$27 $eq$libresoc.v:148955$7541_Y + connect \$29 $eq$libresoc.v:148956$7542_Y + connect \$31 $eq$libresoc.v:148957$7543_Y + connect \$33 $eq$libresoc.v:148958$7544_Y + connect \$35 $eq$libresoc.v:148959$7545_Y + connect \$37 $eq$libresoc.v:148960$7546_Y + connect \$39 $eq$libresoc.v:148961$7547_Y + connect \$41 $eq$libresoc.v:148962$7548_Y + connect \$43 $eq$libresoc.v:148963$7549_Y + connect \$45 $eq$libresoc.v:148964$7550_Y + connect \$47 $eq$libresoc.v:148965$7551_Y + connect \$49 $eq$libresoc.v:148966$7552_Y + connect \$51 $eq$libresoc.v:148967$7553_Y + connect \$53 $eq$libresoc.v:148968$7554_Y + connect \$55 $eq$libresoc.v:148969$7555_Y + connect \$57 $eq$libresoc.v:148970$7556_Y + connect \$59 $eq$libresoc.v:148971$7557_Y + connect \$61 $eq$libresoc.v:148972$7558_Y + connect \$63 $eq$libresoc.v:148973$7559_Y + connect \$65 $eq$libresoc.v:148974$7560_Y + connect \$67 $eq$libresoc.v:148975$7561_Y + connect \$69 $eq$libresoc.v:148976$7562_Y + connect \$71 $eq$libresoc.v:148977$7563_Y + connect \$73 $eq$libresoc.v:148978$7564_Y + connect \$75 $eq$libresoc.v:148979$7565_Y + connect \$77 $eq$libresoc.v:148980$7566_Y + connect \$79 $eq$libresoc.v:148981$7567_Y + connect \$81 $eq$libresoc.v:148982$7568_Y + connect \$83 $eq$libresoc.v:148983$7569_Y + connect \$85 $eq$libresoc.v:148984$7570_Y + connect \$87 $eq$libresoc.v:148985$7571_Y + connect \$89 $eq$libresoc.v:148986$7572_Y + connect \$91 $eq$libresoc.v:148987$7573_Y + connect \$93 $eq$libresoc.v:148988$7574_Y + connect \$95 $eq$libresoc.v:148989$7575_Y + connect \$97 $eq$libresoc.v:148990$7576_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so end -attribute \src "libresoc.v:158315.1-159597.10" +attribute \src "libresoc.v:149196.1-149707.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" -module \mul_pipe3 - attribute \src "libresoc.v:159515.3-159533.6" - wire width 4 $0\cr_a$next[3:0]$8232 - attribute \src "libresoc.v:159307.3-159308.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:159515.3-159533.6" - wire $0\cr_a_ok$next[0:0]$8233 - attribute \src "libresoc.v:159309.3-159310.31" +module \main$9 + attribute \src "libresoc.v:149562.3-149572.6" + wire width 2 $0\BC[1:0] + attribute \src "libresoc.v:149616.3-149626.6" + wire width 2 $0\ba[1:0] + attribute \src "libresoc.v:149627.3-149637.6" + wire width 2 $0\bb[1:0] + attribute \src "libresoc.v:149638.3-149658.6" + wire $0\bit_a[0:0] + attribute \src "libresoc.v:149659.3-149679.6" + wire $0\bit_b[0:0] + attribute \src "libresoc.v:149680.3-149690.6" + wire $0\bit_o[0:0] + attribute \src "libresoc.v:149605.3-149615.6" + wire width 2 $0\bt[1:0] + attribute \src "libresoc.v:149474.3-149508.6" + wire width 4 $0\cr_a$6[3:0]$7604 + attribute \src "libresoc.v:149474.3-149508.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:158316.7-158316.20" + attribute \src "libresoc.v:149573.3-149593.6" + wire $0\cr_bit[0:0] + attribute \src "libresoc.v:149691.3-149701.6" + wire width 32 $0\full_cr$5[31:0]$7619 + attribute \src "libresoc.v:149509.3-149519.6" + wire $0\full_cr_ok[0:0] + attribute \src "libresoc.v:149197.7-149197.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159460.3-159495.6" - wire width 13 $0\mul_op__fn_unit$3$next[12:0]$8195 - attribute \src "libresoc.v:159317.3-159318.53" - wire width 13 $0\mul_op__fn_unit$3[12:0]$8163 - attribute \src "libresoc.v:158621.14-158621.44" - wire width 13 $0\mul_op__fn_unit$3[12:0]$8253 - attribute \src "libresoc.v:159460.3-159495.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8196 - attribute \src "libresoc.v:159319.3-159320.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8165 - attribute \src "libresoc.v:158644.14-158644.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8255 - attribute \src "libresoc.v:159460.3-159495.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8197 - attribute \src "libresoc.v:159321.3-159322.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8167 - attribute \src "libresoc.v:158653.7-158653.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8257 - attribute \src "libresoc.v:159460.3-159495.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8198 - attribute \src "libresoc.v:159337.3-159338.49" - wire width 32 $0\mul_op__insn$13[31:0]$8183 - attribute \src "libresoc.v:158662.14-158662.39" - wire width 32 $0\mul_op__insn$13[31:0]$8259 - attribute \src "libresoc.v:159460.3-159495.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8199 - attribute \src "libresoc.v:159315.3-159316.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$8161 - attribute \src "libresoc.v:158819.13-158819.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8261 - attribute \src "libresoc.v:159460.3-159495.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8200 - attribute \src "libresoc.v:159333.3-159334.57" - wire $0\mul_op__is_32bit$11[0:0]$8179 - attribute \src "libresoc.v:158902.7-158902.35" - wire $0\mul_op__is_32bit$11[0:0]$8263 - attribute \src "libresoc.v:159460.3-159495.6" - wire $0\mul_op__is_signed$12$next[0:0]$8201 - attribute \src "libresoc.v:159335.3-159336.59" - wire $0\mul_op__is_signed$12[0:0]$8181 - attribute \src "libresoc.v:158911.7-158911.36" - wire $0\mul_op__is_signed$12[0:0]$8265 - attribute \src "libresoc.v:159460.3-159495.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8202 - attribute \src "libresoc.v:159327.3-159328.51" - wire $0\mul_op__oe__oe$8[0:0]$8173 - attribute \src "libresoc.v:158922.7-158922.32" - wire $0\mul_op__oe__oe$8[0:0]$8267 - attribute \src "libresoc.v:159460.3-159495.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8203 - attribute \src "libresoc.v:159329.3-159330.51" - wire $0\mul_op__oe__ok$9[0:0]$8175 - attribute \src "libresoc.v:158931.7-158931.32" - wire $0\mul_op__oe__ok$9[0:0]$8269 - attribute \src "libresoc.v:159460.3-159495.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8204 - attribute \src "libresoc.v:159325.3-159326.51" - wire $0\mul_op__rc__ok$7[0:0]$8171 - attribute \src "libresoc.v:158940.7-158940.32" - wire $0\mul_op__rc__ok$7[0:0]$8271 - attribute \src "libresoc.v:159460.3-159495.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8205 - attribute \src "libresoc.v:159323.3-159324.51" - wire $0\mul_op__rc__rc$6[0:0]$8169 - attribute \src "libresoc.v:158947.7-158947.32" - wire $0\mul_op__rc__rc$6[0:0]$8273 - attribute \src "libresoc.v:159460.3-159495.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8206 - attribute \src "libresoc.v:159331.3-159332.59" - wire $0\mul_op__write_cr0$10[0:0]$8177 - attribute \src "libresoc.v:158956.7-158956.36" - wire $0\mul_op__write_cr0$10[0:0]$8275 - attribute \src "libresoc.v:159447.3-159459.6" - wire width 2 $0\muxid$1$next[1:0]$8192 - attribute \src "libresoc.v:159339.3-159340.33" - wire width 2 $0\muxid$1[1:0]$8185 - attribute \src "libresoc.v:158965.13-158965.29" - wire width 2 $0\muxid$1[1:0]$8277 - attribute \src "libresoc.v:159496.3-159514.6" - wire width 64 $0\o$14$next[63:0]$8227 - attribute \src "libresoc.v:159311.3-159312.27" - wire width 64 $0\o$14[63:0]$8158 - attribute \src "libresoc.v:158986.14-158986.43" - wire width 64 $0\o$14[63:0]$8279 - attribute \src "libresoc.v:159496.3-159514.6" - wire $0\o_ok$next[0:0]$8226 - attribute \src "libresoc.v:159313.3-159314.25" + attribute \src "libresoc.v:149594.3-149604.6" + wire width 4 $0\lut[3:0] + attribute \src "libresoc.v:149520.3-149561.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:149520.3-149561.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:159429.3-159446.6" - wire $0\r_busy$next[0:0]$8188 - attribute \src "libresoc.v:159341.3-159342.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:159534.3-159552.6" - wire width 2 $0\xer_ov$next[1:0]$8238 - attribute \src "libresoc.v:159303.3-159304.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:159534.3-159552.6" - wire $0\xer_ov_ok$next[0:0]$8239 - attribute \src "libresoc.v:159305.3-159306.35" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:159553.3-159571.6" - wire $0\xer_so$15$next[0:0]$8245 - attribute \src "libresoc.v:159299.3-159300.37" - wire $0\xer_so$15[0:0]$8151 - attribute \src "libresoc.v:159284.7-159284.25" - wire $0\xer_so$15[0:0]$8285 - attribute \src "libresoc.v:159553.3-159571.6" - wire $0\xer_so_ok$next[0:0]$8244 - attribute \src "libresoc.v:159301.3-159302.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:159515.3-159533.6" - wire width 4 $1\cr_a$next[3:0]$8234 - attribute \src "libresoc.v:158325.13-158325.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:159515.3-159533.6" - wire $1\cr_a_ok$next[0:0]$8235 - attribute \src "libresoc.v:158334.7-158334.21" + attribute \src "libresoc.v:149562.3-149572.6" + wire width 2 $1\BC[1:0] + attribute \src "libresoc.v:149616.3-149626.6" + wire width 2 $1\ba[1:0] + attribute \src "libresoc.v:149627.3-149637.6" + wire width 2 $1\bb[1:0] + attribute \src "libresoc.v:149638.3-149658.6" + wire $1\bit_a[0:0] + attribute \src "libresoc.v:149659.3-149679.6" + wire $1\bit_b[0:0] + attribute \src "libresoc.v:149680.3-149690.6" + wire $1\bit_o[0:0] + attribute \src "libresoc.v:149605.3-149615.6" + wire width 2 $1\bt[1:0] + attribute \src "libresoc.v:149474.3-149508.6" + wire width 4 $1\cr_a$6[3:0]$7605 + attribute \src "libresoc.v:149474.3-149508.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:159460.3-159495.6" - wire width 13 $1\mul_op__fn_unit$3$next[12:0]$8207 - attribute \src "libresoc.v:159460.3-159495.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8208 - attribute \src "libresoc.v:159460.3-159495.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8209 - attribute \src "libresoc.v:159460.3-159495.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8210 - attribute \src "libresoc.v:159460.3-159495.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8211 - attribute \src "libresoc.v:159460.3-159495.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8212 - attribute \src "libresoc.v:159460.3-159495.6" - wire $1\mul_op__is_signed$12$next[0:0]$8213 - attribute \src "libresoc.v:159460.3-159495.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8214 - attribute \src "libresoc.v:159460.3-159495.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8215 - attribute \src "libresoc.v:159460.3-159495.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8216 - attribute \src "libresoc.v:159460.3-159495.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8217 - attribute \src "libresoc.v:159460.3-159495.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8218 - attribute \src "libresoc.v:159447.3-159459.6" - wire width 2 $1\muxid$1$next[1:0]$8193 - attribute \src "libresoc.v:159496.3-159514.6" - wire width 64 $1\o$14$next[63:0]$8229 - attribute \src "libresoc.v:159496.3-159514.6" - wire $1\o_ok$next[0:0]$8228 - attribute \src "libresoc.v:158993.7-158993.18" + attribute \src "libresoc.v:149573.3-149593.6" + wire $1\cr_bit[0:0] + attribute \src "libresoc.v:149691.3-149701.6" + wire width 32 $1\full_cr$5[31:0]$7620 + attribute \src "libresoc.v:149509.3-149519.6" + wire $1\full_cr_ok[0:0] + attribute \src "libresoc.v:149594.3-149604.6" + wire width 4 $1\lut[3:0] + attribute \src "libresoc.v:149520.3-149561.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:149520.3-149561.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:159429.3-159446.6" - wire $1\r_busy$next[0:0]$8189 - attribute \src "libresoc.v:159261.7-159261.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:159534.3-159552.6" - wire width 2 $1\xer_ov$next[1:0]$8240 - attribute \src "libresoc.v:159266.13-159266.26" - wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:159534.3-159552.6" - wire $1\xer_ov_ok$next[0:0]$8241 - attribute \src "libresoc.v:159273.7-159273.23" - wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159553.3-159571.6" - wire $1\xer_so$15$next[0:0]$8247 - attribute \src "libresoc.v:159553.3-159571.6" - wire $1\xer_so_ok$next[0:0]$8246 - attribute \src "libresoc.v:159291.7-159291.23" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159515.3-159533.6" - wire $2\cr_a_ok$next[0:0]$8236 - attribute \src "libresoc.v:159460.3-159495.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8219 - attribute \src "libresoc.v:159460.3-159495.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8220 - attribute \src "libresoc.v:159460.3-159495.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8221 - attribute \src "libresoc.v:159460.3-159495.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8222 - attribute \src "libresoc.v:159460.3-159495.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8223 - attribute \src "libresoc.v:159460.3-159495.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8224 - attribute \src "libresoc.v:159496.3-159514.6" - wire $2\o_ok$next[0:0]$8230 - attribute \src "libresoc.v:159429.3-159446.6" - wire $2\r_busy$next[0:0]$8190 - attribute \src "libresoc.v:159534.3-159552.6" - wire $2\xer_ov_ok$next[0:0]$8242 - attribute \src "libresoc.v:159553.3-159571.6" - wire $2\xer_so_ok$next[0:0]$8248 - attribute \src "libresoc.v:159298.18-159298.118" - wire $and$libresoc.v:159298$8149_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 44 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 38 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 39 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$52 + attribute \src "libresoc.v:149638.3-149658.6" + wire $2\bit_a[0:0] + attribute \src "libresoc.v:149659.3-149679.6" + wire $2\bit_b[0:0] + attribute \src "libresoc.v:149474.3-149508.6" + wire width 4 $2\cr_a$6[3:0]$7606 + attribute \src "libresoc.v:149573.3-149593.6" + wire $2\cr_bit[0:0] + attribute \src "libresoc.v:149520.3-149561.6" + wire width 64 $2\o[63:0] + attribute \src "libresoc.v:149470.18-149470.96" + wire width 64 $extend$libresoc.v:149470$7596_Y + attribute \src "libresoc.v:149472.18-149472.98" + wire width 65 $extend$libresoc.v:149472$7599_Y + attribute \src "libresoc.v:149473.17-149473.92" + wire width 5 $extend$libresoc.v:149473$7601_Y + attribute \src "libresoc.v:149470.18-149470.96" + wire width 64 $pos$libresoc.v:149470$7597_Y + attribute \src "libresoc.v:149472.18-149472.98" + wire width 65 $pos$libresoc.v:149472$7600_Y + attribute \src "libresoc.v:149473.17-149473.92" + wire width 5 $pos$libresoc.v:149473$7602_Y + attribute \src "libresoc.v:149464.18-149464.116" + wire width 3 $sub$libresoc.v:149464$7590_Y + attribute \src "libresoc.v:149465.18-149465.116" + wire width 3 $sub$libresoc.v:149465$7591_Y + attribute \src "libresoc.v:149466.18-149466.116" + wire width 3 $sub$libresoc.v:149466$7592_Y + attribute \src "libresoc.v:149467.18-149467.114" + wire $ternary$libresoc.v:149467$7593_Y + attribute \src "libresoc.v:149468.18-149468.115" + wire $ternary$libresoc.v:149468$7594_Y + attribute \src "libresoc.v:149469.18-149469.112" + wire $ternary$libresoc.v:149469$7595_Y + attribute \src "libresoc.v:149471.18-149471.108" + wire width 64 $ternary$libresoc.v:149471$7598_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + wire width 3 \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + wire width 3 \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 3 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + wire width 65 \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + wire width 64 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" + wire width 2 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" + wire width 2 \ba + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:83" + wire width 2 \bb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" + wire \bit_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:92" + wire \bit_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97" + wire \bit_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:81" + wire width 2 \bt + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 7 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$74 + wire width 4 output 18 \cr_a$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$next - attribute \src "libresoc.v:158316.7-158316.15" - wire \initial + wire output 19 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 8 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" + wire \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 9 \cr_c attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -327566,7 +313258,7 @@ module \mul_pipe3 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul3_mul_op__fn_unit + wire width 13 input 2 \cr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -327582,19 +313274,11 @@ module \mul_pipe3 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul3_mul_op__fn_unit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul3_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul3_mul_op__imm_data__data$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__imm_data__ok$20 + wire width 13 output 12 \cr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul3_mul_op__insn + wire width 32 input 3 \cr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul3_mul_op__insn$28 + wire width 32 output 13 \cr_op__insn$4 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -327670,7 +313354,7 @@ module \mul_pipe3 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul3_mul_op__insn_type + wire width 7 input 1 \cr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -327746,91 +313430,1224 @@ module \mul_pipe3 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul3_mul_op__insn_type$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__is_32bit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__is_signed$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__oe__oe$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__oe__ok$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__rc__ok$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__rc__rc$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__write_cr0$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \mul3_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \mul3_muxid$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \mul3_neg_res + wire width 7 output 11 \cr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul3_o + wire width 32 input 6 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \mul3_o$29 + wire width 32 output 16 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul3_o_ok + wire output 17 \full_cr_ok + attribute \src "libresoc.v:149197.7-149197.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + wire width 4 \lut + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 20 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 10 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \mul3_xer_ov + wire width 64 output 14 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul3_xer_ov_ok + wire output 15 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul3_xer_so$30 + wire width 64 input 4 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 5 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:149470$7596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \full_cr + connect \Y $extend$libresoc.v:149470$7596_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $extend$libresoc.v:149472$7599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$27 + connect \Y $extend$libresoc.v:149472$7599_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:149473$7601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A \cr_a + connect \Y $extend$libresoc.v:149473$7601_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:149470$7597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:149470$7596_Y + connect \Y $pos$libresoc.v:149470$7597_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $pos$libresoc.v:149472$7600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:149472$7599_Y + connect \Y $pos$libresoc.v:149472$7600_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:149473$7602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $extend$libresoc.v:149473$7601_Y + connect \Y $pos$libresoc.v:149473$7602_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + cell $sub $sub$libresoc.v:149464$7590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [22:21] + connect \Y $sub$libresoc.v:149464$7590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + cell $sub $sub$libresoc.v:149465$7591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [17:16] + connect \Y $sub$libresoc.v:149465$7591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + cell $sub $sub$libresoc.v:149466$7592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [12:11] + connect \Y $sub$libresoc.v:149466$7592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + cell $mux $ternary$libresoc.v:149467$7593 + parameter \WIDTH 1 + connect \A \lut [1] + connect \B \lut [3] + connect \S \bit_a + connect \Y $ternary$libresoc.v:149467$7593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$libresoc.v:149468$7594 + parameter \WIDTH 1 + connect \A \lut [0] + connect \B \lut [2] + connect \S \bit_a + connect \Y $ternary$libresoc.v:149468$7594_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$libresoc.v:149469$7595 + parameter \WIDTH 1 + connect \A \$20 + connect \B \$18 + connect \S \bit_b + connect \Y $ternary$libresoc.v:149469$7595_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $mux $ternary$libresoc.v:149471$7598 + parameter \WIDTH 64 + connect \A \rb + connect \B \ra + connect \S \cr_bit + connect \Y $ternary$libresoc.v:149471$7598_Y + end + attribute \src "libresoc.v:149197.7-149197.20" + process $proc$libresoc.v:149197$7621 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:149474.3-149508.6" + process $proc$libresoc.v:149474$7603 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + assign $0\cr_a$6[3:0]$7604 $1\cr_a$6[3:0]$7605 + attribute \src "libresoc.v:149475.5-149475.29" + switch \initial + attribute \src "libresoc.v:149475.9-149475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$7605 \$7 [3:0] + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$7605 $2\cr_a$6[3:0]$7606 + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" + switch \bt + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $2\cr_a$6[3:0]$7606 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7606 [0] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { $2\cr_a$6[3:0]$7606 [3:2] $2\cr_a$6[3:0]$7606 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7606 [1] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { $2\cr_a$6[3:0]$7606 [3] $2\cr_a$6[3:0]$7606 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7606 [2] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign $2\cr_a$6[3:0]$7606 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7606 [3] \bit_o + case + assign $2\cr_a$6[3:0]$7606 \cr_c + end + case + assign $1\cr_a_ok[0:0] 1'0 + assign $1\cr_a$6[3:0]$7605 4'0000 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + update \cr_a$6 $0\cr_a$6[3:0]$7604 + end + attribute \src "libresoc.v:149509.3-149519.6" + process $proc$libresoc.v:149509$7607 + assign { } { } + assign { } { } + assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] + attribute \src "libresoc.v:149510.5-149510.29" + switch \initial + attribute \src "libresoc.v:149510.9-149510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr_ok[0:0] 1'1 + case + assign $1\full_cr_ok[0:0] 1'0 + end + sync always + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "libresoc.v:149520.3-149561.6" + process $proc$libresoc.v:149520$7608 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:149521.5-149521.29" + switch \initial + attribute \src "libresoc.v:149521.9-149521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101101 + assign { } { } + assign { } { } + assign $1\o[63:0] \$24 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign { } { } + assign $1\o[63:0] \$26 [63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111011 + assign { } { } + assign { } { } + assign $1\o[63:0] $2\o[63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" + switch { \cr_a [2] \cr_a [3] } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\o[63:0] 64'1111111111111111111111111111111111111111111111111111111111111111 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:149562.3-149572.6" + process $proc$libresoc.v:149562$7609 + assign { } { } + assign { } { } + assign $0\BC[1:0] $1\BC[1:0] + attribute \src "libresoc.v:149563.5-149563.29" + switch \initial + attribute \src "libresoc.v:149563.9-149563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\BC[1:0] \cr_op__insn [7:6] + case + assign $1\BC[1:0] 2'00 + end + sync always + update \BC $0\BC[1:0] + end + attribute \src "libresoc.v:149573.3-149593.6" + process $proc$libresoc.v:149573$7610 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "libresoc.v:149574.5-149574.29" + switch \initial + attribute \src "libresoc.v:149574.9-149574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\cr_bit[0:0] $2\cr_bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" + switch \BC + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [3] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\cr_bit[0:0] \cr_a [0] + case + assign $2\cr_bit[0:0] 1'0 + end + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "libresoc.v:149594.3-149604.6" + process $proc$libresoc.v:149594$7611 + assign { } { } + assign { } { } + assign $0\lut[3:0] $1\lut[3:0] + attribute \src "libresoc.v:149595.5-149595.29" + switch \initial + attribute \src "libresoc.v:149595.9-149595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\lut[3:0] \cr_op__insn [9:6] + case + assign $1\lut[3:0] 4'0000 + end + sync always + update \lut $0\lut[3:0] + end + attribute \src "libresoc.v:149605.3-149615.6" + process $proc$libresoc.v:149605$7612 + assign { } { } + assign { } { } + assign $0\bt[1:0] $1\bt[1:0] + attribute \src "libresoc.v:149606.5-149606.29" + switch \initial + attribute \src "libresoc.v:149606.9-149606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bt[1:0] \$9 [1:0] + case + assign $1\bt[1:0] 2'00 + end + sync always + update \bt $0\bt[1:0] + end + attribute \src "libresoc.v:149616.3-149626.6" + process $proc$libresoc.v:149616$7613 + assign { } { } + assign { } { } + assign $0\ba[1:0] $1\ba[1:0] + attribute \src "libresoc.v:149617.5-149617.29" + switch \initial + attribute \src "libresoc.v:149617.9-149617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\ba[1:0] \$12 [1:0] + case + assign $1\ba[1:0] 2'00 + end + sync always + update \ba $0\ba[1:0] + end + attribute \src "libresoc.v:149627.3-149637.6" + process $proc$libresoc.v:149627$7614 + assign { } { } + assign { } { } + assign $0\bb[1:0] $1\bb[1:0] + attribute \src "libresoc.v:149628.5-149628.29" + switch \initial + attribute \src "libresoc.v:149628.9-149628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bb[1:0] \$15 [1:0] + case + assign $1\bb[1:0] 2'00 + end + sync always + update \bb $0\bb[1:0] + end + attribute \src "libresoc.v:149638.3-149658.6" + process $proc$libresoc.v:149638$7615 + assign { } { } + assign { } { } + assign $0\bit_a[0:0] $1\bit_a[0:0] + attribute \src "libresoc.v:149639.5-149639.29" + switch \initial + attribute \src "libresoc.v:149639.9-149639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_a[0:0] $2\bit_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" + switch \ba + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_a[0:0] \cr_a [0] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_a[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_a[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_a[0:0] \cr_a [3] + case + assign $2\bit_a[0:0] 1'0 + end + case + assign $1\bit_a[0:0] 1'0 + end + sync always + update \bit_a $0\bit_a[0:0] + end + attribute \src "libresoc.v:149659.3-149679.6" + process $proc$libresoc.v:149659$7616 + assign { } { } + assign { } { } + assign $0\bit_b[0:0] $1\bit_b[0:0] + attribute \src "libresoc.v:149660.5-149660.29" + switch \initial + attribute \src "libresoc.v:149660.9-149660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_b[0:0] $2\bit_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" + switch \bb + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_b[0:0] \cr_b [0] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_b[0:0] \cr_b [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_b[0:0] \cr_b [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_b[0:0] \cr_b [3] + case + assign $2\bit_b[0:0] 1'0 + end + case + assign $1\bit_b[0:0] 1'0 + end + sync always + update \bit_b $0\bit_b[0:0] + end + attribute \src "libresoc.v:149680.3-149690.6" + process $proc$libresoc.v:149680$7617 + assign { } { } + assign { } { } + assign $0\bit_o[0:0] $1\bit_o[0:0] + attribute \src "libresoc.v:149681.5-149681.29" + switch \initial + attribute \src "libresoc.v:149681.9-149681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_o[0:0] \$22 + case + assign $1\bit_o[0:0] 1'0 + end + sync always + update \bit_o $0\bit_o[0:0] + end + attribute \src "libresoc.v:149691.3-149701.6" + process $proc$libresoc.v:149691$7618 + assign { } { } + assign { } { } + assign $0\full_cr$5[31:0]$7619 $1\full_cr$5[31:0]$7620 + attribute \src "libresoc.v:149692.5-149692.29" + switch \initial + attribute \src "libresoc.v:149692.9-149692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr$5[31:0]$7620 \ra [31:0] + case + assign $1\full_cr$5[31:0]$7620 0 + end + sync always + update \full_cr$5 $0\full_cr$5[31:0]$7619 + end + connect \$10 $sub$libresoc.v:149464$7590_Y + connect \$13 $sub$libresoc.v:149465$7591_Y + connect \$16 $sub$libresoc.v:149466$7592_Y + connect \$18 $ternary$libresoc.v:149467$7593_Y + connect \$20 $ternary$libresoc.v:149468$7594_Y + connect \$22 $ternary$libresoc.v:149469$7595_Y + connect \$24 $pos$libresoc.v:149470$7597_Y + connect \$27 $ternary$libresoc.v:149471$7598_Y + connect \$26 $pos$libresoc.v:149472$7600_Y + connect \$7 $pos$libresoc.v:149473$7602_Y + connect \$9 \$10 + connect \$12 \$13 + connect \$15 \$16 + connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \muxid$1 \muxid +end +attribute \src "libresoc.v:149711.1-150868.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" +attribute \generator "nMigen" +module \mul0 + attribute \src "libresoc.v:150439.3-150440.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:150437.3-150438.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:150780.3-150788.6" + wire $0\alu_l_r_alu$next[0:0]$7827 + attribute \src "libresoc.v:150365.3-150366.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire width 13 $0\alu_mul0_mul_op__fn_unit$next[12:0]$7752 + attribute \src "libresoc.v:150393.3-150394.65" + wire width 13 $0\alu_mul0_mul_op__fn_unit[12:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7753 + attribute \src "libresoc.v:150395.3-150396.79" + wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7754 + attribute \src "libresoc.v:150397.3-150398.75" + wire $0\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7755 + attribute \src "libresoc.v:150413.3-150414.59" + wire width 32 $0\alu_mul0_mul_op__insn[31:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7756 + attribute \src "libresoc.v:150391.3-150392.69" + wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7757 + attribute \src "libresoc.v:150409.3-150410.67" + wire $0\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7758 + attribute \src "libresoc.v:150411.3-150412.69" + wire $0\alu_mul0_mul_op__is_signed[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7759 + attribute \src "libresoc.v:150403.3-150404.63" + wire $0\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7760 + attribute \src "libresoc.v:150405.3-150406.63" + wire $0\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7761 + attribute \src "libresoc.v:150401.3-150402.63" + wire $0\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7762 + attribute \src "libresoc.v:150399.3-150400.63" + wire $0\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7763 + attribute \src "libresoc.v:150407.3-150408.69" + wire $0\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "libresoc.v:150771.3-150779.6" + wire $0\alui_l_r_alui$next[0:0]$7824 + attribute \src "libresoc.v:150367.3-150368.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:150653.3-150674.6" + wire width 64 $0\data_r0__o$next[63:0]$7783 + attribute \src "libresoc.v:150387.3-150388.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:150653.3-150674.6" + wire $0\data_r0__o_ok$next[0:0]$7784 + attribute \src "libresoc.v:150389.3-150390.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:150675.3-150696.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7791 + attribute \src "libresoc.v:150383.3-150384.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:150675.3-150696.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7792 + attribute \src "libresoc.v:150385.3-150386.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:150697.3-150718.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7799 + attribute \src "libresoc.v:150379.3-150380.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:150697.3-150718.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7800 + attribute \src "libresoc.v:150381.3-150382.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:150719.3-150740.6" + wire $0\data_r3__xer_so$next[0:0]$7807 + attribute \src "libresoc.v:150375.3-150376.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:150719.3-150740.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7808 + attribute \src "libresoc.v:150377.3-150378.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:150789.3-150798.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:150799.3-150808.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:150809.3-150818.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:150819.3-150828.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:149712.7-149712.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:150575.3-150583.6" + wire $0\opc_l_r_opc$next[0:0]$7737 + attribute \src "libresoc.v:150423.3-150424.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:150566.3-150574.6" + wire $0\opc_l_s_opc$next[0:0]$7734 + attribute \src "libresoc.v:150425.3-150426.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:150829.3-150837.6" + wire width 4 $0\prev_wr_go$next[3:0]$7834 + attribute \src "libresoc.v:150435.3-150436.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "libresoc.v:150520.3-150529.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:150611.3-150619.6" + wire width 4 $0\req_l_r_req$next[3:0]$7749 + attribute \src "libresoc.v:150415.3-150416.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "libresoc.v:150602.3-150610.6" + wire width 4 $0\req_l_s_req$next[3:0]$7746 + attribute \src "libresoc.v:150417.3-150418.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "libresoc.v:150539.3-150547.6" + wire $0\rok_l_r_rdok$next[0:0]$7725 + attribute \src "libresoc.v:150431.3-150432.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:150530.3-150538.6" + wire $0\rok_l_s_rdok$next[0:0]$7722 + attribute \src "libresoc.v:150433.3-150434.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:150557.3-150565.6" + wire $0\rst_l_r_rst$next[0:0]$7731 + attribute \src "libresoc.v:150427.3-150428.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:150548.3-150556.6" + wire $0\rst_l_s_rst$next[0:0]$7728 + attribute \src "libresoc.v:150429.3-150430.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:150593.3-150601.6" + wire width 3 $0\src_l_r_src$next[2:0]$7743 + attribute \src "libresoc.v:150419.3-150420.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:150584.3-150592.6" + wire width 3 $0\src_l_s_src$next[2:0]$7740 + attribute \src "libresoc.v:150421.3-150422.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:150741.3-150750.6" + wire width 64 $0\src_r0$next[63:0]$7815 + attribute \src "libresoc.v:150373.3-150374.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:150751.3-150760.6" + wire width 64 $0\src_r1$next[63:0]$7818 + attribute \src "libresoc.v:150371.3-150372.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:150761.3-150770.6" + wire $0\src_r2$next[0:0]$7821 + attribute \src "libresoc.v:150369.3-150370.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:149836.7-149836.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:149846.7-149846.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:150780.3-150788.6" + wire $1\alu_l_r_alu$next[0:0]$7828 + attribute \src "libresoc.v:149854.7-149854.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire width 13 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7764 + attribute \src "libresoc.v:149876.14-149876.49" + wire width 13 $1\alu_mul0_mul_op__fn_unit[12:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7765 + attribute \src "libresoc.v:149880.14-149880.68" + wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7766 + attribute \src "libresoc.v:149884.7-149884.43" + wire $1\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7767 + attribute \src "libresoc.v:149888.14-149888.43" + wire width 32 $1\alu_mul0_mul_op__insn[31:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7768 + attribute \src "libresoc.v:149966.13-149966.47" + wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7769 + attribute \src "libresoc.v:149970.7-149970.39" + wire $1\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7770 + attribute \src "libresoc.v:149974.7-149974.40" + wire $1\alu_mul0_mul_op__is_signed[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7771 + attribute \src "libresoc.v:149978.7-149978.37" + wire $1\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7772 + attribute \src "libresoc.v:149982.7-149982.37" + wire $1\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7773 + attribute \src "libresoc.v:149986.7-149986.37" + wire $1\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7774 + attribute \src "libresoc.v:149990.7-149990.37" + wire $1\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7775 + attribute \src "libresoc.v:149994.7-149994.40" + wire $1\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "libresoc.v:150771.3-150779.6" + wire $1\alui_l_r_alui$next[0:0]$7825 + attribute \src "libresoc.v:150024.7-150024.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:150653.3-150674.6" + wire width 64 $1\data_r0__o$next[63:0]$7785 + attribute \src "libresoc.v:150058.14-150058.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:150653.3-150674.6" + wire $1\data_r0__o_ok$next[0:0]$7786 + attribute \src "libresoc.v:150062.7-150062.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:150675.3-150696.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7793 + attribute \src "libresoc.v:150066.13-150066.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:150675.3-150696.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7794 + attribute \src "libresoc.v:150070.7-150070.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:150697.3-150718.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7801 + attribute \src "libresoc.v:150074.13-150074.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:150697.3-150718.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7802 + attribute \src "libresoc.v:150078.7-150078.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:150719.3-150740.6" + wire $1\data_r3__xer_so$next[0:0]$7809 + attribute \src "libresoc.v:150082.7-150082.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:150719.3-150740.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7810 + attribute \src "libresoc.v:150086.7-150086.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:150789.3-150798.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:150799.3-150808.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:150809.3-150818.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:150819.3-150828.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:150575.3-150583.6" + wire $1\opc_l_r_opc$next[0:0]$7738 + attribute \src "libresoc.v:150106.7-150106.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:150566.3-150574.6" + wire $1\opc_l_s_opc$next[0:0]$7735 + attribute \src "libresoc.v:150110.7-150110.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:150829.3-150837.6" + wire width 4 $1\prev_wr_go$next[3:0]$7835 + attribute \src "libresoc.v:150226.13-150226.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "libresoc.v:150520.3-150529.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:150611.3-150619.6" + wire width 4 $1\req_l_r_req$next[3:0]$7750 + attribute \src "libresoc.v:150234.13-150234.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "libresoc.v:150602.3-150610.6" + wire width 4 $1\req_l_s_req$next[3:0]$7747 + attribute \src "libresoc.v:150238.13-150238.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "libresoc.v:150539.3-150547.6" + wire $1\rok_l_r_rdok$next[0:0]$7726 + attribute \src "libresoc.v:150250.7-150250.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:150530.3-150538.6" + wire $1\rok_l_s_rdok$next[0:0]$7723 + attribute \src "libresoc.v:150254.7-150254.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:150557.3-150565.6" + wire $1\rst_l_r_rst$next[0:0]$7732 + attribute \src "libresoc.v:150258.7-150258.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:150548.3-150556.6" + wire $1\rst_l_s_rst$next[0:0]$7729 + attribute \src "libresoc.v:150262.7-150262.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:150593.3-150601.6" + wire width 3 $1\src_l_r_src$next[2:0]$7744 + attribute \src "libresoc.v:150276.13-150276.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:150584.3-150592.6" + wire width 3 $1\src_l_s_src$next[2:0]$7741 + attribute \src "libresoc.v:150280.13-150280.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:150741.3-150750.6" + wire width 64 $1\src_r0$next[63:0]$7816 + attribute \src "libresoc.v:150286.14-150286.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:150751.3-150760.6" + wire width 64 $1\src_r1$next[63:0]$7819 + attribute \src "libresoc.v:150290.14-150290.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:150761.3-150770.6" + wire $1\src_r2$next[0:0]$7822 + attribute \src "libresoc.v:150294.7-150294.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:150620.3-150652.6" + wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7776 + attribute \src "libresoc.v:150620.3-150652.6" + wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7777 + attribute \src "libresoc.v:150620.3-150652.6" + wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7778 + attribute \src "libresoc.v:150620.3-150652.6" + wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7779 + attribute \src "libresoc.v:150620.3-150652.6" + wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7780 + attribute \src "libresoc.v:150620.3-150652.6" + wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7781 + attribute \src "libresoc.v:150653.3-150674.6" + wire width 64 $2\data_r0__o$next[63:0]$7787 + attribute \src "libresoc.v:150653.3-150674.6" + wire $2\data_r0__o_ok$next[0:0]$7788 + attribute \src "libresoc.v:150675.3-150696.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$7795 + attribute \src "libresoc.v:150675.3-150696.6" + wire $2\data_r1__cr_a_ok$next[0:0]$7796 + attribute \src "libresoc.v:150697.3-150718.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$7803 + attribute \src "libresoc.v:150697.3-150718.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$7804 + attribute \src "libresoc.v:150719.3-150740.6" + wire $2\data_r3__xer_so$next[0:0]$7811 + attribute \src "libresoc.v:150719.3-150740.6" + wire $2\data_r3__xer_so_ok$next[0:0]$7812 + attribute \src "libresoc.v:150653.3-150674.6" + wire $3\data_r0__o_ok$next[0:0]$7789 + attribute \src "libresoc.v:150675.3-150696.6" + wire $3\data_r1__cr_a_ok$next[0:0]$7797 + attribute \src "libresoc.v:150697.3-150718.6" + wire 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\enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \mul_op__fn_unit$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$62 + wire width 13 \alu_mul0_mul_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \mul_op__insn + wire width 13 \alu_mul0_mul_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 35 \mul_op__insn$13 + wire width 64 \alu_mul0_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$13$next + wire width 64 \alu_mul0_mul_op__imm_data__data$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$70 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire \alu_mul0_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire \alu_mul0_mul_op__imm_data__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \mul_op__insn_type$2 + wire width 32 \alu_mul0_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$2$next + wire width 32 \alu_mul0_mul_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -328100,119 +314753,151 @@ module \mul_pipe3 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \mul_op__oe__ok + wire width 7 \alu_mul0_mul_op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$66 + wire width 7 \alu_mul0_mul_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \mul_op__oe__ok$9 + wire \alu_mul0_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$9$next + wire \alu_mul0_mul_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__rc__ok + wire \alu_mul0_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$64 + wire \alu_mul0_mul_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \mul_op__rc__ok$7 + wire \alu_mul0_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$7$next + wire \alu_mul0_mul_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__rc__rc + wire \alu_mul0_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \mul_op__rc__rc$6 + wire \alu_mul0_mul_op__oe__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$6$next + wire \alu_mul0_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$63 + wire \alu_mul0_mul_op__rc__ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \mul_op__write_cr0 + wire \alu_mul0_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \mul_op__write_cr0$10 + wire \alu_mul0_mul_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$10$next + wire \alu_mul0_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data + wire \alu_mul0_mul_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 22 \n_ready_i + wire \alu_mul0_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 21 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire input 19 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire input 20 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \neg_res32$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 input 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 36 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 37 \o_ok + wire \alu_mul0_n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$72 + wire width 64 \alu_mul0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \alu_mul0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \alu_mul0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next + wire width 2 \alu_mul0_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a + wire \alu_mul0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_mul0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 32 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$46 + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 15 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 14 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 18 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 17 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 16 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 24 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 23 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 25 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 27 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 29 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 31 \dest4_o + attribute \src "libresoc.v:149712.7-149712.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_mul_op__fn_unit + wire output 22 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -328228,95 +314913,13 @@ module \mul_pipe3 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_mul_op__fn_unit$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_mul_op__imm_data__data$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__imm_data__ok$35 + wire width 13 input 3 \oper_i_alu_mul0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_mul_op__insn + wire width 64 input 4 \oper_i_alu_mul0__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_mul_op__insn$43 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire input 5 \oper_i_alu_mul0__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_mul_op__insn_type + wire width 32 input 13 \oper_i_alu_mul0__insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -328392,610 +314995,1638 @@ module \mul_pipe3 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_mul_op__insn_type$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_32bit$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_signed$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__oe$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__ok + wire width 7 input 2 \oper_i_alu_mul0__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__ok$39 + wire input 11 \oper_i_alu_mul0__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__ok + wire input 12 \oper_i_alu_mul0__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__ok$37 + wire input 8 \oper_i_alu_mul0__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__rc + wire input 9 \oper_i_alu_mul0__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__rc$36 + wire input 7 \oper_i_alu_mul0__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__write_cr0 + wire input 6 \oper_i_alu_mul0__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__write_cr0$40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_muxid$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 40 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 41 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 18 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 42 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 43 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$54 + wire input 10 \oper_i_alu_mul0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 4 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 19 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 20 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 21 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$78 + wire output 28 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:159298$8149 + wire output 30 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:150305$7622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$96 + connect \B \$98 + connect \Y $and$libresoc.v:150305$7622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:150306$7623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$55 - connect \B \p_ready_o - connect \Y $and$libresoc.v:159298$8149_Y + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:150306$7623_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:150307$7624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:150307$7624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:150308$7625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:150308$7625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:150309$7626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:150309$7626_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:150310$7627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $and$libresoc.v:150310$7627_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:150311$7628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B { \$102 \$104 \$106 \$108 } + connect \Y $and$libresoc.v:150311$7628_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$libresoc.v:150312$7629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$110 + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:150312$7629_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:150313$7630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:150313$7630_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:150314$7631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:150314$7631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:150315$7632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:150315$7632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $and$libresoc.v:150316$7633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $and$libresoc.v:150316$7633_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:150318$7635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$12 + connect \Y $and$libresoc.v:150318$7635_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:150320$7637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$16 + connect \Y $and$libresoc.v:150320$7637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $and$libresoc.v:150321$7638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:150321$7638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:150323$7640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__rel_o + connect \B \$24 + connect \Y $and$libresoc.v:150323$7640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:150326$7643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:150326$7643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$libresoc.v:150327$7644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$22 + connect \Y $and$libresoc.v:150327$7644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:150332$7649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$38 + connect \Y $and$libresoc.v:150332$7649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:150333$7650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:150333$7650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:150335$7652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \B \$44 + connect \Y $and$libresoc.v:150335$7652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:150337$7654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$48 + connect \B \alu_mul0_n_ready_i + connect \Y $and$libresoc.v:150337$7654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:150338$7655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$50 + connect \B \alu_mul0_n_valid_o + connect \Y $and$libresoc.v:150338$7655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:150339$7656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$52 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:150339$7656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:150345$7662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:150345$7662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:150346$7663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:150346$7663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:150348$7665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:150348$7665_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:150349$7666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:150349$7666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:150350$7667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:150350$7667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:150351$7668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:150351$7668_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:150358$7675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:150358$7675_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:150360$7677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:150360$7677_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:150361$7678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:150361$7678_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:150363$7680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$92 + connect \B { 1'1 \$94 1'1 } + connect \Y $and$libresoc.v:150363$7680_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:150334$7651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$libresoc.v:150334$7651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:150336$7653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:150336$7653_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:150317$7634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:150317$7634_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:150319$7636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:150319$7636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:150322$7639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:150322$7639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:150325$7642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:150325$7642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:150331$7648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_ready_i + connect \Y $not$libresoc.v:150331$7648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:150342$7659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:150342$7659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:150362$7679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_mul_op__imm_data__ok + connect \Y $not$libresoc.v:150362$7679_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:150364$7681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:150364$7681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:150330$7647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:150330$7647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:150340$7657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:150340$7657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:150341$7658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:150341$7658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:150343$7660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:150343$7660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:150344$7661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:150344$7661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:150347$7664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:150347$7664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:150353$7670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:150353$7670_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:150359$7676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:150359$7676_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:150324$7641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:150324$7641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:150328$7645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:150328$7645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:150329$7646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:150329$7646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:150352$7669 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$libresoc.v:150352$7669_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:150354$7671 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_mul0_mul_op__imm_data__data + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$libresoc.v:150354$7671_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:150355$7672 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:150355$7672_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:150356$7673 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:150356$7673_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:150357$7674 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:150357$7674_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:159343.8-159379.4" - cell \mul3 \mul3 - connect \mul_op__fn_unit \mul3_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 - connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 - connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 - connect \mul_op__insn \mul3_mul_op__insn - connect \mul_op__insn$13 \mul3_mul_op__insn$28 - connect \mul_op__insn_type \mul3_mul_op__insn_type - connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 - connect \mul_op__is_32bit \mul3_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 - connect \mul_op__is_signed \mul3_mul_op__is_signed - connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 - connect \mul_op__oe__oe \mul3_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 - connect \mul_op__oe__ok \mul3_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 - connect \mul_op__rc__ok \mul3_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 - connect \mul_op__rc__rc \mul3_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 - connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 - connect \muxid \mul3_muxid - connect \muxid$1 \mul3_muxid$16 - connect \neg_res \mul3_neg_res - connect \o \mul3_o - connect \o$14 \mul3_o$29 - connect \o_ok \mul3_o_ok - connect \xer_ov \mul3_xer_ov - connect \xer_ov_ok \mul3_xer_ov_ok - connect \xer_so \mul3_xer_so - connect \xer_so$15 \mul3_xer_so$30 - connect \xer_so_ok \mul3_xer_so_ok + attribute \src "libresoc.v:150441.15-150447.4" + cell \alu_l$107 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:159380.10-159383.4" - cell \n$99 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:150448.12-150478.4" + cell \alu_mul0 \alu_mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_mul0_cr_a + connect \cr_a_ok \cr_a_ok + connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit + connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data + connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok + connect \mul_op__insn \alu_mul0_mul_op__insn + connect \mul_op__insn_type \alu_mul0_mul_op__insn_type + connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit + connect \mul_op__is_signed \alu_mul0_mul_op__is_signed + connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe + connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok + connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok + connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc + connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 + connect \n_ready_i \alu_mul0_n_ready_i + connect \n_valid_o \alu_mul0_n_valid_o + connect \o \alu_mul0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_mul0_p_ready_o + connect \p_valid_i \alu_mul0_p_valid_i + connect \ra \alu_mul0_ra + connect \rb \alu_mul0_rb + connect \xer_ov \alu_mul0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_mul0_xer_so + connect \xer_so$1 \alu_mul0_xer_so$1 + connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:159384.16-159424.4" - cell \output$100 \output - connect \cr_a \output_cr_a - connect \cr_a$16 \output_cr_a$46 - connect \cr_a_ok \output_cr_a_ok - connect \mul_op__fn_unit \output_mul_op__fn_unit - connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 - connect \mul_op__imm_data__data \output_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 - connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 - connect \mul_op__insn \output_mul_op__insn - connect \mul_op__insn$13 \output_mul_op__insn$43 - connect \mul_op__insn_type \output_mul_op__insn_type - connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 - connect \mul_op__is_32bit \output_mul_op__is_32bit - connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 - connect \mul_op__is_signed \output_mul_op__is_signed - connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 - connect \mul_op__oe__oe \output_mul_op__oe__oe - connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 - connect \mul_op__oe__ok \output_mul_op__oe__ok - connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 - connect \mul_op__rc__ok \output_mul_op__rc__ok - connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 - connect \mul_op__rc__rc \output_mul_op__rc__rc - connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 - connect \mul_op__write_cr0 \output_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$31 - connect \o \output_o - connect \o$14 \output_o$44 - connect \o_ok \output_o_ok - connect \o_ok$15 \output_o_ok$45 - connect \xer_ov \output_xer_ov - connect \xer_ov$17 \output_xer_ov$47 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so \output_xer_so - connect \xer_so$18 \output_xer_so$48 - connect \xer_so_ok \output_xer_so_ok + attribute \src "libresoc.v:150479.16-150485.4" + cell \alui_l$106 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:159425.10-159428.4" - cell \p$98 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i + attribute \src "libresoc.v:150486.15-150492.4" + cell \opc_l$102 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150493.15-150499.4" + cell \req_l$103 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150500.15-150506.4" + cell \rok_l$105 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150507.15-150512.4" + cell \rst_l$104 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:150513.15-150519.4" + cell \src_l$101 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src end - attribute \src "libresoc.v:158316.7-158316.20" - process $proc$libresoc.v:158316$8249 + attribute \src "libresoc.v:149712.7-149712.20" + process $proc$libresoc.v:149712$7836 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158325.13-158325.24" - process $proc$libresoc.v:158325$8250 + attribute \src "libresoc.v:149836.7-149836.24" + process $proc$libresoc.v:149836$7837 assign { } { } - assign $1\cr_a[3:0] 4'0000 + assign $1\all_rd_dly[0:0] 1'0 sync always sync init - update \cr_a $1\cr_a[3:0] + update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:158334.7-158334.21" - process $proc$libresoc.v:158334$8251 + attribute \src "libresoc.v:149846.7-149846.26" + process $proc$libresoc.v:149846$7838 assign { } { } - assign $1\cr_a_ok[0:0] 1'0 + assign $1\alu_done_dly[0:0] 1'0 sync always sync init - update \cr_a_ok $1\cr_a_ok[0:0] + update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:158621.14-158621.44" - process $proc$libresoc.v:158621$8252 + attribute \src "libresoc.v:149854.7-149854.25" + process $proc$libresoc.v:149854$7839 assign { } { } - assign $0\mul_op__fn_unit$3[12:0]$8253 13'0000000000000 + assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8253 + update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:158644.14-158644.63" - process $proc$libresoc.v:158644$8254 + attribute \src "libresoc.v:149876.14-149876.49" + process $proc$libresoc.v:149876$7840 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8255 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_mul0_mul_op__fn_unit[12:0] 13'0000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8255 + update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[12:0] end - attribute \src "libresoc.v:158653.7-158653.38" - process $proc$libresoc.v:158653$8256 + attribute \src "libresoc.v:149880.14-149880.68" + process $proc$libresoc.v:149880$7841 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8257 1'0 + assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8257 + update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:158662.14-158662.39" - process $proc$libresoc.v:158662$8258 + attribute \src "libresoc.v:149884.7-149884.43" + process $proc$libresoc.v:149884$7842 assign { } { } - assign $0\mul_op__insn$13[31:0]$8259 0 + assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8259 + update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:158819.13-158819.42" - process $proc$libresoc.v:158819$8260 + attribute \src "libresoc.v:149888.14-149888.43" + process $proc$libresoc.v:149888$7843 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8261 7'0000000 + assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8261 + update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:158902.7-158902.35" - process $proc$libresoc.v:158902$8262 + attribute \src "libresoc.v:149966.13-149966.47" + process $proc$libresoc.v:149966$7844 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8263 1'0 + assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8263 + update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:158911.7-158911.36" - process $proc$libresoc.v:158911$8264 + attribute \src "libresoc.v:149970.7-149970.39" + process $proc$libresoc.v:149970$7845 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8265 1'0 + assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8265 + update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:158922.7-158922.32" - process $proc$libresoc.v:158922$8266 + attribute \src "libresoc.v:149974.7-149974.40" + process $proc$libresoc.v:149974$7846 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8267 1'0 + assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8267 + update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:158931.7-158931.32" - process $proc$libresoc.v:158931$8268 + attribute \src "libresoc.v:149978.7-149978.37" + process $proc$libresoc.v:149978$7847 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8269 1'0 + assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8269 + update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:158940.7-158940.32" - process $proc$libresoc.v:158940$8270 + attribute \src "libresoc.v:149982.7-149982.37" + process $proc$libresoc.v:149982$7848 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8271 1'0 + assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8271 + update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:158947.7-158947.32" - process $proc$libresoc.v:158947$8272 + attribute \src "libresoc.v:149986.7-149986.37" + process $proc$libresoc.v:149986$7849 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8273 1'0 + assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8273 + update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:158956.7-158956.36" - process $proc$libresoc.v:158956$8274 + attribute \src "libresoc.v:149990.7-149990.37" + process $proc$libresoc.v:149990$7850 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8275 1'0 + assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8275 + update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:158965.13-158965.29" - process $proc$libresoc.v:158965$8276 + attribute \src "libresoc.v:149994.7-149994.40" + process $proc$libresoc.v:149994$7851 assign { } { } - assign $0\muxid$1[1:0]$8277 2'00 + assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8277 + update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:158986.14-158986.43" - process $proc$libresoc.v:158986$8278 + attribute \src "libresoc.v:150024.7-150024.27" + process $proc$libresoc.v:150024$7852 assign { } { } - assign $0\o$14[63:0]$8279 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init - update \o$14 $0\o$14[63:0]$8279 + update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:158993.7-158993.18" - process $proc$libresoc.v:158993$8280 + attribute \src "libresoc.v:150058.14-150058.47" + process $proc$libresoc.v:150058$7853 assign { } { } - assign $1\o_ok[0:0] 1'0 + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o_ok $1\o_ok[0:0] + update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:159261.7-159261.20" - process $proc$libresoc.v:159261$8281 + attribute \src "libresoc.v:150062.7-150062.27" + process $proc$libresoc.v:150062$7854 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:159266.13-159266.26" - process $proc$libresoc.v:159266$8282 + attribute \src "libresoc.v:150066.13-150066.33" + process $proc$libresoc.v:150066$7855 assign { } { } - assign $1\xer_ov[1:0] 2'00 + assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init - update \xer_ov $1\xer_ov[1:0] + update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:159273.7-159273.23" - process $proc$libresoc.v:159273$8283 + attribute \src "libresoc.v:150070.7-150070.30" + process $proc$libresoc.v:150070$7856 assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 + assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:159284.7-159284.25" - process $proc$libresoc.v:159284$8284 + attribute \src "libresoc.v:150074.13-150074.35" + process $proc$libresoc.v:150074$7857 assign { } { } - assign $0\xer_so$15[0:0]$8285 1'0 + assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init - update \xer_so$15 $0\xer_so$15[0:0]$8285 + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:159291.7-159291.23" - process $proc$libresoc.v:159291$8286 + attribute \src "libresoc.v:150078.7-150078.32" + process $proc$libresoc.v:150078$7858 assign { } { } - assign $1\xer_so_ok[0:0] 1'0 + assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init - update \xer_so_ok $1\xer_so_ok[0:0] + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:150082.7-150082.29" + process $proc$libresoc.v:150082$7859 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:150086.7-150086.32" + process $proc$libresoc.v:150086$7860 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:150106.7-150106.25" + process $proc$libresoc.v:150106$7861 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:150110.7-150110.25" + process $proc$libresoc.v:150110$7862 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:150226.13-150226.30" + process $proc$libresoc.v:150226$7863 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "libresoc.v:150234.13-150234.31" + process $proc$libresoc.v:150234$7864 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "libresoc.v:150238.13-150238.31" + process $proc$libresoc.v:150238$7865 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "libresoc.v:150250.7-150250.26" + process $proc$libresoc.v:150250$7866 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:150254.7-150254.26" + process $proc$libresoc.v:150254$7867 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:150258.7-150258.25" + process $proc$libresoc.v:150258$7868 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:150262.7-150262.25" + process $proc$libresoc.v:150262$7869 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:150276.13-150276.31" + process $proc$libresoc.v:150276$7870 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:150280.13-150280.31" + process $proc$libresoc.v:150280$7871 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:150286.14-150286.43" + process $proc$libresoc.v:150286$7872 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:150290.14-150290.43" + process $proc$libresoc.v:150290$7873 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:150294.7-150294.20" + process $proc$libresoc.v:150294$7874 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:159299.3-159300.37" - process $proc$libresoc.v:159299$8150 + attribute \src "libresoc.v:150365.3-150366.39" + process $proc$libresoc.v:150365$7682 assign { } { } - assign $0\xer_so$15[0:0]$8151 \xer_so$15$next + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk - update \xer_so$15 $0\xer_so$15[0:0]$8151 + update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:159301.3-159302.35" - process $proc$libresoc.v:159301$8152 + attribute \src "libresoc.v:150367.3-150368.43" + process $proc$libresoc.v:150367$7683 assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] + update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:159303.3-159304.29" - process $proc$libresoc.v:159303$8153 + attribute \src "libresoc.v:150369.3-150370.29" + process $proc$libresoc.v:150369$7684 assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next + assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] + update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:159305.3-159306.35" - process $proc$libresoc.v:159305$8154 + attribute \src "libresoc.v:150371.3-150372.29" + process $proc$libresoc.v:150371$7685 assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] + update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:159307.3-159308.25" - process $proc$libresoc.v:159307$8155 + attribute \src "libresoc.v:150373.3-150374.29" + process $proc$libresoc.v:150373$7686 assign { } { } - assign $0\cr_a[3:0] \cr_a$next + assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] + update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:159309.3-159310.31" - process $proc$libresoc.v:159309$8156 + attribute \src "libresoc.v:150375.3-150376.47" + process $proc$libresoc.v:150375$7687 assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] + update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:159311.3-159312.27" - process $proc$libresoc.v:159311$8157 + attribute \src "libresoc.v:150377.3-150378.53" + process $proc$libresoc.v:150377$7688 assign { } { } - assign $0\o$14[63:0]$8158 \o$14$next + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk - update \o$14 $0\o$14[63:0]$8158 + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:159313.3-159314.25" - process $proc$libresoc.v:159313$8159 + attribute \src "libresoc.v:150379.3-150380.47" + process $proc$libresoc.v:150379$7689 assign { } { } - assign $0\o_ok[0:0] \o_ok$next + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:150381.3-150382.53" + process $proc$libresoc.v:150381$7690 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:150383.3-150384.43" + process $proc$libresoc.v:150383$7691 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:150385.3-150386.49" + process $proc$libresoc.v:150385$7692 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:150387.3-150388.37" + process $proc$libresoc.v:150387$7693 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:150389.3-150390.43" + process $proc$libresoc.v:150389$7694 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:150391.3-150392.69" + process $proc$libresoc.v:150391$7695 + assign { } { } + assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:150393.3-150394.65" + process $proc$libresoc.v:150393$7696 + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit[12:0] \alu_mul0_mul_op__fn_unit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[12:0] + end + attribute \src "libresoc.v:150395.3-150396.79" + process $proc$libresoc.v:150395$7697 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:150397.3-150398.75" + process $proc$libresoc.v:150397$7698 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:150399.3-150400.63" + process $proc$libresoc.v:150399$7699 + assign { } { } + assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:150401.3-150402.63" + process $proc$libresoc.v:150401$7700 + assign { } { } + assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:150403.3-150404.63" + process $proc$libresoc.v:150403$7701 + assign { } { } + assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:150405.3-150406.63" + process $proc$libresoc.v:150405$7702 + assign { } { } + assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:150407.3-150408.69" + process $proc$libresoc.v:150407$7703 + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:150409.3-150410.67" + process $proc$libresoc.v:150409$7704 + assign { } { } + assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:150411.3-150412.69" + process $proc$libresoc.v:150411$7705 + assign { } { } + assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:150413.3-150414.59" + process $proc$libresoc.v:150413$7706 + assign { } { } + assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] + end + attribute \src "libresoc.v:150415.3-150416.39" + process $proc$libresoc.v:150415$7707 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "libresoc.v:150417.3-150418.39" + process $proc$libresoc.v:150417$7708 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:159315.3-159316.57" - process $proc$libresoc.v:159315$8160 + attribute \src "libresoc.v:150419.3-150420.39" + process $proc$libresoc.v:150419$7709 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8161 \mul_op__insn_type$2$next + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:150421.3-150422.39" + process $proc$libresoc.v:150421$7710 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8161 + update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:159317.3-159318.53" - process $proc$libresoc.v:159317$8162 + attribute \src "libresoc.v:150423.3-150424.39" + process $proc$libresoc.v:150423$7711 assign { } { } - assign $0\mul_op__fn_unit$3[12:0]$8163 \mul_op__fn_unit$3$next + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8163 + update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:159319.3-159320.67" - process $proc$libresoc.v:159319$8164 + attribute \src "libresoc.v:150425.3-150426.39" + process $proc$libresoc.v:150425$7712 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8165 \mul_op__imm_data__data$4$next + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8165 + update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:159321.3-159322.63" - process $proc$libresoc.v:159321$8166 + attribute \src "libresoc.v:150427.3-150428.39" + process $proc$libresoc.v:150427$7713 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8167 \mul_op__imm_data__ok$5$next + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8167 + update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:159323.3-159324.51" - process $proc$libresoc.v:159323$8168 + attribute \src "libresoc.v:150429.3-150430.39" + process $proc$libresoc.v:150429$7714 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8169 \mul_op__rc__rc$6$next + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8169 + update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:159325.3-159326.51" - process $proc$libresoc.v:159325$8170 + attribute \src "libresoc.v:150431.3-150432.41" + process $proc$libresoc.v:150431$7715 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8171 \mul_op__rc__ok$7$next + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8171 + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:159327.3-159328.51" - process $proc$libresoc.v:159327$8172 + attribute \src "libresoc.v:150433.3-150434.41" + process $proc$libresoc.v:150433$7716 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8173 \mul_op__oe__oe$8$next + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8173 + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:159329.3-159330.51" - process $proc$libresoc.v:159329$8174 + attribute \src "libresoc.v:150435.3-150436.37" + process $proc$libresoc.v:150435$7717 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8175 \mul_op__oe__ok$9$next + assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8175 + update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:159331.3-159332.59" - process $proc$libresoc.v:159331$8176 + attribute \src "libresoc.v:150437.3-150438.40" + process $proc$libresoc.v:150437$7718 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8177 \mul_op__write_cr0$10$next + assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8177 + update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:159333.3-159334.57" - process $proc$libresoc.v:159333$8178 + attribute \src "libresoc.v:150439.3-150440.25" + process $proc$libresoc.v:150439$7719 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8179 \mul_op__is_32bit$11$next + assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8179 + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:150520.3-150529.6" + process $proc$libresoc.v:150520$7720 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:150521.5-150521.29" + switch \initial + attribute \src "libresoc.v:150521.9-150521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:150530.3-150538.6" + process $proc$libresoc.v:150530$7721 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$7722 $1\rok_l_s_rdok$next[0:0]$7723 + attribute \src "libresoc.v:150531.5-150531.29" + switch \initial + attribute \src "libresoc.v:150531.9-150531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$7723 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$7723 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7722 + end + attribute \src "libresoc.v:150539.3-150547.6" + process $proc$libresoc.v:150539$7724 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$7725 $1\rok_l_r_rdok$next[0:0]$7726 + attribute \src "libresoc.v:150540.5-150540.29" + switch \initial + attribute \src "libresoc.v:150540.9-150540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$7726 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$7726 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7725 + end + attribute \src "libresoc.v:150548.3-150556.6" + process $proc$libresoc.v:150548$7727 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$7728 $1\rst_l_s_rst$next[0:0]$7729 + attribute \src "libresoc.v:150549.5-150549.29" + switch \initial + attribute \src "libresoc.v:150549.9-150549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$7729 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$7729 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7728 + end + attribute \src "libresoc.v:150557.3-150565.6" + process $proc$libresoc.v:150557$7730 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$7731 $1\rst_l_r_rst$next[0:0]$7732 + attribute \src "libresoc.v:150558.5-150558.29" + switch \initial + attribute \src "libresoc.v:150558.9-150558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$7732 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$7732 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7731 end - attribute \src "libresoc.v:159335.3-159336.59" - process $proc$libresoc.v:159335$8180 + attribute \src "libresoc.v:150566.3-150574.6" + process $proc$libresoc.v:150566$7733 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8181 \mul_op__is_signed$12$next - sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8181 - end - attribute \src "libresoc.v:159337.3-159338.49" - process $proc$libresoc.v:159337$8182 assign { } { } - assign $0\mul_op__insn$13[31:0]$8183 \mul_op__insn$13$next - sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8183 + assign $0\opc_l_s_opc$next[0:0]$7734 $1\opc_l_s_opc$next[0:0]$7735 + attribute \src "libresoc.v:150567.5-150567.29" + switch \initial + attribute \src "libresoc.v:150567.9-150567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$7735 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$7735 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7734 end - attribute \src "libresoc.v:159339.3-159340.33" - process $proc$libresoc.v:159339$8184 + attribute \src "libresoc.v:150575.3-150583.6" + process $proc$libresoc.v:150575$7736 assign { } { } - assign $0\muxid$1[1:0]$8185 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8185 - end - attribute \src "libresoc.v:159341.3-159342.29" - process $proc$libresoc.v:159341$8186 assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + assign $0\opc_l_r_opc$next[0:0]$7737 $1\opc_l_r_opc$next[0:0]$7738 + attribute \src "libresoc.v:150576.5-150576.29" + switch \initial + attribute \src "libresoc.v:150576.9-150576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$7738 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$7738 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7737 end - attribute \src "libresoc.v:159429.3-159446.6" - process $proc$libresoc.v:159429$8187 + attribute \src "libresoc.v:150584.3-150592.6" + process $proc$libresoc.v:150584$7739 assign { } { } assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8188 $2\r_busy$next[0:0]$8190 - attribute \src "libresoc.v:159430.5-159430.29" + assign $0\src_l_s_src$next[2:0]$7740 $1\src_l_s_src$next[2:0]$7741 + attribute \src "libresoc.v:150585.5-150585.29" switch \initial - attribute \src "libresoc.v:159430.9-159430.17" + attribute \src "libresoc.v:150585.9-150585.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$8189 1'1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\r_busy$next[0:0]$8189 1'0 + assign $1\src_l_s_src$next[2:0]$7741 3'000 + case + assign $1\src_l_s_src$next[2:0]$7741 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7740 + end + attribute \src "libresoc.v:150593.3-150601.6" + process $proc$libresoc.v:150593$7742 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$7743 $1\src_l_r_src$next[2:0]$7744 + attribute \src "libresoc.v:150594.5-150594.29" + switch \initial + attribute \src "libresoc.v:150594.9-150594.17" + case 1'1 case - assign $1\r_busy$next[0:0]$8189 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8190 1'0 + assign $1\src_l_r_src$next[2:0]$7744 3'111 case - assign $2\r_busy$next[0:0]$8190 $1\r_busy$next[0:0]$8189 + assign $1\src_l_r_src$next[2:0]$7744 \reset_r end sync always - update \r_busy$next $0\r_busy$next[0:0]$8188 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7743 end - attribute \src "libresoc.v:159447.3-159459.6" - process $proc$libresoc.v:159447$8191 + attribute \src "libresoc.v:150602.3-150610.6" + process $proc$libresoc.v:150602$7745 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8192 $1\muxid$1$next[1:0]$8193 - attribute \src "libresoc.v:159448.5-159448.29" + assign $0\req_l_s_req$next[3:0]$7746 $1\req_l_s_req$next[3:0]$7747 + attribute \src "libresoc.v:150603.5-150603.29" switch \initial - attribute \src "libresoc.v:159448.9-159448.17" + attribute \src "libresoc.v:150603.9-150603.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\muxid$1$next[1:0]$8193 \muxid$58 + assign $1\req_l_s_req$next[3:0]$7747 4'0000 + case + assign $1\req_l_s_req$next[3:0]$7747 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7746 + end + attribute \src "libresoc.v:150611.3-150619.6" + process $proc$libresoc.v:150611$7748 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$7749 $1\req_l_r_req$next[3:0]$7750 + attribute \src "libresoc.v:150612.5-150612.29" + switch \initial + attribute \src "libresoc.v:150612.9-150612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\muxid$1$next[1:0]$8193 \muxid$58 + assign $1\req_l_r_req$next[3:0]$7750 4'1111 case - assign $1\muxid$1$next[1:0]$8193 \muxid$1 + assign $1\req_l_r_req$next[3:0]$7750 \$68 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8192 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7749 end - attribute \src "libresoc.v:159460.3-159495.6" - process $proc$libresoc.v:159460$8194 + attribute \src "libresoc.v:150620.3-150652.6" + process $proc$libresoc.v:150620$7751 assign { } { } assign { } { } assign { } { } @@ -329020,34 +316651,34 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[12:0]$8195 $1\mul_op__fn_unit$3$next[12:0]$8207 + assign $0\alu_mul0_mul_op__fn_unit$next[12:0]$7752 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7764 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8198 $1\mul_op__insn$13$next[31:0]$8210 - assign $0\mul_op__insn_type$2$next[6:0]$8199 $1\mul_op__insn_type$2$next[6:0]$8211 - assign $0\mul_op__is_32bit$11$next[0:0]$8200 $1\mul_op__is_32bit$11$next[0:0]$8212 - assign $0\mul_op__is_signed$12$next[0:0]$8201 $1\mul_op__is_signed$12$next[0:0]$8213 + assign $0\alu_mul0_mul_op__insn$next[31:0]$7755 $1\alu_mul0_mul_op__insn$next[31:0]$7767 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7756 $1\alu_mul0_mul_op__insn_type$next[6:0]$7768 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7757 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7769 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7758 $1\alu_mul0_mul_op__is_signed$next[0:0]$7770 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8206 $1\mul_op__write_cr0$10$next[0:0]$8218 - assign $0\mul_op__imm_data__data$4$next[63:0]$8196 $2\mul_op__imm_data__data$4$next[63:0]$8219 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8197 $2\mul_op__imm_data__ok$5$next[0:0]$8220 - assign $0\mul_op__oe__oe$8$next[0:0]$8202 $2\mul_op__oe__oe$8$next[0:0]$8221 - assign $0\mul_op__oe__ok$9$next[0:0]$8203 $2\mul_op__oe__ok$9$next[0:0]$8222 - assign $0\mul_op__rc__ok$7$next[0:0]$8204 $2\mul_op__rc__ok$7$next[0:0]$8223 - assign $0\mul_op__rc__rc$6$next[0:0]$8205 $2\mul_op__rc__rc$6$next[0:0]$8224 - attribute \src "libresoc.v:159461.5-159461.29" + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7763 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7775 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7753 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7776 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7754 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7777 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7759 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7778 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7760 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7779 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7761 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7780 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7762 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7781 + attribute \src "libresoc.v:150621.5-150621.29" switch \initial - attribute \src "libresoc.v:159461.9-159461.17" + attribute \src "libresoc.v:150621.9-150621.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } assign { } { } assign { } { } @@ -329060,3465 +316691,4328 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8210 $1\mul_op__is_signed$12$next[0:0]$8213 $1\mul_op__is_32bit$11$next[0:0]$8212 $1\mul_op__write_cr0$10$next[0:0]$8218 $1\mul_op__oe__ok$9$next[0:0]$8215 $1\mul_op__oe__oe$8$next[0:0]$8214 $1\mul_op__rc__ok$7$next[0:0]$8216 $1\mul_op__rc__rc$6$next[0:0]$8217 $1\mul_op__imm_data__ok$5$next[0:0]$8209 $1\mul_op__imm_data__data$4$next[63:0]$8208 $1\mul_op__fn_unit$3$next[12:0]$8207 $1\mul_op__insn_type$2$next[6:0]$8211 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7767 $1\alu_mul0_mul_op__is_signed$next[0:0]$7770 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7769 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7775 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7772 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7771 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7773 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7774 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7766 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7765 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7764 $1\alu_mul0_mul_op__insn_type$next[6:0]$7768 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + case + assign $1\alu_mul0_mul_op__fn_unit$next[12:0]$7764 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7765 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7766 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7767 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7768 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7769 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7770 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7771 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7772 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7773 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7774 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7775 \alu_mul0_mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } + case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7776 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7777 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7781 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7780 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7778 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7779 1'0 + case + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7776 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7765 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7777 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7766 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7778 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7771 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7779 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7772 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7780 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7773 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7781 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7774 + end + sync always + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[12:0]$7752 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7753 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7754 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7755 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7756 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7757 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7758 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7759 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7760 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7761 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7762 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7763 + end + attribute \src "libresoc.v:150653.3-150674.6" + process $proc$libresoc.v:150653$7782 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$7783 $2\data_r0__o$next[63:0]$7787 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$7784 $3\data_r0__o_ok$next[0:0]$7789 + attribute \src "libresoc.v:150654.5-150654.29" + switch \initial + attribute \src "libresoc.v:150654.9-150654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$7786 $1\data_r0__o$next[63:0]$7785 } { \o_ok \alu_mul0_o } + case + assign $1\data_r0__o$next[63:0]$7785 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7786 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8210 $1\mul_op__is_signed$12$next[0:0]$8213 $1\mul_op__is_32bit$11$next[0:0]$8212 $1\mul_op__write_cr0$10$next[0:0]$8218 $1\mul_op__oe__ok$9$next[0:0]$8215 $1\mul_op__oe__oe$8$next[0:0]$8214 $1\mul_op__rc__ok$7$next[0:0]$8216 $1\mul_op__rc__rc$6$next[0:0]$8217 $1\mul_op__imm_data__ok$5$next[0:0]$8209 $1\mul_op__imm_data__data$4$next[63:0]$8208 $1\mul_op__fn_unit$3$next[12:0]$8207 $1\mul_op__insn_type$2$next[6:0]$8211 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $2\data_r0__o_ok$next[0:0]$7788 $2\data_r0__o$next[63:0]$7787 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $1\mul_op__fn_unit$3$next[12:0]$8207 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8208 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8209 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8210 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8211 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8212 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8213 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8214 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8215 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8216 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8217 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8218 \mul_op__write_cr0$10 + assign $2\data_r0__o$next[63:0]$7787 $1\data_r0__o$next[63:0]$7785 + assign $2\data_r0__o_ok$next[0:0]$7788 $1\data_r0__o_ok$next[0:0]$7786 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8219 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8220 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8224 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8223 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8221 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8222 1'0 + assign $3\data_r0__o_ok$next[0:0]$7789 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8219 $1\mul_op__imm_data__data$4$next[63:0]$8208 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8220 $1\mul_op__imm_data__ok$5$next[0:0]$8209 - assign $2\mul_op__oe__oe$8$next[0:0]$8221 $1\mul_op__oe__oe$8$next[0:0]$8214 - assign $2\mul_op__oe__ok$9$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8215 - assign $2\mul_op__rc__ok$7$next[0:0]$8223 $1\mul_op__rc__ok$7$next[0:0]$8216 - assign $2\mul_op__rc__rc$6$next[0:0]$8224 $1\mul_op__rc__rc$6$next[0:0]$8217 + assign $3\data_r0__o_ok$next[0:0]$7789 $2\data_r0__o_ok$next[0:0]$7788 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$8195 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8196 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8197 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8198 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8199 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8200 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8201 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8202 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8203 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8204 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8205 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8206 + update \data_r0__o$next $0\data_r0__o$next[63:0]$7783 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7784 end - attribute \src "libresoc.v:159496.3-159514.6" - process $proc$libresoc.v:159496$8225 + attribute \src "libresoc.v:150675.3-150696.6" + process $proc$libresoc.v:150675$7790 + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\data_r1__cr_a$next[3:0]$7791 $2\data_r1__cr_a$next[3:0]$7795 assign { } { } - assign $0\o$14$next[63:0]$8227 $1\o$14$next[63:0]$8229 - assign $0\o_ok$next[0:0]$8226 $2\o_ok$next[0:0]$8230 - attribute \src "libresoc.v:159497.5-159497.29" + assign $0\data_r1__cr_a_ok$next[0:0]$7792 $3\data_r1__cr_a_ok$next[0:0]$7797 + attribute \src "libresoc.v:150676.5-150676.29" switch \initial - attribute \src "libresoc.v:159497.9-159497.17" + attribute \src "libresoc.v:150676.9-150676.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8228 $1\o$14$next[63:0]$8229 } { \o_ok$72 \o$71 } + assign { $1\data_r1__cr_a_ok$next[0:0]$7794 $1\data_r1__cr_a$next[3:0]$7793 } { \cr_a_ok \alu_mul0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$7793 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7794 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8228 $1\o$14$next[63:0]$8229 } { \o_ok$72 \o$71 } + assign { $2\data_r1__cr_a_ok$next[0:0]$7796 $2\data_r1__cr_a$next[3:0]$7795 } 5'00000 case - assign $1\o_ok$next[0:0]$8228 \o_ok - assign $1\o$14$next[63:0]$8229 \o$14 + assign $2\data_r1__cr_a$next[3:0]$7795 $1\data_r1__cr_a$next[3:0]$7793 + assign $2\data_r1__cr_a_ok$next[0:0]$7796 $1\data_r1__cr_a_ok$next[0:0]$7794 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8230 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$7797 1'0 case - assign $2\o_ok$next[0:0]$8230 $1\o_ok$next[0:0]$8228 + assign $3\data_r1__cr_a_ok$next[0:0]$7797 $2\data_r1__cr_a_ok$next[0:0]$7796 end sync always - update \o_ok$next $0\o_ok$next[0:0]$8226 - update \o$14$next $0\o$14$next[63:0]$8227 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7791 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7792 end - attribute \src "libresoc.v:159515.3-159533.6" - process $proc$libresoc.v:159515$8231 + attribute \src "libresoc.v:150697.3-150718.6" + process $proc$libresoc.v:150697$7798 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8232 $1\cr_a$next[3:0]$8234 assign { } { } - assign $0\cr_a_ok$next[0:0]$8233 $2\cr_a_ok$next[0:0]$8236 - attribute \src "libresoc.v:159516.5-159516.29" + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$7799 $2\data_r2__xer_ov$next[1:0]$7803 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$7800 $3\data_r2__xer_ov_ok$next[0:0]$7805 + attribute \src "libresoc.v:150698.5-150698.29" switch \initial - attribute \src "libresoc.v:159516.9-159516.17" + attribute \src "libresoc.v:150698.9-150698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8235 $1\cr_a$next[3:0]$8234 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7802 $1\data_r2__xer_ov$next[1:0]$7801 } { \xer_ov_ok \alu_mul0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$7801 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7802 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8235 $1\cr_a$next[3:0]$8234 } { \cr_a_ok$74 \cr_a$73 } + assign { $2\data_r2__xer_ov_ok$next[0:0]$7804 $2\data_r2__xer_ov$next[1:0]$7803 } 3'000 case - assign $1\cr_a$next[3:0]$8234 \cr_a - assign $1\cr_a_ok$next[0:0]$8235 \cr_a_ok + assign $2\data_r2__xer_ov$next[1:0]$7803 $1\data_r2__xer_ov$next[1:0]$7801 + assign $2\data_r2__xer_ov_ok$next[0:0]$7804 $1\data_r2__xer_ov_ok$next[0:0]$7802 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8236 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$7805 1'0 case - assign $2\cr_a_ok$next[0:0]$8236 $1\cr_a_ok$next[0:0]$8235 + assign $3\data_r2__xer_ov_ok$next[0:0]$7805 $2\data_r2__xer_ov_ok$next[0:0]$7804 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8232 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8233 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7799 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7800 end - attribute \src "libresoc.v:159534.3-159552.6" - process $proc$libresoc.v:159534$8237 + attribute \src "libresoc.v:150719.3-150740.6" + process $proc$libresoc.v:150719$7806 + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$8238 $1\xer_ov$next[1:0]$8240 + assign $0\data_r3__xer_so$next[0:0]$7807 $2\data_r3__xer_so$next[0:0]$7811 assign { } { } - assign $0\xer_ov_ok$next[0:0]$8239 $2\xer_ov_ok$next[0:0]$8242 - attribute \src "libresoc.v:159535.5-159535.29" + assign $0\data_r3__xer_so_ok$next[0:0]$7808 $3\data_r3__xer_so_ok$next[0:0]$7813 + attribute \src "libresoc.v:150720.5-150720.29" switch \initial - attribute \src "libresoc.v:159535.9-159535.17" + attribute \src "libresoc.v:150720.9-150720.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8241 $1\xer_ov$next[1:0]$8240 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\data_r3__xer_so_ok$next[0:0]$7810 $1\data_r3__xer_so$next[0:0]$7809 } { \xer_so_ok \alu_mul0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$7809 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7810 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8241 $1\xer_ov$next[1:0]$8240 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $2\data_r3__xer_so_ok$next[0:0]$7812 $2\data_r3__xer_so$next[0:0]$7811 } 2'00 case - assign $1\xer_ov$next[1:0]$8240 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8241 \xer_ov_ok + assign $2\data_r3__xer_so$next[0:0]$7811 $1\data_r3__xer_so$next[0:0]$7809 + assign $2\data_r3__xer_so_ok$next[0:0]$7812 $1\data_r3__xer_so_ok$next[0:0]$7810 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8242 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$7813 1'0 case - assign $2\xer_ov_ok$next[0:0]$8242 $1\xer_ov_ok$next[0:0]$8241 + assign $3\data_r3__xer_so_ok$next[0:0]$7813 $2\data_r3__xer_so_ok$next[0:0]$7812 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8238 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8239 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7807 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7808 end - attribute \src "libresoc.v:159553.3-159571.6" - process $proc$libresoc.v:159553$8243 - assign { } { } + attribute \src "libresoc.v:150741.3-150750.6" + process $proc$libresoc.v:150741$7814 assign { } { } assign { } { } + assign $0\src_r0$next[63:0]$7815 $1\src_r0$next[63:0]$7816 + attribute \src "libresoc.v:150742.5-150742.29" + switch \initial + attribute \src "libresoc.v:150742.9-150742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$7816 \src1_i + case + assign $1\src_r0$next[63:0]$7816 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$7815 + end + attribute \src "libresoc.v:150751.3-150760.6" + process $proc$libresoc.v:150751$7817 assign { } { } assign { } { } - assign $0\xer_so$15$next[0:0]$8245 $1\xer_so$15$next[0:0]$8247 - assign $0\xer_so_ok$next[0:0]$8244 $2\xer_so_ok$next[0:0]$8248 - attribute \src "libresoc.v:159554.5-159554.29" + assign $0\src_r1$next[63:0]$7818 $1\src_r1$next[63:0]$7819 + attribute \src "libresoc.v:150752.5-150752.29" switch \initial - attribute \src "libresoc.v:159554.9-159554.17" + attribute \src "libresoc.v:150752.9-150752.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } + case 1'1 assign { } { } - assign { $1\xer_so_ok$next[0:0]$8246 $1\xer_so$15$next[0:0]$8247 } { \xer_so_ok$78 \xer_so$77 } + assign $1\src_r1$next[63:0]$7819 \src_or_imm + case + assign $1\src_r1$next[63:0]$7819 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$7818 + end + attribute \src "libresoc.v:150761.3-150770.6" + process $proc$libresoc.v:150761$7820 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$7821 $1\src_r2$next[0:0]$7822 + attribute \src "libresoc.v:150762.5-150762.29" + switch \initial + attribute \src "libresoc.v:150762.9-150762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } + assign $1\src_r2$next[0:0]$7822 \src3_i + case + assign $1\src_r2$next[0:0]$7822 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$7821 + end + attribute \src "libresoc.v:150771.3-150779.6" + process $proc$libresoc.v:150771$7823 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$7824 $1\alui_l_r_alui$next[0:0]$7825 + attribute \src "libresoc.v:150772.5-150772.29" + switch \initial + attribute \src "libresoc.v:150772.9-150772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { $1\xer_so_ok$next[0:0]$8246 $1\xer_so$15$next[0:0]$8247 } { \xer_so_ok$78 \xer_so$77 } + assign $1\alui_l_r_alui$next[0:0]$7825 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$7825 \$88 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7824 + end + attribute \src "libresoc.v:150780.3-150788.6" + process $proc$libresoc.v:150780$7826 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$7827 $1\alu_l_r_alu$next[0:0]$7828 + attribute \src "libresoc.v:150781.5-150781.29" + switch \initial + attribute \src "libresoc.v:150781.9-150781.17" + case 1'1 case - assign $1\xer_so_ok$next[0:0]$8246 \xer_so_ok - assign $1\xer_so$15$next[0:0]$8247 \xer_so$15 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8248 1'0 + assign $1\alu_l_r_alu$next[0:0]$7828 1'1 case - assign $2\xer_so_ok$next[0:0]$8248 $1\xer_so_ok$next[0:0]$8246 + assign $1\alu_l_r_alu$next[0:0]$7828 \$90 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8244 - update \xer_so$15$next $0\xer_so$15$next[0:0]$8245 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7827 end - connect \$56 $and$libresoc.v:159298$8149_Y - connect \cr_a$51 4'0000 - connect \cr_a_ok$52 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } - connect { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } - connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } - connect { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } - connect { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } - connect \muxid$58 \output_muxid$31 - connect \p_valid_i_p_ready_o \$56 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$55 \p_valid_i - connect { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } - connect { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } - connect { \cr_a_ok$50 \output_cr_a } 5'00000 - connect { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } - connect { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__oe__ok \output_mul_op__oe__oe \output_mul_op__rc__ok \output_mul_op__rc__rc \output_mul_op__imm_data__ok \output_mul_op__imm_data__data \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } - connect \output_muxid \mul3_muxid$16 - connect \neg_res32$49 \neg_res32 - connect \mul3_neg_res \neg_res - connect \mul3_xer_so \xer_so - connect \mul3_o \o - connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \mul3_muxid \muxid + attribute \src "libresoc.v:150789.3-150798.6" + process $proc$libresoc.v:150789$7829 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:150790.5-150790.29" + switch \initial + attribute \src "libresoc.v:150790.9-150790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$114 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:150799.3-150808.6" + process $proc$libresoc.v:150799$7830 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:150800.5-150800.29" + switch \initial + attribute \src "libresoc.v:150800.9-150800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$116 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:150809.3-150818.6" + process $proc$libresoc.v:150809$7831 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:150810.5-150810.29" + switch \initial + attribute \src "libresoc.v:150810.9-150810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$118 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ov + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:150819.3-150828.6" + process $proc$libresoc.v:150819$7832 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:150820.5-150820.29" + switch \initial + attribute \src "libresoc.v:150820.9-150820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$120 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "libresoc.v:150829.3-150837.6" + process $proc$libresoc.v:150829$7833 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[3:0]$7834 $1\prev_wr_go$next[3:0]$7835 + attribute \src "libresoc.v:150830.5-150830.29" + switch \initial + attribute \src "libresoc.v:150830.9-150830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[3:0]$7835 4'0000 + case + assign $1\prev_wr_go$next[3:0]$7835 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7834 + end + connect \$100 $and$libresoc.v:150305$7622_Y + connect \$102 $and$libresoc.v:150306$7623_Y + connect \$104 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\enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 34 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 32 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 33 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" + wire \sign32_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" + wire \sign32_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" + wire \sign_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" + wire \sign_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $and $and$libresoc.v:151168$7876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159610$8287_Y + connect \A \$17 + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:151168$7876_Y end - connect \$1 $and$libresoc.v:159610$8287_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159616.1-159627.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" -attribute \generator "nMigen" -module \n$109 - attribute \src "libresoc.v:159625.17-159625.111" - wire $and$libresoc.v:159625$8288_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159625$8288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $and $and$libresoc.v:151170$7878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159625$8288_Y + connect \A \$21 + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:151170$7878_Y end - connect \$1 $and$libresoc.v:159625$8288_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159631.1-159642.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" -attribute \generator "nMigen" -module \n$112 - attribute \src "libresoc.v:159640.17-159640.111" - wire $and$libresoc.v:159640$8289_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159640$8289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" + cell $and $and$libresoc.v:151171$7879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159640$8289_Y + connect \A \ra [31] + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:151171$7879_Y end - connect \$1 $and$libresoc.v:159640$8289_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159646.1-159657.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" -attribute \generator "nMigen" -module \n$117 - attribute \src "libresoc.v:159655.17-159655.111" - wire $and$libresoc.v:159655$8290_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159655$8290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" + cell $and $and$libresoc.v:151172$7880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159655$8290_Y + connect \A \rb [31] + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:151172$7880_Y end - connect \$1 $and$libresoc.v:159655$8290_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159661.1-159672.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" -attribute \generator "nMigen" -module \n$18 - attribute \src "libresoc.v:159670.17-159670.111" - wire $and$libresoc.v:159670$8291_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159670$8291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $pos $extend$libresoc.v:151175$7883 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159670$8291_Y + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:151175$7883_Y end - connect \$1 $and$libresoc.v:159670$8291_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159676.1-159687.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" -attribute \generator "nMigen" -module \n$2 - attribute \src "libresoc.v:159685.17-159685.111" - wire $and$libresoc.v:159685$8292_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159685$8292 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:151176$7885 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159685$8292_Y + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:151176$7885_Y end - connect \$1 $and$libresoc.v:159685$8292_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159691.1-159702.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" -attribute \generator "nMigen" -module \n$21 - attribute \src "libresoc.v:159700.17-159700.111" - wire $and$libresoc.v:159700$8293_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159700$8293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $pos $extend$libresoc.v:151178$7888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:151178$7888_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:151179$7890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:151179$7890_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $neg $neg$libresoc.v:151175$7884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:151175$7883_Y + connect \Y $neg$libresoc.v:151175$7884_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $neg $neg$libresoc.v:151178$7889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:151178$7888_Y + connect \Y $neg$libresoc.v:151178$7889_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:151176$7886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:151176$7885_Y + connect \Y $pos$libresoc.v:151176$7886_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:151179$7891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:151179$7890_Y + connect \Y $pos$libresoc.v:151179$7891_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $mux $ternary$libresoc.v:151167$7875 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$libresoc.v:151167$7875_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $mux $ternary$libresoc.v:151169$7877 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$libresoc.v:151169$7877_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $mux $ternary$libresoc.v:151177$7887 + parameter \WIDTH 65 + connect \A \$36 + connect \B \$34 + connect \S \sign_a + connect \Y $ternary$libresoc.v:151177$7887_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $mux $ternary$libresoc.v:151180$7892 + parameter \WIDTH 65 + connect \A \$43 + connect \B \$41 + connect \S \sign_b + connect \Y $ternary$libresoc.v:151180$7892_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:151181$7893 + parameter \WIDTH 32 + connect \A \abs_a [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:151181$7893_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:151182$7894 + parameter \WIDTH 32 + connect \A \abs_b [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:151182$7894_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" + cell $xor $xor$libresoc.v:151173$7881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159700$8293_Y + connect \A \sign_a + connect \B \sign_b + connect \Y $xor$libresoc.v:151173$7881_Y end - connect \$1 $and$libresoc.v:159700$8293_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159706.1-159717.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" -attribute \generator "nMigen" -module \n$31 - attribute \src "libresoc.v:159715.17-159715.111" - wire $and$libresoc.v:159715$8294_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159715$8294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" + cell $xor $xor$libresoc.v:151174$7882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159715$8294_Y - end - connect \$1 $and$libresoc.v:159715$8294_Y - connect \trigger \$1 + connect \A \sign32_a + connect \B \sign32_b + connect \Y $xor$libresoc.v:151174$7882_Y + end + connect \$17 $ternary$libresoc.v:151167$7875_Y + connect \$19 $and$libresoc.v:151168$7876_Y + connect \$21 $ternary$libresoc.v:151169$7877_Y + connect \$23 $and$libresoc.v:151170$7878_Y + connect \$25 $and$libresoc.v:151171$7879_Y + connect \$27 $and$libresoc.v:151172$7880_Y + connect \$29 $xor$libresoc.v:151173$7881_Y + connect \$31 $xor$libresoc.v:151174$7882_Y + connect \$34 $neg$libresoc.v:151175$7884_Y + connect \$36 $pos$libresoc.v:151176$7886_Y + connect \$38 $ternary$libresoc.v:151177$7887_Y + connect \$41 $neg$libresoc.v:151178$7889_Y + connect \$43 $pos$libresoc.v:151179$7891_Y + connect \$45 $ternary$libresoc.v:151180$7892_Y + connect \$47 $ternary$libresoc.v:151181$7893_Y + connect \$49 $ternary$libresoc.v:151182$7894_Y + connect \$33 \$38 + connect \$40 \$45 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 [63:32] \$49 + connect \rb$15 [31:0] \abs_b [31:0] + connect \ra$14 [63:32] \$47 + connect \ra$14 [31:0] \abs_a [31:0] + connect \abs_b \$45 [63:0] + connect \abs_a \$38 [63:0] + connect \neg_res32 \$31 + connect \neg_res \$29 + connect \sign32_b \$27 + connect \sign32_a \$25 + connect \sign_b \$23 + connect \sign_a \$19 + connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:159721.1-159732.10" +attribute \src "libresoc.v:151205.1-151464.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" -module \n$34 - attribute \src "libresoc.v:159730.17-159730.111" - wire $and$libresoc.v:159730$8295_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159730$8295 +module \mul2 + attribute \src "libresoc.v:151457.18-151457.98" + wire width 129 $extend$libresoc.v:151457$7896_Y + attribute \src "libresoc.v:151456.18-151456.99" + wire width 128 $mul$libresoc.v:151456$7895_Y + attribute \src "libresoc.v:151457.18-151457.98" + wire width 129 $pos$libresoc.v:151457$7897_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 129 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 128 \$18 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 16 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 33 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 17 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 34 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 31 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 32 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $extend$libresoc.v:151457$7896 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159730$8295_Y + parameter \A_WIDTH 128 + parameter \Y_WIDTH 129 + connect \A \$18 + connect \Y $extend$libresoc.v:151457$7896_Y end - connect \$1 $and$libresoc.v:159730$8295_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159736.1-159747.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" -attribute \generator "nMigen" -module \n$37 - attribute \src "libresoc.v:159745.17-159745.111" - wire $and$libresoc.v:159745$8296_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159745$8296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $mul $mul$libresoc.v:151456$7895 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159745$8296_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 128 + connect \A \ra + connect \B \rb + connect \Y $mul$libresoc.v:151456$7895_Y end - connect \$1 $and$libresoc.v:159745$8296_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159751.1-159762.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" -attribute \generator "nMigen" -module \n$4 - attribute \src "libresoc.v:159760.17-159760.111" - wire $and$libresoc.v:159760$8297_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159760$8297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $pos$libresoc.v:151457$7897 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159760$8297_Y + parameter \A_WIDTH 129 + parameter \Y_WIDTH 129 + connect \A $extend$libresoc.v:151457$7896_Y + connect \Y $pos$libresoc.v:151457$7897_Y end - connect \$1 $and$libresoc.v:159760$8297_Y - connect \trigger \$1 + connect \$18 $mul$libresoc.v:151456$7895_Y + connect \$17 $pos$libresoc.v:151457$7897_Y + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$14 \xer_so + connect \neg_res32$16 \neg_res32 + connect \neg_res$15 \neg_res + connect \o \$17 end -attribute \src "libresoc.v:159766.1-159777.10" +attribute \src "libresoc.v:151468.1-151849.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" -module \n$47 - attribute \src "libresoc.v:159775.17-159775.111" - wire $and$libresoc.v:159775$8298_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159775$8298 +module \mul3 + attribute \src "libresoc.v:151469.7-151469.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:151802.3-151820.6" + wire $0\mul_ov[0:0] + attribute \src "libresoc.v:151764.3-151782.6" + wire width 64 $0\o$14[63:0]$7914 + attribute \src "libresoc.v:151783.3-151801.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:151821.3-151831.6" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:151832.3-151842.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:151802.3-151820.6" + wire $1\mul_ov[0:0] + attribute \src "libresoc.v:151764.3-151782.6" + wire width 64 $1\o$14[63:0]$7915 + attribute \src "libresoc.v:151783.3-151801.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:151821.3-151831.6" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:151832.3-151842.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:151802.3-151820.6" + wire $2\mul_ov[0:0] + attribute \src "libresoc.v:151758.18-151758.104" + wire $and$libresoc.v:151758$7906_Y + attribute \src "libresoc.v:151762.18-151762.104" + wire $and$libresoc.v:151762$7910_Y + attribute \src "libresoc.v:151752.18-151752.95" + wire width 130 $extend$libresoc.v:151752$7898_Y + attribute \src "libresoc.v:151753.18-151753.90" + wire width 130 $extend$libresoc.v:151753$7900_Y + attribute \src "libresoc.v:151763.18-151763.95" + wire width 2 $extend$libresoc.v:151763$7911_Y + attribute \src "libresoc.v:151752.18-151752.95" + wire width 130 $neg$libresoc.v:151752$7899_Y + attribute \src "libresoc.v:151757.18-151757.98" + wire $not$libresoc.v:151757$7905_Y + attribute \src "libresoc.v:151761.18-151761.98" + wire $not$libresoc.v:151761$7909_Y + attribute \src "libresoc.v:151753.18-151753.90" + wire width 130 $pos$libresoc.v:151753$7901_Y + attribute \src "libresoc.v:151763.18-151763.95" + wire width 2 $pos$libresoc.v:151763$7912_Y + attribute \src "libresoc.v:151756.18-151756.106" + wire $reduce_and$libresoc.v:151756$7904_Y + attribute \src "libresoc.v:151760.18-151760.107" + wire $reduce_and$libresoc.v:151760$7908_Y + attribute \src "libresoc.v:151755.18-151755.106" + wire $reduce_or$libresoc.v:151755$7903_Y + attribute \src "libresoc.v:151759.18-151759.107" + wire $reduce_or$libresoc.v:151759$7907_Y + attribute \src "libresoc.v:151754.18-151754.114" + wire width 130 $ternary$libresoc.v:151754$7902_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 130 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \$39 + attribute \src "libresoc.v:151469.7-151469.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" + wire width 129 \mul_o + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" + wire \mul_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 15 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 29 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 31 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 14 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 34 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $and $and$libresoc.v:151758$7906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159775$8298_Y + connect \A \$23 + connect \B \$25 + connect \Y $and$libresoc.v:151758$7906_Y end - connect \$1 $and$libresoc.v:159775$8298_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159781.1-159792.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" -attribute \generator "nMigen" -module \n$49 - attribute \src "libresoc.v:159790.17-159790.111" - wire $and$libresoc.v:159790$8299_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159790$8299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $and $and$libresoc.v:151762$7910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159790$8299_Y + connect \A \$31 + connect \B \$33 + connect \Y $and$libresoc.v:151762$7910_Y end - connect \$1 $and$libresoc.v:159790$8299_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159796.1-159807.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" -attribute \generator "nMigen" -module \n$53 - attribute \src "libresoc.v:159805.17-159805.111" - wire $and$libresoc.v:159805$8300_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159805$8300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $pos $extend$libresoc.v:151752$7898 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159805$8300_Y + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$libresoc.v:151752$7898_Y end - connect \$1 $and$libresoc.v:159805$8300_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159811.1-159822.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" -attribute \generator "nMigen" -module \n$6 - attribute \src "libresoc.v:159820.17-159820.111" - wire $and$libresoc.v:159820$8301_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159820$8301 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:151753$7900 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159820$8301_Y + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$libresoc.v:151753$7900_Y end - connect \$1 $and$libresoc.v:159820$8301_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159826.1-159837.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" -attribute \generator "nMigen" -module \n$63 - attribute \src "libresoc.v:159835.17-159835.111" - wire $and$libresoc.v:159835$8302_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159835$8302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:151763$7911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159835$8302_Y + parameter \Y_WIDTH 2 + connect \A \xer_so + connect \Y $extend$libresoc.v:151763$7911_Y end - connect \$1 $and$libresoc.v:159835$8302_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159841.1-159852.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" -attribute \generator "nMigen" -module \n$66 - attribute \src "libresoc.v:159850.17-159850.111" - wire $and$libresoc.v:159850$8303_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159850$8303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $neg $neg$libresoc.v:151752$7899 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159850$8303_Y + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$libresoc.v:151752$7898_Y + connect \Y $neg$libresoc.v:151752$7899_Y end - connect \$1 $and$libresoc.v:159850$8303_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159856.1-159867.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" -attribute \generator "nMigen" -module \n$75 - attribute \src "libresoc.v:159865.17-159865.111" - wire $and$libresoc.v:159865$8304_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159865$8304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $not $not$libresoc.v:151757$7905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159865$8304_Y + connect \A \$26 + connect \Y $not$libresoc.v:151757$7905_Y end - connect \$1 $and$libresoc.v:159865$8304_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159871.1-159882.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" -attribute \generator "nMigen" -module \n$77 - attribute \src "libresoc.v:159880.17-159880.111" - wire $and$libresoc.v:159880$8305_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159880$8305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $not $not$libresoc.v:151761$7909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159880$8305_Y + connect \A \$34 + connect \Y $not$libresoc.v:151761$7909_Y end - connect \$1 $and$libresoc.v:159880$8305_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159886.1-159897.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" -attribute \generator "nMigen" -module \n$8 - attribute \src "libresoc.v:159895.17-159895.111" - wire $and$libresoc.v:159895$8306_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159895$8306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:151753$7901 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159895$8306_Y + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$libresoc.v:151753$7900_Y + connect \Y $pos$libresoc.v:151753$7901_Y end - connect \$1 $and$libresoc.v:159895$8306_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159901.1-159912.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" -attribute \generator "nMigen" -module \n$80 - attribute \src "libresoc.v:159910.17-159910.111" - wire $and$libresoc.v:159910$8307_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159910$8307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:151763$7912 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159910$8307_Y + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $extend$libresoc.v:151763$7911_Y + connect \Y $pos$libresoc.v:151763$7912_Y end - connect \$1 $and$libresoc.v:159910$8307_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159916.1-159927.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" -attribute \generator "nMigen" -module \n$82 - attribute \src "libresoc.v:159925.17-159925.111" - wire $and$libresoc.v:159925$8308_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159925$8308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_and $reduce_and$libresoc.v:151756$7904 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 33 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159925$8308_Y + connect \A \mul_o [63:31] + connect \Y $reduce_and$libresoc.v:151756$7904_Y end - connect \$1 $and$libresoc.v:159925$8308_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159931.1-159942.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" -attribute \generator "nMigen" -module \n$92 - attribute \src "libresoc.v:159940.17-159940.111" - wire $and$libresoc.v:159940$8309_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159940$8309 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_and $reduce_and$libresoc.v:151760$7908 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 65 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159940$8309_Y + connect \A \mul_o [127:63] + connect \Y $reduce_and$libresoc.v:151760$7908_Y end - connect \$1 $and$libresoc.v:159940$8309_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159946.1-159957.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" -attribute \generator "nMigen" -module \n$94 - attribute \src "libresoc.v:159955.17-159955.111" - wire $and$libresoc.v:159955$8310_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159955$8310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_or $reduce_or$libresoc.v:151755$7903 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 33 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159955$8310_Y + connect \A \mul_o [63:31] + connect \Y $reduce_or$libresoc.v:151755$7903_Y end - connect \$1 $and$libresoc.v:159955$8310_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159961.1-159972.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" -attribute \generator "nMigen" -module \n$97 - attribute \src "libresoc.v:159970.17-159970.111" - wire $and$libresoc.v:159970$8311_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159970$8311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_or $reduce_or$libresoc.v:151759$7907 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \A_WIDTH 65 parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159970$8311_Y + connect \A \mul_o [127:63] + connect \Y $reduce_or$libresoc.v:151759$7907_Y end - connect \$1 $and$libresoc.v:159970$8311_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159976.1-159987.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" -attribute \generator "nMigen" -module \n$99 - attribute \src "libresoc.v:159985.17-159985.111" - wire $and$libresoc.v:159985$8312_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:159985$8312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:159985$8312_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $mux $ternary$libresoc.v:151754$7902 + parameter \WIDTH 130 + connect \A \$19 + connect \B \$17 + connect \S \neg_res + connect \Y $ternary$libresoc.v:151754$7902_Y end - connect \$1 $and$libresoc.v:159985$8312_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:159991.1-160092.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.o2_svdec" -attribute \generator "nMigen" -module \o2_svdec - attribute \src "libresoc.v:159992.7-159992.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160078.3-160089.6" - wire width 7 $0\reg_out[6:0] - attribute \src "libresoc.v:160019.3-160077.6" - wire width 3 $0\spec[2:0] - attribute \src "libresoc.v:160078.3-160089.6" - wire width 7 $1\reg_out[6:0] - attribute \src "libresoc.v:160019.3-160077.6" - wire width 3 $1\spec[2:0] - attribute \src "libresoc.v:160019.3-160077.6" - wire width 2 $2\spec[2:1] - attribute \src "libresoc.v:160019.3-160077.6" - wire width 3 $3\spec[2:0] - attribute \enum_base_type "SVEtype" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "EXTRA2" - attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" - wire width 2 input 1 \etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" - wire width 9 input 5 \extra - attribute \enum_base_type "SVEXTRA" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "Idx0" - attribute \enum_value_010 "Idx1" - attribute \enum_value_011 "Idx2" - attribute \enum_value_100 "Idx3" - attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" - wire width 3 \idx - attribute \src "libresoc.v:159992.7-159992.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire output 3 \isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - wire width 5 input 2 \reg_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 7 output 4 \reg_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" - wire width 3 \spec - attribute \src "libresoc.v:159992.7-159992.20" - process $proc$libresoc.v:159992$8315 + attribute \src "libresoc.v:151469.7-151469.20" + process $proc$libresoc.v:151469$7920 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160019.3-160077.6" - process $proc$libresoc.v:160019$8313 + attribute \src "libresoc.v:151764.3-151782.6" + process $proc$libresoc.v:151764$7913 assign { } { } assign { } { } - assign $0\spec[2:0] $1\spec[2:0] - attribute \src "libresoc.v:160020.5-160020.29" + assign $0\o$14[63:0]$7914 $1\o$14[63:0]$7915 + attribute \src "libresoc.v:151765.5-151765.29" switch \initial - attribute \src "libresoc.v:160020.9-160020.17" + attribute \src "libresoc.v:151765.9-151765.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign $1\spec[2:0] [0] 1'0 - assign $1\spec[2:0] [2:1] $2\spec[2:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" - switch \idx - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $2\spec[2:1] [1] \extra [8] - assign $2\spec[2:1] [0] \extra [7] - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $2\spec[2:1] [1] \extra [6] - assign $2\spec[2:1] [0] \extra [5] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $2\spec[2:1] [1] \extra [4] - assign $2\spec[2:1] [0] \extra [3] - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $2\spec[2:1] [1] \extra [2] - assign $2\spec[2:1] [0] \extra [1] - case - assign $2\spec[2:1] 2'00 - end + case 7'0110100 + assign { } { } + assign $1\o$14[63:0]$7915 { \mul_o [63:32] \mul_o [63:32] } attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 7'0110011 assign { } { } - assign $1\spec[2:0] $3\spec[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" - switch \idx - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $3\spec[2:0] \extra [8:6] - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $3\spec[2:0] \extra [5:3] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $3\spec[2:0] \extra [2:0] - case - assign $3\spec[2:0] 3'000 - end + assign $1\o$14[63:0]$7915 \mul_o [127:64] + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o$14[63:0]$7915 \mul_o [63:0] case - assign $1\spec[2:0] 3'000 + assign $1\o$14[63:0]$7915 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spec $0\spec[2:0] + update \o$14 $0\o$14[63:0]$7914 end - attribute \src "libresoc.v:160078.3-160089.6" - process $proc$libresoc.v:160078$8314 + attribute \src "libresoc.v:151783.3-151801.6" + process $proc$libresoc.v:151783$7916 assign { } { } - assign $0\reg_out[6:0] $1\reg_out[6:0] - attribute \src "libresoc.v:160079.5-160079.29" + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:151784.5-151784.29" switch \initial - attribute \src "libresoc.v:160079.9-160079.17" + attribute \src "libresoc.v:151784.9-151784.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" - switch \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 7'0110100 assign { } { } - assign $1\reg_out[6:0] { \reg_in \spec [1:0] } + assign $1\o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case + case 7'0110011 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 assign { } { } - assign $1\reg_out[6:0] { \spec [1:0] \reg_in } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 end sync always - update \reg_out $0\reg_out[6:0] - end - connect \idx 3'000 - connect \isvec \spec [2] -end -attribute \src "libresoc.v:160096.1-160196.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.o_svdec" -attribute \generator "nMigen" -module \o_svdec - attribute \src "libresoc.v:160097.7-160097.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160183.3-160194.6" - wire width 7 $0\reg_out[6:0] - attribute \src "libresoc.v:160124.3-160182.6" - wire width 3 $0\spec[2:0] - attribute \src "libresoc.v:160183.3-160194.6" - wire width 7 $1\reg_out[6:0] - attribute \src "libresoc.v:160124.3-160182.6" - wire width 3 $1\spec[2:0] - attribute \src "libresoc.v:160124.3-160182.6" - wire width 2 $2\spec[2:1] - attribute \src "libresoc.v:160124.3-160182.6" - wire width 3 $3\spec[2:0] - attribute \enum_base_type "SVEtype" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "EXTRA2" - attribute \enum_value_10 "EXTRA3" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" - wire width 2 input 1 \etype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" - wire width 9 input 6 \extra - attribute \enum_base_type "SVEXTRA" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "Idx0" - attribute \enum_value_010 "Idx1" - attribute \enum_value_011 "Idx2" - attribute \enum_value_100 "Idx3" - attribute \enum_value_101 "Idx_1_2" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" - wire width 3 input 5 \idx - attribute \src "libresoc.v:160097.7-160097.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire output 3 \isvec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - wire width 5 input 2 \reg_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 7 output 4 \reg_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" - wire width 3 \spec - attribute \src "libresoc.v:160097.7-160097.20" - process $proc$libresoc.v:160097$8318 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:160124.3-160182.6" - process $proc$libresoc.v:160124$8316 - assign { } { } + attribute \src "libresoc.v:151802.3-151820.6" + process $proc$libresoc.v:151802$7917 assign { } { } - assign $0\spec[2:0] $1\spec[2:0] - attribute \src "libresoc.v:160125.5-160125.29" - switch \initial - attribute \src "libresoc.v:160125.9-160125.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch \etype - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign $1\spec[2:0] [0] 1'0 - assign $1\spec[2:0] [2:1] $2\spec[2:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" - switch \idx - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $2\spec[2:1] [1] \extra [8] - assign $2\spec[2:1] [0] \extra [7] - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $2\spec[2:1] [1] \extra [6] - assign $2\spec[2:1] [0] \extra [5] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $2\spec[2:1] [1] \extra [4] - assign $2\spec[2:1] [0] \extra [3] - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $2\spec[2:1] [1] \extra [2] - assign $2\spec[2:1] [0] \extra [1] - case - assign $2\spec[2:1] 2'00 - end + assign { } { } + assign $0\mul_ov[0:0] $1\mul_ov[0:0] + attribute \src "libresoc.v:151803.5-151803.29" + switch \initial + attribute \src "libresoc.v:151803.9-151803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 7'0110010 assign { } { } - assign $1\spec[2:0] $3\spec[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" - switch \idx - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $3\spec[2:0] \extra [8:6] + assign $1\mul_ov[0:0] $2\mul_ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" + switch \is_32bit attribute \src "libresoc.v:0.0-0.0" - case 3'010 + case 1'1 assign { } { } - assign $3\spec[2:0] \extra [5:3] + assign $2\mul_ov[0:0] \$29 attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $3\spec[2:0] \extra [2:0] case - assign $3\spec[2:0] 3'000 + assign { } { } + assign $2\mul_ov[0:0] \$37 end case - assign $1\spec[2:0] 3'000 + assign $1\mul_ov[0:0] 1'0 end sync always - update \spec $0\spec[2:0] + update \mul_ov $0\mul_ov[0:0] end - attribute \src "libresoc.v:160183.3-160194.6" - process $proc$libresoc.v:160183$8317 + attribute \src "libresoc.v:151821.3-151831.6" + process $proc$libresoc.v:151821$7918 assign { } { } - assign $0\reg_out[6:0] $1\reg_out[6:0] - attribute \src "libresoc.v:160184.5-160184.29" + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "libresoc.v:151822.5-151822.29" switch \initial - attribute \src "libresoc.v:160184.9-160184.17" + attribute \src "libresoc.v:151822.9-151822.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" - switch \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 7'0110010 assign { } { } - assign $1\reg_out[6:0] { \reg_in \spec [1:0] } - attribute \src "libresoc.v:0.0-0.0" + assign $1\xer_ov[1:0] { \mul_ov \mul_ov } + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:151832.3-151842.6" + process $proc$libresoc.v:151832$7919 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:151833.5-151833.29" + switch \initial + attribute \src "libresoc.v:151833.9-151833.17" + case 1'1 case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 assign { } { } - assign $1\reg_out[6:0] { \spec [1:0] \reg_in } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 end sync always - update \reg_out $0\reg_out[6:0] + update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \isvec \spec [2] + connect \$17 $neg$libresoc.v:151752$7899_Y + connect \$19 $pos$libresoc.v:151753$7901_Y + connect \$21 $ternary$libresoc.v:151754$7902_Y + connect \$23 $reduce_or$libresoc.v:151755$7903_Y + connect \$26 $reduce_and$libresoc.v:151756$7904_Y + connect \$25 $not$libresoc.v:151757$7905_Y + connect \$29 $and$libresoc.v:151758$7906_Y + connect \$31 $reduce_or$libresoc.v:151759$7907_Y + connect \$34 $reduce_and$libresoc.v:151760$7908_Y + connect \$33 $not$libresoc.v:151761$7909_Y + connect \$37 $and$libresoc.v:151762$7910_Y + connect \$39 $pos$libresoc.v:151763$7912_Y + connect \$16 \$21 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect { \xer_so_ok \xer_so$15 } \$39 + connect \mul_o \$21 [128:0] + connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:160200.1-160258.10" +attribute \src "libresoc.v:151853.1-153056.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" -module \opc_l - attribute \src "libresoc.v:160201.7-160201.20" +module \mul_pipe1 + attribute \src "libresoc.v:151854.7-151854.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160246.3-160254.6" - wire $0\q_int$next[0:0]$8329 - attribute \src "libresoc.v:160244.3-160245.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:160246.3-160254.6" - wire $1\q_int$next[0:0]$8330 - attribute \src "libresoc.v:160223.7-160223.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:160236.17-160236.96" - wire $and$libresoc.v:160236$8319_Y - attribute \src "libresoc.v:160241.17-160241.96" - wire $and$libresoc.v:160241$8324_Y - attribute \src "libresoc.v:160238.18-160238.93" - wire $not$libresoc.v:160238$8321_Y - attribute \src "libresoc.v:160240.17-160240.92" - wire $not$libresoc.v:160240$8323_Y - attribute \src "libresoc.v:160243.17-160243.92" - wire $not$libresoc.v:160243$8326_Y - attribute \src "libresoc.v:160237.18-160237.98" - wire $or$libresoc.v:160237$8320_Y - attribute \src "libresoc.v:160239.18-160239.99" - wire $or$libresoc.v:160239$8322_Y - attribute \src "libresoc.v:160242.17-160242.97" - wire $or$libresoc.v:160242$8325_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "libresoc.v:152933.3-152968.6" + wire width 13 $0\mul_op__fn_unit$next[12:0]$7949 + attribute \src "libresoc.v:152798.3-152799.47" + wire width 13 $0\mul_op__fn_unit[12:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7950 + attribute \src "libresoc.v:152800.3-152801.61" + wire width 64 $0\mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7951 + attribute \src "libresoc.v:152802.3-152803.57" + wire $0\mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire width 32 $0\mul_op__insn$next[31:0]$7952 + attribute \src "libresoc.v:152818.3-152819.41" + wire width 32 $0\mul_op__insn[31:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7953 + attribute \src "libresoc.v:152796.3-152797.51" + wire width 7 $0\mul_op__insn_type[6:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $0\mul_op__is_32bit$next[0:0]$7954 + attribute \src "libresoc.v:152814.3-152815.49" + wire $0\mul_op__is_32bit[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $0\mul_op__is_signed$next[0:0]$7955 + attribute \src "libresoc.v:152816.3-152817.51" + wire $0\mul_op__is_signed[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $0\mul_op__oe__oe$next[0:0]$7956 + attribute \src "libresoc.v:152808.3-152809.45" + wire $0\mul_op__oe__oe[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $0\mul_op__oe__ok$next[0:0]$7957 + attribute \src "libresoc.v:152810.3-152811.45" + wire $0\mul_op__oe__ok[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $0\mul_op__rc__ok$next[0:0]$7958 + attribute \src "libresoc.v:152806.3-152807.45" + wire $0\mul_op__rc__ok[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $0\mul_op__rc__rc$next[0:0]$7959 + attribute \src "libresoc.v:152804.3-152805.45" + wire $0\mul_op__rc__rc[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $0\mul_op__write_cr0$next[0:0]$7960 + attribute \src "libresoc.v:152812.3-152813.51" + wire $0\mul_op__write_cr0[0:0] + attribute \src "libresoc.v:152920.3-152932.6" + wire width 2 $0\muxid$next[1:0]$7946 + attribute \src "libresoc.v:152820.3-152821.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:153008.3-153020.6" + wire $0\neg_res$next[0:0]$7989 + attribute \src "libresoc.v:153021.3-153033.6" + wire $0\neg_res32$next[0:0]$7992 + attribute \src "libresoc.v:152786.3-152787.35" + wire $0\neg_res32[0:0] + attribute \src "libresoc.v:152788.3-152789.31" + wire $0\neg_res[0:0] + attribute \src "libresoc.v:152902.3-152919.6" + wire $0\r_busy$next[0:0]$7942 + attribute \src "libresoc.v:152822.3-152823.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:152969.3-152981.6" + wire width 64 $0\ra$next[63:0]$7980 + attribute \src "libresoc.v:152794.3-152795.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:152982.3-152994.6" + wire width 64 $0\rb$next[63:0]$7983 + attribute \src "libresoc.v:152792.3-152793.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:152995.3-153007.6" + wire $0\xer_so$next[0:0]$7986 + attribute \src "libresoc.v:152790.3-152791.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire width 13 $1\mul_op__fn_unit$next[12:0]$7961 + attribute \src "libresoc.v:152361.14-152361.40" + wire width 13 $1\mul_op__fn_unit[12:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7962 + attribute \src "libresoc.v:152398.14-152398.59" + wire width 64 $1\mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7963 + attribute \src "libresoc.v:152407.7-152407.34" + wire $1\mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire width 32 $1\mul_op__insn$next[31:0]$7964 + attribute \src "libresoc.v:152416.14-152416.34" + wire width 32 $1\mul_op__insn[31:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7965 + attribute \src "libresoc.v:152499.13-152499.38" + wire width 7 $1\mul_op__insn_type[6:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $1\mul_op__is_32bit$next[0:0]$7966 + attribute \src "libresoc.v:152656.7-152656.30" + wire $1\mul_op__is_32bit[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $1\mul_op__is_signed$next[0:0]$7967 + attribute \src "libresoc.v:152665.7-152665.31" + wire $1\mul_op__is_signed[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $1\mul_op__oe__oe$next[0:0]$7968 + attribute \src "libresoc.v:152674.7-152674.28" + wire $1\mul_op__oe__oe[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $1\mul_op__oe__ok$next[0:0]$7969 + attribute \src "libresoc.v:152683.7-152683.28" + wire $1\mul_op__oe__ok[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $1\mul_op__rc__ok$next[0:0]$7970 + attribute \src "libresoc.v:152692.7-152692.28" + wire $1\mul_op__rc__ok[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $1\mul_op__rc__rc$next[0:0]$7971 + attribute \src "libresoc.v:152701.7-152701.28" + wire $1\mul_op__rc__rc[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire $1\mul_op__write_cr0$next[0:0]$7972 + attribute \src "libresoc.v:152710.7-152710.31" + wire $1\mul_op__write_cr0[0:0] + attribute \src "libresoc.v:152920.3-152932.6" + wire width 2 $1\muxid$next[1:0]$7947 + attribute \src "libresoc.v:152719.13-152719.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:153008.3-153020.6" + wire $1\neg_res$next[0:0]$7990 + attribute \src "libresoc.v:153021.3-153033.6" + wire $1\neg_res32$next[0:0]$7993 + attribute \src "libresoc.v:152741.7-152741.23" + wire $1\neg_res32[0:0] + attribute \src "libresoc.v:152734.7-152734.21" + wire $1\neg_res[0:0] + attribute \src "libresoc.v:152902.3-152919.6" + wire $1\r_busy$next[0:0]$7943 + attribute \src "libresoc.v:152755.7-152755.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:152969.3-152981.6" + wire width 64 $1\ra$next[63:0]$7981 + attribute \src "libresoc.v:152760.14-152760.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:152982.3-152994.6" + wire width 64 $1\rb$next[63:0]$7984 + attribute \src "libresoc.v:152769.14-152769.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:152995.3-153007.6" + wire $1\xer_so$next[0:0]$7987 + attribute \src "libresoc.v:152778.7-152778.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:152933.3-152968.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7973 + attribute \src "libresoc.v:152933.3-152968.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7974 + attribute \src "libresoc.v:152933.3-152968.6" + wire $2\mul_op__oe__oe$next[0:0]$7975 + attribute \src "libresoc.v:152933.3-152968.6" + wire $2\mul_op__oe__ok$next[0:0]$7976 + attribute \src "libresoc.v:152933.3-152968.6" + wire $2\mul_op__rc__ok$next[0:0]$7977 + attribute \src "libresoc.v:152933.3-152968.6" + wire $2\mul_op__rc__rc$next[0:0]$7978 + attribute \src "libresoc.v:152902.3-152919.6" + wire $2\r_busy$next[0:0]$7944 + attribute \src "libresoc.v:152785.18-152785.118" + wire $and$libresoc.v:152785$7921_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 40 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:160201.7-160201.15" + attribute \src "libresoc.v:151854.7-151854.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:160236$8319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:160236$8319_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:160241$8324 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$32 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul1_mul_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn$45 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul1_muxid$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so$48 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 26 \mul_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_op__fn_unit$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 25 \mul_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 23 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 22 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 37 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 38 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 39 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:152785$7921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:160241$8324_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:160238$8321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:160238$8321_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:160240$8323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160240$8323_Y + connect \A \p_valid_i$49 + connect \B \p_ready_o + connect \Y $and$libresoc.v:152785$7921_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:160243$8326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160243$8326_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:152824.14-152857.4" + cell \input$95 \input + connect \mul_op__fn_unit \input_mul_op__fn_unit + connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \input_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 + connect \mul_op__insn \input_mul_op__insn + connect \mul_op__insn$13 \input_mul_op__insn$29 + connect \mul_op__insn_type \input_mul_op__insn_type + connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 + connect \mul_op__is_32bit \input_mul_op__is_32bit + connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 + connect \mul_op__is_signed \input_mul_op__is_signed + connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 + connect \mul_op__oe__oe \input_mul_op__oe__oe + connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 + connect \mul_op__oe__ok \input_mul_op__oe__ok + connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 + connect \mul_op__rc__ok \input_mul_op__rc__ok + connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 + connect \mul_op__rc__rc \input_mul_op__rc__rc + connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \input_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$17 + connect \ra \input_ra + connect \ra$14 \input_ra$30 + connect \rb \input_rb + connect \rb$15 \input_rb$31 + connect \xer_so \input_xer_so + connect \xer_so$16 \input_xer_so$32 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:160237$8320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:160237$8320_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:152858.8-152893.4" + cell \mul1 \mul1 + connect \mul_op__fn_unit \mul1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 + connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 + connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 + connect \mul_op__insn \mul1_mul_op__insn + connect \mul_op__insn$13 \mul1_mul_op__insn$45 + connect \mul_op__insn_type \mul1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 + connect \mul_op__is_32bit \mul1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 + connect \mul_op__is_signed \mul1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 + connect \mul_op__oe__oe \mul1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 + connect \mul_op__oe__ok \mul1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 + connect \mul_op__rc__ok \mul1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 + connect \mul_op__rc__rc \mul1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 + connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 + connect \muxid \mul1_muxid + connect \muxid$1 \mul1_muxid$33 + connect \neg_res \mul1_neg_res + connect \neg_res32 \mul1_neg_res32 + connect \ra \mul1_ra + connect \ra$14 \mul1_ra$46 + connect \rb \mul1_rb + connect \rb$15 \mul1_rb$47 + connect \xer_so \mul1_xer_so + connect \xer_so$16 \mul1_xer_so$48 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:160239$8322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:160239$8322_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:152894.10-152897.4" + cell \n$94 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:160242$8325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:160242$8325_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:152898.10-152901.4" + cell \p$93 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:160201.7-160201.20" - process $proc$libresoc.v:160201$8331 + attribute \src "libresoc.v:151854.7-151854.20" + process $proc$libresoc.v:151854$7994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160223.7-160223.19" - process $proc$libresoc.v:160223$8332 + attribute \src "libresoc.v:152361.14-152361.40" + process $proc$libresoc.v:152361$7995 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $1\mul_op__fn_unit[12:0] 13'0000000000000 sync always sync init - update \q_int $1\q_int[0:0] + update \mul_op__fn_unit $1\mul_op__fn_unit[12:0] end - attribute \src "libresoc.v:160244.3-160245.27" - process $proc$libresoc.v:160244$8327 + attribute \src "libresoc.v:152398.14-152398.59" + process $proc$libresoc.v:152398$7996 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:160246.3-160254.6" - process $proc$libresoc.v:160246$8328 - assign { } { } + attribute \src "libresoc.v:152407.7-152407.34" + process $proc$libresoc.v:152407$7997 assign { } { } - assign $0\q_int$next[0:0]$8329 $1\q_int$next[0:0]$8330 - attribute \src "libresoc.v:160247.5-160247.29" - switch \initial - attribute \src "libresoc.v:160247.9-160247.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8330 1'0 - case - assign $1\q_int$next[0:0]$8330 \$5 - end + assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always - update \q_int$next $0\q_int$next[0:0]$8329 - end - connect \$9 $and$libresoc.v:160236$8319_Y - connect \$11 $or$libresoc.v:160237$8320_Y - connect \$13 $not$libresoc.v:160238$8321_Y - connect \$15 $or$libresoc.v:160239$8322_Y - connect \$1 $not$libresoc.v:160240$8323_Y - connect \$3 $and$libresoc.v:160241$8324_Y - connect \$5 $or$libresoc.v:160242$8325_Y - connect \$7 $not$libresoc.v:160243$8326_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:160262.1-160320.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" -attribute \generator "nMigen" -module \opc_l$102 - attribute \src "libresoc.v:160263.7-160263.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160308.3-160316.6" - wire $0\q_int$next[0:0]$8343 - attribute \src "libresoc.v:160306.3-160307.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:160308.3-160316.6" - wire $1\q_int$next[0:0]$8344 - attribute \src "libresoc.v:160285.7-160285.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:160298.17-160298.96" - wire $and$libresoc.v:160298$8333_Y - attribute \src "libresoc.v:160303.17-160303.96" - wire $and$libresoc.v:160303$8338_Y - attribute \src "libresoc.v:160300.18-160300.93" - wire $not$libresoc.v:160300$8335_Y - attribute \src "libresoc.v:160302.17-160302.92" - wire $not$libresoc.v:160302$8337_Y - attribute \src "libresoc.v:160305.17-160305.92" - wire $not$libresoc.v:160305$8340_Y - attribute \src "libresoc.v:160299.18-160299.98" - wire $or$libresoc.v:160299$8334_Y - attribute \src "libresoc.v:160301.18-160301.99" - wire $or$libresoc.v:160301$8336_Y - attribute \src "libresoc.v:160304.17-160304.97" - wire $or$libresoc.v:160304$8339_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:160263.7-160263.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:160298$8333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:160298$8333_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:160303$8338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:160303$8338_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:160300$8335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:160300$8335_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:160302$8337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160302$8337_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:160305$8340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160305$8340_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:160299$8334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:160299$8334_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:160301$8336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:160301$8336_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:160304$8339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:160304$8339_Y + sync init + update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:160263.7-160263.20" - process $proc$libresoc.v:160263$8345 + attribute \src "libresoc.v:152416.14-152416.34" + process $proc$libresoc.v:152416$7998 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\mul_op__insn[31:0] 0 sync always - update \initial $0\initial[0:0] sync init + update \mul_op__insn $1\mul_op__insn[31:0] end - attribute \src "libresoc.v:160285.7-160285.19" - process $proc$libresoc.v:160285$8346 + attribute \src "libresoc.v:152499.13-152499.38" + process $proc$libresoc.v:152499$7999 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init - update \q_int $1\q_int[0:0] + update \mul_op__insn_type $1\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:160306.3-160307.27" - process $proc$libresoc.v:160306$8341 + attribute \src "libresoc.v:152656.7-152656.30" + process $proc$libresoc.v:152656$8000 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + assign $1\mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:160308.3-160316.6" - process $proc$libresoc.v:160308$8342 + attribute \src "libresoc.v:152665.7-152665.31" + process $proc$libresoc.v:152665$8001 assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$8343 $1\q_int$next[0:0]$8344 - attribute \src "libresoc.v:160309.5-160309.29" - switch \initial - attribute \src "libresoc.v:160309.9-160309.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8344 1'0 - case - assign $1\q_int$next[0:0]$8344 \$5 - end + assign $1\mul_op__is_signed[0:0] 1'0 sync always - update \q_int$next $0\q_int$next[0:0]$8343 - end - connect \$9 $and$libresoc.v:160298$8333_Y - connect \$11 $or$libresoc.v:160299$8334_Y - connect \$13 $not$libresoc.v:160300$8335_Y - connect \$15 $or$libresoc.v:160301$8336_Y - connect \$1 $not$libresoc.v:160302$8337_Y - connect \$3 $and$libresoc.v:160303$8338_Y - connect \$5 $or$libresoc.v:160304$8339_Y - connect \$7 $not$libresoc.v:160305$8340_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:160324.1-160382.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" -attribute \generator "nMigen" -module \opc_l$11 - attribute \src "libresoc.v:160325.7-160325.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160370.3-160378.6" - wire $0\q_int$next[0:0]$8357 - attribute \src "libresoc.v:160368.3-160369.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:160370.3-160378.6" - wire $1\q_int$next[0:0]$8358 - attribute \src "libresoc.v:160347.7-160347.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:160360.17-160360.96" - wire $and$libresoc.v:160360$8347_Y - attribute \src "libresoc.v:160365.17-160365.96" - wire $and$libresoc.v:160365$8352_Y - attribute \src "libresoc.v:160362.18-160362.93" - wire $not$libresoc.v:160362$8349_Y - attribute \src "libresoc.v:160364.17-160364.92" - wire $not$libresoc.v:160364$8351_Y - attribute \src "libresoc.v:160367.17-160367.92" - wire $not$libresoc.v:160367$8354_Y - attribute \src "libresoc.v:160361.18-160361.98" - wire $or$libresoc.v:160361$8348_Y - attribute \src "libresoc.v:160363.18-160363.99" - wire $or$libresoc.v:160363$8350_Y - attribute \src "libresoc.v:160366.17-160366.97" - wire $or$libresoc.v:160366$8353_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:160325.7-160325.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:160360$8347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:160360$8347_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:160365$8352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:160365$8352_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:160362$8349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:160362$8349_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:160364$8351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160364$8351_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:160367$8354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160367$8354_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:160361$8348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:160361$8348_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:160363$8350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:160363$8350_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:160366$8353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:160366$8353_Y + sync init + update \mul_op__is_signed $1\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:160325.7-160325.20" - process $proc$libresoc.v:160325$8359 + attribute \src "libresoc.v:152674.7-152674.28" + process $proc$libresoc.v:152674$8002 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\mul_op__oe__oe[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:160347.7-160347.19" - process $proc$libresoc.v:160347$8360 + attribute \src "libresoc.v:152683.7-152683.28" + process $proc$libresoc.v:152683$8003 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init - update \q_int $1\q_int[0:0] + update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:160368.3-160369.27" - process $proc$libresoc.v:160368$8355 + attribute \src "libresoc.v:152692.7-152692.28" + process $proc$libresoc.v:152692$8004 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + assign $1\mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:160370.3-160378.6" - process $proc$libresoc.v:160370$8356 - assign { } { } + attribute \src "libresoc.v:152701.7-152701.28" + process $proc$libresoc.v:152701$8005 assign { } { } - assign $0\q_int$next[0:0]$8357 $1\q_int$next[0:0]$8358 - attribute \src "libresoc.v:160371.5-160371.29" - switch \initial - attribute \src "libresoc.v:160371.9-160371.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8358 1'0 - case - assign $1\q_int$next[0:0]$8358 \$5 - end + assign $1\mul_op__rc__rc[0:0] 1'0 sync always - update \q_int$next $0\q_int$next[0:0]$8357 - end - connect \$9 $and$libresoc.v:160360$8347_Y - connect \$11 $or$libresoc.v:160361$8348_Y - connect \$13 $not$libresoc.v:160362$8349_Y - connect \$15 $or$libresoc.v:160363$8350_Y - connect \$1 $not$libresoc.v:160364$8351_Y - connect \$3 $and$libresoc.v:160365$8352_Y - connect \$5 $or$libresoc.v:160366$8353_Y - connect \$7 $not$libresoc.v:160367$8354_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:160386.1-160444.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" -attribute \generator "nMigen" -module \opc_l$120 - attribute \src "libresoc.v:160387.7-160387.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160432.3-160440.6" - wire $0\q_int$next[0:0]$8371 - attribute \src "libresoc.v:160430.3-160431.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:160432.3-160440.6" - wire $1\q_int$next[0:0]$8372 - attribute \src "libresoc.v:160409.7-160409.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:160422.17-160422.96" - wire $and$libresoc.v:160422$8361_Y - attribute \src "libresoc.v:160427.17-160427.96" - wire $and$libresoc.v:160427$8366_Y - attribute \src "libresoc.v:160424.18-160424.93" - wire $not$libresoc.v:160424$8363_Y - attribute \src "libresoc.v:160426.17-160426.92" - wire $not$libresoc.v:160426$8365_Y - attribute \src "libresoc.v:160429.17-160429.92" - wire $not$libresoc.v:160429$8368_Y - attribute \src "libresoc.v:160423.18-160423.98" - wire $or$libresoc.v:160423$8362_Y - attribute \src "libresoc.v:160425.18-160425.99" - wire $or$libresoc.v:160425$8364_Y - attribute \src "libresoc.v:160428.17-160428.97" - wire $or$libresoc.v:160428$8367_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:160387.7-160387.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:160422$8361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:160422$8361_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:160427$8366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:160427$8366_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:160424$8363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:160424$8363_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:160426$8365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160426$8365_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:160429$8368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160429$8368_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:160423$8362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:160423$8362_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:160425$8364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:160425$8364_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:160428$8367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:160428$8367_Y + sync init + update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:160387.7-160387.20" - process $proc$libresoc.v:160387$8373 + attribute \src "libresoc.v:152710.7-152710.31" + process $proc$libresoc.v:152710$8006 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\mul_op__write_cr0[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:160409.7-160409.19" - process $proc$libresoc.v:160409$8374 + attribute \src "libresoc.v:152719.13-152719.25" + process $proc$libresoc.v:152719$8007 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $1\muxid[1:0] 2'00 sync always sync init - update \q_int $1\q_int[0:0] + update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:160430.3-160431.27" - process $proc$libresoc.v:160430$8369 + attribute \src "libresoc.v:152734.7-152734.21" + process $proc$libresoc.v:152734$8008 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + assign $1\neg_res[0:0] 1'0 + sync always + sync init + update \neg_res $1\neg_res[0:0] end - attribute \src "libresoc.v:160432.3-160440.6" - process $proc$libresoc.v:160432$8370 + attribute \src "libresoc.v:152741.7-152741.23" + process $proc$libresoc.v:152741$8009 assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$8371 $1\q_int$next[0:0]$8372 - attribute \src "libresoc.v:160433.5-160433.29" - switch \initial - attribute \src "libresoc.v:160433.9-160433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8372 1'0 - case - assign $1\q_int$next[0:0]$8372 \$5 - end + assign $1\neg_res32[0:0] 1'0 sync always - update \q_int$next $0\q_int$next[0:0]$8371 - end - connect \$9 $and$libresoc.v:160422$8361_Y - connect \$11 $or$libresoc.v:160423$8362_Y - connect \$13 $not$libresoc.v:160424$8363_Y - connect \$15 $or$libresoc.v:160425$8364_Y - connect \$1 $not$libresoc.v:160426$8365_Y - connect \$3 $and$libresoc.v:160427$8366_Y - connect \$5 $or$libresoc.v:160428$8367_Y - connect \$7 $not$libresoc.v:160429$8368_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:160448.1-160506.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" -attribute \generator "nMigen" -module \opc_l$126 - attribute \src "libresoc.v:160449.7-160449.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160494.3-160502.6" - wire $0\q_int$next[0:0]$8385 - attribute \src "libresoc.v:160492.3-160493.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:160494.3-160502.6" - wire $1\q_int$next[0:0]$8386 - attribute \src "libresoc.v:160471.7-160471.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:160484.17-160484.96" - wire $and$libresoc.v:160484$8375_Y - attribute \src "libresoc.v:160489.17-160489.96" - wire $and$libresoc.v:160489$8380_Y - attribute \src "libresoc.v:160486.18-160486.93" - wire $not$libresoc.v:160486$8377_Y - attribute \src "libresoc.v:160488.17-160488.92" - wire $not$libresoc.v:160488$8379_Y - attribute \src "libresoc.v:160491.17-160491.92" - wire $not$libresoc.v:160491$8382_Y - attribute \src "libresoc.v:160485.18-160485.98" - wire $or$libresoc.v:160485$8376_Y - attribute \src "libresoc.v:160487.18-160487.99" - wire $or$libresoc.v:160487$8378_Y - attribute \src "libresoc.v:160490.17-160490.97" - wire $or$libresoc.v:160490$8381_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:160449.7-160449.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:160484$8375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:160484$8375_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:160489$8380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:160489$8380_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:160486$8377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:160486$8377_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:160488$8379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160488$8379_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:160491$8382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160491$8382_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:160485$8376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:160485$8376_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:160487$8378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:160487$8378_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:160490$8381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:160490$8381_Y + sync init + update \neg_res32 $1\neg_res32[0:0] end - attribute \src "libresoc.v:160449.7-160449.20" - process $proc$libresoc.v:160449$8387 + attribute \src "libresoc.v:152755.7-152755.20" + process $proc$libresoc.v:152755$8010 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\r_busy[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:160471.7-160471.19" - process $proc$libresoc.v:160471$8388 + attribute \src "libresoc.v:152760.14-152760.39" + process $proc$libresoc.v:152760$8011 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \q_int $1\q_int[0:0] + update \ra $1\ra[63:0] end - attribute \src "libresoc.v:160492.3-160493.27" - process $proc$libresoc.v:160492$8383 + attribute \src "libresoc.v:152769.14-152769.39" + process $proc$libresoc.v:152769$8012 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] end - attribute \src "libresoc.v:160494.3-160502.6" - process $proc$libresoc.v:160494$8384 - assign { } { } + attribute \src "libresoc.v:152778.7-152778.20" + process $proc$libresoc.v:152778$8013 assign { } { } - assign $0\q_int$next[0:0]$8385 $1\q_int$next[0:0]$8386 - attribute \src "libresoc.v:160495.5-160495.29" - switch \initial - attribute \src "libresoc.v:160495.9-160495.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8386 1'0 - case - assign $1\q_int$next[0:0]$8386 \$5 - end + assign $1\xer_so[0:0] 1'0 sync always - update \q_int$next $0\q_int$next[0:0]$8385 - end - connect \$9 $and$libresoc.v:160484$8375_Y - connect \$11 $or$libresoc.v:160485$8376_Y - connect \$13 $not$libresoc.v:160486$8377_Y - connect \$15 $or$libresoc.v:160487$8378_Y - connect \$1 $not$libresoc.v:160488$8379_Y - connect \$3 $and$libresoc.v:160489$8380_Y - connect \$5 $or$libresoc.v:160490$8381_Y - connect \$7 $not$libresoc.v:160491$8382_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:160510.1-160568.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" -attribute \generator "nMigen" -module \opc_l$24 - attribute \src "libresoc.v:160511.7-160511.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160556.3-160564.6" - wire $0\q_int$next[0:0]$8399 - attribute \src "libresoc.v:160554.3-160555.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:160556.3-160564.6" - wire $1\q_int$next[0:0]$8400 - attribute \src "libresoc.v:160533.7-160533.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:160546.17-160546.96" - wire $and$libresoc.v:160546$8389_Y - attribute \src "libresoc.v:160551.17-160551.96" - wire $and$libresoc.v:160551$8394_Y - attribute \src "libresoc.v:160548.18-160548.93" - wire $not$libresoc.v:160548$8391_Y - attribute \src "libresoc.v:160550.17-160550.92" - wire $not$libresoc.v:160550$8393_Y - attribute \src "libresoc.v:160553.17-160553.92" - wire $not$libresoc.v:160553$8396_Y - attribute \src "libresoc.v:160547.18-160547.98" - wire $or$libresoc.v:160547$8390_Y - attribute \src "libresoc.v:160549.18-160549.99" - wire $or$libresoc.v:160549$8392_Y - attribute \src "libresoc.v:160552.17-160552.97" - wire $or$libresoc.v:160552$8395_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:160511.7-160511.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:160546$8389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:160546$8389_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:160551$8394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:160551$8394_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:160548$8391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:160548$8391_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:160550$8393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160550$8393_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:160553$8396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160553$8396_Y + sync init + update \xer_so $1\xer_so[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:160547$8390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:160547$8390_Y + attribute \src "libresoc.v:152786.3-152787.35" + process $proc$libresoc.v:152786$7922 + assign { } { } + assign $0\neg_res32[0:0] \neg_res32$next + sync posedge \coresync_clk + update \neg_res32 $0\neg_res32[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:160549$8392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:160549$8392_Y + attribute \src "libresoc.v:152788.3-152789.31" + process $proc$libresoc.v:152788$7923 + assign { } { } + assign $0\neg_res[0:0] \neg_res$next + sync posedge \coresync_clk + update \neg_res $0\neg_res[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:160552$8395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:160552$8395_Y + attribute \src "libresoc.v:152790.3-152791.29" + process $proc$libresoc.v:152790$7924 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:160511.7-160511.20" - process $proc$libresoc.v:160511$8401 + attribute \src "libresoc.v:152792.3-152793.21" + process $proc$libresoc.v:152792$7925 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] end - attribute \src "libresoc.v:160533.7-160533.19" - process $proc$libresoc.v:160533$8402 + attribute \src "libresoc.v:152794.3-152795.21" + process $proc$libresoc.v:152794$7926 assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] end - attribute \src "libresoc.v:160554.3-160555.27" - process $proc$libresoc.v:160554$8397 + attribute \src "libresoc.v:152796.3-152797.51" + process $proc$libresoc.v:152796$7927 assign { } { } - assign $0\q_int[0:0] \q_int$next + assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \mul_op__insn_type $0\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:160556.3-160564.6" - process $proc$libresoc.v:160556$8398 + attribute \src "libresoc.v:152798.3-152799.47" + process $proc$libresoc.v:152798$7928 assign { } { } + assign $0\mul_op__fn_unit[12:0] \mul_op__fn_unit$next + sync posedge \coresync_clk + update \mul_op__fn_unit $0\mul_op__fn_unit[12:0] + end + attribute \src "libresoc.v:152800.3-152801.61" + process $proc$libresoc.v:152800$7929 assign { } { } - assign $0\q_int$next[0:0]$8399 $1\q_int$next[0:0]$8400 - attribute \src "libresoc.v:160557.5-160557.29" - switch \initial - attribute \src "libresoc.v:160557.9-160557.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8400 1'0 - case - assign $1\q_int$next[0:0]$8400 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$8399 + assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next + sync posedge \coresync_clk + update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end - connect \$9 $and$libresoc.v:160546$8389_Y - connect \$11 $or$libresoc.v:160547$8390_Y - connect \$13 $not$libresoc.v:160548$8391_Y - connect \$15 $or$libresoc.v:160549$8392_Y - connect \$1 $not$libresoc.v:160550$8393_Y - connect \$3 $and$libresoc.v:160551$8394_Y - connect \$5 $or$libresoc.v:160552$8395_Y - connect \$7 $not$libresoc.v:160553$8396_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:160572.1-160630.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" -attribute \generator "nMigen" -module \opc_l$40 - attribute \src "libresoc.v:160573.7-160573.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160618.3-160626.6" - wire $0\q_int$next[0:0]$8413 - attribute \src "libresoc.v:160616.3-160617.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:160618.3-160626.6" - wire $1\q_int$next[0:0]$8414 - attribute \src "libresoc.v:160595.7-160595.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:160608.17-160608.96" - wire $and$libresoc.v:160608$8403_Y - attribute \src "libresoc.v:160613.17-160613.96" - wire $and$libresoc.v:160613$8408_Y - attribute \src "libresoc.v:160610.18-160610.93" - wire $not$libresoc.v:160610$8405_Y - attribute \src "libresoc.v:160612.17-160612.92" - wire $not$libresoc.v:160612$8407_Y - attribute \src "libresoc.v:160615.17-160615.92" - wire $not$libresoc.v:160615$8410_Y - attribute \src "libresoc.v:160609.18-160609.98" - wire $or$libresoc.v:160609$8404_Y - attribute \src "libresoc.v:160611.18-160611.99" - wire $or$libresoc.v:160611$8406_Y - attribute \src "libresoc.v:160614.17-160614.97" - wire $or$libresoc.v:160614$8409_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:160573.7-160573.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:160608$8403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:160608$8403_Y + attribute \src "libresoc.v:152802.3-152803.57" + process $proc$libresoc.v:152802$7930 + assign { } { } + assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:160613$8408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:160613$8408_Y + attribute \src "libresoc.v:152804.3-152805.45" + process $proc$libresoc.v:152804$7931 + assign { } { } + assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next + sync posedge \coresync_clk + update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:160610$8405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:160610$8405_Y + attribute \src "libresoc.v:152806.3-152807.45" + process $proc$libresoc.v:152806$7932 + assign { } { } + assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next + sync posedge \coresync_clk + update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:160612$8407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160612$8407_Y + attribute \src "libresoc.v:152808.3-152809.45" + process $proc$libresoc.v:152808$7933 + assign { } { } + assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next + sync posedge \coresync_clk + update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:160615$8410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160615$8410_Y + attribute \src "libresoc.v:152810.3-152811.45" + process $proc$libresoc.v:152810$7934 + assign { } { } + assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next + sync posedge \coresync_clk + update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:160609$8404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:160609$8404_Y + attribute \src "libresoc.v:152812.3-152813.51" + process $proc$libresoc.v:152812$7935 + assign { } { } + assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next + sync posedge \coresync_clk + update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:160611$8406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:160611$8406_Y + attribute \src "libresoc.v:152814.3-152815.49" + process $proc$libresoc.v:152814$7936 + assign { } { } + assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next + sync posedge \coresync_clk + update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:160614$8409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:160614$8409_Y + attribute \src "libresoc.v:152816.3-152817.51" + process $proc$libresoc.v:152816$7937 + assign { } { } + assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next + sync posedge \coresync_clk + update \mul_op__is_signed $0\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:160573.7-160573.20" - process $proc$libresoc.v:160573$8415 + attribute \src "libresoc.v:152818.3-152819.41" + process $proc$libresoc.v:152818$7938 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + assign $0\mul_op__insn[31:0] \mul_op__insn$next + sync posedge \coresync_clk + update \mul_op__insn $0\mul_op__insn[31:0] end - attribute \src "libresoc.v:160595.7-160595.19" - process $proc$libresoc.v:160595$8416 + attribute \src "libresoc.v:152820.3-152821.27" + process $proc$libresoc.v:152820$7939 assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:160616.3-160617.27" - process $proc$libresoc.v:160616$8411 + attribute \src "libresoc.v:152822.3-152823.29" + process $proc$libresoc.v:152822$7940 assign { } { } - assign $0\q_int[0:0] \q_int$next + assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:160618.3-160626.6" - process $proc$libresoc.v:160618$8412 + attribute \src "libresoc.v:152902.3-152919.6" + process $proc$libresoc.v:152902$7941 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8413 $1\q_int$next[0:0]$8414 - attribute \src "libresoc.v:160619.5-160619.29" + assign { } { } + assign $0\r_busy$next[0:0]$7942 $2\r_busy$next[0:0]$7944 + attribute \src "libresoc.v:152903.5-152903.29" switch \initial - attribute \src "libresoc.v:160619.9-160619.17" + attribute \src "libresoc.v:152903.9-152903.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7943 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7943 1'0 + case + assign $1\r_busy$next[0:0]$7943 \r_busy + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8414 1'0 + assign $2\r_busy$next[0:0]$7944 1'0 case - assign $1\q_int$next[0:0]$8414 \$5 + assign $2\r_busy$next[0:0]$7944 $1\r_busy$next[0:0]$7943 end sync always - update \q_int$next $0\q_int$next[0:0]$8413 - end - connect \$9 $and$libresoc.v:160608$8403_Y - connect \$11 $or$libresoc.v:160609$8404_Y - connect \$13 $not$libresoc.v:160610$8405_Y - connect \$15 $or$libresoc.v:160611$8406_Y - connect \$1 $not$libresoc.v:160612$8407_Y - connect \$3 $and$libresoc.v:160613$8408_Y - connect \$5 $or$libresoc.v:160614$8409_Y - connect \$7 $not$libresoc.v:160615$8410_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:160634.1-160692.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" -attribute \generator "nMigen" -module \opc_l$56 - attribute \src "libresoc.v:160635.7-160635.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160680.3-160688.6" - wire $0\q_int$next[0:0]$8427 - attribute \src "libresoc.v:160678.3-160679.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:160680.3-160688.6" - wire $1\q_int$next[0:0]$8428 - attribute \src "libresoc.v:160657.7-160657.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:160670.17-160670.96" - wire $and$libresoc.v:160670$8417_Y - attribute \src "libresoc.v:160675.17-160675.96" - wire $and$libresoc.v:160675$8422_Y - attribute \src "libresoc.v:160672.18-160672.93" - wire $not$libresoc.v:160672$8419_Y - attribute \src "libresoc.v:160674.17-160674.92" - wire $not$libresoc.v:160674$8421_Y - attribute \src "libresoc.v:160677.17-160677.92" - wire $not$libresoc.v:160677$8424_Y - attribute \src "libresoc.v:160671.18-160671.98" - wire $or$libresoc.v:160671$8418_Y - attribute \src "libresoc.v:160673.18-160673.99" - wire $or$libresoc.v:160673$8420_Y - attribute \src "libresoc.v:160676.17-160676.97" - wire $or$libresoc.v:160676$8423_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:160635.7-160635.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:160670$8417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:160670$8417_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:160675$8422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:160675$8422_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:160672$8419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:160672$8419_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:160674$8421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160674$8421_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:160677$8424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160677$8424_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:160671$8418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:160671$8418_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:160673$8420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:160673$8420_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:160676$8423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:160676$8423_Y + update \r_busy$next $0\r_busy$next[0:0]$7942 end - attribute \src "libresoc.v:160635.7-160635.20" - process $proc$libresoc.v:160635$8429 + attribute \src "libresoc.v:152920.3-152932.6" + process $proc$libresoc.v:152920$7945 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:160657.7-160657.19" - process $proc$libresoc.v:160657$8430 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\muxid$next[1:0]$7946 $1\muxid$next[1:0]$7947 + attribute \src "libresoc.v:152921.5-152921.29" + switch \initial + attribute \src "libresoc.v:152921.9-152921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$7947 \muxid$52 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$7947 \muxid$52 + case + assign $1\muxid$next[1:0]$7947 \muxid + end sync always - sync init - update \q_int $1\q_int[0:0] + update \muxid$next $0\muxid$next[1:0]$7946 end - attribute \src "libresoc.v:160678.3-160679.27" - process $proc$libresoc.v:160678$8425 + attribute \src "libresoc.v:152933.3-152968.6" + process $proc$libresoc.v:152933$7948 + assign { } { } + assign { } { } assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:160680.3-160688.6" - process $proc$libresoc.v:160680$8426 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8427 $1\q_int$next[0:0]$8428 - attribute \src "libresoc.v:160681.5-160681.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$next[12:0]$7949 $1\mul_op__fn_unit$next[12:0]$7961 + assign { } { } + assign { } { } + assign $0\mul_op__insn$next[31:0]$7952 $1\mul_op__insn$next[31:0]$7964 + assign $0\mul_op__insn_type$next[6:0]$7953 $1\mul_op__insn_type$next[6:0]$7965 + assign $0\mul_op__is_32bit$next[0:0]$7954 $1\mul_op__is_32bit$next[0:0]$7966 + assign $0\mul_op__is_signed$next[0:0]$7955 $1\mul_op__is_signed$next[0:0]$7967 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$next[0:0]$7960 $1\mul_op__write_cr0$next[0:0]$7972 + assign $0\mul_op__imm_data__data$next[63:0]$7950 $2\mul_op__imm_data__data$next[63:0]$7973 + assign $0\mul_op__imm_data__ok$next[0:0]$7951 $2\mul_op__imm_data__ok$next[0:0]$7974 + assign $0\mul_op__oe__oe$next[0:0]$7956 $2\mul_op__oe__oe$next[0:0]$7975 + assign $0\mul_op__oe__ok$next[0:0]$7957 $2\mul_op__oe__ok$next[0:0]$7976 + assign $0\mul_op__rc__ok$next[0:0]$7958 $2\mul_op__rc__ok$next[0:0]$7977 + assign $0\mul_op__rc__rc$next[0:0]$7959 $2\mul_op__rc__rc$next[0:0]$7978 + attribute \src "libresoc.v:152934.5-152934.29" switch \initial - attribute \src "libresoc.v:160681.9-160681.17" + attribute \src "libresoc.v:152934.9-152934.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$7964 $1\mul_op__is_signed$next[0:0]$7967 $1\mul_op__is_32bit$next[0:0]$7966 $1\mul_op__write_cr0$next[0:0]$7972 $1\mul_op__oe__ok$next[0:0]$7969 $1\mul_op__oe__oe$next[0:0]$7968 $1\mul_op__rc__ok$next[0:0]$7970 $1\mul_op__rc__rc$next[0:0]$7971 $1\mul_op__imm_data__ok$next[0:0]$7963 $1\mul_op__imm_data__data$next[63:0]$7962 $1\mul_op__fn_unit$next[12:0]$7961 $1\mul_op__insn_type$next[6:0]$7965 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$7964 $1\mul_op__is_signed$next[0:0]$7967 $1\mul_op__is_32bit$next[0:0]$7966 $1\mul_op__write_cr0$next[0:0]$7972 $1\mul_op__oe__ok$next[0:0]$7969 $1\mul_op__oe__oe$next[0:0]$7968 $1\mul_op__rc__ok$next[0:0]$7970 $1\mul_op__rc__rc$next[0:0]$7971 $1\mul_op__imm_data__ok$next[0:0]$7963 $1\mul_op__imm_data__data$next[63:0]$7962 $1\mul_op__fn_unit$next[12:0]$7961 $1\mul_op__insn_type$next[6:0]$7965 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + case + assign $1\mul_op__fn_unit$next[12:0]$7961 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7962 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7963 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7964 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7965 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7966 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7967 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7968 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7969 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7970 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7971 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7972 \mul_op__write_cr0 + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8428 1'0 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$next[63:0]$7973 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7974 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7978 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7977 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7975 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7976 1'0 case - assign $1\q_int$next[0:0]$8428 \$5 + assign $2\mul_op__imm_data__data$next[63:0]$7973 $1\mul_op__imm_data__data$next[63:0]$7962 + assign $2\mul_op__imm_data__ok$next[0:0]$7974 $1\mul_op__imm_data__ok$next[0:0]$7963 + assign $2\mul_op__oe__oe$next[0:0]$7975 $1\mul_op__oe__oe$next[0:0]$7968 + assign $2\mul_op__oe__ok$next[0:0]$7976 $1\mul_op__oe__ok$next[0:0]$7969 + assign $2\mul_op__rc__ok$next[0:0]$7977 $1\mul_op__rc__ok$next[0:0]$7970 + assign $2\mul_op__rc__rc$next[0:0]$7978 $1\mul_op__rc__rc$next[0:0]$7971 end sync always - update \q_int$next $0\q_int$next[0:0]$8427 - end - connect \$9 $and$libresoc.v:160670$8417_Y - connect \$11 $or$libresoc.v:160671$8418_Y - connect \$13 $not$libresoc.v:160672$8419_Y - connect \$15 $or$libresoc.v:160673$8420_Y - connect \$1 $not$libresoc.v:160674$8421_Y - connect \$3 $and$libresoc.v:160675$8422_Y - connect \$5 $or$libresoc.v:160676$8423_Y - connect \$7 $not$libresoc.v:160677$8424_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:160696.1-160754.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" -attribute \generator "nMigen" -module \opc_l$68 - attribute \src "libresoc.v:160697.7-160697.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160742.3-160750.6" - wire $0\q_int$next[0:0]$8441 - attribute \src "libresoc.v:160740.3-160741.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:160742.3-160750.6" - wire $1\q_int$next[0:0]$8442 - attribute \src "libresoc.v:160719.7-160719.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:160732.17-160732.96" - wire $and$libresoc.v:160732$8431_Y - attribute \src "libresoc.v:160737.17-160737.96" - wire $and$libresoc.v:160737$8436_Y - attribute \src "libresoc.v:160734.18-160734.93" - wire $not$libresoc.v:160734$8433_Y - attribute \src "libresoc.v:160736.17-160736.92" - wire $not$libresoc.v:160736$8435_Y - attribute \src "libresoc.v:160739.17-160739.92" - wire $not$libresoc.v:160739$8438_Y - attribute \src "libresoc.v:160733.18-160733.98" - wire $or$libresoc.v:160733$8432_Y - attribute \src "libresoc.v:160735.18-160735.99" - wire $or$libresoc.v:160735$8434_Y - attribute \src "libresoc.v:160738.17-160738.97" - wire $or$libresoc.v:160738$8437_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:160697.7-160697.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:160732$8431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:160732$8431_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:160737$8436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:160737$8436_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:160734$8433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:160734$8433_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:160736$8435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160736$8435_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:160739$8438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160739$8438_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:160733$8432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:160733$8432_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:160735$8434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:160735$8434_Y + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[12:0]$7949 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7950 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7951 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7952 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7953 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7954 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7955 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7956 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7957 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7958 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7959 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7960 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:160738$8437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:160738$8437_Y - end - attribute \src "libresoc.v:160697.7-160697.20" - process $proc$libresoc.v:160697$8443 + attribute \src "libresoc.v:152969.3-152981.6" + process $proc$libresoc.v:152969$7979 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:160719.7-160719.19" - process $proc$libresoc.v:160719$8444 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\ra$next[63:0]$7980 $1\ra$next[63:0]$7981 + attribute \src "libresoc.v:152970.5-152970.29" + switch \initial + attribute \src "libresoc.v:152970.9-152970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$7981 \ra$65 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$7981 \ra$65 + case + assign $1\ra$next[63:0]$7981 \ra + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:160740.3-160741.27" - process $proc$libresoc.v:160740$8439 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \ra$next $0\ra$next[63:0]$7980 end - attribute \src "libresoc.v:160742.3-160750.6" - process $proc$libresoc.v:160742$8440 + attribute \src "libresoc.v:152982.3-152994.6" + process $proc$libresoc.v:152982$7982 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8441 $1\q_int$next[0:0]$8442 - attribute \src "libresoc.v:160743.5-160743.29" + assign $0\rb$next[63:0]$7983 $1\rb$next[63:0]$7984 + attribute \src "libresoc.v:152983.5-152983.29" switch \initial - attribute \src "libresoc.v:160743.9-160743.17" + attribute \src "libresoc.v:152983.9-152983.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$7984 \rb$66 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $1\q_int$next[0:0]$8442 1'0 + assign $1\rb$next[63:0]$7984 \rb$66 case - assign $1\q_int$next[0:0]$8442 \$5 + assign $1\rb$next[63:0]$7984 \rb end sync always - update \q_int$next $0\q_int$next[0:0]$8441 - end - connect \$9 $and$libresoc.v:160732$8431_Y - connect \$11 $or$libresoc.v:160733$8432_Y - connect \$13 $not$libresoc.v:160734$8433_Y - connect \$15 $or$libresoc.v:160735$8434_Y - connect \$1 $not$libresoc.v:160736$8435_Y - connect \$3 $and$libresoc.v:160737$8436_Y - connect \$5 $or$libresoc.v:160738$8437_Y - connect \$7 $not$libresoc.v:160739$8438_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:160758.1-160816.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" -attribute \generator "nMigen" -module \opc_l$85 - attribute \src "libresoc.v:160759.7-160759.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:160804.3-160812.6" - wire $0\q_int$next[0:0]$8455 - attribute \src "libresoc.v:160802.3-160803.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:160804.3-160812.6" - wire $1\q_int$next[0:0]$8456 - attribute \src "libresoc.v:160781.7-160781.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:160794.17-160794.96" - wire $and$libresoc.v:160794$8445_Y - attribute \src "libresoc.v:160799.17-160799.96" - wire $and$libresoc.v:160799$8450_Y - attribute \src "libresoc.v:160796.18-160796.93" - wire $not$libresoc.v:160796$8447_Y - attribute \src "libresoc.v:160798.17-160798.92" - wire $not$libresoc.v:160798$8449_Y - attribute \src "libresoc.v:160801.17-160801.92" - wire $not$libresoc.v:160801$8452_Y - attribute \src "libresoc.v:160795.18-160795.98" - wire $or$libresoc.v:160795$8446_Y - attribute \src "libresoc.v:160797.18-160797.99" - wire $or$libresoc.v:160797$8448_Y - attribute \src "libresoc.v:160800.17-160800.97" - wire $or$libresoc.v:160800$8451_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "libresoc.v:160759.7-160759.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:160794$8445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:160794$8445_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:160799$8450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:160799$8450_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:160796$8447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:160796$8447_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:160798$8449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160798$8449_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:160801$8452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:160801$8452_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:160795$8446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:160795$8446_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:160797$8448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:160797$8448_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:160800$8451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:160800$8451_Y + update \rb$next $0\rb$next[63:0]$7983 end - attribute \src "libresoc.v:160759.7-160759.20" - process $proc$libresoc.v:160759$8457 + attribute \src "libresoc.v:152995.3-153007.6" + process $proc$libresoc.v:152995$7985 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:160781.7-160781.19" - process $proc$libresoc.v:160781$8458 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\xer_so$next[0:0]$7986 $1\xer_so$next[0:0]$7987 + attribute \src "libresoc.v:152996.5-152996.29" + switch \initial + attribute \src "libresoc.v:152996.9-152996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$7987 \xer_so$67 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$7987 \xer_so$67 + case + assign $1\xer_so$next[0:0]$7987 \xer_so + end sync always - sync init - update \q_int $1\q_int[0:0] + update \xer_so$next $0\xer_so$next[0:0]$7986 end - attribute \src "libresoc.v:160802.3-160803.27" - process $proc$libresoc.v:160802$8453 + attribute \src "libresoc.v:153008.3-153020.6" + process $proc$libresoc.v:153008$7988 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + assign { } { } + assign $0\neg_res$next[0:0]$7989 $1\neg_res$next[0:0]$7990 + attribute \src "libresoc.v:153009.5-153009.29" + switch \initial + attribute \src "libresoc.v:153009.9-153009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$next[0:0]$7990 \neg_res$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$next[0:0]$7990 \neg_res$68 + case + assign $1\neg_res$next[0:0]$7990 \neg_res + end + sync always + update \neg_res$next $0\neg_res$next[0:0]$7989 end - attribute \src "libresoc.v:160804.3-160812.6" - process $proc$libresoc.v:160804$8454 + attribute \src "libresoc.v:153021.3-153033.6" + process $proc$libresoc.v:153021$7991 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8455 $1\q_int$next[0:0]$8456 - attribute \src "libresoc.v:160805.5-160805.29" + assign $0\neg_res32$next[0:0]$7992 $1\neg_res32$next[0:0]$7993 + attribute \src "libresoc.v:153022.5-153022.29" switch \initial - attribute \src "libresoc.v:160805.9-160805.17" + attribute \src "libresoc.v:153022.9-153022.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } + assign $1\neg_res32$next[0:0]$7993 \neg_res32$69 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $1\q_int$next[0:0]$8456 1'0 + assign $1\neg_res32$next[0:0]$7993 \neg_res32$69 case - assign $1\q_int$next[0:0]$8456 \$5 + assign $1\neg_res32$next[0:0]$7993 \neg_res32 end sync always - update \q_int$next $0\q_int$next[0:0]$8455 + update \neg_res32$next $0\neg_res32$next[0:0]$7992 end - connect \$9 $and$libresoc.v:160794$8445_Y - connect \$11 $or$libresoc.v:160795$8446_Y - connect \$13 $not$libresoc.v:160796$8447_Y - connect \$15 $or$libresoc.v:160797$8448_Y - connect \$1 $not$libresoc.v:160798$8449_Y - connect \$3 $and$libresoc.v:160799$8450_Y - connect \$5 $or$libresoc.v:160800$8451_Y - connect \$7 $not$libresoc.v:160801$8452_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 + connect \$50 $and$libresoc.v:152785$7921_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$69 \mul1_neg_res32 + connect \neg_res$68 \mul1_neg_res + connect \xer_so$67 \mul1_xer_so$48 + connect \rb$66 \mul1_rb$47 + connect \ra$65 \mul1_ra$46 + connect { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } + connect \muxid$52 \mul1_muxid$33 + connect \p_valid_i_p_ready_o \$50 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$49 \p_valid_i + connect \mul1_xer_so \input_xer_so$32 + connect \mul1_rb \input_rb$31 + connect \mul1_ra \input_ra$30 + connect { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } + connect \mul1_muxid \input_muxid$17 + connect \input_xer_so \xer_so$16 + connect \input_rb \rb$15 + connect \input_ra \ra$14 + connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } + connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:160820.1-161274.10" +attribute \src "libresoc.v:153060.1-153970.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" -module \output - attribute \src "libresoc.v:161193.3-161204.6" - wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:160821.7-160821.20" +module \mul_pipe2 + attribute \src "libresoc.v:153061.7-153061.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161205.3-161216.6" - wire width 65 $0\o$28[64:0]$8477 - attribute \src "libresoc.v:161181.3-161192.6" - wire $0\so[0:0] - attribute \src "libresoc.v:161237.3-161246.6" - wire width 2 $0\xer_ov$24[1:0]$8484 - attribute \src "libresoc.v:161247.3-161256.6" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:161217.3-161226.6" - wire $0\xer_so$25[0:0]$8480 - attribute \src "libresoc.v:161227.3-161236.6" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:161193.3-161204.6" - wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:161205.3-161216.6" - wire width 65 $1\o$28[64:0]$8478 - attribute \src "libresoc.v:161181.3-161192.6" - wire $1\so[0:0] - attribute \src "libresoc.v:161237.3-161246.6" - wire width 2 $1\xer_ov$24[1:0]$8485 - attribute \src "libresoc.v:161247.3-161256.6" - wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:161217.3-161226.6" - wire $1\xer_so$25[0:0]$8481 - attribute \src "libresoc.v:161227.3-161236.6" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:161168.18-161168.128" - wire $and$libresoc.v:161168$8459_Y - attribute \src "libresoc.v:161176.18-161176.112" - wire $and$libresoc.v:161176$8469_Y - attribute \src "libresoc.v:161179.18-161179.125" - wire $and$libresoc.v:161179$8472_Y - attribute \src "libresoc.v:161172.18-161172.123" - wire $eq$libresoc.v:161172$8465_Y - attribute \src "libresoc.v:161173.18-161173.123" - wire $eq$libresoc.v:161173$8466_Y - attribute \src "libresoc.v:161170.18-161170.103" - wire width 65 $extend$libresoc.v:161170$8461_Y - attribute \src "libresoc.v:161171.18-161171.101" - wire width 65 $extend$libresoc.v:161171$8463_Y - attribute \src "libresoc.v:161169.18-161169.100" - wire width 64 $not$libresoc.v:161169$8460_Y - attribute \src "libresoc.v:161175.18-161175.107" - wire $not$libresoc.v:161175$8468_Y - attribute \src "libresoc.v:161178.18-161178.107" - wire $not$libresoc.v:161178$8471_Y - attribute \src "libresoc.v:161177.18-161177.115" - wire $or$libresoc.v:161177$8470_Y - attribute \src "libresoc.v:161180.18-161180.112" - wire $or$libresoc.v:161180$8473_Y - attribute \src "libresoc.v:161170.18-161170.103" - wire width 65 $pos$libresoc.v:161170$8462_Y - attribute \src "libresoc.v:161171.18-161171.101" - wire width 65 $pos$libresoc.v:161171$8464_Y - attribute \src "libresoc.v:161174.18-161174.105" - wire $reduce_or$libresoc.v:161174$8467_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - wire \$52 + attribute \src "libresoc.v:153864.3-153899.6" + wire width 13 $0\mul_op__fn_unit$3$next[12:0]$8057 + attribute \src "libresoc.v:153762.3-153763.53" + wire width 13 $0\mul_op__fn_unit$3[12:0]$8025 + attribute \src "libresoc.v:153346.14-153346.44" + wire width 13 $0\mul_op__fn_unit$3[12:0]$8101 + attribute \src "libresoc.v:153864.3-153899.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8058 + attribute \src "libresoc.v:153764.3-153765.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8027 + attribute \src "libresoc.v:153371.14-153371.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8103 + attribute \src "libresoc.v:153864.3-153899.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8059 + attribute \src "libresoc.v:153766.3-153767.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8029 + attribute \src "libresoc.v:153380.7-153380.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8105 + attribute \src "libresoc.v:153864.3-153899.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8060 + attribute \src "libresoc.v:153782.3-153783.49" + wire width 32 $0\mul_op__insn$13[31:0]$8045 + attribute \src "libresoc.v:153387.14-153387.39" + wire width 32 $0\mul_op__insn$13[31:0]$8107 + attribute \src "libresoc.v:153864.3-153899.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8061 + attribute \src "libresoc.v:153760.3-153761.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8023 + attribute \src "libresoc.v:153544.13-153544.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8109 + attribute \src "libresoc.v:153864.3-153899.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8062 + attribute \src "libresoc.v:153778.3-153779.57" + wire $0\mul_op__is_32bit$11[0:0]$8041 + attribute \src "libresoc.v:153627.7-153627.35" + wire $0\mul_op__is_32bit$11[0:0]$8111 + attribute \src "libresoc.v:153864.3-153899.6" + wire $0\mul_op__is_signed$12$next[0:0]$8063 + attribute \src "libresoc.v:153780.3-153781.59" + wire $0\mul_op__is_signed$12[0:0]$8043 + attribute \src "libresoc.v:153636.7-153636.36" + wire $0\mul_op__is_signed$12[0:0]$8113 + attribute \src "libresoc.v:153864.3-153899.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8064 + attribute \src "libresoc.v:153772.3-153773.51" + wire $0\mul_op__oe__oe$8[0:0]$8035 + attribute \src "libresoc.v:153647.7-153647.32" + wire $0\mul_op__oe__oe$8[0:0]$8115 + attribute \src "libresoc.v:153864.3-153899.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8065 + attribute \src "libresoc.v:153774.3-153775.51" + wire $0\mul_op__oe__ok$9[0:0]$8037 + attribute \src "libresoc.v:153656.7-153656.32" + wire $0\mul_op__oe__ok$9[0:0]$8117 + attribute \src "libresoc.v:153864.3-153899.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8066 + attribute \src "libresoc.v:153770.3-153771.51" + wire $0\mul_op__rc__ok$7[0:0]$8033 + attribute \src "libresoc.v:153665.7-153665.32" + wire $0\mul_op__rc__ok$7[0:0]$8119 + attribute \src "libresoc.v:153864.3-153899.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8067 + attribute \src "libresoc.v:153768.3-153769.51" + wire $0\mul_op__rc__rc$6[0:0]$8031 + attribute \src "libresoc.v:153674.7-153674.32" + wire $0\mul_op__rc__rc$6[0:0]$8121 + attribute \src "libresoc.v:153864.3-153899.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8068 + attribute \src "libresoc.v:153776.3-153777.59" + wire $0\mul_op__write_cr0$10[0:0]$8039 + attribute \src "libresoc.v:153681.7-153681.36" + wire $0\mul_op__write_cr0$10[0:0]$8123 + attribute \src "libresoc.v:153851.3-153863.6" + wire width 2 $0\muxid$1$next[1:0]$8054 + attribute \src "libresoc.v:153784.3-153785.33" + wire width 2 $0\muxid$1[1:0]$8047 + attribute \src "libresoc.v:153690.13-153690.29" + wire width 2 $0\muxid$1[1:0]$8125 + attribute \src "libresoc.v:153926.3-153938.6" + wire $0\neg_res$15$next[0:0]$8094 + attribute \src "libresoc.v:153754.3-153755.39" + wire $0\neg_res$15[0:0]$8018 + attribute \src "libresoc.v:153705.7-153705.26" + wire $0\neg_res$15[0:0]$8127 + attribute \src "libresoc.v:153939.3-153951.6" + wire $0\neg_res32$16$next[0:0]$8097 + attribute \src "libresoc.v:153752.3-153753.43" + wire $0\neg_res32$16[0:0]$8016 + attribute \src "libresoc.v:153714.7-153714.28" + wire $0\neg_res32$16[0:0]$8129 + attribute \src "libresoc.v:153900.3-153912.6" + wire width 129 $0\o$next[128:0]$8088 + attribute \src "libresoc.v:153758.3-153759.19" + wire width 129 $0\o[128:0] + attribute \src "libresoc.v:153833.3-153850.6" + wire $0\r_busy$next[0:0]$8050 + attribute \src "libresoc.v:153786.3-153787.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:153913.3-153925.6" + wire $0\xer_so$14$next[0:0]$8091 + attribute \src "libresoc.v:153756.3-153757.37" + wire $0\xer_so$14[0:0]$8020 + attribute \src "libresoc.v:153746.7-153746.25" + wire $0\xer_so$14[0:0]$8133 + attribute \src "libresoc.v:153864.3-153899.6" + wire width 13 $1\mul_op__fn_unit$3$next[12:0]$8069 + attribute \src "libresoc.v:153864.3-153899.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8070 + attribute \src "libresoc.v:153864.3-153899.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8071 + attribute \src "libresoc.v:153864.3-153899.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8072 + attribute \src "libresoc.v:153864.3-153899.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8073 + attribute \src "libresoc.v:153864.3-153899.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8074 + attribute \src "libresoc.v:153864.3-153899.6" + wire $1\mul_op__is_signed$12$next[0:0]$8075 + attribute \src "libresoc.v:153864.3-153899.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8076 + attribute \src "libresoc.v:153864.3-153899.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8077 + attribute \src "libresoc.v:153864.3-153899.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8078 + attribute \src "libresoc.v:153864.3-153899.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8079 + attribute \src "libresoc.v:153864.3-153899.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8080 + attribute \src "libresoc.v:153851.3-153863.6" + wire width 2 $1\muxid$1$next[1:0]$8055 + attribute \src "libresoc.v:153926.3-153938.6" + wire $1\neg_res$15$next[0:0]$8095 + attribute \src "libresoc.v:153939.3-153951.6" + wire $1\neg_res32$16$next[0:0]$8098 + attribute \src "libresoc.v:153900.3-153912.6" + wire width 129 $1\o$next[128:0]$8089 + attribute \src "libresoc.v:153721.15-153721.57" + wire width 129 $1\o[128:0] + attribute \src "libresoc.v:153833.3-153850.6" + wire $1\r_busy$next[0:0]$8051 + attribute \src "libresoc.v:153735.7-153735.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:153913.3-153925.6" + wire $1\xer_so$14$next[0:0]$8092 + attribute \src "libresoc.v:153864.3-153899.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8081 + attribute \src "libresoc.v:153864.3-153899.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8082 + attribute \src "libresoc.v:153864.3-153899.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8083 + attribute \src "libresoc.v:153864.3-153899.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8084 + attribute \src "libresoc.v:153864.3-153899.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8085 + attribute \src "libresoc.v:153864.3-153899.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8086 + attribute \src "libresoc.v:153833.3-153850.6" + wire $2\r_busy$next[0:0]$8052 + attribute \src "libresoc.v:153751.18-153751.118" + wire $and$libresoc.v:153751$8014_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 41 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:153061.7-153061.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \alu_op__data_len + wire width 13 \mul2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 42 \alu_op__data_len$18 + wire width 13 \mul2_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul2_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul2_neg_res$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul2_neg_res32$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so$30 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -332534,7 +321028,7 @@ module \output attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \alu_op__fn_unit + wire width 13 input 6 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -332550,31 +321044,49 @@ module \output attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 27 \alu_op__fn_unit$3 + wire width 13 output 26 \mul_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__data + wire width 13 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 28 \alu_op__imm_data__data$4 + wire width 13 \mul_op__fn_unit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \alu_op__imm_data__ok + wire width 64 input 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \alu_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 \mul_op__imm_data__data$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 output 27 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 38 \alu_op__input_carry$14 + wire width 64 \mul_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn + wire input 8 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 43 \alu_op__insn$19 + wire \mul_op__imm_data__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$48 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -332650,7 +321162,7 @@ module \output attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \alu_op__insn_type + wire width 7 input 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -332726,556 +321238,1100 @@ module \output attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 26 \alu_op__insn_type$2 + wire width 7 output 25 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__invert_in + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \alu_op__invert_in$10 + wire width 7 \mul_op__insn_type$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__invert_out + wire input 14 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \alu_op__invert_out$12 + wire output 34 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__is_32bit + wire \mul_op__is_32bit$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \alu_op__is_32bit$16 + wire \mul_op__is_32bit$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__is_signed + wire input 15 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \alu_op__is_signed$17 + wire output 35 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \alu_op__oe__oe + wire \mul_op__is_signed$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \alu_op__oe__oe$8 + wire \mul_op__is_signed$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__oe__ok + wire input 11 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \alu_op__oe__ok$9 + wire \mul_op__oe__oe$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__output_carry + wire output 31 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__output_carry$15 + wire \mul_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \alu_op__rc__ok + wire input 12 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \alu_op__rc__ok$7 + wire \mul_op__oe__ok$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \alu_op__rc__rc + wire output 32 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \alu_op__rc__rc$6 + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__write_cr0 + wire input 13 \mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \alu_op__write_cr0$13 + wire output 33 \mul_op__write_cr0$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__zero_a + wire \mul_op__write_cr0$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 46 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 47 \cr_a_ok - attribute \src "libresoc.v:160821.7-160821.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test + wire \mul_op__write_cr0$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 54 \muxid + wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 25 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 44 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 45 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire \oe$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - wire \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 48 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 49 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 23 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 50 \xer_ov$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 51 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 24 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 52 \xer_so$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 53 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:161168$8459 + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 23 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 22 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 39 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 40 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 37 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 38 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:153751$8014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_op__oe__oe - connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:161168$8459_Y + connect \A \p_valid_i$33 + connect \B \p_ready_o + connect \Y $and$libresoc.v:153751$8014_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:161176$8469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B \$41 - connect \Y $and$libresoc.v:161176$8469_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:153788.8-153824.4" + cell \mul2 \mul2 + connect \mul_op__fn_unit \mul2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 + connect \mul_op__insn \mul2_mul_op__insn + connect \mul_op__insn$13 \mul2_mul_op__insn$29 + connect \mul_op__insn_type \mul2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 + connect \mul_op__is_32bit \mul2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 + connect \mul_op__is_signed \mul2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 + connect \mul_op__oe__oe \mul2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 + connect \mul_op__oe__ok \mul2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 + connect \mul_op__rc__ok \mul2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 + connect \mul_op__rc__rc \mul2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 + connect \muxid \mul2_muxid + connect \muxid$1 \mul2_muxid$17 + connect \neg_res \mul2_neg_res + connect \neg_res$15 \mul2_neg_res$31 + connect \neg_res32 \mul2_neg_res32 + connect \neg_res32$16 \mul2_neg_res32$32 + connect \o \mul2_o + connect \ra \mul2_ra + connect \rb \mul2_rb + connect \xer_so \mul2_xer_so + connect \xer_so$14 \mul2_xer_so$30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:161179$8472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__oe__oe - connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:161179$8472_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:153825.10-153828.4" + cell \n$97 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:161172$8465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:161172$8465_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:153829.10-153832.4" + cell \p$96 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:161173$8466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001100 - connect \Y $eq$libresoc.v:161173$8466_Y + attribute \src "libresoc.v:153061.7-153061.20" + process $proc$libresoc.v:153061$8099 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:161170$8461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \$30 - connect \Y $extend$libresoc.v:161170$8461_Y + attribute \src "libresoc.v:153346.14-153346.44" + process $proc$libresoc.v:153346$8100 + assign { } { } + assign $0\mul_op__fn_unit$3[12:0]$8101 13'0000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8101 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:161171$8463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $extend$libresoc.v:161171$8463_Y + attribute \src "libresoc.v:153371.14-153371.63" + process $proc$libresoc.v:153371$8102 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8103 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8103 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:161169$8460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $not$libresoc.v:161169$8460_Y + attribute \src "libresoc.v:153380.7-153380.38" + process $proc$libresoc.v:153380$8104 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8105 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8105 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:161175$8468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $not$libresoc.v:161175$8468_Y + attribute \src "libresoc.v:153387.14-153387.39" + process $proc$libresoc.v:153387$8106 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8107 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8107 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:161178$8471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $not$libresoc.v:161178$8471_Y + attribute \src "libresoc.v:153544.13-153544.42" + process $proc$libresoc.v:153544$8108 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8109 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8109 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:161177$8470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $or$libresoc.v:161177$8470_Y + attribute \src "libresoc.v:153627.7-153627.35" + process $proc$libresoc.v:153627$8110 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8111 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8111 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:161180$8473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $or$libresoc.v:161180$8473_Y + attribute \src "libresoc.v:153636.7-153636.36" + process $proc$libresoc.v:153636$8112 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8113 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8113 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:161170$8462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:161170$8461_Y - connect \Y $pos$libresoc.v:161170$8462_Y + attribute \src "libresoc.v:153647.7-153647.32" + process $proc$libresoc.v:153647$8114 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8115 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8115 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:161171$8464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:161171$8463_Y - connect \Y $pos$libresoc.v:161171$8464_Y + attribute \src "libresoc.v:153656.7-153656.32" + process $proc$libresoc.v:153656$8116 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8117 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8117 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:161174$8467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $reduce_or$libresoc.v:161174$8467_Y + attribute \src "libresoc.v:153665.7-153665.32" + process $proc$libresoc.v:153665$8118 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8119 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8119 end - attribute \src "libresoc.v:160821.7-160821.20" - process $proc$libresoc.v:160821$8487 + attribute \src "libresoc.v:153674.7-153674.32" + process $proc$libresoc.v:153674$8120 assign { } { } - assign $0\initial[0:0] 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8121 1'0 sync always - update \initial $0\initial[0:0] sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8121 end - attribute \src "libresoc.v:161181.3-161192.6" - process $proc$libresoc.v:161181$8474 + attribute \src "libresoc.v:153681.7-153681.36" + process $proc$libresoc.v:153681$8122 assign { } { } - assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:161182.5-161182.29" + assign $0\mul_op__write_cr0$10[0:0]$8123 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8123 + end + attribute \src "libresoc.v:153690.13-153690.29" + process $proc$libresoc.v:153690$8124 + assign { } { } + assign $0\muxid$1[1:0]$8125 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8125 + end + attribute \src "libresoc.v:153705.7-153705.26" + process $proc$libresoc.v:153705$8126 + assign { } { } + assign $0\neg_res$15[0:0]$8127 1'0 + sync always + sync init + update \neg_res$15 $0\neg_res$15[0:0]$8127 + end + attribute \src "libresoc.v:153714.7-153714.28" + process $proc$libresoc.v:153714$8128 + assign { } { } + assign $0\neg_res32$16[0:0]$8129 1'0 + sync always + sync init + update \neg_res32$16 $0\neg_res32$16[0:0]$8129 + end + attribute \src "libresoc.v:153721.15-153721.57" + process $proc$libresoc.v:153721$8130 + assign { } { } + assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[128:0] + end + attribute \src "libresoc.v:153735.7-153735.20" + process $proc$libresoc.v:153735$8131 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:153746.7-153746.25" + process $proc$libresoc.v:153746$8132 + assign { } { } + assign $0\xer_so$14[0:0]$8133 1'0 + sync always + sync init + update \xer_so$14 $0\xer_so$14[0:0]$8133 + end + attribute \src "libresoc.v:153752.3-153753.43" + process $proc$libresoc.v:153752$8015 + assign { } { } + assign $0\neg_res32$16[0:0]$8016 \neg_res32$16$next + sync posedge \coresync_clk + update \neg_res32$16 $0\neg_res32$16[0:0]$8016 + end + attribute \src "libresoc.v:153754.3-153755.39" + process $proc$libresoc.v:153754$8017 + assign { } { } + assign $0\neg_res$15[0:0]$8018 \neg_res$15$next + sync posedge \coresync_clk + update \neg_res$15 $0\neg_res$15[0:0]$8018 + end + attribute \src "libresoc.v:153756.3-153757.37" + process $proc$libresoc.v:153756$8019 + assign { } { } + assign $0\xer_so$14[0:0]$8020 \xer_so$14$next + sync posedge \coresync_clk + update \xer_so$14 $0\xer_so$14[0:0]$8020 + end + attribute \src "libresoc.v:153758.3-153759.19" + process $proc$libresoc.v:153758$8021 + assign { } { } + assign $0\o[128:0] \o$next + sync posedge \coresync_clk + update \o $0\o[128:0] + end + attribute \src "libresoc.v:153760.3-153761.57" + process $proc$libresoc.v:153760$8022 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8023 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8023 + end + attribute \src "libresoc.v:153762.3-153763.53" + process $proc$libresoc.v:153762$8024 + assign { } { } + assign $0\mul_op__fn_unit$3[12:0]$8025 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8025 + end + attribute \src "libresoc.v:153764.3-153765.67" + process $proc$libresoc.v:153764$8026 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8027 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8027 + end + attribute \src "libresoc.v:153766.3-153767.63" + process $proc$libresoc.v:153766$8028 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8029 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8029 + end + attribute \src "libresoc.v:153768.3-153769.51" + process $proc$libresoc.v:153768$8030 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8031 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8031 + end + attribute \src "libresoc.v:153770.3-153771.51" + process $proc$libresoc.v:153770$8032 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8033 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8033 + end + attribute \src "libresoc.v:153772.3-153773.51" + process $proc$libresoc.v:153772$8034 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8035 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8035 + end + attribute \src "libresoc.v:153774.3-153775.51" + process $proc$libresoc.v:153774$8036 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8037 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8037 + end + attribute \src "libresoc.v:153776.3-153777.59" + process $proc$libresoc.v:153776$8038 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8039 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8039 + end + attribute \src "libresoc.v:153778.3-153779.57" + process $proc$libresoc.v:153778$8040 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8041 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8041 + end + attribute \src "libresoc.v:153780.3-153781.59" + process $proc$libresoc.v:153780$8042 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8043 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8043 + end + attribute \src "libresoc.v:153782.3-153783.49" + process $proc$libresoc.v:153782$8044 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8045 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8045 + end + attribute \src "libresoc.v:153784.3-153785.33" + process $proc$libresoc.v:153784$8046 + assign { } { } + assign $0\muxid$1[1:0]$8047 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8047 + end + attribute \src "libresoc.v:153786.3-153787.29" + process $proc$libresoc.v:153786$8048 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:153833.3-153850.6" + process $proc$libresoc.v:153833$8049 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8050 $2\r_busy$next[0:0]$8052 + attribute \src "libresoc.v:153834.5-153834.29" switch \initial - attribute \src "libresoc.v:161182.9-161182.17" + attribute \src "libresoc.v:153834.9-153834.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - switch \oe + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\so[0:0] \xer_so$25 + assign $1\r_busy$next[0:0]$8051 1'1 attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8051 1'0 case + assign $1\r_busy$next[0:0]$8051 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\so[0:0] \xer_so + assign $2\r_busy$next[0:0]$8052 1'0 + case + assign $2\r_busy$next[0:0]$8052 $1\r_busy$next[0:0]$8051 end sync always - update \so $0\so[0:0] + update \r_busy$next $0\r_busy$next[0:0]$8050 end - attribute \src "libresoc.v:161193.3-161204.6" - process $proc$libresoc.v:161193$8475 + attribute \src "libresoc.v:153851.3-153863.6" + process $proc$libresoc.v:153851$8053 assign { } { } - assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:161194.5-161194.29" + assign { } { } + assign $0\muxid$1$next[1:0]$8054 $1\muxid$1$next[1:0]$8055 + attribute \src "libresoc.v:153852.5-153852.29" switch \initial - attribute \src "libresoc.v:161194.9-161194.17" + attribute \src "libresoc.v:153852.9-153852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\cr0[3:0] \cr_a + assign $1\muxid$1$next[1:0]$8055 \muxid$36 attribute \src "libresoc.v:0.0-0.0" - case + case 2'1- assign { } { } - assign $1\cr0[3:0] { \is_negative \is_positive \$47 \so } + assign $1\muxid$1$next[1:0]$8055 \muxid$36 + case + assign $1\muxid$1$next[1:0]$8055 \muxid$1 end sync always - update \cr0 $0\cr0[3:0] + update \muxid$1$next $0\muxid$1$next[1:0]$8054 end - attribute \src "libresoc.v:161205.3-161216.6" - process $proc$libresoc.v:161205$8476 + attribute \src "libresoc.v:153864.3-153899.6" + process $proc$libresoc.v:153864$8056 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[12:0]$8057 $1\mul_op__fn_unit$3$next[12:0]$8069 + assign { } { } assign { } { } - assign $0\o$28[64:0]$8477 $1\o$28[64:0]$8478 - attribute \src "libresoc.v:161206.5-161206.29" + assign $0\mul_op__insn$13$next[31:0]$8060 $1\mul_op__insn$13$next[31:0]$8072 + assign $0\mul_op__insn_type$2$next[6:0]$8061 $1\mul_op__insn_type$2$next[6:0]$8073 + assign $0\mul_op__is_32bit$11$next[0:0]$8062 $1\mul_op__is_32bit$11$next[0:0]$8074 + assign $0\mul_op__is_signed$12$next[0:0]$8063 $1\mul_op__is_signed$12$next[0:0]$8075 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$8068 $1\mul_op__write_cr0$10$next[0:0]$8080 + assign $0\mul_op__imm_data__data$4$next[63:0]$8058 $2\mul_op__imm_data__data$4$next[63:0]$8081 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8059 $2\mul_op__imm_data__ok$5$next[0:0]$8082 + assign $0\mul_op__oe__oe$8$next[0:0]$8064 $2\mul_op__oe__oe$8$next[0:0]$8083 + assign $0\mul_op__oe__ok$9$next[0:0]$8065 $2\mul_op__oe__ok$9$next[0:0]$8084 + assign $0\mul_op__rc__ok$7$next[0:0]$8066 $2\mul_op__rc__ok$7$next[0:0]$8085 + assign $0\mul_op__rc__rc$6$next[0:0]$8067 $2\mul_op__rc__rc$6$next[0:0]$8086 + attribute \src "libresoc.v:153865.5-153865.29" switch \initial - attribute \src "libresoc.v:161206.9-161206.17" + attribute \src "libresoc.v:153865.9-153865.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" - switch \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } - assign $1\o$28[64:0]$8478 \$29 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8072 $1\mul_op__is_signed$12$next[0:0]$8075 $1\mul_op__is_32bit$11$next[0:0]$8074 $1\mul_op__write_cr0$10$next[0:0]$8080 $1\mul_op__oe__ok$9$next[0:0]$8077 $1\mul_op__oe__oe$8$next[0:0]$8076 $1\mul_op__rc__ok$7$next[0:0]$8078 $1\mul_op__rc__rc$6$next[0:0]$8079 $1\mul_op__imm_data__ok$5$next[0:0]$8071 $1\mul_op__imm_data__data$4$next[63:0]$8070 $1\mul_op__fn_unit$3$next[12:0]$8069 $1\mul_op__insn_type$2$next[6:0]$8073 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8072 $1\mul_op__is_signed$12$next[0:0]$8075 $1\mul_op__is_32bit$11$next[0:0]$8074 $1\mul_op__write_cr0$10$next[0:0]$8080 $1\mul_op__oe__ok$9$next[0:0]$8077 $1\mul_op__oe__oe$8$next[0:0]$8076 $1\mul_op__rc__ok$7$next[0:0]$8078 $1\mul_op__rc__rc$6$next[0:0]$8079 $1\mul_op__imm_data__ok$5$next[0:0]$8071 $1\mul_op__imm_data__data$4$next[63:0]$8070 $1\mul_op__fn_unit$3$next[12:0]$8069 $1\mul_op__insn_type$2$next[6:0]$8073 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } case + assign $1\mul_op__fn_unit$3$next[12:0]$8069 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8070 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8071 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8072 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8073 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8074 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8075 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8076 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8077 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8078 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8079 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8080 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } assign { } { } - assign $1\o$28[64:0]$8478 \$33 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$8081 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8082 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8086 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8085 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8083 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8084 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$8081 $1\mul_op__imm_data__data$4$next[63:0]$8070 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8082 $1\mul_op__imm_data__ok$5$next[0:0]$8071 + assign $2\mul_op__oe__oe$8$next[0:0]$8083 $1\mul_op__oe__oe$8$next[0:0]$8076 + assign $2\mul_op__oe__ok$9$next[0:0]$8084 $1\mul_op__oe__ok$9$next[0:0]$8077 + assign $2\mul_op__rc__ok$7$next[0:0]$8085 $1\mul_op__rc__ok$7$next[0:0]$8078 + assign $2\mul_op__rc__rc$6$next[0:0]$8086 $1\mul_op__rc__rc$6$next[0:0]$8079 end sync always - update \o$28 $0\o$28[64:0]$8477 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$8057 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8058 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8059 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8060 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8061 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8062 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8063 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8064 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8065 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8066 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8067 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8068 end - attribute \src "libresoc.v:161217.3-161226.6" - process $proc$libresoc.v:161217$8479 + attribute \src "libresoc.v:153900.3-153912.6" + process $proc$libresoc.v:153900$8087 assign { } { } assign { } { } - assign $0\xer_so$25[0:0]$8480 $1\xer_so$25[0:0]$8481 - attribute \src "libresoc.v:161218.5-161218.29" + assign $0\o$next[128:0]$8088 $1\o$next[128:0]$8089 + attribute \src "libresoc.v:153901.5-153901.29" switch \initial - attribute \src "libresoc.v:161218.9-161218.17" + attribute \src "libresoc.v:153901.9-153901.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } + assign $1\o$next[128:0]$8089 \o$49 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $1\xer_so$25[0:0]$8481 \$52 + assign $1\o$next[128:0]$8089 \o$49 case - assign $1\xer_so$25[0:0]$8481 1'0 + assign $1\o$next[128:0]$8089 \o end sync always - update \xer_so$25 $0\xer_so$25[0:0]$8480 + update \o$next $0\o$next[128:0]$8088 end - attribute \src "libresoc.v:161227.3-161236.6" - process $proc$libresoc.v:161227$8482 + attribute \src "libresoc.v:153913.3-153925.6" + process $proc$libresoc.v:153913$8090 assign { } { } assign { } { } - assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:161228.5-161228.29" + assign $0\xer_so$14$next[0:0]$8091 $1\xer_so$14$next[0:0]$8092 + attribute \src "libresoc.v:153914.5-153914.29" switch \initial - attribute \src "libresoc.v:161228.9-161228.17" + attribute \src "libresoc.v:153914.9-153914.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\xer_so_ok[0:0] 1'1 + assign $1\xer_so$14$next[0:0]$8092 \xer_so$50 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$14$next[0:0]$8092 \xer_so$50 case - assign $1\xer_so_ok[0:0] 1'0 + assign $1\xer_so$14$next[0:0]$8092 \xer_so$14 end sync always - update \xer_so_ok $0\xer_so_ok[0:0] + update \xer_so$14$next $0\xer_so$14$next[0:0]$8091 end - attribute \src "libresoc.v:161237.3-161246.6" - process $proc$libresoc.v:161237$8483 + attribute \src "libresoc.v:153926.3-153938.6" + process $proc$libresoc.v:153926$8093 assign { } { } assign { } { } - assign $0\xer_ov$24[1:0]$8484 $1\xer_ov$24[1:0]$8485 - attribute \src "libresoc.v:161238.5-161238.29" + assign $0\neg_res$15$next[0:0]$8094 $1\neg_res$15$next[0:0]$8095 + attribute \src "libresoc.v:153927.5-153927.29" switch \initial - attribute \src "libresoc.v:161238.9-161238.17" + attribute \src "libresoc.v:153927.9-153927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 + assign { } { } + assign $1\neg_res$15$next[0:0]$8095 \neg_res$51 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign $1\xer_ov$24[1:0]$8485 \xer_ov + assign $1\neg_res$15$next[0:0]$8095 \neg_res$51 case - assign $1\xer_ov$24[1:0]$8485 2'00 + assign $1\neg_res$15$next[0:0]$8095 \neg_res$15 end sync always - update \xer_ov$24 $0\xer_ov$24[1:0]$8484 + update \neg_res$15$next $0\neg_res$15$next[0:0]$8094 end - attribute \src "libresoc.v:161247.3-161256.6" - process $proc$libresoc.v:161247$8486 + attribute \src "libresoc.v:153939.3-153951.6" + process $proc$libresoc.v:153939$8096 assign { } { } assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:161248.5-161248.29" + assign $0\neg_res32$16$next[0:0]$8097 $1\neg_res32$16$next[0:0]$8098 + attribute \src "libresoc.v:153940.5-153940.29" switch \initial - attribute \src "libresoc.v:161248.9-161248.17" + attribute \src "libresoc.v:153940.9-153940.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 + assign $1\neg_res32$16$next[0:0]$8098 \neg_res32$52 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$16$next[0:0]$8098 \neg_res32$52 case - assign $1\xer_ov_ok[0:0] 1'0 + assign $1\neg_res32$16$next[0:0]$8098 \neg_res32$16 end sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8097 end - connect \$26 $and$libresoc.v:161168$8459_Y - connect \$30 $not$libresoc.v:161169$8460_Y - connect \$29 $pos$libresoc.v:161170$8462_Y - connect \$33 $pos$libresoc.v:161171$8464_Y - connect \$35 $eq$libresoc.v:161172$8465_Y - connect \$37 $eq$libresoc.v:161173$8466_Y - connect \$39 $reduce_or$libresoc.v:161174$8467_Y - connect \$41 $not$libresoc.v:161175$8468_Y - connect \$43 $and$libresoc.v:161176$8469_Y - connect \$45 $or$libresoc.v:161177$8470_Y - connect \$47 $not$libresoc.v:161178$8471_Y - connect \$50 $and$libresoc.v:161179$8472_Y - connect \$52 $or$libresoc.v:161180$8473_Y - connect \oe$49 \$50 - connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \muxid$1 \muxid - connect \cr_a_ok \alu_op__write_cr0 - connect \cr_a$22 \cr0 - connect \o_ok$21 \o_ok - connect \o$20 \o$28 [63:0] - connect \is_positive \$43 - connect \is_negative \msb_test - connect \is_nzero \$39 - connect \msb_test \target [63] - connect \is_cmpeqb \$37 - connect \is_cmp \$35 - connect \xer_ca_ok \alu_op__output_carry - connect \xer_ca$23 \xer_ca - connect \target \o$28 [63:0] - connect \oe \$26 + connect \$34 $and$libresoc.v:153751$8014_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$52 \mul2_neg_res32$32 + connect \neg_res$51 \mul2_neg_res$31 + connect \xer_so$50 \mul2_xer_so$30 + connect \o$49 \mul2_o + connect { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } + connect \muxid$36 \mul2_muxid$17 + connect \p_valid_i_p_ready_o \$34 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$33 \p_valid_i + connect \mul2_neg_res32 \neg_res32 + connect \mul2_neg_res \neg_res + connect \mul2_xer_so \xer_so + connect \mul2_rb \rb + connect \mul2_ra \ra + connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul2_muxid \muxid end -attribute \src "libresoc.v:161278.1-161675.10" +attribute \src "libresoc.v:153974.1-155256.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" -module \output$100 - attribute \src "libresoc.v:161607.3-161618.6" - wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:161279.7-161279.20" +module \mul_pipe3 + attribute \src "libresoc.v:155174.3-155192.6" + wire width 4 $0\cr_a$next[3:0]$8217 + attribute \src "libresoc.v:154966.3-154967.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:155174.3-155192.6" + wire $0\cr_a_ok$next[0:0]$8218 + attribute \src "libresoc.v:154968.3-154969.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:153975.7-153975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161595.3-161606.6" - wire $0\so[0:0] - attribute \src "libresoc.v:161639.3-161648.6" - wire width 2 $0\xer_ov$17[1:0]$8507 - attribute \src "libresoc.v:161649.3-161658.6" + attribute \src "libresoc.v:155119.3-155154.6" + wire width 13 $0\mul_op__fn_unit$3$next[12:0]$8180 + attribute \src "libresoc.v:154976.3-154977.53" + wire width 13 $0\mul_op__fn_unit$3[12:0]$8148 + attribute \src "libresoc.v:154280.14-154280.44" + wire width 13 $0\mul_op__fn_unit$3[12:0]$8238 + attribute \src "libresoc.v:155119.3-155154.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8181 + attribute \src "libresoc.v:154978.3-154979.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8150 + attribute \src "libresoc.v:154303.14-154303.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8240 + attribute \src "libresoc.v:155119.3-155154.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8182 + attribute \src "libresoc.v:154980.3-154981.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8152 + attribute \src "libresoc.v:154312.7-154312.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8242 + attribute \src "libresoc.v:155119.3-155154.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8183 + attribute \src "libresoc.v:154996.3-154997.49" + wire width 32 $0\mul_op__insn$13[31:0]$8168 + attribute \src "libresoc.v:154321.14-154321.39" + wire width 32 $0\mul_op__insn$13[31:0]$8244 + attribute \src "libresoc.v:155119.3-155154.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8184 + attribute \src "libresoc.v:154974.3-154975.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8146 + attribute \src "libresoc.v:154478.13-154478.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8246 + attribute \src "libresoc.v:155119.3-155154.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8185 + attribute \src "libresoc.v:154992.3-154993.57" + wire $0\mul_op__is_32bit$11[0:0]$8164 + attribute \src "libresoc.v:154561.7-154561.35" + wire $0\mul_op__is_32bit$11[0:0]$8248 + attribute \src "libresoc.v:155119.3-155154.6" + wire $0\mul_op__is_signed$12$next[0:0]$8186 + attribute \src "libresoc.v:154994.3-154995.59" + wire $0\mul_op__is_signed$12[0:0]$8166 + attribute \src "libresoc.v:154570.7-154570.36" + wire $0\mul_op__is_signed$12[0:0]$8250 + attribute \src "libresoc.v:155119.3-155154.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8187 + attribute \src "libresoc.v:154986.3-154987.51" + wire $0\mul_op__oe__oe$8[0:0]$8158 + attribute \src "libresoc.v:154581.7-154581.32" + wire $0\mul_op__oe__oe$8[0:0]$8252 + attribute \src "libresoc.v:155119.3-155154.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8188 + attribute \src "libresoc.v:154988.3-154989.51" + wire $0\mul_op__oe__ok$9[0:0]$8160 + attribute \src "libresoc.v:154590.7-154590.32" + wire $0\mul_op__oe__ok$9[0:0]$8254 + attribute \src "libresoc.v:155119.3-155154.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8189 + attribute \src "libresoc.v:154984.3-154985.51" + wire $0\mul_op__rc__ok$7[0:0]$8156 + attribute \src "libresoc.v:154599.7-154599.32" + wire $0\mul_op__rc__ok$7[0:0]$8256 + attribute \src "libresoc.v:155119.3-155154.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8190 + attribute \src "libresoc.v:154982.3-154983.51" + wire $0\mul_op__rc__rc$6[0:0]$8154 + attribute \src "libresoc.v:154606.7-154606.32" + wire $0\mul_op__rc__rc$6[0:0]$8258 + attribute \src "libresoc.v:155119.3-155154.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8191 + attribute \src "libresoc.v:154990.3-154991.59" + wire $0\mul_op__write_cr0$10[0:0]$8162 + attribute \src "libresoc.v:154615.7-154615.36" + wire $0\mul_op__write_cr0$10[0:0]$8260 + attribute \src "libresoc.v:155106.3-155118.6" + wire width 2 $0\muxid$1$next[1:0]$8177 + attribute \src "libresoc.v:154998.3-154999.33" + wire width 2 $0\muxid$1[1:0]$8170 + attribute \src "libresoc.v:154624.13-154624.29" + wire width 2 $0\muxid$1[1:0]$8262 + attribute \src "libresoc.v:155155.3-155173.6" + wire width 64 $0\o$14$next[63:0]$8212 + attribute \src "libresoc.v:154970.3-154971.27" + wire width 64 $0\o$14[63:0]$8143 + attribute \src "libresoc.v:154645.14-154645.43" + wire width 64 $0\o$14[63:0]$8264 + attribute \src "libresoc.v:155155.3-155173.6" + wire $0\o_ok$next[0:0]$8211 + attribute \src "libresoc.v:154972.3-154973.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:155088.3-155105.6" + wire $0\r_busy$next[0:0]$8173 + attribute \src "libresoc.v:155000.3-155001.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:155193.3-155211.6" + wire width 2 $0\xer_ov$next[1:0]$8223 + attribute \src "libresoc.v:154962.3-154963.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:155193.3-155211.6" + wire $0\xer_ov_ok$next[0:0]$8224 + attribute \src "libresoc.v:154964.3-154965.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:161619.3-161628.6" - wire $0\xer_so$18[0:0]$8503 - attribute \src "libresoc.v:161629.3-161638.6" + attribute \src "libresoc.v:155212.3-155230.6" + wire $0\xer_so$15$next[0:0]$8230 + attribute \src "libresoc.v:154958.3-154959.37" + wire $0\xer_so$15[0:0]$8136 + attribute \src "libresoc.v:154943.7-154943.25" + wire $0\xer_so$15[0:0]$8270 + attribute \src "libresoc.v:155212.3-155230.6" + wire $0\xer_so_ok$next[0:0]$8229 + attribute \src "libresoc.v:154960.3-154961.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:161607.3-161618.6" - wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:161595.3-161606.6" - wire $1\so[0:0] - attribute \src "libresoc.v:161639.3-161648.6" - wire width 2 $1\xer_ov$17[1:0]$8508 - attribute \src "libresoc.v:161649.3-161658.6" + attribute \src "libresoc.v:155174.3-155192.6" + wire width 4 $1\cr_a$next[3:0]$8219 + attribute \src "libresoc.v:153984.13-153984.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:155174.3-155192.6" + wire $1\cr_a_ok$next[0:0]$8220 + attribute \src "libresoc.v:153993.7-153993.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:155119.3-155154.6" + wire width 13 $1\mul_op__fn_unit$3$next[12:0]$8192 + attribute \src "libresoc.v:155119.3-155154.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8193 + attribute \src "libresoc.v:155119.3-155154.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8194 + attribute \src "libresoc.v:155119.3-155154.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8195 + attribute \src "libresoc.v:155119.3-155154.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8196 + attribute \src "libresoc.v:155119.3-155154.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8197 + attribute \src "libresoc.v:155119.3-155154.6" + wire $1\mul_op__is_signed$12$next[0:0]$8198 + attribute \src "libresoc.v:155119.3-155154.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8199 + attribute \src "libresoc.v:155119.3-155154.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8200 + attribute \src "libresoc.v:155119.3-155154.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8201 + attribute \src "libresoc.v:155119.3-155154.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8202 + attribute \src "libresoc.v:155119.3-155154.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8203 + attribute \src "libresoc.v:155106.3-155118.6" + wire width 2 $1\muxid$1$next[1:0]$8178 + attribute \src "libresoc.v:155155.3-155173.6" + wire width 64 $1\o$14$next[63:0]$8214 + attribute \src "libresoc.v:155155.3-155173.6" + wire $1\o_ok$next[0:0]$8213 + attribute \src "libresoc.v:154652.7-154652.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:155088.3-155105.6" + wire $1\r_busy$next[0:0]$8174 + attribute \src "libresoc.v:154920.7-154920.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:155193.3-155211.6" + wire width 2 $1\xer_ov$next[1:0]$8225 + attribute \src "libresoc.v:154925.13-154925.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:155193.3-155211.6" + wire $1\xer_ov_ok$next[0:0]$8226 + attribute \src "libresoc.v:154932.7-154932.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:161619.3-161628.6" - wire $1\xer_so$18[0:0]$8504 - attribute \src "libresoc.v:161629.3-161638.6" + attribute \src "libresoc.v:155212.3-155230.6" + wire $1\xer_so$15$next[0:0]$8232 + attribute \src "libresoc.v:155212.3-155230.6" + wire $1\xer_so_ok$next[0:0]$8231 + attribute \src "libresoc.v:154950.7-154950.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:161584.18-161584.128" - wire $and$libresoc.v:161584$8488_Y - attribute \src "libresoc.v:161590.18-161590.112" - wire $and$libresoc.v:161590$8495_Y - attribute \src "libresoc.v:161593.18-161593.125" - wire $and$libresoc.v:161593$8498_Y - attribute \src "libresoc.v:161586.18-161586.123" - wire $eq$libresoc.v:161586$8491_Y - attribute \src "libresoc.v:161587.18-161587.123" - wire $eq$libresoc.v:161587$8492_Y - attribute \src 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$2\mul_op__imm_data__ok$5$next[0:0]$8205 + attribute \src "libresoc.v:155119.3-155154.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8206 + attribute \src "libresoc.v:155119.3-155154.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8207 + attribute \src "libresoc.v:155119.3-155154.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8208 + attribute \src "libresoc.v:155119.3-155154.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8209 + attribute \src "libresoc.v:155155.3-155173.6" + wire $2\o_ok$next[0:0]$8215 + attribute \src "libresoc.v:155088.3-155105.6" + wire $2\r_busy$next[0:0]$8175 + attribute \src "libresoc.v:155193.3-155211.6" + wire $2\xer_ov_ok$next[0:0]$8227 + attribute \src "libresoc.v:155212.3-155230.6" + wire $2\xer_so_ok$next[0:0]$8233 + attribute \src "libresoc.v:154957.18-154957.118" + wire $and$libresoc.v:154957$8134_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 44 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 65 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 + wire width 4 output 38 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 15 \cr_a + wire width 4 \cr_a$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 33 \cr_a$16 + wire width 4 \cr_a$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 34 \cr_a_ok - attribute \src "libresoc.v:161279.7-161279.15" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:153975.7-153975.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -333291,7 +322347,7 @@ module \output$100 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \mul_op__fn_unit + wire width 13 \mul3_mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -333307,19 +322363,19 @@ module \output$100 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 20 \mul_op__fn_unit$3 + wire width 13 \mul3_mul_op__fn_unit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data + wire width 64 \mul3_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 21 \mul_op__imm_data__data$4 + wire width 64 \mul3_mul_op__imm_data__data$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \mul_op__imm_data__ok + wire \mul3_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 22 \mul_op__imm_data__ok$5 + wire \mul3_mul_op__imm_data__ok$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn + wire width 32 \mul3_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 30 \mul_op__insn$13 + wire width 32 \mul3_mul_op__insn$28 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -333395,7 +322451,7 @@ module \output$100 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type + wire width 7 \mul3_mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -333471,443 +322527,73 @@ module \output$100 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 19 \mul_op__insn_type$2 + wire width 7 \mul3_mul_op__insn_type$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__is_32bit + wire \mul3_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \mul_op__is_32bit$11 + wire \mul3_mul_op__is_32bit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__is_signed + wire \mul3_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \mul_op__is_signed$12 + wire \mul3_mul_op__is_signed$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \mul_op__oe__oe + wire \mul3_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \mul_op__oe__oe$8 + wire \mul3_mul_op__oe__oe$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__oe__ok + wire \mul3_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \mul_op__oe__ok$9 + wire \mul3_mul_op__oe__ok$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \mul_op__rc__ok + wire \mul3_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \mul_op__rc__ok$7 + wire \mul3_mul_op__rc__ok$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc + wire \mul3_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__rc__rc$6 + wire \mul3_mul_op__rc__rc$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 + wire \mul3_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__write_cr0$10 + wire \mul3_mul_op__write_cr0$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 39 \muxid + wire width 2 \mul3_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 18 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 13 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 31 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 14 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \o_ok$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire \oe$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - wire \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 16 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 35 \xer_ov$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 36 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 17 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 37 \xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 38 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:161584$8488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \mul_op__oe__oe - connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:161584$8488_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:161590$8495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B \$30 - connect \Y $and$libresoc.v:161590$8495_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:161593$8498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \mul_op__oe__oe - connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:161593$8498_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:161586$8491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \mul_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:161586$8491_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:161587$8492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \mul_op__insn_type - connect \B 7'0001100 - connect \Y $eq$libresoc.v:161587$8492_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:161585$8489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $extend$libresoc.v:161585$8489_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:161589$8494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $not$libresoc.v:161589$8494_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:161592$8497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $not$libresoc.v:161592$8497_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:161591$8496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $or$libresoc.v:161591$8496_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:161594$8499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $or$libresoc.v:161594$8499_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:161585$8490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:161585$8489_Y - connect \Y $pos$libresoc.v:161585$8490_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:161588$8493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $reduce_or$libresoc.v:161588$8493_Y - end - attribute \src "libresoc.v:161279.7-161279.20" - process $proc$libresoc.v:161279$8510 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:161595.3-161606.6" - process $proc$libresoc.v:161595$8500 - assign { } { } - assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:161596.5-161596.29" - switch \initial - attribute \src "libresoc.v:161596.9-161596.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - switch \oe - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\so[0:0] \xer_so$18 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\so[0:0] \xer_so - end - sync always - update \so $0\so[0:0] - end - attribute \src "libresoc.v:161607.3-161618.6" - process $proc$libresoc.v:161607$8501 - assign { } { } - assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:161608.5-161608.29" - switch \initial - attribute \src "libresoc.v:161608.9-161608.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch \$34 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cr0[3:0] \cr_a - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cr0[3:0] { \is_negative \is_positive \$36 \so } - end - sync always - update \cr0 $0\cr0[3:0] - end - attribute \src "libresoc.v:161619.3-161628.6" - process $proc$libresoc.v:161619$8502 - assign { } { } - assign { } { } - assign $0\xer_so$18[0:0]$8503 $1\xer_so$18[0:0]$8504 - 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always - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:161639.3-161648.6" - process $proc$libresoc.v:161639$8506 - assign { } { } - assign { } { } - assign $0\xer_ov$17[1:0]$8507 $1\xer_ov$17[1:0]$8508 - attribute \src "libresoc.v:161640.5-161640.29" - switch \initial - attribute \src "libresoc.v:161640.9-161640.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$38 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_ov$17[1:0]$8508 \xer_ov - case - assign $1\xer_ov$17[1:0]$8508 2'00 - end - sync always - update \xer_ov$17 $0\xer_ov$17[1:0]$8507 - end - attribute \src "libresoc.v:161649.3-161658.6" - process $proc$libresoc.v:161649$8509 - assign { } { } - assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:161650.5-161650.29" - switch \initial - attribute \src "libresoc.v:161650.9-161650.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$38 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 - case - assign $1\xer_ov_ok[0:0] 1'0 - end - sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - connect \$19 $and$libresoc.v:161584$8488_Y - connect \$22 $pos$libresoc.v:161585$8490_Y - connect \$24 $eq$libresoc.v:161586$8491_Y - connect \$26 $eq$libresoc.v:161587$8492_Y - connect \$28 $reduce_or$libresoc.v:161588$8493_Y - connect \$30 $not$libresoc.v:161589$8494_Y - connect \$32 $and$libresoc.v:161590$8495_Y - connect \$34 $or$libresoc.v:161591$8496_Y - connect \$36 $not$libresoc.v:161592$8497_Y - connect \$39 $and$libresoc.v:161593$8498_Y - connect \$41 $or$libresoc.v:161594$8499_Y - connect \oe$38 \$39 - connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \muxid$1 \muxid - connect \cr_a_ok \mul_op__write_cr0 - connect \cr_a$16 \cr0 - connect \o_ok$15 \o_ok - connect \o$14 \o$21 [63:0] - connect \is_positive \$32 - connect \is_negative \msb_test - connect \is_nzero \$28 - connect \msb_test \target [63] - connect \is_cmpeqb \$26 - connect \is_cmp \$24 - connect \target \o$21 [63:0] - connect \o$21 \$22 - connect \oe \$19 -end -attribute \src "libresoc.v:161679.1-162029.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" -attribute \generator "nMigen" -module \output$118 - attribute \src "libresoc.v:162001.3-162012.6" - wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:161680.7-161680.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:162001.3-162012.6" - wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:161998.18-161998.112" - wire $and$libresoc.v:161998$8517_Y - attribute \src "libresoc.v:161994.18-161994.122" - wire $eq$libresoc.v:161994$8513_Y - attribute \src "libresoc.v:161995.18-161995.122" - wire $eq$libresoc.v:161995$8514_Y - attribute \src "libresoc.v:161993.18-161993.101" - wire width 65 $extend$libresoc.v:161993$8511_Y - attribute \src "libresoc.v:161997.18-161997.107" - wire $not$libresoc.v:161997$8516_Y - attribute \src "libresoc.v:162000.18-162000.107" - wire $not$libresoc.v:162000$8519_Y - attribute \src "libresoc.v:161999.18-161999.115" - wire $or$libresoc.v:161999$8518_Y - attribute \src "libresoc.v:161993.18-161993.101" - wire width 65 $pos$libresoc.v:161993$8512_Y - attribute \src "libresoc.v:161996.18-161996.105" - wire $reduce_or$libresoc.v:161996$8515_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 65 \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 20 \cr_a + wire width 2 \mul3_muxid$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 43 \cr_a$21 + wire width 64 \mul3_o$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 44 \cr_a_ok - attribute \src "libresoc.v:161680.7-161680.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 47 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 23 \muxid$1 + wire \mul3_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 18 \o + wire width 2 \mul3_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 41 \o$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$23 + wire \mul3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul3_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 19 \o_ok + wire \mul3_xer_so$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 42 \o_ok$20 + wire \mul3_xer_so_ok + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -333923,7 +322609,9 @@ module \output$118 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \sr_op__fn_unit + wire width 13 output 25 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_op__fn_unit$3$next attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -333939,35 +322627,31 @@ module \output$118 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 25 \sr_op__fn_unit$3 + wire width 13 \mul_op__fn_unit$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__data + wire width 64 input 7 \mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \sr_op__imm_data__data$4 + wire width 64 output 26 \mul_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \sr_op__imm_data__ok + wire width 64 \mul_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \sr_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 \mul_op__imm_data__data$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire input 8 \mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 34 \sr_op__input_carry$12 + wire output 27 \mul_op__imm_data__ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__input_cr + wire \mul_op__imm_data__ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__input_cr$14 + wire \mul_op__imm_data__ok$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 17 \sr_op__insn + wire width 32 input 16 \mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \sr_op__insn$18 + wire width 32 output 35 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$70 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -334043,7 +322727,7 @@ module \output$118 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \sr_op__insn_type + wire width 7 input 5 \mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -334119,281 +322803,181 @@ module \output$118 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \sr_op__insn_type$2 + wire width 7 output 24 \mul_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__invert_in + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \sr_op__invert_in$11 + wire width 7 \mul_op__insn_type$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__is_32bit + wire input 14 \mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \sr_op__is_32bit$16 + wire output 33 \mul_op__is_32bit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \sr_op__is_signed + wire \mul_op__is_32bit$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \sr_op__is_signed$17 + wire \mul_op__is_32bit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \sr_op__oe__oe + wire input 15 \mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \sr_op__oe__oe$8 + wire output 34 \mul_op__is_signed$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \sr_op__oe__ok + wire \mul_op__is_signed$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \sr_op__oe__ok$9 + wire \mul_op__is_signed$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__output_carry + wire input 11 \mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \sr_op__output_carry$13 + wire \mul_op__oe__oe$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__output_cr + wire output 30 \mul_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__output_cr$15 + wire \mul_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \sr_op__rc__ok + wire input 12 \mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \sr_op__rc__ok$7 + wire \mul_op__oe__ok$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \sr_op__rc__rc + wire output 31 \mul_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \sr_op__rc__rc$6 + wire \mul_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \sr_op__write_cr0 + wire input 10 \mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \sr_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 22 \xer_ca + wire \mul_op__rc__ok$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 22 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 21 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 19 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire input 20 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 17 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 45 \xer_ca$22 + wire width 64 output 36 \o$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 46 \xer_ca_ok + wire width 64 \o$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:161998$8517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B \$32 - connect \Y $and$libresoc.v:161998$8517_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:161994$8513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \sr_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:161994$8513_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:161995$8514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \sr_op__insn_type - connect \B 7'0001100 - connect \Y $eq$libresoc.v:161995$8514_Y - end + wire width 64 \o$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:161993$8511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $extend$libresoc.v:161993$8511_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:161997$8516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $not$libresoc.v:161997$8516_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:162000$8519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $not$libresoc.v:162000$8519_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:161999$8518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $or$libresoc.v:161999$8518_Y - end + wire output 37 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:161993$8512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:161993$8511_Y - connect \Y $pos$libresoc.v:161993$8512_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:161996$8515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $reduce_or$libresoc.v:161996$8515_Y - end - attribute \src "libresoc.v:161680.7-161680.20" - process $proc$libresoc.v:161680$8521 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:162001.3-162012.6" - process $proc$libresoc.v:162001$8520 - assign { } { } - assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:162002.5-162002.29" - switch \initial - attribute \src "libresoc.v:162002.9-162002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch \$36 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cr0[3:0] \cr_a - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cr0[3:0] { \is_negative \is_positive \$38 \xer_so } - end - sync always - update \cr0 $0\cr0[3:0] - end - connect \$24 $pos$libresoc.v:161993$8512_Y - connect \$26 $eq$libresoc.v:161994$8513_Y - connect \$28 $eq$libresoc.v:161995$8514_Y - connect \$30 $reduce_or$libresoc.v:161996$8515_Y - connect \$32 $not$libresoc.v:161997$8516_Y - connect \$34 $and$libresoc.v:161998$8517_Y - connect \$36 $or$libresoc.v:161999$8518_Y - connect \$38 $not$libresoc.v:162000$8519_Y - connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \muxid$1 \muxid - connect \cr_a_ok \sr_op__write_cr0 - connect \cr_a$21 \cr0 - connect \o_ok$20 \o_ok - connect \o$19 \o$23 [63:0] - connect \is_positive \$34 - connect \is_negative \msb_test - connect \is_nzero \$30 - connect \msb_test \target [63] - connect \is_cmpeqb \$28 - connect \is_cmp \$26 - connect \xer_ca_ok \sr_op__output_carry - connect \xer_ca$22 \xer_ca - connect \target \o$23 [63:0] - connect \o$23 \$24 -end -attribute \src "libresoc.v:162033.1-162396.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" -attribute \generator "nMigen" -module \output$54 - attribute \src "libresoc.v:162371.3-162382.6" - wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:162034.7-162034.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:162359.3-162370.6" - wire width 65 $0\o$23[64:0]$8535 - attribute \src "libresoc.v:162371.3-162382.6" - wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:162359.3-162370.6" - wire width 65 $1\o$23[64:0]$8536 - attribute \src "libresoc.v:162356.18-162356.112" - wire $and$libresoc.v:162356$8531_Y - attribute \src "libresoc.v:162352.18-162352.127" - wire $eq$libresoc.v:162352$8527_Y - attribute \src "libresoc.v:162353.18-162353.127" - wire $eq$libresoc.v:162353$8528_Y - attribute \src "libresoc.v:162350.18-162350.103" - wire width 65 $extend$libresoc.v:162350$8523_Y - attribute \src "libresoc.v:162351.18-162351.101" - wire width 65 $extend$libresoc.v:162351$8525_Y - attribute \src "libresoc.v:162349.18-162349.100" - wire width 64 $not$libresoc.v:162349$8522_Y - attribute \src "libresoc.v:162355.18-162355.107" - wire $not$libresoc.v:162355$8530_Y - attribute \src "libresoc.v:162358.18-162358.107" - wire $not$libresoc.v:162358$8533_Y - attribute \src "libresoc.v:162357.18-162357.115" - wire $or$libresoc.v:162357$8532_Y - attribute \src "libresoc.v:162350.18-162350.103" - wire width 65 $pos$libresoc.v:162350$8524_Y - attribute \src "libresoc.v:162351.18-162351.101" - wire width 65 $pos$libresoc.v:162351$8526_Y - attribute \src "libresoc.v:162354.18-162354.105" - wire $reduce_or$libresoc.v:162354$8529_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - wire width 65 \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - wire width 64 \$25 + wire \o_ok$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 65 \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 + wire \o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 21 \cr_a + wire width 4 \output_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 44 \cr_a$22 + wire width 4 \output_cr_a$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 45 \cr_a_ok - attribute \src "libresoc.v:162034.7-162034.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 40 \logical_op__data_len$18 + wire \output_cr_a_ok attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -334409,7 +322993,7 @@ module \output$54 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 2 \logical_op__fn_unit + wire width 13 \output_mul_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -334425,31 +323009,19 @@ module \output$54 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 25 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \logical_op__imm_data__data$4 + wire width 13 \output_mul_op__fn_unit$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \logical_op__imm_data__ok + wire width 64 \output_mul_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 \output_mul_op__imm_data__data$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire \output_mul_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 34 \logical_op__input_carry$12 + wire \output_mul_op__imm_data__ok$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn + wire width 32 \output_mul_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \logical_op__insn$19 + wire width 32 \output_mul_op__insn$43 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -334525,7 +323097,7 @@ module \output$54 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type + wire width 7 \output_mul_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -334601,4932 +323173,6254 @@ module \output$54 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__is_signed$17 + wire width 7 \output_mul_op__insn_type$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe + wire \output_mul_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__oe$8 + wire \output_mul_op__is_32bit$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok + wire \output_mul_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__oe__ok$9 + wire \output_mul_op__is_signed$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry + wire \output_mul_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__output_carry$15 + wire \output_mul_op__oe__oe$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok + wire \output_mul_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__rc__ok$7 + wire \output_mul_op__oe__ok$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc + wire \output_mul_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__rc$6 + wire \output_mul_op__rc__ok$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 + wire \output_mul_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__write_cr0$14 + wire \output_mul_op__rc__rc$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a + wire \output_mul_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test + wire \output_mul_op__write_cr0$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 46 \muxid + wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 23 \muxid$1 + wire width 2 \output_muxid$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 19 \o + wire width 64 \output_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 42 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$23 + wire width 64 \output_o$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 20 \o_ok + wire \output_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 43 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target + wire \output_o_ok$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 22 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:162356$8531 + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 40 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 41 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 18 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:154957$8134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$55 + connect \B \p_ready_o + connect \Y $and$libresoc.v:154957$8134_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155002.8-155038.4" + cell \mul3 \mul3 + connect \mul_op__fn_unit \mul3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 + connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 + connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 + connect \mul_op__insn \mul3_mul_op__insn + connect \mul_op__insn$13 \mul3_mul_op__insn$28 + connect \mul_op__insn_type \mul3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 + connect \mul_op__is_32bit \mul3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 + connect \mul_op__is_signed \mul3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 + connect \mul_op__oe__oe \mul3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 + connect \mul_op__oe__ok \mul3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 + connect \mul_op__rc__ok \mul3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 + connect \mul_op__rc__rc \mul3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 + connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 + connect \muxid \mul3_muxid + connect \muxid$1 \mul3_muxid$16 + connect \neg_res \mul3_neg_res + connect \o \mul3_o + connect \o$14 \mul3_o$29 + connect \o_ok \mul3_o_ok + connect \xer_ov \mul3_xer_ov + connect \xer_ov_ok \mul3_xer_ov_ok + connect \xer_so \mul3_xer_so + connect \xer_so$15 \mul3_xer_so$30 + connect \xer_so_ok \mul3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155039.10-155042.4" + cell \n$99 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155043.16-155083.4" + cell \output$100 \output + connect \cr_a \output_cr_a + connect \cr_a$16 \output_cr_a$46 + connect \cr_a_ok \output_cr_a_ok + connect \mul_op__fn_unit \output_mul_op__fn_unit + connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 + connect \mul_op__imm_data__data \output_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 + connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 + connect \mul_op__insn \output_mul_op__insn + connect \mul_op__insn$13 \output_mul_op__insn$43 + connect \mul_op__insn_type \output_mul_op__insn_type + connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 + connect \mul_op__is_32bit \output_mul_op__is_32bit + connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 + connect \mul_op__is_signed \output_mul_op__is_signed + connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 + connect \mul_op__oe__oe \output_mul_op__oe__oe + connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 + connect \mul_op__oe__ok \output_mul_op__oe__ok + connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 + connect \mul_op__rc__ok \output_mul_op__rc__ok + connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 + connect \mul_op__rc__rc \output_mul_op__rc__rc + connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 + connect \mul_op__write_cr0 \output_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$31 + connect \o \output_o + connect \o$14 \output_o$44 + connect \o_ok \output_o_ok + connect \o_ok$15 \output_o_ok$45 + connect \xer_ov \output_xer_ov + connect \xer_ov$17 \output_xer_ov$47 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$18 \output_xer_so$48 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:155084.10-155087.4" + cell \p$98 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:153975.7-153975.20" + process $proc$libresoc.v:153975$8234 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:153984.13-153984.24" + process $proc$libresoc.v:153984$8235 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:153993.7-153993.21" + process $proc$libresoc.v:153993$8236 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:154280.14-154280.44" + process $proc$libresoc.v:154280$8237 + assign { } { } + assign $0\mul_op__fn_unit$3[12:0]$8238 13'0000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8238 + end + attribute \src "libresoc.v:154303.14-154303.63" + process $proc$libresoc.v:154303$8239 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8240 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8240 + end + attribute \src "libresoc.v:154312.7-154312.38" + process $proc$libresoc.v:154312$8241 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8242 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8242 + end + attribute \src "libresoc.v:154321.14-154321.39" + process $proc$libresoc.v:154321$8243 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8244 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8244 + end + attribute \src "libresoc.v:154478.13-154478.42" + process $proc$libresoc.v:154478$8245 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8246 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8246 + end + attribute \src "libresoc.v:154561.7-154561.35" + process $proc$libresoc.v:154561$8247 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8248 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8248 + end + attribute \src "libresoc.v:154570.7-154570.36" + process $proc$libresoc.v:154570$8249 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8250 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8250 + end + attribute \src "libresoc.v:154581.7-154581.32" + process $proc$libresoc.v:154581$8251 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8252 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8252 + end + attribute \src "libresoc.v:154590.7-154590.32" + process $proc$libresoc.v:154590$8253 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8254 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8254 + end + attribute \src "libresoc.v:154599.7-154599.32" + process $proc$libresoc.v:154599$8255 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8256 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8256 + end + attribute \src "libresoc.v:154606.7-154606.32" + process $proc$libresoc.v:154606$8257 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8258 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8258 + end + attribute \src "libresoc.v:154615.7-154615.36" + process $proc$libresoc.v:154615$8259 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8260 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8260 + end + attribute \src "libresoc.v:154624.13-154624.29" + process $proc$libresoc.v:154624$8261 + assign { } { } + assign $0\muxid$1[1:0]$8262 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8262 + end + attribute \src "libresoc.v:154645.14-154645.43" + process $proc$libresoc.v:154645$8263 + assign { } { } + assign $0\o$14[63:0]$8264 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$14 $0\o$14[63:0]$8264 + end + attribute \src "libresoc.v:154652.7-154652.18" + process $proc$libresoc.v:154652$8265 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:154920.7-154920.20" + process $proc$libresoc.v:154920$8266 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:154925.13-154925.26" + process $proc$libresoc.v:154925$8267 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:154932.7-154932.23" + process $proc$libresoc.v:154932$8268 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:154943.7-154943.25" + process $proc$libresoc.v:154943$8269 + assign { } { } + assign $0\xer_so$15[0:0]$8270 1'0 + sync always + sync init + update \xer_so$15 $0\xer_so$15[0:0]$8270 + end + attribute \src "libresoc.v:154950.7-154950.23" + process $proc$libresoc.v:154950$8271 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:154958.3-154959.37" + process $proc$libresoc.v:154958$8135 + assign { } { } + assign $0\xer_so$15[0:0]$8136 \xer_so$15$next + sync posedge \coresync_clk + update \xer_so$15 $0\xer_so$15[0:0]$8136 + end + attribute \src "libresoc.v:154960.3-154961.35" + process $proc$libresoc.v:154960$8137 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:154962.3-154963.29" + process $proc$libresoc.v:154962$8138 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:154964.3-154965.35" + process $proc$libresoc.v:154964$8139 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:154966.3-154967.25" + process $proc$libresoc.v:154966$8140 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:154968.3-154969.31" + process $proc$libresoc.v:154968$8141 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:154970.3-154971.27" + process $proc$libresoc.v:154970$8142 + assign { } { } + assign $0\o$14[63:0]$8143 \o$14$next + sync posedge \coresync_clk + update \o$14 $0\o$14[63:0]$8143 + end + attribute \src "libresoc.v:154972.3-154973.25" + process $proc$libresoc.v:154972$8144 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:154974.3-154975.57" + process $proc$libresoc.v:154974$8145 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8146 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8146 + end + attribute \src "libresoc.v:154976.3-154977.53" + process $proc$libresoc.v:154976$8147 + assign { } { } + assign $0\mul_op__fn_unit$3[12:0]$8148 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8148 + end + attribute \src "libresoc.v:154978.3-154979.67" + process $proc$libresoc.v:154978$8149 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8150 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8150 + end + attribute \src "libresoc.v:154980.3-154981.63" + process $proc$libresoc.v:154980$8151 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8152 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8152 + end + attribute \src "libresoc.v:154982.3-154983.51" + process $proc$libresoc.v:154982$8153 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8154 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8154 + end + attribute \src "libresoc.v:154984.3-154985.51" + process $proc$libresoc.v:154984$8155 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8156 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8156 + end + attribute \src "libresoc.v:154986.3-154987.51" + process $proc$libresoc.v:154986$8157 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8158 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8158 + end + attribute \src "libresoc.v:154988.3-154989.51" + process $proc$libresoc.v:154988$8159 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8160 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8160 + end + attribute \src "libresoc.v:154990.3-154991.59" + process $proc$libresoc.v:154990$8161 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8162 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8162 + end + attribute \src "libresoc.v:154992.3-154993.57" + process $proc$libresoc.v:154992$8163 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8164 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8164 + end + attribute \src "libresoc.v:154994.3-154995.59" + process $proc$libresoc.v:154994$8165 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8166 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8166 + end + attribute \src "libresoc.v:154996.3-154997.49" + process $proc$libresoc.v:154996$8167 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8168 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8168 + end + attribute \src "libresoc.v:154998.3-154999.33" + process $proc$libresoc.v:154998$8169 + assign { } { } + assign $0\muxid$1[1:0]$8170 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8170 + end + attribute \src "libresoc.v:155000.3-155001.29" + process $proc$libresoc.v:155000$8171 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:155088.3-155105.6" + process $proc$libresoc.v:155088$8172 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8173 $2\r_busy$next[0:0]$8175 + attribute \src "libresoc.v:155089.5-155089.29" + switch \initial + attribute \src "libresoc.v:155089.9-155089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8174 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8174 1'0 + case + assign $1\r_busy$next[0:0]$8174 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8175 1'0 + case + assign $2\r_busy$next[0:0]$8175 $1\r_busy$next[0:0]$8174 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8173 + end + attribute \src "libresoc.v:155106.3-155118.6" + process $proc$libresoc.v:155106$8176 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8177 $1\muxid$1$next[1:0]$8178 + attribute \src "libresoc.v:155107.5-155107.29" + switch \initial + attribute \src "libresoc.v:155107.9-155107.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8178 \muxid$58 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8178 \muxid$58 + case + assign $1\muxid$1$next[1:0]$8178 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8177 + end + attribute \src "libresoc.v:155119.3-155154.6" + process $proc$libresoc.v:155119$8179 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[12:0]$8180 $1\mul_op__fn_unit$3$next[12:0]$8192 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$8183 $1\mul_op__insn$13$next[31:0]$8195 + assign $0\mul_op__insn_type$2$next[6:0]$8184 $1\mul_op__insn_type$2$next[6:0]$8196 + assign $0\mul_op__is_32bit$11$next[0:0]$8185 $1\mul_op__is_32bit$11$next[0:0]$8197 + assign $0\mul_op__is_signed$12$next[0:0]$8186 $1\mul_op__is_signed$12$next[0:0]$8198 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$8191 $1\mul_op__write_cr0$10$next[0:0]$8203 + assign $0\mul_op__imm_data__data$4$next[63:0]$8181 $2\mul_op__imm_data__data$4$next[63:0]$8204 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8182 $2\mul_op__imm_data__ok$5$next[0:0]$8205 + assign $0\mul_op__oe__oe$8$next[0:0]$8187 $2\mul_op__oe__oe$8$next[0:0]$8206 + assign $0\mul_op__oe__ok$9$next[0:0]$8188 $2\mul_op__oe__ok$9$next[0:0]$8207 + assign $0\mul_op__rc__ok$7$next[0:0]$8189 $2\mul_op__rc__ok$7$next[0:0]$8208 + assign $0\mul_op__rc__rc$6$next[0:0]$8190 $2\mul_op__rc__rc$6$next[0:0]$8209 + attribute \src "libresoc.v:155120.5-155120.29" + switch \initial + attribute \src "libresoc.v:155120.9-155120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8195 $1\mul_op__is_signed$12$next[0:0]$8198 $1\mul_op__is_32bit$11$next[0:0]$8197 $1\mul_op__write_cr0$10$next[0:0]$8203 $1\mul_op__oe__ok$9$next[0:0]$8200 $1\mul_op__oe__oe$8$next[0:0]$8199 $1\mul_op__rc__ok$7$next[0:0]$8201 $1\mul_op__rc__rc$6$next[0:0]$8202 $1\mul_op__imm_data__ok$5$next[0:0]$8194 $1\mul_op__imm_data__data$4$next[63:0]$8193 $1\mul_op__fn_unit$3$next[12:0]$8192 $1\mul_op__insn_type$2$next[6:0]$8196 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8195 $1\mul_op__is_signed$12$next[0:0]$8198 $1\mul_op__is_32bit$11$next[0:0]$8197 $1\mul_op__write_cr0$10$next[0:0]$8203 $1\mul_op__oe__ok$9$next[0:0]$8200 $1\mul_op__oe__oe$8$next[0:0]$8199 $1\mul_op__rc__ok$7$next[0:0]$8201 $1\mul_op__rc__rc$6$next[0:0]$8202 $1\mul_op__imm_data__ok$5$next[0:0]$8194 $1\mul_op__imm_data__data$4$next[63:0]$8193 $1\mul_op__fn_unit$3$next[12:0]$8192 $1\mul_op__insn_type$2$next[6:0]$8196 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + case + assign $1\mul_op__fn_unit$3$next[12:0]$8192 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8193 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8194 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8195 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8196 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8197 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8198 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8199 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8200 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8201 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8202 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8203 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$8204 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8205 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8209 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8208 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8206 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8207 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$8204 $1\mul_op__imm_data__data$4$next[63:0]$8193 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8205 $1\mul_op__imm_data__ok$5$next[0:0]$8194 + assign $2\mul_op__oe__oe$8$next[0:0]$8206 $1\mul_op__oe__oe$8$next[0:0]$8199 + assign $2\mul_op__oe__ok$9$next[0:0]$8207 $1\mul_op__oe__ok$9$next[0:0]$8200 + assign $2\mul_op__rc__ok$7$next[0:0]$8208 $1\mul_op__rc__ok$7$next[0:0]$8201 + assign $2\mul_op__rc__rc$6$next[0:0]$8209 $1\mul_op__rc__rc$6$next[0:0]$8202 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$8180 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8181 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8182 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8183 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8184 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8185 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8186 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8187 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8188 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8189 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8190 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8191 + end + attribute \src "libresoc.v:155155.3-155173.6" + process $proc$libresoc.v:155155$8210 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$14$next[63:0]$8212 $1\o$14$next[63:0]$8214 + assign $0\o_ok$next[0:0]$8211 $2\o_ok$next[0:0]$8215 + attribute \src "libresoc.v:155156.5-155156.29" + switch \initial + attribute \src "libresoc.v:155156.9-155156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8213 $1\o$14$next[63:0]$8214 } { \o_ok$72 \o$71 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8213 $1\o$14$next[63:0]$8214 } { \o_ok$72 \o$71 } + case + assign $1\o_ok$next[0:0]$8213 \o_ok + assign $1\o$14$next[63:0]$8214 \o$14 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8215 1'0 + case + assign $2\o_ok$next[0:0]$8215 $1\o_ok$next[0:0]$8213 + end + sync always + update \o_ok$next $0\o_ok$next[0:0]$8211 + update \o$14$next $0\o$14$next[63:0]$8212 + end + attribute \src "libresoc.v:155174.3-155192.6" + process $proc$libresoc.v:155174$8216 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8217 $1\cr_a$next[3:0]$8219 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8218 $2\cr_a_ok$next[0:0]$8221 + attribute \src "libresoc.v:155175.5-155175.29" + switch \initial + attribute \src "libresoc.v:155175.9-155175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8220 $1\cr_a$next[3:0]$8219 } { \cr_a_ok$74 \cr_a$73 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8220 $1\cr_a$next[3:0]$8219 } { \cr_a_ok$74 \cr_a$73 } + case + assign $1\cr_a$next[3:0]$8219 \cr_a + assign $1\cr_a_ok$next[0:0]$8220 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8221 1'0 + case + assign $2\cr_a_ok$next[0:0]$8221 $1\cr_a_ok$next[0:0]$8220 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8217 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8218 + end + attribute \src "libresoc.v:155193.3-155211.6" + process $proc$libresoc.v:155193$8222 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$8223 $1\xer_ov$next[1:0]$8225 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$8224 $2\xer_ov_ok$next[0:0]$8227 + attribute \src "libresoc.v:155194.5-155194.29" + switch \initial + attribute \src "libresoc.v:155194.9-155194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8226 $1\xer_ov$next[1:0]$8225 } { \xer_ov_ok$76 \xer_ov$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8226 $1\xer_ov$next[1:0]$8225 } { \xer_ov_ok$76 \xer_ov$75 } + case + assign $1\xer_ov$next[1:0]$8225 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8226 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8227 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8227 $1\xer_ov_ok$next[0:0]$8226 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$8223 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8224 + end + attribute \src "libresoc.v:155212.3-155230.6" + process $proc$libresoc.v:155212$8228 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$15$next[0:0]$8230 $1\xer_so$15$next[0:0]$8232 + assign $0\xer_so_ok$next[0:0]$8229 $2\xer_so_ok$next[0:0]$8233 + attribute \src "libresoc.v:155213.5-155213.29" + switch \initial + attribute \src "libresoc.v:155213.9-155213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8231 $1\xer_so$15$next[0:0]$8232 } { \xer_so_ok$78 \xer_so$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8231 $1\xer_so$15$next[0:0]$8232 } { \xer_so_ok$78 \xer_so$77 } + case + assign $1\xer_so_ok$next[0:0]$8231 \xer_so_ok + assign $1\xer_so$15$next[0:0]$8232 \xer_so$15 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8233 1'0 + case + assign $2\xer_so_ok$next[0:0]$8233 $1\xer_so_ok$next[0:0]$8231 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8229 + update \xer_so$15$next $0\xer_so$15$next[0:0]$8230 + end + connect \$56 $and$libresoc.v:154957$8134_Y + connect \cr_a$51 4'0000 + connect \cr_a_ok$52 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } + connect { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } + connect { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } + connect { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } + connect \muxid$58 \output_muxid$31 + connect \p_valid_i_p_ready_o \$56 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$55 \p_valid_i + connect { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } + connect { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } + connect { \cr_a_ok$50 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } + connect { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__oe__ok \output_mul_op__oe__oe \output_mul_op__rc__ok \output_mul_op__rc__rc \output_mul_op__imm_data__ok \output_mul_op__imm_data__data \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } + connect \output_muxid \mul3_muxid$16 + connect \neg_res32$49 \neg_res32 + connect \mul3_neg_res \neg_res + connect \mul3_xer_so \xer_so + connect \mul3_o \o + connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul3_muxid \muxid +end +attribute \src "libresoc.v:155260.1-155271.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" +attribute \generator "nMigen" +module \n + attribute \src "libresoc.v:155269.17-155269.111" + wire $and$libresoc.v:155269$8272_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155269$8272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B \$36 - connect \Y $and$libresoc.v:162356$8531_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155269$8272_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:162352$8527 + connect \$1 $and$libresoc.v:155269$8272_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155275.1-155286.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" +attribute \generator "nMigen" +module \n$109 + attribute \src "libresoc.v:155284.17-155284.111" + wire $and$libresoc.v:155284$8273_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155284$8273 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:162352$8527_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155284$8273_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:162353$8528 + connect \$1 $and$libresoc.v:155284$8273_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155290.1-155301.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" +attribute \generator "nMigen" +module \n$112 + attribute \src "libresoc.v:155299.17-155299.111" + wire $and$libresoc.v:155299$8274_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155299$8274 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001100 - connect \Y $eq$libresoc.v:162353$8528_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155299$8274_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:162350$8523 + connect \$1 $and$libresoc.v:155299$8274_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155305.1-155316.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" +attribute \generator "nMigen" +module \n$117 + attribute \src "libresoc.v:155314.17-155314.111" + wire $and$libresoc.v:155314$8275_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155314$8275 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \$25 - connect \Y $extend$libresoc.v:162350$8523_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155314$8275_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:162351$8525 + connect \$1 $and$libresoc.v:155314$8275_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155320.1-155331.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" +attribute \generator "nMigen" +module \n$18 + attribute \src "libresoc.v:155329.17-155329.111" + wire $and$libresoc.v:155329$8276_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155329$8276 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $extend$libresoc.v:162351$8525_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155329$8276_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:162349$8522 + connect \$1 $and$libresoc.v:155329$8276_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155335.1-155346.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" +attribute \generator "nMigen" +module \n$2 + attribute \src "libresoc.v:155344.17-155344.111" + wire $and$libresoc.v:155344$8277_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155344$8277 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $not$libresoc.v:162349$8522_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155344$8277_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:162355$8530 + connect \$1 $and$libresoc.v:155344$8277_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155350.1-155361.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" +attribute \generator "nMigen" +module \n$21 + attribute \src "libresoc.v:155359.17-155359.111" + wire $and$libresoc.v:155359$8278_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155359$8278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $not$libresoc.v:162355$8530_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155359$8278_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:162358$8533 + connect \$1 $and$libresoc.v:155359$8278_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155365.1-155376.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" +attribute \generator "nMigen" +module \n$31 + attribute \src "libresoc.v:155374.17-155374.111" + wire $and$libresoc.v:155374$8279_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155374$8279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $not$libresoc.v:162358$8533_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155374$8279_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:162357$8532 + connect \$1 $and$libresoc.v:155374$8279_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155380.1-155391.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" +attribute \generator "nMigen" +module \n$34 + attribute \src "libresoc.v:155389.17-155389.111" + wire $and$libresoc.v:155389$8280_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155389$8280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $or$libresoc.v:162357$8532_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155389$8280_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:162350$8524 + connect \$1 $and$libresoc.v:155389$8280_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155395.1-155406.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" +attribute \generator "nMigen" +module \n$37 + attribute \src "libresoc.v:155404.17-155404.111" + wire $and$libresoc.v:155404$8281_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155404$8281 parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:162350$8523_Y - connect \Y $pos$libresoc.v:162350$8524_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155404$8281_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:162351$8526 + connect \$1 $and$libresoc.v:155404$8281_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155410.1-155421.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" +attribute \generator "nMigen" +module \n$4 + attribute \src "libresoc.v:155419.17-155419.111" + wire $and$libresoc.v:155419$8282_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155419$8282 parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:162351$8525_Y - connect \Y $pos$libresoc.v:162351$8526_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155419$8282_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:162354$8529 + connect \$1 $and$libresoc.v:155419$8282_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155425.1-155436.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" +attribute \generator "nMigen" +module \n$47 + attribute \src "libresoc.v:155434.17-155434.111" + wire $and$libresoc.v:155434$8283_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155434$8283 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \target - connect \Y $reduce_or$libresoc.v:162354$8529_Y - end - attribute \src "libresoc.v:162034.7-162034.20" - process $proc$libresoc.v:162034$8538 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155434$8283_Y end - attribute \src "libresoc.v:162359.3-162370.6" - process $proc$libresoc.v:162359$8534 - assign { } { } - assign $0\o$23[64:0]$8535 $1\o$23[64:0]$8536 - attribute \src "libresoc.v:162360.5-162360.29" - switch \initial - attribute \src "libresoc.v:162360.9-162360.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" - switch \logical_op__invert_out - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o$23[64:0]$8536 \$24 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\o$23[64:0]$8536 \$28 - end - sync always - update \o$23 $0\o$23[64:0]$8535 + connect \$1 $and$libresoc.v:155434$8283_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155440.1-155451.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" +attribute \generator "nMigen" +module \n$49 + attribute \src "libresoc.v:155449.17-155449.111" + wire $and$libresoc.v:155449$8284_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155449$8284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155449$8284_Y end - attribute \src "libresoc.v:162371.3-162382.6" - process $proc$libresoc.v:162371$8537 - assign { } { } - assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:162372.5-162372.29" - switch \initial - attribute \src "libresoc.v:162372.9-162372.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch \$40 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cr0[3:0] \cr_a - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cr0[3:0] { \is_negative \is_positive \$42 \xer_so } - end - sync always - update \cr0 $0\cr0[3:0] + connect \$1 $and$libresoc.v:155449$8284_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155455.1-155466.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" +attribute \generator "nMigen" +module \n$53 + attribute \src "libresoc.v:155464.17-155464.111" + wire $and$libresoc.v:155464$8285_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155464$8285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155464$8285_Y end - connect \$25 $not$libresoc.v:162349$8522_Y - connect \$24 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\enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 25 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 43 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 44 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire \oe$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - wire \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 47 \xer_ov$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 48 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 23 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 49 \xer_so$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 50 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:162742$8539 +module \n$6 + attribute \src "libresoc.v:155479.17-155479.111" + wire $and$libresoc.v:155479$8286_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155479$8286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__oe__oe - connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:162742$8539_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155479$8286_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:162750$8549 + connect \$1 $and$libresoc.v:155479$8286_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155485.1-155496.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" +attribute \generator "nMigen" +module \n$63 + attribute \src "libresoc.v:155494.17-155494.111" + wire $and$libresoc.v:155494$8287_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155494$8287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B \$40 - connect \Y $and$libresoc.v:162750$8549_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155494$8287_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:162753$8552 + connect \$1 $and$libresoc.v:155494$8287_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155500.1-155511.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" +attribute \generator "nMigen" +module \n$66 + attribute \src "libresoc.v:155509.17-155509.111" + wire $and$libresoc.v:155509$8288_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155509$8288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__oe__oe - connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:162753$8552_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155509$8288_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:162746$8545 + connect \$1 $and$libresoc.v:155509$8288_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155515.1-155526.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" +attribute \generator "nMigen" +module \n$75 + attribute \src "libresoc.v:155524.17-155524.111" + wire $and$libresoc.v:155524$8289_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155524$8289 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:162746$8545_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155524$8289_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:162747$8546 + connect \$1 $and$libresoc.v:155524$8289_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155530.1-155541.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" +attribute \generator "nMigen" +module \n$77 + attribute \src "libresoc.v:155539.17-155539.111" + wire $and$libresoc.v:155539$8290_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155539$8290 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001100 - connect \Y $eq$libresoc.v:162747$8546_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155539$8290_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:162744$8541 + connect \$1 $and$libresoc.v:155539$8290_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155545.1-155556.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" +attribute \generator "nMigen" +module \n$8 + attribute \src "libresoc.v:155554.17-155554.111" + wire $and$libresoc.v:155554$8291_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155554$8291 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \$29 - connect \Y $extend$libresoc.v:162744$8541_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155554$8291_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:162745$8543 + connect \$1 $and$libresoc.v:155554$8291_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155560.1-155571.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" +attribute \generator "nMigen" +module \n$80 + attribute \src "libresoc.v:155569.17-155569.111" + wire $and$libresoc.v:155569$8292_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155569$8292 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $extend$libresoc.v:162745$8543_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155569$8292_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:162743$8540 + connect \$1 $and$libresoc.v:155569$8292_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155575.1-155586.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" +attribute \generator "nMigen" +module \n$82 + attribute \src "libresoc.v:155584.17-155584.111" + wire $and$libresoc.v:155584$8293_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155584$8293 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $not$libresoc.v:162743$8540_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155584$8293_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:162749$8548 + connect \$1 $and$libresoc.v:155584$8293_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155590.1-155601.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" +attribute \generator "nMigen" +module \n$92 + attribute \src "libresoc.v:155599.17-155599.111" + wire $and$libresoc.v:155599$8294_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155599$8294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $not$libresoc.v:162749$8548_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155599$8294_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:162752$8551 + connect \$1 $and$libresoc.v:155599$8294_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155605.1-155616.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" +attribute \generator "nMigen" +module \n$94 + attribute \src "libresoc.v:155614.17-155614.111" + wire $and$libresoc.v:155614$8295_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155614$8295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $not$libresoc.v:162752$8551_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155614$8295_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:162751$8550 + connect \$1 $and$libresoc.v:155614$8295_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155620.1-155631.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" +attribute \generator "nMigen" +module \n$97 + attribute \src "libresoc.v:155629.17-155629.111" + wire $and$libresoc.v:155629$8296_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155629$8296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $or$libresoc.v:162751$8550_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155629$8296_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:162754$8553 + connect \$1 $and$libresoc.v:155629$8296_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155635.1-155646.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" +attribute \generator "nMigen" +module \n$99 + attribute \src "libresoc.v:155644.17-155644.111" + wire $and$libresoc.v:155644$8297_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:155644$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $or$libresoc.v:162754$8553_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:162744$8542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:162744$8541_Y - connect \Y $pos$libresoc.v:162744$8542_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:162745$8544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:162745$8543_Y - connect \Y $pos$libresoc.v:162745$8544_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:162748$8547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $reduce_or$libresoc.v:162748$8547_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:155644$8297_Y end - attribute \src "libresoc.v:162401.7-162401.20" - process $proc$libresoc.v:162401$8567 + connect \$1 $and$libresoc.v:155644$8297_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:155650.1-155811.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.o2_svdec" +attribute \generator "nMigen" +module \o2_svdec + attribute \src "libresoc.v:155745.3-155761.6" + wire width 3 $0\extra3_idx0[2:0] + attribute \src "libresoc.v:155762.3-155778.6" + wire width 3 $0\extra3_idx1[2:0] + attribute \src "libresoc.v:155779.3-155795.6" + wire width 3 $0\extra3_idx2[2:0] + attribute \src "libresoc.v:155651.7-155651.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:155796.3-155807.6" + wire width 7 $0\reg_out[6:0] + attribute \src "libresoc.v:155686.3-155744.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:155745.3-155761.6" + wire width 3 $1\extra3_idx0[2:0] + attribute \src "libresoc.v:155762.3-155778.6" + wire width 3 $1\extra3_idx1[2:0] + attribute \src "libresoc.v:155779.3-155795.6" + wire width 3 $1\extra3_idx2[2:0] + attribute \src "libresoc.v:155796.3-155807.6" + wire width 7 $1\reg_out[6:0] + attribute \src "libresoc.v:155686.3-155744.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:155745.3-155761.6" + wire width 3 $2\extra3_idx0[2:0] + attribute \src "libresoc.v:155762.3-155778.6" + wire width 3 $2\extra3_idx1[2:0] + attribute \src "libresoc.v:155779.3-155795.6" + wire width 3 $2\extra3_idx2[2:0] + attribute \src "libresoc.v:155686.3-155744.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:155686.3-155744.6" + wire width 3 $3\spec[2:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" + wire width 2 input 1 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" + wire width 9 input 5 \extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57" + wire width 3 \extra3_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60" + wire width 3 \extra3_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63" + wire width 3 \extra3_idx2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" + wire width 3 \idx + attribute \src "libresoc.v:155651.7-155651.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85" + wire output 3 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83" + wire width 5 input 2 \reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84" + wire width 7 output 4 \reg_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25" + wire width 3 \spec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:101" + wire width 2 \spec_aug + attribute \src "libresoc.v:155651.7-155651.20" + process $proc$libresoc.v:155651$8303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:162755.3-162766.6" - process $proc$libresoc.v:162755$8554 + attribute \src "libresoc.v:155686.3-155744.6" + process $proc$libresoc.v:155686$8298 assign { } { } - assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:162756.5-162756.29" + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:155687.5-155687.29" switch \initial - attribute \src "libresoc.v:162756.9-162756.17" + attribute \src "libresoc.v:155687.9-155687.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - switch \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\so[0:0] \xer_so$24 + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end attribute \src "libresoc.v:0.0-0.0" - case + case 2'10 assign { } { } - assign $1\so[0:0] \xer_so + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra3_idx0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra3_idx1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra3_idx2 + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 end sync always - update \so $0\so[0:0] + update \spec $0\spec[2:0] end - attribute \src "libresoc.v:162767.3-162778.6" - process $proc$libresoc.v:162767$8555 + attribute \src "libresoc.v:155745.3-155761.6" + process $proc$libresoc.v:155745$8299 assign { } { } - assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:162768.5-162768.29" + assign { } { } + assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0] + attribute \src "libresoc.v:155746.5-155746.29" switch \initial - attribute \src "libresoc.v:162768.9-162768.17" + attribute \src "libresoc.v:155746.9-155746.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $1\cr0[3:0] \cr_a + assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\extra3_idx0[2:0] \extra [8:6] + case + assign $2\extra3_idx0[2:0] 3'000 + end + case + assign $1\extra3_idx0[2:0] 3'000 + end + sync always + update \extra3_idx0 $0\extra3_idx0[2:0] + end + attribute \src "libresoc.v:155762.3-155778.6" + process $proc$libresoc.v:155762$8300 + assign { } { } + assign { } { } + assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0] + attribute \src "libresoc.v:155763.5-155763.29" + switch \initial + attribute \src "libresoc.v:155763.9-155763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\extra3_idx1[2:0] \extra [5:3] + case + assign $2\extra3_idx1[2:0] 3'000 + end + case + assign $1\extra3_idx1[2:0] 3'000 + end + sync always + update \extra3_idx1 $0\extra3_idx1[2:0] + end + attribute \src "libresoc.v:155779.3-155795.6" + process $proc$libresoc.v:155779$8301 + assign { } { } + assign { } { } + assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0] + attribute \src "libresoc.v:155780.5-155780.29" + switch \initial + attribute \src "libresoc.v:155780.9-155780.17" + case 1'1 case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } - assign $1\cr0[3:0] { \is_negative \is_positive \$46 \so } + assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\extra3_idx2[2:0] \extra [2:0] + case + assign $2\extra3_idx2[2:0] 3'000 + end + case + assign $1\extra3_idx2[2:0] 3'000 end sync always - update \cr0 $0\cr0[3:0] + update \extra3_idx2 $0\extra3_idx2[2:0] end - attribute \src "libresoc.v:162779.3-162790.6" - process $proc$libresoc.v:162779$8556 + attribute \src "libresoc.v:155796.3-155807.6" + process $proc$libresoc.v:155796$8302 assign { } { } - assign $0\o$27[64:0]$8557 $1\o$27[64:0]$8558 - attribute \src "libresoc.v:162780.5-162780.29" + assign $0\reg_out[6:0] $1\reg_out[6:0] + attribute \src "libresoc.v:155797.5-155797.29" switch \initial - attribute \src "libresoc.v:162780.9-162780.17" + attribute \src "libresoc.v:155797.9-155797.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" - switch \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:105" + switch \isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$27[64:0]$8558 \$28 + assign $1\reg_out[6:0] { \reg_in \spec_aug } attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$27[64:0]$8558 \$32 + assign $1\reg_out[6:0] { \spec_aug \reg_in } end sync always - update \o$27 $0\o$27[64:0]$8557 + update \reg_out $0\reg_out[6:0] + end + connect \idx 3'000 + connect \spec_aug \spec [1:0] + connect \isvec \spec [2] +end +attribute \src "libresoc.v:155815.1-155975.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.o_svdec" +attribute \generator "nMigen" +module \o_svdec + attribute \src "libresoc.v:155910.3-155926.6" + wire width 3 $0\extra3_idx0[2:0] + attribute \src "libresoc.v:155927.3-155943.6" + wire width 3 $0\extra3_idx1[2:0] + attribute \src "libresoc.v:155944.3-155960.6" + wire width 3 $0\extra3_idx2[2:0] + attribute \src "libresoc.v:155816.7-155816.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:155961.3-155972.6" + wire width 7 $0\reg_out[6:0] + attribute \src "libresoc.v:155851.3-155909.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:155910.3-155926.6" + wire width 3 $1\extra3_idx0[2:0] + attribute \src "libresoc.v:155927.3-155943.6" + wire width 3 $1\extra3_idx1[2:0] + attribute \src "libresoc.v:155944.3-155960.6" + wire width 3 $1\extra3_idx2[2:0] + attribute \src "libresoc.v:155961.3-155972.6" + wire width 7 $1\reg_out[6:0] + attribute \src "libresoc.v:155851.3-155909.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:155910.3-155926.6" + wire width 3 $2\extra3_idx0[2:0] + attribute \src "libresoc.v:155927.3-155943.6" + wire width 3 $2\extra3_idx1[2:0] + attribute \src "libresoc.v:155944.3-155960.6" + wire width 3 $2\extra3_idx2[2:0] + attribute \src "libresoc.v:155851.3-155909.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:155851.3-155909.6" + wire width 3 $3\spec[2:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:23" + wire width 2 input 1 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:22" + wire width 9 input 6 \extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:57" + wire width 3 \extra3_idx0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:60" + wire width 3 \extra3_idx1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:63" + wire width 3 \extra3_idx2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:24" + wire width 3 input 5 \idx + attribute \src "libresoc.v:155816.7-155816.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:85" + wire output 3 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:83" + wire width 5 input 2 \reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:84" + wire width 7 output 4 \reg_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:25" + wire width 3 \spec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:101" + wire width 2 \spec_aug + attribute \src "libresoc.v:155816.7-155816.20" + process $proc$libresoc.v:155816$8309 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:162791.3-162800.6" - process $proc$libresoc.v:162791$8559 + attribute \src "libresoc.v:155851.3-155909.6" + process $proc$libresoc.v:155851$8304 assign { } { } assign { } { } - assign $0\xer_so$24[0:0]$8560 $1\xer_so$24[0:0]$8561 - attribute \src "libresoc.v:162792.5-162792.29" + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:155852.5-155852.29" switch \initial - attribute \src "libresoc.v:162792.9-162792.17" + attribute \src "libresoc.v:155852.9-155852.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:40" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } - assign $1\xer_so$24[0:0]$8561 \$51 + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra3_idx0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra3_idx1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra3_idx2 + case + assign $3\spec[2:0] 3'000 + end case - assign $1\xer_so$24[0:0]$8561 1'0 + assign $1\spec[2:0] 3'000 end sync always - update \xer_so$24 $0\xer_so$24[0:0]$8560 + update \spec $0\spec[2:0] end - attribute \src "libresoc.v:162801.3-162810.6" - process $proc$libresoc.v:162801$8562 + attribute \src "libresoc.v:155910.3-155926.6" + process $proc$libresoc.v:155910$8305 assign { } { } assign { } { } - assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:162802.5-162802.29" + assign $0\extra3_idx0[2:0] $1\extra3_idx0[2:0] + attribute \src "libresoc.v:155911.5-155911.29" switch \initial - attribute \src "libresoc.v:162802.9-162802.17" + attribute \src "libresoc.v:155911.9-155911.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx0[2:0] $2\extra3_idx0[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\extra3_idx0[2:0] \extra [8:6] + case + assign $2\extra3_idx0[2:0] 3'000 + end + case + assign $1\extra3_idx0[2:0] 3'000 + end + sync always + update \extra3_idx0 $0\extra3_idx0[2:0] + end + attribute \src "libresoc.v:155927.3-155943.6" + process $proc$libresoc.v:155927$8306 + assign { } { } + assign { } { } + assign $0\extra3_idx1[2:0] $1\extra3_idx1[2:0] + attribute \src "libresoc.v:155928.5-155928.29" + switch \initial + attribute \src "libresoc.v:155928.9-155928.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } - assign $1\xer_so_ok[0:0] 1'1 + assign $1\extra3_idx1[2:0] $2\extra3_idx1[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\extra3_idx1[2:0] \extra [5:3] + case + assign $2\extra3_idx1[2:0] 3'000 + end case - assign $1\xer_so_ok[0:0] 1'0 + assign $1\extra3_idx1[2:0] 3'000 end sync always - update \xer_so_ok $0\xer_so_ok[0:0] + update \extra3_idx1 $0\extra3_idx1[2:0] end - attribute \src "libresoc.v:162811.3-162820.6" - process $proc$libresoc.v:162811$8563 + attribute \src "libresoc.v:155944.3-155960.6" + process $proc$libresoc.v:155944$8307 assign { } { } assign { } { } - assign $0\xer_ov$23[1:0]$8564 $1\xer_ov$23[1:0]$8565 - attribute \src "libresoc.v:162812.5-162812.29" + assign $0\extra3_idx2[2:0] $1\extra3_idx2[2:0] + attribute \src "libresoc.v:155945.5-155945.29" switch \initial - attribute \src "libresoc.v:162812.9-162812.17" + attribute \src "libresoc.v:155945.9-155945.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:37" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\extra3_idx2[2:0] $2\extra3_idx2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:55" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\extra3_idx2[2:0] \extra [2:0] + case + assign $2\extra3_idx2[2:0] 3'000 + end + case + assign $1\extra3_idx2[2:0] 3'000 + end + sync always + update \extra3_idx2 $0\extra3_idx2[2:0] + end + attribute \src "libresoc.v:155961.3-155972.6" + process $proc$libresoc.v:155961$8308 + assign { } { } + assign $0\reg_out[6:0] $1\reg_out[6:0] + attribute \src "libresoc.v:155962.5-155962.29" + switch \initial + attribute \src "libresoc.v:155962.9-155962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_extra.py:105" + switch \isvec attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$23[1:0]$8565 \xer_ov + assign $1\reg_out[6:0] { \reg_in \spec_aug } + attribute \src "libresoc.v:0.0-0.0" case - assign $1\xer_ov$23[1:0]$8565 2'00 + assign { } { } + assign $1\reg_out[6:0] { \spec_aug \reg_in } end sync always - update \xer_ov$23 $0\xer_ov$23[1:0]$8564 + update \reg_out $0\reg_out[6:0] + end + connect \spec_aug \spec [1:0] + connect \isvec \spec [2] +end +attribute \src "libresoc.v:155979.1-156037.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" +attribute \generator "nMigen" +module \opc_l + attribute \src "libresoc.v:155980.7-155980.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156025.3-156033.6" + wire $0\q_int$next[0:0]$8320 + attribute \src "libresoc.v:156023.3-156024.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:156025.3-156033.6" + wire $1\q_int$next[0:0]$8321 + attribute \src "libresoc.v:156002.7-156002.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:156015.17-156015.96" + wire $and$libresoc.v:156015$8310_Y + attribute \src "libresoc.v:156020.17-156020.96" + wire $and$libresoc.v:156020$8315_Y + attribute \src "libresoc.v:156017.18-156017.93" + wire $not$libresoc.v:156017$8312_Y + attribute \src "libresoc.v:156019.17-156019.92" + wire $not$libresoc.v:156019$8314_Y + attribute \src "libresoc.v:156022.17-156022.92" + wire $not$libresoc.v:156022$8317_Y + attribute \src "libresoc.v:156016.18-156016.98" + wire $or$libresoc.v:156016$8311_Y + attribute \src "libresoc.v:156018.18-156018.99" + wire $or$libresoc.v:156018$8313_Y + attribute \src "libresoc.v:156021.17-156021.97" + wire $or$libresoc.v:156021$8316_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:155980.7-155980.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156015$8310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:156015$8310_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156020$8315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:156020$8315_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156017$8312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:156017$8312_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156019$8314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156019$8314_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156022$8317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156022$8317_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156016$8311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:156016$8311_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156018$8313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:156018$8313_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156021$8316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:156021$8316_Y + end + attribute \src "libresoc.v:155980.7-155980.20" + process $proc$libresoc.v:155980$8322 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:162821.3-162830.6" - process $proc$libresoc.v:162821$8566 + attribute \src "libresoc.v:156002.7-156002.19" + process $proc$libresoc.v:156002$8323 assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:156023.3-156024.27" + process $proc$libresoc.v:156023$8318 assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:162822.5-162822.29" + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:156025.3-156033.6" + process $proc$libresoc.v:156025$8319 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8320 $1\q_int$next[0:0]$8321 + attribute \src "libresoc.v:156026.5-156026.29" switch \initial - attribute \src "libresoc.v:162822.9-162822.17" + attribute \src "libresoc.v:156026.9-156026.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 + assign $1\q_int$next[0:0]$8321 1'0 case - assign $1\xer_ov_ok[0:0] 1'0 + assign $1\q_int$next[0:0]$8321 \$5 end sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] + update \q_int$next $0\q_int$next[0:0]$8320 end - connect \$25 $and$libresoc.v:162742$8539_Y - connect \$29 $not$libresoc.v:162743$8540_Y - connect \$28 $pos$libresoc.v:162744$8542_Y - connect \$32 $pos$libresoc.v:162745$8544_Y - connect \$34 $eq$libresoc.v:162746$8545_Y - connect \$36 $eq$libresoc.v:162747$8546_Y - connect \$38 $reduce_or$libresoc.v:162748$8547_Y - connect \$40 $not$libresoc.v:162749$8548_Y - connect \$42 $and$libresoc.v:162750$8549_Y - connect \$44 $or$libresoc.v:162751$8550_Y - connect \$46 $not$libresoc.v:162752$8551_Y - connect \$49 $and$libresoc.v:162753$8552_Y - connect \$51 $or$libresoc.v:162754$8553_Y - connect \oe$48 \$49 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \cr_a_ok \logical_op__write_cr0 - connect \cr_a$22 \cr0 - connect \o_ok$21 \o_ok - connect \o$20 \o$27 [63:0] - connect \is_positive \$42 - connect \is_negative \msb_test - connect \is_nzero \$38 - connect \msb_test \target [63] - connect \is_cmpeqb \$36 - connect \is_cmp \$34 - connect \target \o$27 [63:0] - connect \oe \$25 + connect \$9 $and$libresoc.v:156015$8310_Y + connect \$11 $or$libresoc.v:156016$8311_Y + connect \$13 $not$libresoc.v:156017$8312_Y + connect \$15 $or$libresoc.v:156018$8313_Y + connect \$1 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"OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 28 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 27 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 46 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 47 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" - wire \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" - wire width 65 \quotient_65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" - wire \quotient_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 input 25 \quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 input 26 \remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" - wire width 64 \remainder_64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" - wire \remainder_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - wire width 32 \remainder_s32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" - wire width 64 \remainder_s32_as_s64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 49 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 50 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$libresoc.v:163200$8581 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156077$8324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__is_signed - connect \B \$38 - connect \Y $and$libresoc.v:163200$8581_Y + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:156077$8324_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$libresoc.v:163192$8569 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156082$8329 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \quotient_root - connect \Y $extend$libresoc.v:163192$8569_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:156082$8329_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$libresoc.v:163193$8571 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156079$8326 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \quotient_root - connect \Y $extend$libresoc.v:163193$8571_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:156079$8326_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$libresoc.v:163195$8574 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156081$8328 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:163195$8574_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156081$8328_Y end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:163196$8576 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156084$8331 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:163196$8576_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156084$8331_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $extend$libresoc.v:163204$8585 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156078$8325 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:163204$8585_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:156078$8325_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $extend$libresoc.v:163205$8587 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156080$8327 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:163205$8587_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:156080$8327_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $extend$libresoc.v:163206$8589 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156083$8330 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:163206$8589_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:156083$8330_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $extend$libresoc.v:163207$8591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:163207$8591_Y + attribute \src "libresoc.v:156042.7-156042.20" + process $proc$libresoc.v:156042$8336 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $extend$libresoc.v:163208$8593 + attribute \src "libresoc.v:156064.7-156064.19" + process $proc$libresoc.v:156064$8337 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:156085.3-156086.27" + process $proc$libresoc.v:156085$8332 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:156087.3-156095.6" + process $proc$libresoc.v:156087$8333 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8334 $1\q_int$next[0:0]$8335 + attribute \src "libresoc.v:156088.5-156088.29" + switch \initial + attribute \src "libresoc.v:156088.9-156088.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8335 1'0 + case + assign $1\q_int$next[0:0]$8335 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8334 + end + connect \$9 $and$libresoc.v:156077$8324_Y + connect \$11 $or$libresoc.v:156078$8325_Y + connect \$13 $not$libresoc.v:156079$8326_Y + connect \$15 $or$libresoc.v:156080$8327_Y + connect \$1 $not$libresoc.v:156081$8328_Y + connect \$3 $and$libresoc.v:156082$8329_Y + connect \$5 $or$libresoc.v:156083$8330_Y + connect \$7 $not$libresoc.v:156084$8331_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:156103.1-156161.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" +attribute \generator "nMigen" +module \opc_l$11 + attribute \src "libresoc.v:156104.7-156104.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156149.3-156157.6" + wire $0\q_int$next[0:0]$8348 + attribute \src "libresoc.v:156147.3-156148.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:156149.3-156157.6" + wire $1\q_int$next[0:0]$8349 + attribute \src "libresoc.v:156126.7-156126.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:156139.17-156139.96" + wire $and$libresoc.v:156139$8338_Y + attribute \src "libresoc.v:156144.17-156144.96" + wire $and$libresoc.v:156144$8343_Y + attribute \src "libresoc.v:156141.18-156141.93" + wire $not$libresoc.v:156141$8340_Y + attribute \src "libresoc.v:156143.17-156143.92" + wire $not$libresoc.v:156143$8342_Y + attribute \src "libresoc.v:156146.17-156146.92" + wire $not$libresoc.v:156146$8345_Y + attribute \src "libresoc.v:156140.18-156140.98" + wire $or$libresoc.v:156140$8339_Y + attribute \src "libresoc.v:156142.18-156142.99" + wire $or$libresoc.v:156142$8341_Y + attribute \src "libresoc.v:156145.17-156145.97" + wire $or$libresoc.v:156145$8344_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:156104.7-156104.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156139$8338 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \remainder_64 [31:0] - connect \Y $extend$libresoc.v:163208$8593_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:156139$8338_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$libresoc.v:163201$8582 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156144$8343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \quotient_65 [32] - connect \B \quotient_65 [31] - connect \Y $ne$libresoc.v:163201$8582_Y + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:156144$8343_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$libresoc.v:163192$8570 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156141$8340 parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:163192$8569_Y - connect \Y $neg$libresoc.v:163192$8570_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:156141$8340_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$libresoc.v:163195$8575 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156143$8342 parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:163195$8574_Y - connect \Y $neg$libresoc.v:163195$8575_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156143$8342_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$libresoc.v:163198$8579 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156146$8345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__is_32bit - connect \Y $not$libresoc.v:163198$8579_Y + connect \A \r_opc + connect \Y $not$libresoc.v:156146$8345_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $not $not$libresoc.v:163203$8584 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156140$8339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ov - connect \Y $not$libresoc.v:163203$8584_Y + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:156140$8339_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$libresoc.v:163193$8572 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156142$8341 parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:163193$8571_Y - connect \Y $pos$libresoc.v:163193$8572_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:156142$8341_Y end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:163196$8577 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156145$8344 parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:163196$8576_Y - connect \Y $pos$libresoc.v:163196$8577_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:156145$8344_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - cell $pos $pos$libresoc.v:163202$8583 - parameter \A_SIGNED 1 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } - connect \Y $pos$libresoc.v:163202$8583_Y + attribute \src "libresoc.v:156104.7-156104.20" + process $proc$libresoc.v:156104$8350 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $pos$libresoc.v:163204$8586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:163204$8585_Y - connect \Y $pos$libresoc.v:163204$8586_Y + attribute \src "libresoc.v:156126.7-156126.19" + process $proc$libresoc.v:156126$8351 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $pos$libresoc.v:163205$8588 + attribute \src "libresoc.v:156147.3-156148.27" + process $proc$libresoc.v:156147$8346 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:156149.3-156157.6" + process $proc$libresoc.v:156149$8347 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8348 $1\q_int$next[0:0]$8349 + attribute \src "libresoc.v:156150.5-156150.29" + switch \initial + attribute \src "libresoc.v:156150.9-156150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8349 1'0 + case + assign $1\q_int$next[0:0]$8349 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8348 + end + connect \$9 $and$libresoc.v:156139$8338_Y + connect \$11 $or$libresoc.v:156140$8339_Y + connect \$13 $not$libresoc.v:156141$8340_Y + connect \$15 $or$libresoc.v:156142$8341_Y + connect \$1 $not$libresoc.v:156143$8342_Y + connect \$3 $and$libresoc.v:156144$8343_Y + connect \$5 $or$libresoc.v:156145$8344_Y + connect \$7 $not$libresoc.v:156146$8345_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:156165.1-156223.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" +attribute \generator "nMigen" +module \opc_l$120 + attribute \src "libresoc.v:156166.7-156166.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156211.3-156219.6" + wire $0\q_int$next[0:0]$8362 + attribute \src "libresoc.v:156209.3-156210.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:156211.3-156219.6" + wire $1\q_int$next[0:0]$8363 + attribute \src "libresoc.v:156188.7-156188.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:156201.17-156201.96" + wire $and$libresoc.v:156201$8352_Y + attribute \src "libresoc.v:156206.17-156206.96" + wire $and$libresoc.v:156206$8357_Y + attribute \src "libresoc.v:156203.18-156203.93" + wire $not$libresoc.v:156203$8354_Y + attribute \src "libresoc.v:156205.17-156205.92" + wire $not$libresoc.v:156205$8356_Y + attribute \src "libresoc.v:156208.17-156208.92" + wire $not$libresoc.v:156208$8359_Y + attribute \src "libresoc.v:156202.18-156202.98" + wire $or$libresoc.v:156202$8353_Y + attribute \src "libresoc.v:156204.18-156204.99" + wire $or$libresoc.v:156204$8355_Y + attribute \src "libresoc.v:156207.17-156207.97" + wire $or$libresoc.v:156207$8358_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:156166.7-156166.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156201$8352 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:163205$8587_Y - connect \Y $pos$libresoc.v:163205$8588_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:156201$8352_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $pos$libresoc.v:163206$8590 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156206$8357 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:163206$8589_Y - connect \Y $pos$libresoc.v:163206$8590_Y + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:156206$8357_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $pos$libresoc.v:163207$8592 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156203$8354 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:163207$8591_Y - connect \Y $pos$libresoc.v:163207$8592_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:156203$8354_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $pos$libresoc.v:163208$8594 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156205$8356 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:163208$8593_Y - connect \Y $pos$libresoc.v:163208$8594_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156205$8356_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$libresoc.v:163194$8573 - parameter \WIDTH 65 - connect \A \$25 - connect \B \$23 - connect \S \quotient_neg - connect \Y $ternary$libresoc.v:163194$8573_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156208$8359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156208$8359_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$libresoc.v:163197$8578 - parameter \WIDTH 65 - connect \A \$32 - connect \B \$30 - connect \S \remainder_neg - connect \Y $ternary$libresoc.v:163197$8578_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156202$8353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:156202$8353_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$libresoc.v:163191$8568 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156204$8355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dividend_neg - connect \B \divisor_neg - connect \Y $xor$libresoc.v:163191$8568_Y + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:156204$8355_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$libresoc.v:163199$8580 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156207$8358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \quotient_65 [64] - connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:163199$8580_Y + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:156207$8358_Y end - attribute \src "libresoc.v:162851.7-162851.20" - process $proc$libresoc.v:162851$8597 + attribute \src "libresoc.v:156166.7-156166.20" + process $proc$libresoc.v:156166$8364 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:163209.3-163280.6" - process $proc$libresoc.v:163209$8595 + attribute \src "libresoc.v:156188.7-156188.19" + process $proc$libresoc.v:156188$8365 assign { } { } - assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:163210.5-163210.29" - switch \initial - attribute \src "libresoc.v:163210.9-163210.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - switch \$46 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o[63:0] $2\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0011110 - assign { } { } - assign $2\o[63:0] $3\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" - switch \logical_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\o[63:0] $4\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" - switch \logical_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\o[63:0] \$48 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\o[63:0] \$50 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\o[63:0] \quotient_65 [63:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0011101 - assign { } { } - assign $2\o[63:0] $5\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" - switch \logical_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\o[63:0] $6\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" - switch \logical_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\o[63:0] \$52 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $6\o[63:0] \$54 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $5\o[63:0] \quotient_65 [63:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0101111 - assign { } { } - assign $2\o[63:0] $7\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" - switch \logical_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\o[63:0] $8\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" - switch \logical_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\o[63:0] \remainder_s32_as_s64 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $8\o[63:0] \$56 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $7\o[63:0] \remainder_64 - end - case - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign $1\q_int[0:0] 1'0 sync always - update \o $0\o[63:0] + sync init + update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:163281.3-163314.6" - process $proc$libresoc.v:163281$8596 + attribute \src "libresoc.v:156209.3-156210.27" + process $proc$libresoc.v:156209$8360 assign { } { } - assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:163282.5-163282.29" + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:156211.3-156219.6" + process $proc$libresoc.v:156211$8361 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8362 $1\q_int$next[0:0]$8363 + attribute \src "libresoc.v:156212.5-156212.29" switch \initial - attribute \src "libresoc.v:163282.9-163282.17" + attribute \src "libresoc.v:156212.9-156212.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" - switch { \logical_op__is_signed \$36 \div_by_zero } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\ov[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign { } { } - assign $1\ov[0:0] $2\ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - switch \$40 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ov[0:0] 1'1 - case - assign $2\ov[0:0] \dive_abs_ov64 - end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } + case 1'1 assign { } { } - assign $1\ov[0:0] $3\ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - switch \$42 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ov[0:0] 1'1 - case - assign $3\ov[0:0] \dive_abs_ov32 - end - attribute \src "libresoc.v:0.0-0.0" + assign $1\q_int$next[0:0]$8363 1'0 case - assign { } { } - assign $1\ov[0:0] \dive_abs_ov32 + assign $1\q_int$next[0:0]$8363 \$5 end sync always - update \ov $0\ov[0:0] + update \q_int$next $0\q_int$next[0:0]$8362 end - connect \$21 $xor$libresoc.v:163191$8568_Y - connect \$23 $neg$libresoc.v:163192$8570_Y - connect \$25 $pos$libresoc.v:163193$8572_Y - connect \$27 $ternary$libresoc.v:163194$8573_Y - connect \$30 $neg$libresoc.v:163195$8575_Y - connect \$32 $pos$libresoc.v:163196$8577_Y - connect \$34 $ternary$libresoc.v:163197$8578_Y - connect \$36 $not$libresoc.v:163198$8579_Y - connect \$38 $xor$libresoc.v:163199$8580_Y - connect \$40 $and$libresoc.v:163200$8581_Y - connect \$42 $ne$libresoc.v:163201$8582_Y - connect \$44 $pos$libresoc.v:163202$8583_Y - connect \$46 $not$libresoc.v:163203$8584_Y - connect \$48 $pos$libresoc.v:163204$8586_Y - connect \$50 $pos$libresoc.v:163205$8588_Y - connect \$52 $pos$libresoc.v:163206$8590_Y - connect \$54 $pos$libresoc.v:163207$8592_Y - connect \$56 $pos$libresoc.v:163208$8594_Y - connect \$29 \$34 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$20 \xer_so - connect \remainder_s32_as_s64 \$44 - connect \remainder_s32 \remainder_64 [31:0] - connect \o_ok 1'1 - connect \xer_ov { \ov \ov } - connect \xer_ov_ok 1'1 - connect \remainder_64 \$34 [63:0] - connect \quotient_65 \$27 - connect \remainder_neg \dividend_neg - connect \quotient_neg \$21 + connect \$9 $and$libresoc.v:156201$8352_Y + connect \$11 $or$libresoc.v:156202$8353_Y + connect \$13 $not$libresoc.v:156203$8354_Y + connect \$15 $or$libresoc.v:156204$8355_Y + connect \$1 $not$libresoc.v:156205$8356_Y + connect \$3 $and$libresoc.v:156206$8357_Y + connect \$5 $or$libresoc.v:156207$8358_Y + connect \$7 $not$libresoc.v:156208$8359_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 end -attribute \src "libresoc.v:163332.1-163343.10" +attribute \src "libresoc.v:156227.1-156285.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" -module \p - attribute \src "libresoc.v:163341.17-163341.111" - wire $and$libresoc.v:163341$8598_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" +module \opc_l$126 + attribute \src "libresoc.v:156228.7-156228.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156273.3-156281.6" + wire $0\q_int$next[0:0]$8376 + attribute \src "libresoc.v:156271.3-156272.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:156273.3-156281.6" + wire $1\q_int$next[0:0]$8377 + attribute \src "libresoc.v:156250.7-156250.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:156263.17-156263.96" + wire $and$libresoc.v:156263$8366_Y + attribute \src "libresoc.v:156268.17-156268.96" + wire $and$libresoc.v:156268$8371_Y + attribute \src "libresoc.v:156265.18-156265.93" + wire $not$libresoc.v:156265$8368_Y + attribute \src "libresoc.v:156267.17-156267.92" + wire $not$libresoc.v:156267$8370_Y + attribute \src "libresoc.v:156270.17-156270.92" + wire $not$libresoc.v:156270$8373_Y + attribute \src "libresoc.v:156264.18-156264.98" + wire $or$libresoc.v:156264$8367_Y + attribute \src "libresoc.v:156266.18-156266.99" + wire $or$libresoc.v:156266$8369_Y + attribute \src "libresoc.v:156269.17-156269.97" + wire $or$libresoc.v:156269$8372_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163341$8598 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:156228.7-156228.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156263$8366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163341$8598_Y + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:156263$8366_Y end - connect \$1 $and$libresoc.v:163341$8598_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163347.1-163358.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" -attribute \generator "nMigen" -module \p$1 - attribute \src "libresoc.v:163356.17-163356.111" - wire $and$libresoc.v:163356$8599_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163356$8599 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156268$8371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163356$8599_Y + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:156268$8371_Y end - connect \$1 $and$libresoc.v:163356$8599_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163362.1-163373.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" -attribute \generator "nMigen" -module \p$108 - attribute \src "libresoc.v:163371.17-163371.111" - wire $and$libresoc.v:163371$8600_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163371$8600 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156265$8368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:156265$8368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156267$8370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156267$8370_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156270$8373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156270$8373_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156264$8367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163371$8600_Y + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:156264$8367_Y end - connect \$1 $and$libresoc.v:163371$8600_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163377.1-163388.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" -attribute \generator "nMigen" -module \p$111 - attribute \src "libresoc.v:163386.17-163386.111" - wire $and$libresoc.v:163386$8601_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163386$8601 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156266$8369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163386$8601_Y + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:156266$8369_Y end - connect \$1 $and$libresoc.v:163386$8601_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163392.1-163403.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" -attribute \generator "nMigen" -module \p$116 - attribute \src "libresoc.v:163401.17-163401.111" - wire $and$libresoc.v:163401$8602_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163401$8602 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156269$8372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163401$8602_Y + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:156269$8372_Y end - connect \$1 $and$libresoc.v:163401$8602_Y - connect \trigger \$1 + attribute \src "libresoc.v:156228.7-156228.20" + process $proc$libresoc.v:156228$8378 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:156250.7-156250.19" + process $proc$libresoc.v:156250$8379 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:156271.3-156272.27" + process $proc$libresoc.v:156271$8374 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:156273.3-156281.6" + process $proc$libresoc.v:156273$8375 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8376 $1\q_int$next[0:0]$8377 + attribute \src "libresoc.v:156274.5-156274.29" + switch \initial + attribute \src "libresoc.v:156274.9-156274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8377 1'0 + case + assign $1\q_int$next[0:0]$8377 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8376 + end + connect \$9 $and$libresoc.v:156263$8366_Y + connect \$11 $or$libresoc.v:156264$8367_Y + connect \$13 $not$libresoc.v:156265$8368_Y + connect \$15 $or$libresoc.v:156266$8369_Y + connect \$1 $not$libresoc.v:156267$8370_Y + connect \$3 $and$libresoc.v:156268$8371_Y + connect \$5 $or$libresoc.v:156269$8372_Y + connect \$7 $not$libresoc.v:156270$8373_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 end -attribute \src "libresoc.v:163407.1-163418.10" +attribute \src "libresoc.v:156289.1-156347.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" -module \p$17 - attribute \src "libresoc.v:163416.17-163416.111" - wire $and$libresoc.v:163416$8603_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" +module \opc_l$24 + attribute \src "libresoc.v:156290.7-156290.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156335.3-156343.6" + wire $0\q_int$next[0:0]$8390 + attribute \src "libresoc.v:156333.3-156334.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:156335.3-156343.6" + wire $1\q_int$next[0:0]$8391 + attribute \src "libresoc.v:156312.7-156312.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:156325.17-156325.96" + wire $and$libresoc.v:156325$8380_Y + attribute \src "libresoc.v:156330.17-156330.96" + wire $and$libresoc.v:156330$8385_Y + attribute \src "libresoc.v:156327.18-156327.93" + wire $not$libresoc.v:156327$8382_Y + attribute \src "libresoc.v:156329.17-156329.92" + wire $not$libresoc.v:156329$8384_Y + attribute \src "libresoc.v:156332.17-156332.92" + wire $not$libresoc.v:156332$8387_Y + attribute \src "libresoc.v:156326.18-156326.98" + wire $or$libresoc.v:156326$8381_Y + attribute \src "libresoc.v:156328.18-156328.99" + wire $or$libresoc.v:156328$8383_Y + attribute \src "libresoc.v:156331.17-156331.97" + wire $or$libresoc.v:156331$8386_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163416$8603 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:156290.7-156290.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156325$8380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163416$8603_Y + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:156325$8380_Y end - connect \$1 $and$libresoc.v:163416$8603_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163422.1-163433.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" -attribute \generator "nMigen" -module \p$20 - attribute \src "libresoc.v:163431.17-163431.111" - wire $and$libresoc.v:163431$8604_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163431$8604 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156330$8385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163431$8604_Y + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:156330$8385_Y end - connect \$1 $and$libresoc.v:163431$8604_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163437.1-163448.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" -attribute \generator "nMigen" -module \p$3 - attribute \src "libresoc.v:163446.17-163446.111" - wire $and$libresoc.v:163446$8605_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163446$8605 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156327$8382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:156327$8382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156329$8384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156329$8384_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156332$8387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156332$8387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156326$8381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163446$8605_Y + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:156326$8381_Y end - connect \$1 $and$libresoc.v:163446$8605_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163452.1-163463.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" -attribute \generator "nMigen" -module \p$30 - attribute \src "libresoc.v:163461.17-163461.111" - wire $and$libresoc.v:163461$8606_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163461$8606 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156328$8383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163461$8606_Y + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:156328$8383_Y end - connect \$1 $and$libresoc.v:163461$8606_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163467.1-163478.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" -attribute \generator "nMigen" -module \p$33 - attribute \src "libresoc.v:163476.17-163476.111" - wire $and$libresoc.v:163476$8607_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163476$8607 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156331$8386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163476$8607_Y + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:156331$8386_Y end - connect \$1 $and$libresoc.v:163476$8607_Y - connect \trigger \$1 + attribute \src "libresoc.v:156290.7-156290.20" + process $proc$libresoc.v:156290$8392 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:156312.7-156312.19" + process $proc$libresoc.v:156312$8393 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:156333.3-156334.27" + process $proc$libresoc.v:156333$8388 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:156335.3-156343.6" + process $proc$libresoc.v:156335$8389 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8390 $1\q_int$next[0:0]$8391 + attribute \src "libresoc.v:156336.5-156336.29" + switch \initial + attribute \src "libresoc.v:156336.9-156336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8391 1'0 + case + assign $1\q_int$next[0:0]$8391 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8390 + end + connect \$9 $and$libresoc.v:156325$8380_Y + connect \$11 $or$libresoc.v:156326$8381_Y + connect \$13 $not$libresoc.v:156327$8382_Y + connect \$15 $or$libresoc.v:156328$8383_Y + connect \$1 $not$libresoc.v:156329$8384_Y + connect \$3 $and$libresoc.v:156330$8385_Y + connect \$5 $or$libresoc.v:156331$8386_Y + connect \$7 $not$libresoc.v:156332$8387_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 end -attribute \src "libresoc.v:163482.1-163493.10" +attribute \src "libresoc.v:156351.1-156409.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" -module \p$36 - attribute \src "libresoc.v:163491.17-163491.111" - wire $and$libresoc.v:163491$8608_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" +module \opc_l$40 + attribute \src "libresoc.v:156352.7-156352.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156397.3-156405.6" + wire $0\q_int$next[0:0]$8404 + attribute \src "libresoc.v:156395.3-156396.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:156397.3-156405.6" + wire $1\q_int$next[0:0]$8405 + attribute \src "libresoc.v:156374.7-156374.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:156387.17-156387.96" + wire $and$libresoc.v:156387$8394_Y + attribute \src "libresoc.v:156392.17-156392.96" + wire $and$libresoc.v:156392$8399_Y + attribute \src "libresoc.v:156389.18-156389.93" + wire $not$libresoc.v:156389$8396_Y + attribute \src "libresoc.v:156391.17-156391.92" + wire $not$libresoc.v:156391$8398_Y + attribute \src "libresoc.v:156394.17-156394.92" + wire $not$libresoc.v:156394$8401_Y + attribute \src "libresoc.v:156388.18-156388.98" + wire $or$libresoc.v:156388$8395_Y + attribute \src "libresoc.v:156390.18-156390.99" + wire $or$libresoc.v:156390$8397_Y + attribute \src "libresoc.v:156393.17-156393.97" + wire $or$libresoc.v:156393$8400_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163491$8608 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:156352.7-156352.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156387$8394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163491$8608_Y + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:156387$8394_Y end - connect \$1 $and$libresoc.v:163491$8608_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163497.1-163508.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" -attribute \generator "nMigen" -module \p$46 - attribute \src "libresoc.v:163506.17-163506.111" - wire $and$libresoc.v:163506$8609_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163506$8609 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156392$8399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163506$8609_Y + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:156392$8399_Y end - connect \$1 $and$libresoc.v:163506$8609_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163512.1-163523.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" -attribute \generator "nMigen" -module \p$48 - attribute \src "libresoc.v:163521.17-163521.111" - wire $and$libresoc.v:163521$8610_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163521$8610 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156389$8396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:156389$8396_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156391$8398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156391$8398_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156394$8401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156394$8401_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156388$8395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163521$8610_Y + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:156388$8395_Y end - connect \$1 $and$libresoc.v:163521$8610_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163527.1-163538.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" -attribute \generator "nMigen" -module \p$5 - attribute \src "libresoc.v:163536.17-163536.111" - wire $and$libresoc.v:163536$8611_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163536$8611 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156390$8397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163536$8611_Y + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:156390$8397_Y end - connect \$1 $and$libresoc.v:163536$8611_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163542.1-163553.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" -attribute \generator "nMigen" -module \p$52 - attribute \src "libresoc.v:163551.17-163551.111" - wire $and$libresoc.v:163551$8612_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163551$8612 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156393$8400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163551$8612_Y + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:156393$8400_Y end - connect \$1 $and$libresoc.v:163551$8612_Y - connect \trigger \$1 + attribute \src "libresoc.v:156352.7-156352.20" + process $proc$libresoc.v:156352$8406 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:156374.7-156374.19" + process $proc$libresoc.v:156374$8407 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:156395.3-156396.27" + process $proc$libresoc.v:156395$8402 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:156397.3-156405.6" + process $proc$libresoc.v:156397$8403 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8404 $1\q_int$next[0:0]$8405 + attribute \src "libresoc.v:156398.5-156398.29" + switch \initial + attribute \src "libresoc.v:156398.9-156398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8405 1'0 + case + assign $1\q_int$next[0:0]$8405 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8404 + end + connect \$9 $and$libresoc.v:156387$8394_Y + connect \$11 $or$libresoc.v:156388$8395_Y + connect \$13 $not$libresoc.v:156389$8396_Y + connect \$15 $or$libresoc.v:156390$8397_Y + connect \$1 $not$libresoc.v:156391$8398_Y + connect \$3 $and$libresoc.v:156392$8399_Y + connect \$5 $or$libresoc.v:156393$8400_Y + connect \$7 $not$libresoc.v:156394$8401_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 end -attribute \src "libresoc.v:163557.1-163568.10" +attribute \src "libresoc.v:156413.1-156471.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" -module \p$62 - attribute \src "libresoc.v:163566.17-163566.111" - wire $and$libresoc.v:163566$8613_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" +module \opc_l$56 + attribute \src "libresoc.v:156414.7-156414.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156459.3-156467.6" + wire $0\q_int$next[0:0]$8418 + attribute \src "libresoc.v:156457.3-156458.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:156459.3-156467.6" + wire $1\q_int$next[0:0]$8419 + attribute \src "libresoc.v:156436.7-156436.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:156449.17-156449.96" + wire $and$libresoc.v:156449$8408_Y + attribute \src "libresoc.v:156454.17-156454.96" + wire $and$libresoc.v:156454$8413_Y + attribute \src "libresoc.v:156451.18-156451.93" + wire $not$libresoc.v:156451$8410_Y + attribute \src "libresoc.v:156453.17-156453.92" + wire $not$libresoc.v:156453$8412_Y + attribute \src "libresoc.v:156456.17-156456.92" + wire $not$libresoc.v:156456$8415_Y + attribute \src "libresoc.v:156450.18-156450.98" + wire $or$libresoc.v:156450$8409_Y + attribute \src "libresoc.v:156452.18-156452.99" + wire $or$libresoc.v:156452$8411_Y + attribute \src "libresoc.v:156455.17-156455.97" + wire $or$libresoc.v:156455$8414_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163566$8613 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:156414.7-156414.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156449$8408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163566$8613_Y + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:156449$8408_Y end - connect \$1 $and$libresoc.v:163566$8613_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163572.1-163583.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" -attribute \generator "nMigen" -module \p$65 - attribute \src "libresoc.v:163581.17-163581.111" - wire $and$libresoc.v:163581$8614_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163581$8614 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156454$8413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163581$8614_Y + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:156454$8413_Y end - connect \$1 $and$libresoc.v:163581$8614_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163587.1-163598.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" -attribute \generator "nMigen" -module \p$7 - attribute \src "libresoc.v:163596.17-163596.111" - wire $and$libresoc.v:163596$8615_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163596$8615 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156451$8410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:156451$8410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156453$8412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156453$8412_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156456$8415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163596$8615_Y + connect \A \r_opc + connect \Y $not$libresoc.v:156456$8415_Y end - connect \$1 $and$libresoc.v:163596$8615_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163602.1-163613.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" -attribute \generator "nMigen" -module \p$74 - attribute \src "libresoc.v:163611.17-163611.111" - wire $and$libresoc.v:163611$8616_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163611$8616 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156450$8409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163611$8616_Y + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:156450$8409_Y end - connect \$1 $and$libresoc.v:163611$8616_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163617.1-163628.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" -attribute \generator "nMigen" -module \p$76 - attribute \src "libresoc.v:163626.17-163626.111" - wire $and$libresoc.v:163626$8617_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163626$8617 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156452$8411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163626$8617_Y + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:156452$8411_Y end - connect \$1 $and$libresoc.v:163626$8617_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163632.1-163643.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" -attribute \generator "nMigen" -module \p$79 - attribute \src "libresoc.v:163641.17-163641.111" - wire $and$libresoc.v:163641$8618_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163641$8618 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156455$8414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163641$8618_Y + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:156455$8414_Y end - connect \$1 $and$libresoc.v:163641$8618_Y - connect \trigger \$1 + attribute \src "libresoc.v:156414.7-156414.20" + process $proc$libresoc.v:156414$8420 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:156436.7-156436.19" + process $proc$libresoc.v:156436$8421 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:156457.3-156458.27" + process $proc$libresoc.v:156457$8416 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:156459.3-156467.6" + process $proc$libresoc.v:156459$8417 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8418 $1\q_int$next[0:0]$8419 + attribute \src "libresoc.v:156460.5-156460.29" + switch \initial + attribute \src "libresoc.v:156460.9-156460.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8419 1'0 + case + assign $1\q_int$next[0:0]$8419 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8418 + end + connect \$9 $and$libresoc.v:156449$8408_Y + connect \$11 $or$libresoc.v:156450$8409_Y + connect \$13 $not$libresoc.v:156451$8410_Y + connect \$15 $or$libresoc.v:156452$8411_Y + connect \$1 $not$libresoc.v:156453$8412_Y + connect \$3 $and$libresoc.v:156454$8413_Y + connect \$5 $or$libresoc.v:156455$8414_Y + connect \$7 $not$libresoc.v:156456$8415_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 end -attribute \src "libresoc.v:163647.1-163658.10" +attribute \src "libresoc.v:156475.1-156533.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" -module \p$81 - attribute \src "libresoc.v:163656.17-163656.111" - wire $and$libresoc.v:163656$8619_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" +module \opc_l$68 + attribute \src "libresoc.v:156476.7-156476.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:156521.3-156529.6" + wire $0\q_int$next[0:0]$8432 + attribute \src "libresoc.v:156519.3-156520.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:156521.3-156529.6" + wire $1\q_int$next[0:0]$8433 + attribute \src "libresoc.v:156498.7-156498.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:156511.17-156511.96" + wire $and$libresoc.v:156511$8422_Y + attribute \src "libresoc.v:156516.17-156516.96" + wire $and$libresoc.v:156516$8427_Y + attribute \src "libresoc.v:156513.18-156513.93" + wire $not$libresoc.v:156513$8424_Y + attribute \src "libresoc.v:156515.17-156515.92" + wire $not$libresoc.v:156515$8426_Y + attribute \src "libresoc.v:156518.17-156518.92" + wire $not$libresoc.v:156518$8429_Y + attribute \src "libresoc.v:156512.18-156512.98" + wire $or$libresoc.v:156512$8423_Y + attribute \src "libresoc.v:156514.18-156514.99" + wire $or$libresoc.v:156514$8425_Y + attribute \src "libresoc.v:156517.17-156517.97" + wire $or$libresoc.v:156517$8428_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163656$8619 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "libresoc.v:156476.7-156476.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:156511$8422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163656$8619_Y + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:156511$8422_Y end - connect \$1 $and$libresoc.v:163656$8619_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163662.1-163673.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" -attribute \generator "nMigen" -module \p$91 - attribute \src "libresoc.v:163671.17-163671.111" - wire $and$libresoc.v:163671$8620_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163671$8620 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:156516$8427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163671$8620_Y + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:156516$8427_Y end - connect \$1 $and$libresoc.v:163671$8620_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163677.1-163688.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" -attribute \generator "nMigen" -module \p$93 - attribute \src "libresoc.v:163686.17-163686.111" - wire $and$libresoc.v:163686$8621_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163686$8621 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:156513$8424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163686$8621_Y + connect \A \q_opc + connect \Y $not$libresoc.v:156513$8424_Y end - connect \$1 $and$libresoc.v:163686$8621_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163692.1-163703.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" -attribute \generator "nMigen" -module \p$96 - attribute \src "libresoc.v:163701.17-163701.111" - wire $and$libresoc.v:163701$8622_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163701$8622 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:156515$8426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156515$8426_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:156518$8429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:156518$8429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:156512$8423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163701$8622_Y + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:156512$8423_Y end - connect \$1 $and$libresoc.v:163701$8622_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163707.1-163718.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" -attribute \generator "nMigen" -module \p$98 - attribute \src "libresoc.v:163716.17-163716.111" - wire $and$libresoc.v:163716$8623_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:163716$8623 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:156514$8425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:163716$8623_Y + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:156514$8425_Y end - connect \$1 $and$libresoc.v:163716$8623_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:163722.1-163745.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" -attribute \generator "nMigen" -module \pick - attribute \src "libresoc.v:163723.7-163723.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:163734.3-163743.6" - wire $0\o[0:0] - attribute \src "libresoc.v:163734.3-163743.6" - wire $1\o[0:0] - attribute \src "libresoc.v:163733.17-163733.95" - wire $eq$libresoc.v:163733$8624_Y - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire input 3 \i - attribute \src "libresoc.v:163723.7-163723.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire output 2 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:163733$8624 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:156517$8428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $eq$libresoc.v:163733$8624_Y + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:156517$8428_Y end - attribute \src "libresoc.v:163723.7-163723.20" - process $proc$libresoc.v:163723$8626 + attribute \src "libresoc.v:156476.7-156476.20" + process $proc$libresoc.v:156476$8434 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:163734.3-163743.6" - process $proc$libresoc.v:163734$8625 + attribute \src "libresoc.v:156498.7-156498.19" + process $proc$libresoc.v:156498$8435 assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:156519.3-156520.27" + process $proc$libresoc.v:156519$8430 assign { } { } - assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:163735.5-163735.29" + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:156521.3-156529.6" + process $proc$libresoc.v:156521$8431 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8432 $1\q_int$next[0:0]$8433 + attribute \src "libresoc.v:156522.5-156522.29" switch \initial - attribute \src "libresoc.v:163735.9-163735.17" + attribute \src "libresoc.v:156522.9-156522.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o[0:0] 1'0 + assign $1\q_int$next[0:0]$8433 1'0 case - assign $1\o[0:0] 1'0 + assign $1\q_int$next[0:0]$8433 \$5 end sync always - update \o $0\o[0:0] + update \q_int$next $0\q_int$next[0:0]$8432 end - connect \$1 $eq$libresoc.v:163733$8624_Y - connect \n \$1 + connect \$9 $and$libresoc.v:156511$8422_Y + connect \$11 $or$libresoc.v:156512$8423_Y + connect \$13 $not$libresoc.v:156513$8424_Y + connect \$15 $or$libresoc.v:156514$8425_Y + connect \$1 $not$libresoc.v:156515$8426_Y + connect \$3 $and$libresoc.v:156516$8427_Y + connect \$5 $or$libresoc.v:156517$8428_Y + connect \$7 $not$libresoc.v:156518$8429_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 end -attribute \src "libresoc.v:163749.1-164563.10" +attribute \src "libresoc.v:156537.1-156595.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" attribute \generator "nMigen" -module \pimem - attribute \src "libresoc.v:164526.3-164541.6" - wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:164490.3-164525.6" - wire $0\adrok_l_s_addr_acked$next[0:0]$8716 - attribute \src "libresoc.v:164048.3-164049.57" - wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:164140.3-164148.6" - wire $0\busy_delay$next[0:0]$8684 - attribute \src "libresoc.v:164046.3-164047.37" - wire $0\busy_delay[0:0] - attribute \src "libresoc.v:164474.3-164489.6" - wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:164464.3-164473.6" - wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:164454.3-164463.6" - wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:164435.3-164444.6" - wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:164396.3-164434.6" - wire width 2 $0\fsm_state$next[1:0]$8702 - attribute \src "libresoc.v:164038.3-164039.35" - wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:163750.7-163750.20" +module \opc_l$85 + attribute \src "libresoc.v:156538.7-156538.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164336.3-164345.6" - wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:164044.3-164045.35" - wire $0\lds_dly[0:0] - attribute \src "libresoc.v:164269.3-164299.6" - wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:164326.3-164335.6" - wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:164346.3-164355.6" - wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:164175.3-164190.6" - wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:164159.3-164174.6" - wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:164445.3-164453.6" - wire $0\lsui_active_dly$next[0:0]$8710 - attribute \src "libresoc.v:164036.3-164037.47" - wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:164376.3-164395.6" - wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:164040.3-164041.36" - wire $0\reset_delay[0:0] - attribute \src "libresoc.v:164316.3-164325.6" - wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:164300.3-164315.6" - wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:164149.3-164158.6" - wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:164130.3-164139.6" - wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:164115.3-164129.6" - wire $0\st_done_s_st_done$next[0:0]$8679 - attribute \src "libresoc.v:164050.3-164051.51" - wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:164356.3-164365.6" - wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:164042.3-164043.35" - wire $0\sts_dly[0:0] - attribute \src "libresoc.v:164191.3-164216.6" - wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:164243.3-164268.6" - wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:164217.3-164242.6" - wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:164366.3-164375.6" - wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:164526.3-164541.6" - wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:164490.3-164525.6" - wire $1\adrok_l_s_addr_acked$next[0:0]$8717 - attribute \src "libresoc.v:163844.7-163844.34" - wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:164140.3-164148.6" - wire $1\busy_delay$next[0:0]$8685 - attribute \src "libresoc.v:163848.7-163848.24" - wire $1\busy_delay[0:0] - attribute \src "libresoc.v:164474.3-164489.6" - wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:164464.3-164473.6" - wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:164454.3-164463.6" - wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:164435.3-164444.6" - wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:164396.3-164434.6" - wire width 2 $1\fsm_state$next[1:0]$8703 - attribute \src "libresoc.v:163870.13-163870.29" - wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:164336.3-164345.6" - wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:163884.7-163884.21" - wire $1\lds_dly[0:0] - attribute \src "libresoc.v:164269.3-164299.6" - wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:164326.3-164335.6" - wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:164346.3-164355.6" - wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:164175.3-164190.6" - wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:164159.3-164174.6" - wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:164445.3-164453.6" - wire $1\lsui_active_dly$next[0:0]$8711 - attribute \src "libresoc.v:163927.7-163927.29" - wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:164376.3-164395.6" - wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:163939.7-163939.25" - wire $1\reset_delay[0:0] - attribute \src "libresoc.v:164316.3-164325.6" - wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:164300.3-164315.6" - wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:164149.3-164158.6" - wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:164130.3-164139.6" - wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:164115.3-164129.6" - wire $1\st_done_s_st_done$next[0:0]$8680 - attribute \src "libresoc.v:163959.7-163959.31" - wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:164356.3-164365.6" - wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:163967.7-163967.21" - wire $1\sts_dly[0:0] - attribute \src "libresoc.v:164191.3-164216.6" - wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:164243.3-164268.6" - wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:164217.3-164242.6" - wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:164366.3-164375.6" - wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:164526.3-164541.6" - wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:164490.3-164525.6" - wire $2\adrok_l_s_addr_acked$next[0:0]$8718 - attribute \src "libresoc.v:164474.3-164489.6" - wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:164396.3-164434.6" - wire width 2 $2\fsm_state$next[1:0]$8704 - attribute \src "libresoc.v:164269.3-164299.6" - wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:164175.3-164190.6" - wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:164159.3-164174.6" - wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:164376.3-164395.6" - wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:164300.3-164315.6" - wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:164115.3-164129.6" - wire $2\st_done_s_st_done$next[0:0]$8681 - attribute \src "libresoc.v:164191.3-164216.6" - wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:164243.3-164268.6" - wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:164217.3-164242.6" - wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:164490.3-164525.6" - wire $3\adrok_l_s_addr_acked$next[0:0]$8719 - attribute \src "libresoc.v:164396.3-164434.6" - wire width 2 $3\fsm_state$next[1:0]$8705 - attribute \src "libresoc.v:164269.3-164299.6" - wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:164191.3-164216.6" - wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:164243.3-164268.6" - wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:164217.3-164242.6" - wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:164490.3-164525.6" - wire $4\adrok_l_s_addr_acked$next[0:0]$8720 - attribute \src "libresoc.v:164396.3-164434.6" - wire width 2 $4\fsm_state$next[1:0]$8706 - attribute \src "libresoc.v:164269.3-164299.6" - wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:164191.3-164216.6" - wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:164243.3-164268.6" - wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:164217.3-164242.6" - wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:164490.3-164525.6" - wire $5\adrok_l_s_addr_acked$next[0:0]$8721 - attribute \src "libresoc.v:164396.3-164434.6" - wire width 2 $5\fsm_state$next[1:0]$8707 - attribute \src "libresoc.v:164269.3-164299.6" - wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:164490.3-164525.6" - wire $6\adrok_l_s_addr_acked$next[0:0]$8722 - attribute \src "libresoc.v:163996.18-163996.115" - wire $and$libresoc.v:163996$8628_Y - attribute \src "libresoc.v:163998.18-163998.95" - wire $and$libresoc.v:163998$8630_Y - attribute \src "libresoc.v:164000.17-164000.138" - wire $and$libresoc.v:164000$8632_Y - attribute \src "libresoc.v:164001.18-164001.95" - wire $and$libresoc.v:164001$8633_Y - attribute \src "libresoc.v:164004.18-164004.136" - wire $and$libresoc.v:164004$8638_Y - attribute \src "libresoc.v:164005.18-164005.136" - wire $and$libresoc.v:164005$8639_Y - attribute \src "libresoc.v:164006.18-164006.136" - wire $and$libresoc.v:164006$8640_Y - attribute \src "libresoc.v:164007.18-164007.136" - wire $and$libresoc.v:164007$8641_Y - attribute \src "libresoc.v:164008.18-164008.136" - wire $and$libresoc.v:164008$8642_Y - attribute \src "libresoc.v:164013.18-164013.119" - wire width 176 $and$libresoc.v:164013$8647_Y - attribute \src "libresoc.v:164016.18-164016.136" - wire $and$libresoc.v:164016$8650_Y - attribute \src "libresoc.v:164017.18-164017.136" - wire $and$libresoc.v:164017$8651_Y - attribute \src "libresoc.v:164019.18-164019.139" - wire $and$libresoc.v:164019$8653_Y - attribute \src "libresoc.v:164023.18-164023.139" - wire $and$libresoc.v:164023$8657_Y - attribute \src "libresoc.v:164025.18-164025.114" - wire $and$libresoc.v:164025$8659_Y - attribute \src "libresoc.v:164027.18-164027.114" - wire $and$libresoc.v:164027$8661_Y - attribute \src "libresoc.v:164031.18-164031.103" - wire $and$libresoc.v:164031$8665_Y - attribute \src "libresoc.v:164032.17-164032.135" - wire $and$libresoc.v:164032$8666_Y - attribute \src "libresoc.v:164035.18-164035.103" - wire $and$libresoc.v:164035$8669_Y - attribute \src "libresoc.v:164002.18-164002.109" - wire width 4 $extend$libresoc.v:164002$8634_Y - attribute \src "libresoc.v:164003.18-164003.109" - wire width 4 $extend$libresoc.v:164003$8636_Y - attribute \src "libresoc.v:164014.18-164014.112" - wire width 8 $mul$libresoc.v:164014$8648_Y - attribute \src "libresoc.v:164020.18-164020.112" - wire width 8 $mul$libresoc.v:164020$8654_Y - attribute \src "libresoc.v:163995.17-163995.103" - wire $not$libresoc.v:163995$8627_Y - attribute \src "libresoc.v:163997.18-163997.94" - wire $not$libresoc.v:163997$8629_Y - attribute \src "libresoc.v:163999.18-163999.94" - wire $not$libresoc.v:163999$8631_Y - attribute \src "libresoc.v:164009.18-164009.102" - wire $not$libresoc.v:164009$8643_Y - attribute \src "libresoc.v:164012.18-164012.97" - wire $not$libresoc.v:164012$8646_Y - attribute \src "libresoc.v:164018.18-164018.102" - wire $not$libresoc.v:164018$8652_Y - attribute \src "libresoc.v:164021.17-164021.103" - wire $not$libresoc.v:164021$8655_Y - attribute \src "libresoc.v:164028.18-164028.101" - wire $not$libresoc.v:164028$8662_Y - attribute \src "libresoc.v:164029.18-164029.111" - wire $not$libresoc.v:164029$8663_Y - attribute \src "libresoc.v:164030.18-164030.110" - wire $not$libresoc.v:164030$8664_Y - attribute \src "libresoc.v:164033.18-164033.102" - wire $not$libresoc.v:164033$8667_Y - attribute \src "libresoc.v:164034.18-164034.102" - wire $not$libresoc.v:164034$8668_Y - attribute \src "libresoc.v:164010.18-164010.111" - wire $or$libresoc.v:164010$8644_Y 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 4 \$21 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 4 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - wire width 176 \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - wire width 176 \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - wire width 8 \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - wire width 176 \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - wire \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - wire width 319 \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - wire width 8 \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - wire width 319 \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \adrok_l_q_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \adrok_l_qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \adrok_l_r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \adrok_l_s_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \adrok_l_s_addr_acked$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" - wire \busy_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" - wire \busy_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:214" - wire \busy_edge - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \busy_l_q_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \busy_l_r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \cyc_l_q_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \cyc_l_r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \cyc_l_s_cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - wire width 2 \fsm_state$next - attribute \src "libresoc.v:163750.7-163750.15" + attribute \src "libresoc.v:156538.7-156538.15" wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" - wire \ld_active_q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \ld_active_r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" - wire \ld_active_s_ld_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:255" - wire width 64 \lddata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" - wire \lds - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \lds_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" - wire \lds_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" - wire \lds_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 48 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 10 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire output 4 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 18 \ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire input 2 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire input 3 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 12 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 13 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 15 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 14 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" - wire width 4 \lenexp_addr_i - attribute \src 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\enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 26 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 46 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \cr_a_ok + attribute \src "libresoc.v:156600.7-156600.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 54 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 25 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 44 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 48 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 23 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 50 \xer_ov$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 52 \xer_so$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 53 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:156947$8450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:164004$8638_Y + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $and$libresoc.v:156947$8450_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:164005$8639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:156955$8460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:164005$8639_Y + connect \A \is_nzero + connect \B \$41 + connect \Y $and$libresoc.v:156955$8460_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:164006$8640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:156958$8463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:164006$8640_Y + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $and$libresoc.v:156958$8463_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:164007$8641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:156951$8456 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:164007$8641_Y + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:156951$8456_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:164008$8642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:156952$8457 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:164008$8642_Y + connect \A \alu_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:156952$8457_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - cell $and $and$libresoc.v:164013$8647 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:156949$8452 parameter \A_SIGNED 0 parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 176 - parameter \Y_WIDTH 176 - connect \A \m_ld_data_o - connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:164013$8647_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:164016$8650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:164016$8650_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:164017$8651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:164017$8651_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:164019$8653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:164019$8653_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:164023$8657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:164023$8657_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:164025$8659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$63 - connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:164025$8659_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:164027$8661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$67 - connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:164027$8661_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:164031$8665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$73 - connect \B \$75 - connect \Y $and$libresoc.v:164031$8665_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:164032$8666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:164032$8666_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:164035$8669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_active - connect \B \$81 - connect \Y $and$libresoc.v:164035$8669_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:164002$8634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:164002$8634_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:164003$8636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:164003$8636_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $mul $mul$libresoc.v:164014$8648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \lenexp_addr_i - connect \B 4'1000 - connect \Y $mul$libresoc.v:164014$8648_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $mul $mul$libresoc.v:164020$8654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \lenexp_addr_i - connect \B 4'1000 - connect \Y $mul$libresoc.v:164020$8654_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $not $not$libresoc.v:163995$8627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \busy_delay - connect \Y $not$libresoc.v:163995$8627_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:163997$8629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lds_dly - connect \Y $not$libresoc.v:163997$8629_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:163999$8631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sts_dly - connect \Y $not$libresoc.v:163999$8631_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:164009$8643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_busy - connect \Y $not$libresoc.v:164009$8643_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:164012$8646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$38 - connect \Y $not$libresoc.v:164012$8646_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:164018$8652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_busy - connect \Y $not$libresoc.v:164018$8652_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - cell $not $not$libresoc.v:164021$8655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \busy_delay - connect \Y $not$libresoc.v:164021$8655_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:164028$8662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_busy_o - connect \Y $not$libresoc.v:164028$8662_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:164029$8663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:164029$8663_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:164030$8664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:164030$8664_Y + parameter \Y_WIDTH 65 + connect \A \$30 + connect \Y $extend$libresoc.v:156949$8452_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:164033$8667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:156950$8454 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_busy_o - connect \Y $not$libresoc.v:164033$8667_Y + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:156950$8454_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:164034$8668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:156948$8451 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_active_dly - connect \Y $not$libresoc.v:164034$8668_Y + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:156948$8451_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:164010$8644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:156954$8459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \x_busy_o - connect \B \lsui_busy - connect \Y $or$libresoc.v:164010$8644_Y + connect \A \msb_test + connect \Y $not$libresoc.v:156954$8459_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - cell $or $or$libresoc.v:164011$8645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:156957$8462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:164011$8645_Y + connect \A \is_nzero + connect \Y $not$libresoc.v:156957$8462_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:164024$8658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:156956$8461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:164024$8658_Y + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:156956$8461_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:164026$8660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:156959$8464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:164026$8660_Y + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:156959$8464_Y end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:164002$8635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:156949$8453 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:164002$8634_Y - connect \Y $pos$libresoc.v:164002$8635_Y + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:156949$8452_Y + connect \Y $pos$libresoc.v:156949$8453_Y end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:164003$8637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:156950$8455 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:164003$8636_Y - connect \Y $pos$libresoc.v:164003$8637_Y + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:156950$8454_Y + connect \Y $pos$libresoc.v:156950$8455_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $sshl $sshl$libresoc.v:164022$8656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:156953$8458 parameter \A_SIGNED 0 parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 319 - connect \A \ldst_port0_st_data_i - connect \B \$57 - connect \Y $sshl$libresoc.v:164022$8656_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $sshr $sshr$libresoc.v:164015$8649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 176 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 176 - connect \A \$42 - connect \B \$44 - connect \Y $sshr$libresoc.v:164015$8649_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:164052.11-164059.4" - cell \adrok_l \adrok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_addr_acked \adrok_l_q_addr_acked - connect \qn_addr_acked \adrok_l_qn_addr_acked - connect \r_addr_acked \adrok_l_r_addr_acked - connect \s_addr_acked \adrok_l_s_addr_acked - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:164060.10-164066.4" - cell \busy_l \busy_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_busy \busy_l_q_busy - connect \r_busy \busy_l_r_busy - connect \s_busy \busy_l_s_busy - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:164067.9-164073.4" - cell \cyc_l \cyc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_cyc \cyc_l_q_cyc - connect \r_cyc \cyc_l_r_cyc - connect \s_cyc \cyc_l_s_cyc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:164074.13-164080.4" - cell \ld_active \ld_active - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_ld_active \ld_active_q_ld_active - connect \r_ld_active \ld_active_r_ld_active - connect \s_ld_active \ld_active_s_ld_active - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:164081.10-164086.4" - cell \lenexp \lenexp - connect \addr_i \lenexp_addr_i - connect \len_i \lenexp_len_i - connect \lexp_o \lenexp_lexp_o - connect \rexp_o \lenexp_rexp_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:164087.11-164093.4" - cell \reset_l \reset_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_reset \reset_l_q_reset - connect \r_reset \reset_l_r_reset - connect \s_reset \reset_l_s_reset - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:164094.13-164100.4" - cell \st_active \st_active - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_st_active \st_active_q_st_active - connect \r_st_active \st_active_r_st_active - connect \s_st_active \st_active_s_st_active - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:164101.11-164107.4" - cell \st_done \st_done - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_st_done \st_done_q_st_done - connect \r_st_done \st_done_r_st_done - connect \s_st_done \st_done_s_st_done - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:164108.11-164114.4" - cell \valid_l \valid_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_valid \valid_l_q_valid - connect \r_valid \valid_l_r_valid - connect \s_valid \valid_l_s_valid + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:156953$8458_Y end - attribute \src "libresoc.v:163750.7-163750.20" - process $proc$libresoc.v:163750$8724 + attribute \src "libresoc.v:156600.7-156600.20" + process $proc$libresoc.v:156600$8478 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:163844.7-163844.34" - process $proc$libresoc.v:163844$8725 - assign { } { } - assign $1\adrok_l_s_addr_acked[0:0] 1'0 - sync always - sync init - update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] - end - attribute \src "libresoc.v:163848.7-163848.24" - process $proc$libresoc.v:163848$8726 - assign { } { } - assign $1\busy_delay[0:0] 1'0 - sync always - sync init - update \busy_delay $1\busy_delay[0:0] - end - attribute \src "libresoc.v:163870.13-163870.29" - process $proc$libresoc.v:163870$8727 - assign { } { } - assign $1\fsm_state[1:0] 2'00 - sync always - sync init - update \fsm_state $1\fsm_state[1:0] - end - attribute \src "libresoc.v:163884.7-163884.21" - process $proc$libresoc.v:163884$8728 - assign { } { } - assign $1\lds_dly[0:0] 1'0 - sync always - sync init - update \lds_dly $1\lds_dly[0:0] - end - attribute \src "libresoc.v:163927.7-163927.29" - process $proc$libresoc.v:163927$8729 - assign { } { } - assign $1\lsui_active_dly[0:0] 1'0 - sync always - sync init - update \lsui_active_dly $1\lsui_active_dly[0:0] - end - attribute \src "libresoc.v:163939.7-163939.25" - process $proc$libresoc.v:163939$8730 - assign { } { } - assign $1\reset_delay[0:0] 1'0 - sync always - sync init - update \reset_delay $1\reset_delay[0:0] - end - attribute \src "libresoc.v:163959.7-163959.31" - process $proc$libresoc.v:163959$8731 - assign { } { } - assign $1\st_done_s_st_done[0:0] 1'0 - sync always - sync init - update \st_done_s_st_done $1\st_done_s_st_done[0:0] - end - attribute \src "libresoc.v:163967.7-163967.21" - process $proc$libresoc.v:163967$8732 - assign { } { } - assign $1\sts_dly[0:0] 1'0 - sync always - sync init - update \sts_dly $1\sts_dly[0:0] - end - attribute \src "libresoc.v:164036.3-164037.47" - process $proc$libresoc.v:164036$8670 - assign { } { } - assign $0\lsui_active_dly[0:0] \lsui_active_dly$next - sync posedge \coresync_clk - update \lsui_active_dly $0\lsui_active_dly[0:0] - end - attribute \src "libresoc.v:164038.3-164039.35" - process $proc$libresoc.v:164038$8671 - assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next - sync posedge \coresync_clk - update \fsm_state $0\fsm_state[1:0] - end - attribute \src "libresoc.v:164040.3-164041.36" - process $proc$libresoc.v:164040$8672 - assign { } { } - assign $0\reset_delay[0:0] \reset_l_q_reset - sync posedge \coresync_clk - update \reset_delay $0\reset_delay[0:0] - end - attribute \src "libresoc.v:164042.3-164043.35" - process $proc$libresoc.v:164042$8673 - assign { } { } - assign $0\sts_dly[0:0] \ldst_port0_is_st_i - sync posedge \coresync_clk - update \sts_dly $0\sts_dly[0:0] - end - attribute \src "libresoc.v:164044.3-164045.35" - process $proc$libresoc.v:164044$8674 - assign { } { } - assign $0\lds_dly[0:0] \ldst_port0_is_ld_i - sync posedge \coresync_clk - update \lds_dly $0\lds_dly[0:0] - end - attribute \src "libresoc.v:164046.3-164047.37" - process $proc$libresoc.v:164046$8675 - assign { } { } - assign $0\busy_delay[0:0] \busy_delay$next - sync posedge \coresync_clk - update \busy_delay $0\busy_delay[0:0] - end - attribute \src "libresoc.v:164048.3-164049.57" - process $proc$libresoc.v:164048$8676 - assign { } { } - assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next - sync posedge \coresync_clk - update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] - end - attribute \src "libresoc.v:164050.3-164051.51" - process $proc$libresoc.v:164050$8677 - assign { } { } - assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next - sync posedge \coresync_clk - update \st_done_s_st_done $0\st_done_s_st_done[0:0] - end - attribute \src "libresoc.v:164115.3-164129.6" - process $proc$libresoc.v:164115$8678 - assign { } { } - assign { } { } - assign { } { } - assign $0\st_done_s_st_done$next[0:0]$8679 $2\st_done_s_st_done$next[0:0]$8681 - attribute \src "libresoc.v:164116.5-164116.29" - switch \initial - attribute \src "libresoc.v:164116.9-164116.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\st_done_s_st_done$next[0:0]$8680 1'1 - case - assign $1\st_done_s_st_done$next[0:0]$8680 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\st_done_s_st_done$next[0:0]$8681 1'0 - case - assign $2\st_done_s_st_done$next[0:0]$8681 $1\st_done_s_st_done$next[0:0]$8680 - end - sync always - update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8679 - end - attribute \src "libresoc.v:164130.3-164139.6" - process $proc$libresoc.v:164130$8682 - assign { } { } - assign { } { } - assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:164131.5-164131.29" - switch \initial - attribute \src "libresoc.v:164131.9-164131.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\st_done_r_st_done[0:0] 1'1 - case - assign $1\st_done_r_st_done[0:0] 1'0 - end - sync always - update \st_done_r_st_done $0\st_done_r_st_done[0:0] - end - attribute \src "libresoc.v:164140.3-164148.6" - process $proc$libresoc.v:164140$8683 - assign { } { } - assign { } { } - assign $0\busy_delay$next[0:0]$8684 $1\busy_delay$next[0:0]$8685 - attribute \src "libresoc.v:164141.5-164141.29" - switch \initial - attribute \src "libresoc.v:164141.9-164141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\busy_delay$next[0:0]$8685 1'0 - case - assign $1\busy_delay$next[0:0]$8685 \ldst_port0_busy_o - end - sync always - update \busy_delay$next $0\busy_delay$next[0:0]$8684 - end - attribute \src "libresoc.v:164149.3-164158.6" - process $proc$libresoc.v:164149$8686 - assign { } { } - assign { } { } - assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:164150.5-164150.29" - switch \initial - attribute \src "libresoc.v:164150.9-164150.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\st_active_r_st_active[0:0] 1'1 - case - assign $1\st_active_r_st_active[0:0] 1'0 - end - sync always - update \st_active_r_st_active $0\st_active_r_st_active[0:0] - end - attribute \src "libresoc.v:164159.3-164174.6" - process $proc$libresoc.v:164159$8687 - assign { } { } - assign { } { } - assign { } { } - assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:164160.5-164160.29" - switch \initial - attribute \src "libresoc.v:164160.9-164160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lenexp_len_i[3:0] \ldst_port0_data_len - case - assign $1\lenexp_len_i[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\lenexp_len_i[3:0] \ldst_port0_data_len - case - assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] - end - sync always - update \lenexp_len_i $0\lenexp_len_i[3:0] - end - attribute \src "libresoc.v:164175.3-164190.6" - process $proc$libresoc.v:164175$8688 - assign { } { } - assign { } { } - assign { } { } - assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:164176.5-164176.29" - switch \initial - attribute \src "libresoc.v:164176.9-164176.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lenexp_addr_i[3:0] \$21 - case - assign $1\lenexp_addr_i[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\lenexp_addr_i[3:0] \$23 - case - assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] - end - sync always - update \lenexp_addr_i $0\lenexp_addr_i[3:0] - end - attribute \src "libresoc.v:164191.3-164216.6" - process $proc$libresoc.v:164191$8689 - assign { } { } - assign { } { } - assign { } { } - assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:164192.5-164192.29" - switch \initial - attribute \src "libresoc.v:164192.9-164192.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\valid_l_s_valid[0:0] 1'1 - case - assign $2\valid_l_s_valid[0:0] 1'0 - end - case - assign $1\valid_l_s_valid[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\valid_l_s_valid[0:0] 1'1 - case - assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] - end - case - assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] - end - sync always - update \valid_l_s_valid $0\valid_l_s_valid[0:0] - end - attribute \src "libresoc.v:164217.3-164242.6" - process $proc$libresoc.v:164217$8690 - assign { } { } - assign { } { } - assign { } { } - assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:164218.5-164218.29" - switch \initial - attribute \src "libresoc.v:164218.9-164218.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] - case - assign $2\x_mask_i[7:0] 8'00000000 - end - case - assign $1\x_mask_i[7:0] 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] - case - assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] - end - case - assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] - end - sync always - update \x_mask_i $0\x_mask_i[7:0] - end - attribute \src "libresoc.v:164243.3-164268.6" - process $proc$libresoc.v:164243$8691 - assign { } { } - assign { } { } - assign { } { } - assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:164244.5-164244.29" - switch \initial - attribute \src "libresoc.v:164244.9-164244.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\x_addr_i[47:0] \ldst_port0_addr_i - case - assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - case - assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\x_addr_i[47:0] \ldst_port0_addr_i - case - assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] - end - case - assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] - end - sync always - update \x_addr_i $0\x_addr_i[47:0] - end - attribute \src "libresoc.v:164269.3-164299.6" - process $proc$libresoc.v:164269$8692 - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:164270.5-164270.29" - switch \initial - attribute \src "libresoc.v:164270.9-164270.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$31 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ldst_port0_addr_ok_o[0:0] 1'1 - case - assign $2\ldst_port0_addr_ok_o[0:0] 1'0 - end - case - assign $1\ldst_port0_addr_ok_o[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" - switch \adrok_l_qn_addr_acked - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\ldst_port0_addr_ok_o[0:0] 1'1 - case - assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end - case - assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end - case - assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end - sync always - update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] - end - attribute \src "libresoc.v:164300.3-164315.6" - process $proc$libresoc.v:164300$8693 - assign { } { } - assign { } { } - assign { } { } - assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:164301.5-164301.29" - switch \initial - attribute \src "libresoc.v:164301.9-164301.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch \$33 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_s_reset[0:0] \$35 - case - assign $1\reset_l_s_reset[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" - switch \st_done_q_st_done - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reset_l_s_reset[0:0] \$37 - case - assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - end - sync always - update \reset_l_s_reset $0\reset_l_s_reset[0:0] - end - attribute \src "libresoc.v:164316.3-164325.6" - process $proc$libresoc.v:164316$8694 - assign { } { } - assign { } { } - assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:164317.5-164317.29" - switch \initial - attribute \src "libresoc.v:164317.9-164317.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_r_reset[0:0] 1'1 - case - assign $1\reset_l_r_reset[0:0] 1'0 - end - sync always - update \reset_l_r_reset $0\reset_l_r_reset[0:0] - end - attribute \src "libresoc.v:164326.3-164335.6" - process $proc$libresoc.v:164326$8695 + attribute \src "libresoc.v:156960.3-156971.6" + process $proc$libresoc.v:156960$8465 assign { } { } - assign { } { } - assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:164327.5-164327.29" + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:156961.5-156961.29" switch \initial - attribute \src "libresoc.v:164327.9-164327.17" + attribute \src "libresoc.v:156961.9-156961.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_ld_data_o[63:0] \lddata - case - assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] - end - attribute \src "libresoc.v:164336.3-164345.6" - process $proc$libresoc.v:164336$8696 - assign { } { } - assign { } { } - assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:164337.5-164337.29" - switch \initial - attribute \src "libresoc.v:164337.9-164337.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset + assign $1\so[0:0] \xer_so$25 attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ld_active_r_ld_active[0:0] 1'1 - case - assign $1\ld_active_r_ld_active[0:0] 1'0 - end - sync always - update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] - end - attribute \src "libresoc.v:164346.3-164355.6" - process $proc$libresoc.v:164346$8697 - assign { } { } - assign { } { } - assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:164347.5-164347.29" - switch \initial - attribute \src "libresoc.v:164347.9-164347.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch \$50 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 - case - assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + assign $1\so[0:0] \xer_so end sync always - update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + update \so $0\so[0:0] end - attribute \src "libresoc.v:164356.3-164365.6" - process $proc$libresoc.v:164356$8698 - assign { } { } + attribute \src "libresoc.v:156972.3-156983.6" + process $proc$libresoc.v:156972$8466 assign { } { } - assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:164357.5-164357.29" + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:156973.5-156973.29" switch \initial - attribute \src "libresoc.v:164357.9-164357.17" + attribute \src "libresoc.v:156973.9-156973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - switch \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$45 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\stdata[63:0] \$56 [63:0] - case - assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \stdata $0\stdata[63:0] - end - attribute \src "libresoc.v:164366.3-164375.6" - process $proc$libresoc.v:164366$8699 - assign { } { } - assign { } { } - assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:164367.5-164367.29" - switch \initial - attribute \src "libresoc.v:164367.9-164367.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - switch \$61 + assign $1\cr0[3:0] \cr_a attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\x_st_data_i[63:0] \stdata - case - assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \x_st_data_i $0\x_st_data_i[63:0] - end - attribute \src "libresoc.v:164376.3-164395.6" - process $proc$libresoc.v:164376$8700 - assign { } { } - assign { } { } - assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:164377.5-164377.29" - switch \initial - attribute \src "libresoc.v:164377.9-164377.17" - case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - switch \$65 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\lsui_busy[0:0] 1'1 - case - assign $2\lsui_busy[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 assign { } { } - assign $1\lsui_busy[0:0] 1'1 - case - assign $1\lsui_busy[0:0] 1'0 + assign $1\cr0[3:0] { \is_negative \is_positive \$47 \so } end sync always - update \lsui_busy $0\lsui_busy[0:0] + update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:164396.3-164434.6" - process $proc$libresoc.v:164396$8701 - assign { } { } + attribute \src "libresoc.v:156984.3-156995.6" + process $proc$libresoc.v:156984$8467 assign { } { } - assign { } { } - assign $0\fsm_state$next[1:0]$8702 $5\fsm_state$next[1:0]$8707 - attribute \src "libresoc.v:164397.5-164397.29" + assign $0\o$28[64:0]$8468 $1\o$28[64:0]$8469 + attribute \src "libresoc.v:156985.5-156985.29" switch \initial - attribute \src "libresoc.v:164397.9-164397.17" + attribute \src "libresoc.v:156985.9-156985.17" case 1'1 case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\fsm_state$next[1:0]$8703 $2\fsm_state$next[1:0]$8704 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - switch \$69 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[1:0]$8704 2'01 - case - assign $2\fsm_state$next[1:0]$8704 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\fsm_state$next[1:0]$8703 $3\fsm_state$next[1:0]$8705 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - switch \$71 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[1:0]$8705 2'10 - case - assign $3\fsm_state$next[1:0]$8705 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\fsm_state$next[1:0]$8703 $4\fsm_state$next[1:0]$8706 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - switch \$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[1:0]$8706 2'00 - case - assign $4\fsm_state$next[1:0]$8706 \fsm_state - end - case - assign $1\fsm_state$next[1:0]$8703 \fsm_state - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \alu_op__invert_out attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$8707 2'00 + assign $1\o$28[64:0]$8469 \$29 + attribute \src "libresoc.v:0.0-0.0" case - assign $5\fsm_state$next[1:0]$8707 $1\fsm_state$next[1:0]$8703 + assign { } { } + assign $1\o$28[64:0]$8469 \$33 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$8702 + update \o$28 $0\o$28[64:0]$8468 end - attribute \src "libresoc.v:164435.3-164444.6" - process $proc$libresoc.v:164435$8708 + attribute \src "libresoc.v:156996.3-157005.6" + process $proc$libresoc.v:156996$8470 assign { } { } assign { } { } - assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:164436.5-164436.29" + assign $0\xer_so$25[0:0]$8471 $1\xer_so$25[0:0]$8472 + attribute \src "libresoc.v:156997.5-156997.29" switch \initial - attribute \src "libresoc.v:164436.9-164436.17" + attribute \src "libresoc.v:156997.9-156997.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" - switch \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\cyc_l_s_cyc[0:0] 1'1 + assign $1\xer_so$25[0:0]$8472 \$52 case - assign $1\cyc_l_s_cyc[0:0] 1'0 + assign $1\xer_so$25[0:0]$8472 1'0 end sync always - update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] + update \xer_so$25 $0\xer_so$25[0:0]$8471 end - attribute \src "libresoc.v:164445.3-164453.6" - process $proc$libresoc.v:164445$8709 + attribute \src "libresoc.v:157006.3-157015.6" + process $proc$libresoc.v:157006$8473 assign { } { } assign { } { } - assign $0\lsui_active_dly$next[0:0]$8710 $1\lsui_active_dly$next[0:0]$8711 - attribute \src "libresoc.v:164446.5-164446.29" + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:157007.5-157007.29" switch \initial - attribute \src "libresoc.v:164446.9-164446.17" + attribute \src "libresoc.v:157007.9-157007.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsui_active_dly$next[0:0]$8711 1'0 + assign $1\xer_so_ok[0:0] 1'1 case - assign $1\lsui_active_dly$next[0:0]$8711 \lsui_active + assign $1\xer_so_ok[0:0] 1'0 end sync always - update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8710 + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:164454.3-164463.6" - process $proc$libresoc.v:164454$8712 + attribute \src "libresoc.v:157016.3-157025.6" + process $proc$libresoc.v:157016$8474 assign { } { } assign { } { } - assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:164455.5-164455.29" + assign $0\xer_ov$24[1:0]$8475 $1\xer_ov$24[1:0]$8476 + attribute \src "libresoc.v:157017.5-157017.29" switch \initial - attribute \src "libresoc.v:164455.9-164455.17" + attribute \src "libresoc.v:157017.9-157017.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" - switch \cyc_l_q_cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\cyc_l_r_cyc[0:0] 1'1 + assign $1\xer_ov$24[1:0]$8476 \xer_ov case - assign $1\cyc_l_r_cyc[0:0] 1'0 + assign $1\xer_ov$24[1:0]$8476 2'00 end sync always - update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] + update \xer_ov$24 $0\xer_ov$24[1:0]$8475 end - attribute \src "libresoc.v:164464.3-164473.6" - process $proc$libresoc.v:164464$8713 + attribute \src "libresoc.v:157026.3-157035.6" + process $proc$libresoc.v:157026$8477 assign { } { } assign { } { } - assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:164465.5-164465.29" + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:157027.5-157027.29" switch \initial - attribute \src "libresoc.v:164465.9-164465.17" + attribute \src "libresoc.v:157027.9-157027.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - switch \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\busy_l_s_busy[0:0] \$5 + assign $1\xer_ov_ok[0:0] 1'1 case - assign $1\busy_l_s_busy[0:0] 1'0 + assign $1\xer_ov_ok[0:0] 1'0 end sync always - update \busy_l_s_busy $0\busy_l_s_busy[0:0] + update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:164474.3-164489.6" - process $proc$libresoc.v:164474$8714 - assign { } { } + connect \$26 $and$libresoc.v:156947$8450_Y + connect \$30 $not$libresoc.v:156948$8451_Y + connect \$29 $pos$libresoc.v:156949$8453_Y + connect \$33 $pos$libresoc.v:156950$8455_Y + connect \$35 $eq$libresoc.v:156951$8456_Y + connect \$37 $eq$libresoc.v:156952$8457_Y + connect \$39 $reduce_or$libresoc.v:156953$8458_Y + connect \$41 $not$libresoc.v:156954$8459_Y + connect \$43 $and$libresoc.v:156955$8460_Y + connect \$45 $or$libresoc.v:156956$8461_Y + connect \$47 $not$libresoc.v:156957$8462_Y + connect \$50 $and$libresoc.v:156958$8463_Y + connect \$52 $or$libresoc.v:156959$8464_Y + connect \oe$49 \$50 + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \alu_op__write_cr0 + connect \cr_a$22 \cr0 + connect \o_ok$21 \o_ok + connect \o$20 \o$28 [63:0] + connect \is_positive \$43 + connect \is_negative \msb_test + connect \is_nzero \$39 + connect \msb_test \target [63] + connect \is_cmpeqb \$37 + connect \is_cmp \$35 + connect \xer_ca_ok \alu_op__output_carry + connect \xer_ca$23 \xer_ca + connect \target \o$28 [63:0] + connect \oe \$26 +end +attribute \src "libresoc.v:157057.1-157454.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" +attribute \generator "nMigen" +module \output$100 + attribute \src "libresoc.v:157386.3-157397.6" + wire width 4 $0\cr0[3:0] + attribute \src "libresoc.v:157058.7-157058.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:157374.3-157385.6" + wire $0\so[0:0] + attribute \src "libresoc.v:157418.3-157427.6" + wire width 2 $0\xer_ov$17[1:0]$8498 + attribute \src "libresoc.v:157428.3-157437.6" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:157398.3-157407.6" + wire $0\xer_so$18[0:0]$8494 + attribute \src "libresoc.v:157408.3-157417.6" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:157386.3-157397.6" + wire width 4 $1\cr0[3:0] + attribute \src "libresoc.v:157374.3-157385.6" + wire $1\so[0:0] + attribute \src "libresoc.v:157418.3-157427.6" + wire width 2 $1\xer_ov$17[1:0]$8499 + attribute \src "libresoc.v:157428.3-157437.6" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:157398.3-157407.6" + wire $1\xer_so$18[0:0]$8495 + attribute \src "libresoc.v:157408.3-157417.6" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:157363.18-157363.128" + wire $and$libresoc.v:157363$8479_Y + attribute \src "libresoc.v:157369.18-157369.112" + wire $and$libresoc.v:157369$8486_Y + attribute \src "libresoc.v:157372.18-157372.125" + wire $and$libresoc.v:157372$8489_Y + attribute \src "libresoc.v:157365.18-157365.123" + wire $eq$libresoc.v:157365$8482_Y + attribute \src "libresoc.v:157366.18-157366.123" + wire $eq$libresoc.v:157366$8483_Y + attribute \src "libresoc.v:157364.18-157364.101" + wire width 65 $extend$libresoc.v:157364$8480_Y + attribute \src "libresoc.v:157368.18-157368.107" + wire $not$libresoc.v:157368$8485_Y + attribute \src "libresoc.v:157371.18-157371.107" + wire $not$libresoc.v:157371$8488_Y + attribute \src "libresoc.v:157370.18-157370.115" + wire $or$libresoc.v:157370$8487_Y + attribute \src "libresoc.v:157373.18-157373.112" + wire $or$libresoc.v:157373$8490_Y + attribute \src "libresoc.v:157364.18-157364.101" + wire width 65 $pos$libresoc.v:157364$8481_Y + attribute \src "libresoc.v:157367.18-157367.105" + wire $reduce_or$libresoc.v:157367$8484_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 65 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 33 \cr_a$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 34 \cr_a_ok + attribute \src "libresoc.v:157058.7-157058.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 39 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 14 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \o_ok$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 16 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 35 \xer_ov$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 36 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:157363$8479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:157363$8479_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:157369$8486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$30 + connect \Y $and$libresoc.v:157369$8486_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:157372$8489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:157372$8489_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:157365$8482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:157365$8482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:157366$8483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:157366$8483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:157364$8480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:157364$8480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:157368$8485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:157368$8485_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:157371$8488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:157371$8488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:157370$8487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:157370$8487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:157373$8490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:157373$8490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:157364$8481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:157364$8480_Y + connect \Y $pos$libresoc.v:157364$8481_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:157367$8484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:157367$8484_Y + end + attribute \src "libresoc.v:157058.7-157058.20" + process $proc$libresoc.v:157058$8501 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157374.3-157385.6" + process $proc$libresoc.v:157374$8491 assign { } { } - assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:164475.5-164475.29" + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:157375.5-157375.29" switch \initial - attribute \src "libresoc.v:164475.9-164475.17" + attribute \src "libresoc.v:157375.9-157375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" - switch \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\busy_l_r_busy[0:0] 1'1 + assign $1\so[0:0] \xer_so$18 + attribute \src "libresoc.v:0.0-0.0" case - assign $1\busy_l_r_busy[0:0] 1'0 + assign { } { } + assign $1\so[0:0] \xer_so end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" - switch \cyc_l_q_cyc + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:157386.3-157397.6" + process $proc$libresoc.v:157386$8492 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:157387.5-157387.29" + switch \initial + attribute \src "libresoc.v:157387.9-157387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\busy_l_r_busy[0:0] 1'1 + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" case - assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$36 \so } end sync always - update \busy_l_r_busy $0\busy_l_r_busy[0:0] + update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:164490.3-164525.6" - process $proc$libresoc.v:164490$8715 + attribute \src "libresoc.v:157398.3-157407.6" + process $proc$libresoc.v:157398$8493 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\adrok_l_s_addr_acked$next[0:0]$8716 $6\adrok_l_s_addr_acked$next[0:0]$8722 - attribute \src "libresoc.v:164491.5-164491.29" + assign $0\xer_so$18[0:0]$8494 $1\xer_so$18[0:0]$8495 + attribute \src "libresoc.v:157399.5-157399.29" switch \initial - attribute \src "libresoc.v:164491.9-164491.17" + attribute \src "libresoc.v:157399.9-157399.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adrok_l_s_addr_acked$next[0:0]$8717 $2\adrok_l_s_addr_acked$next[0:0]$8718 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\adrok_l_s_addr_acked$next[0:0]$8718 1'1 - case - assign $2\adrok_l_s_addr_acked$next[0:0]$8718 1'0 - end + assign $1\xer_so$18[0:0]$8495 \$41 case - assign $1\adrok_l_s_addr_acked$next[0:0]$8717 1'0 + assign $1\xer_so$18[0:0]$8495 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active + sync always + update \xer_so$18 $0\xer_so$18[0:0]$8494 + end + attribute \src "libresoc.v:157408.3-157417.6" + process $proc$libresoc.v:157408$8496 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:157409.5-157409.29" + switch \initial + attribute \src "libresoc.v:157409.9-157409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\adrok_l_s_addr_acked$next[0:0]$8719 $4\adrok_l_s_addr_acked$next[0:0]$8720 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\adrok_l_s_addr_acked$next[0:0]$8720 $5\adrok_l_s_addr_acked$next[0:0]$8721 - attribute \src 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"libresoc.v:157419.9-157419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\adrok_l_s_addr_acked$next[0:0]$8722 1'0 + assign $1\xer_ov$17[1:0]$8499 \xer_ov case - assign $6\adrok_l_s_addr_acked$next[0:0]$8722 $3\adrok_l_s_addr_acked$next[0:0]$8719 + assign $1\xer_ov$17[1:0]$8499 2'00 end sync always - update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8716 + update \xer_ov$17 $0\xer_ov$17[1:0]$8498 end - attribute \src "libresoc.v:164526.3-164541.6" - process $proc$libresoc.v:164526$8723 - assign { } { } + attribute \src "libresoc.v:157428.3-157437.6" + process $proc$libresoc.v:157428$8500 assign { } { } assign { } { } - assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:164527.5-164527.29" + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src 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\target [63] + connect \is_cmpeqb \$26 + connect \is_cmp \$24 + connect \target \o$21 [63:0] + connect \o$21 \$22 + connect \oe \$19 +end +attribute \src "libresoc.v:157458.1-157808.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" +attribute \generator "nMigen" +module \output$118 + attribute \src "libresoc.v:157780.3-157791.6" + wire width 4 $0\cr0[3:0] + attribute \src "libresoc.v:157459.7-157459.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:157780.3-157791.6" + wire width 4 $1\cr0[3:0] + attribute \src "libresoc.v:157777.18-157777.112" + wire $and$libresoc.v:157777$8508_Y + attribute \src "libresoc.v:157773.18-157773.122" + wire $eq$libresoc.v:157773$8504_Y + attribute \src "libresoc.v:157774.18-157774.122" + wire $eq$libresoc.v:157774$8505_Y + attribute \src "libresoc.v:157772.18-157772.101" + wire width 65 $extend$libresoc.v:157772$8502_Y + attribute \src "libresoc.v:157776.18-157776.107" + wire $not$libresoc.v:157776$8507_Y + attribute \src "libresoc.v:157779.18-157779.107" + wire $not$libresoc.v:157779$8510_Y + attribute \src "libresoc.v:157778.18-157778.115" + wire $or$libresoc.v:157778$8509_Y + attribute \src "libresoc.v:157772.18-157772.101" + wire width 65 $pos$libresoc.v:157772$8503_Y + attribute \src "libresoc.v:157775.18-157775.105" + wire $reduce_or$libresoc.v:157775$8506_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 65 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 20 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 43 \cr_a$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 44 \cr_a_ok + attribute \src "libresoc.v:157459.7-157459.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 47 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 18 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 41 \o$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 19 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \o_ok$20 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 25 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 34 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 45 \xer_ca$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 46 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:157777$8508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$32 + connect \Y $and$libresoc.v:157777$8508_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:157773$8504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \sr_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:157773$8504_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:157774$8505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \sr_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:157774$8505_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:157772$8502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:157772$8502_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:157776$8507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:157776$8507_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:157779$8510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:157779$8510_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:157778$8509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:157778$8509_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:157772$8503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:157772$8502_Y + connect \Y $pos$libresoc.v:157772$8503_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:157775$8506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:157775$8506_Y + end + attribute \src "libresoc.v:157459.7-157459.20" + process $proc$libresoc.v:157459$8512 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157780.3-157791.6" + process $proc$libresoc.v:157780$8511 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:157781.5-157781.29" + switch \initial + attribute \src "libresoc.v:157781.9-157781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$36 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\adrok_l_r_addr_acked[0:0] 1'1 + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" case - assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$38 \xer_so } end sync always - update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] + update \cr0 $0\cr0[3:0] end - connect \$9 $not$libresoc.v:163995$8627_Y - connect \$11 $and$libresoc.v:163996$8628_Y - connect \$13 $not$libresoc.v:163997$8629_Y - connect \$15 $and$libresoc.v:163998$8630_Y - connect \$17 $not$libresoc.v:163999$8631_Y - connect \$1 $and$libresoc.v:164000$8632_Y - connect \$19 $and$libresoc.v:164001$8633_Y - connect \$21 $pos$libresoc.v:164002$8635_Y - connect \$23 $pos$libresoc.v:164003$8637_Y - connect \$25 $and$libresoc.v:164004$8638_Y - connect \$27 $and$libresoc.v:164005$8639_Y - connect \$29 $and$libresoc.v:164006$8640_Y - connect \$31 $and$libresoc.v:164007$8641_Y - connect \$33 $and$libresoc.v:164008$8642_Y - connect \$35 $not$libresoc.v:164009$8643_Y - connect \$38 $or$libresoc.v:164010$8644_Y - connect \$3 $or$libresoc.v:164011$8645_Y - connect \$37 $not$libresoc.v:164012$8646_Y - connect \$42 $and$libresoc.v:164013$8647_Y - connect \$44 $mul$libresoc.v:164014$8648_Y - connect \$46 $sshr$libresoc.v:164015$8649_Y - connect \$48 $and$libresoc.v:164016$8650_Y - connect \$50 $and$libresoc.v:164017$8651_Y - connect \$52 $not$libresoc.v:164018$8652_Y - connect \$54 $and$libresoc.v:164019$8653_Y - connect \$57 $mul$libresoc.v:164020$8654_Y - connect \$5 $not$libresoc.v:164021$8655_Y - connect \$59 $sshl$libresoc.v:164022$8656_Y - connect \$61 $and$libresoc.v:164023$8657_Y - connect \$63 $or$libresoc.v:164024$8658_Y - connect \$65 $and$libresoc.v:164025$8659_Y - connect \$67 $or$libresoc.v:164026$8660_Y - connect \$69 $and$libresoc.v:164027$8661_Y - connect \$71 $not$libresoc.v:164028$8662_Y - connect \$73 $not$libresoc.v:164029$8663_Y - connect \$75 $not$libresoc.v:164030$8664_Y - connect \$77 $and$libresoc.v:164031$8665_Y - connect \$7 $and$libresoc.v:164032$8666_Y - connect \$79 $not$libresoc.v:164033$8667_Y - connect \$81 $not$libresoc.v:164034$8668_Y - connect \$83 $and$libresoc.v:164035$8669_Y - connect \$41 \$46 - connect \$56 \$59 - connect \valid_l_r_valid \lsui_active_rise - connect \lsui_active_rise \$83 - connect \lsui_active \$79 - connect \x_valid_i \valid_l_q_valid - connect \m_valid_i \valid_l_q_valid - connect \x_st_i \ldst_port0_is_st_i - connect \x_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_busy_o \busy_l_q_busy - connect \reset_delay$next \reset_l_q_reset - connect \lddata \$46 [63:0] - connect \st_active_s_st_active \sts_rise - connect \sts_rise \$19 - connect \sts_dly$next \sts - connect \ld_active_s_ld_active \lds_rise - connect \lds_rise \$15 - connect \lds_dly$next \lds - connect \busy_edge \$11 - connect \sts \ldst_port0_is_st_i - connect \lds \ldst_port0_is_ld_i + connect \$24 $pos$libresoc.v:157772$8503_Y + connect \$26 $eq$libresoc.v:157773$8504_Y + connect \$28 $eq$libresoc.v:157774$8505_Y + connect \$30 $reduce_or$libresoc.v:157775$8506_Y + connect \$32 $not$libresoc.v:157776$8507_Y + connect \$34 $and$libresoc.v:157777$8508_Y + connect \$36 $or$libresoc.v:157778$8509_Y + connect \$38 $not$libresoc.v:157779$8510_Y + connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \sr_op__write_cr0 + connect \cr_a$21 \cr0 + connect \o_ok$20 \o_ok + connect \o$19 \o$23 [63:0] + connect \is_positive \$34 + connect \is_negative \msb_test + connect \is_nzero \$30 + connect \msb_test \target [63] + connect \is_cmpeqb \$28 + connect \is_cmp \$26 + connect \xer_ca_ok \sr_op__output_carry + connect \xer_ca$22 \xer_ca + connect \target \o$23 [63:0] + connect \o$23 \$24 end -attribute \src "libresoc.v:164567.1-165337.10" +attribute \src "libresoc.v:157812.1-158175.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" -module \pipe - attribute \src "libresoc.v:165300.3-165318.6" - wire width 4 $0\cr_a$6$next[3:0]$8779 - attribute \src "libresoc.v:165164.3-165165.31" - wire width 4 $0\cr_a$6[3:0]$8735 - attribute \src "libresoc.v:164581.13-164581.28" - wire width 4 $0\cr_a$6[3:0]$8785 - attribute \src "libresoc.v:165300.3-165318.6" - wire $0\cr_a_ok$next[0:0]$8778 - attribute \src "libresoc.v:165166.3-165167.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:165247.3-165261.6" - wire width 13 $0\cr_op__fn_unit$3$next[12:0]$8759 - attribute \src "libresoc.v:165178.3-165179.51" - wire width 13 $0\cr_op__fn_unit$3[12:0]$8745 - attribute \src "libresoc.v:164643.14-164643.43" - wire width 13 $0\cr_op__fn_unit$3[12:0]$8788 - attribute \src "libresoc.v:165247.3-165261.6" - wire width 32 $0\cr_op__insn$4$next[31:0]$8760 - attribute \src "libresoc.v:165180.3-165181.45" - wire width 32 $0\cr_op__insn$4[31:0]$8747 - attribute \src "libresoc.v:164652.14-164652.37" - wire width 32 $0\cr_op__insn$4[31:0]$8790 - attribute \src "libresoc.v:165247.3-165261.6" - wire width 7 $0\cr_op__insn_type$2$next[6:0]$8761 - attribute \src "libresoc.v:165176.3-165177.55" - wire width 7 $0\cr_op__insn_type$2[6:0]$8743 - attribute \src "libresoc.v:164883.13-164883.41" - wire width 7 $0\cr_op__insn_type$2[6:0]$8792 - attribute \src "libresoc.v:165281.3-165299.6" - wire width 32 $0\full_cr$5$next[31:0]$8772 - attribute \src "libresoc.v:165168.3-165169.37" - wire width 32 $0\full_cr$5[31:0]$8738 - attribute \src "libresoc.v:164892.14-164892.33" - wire width 32 $0\full_cr$5[31:0]$8794 - attribute \src "libresoc.v:165281.3-165299.6" - wire $0\full_cr_ok$next[0:0]$8773 - attribute \src "libresoc.v:165170.3-165171.37" - wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:164568.7-164568.20" +module \output$54 + attribute \src "libresoc.v:158150.3-158161.6" + wire width 4 $0\cr0[3:0] + attribute \src "libresoc.v:157813.7-157813.20" wire $0\initial[0:0] - attribute \src "libresoc.v:165234.3-165246.6" - wire width 2 $0\muxid$1$next[1:0]$8756 - attribute \src "libresoc.v:165182.3-165183.33" - wire width 2 $0\muxid$1[1:0]$8749 - attribute \src "libresoc.v:165122.13-165122.29" - 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$2\full_cr_ok$next[0:0]$8776 - attribute \src "libresoc.v:165262.3-165280.6" - wire $2\o_ok$next[0:0]$8770 - attribute \src "libresoc.v:165216.3-165233.6" - wire $2\r_busy$next[0:0]$8754 - attribute \src "libresoc.v:165163.18-165163.118" - wire $and$libresoc.v:165163$8733_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 11 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 24 \cr_a$6 + attribute \src "libresoc.v:158138.3-158149.6" + wire width 65 $0\o$23[64:0]$8526 + attribute \src "libresoc.v:158150.3-158161.6" + wire width 4 $1\cr0[3:0] + attribute \src "libresoc.v:158138.3-158149.6" + wire width 65 $1\o$23[64:0]$8527 + attribute \src "libresoc.v:158135.18-158135.112" + wire $and$libresoc.v:158135$8522_Y + attribute \src "libresoc.v:158131.18-158131.127" + wire $eq$libresoc.v:158131$8518_Y + attribute \src "libresoc.v:158132.18-158132.127" + wire $eq$libresoc.v:158132$8519_Y + attribute \src "libresoc.v:158129.18-158129.103" + wire width 65 $extend$libresoc.v:158129$8514_Y + attribute \src "libresoc.v:158130.18-158130.101" + wire width 65 $extend$libresoc.v:158130$8516_Y + attribute \src "libresoc.v:158128.18-158128.100" + wire width 64 $not$libresoc.v:158128$8513_Y + attribute \src "libresoc.v:158134.18-158134.107" + wire $not$libresoc.v:158134$8521_Y + attribute \src "libresoc.v:158137.18-158137.107" + wire $not$libresoc.v:158137$8524_Y + attribute \src "libresoc.v:158136.18-158136.115" + wire $or$libresoc.v:158136$8523_Y + attribute \src "libresoc.v:158129.18-158129.103" + wire width 65 $pos$libresoc.v:158129$8515_Y + attribute \src "libresoc.v:158130.18-158130.101" + wire width 65 $pos$libresoc.v:158130$8517_Y + attribute \src "libresoc.v:158133.18-158133.105" + wire $reduce_or$libresoc.v:158133$8520_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 65 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 64 \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$6$next + wire width 65 \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 25 \cr_a_ok + wire width 4 input 21 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$25 + wire width 4 output 44 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 12 \cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 13 \cr_c - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" + wire output 45 \cr_a_ok + attribute \src "libresoc.v:157813.7-157813.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \cr_op__fn_unit + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -339542,7 +329436,7 @@ module \pipe attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \cr_op__fn_unit$18 + wire width 13 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -339558,17 +329452,31 @@ module \pipe attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 18 \cr_op__fn_unit$3 + wire width 13 output 25 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \cr_op__fn_unit$3$next + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \cr_op__insn + wire width 64 output 26 \logical_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$19 + wire input 4 \logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \cr_op__insn$4 + wire output 27 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$4$next + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 34 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -339644,7 +329552,7 @@ module \pipe attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \cr_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -339720,7 +329628,430 @@ module \pipe attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$17 + wire width 7 output 24 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 42 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 22 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:158135$8522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$36 + connect \Y $and$libresoc.v:158135$8522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:158131$8518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:158131$8518_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:158132$8519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:158132$8519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:158129$8514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$25 + connect \Y $extend$libresoc.v:158129$8514_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:158130$8516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:158130$8516_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:158128$8513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:158128$8513_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:158134$8521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:158134$8521_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:158137$8524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:158137$8524_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:158136$8523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:158136$8523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:158129$8515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:158129$8514_Y + connect \Y $pos$libresoc.v:158129$8515_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:158130$8517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:158130$8516_Y + connect \Y $pos$libresoc.v:158130$8517_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:158133$8520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:158133$8520_Y + end + attribute \src "libresoc.v:157813.7-157813.20" + process $proc$libresoc.v:157813$8529 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:158138.3-158149.6" + process $proc$libresoc.v:158138$8525 + assign { } { } + assign $0\o$23[64:0]$8526 $1\o$23[64:0]$8527 + attribute \src "libresoc.v:158139.5-158139.29" + switch \initial + attribute \src "libresoc.v:158139.9-158139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \logical_op__invert_out + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$23[64:0]$8527 \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o$23[64:0]$8527 \$28 + end + sync always + update \o$23 $0\o$23[64:0]$8526 + end + attribute \src "libresoc.v:158150.3-158161.6" + process $proc$libresoc.v:158150$8528 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:158151.5-158151.29" + switch \initial + attribute \src "libresoc.v:158151.9-158151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$42 \xer_so } + end + sync always + update \cr0 $0\cr0[3:0] + end + connect \$25 $not$libresoc.v:158128$8513_Y + connect \$24 $pos$libresoc.v:158129$8515_Y + connect \$28 $pos$libresoc.v:158130$8517_Y + connect \$30 $eq$libresoc.v:158131$8518_Y + connect \$32 $eq$libresoc.v:158132$8519_Y + connect \$34 $reduce_or$libresoc.v:158133$8520_Y + connect \$36 $not$libresoc.v:158134$8521_Y + connect \$38 $and$libresoc.v:158135$8522_Y + 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\enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 10 \full_cr + wire width 7 output 25 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 23 \full_cr_ok + wire output 44 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \full_cr_ok$23 + wire width 2 input 22 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \full_cr_ok$next - attribute \src "libresoc.v:164568.7-164568.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_a + wire width 2 output 47 \xer_ov$23 attribute \src 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$and$libresoc.v:158521$8530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:158529$8540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$40 + connect \Y $and$libresoc.v:158529$8540_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:158532$8543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $and$libresoc.v:158532$8543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:158525$8536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:158525$8536_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:158526$8537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:158526$8537_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:158523$8532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$29 + connect \Y $extend$libresoc.v:158523$8532_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:158524$8534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:158524$8534_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:158522$8531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:158522$8531_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:158528$8539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:158528$8539_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:158531$8542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:158531$8542_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:158530$8541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:158530$8541_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:158533$8544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:158533$8544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:158523$8533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:158523$8532_Y + connect \Y $pos$libresoc.v:158523$8533_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:158524$8535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:158524$8534_Y + connect \Y $pos$libresoc.v:158524$8535_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:158527$8538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:158527$8538_Y + end + attribute \src "libresoc.v:158180.7-158180.20" + process $proc$libresoc.v:158180$8558 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:158534.3-158545.6" + process $proc$libresoc.v:158534$8545 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:158535.5-158535.29" + switch \initial + attribute \src "libresoc.v:158535.9-158535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:158546.3-158557.6" + process $proc$libresoc.v:158546$8546 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:158547.5-158547.29" + switch \initial + attribute \src "libresoc.v:158547.9-158547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$46 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:158558.3-158569.6" + process $proc$libresoc.v:158558$8547 + assign { } { } + assign $0\o$27[64:0]$8548 $1\o$27[64:0]$8549 + attribute \src "libresoc.v:158559.5-158559.29" + switch \initial + attribute \src "libresoc.v:158559.9-158559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \logical_op__invert_out + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$27[64:0]$8549 \$28 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o$27[64:0]$8549 \$32 + end + sync always + update \o$27 $0\o$27[64:0]$8548 + end + attribute \src "libresoc.v:158570.3-158579.6" + process $proc$libresoc.v:158570$8550 + assign { } { } + assign { } { } + assign $0\xer_so$24[0:0]$8551 $1\xer_so$24[0:0]$8552 + attribute \src "libresoc.v:158571.5-158571.29" + switch \initial + attribute \src "libresoc.v:158571.9-158571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$24[0:0]$8552 \$51 + case + assign $1\xer_so$24[0:0]$8552 1'0 + end + sync always + update \xer_so$24 $0\xer_so$24[0:0]$8551 + end + attribute \src "libresoc.v:158580.3-158589.6" + process $proc$libresoc.v:158580$8553 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:158581.5-158581.29" + switch \initial + attribute \src "libresoc.v:158581.9-158581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:158590.3-158599.6" + process $proc$libresoc.v:158590$8554 + assign { } { } + assign { } { } + assign $0\xer_ov$23[1:0]$8555 $1\xer_ov$23[1:0]$8556 + attribute \src "libresoc.v:158591.5-158591.29" + switch \initial + attribute \src "libresoc.v:158591.9-158591.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$23[1:0]$8556 \xer_ov + case + assign $1\xer_ov$23[1:0]$8556 2'00 + end + sync always + update \xer_ov$23 $0\xer_ov$23[1:0]$8555 + end + attribute \src "libresoc.v:158600.3-158609.6" + process $proc$libresoc.v:158600$8557 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:158601.5-158601.29" + switch \initial + attribute \src "libresoc.v:158601.9-158601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$25 $and$libresoc.v:158521$8530_Y + connect \$29 $not$libresoc.v:158522$8531_Y + connect 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$pos$libresoc.v:158985$8581_Y + attribute \src "libresoc.v:158986.18-158986.114" + wire width 64 $pos$libresoc.v:158986$8583_Y + attribute \src "libresoc.v:158987.18-158987.115" + wire width 64 $pos$libresoc.v:158987$8585_Y + attribute \src "libresoc.v:158973.18-158973.121" + wire width 65 $ternary$libresoc.v:158973$8564_Y + attribute \src "libresoc.v:158976.18-158976.122" + wire width 65 $ternary$libresoc.v:158976$8569_Y + attribute \src "libresoc.v:158970.18-158970.120" + wire $xor$libresoc.v:158970$8559_Y + attribute \src "libresoc.v:158978.18-158978.127" + wire $xor$libresoc.v:158978$8571_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + wire width 65 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 65 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + wire width 65 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 \$30 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 65 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + wire width 64 \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + wire width 64 \$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + wire width 64 \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + wire width 64 \$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + wire width 64 \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + wire width 64 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 24 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 22 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 23 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 21 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 20 \divisor_neg + attribute \src "libresoc.v:158630.7-158630.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 44 \logical_op__data_len$18 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -339840,7 +330782,7 @@ module \pipe attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_cr_op__fn_unit + wire width 13 input 2 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -339856,11 +330798,31 @@ module \pipe attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_cr_op__fn_unit$9 + wire width 13 output 29 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn + wire width 64 input 3 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn$10 + wire width 64 output 30 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 38 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 45 \logical_op__insn$19 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -339936,7 +330898,7 @@ module \pipe attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -340012,2197 +330974,3570 @@ module \pipe attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \main_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 32 \main_full_cr$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \main_muxid$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 16 \muxid$1 + wire width 7 output 28 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$1$next + wire width 2 input 51 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 15 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 14 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$20 + wire width 2 output 27 \muxid$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next + wire width 64 output 46 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 21 \o_ok + wire output 47 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" + wire \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" + wire width 65 \quotient_65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" + wire \quotient_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 25 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 26 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" + wire width 64 \remainder_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" + wire \remainder_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + wire width 32 \remainder_s32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + wire width 64 \remainder_s32_as_s64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$21 + wire width 2 output 48 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 8 \ra + wire output 49 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:165163$8733 + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 50 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $and $and$libresoc.v:158979$8572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$13 - connect \B \p_ready_o - connect \Y $and$libresoc.v:165163$8733_Y + connect \A \logical_op__is_signed + connect \B \$38 + connect \Y $and$libresoc.v:158979$8572_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:165186.12-165207.4" - cell \main$9 \main - connect \cr_a \main_cr_a - connect \cr_a$6 \main_cr_a$12 - connect \cr_a_ok \main_cr_a_ok - connect \cr_b \main_cr_b - connect \cr_c \main_cr_c - connect \cr_op__fn_unit \main_cr_op__fn_unit - connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 - connect \cr_op__insn \main_cr_op__insn - connect \cr_op__insn$4 \main_cr_op__insn$10 - connect \cr_op__insn_type \main_cr_op__insn_type - connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 - connect \full_cr \main_full_cr - connect \full_cr$5 \main_full_cr$11 - connect \full_cr_ok \main_full_cr_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$7 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $pos $extend$libresoc.v:158971$8560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$libresoc.v:158971$8560_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:165208.9-165211.4" - cell \n$8 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $extend$libresoc.v:158972$8562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$libresoc.v:158972$8562_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:165212.9-165215.4" - cell \p$7 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $pos $extend$libresoc.v:158974$8565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$libresoc.v:158974$8565_Y end - attribute \src "libresoc.v:164568.7-164568.20" - process $proc$libresoc.v:164568$8783 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:158975$8567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$libresoc.v:158975$8567_Y end - attribute \src "libresoc.v:164581.13-164581.28" - process $proc$libresoc.v:164581$8784 - assign { } { } - assign $0\cr_a$6[3:0]$8785 4'0000 - sync always - sync init - update \cr_a$6 $0\cr_a$6[3:0]$8785 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + cell $pos $extend$libresoc.v:158983$8576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:158983$8576_Y end - attribute \src "libresoc.v:164586.7-164586.21" - process $proc$libresoc.v:164586$8786 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + cell $pos $extend$libresoc.v:158984$8578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:158984$8578_Y end - attribute \src "libresoc.v:164643.14-164643.43" - process $proc$libresoc.v:164643$8787 - assign { } { } - assign $0\cr_op__fn_unit$3[12:0]$8788 13'0000000000000 - sync always - sync init - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + cell $pos $extend$libresoc.v:158985$8580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:158985$8580_Y end - attribute \src "libresoc.v:164652.14-164652.37" - process $proc$libresoc.v:164652$8789 - assign { } { } - assign $0\cr_op__insn$4[31:0]$8790 0 - sync always - sync init - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + cell $pos $extend$libresoc.v:158986$8582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:158986$8582_Y end - attribute \src "libresoc.v:164883.13-164883.41" - process $proc$libresoc.v:164883$8791 - assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8792 7'0000000 - sync always - sync init - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + cell $pos $extend$libresoc.v:158987$8584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $extend$libresoc.v:158987$8584_Y end - attribute \src "libresoc.v:164892.14-164892.33" - process $proc$libresoc.v:164892$8793 - assign { } { } - assign $0\full_cr$5[31:0]$8794 0 - sync always - sync init - update \full_cr$5 $0\full_cr$5[31:0]$8794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + cell $ne $ne$libresoc.v:158980$8573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [32] + connect \B \quotient_65 [31] + connect \Y $ne$libresoc.v:158980$8573_Y end - attribute \src "libresoc.v:164897.7-164897.24" - process $proc$libresoc.v:164897$8795 - assign { } { } - assign $1\full_cr_ok[0:0] 1'0 - sync always - sync init - update \full_cr_ok $1\full_cr_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $neg $neg$libresoc.v:158971$8561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:158971$8560_Y + connect \Y $neg$libresoc.v:158971$8561_Y end - attribute \src "libresoc.v:165122.13-165122.29" - process $proc$libresoc.v:165122$8796 - assign { } { } - assign $0\muxid$1[1:0]$8797 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $neg $neg$libresoc.v:158974$8566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:158974$8565_Y + connect \Y $neg$libresoc.v:158974$8566_Y end - attribute \src "libresoc.v:165135.14-165135.38" - process $proc$libresoc.v:165135$8798 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + cell $not $not$libresoc.v:158977$8570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_32bit + connect \Y $not$libresoc.v:158977$8570_Y end - attribute \src "libresoc.v:165142.7-165142.18" - process $proc$libresoc.v:165142$8799 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $not $not$libresoc.v:158982$8575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ov + connect \Y $not$libresoc.v:158982$8575_Y end - attribute \src "libresoc.v:165156.7-165156.20" - process $proc$libresoc.v:165156$8800 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $pos$libresoc.v:158972$8563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:158972$8562_Y + connect \Y $pos$libresoc.v:158972$8563_Y end - attribute \src "libresoc.v:165164.3-165165.31" - process $proc$libresoc.v:165164$8734 - assign { } { } - assign $0\cr_a$6[3:0]$8735 \cr_a$6$next - sync posedge \coresync_clk - update \cr_a$6 $0\cr_a$6[3:0]$8735 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:158975$8568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:158975$8567_Y + connect \Y $pos$libresoc.v:158975$8568_Y end - attribute \src "libresoc.v:165166.3-165167.31" - process $proc$libresoc.v:165166$8736 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + cell $pos $pos$libresoc.v:158981$8574 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } + connect \Y $pos$libresoc.v:158981$8574_Y end - attribute \src "libresoc.v:165168.3-165169.37" - process $proc$libresoc.v:165168$8737 - assign { } { } - assign $0\full_cr$5[31:0]$8738 \full_cr$5$next - sync posedge \coresync_clk - update \full_cr$5 $0\full_cr$5[31:0]$8738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + cell $pos $pos$libresoc.v:158983$8577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:158983$8576_Y + connect \Y $pos$libresoc.v:158983$8577_Y end - attribute \src "libresoc.v:165170.3-165171.37" - process $proc$libresoc.v:165170$8739 - assign { } { } - assign $0\full_cr_ok[0:0] \full_cr_ok$next - sync posedge \coresync_clk - update \full_cr_ok $0\full_cr_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + cell $pos $pos$libresoc.v:158984$8579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:158984$8578_Y + connect \Y $pos$libresoc.v:158984$8579_Y end - attribute \src "libresoc.v:165172.3-165173.19" - process $proc$libresoc.v:165172$8740 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + cell $pos $pos$libresoc.v:158985$8581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:158985$8580_Y + connect \Y $pos$libresoc.v:158985$8581_Y end - attribute \src "libresoc.v:165174.3-165175.25" - process $proc$libresoc.v:165174$8741 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + cell $pos $pos$libresoc.v:158986$8583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:158986$8582_Y + connect \Y $pos$libresoc.v:158986$8583_Y end - attribute \src "libresoc.v:165176.3-165177.55" - process $proc$libresoc.v:165176$8742 - assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8743 \cr_op__insn_type$2$next - sync posedge \coresync_clk - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + cell $pos $pos$libresoc.v:158987$8585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:158987$8584_Y + connect \Y $pos$libresoc.v:158987$8585_Y end - attribute \src "libresoc.v:165178.3-165179.51" - process $proc$libresoc.v:165178$8744 - assign { } { } - assign $0\cr_op__fn_unit$3[12:0]$8745 \cr_op__fn_unit$3$next - sync posedge \coresync_clk - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $mux $ternary$libresoc.v:158973$8564 + parameter \WIDTH 65 + connect \A \$25 + connect \B \$23 + connect \S \quotient_neg + connect \Y $ternary$libresoc.v:158973$8564_Y end - attribute \src "libresoc.v:165180.3-165181.45" - process $proc$libresoc.v:165180$8746 - assign { } { } - assign $0\cr_op__insn$4[31:0]$8747 \cr_op__insn$4$next - sync posedge \coresync_clk - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $mux $ternary$libresoc.v:158976$8569 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \remainder_neg + connect \Y $ternary$libresoc.v:158976$8569_Y end - attribute \src "libresoc.v:165182.3-165183.33" - process $proc$libresoc.v:165182$8748 - assign { } { } - assign $0\muxid$1[1:0]$8749 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + cell $xor $xor$libresoc.v:158970$8559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dividend_neg + connect \B \divisor_neg + connect \Y $xor$libresoc.v:158970$8559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $xor $xor$libresoc.v:158978$8571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [64] + connect \B \quotient_65 [63] + connect \Y $xor$libresoc.v:158978$8571_Y end - attribute \src "libresoc.v:165184.3-165185.29" - process $proc$libresoc.v:165184$8750 + attribute \src "libresoc.v:158630.7-158630.20" + process $proc$libresoc.v:158630$8588 assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:165216.3-165233.6" - process $proc$libresoc.v:165216$8751 + attribute \src "libresoc.v:158988.3-159059.6" + process $proc$libresoc.v:158988$8586 assign { } { } assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:158989.5-158989.29" + switch \initial + attribute \src "libresoc.v:158989.9-158989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $2\o[63:0] $3\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] \$48 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\o[63:0] \$50 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\o[63:0] \quotient_65 [63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0011101 + assign { } { } + assign $2\o[63:0] $5\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\o[63:0] $6\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\o[63:0] \$52 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\o[63:0] \$54 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\o[63:0] \quotient_65 [63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0101111 + assign { } { } + assign $2\o[63:0] $7\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\o[63:0] $8\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\o[63:0] \remainder_s32_as_s64 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\o[63:0] \$56 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $7\o[63:0] \remainder_64 + end + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:159060.3-159093.6" + process $proc$libresoc.v:159060$8587 assign { } { } - assign $0\r_busy$next[0:0]$8752 $2\r_busy$next[0:0]$8754 - attribute \src "libresoc.v:165217.5-165217.29" + assign $0\ov[0:0] $1\ov[0:0] + attribute \src "libresoc.v:159061.5-159061.29" switch \initial - attribute \src "libresoc.v:165217.9-165217.17" + attribute \src "libresoc.v:159061.9-159061.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + switch { \logical_op__is_signed \$36 \div_by_zero } attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 3'--1 assign { } { } - assign $1\r_busy$next[0:0]$8753 1'1 + assign $1\ov[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 3'-1- assign { } { } - assign $1\r_busy$next[0:0]$8753 1'0 - case - assign $1\r_busy$next[0:0]$8753 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign { } { } + assign $1\ov[0:0] $2\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ov[0:0] 1'1 + case + assign $2\ov[0:0] \dive_abs_ov64 + end attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'1-- + assign { } { } assign { } { } - assign $2\r_busy$next[0:0]$8754 1'0 + assign $1\ov[0:0] $3\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ov[0:0] 1'1 + case + assign $3\ov[0:0] \dive_abs_ov32 + end + attribute \src "libresoc.v:0.0-0.0" case - assign $2\r_busy$next[0:0]$8754 $1\r_busy$next[0:0]$8753 + assign { } { } + assign $1\ov[0:0] \dive_abs_ov32 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8752 + update \ov $0\ov[0:0] + end + connect \$21 $xor$libresoc.v:158970$8559_Y + connect \$23 $neg$libresoc.v:158971$8561_Y + connect \$25 $pos$libresoc.v:158972$8563_Y + connect \$27 $ternary$libresoc.v:158973$8564_Y + connect \$30 $neg$libresoc.v:158974$8566_Y + connect \$32 $pos$libresoc.v:158975$8568_Y + connect \$34 $ternary$libresoc.v:158976$8569_Y + connect \$36 $not$libresoc.v:158977$8570_Y + connect \$38 $xor$libresoc.v:158978$8571_Y + connect \$40 $and$libresoc.v:158979$8572_Y + connect \$42 $ne$libresoc.v:158980$8573_Y + connect \$44 $pos$libresoc.v:158981$8574_Y + connect \$46 $not$libresoc.v:158982$8575_Y + connect \$48 $pos$libresoc.v:158983$8577_Y + connect \$50 $pos$libresoc.v:158984$8579_Y + connect \$52 $pos$libresoc.v:158985$8581_Y + connect \$54 $pos$libresoc.v:158986$8583_Y + connect \$56 $pos$libresoc.v:158987$8585_Y + connect \$29 \$34 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \remainder_s32_as_s64 \$44 + connect \remainder_s32 \remainder_64 [31:0] + connect \o_ok 1'1 + connect \xer_ov { \ov \ov } + connect \xer_ov_ok 1'1 + connect \remainder_64 \$34 [63:0] + connect \quotient_65 \$27 + connect \remainder_neg \dividend_neg + connect \quotient_neg \$21 +end +attribute \src "libresoc.v:159111.1-159122.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" +attribute \generator "nMigen" +module \p + attribute \src "libresoc.v:159120.17-159120.111" + wire $and$libresoc.v:159120$8589_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159120$8589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:159120$8589_Y + end + connect \$1 $and$libresoc.v:159120$8589_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159126.1-159137.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" +attribute \generator "nMigen" +module \p$1 + attribute \src "libresoc.v:159135.17-159135.111" + wire $and$libresoc.v:159135$8590_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159135$8590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:159135$8590_Y + end + connect \$1 $and$libresoc.v:159135$8590_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159141.1-159152.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" +attribute \generator "nMigen" +module \p$108 + attribute \src "libresoc.v:159150.17-159150.111" + wire $and$libresoc.v:159150$8591_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159150$8591 + parameter \A_SIGNED 0 + parameter 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"test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" +attribute \generator "nMigen" +module \p$76 + attribute \src "libresoc.v:159405.17-159405.111" + wire $and$libresoc.v:159405$8608_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159405$8608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:159405$8608_Y + end + connect \$1 $and$libresoc.v:159405$8608_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159411.1-159422.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" +attribute \generator "nMigen" +module \p$79 + attribute \src "libresoc.v:159420.17-159420.111" + wire $and$libresoc.v:159420$8609_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159420$8609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:159420$8609_Y + end + connect \$1 $and$libresoc.v:159420$8609_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159426.1-159437.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" +attribute \generator "nMigen" +module \p$81 + attribute \src "libresoc.v:159435.17-159435.111" + wire $and$libresoc.v:159435$8610_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159435$8610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:159435$8610_Y + end + connect \$1 $and$libresoc.v:159435$8610_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159441.1-159452.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" +attribute \generator "nMigen" +module \p$91 + attribute \src "libresoc.v:159450.17-159450.111" + wire $and$libresoc.v:159450$8611_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159450$8611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:159450$8611_Y + end + connect \$1 $and$libresoc.v:159450$8611_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159456.1-159467.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" +attribute \generator "nMigen" +module \p$93 + attribute \src "libresoc.v:159465.17-159465.111" + wire $and$libresoc.v:159465$8612_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159465$8612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:159465$8612_Y end - attribute \src "libresoc.v:165234.3-165246.6" - process $proc$libresoc.v:165234$8755 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$8756 $1\muxid$1$next[1:0]$8757 - attribute \src "libresoc.v:165235.5-165235.29" - switch \initial - attribute \src "libresoc.v:165235.9-165235.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$8757 \muxid$16 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$8757 \muxid$16 - case - assign $1\muxid$1$next[1:0]$8757 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8756 + connect \$1 $and$libresoc.v:159465$8612_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159471.1-159482.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" +attribute \generator "nMigen" +module \p$96 + attribute \src "libresoc.v:159480.17-159480.111" + wire $and$libresoc.v:159480$8613_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159480$8613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:159480$8613_Y end - attribute \src "libresoc.v:165247.3-165261.6" - process $proc$libresoc.v:165247$8758 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_op__fn_unit$3$next[12:0]$8759 $1\cr_op__fn_unit$3$next[12:0]$8762 - assign $0\cr_op__insn$4$next[31:0]$8760 $1\cr_op__insn$4$next[31:0]$8763 - assign $0\cr_op__insn_type$2$next[6:0]$8761 $1\cr_op__insn_type$2$next[6:0]$8764 - attribute \src "libresoc.v:165248.5-165248.29" - switch \initial - attribute \src "libresoc.v:165248.9-165248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8763 $1\cr_op__fn_unit$3$next[12:0]$8762 $1\cr_op__insn_type$2$next[6:0]$8764 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8763 $1\cr_op__fn_unit$3$next[12:0]$8762 $1\cr_op__insn_type$2$next[6:0]$8764 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } - case - assign $1\cr_op__fn_unit$3$next[12:0]$8762 \cr_op__fn_unit$3 - assign $1\cr_op__insn$4$next[31:0]$8763 \cr_op__insn$4 - assign $1\cr_op__insn_type$2$next[6:0]$8764 \cr_op__insn_type$2 - end - sync always - update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[12:0]$8759 - update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8760 - update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8761 + connect \$1 $and$libresoc.v:159480$8613_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159486.1-159497.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" +attribute \generator "nMigen" +module \p$98 + attribute \src "libresoc.v:159495.17-159495.111" + wire $and$libresoc.v:159495$8614_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:159495$8614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:159495$8614_Y end - attribute \src "libresoc.v:165262.3-165280.6" - process $proc$libresoc.v:165262$8765 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$8766 $1\o$next[63:0]$8768 - assign { } { } - assign $0\o_ok$next[0:0]$8767 $2\o_ok$next[0:0]$8770 - attribute \src "libresoc.v:165263.5-165263.29" - switch \initial - attribute \src "libresoc.v:165263.9-165263.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8769 $1\o$next[63:0]$8768 } { \o_ok$21 \o$20 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8769 $1\o$next[63:0]$8768 } { \o_ok$21 \o$20 } - case - assign $1\o$next[63:0]$8768 \o - assign $1\o_ok$next[0:0]$8769 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$8770 1'0 - case - assign $2\o_ok$next[0:0]$8770 $1\o_ok$next[0:0]$8769 - end - sync always - update \o$next $0\o$next[63:0]$8766 - update \o_ok$next $0\o_ok$next[0:0]$8767 + connect \$1 $and$libresoc.v:159495$8614_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159501.1-159524.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" +attribute \generator "nMigen" +module \pick + attribute \src "libresoc.v:159502.7-159502.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:159513.3-159522.6" + wire $0\o[0:0] + attribute \src "libresoc.v:159513.3-159522.6" + wire $1\o[0:0] + attribute \src "libresoc.v:159512.17-159512.95" + wire $eq$libresoc.v:159512$8615_Y + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire input 3 \i + attribute \src "libresoc.v:159502.7-159502.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire output 2 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $eq$libresoc.v:159512$8615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $eq$libresoc.v:159512$8615_Y end - attribute \src "libresoc.v:165281.3-165299.6" - process $proc$libresoc.v:165281$8771 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:159502.7-159502.20" + process $proc$libresoc.v:159502$8617 assign { } { } - assign $0\full_cr$5$next[31:0]$8772 $1\full_cr$5$next[31:0]$8774 - assign { } { } - assign $0\full_cr_ok$next[0:0]$8773 $2\full_cr_ok$next[0:0]$8776 - attribute \src "libresoc.v:165282.5-165282.29" - switch \initial - attribute \src "libresoc.v:165282.9-165282.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\full_cr_ok$next[0:0]$8775 $1\full_cr$5$next[31:0]$8774 } { \full_cr_ok$23 \full_cr$22 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\full_cr_ok$next[0:0]$8775 $1\full_cr$5$next[31:0]$8774 } { \full_cr_ok$23 \full_cr$22 } - case - assign $1\full_cr$5$next[31:0]$8774 \full_cr$5 - assign $1\full_cr_ok$next[0:0]$8775 \full_cr_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\full_cr_ok$next[0:0]$8776 1'0 - case - assign $2\full_cr_ok$next[0:0]$8776 $1\full_cr_ok$next[0:0]$8775 - end + assign $0\initial[0:0] 1'0 sync always - update \full_cr$5$next $0\full_cr$5$next[31:0]$8772 - update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8773 + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:165300.3-165318.6" - process $proc$libresoc.v:165300$8777 - assign { } { } + attribute \src "libresoc.v:159513.3-159522.6" + process $proc$libresoc.v:159513$8616 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$6$next[3:0]$8779 $1\cr_a$6$next[3:0]$8781 - assign $0\cr_a_ok$next[0:0]$8778 $2\cr_a_ok$next[0:0]$8782 - attribute \src "libresoc.v:165301.5-165301.29" + assign $0\o[0:0] $1\o[0:0] + attribute \src "libresoc.v:159514.5-159514.29" switch \initial - attribute \src "libresoc.v:165301.9-165301.17" + attribute \src "libresoc.v:159514.9-159514.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8780 $1\cr_a$6$next[3:0]$8781 } { \cr_a_ok$25 \cr_a$24 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$8780 $1\cr_a$6$next[3:0]$8781 } { \cr_a_ok$25 \cr_a$24 } - case - assign $1\cr_a_ok$next[0:0]$8780 \cr_a_ok - assign $1\cr_a$6$next[3:0]$8781 \cr_a$6 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch \i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8782 1'0 + assign $1\o[0:0] 1'0 case - assign $2\cr_a_ok$next[0:0]$8782 $1\cr_a_ok$next[0:0]$8780 + assign $1\o[0:0] 1'0 end sync always - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8778 - update \cr_a$6$next $0\cr_a$6$next[3:0]$8779 + update \o $0\o[0:0] end - connect \$14 $and$libresoc.v:165163$8733_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } - connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } - connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } - connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } - connect \muxid$16 \main_muxid$7 - connect \p_valid_i_p_ready_o \$14 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$13 \p_valid_i - connect \main_cr_c \cr_c - connect \main_cr_b \cr_b - connect \main_cr_a \cr_a - connect \main_full_cr \full_cr - connect \main_rb \rb - connect \main_ra \ra - connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - connect \main_muxid \muxid + connect \$1 $eq$libresoc.v:159512$8615_Y + connect \n \$1 end -attribute \src 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$0\lenexp_addr_i[3:0] + attribute \src "libresoc.v:159938.3-159953.6" + wire width 4 $0\lenexp_len_i[3:0] + attribute \src "libresoc.v:160224.3-160232.6" + wire $0\lsui_active_dly$next[0:0]$8701 + attribute \src "libresoc.v:159815.3-159816.47" + wire $0\lsui_active_dly[0:0] + attribute \src "libresoc.v:160155.3-160174.6" + wire $0\lsui_busy[0:0] + attribute \src "libresoc.v:159819.3-159820.36" + wire $0\reset_delay[0:0] + attribute \src "libresoc.v:160095.3-160104.6" + wire $0\reset_l_r_reset[0:0] + attribute \src "libresoc.v:160079.3-160094.6" + wire $0\reset_l_s_reset[0:0] + attribute \src "libresoc.v:159928.3-159937.6" + wire $0\st_active_r_st_active[0:0] + attribute \src "libresoc.v:159909.3-159918.6" + wire $0\st_done_r_st_done[0:0] + attribute \src "libresoc.v:159894.3-159908.6" + wire $0\st_done_s_st_done$next[0:0]$8670 + attribute \src "libresoc.v:159829.3-159830.51" + wire $0\st_done_s_st_done[0:0] + attribute \src "libresoc.v:160135.3-160144.6" + wire width 64 $0\stdata[63:0] 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \adrok_l_s_addr_acked$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" + wire \busy_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" + wire \busy_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:214" + wire \busy_edge + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \busy_l_q_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \busy_l_r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \busy_l_s_busy + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 23 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \cyc_l_q_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \cyc_l_r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \cyc_l_s_cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + wire width 2 \fsm_state$next + attribute \src "libresoc.v:159529.7-159529.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \ld_active_q_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \ld_active_r_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \ld_active_s_ld_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:255" + wire width 64 \lddata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" + wire \lds + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \lds_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \lds_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \lds_rise attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 31 \nia + wire width 48 input 6 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \nia$39 + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 10 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 4 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 18 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 2 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 3 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \nia$next + wire width 64 output 12 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \nia_ok + wire output 13 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \nia_ok$40 + wire width 64 input 15 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \nia_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" 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"/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" + wire width 176 \lenexp_rexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:107" + wire \lsui_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \lsui_active_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \lsui_active_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \lsui_active_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" + wire \lsui_busy + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" + wire width 64 input 11 \m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" + wire output 21 \m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" + wire \reset_delay + attribute \src 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\A \ldst_port0_busy_o + connect \B \$9 + connect \Y $and$libresoc.v:159775$8619_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:159777$8621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds + connect \B \$13 + connect \Y $and$libresoc.v:159777$8621_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + cell $and $and$libresoc.v:159779$8623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$libresoc.v:159779$8623_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:159780$8624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts + connect \B \$17 + connect \Y $and$libresoc.v:159780$8624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:159783$8629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:159783$8629_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:159784$8630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$libresoc.v:159784$8630_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + cell $and $and$libresoc.v:159785$8631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 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\A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$libresoc.v:159793$8639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + cell $mul $mul$libresoc.v:159799$8645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$libresoc.v:159799$8645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $not $not$libresoc.v:159774$8618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$libresoc.v:159774$8618_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:159776$8620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds_dly + connect \Y $not$libresoc.v:159776$8620_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:159778$8622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts_dly + connect \Y $not$libresoc.v:159778$8622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$libresoc.v:159788$8634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$libresoc.v:159788$8634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $not $not$libresoc.v:159791$8637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \Y $not$libresoc.v:159791$8637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$libresoc.v:159797$8643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$libresoc.v:159797$8643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" + cell $not $not$libresoc.v:159800$8646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$libresoc.v:159800$8646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + cell $not $not$libresoc.v:159807$8653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$libresoc.v:159807$8653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $not$libresoc.v:159808$8654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_st_i + connect \Y $not$libresoc.v:159808$8654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $not$libresoc.v:159809$8655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:159809$8655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" + cell $not $not$libresoc.v:159812$8658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$libresoc.v:159812$8658_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:159813$8659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active_dly + connect \Y $not$libresoc.v:159813$8659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $or $or$libresoc.v:159789$8635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \B \lsui_busy + connect \Y $or$libresoc.v:159789$8635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + cell $or $or$libresoc.v:159790$8636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:159790$8636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$libresoc.v:159803$8649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:159803$8649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$libresoc.v:159805$8651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:159805$8651_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:159781$8626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:159781$8625_Y + connect \Y $pos$libresoc.v:159781$8626_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:159782$8628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:159782$8627_Y + connect \Y $pos$libresoc.v:159782$8628_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + cell $sshl $sshl$libresoc.v:159801$8647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 319 + connect \A \ldst_port0_st_data_i + connect \B \$57 + connect \Y $sshl$libresoc.v:159801$8647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" + cell $sshr $sshr$libresoc.v:159794$8640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 176 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 176 + connect \A \$42 + connect \B \$44 + connect \Y $sshr$libresoc.v:159794$8640_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:166023.13-166051.4" - cell \main$22 \main - connect \br_op__cia \main_br_op__cia - connect \br_op__cia$2 \main_br_op__cia$13 - connect \br_op__fn_unit \main_br_op__fn_unit - connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 - connect \br_op__imm_data__data \main_br_op__imm_data__data - connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 - connect \br_op__imm_data__ok \main_br_op__imm_data__ok - connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 - connect \br_op__insn \main_br_op__insn - connect \br_op__insn$5 \main_br_op__insn$16 - connect \br_op__insn_type \main_br_op__insn_type - connect \br_op__insn_type$3 \main_br_op__insn_type$14 - connect \br_op__is_32bit \main_br_op__is_32bit - connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 - connect \br_op__lk \main_br_op__lk - connect \br_op__lk$8 \main_br_op__lk$19 - connect \cr_a \main_cr_a - connect \fast1 \main_fast1 - connect \fast1$10 \main_fast1$21 - connect \fast1_ok \main_fast1_ok - connect \fast2 \main_fast2 - connect \fast2$11 \main_fast2$22 - connect \fast2_ok \main_fast2_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$12 - connect \nia \main_nia - connect \nia_ok \main_nia_ok + attribute \src "libresoc.v:159831.11-159838.4" + cell \adrok_l \adrok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_addr_acked \adrok_l_q_addr_acked + connect \qn_addr_acked \adrok_l_qn_addr_acked + connect \r_addr_acked \adrok_l_r_addr_acked + connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 - attribute \src "libresoc.v:166052.10-166055.4" - cell \n$21 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:159839.10-159845.4" + cell \busy_l \busy_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_busy \busy_l_q_busy + connect \r_busy \busy_l_r_busy + connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 - attribute \src "libresoc.v:166056.10-166059.4" - cell \p$20 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i + attribute \src "libresoc.v:159846.9-159852.4" + cell \cyc_l \cyc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_cyc \cyc_l_q_cyc + connect \r_cyc \cyc_l_r_cyc + connect \s_cyc \cyc_l_s_cyc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159853.13-159859.4" + cell \ld_active \ld_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_ld_active \ld_active_q_ld_active + connect \r_ld_active \ld_active_r_ld_active + connect \s_ld_active \ld_active_s_ld_active + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159860.10-159865.4" + cell \lenexp \lenexp + connect \addr_i \lenexp_addr_i + connect \len_i \lenexp_len_i + connect \lexp_o \lenexp_lexp_o + connect \rexp_o \lenexp_rexp_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159866.11-159872.4" + cell \reset_l \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159873.13-159879.4" + cell \st_active \st_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_active \st_active_q_st_active + connect \r_st_active \st_active_r_st_active + connect \s_st_active \st_active_s_st_active + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159880.11-159886.4" + cell \st_done \st_done + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_done \st_done_q_st_done + connect \r_st_done \st_done_r_st_done + connect \s_st_done \st_done_s_st_done + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159887.11-159893.4" + cell \valid_l \valid_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_valid \valid_l_q_valid + connect \r_valid \valid_l_r_valid + connect \s_valid \valid_l_s_valid end - attribute \src "libresoc.v:165342.7-165342.20" - process $proc$libresoc.v:165342$8873 + attribute \src "libresoc.v:159529.7-159529.20" + process $proc$libresoc.v:159529$8715 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:165349.14-165349.51" - process $proc$libresoc.v:165349$8874 + attribute \src "libresoc.v:159623.7-159623.34" + process $proc$libresoc.v:159623$8716 assign { } { } - assign $0\br_op__cia$2[63:0]$8875 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always sync init - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8875 + update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:165402.14-165402.43" - process $proc$libresoc.v:165402$8876 + attribute \src "libresoc.v:159627.7-159627.24" + process $proc$libresoc.v:159627$8717 assign { } { } - assign $0\br_op__fn_unit$4[12:0]$8877 13'0000000000000 + assign $1\busy_delay[0:0] 1'0 sync always sync init - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8877 + update \busy_delay $1\busy_delay[0:0] end - attribute \src "libresoc.v:165411.14-165411.62" - process $proc$libresoc.v:165411$8878 + attribute \src "libresoc.v:159649.13-159649.29" + process $proc$libresoc.v:159649$8718 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8879 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fsm_state[1:0] 2'00 sync always sync init - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8879 + update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:165420.7-165420.37" - process $proc$libresoc.v:165420$8880 + attribute \src "libresoc.v:159663.7-159663.21" + process $proc$libresoc.v:159663$8719 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8881 1'0 + assign $1\lds_dly[0:0] 1'0 sync always sync init - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8881 + update \lds_dly $1\lds_dly[0:0] end - attribute \src "libresoc.v:165429.14-165429.37" - process $proc$libresoc.v:165429$8882 + attribute \src "libresoc.v:159706.7-159706.29" + process $proc$libresoc.v:159706$8720 assign { } { } - assign $0\br_op__insn$5[31:0]$8883 0 + assign $1\lsui_active_dly[0:0] 1'0 sync always sync init - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8883 + update \lsui_active_dly $1\lsui_active_dly[0:0] end - attribute \src "libresoc.v:165660.13-165660.41" - process $proc$libresoc.v:165660$8884 + attribute \src "libresoc.v:159718.7-159718.25" + process $proc$libresoc.v:159718$8721 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8885 7'0000000 + assign $1\reset_delay[0:0] 1'0 sync always sync init - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8885 + update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:165669.7-165669.33" - process $proc$libresoc.v:165669$8886 + attribute \src "libresoc.v:159738.7-159738.31" + process $proc$libresoc.v:159738$8722 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8887 1'0 + assign $1\st_done_s_st_done[0:0] 1'0 sync always sync init - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8887 + update \st_done_s_st_done $1\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:165678.7-165678.27" - process $proc$libresoc.v:165678$8888 + attribute \src "libresoc.v:159746.7-159746.21" + process $proc$libresoc.v:159746$8723 assign { } { } - assign $0\br_op__lk$8[0:0]$8889 1'0 + assign $1\sts_dly[0:0] 1'0 sync always sync init - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8889 + update \sts_dly $1\sts_dly[0:0] end - attribute \src "libresoc.v:165691.14-165691.47" - process $proc$libresoc.v:165691$8890 + attribute \src "libresoc.v:159815.3-159816.47" + process $proc$libresoc.v:159815$8661 assign { } { } - assign $0\fast1$10[63:0]$8891 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast1$10 $0\fast1$10[63:0]$8891 + assign $0\lsui_active_dly[0:0] \lsui_active_dly$next + sync posedge \coresync_clk + update \lsui_active_dly $0\lsui_active_dly[0:0] end - attribute \src "libresoc.v:165698.7-165698.22" - process $proc$libresoc.v:165698$8892 + attribute \src "libresoc.v:159817.3-159818.35" + process $proc$libresoc.v:159817$8662 assign { } { } - assign $1\fast1_ok[0:0] 1'0 + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \coresync_clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:159819.3-159820.36" + process $proc$libresoc.v:159819$8663 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "libresoc.v:159821.3-159822.35" + process $proc$libresoc.v:159821$8664 + assign { } { } + assign $0\sts_dly[0:0] \ldst_port0_is_st_i + sync posedge \coresync_clk + update \sts_dly $0\sts_dly[0:0] + end + attribute \src "libresoc.v:159823.3-159824.35" + process $proc$libresoc.v:159823$8665 + assign { } { } + assign $0\lds_dly[0:0] \ldst_port0_is_ld_i + sync posedge \coresync_clk + update \lds_dly $0\lds_dly[0:0] + end + attribute \src "libresoc.v:159825.3-159826.37" + process $proc$libresoc.v:159825$8666 + assign { } { } + assign $0\busy_delay[0:0] \busy_delay$next + sync posedge \coresync_clk + update \busy_delay $0\busy_delay[0:0] + end + attribute \src "libresoc.v:159827.3-159828.57" + process $proc$libresoc.v:159827$8667 + assign { } { } + assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next + sync posedge \coresync_clk + update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] + end + attribute \src "libresoc.v:159829.3-159830.51" + process $proc$libresoc.v:159829$8668 + assign { } { } + assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next + sync posedge \coresync_clk + update \st_done_s_st_done $0\st_done_s_st_done[0:0] + end + attribute \src "libresoc.v:159894.3-159908.6" + process $proc$libresoc.v:159894$8669 + assign { } { } + assign { } { } + assign { } { } + assign $0\st_done_s_st_done$next[0:0]$8670 $2\st_done_s_st_done$next[0:0]$8672 + attribute \src "libresoc.v:159895.5-159895.29" + switch \initial + attribute \src "libresoc.v:159895.9-159895.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_s_st_done$next[0:0]$8671 1'1 + case + assign $1\st_done_s_st_done$next[0:0]$8671 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\st_done_s_st_done$next[0:0]$8672 1'0 + case + assign $2\st_done_s_st_done$next[0:0]$8672 $1\st_done_s_st_done$next[0:0]$8671 + end sync always - sync init - update \fast1_ok $1\fast1_ok[0:0] + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8670 end - attribute \src "libresoc.v:165707.14-165707.47" - process $proc$libresoc.v:165707$8893 + attribute \src "libresoc.v:159909.3-159918.6" + process $proc$libresoc.v:159909$8673 + assign { } { } assign { } { } - assign $0\fast2$11[63:0]$8894 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] + attribute \src "libresoc.v:159910.5-159910.29" + switch \initial + attribute \src "libresoc.v:159910.9-159910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_r_st_done[0:0] 1'1 + case + assign $1\st_done_r_st_done[0:0] 1'0 + end sync always - sync init - update \fast2$11 $0\fast2$11[63:0]$8894 + update \st_done_r_st_done $0\st_done_r_st_done[0:0] end - attribute \src "libresoc.v:165714.7-165714.22" - process $proc$libresoc.v:165714$8895 + attribute \src "libresoc.v:159919.3-159927.6" + process $proc$libresoc.v:159919$8674 assign { } { } - assign $1\fast2_ok[0:0] 1'0 + assign { } { } + assign $0\busy_delay$next[0:0]$8675 $1\busy_delay$next[0:0]$8676 + attribute \src "libresoc.v:159920.5-159920.29" + switch \initial + attribute \src "libresoc.v:159920.9-159920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_delay$next[0:0]$8676 1'0 + case + assign $1\busy_delay$next[0:0]$8676 \ldst_port0_busy_o + end sync always - sync init - update \fast2_ok $1\fast2_ok[0:0] + update \busy_delay$next $0\busy_delay$next[0:0]$8675 end - attribute \src "libresoc.v:165953.13-165953.29" - process $proc$libresoc.v:165953$8896 + attribute \src "libresoc.v:159928.3-159937.6" + process $proc$libresoc.v:159928$8677 + assign { } { } assign { } { } - assign $0\muxid$1[1:0]$8897 2'00 + assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] + attribute \src "libresoc.v:159929.5-159929.29" + switch \initial + attribute \src "libresoc.v:159929.9-159929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_active_r_st_active[0:0] 1'1 + case + assign $1\st_active_r_st_active[0:0] 1'0 + end sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8897 + update \st_active_r_st_active $0\st_active_r_st_active[0:0] end - attribute \src "libresoc.v:165966.14-165966.40" - process $proc$libresoc.v:165966$8898 + attribute \src "libresoc.v:159938.3-159953.6" + process $proc$libresoc.v:159938$8678 assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign { } { } + assign { } { } + assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] + attribute \src "libresoc.v:159939.5-159939.29" + switch \initial + attribute \src "libresoc.v:159939.9-159939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $1\lenexp_len_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] + end sync always - sync init - update \nia $1\nia[63:0] + update \lenexp_len_i $0\lenexp_len_i[3:0] end - attribute \src "libresoc.v:165973.7-165973.20" - process $proc$libresoc.v:165973$8899 + attribute \src "libresoc.v:159954.3-159969.6" + process $proc$libresoc.v:159954$8679 assign { } { } - assign $1\nia_ok[0:0] 1'0 + assign { } { } + assign { } { } + assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] + attribute \src "libresoc.v:159955.5-159955.29" + switch \initial + attribute \src "libresoc.v:159955.9-159955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_addr_i[3:0] \$21 + case + assign $1\lenexp_addr_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_addr_i[3:0] \$23 + case + assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] + end sync always - sync init - update \nia_ok $1\nia_ok[0:0] + update \lenexp_addr_i $0\lenexp_addr_i[3:0] end - attribute \src "libresoc.v:165987.7-165987.20" - process $proc$libresoc.v:165987$8900 + attribute \src "libresoc.v:159970.3-159995.6" + process $proc$libresoc.v:159970$8680 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign { } { } + assign { } { } + assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] + attribute \src "libresoc.v:159971.5-159971.29" + switch \initial + attribute \src "libresoc.v:159971.9-159971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\valid_l_s_valid[0:0] 1'1 + case + assign $2\valid_l_s_valid[0:0] 1'0 + end + case + assign $1\valid_l_s_valid[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\valid_l_s_valid[0:0] 1'1 + case + assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + case + assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end sync always - sync init - update \r_busy $1\r_busy[0:0] + update \valid_l_s_valid $0\valid_l_s_valid[0:0] end - attribute \src "libresoc.v:165991.3-165992.23" - process $proc$libresoc.v:165991$8802 + attribute \src "libresoc.v:159996.3-160021.6" + process $proc$libresoc.v:159996$8681 assign { } { } - assign $0\nia[63:0] \nia$next - sync posedge \coresync_clk - update \nia $0\nia[63:0] + assign { } { } + assign { } { } + assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] + attribute \src "libresoc.v:159997.5-159997.29" + switch \initial + attribute \src "libresoc.v:159997.9-159997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $2\x_mask_i[7:0] 8'00000000 + end + case + assign $1\x_mask_i[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] + end + case + assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] + end + sync always + update \x_mask_i $0\x_mask_i[7:0] end - attribute \src "libresoc.v:165993.3-165994.29" - process $proc$libresoc.v:165993$8803 + attribute \src "libresoc.v:160022.3-160047.6" + process $proc$libresoc.v:160022$8682 assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next - sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] + assign { } { } + assign { } { } + assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] + attribute \src "libresoc.v:160023.5-160023.29" + switch \initial + attribute \src "libresoc.v:160023.9-160023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] + end + case + assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] + end + sync always + update \x_addr_i $0\x_addr_i[47:0] end - attribute \src "libresoc.v:165995.3-165996.35" - process $proc$libresoc.v:165995$8804 + attribute \src "libresoc.v:160048.3-160078.6" + process $proc$libresoc.v:160048$8683 assign { } { } - assign $0\fast2$11[63:0]$8805 \fast2$11$next - sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$8805 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:160049.5-160049.29" + switch \initial + attribute \src "libresoc.v:160049.9-160049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $2\ldst_port0_addr_ok_o[0:0] 1'0 + end + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:165997.3-165998.33" - process $proc$libresoc.v:165997$8806 + attribute \src "libresoc.v:160079.3-160094.6" + process $proc$libresoc.v:160079$8684 assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next - sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] + assign { } { } + assign { } { } + assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:160080.5-160080.29" + switch \initial + attribute \src "libresoc.v:160080.9-160080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] \$35 + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" + switch \st_done_q_st_done + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] \$37 + case + assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + end + sync always + update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:165999.3-166000.35" - process $proc$libresoc.v:165999$8807 + attribute \src "libresoc.v:160095.3-160104.6" + process $proc$libresoc.v:160095$8685 assign { } { } - assign $0\fast1$10[63:0]$8808 \fast1$10$next - sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$8808 + assign { } { } + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:160096.5-160096.29" + switch \initial + attribute \src "libresoc.v:160096.9-160096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end + sync always + update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:166001.3-166002.33" - process $proc$libresoc.v:166001$8809 + attribute \src "libresoc.v:160105.3-160114.6" + process $proc$libresoc.v:160105$8686 assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next - sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:160106.5-160106.29" + switch \initial + attribute \src "libresoc.v:160106.9-160106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o[63:0] \lddata + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end - attribute \src "libresoc.v:166003.3-166004.43" - process $proc$libresoc.v:166003$8810 + attribute \src "libresoc.v:160115.3-160124.6" + process $proc$libresoc.v:160115$8687 assign { } { } - assign $0\br_op__cia$2[63:0]$8811 \br_op__cia$2$next - sync posedge \coresync_clk - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8811 - end - attribute \src "libresoc.v:166005.3-166006.55" - process $proc$libresoc.v:166005$8812 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8813 \br_op__insn_type$3$next - sync posedge \coresync_clk - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8813 + assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] + attribute \src "libresoc.v:160116.5-160116.29" + switch \initial + attribute \src "libresoc.v:160116.9-160116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ld_active_r_ld_active[0:0] 1'1 + case + assign $1\ld_active_r_ld_active[0:0] 1'0 + end + sync always + update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end - attribute \src "libresoc.v:166007.3-166008.51" - process $proc$libresoc.v:166007$8814 + attribute \src "libresoc.v:160125.3-160134.6" + process $proc$libresoc.v:160125$8688 assign { } { } - assign $0\br_op__fn_unit$4[12:0]$8815 \br_op__fn_unit$4$next - sync posedge \coresync_clk - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8815 - end - attribute \src "libresoc.v:166009.3-166010.45" - process $proc$libresoc.v:166009$8816 assign { } { } - assign $0\br_op__insn$5[31:0]$8817 \br_op__insn$5$next - sync posedge \coresync_clk - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8817 + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:160126.5-160126.29" + switch \initial + attribute \src "libresoc.v:160126.9-160126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$50 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 + case + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:166011.3-166012.65" - process $proc$libresoc.v:166011$8818 + attribute \src "libresoc.v:160135.3-160144.6" + process $proc$libresoc.v:160135$8689 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8819 \br_op__imm_data__data$6$next - sync posedge \coresync_clk - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8819 - end - attribute \src "libresoc.v:166013.3-166014.61" - process $proc$libresoc.v:166013$8820 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8821 \br_op__imm_data__ok$7$next - sync posedge \coresync_clk - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8821 + assign $0\stdata[63:0] $1\stdata[63:0] + attribute \src "libresoc.v:160136.5-160136.29" + switch \initial + attribute \src "libresoc.v:160136.9-160136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\stdata[63:0] \$56 [63:0] + case + assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \stdata $0\stdata[63:0] end - attribute \src "libresoc.v:166015.3-166016.41" - process $proc$libresoc.v:166015$8822 + attribute \src "libresoc.v:160145.3-160154.6" + process $proc$libresoc.v:160145$8690 assign { } { } - assign $0\br_op__lk$8[0:0]$8823 \br_op__lk$8$next - sync posedge \coresync_clk - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8823 - end - attribute \src "libresoc.v:166017.3-166018.53" - process $proc$libresoc.v:166017$8824 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8825 \br_op__is_32bit$9$next - sync posedge \coresync_clk - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8825 + assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] + attribute \src "libresoc.v:160146.5-160146.29" + switch \initial + attribute \src "libresoc.v:160146.9-160146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_st_data_i[63:0] \stdata + case + assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \x_st_data_i $0\x_st_data_i[63:0] end - attribute \src "libresoc.v:166019.3-166020.33" - process $proc$libresoc.v:166019$8826 + attribute \src "libresoc.v:160155.3-160174.6" + process $proc$libresoc.v:160155$8691 assign { } { } - assign $0\muxid$1[1:0]$8827 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8827 - end - attribute \src "libresoc.v:166021.3-166022.29" - process $proc$libresoc.v:166021$8828 assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] + attribute \src "libresoc.v:160156.5-160156.29" + switch \initial + attribute \src "libresoc.v:160156.9-160156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lsui_busy[0:0] 1'1 + case + assign $2\lsui_busy[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\lsui_busy[0:0] 1'1 + case + assign $1\lsui_busy[0:0] 1'0 + end + sync always + update \lsui_busy $0\lsui_busy[0:0] end - attribute \src "libresoc.v:166060.3-166077.6" - process $proc$libresoc.v:166060$8829 + attribute \src "libresoc.v:160175.3-160213.6" + process $proc$libresoc.v:160175$8692 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8830 $2\r_busy$next[0:0]$8832 - attribute \src "libresoc.v:166061.5-166061.29" + assign $0\fsm_state$next[1:0]$8693 $5\fsm_state$next[1:0]$8698 + attribute \src "libresoc.v:160176.5-160176.29" switch \initial - attribute \src "libresoc.v:166061.9-166061.17" + attribute \src "libresoc.v:160176.9-160176.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$8694 $2\fsm_state$next[1:0]$8695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$8695 2'01 + case + assign $2\fsm_state$next[1:0]$8695 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 assign { } { } - assign $1\r_busy$next[0:0]$8831 1'1 + assign $1\fsm_state$next[1:0]$8694 $3\fsm_state$next[1:0]$8696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[1:0]$8696 2'10 + case + assign $3\fsm_state$next[1:0]$8696 \fsm_state + end attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 2'10 assign { } { } - assign $1\r_busy$next[0:0]$8831 1'0 + assign $1\fsm_state$next[1:0]$8694 $4\fsm_state$next[1:0]$8697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$8697 2'00 + case + assign $4\fsm_state$next[1:0]$8697 \fsm_state + end case - assign $1\r_busy$next[0:0]$8831 \r_busy + assign $1\fsm_state$next[1:0]$8694 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8832 1'0 + assign $5\fsm_state$next[1:0]$8698 2'00 case - assign $2\r_busy$next[0:0]$8832 $1\r_busy$next[0:0]$8831 + assign $5\fsm_state$next[1:0]$8698 $1\fsm_state$next[1:0]$8694 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8830 + update \fsm_state$next $0\fsm_state$next[1:0]$8693 end - attribute \src "libresoc.v:166078.3-166090.6" - process $proc$libresoc.v:166078$8833 + attribute \src "libresoc.v:160214.3-160223.6" + process $proc$libresoc.v:160214$8699 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8834 $1\muxid$1$next[1:0]$8835 - attribute \src "libresoc.v:166079.5-166079.29" + assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] + attribute \src "libresoc.v:160215.5-160215.29" switch \initial - attribute \src "libresoc.v:166079.9-166079.17" + attribute \src "libresoc.v:160215.9-160215.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$8835 \muxid$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" + switch \reset_l_s_reset attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\muxid$1$next[1:0]$8835 \muxid$26 + assign $1\cyc_l_s_cyc[0:0] 1'1 case - assign $1\muxid$1$next[1:0]$8835 \muxid$1 + assign $1\cyc_l_s_cyc[0:0] 1'0 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8834 + update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] end - attribute \src "libresoc.v:166091.3-166118.6" - process $proc$libresoc.v:166091$8836 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:160224.3-160232.6" + process $proc$libresoc.v:160224$8700 assign { } { } - assign $0\br_op__cia$2$next[63:0]$8837 $1\br_op__cia$2$next[63:0]$8845 - assign $0\br_op__fn_unit$4$next[12:0]$8838 $1\br_op__fn_unit$4$next[12:0]$8846 assign { } { } - assign { } { } - assign $0\br_op__insn$5$next[31:0]$8841 $1\br_op__insn$5$next[31:0]$8849 - assign $0\br_op__insn_type$3$next[6:0]$8842 $1\br_op__insn_type$3$next[6:0]$8850 - assign $0\br_op__is_32bit$9$next[0:0]$8843 $1\br_op__is_32bit$9$next[0:0]$8851 - assign $0\br_op__lk$8$next[0:0]$8844 $1\br_op__lk$8$next[0:0]$8852 - assign $0\br_op__imm_data__data$6$next[63:0]$8839 $2\br_op__imm_data__data$6$next[63:0]$8853 - assign $0\br_op__imm_data__ok$7$next[0:0]$8840 $2\br_op__imm_data__ok$7$next[0:0]$8854 - attribute \src "libresoc.v:166092.5-166092.29" + assign $0\lsui_active_dly$next[0:0]$8701 $1\lsui_active_dly$next[0:0]$8702 + attribute \src "libresoc.v:160225.5-160225.29" switch \initial - attribute \src "libresoc.v:166092.9-166092.17" + attribute \src "libresoc.v:160225.9-160225.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8851 $1\br_op__lk$8$next[0:0]$8852 $1\br_op__imm_data__ok$7$next[0:0]$8848 $1\br_op__imm_data__data$6$next[63:0]$8847 $1\br_op__insn$5$next[31:0]$8849 $1\br_op__fn_unit$4$next[12:0]$8846 $1\br_op__insn_type$3$next[6:0]$8850 $1\br_op__cia$2$next[63:0]$8845 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + case 1'1 assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8851 $1\br_op__lk$8$next[0:0]$8852 $1\br_op__imm_data__ok$7$next[0:0]$8848 $1\br_op__imm_data__data$6$next[63:0]$8847 $1\br_op__insn$5$next[31:0]$8849 $1\br_op__fn_unit$4$next[12:0]$8846 $1\br_op__insn_type$3$next[6:0]$8850 $1\br_op__cia$2$next[63:0]$8845 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign $1\lsui_active_dly$next[0:0]$8702 1'0 case - assign $1\br_op__cia$2$next[63:0]$8845 \br_op__cia$2 - assign $1\br_op__fn_unit$4$next[12:0]$8846 \br_op__fn_unit$4 - assign $1\br_op__imm_data__data$6$next[63:0]$8847 \br_op__imm_data__data$6 - assign $1\br_op__imm_data__ok$7$next[0:0]$8848 \br_op__imm_data__ok$7 - assign $1\br_op__insn$5$next[31:0]$8849 \br_op__insn$5 - assign $1\br_op__insn_type$3$next[6:0]$8850 \br_op__insn_type$3 - assign $1\br_op__is_32bit$9$next[0:0]$8851 \br_op__is_32bit$9 - assign $1\br_op__lk$8$next[0:0]$8852 \br_op__lk$8 + assign $1\lsui_active_dly$next[0:0]$8702 \lsui_active end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + sync always + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8701 + end + attribute \src "libresoc.v:160233.3-160242.6" + process $proc$libresoc.v:160233$8703 + assign { } { } + assign { } { } + assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] + attribute \src "libresoc.v:160234.5-160234.29" + switch \initial + attribute \src "libresoc.v:160234.9-160234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" + switch \cyc_l_q_cyc attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign $2\br_op__imm_data__data$6$next[63:0]$8853 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\br_op__imm_data__ok$7$next[0:0]$8854 1'0 + assign $1\cyc_l_r_cyc[0:0] 1'1 case - assign $2\br_op__imm_data__data$6$next[63:0]$8853 $1\br_op__imm_data__data$6$next[63:0]$8847 - assign $2\br_op__imm_data__ok$7$next[0:0]$8854 $1\br_op__imm_data__ok$7$next[0:0]$8848 + assign $1\cyc_l_r_cyc[0:0] 1'0 end sync always - update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8837 - update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[12:0]$8838 - update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8839 - update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8840 - update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8841 - update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8842 - update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8843 - update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8844 + update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] end - attribute \src "libresoc.v:166119.3-166137.6" - process $proc$libresoc.v:166119$8855 + attribute \src "libresoc.v:160243.3-160252.6" + process $proc$libresoc.v:160243$8704 assign { } { } assign { } { } + assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] + attribute \src "libresoc.v:160244.5-160244.29" + switch \initial + attribute \src "libresoc.v:160244.9-160244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_s_busy[0:0] \$5 + case + assign $1\busy_l_s_busy[0:0] 1'0 + end + sync always + update \busy_l_s_busy $0\busy_l_s_busy[0:0] + end + attribute \src "libresoc.v:160253.3-160268.6" + process $proc$libresoc.v:160253$8705 assign { } { } assign { } { } - assign $0\fast1$10$next[63:0]$8856 $1\fast1$10$next[63:0]$8858 assign { } { } - assign $0\fast1_ok$next[0:0]$8857 $2\fast1_ok$next[0:0]$8860 - attribute \src "libresoc.v:166120.5-166120.29" + assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] + attribute \src "libresoc.v:160254.5-160254.29" switch \initial - attribute \src "libresoc.v:166120.9-166120.17" + attribute \src "libresoc.v:160254.9-160254.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\fast1_ok$next[0:0]$8859 $1\fast1$10$next[63:0]$8858 } { \fast1_ok$36 \fast1$35 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" + switch \ldst_port0_exc_$signal attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1'1 assign { } { } - assign { $1\fast1_ok$next[0:0]$8859 $1\fast1$10$next[63:0]$8858 } { \fast1_ok$36 \fast1$35 } + assign $1\busy_l_r_busy[0:0] 1'1 case - assign $1\fast1$10$next[63:0]$8858 \fast1$10 - assign $1\fast1_ok$next[0:0]$8859 \fast1_ok + assign $1\busy_l_r_busy[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" + switch \cyc_l_q_cyc attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8860 1'0 + assign $2\busy_l_r_busy[0:0] 1'1 case - assign $2\fast1_ok$next[0:0]$8860 $1\fast1_ok$next[0:0]$8859 + assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] end sync always - update \fast1$10$next $0\fast1$10$next[63:0]$8856 - update \fast1_ok$next $0\fast1_ok$next[0:0]$8857 + update \busy_l_r_busy $0\busy_l_r_busy[0:0] end - attribute \src "libresoc.v:166138.3-166156.6" - process $proc$libresoc.v:166138$8861 - assign { } { } + attribute \src "libresoc.v:160269.3-160304.6" + process $proc$libresoc.v:160269$8706 assign { } { } assign { } { } assign { } { } - assign $0\fast2$11$next[63:0]$8862 $1\fast2$11$next[63:0]$8864 assign { } { } - assign $0\fast2_ok$next[0:0]$8863 $2\fast2_ok$next[0:0]$8866 - attribute \src "libresoc.v:166139.5-166139.29" + assign $0\adrok_l_s_addr_acked$next[0:0]$8707 $6\adrok_l_s_addr_acked$next[0:0]$8713 + attribute \src "libresoc.v:160270.5-160270.29" switch \initial - attribute \src "libresoc.v:166139.9-166139.17" + attribute \src "libresoc.v:160270.9-160270.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } + case 1'1 assign { } { } - assign { $1\fast2_ok$next[0:0]$8865 $1\fast2$11$next[63:0]$8864 } { \fast2_ok$38 \fast2$37 } + assign $1\adrok_l_s_addr_acked$next[0:0]$8708 $2\adrok_l_s_addr_acked$next[0:0]$8709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_s_addr_acked$next[0:0]$8709 1'1 + case + assign $2\adrok_l_s_addr_acked$next[0:0]$8709 1'0 + end + case + assign $1\adrok_l_s_addr_acked$next[0:0]$8708 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1'1 assign { } { } - assign { $1\fast2_ok$next[0:0]$8865 $1\fast2$11$next[63:0]$8864 } { \fast2_ok$38 \fast2$37 } + assign $3\adrok_l_s_addr_acked$next[0:0]$8710 $4\adrok_l_s_addr_acked$next[0:0]$8711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\adrok_l_s_addr_acked$next[0:0]$8711 $5\adrok_l_s_addr_acked$next[0:0]$8712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\adrok_l_s_addr_acked$next[0:0]$8712 1'1 + case + assign $5\adrok_l_s_addr_acked$next[0:0]$8712 $1\adrok_l_s_addr_acked$next[0:0]$8708 + end + case + assign $4\adrok_l_s_addr_acked$next[0:0]$8711 $1\adrok_l_s_addr_acked$next[0:0]$8708 + end case - assign $1\fast2$11$next[63:0]$8864 \fast2$11 - assign $1\fast2_ok$next[0:0]$8865 \fast2_ok + assign $3\adrok_l_s_addr_acked$next[0:0]$8710 $1\adrok_l_s_addr_acked$next[0:0]$8708 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$8866 1'0 + assign $6\adrok_l_s_addr_acked$next[0:0]$8713 1'0 case - assign $2\fast2_ok$next[0:0]$8866 $1\fast2_ok$next[0:0]$8865 + assign $6\adrok_l_s_addr_acked$next[0:0]$8713 $3\adrok_l_s_addr_acked$next[0:0]$8710 end sync always - update \fast2$11$next $0\fast2$11$next[63:0]$8862 - update \fast2_ok$next $0\fast2_ok$next[0:0]$8863 + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8707 end - attribute \src "libresoc.v:166157.3-166175.6" - process $proc$libresoc.v:166157$8867 - assign { } { } + attribute \src "libresoc.v:160305.3-160320.6" + process $proc$libresoc.v:160305$8714 assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$8868 $1\nia$next[63:0]$8870 - assign { } { } - assign $0\nia_ok$next[0:0]$8869 $2\nia_ok$next[0:0]$8872 - attribute \src "libresoc.v:166158.5-166158.29" + assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:160306.5-160306.29" switch \initial - attribute \src "libresoc.v:166158.9-166158.17" + attribute \src "libresoc.v:160306.9-160306.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\nia_ok$next[0:0]$8871 $1\nia$next[63:0]$8870 } { \nia_ok$40 \nia$39 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" + switch \reset_delay attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1'1 assign { } { } - assign { $1\nia_ok$next[0:0]$8871 $1\nia$next[63:0]$8870 } { \nia_ok$40 \nia$39 } + assign $1\adrok_l_r_addr_acked[0:0] 1'1 case - assign $1\nia$next[63:0]$8870 \nia - assign $1\nia_ok$next[0:0]$8871 \nia_ok + assign $1\adrok_l_r_addr_acked[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$8872 1'0 + assign $2\adrok_l_r_addr_acked[0:0] 1'1 case - assign $2\nia_ok$next[0:0]$8872 $1\nia_ok$next[0:0]$8871 + assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] end sync always - update \nia$next $0\nia$next[63:0]$8868 - update \nia_ok$next $0\nia_ok$next[0:0]$8869 + update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end - connect \$24 $and$libresoc.v:165990$8801_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } - connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } - connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } - connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } - connect \muxid$26 \main_muxid$12 - connect \p_valid_i_p_ready_o \$24 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$23 \p_valid_i - connect \main_cr_a \cr_a - connect \main_fast2 \fast2 - connect \main_fast1 \fast1 - connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - connect \main_muxid \muxid + connect \$9 $not$libresoc.v:159774$8618_Y + connect \$11 $and$libresoc.v:159775$8619_Y + connect \$13 $not$libresoc.v:159776$8620_Y + connect \$15 $and$libresoc.v:159777$8621_Y + connect \$17 $not$libresoc.v:159778$8622_Y + connect \$1 $and$libresoc.v:159779$8623_Y + connect \$19 $and$libresoc.v:159780$8624_Y + connect \$21 $pos$libresoc.v:159781$8626_Y + connect \$23 $pos$libresoc.v:159782$8628_Y + connect \$25 $and$libresoc.v:159783$8629_Y + connect \$27 $and$libresoc.v:159784$8630_Y + connect \$29 $and$libresoc.v:159785$8631_Y + connect \$31 $and$libresoc.v:159786$8632_Y + connect \$33 $and$libresoc.v:159787$8633_Y + connect \$35 $not$libresoc.v:159788$8634_Y + connect \$38 $or$libresoc.v:159789$8635_Y + connect \$3 $or$libresoc.v:159790$8636_Y + connect \$37 $not$libresoc.v:159791$8637_Y + connect \$42 $and$libresoc.v:159792$8638_Y + connect \$44 $mul$libresoc.v:159793$8639_Y + connect \$46 $sshr$libresoc.v:159794$8640_Y + connect \$48 $and$libresoc.v:159795$8641_Y + connect \$50 $and$libresoc.v:159796$8642_Y + connect \$52 $not$libresoc.v:159797$8643_Y + connect \$54 $and$libresoc.v:159798$8644_Y + connect \$57 $mul$libresoc.v:159799$8645_Y + connect \$5 $not$libresoc.v:159800$8646_Y + connect \$59 $sshl$libresoc.v:159801$8647_Y + connect \$61 $and$libresoc.v:159802$8648_Y + connect \$63 $or$libresoc.v:159803$8649_Y + connect \$65 $and$libresoc.v:159804$8650_Y + connect \$67 $or$libresoc.v:159805$8651_Y + connect \$69 $and$libresoc.v:159806$8652_Y + connect \$71 $not$libresoc.v:159807$8653_Y + connect \$73 $not$libresoc.v:159808$8654_Y + connect \$75 $not$libresoc.v:159809$8655_Y + connect \$77 $and$libresoc.v:159810$8656_Y + connect \$7 $and$libresoc.v:159811$8657_Y + connect \$79 $not$libresoc.v:159812$8658_Y + connect \$81 $not$libresoc.v:159813$8659_Y + connect \$83 $and$libresoc.v:159814$8660_Y + connect \$41 \$46 + connect \$56 \$59 + connect \valid_l_r_valid \lsui_active_rise + connect \lsui_active_rise \$83 + connect \lsui_active \$79 + connect \x_valid_i \valid_l_q_valid + connect \m_valid_i \valid_l_q_valid + connect \x_st_i \ldst_port0_is_st_i + connect \x_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_busy_o \busy_l_q_busy + connect \reset_delay$next \reset_l_q_reset + connect \lddata \$46 [63:0] + connect \st_active_s_st_active \sts_rise + connect \sts_rise \$19 + connect \sts_dly$next \sts + connect \ld_active_s_ld_active \lds_rise + connect \lds_rise \$15 + connect \lds_dly$next \lds + connect \busy_edge \$11 + connect \sts \ldst_port0_is_st_i + connect \lds \ldst_port0_is_ld_i end -attribute \src "libresoc.v:166195.1-167115.10" +attribute \src "libresoc.v:160346.1-161116.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" -module \pipe$64 - attribute \src "libresoc.v:167018.3-167036.6" - wire width 64 $0\fast1$7$next[63:0]$8960 - attribute \src "libresoc.v:166871.3-166872.33" - wire width 64 $0\fast1$7[63:0]$8912 - attribute \src "libresoc.v:166209.14-166209.46" - wire width 64 $0\fast1$7[63:0]$8984 - attribute \src "libresoc.v:167018.3-167036.6" - wire $0\fast1_ok$next[0:0]$8959 - attribute \src "libresoc.v:166873.3-166874.33" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:166196.7-166196.20" +module \pipe + attribute \src "libresoc.v:161079.3-161097.6" + wire width 4 $0\cr_a$6$next[3:0]$8770 + attribute \src "libresoc.v:160943.3-160944.31" + wire width 4 $0\cr_a$6[3:0]$8726 + attribute \src "libresoc.v:160360.13-160360.28" + wire width 4 $0\cr_a$6[3:0]$8776 + attribute \src "libresoc.v:161079.3-161097.6" + wire $0\cr_a_ok$next[0:0]$8769 + attribute \src "libresoc.v:160945.3-160946.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:161026.3-161040.6" + wire width 13 $0\cr_op__fn_unit$3$next[12:0]$8750 + attribute \src "libresoc.v:160957.3-160958.51" + wire width 13 $0\cr_op__fn_unit$3[12:0]$8736 + attribute \src "libresoc.v:160422.14-160422.43" + wire width 13 $0\cr_op__fn_unit$3[12:0]$8779 + attribute \src "libresoc.v:161026.3-161040.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$8751 + attribute \src "libresoc.v:160959.3-160960.45" + wire width 32 $0\cr_op__insn$4[31:0]$8738 + attribute \src "libresoc.v:160431.14-160431.37" + wire width 32 $0\cr_op__insn$4[31:0]$8781 + attribute \src "libresoc.v:161026.3-161040.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$8752 + attribute \src "libresoc.v:160955.3-160956.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$8734 + attribute \src "libresoc.v:160662.13-160662.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$8783 + attribute \src "libresoc.v:161060.3-161078.6" + wire width 32 $0\full_cr$5$next[31:0]$8763 + attribute \src "libresoc.v:160947.3-160948.37" + wire width 32 $0\full_cr$5[31:0]$8729 + attribute \src "libresoc.v:160671.14-160671.33" + wire width 32 $0\full_cr$5[31:0]$8785 + attribute \src "libresoc.v:161060.3-161078.6" + wire $0\full_cr_ok$next[0:0]$8764 + attribute \src "libresoc.v:160949.3-160950.37" + wire $0\full_cr_ok[0:0] + attribute \src "libresoc.v:160347.7-160347.20" wire $0\initial[0:0] - attribute \src "libresoc.v:166951.3-166963.6" - wire width 2 $0\muxid$1$next[1:0]$8935 - attribute \src "libresoc.v:166891.3-166892.33" - wire width 2 $0\muxid$1[1:0]$8928 - attribute \src "libresoc.v:166223.13-166223.29" - wire width 2 $0\muxid$1[1:0]$8987 - attribute \src "libresoc.v:166980.3-166998.6" - wire width 64 $0\o$next[63:0]$8947 - attribute \src "libresoc.v:166879.3-166880.19" + attribute \src "libresoc.v:161013.3-161025.6" + wire width 2 $0\muxid$1$next[1:0]$8747 + attribute \src "libresoc.v:160961.3-160962.33" + wire width 2 $0\muxid$1[1:0]$8740 + attribute \src "libresoc.v:160901.13-160901.29" + wire width 2 $0\muxid$1[1:0]$8788 + attribute \src "libresoc.v:161041.3-161059.6" + wire width 64 $0\o$next[63:0]$8757 + attribute \src "libresoc.v:160951.3-160952.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:166980.3-166998.6" - wire $0\o_ok$next[0:0]$8948 - attribute \src "libresoc.v:166881.3-166882.25" + attribute \src "libresoc.v:161041.3-161059.6" + wire $0\o_ok$next[0:0]$8758 + attribute \src "libresoc.v:160953.3-160954.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:166933.3-166950.6" - wire $0\r_busy$next[0:0]$8931 - attribute \src "libresoc.v:166893.3-166894.29" + attribute \src "libresoc.v:160995.3-161012.6" + wire $0\r_busy$next[0:0]$8743 + attribute \src "libresoc.v:160963.3-160964.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:166999.3-167017.6" - wire width 64 $0\spr1$6$next[63:0]$8953 - attribute \src "libresoc.v:166875.3-166876.31" - wire width 64 $0\spr1$6[63:0]$8915 - attribute \src "libresoc.v:166268.14-166268.45" - wire width 64 $0\spr1$6[63:0]$8992 - attribute \src "libresoc.v:166999.3-167017.6" - wire $0\spr1_ok$next[0:0]$8954 - attribute \src "libresoc.v:166877.3-166878.31" - wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:166964.3-166979.6" - wire width 13 $0\spr_op__fn_unit$3$next[12:0]$8938 - attribute \src "libresoc.v:166885.3-166886.53" - wire width 13 $0\spr_op__fn_unit$3[12:0]$8922 - attribute \src "libresoc.v:166558.14-166558.44" - wire width 13 $0\spr_op__fn_unit$3[12:0]$8995 - attribute \src "libresoc.v:166964.3-166979.6" - wire width 32 $0\spr_op__insn$4$next[31:0]$8939 - attribute \src "libresoc.v:166887.3-166888.47" - wire width 32 $0\spr_op__insn$4[31:0]$8924 - attribute \src "libresoc.v:166567.14-166567.38" - wire width 32 $0\spr_op__insn$4[31:0]$8997 - attribute \src "libresoc.v:166964.3-166979.6" - wire width 7 $0\spr_op__insn_type$2$next[6:0]$8940 - attribute \src "libresoc.v:166883.3-166884.57" - wire width 7 $0\spr_op__insn_type$2[6:0]$8920 - attribute \src "libresoc.v:166722.13-166722.42" - wire width 7 $0\spr_op__insn_type$2[6:0]$8999 - attribute \src "libresoc.v:166964.3-166979.6" - wire $0\spr_op__is_32bit$5$next[0:0]$8941 - attribute \src "libresoc.v:166889.3-166890.55" - wire $0\spr_op__is_32bit$5[0:0]$8926 - attribute \src "libresoc.v:166807.7-166807.34" - wire $0\spr_op__is_32bit$5[0:0]$9001 - attribute \src "libresoc.v:167075.3-167093.6" - wire width 2 $0\xer_ca$10$next[1:0]$8977 - attribute \src "libresoc.v:166859.3-166860.37" - wire width 2 $0\xer_ca$10[1:0]$8903 - attribute \src "libresoc.v:166814.13-166814.31" - wire width 2 $0\xer_ca$10[1:0]$9003 - attribute \src "libresoc.v:167075.3-167093.6" - wire $0\xer_ca_ok$next[0:0]$8978 - attribute \src "libresoc.v:166861.3-166862.35" - wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:167056.3-167074.6" - wire width 2 $0\xer_ov$9$next[1:0]$8972 - attribute \src "libresoc.v:166863.3-166864.35" - wire width 2 $0\xer_ov$9[1:0]$8906 - attribute \src "libresoc.v:166832.13-166832.30" - wire width 2 $0\xer_ov$9[1:0]$9006 - attribute \src "libresoc.v:167056.3-167074.6" - wire $0\xer_ov_ok$next[0:0]$8971 - attribute \src "libresoc.v:166865.3-166866.35" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:167037.3-167055.6" - wire $0\xer_so$8$next[0:0]$8966 - attribute \src "libresoc.v:166867.3-166868.35" - wire $0\xer_so$8[0:0]$8909 - attribute \src "libresoc.v:166848.7-166848.24" - wire $0\xer_so$8[0:0]$9009 - attribute \src "libresoc.v:167037.3-167055.6" - wire $0\xer_so_ok$next[0:0]$8965 - attribute \src "libresoc.v:166869.3-166870.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:167018.3-167036.6" - wire width 64 $1\fast1$7$next[63:0]$8962 - attribute \src "libresoc.v:167018.3-167036.6" - wire $1\fast1_ok$next[0:0]$8961 - attribute \src "libresoc.v:166214.7-166214.22" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:166951.3-166963.6" - wire width 2 $1\muxid$1$next[1:0]$8936 - attribute \src "libresoc.v:166980.3-166998.6" - wire width 64 $1\o$next[63:0]$8949 - attribute \src "libresoc.v:166236.14-166236.38" + attribute \src "libresoc.v:161079.3-161097.6" + wire width 4 $1\cr_a$6$next[3:0]$8772 + attribute \src "libresoc.v:161079.3-161097.6" + wire $1\cr_a_ok$next[0:0]$8771 + attribute \src "libresoc.v:160365.7-160365.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:161026.3-161040.6" + wire width 13 $1\cr_op__fn_unit$3$next[12:0]$8753 + attribute \src "libresoc.v:161026.3-161040.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$8754 + attribute \src "libresoc.v:161026.3-161040.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$8755 + attribute \src "libresoc.v:161060.3-161078.6" + wire width 32 $1\full_cr$5$next[31:0]$8765 + attribute \src "libresoc.v:161060.3-161078.6" + wire $1\full_cr_ok$next[0:0]$8766 + attribute \src "libresoc.v:160676.7-160676.24" + wire $1\full_cr_ok[0:0] + attribute \src "libresoc.v:161013.3-161025.6" + wire width 2 $1\muxid$1$next[1:0]$8748 + attribute \src "libresoc.v:161041.3-161059.6" + wire width 64 $1\o$next[63:0]$8759 + attribute \src "libresoc.v:160914.14-160914.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:166980.3-166998.6" - wire $1\o_ok$next[0:0]$8950 - attribute \src "libresoc.v:166243.7-166243.18" + attribute \src "libresoc.v:161041.3-161059.6" + wire $1\o_ok$next[0:0]$8760 + attribute \src "libresoc.v:160921.7-160921.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:166933.3-166950.6" - wire $1\r_busy$next[0:0]$8932 - attribute \src "libresoc.v:166257.7-166257.20" + attribute \src "libresoc.v:160995.3-161012.6" + wire $1\r_busy$next[0:0]$8744 + attribute \src "libresoc.v:160935.7-160935.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:166999.3-167017.6" - wire width 64 $1\spr1$6$next[63:0]$8955 - attribute \src "libresoc.v:166999.3-167017.6" - wire $1\spr1_ok$next[0:0]$8956 - attribute \src "libresoc.v:166273.7-166273.21" - wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:166964.3-166979.6" - wire width 13 $1\spr_op__fn_unit$3$next[12:0]$8942 - attribute \src "libresoc.v:166964.3-166979.6" - wire width 32 $1\spr_op__insn$4$next[31:0]$8943 - attribute \src "libresoc.v:166964.3-166979.6" - wire width 7 $1\spr_op__insn_type$2$next[6:0]$8944 - attribute \src "libresoc.v:166964.3-166979.6" - wire $1\spr_op__is_32bit$5$next[0:0]$8945 - attribute \src "libresoc.v:167075.3-167093.6" - wire width 2 $1\xer_ca$10$next[1:0]$8979 - attribute \src "libresoc.v:167075.3-167093.6" - wire $1\xer_ca_ok$next[0:0]$8980 - attribute \src "libresoc.v:166821.7-166821.23" - wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:167056.3-167074.6" - wire width 2 $1\xer_ov$9$next[1:0]$8974 - attribute \src "libresoc.v:167056.3-167074.6" - wire $1\xer_ov_ok$next[0:0]$8973 - attribute \src "libresoc.v:166837.7-166837.23" - wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:167037.3-167055.6" - wire $1\xer_so$8$next[0:0]$8968 - attribute \src "libresoc.v:167037.3-167055.6" - wire $1\xer_so_ok$next[0:0]$8967 - attribute \src "libresoc.v:166853.7-166853.23" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:167018.3-167036.6" - wire $2\fast1_ok$next[0:0]$8963 - attribute \src "libresoc.v:166980.3-166998.6" - wire $2\o_ok$next[0:0]$8951 - attribute \src "libresoc.v:166933.3-166950.6" - wire $2\r_busy$next[0:0]$8933 - attribute \src "libresoc.v:166999.3-167017.6" - wire $2\spr1_ok$next[0:0]$8957 - attribute \src "libresoc.v:167075.3-167093.6" - wire $2\xer_ca_ok$next[0:0]$8981 - attribute \src "libresoc.v:167056.3-167074.6" - wire $2\xer_ov_ok$next[0:0]$8975 - attribute \src "libresoc.v:167037.3-167055.6" - wire $2\xer_so_ok$next[0:0]$8969 - attribute \src "libresoc.v:166858.18-166858.118" - wire $and$libresoc.v:166858$8901_Y + attribute \src "libresoc.v:161079.3-161097.6" + wire $2\cr_a_ok$next[0:0]$8773 + attribute \src "libresoc.v:161060.3-161078.6" + wire $2\full_cr_ok$next[0:0]$8767 + attribute \src "libresoc.v:161041.3-161059.6" + wire $2\o_ok$next[0:0]$8761 + attribute \src "libresoc.v:160995.3-161012.6" + wire $2\r_busy$next[0:0]$8745 + attribute \src "libresoc.v:160942.18-160942.118" + wire $and$libresoc.v:160942$8724_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 26 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast1$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 26 \fast1$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast1$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 27 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast1_ok$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast1_ok$next - attribute \src "libresoc.v:166196.7-166196.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 17 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 16 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 15 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \spr1$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 24 \spr1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \spr1$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 25 \spr1_ok + wire width 4 input 11 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr1_ok$32 + wire width 4 \cr_a$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_fast1 + wire width 4 output 24 \cr_a$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \spr_main_fast1$17 + wire width 4 \cr_a$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \spr_main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \spr_main_muxid$11 + wire output 25 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \spr_main_o + wire \cr_a_ok$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_o_ok + wire \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_ra + wire width 4 input 12 \cr_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \spr_main_spr1$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_spr1_ok + wire width 4 input 13 \cr_c attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -342218,7 +334553,7 @@ module \pipe$64 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \spr_main_spr_op__fn_unit + wire width 13 input 6 \cr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -342234,11 +334569,33 @@ module \pipe$64 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \spr_main_spr_op__fn_unit$13 + wire width 13 \cr_op__fn_unit$18 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_main_spr_op__insn + wire width 13 output 18 \cr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_main_spr_op__insn$14 + wire width 13 \cr_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \cr_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -342314,7 +334671,7 @@ module \pipe$64 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_main_spr_op__insn_type + wire width 7 input 5 \cr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -342390,87 +334747,7 @@ module \pipe$64 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_main_spr_op__insn_type$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_main_spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_main_spr_op__is_32bit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \spr_main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \spr_main_xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \spr_main_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \spr_main_xer_ov$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \spr_main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \spr_main_xer_so_ok - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \spr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \spr_op__fn_unit$26 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 19 \spr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \spr_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 20 \spr_op__insn$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$4$next + wire width 7 \cr_op__insn_type$17 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -342546,7 +334823,71 @@ module \pipe$64 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \spr_op__insn_type + wire width 7 output 17 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 10 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \full_cr$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 output 22 \full_cr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \full_cr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \full_cr_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \full_cr_ok$next + attribute \src "libresoc.v:160347.7-160347.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \main_cr_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_cr_op__fn_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn$10 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -342622,9 +334963,7 @@ module \pipe$64 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 18 \spr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$2$next + wire width 7 \main_cr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -342700,399 +335039,296 @@ module \pipe$64 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_op__is_32bit$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \spr_op__is_32bit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_op__is_32bit$5$next + wire width 7 \main_cr_op__insn_type$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 14 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 32 \xer_ca$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$10$next + wire width 32 \main_full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$39 + wire width 32 \main_full_cr$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 33 \xer_ca_ok + wire \main_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$40 + wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$next + wire \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 13 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 30 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 31 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$next + wire width 64 \main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 12 \xer_so + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 15 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 14 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$35 + wire width 64 output 20 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \xer_so$8 + wire width 64 \o$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$8$next + wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 29 \xer_so_ok + wire output 21 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$36 + wire \o_ok$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 8 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:166858$8901 + cell $and $and$libresoc.v:160942$8724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$21 + connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $and$libresoc.v:166858$8901_Y + connect \Y $and$libresoc.v:160942$8724_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:166895.10-166898.4" - cell \n$66 \n + attribute \src "libresoc.v:160965.12-160986.4" + cell \main$9 \main + connect \cr_a \main_cr_a + connect \cr_a$6 \main_cr_a$12 + connect \cr_a_ok \main_cr_a_ok + connect \cr_b \main_cr_b + connect \cr_c \main_cr_c + connect \cr_op__fn_unit \main_cr_op__fn_unit + connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 + connect \cr_op__insn \main_cr_op__insn + connect \cr_op__insn$4 \main_cr_op__insn$10 + connect \cr_op__insn_type \main_cr_op__insn_type + connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 + connect \full_cr \main_full_cr + connect \full_cr$5 \main_full_cr$11 + connect \full_cr_ok \main_full_cr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$7 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:160987.9-160990.4" + cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:166899.10-166902.4" - cell \p$65 \p + attribute \src "libresoc.v:160991.9-160994.4" + cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \module_not_derived 1 - attribute \src "libresoc.v:166903.12-166932.4" - cell \spr_main \spr_main - connect \fast1 \spr_main_fast1 - connect \fast1$7 \spr_main_fast1$17 - connect \fast1_ok \spr_main_fast1_ok - connect \muxid \spr_main_muxid - connect \muxid$1 \spr_main_muxid$11 - connect \o \spr_main_o - connect \o_ok \spr_main_o_ok - connect \ra \spr_main_ra - connect \spr1 \spr_main_spr1 - connect \spr1$6 \spr_main_spr1$16 - connect \spr1_ok \spr_main_spr1_ok - connect \spr_op__fn_unit \spr_main_spr_op__fn_unit - connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 - connect \spr_op__insn \spr_main_spr_op__insn - connect \spr_op__insn$4 \spr_main_spr_op__insn$14 - connect \spr_op__insn_type \spr_main_spr_op__insn_type - connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 - connect \spr_op__is_32bit \spr_main_spr_op__is_32bit - connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 - connect \xer_ca \spr_main_xer_ca - connect \xer_ca$10 \spr_main_xer_ca$20 - connect \xer_ca_ok \spr_main_xer_ca_ok - connect \xer_ov \spr_main_xer_ov - connect \xer_ov$9 \spr_main_xer_ov$19 - connect \xer_ov_ok \spr_main_xer_ov_ok - connect \xer_so \spr_main_xer_so - connect \xer_so$8 \spr_main_xer_so$18 - connect \xer_so_ok \spr_main_xer_so_ok - end - attribute \src "libresoc.v:166196.7-166196.20" - process $proc$libresoc.v:166196$8982 + attribute \src "libresoc.v:160347.7-160347.20" + process $proc$libresoc.v:160347$8774 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:166209.14-166209.46" - process $proc$libresoc.v:166209$8983 - assign { } { } - assign $0\fast1$7[63:0]$8984 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast1$7 $0\fast1$7[63:0]$8984 - end - attribute \src "libresoc.v:166214.7-166214.22" - process $proc$libresoc.v:166214$8985 - assign { } { } - assign $1\fast1_ok[0:0] 1'0 - sync always - sync init - update \fast1_ok $1\fast1_ok[0:0] - end - attribute \src "libresoc.v:166223.13-166223.29" - process $proc$libresoc.v:166223$8986 - assign { } { } - assign $0\muxid$1[1:0]$8987 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8987 - end - attribute \src "libresoc.v:166236.14-166236.38" - process $proc$libresoc.v:166236$8988 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:166243.7-166243.18" - process $proc$libresoc.v:166243$8989 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:166257.7-166257.20" - process $proc$libresoc.v:166257$8990 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:166268.14-166268.45" - process $proc$libresoc.v:166268$8991 - assign { } { } - assign $0\spr1$6[63:0]$8992 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \spr1$6 $0\spr1$6[63:0]$8992 - end - attribute \src "libresoc.v:166273.7-166273.21" - process $proc$libresoc.v:166273$8993 + attribute \src "libresoc.v:160360.13-160360.28" + process $proc$libresoc.v:160360$8775 assign { } { } - assign $1\spr1_ok[0:0] 1'0 + assign $0\cr_a$6[3:0]$8776 4'0000 sync always sync init - update \spr1_ok $1\spr1_ok[0:0] + update \cr_a$6 $0\cr_a$6[3:0]$8776 end - attribute \src "libresoc.v:166558.14-166558.44" - process $proc$libresoc.v:166558$8994 + attribute \src "libresoc.v:160365.7-160365.21" + process $proc$libresoc.v:160365$8777 assign { } { } - assign $0\spr_op__fn_unit$3[12:0]$8995 13'0000000000000 + assign $1\cr_a_ok[0:0] 1'0 sync always sync init - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8995 + update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:166567.14-166567.38" - process $proc$libresoc.v:166567$8996 + attribute \src "libresoc.v:160422.14-160422.43" + process $proc$libresoc.v:160422$8778 assign { } { } - assign $0\spr_op__insn$4[31:0]$8997 0 + assign $0\cr_op__fn_unit$3[12:0]$8779 13'0000000000000 sync always sync init - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8997 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8779 end - attribute \src "libresoc.v:166722.13-166722.42" - process $proc$libresoc.v:166722$8998 + attribute \src "libresoc.v:160431.14-160431.37" + process $proc$libresoc.v:160431$8780 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8999 7'0000000 + assign $0\cr_op__insn$4[31:0]$8781 0 sync always sync init - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8999 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8781 end - attribute \src "libresoc.v:166807.7-166807.34" - process $proc$libresoc.v:166807$9000 + attribute \src "libresoc.v:160662.13-160662.41" + process $proc$libresoc.v:160662$8782 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$9001 1'0 + assign $0\cr_op__insn_type$2[6:0]$8783 7'0000000 sync always sync init - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$9001 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8783 end - attribute \src "libresoc.v:166814.13-166814.31" - process $proc$libresoc.v:166814$9002 + attribute \src "libresoc.v:160671.14-160671.33" + process $proc$libresoc.v:160671$8784 assign { } { } - assign $0\xer_ca$10[1:0]$9003 2'00 + assign $0\full_cr$5[31:0]$8785 0 sync always sync init - update \xer_ca$10 $0\xer_ca$10[1:0]$9003 + update \full_cr$5 $0\full_cr$5[31:0]$8785 end - attribute \src "libresoc.v:166821.7-166821.23" - process $proc$libresoc.v:166821$9004 + attribute \src "libresoc.v:160676.7-160676.24" + process $proc$libresoc.v:160676$8786 assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 + assign $1\full_cr_ok[0:0] 1'0 sync always sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] + update \full_cr_ok $1\full_cr_ok[0:0] end - attribute \src "libresoc.v:166832.13-166832.30" - process $proc$libresoc.v:166832$9005 + attribute \src "libresoc.v:160901.13-160901.29" + process $proc$libresoc.v:160901$8787 assign { } { } - assign $0\xer_ov$9[1:0]$9006 2'00 + assign $0\muxid$1[1:0]$8788 2'00 sync always sync init - update \xer_ov$9 $0\xer_ov$9[1:0]$9006 + update \muxid$1 $0\muxid$1[1:0]$8788 end - attribute \src "libresoc.v:166837.7-166837.23" - process $proc$libresoc.v:166837$9007 + attribute \src "libresoc.v:160914.14-160914.38" + process $proc$libresoc.v:160914$8789 assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] + update \o $1\o[63:0] end - attribute \src "libresoc.v:166848.7-166848.24" - process $proc$libresoc.v:166848$9008 + attribute \src "libresoc.v:160921.7-160921.18" + process $proc$libresoc.v:160921$8790 assign { } { } - assign $0\xer_so$8[0:0]$9009 1'0 + assign $1\o_ok[0:0] 1'0 sync always sync init - update \xer_so$8 $0\xer_so$8[0:0]$9009 + update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:166853.7-166853.23" - process $proc$libresoc.v:166853$9010 + attribute \src "libresoc.v:160935.7-160935.20" + process $proc$libresoc.v:160935$8791 assign { } { } - assign $1\xer_so_ok[0:0] 1'0 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:166859.3-166860.37" - process $proc$libresoc.v:166859$8902 - assign { } { } - assign $0\xer_ca$10[1:0]$8903 \xer_ca$10$next - sync posedge \coresync_clk - update \xer_ca$10 $0\xer_ca$10[1:0]$8903 - end - attribute \src "libresoc.v:166861.3-166862.35" - process $proc$libresoc.v:166861$8904 - assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:166863.3-166864.35" - process $proc$libresoc.v:166863$8905 - assign { } { } - assign $0\xer_ov$9[1:0]$8906 \xer_ov$9$next - sync posedge \coresync_clk - update \xer_ov$9 $0\xer_ov$9[1:0]$8906 - end - attribute \src "libresoc.v:166865.3-166866.35" - process $proc$libresoc.v:166865$8907 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:166867.3-166868.35" - process $proc$libresoc.v:166867$8908 - assign { } { } - assign $0\xer_so$8[0:0]$8909 \xer_so$8$next - sync posedge \coresync_clk - update \xer_so$8 $0\xer_so$8[0:0]$8909 - end - attribute \src "libresoc.v:166869.3-166870.35" - process $proc$libresoc.v:166869$8910 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:166871.3-166872.33" - process $proc$libresoc.v:166871$8911 + attribute \src "libresoc.v:160943.3-160944.31" + process $proc$libresoc.v:160943$8725 assign { } { } - assign $0\fast1$7[63:0]$8912 \fast1$7$next + assign $0\cr_a$6[3:0]$8726 \cr_a$6$next sync posedge \coresync_clk - update \fast1$7 $0\fast1$7[63:0]$8912 + update \cr_a$6 $0\cr_a$6[3:0]$8726 end - attribute \src "libresoc.v:166873.3-166874.33" - process $proc$libresoc.v:166873$8913 + attribute \src "libresoc.v:160945.3-160946.31" + process $proc$libresoc.v:160945$8727 assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next + assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] + update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:166875.3-166876.31" - process $proc$libresoc.v:166875$8914 + attribute \src "libresoc.v:160947.3-160948.37" + process $proc$libresoc.v:160947$8728 assign { } { } - assign $0\spr1$6[63:0]$8915 \spr1$6$next + assign $0\full_cr$5[31:0]$8729 \full_cr$5$next sync posedge \coresync_clk - update \spr1$6 $0\spr1$6[63:0]$8915 + update \full_cr$5 $0\full_cr$5[31:0]$8729 end - attribute \src "libresoc.v:166877.3-166878.31" - process $proc$libresoc.v:166877$8916 + attribute \src "libresoc.v:160949.3-160950.37" + process $proc$libresoc.v:160949$8730 assign { } { } - assign $0\spr1_ok[0:0] \spr1_ok$next + assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk - update \spr1_ok $0\spr1_ok[0:0] + update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:166879.3-166880.19" - process $proc$libresoc.v:166879$8917 + attribute \src "libresoc.v:160951.3-160952.19" + process $proc$libresoc.v:160951$8731 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:166881.3-166882.25" - process $proc$libresoc.v:166881$8918 + attribute \src "libresoc.v:160953.3-160954.25" + process $proc$libresoc.v:160953$8732 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:166883.3-166884.57" - process $proc$libresoc.v:166883$8919 - assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8920 \spr_op__insn_type$2$next - sync posedge \coresync_clk - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8920 - end - attribute \src "libresoc.v:166885.3-166886.53" - process $proc$libresoc.v:166885$8921 + attribute \src "libresoc.v:160955.3-160956.55" + process $proc$libresoc.v:160955$8733 assign { } { } - assign $0\spr_op__fn_unit$3[12:0]$8922 \spr_op__fn_unit$3$next + assign $0\cr_op__insn_type$2[6:0]$8734 \cr_op__insn_type$2$next sync posedge \coresync_clk - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8922 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8734 end - attribute \src "libresoc.v:166887.3-166888.47" - process $proc$libresoc.v:166887$8923 + attribute \src "libresoc.v:160957.3-160958.51" + process $proc$libresoc.v:160957$8735 assign { } { } - assign $0\spr_op__insn$4[31:0]$8924 \spr_op__insn$4$next + assign $0\cr_op__fn_unit$3[12:0]$8736 \cr_op__fn_unit$3$next sync posedge \coresync_clk - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8924 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8736 end - attribute \src "libresoc.v:166889.3-166890.55" - process $proc$libresoc.v:166889$8925 + attribute \src "libresoc.v:160959.3-160960.45" + process $proc$libresoc.v:160959$8737 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8926 \spr_op__is_32bit$5$next + assign $0\cr_op__insn$4[31:0]$8738 \cr_op__insn$4$next sync posedge \coresync_clk - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8926 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8738 end - attribute \src "libresoc.v:166891.3-166892.33" - process $proc$libresoc.v:166891$8927 + attribute \src "libresoc.v:160961.3-160962.33" + process $proc$libresoc.v:160961$8739 assign { } { } - assign $0\muxid$1[1:0]$8928 \muxid$1$next + assign $0\muxid$1[1:0]$8740 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8928 + update \muxid$1 $0\muxid$1[1:0]$8740 end - attribute \src "libresoc.v:166893.3-166894.29" - process $proc$libresoc.v:166893$8929 + attribute \src "libresoc.v:160963.3-160964.29" + process $proc$libresoc.v:160963$8741 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:166933.3-166950.6" - process $proc$libresoc.v:166933$8930 + attribute \src "libresoc.v:160995.3-161012.6" + process $proc$libresoc.v:160995$8742 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8931 $2\r_busy$next[0:0]$8933 - attribute \src "libresoc.v:166934.5-166934.29" + assign $0\r_busy$next[0:0]$8743 $2\r_busy$next[0:0]$8745 + attribute \src "libresoc.v:160996.5-160996.29" switch \initial - attribute \src "libresoc.v:166934.9-166934.17" + attribute \src "libresoc.v:160996.9-160996.17" case 1'1 case end @@ -343101,70 +335337,34 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8932 1'1 + assign $1\r_busy$next[0:0]$8744 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8932 1'0 + assign $1\r_busy$next[0:0]$8744 1'0 case - assign $1\r_busy$next[0:0]$8932 \r_busy + assign $1\r_busy$next[0:0]$8744 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8933 1'0 - case - assign $2\r_busy$next[0:0]$8933 $1\r_busy$next[0:0]$8932 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8931 - end - attribute \src "libresoc.v:166951.3-166963.6" - process $proc$libresoc.v:166951$8934 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$8935 $1\muxid$1$next[1:0]$8936 - attribute \src "libresoc.v:166952.5-166952.29" - switch \initial - attribute \src "libresoc.v:166952.9-166952.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$8936 \muxid$24 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$8936 \muxid$24 + assign $2\r_busy$next[0:0]$8745 1'0 case - assign $1\muxid$1$next[1:0]$8936 \muxid$1 + assign $2\r_busy$next[0:0]$8745 $1\r_busy$next[0:0]$8744 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8935 + update \r_busy$next $0\r_busy$next[0:0]$8743 end - attribute \src "libresoc.v:166964.3-166979.6" - process $proc$libresoc.v:166964$8937 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:161013.3-161025.6" + process $proc$libresoc.v:161013$8746 assign { } { } assign { } { } - assign { } { } - assign $0\spr_op__fn_unit$3$next[12:0]$8938 $1\spr_op__fn_unit$3$next[12:0]$8942 - assign $0\spr_op__insn$4$next[31:0]$8939 $1\spr_op__insn$4$next[31:0]$8943 - assign $0\spr_op__insn_type$2$next[6:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8944 - assign $0\spr_op__is_32bit$5$next[0:0]$8941 $1\spr_op__is_32bit$5$next[0:0]$8945 - attribute \src "libresoc.v:166965.5-166965.29" + assign $0\muxid$1$next[1:0]$8747 $1\muxid$1$next[1:0]$8748 + attribute \src "libresoc.v:161014.5-161014.29" switch \initial - attribute \src "libresoc.v:166965.9-166965.17" + attribute \src "libresoc.v:161014.9-161014.17" case 1'1 case end @@ -343173,85 +335373,31 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8945 $1\spr_op__insn$4$next[31:0]$8943 $1\spr_op__fn_unit$3$next[12:0]$8942 $1\spr_op__insn_type$2$next[6:0]$8944 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign $1\muxid$1$next[1:0]$8748 \muxid$16 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8945 $1\spr_op__insn$4$next[31:0]$8943 $1\spr_op__fn_unit$3$next[12:0]$8942 $1\spr_op__insn_type$2$next[6:0]$8944 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign $1\muxid$1$next[1:0]$8748 \muxid$16 case - assign $1\spr_op__fn_unit$3$next[12:0]$8942 \spr_op__fn_unit$3 - assign $1\spr_op__insn$4$next[31:0]$8943 \spr_op__insn$4 - assign $1\spr_op__insn_type$2$next[6:0]$8944 \spr_op__insn_type$2 - assign $1\spr_op__is_32bit$5$next[0:0]$8945 \spr_op__is_32bit$5 + assign $1\muxid$1$next[1:0]$8748 \muxid$1 end sync always - update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[12:0]$8938 - update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8939 - update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8940 - update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8941 + update \muxid$1$next $0\muxid$1$next[1:0]$8747 end - attribute \src "libresoc.v:166980.3-166998.6" - process $proc$libresoc.v:166980$8946 - assign { } { } + attribute \src "libresoc.v:161026.3-161040.6" + process $proc$libresoc.v:161026$8749 assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$8947 $1\o$next[63:0]$8949 - assign { } { } - assign $0\o_ok$next[0:0]$8948 $2\o_ok$next[0:0]$8951 - attribute \src "libresoc.v:166981.5-166981.29" - switch \initial - attribute \src "libresoc.v:166981.9-166981.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8950 $1\o$next[63:0]$8949 } { \o_ok$30 \o$29 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$8950 $1\o$next[63:0]$8949 } { \o_ok$30 \o$29 } - case - assign $1\o$next[63:0]$8949 \o - assign $1\o_ok$next[0:0]$8950 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$8951 1'0 - case - assign $2\o_ok$next[0:0]$8951 $1\o_ok$next[0:0]$8950 - end - sync always - update \o$next $0\o$next[63:0]$8947 - update \o_ok$next $0\o_ok$next[0:0]$8948 - end - attribute \src "libresoc.v:166999.3-167017.6" - process $proc$libresoc.v:166999$8952 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\spr1$6$next[63:0]$8953 $1\spr1$6$next[63:0]$8955 assign { } { } - assign $0\spr1_ok$next[0:0]$8954 $2\spr1_ok$next[0:0]$8957 - attribute \src "libresoc.v:167000.5-167000.29" + assign $0\cr_op__fn_unit$3$next[12:0]$8750 $1\cr_op__fn_unit$3$next[12:0]$8753 + assign $0\cr_op__insn$4$next[31:0]$8751 $1\cr_op__insn$4$next[31:0]$8754 + assign $0\cr_op__insn_type$2$next[6:0]$8752 $1\cr_op__insn_type$2$next[6:0]$8755 + attribute \src "libresoc.v:161027.5-161027.29" switch \initial - attribute \src "libresoc.v:167000.9-167000.17" + attribute \src "libresoc.v:161027.9-161027.17" case 1'1 case end @@ -343260,86 +335406,37 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\spr1_ok$next[0:0]$8956 $1\spr1$6$next[63:0]$8955 } { \spr1_ok$32 \spr1$31 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\spr1_ok$next[0:0]$8956 $1\spr1$6$next[63:0]$8955 } { \spr1_ok$32 \spr1$31 } - case - assign $1\spr1$6$next[63:0]$8955 \spr1$6 - assign $1\spr1_ok$next[0:0]$8956 \spr1_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\spr1_ok$next[0:0]$8957 1'0 - case - assign $2\spr1_ok$next[0:0]$8957 $1\spr1_ok$next[0:0]$8956 - end - sync always - update \spr1$6$next $0\spr1$6$next[63:0]$8953 - update \spr1_ok$next $0\spr1_ok$next[0:0]$8954 - end - attribute \src "libresoc.v:167018.3-167036.6" - process $proc$libresoc.v:167018$8958 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast1$7$next[63:0]$8960 $1\fast1$7$next[63:0]$8962 - assign $0\fast1_ok$next[0:0]$8959 $2\fast1_ok$next[0:0]$8963 - attribute \src "libresoc.v:167019.5-167019.29" - switch \initial - attribute \src "libresoc.v:167019.9-167019.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8961 $1\fast1$7$next[63:0]$8962 } { \fast1_ok$34 \fast1$33 } + assign { $1\cr_op__insn$4$next[31:0]$8754 $1\cr_op__fn_unit$3$next[12:0]$8753 $1\cr_op__insn_type$2$next[6:0]$8755 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8961 $1\fast1$7$next[63:0]$8962 } { \fast1_ok$34 \fast1$33 } - case - assign $1\fast1_ok$next[0:0]$8961 \fast1_ok - assign $1\fast1$7$next[63:0]$8962 \fast1$7 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8963 1'0 + assign { $1\cr_op__insn$4$next[31:0]$8754 $1\cr_op__fn_unit$3$next[12:0]$8753 $1\cr_op__insn_type$2$next[6:0]$8755 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } case - assign $2\fast1_ok$next[0:0]$8963 $1\fast1_ok$next[0:0]$8961 + assign $1\cr_op__fn_unit$3$next[12:0]$8753 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8754 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8755 \cr_op__insn_type$2 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$8959 - update \fast1$7$next $0\fast1$7$next[63:0]$8960 + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[12:0]$8750 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8751 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8752 end - attribute \src "libresoc.v:167037.3-167055.6" - process $proc$libresoc.v:167037$8964 + attribute \src "libresoc.v:161041.3-161059.6" + process $proc$libresoc.v:161041$8756 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\o$next[63:0]$8757 $1\o$next[63:0]$8759 assign { } { } - assign $0\xer_so$8$next[0:0]$8966 $1\xer_so$8$next[0:0]$8968 - assign $0\xer_so_ok$next[0:0]$8965 $2\xer_so_ok$next[0:0]$8969 - attribute \src "libresoc.v:167038.5-167038.29" + assign $0\o_ok$next[0:0]$8758 $2\o_ok$next[0:0]$8761 + attribute \src "libresoc.v:161042.5-161042.29" switch \initial - attribute \src "libresoc.v:167038.9-167038.17" + attribute \src "libresoc.v:161042.9-161042.17" case 1'1 case end @@ -343349,41 +335446,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8967 $1\xer_so$8$next[0:0]$8968 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\o_ok$next[0:0]$8760 $1\o$next[63:0]$8759 } { \o_ok$21 \o$20 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8967 $1\xer_so$8$next[0:0]$8968 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\o_ok$next[0:0]$8760 $1\o$next[63:0]$8759 } { \o_ok$21 \o$20 } case - assign $1\xer_so_ok$next[0:0]$8967 \xer_so_ok - assign $1\xer_so$8$next[0:0]$8968 \xer_so$8 + assign $1\o$next[63:0]$8759 \o + assign $1\o_ok$next[0:0]$8760 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8969 1'0 + assign $2\o_ok$next[0:0]$8761 1'0 case - assign $2\xer_so_ok$next[0:0]$8969 $1\xer_so_ok$next[0:0]$8967 + assign $2\o_ok$next[0:0]$8761 $1\o_ok$next[0:0]$8760 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8965 - update \xer_so$8$next $0\xer_so$8$next[0:0]$8966 + update \o$next $0\o$next[63:0]$8757 + update \o_ok$next $0\o_ok$next[0:0]$8758 end - attribute \src "libresoc.v:167056.3-167074.6" - process $proc$libresoc.v:167056$8970 + attribute \src "libresoc.v:161060.3-161078.6" + process $proc$libresoc.v:161060$8762 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\full_cr$5$next[31:0]$8763 $1\full_cr$5$next[31:0]$8765 assign { } { } - assign $0\xer_ov$9$next[1:0]$8972 $1\xer_ov$9$next[1:0]$8974 - assign $0\xer_ov_ok$next[0:0]$8971 $2\xer_ov_ok$next[0:0]$8975 - attribute \src "libresoc.v:167057.5-167057.29" + assign $0\full_cr_ok$next[0:0]$8764 $2\full_cr_ok$next[0:0]$8767 + attribute \src "libresoc.v:161061.5-161061.29" switch \initial - attribute \src "libresoc.v:167057.9-167057.17" + attribute \src "libresoc.v:161061.9-161061.17" case 1'1 case end @@ -343393,41 +335490,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8973 $1\xer_ov$9$next[1:0]$8974 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\full_cr_ok$next[0:0]$8766 $1\full_cr$5$next[31:0]$8765 } { \full_cr_ok$23 \full_cr$22 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8973 $1\xer_ov$9$next[1:0]$8974 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\full_cr_ok$next[0:0]$8766 $1\full_cr$5$next[31:0]$8765 } { \full_cr_ok$23 \full_cr$22 } case - assign $1\xer_ov_ok$next[0:0]$8973 \xer_ov_ok - assign $1\xer_ov$9$next[1:0]$8974 \xer_ov$9 + assign $1\full_cr$5$next[31:0]$8765 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8766 \full_cr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8975 1'0 + assign $2\full_cr_ok$next[0:0]$8767 1'0 case - assign $2\xer_ov_ok$next[0:0]$8975 $1\xer_ov_ok$next[0:0]$8973 + assign $2\full_cr_ok$next[0:0]$8767 $1\full_cr_ok$next[0:0]$8766 end sync always - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8971 - update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8972 + update \full_cr$5$next $0\full_cr$5$next[31:0]$8763 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8764 end - attribute \src "libresoc.v:167075.3-167093.6" - process $proc$libresoc.v:167075$8976 + attribute \src "libresoc.v:161079.3-161097.6" + process $proc$libresoc.v:161079$8768 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$10$next[1:0]$8977 $1\xer_ca$10$next[1:0]$8979 assign { } { } - assign $0\xer_ca_ok$next[0:0]$8978 $2\xer_ca_ok$next[0:0]$8981 - attribute \src "libresoc.v:167076.5-167076.29" + assign $0\cr_a$6$next[3:0]$8770 $1\cr_a$6$next[3:0]$8772 + assign $0\cr_a_ok$next[0:0]$8769 $2\cr_a_ok$next[0:0]$8773 + attribute \src "libresoc.v:161080.5-161080.29" switch \initial - attribute \src "libresoc.v:167076.9-167076.17" + attribute \src "libresoc.v:161080.9-161080.17" case 1'1 case end @@ -343437,335 +335534,208 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8980 $1\xer_ca$10$next[1:0]$8979 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\cr_a_ok$next[0:0]$8771 $1\cr_a$6$next[3:0]$8772 } { \cr_a_ok$25 \cr_a$24 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8980 $1\xer_ca$10$next[1:0]$8979 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\cr_a_ok$next[0:0]$8771 $1\cr_a$6$next[3:0]$8772 } { \cr_a_ok$25 \cr_a$24 } case - assign $1\xer_ca$10$next[1:0]$8979 \xer_ca$10 - assign $1\xer_ca_ok$next[0:0]$8980 \xer_ca_ok + assign $1\cr_a_ok$next[0:0]$8771 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8772 \cr_a$6 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8981 1'0 + assign $2\cr_a_ok$next[0:0]$8773 1'0 case - assign $2\xer_ca_ok$next[0:0]$8981 $1\xer_ca_ok$next[0:0]$8980 + assign $2\cr_a_ok$next[0:0]$8773 $1\cr_a_ok$next[0:0]$8771 end sync always - update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8977 - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8978 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8769 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8770 end - connect \$22 $and$libresoc.v:166858$8901_Y + connect \$14 $and$libresoc.v:160942$8724_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } - connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } - connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } - connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } - connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } - connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } - connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } - connect \muxid$24 \spr_main_muxid$11 - connect \p_valid_i_p_ready_o \$22 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$21 \p_valid_i - connect \spr_main_xer_ca \xer_ca - connect \spr_main_xer_ov \xer_ov - connect \spr_main_xer_so \xer_so - connect \spr_main_fast1 \fast1 - connect \spr_main_spr1 \spr1 - connect \spr_main_ra \ra - connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - connect \spr_main_muxid \muxid -end -attribute \src "libresoc.v:167119.1-168597.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" -attribute \generator "nMigen" -module \pipe1 - attribute \src "libresoc.v:168511.3-168552.6" - wire width 4 $0\alu_op__data_len$next[3:0]$9074 - attribute \src "libresoc.v:168287.3-168288.49" - wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 13 $0\alu_op__fn_unit$next[12:0]$9075 - attribute \src "libresoc.v:168257.3-168258.47" - wire width 13 $0\alu_op__fn_unit[12:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 64 $0\alu_op__imm_data__data$next[63:0]$9076 - attribute \src "libresoc.v:168259.3-168260.61" - wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__imm_data__ok$next[0:0]$9077 - attribute \src "libresoc.v:168261.3-168262.57" - wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 2 $0\alu_op__input_carry$next[1:0]$9078 - attribute \src "libresoc.v:168279.3-168280.55" - wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 32 $0\alu_op__insn$next[31:0]$9079 - attribute \src "libresoc.v:168289.3-168290.41" - wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 7 $0\alu_op__insn_type$next[6:0]$9080 - attribute \src "libresoc.v:168255.3-168256.51" - wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__invert_in$next[0:0]$9081 - attribute \src "libresoc.v:168271.3-168272.51" - wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__invert_out$next[0:0]$9082 - attribute \src "libresoc.v:168275.3-168276.53" - wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__is_32bit$next[0:0]$9083 - attribute \src "libresoc.v:168283.3-168284.49" - wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__is_signed$next[0:0]$9084 - attribute \src "libresoc.v:168285.3-168286.51" - wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__oe__oe$next[0:0]$9085 - attribute \src "libresoc.v:168267.3-168268.45" - wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__oe__ok$next[0:0]$9086 - attribute \src "libresoc.v:168269.3-168270.45" - wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__output_carry$next[0:0]$9087 - attribute \src "libresoc.v:168281.3-168282.57" - wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__rc__ok$next[0:0]$9088 - attribute \src "libresoc.v:168265.3-168266.45" - wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__rc__rc$next[0:0]$9089 - attribute \src "libresoc.v:168263.3-168264.45" - wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__write_cr0$next[0:0]$9090 - attribute \src "libresoc.v:168277.3-168278.51" - wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $0\alu_op__zero_a$next[0:0]$9091 - attribute \src "libresoc.v:168273.3-168274.45" - wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:168404.3-168422.6" - wire width 4 $0\cr_a$next[3:0]$9043 - attribute \src "libresoc.v:168247.3-168248.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:168404.3-168422.6" - wire $0\cr_a_ok$next[0:0]$9044 - attribute \src "libresoc.v:168249.3-168250.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:167120.7-167120.20" + connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } + connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } + connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } + connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } + connect \muxid$16 \main_muxid$7 + connect \p_valid_i_p_ready_o \$14 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$13 \p_valid_i + connect \main_cr_c \cr_c + connect \main_cr_b \cr_b + connect \main_cr_a \cr_a + connect \main_full_cr \full_cr + connect \main_rb \rb + connect \main_ra \ra + connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:161120.1-161970.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" +attribute \generator "nMigen" +module \pipe$19 + attribute \src "libresoc.v:161870.3-161897.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8828 + attribute \src "libresoc.v:161782.3-161783.43" + wire width 64 $0\br_op__cia$2[63:0]$8802 + attribute \src "libresoc.v:161128.14-161128.51" + wire width 64 $0\br_op__cia$2[63:0]$8866 + attribute \src "libresoc.v:161870.3-161897.6" + wire width 13 $0\br_op__fn_unit$4$next[12:0]$8829 + attribute \src "libresoc.v:161786.3-161787.51" + wire width 13 $0\br_op__fn_unit$4[12:0]$8806 + attribute \src "libresoc.v:161181.14-161181.43" + wire width 13 $0\br_op__fn_unit$4[12:0]$8868 + attribute \src "libresoc.v:161870.3-161897.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8830 + attribute \src "libresoc.v:161790.3-161791.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8810 + attribute \src "libresoc.v:161190.14-161190.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8870 + attribute \src "libresoc.v:161870.3-161897.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8831 + attribute \src "libresoc.v:161792.3-161793.61" + wire $0\br_op__imm_data__ok$7[0:0]$8812 + attribute \src "libresoc.v:161199.7-161199.37" + wire $0\br_op__imm_data__ok$7[0:0]$8872 + attribute \src "libresoc.v:161870.3-161897.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8832 + attribute \src "libresoc.v:161788.3-161789.45" + wire width 32 $0\br_op__insn$5[31:0]$8808 + attribute \src "libresoc.v:161208.14-161208.37" + wire width 32 $0\br_op__insn$5[31:0]$8874 + attribute \src "libresoc.v:161870.3-161897.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8833 + attribute \src "libresoc.v:161784.3-161785.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8804 + attribute \src "libresoc.v:161439.13-161439.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8876 + attribute \src "libresoc.v:161870.3-161897.6" + wire $0\br_op__is_32bit$9$next[0:0]$8834 + attribute \src "libresoc.v:161796.3-161797.53" + wire $0\br_op__is_32bit$9[0:0]$8816 + attribute \src "libresoc.v:161448.7-161448.33" + wire $0\br_op__is_32bit$9[0:0]$8878 + attribute \src "libresoc.v:161870.3-161897.6" + wire $0\br_op__lk$8$next[0:0]$8835 + attribute \src "libresoc.v:161794.3-161795.41" + wire $0\br_op__lk$8[0:0]$8814 + attribute \src "libresoc.v:161457.7-161457.27" + wire $0\br_op__lk$8[0:0]$8880 + attribute \src "libresoc.v:161898.3-161916.6" + wire width 64 $0\fast1$10$next[63:0]$8847 + attribute \src "libresoc.v:161778.3-161779.35" + wire width 64 $0\fast1$10[63:0]$8799 + attribute \src "libresoc.v:161470.14-161470.47" + wire width 64 $0\fast1$10[63:0]$8882 + attribute \src "libresoc.v:161898.3-161916.6" + wire $0\fast1_ok$next[0:0]$8848 + attribute \src "libresoc.v:161780.3-161781.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:161917.3-161935.6" + wire width 64 $0\fast2$11$next[63:0]$8853 + attribute \src "libresoc.v:161774.3-161775.35" + wire width 64 $0\fast2$11[63:0]$8796 + attribute \src "libresoc.v:161486.14-161486.47" + wire width 64 $0\fast2$11[63:0]$8885 + attribute \src "libresoc.v:161917.3-161935.6" + wire $0\fast2_ok$next[0:0]$8854 + attribute \src "libresoc.v:161776.3-161777.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:161121.7-161121.20" wire $0\initial[0:0] - attribute \src "libresoc.v:168498.3-168510.6" - wire width 2 $0\muxid$next[1:0]$9071 - attribute \src "libresoc.v:168291.3-168292.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:168553.3-168571.6" - wire width 64 $0\o$next[63:0]$9117 - attribute \src "libresoc.v:168251.3-168252.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:168553.3-168571.6" - wire $0\o_ok$next[0:0]$9118 - attribute \src "libresoc.v:168253.3-168254.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:168480.3-168497.6" - wire $0\r_busy$next[0:0]$9067 - attribute \src "libresoc.v:168293.3-168294.29" + attribute \src "libresoc.v:161857.3-161869.6" + wire width 2 $0\muxid$1$next[1:0]$8825 + attribute \src "libresoc.v:161798.3-161799.33" + wire width 2 $0\muxid$1[1:0]$8818 + attribute \src "libresoc.v:161732.13-161732.29" + wire width 2 $0\muxid$1[1:0]$8888 + attribute \src "libresoc.v:161936.3-161954.6" + wire width 64 $0\nia$next[63:0]$8859 + attribute \src "libresoc.v:161770.3-161771.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:161936.3-161954.6" + wire $0\nia_ok$next[0:0]$8860 + attribute \src "libresoc.v:161772.3-161773.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:161839.3-161856.6" + wire $0\r_busy$next[0:0]$8821 + attribute \src "libresoc.v:161800.3-161801.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:168423.3-168441.6" - wire width 2 $0\xer_ca$next[1:0]$9050 - attribute \src "libresoc.v:168243.3-168244.29" - wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:168423.3-168441.6" - wire $0\xer_ca_ok$next[0:0]$9049 - attribute \src "libresoc.v:168245.3-168246.35" - wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:168442.3-168460.6" - wire width 2 $0\xer_ov$next[1:0]$9055 - attribute \src "libresoc.v:168239.3-168240.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:168442.3-168460.6" - wire $0\xer_ov_ok$next[0:0]$9056 - attribute \src "libresoc.v:168241.3-168242.35" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:168461.3-168479.6" - wire $0\xer_so$next[0:0]$9061 - attribute \src "libresoc.v:168235.3-168236.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:168461.3-168479.6" - wire $0\xer_so_ok$next[0:0]$9062 - attribute \src "libresoc.v:168237.3-168238.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 4 $1\alu_op__data_len$next[3:0]$9092 - attribute \src "libresoc.v:167125.13-167125.36" - wire width 4 $1\alu_op__data_len[3:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 13 $1\alu_op__fn_unit$next[12:0]$9093 - attribute \src "libresoc.v:167148.14-167148.40" - wire width 13 $1\alu_op__fn_unit[12:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 64 $1\alu_op__imm_data__data$next[63:0]$9094 - attribute \src "libresoc.v:167185.14-167185.59" - wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__imm_data__ok$next[0:0]$9095 - attribute \src "libresoc.v:167194.7-167194.34" - wire $1\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 2 $1\alu_op__input_carry$next[1:0]$9096 - attribute \src "libresoc.v:167207.13-167207.39" - wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 32 $1\alu_op__insn$next[31:0]$9097 - attribute \src "libresoc.v:167224.14-167224.34" - wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 7 $1\alu_op__insn_type$next[6:0]$9098 - attribute \src "libresoc.v:167307.13-167307.38" - wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__invert_in$next[0:0]$9099 - attribute \src "libresoc.v:167464.7-167464.31" - wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__invert_out$next[0:0]$9100 - attribute \src "libresoc.v:167473.7-167473.32" - wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__is_32bit$next[0:0]$9101 - attribute \src "libresoc.v:167482.7-167482.30" - wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__is_signed$next[0:0]$9102 - attribute \src "libresoc.v:167491.7-167491.31" - wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__oe__oe$next[0:0]$9103 - attribute \src "libresoc.v:167500.7-167500.28" - wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__oe__ok$next[0:0]$9104 - attribute \src "libresoc.v:167509.7-167509.28" - wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__output_carry$next[0:0]$9105 - attribute \src "libresoc.v:167518.7-167518.34" - wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__rc__ok$next[0:0]$9106 - attribute \src "libresoc.v:167527.7-167527.28" - wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__rc__rc$next[0:0]$9107 - attribute \src "libresoc.v:167536.7-167536.28" - wire $1\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__write_cr0$next[0:0]$9108 - attribute \src "libresoc.v:167545.7-167545.31" - wire $1\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire $1\alu_op__zero_a$next[0:0]$9109 - attribute \src "libresoc.v:167554.7-167554.28" - wire $1\alu_op__zero_a[0:0] - attribute \src "libresoc.v:168404.3-168422.6" - wire width 4 $1\cr_a$next[3:0]$9045 - attribute \src "libresoc.v:167567.13-167567.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:168404.3-168422.6" - wire $1\cr_a_ok$next[0:0]$9046 - attribute \src "libresoc.v:167574.7-167574.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:168498.3-168510.6" - wire width 2 $1\muxid$next[1:0]$9072 - attribute \src "libresoc.v:168143.13-168143.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:168553.3-168571.6" - wire width 64 $1\o$next[63:0]$9119 - attribute \src "libresoc.v:168158.14-168158.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:168553.3-168571.6" - wire $1\o_ok$next[0:0]$9120 - attribute \src "libresoc.v:168165.7-168165.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:168480.3-168497.6" - wire $1\r_busy$next[0:0]$9068 - attribute \src "libresoc.v:168179.7-168179.20" + attribute \src "libresoc.v:161870.3-161897.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8836 + attribute \src "libresoc.v:161870.3-161897.6" + wire width 13 $1\br_op__fn_unit$4$next[12:0]$8837 + attribute \src "libresoc.v:161870.3-161897.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8838 + attribute \src "libresoc.v:161870.3-161897.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8839 + attribute \src "libresoc.v:161870.3-161897.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8840 + attribute \src "libresoc.v:161870.3-161897.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8841 + attribute \src "libresoc.v:161870.3-161897.6" + wire $1\br_op__is_32bit$9$next[0:0]$8842 + attribute \src "libresoc.v:161870.3-161897.6" + wire $1\br_op__lk$8$next[0:0]$8843 + attribute \src "libresoc.v:161898.3-161916.6" + wire width 64 $1\fast1$10$next[63:0]$8849 + attribute \src "libresoc.v:161898.3-161916.6" + wire $1\fast1_ok$next[0:0]$8850 + attribute \src "libresoc.v:161477.7-161477.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:161917.3-161935.6" + wire width 64 $1\fast2$11$next[63:0]$8855 + attribute \src "libresoc.v:161917.3-161935.6" + wire $1\fast2_ok$next[0:0]$8856 + attribute \src "libresoc.v:161493.7-161493.22" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:161857.3-161869.6" + wire width 2 $1\muxid$1$next[1:0]$8826 + attribute \src "libresoc.v:161936.3-161954.6" + wire width 64 $1\nia$next[63:0]$8861 + attribute \src "libresoc.v:161745.14-161745.40" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:161936.3-161954.6" + wire $1\nia_ok$next[0:0]$8862 + attribute \src "libresoc.v:161752.7-161752.20" + wire $1\nia_ok[0:0] + attribute \src "libresoc.v:161839.3-161856.6" + wire $1\r_busy$next[0:0]$8822 + attribute \src "libresoc.v:161766.7-161766.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:168423.3-168441.6" - wire width 2 $1\xer_ca$next[1:0]$9052 - attribute \src "libresoc.v:168188.13-168188.26" - wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:168423.3-168441.6" - wire $1\xer_ca_ok$next[0:0]$9051 - attribute \src "libresoc.v:168197.7-168197.23" - wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:168442.3-168460.6" - wire width 2 $1\xer_ov$next[1:0]$9057 - attribute \src "libresoc.v:168204.13-168204.26" - wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:168442.3-168460.6" - wire $1\xer_ov_ok$next[0:0]$9058 - attribute \src "libresoc.v:168211.7-168211.23" - wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:168461.3-168479.6" - wire $1\xer_so$next[0:0]$9063 - attribute \src "libresoc.v:168218.7-168218.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:168461.3-168479.6" - wire $1\xer_so_ok$next[0:0]$9064 - attribute \src "libresoc.v:168227.7-168227.23" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:168511.3-168552.6" - wire width 64 $2\alu_op__imm_data__data$next[63:0]$9110 - attribute \src "libresoc.v:168511.3-168552.6" - wire $2\alu_op__imm_data__ok$next[0:0]$9111 - attribute \src "libresoc.v:168511.3-168552.6" - wire $2\alu_op__oe__oe$next[0:0]$9112 - attribute \src "libresoc.v:168511.3-168552.6" - wire $2\alu_op__oe__ok$next[0:0]$9113 - attribute \src "libresoc.v:168511.3-168552.6" - wire $2\alu_op__rc__ok$next[0:0]$9114 - attribute \src "libresoc.v:168511.3-168552.6" - wire $2\alu_op__rc__rc$next[0:0]$9115 - attribute \src "libresoc.v:168404.3-168422.6" - wire $2\cr_a_ok$next[0:0]$9047 - attribute \src "libresoc.v:168553.3-168571.6" - wire $2\o_ok$next[0:0]$9121 - attribute \src "libresoc.v:168480.3-168497.6" - wire $2\r_busy$next[0:0]$9069 - attribute \src "libresoc.v:168423.3-168441.6" - wire $2\xer_ca_ok$next[0:0]$9053 - attribute \src "libresoc.v:168442.3-168460.6" - wire $2\xer_ov_ok$next[0:0]$9059 - attribute \src "libresoc.v:168461.3-168479.6" - wire $2\xer_so_ok$next[0:0]$9065 - attribute \src "libresoc.v:168234.18-168234.118" - wire $and$libresoc.v:168234$9011_Y + attribute \src "libresoc.v:161870.3-161897.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8844 + attribute \src "libresoc.v:161870.3-161897.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8845 + attribute \src "libresoc.v:161898.3-161916.6" + wire $2\fast1_ok$next[0:0]$8851 + attribute \src "libresoc.v:161917.3-161935.6" + wire $2\fast2_ok$next[0:0]$8857 + attribute \src "libresoc.v:161936.3-161954.6" + wire $2\nia_ok$next[0:0]$8863 + attribute \src "libresoc.v:161839.3-161856.6" + wire $2\r_busy$next[0:0]$8823 + attribute \src "libresoc.v:161769.18-161769.118" + wire $and$libresoc.v:161769$8792_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$67 + wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 21 \alu_op__data_len + wire width 64 input 5 \br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 52 \alu_op__data_len$18 + wire width 64 output 19 \br_op__cia$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$86 + wire width 64 \br_op__cia$2$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$next + wire width 64 \br_op__cia$27 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -343781,7 +335751,7 @@ module \pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \alu_op__fn_unit + wire width 13 input 7 \br_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -343797,7 +335767,7 @@ module \pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 37 \alu_op__fn_unit$3 + wire width 13 \br_op__fn_unit$29 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -343813,53 +335783,33 @@ module \pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_op__fn_unit$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 38 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$72 + wire width 13 output 21 \br_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$next + wire width 13 \br_op__fn_unit$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \alu_op__imm_data__ok + wire width 64 input 9 \br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \alu_op__imm_data__ok$5 + wire width 64 \br_op__imm_data__data$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$73 + wire width 64 output 23 \br_op__imm_data__data$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 \br_op__imm_data__data$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 17 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire input 10 \br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 48 \alu_op__input_carry$14 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire \br_op__imm_data__ok$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$82 + wire output 24 \br_op__imm_data__ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$next + wire \br_op__imm_data__ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \alu_op__insn + wire width 32 input 8 \br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 53 \alu_op__insn$19 + wire width 32 \br_op__insn$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$87 + wire width 32 output 22 \br_op__insn$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$next + wire width 32 \br_op__insn$5$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -343935,7 +335885,7 @@ module \pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \alu_op__insn_type + wire width 7 input 6 \br_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -344011,7 +335961,7 @@ module \pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 36 \alu_op__insn_type$2 + wire width 7 \br_op__insn_type$28 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -344087,119 +336037,65 @@ module \pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 49 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$74 + wire width 7 output 20 \br_op__insn_type$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$next + wire width 7 \br_op__insn_type$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \alu_op__write_cr0 + wire input 12 \br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 47 \alu_op__write_cr0$13 + wire \br_op__is_32bit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$81 + wire output 26 \br_op__is_32bit$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$next + wire \br_op__is_32bit$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \alu_op__zero_a + wire input 11 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \alu_op__zero_a$11 + wire \br_op__lk$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$79 + wire output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \br_op__lk$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 25 \cr_a + wire width 64 output 27 \fast1$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$90 + wire width 64 \fast1$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$next + wire width 64 \fast1$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 26 \cr_a_ok + wire output 28 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$91 + wire \fast1_ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$next - attribute \src "libresoc.v:167120.7-167120.15" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 29 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$next + attribute \src "libresoc.v:161121.7-161121.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len + wire width 64 \main_br_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len$39 + wire width 64 \main_br_op__cia$13 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -344215,7 +336111,7 @@ module \pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_alu_op__fn_unit + wire width 13 \main_br_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -344231,31 +336127,19 @@ module \pipe1 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_alu_op__fn_unit$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__data$25 + wire width 13 \main_br_op__fn_unit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__imm_data__ok + wire width 64 \main_br_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__imm_data__ok$26 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 64 \main_br_op__imm_data__data$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire \main_br_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_alu_op__input_carry$35 + wire \main_br_op__imm_data__ok$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_alu_op__insn + wire width 32 \main_br_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_alu_op__insn$40 + wire width 32 \main_br_op__insn$16 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -344331,7 +336215,7 @@ module \pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_alu_op__insn_type + wire width 7 \main_br_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -344407,1039 +336291,386 @@ module \pipe1 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_alu_op__insn_type$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_in$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__invert_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_32bit$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__is_signed$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__oe$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__oe__ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__output_carry$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__ok$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__rc__rc$27 + wire width 7 \main_br_op__insn_type$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__write_cr0 + wire \main_br_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__write_cr0$34 + wire \main_br_op__is_32bit$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__zero_a + wire \main_br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__zero_a$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \input_muxid$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca + wire \main_br_op__lk$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$44 + wire width 4 \main_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast1$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_alu_op__data_len$62 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_alu_op__fn_unit$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__data$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__imm_data__ok$49 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_alu_op__input_carry$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_alu_op__insn$63 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_alu_op__insn_type$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_in$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__invert_out$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_32bit$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_signed$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__oe$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__output_carry$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__ok$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__rc$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__write_cr0$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__zero_a$55 + wire width 64 \main_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \main_cr_a + wire width 64 \main_fast2$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_cr_a_ok + wire \main_fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \main_muxid$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \main_xer_ca$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \main_xer_ov + wire width 2 \main_muxid$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so + wire width 64 \main_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_so$65 + wire \main_nia_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 4 \muxid + wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 35 \muxid$1 + wire width 2 output 18 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$69 + wire width 2 \muxid$1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$next + wire width 2 \muxid$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 3 \n_ready_i + wire input 17 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 2 \n_valid_o + wire output 16 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 23 \o + wire width 64 output 31 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$88 + wire width 64 \nia$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next + wire width 64 \nia$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 24 \o_ok + wire output 32 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$89 + wire \nia_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next + wire \nia_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 34 \p_ready_o + wire output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 33 \p_valid_i + wire input 2 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$66 + wire \p_valid_i$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 54 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 55 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 57 \xer_ca$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 30 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 31 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 56 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:168234$9011 + cell $and $and$libresoc.v:161769$8792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$66 + connect \A \p_valid_i$23 connect \B \p_ready_o - connect \Y $and$libresoc.v:168234$9011_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:168295.11-168342.4" - cell \input \input - connect \alu_op__data_len \input_alu_op__data_len - connect \alu_op__data_len$18 \input_alu_op__data_len$39 - connect \alu_op__fn_unit \input_alu_op__fn_unit - connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 - connect \alu_op__imm_data__data \input_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 - connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 - connect \alu_op__input_carry \input_alu_op__input_carry - connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 - connect \alu_op__insn \input_alu_op__insn - connect \alu_op__insn$19 \input_alu_op__insn$40 - connect \alu_op__insn_type \input_alu_op__insn_type - connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 - connect \alu_op__invert_in \input_alu_op__invert_in - connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 - connect \alu_op__invert_out \input_alu_op__invert_out - connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 - connect \alu_op__is_32bit \input_alu_op__is_32bit - connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 - connect \alu_op__is_signed \input_alu_op__is_signed - connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 - connect \alu_op__oe__oe \input_alu_op__oe__oe - connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 - connect \alu_op__oe__ok \input_alu_op__oe__ok - connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 - connect \alu_op__output_carry \input_alu_op__output_carry - connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 - connect \alu_op__rc__ok \input_alu_op__rc__ok - connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 - connect \alu_op__rc__rc \input_alu_op__rc__rc - connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 - connect \alu_op__write_cr0 \input_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 - connect \alu_op__zero_a \input_alu_op__zero_a - connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$22 - connect \ra \input_ra - connect \ra$20 \input_ra$41 - connect \rb \input_rb - connect \rb$21 \input_rb$42 - connect \xer_ca \input_xer_ca - connect \xer_ca$23 \input_xer_ca$44 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$43 + connect \Y $and$libresoc.v:161769$8792_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:168343.8-168395.4" - cell \main \main - connect \alu_op__data_len \main_alu_op__data_len - connect \alu_op__data_len$18 \main_alu_op__data_len$62 - connect \alu_op__fn_unit \main_alu_op__fn_unit - connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 - connect \alu_op__imm_data__data \main_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 - connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 - connect \alu_op__input_carry \main_alu_op__input_carry - connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 - connect \alu_op__insn \main_alu_op__insn - connect \alu_op__insn$19 \main_alu_op__insn$63 - connect \alu_op__insn_type \main_alu_op__insn_type - connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 - connect \alu_op__invert_in \main_alu_op__invert_in - connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 - connect \alu_op__invert_out \main_alu_op__invert_out - connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 - connect \alu_op__is_32bit \main_alu_op__is_32bit - connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 - connect \alu_op__is_signed \main_alu_op__is_signed - connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 - connect \alu_op__oe__oe \main_alu_op__oe__oe - connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 - connect \alu_op__oe__ok \main_alu_op__oe__ok - connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 - connect \alu_op__output_carry \main_alu_op__output_carry - connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 - connect \alu_op__rc__ok \main_alu_op__rc__ok - connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 - connect \alu_op__rc__rc \main_alu_op__rc__rc - connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 - connect \alu_op__write_cr0 \main_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 - connect \alu_op__zero_a \main_alu_op__zero_a - connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + attribute \src "libresoc.v:161802.13-161830.4" + cell \main$22 \main + connect \br_op__cia \main_br_op__cia + connect \br_op__cia$2 \main_br_op__cia$13 + connect \br_op__fn_unit \main_br_op__fn_unit + connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 + connect \br_op__imm_data__data \main_br_op__imm_data__data + connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 + connect \br_op__imm_data__ok \main_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 + connect \br_op__insn \main_br_op__insn + connect \br_op__insn$5 \main_br_op__insn$16 + connect \br_op__insn_type \main_br_op__insn_type + connect \br_op__insn_type$3 \main_br_op__insn_type$14 + connect \br_op__is_32bit \main_br_op__is_32bit + connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 + connect \br_op__lk \main_br_op__lk + connect \br_op__lk$8 \main_br_op__lk$19 connect \cr_a \main_cr_a - connect \cr_a_ok \main_cr_a_ok + connect \fast1 \main_fast1 + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok connect \muxid \main_muxid - connect \muxid$1 \main_muxid$45 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \xer_ca \main_xer_ca - connect \xer_ca$20 \main_xer_ca$64 - connect \xer_ca_ok \main_xer_ca_ok - connect \xer_ov \main_xer_ov - connect \xer_ov_ok \main_xer_ov_ok - connect \xer_so \main_xer_so - connect \xer_so$21 \main_xer_so$65 + connect \muxid$1 \main_muxid$12 + connect \nia \main_nia + connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:168396.9-168399.4" - cell \n$2 \n + attribute \src "libresoc.v:161831.10-161834.4" + cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:168400.9-168403.4" - cell \p$1 \p + attribute \src "libresoc.v:161835.10-161838.4" + cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:167120.7-167120.20" - process $proc$libresoc.v:167120$9122 + attribute \src "libresoc.v:161121.7-161121.20" + process $proc$libresoc.v:161121$8864 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167125.13-167125.36" - process $proc$libresoc.v:167125$9123 - assign { } { } - assign $1\alu_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_op__data_len $1\alu_op__data_len[3:0] - end - attribute \src "libresoc.v:167148.14-167148.40" - process $proc$libresoc.v:167148$9124 - assign { } { } - assign $1\alu_op__fn_unit[12:0] 13'0000000000000 - sync always - sync init - update \alu_op__fn_unit $1\alu_op__fn_unit[12:0] - end - attribute \src "libresoc.v:167185.14-167185.59" - process $proc$libresoc.v:167185$9125 - assign { } { } - assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:167194.7-167194.34" - process $proc$libresoc.v:167194$9126 - assign { } { } - assign $1\alu_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:167207.13-167207.39" - process $proc$libresoc.v:167207$9127 - assign { } { } - assign $1\alu_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_op__input_carry $1\alu_op__input_carry[1:0] - end - attribute \src "libresoc.v:167224.14-167224.34" - process $proc$libresoc.v:167224$9128 - assign { } { } - assign $1\alu_op__insn[31:0] 0 - sync always - sync init - update \alu_op__insn $1\alu_op__insn[31:0] - end - attribute \src "libresoc.v:167307.13-167307.38" - process $proc$libresoc.v:167307$9129 - assign { } { } - assign $1\alu_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_op__insn_type $1\alu_op__insn_type[6:0] - end - attribute \src "libresoc.v:167464.7-167464.31" - process $proc$libresoc.v:167464$9130 - assign { } { } - assign $1\alu_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_op__invert_in $1\alu_op__invert_in[0:0] - end - attribute \src "libresoc.v:167473.7-167473.32" - process $proc$libresoc.v:167473$9131 - assign { } { } - assign $1\alu_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_op__invert_out $1\alu_op__invert_out[0:0] - end - attribute \src "libresoc.v:167482.7-167482.30" - process $proc$libresoc.v:167482$9132 - assign { } { } - assign $1\alu_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] - end - attribute \src "libresoc.v:167491.7-167491.31" - process $proc$libresoc.v:167491$9133 - assign { } { } - assign $1\alu_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_op__is_signed $1\alu_op__is_signed[0:0] - end - attribute \src "libresoc.v:167500.7-167500.28" - process $proc$libresoc.v:167500$9134 - assign { } { } - assign $1\alu_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] - end - attribute \src "libresoc.v:167509.7-167509.28" - process $proc$libresoc.v:167509$9135 - assign { } { } - assign $1\alu_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] - end - attribute \src "libresoc.v:167518.7-167518.34" - process $proc$libresoc.v:167518$9136 - assign { } { } - assign $1\alu_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_op__output_carry $1\alu_op__output_carry[0:0] - end - attribute \src "libresoc.v:167527.7-167527.28" - process $proc$libresoc.v:167527$9137 - assign { } { } - assign $1\alu_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] - end - attribute \src "libresoc.v:167536.7-167536.28" - process $proc$libresoc.v:167536$9138 - assign { } { } - assign $1\alu_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] - end - attribute \src "libresoc.v:167545.7-167545.31" - process $proc$libresoc.v:167545$9139 - assign { } { } - assign $1\alu_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] - end - attribute \src "libresoc.v:167554.7-167554.28" - process $proc$libresoc.v:167554$9140 - assign { } { } - assign $1\alu_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_op__zero_a $1\alu_op__zero_a[0:0] - end - attribute \src "libresoc.v:167567.13-167567.24" - process $proc$libresoc.v:167567$9141 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "libresoc.v:167574.7-167574.21" - process $proc$libresoc.v:167574$9142 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:168143.13-168143.25" - process $proc$libresoc.v:168143$9143 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "libresoc.v:168158.14-168158.38" - process $proc$libresoc.v:168158$9144 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:168165.7-168165.18" - process $proc$libresoc.v:168165$9145 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:168179.7-168179.20" - process $proc$libresoc.v:168179$9146 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:168188.13-168188.26" - process $proc$libresoc.v:168188$9147 - assign { } { } - assign $1\xer_ca[1:0] 2'00 - sync always - sync init - update \xer_ca $1\xer_ca[1:0] - end - attribute \src "libresoc.v:168197.7-168197.23" - process $proc$libresoc.v:168197$9148 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 - sync always - sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:168204.13-168204.26" - process $proc$libresoc.v:168204$9149 - assign { } { } - assign $1\xer_ov[1:0] 2'00 - sync always - sync init - update \xer_ov $1\xer_ov[1:0] - end - attribute \src "libresoc.v:168211.7-168211.23" - process $proc$libresoc.v:168211$9150 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:168218.7-168218.20" - process $proc$libresoc.v:168218$9151 + attribute \src "libresoc.v:161128.14-161128.51" + process $proc$libresoc.v:161128$8865 assign { } { } - assign $1\xer_so[0:0] 1'0 + assign $0\br_op__cia$2[63:0]$8866 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \xer_so $1\xer_so[0:0] + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8866 end - attribute \src "libresoc.v:168227.7-168227.23" - process $proc$libresoc.v:168227$9152 + attribute \src "libresoc.v:161181.14-161181.43" + process $proc$libresoc.v:161181$8867 assign { } { } - assign $1\xer_so_ok[0:0] 1'0 + assign $0\br_op__fn_unit$4[12:0]$8868 13'0000000000000 sync always sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:168235.3-168236.29" - process $proc$libresoc.v:168235$9012 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8868 end - attribute \src "libresoc.v:168237.3-168238.35" - process $proc$libresoc.v:168237$9013 + attribute \src "libresoc.v:161190.14-161190.62" + process $proc$libresoc.v:161190$8869 assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] + assign $0\br_op__imm_data__data$6[63:0]$8870 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8870 end - attribute \src "libresoc.v:168239.3-168240.29" - process $proc$libresoc.v:168239$9014 + attribute \src "libresoc.v:161199.7-161199.37" + process $proc$libresoc.v:161199$8871 assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] + assign $0\br_op__imm_data__ok$7[0:0]$8872 1'0 + sync always + sync init + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8872 end - attribute \src "libresoc.v:168241.3-168242.35" - process $proc$libresoc.v:168241$9015 + attribute \src "libresoc.v:161208.14-161208.37" + process $proc$libresoc.v:161208$8873 assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] + assign $0\br_op__insn$5[31:0]$8874 0 + sync always + sync init + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8874 end - attribute \src "libresoc.v:168243.3-168244.29" - process $proc$libresoc.v:168243$9016 + attribute \src "libresoc.v:161439.13-161439.41" + process $proc$libresoc.v:161439$8875 assign { } { } - assign $0\xer_ca[1:0] \xer_ca$next - sync posedge \coresync_clk - update \xer_ca $0\xer_ca[1:0] + assign $0\br_op__insn_type$3[6:0]$8876 7'0000000 + sync always + sync init + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8876 end - attribute \src "libresoc.v:168245.3-168246.35" - process $proc$libresoc.v:168245$9017 + attribute \src "libresoc.v:161448.7-161448.33" + process $proc$libresoc.v:161448$8877 assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] + assign $0\br_op__is_32bit$9[0:0]$8878 1'0 + sync always + sync init + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8878 end - attribute \src "libresoc.v:168247.3-168248.25" - process $proc$libresoc.v:168247$9018 + attribute \src "libresoc.v:161457.7-161457.27" + process $proc$libresoc.v:161457$8879 assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] + assign $0\br_op__lk$8[0:0]$8880 1'0 + sync always + sync init + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8880 end - attribute \src "libresoc.v:168249.3-168250.31" - process $proc$libresoc.v:168249$9019 + attribute \src "libresoc.v:161470.14-161470.47" + process $proc$libresoc.v:161470$8881 assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] + assign $0\fast1$10[63:0]$8882 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$10 $0\fast1$10[63:0]$8882 end - attribute \src "libresoc.v:168251.3-168252.19" - process $proc$libresoc.v:168251$9020 + attribute \src "libresoc.v:161477.7-161477.22" + process $proc$libresoc.v:161477$8883 assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:168253.3-168254.25" - process $proc$libresoc.v:168253$9021 + attribute \src "libresoc.v:161486.14-161486.47" + process $proc$libresoc.v:161486$8884 assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + assign $0\fast2$11[63:0]$8885 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$11 $0\fast2$11[63:0]$8885 end - attribute \src "libresoc.v:168255.3-168256.51" - process $proc$libresoc.v:168255$9022 + attribute \src "libresoc.v:161493.7-161493.22" + process $proc$libresoc.v:161493$8886 assign { } { } - assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next - sync posedge \coresync_clk - update \alu_op__insn_type $0\alu_op__insn_type[6:0] + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:168257.3-168258.47" - process $proc$libresoc.v:168257$9023 + attribute \src "libresoc.v:161732.13-161732.29" + process $proc$libresoc.v:161732$8887 assign { } { } - assign $0\alu_op__fn_unit[12:0] \alu_op__fn_unit$next - sync posedge \coresync_clk - update \alu_op__fn_unit $0\alu_op__fn_unit[12:0] + assign $0\muxid$1[1:0]$8888 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8888 end - attribute \src "libresoc.v:168259.3-168260.61" - process $proc$libresoc.v:168259$9024 + attribute \src "libresoc.v:161745.14-161745.40" + process $proc$libresoc.v:161745$8889 assign { } { } - assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] end - attribute \src "libresoc.v:168261.3-168262.57" - process $proc$libresoc.v:168261$9025 + attribute \src "libresoc.v:161752.7-161752.20" + process $proc$libresoc.v:161752$8890 assign { } { } - assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:168263.3-168264.45" - process $proc$libresoc.v:168263$9026 + attribute \src "libresoc.v:161766.7-161766.20" + process $proc$libresoc.v:161766$8891 assign { } { } - assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:161770.3-161771.23" + process $proc$libresoc.v:161770$8793 + assign { } { } + assign $0\nia[63:0] \nia$next sync posedge \coresync_clk - update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + update \nia $0\nia[63:0] end - attribute \src "libresoc.v:168265.3-168266.45" - process $proc$libresoc.v:168265$9027 + attribute \src "libresoc.v:161772.3-161773.29" + process $proc$libresoc.v:161772$8794 assign { } { } - assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next + assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk - update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] + update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:168267.3-168268.45" - process $proc$libresoc.v:168267$9028 + attribute \src "libresoc.v:161774.3-161775.35" + process $proc$libresoc.v:161774$8795 assign { } { } - assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + assign $0\fast2$11[63:0]$8796 \fast2$11$next sync posedge \coresync_clk - update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + update \fast2$11 $0\fast2$11[63:0]$8796 end - attribute \src "libresoc.v:168269.3-168270.45" - process $proc$libresoc.v:168269$9029 + attribute \src "libresoc.v:161776.3-161777.33" + process $proc$libresoc.v:161776$8797 assign { } { } - assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk - update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:168271.3-168272.51" - process $proc$libresoc.v:168271$9030 + attribute \src "libresoc.v:161778.3-161779.35" + process $proc$libresoc.v:161778$8798 assign { } { } - assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + assign $0\fast1$10[63:0]$8799 \fast1$10$next sync posedge \coresync_clk - update \alu_op__invert_in $0\alu_op__invert_in[0:0] + update \fast1$10 $0\fast1$10[63:0]$8799 end - attribute \src "libresoc.v:168273.3-168274.45" - process $proc$libresoc.v:168273$9031 + attribute \src "libresoc.v:161780.3-161781.33" + process $proc$libresoc.v:161780$8800 assign { } { } - assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk - update \alu_op__zero_a $0\alu_op__zero_a[0:0] + update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:168275.3-168276.53" - process $proc$libresoc.v:168275$9032 + attribute \src "libresoc.v:161782.3-161783.43" + process $proc$libresoc.v:161782$8801 assign { } { } - assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + assign $0\br_op__cia$2[63:0]$8802 \br_op__cia$2$next sync posedge \coresync_clk - update \alu_op__invert_out $0\alu_op__invert_out[0:0] + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8802 end - attribute \src "libresoc.v:168277.3-168278.51" - process $proc$libresoc.v:168277$9033 + attribute \src "libresoc.v:161784.3-161785.55" + process $proc$libresoc.v:161784$8803 assign { } { } - assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + assign $0\br_op__insn_type$3[6:0]$8804 \br_op__insn_type$3$next sync posedge \coresync_clk - update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8804 end - attribute \src "libresoc.v:168279.3-168280.55" - process $proc$libresoc.v:168279$9034 + attribute \src "libresoc.v:161786.3-161787.51" + process $proc$libresoc.v:161786$8805 assign { } { } - assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + assign $0\br_op__fn_unit$4[12:0]$8806 \br_op__fn_unit$4$next sync posedge \coresync_clk - update \alu_op__input_carry $0\alu_op__input_carry[1:0] + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8806 end - attribute \src "libresoc.v:168281.3-168282.57" - process $proc$libresoc.v:168281$9035 + attribute \src "libresoc.v:161788.3-161789.45" + process $proc$libresoc.v:161788$8807 assign { } { } - assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + assign $0\br_op__insn$5[31:0]$8808 \br_op__insn$5$next sync posedge \coresync_clk - update \alu_op__output_carry $0\alu_op__output_carry[0:0] + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8808 end - attribute \src "libresoc.v:168283.3-168284.49" - process $proc$libresoc.v:168283$9036 + attribute \src "libresoc.v:161790.3-161791.65" + process $proc$libresoc.v:161790$8809 assign { } { } - assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + assign $0\br_op__imm_data__data$6[63:0]$8810 \br_op__imm_data__data$6$next sync posedge \coresync_clk - update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8810 end - attribute \src "libresoc.v:168285.3-168286.51" - process $proc$libresoc.v:168285$9037 + attribute \src "libresoc.v:161792.3-161793.61" + process $proc$libresoc.v:161792$8811 assign { } { } - assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + assign $0\br_op__imm_data__ok$7[0:0]$8812 \br_op__imm_data__ok$7$next sync posedge \coresync_clk - update \alu_op__is_signed $0\alu_op__is_signed[0:0] + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8812 end - attribute \src "libresoc.v:168287.3-168288.49" - process $proc$libresoc.v:168287$9038 + attribute \src "libresoc.v:161794.3-161795.41" + process $proc$libresoc.v:161794$8813 assign { } { } - assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + assign $0\br_op__lk$8[0:0]$8814 \br_op__lk$8$next sync posedge \coresync_clk - update \alu_op__data_len $0\alu_op__data_len[3:0] + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8814 end - attribute \src "libresoc.v:168289.3-168290.41" - process $proc$libresoc.v:168289$9039 + attribute \src "libresoc.v:161796.3-161797.53" + process $proc$libresoc.v:161796$8815 assign { } { } - assign $0\alu_op__insn[31:0] \alu_op__insn$next + assign $0\br_op__is_32bit$9[0:0]$8816 \br_op__is_32bit$9$next sync posedge \coresync_clk - update \alu_op__insn $0\alu_op__insn[31:0] + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8816 end - attribute \src "libresoc.v:168291.3-168292.27" - process $proc$libresoc.v:168291$9040 + attribute \src "libresoc.v:161798.3-161799.33" + process $proc$libresoc.v:161798$8817 assign { } { } - assign $0\muxid[1:0] \muxid$next + assign $0\muxid$1[1:0]$8818 \muxid$1$next sync posedge \coresync_clk - update \muxid $0\muxid[1:0] + update \muxid$1 $0\muxid$1[1:0]$8818 end - attribute \src "libresoc.v:168293.3-168294.29" - process $proc$libresoc.v:168293$9041 + attribute \src "libresoc.v:161800.3-161801.29" + process $proc$libresoc.v:161800$8819 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:168404.3-168422.6" - process $proc$libresoc.v:168404$9042 - assign { } { } + attribute \src "libresoc.v:161839.3-161856.6" + process $proc$libresoc.v:161839$8820 assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9043 $1\cr_a$next[3:0]$9045 - assign { } { } - assign $0\cr_a_ok$next[0:0]$9044 $2\cr_a_ok$next[0:0]$9047 - attribute \src "libresoc.v:168405.5-168405.29" + assign $0\r_busy$next[0:0]$8821 $2\r_busy$next[0:0]$8823 + attribute \src "libresoc.v:161840.5-161840.29" switch \initial - attribute \src "libresoc.v:168405.9-168405.17" + attribute \src "libresoc.v:161840.9-161840.17" case 1'1 case end @@ -345448,42 +336679,34 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$9046 $1\cr_a$next[3:0]$9045 } { \cr_a_ok$91 \cr_a$90 } + assign $1\r_busy$next[0:0]$8822 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$9046 $1\cr_a$next[3:0]$9045 } { \cr_a_ok$91 \cr_a$90 } + assign $1\r_busy$next[0:0]$8822 1'0 case - assign $1\cr_a$next[3:0]$9045 \cr_a - assign $1\cr_a_ok$next[0:0]$9046 \cr_a_ok + assign $1\r_busy$next[0:0]$8822 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9047 1'0 + assign $2\r_busy$next[0:0]$8823 1'0 case - assign $2\cr_a_ok$next[0:0]$9047 $1\cr_a_ok$next[0:0]$9046 + assign $2\r_busy$next[0:0]$8823 $1\r_busy$next[0:0]$8822 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9043 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9044 + update \r_busy$next $0\r_busy$next[0:0]$8821 end - attribute \src "libresoc.v:168423.3-168441.6" - process $proc$libresoc.v:168423$9048 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:161857.3-161869.6" + process $proc$libresoc.v:161857$8824 assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9050 $1\xer_ca$next[1:0]$9052 - assign $0\xer_ca_ok$next[0:0]$9049 $2\xer_ca_ok$next[0:0]$9053 - attribute \src "libresoc.v:168424.5-168424.29" + assign $0\muxid$1$next[1:0]$8825 $1\muxid$1$next[1:0]$8826 + attribute \src "libresoc.v:161858.5-161858.29" switch \initial - attribute \src "libresoc.v:168424.9-168424.17" + attribute \src "libresoc.v:161858.9-161858.17" case 1'1 case end @@ -345492,86 +336715,48 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9051 $1\xer_ca$next[1:0]$9052 } { \xer_ca_ok$93 \xer_ca$92 } + assign $1\muxid$1$next[1:0]$8826 \muxid$26 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9051 $1\xer_ca$next[1:0]$9052 } { \xer_ca_ok$93 \xer_ca$92 } - case - assign $1\xer_ca_ok$next[0:0]$9051 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9052 \xer_ca - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ca_ok$next[0:0]$9053 1'0 + assign $1\muxid$1$next[1:0]$8826 \muxid$26 case - assign $2\xer_ca_ok$next[0:0]$9053 $1\xer_ca_ok$next[0:0]$9051 + assign $1\muxid$1$next[1:0]$8826 \muxid$1 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9049 - update \xer_ca$next $0\xer_ca$next[1:0]$9050 + update \muxid$1$next $0\muxid$1$next[1:0]$8825 end - attribute \src "libresoc.v:168442.3-168460.6" - process $proc$libresoc.v:168442$9054 + attribute \src "libresoc.v:161870.3-161897.6" + process $proc$libresoc.v:161870$8827 + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9055 $1\xer_ov$next[1:0]$9057 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9056 $2\xer_ov_ok$next[0:0]$9059 - attribute \src "libresoc.v:168443.5-168443.29" - switch \initial - attribute \src "libresoc.v:168443.9-168443.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9058 $1\xer_ov$next[1:0]$9057 } { \xer_ov_ok$95 \xer_ov$94 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9058 $1\xer_ov$next[1:0]$9057 } { \xer_ov_ok$95 \xer_ov$94 } - case - assign $1\xer_ov$next[1:0]$9057 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9058 \xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ov_ok$next[0:0]$9059 1'0 - case - assign $2\xer_ov_ok$next[0:0]$9059 $1\xer_ov_ok$next[0:0]$9058 - end - sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9055 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9056 - end - attribute \src "libresoc.v:168461.3-168479.6" - process $proc$libresoc.v:168461$9060 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9061 $1\xer_so$next[0:0]$9063 assign { } { } - assign $0\xer_so_ok$next[0:0]$9062 $2\xer_so_ok$next[0:0]$9065 - attribute \src "libresoc.v:168462.5-168462.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\br_op__cia$2$next[63:0]$8828 $1\br_op__cia$2$next[63:0]$8836 + assign $0\br_op__fn_unit$4$next[12:0]$8829 $1\br_op__fn_unit$4$next[12:0]$8837 + assign { } { } + assign { } { } + assign $0\br_op__insn$5$next[31:0]$8832 $1\br_op__insn$5$next[31:0]$8840 + assign $0\br_op__insn_type$3$next[6:0]$8833 $1\br_op__insn_type$3$next[6:0]$8841 + assign $0\br_op__is_32bit$9$next[0:0]$8834 $1\br_op__is_32bit$9$next[0:0]$8842 + assign $0\br_op__lk$8$next[0:0]$8835 $1\br_op__lk$8$next[0:0]$8843 + assign $0\br_op__imm_data__data$6$next[63:0]$8830 $2\br_op__imm_data__data$6$next[63:0]$8844 + assign $0\br_op__imm_data__ok$7$next[0:0]$8831 $2\br_op__imm_data__ok$7$next[0:0]$8845 + attribute \src "libresoc.v:161871.5-161871.29" switch \initial - attribute \src "libresoc.v:168462.9-168462.17" + attribute \src "libresoc.v:161871.9-161871.17" case 1'1 case end @@ -345581,38 +336766,68 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9064 $1\xer_so$next[0:0]$9063 } { \xer_so_ok$97 \xer_so$96 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8842 $1\br_op__lk$8$next[0:0]$8843 $1\br_op__imm_data__ok$7$next[0:0]$8839 $1\br_op__imm_data__data$6$next[63:0]$8838 $1\br_op__insn$5$next[31:0]$8840 $1\br_op__fn_unit$4$next[12:0]$8837 $1\br_op__insn_type$3$next[6:0]$8841 $1\br_op__cia$2$next[63:0]$8836 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9064 $1\xer_so$next[0:0]$9063 } { \xer_so_ok$97 \xer_so$96 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8842 $1\br_op__lk$8$next[0:0]$8843 $1\br_op__imm_data__ok$7$next[0:0]$8839 $1\br_op__imm_data__data$6$next[63:0]$8838 $1\br_op__insn$5$next[31:0]$8840 $1\br_op__fn_unit$4$next[12:0]$8837 $1\br_op__insn_type$3$next[6:0]$8841 $1\br_op__cia$2$next[63:0]$8836 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } case - assign $1\xer_so$next[0:0]$9063 \xer_so - assign $1\xer_so_ok$next[0:0]$9064 \xer_so_ok + assign $1\br_op__cia$2$next[63:0]$8836 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[12:0]$8837 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8838 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8839 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8840 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8841 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8842 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8843 \br_op__lk$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9065 1'0 + assign { } { } + assign $2\br_op__imm_data__data$6$next[63:0]$8844 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8845 1'0 case - assign $2\xer_so_ok$next[0:0]$9065 $1\xer_so_ok$next[0:0]$9064 + assign $2\br_op__imm_data__data$6$next[63:0]$8844 $1\br_op__imm_data__data$6$next[63:0]$8838 + assign $2\br_op__imm_data__ok$7$next[0:0]$8845 $1\br_op__imm_data__ok$7$next[0:0]$8839 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9061 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9062 + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8828 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[12:0]$8829 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8830 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8831 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8832 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8833 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8834 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8835 end - attribute \src "libresoc.v:168480.3-168497.6" - process $proc$libresoc.v:168480$9066 + attribute \src "libresoc.v:161898.3-161916.6" + process $proc$libresoc.v:161898$8846 + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9067 $2\r_busy$next[0:0]$9069 - attribute \src "libresoc.v:168481.5-168481.29" + assign $0\fast1$10$next[63:0]$8847 $1\fast1$10$next[63:0]$8849 + assign { } { } + assign $0\fast1_ok$next[0:0]$8848 $2\fast1_ok$next[0:0]$8851 + attribute \src "libresoc.v:161899.5-161899.29" switch \initial - attribute \src "libresoc.v:168481.9-168481.17" + attribute \src "libresoc.v:161899.9-161899.17" case 1'1 case end @@ -345621,118 +336836,42 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9068 1'1 + assign { } { } + assign { $1\fast1_ok$next[0:0]$8850 $1\fast1$10$next[63:0]$8849 } { \fast1_ok$36 \fast1$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9068 1'0 + assign { } { } + assign { $1\fast1_ok$next[0:0]$8850 $1\fast1$10$next[63:0]$8849 } { \fast1_ok$36 \fast1$35 } case - assign $1\r_busy$next[0:0]$9068 \r_busy + assign $1\fast1$10$next[63:0]$8849 \fast1$10 + assign $1\fast1_ok$next[0:0]$8850 \fast1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9069 1'0 - case - assign $2\r_busy$next[0:0]$9069 $1\r_busy$next[0:0]$9068 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$9067 - end - attribute \src "libresoc.v:168498.3-168510.6" - process $proc$libresoc.v:168498$9070 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$9071 $1\muxid$next[1:0]$9072 - attribute \src "libresoc.v:168499.5-168499.29" - switch \initial - attribute \src "libresoc.v:168499.9-168499.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$9072 \muxid$69 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$9072 \muxid$69 + assign $2\fast1_ok$next[0:0]$8851 1'0 case - assign $1\muxid$next[1:0]$9072 \muxid + assign $2\fast1_ok$next[0:0]$8851 $1\fast1_ok$next[0:0]$8850 end sync always - update \muxid$next $0\muxid$next[1:0]$9071 + update \fast1$10$next $0\fast1$10$next[63:0]$8847 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8848 end - attribute \src "libresoc.v:168511.3-168552.6" - process $proc$libresoc.v:168511$9073 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:161917.3-161935.6" + process $proc$libresoc.v:161917$8852 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\fast2$11$next[63:0]$8853 $1\fast2$11$next[63:0]$8855 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_op__data_len$next[3:0]$9074 $1\alu_op__data_len$next[3:0]$9092 - assign $0\alu_op__fn_unit$next[12:0]$9075 $1\alu_op__fn_unit$next[12:0]$9093 - assign { } { } - assign { } { } - assign $0\alu_op__input_carry$next[1:0]$9078 $1\alu_op__input_carry$next[1:0]$9096 - assign $0\alu_op__insn$next[31:0]$9079 $1\alu_op__insn$next[31:0]$9097 - assign $0\alu_op__insn_type$next[6:0]$9080 $1\alu_op__insn_type$next[6:0]$9098 - assign $0\alu_op__invert_in$next[0:0]$9081 $1\alu_op__invert_in$next[0:0]$9099 - assign $0\alu_op__invert_out$next[0:0]$9082 $1\alu_op__invert_out$next[0:0]$9100 - assign $0\alu_op__is_32bit$next[0:0]$9083 $1\alu_op__is_32bit$next[0:0]$9101 - assign $0\alu_op__is_signed$next[0:0]$9084 $1\alu_op__is_signed$next[0:0]$9102 - assign { } { } - assign { } { } - assign $0\alu_op__output_carry$next[0:0]$9087 $1\alu_op__output_carry$next[0:0]$9105 - assign { } { } - assign { } { } - assign $0\alu_op__write_cr0$next[0:0]$9090 $1\alu_op__write_cr0$next[0:0]$9108 - assign $0\alu_op__zero_a$next[0:0]$9091 $1\alu_op__zero_a$next[0:0]$9109 - assign $0\alu_op__imm_data__data$next[63:0]$9076 $2\alu_op__imm_data__data$next[63:0]$9110 - assign $0\alu_op__imm_data__ok$next[0:0]$9077 $2\alu_op__imm_data__ok$next[0:0]$9111 - assign $0\alu_op__oe__oe$next[0:0]$9085 $2\alu_op__oe__oe$next[0:0]$9112 - assign $0\alu_op__oe__ok$next[0:0]$9086 $2\alu_op__oe__ok$next[0:0]$9113 - assign $0\alu_op__rc__ok$next[0:0]$9088 $2\alu_op__rc__ok$next[0:0]$9114 - assign $0\alu_op__rc__rc$next[0:0]$9089 $2\alu_op__rc__rc$next[0:0]$9115 - attribute \src "libresoc.v:168512.5-168512.29" + assign $0\fast2_ok$next[0:0]$8854 $2\fast2_ok$next[0:0]$8857 + attribute \src "libresoc.v:161918.5-161918.29" switch \initial - attribute \src "libresoc.v:168512.9-168512.17" + attribute \src "libresoc.v:161918.9-161918.17" case 1'1 case end @@ -345742,120 +336881,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_op__insn$next[31:0]$9097 $1\alu_op__data_len$next[3:0]$9092 $1\alu_op__is_signed$next[0:0]$9102 $1\alu_op__is_32bit$next[0:0]$9101 $1\alu_op__output_carry$next[0:0]$9105 $1\alu_op__input_carry$next[1:0]$9096 $1\alu_op__write_cr0$next[0:0]$9108 $1\alu_op__invert_out$next[0:0]$9100 $1\alu_op__zero_a$next[0:0]$9109 $1\alu_op__invert_in$next[0:0]$9099 $1\alu_op__oe__ok$next[0:0]$9104 $1\alu_op__oe__oe$next[0:0]$9103 $1\alu_op__rc__ok$next[0:0]$9106 $1\alu_op__rc__rc$next[0:0]$9107 $1\alu_op__imm_data__ok$next[0:0]$9095 $1\alu_op__imm_data__data$next[63:0]$9094 $1\alu_op__fn_unit$next[12:0]$9093 $1\alu_op__insn_type$next[6:0]$9098 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\fast2_ok$next[0:0]$8856 $1\fast2$11$next[63:0]$8855 } { \fast2_ok$38 \fast2$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_op__insn$next[31:0]$9097 $1\alu_op__data_len$next[3:0]$9092 $1\alu_op__is_signed$next[0:0]$9102 $1\alu_op__is_32bit$next[0:0]$9101 $1\alu_op__output_carry$next[0:0]$9105 $1\alu_op__input_carry$next[1:0]$9096 $1\alu_op__write_cr0$next[0:0]$9108 $1\alu_op__invert_out$next[0:0]$9100 $1\alu_op__zero_a$next[0:0]$9109 $1\alu_op__invert_in$next[0:0]$9099 $1\alu_op__oe__ok$next[0:0]$9104 $1\alu_op__oe__oe$next[0:0]$9103 $1\alu_op__rc__ok$next[0:0]$9106 $1\alu_op__rc__rc$next[0:0]$9107 $1\alu_op__imm_data__ok$next[0:0]$9095 $1\alu_op__imm_data__data$next[63:0]$9094 $1\alu_op__fn_unit$next[12:0]$9093 $1\alu_op__insn_type$next[6:0]$9098 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\fast2_ok$next[0:0]$8856 $1\fast2$11$next[63:0]$8855 } { \fast2_ok$38 \fast2$37 } case - assign $1\alu_op__data_len$next[3:0]$9092 \alu_op__data_len - assign $1\alu_op__fn_unit$next[12:0]$9093 \alu_op__fn_unit - assign $1\alu_op__imm_data__data$next[63:0]$9094 \alu_op__imm_data__data - assign $1\alu_op__imm_data__ok$next[0:0]$9095 \alu_op__imm_data__ok - assign $1\alu_op__input_carry$next[1:0]$9096 \alu_op__input_carry - assign $1\alu_op__insn$next[31:0]$9097 \alu_op__insn - assign $1\alu_op__insn_type$next[6:0]$9098 \alu_op__insn_type - assign $1\alu_op__invert_in$next[0:0]$9099 \alu_op__invert_in - assign $1\alu_op__invert_out$next[0:0]$9100 \alu_op__invert_out - assign $1\alu_op__is_32bit$next[0:0]$9101 \alu_op__is_32bit - assign $1\alu_op__is_signed$next[0:0]$9102 \alu_op__is_signed - assign $1\alu_op__oe__oe$next[0:0]$9103 \alu_op__oe__oe - assign $1\alu_op__oe__ok$next[0:0]$9104 \alu_op__oe__ok - assign $1\alu_op__output_carry$next[0:0]$9105 \alu_op__output_carry - assign $1\alu_op__rc__ok$next[0:0]$9106 \alu_op__rc__ok - assign $1\alu_op__rc__rc$next[0:0]$9107 \alu_op__rc__rc - assign $1\alu_op__write_cr0$next[0:0]$9108 \alu_op__write_cr0 - assign $1\alu_op__zero_a$next[0:0]$9109 \alu_op__zero_a + assign $1\fast2$11$next[63:0]$8855 \fast2$11 + assign $1\fast2_ok$next[0:0]$8856 \fast2_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_op__imm_data__data$next[63:0]$9110 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$next[0:0]$9111 1'0 - assign $2\alu_op__rc__rc$next[0:0]$9115 1'0 - assign $2\alu_op__rc__ok$next[0:0]$9114 1'0 - assign $2\alu_op__oe__oe$next[0:0]$9112 1'0 - assign $2\alu_op__oe__ok$next[0:0]$9113 1'0 + assign $2\fast2_ok$next[0:0]$8857 1'0 case - assign $2\alu_op__imm_data__data$next[63:0]$9110 $1\alu_op__imm_data__data$next[63:0]$9094 - assign $2\alu_op__imm_data__ok$next[0:0]$9111 $1\alu_op__imm_data__ok$next[0:0]$9095 - assign $2\alu_op__oe__oe$next[0:0]$9112 $1\alu_op__oe__oe$next[0:0]$9103 - assign $2\alu_op__oe__ok$next[0:0]$9113 $1\alu_op__oe__ok$next[0:0]$9104 - assign $2\alu_op__rc__ok$next[0:0]$9114 $1\alu_op__rc__ok$next[0:0]$9106 - assign $2\alu_op__rc__rc$next[0:0]$9115 $1\alu_op__rc__rc$next[0:0]$9107 + assign $2\fast2_ok$next[0:0]$8857 $1\fast2_ok$next[0:0]$8856 end sync always - update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9074 - update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[12:0]$9075 - update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9076 - update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9077 - update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9078 - update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9079 - update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9080 - update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9081 - update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9082 - update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9083 - update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9084 - update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9085 - update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9086 - update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9087 - update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9088 - update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9089 - update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9090 - update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9091 + update \fast2$11$next $0\fast2$11$next[63:0]$8853 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8854 end - attribute \src "libresoc.v:168553.3-168571.6" - process $proc$libresoc.v:168553$9116 + attribute \src "libresoc.v:161936.3-161954.6" + process $proc$libresoc.v:161936$8858 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9117 $1\o$next[63:0]$9119 + assign $0\nia$next[63:0]$8859 $1\nia$next[63:0]$8861 assign { } { } - assign $0\o_ok$next[0:0]$9118 $2\o_ok$next[0:0]$9121 - attribute \src "libresoc.v:168554.5-168554.29" + assign $0\nia_ok$next[0:0]$8860 $2\nia_ok$next[0:0]$8863 + attribute \src "libresoc.v:161937.5-161937.29" switch \initial - attribute \src "libresoc.v:168554.9-168554.17" + attribute \src "libresoc.v:161937.9-161937.17" case 1'1 case end @@ -345865,617 +336925,311 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9120 $1\o$next[63:0]$9119 } { \o_ok$89 \o$88 } + assign { $1\nia_ok$next[0:0]$8862 $1\nia$next[63:0]$8861 } { \nia_ok$40 \nia$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9120 $1\o$next[63:0]$9119 } { \o_ok$89 \o$88 } + assign { $1\nia_ok$next[0:0]$8862 $1\nia$next[63:0]$8861 } { \nia_ok$40 \nia$39 } case - assign $1\o$next[63:0]$9119 \o - assign $1\o_ok$next[0:0]$9120 \o_ok + assign $1\nia$next[63:0]$8861 \nia + assign $1\nia_ok$next[0:0]$8862 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9121 1'0 + assign $2\nia_ok$next[0:0]$8863 1'0 case - assign $2\o_ok$next[0:0]$9121 $1\o_ok$next[0:0]$9120 + assign $2\nia_ok$next[0:0]$8863 $1\nia_ok$next[0:0]$8862 end sync always - update \o$next $0\o$next[63:0]$9117 - update \o_ok$next $0\o_ok$next[0:0]$9118 + update \nia$next $0\nia$next[63:0]$8859 + update \nia_ok$next $0\nia_ok$next[0:0]$8860 end - connect \$67 $and$libresoc.v:168234$9011_Y - connect \xer_so_ok$98 1'0 + connect \$24 $and$libresoc.v:161769$8792_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } - connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } - connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } - connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } - connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } - connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } - connect \muxid$69 \main_muxid$45 - connect \p_valid_i_p_ready_o \$67 + connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } + connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } + connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } + connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } + connect \muxid$26 \main_muxid$12 + connect \p_valid_i_p_ready_o \$24 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$66 \p_valid_i - connect \main_xer_ca \input_xer_ca$44 - connect \main_xer_so \input_xer_so$43 - connect \main_rb \input_rb$42 - connect \main_ra \input_ra$41 - connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } - connect \main_muxid \input_muxid$22 - connect \input_xer_ca \xer_ca$21 - connect \input_xer_so \xer_so$20 - connect \input_rb \rb - connect \input_ra \ra - connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } - connect \input_muxid \muxid$1 + connect \p_valid_i$23 \p_valid_i + connect \main_cr_a \cr_a + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \main_muxid \muxid end -attribute \src "libresoc.v:168601.1-170023.10" +attribute \src "libresoc.v:161974.1-162894.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" -module \pipe1$110 - attribute \src "libresoc.v:169956.3-169974.6" - wire width 4 $0\cr_a$next[3:0]$9242 - attribute \src "libresoc.v:169698.3-169699.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:169956.3-169974.6" - wire $0\cr_a_ok$next[0:0]$9243 - attribute \src "libresoc.v:169700.3-169701.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:168602.7-168602.20" +module \pipe$64 + attribute \src "libresoc.v:162797.3-162815.6" + wire width 64 $0\fast1$7$next[63:0]$8951 + attribute \src "libresoc.v:162650.3-162651.33" + wire width 64 $0\fast1$7[63:0]$8903 + attribute \src "libresoc.v:161988.14-161988.46" + wire width 64 $0\fast1$7[63:0]$8975 + attribute \src "libresoc.v:162797.3-162815.6" + wire $0\fast1_ok$next[0:0]$8950 + attribute \src "libresoc.v:162652.3-162653.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:161975.7-161975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169883.3-169895.6" - wire width 2 $0\muxid$next[1:0]$9192 - attribute \src "libresoc.v:169740.3-169741.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:169937.3-169955.6" - wire width 64 $0\o$next[63:0]$9236 - attribute \src "libresoc.v:169702.3-169703.19" + attribute \src "libresoc.v:162730.3-162742.6" + wire width 2 $0\muxid$1$next[1:0]$8926 + attribute \src "libresoc.v:162670.3-162671.33" + wire width 2 $0\muxid$1[1:0]$8919 + attribute \src "libresoc.v:162002.13-162002.29" + wire width 2 $0\muxid$1[1:0]$8978 + attribute \src "libresoc.v:162759.3-162777.6" + wire width 64 $0\o$next[63:0]$8938 + attribute \src "libresoc.v:162658.3-162659.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:169937.3-169955.6" - wire $0\o_ok$next[0:0]$9237 - attribute \src "libresoc.v:169704.3-169705.25" + attribute \src "libresoc.v:162759.3-162777.6" + wire $0\o_ok$next[0:0]$8939 + attribute \src "libresoc.v:162660.3-162661.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:169865.3-169882.6" - wire $0\r_busy$next[0:0]$9188 - attribute \src "libresoc.v:169742.3-169743.29" + attribute \src "libresoc.v:162712.3-162729.6" + wire $0\r_busy$next[0:0]$8922 + attribute \src "libresoc.v:162672.3-162673.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire width 13 $0\sr_op__fn_unit$next[12:0]$9195 - attribute \src "libresoc.v:169708.3-169709.45" - wire width 13 $0\sr_op__fn_unit[12:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire width 64 $0\sr_op__imm_data__data$next[63:0]$9196 - attribute \src "libresoc.v:169710.3-169711.59" - wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__imm_data__ok$next[0:0]$9197 - attribute \src "libresoc.v:169712.3-169713.55" - wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire width 2 $0\sr_op__input_carry$next[1:0]$9198 - attribute \src "libresoc.v:169726.3-169727.53" - wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__input_cr$next[0:0]$9199 - attribute \src "libresoc.v:169730.3-169731.47" - wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire width 32 $0\sr_op__insn$next[31:0]$9200 - attribute \src "libresoc.v:169738.3-169739.39" - wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire width 7 $0\sr_op__insn_type$next[6:0]$9201 - attribute \src "libresoc.v:169706.3-169707.49" - wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__invert_in$next[0:0]$9202 - attribute \src "libresoc.v:169724.3-169725.49" - wire $0\sr_op__invert_in[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__is_32bit$next[0:0]$9203 - attribute \src "libresoc.v:169734.3-169735.47" - wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__is_signed$next[0:0]$9204 - attribute \src "libresoc.v:169736.3-169737.49" - wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__oe__oe$next[0:0]$9205 - attribute \src "libresoc.v:169718.3-169719.43" - wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__oe__ok$next[0:0]$9206 - attribute \src "libresoc.v:169720.3-169721.43" - wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__output_carry$next[0:0]$9207 - attribute \src "libresoc.v:169728.3-169729.55" - wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__output_cr$next[0:0]$9208 - attribute \src "libresoc.v:169732.3-169733.49" - wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__rc__ok$next[0:0]$9209 - attribute \src "libresoc.v:169716.3-169717.43" - wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__rc__rc$next[0:0]$9210 - attribute \src "libresoc.v:169714.3-169715.43" - wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $0\sr_op__write_cr0$next[0:0]$9211 - attribute \src "libresoc.v:169722.3-169723.49" - wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:169846.3-169864.6" - wire width 2 $0\xer_ca$next[1:0]$9183 - attribute \src "libresoc.v:169690.3-169691.29" - wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:169846.3-169864.6" - wire $0\xer_ca_ok$next[0:0]$9182 - attribute \src "libresoc.v:169692.3-169693.35" + attribute \src "libresoc.v:162778.3-162796.6" + wire width 64 $0\spr1$6$next[63:0]$8944 + attribute \src "libresoc.v:162654.3-162655.31" + wire width 64 $0\spr1$6[63:0]$8906 + attribute \src "libresoc.v:162047.14-162047.45" + wire width 64 $0\spr1$6[63:0]$8983 + attribute \src "libresoc.v:162778.3-162796.6" + wire $0\spr1_ok$next[0:0]$8945 + attribute \src "libresoc.v:162656.3-162657.31" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:162743.3-162758.6" + wire width 13 $0\spr_op__fn_unit$3$next[12:0]$8929 + attribute \src "libresoc.v:162664.3-162665.53" + wire width 13 $0\spr_op__fn_unit$3[12:0]$8913 + attribute \src "libresoc.v:162337.14-162337.44" + wire width 13 $0\spr_op__fn_unit$3[12:0]$8986 + attribute \src "libresoc.v:162743.3-162758.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8930 + attribute \src "libresoc.v:162666.3-162667.47" + wire width 32 $0\spr_op__insn$4[31:0]$8915 + attribute \src "libresoc.v:162346.14-162346.38" + wire width 32 $0\spr_op__insn$4[31:0]$8988 + attribute \src "libresoc.v:162743.3-162758.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8931 + attribute \src "libresoc.v:162662.3-162663.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8911 + attribute \src "libresoc.v:162501.13-162501.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8990 + attribute \src "libresoc.v:162743.3-162758.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8932 + attribute \src "libresoc.v:162668.3-162669.55" + wire $0\spr_op__is_32bit$5[0:0]$8917 + attribute \src "libresoc.v:162586.7-162586.34" + wire $0\spr_op__is_32bit$5[0:0]$8992 + attribute \src "libresoc.v:162854.3-162872.6" + wire width 2 $0\xer_ca$10$next[1:0]$8968 + attribute \src "libresoc.v:162638.3-162639.37" + wire width 2 $0\xer_ca$10[1:0]$8894 + attribute \src "libresoc.v:162593.13-162593.31" + wire width 2 $0\xer_ca$10[1:0]$8994 + attribute \src "libresoc.v:162854.3-162872.6" + wire $0\xer_ca_ok$next[0:0]$8969 + attribute \src "libresoc.v:162640.3-162641.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:169975.3-169993.6" - wire $0\xer_so$next[0:0]$9248 - attribute \src "libresoc.v:169694.3-169695.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:169975.3-169993.6" - wire $0\xer_so_ok$next[0:0]$9249 - attribute \src "libresoc.v:169696.3-169697.35" + attribute \src "libresoc.v:162835.3-162853.6" + wire width 2 $0\xer_ov$9$next[1:0]$8963 + attribute \src "libresoc.v:162642.3-162643.35" + wire width 2 $0\xer_ov$9[1:0]$8897 + attribute \src "libresoc.v:162611.13-162611.30" + wire width 2 $0\xer_ov$9[1:0]$8997 + attribute \src "libresoc.v:162835.3-162853.6" + wire $0\xer_ov_ok$next[0:0]$8962 + attribute \src "libresoc.v:162644.3-162645.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:162816.3-162834.6" + wire $0\xer_so$8$next[0:0]$8957 + attribute \src "libresoc.v:162646.3-162647.35" + wire $0\xer_so$8[0:0]$8900 + attribute \src "libresoc.v:162627.7-162627.24" + wire $0\xer_so$8[0:0]$9000 + attribute \src "libresoc.v:162816.3-162834.6" + wire $0\xer_so_ok$next[0:0]$8956 + attribute \src "libresoc.v:162648.3-162649.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:169956.3-169974.6" - wire width 4 $1\cr_a$next[3:0]$9244 - attribute \src "libresoc.v:168611.13-168611.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:169956.3-169974.6" - wire $1\cr_a_ok$next[0:0]$9245 - attribute \src "libresoc.v:168620.7-168620.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:169883.3-169895.6" - wire width 2 $1\muxid$next[1:0]$9193 - attribute \src "libresoc.v:169177.13-169177.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:169937.3-169955.6" - wire width 64 $1\o$next[63:0]$9238 - attribute \src "libresoc.v:169192.14-169192.38" + attribute \src "libresoc.v:162797.3-162815.6" + wire width 64 $1\fast1$7$next[63:0]$8953 + attribute \src "libresoc.v:162797.3-162815.6" + wire $1\fast1_ok$next[0:0]$8952 + attribute \src "libresoc.v:161993.7-161993.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:162730.3-162742.6" + wire width 2 $1\muxid$1$next[1:0]$8927 + attribute \src "libresoc.v:162759.3-162777.6" + wire width 64 $1\o$next[63:0]$8940 + attribute \src "libresoc.v:162015.14-162015.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:169937.3-169955.6" - wire $1\o_ok$next[0:0]$9239 - attribute \src "libresoc.v:169199.7-169199.18" + attribute \src "libresoc.v:162759.3-162777.6" + wire $1\o_ok$next[0:0]$8941 + attribute \src "libresoc.v:162022.7-162022.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:169865.3-169882.6" - wire $1\r_busy$next[0:0]$9189 - attribute \src "libresoc.v:169213.7-169213.20" + attribute \src "libresoc.v:162712.3-162729.6" + wire $1\r_busy$next[0:0]$8923 + attribute \src "libresoc.v:162036.7-162036.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire width 13 $1\sr_op__fn_unit$next[12:0]$9212 - attribute \src "libresoc.v:169238.14-169238.39" - wire width 13 $1\sr_op__fn_unit[12:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire width 64 $1\sr_op__imm_data__data$next[63:0]$9213 - attribute \src "libresoc.v:169275.14-169275.58" - wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__imm_data__ok$next[0:0]$9214 - attribute \src "libresoc.v:169284.7-169284.33" - wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire width 2 $1\sr_op__input_carry$next[1:0]$9215 - attribute \src "libresoc.v:169297.13-169297.38" - wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__input_cr$next[0:0]$9216 - attribute \src "libresoc.v:169314.7-169314.29" - wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire width 32 $1\sr_op__insn$next[31:0]$9217 - attribute \src "libresoc.v:169323.14-169323.33" - wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire width 7 $1\sr_op__insn_type$next[6:0]$9218 - attribute \src "libresoc.v:169406.13-169406.37" - wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__invert_in$next[0:0]$9219 - attribute \src "libresoc.v:169563.7-169563.30" - wire $1\sr_op__invert_in[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__is_32bit$next[0:0]$9220 - attribute \src "libresoc.v:169572.7-169572.29" - wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__is_signed$next[0:0]$9221 - attribute \src "libresoc.v:169581.7-169581.30" - wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__oe__oe$next[0:0]$9222 - attribute \src "libresoc.v:169590.7-169590.27" - wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__oe__ok$next[0:0]$9223 - attribute \src "libresoc.v:169599.7-169599.27" - wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__output_carry$next[0:0]$9224 - attribute \src "libresoc.v:169608.7-169608.33" - wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__output_cr$next[0:0]$9225 - attribute \src "libresoc.v:169617.7-169617.30" - wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__rc__ok$next[0:0]$9226 - attribute \src "libresoc.v:169626.7-169626.27" - wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__rc__rc$next[0:0]$9227 - attribute \src "libresoc.v:169635.7-169635.27" - wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:169896.3-169936.6" - wire $1\sr_op__write_cr0$next[0:0]$9228 - attribute \src "libresoc.v:169644.7-169644.30" - wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:169846.3-169864.6" - wire width 2 $1\xer_ca$next[1:0]$9185 - attribute \src "libresoc.v:169653.13-169653.26" - wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:169846.3-169864.6" - wire $1\xer_ca_ok$next[0:0]$9184 - attribute \src "libresoc.v:169664.7-169664.23" + attribute \src "libresoc.v:162778.3-162796.6" + wire width 64 $1\spr1$6$next[63:0]$8946 + attribute \src "libresoc.v:162778.3-162796.6" + wire $1\spr1_ok$next[0:0]$8947 + attribute \src "libresoc.v:162052.7-162052.21" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:162743.3-162758.6" + wire width 13 $1\spr_op__fn_unit$3$next[12:0]$8933 + attribute \src "libresoc.v:162743.3-162758.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8934 + attribute \src "libresoc.v:162743.3-162758.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8935 + attribute \src "libresoc.v:162743.3-162758.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8936 + attribute \src "libresoc.v:162854.3-162872.6" + wire width 2 $1\xer_ca$10$next[1:0]$8970 + attribute \src "libresoc.v:162854.3-162872.6" + wire $1\xer_ca_ok$next[0:0]$8971 + attribute \src "libresoc.v:162600.7-162600.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:169975.3-169993.6" - wire $1\xer_so$next[0:0]$9250 - attribute \src "libresoc.v:169673.7-169673.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:169975.3-169993.6" - wire $1\xer_so_ok$next[0:0]$9251 - attribute \src "libresoc.v:169682.7-169682.23" + attribute \src "libresoc.v:162835.3-162853.6" + wire width 2 $1\xer_ov$9$next[1:0]$8965 + attribute \src "libresoc.v:162835.3-162853.6" + wire $1\xer_ov_ok$next[0:0]$8964 + attribute \src "libresoc.v:162616.7-162616.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:162816.3-162834.6" + wire $1\xer_so$8$next[0:0]$8959 + attribute \src "libresoc.v:162816.3-162834.6" + wire $1\xer_so_ok$next[0:0]$8958 + attribute \src "libresoc.v:162632.7-162632.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:169956.3-169974.6" - wire $2\cr_a_ok$next[0:0]$9246 - attribute \src "libresoc.v:169937.3-169955.6" - wire $2\o_ok$next[0:0]$9240 - attribute \src "libresoc.v:169865.3-169882.6" - wire $2\r_busy$next[0:0]$9190 - attribute \src "libresoc.v:169896.3-169936.6" - wire width 64 $2\sr_op__imm_data__data$next[63:0]$9229 - attribute \src "libresoc.v:169896.3-169936.6" - wire $2\sr_op__imm_data__ok$next[0:0]$9230 - attribute \src "libresoc.v:169896.3-169936.6" - wire $2\sr_op__oe__oe$next[0:0]$9231 - attribute \src "libresoc.v:169896.3-169936.6" - wire $2\sr_op__oe__ok$next[0:0]$9232 - attribute \src "libresoc.v:169896.3-169936.6" - wire $2\sr_op__rc__ok$next[0:0]$9233 - attribute \src "libresoc.v:169896.3-169936.6" - wire $2\sr_op__rc__rc$next[0:0]$9234 - attribute \src "libresoc.v:169846.3-169864.6" - wire $2\xer_ca_ok$next[0:0]$9186 - attribute \src "libresoc.v:169975.3-169993.6" - wire $2\xer_so_ok$next[0:0]$9252 - attribute \src "libresoc.v:169689.18-169689.118" - wire $and$libresoc.v:169689$9153_Y + attribute \src "libresoc.v:162797.3-162815.6" + wire $2\fast1_ok$next[0:0]$8954 + attribute \src "libresoc.v:162759.3-162777.6" + wire $2\o_ok$next[0:0]$8942 + attribute \src "libresoc.v:162712.3-162729.6" + wire $2\r_busy$next[0:0]$8924 + attribute \src "libresoc.v:162778.3-162796.6" + wire $2\spr1_ok$next[0:0]$8948 + attribute \src "libresoc.v:162854.3-162872.6" + wire $2\xer_ca_ok$next[0:0]$8972 + attribute \src "libresoc.v:162835.3-162853.6" + wire $2\xer_ov_ok$next[0:0]$8966 + attribute \src "libresoc.v:162816.3-162834.6" + wire $2\xer_so_ok$next[0:0]$8960 + attribute \src "libresoc.v:162637.18-162637.118" + wire $and$libresoc.v:162637$8892_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 55 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 24 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$89 + wire width 64 \fast1$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$next + wire width 64 output 26 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 25 \cr_a_ok + wire width 64 \fast1$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$88 + wire output 27 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$90 + wire \fast1_ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$next - attribute \src "libresoc.v:168602.7-168602.15" + wire \fast1_ok$next + attribute \src "libresoc.v:161975.7-161975.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \input_muxid + wire width 2 input 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \input_muxid$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc$41 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_sr_op__fn_unit$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__data$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__imm_data__ok$25 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__input_cr$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_sr_op__insn$38 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_sr_op__insn_type$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__invert_in$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_32bit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__is_signed$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__oe$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__oe__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_carry$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__output_cr$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__rc__rc$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_sr_op__write_cr0$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca + wire width 2 output 17 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 16 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 15 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$43 + wire width 64 input 9 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so + wire width 64 input 10 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr1$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr1$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr1_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$42 + wire width 64 \spr_main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_fast1$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \main_muxid + wire width 2 \spr_main_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \main_muxid$44 + wire width 2 \spr_main_muxid$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o + wire width 64 \spr_main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra + wire \spr_main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb + wire width 64 \spr_main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rc + wire width 64 \spr_main_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_spr1$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_spr1_ok attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -346491,7 +337245,7 @@ module \pipe1$110 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_sr_op__fn_unit + wire width 13 \spr_main_spr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -346507,35 +337261,11 @@ module \pipe1$110 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_sr_op__fn_unit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_sr_op__imm_data__data$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__imm_data__ok$48 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_sr_op__input_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__input_cr$57 + wire width 13 \spr_main_spr_op__fn_unit$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_sr_op__insn + wire width 32 \spr_main_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_sr_op__insn$61 + wire width 32 \spr_main_spr_op__insn$14 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -346611,7 +337341,7 @@ module \pipe1$110 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_sr_op__insn_type + wire width 7 \spr_main_spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -346687,97 +337417,29 @@ module \pipe1$110 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_sr_op__insn_type$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__invert_in$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_32bit$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__is_signed$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__oe$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__oe__ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_carry$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__output_cr$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__rc__rc$49 + wire width 7 \spr_main_spr_op__insn_type$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__write_cr0 + wire \spr_main_spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_sr_op__write_cr0$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \main_xer_ca + wire \spr_main_spr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_so$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 32 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 2 \n_valid_o + wire width 2 \spr_main_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 22 \o + wire width 2 \spr_main_xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$85 + wire \spr_main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \spr_main_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next + wire width 2 \spr_main_xer_ov$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 23 \o_ok + wire \spr_main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \spr_main_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$86 + wire \spr_main_xer_so$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 31 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 30 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$64 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 50 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 51 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 52 \rc + wire \spr_main_xer_so_ok attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -346793,7 +337455,7 @@ module \pipe1$110 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \sr_op__fn_unit + wire width 13 input 6 \spr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -346809,7 +337471,7 @@ module \pipe1$110 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 34 \sr_op__fn_unit$3 + wire width 13 \spr_op__fn_unit$26 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -346825,61 +337487,17 @@ module \pipe1$110 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \sr_op__fn_unit$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \sr_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 35 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 36 \sr_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 15 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 43 \sr_op__input_carry$12 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \sr_op__input_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$80 + wire width 13 output 19 \spr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$next + wire width 13 \spr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 21 \sr_op__insn + wire width 32 input 7 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 49 \sr_op__insn$18 + wire width 32 \spr_op__insn$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$84 + wire width 32 output 20 \spr_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$next + wire width 32 \spr_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -346955,7 +337573,7 @@ module \pipe1$110 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \sr_op__insn_type + wire width 7 input 5 \spr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -347031,7 +337649,9 @@ module \pipe1$110 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 33 \sr_op__insn_type$2 + wire width 7 output 18 \spr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -347081,695 +337701,497 @@ module \pipe1$110 attribute \enum_value_0101101 "OP_MFCR" attribute \enum_value_0101110 "OP_MFSPR" attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \sr_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 47 \sr_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 48 \sr_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \sr_op__output_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \sr_op__output_cr$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 38 \sr_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 37 \sr_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$72 + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$next + wire width 7 \spr_op__insn_type$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \sr_op__write_cr0 + wire input 8 \spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \sr_op__write_cr0$10 + wire \spr_op__is_32bit$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$76 + wire output 21 \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 28 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 54 \xer_ca$20 + wire \spr_op__is_32bit$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \xer_ca$63 + wire width 2 input 14 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$94 + wire width 2 output 32 \xer_ca$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$next + wire width 2 \xer_ca$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 29 \xer_ca_ok + wire width 2 \xer_ca$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$95 + wire output 33 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$96 + wire \xer_ca_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 13 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 26 \xer_so + wire width 2 \xer_ov$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 30 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 53 \xer_so$19 + wire input 12 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$91 + wire \xer_so$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$next + wire output 28 \xer_so$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 27 \xer_so_ok + wire \xer_so$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$92 + wire output 29 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$93 + wire \xer_so_ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:169689$9153 + cell $and $and$libresoc.v:162637$8892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$64 + connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $and$libresoc.v:169689$9153_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:169744.15-169791.4" - cell \input$113 \input - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$21 - connect \ra \input_ra - connect \ra$19 \input_ra$39 - connect \rb \input_rb - connect \rb$20 \input_rb$40 - connect \rc \input_rc - connect \rc$21 \input_rc$41 - connect \sr_op__fn_unit \input_sr_op__fn_unit - connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$23 - connect \sr_op__imm_data__data \input_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$24 - connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$25 - connect \sr_op__input_carry \input_sr_op__input_carry - connect \sr_op__input_carry$12 \input_sr_op__input_carry$32 - connect \sr_op__input_cr \input_sr_op__input_cr - connect \sr_op__input_cr$14 \input_sr_op__input_cr$34 - connect \sr_op__insn \input_sr_op__insn - connect \sr_op__insn$18 \input_sr_op__insn$38 - connect \sr_op__insn_type \input_sr_op__insn_type - connect \sr_op__insn_type$2 \input_sr_op__insn_type$22 - connect \sr_op__invert_in \input_sr_op__invert_in - connect \sr_op__invert_in$11 \input_sr_op__invert_in$31 - connect \sr_op__is_32bit \input_sr_op__is_32bit - connect \sr_op__is_32bit$16 \input_sr_op__is_32bit$36 - connect \sr_op__is_signed \input_sr_op__is_signed - connect \sr_op__is_signed$17 \input_sr_op__is_signed$37 - connect \sr_op__oe__oe \input_sr_op__oe__oe - connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$28 - connect \sr_op__oe__ok \input_sr_op__oe__ok - connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$29 - connect \sr_op__output_carry \input_sr_op__output_carry - connect \sr_op__output_carry$13 \input_sr_op__output_carry$33 - connect \sr_op__output_cr \input_sr_op__output_cr - connect \sr_op__output_cr$15 \input_sr_op__output_cr$35 - connect \sr_op__rc__ok \input_sr_op__rc__ok - connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$27 - connect \sr_op__rc__rc \input_sr_op__rc__rc - connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$26 - connect \sr_op__write_cr0 \input_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$30 - connect \xer_ca \input_xer_ca - connect \xer_ca$23 \input_xer_ca$43 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$42 + connect \Y $and$libresoc.v:162637$8892_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:169792.14-169837.4" - cell \main$114 \main - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$44 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \rc \main_rc - connect \sr_op__fn_unit \main_sr_op__fn_unit - connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$46 - connect \sr_op__imm_data__data \main_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$47 - connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$48 - connect \sr_op__input_carry \main_sr_op__input_carry - connect \sr_op__input_carry$12 \main_sr_op__input_carry$55 - connect \sr_op__input_cr \main_sr_op__input_cr - connect \sr_op__input_cr$14 \main_sr_op__input_cr$57 - connect \sr_op__insn \main_sr_op__insn - connect \sr_op__insn$18 \main_sr_op__insn$61 - connect \sr_op__insn_type \main_sr_op__insn_type - connect \sr_op__insn_type$2 \main_sr_op__insn_type$45 - connect \sr_op__invert_in \main_sr_op__invert_in - connect \sr_op__invert_in$11 \main_sr_op__invert_in$54 - connect \sr_op__is_32bit \main_sr_op__is_32bit - connect \sr_op__is_32bit$16 \main_sr_op__is_32bit$59 - connect \sr_op__is_signed \main_sr_op__is_signed - connect \sr_op__is_signed$17 \main_sr_op__is_signed$60 - connect \sr_op__oe__oe \main_sr_op__oe__oe - connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$51 - connect \sr_op__oe__ok \main_sr_op__oe__ok - connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$52 - connect \sr_op__output_carry \main_sr_op__output_carry - connect \sr_op__output_carry$13 \main_sr_op__output_carry$56 - connect \sr_op__output_cr \main_sr_op__output_cr - connect \sr_op__output_cr$15 \main_sr_op__output_cr$58 - connect \sr_op__rc__ok \main_sr_op__rc__ok - connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$50 - connect \sr_op__rc__rc \main_sr_op__rc__rc - connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$49 - connect \sr_op__write_cr0 \main_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$53 - connect \xer_ca \main_xer_ca - connect \xer_so \main_xer_so - connect \xer_so$19 \main_xer_so$62 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:169838.11-169841.4" - cell \n$112 \n + attribute \src "libresoc.v:162674.10-162677.4" + cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:169842.11-169845.4" - cell \p$111 \p + attribute \src "libresoc.v:162678.10-162681.4" + cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:168602.7-168602.20" - process $proc$libresoc.v:168602$9253 + attribute \module_not_derived 1 + attribute \src "libresoc.v:162682.12-162711.4" + cell \spr_main \spr_main + connect \fast1 \spr_main_fast1 + connect \fast1$7 \spr_main_fast1$17 + connect \fast1_ok \spr_main_fast1_ok + connect \muxid \spr_main_muxid + connect \muxid$1 \spr_main_muxid$11 + connect \o \spr_main_o + connect \o_ok \spr_main_o_ok + connect \ra \spr_main_ra + connect \spr1 \spr_main_spr1 + connect \spr1$6 \spr_main_spr1$16 + connect \spr1_ok \spr_main_spr1_ok + connect \spr_op__fn_unit \spr_main_spr_op__fn_unit + connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 + connect \spr_op__insn \spr_main_spr_op__insn + connect \spr_op__insn$4 \spr_main_spr_op__insn$14 + connect \spr_op__insn_type \spr_main_spr_op__insn_type + connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 + connect \spr_op__is_32bit \spr_main_spr_op__is_32bit + connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 + connect \xer_ca \spr_main_xer_ca + connect \xer_ca$10 \spr_main_xer_ca$20 + connect \xer_ca_ok \spr_main_xer_ca_ok + connect \xer_ov \spr_main_xer_ov + connect \xer_ov$9 \spr_main_xer_ov$19 + connect \xer_ov_ok \spr_main_xer_ov_ok + connect \xer_so \spr_main_xer_so + connect \xer_so$8 \spr_main_xer_so$18 + connect \xer_so_ok \spr_main_xer_so_ok + end + attribute \src "libresoc.v:161975.7-161975.20" + process $proc$libresoc.v:161975$8973 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168611.13-168611.24" - process $proc$libresoc.v:168611$9254 + attribute \src "libresoc.v:161988.14-161988.46" + process $proc$libresoc.v:161988$8974 assign { } { } - assign $1\cr_a[3:0] 4'0000 + assign $0\fast1$7[63:0]$8975 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \cr_a $1\cr_a[3:0] + update \fast1$7 $0\fast1$7[63:0]$8975 end - attribute \src "libresoc.v:168620.7-168620.21" - process $proc$libresoc.v:168620$9255 + attribute \src "libresoc.v:161993.7-161993.22" + process $proc$libresoc.v:161993$8976 assign { } { } - assign $1\cr_a_ok[0:0] 1'0 + assign $1\fast1_ok[0:0] 1'0 sync always sync init - update \cr_a_ok $1\cr_a_ok[0:0] + update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:169177.13-169177.25" - process $proc$libresoc.v:169177$9256 + attribute \src "libresoc.v:162002.13-162002.29" + process $proc$libresoc.v:162002$8977 assign { } { } - assign $1\muxid[1:0] 2'00 + assign $0\muxid$1[1:0]$8978 2'00 sync always sync init - update \muxid $1\muxid[1:0] + update \muxid$1 $0\muxid$1[1:0]$8978 end - attribute \src "libresoc.v:169192.14-169192.38" - process $proc$libresoc.v:169192$9257 + attribute \src "libresoc.v:162015.14-162015.38" + process $proc$libresoc.v:162015$8979 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:169199.7-169199.18" - process $proc$libresoc.v:169199$9258 + attribute \src "libresoc.v:162022.7-162022.18" + process $proc$libresoc.v:162022$8980 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:169213.7-169213.20" - process $proc$libresoc.v:169213$9259 + attribute \src "libresoc.v:162036.7-162036.20" + process $proc$libresoc.v:162036$8981 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:169238.14-169238.39" - process $proc$libresoc.v:169238$9260 - assign { } { } - assign $1\sr_op__fn_unit[12:0] 13'0000000000000 - sync always - sync init - update \sr_op__fn_unit $1\sr_op__fn_unit[12:0] - end - attribute \src "libresoc.v:169275.14-169275.58" - process $proc$libresoc.v:169275$9261 - assign { } { } - assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:169284.7-169284.33" - process $proc$libresoc.v:169284$9262 - assign { } { } - assign $1\sr_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:169297.13-169297.38" - process $proc$libresoc.v:169297$9263 - assign { } { } - assign $1\sr_op__input_carry[1:0] 2'00 - sync always - sync init - update \sr_op__input_carry $1\sr_op__input_carry[1:0] - end - attribute \src "libresoc.v:169314.7-169314.29" - process $proc$libresoc.v:169314$9264 - assign { } { } - assign $1\sr_op__input_cr[0:0] 1'0 - sync always - sync init - update \sr_op__input_cr $1\sr_op__input_cr[0:0] - end - attribute \src "libresoc.v:169323.14-169323.33" - process $proc$libresoc.v:169323$9265 - assign { } { } - assign $1\sr_op__insn[31:0] 0 - sync always - sync init - update \sr_op__insn $1\sr_op__insn[31:0] - end - attribute \src "libresoc.v:169406.13-169406.37" - process $proc$libresoc.v:169406$9266 - assign { } { } - assign $1\sr_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \sr_op__insn_type $1\sr_op__insn_type[6:0] - end - attribute \src "libresoc.v:169563.7-169563.30" - process $proc$libresoc.v:169563$9267 - assign { } { } - assign $1\sr_op__invert_in[0:0] 1'0 - sync always - sync init - update \sr_op__invert_in $1\sr_op__invert_in[0:0] - end - attribute \src "libresoc.v:169572.7-169572.29" - process $proc$libresoc.v:169572$9268 - assign { } { } - assign $1\sr_op__is_32bit[0:0] 1'0 - sync always - sync init - update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] - end - attribute \src "libresoc.v:169581.7-169581.30" - process $proc$libresoc.v:169581$9269 + attribute \src "libresoc.v:162047.14-162047.45" + process $proc$libresoc.v:162047$8982 assign { } { } - assign $1\sr_op__is_signed[0:0] 1'0 + assign $0\spr1$6[63:0]$8983 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__is_signed $1\sr_op__is_signed[0:0] + update \spr1$6 $0\spr1$6[63:0]$8983 end - attribute \src "libresoc.v:169590.7-169590.27" - process $proc$libresoc.v:169590$9270 + attribute \src "libresoc.v:162052.7-162052.21" + process $proc$libresoc.v:162052$8984 assign { } { } - assign $1\sr_op__oe__oe[0:0] 1'0 + assign $1\spr1_ok[0:0] 1'0 sync always sync init - update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] + update \spr1_ok $1\spr1_ok[0:0] end - attribute \src "libresoc.v:169599.7-169599.27" - process $proc$libresoc.v:169599$9271 + attribute \src "libresoc.v:162337.14-162337.44" + process $proc$libresoc.v:162337$8985 assign { } { } - assign $1\sr_op__oe__ok[0:0] 1'0 + assign $0\spr_op__fn_unit$3[12:0]$8986 13'0000000000000 sync always sync init - update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8986 end - attribute \src "libresoc.v:169608.7-169608.33" - process $proc$libresoc.v:169608$9272 + attribute \src "libresoc.v:162346.14-162346.38" + process $proc$libresoc.v:162346$8987 assign { } { } - assign $1\sr_op__output_carry[0:0] 1'0 + assign $0\spr_op__insn$4[31:0]$8988 0 sync always sync init - update \sr_op__output_carry $1\sr_op__output_carry[0:0] + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8988 end - attribute \src "libresoc.v:169617.7-169617.30" - process $proc$libresoc.v:169617$9273 + attribute \src "libresoc.v:162501.13-162501.42" + process $proc$libresoc.v:162501$8989 assign { } { } - assign $1\sr_op__output_cr[0:0] 1'0 + assign $0\spr_op__insn_type$2[6:0]$8990 7'0000000 sync always sync init - update \sr_op__output_cr $1\sr_op__output_cr[0:0] + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8990 end - attribute \src "libresoc.v:169626.7-169626.27" - process $proc$libresoc.v:169626$9274 + attribute \src "libresoc.v:162586.7-162586.34" + process $proc$libresoc.v:162586$8991 assign { } { } - assign $1\sr_op__rc__ok[0:0] 1'0 + assign $0\spr_op__is_32bit$5[0:0]$8992 1'0 sync always sync init - update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8992 end - attribute \src "libresoc.v:169635.7-169635.27" - process $proc$libresoc.v:169635$9275 + attribute \src "libresoc.v:162593.13-162593.31" + process $proc$libresoc.v:162593$8993 assign { } { } - assign $1\sr_op__rc__rc[0:0] 1'0 + assign $0\xer_ca$10[1:0]$8994 2'00 sync always sync init - update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] + update \xer_ca$10 $0\xer_ca$10[1:0]$8994 end - attribute \src "libresoc.v:169644.7-169644.30" - process $proc$libresoc.v:169644$9276 + attribute \src "libresoc.v:162600.7-162600.23" + process $proc$libresoc.v:162600$8995 assign { } { } - assign $1\sr_op__write_cr0[0:0] 1'0 + assign $1\xer_ca_ok[0:0] 1'0 sync always sync init - update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] + update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:169653.13-169653.26" - process $proc$libresoc.v:169653$9277 + attribute \src "libresoc.v:162611.13-162611.30" + process $proc$libresoc.v:162611$8996 assign { } { } - assign $1\xer_ca[1:0] 2'00 + assign $0\xer_ov$9[1:0]$8997 2'00 sync always sync init - update \xer_ca $1\xer_ca[1:0] + update \xer_ov$9 $0\xer_ov$9[1:0]$8997 end - attribute \src "libresoc.v:169664.7-169664.23" - process $proc$libresoc.v:169664$9278 + attribute \src "libresoc.v:162616.7-162616.23" + process $proc$libresoc.v:162616$8998 assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 + assign $1\xer_ov_ok[0:0] 1'0 sync always sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] + update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:169673.7-169673.20" - process $proc$libresoc.v:169673$9279 + attribute \src "libresoc.v:162627.7-162627.24" + process $proc$libresoc.v:162627$8999 assign { } { } - assign $1\xer_so[0:0] 1'0 + assign $0\xer_so$8[0:0]$9000 1'0 sync always sync init - update \xer_so $1\xer_so[0:0] + update \xer_so$8 $0\xer_so$8[0:0]$9000 end - attribute \src "libresoc.v:169682.7-169682.23" - process $proc$libresoc.v:169682$9280 + attribute \src "libresoc.v:162632.7-162632.23" + process $proc$libresoc.v:162632$9001 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:169690.3-169691.29" - process $proc$libresoc.v:169690$9154 + attribute \src "libresoc.v:162638.3-162639.37" + process $proc$libresoc.v:162638$8893 assign { } { } - assign $0\xer_ca[1:0] \xer_ca$next + assign $0\xer_ca$10[1:0]$8894 \xer_ca$10$next sync posedge \coresync_clk - update \xer_ca $0\xer_ca[1:0] + update \xer_ca$10 $0\xer_ca$10[1:0]$8894 end - attribute \src "libresoc.v:169692.3-169693.35" - process $proc$libresoc.v:169692$9155 + attribute \src "libresoc.v:162640.3-162641.35" + process $proc$libresoc.v:162640$8895 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:169694.3-169695.29" - process $proc$libresoc.v:169694$9156 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:169696.3-169697.35" - process $proc$libresoc.v:169696$9157 + attribute \src "libresoc.v:162642.3-162643.35" + process $proc$libresoc.v:162642$8896 assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next + assign $0\xer_ov$9[1:0]$8897 \xer_ov$9$next sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] + update \xer_ov$9 $0\xer_ov$9[1:0]$8897 end - attribute \src "libresoc.v:169698.3-169699.25" - process $proc$libresoc.v:169698$9158 + attribute \src "libresoc.v:162644.3-162645.35" + process $proc$libresoc.v:162644$8898 assign { } { } - assign $0\cr_a[3:0] \cr_a$next + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] + update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:169700.3-169701.31" - process $proc$libresoc.v:169700$9159 + attribute \src "libresoc.v:162646.3-162647.35" + process $proc$libresoc.v:162646$8899 assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next + assign $0\xer_so$8[0:0]$8900 \xer_so$8$next sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] + update \xer_so$8 $0\xer_so$8[0:0]$8900 end - attribute \src "libresoc.v:169702.3-169703.19" - process $proc$libresoc.v:169702$9160 + attribute \src "libresoc.v:162648.3-162649.35" + process $proc$libresoc.v:162648$8901 assign { } { } - assign $0\o[63:0] \o$next + assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk - update \o $0\o[63:0] + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:169704.3-169705.25" - process $proc$libresoc.v:169704$9161 + attribute \src "libresoc.v:162650.3-162651.33" + process $proc$libresoc.v:162650$8902 assign { } { } - assign $0\o_ok[0:0] \o_ok$next + assign $0\fast1$7[63:0]$8903 \fast1$7$next sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + update \fast1$7 $0\fast1$7[63:0]$8903 end - attribute \src "libresoc.v:169706.3-169707.49" - process $proc$libresoc.v:169706$9162 + attribute \src "libresoc.v:162652.3-162653.33" + process $proc$libresoc.v:162652$8904 assign { } { } - assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next + assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk - update \sr_op__insn_type $0\sr_op__insn_type[6:0] + update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:169708.3-169709.45" - process $proc$libresoc.v:169708$9163 + attribute \src "libresoc.v:162654.3-162655.31" + process $proc$libresoc.v:162654$8905 assign { } { } - assign $0\sr_op__fn_unit[12:0] \sr_op__fn_unit$next + assign $0\spr1$6[63:0]$8906 \spr1$6$next sync posedge \coresync_clk - update \sr_op__fn_unit $0\sr_op__fn_unit[12:0] + update \spr1$6 $0\spr1$6[63:0]$8906 end - attribute \src "libresoc.v:169710.3-169711.59" - process $proc$libresoc.v:169710$9164 + attribute \src "libresoc.v:162656.3-162657.31" + process $proc$libresoc.v:162656$8907 assign { } { } - assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next + assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk - update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] + update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:169712.3-169713.55" - process $proc$libresoc.v:169712$9165 + attribute \src "libresoc.v:162658.3-162659.19" + process $proc$libresoc.v:162658$8908 assign { } { } - assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] + update \o $0\o[63:0] end - attribute \src "libresoc.v:169714.3-169715.43" - process $proc$libresoc.v:169714$9166 + attribute \src "libresoc.v:162660.3-162661.25" + process $proc$libresoc.v:162660$8909 assign { } { } - assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:169716.3-169717.43" - process $proc$libresoc.v:169716$9167 + attribute \src "libresoc.v:162662.3-162663.57" + process $proc$libresoc.v:162662$8910 assign { } { } - assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next + assign $0\spr_op__insn_type$2[6:0]$8911 \spr_op__insn_type$2$next sync posedge \coresync_clk - update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8911 end - attribute \src "libresoc.v:169718.3-169719.43" - process $proc$libresoc.v:169718$9168 + attribute \src "libresoc.v:162664.3-162665.53" + process $proc$libresoc.v:162664$8912 assign { } { } - assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next + assign $0\spr_op__fn_unit$3[12:0]$8913 \spr_op__fn_unit$3$next sync posedge \coresync_clk - update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8913 end - attribute \src "libresoc.v:169720.3-169721.43" - process $proc$libresoc.v:169720$9169 + attribute \src "libresoc.v:162666.3-162667.47" + process $proc$libresoc.v:162666$8914 assign { } { } - assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next + assign $0\spr_op__insn$4[31:0]$8915 \spr_op__insn$4$next sync posedge \coresync_clk - update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8915 end - attribute \src "libresoc.v:169722.3-169723.49" - process $proc$libresoc.v:169722$9170 + attribute \src "libresoc.v:162668.3-162669.55" + process $proc$libresoc.v:162668$8916 assign { } { } - assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next + assign $0\spr_op__is_32bit$5[0:0]$8917 \spr_op__is_32bit$5$next sync posedge \coresync_clk - update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8917 end - attribute \src "libresoc.v:169724.3-169725.49" - process $proc$libresoc.v:169724$9171 + attribute \src "libresoc.v:162670.3-162671.33" + process $proc$libresoc.v:162670$8918 assign { } { } - assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next + assign $0\muxid$1[1:0]$8919 \muxid$1$next sync posedge \coresync_clk - update \sr_op__invert_in $0\sr_op__invert_in[0:0] + update \muxid$1 $0\muxid$1[1:0]$8919 end - attribute \src "libresoc.v:169726.3-169727.53" - process $proc$libresoc.v:169726$9172 + attribute \src "libresoc.v:162672.3-162673.29" + process $proc$libresoc.v:162672$8920 assign { } { } - assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next + assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk - update \sr_op__input_carry $0\sr_op__input_carry[1:0] + update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:169728.3-169729.55" - process $proc$libresoc.v:169728$9173 + attribute \src "libresoc.v:162712.3-162729.6" + process $proc$libresoc.v:162712$8921 assign { } { } - assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next - sync posedge \coresync_clk - update \sr_op__output_carry $0\sr_op__output_carry[0:0] - end - attribute \src "libresoc.v:169730.3-169731.47" - process $proc$libresoc.v:169730$9174 assign { } { } - assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next - sync posedge \coresync_clk - update \sr_op__input_cr $0\sr_op__input_cr[0:0] - end - attribute \src "libresoc.v:169732.3-169733.49" - process $proc$libresoc.v:169732$9175 assign { } { } - assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next - sync posedge \coresync_clk - update \sr_op__output_cr $0\sr_op__output_cr[0:0] + assign $0\r_busy$next[0:0]$8922 $2\r_busy$next[0:0]$8924 + attribute \src "libresoc.v:162713.5-162713.29" + switch \initial + attribute \src "libresoc.v:162713.9-162713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8923 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8923 1'0 + case + assign $1\r_busy$next[0:0]$8923 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8924 1'0 + case + assign $2\r_busy$next[0:0]$8924 $1\r_busy$next[0:0]$8923 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8922 end - attribute \src "libresoc.v:169734.3-169735.47" - process $proc$libresoc.v:169734$9176 + attribute \src "libresoc.v:162730.3-162742.6" + process $proc$libresoc.v:162730$8925 assign { } { } - assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next - sync posedge \coresync_clk - update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] - end - attribute \src "libresoc.v:169736.3-169737.49" - process $proc$libresoc.v:169736$9177 assign { } { } - assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next - sync posedge \coresync_clk - update \sr_op__is_signed $0\sr_op__is_signed[0:0] + assign $0\muxid$1$next[1:0]$8926 $1\muxid$1$next[1:0]$8927 + attribute \src "libresoc.v:162731.5-162731.29" + switch \initial + attribute \src "libresoc.v:162731.9-162731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8927 \muxid$24 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8927 \muxid$24 + case + assign $1\muxid$1$next[1:0]$8927 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8926 end - attribute \src "libresoc.v:169738.3-169739.39" - process $proc$libresoc.v:169738$9178 + attribute \src "libresoc.v:162743.3-162758.6" + process $proc$libresoc.v:162743$8928 assign { } { } - assign $0\sr_op__insn[31:0] \sr_op__insn$next - sync posedge \coresync_clk - update \sr_op__insn $0\sr_op__insn[31:0] - end - attribute \src "libresoc.v:169740.3-169741.27" - process $proc$libresoc.v:169740$9179 assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:169742.3-169743.29" - process $proc$libresoc.v:169742$9180 assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:169846.3-169864.6" - process $proc$libresoc.v:169846$9181 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9183 $1\xer_ca$next[1:0]$9185 - assign $0\xer_ca_ok$next[0:0]$9182 $2\xer_ca_ok$next[0:0]$9186 - attribute \src "libresoc.v:169847.5-169847.29" + assign $0\spr_op__fn_unit$3$next[12:0]$8929 $1\spr_op__fn_unit$3$next[12:0]$8933 + assign $0\spr_op__insn$4$next[31:0]$8930 $1\spr_op__insn$4$next[31:0]$8934 + assign $0\spr_op__insn_type$2$next[6:0]$8931 $1\spr_op__insn_type$2$next[6:0]$8935 + assign $0\spr_op__is_32bit$5$next[0:0]$8932 $1\spr_op__is_32bit$5$next[0:0]$8936 + attribute \src "libresoc.v:162744.5-162744.29" switch \initial - attribute \src "libresoc.v:169847.9-169847.17" + attribute \src "libresoc.v:162744.9-162744.17" case 1'1 case end @@ -347779,38 +338201,40 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9184 $1\xer_ca$next[1:0]$9185 } { \xer_ca_ok$95 \xer_ca$94 } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8936 $1\spr_op__insn$4$next[31:0]$8934 $1\spr_op__fn_unit$3$next[12:0]$8933 $1\spr_op__insn_type$2$next[6:0]$8935 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9184 $1\xer_ca$next[1:0]$9185 } { \xer_ca_ok$95 \xer_ca$94 } - case - assign $1\xer_ca_ok$next[0:0]$9184 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9185 \xer_ca - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$9186 1'0 + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8936 $1\spr_op__insn$4$next[31:0]$8934 $1\spr_op__fn_unit$3$next[12:0]$8933 $1\spr_op__insn_type$2$next[6:0]$8935 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } case - assign $2\xer_ca_ok$next[0:0]$9186 $1\xer_ca_ok$next[0:0]$9184 + assign $1\spr_op__fn_unit$3$next[12:0]$8933 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8934 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8935 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8936 \spr_op__is_32bit$5 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9182 - update \xer_ca$next $0\xer_ca$next[1:0]$9183 + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[12:0]$8929 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8930 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8931 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8932 end - attribute \src "libresoc.v:169865.3-169882.6" - process $proc$libresoc.v:169865$9187 + attribute \src "libresoc.v:162759.3-162777.6" + process $proc$libresoc.v:162759$8937 + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9188 $2\r_busy$next[0:0]$9190 - attribute \src "libresoc.v:169866.5-169866.29" + assign $0\o$next[63:0]$8938 $1\o$next[63:0]$8940 + assign { } { } + assign $0\o_ok$next[0:0]$8939 $2\o_ok$next[0:0]$8942 + attribute \src "libresoc.v:162760.5-162760.29" switch \initial - attribute \src "libresoc.v:169866.9-169866.17" + attribute \src "libresoc.v:162760.9-162760.17" case 1'1 case end @@ -347819,34 +338243,42 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9189 1'1 + assign { } { } + assign { $1\o_ok$next[0:0]$8941 $1\o$next[63:0]$8940 } { \o_ok$30 \o$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9189 1'0 + assign { } { } + assign { $1\o_ok$next[0:0]$8941 $1\o$next[63:0]$8940 } { \o_ok$30 \o$29 } case - assign $1\r_busy$next[0:0]$9189 \r_busy + assign $1\o$next[63:0]$8940 \o + assign $1\o_ok$next[0:0]$8941 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9190 1'0 + assign $2\o_ok$next[0:0]$8942 1'0 case - assign $2\r_busy$next[0:0]$9190 $1\r_busy$next[0:0]$9189 + assign $2\o_ok$next[0:0]$8942 $1\o_ok$next[0:0]$8941 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9188 + update \o$next $0\o$next[63:0]$8938 + update \o_ok$next $0\o_ok$next[0:0]$8939 end - attribute \src "libresoc.v:169883.3-169895.6" - process $proc$libresoc.v:169883$9191 + attribute \src "libresoc.v:162778.3-162796.6" + process $proc$libresoc.v:162778$8943 + assign { } { } + assign { } { } + assign { } { } assign { } { } + assign $0\spr1$6$next[63:0]$8944 $1\spr1$6$next[63:0]$8946 assign { } { } - assign $0\muxid$next[1:0]$9192 $1\muxid$next[1:0]$9193 - attribute \src "libresoc.v:169884.5-169884.29" + assign $0\spr1_ok$next[0:0]$8945 $2\spr1_ok$next[0:0]$8948 + attribute \src "libresoc.v:162779.5-162779.29" switch \initial - attribute \src "libresoc.v:169884.9-169884.17" + attribute \src "libresoc.v:162779.9-162779.17" case 1'1 case end @@ -347855,79 +338287,42 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9193 \muxid$67 + assign { } { } + assign { $1\spr1_ok$next[0:0]$8947 $1\spr1$6$next[63:0]$8946 } { \spr1_ok$32 \spr1$31 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9193 \muxid$67 + assign { } { } + assign { $1\spr1_ok$next[0:0]$8947 $1\spr1$6$next[63:0]$8946 } { \spr1_ok$32 \spr1$31 } + case + assign $1\spr1$6$next[63:0]$8946 \spr1$6 + assign $1\spr1_ok$next[0:0]$8947 \spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\spr1_ok$next[0:0]$8948 1'0 case - assign $1\muxid$next[1:0]$9193 \muxid + assign $2\spr1_ok$next[0:0]$8948 $1\spr1_ok$next[0:0]$8947 end sync always - update \muxid$next $0\muxid$next[1:0]$9192 + update \spr1$6$next $0\spr1$6$next[63:0]$8944 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8945 end - attribute \src "libresoc.v:169896.3-169936.6" - process $proc$libresoc.v:169896$9194 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:162797.3-162815.6" + process $proc$libresoc.v:162797$8949 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sr_op__fn_unit$next[12:0]$9195 $1\sr_op__fn_unit$next[12:0]$9212 - assign { } { } - assign { } { } - assign $0\sr_op__input_carry$next[1:0]$9198 $1\sr_op__input_carry$next[1:0]$9215 - assign $0\sr_op__input_cr$next[0:0]$9199 $1\sr_op__input_cr$next[0:0]$9216 - assign $0\sr_op__insn$next[31:0]$9200 $1\sr_op__insn$next[31:0]$9217 - assign $0\sr_op__insn_type$next[6:0]$9201 $1\sr_op__insn_type$next[6:0]$9218 - assign $0\sr_op__invert_in$next[0:0]$9202 $1\sr_op__invert_in$next[0:0]$9219 - assign $0\sr_op__is_32bit$next[0:0]$9203 $1\sr_op__is_32bit$next[0:0]$9220 - assign $0\sr_op__is_signed$next[0:0]$9204 $1\sr_op__is_signed$next[0:0]$9221 - assign { } { } - assign { } { } - assign $0\sr_op__output_carry$next[0:0]$9207 $1\sr_op__output_carry$next[0:0]$9224 - assign $0\sr_op__output_cr$next[0:0]$9208 $1\sr_op__output_cr$next[0:0]$9225 - assign { } { } - assign { } { } - assign $0\sr_op__write_cr0$next[0:0]$9211 $1\sr_op__write_cr0$next[0:0]$9228 - assign $0\sr_op__imm_data__data$next[63:0]$9196 $2\sr_op__imm_data__data$next[63:0]$9229 - assign $0\sr_op__imm_data__ok$next[0:0]$9197 $2\sr_op__imm_data__ok$next[0:0]$9230 - assign $0\sr_op__oe__oe$next[0:0]$9205 $2\sr_op__oe__oe$next[0:0]$9231 - assign $0\sr_op__oe__ok$next[0:0]$9206 $2\sr_op__oe__ok$next[0:0]$9232 - assign $0\sr_op__rc__ok$next[0:0]$9209 $2\sr_op__rc__ok$next[0:0]$9233 - assign $0\sr_op__rc__rc$next[0:0]$9210 $2\sr_op__rc__rc$next[0:0]$9234 - attribute \src "libresoc.v:169897.5-169897.29" + assign $0\fast1$7$next[63:0]$8951 $1\fast1$7$next[63:0]$8953 + assign $0\fast1_ok$next[0:0]$8950 $2\fast1_ok$next[0:0]$8954 + attribute \src "libresoc.v:162798.5-162798.29" switch \initial - attribute \src "libresoc.v:169897.9-169897.17" + attribute \src "libresoc.v:162798.9-162798.17" case 1'1 case end @@ -347937,116 +338332,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$next[31:0]$9217 $1\sr_op__is_signed$next[0:0]$9221 $1\sr_op__is_32bit$next[0:0]$9220 $1\sr_op__output_cr$next[0:0]$9225 $1\sr_op__input_cr$next[0:0]$9216 $1\sr_op__output_carry$next[0:0]$9224 $1\sr_op__input_carry$next[1:0]$9215 $1\sr_op__invert_in$next[0:0]$9219 $1\sr_op__write_cr0$next[0:0]$9228 $1\sr_op__oe__ok$next[0:0]$9223 $1\sr_op__oe__oe$next[0:0]$9222 $1\sr_op__rc__ok$next[0:0]$9226 $1\sr_op__rc__rc$next[0:0]$9227 $1\sr_op__imm_data__ok$next[0:0]$9214 $1\sr_op__imm_data__data$next[63:0]$9213 $1\sr_op__fn_unit$next[12:0]$9212 $1\sr_op__insn_type$next[6:0]$9218 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\fast1_ok$next[0:0]$8952 $1\fast1$7$next[63:0]$8953 } { \fast1_ok$34 \fast1$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$next[31:0]$9217 $1\sr_op__is_signed$next[0:0]$9221 $1\sr_op__is_32bit$next[0:0]$9220 $1\sr_op__output_cr$next[0:0]$9225 $1\sr_op__input_cr$next[0:0]$9216 $1\sr_op__output_carry$next[0:0]$9224 $1\sr_op__input_carry$next[1:0]$9215 $1\sr_op__invert_in$next[0:0]$9219 $1\sr_op__write_cr0$next[0:0]$9228 $1\sr_op__oe__ok$next[0:0]$9223 $1\sr_op__oe__oe$next[0:0]$9222 $1\sr_op__rc__ok$next[0:0]$9226 $1\sr_op__rc__rc$next[0:0]$9227 $1\sr_op__imm_data__ok$next[0:0]$9214 $1\sr_op__imm_data__data$next[63:0]$9213 $1\sr_op__fn_unit$next[12:0]$9212 $1\sr_op__insn_type$next[6:0]$9218 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\fast1_ok$next[0:0]$8952 $1\fast1$7$next[63:0]$8953 } { \fast1_ok$34 \fast1$33 } case - assign $1\sr_op__fn_unit$next[12:0]$9212 \sr_op__fn_unit - assign $1\sr_op__imm_data__data$next[63:0]$9213 \sr_op__imm_data__data - assign $1\sr_op__imm_data__ok$next[0:0]$9214 \sr_op__imm_data__ok - assign $1\sr_op__input_carry$next[1:0]$9215 \sr_op__input_carry - assign $1\sr_op__input_cr$next[0:0]$9216 \sr_op__input_cr - assign $1\sr_op__insn$next[31:0]$9217 \sr_op__insn - assign $1\sr_op__insn_type$next[6:0]$9218 \sr_op__insn_type - assign $1\sr_op__invert_in$next[0:0]$9219 \sr_op__invert_in - assign $1\sr_op__is_32bit$next[0:0]$9220 \sr_op__is_32bit - assign $1\sr_op__is_signed$next[0:0]$9221 \sr_op__is_signed - assign $1\sr_op__oe__oe$next[0:0]$9222 \sr_op__oe__oe - assign $1\sr_op__oe__ok$next[0:0]$9223 \sr_op__oe__ok - assign $1\sr_op__output_carry$next[0:0]$9224 \sr_op__output_carry - assign $1\sr_op__output_cr$next[0:0]$9225 \sr_op__output_cr - assign $1\sr_op__rc__ok$next[0:0]$9226 \sr_op__rc__ok - assign $1\sr_op__rc__rc$next[0:0]$9227 \sr_op__rc__rc - assign $1\sr_op__write_cr0$next[0:0]$9228 \sr_op__write_cr0 + assign $1\fast1_ok$next[0:0]$8952 \fast1_ok + assign $1\fast1$7$next[63:0]$8953 \fast1$7 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\sr_op__imm_data__data$next[63:0]$9229 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$next[0:0]$9230 1'0 - assign $2\sr_op__rc__rc$next[0:0]$9234 1'0 - assign $2\sr_op__rc__ok$next[0:0]$9233 1'0 - assign $2\sr_op__oe__oe$next[0:0]$9231 1'0 - assign $2\sr_op__oe__ok$next[0:0]$9232 1'0 + assign $2\fast1_ok$next[0:0]$8954 1'0 case - assign $2\sr_op__imm_data__data$next[63:0]$9229 $1\sr_op__imm_data__data$next[63:0]$9213 - assign $2\sr_op__imm_data__ok$next[0:0]$9230 $1\sr_op__imm_data__ok$next[0:0]$9214 - assign $2\sr_op__oe__oe$next[0:0]$9231 $1\sr_op__oe__oe$next[0:0]$9222 - assign $2\sr_op__oe__ok$next[0:0]$9232 $1\sr_op__oe__ok$next[0:0]$9223 - assign $2\sr_op__rc__ok$next[0:0]$9233 $1\sr_op__rc__ok$next[0:0]$9226 - assign $2\sr_op__rc__rc$next[0:0]$9234 $1\sr_op__rc__rc$next[0:0]$9227 + assign $2\fast1_ok$next[0:0]$8954 $1\fast1_ok$next[0:0]$8952 end sync always - update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[12:0]$9195 - update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9196 - update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9197 - update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9198 - update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9199 - update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9200 - update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9201 - update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9202 - update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9203 - update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9204 - update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9205 - update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9206 - update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9207 - update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9208 - update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9209 - update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9210 - update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9211 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8950 + update \fast1$7$next $0\fast1$7$next[63:0]$8951 end - attribute \src "libresoc.v:169937.3-169955.6" - process $proc$libresoc.v:169937$9235 + attribute \src "libresoc.v:162816.3-162834.6" + process $proc$libresoc.v:162816$8955 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9236 $1\o$next[63:0]$9238 assign { } { } - assign $0\o_ok$next[0:0]$9237 $2\o_ok$next[0:0]$9240 - attribute \src "libresoc.v:169938.5-169938.29" + assign $0\xer_so$8$next[0:0]$8957 $1\xer_so$8$next[0:0]$8959 + assign $0\xer_so_ok$next[0:0]$8956 $2\xer_so_ok$next[0:0]$8960 + attribute \src "libresoc.v:162817.5-162817.29" switch \initial - attribute \src "libresoc.v:169938.9-169938.17" + attribute \src "libresoc.v:162817.9-162817.17" case 1'1 case end @@ -348056,41 +338376,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9239 $1\o$next[63:0]$9238 } { \o_ok$86 \o$85 } + assign { $1\xer_so_ok$next[0:0]$8958 $1\xer_so$8$next[0:0]$8959 } { \xer_so_ok$36 \xer_so$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9239 $1\o$next[63:0]$9238 } { \o_ok$86 \o$85 } + assign { $1\xer_so_ok$next[0:0]$8958 $1\xer_so$8$next[0:0]$8959 } { \xer_so_ok$36 \xer_so$35 } case - assign $1\o$next[63:0]$9238 \o - assign $1\o_ok$next[0:0]$9239 \o_ok + assign $1\xer_so_ok$next[0:0]$8958 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8959 \xer_so$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9240 1'0 + assign $2\xer_so_ok$next[0:0]$8960 1'0 case - assign $2\o_ok$next[0:0]$9240 $1\o_ok$next[0:0]$9239 + assign $2\xer_so_ok$next[0:0]$8960 $1\xer_so_ok$next[0:0]$8958 end sync always - update \o$next $0\o$next[63:0]$9236 - update \o_ok$next $0\o_ok$next[0:0]$9237 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8956 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8957 end - attribute \src "libresoc.v:169956.3-169974.6" - process $proc$libresoc.v:169956$9241 + attribute \src "libresoc.v:162835.3-162853.6" + process $proc$libresoc.v:162835$8961 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9242 $1\cr_a$next[3:0]$9244 assign { } { } - assign $0\cr_a_ok$next[0:0]$9243 $2\cr_a_ok$next[0:0]$9246 - attribute \src "libresoc.v:169957.5-169957.29" + assign $0\xer_ov$9$next[1:0]$8963 $1\xer_ov$9$next[1:0]$8965 + assign $0\xer_ov_ok$next[0:0]$8962 $2\xer_ov_ok$next[0:0]$8966 + attribute \src "libresoc.v:162836.5-162836.29" switch \initial - attribute \src "libresoc.v:169957.9-169957.17" + attribute \src "libresoc.v:162836.9-162836.17" case 1'1 case end @@ -348100,41 +338420,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9245 $1\cr_a$next[3:0]$9244 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\xer_ov_ok$next[0:0]$8964 $1\xer_ov$9$next[1:0]$8965 } { \xer_ov_ok$38 \xer_ov$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9245 $1\cr_a$next[3:0]$9244 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\xer_ov_ok$next[0:0]$8964 $1\xer_ov$9$next[1:0]$8965 } { \xer_ov_ok$38 \xer_ov$37 } case - assign $1\cr_a$next[3:0]$9244 \cr_a - assign $1\cr_a_ok$next[0:0]$9245 \cr_a_ok + assign $1\xer_ov_ok$next[0:0]$8964 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8965 \xer_ov$9 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9246 1'0 + assign $2\xer_ov_ok$next[0:0]$8966 1'0 case - assign $2\cr_a_ok$next[0:0]$9246 $1\cr_a_ok$next[0:0]$9245 + assign $2\xer_ov_ok$next[0:0]$8966 $1\xer_ov_ok$next[0:0]$8964 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9242 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9243 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8962 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8963 end - attribute \src "libresoc.v:169975.3-169993.6" - process $proc$libresoc.v:169975$9247 + attribute \src "libresoc.v:162854.3-162872.6" + process $proc$libresoc.v:162854$8967 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9248 $1\xer_so$next[0:0]$9250 + assign $0\xer_ca$10$next[1:0]$8968 $1\xer_ca$10$next[1:0]$8970 assign { } { } - assign $0\xer_so_ok$next[0:0]$9249 $2\xer_so_ok$next[0:0]$9252 - attribute \src "libresoc.v:169976.5-169976.29" + assign $0\xer_ca_ok$next[0:0]$8969 $2\xer_ca_ok$next[0:0]$8972 + attribute \src "libresoc.v:162855.5-162855.29" switch \initial - attribute \src "libresoc.v:169976.9-169976.17" + attribute \src "libresoc.v:162855.9-162855.17" case 1'1 case end @@ -348144,221 +338464,769 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9251 $1\xer_so$next[0:0]$9250 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_ca_ok$next[0:0]$8971 $1\xer_ca$10$next[1:0]$8970 } { \xer_ca_ok$40 \xer_ca$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9251 $1\xer_so$next[0:0]$9250 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_ca_ok$next[0:0]$8971 $1\xer_ca$10$next[1:0]$8970 } { \xer_ca_ok$40 \xer_ca$39 } case - assign $1\xer_so$next[0:0]$9250 \xer_so - assign $1\xer_so_ok$next[0:0]$9251 \xer_so_ok + assign $1\xer_ca$10$next[1:0]$8970 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8971 \xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9252 1'0 + assign $2\xer_ca_ok$next[0:0]$8972 1'0 case - assign $2\xer_so_ok$next[0:0]$9252 $1\xer_so_ok$next[0:0]$9251 + assign $2\xer_ca_ok$next[0:0]$8972 $1\xer_ca_ok$next[0:0]$8971 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9248 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9249 + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8968 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8969 end - connect \$65 $and$libresoc.v:169689$9153_Y - connect \cr_a$89 4'0000 - connect \cr_a_ok$90 1'0 - connect \xer_so_ok$93 1'0 - connect \xer_ca_ok$96 1'0 + connect \$22 $and$libresoc.v:162637$8892_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_ca_ok$95 \xer_ca$94 } { 1'0 \main_xer_ca } - connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } - connect { \cr_a_ok$88 \cr_a$87 } 5'00000 - connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } - connect { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } { \main_sr_op__insn$61 \main_sr_op__is_signed$60 \main_sr_op__is_32bit$59 \main_sr_op__output_cr$58 \main_sr_op__input_cr$57 \main_sr_op__output_carry$56 \main_sr_op__input_carry$55 \main_sr_op__invert_in$54 \main_sr_op__write_cr0$53 \main_sr_op__oe__ok$52 \main_sr_op__oe__oe$51 \main_sr_op__rc__ok$50 \main_sr_op__rc__rc$49 \main_sr_op__imm_data__ok$48 \main_sr_op__imm_data__data$47 \main_sr_op__fn_unit$46 \main_sr_op__insn_type$45 } - connect \muxid$67 \main_muxid$44 - connect \p_valid_i_p_ready_o \$65 + connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } + connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } + connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } + connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } + connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } + connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } + connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } + connect \muxid$24 \spr_main_muxid$11 + connect \p_valid_i_p_ready_o \$22 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$64 \p_valid_i - connect \xer_ca$63 \input_xer_ca$43 - connect \main_xer_so \input_xer_so$42 - connect \main_rc \input_rc$41 - connect \main_rb \input_rb$40 - connect \main_ra \input_ra$39 - connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__invert_in \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$38 \input_sr_op__is_signed$37 \input_sr_op__is_32bit$36 \input_sr_op__output_cr$35 \input_sr_op__input_cr$34 \input_sr_op__output_carry$33 \input_sr_op__input_carry$32 \input_sr_op__invert_in$31 \input_sr_op__write_cr0$30 \input_sr_op__oe__ok$29 \input_sr_op__oe__oe$28 \input_sr_op__rc__ok$27 \input_sr_op__rc__rc$26 \input_sr_op__imm_data__ok$25 \input_sr_op__imm_data__data$24 \input_sr_op__fn_unit$23 \input_sr_op__insn_type$22 } - connect \main_muxid \input_muxid$21 - connect \input_xer_ca \xer_ca$20 - connect \input_xer_so \xer_so$19 - connect \input_rc \rc - connect \input_rb \rb - connect \input_ra \ra - connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } - connect \input_muxid \muxid$1 + connect \p_valid_i$21 \p_valid_i + connect \spr_main_xer_ca \xer_ca + connect \spr_main_xer_ov \xer_ov + connect \spr_main_xer_so \xer_so + connect \spr_main_fast1 \fast1 + connect \spr_main_spr1 \spr1 + connect \spr_main_ra \ra + connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \spr_main_muxid \muxid end -attribute \src "libresoc.v:170027.1-170865.10" +attribute \src "libresoc.v:162898.1-164376.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" -module \pipe1$32 - attribute \src "libresoc.v:170822.3-170834.6" - wire width 64 $0\fast1$next[63:0]$9330 - attribute \src "libresoc.v:170678.3-170679.27" - wire width 64 $0\fast1[63:0] - attribute \src "libresoc.v:170835.3-170847.6" - wire width 64 $0\fast2$next[63:0]$9333 - attribute \src "libresoc.v:170676.3-170677.27" - wire width 64 $0\fast2[63:0] - attribute \src "libresoc.v:170028.7-170028.20" +module \pipe1 + attribute \src "libresoc.v:164290.3-164331.6" + wire width 4 $0\alu_op__data_len$next[3:0]$9065 + attribute \src "libresoc.v:164066.3-164067.49" + wire width 4 $0\alu_op__data_len[3:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 13 $0\alu_op__fn_unit$next[12:0]$9066 + attribute \src "libresoc.v:164036.3-164037.47" + wire width 13 $0\alu_op__fn_unit[12:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$9067 + attribute \src "libresoc.v:164038.3-164039.61" + wire width 64 $0\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__imm_data__ok$next[0:0]$9068 + attribute \src "libresoc.v:164040.3-164041.57" + wire $0\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$9069 + attribute \src "libresoc.v:164058.3-164059.55" + wire width 2 $0\alu_op__input_carry[1:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 32 $0\alu_op__insn$next[31:0]$9070 + attribute \src "libresoc.v:164068.3-164069.41" + wire width 32 $0\alu_op__insn[31:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$9071 + attribute \src "libresoc.v:164034.3-164035.51" + wire width 7 $0\alu_op__insn_type[6:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__invert_in$next[0:0]$9072 + attribute \src "libresoc.v:164050.3-164051.51" + wire $0\alu_op__invert_in[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__invert_out$next[0:0]$9073 + attribute \src "libresoc.v:164054.3-164055.53" + wire $0\alu_op__invert_out[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__is_32bit$next[0:0]$9074 + attribute \src "libresoc.v:164062.3-164063.49" + wire $0\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__is_signed$next[0:0]$9075 + attribute \src "libresoc.v:164064.3-164065.51" + wire $0\alu_op__is_signed[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__oe__oe$next[0:0]$9076 + attribute \src "libresoc.v:164046.3-164047.45" + wire $0\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__oe__ok$next[0:0]$9077 + attribute \src "libresoc.v:164048.3-164049.45" + wire $0\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__output_carry$next[0:0]$9078 + attribute \src "libresoc.v:164060.3-164061.57" + wire $0\alu_op__output_carry[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__rc__ok$next[0:0]$9079 + attribute \src "libresoc.v:164044.3-164045.45" + wire $0\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__rc__rc$next[0:0]$9080 + attribute \src "libresoc.v:164042.3-164043.45" + wire $0\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__write_cr0$next[0:0]$9081 + attribute \src "libresoc.v:164056.3-164057.51" + wire $0\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $0\alu_op__zero_a$next[0:0]$9082 + attribute \src "libresoc.v:164052.3-164053.45" + wire $0\alu_op__zero_a[0:0] + attribute \src "libresoc.v:164183.3-164201.6" + wire width 4 $0\cr_a$next[3:0]$9034 + attribute \src "libresoc.v:164026.3-164027.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:164183.3-164201.6" + wire $0\cr_a_ok$next[0:0]$9035 + attribute \src "libresoc.v:164028.3-164029.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:162899.7-162899.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170762.3-170774.6" - wire width 2 $0\muxid$next[1:0]$9302 - attribute \src "libresoc.v:170702.3-170703.27" + attribute \src "libresoc.v:164277.3-164289.6" + wire width 2 $0\muxid$next[1:0]$9062 + attribute \src "libresoc.v:164070.3-164071.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:170744.3-170761.6" - wire $0\r_busy$next[0:0]$9298 - attribute \src "libresoc.v:170704.3-170705.29" + attribute \src "libresoc.v:164332.3-164350.6" + wire width 64 $0\o$next[63:0]$9108 + attribute \src "libresoc.v:164030.3-164031.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:164332.3-164350.6" + wire $0\o_ok$next[0:0]$9109 + attribute \src "libresoc.v:164032.3-164033.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:164259.3-164276.6" + wire $0\r_busy$next[0:0]$9058 + attribute \src "libresoc.v:164072.3-164073.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:170796.3-170808.6" - wire width 64 $0\ra$next[63:0]$9324 - attribute \src "libresoc.v:170682.3-170683.21" - wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:170809.3-170821.6" - wire width 64 $0\rb$next[63:0]$9327 - attribute \src "libresoc.v:170680.3-170681.21" - wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 64 $0\trap_op__cia$next[63:0]$9305 - attribute \src "libresoc.v:170692.3-170693.41" - wire width 64 $0\trap_op__cia[63:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 13 $0\trap_op__fn_unit$next[12:0]$9306 - attribute \src "libresoc.v:170686.3-170687.49" - wire width 13 $0\trap_op__fn_unit[12:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 32 $0\trap_op__insn$next[31:0]$9307 - attribute \src "libresoc.v:170688.3-170689.43" - wire width 32 $0\trap_op__insn[31:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 7 $0\trap_op__insn_type$next[6:0]$9308 - attribute \src "libresoc.v:170684.3-170685.53" - wire width 7 $0\trap_op__insn_type[6:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire $0\trap_op__is_32bit$next[0:0]$9309 - attribute \src "libresoc.v:170694.3-170695.51" - wire $0\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 8 $0\trap_op__ldst_exc$next[7:0]$9310 - attribute \src "libresoc.v:170700.3-170701.51" - wire width 8 $0\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 64 $0\trap_op__msr$next[63:0]$9311 - attribute \src "libresoc.v:170690.3-170691.41" - wire width 64 $0\trap_op__msr[63:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 13 $0\trap_op__trapaddr$next[12:0]$9312 - attribute \src "libresoc.v:170698.3-170699.51" - wire width 13 $0\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 8 $0\trap_op__traptype$next[7:0]$9313 - attribute \src "libresoc.v:170696.3-170697.51" - wire width 8 $0\trap_op__traptype[7:0] - attribute \src "libresoc.v:170822.3-170834.6" - wire width 64 $1\fast1$next[63:0]$9331 - attribute \src "libresoc.v:170269.14-170269.42" - wire width 64 $1\fast1[63:0] - attribute \src "libresoc.v:170835.3-170847.6" - wire width 64 $1\fast2$next[63:0]$9334 - attribute \src "libresoc.v:170278.14-170278.42" - wire width 64 $1\fast2[63:0] - attribute \src "libresoc.v:170762.3-170774.6" - wire width 2 $1\muxid$next[1:0]$9303 - attribute \src "libresoc.v:170287.13-170287.25" + attribute \src "libresoc.v:164202.3-164220.6" + wire width 2 $0\xer_ca$next[1:0]$9041 + attribute \src "libresoc.v:164022.3-164023.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:164202.3-164220.6" + wire $0\xer_ca_ok$next[0:0]$9040 + attribute \src "libresoc.v:164024.3-164025.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:164221.3-164239.6" + wire width 2 $0\xer_ov$next[1:0]$9046 + attribute \src "libresoc.v:164018.3-164019.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:164221.3-164239.6" + wire $0\xer_ov_ok$next[0:0]$9047 + attribute \src "libresoc.v:164020.3-164021.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:164240.3-164258.6" + wire $0\xer_so$next[0:0]$9052 + attribute \src "libresoc.v:164014.3-164015.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:164240.3-164258.6" + wire $0\xer_so_ok$next[0:0]$9053 + attribute \src "libresoc.v:164016.3-164017.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 4 $1\alu_op__data_len$next[3:0]$9083 + attribute \src "libresoc.v:162904.13-162904.36" + wire width 4 $1\alu_op__data_len[3:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 13 $1\alu_op__fn_unit$next[12:0]$9084 + attribute \src "libresoc.v:162927.14-162927.40" + wire width 13 $1\alu_op__fn_unit[12:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$9085 + attribute \src "libresoc.v:162964.14-162964.59" + wire width 64 $1\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__imm_data__ok$next[0:0]$9086 + attribute \src "libresoc.v:162973.7-162973.34" + wire $1\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$9087 + attribute \src "libresoc.v:162986.13-162986.39" + wire width 2 $1\alu_op__input_carry[1:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 32 $1\alu_op__insn$next[31:0]$9088 + attribute \src "libresoc.v:163003.14-163003.34" + wire width 32 $1\alu_op__insn[31:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$9089 + attribute \src "libresoc.v:163086.13-163086.38" + wire width 7 $1\alu_op__insn_type[6:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__invert_in$next[0:0]$9090 + attribute \src "libresoc.v:163243.7-163243.31" + wire $1\alu_op__invert_in[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__invert_out$next[0:0]$9091 + attribute \src "libresoc.v:163252.7-163252.32" + wire $1\alu_op__invert_out[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__is_32bit$next[0:0]$9092 + attribute \src "libresoc.v:163261.7-163261.30" + wire $1\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__is_signed$next[0:0]$9093 + attribute \src "libresoc.v:163270.7-163270.31" + wire $1\alu_op__is_signed[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__oe__oe$next[0:0]$9094 + attribute \src "libresoc.v:163279.7-163279.28" + wire $1\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__oe__ok$next[0:0]$9095 + attribute \src "libresoc.v:163288.7-163288.28" + wire $1\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__output_carry$next[0:0]$9096 + attribute \src "libresoc.v:163297.7-163297.34" + wire $1\alu_op__output_carry[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__rc__ok$next[0:0]$9097 + attribute \src "libresoc.v:163306.7-163306.28" + wire $1\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__rc__rc$next[0:0]$9098 + attribute \src "libresoc.v:163315.7-163315.28" + wire $1\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__write_cr0$next[0:0]$9099 + attribute \src "libresoc.v:163324.7-163324.31" + wire $1\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:164290.3-164331.6" + wire $1\alu_op__zero_a$next[0:0]$9100 + attribute \src "libresoc.v:163333.7-163333.28" + wire $1\alu_op__zero_a[0:0] + attribute \src "libresoc.v:164183.3-164201.6" + wire width 4 $1\cr_a$next[3:0]$9036 + attribute \src "libresoc.v:163346.13-163346.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:164183.3-164201.6" + wire $1\cr_a_ok$next[0:0]$9037 + attribute \src "libresoc.v:163353.7-163353.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:164277.3-164289.6" + wire width 2 $1\muxid$next[1:0]$9063 + attribute \src "libresoc.v:163922.13-163922.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:170744.3-170761.6" - wire $1\r_busy$next[0:0]$9299 - attribute \src "libresoc.v:170309.7-170309.20" + attribute \src "libresoc.v:164332.3-164350.6" + wire width 64 $1\o$next[63:0]$9110 + attribute \src "libresoc.v:163937.14-163937.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:164332.3-164350.6" + wire $1\o_ok$next[0:0]$9111 + attribute \src "libresoc.v:163944.7-163944.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:164259.3-164276.6" + wire $1\r_busy$next[0:0]$9059 + attribute \src "libresoc.v:163958.7-163958.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:170796.3-170808.6" - wire width 64 $1\ra$next[63:0]$9325 - attribute \src "libresoc.v:170314.14-170314.39" - wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:170809.3-170821.6" - wire width 64 $1\rb$next[63:0]$9328 - attribute \src "libresoc.v:170323.14-170323.39" - wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 64 $1\trap_op__cia$next[63:0]$9314 - attribute \src "libresoc.v:170332.14-170332.49" - wire width 64 $1\trap_op__cia[63:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 13 $1\trap_op__fn_unit$next[12:0]$9315 - attribute \src "libresoc.v:170355.14-170355.41" - wire width 13 $1\trap_op__fn_unit[12:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 32 $1\trap_op__insn$next[31:0]$9316 - attribute \src "libresoc.v:170392.14-170392.35" - wire width 32 $1\trap_op__insn[31:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 7 $1\trap_op__insn_type$next[6:0]$9317 - attribute \src "libresoc.v:170475.13-170475.39" - wire width 7 $1\trap_op__insn_type[6:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire $1\trap_op__is_32bit$next[0:0]$9318 - attribute \src "libresoc.v:170632.7-170632.31" - wire $1\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 8 $1\trap_op__ldst_exc$next[7:0]$9319 - attribute \src "libresoc.v:170641.13-170641.38" - wire width 8 $1\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 64 $1\trap_op__msr$next[63:0]$9320 - attribute \src "libresoc.v:170650.14-170650.49" - wire width 64 $1\trap_op__msr[63:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 13 $1\trap_op__trapaddr$next[12:0]$9321 - attribute \src "libresoc.v:170659.14-170659.42" - wire width 13 $1\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:170775.3-170795.6" - wire width 8 $1\trap_op__traptype$next[7:0]$9322 - attribute \src "libresoc.v:170668.13-170668.38" - wire width 8 $1\trap_op__traptype[7:0] - attribute \src "libresoc.v:170744.3-170761.6" - wire $2\r_busy$next[0:0]$9300 - attribute \src "libresoc.v:170675.18-170675.118" - wire $and$libresoc.v:170675$9281_Y + attribute \src "libresoc.v:164202.3-164220.6" + wire width 2 $1\xer_ca$next[1:0]$9043 + attribute \src "libresoc.v:163967.13-163967.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:164202.3-164220.6" + wire $1\xer_ca_ok$next[0:0]$9042 + attribute \src "libresoc.v:163976.7-163976.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:164221.3-164239.6" + wire width 2 $1\xer_ov$next[1:0]$9048 + attribute \src "libresoc.v:163983.13-163983.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:164221.3-164239.6" + wire $1\xer_ov_ok$next[0:0]$9049 + attribute \src "libresoc.v:163990.7-163990.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:164240.3-164258.6" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 6 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 37 \alu_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_op__fn_unit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 48 \alu_op__input_carry$14 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 36 \alu_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast1$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast2$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \dummy_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \dummy_muxid$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_ra$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_rb$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:162899.7-162899.15" + wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dummy_trap_op__cia + wire width 4 \input_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dummy_trap_op__cia$20 + wire width 4 \input_alu_op__data_len$39 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -348374,7 +339242,7 @@ module \pipe1$32 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dummy_trap_op__fn_unit + wire width 13 \input_alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -348390,11 +339258,31 @@ module \pipe1$32 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dummy_trap_op__fn_unit$17 + wire width 13 \input_alu_op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dummy_trap_op__insn + wire width 64 \input_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dummy_trap_op__insn$18 + wire width 64 \input_alu_op__imm_data__data$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn$40 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -348470,7 +339358,7 @@ module \pipe1$32 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dummy_trap_op__insn_type + wire width 7 \input_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -348546,95 +339434,75 @@ module \pipe1$32 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dummy_trap_op__insn_type$16 + wire width 7 \input_alu_op__insn_type$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dummy_trap_op__is_32bit + wire \input_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dummy_trap_op__is_32bit$21 + wire \input_alu_op__invert_in$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \dummy_trap_op__ldst_exc + wire \input_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \dummy_trap_op__ldst_exc$24 + wire \input_alu_op__invert_out$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dummy_trap_op__msr + wire \input_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dummy_trap_op__msr$19 + wire \input_alu_op__is_32bit$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dummy_trap_op__trapaddr + wire \input_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \dummy_trap_op__trapaddr$23 + wire \input_alu_op__is_signed$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \dummy_trap_op__traptype + wire \input_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \dummy_trap_op__traptype$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 16 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 32 \fast1$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \fast1$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \fast1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 17 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 33 \fast2$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \fast2$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \fast2$next - attribute \src "libresoc.v:170028.7-170028.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 20 \muxid$1 + wire \input_alu_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$32 + wire width 2 \input_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 19 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 18 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next + wire width 2 \input_muxid$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 14 \ra + wire width 64 \input_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 30 \ra$11 + wire width 64 \input_ra$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$42 + wire width 64 \input_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next + wire width 64 \input_rb$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 15 \rb + wire width 2 \input_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 31 \rb$12 + wire width 2 \input_xer_ca$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$43 + wire \input_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 9 \trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$37 + wire \input_xer_so$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 25 \trap_op__cia$6 + wire width 4 \main_alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$next + wire width 4 \main_alu_op__data_len$62 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -348650,7 +339518,7 @@ module \pipe1$32 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \trap_op__fn_unit + wire width 13 \main_alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -348666,109 +339534,31 @@ module \pipe1$32 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 22 \trap_op__fn_unit$3 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" + wire width 13 \main_alu_op__fn_unit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__fn_unit$34 + wire width 64 \main_alu_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__fn_unit$next + wire width 64 \main_alu_op__imm_data__data$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 7 \trap_op__insn + wire \main_alu_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$35 + wire \main_alu_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 23 \trap_op__insn$4 + wire width 2 \main_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 2 \main_alu_op__input_carry$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \trap_op__insn_type + wire width 32 \main_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn$63 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -348844,7 +339634,7 @@ module \pipe1$32 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 21 \trap_op__insn_type$2 + wire width 7 \main_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -348920,346 +339710,936 @@ module \pipe1$32 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$33 + wire width 7 \main_alu_op__insn_type$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$next + wire \main_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \trap_op__is_32bit + wire \main_alu_op__invert_in$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$38 + wire \main_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 26 \trap_op__is_32bit$7 + wire \main_alu_op__invert_out$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$next + wire \main_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 13 \trap_op__ldst_exc + wire \main_alu_op__is_32bit$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 29 \trap_op__ldst_exc$10 + wire \main_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$41 + wire \main_alu_op__is_signed$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$next + wire \main_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 8 \trap_op__msr + wire \main_alu_op__oe__oe$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$36 + wire \main_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 24 \trap_op__msr$5 + wire \main_alu_op__oe__ok$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$next + wire \main_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 12 \trap_op__trapaddr + wire \main_alu_op__output_carry$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$40 + wire \main_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 28 \trap_op__trapaddr$9 + wire \main_alu_op__rc__ok$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$next + wire \main_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 11 \trap_op__traptype + wire \main_alu_op__rc__rc$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$39 + wire \main_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 27 \trap_op__traptype$8 + wire \main_alu_op__write_cr0$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$next + wire \main_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ca$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 54 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 57 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 56 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:170675$9281 + cell $and $and$libresoc.v:164013$9002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$29 + connect \A \p_valid_i$66 connect \B \p_ready_o - connect \Y $and$libresoc.v:170675$9281_Y + connect \Y $and$libresoc.v:164013$9002_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:170706.9-170735.4" - cell \dummy \dummy - connect \fast1 \dummy_fast1 - connect \fast1$13 \dummy_fast1$27 - connect \fast2 \dummy_fast2 - connect \fast2$14 \dummy_fast2$28 - connect \muxid \dummy_muxid - connect \muxid$1 \dummy_muxid$15 - connect \ra \dummy_ra - connect \ra$11 \dummy_ra$25 - connect \rb \dummy_rb - connect \rb$12 \dummy_rb$26 - connect \trap_op__cia \dummy_trap_op__cia - connect \trap_op__cia$6 \dummy_trap_op__cia$20 - connect \trap_op__fn_unit \dummy_trap_op__fn_unit - connect \trap_op__fn_unit$3 \dummy_trap_op__fn_unit$17 - connect \trap_op__insn \dummy_trap_op__insn - connect \trap_op__insn$4 \dummy_trap_op__insn$18 - connect \trap_op__insn_type \dummy_trap_op__insn_type - connect \trap_op__insn_type$2 \dummy_trap_op__insn_type$16 - connect \trap_op__is_32bit \dummy_trap_op__is_32bit - connect \trap_op__is_32bit$7 \dummy_trap_op__is_32bit$21 - connect \trap_op__ldst_exc \dummy_trap_op__ldst_exc - connect \trap_op__ldst_exc$10 \dummy_trap_op__ldst_exc$24 - connect \trap_op__msr \dummy_trap_op__msr - connect \trap_op__msr$5 \dummy_trap_op__msr$19 - connect \trap_op__trapaddr \dummy_trap_op__trapaddr - connect \trap_op__trapaddr$9 \dummy_trap_op__trapaddr$23 - connect \trap_op__traptype \dummy_trap_op__traptype - connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 + attribute \src "libresoc.v:164074.11-164121.4" + cell \input \input + connect \alu_op__data_len \input_alu_op__data_len + connect \alu_op__data_len$18 \input_alu_op__data_len$39 + connect \alu_op__fn_unit \input_alu_op__fn_unit + connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 + connect \alu_op__imm_data__data \input_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 + connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 + connect \alu_op__input_carry \input_alu_op__input_carry + connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 + connect \alu_op__insn \input_alu_op__insn + connect \alu_op__insn$19 \input_alu_op__insn$40 + connect \alu_op__insn_type \input_alu_op__insn_type + connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 + connect \alu_op__invert_in \input_alu_op__invert_in + connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 + connect \alu_op__invert_out \input_alu_op__invert_out + connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 + connect \alu_op__is_32bit \input_alu_op__is_32bit + connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 + connect \alu_op__is_signed \input_alu_op__is_signed + connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 + connect \alu_op__oe__oe \input_alu_op__oe__oe + connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 + connect \alu_op__oe__ok \input_alu_op__oe__ok + connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 + connect \alu_op__output_carry \input_alu_op__output_carry + connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 + connect \alu_op__rc__ok \input_alu_op__rc__ok + connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 + connect \alu_op__rc__rc \input_alu_op__rc__rc + connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 + connect \alu_op__write_cr0 \input_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 + connect \alu_op__zero_a \input_alu_op__zero_a + connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$22 + connect \ra \input_ra + connect \ra$20 \input_ra$41 + connect \rb \input_rb + connect \rb$21 \input_rb$42 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$44 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$43 end attribute \module_not_derived 1 - attribute \src "libresoc.v:170736.10-170739.4" - cell \n$34 \n + attribute \src "libresoc.v:164122.8-164174.4" + cell \main \main + connect \alu_op__data_len \main_alu_op__data_len + connect \alu_op__data_len$18 \main_alu_op__data_len$62 + connect \alu_op__fn_unit \main_alu_op__fn_unit + connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 + connect \alu_op__imm_data__data \main_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 + connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 + connect \alu_op__input_carry \main_alu_op__input_carry + connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 + connect \alu_op__insn \main_alu_op__insn + connect \alu_op__insn$19 \main_alu_op__insn$63 + connect \alu_op__insn_type \main_alu_op__insn_type + connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 + connect \alu_op__invert_in \main_alu_op__invert_in + connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 + connect \alu_op__invert_out \main_alu_op__invert_out + connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 + connect \alu_op__is_32bit \main_alu_op__is_32bit + connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 + connect \alu_op__is_signed \main_alu_op__is_signed + connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 + connect \alu_op__oe__oe \main_alu_op__oe__oe + connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 + connect \alu_op__oe__ok \main_alu_op__oe__ok + connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 + connect \alu_op__output_carry \main_alu_op__output_carry + connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 + connect \alu_op__rc__ok \main_alu_op__rc__ok + connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 + connect \alu_op__rc__rc \main_alu_op__rc__rc + connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 + connect \alu_op__write_cr0 \main_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 + connect \alu_op__zero_a \main_alu_op__zero_a + connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + connect \cr_a \main_cr_a + connect \cr_a_ok \main_cr_a_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$45 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_ca \main_xer_ca + connect \xer_ca$20 \main_xer_ca$64 + connect \xer_ca_ok \main_xer_ca_ok + connect \xer_ov \main_xer_ov + connect \xer_ov_ok \main_xer_ov_ok + connect \xer_so \main_xer_so + connect \xer_so$21 \main_xer_so$65 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164175.9-164178.4" + cell \n$2 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:170740.10-170743.4" - cell \p$33 \p + attribute \src "libresoc.v:164179.9-164182.4" + cell \p$1 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:170028.7-170028.20" - process $proc$libresoc.v:170028$9335 + attribute \src "libresoc.v:162899.7-162899.20" + process $proc$libresoc.v:162899$9113 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170269.14-170269.42" - process $proc$libresoc.v:170269$9336 + attribute \src "libresoc.v:162904.13-162904.36" + process $proc$libresoc.v:162904$9114 assign { } { } - assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__data_len[3:0] 4'0000 sync always sync init - update \fast1 $1\fast1[63:0] + update \alu_op__data_len $1\alu_op__data_len[3:0] end - attribute \src "libresoc.v:170278.14-170278.42" - process $proc$libresoc.v:170278$9337 + attribute \src "libresoc.v:162927.14-162927.40" + process $proc$libresoc.v:162927$9115 assign { } { } - assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__fn_unit[12:0] 13'0000000000000 sync always sync init - update \fast2 $1\fast2[63:0] + update \alu_op__fn_unit $1\alu_op__fn_unit[12:0] end - attribute \src "libresoc.v:170287.13-170287.25" - process $proc$libresoc.v:170287$9338 + attribute \src "libresoc.v:162964.14-162964.59" + process $proc$libresoc.v:162964$9116 assign { } { } - assign $1\muxid[1:0] 2'00 + assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \muxid $1\muxid[1:0] + update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:170309.7-170309.20" - process $proc$libresoc.v:170309$9339 + attribute \src "libresoc.v:162973.7-162973.34" + process $proc$libresoc.v:162973$9117 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $1\alu_op__imm_data__ok[0:0] 1'0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:170314.14-170314.39" - process $proc$libresoc.v:170314$9340 + attribute \src "libresoc.v:162986.13-162986.39" + process $proc$libresoc.v:162986$9118 assign { } { } - assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__input_carry[1:0] 2'00 sync always sync init - update \ra $1\ra[63:0] + update \alu_op__input_carry $1\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:170323.14-170323.39" - process $proc$libresoc.v:170323$9341 + attribute \src "libresoc.v:163003.14-163003.34" + process $proc$libresoc.v:163003$9119 assign { } { } - assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__insn[31:0] 0 sync always sync init - update \rb $1\rb[63:0] + update \alu_op__insn $1\alu_op__insn[31:0] end - attribute \src "libresoc.v:170332.14-170332.49" - process $proc$libresoc.v:170332$9342 + attribute \src "libresoc.v:163086.13-163086.38" + process $proc$libresoc.v:163086$9120 assign { } { } - assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__insn_type[6:0] 7'0000000 sync always sync init - update \trap_op__cia $1\trap_op__cia[63:0] + update \alu_op__insn_type $1\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:170355.14-170355.41" - process $proc$libresoc.v:170355$9343 + attribute \src "libresoc.v:163243.7-163243.31" + process $proc$libresoc.v:163243$9121 assign { } { } - assign $1\trap_op__fn_unit[12:0] 13'0000000000000 + assign $1\alu_op__invert_in[0:0] 1'0 sync always sync init - update \trap_op__fn_unit $1\trap_op__fn_unit[12:0] + update \alu_op__invert_in $1\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:170392.14-170392.35" - process $proc$libresoc.v:170392$9344 + attribute \src "libresoc.v:163252.7-163252.32" + process $proc$libresoc.v:163252$9122 assign { } { } - assign $1\trap_op__insn[31:0] 0 + assign $1\alu_op__invert_out[0:0] 1'0 sync always sync init - update \trap_op__insn $1\trap_op__insn[31:0] + update \alu_op__invert_out $1\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:170475.13-170475.39" - process $proc$libresoc.v:170475$9345 + attribute \src "libresoc.v:163261.7-163261.30" + process $proc$libresoc.v:163261$9123 assign { } { } - assign $1\trap_op__insn_type[6:0] 7'0000000 + assign $1\alu_op__is_32bit[0:0] 1'0 sync always sync init - update \trap_op__insn_type $1\trap_op__insn_type[6:0] + update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:170632.7-170632.31" - process $proc$libresoc.v:170632$9346 + attribute \src "libresoc.v:163270.7-163270.31" + process $proc$libresoc.v:163270$9124 assign { } { } - assign $1\trap_op__is_32bit[0:0] 1'0 + assign $1\alu_op__is_signed[0:0] 1'0 sync always sync init - update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] + update \alu_op__is_signed $1\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:170641.13-170641.38" - process $proc$libresoc.v:170641$9347 + attribute \src "libresoc.v:163279.7-163279.28" + process $proc$libresoc.v:163279$9125 assign { } { } - assign $1\trap_op__ldst_exc[7:0] 8'00000000 + assign $1\alu_op__oe__oe[0:0] 1'0 sync always sync init - update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] + update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:170650.14-170650.49" - process $proc$libresoc.v:170650$9348 + attribute \src "libresoc.v:163288.7-163288.28" + process $proc$libresoc.v:163288$9126 assign { } { } - assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\alu_op__oe__ok[0:0] 1'0 sync always sync init - update \trap_op__msr $1\trap_op__msr[63:0] + update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:170659.14-170659.42" - process $proc$libresoc.v:170659$9349 + attribute \src "libresoc.v:163297.7-163297.34" + process $proc$libresoc.v:163297$9127 assign { } { } - assign $1\trap_op__trapaddr[12:0] 13'0000000000000 + assign $1\alu_op__output_carry[0:0] 1'0 sync always sync init - update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] + update \alu_op__output_carry $1\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:170668.13-170668.38" - process $proc$libresoc.v:170668$9350 + attribute \src "libresoc.v:163306.7-163306.28" + process $proc$libresoc.v:163306$9128 assign { } { } - assign $1\trap_op__traptype[7:0] 8'00000000 + assign $1\alu_op__rc__ok[0:0] 1'0 sync always sync init - update \trap_op__traptype $1\trap_op__traptype[7:0] + update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:170676.3-170677.27" - process $proc$libresoc.v:170676$9282 + attribute \src "libresoc.v:163315.7-163315.28" + process $proc$libresoc.v:163315$9129 assign { } { } - assign $0\fast2[63:0] \fast2$next + assign $1\alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:163324.7-163324.31" + process $proc$libresoc.v:163324$9130 + assign { } { } + assign $1\alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:163333.7-163333.28" + process $proc$libresoc.v:163333$9131 + assign { } { } + assign $1\alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_op__zero_a $1\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:163346.13-163346.24" + process $proc$libresoc.v:163346$9132 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:163353.7-163353.21" + process $proc$libresoc.v:163353$9133 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:163922.13-163922.25" + process $proc$libresoc.v:163922$9134 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:163937.14-163937.38" + process $proc$libresoc.v:163937$9135 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:163944.7-163944.18" + process $proc$libresoc.v:163944$9136 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:163958.7-163958.20" + process $proc$libresoc.v:163958$9137 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:163967.13-163967.26" + process $proc$libresoc.v:163967$9138 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:163976.7-163976.23" + process $proc$libresoc.v:163976$9139 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:163983.13-163983.26" + process $proc$libresoc.v:163983$9140 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:163990.7-163990.23" + process $proc$libresoc.v:163990$9141 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:163997.7-163997.20" + process $proc$libresoc.v:163997$9142 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:164006.7-164006.23" + process $proc$libresoc.v:164006$9143 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:164014.3-164015.29" + process $proc$libresoc.v:164014$9003 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk - update \fast2 $0\fast2[63:0] + update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:170678.3-170679.27" - process $proc$libresoc.v:170678$9283 + attribute \src "libresoc.v:164016.3-164017.35" + process $proc$libresoc.v:164016$9004 assign { } { } - assign $0\fast1[63:0] \fast1$next + assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk - update \fast1 $0\fast1[63:0] + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:170680.3-170681.21" - process $proc$libresoc.v:170680$9284 + attribute \src "libresoc.v:164018.3-164019.29" + process $proc$libresoc.v:164018$9005 assign { } { } - assign $0\rb[63:0] \rb$next + assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk - update \rb $0\rb[63:0] + update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:170682.3-170683.21" - process $proc$libresoc.v:170682$9285 + attribute \src "libresoc.v:164020.3-164021.35" + process $proc$libresoc.v:164020$9006 assign { } { } - assign $0\ra[63:0] \ra$next + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk - update \ra $0\ra[63:0] + update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:170684.3-170685.53" - process $proc$libresoc.v:170684$9286 + attribute \src "libresoc.v:164022.3-164023.29" + process $proc$libresoc.v:164022$9007 assign { } { } - assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next + assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk - update \trap_op__insn_type $0\trap_op__insn_type[6:0] + update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:170686.3-170687.49" - process $proc$libresoc.v:170686$9287 + attribute \src "libresoc.v:164024.3-164025.35" + process $proc$libresoc.v:164024$9008 assign { } { } - assign $0\trap_op__fn_unit[12:0] \trap_op__fn_unit$next + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk - update \trap_op__fn_unit $0\trap_op__fn_unit[12:0] + update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:170688.3-170689.43" - process $proc$libresoc.v:170688$9288 + attribute \src "libresoc.v:164026.3-164027.25" + process $proc$libresoc.v:164026$9009 assign { } { } - assign $0\trap_op__insn[31:0] \trap_op__insn$next + assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk - update \trap_op__insn $0\trap_op__insn[31:0] + update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:170690.3-170691.41" - process $proc$libresoc.v:170690$9289 + attribute \src "libresoc.v:164028.3-164029.31" + process $proc$libresoc.v:164028$9010 assign { } { } - assign $0\trap_op__msr[63:0] \trap_op__msr$next + assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk - update \trap_op__msr $0\trap_op__msr[63:0] + update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:170692.3-170693.41" - process $proc$libresoc.v:170692$9290 + attribute \src "libresoc.v:164030.3-164031.19" + process $proc$libresoc.v:164030$9011 assign { } { } - assign $0\trap_op__cia[63:0] \trap_op__cia$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \trap_op__cia $0\trap_op__cia[63:0] + update \o $0\o[63:0] end - attribute \src "libresoc.v:170694.3-170695.51" - process $proc$libresoc.v:170694$9291 + attribute \src "libresoc.v:164032.3-164033.25" + process $proc$libresoc.v:164032$9012 assign { } { } - assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:170696.3-170697.51" - process $proc$libresoc.v:170696$9292 + attribute \src "libresoc.v:164034.3-164035.51" + process $proc$libresoc.v:164034$9013 assign { } { } - assign $0\trap_op__traptype[7:0] \trap_op__traptype$next + assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next sync posedge \coresync_clk - update \trap_op__traptype $0\trap_op__traptype[7:0] + update \alu_op__insn_type $0\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:170698.3-170699.51" - process $proc$libresoc.v:170698$9293 + attribute \src "libresoc.v:164036.3-164037.47" + process $proc$libresoc.v:164036$9014 assign { } { } - assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next + assign $0\alu_op__fn_unit[12:0] \alu_op__fn_unit$next sync posedge \coresync_clk - update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] + update \alu_op__fn_unit $0\alu_op__fn_unit[12:0] end - attribute \src "libresoc.v:170700.3-170701.51" - process $proc$libresoc.v:170700$9294 + attribute \src "libresoc.v:164038.3-164039.61" + process $proc$libresoc.v:164038$9015 assign { } { } - assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next + assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next sync posedge \coresync_clk - update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] + update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:164040.3-164041.57" + process $proc$libresoc.v:164040$9016 + assign { } { } + assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:164042.3-164043.45" + process $proc$libresoc.v:164042$9017 + assign { } { } + assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:164044.3-164045.45" + process $proc$libresoc.v:164044$9018 + assign { } { } + assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:164046.3-164047.45" + process $proc$libresoc.v:164046$9019 + assign { } { } + assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:164048.3-164049.45" + process $proc$libresoc.v:164048$9020 + assign { } { } + assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:164050.3-164051.51" + process $proc$libresoc.v:164050$9021 + assign { } { } + assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_op__invert_in $0\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:164052.3-164053.45" + process $proc$libresoc.v:164052$9022 + assign { } { } + assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_op__zero_a $0\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:164054.3-164055.53" + process $proc$libresoc.v:164054$9023 + assign { } { } + assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_op__invert_out $0\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:164056.3-164057.51" + process $proc$libresoc.v:164056$9024 + assign { } { } + assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:164058.3-164059.55" + process $proc$libresoc.v:164058$9025 + assign { } { } + assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_op__input_carry $0\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:164060.3-164061.57" + process $proc$libresoc.v:164060$9026 + assign { } { } + assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_op__output_carry $0\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:164062.3-164063.49" + process $proc$libresoc.v:164062$9027 + assign { } { } + assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:164064.3-164065.51" + process $proc$libresoc.v:164064$9028 + assign { } { } + assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_op__is_signed $0\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:164066.3-164067.49" + process $proc$libresoc.v:164066$9029 + assign { } { } + assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + sync posedge \coresync_clk + update \alu_op__data_len $0\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:164068.3-164069.41" + process $proc$libresoc.v:164068$9030 + assign { } { } + assign $0\alu_op__insn[31:0] \alu_op__insn$next + sync posedge \coresync_clk + update \alu_op__insn $0\alu_op__insn[31:0] end - attribute \src "libresoc.v:170702.3-170703.27" - process $proc$libresoc.v:170702$9295 + attribute \src "libresoc.v:164070.3-164071.27" + process $proc$libresoc.v:164070$9031 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:170704.3-170705.29" - process $proc$libresoc.v:170704$9296 + attribute \src "libresoc.v:164072.3-164073.29" + process $proc$libresoc.v:164072$9032 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:170744.3-170761.6" - process $proc$libresoc.v:170744$9297 + attribute \src "libresoc.v:164183.3-164201.6" + process $proc$libresoc.v:164183$9033 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9034 $1\cr_a$next[3:0]$9036 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9035 $2\cr_a_ok$next[0:0]$9038 + attribute \src "libresoc.v:164184.5-164184.29" + switch \initial + attribute \src "libresoc.v:164184.9-164184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9037 $1\cr_a$next[3:0]$9036 } { \cr_a_ok$91 \cr_a$90 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9037 $1\cr_a$next[3:0]$9036 } { \cr_a_ok$91 \cr_a$90 } + case + assign $1\cr_a$next[3:0]$9036 \cr_a + assign $1\cr_a_ok$next[0:0]$9037 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9038 1'0 + case + assign $2\cr_a_ok$next[0:0]$9038 $1\cr_a_ok$next[0:0]$9037 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9034 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9035 + end + attribute \src "libresoc.v:164202.3-164220.6" + process $proc$libresoc.v:164202$9039 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$9041 $1\xer_ca$next[1:0]$9043 + assign $0\xer_ca_ok$next[0:0]$9040 $2\xer_ca_ok$next[0:0]$9044 + attribute \src "libresoc.v:164203.5-164203.29" + switch \initial + attribute \src "libresoc.v:164203.9-164203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9042 $1\xer_ca$next[1:0]$9043 } { \xer_ca_ok$93 \xer_ca$92 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9042 $1\xer_ca$next[1:0]$9043 } { \xer_ca_ok$93 \xer_ca$92 } + case + assign $1\xer_ca_ok$next[0:0]$9042 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9043 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$9044 1'0 + case + assign $2\xer_ca_ok$next[0:0]$9044 $1\xer_ca_ok$next[0:0]$9042 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9040 + update \xer_ca$next $0\xer_ca$next[1:0]$9041 + end + attribute \src "libresoc.v:164221.3-164239.6" + process $proc$libresoc.v:164221$9045 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$9046 $1\xer_ov$next[1:0]$9048 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$9047 $2\xer_ov_ok$next[0:0]$9050 + attribute \src "libresoc.v:164222.5-164222.29" + switch \initial + attribute \src "libresoc.v:164222.9-164222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9049 $1\xer_ov$next[1:0]$9048 } { \xer_ov_ok$95 \xer_ov$94 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9049 $1\xer_ov$next[1:0]$9048 } { \xer_ov_ok$95 \xer_ov$94 } + case + assign $1\xer_ov$next[1:0]$9048 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9049 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$9050 1'0 + case + assign $2\xer_ov_ok$next[0:0]$9050 $1\xer_ov_ok$next[0:0]$9049 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$9046 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9047 + end + attribute \src "libresoc.v:164240.3-164258.6" + process $proc$libresoc.v:164240$9051 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$9052 $1\xer_so$next[0:0]$9054 + assign { } { } + assign $0\xer_so_ok$next[0:0]$9053 $2\xer_so_ok$next[0:0]$9056 + attribute \src "libresoc.v:164241.5-164241.29" + switch \initial + attribute \src "libresoc.v:164241.9-164241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9055 $1\xer_so$next[0:0]$9054 } { \xer_so_ok$97 \xer_so$96 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9055 $1\xer_so$next[0:0]$9054 } { \xer_so_ok$97 \xer_so$96 } + case + assign $1\xer_so$next[0:0]$9054 \xer_so + assign $1\xer_so_ok$next[0:0]$9055 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9056 1'0 + case + assign $2\xer_so_ok$next[0:0]$9056 $1\xer_so_ok$next[0:0]$9055 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$9052 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9053 + end + attribute \src "libresoc.v:164259.3-164276.6" + process $proc$libresoc.v:164259$9057 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9298 $2\r_busy$next[0:0]$9300 - attribute \src "libresoc.v:170745.5-170745.29" + assign $0\r_busy$next[0:0]$9058 $2\r_busy$next[0:0]$9060 + attribute \src "libresoc.v:164260.5-164260.29" switch \initial - attribute \src "libresoc.v:170745.9-170745.17" + attribute \src "libresoc.v:164260.9-164260.17" case 1'1 case end @@ -349268,34 +340648,34 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9299 1'1 + assign $1\r_busy$next[0:0]$9059 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9299 1'0 + assign $1\r_busy$next[0:0]$9059 1'0 case - assign $1\r_busy$next[0:0]$9299 \r_busy + assign $1\r_busy$next[0:0]$9059 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9300 1'0 + assign $2\r_busy$next[0:0]$9060 1'0 case - assign $2\r_busy$next[0:0]$9300 $1\r_busy$next[0:0]$9299 + assign $2\r_busy$next[0:0]$9060 $1\r_busy$next[0:0]$9059 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9298 + update \r_busy$next $0\r_busy$next[0:0]$9058 end - attribute \src "libresoc.v:170762.3-170774.6" - process $proc$libresoc.v:170762$9301 + attribute \src "libresoc.v:164277.3-164289.6" + process $proc$libresoc.v:164277$9061 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9302 $1\muxid$next[1:0]$9303 - attribute \src "libresoc.v:170763.5-170763.29" + assign $0\muxid$next[1:0]$9062 $1\muxid$next[1:0]$9063 + attribute \src "libresoc.v:164278.5-164278.29" switch \initial - attribute \src "libresoc.v:170763.9-170763.17" + attribute \src "libresoc.v:164278.9-164278.17" case 1'1 case end @@ -349304,19 +340684,35 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9303 \muxid$32 + assign $1\muxid$next[1:0]$9063 \muxid$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9303 \muxid$32 + assign $1\muxid$next[1:0]$9063 \muxid$69 case - assign $1\muxid$next[1:0]$9303 \muxid + assign $1\muxid$next[1:0]$9063 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9302 + update \muxid$next $0\muxid$next[1:0]$9062 end - attribute \src "libresoc.v:170775.3-170795.6" - process $proc$libresoc.v:170775$9304 + attribute \src "libresoc.v:164290.3-164331.6" + process $proc$libresoc.v:164290$9064 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -349335,18 +340731,35 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$next[63:0]$9305 $1\trap_op__cia$next[63:0]$9314 - assign $0\trap_op__fn_unit$next[12:0]$9306 $1\trap_op__fn_unit$next[12:0]$9315 - assign $0\trap_op__insn$next[31:0]$9307 $1\trap_op__insn$next[31:0]$9316 - assign $0\trap_op__insn_type$next[6:0]$9308 $1\trap_op__insn_type$next[6:0]$9317 - assign $0\trap_op__is_32bit$next[0:0]$9309 $1\trap_op__is_32bit$next[0:0]$9318 - assign $0\trap_op__ldst_exc$next[7:0]$9310 $1\trap_op__ldst_exc$next[7:0]$9319 - assign $0\trap_op__msr$next[63:0]$9311 $1\trap_op__msr$next[63:0]$9320 - assign $0\trap_op__trapaddr$next[12:0]$9312 $1\trap_op__trapaddr$next[12:0]$9321 - assign $0\trap_op__traptype$next[7:0]$9313 $1\trap_op__traptype$next[7:0]$9322 - attribute \src "libresoc.v:170776.5-170776.29" + assign { } { } + assign { } { } + assign $0\alu_op__data_len$next[3:0]$9065 $1\alu_op__data_len$next[3:0]$9083 + assign $0\alu_op__fn_unit$next[12:0]$9066 $1\alu_op__fn_unit$next[12:0]$9084 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$next[1:0]$9069 $1\alu_op__input_carry$next[1:0]$9087 + assign $0\alu_op__insn$next[31:0]$9070 $1\alu_op__insn$next[31:0]$9088 + assign $0\alu_op__insn_type$next[6:0]$9071 $1\alu_op__insn_type$next[6:0]$9089 + assign $0\alu_op__invert_in$next[0:0]$9072 $1\alu_op__invert_in$next[0:0]$9090 + assign $0\alu_op__invert_out$next[0:0]$9073 $1\alu_op__invert_out$next[0:0]$9091 + assign $0\alu_op__is_32bit$next[0:0]$9074 $1\alu_op__is_32bit$next[0:0]$9092 + assign $0\alu_op__is_signed$next[0:0]$9075 $1\alu_op__is_signed$next[0:0]$9093 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$next[0:0]$9078 $1\alu_op__output_carry$next[0:0]$9096 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$next[0:0]$9081 $1\alu_op__write_cr0$next[0:0]$9099 + assign $0\alu_op__zero_a$next[0:0]$9082 $1\alu_op__zero_a$next[0:0]$9100 + assign $0\alu_op__imm_data__data$next[63:0]$9067 $2\alu_op__imm_data__data$next[63:0]$9101 + assign $0\alu_op__imm_data__ok$next[0:0]$9068 $2\alu_op__imm_data__ok$next[0:0]$9102 + assign $0\alu_op__oe__oe$next[0:0]$9076 $2\alu_op__oe__oe$next[0:0]$9103 + assign $0\alu_op__oe__ok$next[0:0]$9077 $2\alu_op__oe__ok$next[0:0]$9104 + assign $0\alu_op__rc__ok$next[0:0]$9079 $2\alu_op__rc__ok$next[0:0]$9105 + assign $0\alu_op__rc__rc$next[0:0]$9080 $2\alu_op__rc__rc$next[0:0]$9106 + attribute \src "libresoc.v:164291.5-164291.29" switch \initial - attribute \src "libresoc.v:170776.9-170776.17" + attribute \src "libresoc.v:164291.9-164291.17" case 1'1 case end @@ -349363,7 +340776,16 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9319 $1\trap_op__trapaddr$next[12:0]$9321 $1\trap_op__traptype$next[7:0]$9322 $1\trap_op__is_32bit$next[0:0]$9318 $1\trap_op__cia$next[63:0]$9314 $1\trap_op__msr$next[63:0]$9320 $1\trap_op__insn$next[31:0]$9316 $1\trap_op__fn_unit$next[12:0]$9315 $1\trap_op__insn_type$next[6:0]$9317 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$9088 $1\alu_op__data_len$next[3:0]$9083 $1\alu_op__is_signed$next[0:0]$9093 $1\alu_op__is_32bit$next[0:0]$9092 $1\alu_op__output_carry$next[0:0]$9096 $1\alu_op__input_carry$next[1:0]$9087 $1\alu_op__write_cr0$next[0:0]$9099 $1\alu_op__invert_out$next[0:0]$9091 $1\alu_op__zero_a$next[0:0]$9100 $1\alu_op__invert_in$next[0:0]$9090 $1\alu_op__oe__ok$next[0:0]$9095 $1\alu_op__oe__oe$next[0:0]$9094 $1\alu_op__rc__ok$next[0:0]$9097 $1\alu_op__rc__rc$next[0:0]$9098 $1\alu_op__imm_data__ok$next[0:0]$9086 $1\alu_op__imm_data__data$next[63:0]$9085 $1\alu_op__fn_unit$next[12:0]$9084 $1\alu_op__insn_type$next[6:0]$9089 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -349375,91 +340797,92 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9319 $1\trap_op__trapaddr$next[12:0]$9321 $1\trap_op__traptype$next[7:0]$9322 $1\trap_op__is_32bit$next[0:0]$9318 $1\trap_op__cia$next[63:0]$9314 $1\trap_op__msr$next[63:0]$9320 $1\trap_op__insn$next[31:0]$9316 $1\trap_op__fn_unit$next[12:0]$9315 $1\trap_op__insn_type$next[6:0]$9317 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } - case - assign $1\trap_op__cia$next[63:0]$9314 \trap_op__cia - assign $1\trap_op__fn_unit$next[12:0]$9315 \trap_op__fn_unit - assign $1\trap_op__insn$next[31:0]$9316 \trap_op__insn - assign $1\trap_op__insn_type$next[6:0]$9317 \trap_op__insn_type - assign $1\trap_op__is_32bit$next[0:0]$9318 \trap_op__is_32bit - assign $1\trap_op__ldst_exc$next[7:0]$9319 \trap_op__ldst_exc - assign $1\trap_op__msr$next[63:0]$9320 \trap_op__msr - assign $1\trap_op__trapaddr$next[12:0]$9321 \trap_op__trapaddr - assign $1\trap_op__traptype$next[7:0]$9322 \trap_op__traptype - end - sync always - update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9305 - update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[12:0]$9306 - update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9307 - update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9308 - update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9309 - update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9310 - update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9311 - update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9312 - update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9313 - end - attribute \src "libresoc.v:170796.3-170808.6" - process $proc$libresoc.v:170796$9323 - assign { } { } - assign { } { } - assign $0\ra$next[63:0]$9324 $1\ra$next[63:0]$9325 - attribute \src "libresoc.v:170797.5-170797.29" - switch \initial - attribute \src "libresoc.v:170797.9-170797.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 assign { } { } - assign $1\ra$next[63:0]$9325 \ra$42 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- assign { } { } - assign $1\ra$next[63:0]$9325 \ra$42 - case - assign $1\ra$next[63:0]$9325 \ra - end - sync always - update \ra$next $0\ra$next[63:0]$9324 - end - attribute \src "libresoc.v:170809.3-170821.6" - process $proc$libresoc.v:170809$9326 - assign { } { } - assign { } { } - assign $0\rb$next[63:0]$9327 $1\rb$next[63:0]$9328 - attribute \src "libresoc.v:170810.5-170810.29" - switch \initial - attribute \src "libresoc.v:170810.9-170810.17" - case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$9088 $1\alu_op__data_len$next[3:0]$9083 $1\alu_op__is_signed$next[0:0]$9093 $1\alu_op__is_32bit$next[0:0]$9092 $1\alu_op__output_carry$next[0:0]$9096 $1\alu_op__input_carry$next[1:0]$9087 $1\alu_op__write_cr0$next[0:0]$9099 $1\alu_op__invert_out$next[0:0]$9091 $1\alu_op__zero_a$next[0:0]$9100 $1\alu_op__invert_in$next[0:0]$9090 $1\alu_op__oe__ok$next[0:0]$9095 $1\alu_op__oe__oe$next[0:0]$9094 $1\alu_op__rc__ok$next[0:0]$9097 $1\alu_op__rc__rc$next[0:0]$9098 $1\alu_op__imm_data__ok$next[0:0]$9086 $1\alu_op__imm_data__data$next[63:0]$9085 $1\alu_op__fn_unit$next[12:0]$9084 $1\alu_op__insn_type$next[6:0]$9089 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } case + assign $1\alu_op__data_len$next[3:0]$9083 \alu_op__data_len + assign $1\alu_op__fn_unit$next[12:0]$9084 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$9085 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$9086 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$9087 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$9088 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$9089 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$9090 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$9091 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$9092 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$9093 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$9094 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$9095 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$9096 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$9097 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$9098 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$9099 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$9100 \alu_op__zero_a end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1'1 assign { } { } - assign $1\rb$next[63:0]$9328 \rb$43 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- assign { } { } - assign $1\rb$next[63:0]$9328 \rb$43 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$next[63:0]$9101 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$9102 1'0 + assign $2\alu_op__rc__rc$next[0:0]$9106 1'0 + assign $2\alu_op__rc__ok$next[0:0]$9105 1'0 + assign $2\alu_op__oe__oe$next[0:0]$9103 1'0 + assign $2\alu_op__oe__ok$next[0:0]$9104 1'0 case - assign $1\rb$next[63:0]$9328 \rb + assign $2\alu_op__imm_data__data$next[63:0]$9101 $1\alu_op__imm_data__data$next[63:0]$9085 + assign $2\alu_op__imm_data__ok$next[0:0]$9102 $1\alu_op__imm_data__ok$next[0:0]$9086 + assign $2\alu_op__oe__oe$next[0:0]$9103 $1\alu_op__oe__oe$next[0:0]$9094 + assign $2\alu_op__oe__ok$next[0:0]$9104 $1\alu_op__oe__ok$next[0:0]$9095 + assign $2\alu_op__rc__ok$next[0:0]$9105 $1\alu_op__rc__ok$next[0:0]$9097 + assign $2\alu_op__rc__rc$next[0:0]$9106 $1\alu_op__rc__rc$next[0:0]$9098 end sync always - update \rb$next $0\rb$next[63:0]$9327 + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9065 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[12:0]$9066 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9067 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9068 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9069 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9070 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9071 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9072 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9073 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9074 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9075 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9076 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9077 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9078 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9079 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9080 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9081 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9082 end - attribute \src "libresoc.v:170822.3-170834.6" - process $proc$libresoc.v:170822$9329 + attribute \src "libresoc.v:164332.3-164350.6" + process $proc$libresoc.v:164332$9107 assign { } { } assign { } { } - assign $0\fast1$next[63:0]$9330 $1\fast1$next[63:0]$9331 - attribute \src "libresoc.v:170823.5-170823.29" + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9108 $1\o$next[63:0]$9110 + assign { } { } + assign $0\o_ok$next[0:0]$9109 $2\o_ok$next[0:0]$9112 + attribute \src "libresoc.v:164333.5-164333.29" switch \initial - attribute \src "libresoc.v:170823.9-170823.17" + attribute \src "libresoc.v:164333.9-164333.17" case 1'1 case end @@ -349468,362 +340891,344 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast1$next[63:0]$9331 \fast1$44 + assign { } { } + assign { $1\o_ok$next[0:0]$9111 $1\o$next[63:0]$9110 } { \o_ok$89 \o$88 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast1$next[63:0]$9331 \fast1$44 - case - assign $1\fast1$next[63:0]$9331 \fast1 - end - sync always - update \fast1$next $0\fast1$next[63:0]$9330 - end - attribute \src "libresoc.v:170835.3-170847.6" - process $proc$libresoc.v:170835$9332 - assign { } { } - assign { } { } - assign $0\fast2$next[63:0]$9333 $1\fast2$next[63:0]$9334 - attribute \src "libresoc.v:170836.5-170836.29" - switch \initial - attribute \src "libresoc.v:170836.9-170836.17" - case 1'1 + assign { } { } + assign { $1\o_ok$next[0:0]$9111 $1\o$next[63:0]$9110 } { \o_ok$89 \o$88 } case + assign $1\o$next[63:0]$9110 \o + assign $1\o_ok$next[0:0]$9111 \o_ok end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\fast2$next[63:0]$9334 \fast2$45 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\fast2$next[63:0]$9334 \fast2$45 + assign $2\o_ok$next[0:0]$9112 1'0 case - assign $1\fast2$next[63:0]$9334 \fast2 + assign $2\o_ok$next[0:0]$9112 $1\o_ok$next[0:0]$9111 end sync always - update \fast2$next $0\fast2$next[63:0]$9333 + update \o$next $0\o$next[63:0]$9108 + update \o_ok$next $0\o_ok$next[0:0]$9109 end - connect \$30 $and$libresoc.v:170675$9281_Y + connect \$67 $and$libresoc.v:164013$9002_Y + connect \xer_so_ok$98 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect \fast2$45 \dummy_fast2$28 - connect \fast1$44 \dummy_fast1$27 - connect \rb$43 \dummy_rb$26 - connect \ra$42 \dummy_ra$25 - connect { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } { \dummy_trap_op__ldst_exc$24 \dummy_trap_op__trapaddr$23 \dummy_trap_op__traptype$22 \dummy_trap_op__is_32bit$21 \dummy_trap_op__cia$20 \dummy_trap_op__msr$19 \dummy_trap_op__insn$18 \dummy_trap_op__fn_unit$17 \dummy_trap_op__insn_type$16 } - connect \muxid$32 \dummy_muxid$15 - connect \p_valid_i_p_ready_o \$30 + connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } + connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } + connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } + connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } + connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } + connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } + connect \muxid$69 \main_muxid$45 + connect \p_valid_i_p_ready_o \$67 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$29 \p_valid_i - connect \dummy_fast2 \fast2$14 - connect \dummy_fast1 \fast1$13 - connect \dummy_rb \rb$12 - connect \dummy_ra \ra$11 - connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } - connect \dummy_muxid \muxid$1 + connect \p_valid_i$66 \p_valid_i + connect \main_xer_ca \input_xer_ca$44 + connect \main_xer_so \input_xer_so$43 + connect \main_rb \input_rb$42 + connect \main_ra \input_ra$41 + connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } + connect \main_muxid \input_muxid$22 + connect \input_xer_ca \xer_ca$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } + connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:170869.1-172044.10" +attribute \src "libresoc.v:164380.1-165802.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" attribute \generator "nMigen" -module \pipe2 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 4 $0\alu_op__data_len$18$next[3:0]$9419 - attribute \src "libresoc.v:171785.3-171786.57" - wire width 4 $0\alu_op__data_len$18[3:0]$9405 - attribute \src "libresoc.v:170877.13-170877.41" - wire width 4 $0\alu_op__data_len$18[3:0]$9493 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 13 $0\alu_op__fn_unit$3$next[12:0]$9420 - attribute \src "libresoc.v:171755.3-171756.53" - wire width 13 $0\alu_op__fn_unit$3[12:0]$9375 - attribute \src "libresoc.v:170914.14-170914.44" - wire width 13 $0\alu_op__fn_unit$3[12:0]$9495 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9421 - attribute \src "libresoc.v:171757.3-171758.67" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9377 - attribute \src "libresoc.v:170937.14-170937.63" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9497 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__imm_data__ok$5$next[0:0]$9422 - attribute \src "libresoc.v:171759.3-171760.63" - wire $0\alu_op__imm_data__ok$5[0:0]$9379 - attribute \src "libresoc.v:170946.7-170946.38" - wire $0\alu_op__imm_data__ok$5[0:0]$9499 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 2 $0\alu_op__input_carry$14$next[1:0]$9423 - attribute \src "libresoc.v:171777.3-171778.63" - wire width 2 $0\alu_op__input_carry$14[1:0]$9397 - attribute \src "libresoc.v:170963.13-170963.44" - wire width 2 $0\alu_op__input_carry$14[1:0]$9501 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 32 $0\alu_op__insn$19$next[31:0]$9424 - attribute \src "libresoc.v:171787.3-171788.49" - wire width 32 $0\alu_op__insn$19[31:0]$9407 - attribute \src "libresoc.v:170976.14-170976.39" - wire width 32 $0\alu_op__insn$19[31:0]$9503 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 7 $0\alu_op__insn_type$2$next[6:0]$9425 - attribute \src "libresoc.v:171753.3-171754.57" - wire width 7 $0\alu_op__insn_type$2[6:0]$9373 - attribute \src "libresoc.v:171133.13-171133.42" - wire width 7 $0\alu_op__insn_type$2[6:0]$9505 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__invert_in$10$next[0:0]$9426 - attribute \src "libresoc.v:171769.3-171770.59" - wire $0\alu_op__invert_in$10[0:0]$9389 - attribute \src "libresoc.v:171216.7-171216.36" - wire $0\alu_op__invert_in$10[0:0]$9507 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__invert_out$12$next[0:0]$9427 - attribute \src "libresoc.v:171773.3-171774.61" - wire $0\alu_op__invert_out$12[0:0]$9393 - attribute \src "libresoc.v:171225.7-171225.37" - wire $0\alu_op__invert_out$12[0:0]$9509 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__is_32bit$16$next[0:0]$9428 - attribute \src "libresoc.v:171781.3-171782.57" - wire $0\alu_op__is_32bit$16[0:0]$9401 - attribute \src "libresoc.v:171234.7-171234.35" - wire $0\alu_op__is_32bit$16[0:0]$9511 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__is_signed$17$next[0:0]$9429 - attribute \src "libresoc.v:171783.3-171784.59" - wire $0\alu_op__is_signed$17[0:0]$9403 - attribute \src "libresoc.v:171243.7-171243.36" - wire $0\alu_op__is_signed$17[0:0]$9513 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__oe__oe$8$next[0:0]$9430 - attribute \src "libresoc.v:171765.3-171766.51" - wire $0\alu_op__oe__oe$8[0:0]$9385 - attribute \src "libresoc.v:171254.7-171254.32" - wire $0\alu_op__oe__oe$8[0:0]$9515 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__oe__ok$9$next[0:0]$9431 - attribute \src "libresoc.v:171767.3-171768.51" - wire $0\alu_op__oe__ok$9[0:0]$9387 - attribute \src "libresoc.v:171263.7-171263.32" - wire $0\alu_op__oe__ok$9[0:0]$9517 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__output_carry$15$next[0:0]$9432 - attribute \src "libresoc.v:171779.3-171780.65" - wire $0\alu_op__output_carry$15[0:0]$9399 - attribute \src "libresoc.v:171270.7-171270.39" - wire $0\alu_op__output_carry$15[0:0]$9519 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__rc__ok$7$next[0:0]$9433 - attribute \src "libresoc.v:171763.3-171764.51" - wire $0\alu_op__rc__ok$7[0:0]$9383 - attribute \src "libresoc.v:171281.7-171281.32" - wire $0\alu_op__rc__ok$7[0:0]$9521 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__rc__rc$6$next[0:0]$9434 - attribute \src "libresoc.v:171761.3-171762.51" - wire $0\alu_op__rc__rc$6[0:0]$9381 - attribute \src "libresoc.v:171288.7-171288.32" - wire $0\alu_op__rc__rc$6[0:0]$9523 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__write_cr0$13$next[0:0]$9435 - attribute \src "libresoc.v:171775.3-171776.59" - wire $0\alu_op__write_cr0$13[0:0]$9395 - attribute \src "libresoc.v:171297.7-171297.36" - wire $0\alu_op__write_cr0$13[0:0]$9525 - attribute \src "libresoc.v:171888.3-171929.6" - wire $0\alu_op__zero_a$11$next[0:0]$9436 - attribute \src "libresoc.v:171771.3-171772.53" - wire $0\alu_op__zero_a$11[0:0]$9391 - attribute \src "libresoc.v:171306.7-171306.33" - wire $0\alu_op__zero_a$11[0:0]$9527 - attribute \src "libresoc.v:171949.3-171967.6" - wire width 4 $0\cr_a$22$next[3:0]$9468 - attribute \src "libresoc.v:171745.3-171746.33" - wire width 4 $0\cr_a$22[3:0]$9365 - attribute \src "libresoc.v:171319.13-171319.29" - wire width 4 $0\cr_a$22[3:0]$9529 - attribute \src "libresoc.v:171949.3-171967.6" - wire $0\cr_a_ok$23$next[0:0]$9469 - attribute \src "libresoc.v:171747.3-171748.39" - wire $0\cr_a_ok$23[0:0]$9367 - attribute \src "libresoc.v:171328.7-171328.26" - wire $0\cr_a_ok$23[0:0]$9531 - attribute \src "libresoc.v:170870.7-170870.20" +module \pipe1$110 + attribute \src "libresoc.v:165735.3-165753.6" + wire width 4 $0\cr_a$next[3:0]$9233 + attribute \src "libresoc.v:165477.3-165478.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:165735.3-165753.6" + wire $0\cr_a_ok$next[0:0]$9234 + attribute \src "libresoc.v:165479.3-165480.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:164381.7-164381.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171875.3-171887.6" - wire width 2 $0\muxid$1$next[1:0]$9416 - attribute \src "libresoc.v:171789.3-171790.33" - wire width 2 $0\muxid$1[1:0]$9409 - attribute \src "libresoc.v:171339.13-171339.29" - wire width 2 $0\muxid$1[1:0]$9533 - attribute \src "libresoc.v:171930.3-171948.6" - wire width 64 $0\o$20$next[63:0]$9462 - attribute \src "libresoc.v:171749.3-171750.27" - wire width 64 $0\o$20[63:0]$9369 - attribute \src "libresoc.v:171354.14-171354.43" - wire width 64 $0\o$20[63:0]$9535 - attribute \src "libresoc.v:171930.3-171948.6" - wire $0\o_ok$21$next[0:0]$9463 - attribute \src "libresoc.v:171751.3-171752.33" - wire $0\o_ok$21[0:0]$9371 - attribute \src "libresoc.v:171363.7-171363.23" - wire $0\o_ok$21[0:0]$9537 - attribute \src "libresoc.v:171857.3-171874.6" - wire $0\r_busy$next[0:0]$9412 - attribute \src "libresoc.v:171791.3-171792.29" + attribute \src "libresoc.v:165662.3-165674.6" + wire width 2 $0\muxid$next[1:0]$9183 + attribute \src "libresoc.v:165519.3-165520.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:165716.3-165734.6" + wire width 64 $0\o$next[63:0]$9227 + attribute \src "libresoc.v:165481.3-165482.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:165716.3-165734.6" + wire $0\o_ok$next[0:0]$9228 + attribute \src "libresoc.v:165483.3-165484.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:165644.3-165661.6" + wire $0\r_busy$next[0:0]$9179 + attribute \src "libresoc.v:165521.3-165522.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:171968.3-171986.6" - wire width 2 $0\xer_ca$24$next[1:0]$9474 - attribute \src "libresoc.v:171741.3-171742.37" - wire width 2 $0\xer_ca$24[1:0]$9361 - attribute \src "libresoc.v:171676.13-171676.31" - wire width 2 $0\xer_ca$24[1:0]$9540 - attribute \src "libresoc.v:171968.3-171986.6" - wire $0\xer_ca_ok$25$next[0:0]$9475 - attribute \src "libresoc.v:171743.3-171744.43" - wire $0\xer_ca_ok$25[0:0]$9363 - attribute \src "libresoc.v:171685.7-171685.28" - wire $0\xer_ca_ok$25[0:0]$9542 - attribute \src "libresoc.v:171987.3-172005.6" - wire width 2 $0\xer_ov$26$next[1:0]$9480 - attribute \src "libresoc.v:171737.3-171738.37" - wire width 2 $0\xer_ov$26[1:0]$9357 - attribute \src "libresoc.v:171696.13-171696.31" - wire width 2 $0\xer_ov$26[1:0]$9544 - attribute \src "libresoc.v:171987.3-172005.6" - wire $0\xer_ov_ok$27$next[0:0]$9481 - attribute \src "libresoc.v:171739.3-171740.43" - wire $0\xer_ov_ok$27[0:0]$9359 - attribute \src "libresoc.v:171705.7-171705.28" - wire $0\xer_ov_ok$27[0:0]$9546 - attribute \src "libresoc.v:172006.3-172024.6" - wire $0\xer_so$28$next[0:0]$9486 - attribute \src "libresoc.v:171733.3-171734.37" - wire $0\xer_so$28[0:0]$9353 - attribute \src "libresoc.v:171716.7-171716.25" - wire $0\xer_so$28[0:0]$9548 - attribute \src "libresoc.v:172006.3-172024.6" - wire $0\xer_so_ok$29$next[0:0]$9487 - attribute \src "libresoc.v:171735.3-171736.43" - wire $0\xer_so_ok$29[0:0]$9355 - attribute \src "libresoc.v:171725.7-171725.28" - wire $0\xer_so_ok$29[0:0]$9550 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 4 $1\alu_op__data_len$18$next[3:0]$9437 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 13 $1\alu_op__fn_unit$3$next[12:0]$9438 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9439 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__imm_data__ok$5$next[0:0]$9440 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 2 $1\alu_op__input_carry$14$next[1:0]$9441 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 32 $1\alu_op__insn$19$next[31:0]$9442 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 7 $1\alu_op__insn_type$2$next[6:0]$9443 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__invert_in$10$next[0:0]$9444 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__invert_out$12$next[0:0]$9445 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__is_32bit$16$next[0:0]$9446 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__is_signed$17$next[0:0]$9447 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__oe__oe$8$next[0:0]$9448 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__oe__ok$9$next[0:0]$9449 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__output_carry$15$next[0:0]$9450 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__rc__ok$7$next[0:0]$9451 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__rc__rc$6$next[0:0]$9452 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__write_cr0$13$next[0:0]$9453 - attribute \src "libresoc.v:171888.3-171929.6" - wire $1\alu_op__zero_a$11$next[0:0]$9454 - attribute \src "libresoc.v:171949.3-171967.6" - wire width 4 $1\cr_a$22$next[3:0]$9470 - attribute \src "libresoc.v:171949.3-171967.6" - wire $1\cr_a_ok$23$next[0:0]$9471 - attribute \src "libresoc.v:171875.3-171887.6" - wire width 2 $1\muxid$1$next[1:0]$9417 - attribute \src "libresoc.v:171930.3-171948.6" - wire width 64 $1\o$20$next[63:0]$9464 - attribute \src "libresoc.v:171930.3-171948.6" - wire $1\o_ok$21$next[0:0]$9465 - attribute \src "libresoc.v:171857.3-171874.6" - wire $1\r_busy$next[0:0]$9413 - attribute \src "libresoc.v:171669.7-171669.20" + attribute \src "libresoc.v:165675.3-165715.6" + wire width 13 $0\sr_op__fn_unit$next[12:0]$9186 + attribute \src "libresoc.v:165487.3-165488.45" + wire width 13 $0\sr_op__fn_unit[12:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$9187 + attribute \src "libresoc.v:165489.3-165490.59" + wire width 64 $0\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__imm_data__ok$next[0:0]$9188 + attribute \src "libresoc.v:165491.3-165492.55" + wire $0\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$9189 + attribute \src "libresoc.v:165505.3-165506.53" + wire width 2 $0\sr_op__input_carry[1:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__input_cr$next[0:0]$9190 + attribute \src "libresoc.v:165509.3-165510.47" + wire $0\sr_op__input_cr[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire width 32 $0\sr_op__insn$next[31:0]$9191 + attribute \src "libresoc.v:165517.3-165518.39" + wire width 32 $0\sr_op__insn[31:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$9192 + attribute \src "libresoc.v:165485.3-165486.49" + wire width 7 $0\sr_op__insn_type[6:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__invert_in$next[0:0]$9193 + attribute \src "libresoc.v:165503.3-165504.49" + wire $0\sr_op__invert_in[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__is_32bit$next[0:0]$9194 + attribute \src "libresoc.v:165513.3-165514.47" + wire $0\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__is_signed$next[0:0]$9195 + attribute \src "libresoc.v:165515.3-165516.49" + wire $0\sr_op__is_signed[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__oe__oe$next[0:0]$9196 + attribute \src "libresoc.v:165497.3-165498.43" + wire $0\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__oe__ok$next[0:0]$9197 + attribute \src "libresoc.v:165499.3-165500.43" + wire $0\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__output_carry$next[0:0]$9198 + attribute \src "libresoc.v:165507.3-165508.55" + wire $0\sr_op__output_carry[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__output_cr$next[0:0]$9199 + attribute \src "libresoc.v:165511.3-165512.49" + wire $0\sr_op__output_cr[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__rc__ok$next[0:0]$9200 + attribute \src "libresoc.v:165495.3-165496.43" + wire $0\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__rc__rc$next[0:0]$9201 + attribute \src "libresoc.v:165493.3-165494.43" + wire $0\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $0\sr_op__write_cr0$next[0:0]$9202 + attribute \src "libresoc.v:165501.3-165502.49" + wire $0\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:165625.3-165643.6" + wire width 2 $0\xer_ca$next[1:0]$9174 + attribute \src "libresoc.v:165469.3-165470.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:165625.3-165643.6" + wire $0\xer_ca_ok$next[0:0]$9173 + attribute \src "libresoc.v:165471.3-165472.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:165754.3-165772.6" + wire $0\xer_so$next[0:0]$9239 + attribute \src "libresoc.v:165473.3-165474.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:165754.3-165772.6" + wire $0\xer_so_ok$next[0:0]$9240 + attribute \src "libresoc.v:165475.3-165476.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:165735.3-165753.6" + wire width 4 $1\cr_a$next[3:0]$9235 + attribute \src "libresoc.v:164390.13-164390.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:165735.3-165753.6" + wire $1\cr_a_ok$next[0:0]$9236 + attribute \src "libresoc.v:164399.7-164399.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:165662.3-165674.6" + wire width 2 $1\muxid$next[1:0]$9184 + attribute \src "libresoc.v:164956.13-164956.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:165716.3-165734.6" + wire width 64 $1\o$next[63:0]$9229 + attribute \src "libresoc.v:164971.14-164971.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:165716.3-165734.6" + wire $1\o_ok$next[0:0]$9230 + attribute \src "libresoc.v:164978.7-164978.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:165644.3-165661.6" + wire $1\r_busy$next[0:0]$9180 + attribute \src "libresoc.v:164992.7-164992.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:171968.3-171986.6" - wire width 2 $1\xer_ca$24$next[1:0]$9476 - attribute \src "libresoc.v:171968.3-171986.6" - wire $1\xer_ca_ok$25$next[0:0]$9477 - attribute \src "libresoc.v:171987.3-172005.6" - wire width 2 $1\xer_ov$26$next[1:0]$9482 - attribute \src "libresoc.v:171987.3-172005.6" - wire $1\xer_ov_ok$27$next[0:0]$9483 - attribute \src "libresoc.v:172006.3-172024.6" - wire $1\xer_so$28$next[0:0]$9488 - attribute \src "libresoc.v:172006.3-172024.6" - wire $1\xer_so_ok$29$next[0:0]$9489 - attribute \src "libresoc.v:171888.3-171929.6" - wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9455 - attribute \src "libresoc.v:171888.3-171929.6" - wire $2\alu_op__imm_data__ok$5$next[0:0]$9456 - attribute \src "libresoc.v:171888.3-171929.6" - wire $2\alu_op__oe__oe$8$next[0:0]$9457 - attribute \src "libresoc.v:171888.3-171929.6" - wire $2\alu_op__oe__ok$9$next[0:0]$9458 - attribute \src "libresoc.v:171888.3-171929.6" - wire $2\alu_op__rc__ok$7$next[0:0]$9459 - attribute \src "libresoc.v:171888.3-171929.6" - wire $2\alu_op__rc__rc$6$next[0:0]$9460 - attribute \src "libresoc.v:171949.3-171967.6" - wire $2\cr_a_ok$23$next[0:0]$9472 - attribute \src "libresoc.v:171930.3-171948.6" - wire $2\o_ok$21$next[0:0]$9466 - attribute \src "libresoc.v:171857.3-171874.6" - wire $2\r_busy$next[0:0]$9414 - attribute \src "libresoc.v:171968.3-171986.6" - wire $2\xer_ca_ok$25$next[0:0]$9478 - attribute \src "libresoc.v:171987.3-172005.6" - wire $2\xer_ov_ok$27$next[0:0]$9484 - attribute \src "libresoc.v:172006.3-172024.6" - wire $2\xer_so_ok$29$next[0:0]$9490 - attribute \src "libresoc.v:171732.18-171732.118" - wire $and$libresoc.v:171732$9351_Y + attribute \src "libresoc.v:165675.3-165715.6" + wire width 13 $1\sr_op__fn_unit$next[12:0]$9203 + attribute \src "libresoc.v:165017.14-165017.39" + wire width 13 $1\sr_op__fn_unit[12:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$9204 + attribute \src "libresoc.v:165054.14-165054.58" + wire width 64 $1\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__imm_data__ok$next[0:0]$9205 + attribute \src "libresoc.v:165063.7-165063.33" + wire $1\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$9206 + attribute \src "libresoc.v:165076.13-165076.38" + wire width 2 $1\sr_op__input_carry[1:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__input_cr$next[0:0]$9207 + attribute \src "libresoc.v:165093.7-165093.29" + wire $1\sr_op__input_cr[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire width 32 $1\sr_op__insn$next[31:0]$9208 + attribute \src "libresoc.v:165102.14-165102.33" + wire width 32 $1\sr_op__insn[31:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$9209 + attribute \src "libresoc.v:165185.13-165185.37" + wire width 7 $1\sr_op__insn_type[6:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__invert_in$next[0:0]$9210 + attribute \src "libresoc.v:165342.7-165342.30" + wire $1\sr_op__invert_in[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__is_32bit$next[0:0]$9211 + attribute \src "libresoc.v:165351.7-165351.29" + wire $1\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__is_signed$next[0:0]$9212 + attribute \src "libresoc.v:165360.7-165360.30" + wire $1\sr_op__is_signed[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__oe__oe$next[0:0]$9213 + attribute \src "libresoc.v:165369.7-165369.27" + wire $1\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__oe__ok$next[0:0]$9214 + attribute \src "libresoc.v:165378.7-165378.27" + wire $1\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__output_carry$next[0:0]$9215 + attribute \src "libresoc.v:165387.7-165387.33" + wire $1\sr_op__output_carry[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__output_cr$next[0:0]$9216 + attribute \src "libresoc.v:165396.7-165396.30" + wire $1\sr_op__output_cr[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__rc__ok$next[0:0]$9217 + attribute \src "libresoc.v:165405.7-165405.27" + wire $1\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__rc__rc$next[0:0]$9218 + attribute \src "libresoc.v:165414.7-165414.27" + wire $1\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:165675.3-165715.6" + wire $1\sr_op__write_cr0$next[0:0]$9219 + attribute \src "libresoc.v:165423.7-165423.30" + wire $1\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:165625.3-165643.6" + wire width 2 $1\xer_ca$next[1:0]$9176 + attribute \src "libresoc.v:165432.13-165432.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:165625.3-165643.6" + wire $1\xer_ca_ok$next[0:0]$9175 + attribute \src "libresoc.v:165443.7-165443.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:165754.3-165772.6" + wire $1\xer_so$next[0:0]$9241 + attribute \src "libresoc.v:165452.7-165452.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:165754.3-165772.6" + wire $1\xer_so_ok$next[0:0]$9242 + attribute \src "libresoc.v:165461.7-165461.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:165735.3-165753.6" + wire $2\cr_a_ok$next[0:0]$9237 + attribute \src "libresoc.v:165716.3-165734.6" + wire $2\o_ok$next[0:0]$9231 + attribute \src "libresoc.v:165644.3-165661.6" + wire $2\r_busy$next[0:0]$9181 + attribute \src "libresoc.v:165675.3-165715.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$9220 + attribute \src "libresoc.v:165675.3-165715.6" + wire $2\sr_op__imm_data__ok$next[0:0]$9221 + attribute \src "libresoc.v:165675.3-165715.6" + wire $2\sr_op__oe__oe$next[0:0]$9222 + attribute \src "libresoc.v:165675.3-165715.6" + wire $2\sr_op__oe__ok$next[0:0]$9223 + attribute \src "libresoc.v:165675.3-165715.6" + wire $2\sr_op__rc__ok$next[0:0]$9224 + attribute \src "libresoc.v:165675.3-165715.6" + wire $2\sr_op__rc__rc$next[0:0]$9225 + attribute \src "libresoc.v:165625.3-165643.6" + wire $2\xer_ca_ok$next[0:0]$9177 + attribute \src "libresoc.v:165754.3-165772.6" + wire $2\xer_so_ok$next[0:0]$9243 + attribute \src "libresoc.v:165468.18-165468.118" + wire $and$libresoc.v:165468$9144_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$79 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \alu_op__fn_unit + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 55 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 24 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:164381.7-164381.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc$41 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -349839,9 +341244,7 @@ module \pipe2 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 37 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_op__fn_unit$3$next + wire width 13 \input_sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -349857,51 +341260,35 @@ module \pipe2 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_op__fn_unit$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__imm_data__ok + wire width 13 \input_sr_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__imm_data__ok$5 + wire width 64 \input_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$5$next + wire width 64 \input_sr_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$66 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire \input_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 17 \alu_op__input_carry + wire \input_sr_op__imm_data__ok$25 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 48 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$14$next + wire width 2 \input_sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$75 + wire width 2 \input_sr_op__input_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \alu_op__insn + wire \input_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \alu_op__insn$19 + wire \input_sr_op__input_cr$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$19$next + wire width 32 \input_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$80 + wire width 32 \input_sr_op__insn$38 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -349977,7 +341364,7 @@ module \pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \alu_op__insn_type + wire width 7 \input_sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -350053,9 +341440,129 @@ module \pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 36 \alu_op__insn_type$2 + wire width 7 \input_sr_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$2$next + wire \input_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rc + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_sr_op__fn_unit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok$48 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn$61 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -350131,153 +341638,189 @@ module \pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \alu_op__oe__ok$9 + wire width 7 \main_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$9$next + wire width 7 \main_sr_op__insn_type$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \alu_op__output_carry + wire \main_sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \alu_op__output_carry$15 + wire \main_sr_op__invert_in$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$15$next + wire \main_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$76 + wire \main_sr_op__is_32bit$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__rc__ok + wire \main_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$68 + wire \main_sr_op__is_signed$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \alu_op__rc__ok$7 + wire \main_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$7$next + wire \main_sr_op__oe__oe$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__rc__rc + wire \main_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \alu_op__rc__rc$6 + wire \main_sr_op__oe__ok$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$6$next + wire \main_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$67 + wire \main_sr_op__output_carry$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__write_cr0 + wire \main_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \alu_op__write_cr0$13 + wire \main_sr_op__output_cr$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$13$next + wire \main_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$74 + wire \main_sr_op__rc__ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__zero_a + wire \main_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \alu_op__zero_a$11 + wire \main_sr_op__rc__rc$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$11$next + wire \main_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 56 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 57 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$23$next + wire \main_sr_op__write_cr0$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$55 + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$84 - attribute \src "libresoc.v:170870.7-170870.15" - wire \initial + wire \main_xer_so$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 4 \muxid + wire width 2 output 4 \muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 35 \muxid$1 + wire width 2 input 32 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$1$next + wire width 2 \muxid$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$62 + wire width 2 \muxid$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" wire \n_i_rdy_data attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 34 \n_ready_i + wire input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 54 \o$20 + wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$20$next + wire width 64 output 22 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$81 + wire width 64 \o$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 24 \o_ok + wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 55 \o_ok$21 + wire output 23 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$21$next + wire \o_ok$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 31 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 30 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 52 \rc + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len$47 + wire width 13 output 6 \sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -350293,7 +341836,7 @@ module \pipe2 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_alu_op__fn_unit + wire width 13 input 34 \sr_op__fn_unit$3 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -350309,31 +341852,61 @@ module \pipe2 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_alu_op__fn_unit$32 + wire width 13 \sr_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_alu_op__imm_data__data + wire width 13 \sr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_alu_op__imm_data__data$33 + wire width 64 output 7 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__imm_data__ok + wire width 64 input 35 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__imm_data__ok$34 + wire width 64 \sr_op__imm_data__data$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_alu_op__input_carry + wire width 2 output 15 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_alu_op__input_carry$43 + wire width 2 input 43 \sr_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_alu_op__insn + wire width 2 \sr_op__input_carry$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_alu_op__insn$48 + wire width 2 \sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -350409,7 +341982,7 @@ module \pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_alu_op__insn_type + wire width 7 output 5 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -350485,701 +342058,745 @@ module \pipe2 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_alu_op__insn_type$31 + wire width 7 input 33 \sr_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_in + wire width 7 \sr_op__insn_type$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_in$39 + wire width 7 \sr_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_out + wire output 14 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__invert_out$41 + wire input 42 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_32bit + wire \sr_op__invert_in$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_32bit$45 + wire \sr_op__invert_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_signed + wire output 19 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__is_signed$46 + wire input 47 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__oe + wire \sr_op__is_32bit$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__oe$37 + wire \sr_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__ok + wire output 20 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__oe__ok$38 + wire input 48 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__output_carry + wire \sr_op__is_signed$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__output_carry$44 + wire \sr_op__is_signed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__ok + wire output 11 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__ok$36 + wire \sr_op__oe__oe$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__rc + wire input 39 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__rc__rc$35 + wire \sr_op__oe__oe$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__write_cr0 + wire output 12 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__write_cr0$42 + wire \sr_op__oe__ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__zero_a + wire input 40 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_alu_op__zero_a$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_muxid$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ca$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 58 \xer_ca$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 59 \xer_ca_ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$25$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 60 \xer_ov$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$26$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$87 + wire \sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 30 \xer_ov_ok + wire width 2 output 28 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 54 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \xer_ca$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 61 \xer_ov_ok$27 + wire width 2 \xer_ca$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$27$next + wire width 2 \xer_ca$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$57 + wire output 29 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$88 + wire \xer_ca_ok$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 31 \xer_so + wire \xer_ca_ok$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 62 \xer_so$28 + wire \xer_ca_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$28$next + wire output 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 53 \xer_so$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$89 + wire \xer_so$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 32 \xer_so_ok + wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 63 \xer_so_ok$29 + wire output 27 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$29$next + wire \xer_so_ok$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$58 + wire \xer_so_ok$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$90 + wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:171732$9351 + cell $and $and$libresoc.v:165468$9144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$59 + connect \A \p_valid_i$64 connect \B \p_ready_o - connect \Y $and$libresoc.v:171732$9351_Y + connect \Y $and$libresoc.v:165468$9144_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:165523.15-165570.4" + cell \input$113 \input + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$19 \input_ra$39 + connect \rb \input_rb + connect \rb$20 \input_rb$40 + connect \rc \input_rc + connect \rc$21 \input_rc$41 + connect \sr_op__fn_unit \input_sr_op__fn_unit + connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$23 + connect \sr_op__imm_data__data \input_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$24 + connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$25 + connect \sr_op__input_carry \input_sr_op__input_carry + connect \sr_op__input_carry$12 \input_sr_op__input_carry$32 + connect \sr_op__input_cr \input_sr_op__input_cr + connect \sr_op__input_cr$14 \input_sr_op__input_cr$34 + connect \sr_op__insn \input_sr_op__insn + connect \sr_op__insn$18 \input_sr_op__insn$38 + connect \sr_op__insn_type \input_sr_op__insn_type + connect \sr_op__insn_type$2 \input_sr_op__insn_type$22 + connect \sr_op__invert_in \input_sr_op__invert_in + connect \sr_op__invert_in$11 \input_sr_op__invert_in$31 + connect \sr_op__is_32bit \input_sr_op__is_32bit + connect \sr_op__is_32bit$16 \input_sr_op__is_32bit$36 + connect \sr_op__is_signed \input_sr_op__is_signed + connect \sr_op__is_signed$17 \input_sr_op__is_signed$37 + connect \sr_op__oe__oe \input_sr_op__oe__oe + connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$28 + connect \sr_op__oe__ok \input_sr_op__oe__ok + connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$29 + connect \sr_op__output_carry \input_sr_op__output_carry + connect \sr_op__output_carry$13 \input_sr_op__output_carry$33 + connect \sr_op__output_cr \input_sr_op__output_cr + connect \sr_op__output_cr$15 \input_sr_op__output_cr$35 + connect \sr_op__rc__ok \input_sr_op__rc__ok + connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$27 + connect \sr_op__rc__rc \input_sr_op__rc__rc + connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$26 + connect \sr_op__write_cr0 \input_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$30 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:171793.9-171796.4" - cell \n$4 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:165571.14-165616.4" + cell \main$114 \main + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$44 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \rc \main_rc + connect \sr_op__fn_unit \main_sr_op__fn_unit + connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$46 + connect \sr_op__imm_data__data \main_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$47 + connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$48 + connect \sr_op__input_carry \main_sr_op__input_carry + connect \sr_op__input_carry$12 \main_sr_op__input_carry$55 + connect \sr_op__input_cr \main_sr_op__input_cr + connect \sr_op__input_cr$14 \main_sr_op__input_cr$57 + connect \sr_op__insn \main_sr_op__insn + connect \sr_op__insn$18 \main_sr_op__insn$61 + connect \sr_op__insn_type \main_sr_op__insn_type + connect \sr_op__insn_type$2 \main_sr_op__insn_type$45 + connect \sr_op__invert_in \main_sr_op__invert_in + connect \sr_op__invert_in$11 \main_sr_op__invert_in$54 + connect \sr_op__is_32bit \main_sr_op__is_32bit + connect \sr_op__is_32bit$16 \main_sr_op__is_32bit$59 + connect \sr_op__is_signed \main_sr_op__is_signed + connect \sr_op__is_signed$17 \main_sr_op__is_signed$60 + connect \sr_op__oe__oe \main_sr_op__oe__oe + connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$51 + connect \sr_op__oe__ok \main_sr_op__oe__ok + connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$52 + connect \sr_op__output_carry \main_sr_op__output_carry + connect \sr_op__output_carry$13 \main_sr_op__output_carry$56 + connect \sr_op__output_cr \main_sr_op__output_cr + connect \sr_op__output_cr$15 \main_sr_op__output_cr$58 + connect \sr_op__rc__ok \main_sr_op__rc__ok + connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$50 + connect \sr_op__rc__rc \main_sr_op__rc__rc + connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$49 + connect \sr_op__write_cr0 \main_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$53 + connect \xer_ca \main_xer_ca + connect \xer_so \main_xer_so + connect \xer_so$19 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:171797.12-171852.4" - cell \output \output - connect \alu_op__data_len \output_alu_op__data_len - connect \alu_op__data_len$18 \output_alu_op__data_len$47 - connect \alu_op__fn_unit \output_alu_op__fn_unit - connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 - connect \alu_op__imm_data__data \output_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 - connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 - connect \alu_op__input_carry \output_alu_op__input_carry - connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 - connect \alu_op__insn \output_alu_op__insn - connect \alu_op__insn$19 \output_alu_op__insn$48 - connect \alu_op__insn_type \output_alu_op__insn_type - connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 - connect \alu_op__invert_in \output_alu_op__invert_in - connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 - connect \alu_op__invert_out \output_alu_op__invert_out - connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 - connect \alu_op__is_32bit \output_alu_op__is_32bit - connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 - connect \alu_op__is_signed \output_alu_op__is_signed - connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 - connect \alu_op__oe__oe \output_alu_op__oe__oe - connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 - connect \alu_op__oe__ok \output_alu_op__oe__ok - connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 - connect \alu_op__output_carry \output_alu_op__output_carry - connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 - connect \alu_op__rc__ok \output_alu_op__rc__ok - connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 - connect \alu_op__rc__rc \output_alu_op__rc__rc - connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 - connect \alu_op__write_cr0 \output_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 - connect \alu_op__zero_a \output_alu_op__zero_a - connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 - connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$51 - connect \cr_a_ok \output_cr_a_ok - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$30 - connect \o \output_o - connect \o$20 \output_o$49 - connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$50 - connect \xer_ca \output_xer_ca - connect \xer_ca$23 \output_xer_ca$52 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_ov \output_xer_ov - connect \xer_ov$24 \output_xer_ov$53 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so \output_xer_so - connect \xer_so$25 \output_xer_so$54 - connect \xer_so_ok \output_xer_so_ok + attribute \src "libresoc.v:165617.11-165620.4" + cell \n$112 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:171853.9-171856.4" - cell \p$3 \p + attribute \src "libresoc.v:165621.11-165624.4" + cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:170870.7-170870.20" - process $proc$libresoc.v:170870$9491 + attribute \src "libresoc.v:164381.7-164381.20" + process $proc$libresoc.v:164381$9244 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170877.13-170877.41" - process $proc$libresoc.v:170877$9492 - assign { } { } - assign $0\alu_op__data_len$18[3:0]$9493 4'0000 - sync always - sync init - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9493 - end - attribute \src "libresoc.v:170914.14-170914.44" - process $proc$libresoc.v:170914$9494 - assign { } { } - assign $0\alu_op__fn_unit$3[12:0]$9495 13'0000000000000 - sync always - sync init - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9495 - end - attribute \src "libresoc.v:170937.14-170937.63" - process $proc$libresoc.v:170937$9496 - assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9497 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9497 - end - attribute \src "libresoc.v:170946.7-170946.38" - process $proc$libresoc.v:170946$9498 + attribute \src "libresoc.v:164390.13-164390.24" + process $proc$libresoc.v:164390$9245 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9499 1'0 + assign $1\cr_a[3:0] 4'0000 sync always sync init - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9499 + update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:170963.13-170963.44" - process $proc$libresoc.v:170963$9500 + attribute \src "libresoc.v:164399.7-164399.21" + process $proc$libresoc.v:164399$9246 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9501 2'00 + assign $1\cr_a_ok[0:0] 1'0 sync always sync init - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9501 + update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:170976.14-170976.39" - process $proc$libresoc.v:170976$9502 + attribute \src "libresoc.v:164956.13-164956.25" + process $proc$libresoc.v:164956$9247 assign { } { } - assign $0\alu_op__insn$19[31:0]$9503 0 + assign $1\muxid[1:0] 2'00 sync always sync init - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9503 + update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:171133.13-171133.42" - process $proc$libresoc.v:171133$9504 + attribute \src "libresoc.v:164971.14-164971.38" + process $proc$libresoc.v:164971$9248 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9505 7'0000000 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9505 + update \o $1\o[63:0] end - attribute \src "libresoc.v:171216.7-171216.36" - process $proc$libresoc.v:171216$9506 + attribute \src "libresoc.v:164978.7-164978.18" + process $proc$libresoc.v:164978$9249 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9507 1'0 + assign $1\o_ok[0:0] 1'0 sync always sync init - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9507 + update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:171225.7-171225.37" - process $proc$libresoc.v:171225$9508 + attribute \src "libresoc.v:164992.7-164992.20" + process $proc$libresoc.v:164992$9250 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9509 1'0 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9509 + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:171234.7-171234.35" - process $proc$libresoc.v:171234$9510 + attribute \src "libresoc.v:165017.14-165017.39" + process $proc$libresoc.v:165017$9251 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9511 1'0 + assign $1\sr_op__fn_unit[12:0] 13'0000000000000 sync always sync init - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9511 + update \sr_op__fn_unit $1\sr_op__fn_unit[12:0] end - attribute \src "libresoc.v:171243.7-171243.36" - process $proc$libresoc.v:171243$9512 + attribute \src "libresoc.v:165054.14-165054.58" + process $proc$libresoc.v:165054$9252 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9513 1'0 + assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9513 + update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:171254.7-171254.32" - process $proc$libresoc.v:171254$9514 + attribute \src "libresoc.v:165063.7-165063.33" + process $proc$libresoc.v:165063$9253 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9515 1'0 + assign $1\sr_op__imm_data__ok[0:0] 1'0 sync always sync init - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9515 + update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:171263.7-171263.32" - process $proc$libresoc.v:171263$9516 + attribute \src "libresoc.v:165076.13-165076.38" + process $proc$libresoc.v:165076$9254 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9517 1'0 + assign $1\sr_op__input_carry[1:0] 2'00 sync always sync init - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9517 + update \sr_op__input_carry $1\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:171270.7-171270.39" - process $proc$libresoc.v:171270$9518 + attribute \src "libresoc.v:165093.7-165093.29" + process $proc$libresoc.v:165093$9255 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9519 1'0 + assign $1\sr_op__input_cr[0:0] 1'0 sync always sync init - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9519 + update \sr_op__input_cr $1\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:171281.7-171281.32" - process $proc$libresoc.v:171281$9520 + attribute \src "libresoc.v:165102.14-165102.33" + process $proc$libresoc.v:165102$9256 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9521 1'0 + assign $1\sr_op__insn[31:0] 0 sync always sync init - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9521 + update \sr_op__insn $1\sr_op__insn[31:0] end - attribute \src "libresoc.v:171288.7-171288.32" - process $proc$libresoc.v:171288$9522 + attribute \src "libresoc.v:165185.13-165185.37" + process $proc$libresoc.v:165185$9257 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9523 1'0 + assign $1\sr_op__insn_type[6:0] 7'0000000 sync always sync init - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9523 + update \sr_op__insn_type $1\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:171297.7-171297.36" - process $proc$libresoc.v:171297$9524 + attribute \src "libresoc.v:165342.7-165342.30" + process $proc$libresoc.v:165342$9258 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9525 1'0 + assign $1\sr_op__invert_in[0:0] 1'0 sync always sync init - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9525 + update \sr_op__invert_in $1\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:171306.7-171306.33" - process $proc$libresoc.v:171306$9526 + attribute \src "libresoc.v:165351.7-165351.29" + process $proc$libresoc.v:165351$9259 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9527 1'0 + assign $1\sr_op__is_32bit[0:0] 1'0 sync always sync init - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9527 + update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:171319.13-171319.29" - process $proc$libresoc.v:171319$9528 + attribute \src "libresoc.v:165360.7-165360.30" + process $proc$libresoc.v:165360$9260 assign { } { } - assign $0\cr_a$22[3:0]$9529 4'0000 + assign $1\sr_op__is_signed[0:0] 1'0 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$9529 + update \sr_op__is_signed $1\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:171328.7-171328.26" - process $proc$libresoc.v:171328$9530 + attribute \src "libresoc.v:165369.7-165369.27" + process $proc$libresoc.v:165369$9261 assign { } { } - assign $0\cr_a_ok$23[0:0]$9531 1'0 + assign $1\sr_op__oe__oe[0:0] 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9531 + update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:171339.13-171339.29" - process $proc$libresoc.v:171339$9532 + attribute \src "libresoc.v:165378.7-165378.27" + process $proc$libresoc.v:165378$9262 assign { } { } - assign $0\muxid$1[1:0]$9533 2'00 + assign $1\sr_op__oe__ok[0:0] 1'0 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9533 + update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:171354.14-171354.43" - process $proc$libresoc.v:171354$9534 + attribute \src "libresoc.v:165387.7-165387.33" + process $proc$libresoc.v:165387$9263 assign { } { } - assign $0\o$20[63:0]$9535 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sr_op__output_carry[0:0] 1'0 sync always sync init - update \o$20 $0\o$20[63:0]$9535 + update \sr_op__output_carry $1\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:171363.7-171363.23" - process $proc$libresoc.v:171363$9536 + attribute \src "libresoc.v:165396.7-165396.30" + process $proc$libresoc.v:165396$9264 assign { } { } - assign $0\o_ok$21[0:0]$9537 1'0 + assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$9537 + update \sr_op__output_cr $1\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:171669.7-171669.20" - process $proc$libresoc.v:171669$9538 + attribute \src "libresoc.v:165405.7-165405.27" + process $proc$libresoc.v:165405$9265 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:171676.13-171676.31" - process $proc$libresoc.v:171676$9539 + attribute \src "libresoc.v:165414.7-165414.27" + process $proc$libresoc.v:165414$9266 assign { } { } - assign $0\xer_ca$24[1:0]$9540 2'00 + assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init - update \xer_ca$24 $0\xer_ca$24[1:0]$9540 + update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:171685.7-171685.28" - process $proc$libresoc.v:171685$9541 + attribute \src "libresoc.v:165423.7-165423.30" + process $proc$libresoc.v:165423$9267 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9542 1'0 + assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9542 + update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:171696.13-171696.31" - process $proc$libresoc.v:171696$9543 + attribute \src "libresoc.v:165432.13-165432.26" + process $proc$libresoc.v:165432$9268 assign { } { } - assign $0\xer_ov$26[1:0]$9544 2'00 + assign $1\xer_ca[1:0] 2'00 sync always sync init - update \xer_ov$26 $0\xer_ov$26[1:0]$9544 + update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:171705.7-171705.28" - process $proc$libresoc.v:171705$9545 + attribute \src "libresoc.v:165443.7-165443.23" + process $proc$libresoc.v:165443$9269 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9546 1'0 + assign $1\xer_ca_ok[0:0] 1'0 sync always sync init - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9546 + update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:171716.7-171716.25" - process $proc$libresoc.v:171716$9547 + attribute \src "libresoc.v:165452.7-165452.20" + process $proc$libresoc.v:165452$9270 assign { } { } - assign $0\xer_so$28[0:0]$9548 1'0 + assign $1\xer_so[0:0] 1'0 sync always sync init - update \xer_so$28 $0\xer_so$28[0:0]$9548 + update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:171725.7-171725.28" - process $proc$libresoc.v:171725$9549 + attribute \src "libresoc.v:165461.7-165461.23" + process $proc$libresoc.v:165461$9271 assign { } { } - assign $0\xer_so_ok$29[0:0]$9550 1'0 + assign $1\xer_so_ok[0:0] 1'0 sync always sync init - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9550 - end - attribute \src "libresoc.v:171733.3-171734.37" - process $proc$libresoc.v:171733$9352 - assign { } { } - assign $0\xer_so$28[0:0]$9353 \xer_so$28$next - sync posedge \coresync_clk - update \xer_so$28 $0\xer_so$28[0:0]$9353 - end - attribute \src "libresoc.v:171735.3-171736.43" - process $proc$libresoc.v:171735$9354 - assign { } { } - assign $0\xer_so_ok$29[0:0]$9355 \xer_so_ok$29$next - sync posedge \coresync_clk - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9355 - end - attribute \src "libresoc.v:171737.3-171738.37" - process $proc$libresoc.v:171737$9356 - assign { } { } - assign $0\xer_ov$26[1:0]$9357 \xer_ov$26$next - sync posedge \coresync_clk - update \xer_ov$26 $0\xer_ov$26[1:0]$9357 + update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:171739.3-171740.43" - process $proc$libresoc.v:171739$9358 + attribute \src "libresoc.v:165469.3-165470.29" + process $proc$libresoc.v:165469$9145 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9359 \xer_ov_ok$27$next + assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9359 + update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:171741.3-171742.37" - process $proc$libresoc.v:171741$9360 + attribute \src "libresoc.v:165471.3-165472.35" + process $proc$libresoc.v:165471$9146 assign { } { } - assign $0\xer_ca$24[1:0]$9361 \xer_ca$24$next + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk - update \xer_ca$24 $0\xer_ca$24[1:0]$9361 + update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:171743.3-171744.43" - process $proc$libresoc.v:171743$9362 + attribute \src "libresoc.v:165473.3-165474.29" + process $proc$libresoc.v:165473$9147 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9363 \xer_ca_ok$25$next + assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9363 + update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:171745.3-171746.33" - process $proc$libresoc.v:171745$9364 + attribute \src "libresoc.v:165475.3-165476.35" + process $proc$libresoc.v:165475$9148 assign { } { } - assign $0\cr_a$22[3:0]$9365 \cr_a$22$next + assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$9365 + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:171747.3-171748.39" - process $proc$libresoc.v:171747$9366 + attribute \src "libresoc.v:165477.3-165478.25" + process $proc$libresoc.v:165477$9149 assign { } { } - assign $0\cr_a_ok$23[0:0]$9367 \cr_a_ok$23$next + assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9367 + update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:171749.3-171750.27" - process $proc$libresoc.v:171749$9368 + attribute \src "libresoc.v:165479.3-165480.31" + process $proc$libresoc.v:165479$9150 assign { } { } - assign $0\o$20[63:0]$9369 \o$20$next + assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$9369 + update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:171751.3-171752.33" - process $proc$libresoc.v:171751$9370 + attribute \src "libresoc.v:165481.3-165482.19" + process $proc$libresoc.v:165481$9151 assign { } { } - assign $0\o_ok$21[0:0]$9371 \o_ok$21$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$9371 + update \o $0\o[63:0] end - attribute \src "libresoc.v:171753.3-171754.57" - process $proc$libresoc.v:171753$9372 + attribute \src "libresoc.v:165483.3-165484.25" + process $proc$libresoc.v:165483$9152 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9373 \alu_op__insn_type$2$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9373 + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:171755.3-171756.53" - process $proc$libresoc.v:171755$9374 + attribute \src "libresoc.v:165485.3-165486.49" + process $proc$libresoc.v:165485$9153 assign { } { } - assign $0\alu_op__fn_unit$3[12:0]$9375 \alu_op__fn_unit$3$next + assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next sync posedge \coresync_clk - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9375 + update \sr_op__insn_type $0\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:171757.3-171758.67" - process $proc$libresoc.v:171757$9376 + attribute \src "libresoc.v:165487.3-165488.45" + process $proc$libresoc.v:165487$9154 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9377 \alu_op__imm_data__data$4$next + assign $0\sr_op__fn_unit[12:0] \sr_op__fn_unit$next sync posedge \coresync_clk - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9377 + update \sr_op__fn_unit $0\sr_op__fn_unit[12:0] end - attribute \src "libresoc.v:171759.3-171760.63" - process $proc$libresoc.v:171759$9378 + attribute \src "libresoc.v:165489.3-165490.59" + process $proc$libresoc.v:165489$9155 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9379 \alu_op__imm_data__ok$5$next + assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9379 + update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:171761.3-171762.51" - process $proc$libresoc.v:171761$9380 + attribute \src "libresoc.v:165491.3-165492.55" + process $proc$libresoc.v:165491$9156 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9381 \alu_op__rc__rc$6$next + assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9381 + update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:171763.3-171764.51" - process $proc$libresoc.v:171763$9382 + attribute \src "libresoc.v:165493.3-165494.43" + process $proc$libresoc.v:165493$9157 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9383 \alu_op__rc__ok$7$next + assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9383 + update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:171765.3-171766.51" - process $proc$libresoc.v:171765$9384 + attribute \src "libresoc.v:165495.3-165496.43" + process $proc$libresoc.v:165495$9158 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9385 \alu_op__oe__oe$8$next + assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9385 + update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:171767.3-171768.51" - process $proc$libresoc.v:171767$9386 + attribute \src "libresoc.v:165497.3-165498.43" + process $proc$libresoc.v:165497$9159 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9387 \alu_op__oe__ok$9$next + assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9387 + update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:171769.3-171770.59" - process $proc$libresoc.v:171769$9388 + attribute \src "libresoc.v:165499.3-165500.43" + process $proc$libresoc.v:165499$9160 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9389 \alu_op__invert_in$10$next + assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9389 + update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:171771.3-171772.53" - process $proc$libresoc.v:171771$9390 + attribute \src "libresoc.v:165501.3-165502.49" + process $proc$libresoc.v:165501$9161 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9391 \alu_op__zero_a$11$next + assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9391 + update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:171773.3-171774.61" - process $proc$libresoc.v:171773$9392 + attribute \src "libresoc.v:165503.3-165504.49" + process $proc$libresoc.v:165503$9162 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9393 \alu_op__invert_out$12$next + assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9393 + update \sr_op__invert_in $0\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:171775.3-171776.59" - process $proc$libresoc.v:171775$9394 + attribute \src "libresoc.v:165505.3-165506.53" + process $proc$libresoc.v:165505$9163 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9395 \alu_op__write_cr0$13$next + assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9395 + update \sr_op__input_carry $0\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:171777.3-171778.63" - process $proc$libresoc.v:171777$9396 + attribute \src "libresoc.v:165507.3-165508.55" + process $proc$libresoc.v:165507$9164 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9397 \alu_op__input_carry$14$next + assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9397 + update \sr_op__output_carry $0\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:171779.3-171780.65" - process $proc$libresoc.v:171779$9398 + attribute \src "libresoc.v:165509.3-165510.47" + process $proc$libresoc.v:165509$9165 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9399 \alu_op__output_carry$15$next + assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9399 + update \sr_op__input_cr $0\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:171781.3-171782.57" - process $proc$libresoc.v:171781$9400 + attribute \src "libresoc.v:165511.3-165512.49" + process $proc$libresoc.v:165511$9166 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9401 \alu_op__is_32bit$16$next + assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9401 + update \sr_op__output_cr $0\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:171783.3-171784.59" - process $proc$libresoc.v:171783$9402 + attribute \src "libresoc.v:165513.3-165514.47" + process $proc$libresoc.v:165513$9167 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9403 \alu_op__is_signed$17$next + assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9403 + update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:171785.3-171786.57" - process $proc$libresoc.v:171785$9404 + attribute \src "libresoc.v:165515.3-165516.49" + process $proc$libresoc.v:165515$9168 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9405 \alu_op__data_len$18$next + assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9405 + update \sr_op__is_signed $0\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:171787.3-171788.49" - process $proc$libresoc.v:171787$9406 + attribute \src "libresoc.v:165517.3-165518.39" + process $proc$libresoc.v:165517$9169 assign { } { } - assign $0\alu_op__insn$19[31:0]$9407 \alu_op__insn$19$next + assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9407 + update \sr_op__insn $0\sr_op__insn[31:0] end - attribute \src "libresoc.v:171789.3-171790.33" - process $proc$libresoc.v:171789$9408 + attribute \src "libresoc.v:165519.3-165520.27" + process $proc$libresoc.v:165519$9170 assign { } { } - assign $0\muxid$1[1:0]$9409 \muxid$1$next + assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9409 + update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:171791.3-171792.29" - process $proc$libresoc.v:171791$9410 + attribute \src "libresoc.v:165521.3-165522.29" + process $proc$libresoc.v:165521$9171 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:171857.3-171874.6" - process $proc$libresoc.v:171857$9411 + attribute \src "libresoc.v:165625.3-165643.6" + process $proc$libresoc.v:165625$9172 + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9412 $2\r_busy$next[0:0]$9414 - attribute \src "libresoc.v:171858.5-171858.29" + assign $0\xer_ca$next[1:0]$9174 $1\xer_ca$next[1:0]$9176 + assign $0\xer_ca_ok$next[0:0]$9173 $2\xer_ca_ok$next[0:0]$9177 + attribute \src "libresoc.v:165626.5-165626.29" switch \initial - attribute \src "libresoc.v:171858.9-171858.17" + attribute \src "libresoc.v:165626.9-165626.17" case 1'1 case end @@ -351188,34 +342805,39 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9413 1'1 + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9175 $1\xer_ca$next[1:0]$9176 } { \xer_ca_ok$95 \xer_ca$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9413 1'0 + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9175 $1\xer_ca$next[1:0]$9176 } { \xer_ca_ok$95 \xer_ca$94 } case - assign $1\r_busy$next[0:0]$9413 \r_busy + assign $1\xer_ca_ok$next[0:0]$9175 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9176 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9414 1'0 + assign $2\xer_ca_ok$next[0:0]$9177 1'0 case - assign $2\r_busy$next[0:0]$9414 $1\r_busy$next[0:0]$9413 + assign $2\xer_ca_ok$next[0:0]$9177 $1\xer_ca_ok$next[0:0]$9175 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9412 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9173 + update \xer_ca$next $0\xer_ca$next[1:0]$9174 end - attribute \src "libresoc.v:171875.3-171887.6" - process $proc$libresoc.v:171875$9415 + attribute \src "libresoc.v:165644.3-165661.6" + process $proc$libresoc.v:165644$9178 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9416 $1\muxid$1$next[1:0]$9417 - attribute \src "libresoc.v:171876.5-171876.29" + assign { } { } + assign $0\r_busy$next[0:0]$9179 $2\r_busy$next[0:0]$9181 + attribute \src "libresoc.v:165645.5-165645.29" switch \initial - attribute \src "libresoc.v:171876.9-171876.17" + attribute \src "libresoc.v:165645.9-165645.17" case 1'1 case end @@ -351224,21 +342846,55 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9417 \muxid$62 + assign $1\r_busy$next[0:0]$9180 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9417 \muxid$62 + assign $1\r_busy$next[0:0]$9180 1'0 + case + assign $1\r_busy$next[0:0]$9180 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9181 1'0 case - assign $1\muxid$1$next[1:0]$9417 \muxid$1 + assign $2\r_busy$next[0:0]$9181 $1\r_busy$next[0:0]$9180 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9416 + update \r_busy$next $0\r_busy$next[0:0]$9179 end - attribute \src "libresoc.v:171888.3-171929.6" - process $proc$libresoc.v:171888$9418 + attribute \src "libresoc.v:165662.3-165674.6" + process $proc$libresoc.v:165662$9182 assign { } { } assign { } { } + assign $0\muxid$next[1:0]$9183 $1\muxid$next[1:0]$9184 + attribute \src "libresoc.v:165663.5-165663.29" + switch \initial + attribute \src "libresoc.v:165663.9-165663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9184 \muxid$67 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9184 \muxid$67 + case + assign $1\muxid$next[1:0]$9184 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9183 + end + attribute \src "libresoc.v:165675.3-165715.6" + process $proc$libresoc.v:165675$9185 assign { } { } assign { } { } assign { } { } @@ -351273,33 +342929,32 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$18$next[3:0]$9419 $1\alu_op__data_len$18$next[3:0]$9437 - assign $0\alu_op__fn_unit$3$next[12:0]$9420 $1\alu_op__fn_unit$3$next[12:0]$9438 + assign $0\sr_op__fn_unit$next[12:0]$9186 $1\sr_op__fn_unit$next[12:0]$9203 assign { } { } assign { } { } - assign $0\alu_op__input_carry$14$next[1:0]$9423 $1\alu_op__input_carry$14$next[1:0]$9441 - assign $0\alu_op__insn$19$next[31:0]$9424 $1\alu_op__insn$19$next[31:0]$9442 - assign $0\alu_op__insn_type$2$next[6:0]$9425 $1\alu_op__insn_type$2$next[6:0]$9443 - assign $0\alu_op__invert_in$10$next[0:0]$9426 $1\alu_op__invert_in$10$next[0:0]$9444 - assign $0\alu_op__invert_out$12$next[0:0]$9427 $1\alu_op__invert_out$12$next[0:0]$9445 - assign $0\alu_op__is_32bit$16$next[0:0]$9428 $1\alu_op__is_32bit$16$next[0:0]$9446 - assign $0\alu_op__is_signed$17$next[0:0]$9429 $1\alu_op__is_signed$17$next[0:0]$9447 + assign $0\sr_op__input_carry$next[1:0]$9189 $1\sr_op__input_carry$next[1:0]$9206 + assign $0\sr_op__input_cr$next[0:0]$9190 $1\sr_op__input_cr$next[0:0]$9207 + assign $0\sr_op__insn$next[31:0]$9191 $1\sr_op__insn$next[31:0]$9208 + assign $0\sr_op__insn_type$next[6:0]$9192 $1\sr_op__insn_type$next[6:0]$9209 + assign $0\sr_op__invert_in$next[0:0]$9193 $1\sr_op__invert_in$next[0:0]$9210 + assign $0\sr_op__is_32bit$next[0:0]$9194 $1\sr_op__is_32bit$next[0:0]$9211 + assign $0\sr_op__is_signed$next[0:0]$9195 $1\sr_op__is_signed$next[0:0]$9212 assign { } { } assign { } { } - assign $0\alu_op__output_carry$15$next[0:0]$9432 $1\alu_op__output_carry$15$next[0:0]$9450 + assign $0\sr_op__output_carry$next[0:0]$9198 $1\sr_op__output_carry$next[0:0]$9215 + assign $0\sr_op__output_cr$next[0:0]$9199 $1\sr_op__output_cr$next[0:0]$9216 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$13$next[0:0]$9435 $1\alu_op__write_cr0$13$next[0:0]$9453 - assign $0\alu_op__zero_a$11$next[0:0]$9436 $1\alu_op__zero_a$11$next[0:0]$9454 - assign $0\alu_op__imm_data__data$4$next[63:0]$9421 $2\alu_op__imm_data__data$4$next[63:0]$9455 - assign $0\alu_op__imm_data__ok$5$next[0:0]$9422 $2\alu_op__imm_data__ok$5$next[0:0]$9456 - assign $0\alu_op__oe__oe$8$next[0:0]$9430 $2\alu_op__oe__oe$8$next[0:0]$9457 - assign $0\alu_op__oe__ok$9$next[0:0]$9431 $2\alu_op__oe__ok$9$next[0:0]$9458 - assign $0\alu_op__rc__ok$7$next[0:0]$9433 $2\alu_op__rc__ok$7$next[0:0]$9459 - assign $0\alu_op__rc__rc$6$next[0:0]$9434 $2\alu_op__rc__rc$6$next[0:0]$9460 - attribute \src "libresoc.v:171889.5-171889.29" + assign $0\sr_op__write_cr0$next[0:0]$9202 $1\sr_op__write_cr0$next[0:0]$9219 + assign $0\sr_op__imm_data__data$next[63:0]$9187 $2\sr_op__imm_data__data$next[63:0]$9220 + assign $0\sr_op__imm_data__ok$next[0:0]$9188 $2\sr_op__imm_data__ok$next[0:0]$9221 + assign $0\sr_op__oe__oe$next[0:0]$9196 $2\sr_op__oe__oe$next[0:0]$9222 + assign $0\sr_op__oe__ok$next[0:0]$9197 $2\sr_op__oe__ok$next[0:0]$9223 + assign $0\sr_op__rc__ok$next[0:0]$9200 $2\sr_op__rc__ok$next[0:0]$9224 + assign $0\sr_op__rc__rc$next[0:0]$9201 $2\sr_op__rc__rc$next[0:0]$9225 + attribute \src "libresoc.v:165676.5-165676.29" switch \initial - attribute \src "libresoc.v:171889.9-171889.17" + attribute \src "libresoc.v:165676.9-165676.17" case 1'1 case end @@ -351324,8 +342979,7 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9442 $1\alu_op__data_len$18$next[3:0]$9437 $1\alu_op__is_signed$17$next[0:0]$9447 $1\alu_op__is_32bit$16$next[0:0]$9446 $1\alu_op__output_carry$15$next[0:0]$9450 $1\alu_op__input_carry$14$next[1:0]$9441 $1\alu_op__write_cr0$13$next[0:0]$9453 $1\alu_op__invert_out$12$next[0:0]$9445 $1\alu_op__zero_a$11$next[0:0]$9454 $1\alu_op__invert_in$10$next[0:0]$9444 $1\alu_op__oe__ok$9$next[0:0]$9449 $1\alu_op__oe__oe$8$next[0:0]$9448 $1\alu_op__rc__ok$7$next[0:0]$9451 $1\alu_op__rc__rc$6$next[0:0]$9452 $1\alu_op__imm_data__ok$5$next[0:0]$9440 $1\alu_op__imm_data__data$4$next[63:0]$9439 $1\alu_op__fn_unit$3$next[12:0]$9438 $1\alu_op__insn_type$2$next[6:0]$9443 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\sr_op__insn$next[31:0]$9208 $1\sr_op__is_signed$next[0:0]$9212 $1\sr_op__is_32bit$next[0:0]$9211 $1\sr_op__output_cr$next[0:0]$9216 $1\sr_op__input_cr$next[0:0]$9207 $1\sr_op__output_carry$next[0:0]$9215 $1\sr_op__input_carry$next[1:0]$9206 $1\sr_op__invert_in$next[0:0]$9210 $1\sr_op__write_cr0$next[0:0]$9219 $1\sr_op__oe__ok$next[0:0]$9214 $1\sr_op__oe__oe$next[0:0]$9213 $1\sr_op__rc__ok$next[0:0]$9217 $1\sr_op__rc__rc$next[0:0]$9218 $1\sr_op__imm_data__ok$next[0:0]$9205 $1\sr_op__imm_data__data$next[63:0]$9204 $1\sr_op__fn_unit$next[12:0]$9203 $1\sr_op__insn_type$next[6:0]$9209 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -351345,172 +342999,81 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9442 $1\alu_op__data_len$18$next[3:0]$9437 $1\alu_op__is_signed$17$next[0:0]$9447 $1\alu_op__is_32bit$16$next[0:0]$9446 $1\alu_op__output_carry$15$next[0:0]$9450 $1\alu_op__input_carry$14$next[1:0]$9441 $1\alu_op__write_cr0$13$next[0:0]$9453 $1\alu_op__invert_out$12$next[0:0]$9445 $1\alu_op__zero_a$11$next[0:0]$9454 $1\alu_op__invert_in$10$next[0:0]$9444 $1\alu_op__oe__ok$9$next[0:0]$9449 $1\alu_op__oe__oe$8$next[0:0]$9448 $1\alu_op__rc__ok$7$next[0:0]$9451 $1\alu_op__rc__rc$6$next[0:0]$9452 $1\alu_op__imm_data__ok$5$next[0:0]$9440 $1\alu_op__imm_data__data$4$next[63:0]$9439 $1\alu_op__fn_unit$3$next[12:0]$9438 $1\alu_op__insn_type$2$next[6:0]$9443 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } - case - assign $1\alu_op__data_len$18$next[3:0]$9437 \alu_op__data_len$18 - assign $1\alu_op__fn_unit$3$next[12:0]$9438 \alu_op__fn_unit$3 - assign $1\alu_op__imm_data__data$4$next[63:0]$9439 \alu_op__imm_data__data$4 - assign $1\alu_op__imm_data__ok$5$next[0:0]$9440 \alu_op__imm_data__ok$5 - assign $1\alu_op__input_carry$14$next[1:0]$9441 \alu_op__input_carry$14 - assign $1\alu_op__insn$19$next[31:0]$9442 \alu_op__insn$19 - assign $1\alu_op__insn_type$2$next[6:0]$9443 \alu_op__insn_type$2 - assign $1\alu_op__invert_in$10$next[0:0]$9444 \alu_op__invert_in$10 - assign $1\alu_op__invert_out$12$next[0:0]$9445 \alu_op__invert_out$12 - assign $1\alu_op__is_32bit$16$next[0:0]$9446 \alu_op__is_32bit$16 - assign $1\alu_op__is_signed$17$next[0:0]$9447 \alu_op__is_signed$17 - assign $1\alu_op__oe__oe$8$next[0:0]$9448 \alu_op__oe__oe$8 - assign $1\alu_op__oe__ok$9$next[0:0]$9449 \alu_op__oe__ok$9 - assign $1\alu_op__output_carry$15$next[0:0]$9450 \alu_op__output_carry$15 - assign $1\alu_op__rc__ok$7$next[0:0]$9451 \alu_op__rc__ok$7 - assign $1\alu_op__rc__rc$6$next[0:0]$9452 \alu_op__rc__rc$6 - assign $1\alu_op__write_cr0$13$next[0:0]$9453 \alu_op__write_cr0$13 - assign $1\alu_op__zero_a$11$next[0:0]$9454 \alu_op__zero_a$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_op__imm_data__data$4$next[63:0]$9455 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9456 1'0 - assign $2\alu_op__rc__rc$6$next[0:0]$9460 1'0 - assign $2\alu_op__rc__ok$7$next[0:0]$9459 1'0 - assign $2\alu_op__oe__oe$8$next[0:0]$9457 1'0 - assign $2\alu_op__oe__ok$9$next[0:0]$9458 1'0 - case - assign $2\alu_op__imm_data__data$4$next[63:0]$9455 $1\alu_op__imm_data__data$4$next[63:0]$9439 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9456 $1\alu_op__imm_data__ok$5$next[0:0]$9440 - assign $2\alu_op__oe__oe$8$next[0:0]$9457 $1\alu_op__oe__oe$8$next[0:0]$9448 - assign $2\alu_op__oe__ok$9$next[0:0]$9458 $1\alu_op__oe__ok$9$next[0:0]$9449 - assign $2\alu_op__rc__ok$7$next[0:0]$9459 $1\alu_op__rc__ok$7$next[0:0]$9451 - assign $2\alu_op__rc__rc$6$next[0:0]$9460 $1\alu_op__rc__rc$6$next[0:0]$9452 - end - sync always - update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9419 - update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[12:0]$9420 - update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9421 - update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9422 - update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9423 - update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9424 - update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9425 - update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9426 - update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9427 - update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9428 - update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9429 - update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9430 - update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9431 - update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9432 - update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9433 - update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9434 - update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9435 - update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9436 - end - attribute \src "libresoc.v:171930.3-171948.6" - process $proc$libresoc.v:171930$9461 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$20$next[63:0]$9462 $1\o$20$next[63:0]$9464 - assign { } { } - assign $0\o_ok$21$next[0:0]$9463 $2\o_ok$21$next[0:0]$9466 - attribute \src "libresoc.v:171931.5-171931.29" - switch \initial - attribute \src "libresoc.v:171931.9-171931.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$9465 $1\o$20$next[63:0]$9464 } { \o_ok$82 \o$81 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$9465 $1\o$20$next[63:0]$9464 } { \o_ok$82 \o$81 } + assign { $1\sr_op__insn$next[31:0]$9208 $1\sr_op__is_signed$next[0:0]$9212 $1\sr_op__is_32bit$next[0:0]$9211 $1\sr_op__output_cr$next[0:0]$9216 $1\sr_op__input_cr$next[0:0]$9207 $1\sr_op__output_carry$next[0:0]$9215 $1\sr_op__input_carry$next[1:0]$9206 $1\sr_op__invert_in$next[0:0]$9210 $1\sr_op__write_cr0$next[0:0]$9219 $1\sr_op__oe__ok$next[0:0]$9214 $1\sr_op__oe__oe$next[0:0]$9213 $1\sr_op__rc__ok$next[0:0]$9217 $1\sr_op__rc__rc$next[0:0]$9218 $1\sr_op__imm_data__ok$next[0:0]$9205 $1\sr_op__imm_data__data$next[63:0]$9204 $1\sr_op__fn_unit$next[12:0]$9203 $1\sr_op__insn_type$next[6:0]$9209 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } case - assign $1\o$20$next[63:0]$9464 \o$20 - assign $1\o_ok$21$next[0:0]$9465 \o_ok$21 + assign $1\sr_op__fn_unit$next[12:0]$9203 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$9204 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$9205 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$9206 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$9207 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$9208 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$9209 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$9210 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$9211 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$9212 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$9213 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$9214 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$9215 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$9216 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$9217 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$9218 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$9219 \sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$9466 1'0 - case - assign $2\o_ok$21$next[0:0]$9466 $1\o_ok$21$next[0:0]$9465 - end - sync always - update \o$20$next $0\o$20$next[63:0]$9462 - update \o_ok$21$next $0\o_ok$21$next[0:0]$9463 - end - attribute \src "libresoc.v:171949.3-171967.6" - process $proc$libresoc.v:171949$9467 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$22$next[3:0]$9468 $1\cr_a$22$next[3:0]$9470 - assign { } { } - assign $0\cr_a_ok$23$next[0:0]$9469 $2\cr_a_ok$23$next[0:0]$9472 - attribute \src "libresoc.v:171950.5-171950.29" - switch \initial - attribute \src "libresoc.v:171950.9-171950.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9471 $1\cr_a$22$next[3:0]$9470 } { \cr_a_ok$84 \cr_a$83 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9471 $1\cr_a$22$next[3:0]$9470 } { \cr_a_ok$84 \cr_a$83 } - case - assign $1\cr_a$22$next[3:0]$9470 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$9471 \cr_a_ok$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$9472 1'0 + assign $2\sr_op__imm_data__data$next[63:0]$9220 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$9221 1'0 + assign $2\sr_op__rc__rc$next[0:0]$9225 1'0 + assign $2\sr_op__rc__ok$next[0:0]$9224 1'0 + assign $2\sr_op__oe__oe$next[0:0]$9222 1'0 + assign $2\sr_op__oe__ok$next[0:0]$9223 1'0 case - assign $2\cr_a_ok$23$next[0:0]$9472 $1\cr_a_ok$23$next[0:0]$9471 + assign $2\sr_op__imm_data__data$next[63:0]$9220 $1\sr_op__imm_data__data$next[63:0]$9204 + assign $2\sr_op__imm_data__ok$next[0:0]$9221 $1\sr_op__imm_data__ok$next[0:0]$9205 + assign $2\sr_op__oe__oe$next[0:0]$9222 $1\sr_op__oe__oe$next[0:0]$9213 + assign $2\sr_op__oe__ok$next[0:0]$9223 $1\sr_op__oe__ok$next[0:0]$9214 + assign $2\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__ok$next[0:0]$9217 + assign $2\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__rc__rc$next[0:0]$9218 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$9468 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9469 + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[12:0]$9186 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9187 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9188 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9189 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9190 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9191 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9192 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9193 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9194 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9195 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9196 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9197 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9198 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9199 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9200 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9201 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9202 end - attribute \src "libresoc.v:171968.3-171986.6" - process $proc$libresoc.v:171968$9473 + attribute \src "libresoc.v:165716.3-165734.6" + process $proc$libresoc.v:165716$9226 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$24$next[1:0]$9474 $1\xer_ca$24$next[1:0]$9476 + assign $0\o$next[63:0]$9227 $1\o$next[63:0]$9229 assign { } { } - assign $0\xer_ca_ok$25$next[0:0]$9475 $2\xer_ca_ok$25$next[0:0]$9478 - attribute \src "libresoc.v:171969.5-171969.29" + assign $0\o_ok$next[0:0]$9228 $2\o_ok$next[0:0]$9231 + attribute \src "libresoc.v:165717.5-165717.29" switch \initial - attribute \src "libresoc.v:171969.9-171969.17" + attribute \src "libresoc.v:165717.9-165717.17" case 1'1 case end @@ -351520,41 +343083,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9477 $1\xer_ca$24$next[1:0]$9476 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\o_ok$next[0:0]$9230 $1\o$next[63:0]$9229 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9477 $1\xer_ca$24$next[1:0]$9476 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\o_ok$next[0:0]$9230 $1\o$next[63:0]$9229 } { \o_ok$86 \o$85 } case - assign $1\xer_ca$24$next[1:0]$9476 \xer_ca$24 - assign $1\xer_ca_ok$25$next[0:0]$9477 \xer_ca_ok$25 + assign $1\o$next[63:0]$9229 \o + assign $1\o_ok$next[0:0]$9230 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$25$next[0:0]$9478 1'0 + assign $2\o_ok$next[0:0]$9231 1'0 case - assign $2\xer_ca_ok$25$next[0:0]$9478 $1\xer_ca_ok$25$next[0:0]$9477 + assign $2\o_ok$next[0:0]$9231 $1\o_ok$next[0:0]$9230 end sync always - update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9474 - update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9475 + update \o$next $0\o$next[63:0]$9227 + update \o_ok$next $0\o_ok$next[0:0]$9228 end - attribute \src "libresoc.v:171987.3-172005.6" - process $proc$libresoc.v:171987$9479 + attribute \src "libresoc.v:165735.3-165753.6" + process $proc$libresoc.v:165735$9232 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$26$next[1:0]$9480 $1\xer_ov$26$next[1:0]$9482 + assign $0\cr_a$next[3:0]$9233 $1\cr_a$next[3:0]$9235 assign { } { } - assign $0\xer_ov_ok$27$next[0:0]$9481 $2\xer_ov_ok$27$next[0:0]$9484 - attribute \src "libresoc.v:171988.5-171988.29" + assign $0\cr_a_ok$next[0:0]$9234 $2\cr_a_ok$next[0:0]$9237 + attribute \src "libresoc.v:165736.5-165736.29" switch \initial - attribute \src "libresoc.v:171988.9-171988.17" + attribute \src "libresoc.v:165736.9-165736.17" case 1'1 case end @@ -351564,41 +343127,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9483 $1\xer_ov$26$next[1:0]$9482 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\cr_a_ok$next[0:0]$9236 $1\cr_a$next[3:0]$9235 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9483 $1\xer_ov$26$next[1:0]$9482 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\cr_a_ok$next[0:0]$9236 $1\cr_a$next[3:0]$9235 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\xer_ov$26$next[1:0]$9482 \xer_ov$26 - assign $1\xer_ov_ok$27$next[0:0]$9483 \xer_ov_ok$27 + assign $1\cr_a$next[3:0]$9235 \cr_a + assign $1\cr_a_ok$next[0:0]$9236 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$27$next[0:0]$9484 1'0 + assign $2\cr_a_ok$next[0:0]$9237 1'0 case - assign $2\xer_ov_ok$27$next[0:0]$9484 $1\xer_ov_ok$27$next[0:0]$9483 + assign $2\cr_a_ok$next[0:0]$9237 $1\cr_a_ok$next[0:0]$9236 end sync always - update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9480 - update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9481 + update \cr_a$next $0\cr_a$next[3:0]$9233 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9234 end - attribute \src "libresoc.v:172006.3-172024.6" - process $proc$libresoc.v:172006$9485 + attribute \src "libresoc.v:165754.3-165772.6" + process $proc$libresoc.v:165754$9238 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$28$next[0:0]$9486 $1\xer_so$28$next[0:0]$9488 + assign $0\xer_so$next[0:0]$9239 $1\xer_so$next[0:0]$9241 assign { } { } - assign $0\xer_so_ok$29$next[0:0]$9487 $2\xer_so_ok$29$next[0:0]$9490 - attribute \src "libresoc.v:172007.5-172007.29" + assign $0\xer_so_ok$next[0:0]$9240 $2\xer_so_ok$next[0:0]$9243 + attribute \src "libresoc.v:165755.5-165755.29" switch \initial - attribute \src "libresoc.v:172007.9-172007.17" + attribute \src "libresoc.v:165755.9-165755.17" case 1'1 case end @@ -351608,353 +343171,221 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9489 $1\xer_so$28$next[0:0]$9488 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$next[0:0]$9242 $1\xer_so$next[0:0]$9241 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9489 $1\xer_so$28$next[0:0]$9488 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$next[0:0]$9242 $1\xer_so$next[0:0]$9241 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$28$next[0:0]$9488 \xer_so$28 - assign $1\xer_so_ok$29$next[0:0]$9489 \xer_so_ok$29 + assign $1\xer_so$next[0:0]$9241 \xer_so + assign $1\xer_so_ok$next[0:0]$9242 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$29$next[0:0]$9490 1'0 + assign $2\xer_so_ok$next[0:0]$9243 1'0 case - assign $2\xer_so_ok$29$next[0:0]$9490 $1\xer_so_ok$29$next[0:0]$9489 + assign $2\xer_so_ok$next[0:0]$9243 $1\xer_so_ok$next[0:0]$9242 end sync always - update \xer_so$28$next $0\xer_so$28$next[0:0]$9486 - update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9487 + update \xer_so$next $0\xer_so$next[0:0]$9239 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9240 end - connect \$60 $and$libresoc.v:171732$9351_Y + connect \$65 $and$libresoc.v:165468$9144_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \xer_ca_ok$96 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } - connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } - connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } - connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } - connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } - connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } - connect \muxid$62 \output_muxid$30 - connect \p_valid_i_p_ready_o \$60 + connect { \xer_ca_ok$95 \xer_ca$94 } { 1'0 \main_xer_ca } + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } { \main_sr_op__insn$61 \main_sr_op__is_signed$60 \main_sr_op__is_32bit$59 \main_sr_op__output_cr$58 \main_sr_op__input_cr$57 \main_sr_op__output_carry$56 \main_sr_op__input_carry$55 \main_sr_op__invert_in$54 \main_sr_op__write_cr0$53 \main_sr_op__oe__ok$52 \main_sr_op__oe__oe$51 \main_sr_op__rc__ok$50 \main_sr_op__rc__rc$49 \main_sr_op__imm_data__ok$48 \main_sr_op__imm_data__data$47 \main_sr_op__fn_unit$46 \main_sr_op__insn_type$45 } + connect \muxid$67 \main_muxid$44 + connect \p_valid_i_p_ready_o \$65 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$59 \p_valid_i - connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } - connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } - connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } - connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \output_muxid \muxid + connect \p_valid_i$64 \p_valid_i + connect \xer_ca$63 \input_xer_ca$43 + connect \main_xer_so \input_xer_so$42 + connect \main_rc \input_rc$41 + connect \main_rb \input_rb$40 + connect \main_ra \input_ra$39 + connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__invert_in \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$38 \input_sr_op__is_signed$37 \input_sr_op__is_32bit$36 \input_sr_op__output_cr$35 \input_sr_op__input_cr$34 \input_sr_op__output_carry$33 \input_sr_op__input_carry$32 \input_sr_op__invert_in$31 \input_sr_op__write_cr0$30 \input_sr_op__oe__ok$29 \input_sr_op__oe__oe$28 \input_sr_op__rc__ok$27 \input_sr_op__rc__rc$26 \input_sr_op__imm_data__ok$25 \input_sr_op__imm_data__data$24 \input_sr_op__fn_unit$23 \input_sr_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_ca \xer_ca$20 + connect \input_xer_so \xer_so$19 + connect \input_rc \rc + connect \input_rb \rb + connect \input_ra \ra + connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } + connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:172048.1-173107.10" +attribute \src "libresoc.v:165806.1-166644.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" -module \pipe2$115 - attribute \src "libresoc.v:173053.3-173071.6" - wire width 4 $0\cr_a$21$next[3:0]$9656 - attribute \src "libresoc.v:172859.3-172860.33" - wire width 4 $0\cr_a$21[3:0]$9557 - attribute \src "libresoc.v:172060.13-172060.29" - wire width 4 $0\cr_a$21[3:0]$9669 - attribute \src "libresoc.v:173053.3-173071.6" - wire $0\cr_a_ok$22$next[0:0]$9657 - attribute \src "libresoc.v:172861.3-172862.39" - wire $0\cr_a_ok$22[0:0]$9559 - attribute \src "libresoc.v:172069.7-172069.26" - wire $0\cr_a_ok$22[0:0]$9671 - attribute \src "libresoc.v:172049.7-172049.20" +module \pipe1$32 + attribute \src "libresoc.v:166601.3-166613.6" + wire width 64 $0\fast1$next[63:0]$9321 + attribute \src "libresoc.v:166457.3-166458.27" + wire width 64 $0\fast1[63:0] + attribute \src "libresoc.v:166614.3-166626.6" + wire width 64 $0\fast2$next[63:0]$9324 + attribute \src "libresoc.v:166455.3-166456.27" + wire width 64 $0\fast2[63:0] + attribute \src "libresoc.v:165807.7-165807.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172980.3-172992.6" - wire width 2 $0\muxid$1$next[1:0]$9606 - attribute \src "libresoc.v:172901.3-172902.33" - wire width 2 $0\muxid$1[1:0]$9599 - attribute \src "libresoc.v:172080.13-172080.29" - wire width 2 $0\muxid$1[1:0]$9673 - attribute \src "libresoc.v:173034.3-173052.6" - wire width 64 $0\o$19$next[63:0]$9650 - attribute \src "libresoc.v:172863.3-172864.27" - wire width 64 $0\o$19[63:0]$9561 - attribute \src "libresoc.v:172095.14-172095.43" - wire width 64 $0\o$19[63:0]$9675 - attribute \src "libresoc.v:173034.3-173052.6" - wire $0\o_ok$20$next[0:0]$9651 - attribute \src "libresoc.v:172865.3-172866.33" - wire $0\o_ok$20[0:0]$9563 - attribute \src "libresoc.v:172104.7-172104.23" - wire $0\o_ok$20[0:0]$9677 - attribute \src "libresoc.v:172962.3-172979.6" - wire $0\r_busy$next[0:0]$9602 - attribute \src "libresoc.v:172903.3-172904.29" + attribute \src "libresoc.v:166541.3-166553.6" + wire width 2 $0\muxid$next[1:0]$9293 + attribute \src "libresoc.v:166481.3-166482.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:166523.3-166540.6" + wire $0\r_busy$next[0:0]$9289 + attribute \src "libresoc.v:166483.3-166484.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:172993.3-173033.6" - wire width 13 $0\sr_op__fn_unit$3$next[12:0]$9609 - attribute \src "libresoc.v:172869.3-172870.51" - wire width 13 $0\sr_op__fn_unit$3[12:0]$9567 - attribute \src "libresoc.v:172431.14-172431.43" - wire width 13 $0\sr_op__fn_unit$3[12:0]$9680 - attribute \src "libresoc.v:172993.3-173033.6" - wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9610 - attribute \src "libresoc.v:172871.3-172872.65" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9569 - attribute \src "libresoc.v:172454.14-172454.62" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9682 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__imm_data__ok$5$next[0:0]$9611 - attribute \src "libresoc.v:172873.3-172874.61" - wire $0\sr_op__imm_data__ok$5[0:0]$9571 - attribute \src "libresoc.v:172463.7-172463.37" - wire $0\sr_op__imm_data__ok$5[0:0]$9684 - attribute \src "libresoc.v:172993.3-173033.6" - wire width 2 $0\sr_op__input_carry$12$next[1:0]$9612 - attribute \src "libresoc.v:172887.3-172888.61" - wire width 2 $0\sr_op__input_carry$12[1:0]$9585 - attribute \src "libresoc.v:172480.13-172480.43" - wire width 2 $0\sr_op__input_carry$12[1:0]$9686 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__input_cr$14$next[0:0]$9613 - attribute \src "libresoc.v:172891.3-172892.55" - wire $0\sr_op__input_cr$14[0:0]$9589 - attribute \src "libresoc.v:172493.7-172493.34" - wire $0\sr_op__input_cr$14[0:0]$9688 - attribute \src "libresoc.v:172993.3-173033.6" - wire width 32 $0\sr_op__insn$18$next[31:0]$9614 - attribute \src "libresoc.v:172899.3-172900.47" - wire width 32 $0\sr_op__insn$18[31:0]$9597 - attribute \src "libresoc.v:172502.14-172502.38" - wire width 32 $0\sr_op__insn$18[31:0]$9690 - attribute \src "libresoc.v:172993.3-173033.6" - wire width 7 $0\sr_op__insn_type$2$next[6:0]$9615 - attribute \src "libresoc.v:172867.3-172868.55" - wire width 7 $0\sr_op__insn_type$2[6:0]$9565 - attribute \src "libresoc.v:172659.13-172659.41" - wire width 7 $0\sr_op__insn_type$2[6:0]$9692 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__invert_in$11$next[0:0]$9616 - attribute \src "libresoc.v:172885.3-172886.57" - wire $0\sr_op__invert_in$11[0:0]$9583 - attribute \src "libresoc.v:172742.7-172742.35" - wire $0\sr_op__invert_in$11[0:0]$9694 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__is_32bit$16$next[0:0]$9617 - attribute \src "libresoc.v:172895.3-172896.55" - wire $0\sr_op__is_32bit$16[0:0]$9593 - attribute \src "libresoc.v:172751.7-172751.34" - wire $0\sr_op__is_32bit$16[0:0]$9696 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__is_signed$17$next[0:0]$9618 - attribute \src "libresoc.v:172897.3-172898.57" - wire $0\sr_op__is_signed$17[0:0]$9595 - attribute \src "libresoc.v:172760.7-172760.35" - wire $0\sr_op__is_signed$17[0:0]$9698 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__oe__oe$8$next[0:0]$9619 - attribute \src "libresoc.v:172879.3-172880.49" - wire $0\sr_op__oe__oe$8[0:0]$9577 - attribute \src "libresoc.v:172771.7-172771.31" - wire $0\sr_op__oe__oe$8[0:0]$9700 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__oe__ok$9$next[0:0]$9620 - attribute \src "libresoc.v:172881.3-172882.49" - wire $0\sr_op__oe__ok$9[0:0]$9579 - attribute \src "libresoc.v:172780.7-172780.31" - wire $0\sr_op__oe__ok$9[0:0]$9702 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__output_carry$13$next[0:0]$9621 - attribute \src "libresoc.v:172889.3-172890.63" - wire $0\sr_op__output_carry$13[0:0]$9587 - attribute \src "libresoc.v:172787.7-172787.38" - wire $0\sr_op__output_carry$13[0:0]$9704 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__output_cr$15$next[0:0]$9622 - attribute \src "libresoc.v:172893.3-172894.57" - wire $0\sr_op__output_cr$15[0:0]$9591 - attribute \src "libresoc.v:172796.7-172796.35" - wire $0\sr_op__output_cr$15[0:0]$9706 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__rc__ok$7$next[0:0]$9623 - attribute \src "libresoc.v:172877.3-172878.49" - wire $0\sr_op__rc__ok$7[0:0]$9575 - attribute \src "libresoc.v:172807.7-172807.31" - wire $0\sr_op__rc__ok$7[0:0]$9708 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__rc__rc$6$next[0:0]$9624 - attribute \src "libresoc.v:172875.3-172876.49" - wire $0\sr_op__rc__rc$6[0:0]$9573 - attribute \src "libresoc.v:172816.7-172816.31" - wire $0\sr_op__rc__rc$6[0:0]$9710 - attribute \src "libresoc.v:172993.3-173033.6" - wire $0\sr_op__write_cr0$10$next[0:0]$9625 - attribute \src "libresoc.v:172883.3-172884.57" - wire $0\sr_op__write_cr0$10[0:0]$9581 - attribute \src "libresoc.v:172823.7-172823.35" - wire $0\sr_op__write_cr0$10[0:0]$9712 - attribute \src "libresoc.v:173072.3-173090.6" - wire width 2 $0\xer_ca$23$next[1:0]$9662 - attribute \src "libresoc.v:172855.3-172856.37" - wire width 2 $0\xer_ca$23[1:0]$9553 - attribute \src "libresoc.v:172832.13-172832.31" - wire width 2 $0\xer_ca$23[1:0]$9714 - attribute \src "libresoc.v:173072.3-173090.6" - wire $0\xer_ca_ok$24$next[0:0]$9663 - attribute \src "libresoc.v:172857.3-172858.43" - wire $0\xer_ca_ok$24[0:0]$9555 - attribute \src "libresoc.v:172841.7-172841.28" - wire $0\xer_ca_ok$24[0:0]$9716 - attribute \src "libresoc.v:173053.3-173071.6" - wire width 4 $1\cr_a$21$next[3:0]$9658 - attribute \src "libresoc.v:173053.3-173071.6" - wire $1\cr_a_ok$22$next[0:0]$9659 - attribute \src "libresoc.v:172980.3-172992.6" - wire width 2 $1\muxid$1$next[1:0]$9607 - attribute \src "libresoc.v:173034.3-173052.6" - wire width 64 $1\o$19$next[63:0]$9652 - attribute \src "libresoc.v:173034.3-173052.6" - wire $1\o_ok$20$next[0:0]$9653 - attribute \src "libresoc.v:172962.3-172979.6" - wire $1\r_busy$next[0:0]$9603 - attribute \src "libresoc.v:172396.7-172396.20" + attribute \src "libresoc.v:166575.3-166587.6" + wire width 64 $0\ra$next[63:0]$9315 + attribute \src "libresoc.v:166461.3-166462.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:166588.3-166600.6" + wire width 64 $0\rb$next[63:0]$9318 + attribute \src "libresoc.v:166459.3-166460.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 64 $0\trap_op__cia$next[63:0]$9296 + attribute \src "libresoc.v:166471.3-166472.41" + wire width 64 $0\trap_op__cia[63:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 13 $0\trap_op__fn_unit$next[12:0]$9297 + attribute \src "libresoc.v:166465.3-166466.49" + wire width 13 $0\trap_op__fn_unit[12:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 32 $0\trap_op__insn$next[31:0]$9298 + attribute \src "libresoc.v:166467.3-166468.43" + wire width 32 $0\trap_op__insn[31:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 7 $0\trap_op__insn_type$next[6:0]$9299 + attribute \src "libresoc.v:166463.3-166464.53" + wire width 7 $0\trap_op__insn_type[6:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire $0\trap_op__is_32bit$next[0:0]$9300 + attribute \src "libresoc.v:166473.3-166474.51" + wire $0\trap_op__is_32bit[0:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 8 $0\trap_op__ldst_exc$next[7:0]$9301 + attribute \src "libresoc.v:166479.3-166480.51" + wire width 8 $0\trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 64 $0\trap_op__msr$next[63:0]$9302 + attribute \src "libresoc.v:166469.3-166470.41" + wire width 64 $0\trap_op__msr[63:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 13 $0\trap_op__trapaddr$next[12:0]$9303 + attribute \src "libresoc.v:166477.3-166478.51" + wire width 13 $0\trap_op__trapaddr[12:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 8 $0\trap_op__traptype$next[7:0]$9304 + attribute \src "libresoc.v:166475.3-166476.51" + wire width 8 $0\trap_op__traptype[7:0] + attribute \src "libresoc.v:166601.3-166613.6" + wire width 64 $1\fast1$next[63:0]$9322 + attribute \src "libresoc.v:166048.14-166048.42" + wire width 64 $1\fast1[63:0] + attribute \src "libresoc.v:166614.3-166626.6" + wire width 64 $1\fast2$next[63:0]$9325 + attribute \src "libresoc.v:166057.14-166057.42" + wire width 64 $1\fast2[63:0] + attribute \src "libresoc.v:166541.3-166553.6" + wire width 2 $1\muxid$next[1:0]$9294 + attribute \src "libresoc.v:166066.13-166066.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:166523.3-166540.6" + wire $1\r_busy$next[0:0]$9290 + attribute \src "libresoc.v:166088.7-166088.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:172993.3-173033.6" - wire width 13 $1\sr_op__fn_unit$3$next[12:0]$9626 - attribute \src "libresoc.v:172993.3-173033.6" - wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9627 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__imm_data__ok$5$next[0:0]$9628 - attribute \src "libresoc.v:172993.3-173033.6" - wire width 2 $1\sr_op__input_carry$12$next[1:0]$9629 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__input_cr$14$next[0:0]$9630 - attribute \src "libresoc.v:172993.3-173033.6" - wire width 32 $1\sr_op__insn$18$next[31:0]$9631 - attribute \src "libresoc.v:172993.3-173033.6" - wire width 7 $1\sr_op__insn_type$2$next[6:0]$9632 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__invert_in$11$next[0:0]$9633 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__is_32bit$16$next[0:0]$9634 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__is_signed$17$next[0:0]$9635 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__oe__oe$8$next[0:0]$9636 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__oe__ok$9$next[0:0]$9637 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__output_carry$13$next[0:0]$9638 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__output_cr$15$next[0:0]$9639 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__rc__ok$7$next[0:0]$9640 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__rc__rc$6$next[0:0]$9641 - attribute \src "libresoc.v:172993.3-173033.6" - wire $1\sr_op__write_cr0$10$next[0:0]$9642 - attribute \src "libresoc.v:173072.3-173090.6" - wire width 2 $1\xer_ca$23$next[1:0]$9664 - attribute \src "libresoc.v:173072.3-173090.6" - wire $1\xer_ca_ok$24$next[0:0]$9665 - attribute \src "libresoc.v:173053.3-173071.6" - wire $2\cr_a_ok$22$next[0:0]$9660 - attribute \src "libresoc.v:173034.3-173052.6" - wire $2\o_ok$20$next[0:0]$9654 - attribute \src "libresoc.v:172962.3-172979.6" - wire $2\r_busy$next[0:0]$9604 - attribute \src "libresoc.v:172993.3-173033.6" - wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9643 - attribute \src "libresoc.v:172993.3-173033.6" - wire $2\sr_op__imm_data__ok$5$next[0:0]$9644 - attribute \src "libresoc.v:172993.3-173033.6" - wire $2\sr_op__oe__oe$8$next[0:0]$9645 - attribute \src "libresoc.v:172993.3-173033.6" - wire $2\sr_op__oe__ok$9$next[0:0]$9646 - attribute \src "libresoc.v:172993.3-173033.6" - wire $2\sr_op__rc__ok$7$next[0:0]$9647 - attribute \src "libresoc.v:172993.3-173033.6" - wire $2\sr_op__rc__rc$6$next[0:0]$9648 - attribute \src "libresoc.v:173072.3-173090.6" - wire $2\xer_ca_ok$24$next[0:0]$9666 - attribute \src "libresoc.v:172854.18-172854.118" - wire $and$libresoc.v:172854$9551_Y + attribute \src "libresoc.v:166575.3-166587.6" + wire width 64 $1\ra$next[63:0]$9316 + attribute \src "libresoc.v:166093.14-166093.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:166588.3-166600.6" + wire width 64 $1\rb$next[63:0]$9319 + attribute \src "libresoc.v:166102.14-166102.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 64 $1\trap_op__cia$next[63:0]$9305 + attribute \src "libresoc.v:166111.14-166111.49" + wire width 64 $1\trap_op__cia[63:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 13 $1\trap_op__fn_unit$next[12:0]$9306 + attribute \src "libresoc.v:166134.14-166134.41" + wire width 13 $1\trap_op__fn_unit[12:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 32 $1\trap_op__insn$next[31:0]$9307 + attribute \src "libresoc.v:166171.14-166171.35" + wire width 32 $1\trap_op__insn[31:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 7 $1\trap_op__insn_type$next[6:0]$9308 + attribute \src "libresoc.v:166254.13-166254.39" + wire width 7 $1\trap_op__insn_type[6:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire $1\trap_op__is_32bit$next[0:0]$9309 + attribute \src "libresoc.v:166411.7-166411.31" + wire $1\trap_op__is_32bit[0:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 8 $1\trap_op__ldst_exc$next[7:0]$9310 + attribute \src "libresoc.v:166420.13-166420.38" + wire width 8 $1\trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 64 $1\trap_op__msr$next[63:0]$9311 + attribute \src "libresoc.v:166429.14-166429.49" + wire width 64 $1\trap_op__msr[63:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 13 $1\trap_op__trapaddr$next[12:0]$9312 + attribute \src "libresoc.v:166438.14-166438.42" + wire width 13 $1\trap_op__trapaddr[12:0] + attribute \src "libresoc.v:166554.3-166574.6" + wire width 8 $1\trap_op__traptype$next[7:0]$9313 + attribute \src "libresoc.v:166447.13-166447.38" + wire width 8 $1\trap_op__traptype[7:0] + attribute \src "libresoc.v:166523.3-166540.6" + wire $2\r_busy$next[0:0]$9291 + attribute \src "libresoc.v:166454.18-166454.118" + wire $and$libresoc.v:166454$9272_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 56 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 24 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 52 \cr_a$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 25 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 53 \cr_a_ok$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$74 - attribute \src "libresoc.v:172049.7-172049.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 32 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 31 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 30 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 50 \o$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 51 \o_ok$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast1$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast2$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_muxid + wire width 2 \dummy_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_muxid$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$44 + wire width 2 \dummy_muxid$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_ra$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_rb$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dummy_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dummy_trap_op__cia$20 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -351970,7 +343401,7 @@ module \pipe2$115 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_sr_op__fn_unit + wire width 13 \dummy_trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -351986,35 +343417,11 @@ module \pipe2$115 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_sr_op__fn_unit$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__data$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__imm_data__ok$29 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__input_cr$38 + wire width 13 \dummy_trap_op__fn_unit$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn + wire width 32 \dummy_trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn$42 + wire width 32 \dummy_trap_op__insn$18 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -352090,7 +343497,7 @@ module \pipe2$115 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type + wire width 7 \dummy_trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -352166,67 +343573,95 @@ module \pipe2$115 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__invert_in$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_32bit$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_signed$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__oe$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__ok$33 + wire width 7 \dummy_trap_op__insn_type$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_carry + wire \dummy_trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_carry$37 + wire \dummy_trap_op__is_32bit$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_cr + wire width 8 \dummy_trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_cr$39 + wire width 8 \dummy_trap_op__ldst_exc$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__ok + wire width 64 \dummy_trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__ok$31 + wire width 64 \dummy_trap_op__msr$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__rc + wire width 13 \dummy_trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__rc$30 + wire width 13 \dummy_trap_op__trapaddr$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__write_cr0 + wire width 8 \dummy_trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ca$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so + wire width 8 \dummy_trap_op__traptype$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 32 \fast1$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast1$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 33 \fast2$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast2$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \fast2$next + attribute \src "libresoc.v:165807.7-165807.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 20 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o + wire output 19 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i + wire input 18 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$50 + wire \p_valid_i$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" wire \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 14 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 30 \ra$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 15 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 31 \rb$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 9 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 25 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$next attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -352242,7 +343677,7 @@ module \pipe2$115 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \sr_op__fn_unit + wire width 13 output 6 \trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -352258,9 +343693,7 @@ module \pipe2$115 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 34 \sr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \sr_op__fn_unit$3$next + wire width 13 input 22 \trap_op__fn_unit$3 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -352276,59 +343709,17 @@ module \pipe2$115 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \sr_op__fn_unit$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 35 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$57 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 43 \sr_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$12$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \sr_op__input_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$14$next + wire width 13 \trap_op__fn_unit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$66 + wire width 13 \trap_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 21 \sr_op__insn + wire width 32 output 7 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 49 \sr_op__insn$18 + wire width 32 \trap_op__insn$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$18$next + wire width 32 input 23 \trap_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$70 + wire width 32 \trap_op__insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -352404,7 +343795,7 @@ module \pipe2$115 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \sr_op__insn_type + wire width 7 output 5 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -352480,9 +343871,7 @@ module \pipe2$115 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 33 \sr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$2$next + wire width 7 input 21 \trap_op__insn_type$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -352558,577 +343947,346 @@ module \pipe2$115 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \sr_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \sr_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \sr_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \sr_op__oe__ok$9 + wire width 7 \trap_op__insn_type$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$9$next + wire width 7 \trap_op__insn_type$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \sr_op__output_carry + wire output 10 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \sr_op__output_carry$13 + wire \trap_op__is_32bit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$13$next + wire input 26 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$65 + wire \trap_op__is_32bit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \sr_op__output_cr + wire width 8 output 13 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \sr_op__output_cr$15 + wire width 8 input 29 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$15$next + wire width 8 \trap_op__ldst_exc$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$67 + wire width 8 \trap_op__ldst_exc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__rc__ok + wire width 64 output 8 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$59 + wire width 64 \trap_op__msr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \sr_op__rc__ok$7 + wire width 64 input 24 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$7$next + wire width 64 \trap_op__msr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \sr_op__rc__rc + wire width 13 output 12 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$58 + wire width 13 \trap_op__trapaddr$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__rc__rc$6 + wire width 13 input 28 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$6$next + wire width 13 \trap_op__trapaddr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__write_cr0 + wire width 8 output 11 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \sr_op__write_cr0$10 + wire width 8 \trap_op__traptype$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$10$next + wire width 8 input 27 \trap_op__traptype$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 28 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 54 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 29 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 55 \xer_ca_ok$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 26 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 27 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$48 + wire width 8 \trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:172854$9551 + cell $and $and$libresoc.v:166454$9272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$50 + connect \A \p_valid_i$29 connect \B \p_ready_o - connect \Y $and$libresoc.v:172854$9551_Y + connect \Y $and$libresoc.v:166454$9272_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:172905.11-172908.4" - cell \n$117 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:166485.9-166514.4" + cell \dummy \dummy + connect \fast1 \dummy_fast1 + connect \fast1$13 \dummy_fast1$27 + connect \fast2 \dummy_fast2 + connect \fast2$14 \dummy_fast2$28 + connect \muxid \dummy_muxid + connect \muxid$1 \dummy_muxid$15 + connect \ra \dummy_ra + connect \ra$11 \dummy_ra$25 + connect \rb \dummy_rb + connect \rb$12 \dummy_rb$26 + connect \trap_op__cia \dummy_trap_op__cia + connect \trap_op__cia$6 \dummy_trap_op__cia$20 + connect \trap_op__fn_unit \dummy_trap_op__fn_unit + connect \trap_op__fn_unit$3 \dummy_trap_op__fn_unit$17 + connect \trap_op__insn \dummy_trap_op__insn + connect \trap_op__insn$4 \dummy_trap_op__insn$18 + connect \trap_op__insn_type \dummy_trap_op__insn_type + connect \trap_op__insn_type$2 \dummy_trap_op__insn_type$16 + connect \trap_op__is_32bit \dummy_trap_op__is_32bit + connect \trap_op__is_32bit$7 \dummy_trap_op__is_32bit$21 + connect \trap_op__ldst_exc \dummy_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \dummy_trap_op__ldst_exc$24 + connect \trap_op__msr \dummy_trap_op__msr + connect \trap_op__msr$5 \dummy_trap_op__msr$19 + connect \trap_op__trapaddr \dummy_trap_op__trapaddr + connect \trap_op__trapaddr$9 \dummy_trap_op__trapaddr$23 + connect \trap_op__traptype \dummy_trap_op__traptype + connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 - attribute \src "libresoc.v:172909.16-172957.4" - cell \output$118 \output - connect \cr_a \output_cr_a - connect \cr_a$21 \output_cr_a$45 - connect \cr_a_ok \output_cr_a_ok - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$25 - connect \o \output_o - connect \o$19 \output_o$43 - connect \o_ok \output_o_ok - connect \o_ok$20 \output_o_ok$44 - connect \sr_op__fn_unit \output_sr_op__fn_unit - connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$27 - connect \sr_op__imm_data__data \output_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$28 - connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$29 - connect \sr_op__input_carry \output_sr_op__input_carry - connect \sr_op__input_carry$12 \output_sr_op__input_carry$36 - connect \sr_op__input_cr \output_sr_op__input_cr - connect \sr_op__input_cr$14 \output_sr_op__input_cr$38 - connect \sr_op__insn \output_sr_op__insn - connect \sr_op__insn$18 \output_sr_op__insn$42 - connect \sr_op__insn_type \output_sr_op__insn_type - connect \sr_op__insn_type$2 \output_sr_op__insn_type$26 - connect \sr_op__invert_in \output_sr_op__invert_in - connect \sr_op__invert_in$11 \output_sr_op__invert_in$35 - connect \sr_op__is_32bit \output_sr_op__is_32bit - connect \sr_op__is_32bit$16 \output_sr_op__is_32bit$40 - connect \sr_op__is_signed \output_sr_op__is_signed - connect \sr_op__is_signed$17 \output_sr_op__is_signed$41 - connect \sr_op__oe__oe \output_sr_op__oe__oe - connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$32 - connect \sr_op__oe__ok \output_sr_op__oe__ok - connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$33 - connect \sr_op__output_carry \output_sr_op__output_carry - connect \sr_op__output_carry$13 \output_sr_op__output_carry$37 - connect \sr_op__output_cr \output_sr_op__output_cr - connect \sr_op__output_cr$15 \output_sr_op__output_cr$39 - connect \sr_op__rc__ok \output_sr_op__rc__ok - connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$31 - connect \sr_op__rc__rc \output_sr_op__rc__rc - connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$30 - connect \sr_op__write_cr0 \output_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$34 - connect \xer_ca \output_xer_ca - connect \xer_ca$22 \output_xer_ca$46 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_so \output_xer_so + attribute \src "libresoc.v:166515.10-166518.4" + cell \n$34 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:172958.11-172961.4" - cell \p$116 \p + attribute \src "libresoc.v:166519.10-166522.4" + cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:172049.7-172049.20" - process $proc$libresoc.v:172049$9667 + attribute \src "libresoc.v:165807.7-165807.20" + process $proc$libresoc.v:165807$9326 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172060.13-172060.29" - process $proc$libresoc.v:172060$9668 - assign { } { } - assign $0\cr_a$21[3:0]$9669 4'0000 - sync always - sync init - update \cr_a$21 $0\cr_a$21[3:0]$9669 - end - attribute \src "libresoc.v:172069.7-172069.26" - process $proc$libresoc.v:172069$9670 - assign { } { } - assign $0\cr_a_ok$22[0:0]$9671 1'0 - sync always - sync init - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9671 - end - attribute \src "libresoc.v:172080.13-172080.29" - process $proc$libresoc.v:172080$9672 + attribute \src "libresoc.v:166048.14-166048.42" + process $proc$libresoc.v:166048$9327 assign { } { } - assign $0\muxid$1[1:0]$9673 2'00 + assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9673 + update \fast1 $1\fast1[63:0] end - attribute \src "libresoc.v:172095.14-172095.43" - process $proc$libresoc.v:172095$9674 + attribute \src "libresoc.v:166057.14-166057.42" + process $proc$libresoc.v:166057$9328 assign { } { } - assign $0\o$19[63:0]$9675 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$19 $0\o$19[63:0]$9675 + update \fast2 $1\fast2[63:0] end - attribute \src "libresoc.v:172104.7-172104.23" - process $proc$libresoc.v:172104$9676 + attribute \src "libresoc.v:166066.13-166066.25" + process $proc$libresoc.v:166066$9329 assign { } { } - assign $0\o_ok$20[0:0]$9677 1'0 + assign $1\muxid[1:0] 2'00 sync always sync init - update \o_ok$20 $0\o_ok$20[0:0]$9677 + update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:172396.7-172396.20" - process $proc$libresoc.v:172396$9678 + attribute \src "libresoc.v:166088.7-166088.20" + process $proc$libresoc.v:166088$9330 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:172431.14-172431.43" - process $proc$libresoc.v:172431$9679 - assign { } { } - assign $0\sr_op__fn_unit$3[12:0]$9680 13'0000000000000 - sync always - sync init - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9680 - end - attribute \src "libresoc.v:172454.14-172454.62" - process $proc$libresoc.v:172454$9681 - assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9682 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9682 - end - attribute \src "libresoc.v:172463.7-172463.37" - process $proc$libresoc.v:172463$9683 - assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9684 1'0 - sync always - sync init - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9684 - end - attribute \src "libresoc.v:172480.13-172480.43" - process $proc$libresoc.v:172480$9685 - assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9686 2'00 - sync always - sync init - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9686 - end - attribute \src "libresoc.v:172493.7-172493.34" - process $proc$libresoc.v:172493$9687 - assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9688 1'0 - sync always - sync init - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9688 - end - attribute \src "libresoc.v:172502.14-172502.38" - process $proc$libresoc.v:172502$9689 - assign { } { } - assign $0\sr_op__insn$18[31:0]$9690 0 - sync always - sync init - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9690 - end - attribute \src "libresoc.v:172659.13-172659.41" - process $proc$libresoc.v:172659$9691 - assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9692 7'0000000 - sync always - sync init - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9692 - end - attribute \src "libresoc.v:172742.7-172742.35" - process $proc$libresoc.v:172742$9693 - assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9694 1'0 - sync always - sync init - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9694 - end - attribute \src "libresoc.v:172751.7-172751.34" - process $proc$libresoc.v:172751$9695 - assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9696 1'0 - sync always - sync init - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9696 - end - attribute \src "libresoc.v:172760.7-172760.35" - process $proc$libresoc.v:172760$9697 - assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9698 1'0 - sync always - sync init - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9698 - end - attribute \src "libresoc.v:172771.7-172771.31" - process $proc$libresoc.v:172771$9699 - assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9700 1'0 - sync always - sync init - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9700 - end - attribute \src "libresoc.v:172780.7-172780.31" - process $proc$libresoc.v:172780$9701 + attribute \src "libresoc.v:166093.14-166093.39" + process $proc$libresoc.v:166093$9331 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9702 1'0 + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9702 + update \ra $1\ra[63:0] end - attribute \src "libresoc.v:172787.7-172787.38" - process $proc$libresoc.v:172787$9703 + attribute \src "libresoc.v:166102.14-166102.39" + process $proc$libresoc.v:166102$9332 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9704 1'0 + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9704 + update \rb $1\rb[63:0] end - attribute \src "libresoc.v:172796.7-172796.35" - process $proc$libresoc.v:172796$9705 + attribute \src "libresoc.v:166111.14-166111.49" + process $proc$libresoc.v:166111$9333 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9706 1'0 + assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9706 + update \trap_op__cia $1\trap_op__cia[63:0] end - attribute \src "libresoc.v:172807.7-172807.31" - process $proc$libresoc.v:172807$9707 + attribute \src "libresoc.v:166134.14-166134.41" + process $proc$libresoc.v:166134$9334 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9708 1'0 + assign $1\trap_op__fn_unit[12:0] 13'0000000000000 sync always sync init - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9708 + update \trap_op__fn_unit $1\trap_op__fn_unit[12:0] end - attribute \src "libresoc.v:172816.7-172816.31" - process $proc$libresoc.v:172816$9709 + attribute \src "libresoc.v:166171.14-166171.35" + process $proc$libresoc.v:166171$9335 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9710 1'0 + assign $1\trap_op__insn[31:0] 0 sync always sync init - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9710 + update \trap_op__insn $1\trap_op__insn[31:0] end - attribute \src "libresoc.v:172823.7-172823.35" - process $proc$libresoc.v:172823$9711 + attribute \src "libresoc.v:166254.13-166254.39" + process $proc$libresoc.v:166254$9336 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9712 1'0 + assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9712 + update \trap_op__insn_type $1\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:172832.13-172832.31" - process $proc$libresoc.v:172832$9713 + attribute \src "libresoc.v:166411.7-166411.31" + process $proc$libresoc.v:166411$9337 assign { } { } - assign $0\xer_ca$23[1:0]$9714 2'00 + assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init - update \xer_ca$23 $0\xer_ca$23[1:0]$9714 + update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:172841.7-172841.28" - process $proc$libresoc.v:172841$9715 + attribute \src "libresoc.v:166420.13-166420.38" + process $proc$libresoc.v:166420$9338 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9716 1'0 + assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9716 - end - attribute \src "libresoc.v:172855.3-172856.37" - process $proc$libresoc.v:172855$9552 - assign { } { } - assign $0\xer_ca$23[1:0]$9553 \xer_ca$23$next - sync posedge \coresync_clk - update \xer_ca$23 $0\xer_ca$23[1:0]$9553 - end - attribute \src "libresoc.v:172857.3-172858.43" - process $proc$libresoc.v:172857$9554 - assign { } { } - assign $0\xer_ca_ok$24[0:0]$9555 \xer_ca_ok$24$next - sync posedge \coresync_clk - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9555 - end - attribute \src "libresoc.v:172859.3-172860.33" - process $proc$libresoc.v:172859$9556 - assign { } { } - assign $0\cr_a$21[3:0]$9557 \cr_a$21$next - sync posedge \coresync_clk - update \cr_a$21 $0\cr_a$21[3:0]$9557 - end - attribute \src "libresoc.v:172861.3-172862.39" - process $proc$libresoc.v:172861$9558 - assign { } { } - assign $0\cr_a_ok$22[0:0]$9559 \cr_a_ok$22$next - sync posedge \coresync_clk - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9559 - end - attribute \src "libresoc.v:172863.3-172864.27" - process $proc$libresoc.v:172863$9560 - assign { } { } - assign $0\o$19[63:0]$9561 \o$19$next - sync posedge \coresync_clk - update \o$19 $0\o$19[63:0]$9561 - end - attribute \src "libresoc.v:172865.3-172866.33" - process $proc$libresoc.v:172865$9562 - assign { } { } - assign $0\o_ok$20[0:0]$9563 \o_ok$20$next - sync posedge \coresync_clk - update \o_ok$20 $0\o_ok$20[0:0]$9563 - end - attribute \src "libresoc.v:172867.3-172868.55" - process $proc$libresoc.v:172867$9564 - assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9565 \sr_op__insn_type$2$next - sync posedge \coresync_clk - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9565 + update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:172869.3-172870.51" - process $proc$libresoc.v:172869$9566 + attribute \src "libresoc.v:166429.14-166429.49" + process $proc$libresoc.v:166429$9339 assign { } { } - assign $0\sr_op__fn_unit$3[12:0]$9567 \sr_op__fn_unit$3$next - sync posedge \coresync_clk - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9567 + assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__msr $1\trap_op__msr[63:0] end - attribute \src "libresoc.v:172871.3-172872.65" - process $proc$libresoc.v:172871$9568 + attribute \src "libresoc.v:166438.14-166438.42" + process $proc$libresoc.v:166438$9340 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9569 \sr_op__imm_data__data$4$next - sync posedge \coresync_clk - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9569 + assign $1\trap_op__trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:172873.3-172874.61" - process $proc$libresoc.v:172873$9570 + attribute \src "libresoc.v:166447.13-166447.38" + process $proc$libresoc.v:166447$9341 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9571 \sr_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9571 + assign $1\trap_op__traptype[7:0] 8'00000000 + sync always + sync init + update \trap_op__traptype $1\trap_op__traptype[7:0] end - attribute \src "libresoc.v:172875.3-172876.49" - process $proc$libresoc.v:172875$9572 + attribute \src "libresoc.v:166455.3-166456.27" + process $proc$libresoc.v:166455$9273 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9573 \sr_op__rc__rc$6$next + assign $0\fast2[63:0] \fast2$next sync posedge \coresync_clk - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9573 + update \fast2 $0\fast2[63:0] end - attribute \src "libresoc.v:172877.3-172878.49" - process $proc$libresoc.v:172877$9574 + attribute \src "libresoc.v:166457.3-166458.27" + process $proc$libresoc.v:166457$9274 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9575 \sr_op__rc__ok$7$next + assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9575 + update \fast1 $0\fast1[63:0] end - attribute \src "libresoc.v:172879.3-172880.49" - process $proc$libresoc.v:172879$9576 + attribute \src "libresoc.v:166459.3-166460.21" + process $proc$libresoc.v:166459$9275 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9577 \sr_op__oe__oe$8$next + assign $0\rb[63:0] \rb$next sync posedge \coresync_clk - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9577 + update \rb $0\rb[63:0] end - attribute \src "libresoc.v:172881.3-172882.49" - process $proc$libresoc.v:172881$9578 + attribute \src "libresoc.v:166461.3-166462.21" + process $proc$libresoc.v:166461$9276 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9579 \sr_op__oe__ok$9$next + assign $0\ra[63:0] \ra$next sync posedge \coresync_clk - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9579 + update \ra $0\ra[63:0] end - attribute \src "libresoc.v:172883.3-172884.57" - process $proc$libresoc.v:172883$9580 + attribute \src "libresoc.v:166463.3-166464.53" + process $proc$libresoc.v:166463$9277 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9581 \sr_op__write_cr0$10$next + assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9581 + update \trap_op__insn_type $0\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:172885.3-172886.57" - process $proc$libresoc.v:172885$9582 + attribute \src "libresoc.v:166465.3-166466.49" + process $proc$libresoc.v:166465$9278 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9583 \sr_op__invert_in$11$next + assign $0\trap_op__fn_unit[12:0] \trap_op__fn_unit$next sync posedge \coresync_clk - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9583 + update \trap_op__fn_unit $0\trap_op__fn_unit[12:0] end - attribute \src "libresoc.v:172887.3-172888.61" - process $proc$libresoc.v:172887$9584 + attribute \src "libresoc.v:166467.3-166468.43" + process $proc$libresoc.v:166467$9279 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9585 \sr_op__input_carry$12$next + assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9585 + update \trap_op__insn $0\trap_op__insn[31:0] end - attribute \src "libresoc.v:172889.3-172890.63" - process $proc$libresoc.v:172889$9586 + attribute \src "libresoc.v:166469.3-166470.41" + process $proc$libresoc.v:166469$9280 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9587 \sr_op__output_carry$13$next + assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9587 + update \trap_op__msr $0\trap_op__msr[63:0] end - attribute \src "libresoc.v:172891.3-172892.55" - process $proc$libresoc.v:172891$9588 + attribute \src "libresoc.v:166471.3-166472.41" + process $proc$libresoc.v:166471$9281 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9589 \sr_op__input_cr$14$next + assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9589 + update \trap_op__cia $0\trap_op__cia[63:0] end - attribute \src "libresoc.v:172893.3-172894.57" - process $proc$libresoc.v:172893$9590 + attribute \src "libresoc.v:166473.3-166474.51" + process $proc$libresoc.v:166473$9282 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9591 \sr_op__output_cr$15$next + assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9591 + update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:172895.3-172896.55" - process $proc$libresoc.v:172895$9592 + attribute \src "libresoc.v:166475.3-166476.51" + process $proc$libresoc.v:166475$9283 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9593 \sr_op__is_32bit$16$next + assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9593 + update \trap_op__traptype $0\trap_op__traptype[7:0] end - attribute \src "libresoc.v:172897.3-172898.57" - process $proc$libresoc.v:172897$9594 + attribute \src "libresoc.v:166477.3-166478.51" + process $proc$libresoc.v:166477$9284 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9595 \sr_op__is_signed$17$next + assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9595 + update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:172899.3-172900.47" - process $proc$libresoc.v:172899$9596 + attribute \src "libresoc.v:166479.3-166480.51" + process $proc$libresoc.v:166479$9285 assign { } { } - assign $0\sr_op__insn$18[31:0]$9597 \sr_op__insn$18$next + assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9597 + update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:172901.3-172902.33" - process $proc$libresoc.v:172901$9598 + attribute \src "libresoc.v:166481.3-166482.27" + process $proc$libresoc.v:166481$9286 assign { } { } - assign $0\muxid$1[1:0]$9599 \muxid$1$next + assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9599 + update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:172903.3-172904.29" - process $proc$libresoc.v:172903$9600 + attribute \src "libresoc.v:166483.3-166484.29" + process $proc$libresoc.v:166483$9287 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:172962.3-172979.6" - process $proc$libresoc.v:172962$9601 + attribute \src "libresoc.v:166523.3-166540.6" + process $proc$libresoc.v:166523$9288 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9602 $2\r_busy$next[0:0]$9604 - attribute \src "libresoc.v:172963.5-172963.29" + assign $0\r_busy$next[0:0]$9289 $2\r_busy$next[0:0]$9291 + attribute \src "libresoc.v:166524.5-166524.29" switch \initial - attribute \src "libresoc.v:172963.9-172963.17" + attribute \src "libresoc.v:166524.9-166524.17" case 1'1 case end @@ -353137,34 +344295,34 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9603 1'1 + assign $1\r_busy$next[0:0]$9290 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9603 1'0 + assign $1\r_busy$next[0:0]$9290 1'0 case - assign $1\r_busy$next[0:0]$9603 \r_busy + assign $1\r_busy$next[0:0]$9290 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9604 1'0 + assign $2\r_busy$next[0:0]$9291 1'0 case - assign $2\r_busy$next[0:0]$9604 $1\r_busy$next[0:0]$9603 + assign $2\r_busy$next[0:0]$9291 $1\r_busy$next[0:0]$9290 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9602 + update \r_busy$next $0\r_busy$next[0:0]$9289 end - attribute \src "libresoc.v:172980.3-172992.6" - process $proc$libresoc.v:172980$9605 + attribute \src "libresoc.v:166541.3-166553.6" + process $proc$libresoc.v:166541$9292 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9606 $1\muxid$1$next[1:0]$9607 - attribute \src "libresoc.v:172981.5-172981.29" + assign $0\muxid$next[1:0]$9293 $1\muxid$next[1:0]$9294 + attribute \src "libresoc.v:166542.5-166542.29" switch \initial - attribute \src "libresoc.v:172981.9-172981.17" + attribute \src "libresoc.v:166542.9-166542.17" case 1'1 case end @@ -353173,40 +344331,19 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9607 \muxid$53 + assign $1\muxid$next[1:0]$9294 \muxid$32 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9607 \muxid$53 + assign $1\muxid$next[1:0]$9294 \muxid$32 case - assign $1\muxid$1$next[1:0]$9607 \muxid$1 + assign $1\muxid$next[1:0]$9294 \muxid end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9606 + update \muxid$next $0\muxid$next[1:0]$9293 end - attribute \src "libresoc.v:172993.3-173033.6" - process $proc$libresoc.v:172993$9608 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:166554.3-166574.6" + process $proc$libresoc.v:166554$9295 assign { } { } assign { } { } assign { } { } @@ -353220,32 +344357,23 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$3$next[12:0]$9609 $1\sr_op__fn_unit$3$next[12:0]$9626 assign { } { } assign { } { } - assign $0\sr_op__input_carry$12$next[1:0]$9612 $1\sr_op__input_carry$12$next[1:0]$9629 - assign $0\sr_op__input_cr$14$next[0:0]$9613 $1\sr_op__input_cr$14$next[0:0]$9630 - assign $0\sr_op__insn$18$next[31:0]$9614 $1\sr_op__insn$18$next[31:0]$9631 - assign $0\sr_op__insn_type$2$next[6:0]$9615 $1\sr_op__insn_type$2$next[6:0]$9632 - assign $0\sr_op__invert_in$11$next[0:0]$9616 $1\sr_op__invert_in$11$next[0:0]$9633 - assign $0\sr_op__is_32bit$16$next[0:0]$9617 $1\sr_op__is_32bit$16$next[0:0]$9634 - assign $0\sr_op__is_signed$17$next[0:0]$9618 $1\sr_op__is_signed$17$next[0:0]$9635 assign { } { } assign { } { } - assign $0\sr_op__output_carry$13$next[0:0]$9621 $1\sr_op__output_carry$13$next[0:0]$9638 - assign $0\sr_op__output_cr$15$next[0:0]$9622 $1\sr_op__output_cr$15$next[0:0]$9639 assign { } { } - assign { } { } - assign $0\sr_op__write_cr0$10$next[0:0]$9625 $1\sr_op__write_cr0$10$next[0:0]$9642 - assign $0\sr_op__imm_data__data$4$next[63:0]$9610 $2\sr_op__imm_data__data$4$next[63:0]$9643 - assign $0\sr_op__imm_data__ok$5$next[0:0]$9611 $2\sr_op__imm_data__ok$5$next[0:0]$9644 - assign $0\sr_op__oe__oe$8$next[0:0]$9619 $2\sr_op__oe__oe$8$next[0:0]$9645 - assign $0\sr_op__oe__ok$9$next[0:0]$9620 $2\sr_op__oe__ok$9$next[0:0]$9646 - assign $0\sr_op__rc__ok$7$next[0:0]$9623 $2\sr_op__rc__ok$7$next[0:0]$9647 - assign $0\sr_op__rc__rc$6$next[0:0]$9624 $2\sr_op__rc__rc$6$next[0:0]$9648 - attribute \src "libresoc.v:172994.5-172994.29" + assign $0\trap_op__cia$next[63:0]$9296 $1\trap_op__cia$next[63:0]$9305 + assign $0\trap_op__fn_unit$next[12:0]$9297 $1\trap_op__fn_unit$next[12:0]$9306 + assign $0\trap_op__insn$next[31:0]$9298 $1\trap_op__insn$next[31:0]$9307 + assign $0\trap_op__insn_type$next[6:0]$9299 $1\trap_op__insn_type$next[6:0]$9308 + assign $0\trap_op__is_32bit$next[0:0]$9300 $1\trap_op__is_32bit$next[0:0]$9309 + assign $0\trap_op__ldst_exc$next[7:0]$9301 $1\trap_op__ldst_exc$next[7:0]$9310 + assign $0\trap_op__msr$next[63:0]$9302 $1\trap_op__msr$next[63:0]$9311 + assign $0\trap_op__trapaddr$next[12:0]$9303 $1\trap_op__trapaddr$next[12:0]$9312 + assign $0\trap_op__traptype$next[7:0]$9304 $1\trap_op__traptype$next[7:0]$9313 + attribute \src "libresoc.v:166555.5-166555.29" switch \initial - attribute \src "libresoc.v:172994.9-172994.17" + attribute \src "libresoc.v:166555.9-166555.17" case 1'1 case end @@ -353262,15 +344390,7 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9631 $1\sr_op__is_signed$17$next[0:0]$9635 $1\sr_op__is_32bit$16$next[0:0]$9634 $1\sr_op__output_cr$15$next[0:0]$9639 $1\sr_op__input_cr$14$next[0:0]$9630 $1\sr_op__output_carry$13$next[0:0]$9638 $1\sr_op__input_carry$12$next[1:0]$9629 $1\sr_op__invert_in$11$next[0:0]$9633 $1\sr_op__write_cr0$10$next[0:0]$9642 $1\sr_op__oe__ok$9$next[0:0]$9637 $1\sr_op__oe__oe$8$next[0:0]$9636 $1\sr_op__rc__ok$7$next[0:0]$9640 $1\sr_op__rc__rc$6$next[0:0]$9641 $1\sr_op__imm_data__ok$5$next[0:0]$9628 $1\sr_op__imm_data__data$4$next[63:0]$9627 $1\sr_op__fn_unit$3$next[12:0]$9626 $1\sr_op__insn_type$2$next[6:0]$9632 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\trap_op__ldst_exc$next[7:0]$9310 $1\trap_op__trapaddr$next[12:0]$9312 $1\trap_op__traptype$next[7:0]$9313 $1\trap_op__is_32bit$next[0:0]$9309 $1\trap_op__cia$next[63:0]$9305 $1\trap_op__msr$next[63:0]$9311 $1\trap_op__insn$next[31:0]$9307 $1\trap_op__fn_unit$next[12:0]$9306 $1\trap_op__insn_type$next[6:0]$9308 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -353282,89 +344402,64 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9631 $1\sr_op__is_signed$17$next[0:0]$9635 $1\sr_op__is_32bit$16$next[0:0]$9634 $1\sr_op__output_cr$15$next[0:0]$9639 $1\sr_op__input_cr$14$next[0:0]$9630 $1\sr_op__output_carry$13$next[0:0]$9638 $1\sr_op__input_carry$12$next[1:0]$9629 $1\sr_op__invert_in$11$next[0:0]$9633 $1\sr_op__write_cr0$10$next[0:0]$9642 $1\sr_op__oe__ok$9$next[0:0]$9637 $1\sr_op__oe__oe$8$next[0:0]$9636 $1\sr_op__rc__ok$7$next[0:0]$9640 $1\sr_op__rc__rc$6$next[0:0]$9641 $1\sr_op__imm_data__ok$5$next[0:0]$9628 $1\sr_op__imm_data__data$4$next[63:0]$9627 $1\sr_op__fn_unit$3$next[12:0]$9626 $1\sr_op__insn_type$2$next[6:0]$9632 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\trap_op__ldst_exc$next[7:0]$9310 $1\trap_op__trapaddr$next[12:0]$9312 $1\trap_op__traptype$next[7:0]$9313 $1\trap_op__is_32bit$next[0:0]$9309 $1\trap_op__cia$next[63:0]$9305 $1\trap_op__msr$next[63:0]$9311 $1\trap_op__insn$next[31:0]$9307 $1\trap_op__fn_unit$next[12:0]$9306 $1\trap_op__insn_type$next[6:0]$9308 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } case - assign $1\sr_op__fn_unit$3$next[12:0]$9626 \sr_op__fn_unit$3 - assign $1\sr_op__imm_data__data$4$next[63:0]$9627 \sr_op__imm_data__data$4 - assign $1\sr_op__imm_data__ok$5$next[0:0]$9628 \sr_op__imm_data__ok$5 - assign $1\sr_op__input_carry$12$next[1:0]$9629 \sr_op__input_carry$12 - assign $1\sr_op__input_cr$14$next[0:0]$9630 \sr_op__input_cr$14 - assign $1\sr_op__insn$18$next[31:0]$9631 \sr_op__insn$18 - assign $1\sr_op__insn_type$2$next[6:0]$9632 \sr_op__insn_type$2 - assign $1\sr_op__invert_in$11$next[0:0]$9633 \sr_op__invert_in$11 - assign $1\sr_op__is_32bit$16$next[0:0]$9634 \sr_op__is_32bit$16 - assign $1\sr_op__is_signed$17$next[0:0]$9635 \sr_op__is_signed$17 - assign $1\sr_op__oe__oe$8$next[0:0]$9636 \sr_op__oe__oe$8 - assign $1\sr_op__oe__ok$9$next[0:0]$9637 \sr_op__oe__ok$9 - assign $1\sr_op__output_carry$13$next[0:0]$9638 \sr_op__output_carry$13 - assign $1\sr_op__output_cr$15$next[0:0]$9639 \sr_op__output_cr$15 - assign $1\sr_op__rc__ok$7$next[0:0]$9640 \sr_op__rc__ok$7 - assign $1\sr_op__rc__rc$6$next[0:0]$9641 \sr_op__rc__rc$6 - assign $1\sr_op__write_cr0$10$next[0:0]$9642 \sr_op__write_cr0$10 + assign $1\trap_op__cia$next[63:0]$9305 \trap_op__cia + assign $1\trap_op__fn_unit$next[12:0]$9306 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$9307 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$9308 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$9309 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$9310 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$9311 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$9312 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$9313 \trap_op__traptype end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9296 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[12:0]$9297 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9298 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9299 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9300 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9301 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9302 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9303 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9304 + end + attribute \src "libresoc.v:166575.3-166587.6" + process $proc$libresoc.v:166575$9314 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$9315 $1\ra$next[63:0]$9316 + attribute \src "libresoc.v:166576.5-166576.29" + switch \initial + attribute \src "libresoc.v:166576.9-166576.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 assign { } { } + assign $1\ra$next[63:0]$9316 \ra$42 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\sr_op__imm_data__data$4$next[63:0]$9643 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9644 1'0 - assign $2\sr_op__rc__rc$6$next[0:0]$9648 1'0 - assign $2\sr_op__rc__ok$7$next[0:0]$9647 1'0 - assign $2\sr_op__oe__oe$8$next[0:0]$9645 1'0 - assign $2\sr_op__oe__ok$9$next[0:0]$9646 1'0 + assign $1\ra$next[63:0]$9316 \ra$42 case - assign $2\sr_op__imm_data__data$4$next[63:0]$9643 $1\sr_op__imm_data__data$4$next[63:0]$9627 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9644 $1\sr_op__imm_data__ok$5$next[0:0]$9628 - assign $2\sr_op__oe__oe$8$next[0:0]$9645 $1\sr_op__oe__oe$8$next[0:0]$9636 - assign $2\sr_op__oe__ok$9$next[0:0]$9646 $1\sr_op__oe__ok$9$next[0:0]$9637 - assign $2\sr_op__rc__ok$7$next[0:0]$9647 $1\sr_op__rc__ok$7$next[0:0]$9640 - assign $2\sr_op__rc__rc$6$next[0:0]$9648 $1\sr_op__rc__rc$6$next[0:0]$9641 + assign $1\ra$next[63:0]$9316 \ra end sync always - update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[12:0]$9609 - update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9610 - update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9611 - update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9612 - update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9613 - update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9614 - update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9615 - update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9616 - update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9617 - update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9618 - update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9619 - update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9620 - update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9621 - update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9622 - update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9623 - update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9624 - update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9625 + update \ra$next $0\ra$next[63:0]$9315 end - attribute \src "libresoc.v:173034.3-173052.6" - process $proc$libresoc.v:173034$9649 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:166588.3-166600.6" + process $proc$libresoc.v:166588$9317 assign { } { } - assign $0\o$19$next[63:0]$9650 $1\o$19$next[63:0]$9652 assign { } { } - assign $0\o_ok$20$next[0:0]$9651 $2\o_ok$20$next[0:0]$9654 - attribute \src "libresoc.v:173035.5-173035.29" + assign $0\rb$next[63:0]$9318 $1\rb$next[63:0]$9319 + attribute \src "libresoc.v:166589.5-166589.29" switch \initial - attribute \src "libresoc.v:173035.9-173035.17" + attribute \src "libresoc.v:166589.9-166589.17" case 1'1 case end @@ -353373,42 +344468,25 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\o_ok$20$next[0:0]$9653 $1\o$19$next[63:0]$9652 } { \o_ok$72 \o$71 } + assign $1\rb$next[63:0]$9319 \rb$43 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\o_ok$20$next[0:0]$9653 $1\o$19$next[63:0]$9652 } { \o_ok$72 \o$71 } - case - assign $1\o$19$next[63:0]$9652 \o$19 - assign $1\o_ok$20$next[0:0]$9653 \o_ok$20 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$20$next[0:0]$9654 1'0 + assign $1\rb$next[63:0]$9319 \rb$43 case - assign $2\o_ok$20$next[0:0]$9654 $1\o_ok$20$next[0:0]$9653 + assign $1\rb$next[63:0]$9319 \rb end sync always - update \o$19$next $0\o$19$next[63:0]$9650 - update \o_ok$20$next $0\o_ok$20$next[0:0]$9651 + update \rb$next $0\rb$next[63:0]$9318 end - attribute \src "libresoc.v:173053.3-173071.6" - process $proc$libresoc.v:173053$9655 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:166601.3-166613.6" + process $proc$libresoc.v:166601$9320 assign { } { } - assign $0\cr_a$21$next[3:0]$9656 $1\cr_a$21$next[3:0]$9658 assign { } { } - assign $0\cr_a_ok$22$next[0:0]$9657 $2\cr_a_ok$22$next[0:0]$9660 - attribute \src "libresoc.v:173054.5-173054.29" + assign $0\fast1$next[63:0]$9321 $1\fast1$next[63:0]$9322 + attribute \src "libresoc.v:166602.5-166602.29" switch \initial - attribute \src "libresoc.v:173054.9-173054.17" + attribute \src "libresoc.v:166602.9-166602.17" case 1'1 case end @@ -353417,42 +344495,25 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9659 $1\cr_a$21$next[3:0]$9658 } { \cr_a_ok$74 \cr_a$73 } + assign $1\fast1$next[63:0]$9322 \fast1$44 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9659 $1\cr_a$21$next[3:0]$9658 } { \cr_a_ok$74 \cr_a$73 } - case - assign $1\cr_a$21$next[3:0]$9658 \cr_a$21 - assign $1\cr_a_ok$22$next[0:0]$9659 \cr_a_ok$22 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$22$next[0:0]$9660 1'0 + assign $1\fast1$next[63:0]$9322 \fast1$44 case - assign $2\cr_a_ok$22$next[0:0]$9660 $1\cr_a_ok$22$next[0:0]$9659 + assign $1\fast1$next[63:0]$9322 \fast1 end sync always - update \cr_a$21$next $0\cr_a$21$next[3:0]$9656 - update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9657 + update \fast1$next $0\fast1$next[63:0]$9321 end - attribute \src "libresoc.v:173072.3-173090.6" - process $proc$libresoc.v:173072$9661 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:166614.3-166626.6" + process $proc$libresoc.v:166614$9323 assign { } { } - assign $0\xer_ca$23$next[1:0]$9662 $1\xer_ca$23$next[1:0]$9664 assign { } { } - assign $0\xer_ca_ok$24$next[0:0]$9663 $2\xer_ca_ok$24$next[0:0]$9666 - attribute \src "libresoc.v:173073.5-173073.29" + assign $0\fast2$next[63:0]$9324 $1\fast2$next[63:0]$9325 + attribute \src "libresoc.v:166615.5-166615.29" switch \initial - attribute \src "libresoc.v:173073.9-173073.17" + attribute \src "libresoc.v:166615.9-166615.17" case 1'1 case end @@ -353461,309 +344522,319 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9665 $1\xer_ca$23$next[1:0]$9664 } { \xer_ca_ok$76 \xer_ca$75 } + assign $1\fast2$next[63:0]$9325 \fast2$45 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9665 $1\xer_ca$23$next[1:0]$9664 } { \xer_ca_ok$76 \xer_ca$75 } - case - assign $1\xer_ca$23$next[1:0]$9664 \xer_ca$23 - assign $1\xer_ca_ok$24$next[0:0]$9665 \xer_ca_ok$24 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ca_ok$24$next[0:0]$9666 1'0 + assign $1\fast2$next[63:0]$9325 \fast2$45 case - assign $2\xer_ca_ok$24$next[0:0]$9666 $1\xer_ca_ok$24$next[0:0]$9665 + assign $1\fast2$next[63:0]$9325 \fast2 end sync always - update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9662 - update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9663 + update \fast2$next $0\fast2$next[63:0]$9324 end - connect \$51 $and$libresoc.v:172854$9551_Y + connect \$30 $and$libresoc.v:166454$9272_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } - connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$45 } - connect { \o_ok$72 \o$71 } { \output_o_ok$44 \output_o$43 } - connect { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } { \output_sr_op__insn$42 \output_sr_op__is_signed$41 \output_sr_op__is_32bit$40 \output_sr_op__output_cr$39 \output_sr_op__input_cr$38 \output_sr_op__output_carry$37 \output_sr_op__input_carry$36 \output_sr_op__invert_in$35 \output_sr_op__write_cr0$34 \output_sr_op__oe__ok$33 \output_sr_op__oe__oe$32 \output_sr_op__rc__ok$31 \output_sr_op__rc__rc$30 \output_sr_op__imm_data__ok$29 \output_sr_op__imm_data__data$28 \output_sr_op__fn_unit$27 \output_sr_op__insn_type$26 } - connect \muxid$53 \output_muxid$25 - connect \p_valid_i_p_ready_o \$51 + connect \fast2$45 \dummy_fast2$28 + connect \fast1$44 \dummy_fast1$27 + connect \rb$43 \dummy_rb$26 + connect \ra$42 \dummy_ra$25 + connect { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } { \dummy_trap_op__ldst_exc$24 \dummy_trap_op__trapaddr$23 \dummy_trap_op__traptype$22 \dummy_trap_op__is_32bit$21 \dummy_trap_op__cia$20 \dummy_trap_op__msr$19 \dummy_trap_op__insn$18 \dummy_trap_op__fn_unit$17 \dummy_trap_op__insn_type$16 } + connect \muxid$32 \dummy_muxid$15 + connect \p_valid_i_p_ready_o \$30 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$50 \p_valid_i - connect { \xer_ca_ok$49 \output_xer_ca } { \xer_ca_ok \xer_ca } - connect { \xer_so_ok$48 \output_xer_so } { \xer_so_ok \xer_so } - connect { \cr_a_ok$47 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \output_muxid \muxid + connect \p_valid_i$29 \p_valid_i + connect \dummy_fast2 \fast2$14 + connect \dummy_fast1 \fast1$13 + connect \dummy_rb \rb$12 + connect \dummy_ra \ra$11 + connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } + connect \dummy_muxid \muxid$1 end -attribute \src "libresoc.v:173111.1-174065.10" +attribute \src "libresoc.v:166648.1-167823.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" -module \pipe2$35 - attribute \src "libresoc.v:173971.3-173989.6" - wire width 64 $0\fast1$11$next[63:0]$9785 - attribute \src "libresoc.v:173826.3-173827.35" - wire width 64 $0\fast1$11[63:0]$9726 - attribute \src "libresoc.v:173123.14-173123.47" - wire width 64 $0\fast1$11[63:0]$9809 - attribute \src "libresoc.v:173971.3-173989.6" - wire $0\fast1_ok$next[0:0]$9784 - attribute \src "libresoc.v:173828.3-173829.33" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:173990.3-174008.6" - wire width 64 $0\fast2$12$next[63:0]$9791 - attribute \src "libresoc.v:173822.3-173823.35" - wire width 64 $0\fast2$12[63:0]$9723 - attribute \src "libresoc.v:173139.14-173139.47" - wire width 64 $0\fast2$12[63:0]$9812 - attribute \src "libresoc.v:173990.3-174008.6" - wire $0\fast2_ok$next[0:0]$9790 - attribute \src "libresoc.v:173824.3-173825.33" - wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:173112.7-173112.20" +module \pipe2 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9410 + attribute \src "libresoc.v:167564.3-167565.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9396 + attribute \src "libresoc.v:166656.13-166656.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9484 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 13 $0\alu_op__fn_unit$3$next[12:0]$9411 + attribute \src "libresoc.v:167534.3-167535.53" + wire width 13 $0\alu_op__fn_unit$3[12:0]$9366 + attribute \src "libresoc.v:166693.14-166693.44" + wire width 13 $0\alu_op__fn_unit$3[12:0]$9486 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9412 + attribute \src "libresoc.v:167536.3-167537.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9368 + attribute \src "libresoc.v:166716.14-166716.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9488 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9413 + attribute \src "libresoc.v:167538.3-167539.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9370 + attribute \src "libresoc.v:166725.7-166725.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9490 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9414 + attribute \src "libresoc.v:167556.3-167557.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9388 + attribute \src "libresoc.v:166742.13-166742.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9492 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9415 + attribute \src "libresoc.v:167566.3-167567.49" + wire width 32 $0\alu_op__insn$19[31:0]$9398 + attribute \src "libresoc.v:166755.14-166755.39" + wire width 32 $0\alu_op__insn$19[31:0]$9494 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9416 + attribute \src "libresoc.v:167532.3-167533.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9364 + attribute \src "libresoc.v:166912.13-166912.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9496 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__invert_in$10$next[0:0]$9417 + attribute \src "libresoc.v:167548.3-167549.59" + wire $0\alu_op__invert_in$10[0:0]$9380 + attribute \src "libresoc.v:166995.7-166995.36" + wire $0\alu_op__invert_in$10[0:0]$9498 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__invert_out$12$next[0:0]$9418 + attribute \src "libresoc.v:167552.3-167553.61" + wire $0\alu_op__invert_out$12[0:0]$9384 + attribute \src "libresoc.v:167004.7-167004.37" + wire $0\alu_op__invert_out$12[0:0]$9500 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9419 + attribute \src "libresoc.v:167560.3-167561.57" + wire $0\alu_op__is_32bit$16[0:0]$9392 + attribute \src "libresoc.v:167013.7-167013.35" + wire $0\alu_op__is_32bit$16[0:0]$9502 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__is_signed$17$next[0:0]$9420 + attribute \src "libresoc.v:167562.3-167563.59" + wire $0\alu_op__is_signed$17[0:0]$9394 + attribute \src "libresoc.v:167022.7-167022.36" + wire $0\alu_op__is_signed$17[0:0]$9504 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9421 + attribute \src "libresoc.v:167544.3-167545.51" + wire $0\alu_op__oe__oe$8[0:0]$9376 + attribute \src "libresoc.v:167033.7-167033.32" + wire $0\alu_op__oe__oe$8[0:0]$9506 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9422 + attribute \src "libresoc.v:167546.3-167547.51" + wire $0\alu_op__oe__ok$9[0:0]$9378 + attribute \src "libresoc.v:167042.7-167042.32" + wire $0\alu_op__oe__ok$9[0:0]$9508 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__output_carry$15$next[0:0]$9423 + attribute \src "libresoc.v:167558.3-167559.65" + wire $0\alu_op__output_carry$15[0:0]$9390 + attribute \src "libresoc.v:167049.7-167049.39" + wire $0\alu_op__output_carry$15[0:0]$9510 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9424 + attribute \src "libresoc.v:167542.3-167543.51" + wire $0\alu_op__rc__ok$7[0:0]$9374 + attribute \src "libresoc.v:167060.7-167060.32" + wire $0\alu_op__rc__ok$7[0:0]$9512 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9425 + attribute \src "libresoc.v:167540.3-167541.51" + wire $0\alu_op__rc__rc$6[0:0]$9372 + attribute \src "libresoc.v:167067.7-167067.32" + wire $0\alu_op__rc__rc$6[0:0]$9514 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9426 + attribute \src "libresoc.v:167554.3-167555.59" + wire $0\alu_op__write_cr0$13[0:0]$9386 + attribute \src "libresoc.v:167076.7-167076.36" + wire $0\alu_op__write_cr0$13[0:0]$9516 + attribute \src "libresoc.v:167667.3-167708.6" + wire $0\alu_op__zero_a$11$next[0:0]$9427 + attribute \src "libresoc.v:167550.3-167551.53" + wire $0\alu_op__zero_a$11[0:0]$9382 + attribute \src "libresoc.v:167085.7-167085.33" + wire $0\alu_op__zero_a$11[0:0]$9518 + attribute \src "libresoc.v:167728.3-167746.6" + wire width 4 $0\cr_a$22$next[3:0]$9459 + attribute \src "libresoc.v:167524.3-167525.33" + wire width 4 $0\cr_a$22[3:0]$9356 + attribute \src "libresoc.v:167098.13-167098.29" + wire width 4 $0\cr_a$22[3:0]$9520 + attribute \src "libresoc.v:167728.3-167746.6" + wire $0\cr_a_ok$23$next[0:0]$9460 + attribute \src "libresoc.v:167526.3-167527.39" + wire $0\cr_a_ok$23[0:0]$9358 + attribute \src "libresoc.v:167107.7-167107.26" + wire $0\cr_a_ok$23[0:0]$9522 + attribute \src "libresoc.v:166649.7-166649.20" wire $0\initial[0:0] - attribute \src "libresoc.v:174028.3-174046.6" - wire width 64 $0\msr$next[63:0]$9802 - attribute \src "libresoc.v:173814.3-173815.23" - wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:174028.3-174046.6" - wire $0\msr_ok$next[0:0]$9803 - attribute \src "libresoc.v:173816.3-173817.29" - wire $0\msr_ok[0:0] - attribute \src "libresoc.v:173918.3-173930.6" - wire width 2 $0\muxid$1$next[1:0]$9756 - attribute \src "libresoc.v:173852.3-173853.33" - wire width 2 $0\muxid$1[1:0]$9749 - attribute \src "libresoc.v:173413.13-173413.29" - wire width 2 $0\muxid$1[1:0]$9817 - attribute \src "libresoc.v:174009.3-174027.6" - wire width 64 $0\nia$next[63:0]$9796 - attribute \src "libresoc.v:173818.3-173819.23" - wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:174009.3-174027.6" - wire $0\nia_ok$next[0:0]$9797 - attribute \src "libresoc.v:173820.3-173821.29" - wire $0\nia_ok[0:0] - attribute \src "libresoc.v:173952.3-173970.6" - wire width 64 $0\o$next[63:0]$9778 - attribute \src "libresoc.v:173830.3-173831.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:173952.3-173970.6" - wire $0\o_ok$next[0:0]$9779 - attribute \src "libresoc.v:173832.3-173833.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:173900.3-173917.6" - wire $0\r_busy$next[0:0]$9752 - attribute \src "libresoc.v:173854.3-173855.29" + attribute \src "libresoc.v:167654.3-167666.6" + wire width 2 $0\muxid$1$next[1:0]$9407 + attribute \src "libresoc.v:167568.3-167569.33" + wire width 2 $0\muxid$1[1:0]$9400 + attribute \src "libresoc.v:167118.13-167118.29" + wire width 2 $0\muxid$1[1:0]$9524 + attribute \src "libresoc.v:167709.3-167727.6" + wire width 64 $0\o$20$next[63:0]$9453 + attribute \src "libresoc.v:167528.3-167529.27" + wire width 64 $0\o$20[63:0]$9360 + attribute \src "libresoc.v:167133.14-167133.43" + wire width 64 $0\o$20[63:0]$9526 + attribute \src "libresoc.v:167709.3-167727.6" + wire $0\o_ok$21$next[0:0]$9454 + attribute \src "libresoc.v:167530.3-167531.33" + wire $0\o_ok$21[0:0]$9362 + attribute \src "libresoc.v:167142.7-167142.23" + wire $0\o_ok$21[0:0]$9528 + attribute \src "libresoc.v:167636.3-167653.6" + wire $0\r_busy$next[0:0]$9403 + attribute \src "libresoc.v:167570.3-167571.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:173931.3-173951.6" - wire width 64 $0\trap_op__cia$6$next[63:0]$9759 - attribute \src "libresoc.v:173842.3-173843.47" - wire width 64 $0\trap_op__cia$6[63:0]$9739 - attribute \src "libresoc.v:173474.14-173474.53" - wire width 64 $0\trap_op__cia$6[63:0]$9824 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 13 $0\trap_op__fn_unit$3$next[12:0]$9760 - attribute \src "libresoc.v:173836.3-173837.55" - wire width 13 $0\trap_op__fn_unit$3[12:0]$9733 - attribute \src "libresoc.v:173509.14-173509.45" - wire width 13 $0\trap_op__fn_unit$3[12:0]$9826 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 32 $0\trap_op__insn$4$next[31:0]$9761 - attribute \src "libresoc.v:173838.3-173839.49" - wire width 32 $0\trap_op__insn$4[31:0]$9735 - attribute \src "libresoc.v:173534.14-173534.39" - wire width 32 $0\trap_op__insn$4[31:0]$9828 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 7 $0\trap_op__insn_type$2$next[6:0]$9762 - attribute \src "libresoc.v:173834.3-173835.59" - wire width 7 $0\trap_op__insn_type$2[6:0]$9731 - attribute \src "libresoc.v:173689.13-173689.43" - wire width 7 $0\trap_op__insn_type$2[6:0]$9830 - attribute \src "libresoc.v:173931.3-173951.6" - wire $0\trap_op__is_32bit$7$next[0:0]$9763 - attribute \src "libresoc.v:173844.3-173845.57" - wire $0\trap_op__is_32bit$7[0:0]$9741 - attribute \src "libresoc.v:173774.7-173774.35" - wire $0\trap_op__is_32bit$7[0:0]$9832 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9764 - attribute \src "libresoc.v:173850.3-173851.59" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9747 - attribute \src "libresoc.v:173781.13-173781.43" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9834 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 64 $0\trap_op__msr$5$next[63:0]$9765 - attribute \src "libresoc.v:173840.3-173841.47" - wire width 64 $0\trap_op__msr$5[63:0]$9737 - attribute \src "libresoc.v:173792.14-173792.53" - wire width 64 $0\trap_op__msr$5[63:0]$9836 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9766 - attribute \src "libresoc.v:173848.3-173849.57" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9745 - attribute \src "libresoc.v:173801.14-173801.46" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9838 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 8 $0\trap_op__traptype$8$next[7:0]$9767 - attribute \src "libresoc.v:173846.3-173847.57" - wire width 8 $0\trap_op__traptype$8[7:0]$9743 - attribute \src "libresoc.v:173810.13-173810.42" - wire width 8 $0\trap_op__traptype$8[7:0]$9840 - attribute \src "libresoc.v:173971.3-173989.6" - wire width 64 $1\fast1$11$next[63:0]$9787 - attribute \src "libresoc.v:173971.3-173989.6" - wire $1\fast1_ok$next[0:0]$9786 - attribute \src "libresoc.v:173130.7-173130.22" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:173990.3-174008.6" - wire width 64 $1\fast2$12$next[63:0]$9793 - attribute \src "libresoc.v:173990.3-174008.6" - wire $1\fast2_ok$next[0:0]$9792 - attribute \src "libresoc.v:173146.7-173146.22" - wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:174028.3-174046.6" - wire width 64 $1\msr$next[63:0]$9804 - attribute \src "libresoc.v:173397.14-173397.40" - wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:174028.3-174046.6" - wire $1\msr_ok$next[0:0]$9805 - attribute \src "libresoc.v:173404.7-173404.20" - wire $1\msr_ok[0:0] - attribute \src "libresoc.v:173918.3-173930.6" - wire width 2 $1\muxid$1$next[1:0]$9757 - attribute \src "libresoc.v:174009.3-174027.6" - wire width 64 $1\nia$next[63:0]$9798 - attribute \src "libresoc.v:173426.14-173426.40" - wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:174009.3-174027.6" - wire $1\nia_ok$next[0:0]$9799 - attribute \src "libresoc.v:173433.7-173433.20" - wire $1\nia_ok[0:0] - attribute \src "libresoc.v:173952.3-173970.6" - wire width 64 $1\o$next[63:0]$9780 - attribute \src "libresoc.v:173440.14-173440.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:173952.3-173970.6" - wire $1\o_ok$next[0:0]$9781 - attribute \src "libresoc.v:173447.7-173447.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:173900.3-173917.6" - wire $1\r_busy$next[0:0]$9753 - attribute \src "libresoc.v:173461.7-173461.20" + attribute \src "libresoc.v:167747.3-167765.6" + wire width 2 $0\xer_ca$24$next[1:0]$9465 + attribute \src "libresoc.v:167520.3-167521.37" + wire width 2 $0\xer_ca$24[1:0]$9352 + attribute \src "libresoc.v:167455.13-167455.31" + wire width 2 $0\xer_ca$24[1:0]$9531 + attribute \src "libresoc.v:167747.3-167765.6" + wire $0\xer_ca_ok$25$next[0:0]$9466 + attribute \src "libresoc.v:167522.3-167523.43" + wire $0\xer_ca_ok$25[0:0]$9354 + attribute \src "libresoc.v:167464.7-167464.28" + wire $0\xer_ca_ok$25[0:0]$9533 + attribute \src "libresoc.v:167766.3-167784.6" + wire width 2 $0\xer_ov$26$next[1:0]$9471 + attribute \src "libresoc.v:167516.3-167517.37" + wire width 2 $0\xer_ov$26[1:0]$9348 + attribute \src "libresoc.v:167475.13-167475.31" + wire width 2 $0\xer_ov$26[1:0]$9535 + attribute \src "libresoc.v:167766.3-167784.6" + wire $0\xer_ov_ok$27$next[0:0]$9472 + attribute \src "libresoc.v:167518.3-167519.43" + wire $0\xer_ov_ok$27[0:0]$9350 + attribute \src "libresoc.v:167484.7-167484.28" + wire $0\xer_ov_ok$27[0:0]$9537 + attribute \src "libresoc.v:167785.3-167803.6" + wire $0\xer_so$28$next[0:0]$9477 + attribute \src "libresoc.v:167512.3-167513.37" + wire $0\xer_so$28[0:0]$9344 + attribute \src "libresoc.v:167495.7-167495.25" + wire $0\xer_so$28[0:0]$9539 + attribute \src "libresoc.v:167785.3-167803.6" + wire $0\xer_so_ok$29$next[0:0]$9478 + attribute \src "libresoc.v:167514.3-167515.43" + wire $0\xer_so_ok$29[0:0]$9346 + attribute \src "libresoc.v:167504.7-167504.28" + wire $0\xer_so_ok$29[0:0]$9541 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$9428 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 13 $1\alu_op__fn_unit$3$next[12:0]$9429 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9430 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$9431 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$9432 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$9433 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$9434 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__invert_in$10$next[0:0]$9435 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__invert_out$12$next[0:0]$9436 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__is_32bit$16$next[0:0]$9437 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__is_signed$17$next[0:0]$9438 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9439 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9440 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__output_carry$15$next[0:0]$9441 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9442 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9443 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9444 + attribute \src "libresoc.v:167667.3-167708.6" + wire $1\alu_op__zero_a$11$next[0:0]$9445 + attribute \src "libresoc.v:167728.3-167746.6" + wire width 4 $1\cr_a$22$next[3:0]$9461 + attribute \src "libresoc.v:167728.3-167746.6" + wire $1\cr_a_ok$23$next[0:0]$9462 + attribute \src "libresoc.v:167654.3-167666.6" + wire width 2 $1\muxid$1$next[1:0]$9408 + attribute \src "libresoc.v:167709.3-167727.6" + wire width 64 $1\o$20$next[63:0]$9455 + attribute \src "libresoc.v:167709.3-167727.6" + wire $1\o_ok$21$next[0:0]$9456 + attribute \src "libresoc.v:167636.3-167653.6" + wire $1\r_busy$next[0:0]$9404 + attribute \src "libresoc.v:167448.7-167448.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:173931.3-173951.6" - wire width 64 $1\trap_op__cia$6$next[63:0]$9768 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 13 $1\trap_op__fn_unit$3$next[12:0]$9769 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 32 $1\trap_op__insn$4$next[31:0]$9770 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 7 $1\trap_op__insn_type$2$next[6:0]$9771 - attribute \src "libresoc.v:173931.3-173951.6" - wire $1\trap_op__is_32bit$7$next[0:0]$9772 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9773 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 64 $1\trap_op__msr$5$next[63:0]$9774 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9775 - attribute \src "libresoc.v:173931.3-173951.6" - wire width 8 $1\trap_op__traptype$8$next[7:0]$9776 - attribute \src "libresoc.v:173971.3-173989.6" - wire $2\fast1_ok$next[0:0]$9788 - attribute \src "libresoc.v:173990.3-174008.6" - wire $2\fast2_ok$next[0:0]$9794 - attribute \src "libresoc.v:174028.3-174046.6" - wire $2\msr_ok$next[0:0]$9806 - attribute \src "libresoc.v:174009.3-174027.6" - wire $2\nia_ok$next[0:0]$9800 - attribute \src "libresoc.v:173952.3-173970.6" - wire $2\o_ok$next[0:0]$9782 - attribute \src "libresoc.v:173900.3-173917.6" - wire $2\r_busy$next[0:0]$9754 - attribute \src "libresoc.v:173813.18-173813.118" - wire $and$libresoc.v:173813$9717_Y + attribute \src "libresoc.v:167747.3-167765.6" + wire width 2 $1\xer_ca$24$next[1:0]$9467 + attribute \src "libresoc.v:167747.3-167765.6" + wire $1\xer_ca_ok$25$next[0:0]$9468 + attribute \src "libresoc.v:167766.3-167784.6" + wire width 2 $1\xer_ov$26$next[1:0]$9473 + attribute \src "libresoc.v:167766.3-167784.6" + wire $1\xer_ov_ok$27$next[0:0]$9474 + attribute \src "libresoc.v:167785.3-167803.6" + wire $1\xer_so$28$next[0:0]$9479 + attribute \src "libresoc.v:167785.3-167803.6" + wire $1\xer_so_ok$29$next[0:0]$9480 + attribute \src "libresoc.v:167667.3-167708.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9446 + attribute \src "libresoc.v:167667.3-167708.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9447 + attribute \src "libresoc.v:167667.3-167708.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9448 + attribute \src "libresoc.v:167667.3-167708.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9449 + attribute \src "libresoc.v:167667.3-167708.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9450 + attribute \src "libresoc.v:167667.3-167708.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9451 + attribute \src "libresoc.v:167728.3-167746.6" + wire $2\cr_a_ok$23$next[0:0]$9463 + attribute \src "libresoc.v:167709.3-167727.6" + wire $2\o_ok$21$next[0:0]$9457 + attribute \src "libresoc.v:167636.3-167653.6" + wire $2\r_busy$next[0:0]$9405 + attribute \src "libresoc.v:167747.3-167765.6" + wire $2\xer_ca_ok$25$next[0:0]$9469 + attribute \src "libresoc.v:167766.3-167784.6" + wire $2\xer_ov_ok$27$next[0:0]$9475 + attribute \src "libresoc.v:167785.3-167803.6" + wire $2\xer_so_ok$29$next[0:0]$9481 + attribute \src "libresoc.v:167511.18-167511.118" + wire $and$libresoc.v:167511$9342_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 16 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 32 \fast1$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast1$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast1$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 33 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast1_ok$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 34 \fast2$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast2$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \fast2$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 35 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast2_ok$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fast2_ok$next - attribute \src "libresoc.v:173112.7-173112.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_fast1$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_fast2$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \main_muxid$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb + wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia + wire width 4 input 21 \alu_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia$18 + wire width 4 output 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$79 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -353779,7 +344850,7 @@ module \pipe2$35 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__fn_unit + wire width 13 input 6 \alu_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -353795,11 +344866,69 @@ module \pipe2$35 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__fn_unit$15 + wire width 13 output 37 \alu_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn + wire width 13 \alu_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn$16 + wire width 13 \alu_op__fn_unit$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$66 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 48 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$14$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$80 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -353875,7 +345004,7 @@ module \pipe2$35 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__insn_type + wire width 7 input 5 \alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -353951,159 +345080,9 @@ module \pipe2$35 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__insn_type$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_trap_op__is_32bit$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \main_trap_op__ldst_exc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \main_trap_op__ldst_exc$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__msr$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__trapaddr$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \main_trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \main_trap_op__traptype$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 38 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \msr$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 39 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \msr_ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \msr_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 20 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 19 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 18 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 36 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \nia$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 37 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \nia_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \nia_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 30 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 31 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 15 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \trap_op__cia$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$6$next - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \trap_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 22 \trap_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__fn_unit$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 23 \trap_op__insn$4 + wire width 7 output 36 \alu_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$4$next + wire width 7 \alu_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -354179,7 +345158,209 @@ module \pipe2$35 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \trap_op__insn_type + wire width 7 \alu_op__insn_type$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 64 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$84 + attribute \src "libresoc.v:166649.7-166649.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len$47 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_alu_op__fn_unit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn$48 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -354255,9 +345436,7 @@ module \pipe2$35 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 21 \trap_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$2$next + wire width 7 \output_alu_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -354333,440 +345512,701 @@ module \pipe2$35 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$29 + wire width 7 \output_alu_op__insn_type$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \trap_op__is_32bit + wire \output_alu_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$34 + wire \output_alu_op__invert_in$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \trap_op__is_32bit$7 + wire \output_alu_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$7$next + wire \output_alu_op__invert_out$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 13 \trap_op__ldst_exc + wire \output_alu_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 29 \trap_op__ldst_exc$10 + wire \output_alu_op__is_32bit$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$10$next + wire \output_alu_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$37 + wire \output_alu_op__is_signed$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \trap_op__msr + wire \output_alu_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$32 + wire \output_alu_op__oe__oe$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \trap_op__msr$5 + wire \output_alu_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$5$next + wire \output_alu_op__oe__ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 12 \trap_op__trapaddr + wire \output_alu_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$36 + wire \output_alu_op__output_carry$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 28 \trap_op__trapaddr$9 + wire \output_alu_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$9$next + wire \output_alu_op__rc__ok$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 11 \trap_op__traptype + wire \output_alu_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$35 + wire \output_alu_op__rc__rc$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 27 \trap_op__traptype$8 + wire \output_alu_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$8$next + wire \output_alu_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 58 \xer_ca$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 59 \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 60 \xer_ov$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 61 \xer_ov_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$27$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 62 \xer_so$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$28$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 63 \xer_so_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:173813$9717 + cell $and $and$libresoc.v:167511$9342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$25 + connect \A \p_valid_i$59 connect \B \p_ready_o - connect \Y $and$libresoc.v:173813$9717_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:173856.13-173891.4" - cell \main$38 \main - connect \fast1 \main_fast1 - connect \fast1$11 \main_fast1$23 - connect \fast1_ok \main_fast1_ok - connect \fast2 \main_fast2 - connect \fast2$12 \main_fast2$24 - connect \fast2_ok \main_fast2_ok - connect \msr \main_msr - connect \msr_ok \main_msr_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$13 - connect \nia \main_nia - connect \nia_ok \main_nia_ok - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \trap_op__cia \main_trap_op__cia - connect \trap_op__cia$6 \main_trap_op__cia$18 - connect \trap_op__fn_unit \main_trap_op__fn_unit - connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$15 - connect \trap_op__insn \main_trap_op__insn - connect \trap_op__insn$4 \main_trap_op__insn$16 - connect \trap_op__insn_type \main_trap_op__insn_type - connect \trap_op__insn_type$2 \main_trap_op__insn_type$14 - connect \trap_op__is_32bit \main_trap_op__is_32bit - connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$19 - connect \trap_op__ldst_exc \main_trap_op__ldst_exc - connect \trap_op__ldst_exc$10 \main_trap_op__ldst_exc$22 - connect \trap_op__msr \main_trap_op__msr - connect \trap_op__msr$5 \main_trap_op__msr$17 - connect \trap_op__trapaddr \main_trap_op__trapaddr - connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$21 - connect \trap_op__traptype \main_trap_op__traptype - connect \trap_op__traptype$8 \main_trap_op__traptype$20 + connect \Y $and$libresoc.v:167511$9342_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:173892.10-173895.4" - cell \n$37 \n + attribute \src "libresoc.v:167572.9-167575.4" + cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:173896.10-173899.4" - cell \p$36 \p + attribute \src "libresoc.v:167576.12-167631.4" + cell \output \output + connect \alu_op__data_len \output_alu_op__data_len + connect \alu_op__data_len$18 \output_alu_op__data_len$47 + connect \alu_op__fn_unit \output_alu_op__fn_unit + connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 + connect \alu_op__imm_data__data \output_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 + connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 + connect \alu_op__input_carry \output_alu_op__input_carry + connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 + connect \alu_op__insn \output_alu_op__insn + connect \alu_op__insn$19 \output_alu_op__insn$48 + connect \alu_op__insn_type \output_alu_op__insn_type + connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 + connect \alu_op__invert_in \output_alu_op__invert_in + connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 + connect \alu_op__invert_out \output_alu_op__invert_out + connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 + connect \alu_op__is_32bit \output_alu_op__is_32bit + connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 + connect \alu_op__is_signed \output_alu_op__is_signed + connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 + connect \alu_op__oe__oe \output_alu_op__oe__oe + connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 + connect \alu_op__oe__ok \output_alu_op__oe__ok + connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 + connect \alu_op__output_carry \output_alu_op__output_carry + connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 + connect \alu_op__rc__ok \output_alu_op__rc__ok + connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 + connect \alu_op__rc__rc \output_alu_op__rc__rc + connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 + connect \alu_op__write_cr0 \output_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 + connect \alu_op__zero_a \output_alu_op__zero_a + connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$51 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$30 + connect \o \output_o + connect \o$20 \output_o$49 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$50 + connect \xer_ca \output_xer_ca + connect \xer_ca$23 \output_xer_ca$52 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_ov \output_xer_ov + connect \xer_ov$24 \output_xer_ov$53 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$25 \output_xer_so$54 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:167632.9-167635.4" + cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:173112.7-173112.20" - process $proc$libresoc.v:173112$9807 + attribute \src "libresoc.v:166649.7-166649.20" + process $proc$libresoc.v:166649$9482 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173123.14-173123.47" - process $proc$libresoc.v:173123$9808 + attribute \src "libresoc.v:166656.13-166656.41" + process $proc$libresoc.v:166656$9483 assign { } { } - assign $0\fast1$11[63:0]$9809 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__data_len$18[3:0]$9484 4'0000 sync always sync init - update \fast1$11 $0\fast1$11[63:0]$9809 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9484 end - attribute \src "libresoc.v:173130.7-173130.22" - process $proc$libresoc.v:173130$9810 + attribute \src "libresoc.v:166693.14-166693.44" + process $proc$libresoc.v:166693$9485 assign { } { } - assign $1\fast1_ok[0:0] 1'0 + assign $0\alu_op__fn_unit$3[12:0]$9486 13'0000000000000 sync always sync init - update \fast1_ok $1\fast1_ok[0:0] + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9486 end - attribute \src "libresoc.v:173139.14-173139.47" - process $proc$libresoc.v:173139$9811 + attribute \src "libresoc.v:166716.14-166716.63" + process $proc$libresoc.v:166716$9487 assign { } { } - assign $0\fast2$12[63:0]$9812 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__imm_data__data$4[63:0]$9488 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$12 $0\fast2$12[63:0]$9812 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9488 end - attribute \src "libresoc.v:173146.7-173146.22" - process $proc$libresoc.v:173146$9813 + attribute \src "libresoc.v:166725.7-166725.38" + process $proc$libresoc.v:166725$9489 assign { } { } - assign $1\fast2_ok[0:0] 1'0 + assign $0\alu_op__imm_data__ok$5[0:0]$9490 1'0 sync always sync init - update \fast2_ok $1\fast2_ok[0:0] + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9490 end - attribute \src "libresoc.v:173397.14-173397.40" - process $proc$libresoc.v:173397$9814 + attribute \src "libresoc.v:166742.13-166742.44" + process $proc$libresoc.v:166742$9491 assign { } { } - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__input_carry$14[1:0]$9492 2'00 sync always sync init - update \msr $1\msr[63:0] + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9492 end - attribute \src "libresoc.v:173404.7-173404.20" - process $proc$libresoc.v:173404$9815 + attribute \src "libresoc.v:166755.14-166755.39" + process $proc$libresoc.v:166755$9493 assign { } { } - assign $1\msr_ok[0:0] 1'0 + assign $0\alu_op__insn$19[31:0]$9494 0 sync always sync init - update \msr_ok $1\msr_ok[0:0] + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9494 end - attribute \src "libresoc.v:173413.13-173413.29" - process $proc$libresoc.v:173413$9816 + attribute \src "libresoc.v:166912.13-166912.42" + process $proc$libresoc.v:166912$9495 assign { } { } - assign $0\muxid$1[1:0]$9817 2'00 + assign $0\alu_op__insn_type$2[6:0]$9496 7'0000000 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9817 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9496 end - attribute \src "libresoc.v:173426.14-173426.40" - process $proc$libresoc.v:173426$9818 + attribute \src "libresoc.v:166995.7-166995.36" + process $proc$libresoc.v:166995$9497 assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__invert_in$10[0:0]$9498 1'0 sync always sync init - update \nia $1\nia[63:0] + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9498 end - attribute \src "libresoc.v:173433.7-173433.20" - process $proc$libresoc.v:173433$9819 + attribute \src "libresoc.v:167004.7-167004.37" + process $proc$libresoc.v:167004$9499 assign { } { } - assign $1\nia_ok[0:0] 1'0 + assign $0\alu_op__invert_out$12[0:0]$9500 1'0 sync always sync init - update \nia_ok $1\nia_ok[0:0] + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9500 end - attribute \src "libresoc.v:173440.14-173440.38" - process $proc$libresoc.v:173440$9820 + attribute \src "libresoc.v:167013.7-167013.35" + process $proc$libresoc.v:167013$9501 assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__is_32bit$16[0:0]$9502 1'0 sync always sync init - update \o $1\o[63:0] + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9502 end - attribute \src "libresoc.v:173447.7-173447.18" - process $proc$libresoc.v:173447$9821 + attribute \src "libresoc.v:167022.7-167022.36" + process $proc$libresoc.v:167022$9503 assign { } { } - assign $1\o_ok[0:0] 1'0 + assign $0\alu_op__is_signed$17[0:0]$9504 1'0 sync always sync init - update \o_ok $1\o_ok[0:0] + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9504 end - attribute \src "libresoc.v:173461.7-173461.20" - process $proc$libresoc.v:173461$9822 + attribute \src "libresoc.v:167033.7-167033.32" + process $proc$libresoc.v:167033$9505 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $0\alu_op__oe__oe$8[0:0]$9506 1'0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9506 end - attribute \src "libresoc.v:173474.14-173474.53" - process $proc$libresoc.v:173474$9823 + attribute \src "libresoc.v:167042.7-167042.32" + process $proc$libresoc.v:167042$9507 assign { } { } - assign $0\trap_op__cia$6[63:0]$9824 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__oe__ok$9[0:0]$9508 1'0 sync always sync init - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9824 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9508 end - attribute \src "libresoc.v:173509.14-173509.45" - process $proc$libresoc.v:173509$9825 + attribute \src "libresoc.v:167049.7-167049.39" + process $proc$libresoc.v:167049$9509 assign { } { } - assign $0\trap_op__fn_unit$3[12:0]$9826 13'0000000000000 + assign $0\alu_op__output_carry$15[0:0]$9510 1'0 sync always sync init - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9826 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9510 end - attribute \src "libresoc.v:173534.14-173534.39" - process $proc$libresoc.v:173534$9827 + attribute \src "libresoc.v:167060.7-167060.32" + process $proc$libresoc.v:167060$9511 assign { } { } - assign $0\trap_op__insn$4[31:0]$9828 0 + assign $0\alu_op__rc__ok$7[0:0]$9512 1'0 sync always sync init - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9828 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9512 end - attribute \src "libresoc.v:173689.13-173689.43" - process $proc$libresoc.v:173689$9829 + attribute \src "libresoc.v:167067.7-167067.32" + process $proc$libresoc.v:167067$9513 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9830 7'0000000 + assign $0\alu_op__rc__rc$6[0:0]$9514 1'0 sync always sync init - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9830 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9514 end - attribute \src "libresoc.v:173774.7-173774.35" - process $proc$libresoc.v:173774$9831 + attribute \src "libresoc.v:167076.7-167076.36" + process $proc$libresoc.v:167076$9515 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9832 1'0 + assign $0\alu_op__write_cr0$13[0:0]$9516 1'0 sync always sync init - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9832 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9516 end - attribute \src "libresoc.v:173781.13-173781.43" - process $proc$libresoc.v:173781$9833 + attribute \src "libresoc.v:167085.7-167085.33" + process $proc$libresoc.v:167085$9517 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9834 8'00000000 + assign $0\alu_op__zero_a$11[0:0]$9518 1'0 sync always sync init - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9834 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9518 end - attribute \src "libresoc.v:173792.14-173792.53" - process $proc$libresoc.v:173792$9835 + attribute \src "libresoc.v:167098.13-167098.29" + process $proc$libresoc.v:167098$9519 assign { } { } - assign $0\trap_op__msr$5[63:0]$9836 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\cr_a$22[3:0]$9520 4'0000 sync always sync init - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9836 + update \cr_a$22 $0\cr_a$22[3:0]$9520 end - attribute \src "libresoc.v:173801.14-173801.46" - process $proc$libresoc.v:173801$9837 + attribute \src "libresoc.v:167107.7-167107.26" + process $proc$libresoc.v:167107$9521 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9838 13'0000000000000 + assign $0\cr_a_ok$23[0:0]$9522 1'0 sync always sync init - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9838 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9522 end - attribute \src "libresoc.v:173810.13-173810.42" - process $proc$libresoc.v:173810$9839 + attribute \src "libresoc.v:167118.13-167118.29" + process $proc$libresoc.v:167118$9523 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9840 8'00000000 + assign $0\muxid$1[1:0]$9524 2'00 sync always sync init - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9840 + update \muxid$1 $0\muxid$1[1:0]$9524 end - attribute \src "libresoc.v:173814.3-173815.23" - process $proc$libresoc.v:173814$9718 + attribute \src "libresoc.v:167133.14-167133.43" + process $proc$libresoc.v:167133$9525 assign { } { } - assign $0\msr[63:0] \msr$next + assign $0\o$20[63:0]$9526 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$9526 + end + attribute \src "libresoc.v:167142.7-167142.23" + process $proc$libresoc.v:167142$9527 + assign { } { } + assign $0\o_ok$21[0:0]$9528 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$9528 + end + attribute \src "libresoc.v:167448.7-167448.20" + process $proc$libresoc.v:167448$9529 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:167455.13-167455.31" + process $proc$libresoc.v:167455$9530 + assign { } { } + assign $0\xer_ca$24[1:0]$9531 2'00 + sync always + sync init + update \xer_ca$24 $0\xer_ca$24[1:0]$9531 + end + attribute \src "libresoc.v:167464.7-167464.28" + process $proc$libresoc.v:167464$9532 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$9533 1'0 + sync always + sync init + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9533 + end + attribute \src "libresoc.v:167475.13-167475.31" + process $proc$libresoc.v:167475$9534 + assign { } { } + assign $0\xer_ov$26[1:0]$9535 2'00 + sync always + sync init + update \xer_ov$26 $0\xer_ov$26[1:0]$9535 + end + attribute \src "libresoc.v:167484.7-167484.28" + process $proc$libresoc.v:167484$9536 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$9537 1'0 + sync always + sync init + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9537 + end + attribute \src "libresoc.v:167495.7-167495.25" + process $proc$libresoc.v:167495$9538 + assign { } { } + assign $0\xer_so$28[0:0]$9539 1'0 + sync always + sync init + update \xer_so$28 $0\xer_so$28[0:0]$9539 + end + attribute \src "libresoc.v:167504.7-167504.28" + process $proc$libresoc.v:167504$9540 + assign { } { } + assign $0\xer_so_ok$29[0:0]$9541 1'0 + sync always + sync init + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9541 + end + attribute \src "libresoc.v:167512.3-167513.37" + process $proc$libresoc.v:167512$9343 + assign { } { } + assign $0\xer_so$28[0:0]$9344 \xer_so$28$next sync posedge \coresync_clk - update \msr $0\msr[63:0] + update \xer_so$28 $0\xer_so$28[0:0]$9344 end - attribute \src "libresoc.v:173816.3-173817.29" - process $proc$libresoc.v:173816$9719 + attribute \src "libresoc.v:167514.3-167515.43" + process $proc$libresoc.v:167514$9345 assign { } { } - assign $0\msr_ok[0:0] \msr_ok$next + assign $0\xer_so_ok$29[0:0]$9346 \xer_so_ok$29$next sync posedge \coresync_clk - update \msr_ok $0\msr_ok[0:0] + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9346 end - attribute \src "libresoc.v:173818.3-173819.23" - process $proc$libresoc.v:173818$9720 + attribute \src "libresoc.v:167516.3-167517.37" + process $proc$libresoc.v:167516$9347 assign { } { } - assign $0\nia[63:0] \nia$next + assign $0\xer_ov$26[1:0]$9348 \xer_ov$26$next sync posedge \coresync_clk - update \nia $0\nia[63:0] + update \xer_ov$26 $0\xer_ov$26[1:0]$9348 end - attribute \src "libresoc.v:173820.3-173821.29" - process $proc$libresoc.v:173820$9721 + attribute \src "libresoc.v:167518.3-167519.43" + process $proc$libresoc.v:167518$9349 assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next + assign $0\xer_ov_ok$27[0:0]$9350 \xer_ov_ok$27$next sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9350 end - attribute \src "libresoc.v:173822.3-173823.35" - process $proc$libresoc.v:173822$9722 + attribute \src "libresoc.v:167520.3-167521.37" + process $proc$libresoc.v:167520$9351 assign { } { } - assign $0\fast2$12[63:0]$9723 \fast2$12$next + assign $0\xer_ca$24[1:0]$9352 \xer_ca$24$next sync posedge \coresync_clk - update \fast2$12 $0\fast2$12[63:0]$9723 + update \xer_ca$24 $0\xer_ca$24[1:0]$9352 end - attribute \src "libresoc.v:173824.3-173825.33" - process $proc$libresoc.v:173824$9724 + attribute \src "libresoc.v:167522.3-167523.43" + process $proc$libresoc.v:167522$9353 assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next + assign $0\xer_ca_ok$25[0:0]$9354 \xer_ca_ok$25$next + sync posedge \coresync_clk + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9354 + end + attribute \src "libresoc.v:167524.3-167525.33" + process $proc$libresoc.v:167524$9355 + assign { } { } + assign $0\cr_a$22[3:0]$9356 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$9356 + end + attribute \src "libresoc.v:167526.3-167527.39" + process $proc$libresoc.v:167526$9357 + assign { } { } + assign $0\cr_a_ok$23[0:0]$9358 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9358 + end + attribute \src "libresoc.v:167528.3-167529.27" + process $proc$libresoc.v:167528$9359 + assign { } { } + assign $0\o$20[63:0]$9360 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$9360 + end + attribute \src "libresoc.v:167530.3-167531.33" + process $proc$libresoc.v:167530$9361 + assign { } { } + assign $0\o_ok$21[0:0]$9362 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$9362 + end + attribute \src "libresoc.v:167532.3-167533.57" + process $proc$libresoc.v:167532$9363 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$9364 \alu_op__insn_type$2$next + sync posedge \coresync_clk + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9364 + end + attribute \src "libresoc.v:167534.3-167535.53" + process $proc$libresoc.v:167534$9365 + assign { } { } + assign $0\alu_op__fn_unit$3[12:0]$9366 \alu_op__fn_unit$3$next + sync posedge \coresync_clk + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9366 + end + attribute \src "libresoc.v:167536.3-167537.67" + process $proc$libresoc.v:167536$9367 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$9368 \alu_op__imm_data__data$4$next + sync posedge \coresync_clk + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9368 + end + attribute \src "libresoc.v:167538.3-167539.63" + process $proc$libresoc.v:167538$9369 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$9370 \alu_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9370 + end + attribute \src "libresoc.v:167540.3-167541.51" + process $proc$libresoc.v:167540$9371 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$9372 \alu_op__rc__rc$6$next sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9372 end - attribute \src "libresoc.v:173826.3-173827.35" - process $proc$libresoc.v:173826$9725 + attribute \src "libresoc.v:167542.3-167543.51" + process $proc$libresoc.v:167542$9373 assign { } { } - assign $0\fast1$11[63:0]$9726 \fast1$11$next + assign $0\alu_op__rc__ok$7[0:0]$9374 \alu_op__rc__ok$7$next sync posedge \coresync_clk - update \fast1$11 $0\fast1$11[63:0]$9726 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9374 end - attribute \src "libresoc.v:173828.3-173829.33" - process $proc$libresoc.v:173828$9727 + attribute \src "libresoc.v:167544.3-167545.51" + process $proc$libresoc.v:167544$9375 assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next + assign $0\alu_op__oe__oe$8[0:0]$9376 \alu_op__oe__oe$8$next sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9376 end - attribute \src "libresoc.v:173830.3-173831.19" - process $proc$libresoc.v:173830$9728 + attribute \src "libresoc.v:167546.3-167547.51" + process $proc$libresoc.v:167546$9377 assign { } { } - assign $0\o[63:0] \o$next + assign $0\alu_op__oe__ok$9[0:0]$9378 \alu_op__oe__ok$9$next sync posedge \coresync_clk - update \o $0\o[63:0] + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9378 end - attribute \src "libresoc.v:173832.3-173833.25" - process $proc$libresoc.v:173832$9729 + attribute \src "libresoc.v:167548.3-167549.59" + process $proc$libresoc.v:167548$9379 assign { } { } - assign $0\o_ok[0:0] \o_ok$next + assign $0\alu_op__invert_in$10[0:0]$9380 \alu_op__invert_in$10$next sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9380 end - attribute \src "libresoc.v:173834.3-173835.59" - process $proc$libresoc.v:173834$9730 + attribute \src "libresoc.v:167550.3-167551.53" + process $proc$libresoc.v:167550$9381 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9731 \trap_op__insn_type$2$next + assign $0\alu_op__zero_a$11[0:0]$9382 \alu_op__zero_a$11$next sync posedge \coresync_clk - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9731 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9382 end - attribute \src "libresoc.v:173836.3-173837.55" - process $proc$libresoc.v:173836$9732 + attribute \src "libresoc.v:167552.3-167553.61" + process $proc$libresoc.v:167552$9383 assign { } { } - assign $0\trap_op__fn_unit$3[12:0]$9733 \trap_op__fn_unit$3$next + assign $0\alu_op__invert_out$12[0:0]$9384 \alu_op__invert_out$12$next sync posedge \coresync_clk - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9733 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9384 end - attribute \src "libresoc.v:173838.3-173839.49" - process $proc$libresoc.v:173838$9734 + attribute \src "libresoc.v:167554.3-167555.59" + process $proc$libresoc.v:167554$9385 assign { } { } - assign $0\trap_op__insn$4[31:0]$9735 \trap_op__insn$4$next + assign $0\alu_op__write_cr0$13[0:0]$9386 \alu_op__write_cr0$13$next sync posedge \coresync_clk - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9735 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9386 end - attribute \src "libresoc.v:173840.3-173841.47" - process $proc$libresoc.v:173840$9736 + attribute \src "libresoc.v:167556.3-167557.63" + process $proc$libresoc.v:167556$9387 assign { } { } - assign $0\trap_op__msr$5[63:0]$9737 \trap_op__msr$5$next + assign $0\alu_op__input_carry$14[1:0]$9388 \alu_op__input_carry$14$next sync posedge \coresync_clk - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9737 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9388 end - attribute \src "libresoc.v:173842.3-173843.47" - process $proc$libresoc.v:173842$9738 + attribute \src "libresoc.v:167558.3-167559.65" + process $proc$libresoc.v:167558$9389 assign { } { } - assign $0\trap_op__cia$6[63:0]$9739 \trap_op__cia$6$next + assign $0\alu_op__output_carry$15[0:0]$9390 \alu_op__output_carry$15$next sync posedge \coresync_clk - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9739 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9390 end - attribute \src "libresoc.v:173844.3-173845.57" - process $proc$libresoc.v:173844$9740 + attribute \src "libresoc.v:167560.3-167561.57" + process $proc$libresoc.v:167560$9391 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9741 \trap_op__is_32bit$7$next + assign $0\alu_op__is_32bit$16[0:0]$9392 \alu_op__is_32bit$16$next sync posedge \coresync_clk - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9741 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9392 end - attribute \src "libresoc.v:173846.3-173847.57" - process $proc$libresoc.v:173846$9742 + attribute \src "libresoc.v:167562.3-167563.59" + process $proc$libresoc.v:167562$9393 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9743 \trap_op__traptype$8$next + assign $0\alu_op__is_signed$17[0:0]$9394 \alu_op__is_signed$17$next sync posedge \coresync_clk - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9743 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9394 end - attribute \src "libresoc.v:173848.3-173849.57" - process $proc$libresoc.v:173848$9744 + attribute \src "libresoc.v:167564.3-167565.57" + process $proc$libresoc.v:167564$9395 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9745 \trap_op__trapaddr$9$next + assign $0\alu_op__data_len$18[3:0]$9396 \alu_op__data_len$18$next sync posedge \coresync_clk - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9745 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9396 end - attribute \src "libresoc.v:173850.3-173851.59" - process $proc$libresoc.v:173850$9746 + attribute \src "libresoc.v:167566.3-167567.49" + process $proc$libresoc.v:167566$9397 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9747 \trap_op__ldst_exc$10$next + assign $0\alu_op__insn$19[31:0]$9398 \alu_op__insn$19$next sync posedge \coresync_clk - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9747 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9398 end - attribute \src "libresoc.v:173852.3-173853.33" - process $proc$libresoc.v:173852$9748 + attribute \src "libresoc.v:167568.3-167569.33" + process $proc$libresoc.v:167568$9399 assign { } { } - assign $0\muxid$1[1:0]$9749 \muxid$1$next + assign $0\muxid$1[1:0]$9400 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9749 + update \muxid$1 $0\muxid$1[1:0]$9400 end - attribute \src "libresoc.v:173854.3-173855.29" - process $proc$libresoc.v:173854$9750 + attribute \src "libresoc.v:167570.3-167571.29" + process $proc$libresoc.v:167570$9401 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:173900.3-173917.6" - process $proc$libresoc.v:173900$9751 + attribute \src "libresoc.v:167636.3-167653.6" + process $proc$libresoc.v:167636$9402 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9752 $2\r_busy$next[0:0]$9754 - attribute \src "libresoc.v:173901.5-173901.29" + assign $0\r_busy$next[0:0]$9403 $2\r_busy$next[0:0]$9405 + attribute \src "libresoc.v:167637.5-167637.29" switch \initial - attribute \src "libresoc.v:173901.9-173901.17" + attribute \src "libresoc.v:167637.9-167637.17" case 1'1 case end @@ -354775,34 +346215,34 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9753 1'1 + assign $1\r_busy$next[0:0]$9404 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9753 1'0 + assign $1\r_busy$next[0:0]$9404 1'0 case - assign $1\r_busy$next[0:0]$9753 \r_busy + assign $1\r_busy$next[0:0]$9404 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9754 1'0 + assign $2\r_busy$next[0:0]$9405 1'0 case - assign $2\r_busy$next[0:0]$9754 $1\r_busy$next[0:0]$9753 + assign $2\r_busy$next[0:0]$9405 $1\r_busy$next[0:0]$9404 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9752 + update \r_busy$next $0\r_busy$next[0:0]$9403 end - attribute \src "libresoc.v:173918.3-173930.6" - process $proc$libresoc.v:173918$9755 + attribute \src "libresoc.v:167654.3-167666.6" + process $proc$libresoc.v:167654$9406 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9756 $1\muxid$1$next[1:0]$9757 - attribute \src "libresoc.v:173919.5-173919.29" + assign $0\muxid$1$next[1:0]$9407 $1\muxid$1$next[1:0]$9408 + attribute \src "libresoc.v:167655.5-167655.29" switch \initial - attribute \src "libresoc.v:173919.9-173919.17" + attribute \src "libresoc.v:167655.9-167655.17" case 1'1 case end @@ -354811,19 +346251,28 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9757 \muxid$28 + assign $1\muxid$1$next[1:0]$9408 \muxid$62 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9757 \muxid$28 + assign $1\muxid$1$next[1:0]$9408 \muxid$62 case - assign $1\muxid$1$next[1:0]$9757 \muxid$1 + assign $1\muxid$1$next[1:0]$9408 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9756 + update \muxid$1$next $0\muxid$1$next[1:0]$9407 end - attribute \src "libresoc.v:173931.3-173951.6" - process $proc$libresoc.v:173931$9758 + attribute \src "libresoc.v:167667.3-167708.6" + process $proc$libresoc.v:167667$9409 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -354842,18 +346291,42 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$6$next[63:0]$9759 $1\trap_op__cia$6$next[63:0]$9768 - assign $0\trap_op__fn_unit$3$next[12:0]$9760 $1\trap_op__fn_unit$3$next[12:0]$9769 - assign $0\trap_op__insn$4$next[31:0]$9761 $1\trap_op__insn$4$next[31:0]$9770 - assign $0\trap_op__insn_type$2$next[6:0]$9762 $1\trap_op__insn_type$2$next[6:0]$9771 - assign $0\trap_op__is_32bit$7$next[0:0]$9763 $1\trap_op__is_32bit$7$next[0:0]$9772 - assign $0\trap_op__ldst_exc$10$next[7:0]$9764 $1\trap_op__ldst_exc$10$next[7:0]$9773 - assign $0\trap_op__msr$5$next[63:0]$9765 $1\trap_op__msr$5$next[63:0]$9774 - assign $0\trap_op__trapaddr$9$next[12:0]$9766 $1\trap_op__trapaddr$9$next[12:0]$9775 - assign $0\trap_op__traptype$8$next[7:0]$9767 $1\trap_op__traptype$8$next[7:0]$9776 - attribute \src "libresoc.v:173932.5-173932.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$18$next[3:0]$9410 $1\alu_op__data_len$18$next[3:0]$9428 + assign $0\alu_op__fn_unit$3$next[12:0]$9411 $1\alu_op__fn_unit$3$next[12:0]$9429 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$14$next[1:0]$9414 $1\alu_op__input_carry$14$next[1:0]$9432 + assign $0\alu_op__insn$19$next[31:0]$9415 $1\alu_op__insn$19$next[31:0]$9433 + assign $0\alu_op__insn_type$2$next[6:0]$9416 $1\alu_op__insn_type$2$next[6:0]$9434 + assign $0\alu_op__invert_in$10$next[0:0]$9417 $1\alu_op__invert_in$10$next[0:0]$9435 + assign $0\alu_op__invert_out$12$next[0:0]$9418 $1\alu_op__invert_out$12$next[0:0]$9436 + assign $0\alu_op__is_32bit$16$next[0:0]$9419 $1\alu_op__is_32bit$16$next[0:0]$9437 + assign $0\alu_op__is_signed$17$next[0:0]$9420 $1\alu_op__is_signed$17$next[0:0]$9438 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$15$next[0:0]$9423 $1\alu_op__output_carry$15$next[0:0]$9441 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$13$next[0:0]$9426 $1\alu_op__write_cr0$13$next[0:0]$9444 + assign $0\alu_op__zero_a$11$next[0:0]$9427 $1\alu_op__zero_a$11$next[0:0]$9445 + assign $0\alu_op__imm_data__data$4$next[63:0]$9412 $2\alu_op__imm_data__data$4$next[63:0]$9446 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9413 $2\alu_op__imm_data__ok$5$next[0:0]$9447 + assign $0\alu_op__oe__oe$8$next[0:0]$9421 $2\alu_op__oe__oe$8$next[0:0]$9448 + assign $0\alu_op__oe__ok$9$next[0:0]$9422 $2\alu_op__oe__ok$9$next[0:0]$9449 + assign $0\alu_op__rc__ok$7$next[0:0]$9424 $2\alu_op__rc__ok$7$next[0:0]$9450 + assign $0\alu_op__rc__rc$6$next[0:0]$9425 $2\alu_op__rc__rc$6$next[0:0]$9451 + attribute \src "libresoc.v:167668.5-167668.29" switch \initial - attribute \src "libresoc.v:173932.9-173932.17" + attribute \src "libresoc.v:167668.9-167668.17" case 1'1 case end @@ -354870,7 +346343,16 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9773 $1\trap_op__trapaddr$9$next[12:0]$9775 $1\trap_op__traptype$8$next[7:0]$9776 $1\trap_op__is_32bit$7$next[0:0]$9772 $1\trap_op__cia$6$next[63:0]$9768 $1\trap_op__msr$5$next[63:0]$9774 $1\trap_op__insn$4$next[31:0]$9770 $1\trap_op__fn_unit$3$next[12:0]$9769 $1\trap_op__insn_type$2$next[6:0]$9771 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9433 $1\alu_op__data_len$18$next[3:0]$9428 $1\alu_op__is_signed$17$next[0:0]$9438 $1\alu_op__is_32bit$16$next[0:0]$9437 $1\alu_op__output_carry$15$next[0:0]$9441 $1\alu_op__input_carry$14$next[1:0]$9432 $1\alu_op__write_cr0$13$next[0:0]$9444 $1\alu_op__invert_out$12$next[0:0]$9436 $1\alu_op__zero_a$11$next[0:0]$9445 $1\alu_op__invert_in$10$next[0:0]$9435 $1\alu_op__oe__ok$9$next[0:0]$9440 $1\alu_op__oe__oe$8$next[0:0]$9439 $1\alu_op__rc__ok$7$next[0:0]$9442 $1\alu_op__rc__rc$6$next[0:0]$9443 $1\alu_op__imm_data__ok$5$next[0:0]$9431 $1\alu_op__imm_data__data$4$next[63:0]$9430 $1\alu_op__fn_unit$3$next[12:0]$9429 $1\alu_op__insn_type$2$next[6:0]$9434 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -354882,41 +346364,92 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9773 $1\trap_op__trapaddr$9$next[12:0]$9775 $1\trap_op__traptype$8$next[7:0]$9776 $1\trap_op__is_32bit$7$next[0:0]$9772 $1\trap_op__cia$6$next[63:0]$9768 $1\trap_op__msr$5$next[63:0]$9774 $1\trap_op__insn$4$next[31:0]$9770 $1\trap_op__fn_unit$3$next[12:0]$9769 $1\trap_op__insn_type$2$next[6:0]$9771 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9433 $1\alu_op__data_len$18$next[3:0]$9428 $1\alu_op__is_signed$17$next[0:0]$9438 $1\alu_op__is_32bit$16$next[0:0]$9437 $1\alu_op__output_carry$15$next[0:0]$9441 $1\alu_op__input_carry$14$next[1:0]$9432 $1\alu_op__write_cr0$13$next[0:0]$9444 $1\alu_op__invert_out$12$next[0:0]$9436 $1\alu_op__zero_a$11$next[0:0]$9445 $1\alu_op__invert_in$10$next[0:0]$9435 $1\alu_op__oe__ok$9$next[0:0]$9440 $1\alu_op__oe__oe$8$next[0:0]$9439 $1\alu_op__rc__ok$7$next[0:0]$9442 $1\alu_op__rc__rc$6$next[0:0]$9443 $1\alu_op__imm_data__ok$5$next[0:0]$9431 $1\alu_op__imm_data__data$4$next[63:0]$9430 $1\alu_op__fn_unit$3$next[12:0]$9429 $1\alu_op__insn_type$2$next[6:0]$9434 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + case + assign $1\alu_op__data_len$18$next[3:0]$9428 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[12:0]$9429 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9430 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9431 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9432 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9433 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9434 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9435 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9436 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9437 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9438 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9439 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9440 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9441 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9442 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9443 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9444 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9445 \alu_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$4$next[63:0]$9446 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9447 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9451 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9450 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9448 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9449 1'0 case - assign $1\trap_op__cia$6$next[63:0]$9768 \trap_op__cia$6 - assign $1\trap_op__fn_unit$3$next[12:0]$9769 \trap_op__fn_unit$3 - assign $1\trap_op__insn$4$next[31:0]$9770 \trap_op__insn$4 - assign $1\trap_op__insn_type$2$next[6:0]$9771 \trap_op__insn_type$2 - assign $1\trap_op__is_32bit$7$next[0:0]$9772 \trap_op__is_32bit$7 - assign $1\trap_op__ldst_exc$10$next[7:0]$9773 \trap_op__ldst_exc$10 - assign $1\trap_op__msr$5$next[63:0]$9774 \trap_op__msr$5 - assign $1\trap_op__trapaddr$9$next[12:0]$9775 \trap_op__trapaddr$9 - assign $1\trap_op__traptype$8$next[7:0]$9776 \trap_op__traptype$8 + assign $2\alu_op__imm_data__data$4$next[63:0]$9446 $1\alu_op__imm_data__data$4$next[63:0]$9430 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9447 $1\alu_op__imm_data__ok$5$next[0:0]$9431 + assign $2\alu_op__oe__oe$8$next[0:0]$9448 $1\alu_op__oe__oe$8$next[0:0]$9439 + assign $2\alu_op__oe__ok$9$next[0:0]$9449 $1\alu_op__oe__ok$9$next[0:0]$9440 + assign $2\alu_op__rc__ok$7$next[0:0]$9450 $1\alu_op__rc__ok$7$next[0:0]$9442 + assign $2\alu_op__rc__rc$6$next[0:0]$9451 $1\alu_op__rc__rc$6$next[0:0]$9443 end sync always - update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9759 - update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[12:0]$9760 - update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9761 - update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9762 - update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9763 - update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9764 - update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9765 - update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9766 - update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9767 + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9410 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[12:0]$9411 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9412 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9413 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9414 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9415 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9416 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9417 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9418 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9419 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9420 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9421 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9422 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9423 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9424 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9425 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9426 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9427 end - attribute \src "libresoc.v:173952.3-173970.6" - process $proc$libresoc.v:173952$9777 + attribute \src "libresoc.v:167709.3-167727.6" + process $proc$libresoc.v:167709$9452 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9778 $1\o$next[63:0]$9780 + assign $0\o$20$next[63:0]$9453 $1\o$20$next[63:0]$9455 assign { } { } - assign $0\o_ok$next[0:0]$9779 $2\o_ok$next[0:0]$9782 - attribute \src "libresoc.v:173953.5-173953.29" + assign $0\o_ok$21$next[0:0]$9454 $2\o_ok$21$next[0:0]$9457 + attribute \src "libresoc.v:167710.5-167710.29" switch \initial - attribute \src "libresoc.v:173953.9-173953.17" + attribute \src "libresoc.v:167710.9-167710.17" case 1'1 case end @@ -354926,41 +346459,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9781 $1\o$next[63:0]$9780 } { \o_ok$39 \o$38 } + assign { $1\o_ok$21$next[0:0]$9456 $1\o$20$next[63:0]$9455 } { \o_ok$82 \o$81 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9781 $1\o$next[63:0]$9780 } { \o_ok$39 \o$38 } + assign { $1\o_ok$21$next[0:0]$9456 $1\o$20$next[63:0]$9455 } { \o_ok$82 \o$81 } case - assign $1\o$next[63:0]$9780 \o - assign $1\o_ok$next[0:0]$9781 \o_ok + assign $1\o$20$next[63:0]$9455 \o$20 + assign $1\o_ok$21$next[0:0]$9456 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9782 1'0 + assign $2\o_ok$21$next[0:0]$9457 1'0 case - assign $2\o_ok$next[0:0]$9782 $1\o_ok$next[0:0]$9781 + assign $2\o_ok$21$next[0:0]$9457 $1\o_ok$21$next[0:0]$9456 end sync always - update \o$next $0\o$next[63:0]$9778 - update \o_ok$next $0\o_ok$next[0:0]$9779 + update \o$20$next $0\o$20$next[63:0]$9453 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9454 end - attribute \src "libresoc.v:173971.3-173989.6" - process $proc$libresoc.v:173971$9783 + attribute \src "libresoc.v:167728.3-167746.6" + process $proc$libresoc.v:167728$9458 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\cr_a$22$next[3:0]$9459 $1\cr_a$22$next[3:0]$9461 assign { } { } - assign $0\fast1$11$next[63:0]$9785 $1\fast1$11$next[63:0]$9787 - assign $0\fast1_ok$next[0:0]$9784 $2\fast1_ok$next[0:0]$9788 - attribute \src "libresoc.v:173972.5-173972.29" + assign $0\cr_a_ok$23$next[0:0]$9460 $2\cr_a_ok$23$next[0:0]$9463 + attribute \src "libresoc.v:167729.5-167729.29" switch \initial - attribute \src "libresoc.v:173972.9-173972.17" + attribute \src "libresoc.v:167729.9-167729.17" case 1'1 case end @@ -354970,41 +346503,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9786 $1\fast1$11$next[63:0]$9787 } { \fast1_ok$41 \fast1$40 } + assign { $1\cr_a_ok$23$next[0:0]$9462 $1\cr_a$22$next[3:0]$9461 } { \cr_a_ok$84 \cr_a$83 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9786 $1\fast1$11$next[63:0]$9787 } { \fast1_ok$41 \fast1$40 } + assign { $1\cr_a_ok$23$next[0:0]$9462 $1\cr_a$22$next[3:0]$9461 } { \cr_a_ok$84 \cr_a$83 } case - assign $1\fast1_ok$next[0:0]$9786 \fast1_ok - assign $1\fast1$11$next[63:0]$9787 \fast1$11 + assign $1\cr_a$22$next[3:0]$9461 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9462 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$9788 1'0 + assign $2\cr_a_ok$23$next[0:0]$9463 1'0 case - assign $2\fast1_ok$next[0:0]$9788 $1\fast1_ok$next[0:0]$9786 + assign $2\cr_a_ok$23$next[0:0]$9463 $1\cr_a_ok$23$next[0:0]$9462 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$9784 - update \fast1$11$next $0\fast1$11$next[63:0]$9785 + update \cr_a$22$next $0\cr_a$22$next[3:0]$9459 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9460 end - attribute \src "libresoc.v:173990.3-174008.6" - process $proc$libresoc.v:173990$9789 + attribute \src "libresoc.v:167747.3-167765.6" + process $proc$libresoc.v:167747$9464 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\xer_ca$24$next[1:0]$9465 $1\xer_ca$24$next[1:0]$9467 assign { } { } - assign $0\fast2$12$next[63:0]$9791 $1\fast2$12$next[63:0]$9793 - assign $0\fast2_ok$next[0:0]$9790 $2\fast2_ok$next[0:0]$9794 - attribute \src "libresoc.v:173991.5-173991.29" + assign $0\xer_ca_ok$25$next[0:0]$9466 $2\xer_ca_ok$25$next[0:0]$9469 + attribute \src "libresoc.v:167748.5-167748.29" switch \initial - attribute \src "libresoc.v:173991.9-173991.17" + attribute \src "libresoc.v:167748.9-167748.17" case 1'1 case end @@ -355014,41 +346547,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9792 $1\fast2$12$next[63:0]$9793 } { \fast2_ok$43 \fast2$42 } + assign { $1\xer_ca_ok$25$next[0:0]$9468 $1\xer_ca$24$next[1:0]$9467 } { \xer_ca_ok$86 \xer_ca$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9792 $1\fast2$12$next[63:0]$9793 } { \fast2_ok$43 \fast2$42 } + assign { $1\xer_ca_ok$25$next[0:0]$9468 $1\xer_ca$24$next[1:0]$9467 } { \xer_ca_ok$86 \xer_ca$85 } case - assign $1\fast2_ok$next[0:0]$9792 \fast2_ok - assign $1\fast2$12$next[63:0]$9793 \fast2$12 + assign $1\xer_ca$24$next[1:0]$9467 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9468 \xer_ca_ok$25 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$9794 1'0 + assign $2\xer_ca_ok$25$next[0:0]$9469 1'0 case - assign $2\fast2_ok$next[0:0]$9794 $1\fast2_ok$next[0:0]$9792 + assign $2\xer_ca_ok$25$next[0:0]$9469 $1\xer_ca_ok$25$next[0:0]$9468 end sync always - update \fast2_ok$next $0\fast2_ok$next[0:0]$9790 - update \fast2$12$next $0\fast2$12$next[63:0]$9791 + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9465 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9466 end - attribute \src "libresoc.v:174009.3-174027.6" - process $proc$libresoc.v:174009$9795 + attribute \src "libresoc.v:167766.3-167784.6" + process $proc$libresoc.v:167766$9470 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$9796 $1\nia$next[63:0]$9798 + assign $0\xer_ov$26$next[1:0]$9471 $1\xer_ov$26$next[1:0]$9473 assign { } { } - assign $0\nia_ok$next[0:0]$9797 $2\nia_ok$next[0:0]$9800 - attribute \src "libresoc.v:174010.5-174010.29" + assign $0\xer_ov_ok$27$next[0:0]$9472 $2\xer_ov_ok$27$next[0:0]$9475 + attribute \src "libresoc.v:167767.5-167767.29" switch \initial - attribute \src "libresoc.v:174010.9-174010.17" + attribute \src "libresoc.v:167767.9-167767.17" case 1'1 case end @@ -355058,41 +346591,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9799 $1\nia$next[63:0]$9798 } { \nia_ok$45 \nia$44 } + assign { $1\xer_ov_ok$27$next[0:0]$9474 $1\xer_ov$26$next[1:0]$9473 } { \xer_ov_ok$88 \xer_ov$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9799 $1\nia$next[63:0]$9798 } { \nia_ok$45 \nia$44 } + assign { $1\xer_ov_ok$27$next[0:0]$9474 $1\xer_ov$26$next[1:0]$9473 } { \xer_ov_ok$88 \xer_ov$87 } case - assign $1\nia$next[63:0]$9798 \nia - assign $1\nia_ok$next[0:0]$9799 \nia_ok + assign $1\xer_ov$26$next[1:0]$9473 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9474 \xer_ov_ok$27 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$9800 1'0 + assign $2\xer_ov_ok$27$next[0:0]$9475 1'0 case - assign $2\nia_ok$next[0:0]$9800 $1\nia_ok$next[0:0]$9799 + assign $2\xer_ov_ok$27$next[0:0]$9475 $1\xer_ov_ok$27$next[0:0]$9474 end sync always - update \nia$next $0\nia$next[63:0]$9796 - update \nia_ok$next $0\nia_ok$next[0:0]$9797 + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9471 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9472 end - attribute \src "libresoc.v:174028.3-174046.6" - process $proc$libresoc.v:174028$9801 + attribute \src "libresoc.v:167785.3-167803.6" + process $proc$libresoc.v:167785$9476 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\msr$next[63:0]$9802 $1\msr$next[63:0]$9804 + assign $0\xer_so$28$next[0:0]$9477 $1\xer_so$28$next[0:0]$9479 assign { } { } - assign $0\msr_ok$next[0:0]$9803 $2\msr_ok$next[0:0]$9806 - attribute \src "libresoc.v:174029.5-174029.29" + assign $0\xer_so_ok$29$next[0:0]$9478 $2\xer_so_ok$29$next[0:0]$9481 + attribute \src "libresoc.v:167786.5-167786.29" switch \initial - attribute \src "libresoc.v:174029.9-174029.17" + attribute \src "libresoc.v:167786.9-167786.17" case 1'1 case end @@ -355102,364 +346635,353 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9805 $1\msr$next[63:0]$9804 } { \msr_ok$47 \msr$46 } + assign { $1\xer_so_ok$29$next[0:0]$9480 $1\xer_so$28$next[0:0]$9479 } { \xer_so_ok$90 \xer_so$89 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9805 $1\msr$next[63:0]$9804 } { \msr_ok$47 \msr$46 } + assign { $1\xer_so_ok$29$next[0:0]$9480 $1\xer_so$28$next[0:0]$9479 } { \xer_so_ok$90 \xer_so$89 } case - assign $1\msr$next[63:0]$9804 \msr - assign $1\msr_ok$next[0:0]$9805 \msr_ok + assign $1\xer_so$28$next[0:0]$9479 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9480 \xer_so_ok$29 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_ok$next[0:0]$9806 1'0 + assign $2\xer_so_ok$29$next[0:0]$9481 1'0 case - assign $2\msr_ok$next[0:0]$9806 $1\msr_ok$next[0:0]$9805 + assign $2\xer_so_ok$29$next[0:0]$9481 $1\xer_so_ok$29$next[0:0]$9480 end sync always - update \msr$next $0\msr$next[63:0]$9802 - update \msr_ok$next $0\msr_ok$next[0:0]$9803 + update \xer_so$28$next $0\xer_so$28$next[0:0]$9477 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9478 end - connect \$26 $and$libresoc.v:173813$9717_Y + connect \$60 $and$libresoc.v:167511$9342_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } - connect { \nia_ok$45 \nia$44 } { \main_nia_ok \main_nia } - connect { \fast2_ok$43 \fast2$42 } { \main_fast2_ok \main_fast2$24 } - connect { \fast1_ok$41 \fast1$40 } { \main_fast1_ok \main_fast1$23 } - connect { \o_ok$39 \o$38 } { \main_o_ok \main_o } - connect { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } { \main_trap_op__ldst_exc$22 \main_trap_op__trapaddr$21 \main_trap_op__traptype$20 \main_trap_op__is_32bit$19 \main_trap_op__cia$18 \main_trap_op__msr$17 \main_trap_op__insn$16 \main_trap_op__fn_unit$15 \main_trap_op__insn_type$14 } - connect \muxid$28 \main_muxid$13 - connect \p_valid_i_p_ready_o \$26 + connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } + connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } + connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } + connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } + connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } + connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } + connect \muxid$62 \output_muxid$30 + connect \p_valid_i_p_ready_o \$60 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$25 \p_valid_i - connect \main_fast2 \fast2 - connect \main_fast1 \fast1 - connect \main_rb \rb - connect \main_ra \ra - connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \main_muxid \muxid + connect \p_valid_i$59 \p_valid_i + connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } + connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } + connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \output_muxid \muxid end -attribute \src "libresoc.v:174069.1-175558.10" +attribute \src "libresoc.v:167827.1-168886.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" -module \pipe_end - attribute \src "libresoc.v:175396.3-175414.6" - wire width 4 $0\cr_a$next[3:0]$9897 - attribute \src "libresoc.v:175215.3-175216.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:175396.3-175414.6" - wire $0\cr_a_ok$next[0:0]$9898 - attribute \src "libresoc.v:175217.3-175218.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:174070.7-174070.20" +module \pipe2$115 + attribute \src "libresoc.v:168832.3-168850.6" + wire width 4 $0\cr_a$21$next[3:0]$9647 + attribute \src "libresoc.v:168638.3-168639.33" + wire width 4 $0\cr_a$21[3:0]$9548 + attribute \src "libresoc.v:167839.13-167839.29" + wire width 4 $0\cr_a$21[3:0]$9660 + attribute \src "libresoc.v:168832.3-168850.6" + wire $0\cr_a_ok$22$next[0:0]$9648 + attribute \src "libresoc.v:168640.3-168641.39" + wire $0\cr_a_ok$22[0:0]$9550 + attribute \src "libresoc.v:167848.7-167848.26" + wire $0\cr_a_ok$22[0:0]$9662 + attribute \src "libresoc.v:167828.7-167828.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175484.3-175525.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$9922 - attribute \src "libresoc.v:175255.3-175256.65" - wire width 4 $0\logical_op__data_len$18[3:0]$9884 - attribute \src "libresoc.v:174111.13-174111.45" - wire width 4 $0\logical_op__data_len$18[3:0]$9968 - attribute \src "libresoc.v:175484.3-175525.6" - wire width 13 $0\logical_op__fn_unit$3$next[12:0]$9923 - attribute \src "libresoc.v:175225.3-175226.61" - wire width 13 $0\logical_op__fn_unit$3[12:0]$9854 - attribute \src "libresoc.v:174148.14-174148.48" - wire width 13 $0\logical_op__fn_unit$3[12:0]$9970 - attribute \src "libresoc.v:175484.3-175525.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9924 - attribute \src "libresoc.v:175227.3-175228.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9856 - attribute \src "libresoc.v:174171.14-174171.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9972 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$9925 - attribute \src "libresoc.v:175229.3-175230.71" - wire $0\logical_op__imm_data__ok$5[0:0]$9858 - attribute \src "libresoc.v:174180.7-174180.42" - wire $0\logical_op__imm_data__ok$5[0:0]$9974 - attribute \src "libresoc.v:175484.3-175525.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$9926 - attribute \src "libresoc.v:175243.3-175244.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$9872 - attribute \src "libresoc.v:174197.13-174197.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$9976 - attribute \src "libresoc.v:175484.3-175525.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$9927 - attribute \src "libresoc.v:175257.3-175258.57" - wire width 32 $0\logical_op__insn$19[31:0]$9886 - attribute \src "libresoc.v:174210.14-174210.43" - wire width 32 $0\logical_op__insn$19[31:0]$9978 - attribute \src "libresoc.v:175484.3-175525.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$9928 - attribute \src "libresoc.v:175223.3-175224.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$9852 - attribute \src "libresoc.v:174367.13-174367.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$9980 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__invert_in$10$next[0:0]$9929 - attribute \src "libresoc.v:175239.3-175240.67" - wire $0\logical_op__invert_in$10[0:0]$9868 - attribute \src "libresoc.v:174450.7-174450.40" - wire $0\logical_op__invert_in$10[0:0]$9982 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__invert_out$13$next[0:0]$9930 - attribute \src "libresoc.v:175245.3-175246.69" - wire $0\logical_op__invert_out$13[0:0]$9874 - attribute \src "libresoc.v:174459.7-174459.41" - wire $0\logical_op__invert_out$13[0:0]$9984 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__is_32bit$16$next[0:0]$9931 - attribute \src "libresoc.v:175251.3-175252.65" - wire $0\logical_op__is_32bit$16[0:0]$9880 - attribute \src "libresoc.v:174468.7-174468.39" - wire $0\logical_op__is_32bit$16[0:0]$9986 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__is_signed$17$next[0:0]$9932 - attribute \src "libresoc.v:175253.3-175254.67" - wire $0\logical_op__is_signed$17[0:0]$9882 - attribute \src "libresoc.v:174477.7-174477.40" - wire $0\logical_op__is_signed$17[0:0]$9988 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__oe__oe$8$next[0:0]$9933 - attribute \src "libresoc.v:175235.3-175236.59" - wire $0\logical_op__oe__oe$8[0:0]$9864 - attribute \src "libresoc.v:174486.7-174486.36" - wire $0\logical_op__oe__oe$8[0:0]$9990 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__oe__ok$9$next[0:0]$9934 - attribute \src "libresoc.v:175237.3-175238.59" - wire $0\logical_op__oe__ok$9[0:0]$9866 - attribute \src "libresoc.v:174497.7-174497.36" - wire $0\logical_op__oe__ok$9[0:0]$9992 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__output_carry$15$next[0:0]$9935 - attribute \src "libresoc.v:175249.3-175250.73" - wire $0\logical_op__output_carry$15[0:0]$9878 - attribute \src "libresoc.v:174504.7-174504.43" - wire $0\logical_op__output_carry$15[0:0]$9994 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__rc__ok$7$next[0:0]$9936 - attribute \src "libresoc.v:175233.3-175234.59" - wire $0\logical_op__rc__ok$7[0:0]$9862 - attribute \src "libresoc.v:174513.7-174513.36" - wire $0\logical_op__rc__ok$7[0:0]$9996 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__rc__rc$6$next[0:0]$9937 - attribute \src "libresoc.v:175231.3-175232.59" - wire $0\logical_op__rc__rc$6[0:0]$9860 - attribute \src "libresoc.v:174522.7-174522.36" - wire $0\logical_op__rc__rc$6[0:0]$9998 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__write_cr0$14$next[0:0]$9938 - attribute \src "libresoc.v:174531.7-174531.40" - wire $0\logical_op__write_cr0$14[0:0]$10000 - attribute \src "libresoc.v:175247.3-175248.67" - wire $0\logical_op__write_cr0$14[0:0]$9876 - attribute \src "libresoc.v:175484.3-175525.6" - wire $0\logical_op__zero_a$11$next[0:0]$9939 - attribute \src "libresoc.v:174540.7-174540.37" - wire $0\logical_op__zero_a$11[0:0]$10002 - attribute \src "libresoc.v:175241.3-175242.61" - wire $0\logical_op__zero_a$11[0:0]$9870 - attribute \src "libresoc.v:175471.3-175483.6" - wire width 2 $0\muxid$1$next[1:0]$9919 - attribute \src "libresoc.v:174549.13-174549.29" - wire width 2 $0\muxid$1[1:0]$10004 - attribute \src "libresoc.v:175259.3-175260.33" - wire width 2 $0\muxid$1[1:0]$9888 - attribute \src "libresoc.v:175377.3-175395.6" - wire width 64 $0\o$next[63:0]$9891 - attribute \src "libresoc.v:175219.3-175220.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:175377.3-175395.6" - wire $0\o_ok$next[0:0]$9892 - attribute \src "libresoc.v:175221.3-175222.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:175453.3-175470.6" - wire $0\r_busy$next[0:0]$9915 - attribute \src "libresoc.v:175261.3-175262.29" + attribute \src "libresoc.v:168759.3-168771.6" + wire width 2 $0\muxid$1$next[1:0]$9597 + attribute \src "libresoc.v:168680.3-168681.33" + wire width 2 $0\muxid$1[1:0]$9590 + attribute \src "libresoc.v:167859.13-167859.29" + wire width 2 $0\muxid$1[1:0]$9664 + attribute \src "libresoc.v:168813.3-168831.6" + wire width 64 $0\o$19$next[63:0]$9641 + attribute \src "libresoc.v:168642.3-168643.27" + wire width 64 $0\o$19[63:0]$9552 + attribute \src "libresoc.v:167874.14-167874.43" + wire width 64 $0\o$19[63:0]$9666 + attribute \src "libresoc.v:168813.3-168831.6" + wire $0\o_ok$20$next[0:0]$9642 + attribute \src "libresoc.v:168644.3-168645.33" + wire $0\o_ok$20[0:0]$9554 + attribute \src "libresoc.v:167883.7-167883.23" + wire $0\o_ok$20[0:0]$9668 + attribute \src "libresoc.v:168741.3-168758.6" + wire $0\r_busy$next[0:0]$9593 + attribute \src "libresoc.v:168682.3-168683.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:175415.3-175433.6" - wire width 2 $0\xer_ov$next[1:0]$9903 - attribute \src "libresoc.v:175211.3-175212.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:175415.3-175433.6" - wire $0\xer_ov_ok$next[0:0]$9904 - attribute \src "libresoc.v:175213.3-175214.35" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:175434.3-175452.6" - wire $0\xer_so$20$next[0:0]$9910 - attribute \src "libresoc.v:175192.7-175192.25" - wire $0\xer_so$20[0:0]$10011 - attribute \src "libresoc.v:175207.3-175208.37" - wire $0\xer_so$20[0:0]$9843 - attribute \src "libresoc.v:175434.3-175452.6" - wire $0\xer_so_ok$next[0:0]$9909 - attribute \src "libresoc.v:175209.3-175210.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:175396.3-175414.6" - wire width 4 $1\cr_a$next[3:0]$9899 - attribute \src "libresoc.v:174079.13-174079.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:175396.3-175414.6" - wire $1\cr_a_ok$next[0:0]$9900 - attribute \src "libresoc.v:174088.7-174088.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:175484.3-175525.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$9940 - attribute \src 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$0\sr_op__insn$18[31:0]$9681 + attribute \src "libresoc.v:168772.3-168812.6" + wire width 7 $0\sr_op__insn_type$2$next[6:0]$9606 + attribute \src "libresoc.v:168646.3-168647.55" + wire width 7 $0\sr_op__insn_type$2[6:0]$9556 + attribute \src "libresoc.v:168438.13-168438.41" + wire width 7 $0\sr_op__insn_type$2[6:0]$9683 + attribute \src "libresoc.v:168772.3-168812.6" + wire $0\sr_op__invert_in$11$next[0:0]$9607 + attribute \src "libresoc.v:168664.3-168665.57" + wire $0\sr_op__invert_in$11[0:0]$9574 + attribute \src "libresoc.v:168521.7-168521.35" + wire $0\sr_op__invert_in$11[0:0]$9685 + attribute \src "libresoc.v:168772.3-168812.6" + wire $0\sr_op__is_32bit$16$next[0:0]$9608 + attribute \src "libresoc.v:168674.3-168675.55" + wire $0\sr_op__is_32bit$16[0:0]$9584 + attribute \src "libresoc.v:168530.7-168530.34" + wire $0\sr_op__is_32bit$16[0:0]$9687 + attribute \src "libresoc.v:168772.3-168812.6" + wire $0\sr_op__is_signed$17$next[0:0]$9609 + attribute \src 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$1\o_ok$20$next[0:0]$9644 + attribute \src "libresoc.v:168741.3-168758.6" + wire $1\r_busy$next[0:0]$9594 + attribute \src "libresoc.v:168175.7-168175.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:175415.3-175433.6" - wire width 2 $1\xer_ov$next[1:0]$9905 - attribute \src "libresoc.v:175172.13-175172.26" - wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:175415.3-175433.6" - wire $1\xer_ov_ok$next[0:0]$9906 - attribute \src "libresoc.v:175179.7-175179.23" - wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:175434.3-175452.6" - wire $1\xer_so$20$next[0:0]$9912 - attribute \src "libresoc.v:175434.3-175452.6" - wire $1\xer_so_ok$next[0:0]$9911 - attribute \src "libresoc.v:175197.7-175197.23" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:175396.3-175414.6" - wire $2\cr_a_ok$next[0:0]$9901 - attribute \src "libresoc.v:175484.3-175525.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9958 - attribute \src "libresoc.v:175484.3-175525.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$9959 - attribute \src "libresoc.v:175484.3-175525.6" - wire $2\logical_op__oe__oe$8$next[0:0]$9960 - attribute \src "libresoc.v:175484.3-175525.6" - wire $2\logical_op__oe__ok$9$next[0:0]$9961 - attribute \src "libresoc.v:175484.3-175525.6" - wire $2\logical_op__rc__ok$7$next[0:0]$9962 - attribute \src "libresoc.v:175484.3-175525.6" - wire $2\logical_op__rc__rc$6$next[0:0]$9963 - attribute \src "libresoc.v:175377.3-175395.6" - wire $2\o_ok$next[0:0]$9895 - attribute \src "libresoc.v:175453.3-175470.6" - wire $2\r_busy$next[0:0]$9917 - attribute \src "libresoc.v:175415.3-175433.6" - wire $2\xer_ov_ok$next[0:0]$9907 - attribute \src "libresoc.v:175434.3-175452.6" - wire $2\xer_so_ok$next[0:0]$9913 - attribute \src "libresoc.v:175206.18-175206.118" - wire $and$libresoc.v:175206$9841_Y + attribute \src "libresoc.v:168772.3-168812.6" + wire width 13 $1\sr_op__fn_unit$3$next[12:0]$9617 + attribute \src "libresoc.v:168772.3-168812.6" + wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9618 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__imm_data__ok$5$next[0:0]$9619 + attribute \src "libresoc.v:168772.3-168812.6" + wire width 2 $1\sr_op__input_carry$12$next[1:0]$9620 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__input_cr$14$next[0:0]$9621 + attribute \src "libresoc.v:168772.3-168812.6" + wire width 32 $1\sr_op__insn$18$next[31:0]$9622 + attribute \src "libresoc.v:168772.3-168812.6" + wire width 7 $1\sr_op__insn_type$2$next[6:0]$9623 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__invert_in$11$next[0:0]$9624 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__is_32bit$16$next[0:0]$9625 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__is_signed$17$next[0:0]$9626 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__oe__oe$8$next[0:0]$9627 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__oe__ok$9$next[0:0]$9628 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__output_carry$13$next[0:0]$9629 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__output_cr$15$next[0:0]$9630 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__rc__ok$7$next[0:0]$9631 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__rc__rc$6$next[0:0]$9632 + attribute \src "libresoc.v:168772.3-168812.6" + wire $1\sr_op__write_cr0$10$next[0:0]$9633 + attribute \src "libresoc.v:168851.3-168869.6" + wire width 2 $1\xer_ca$23$next[1:0]$9655 + attribute \src "libresoc.v:168851.3-168869.6" + wire $1\xer_ca_ok$24$next[0:0]$9656 + attribute \src "libresoc.v:168832.3-168850.6" + wire $2\cr_a_ok$22$next[0:0]$9651 + attribute \src "libresoc.v:168813.3-168831.6" + wire $2\o_ok$20$next[0:0]$9645 + attribute \src "libresoc.v:168741.3-168758.6" + wire $2\r_busy$next[0:0]$9595 + attribute \src "libresoc.v:168772.3-168812.6" + wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9634 + attribute \src "libresoc.v:168772.3-168812.6" + wire $2\sr_op__imm_data__ok$5$next[0:0]$9635 + attribute \src "libresoc.v:168772.3-168812.6" + wire $2\sr_op__oe__oe$8$next[0:0]$9636 + attribute \src "libresoc.v:168772.3-168812.6" + wire $2\sr_op__oe__ok$9$next[0:0]$9637 + attribute \src "libresoc.v:168772.3-168812.6" + wire $2\sr_op__rc__ok$7$next[0:0]$9638 + attribute \src "libresoc.v:168772.3-168812.6" + wire $2\sr_op__rc__rc$6$next[0:0]$9639 + attribute \src "libresoc.v:168851.3-168869.6" + wire $2\xer_ca_ok$24$next[0:0]$9657 + attribute \src "libresoc.v:168633.18-168633.118" + wire $and$libresoc.v:168633$9542_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 56 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 56 \cr_a + wire width 4 input 24 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$68 + wire width 4 output 52 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$97 + wire width 4 \cr_a$21$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$next + wire width 4 \cr_a$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 57 \cr_a_ok + wire input 25 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$67 + wire output 53 \cr_a_ok$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$69 + wire \cr_a_ok$22$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$98 + wire \cr_a_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire input 26 \divisor_neg - attribute \src "libresoc.v:174070.7-174070.15" + wire \cr_a_ok$74 + attribute \src "libresoc.v:167828.7-167828.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$93 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 32 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 31 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 30 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 50 \o$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \o_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$44 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -355475,9 +346997,7 @@ module \pipe_end attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 37 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$3$next + wire width 13 \output_sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -355493,127 +347013,35 @@ module \pipe_end attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok + wire width 13 \output_sr_op__fn_unit$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__imm_data__ok$5 + wire width 64 \output_sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$5$next + wire width 64 \output_sr_op__imm_data__data$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$80 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire \output_sr_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry + wire \output_sr_op__imm_data__ok$29 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 46 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next + wire width 2 \output_sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn + wire width 2 \output_sr_op__input_carry$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \logical_op__insn$19 + wire \output_sr_op__input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next + wire \output_sr_op__input_cr$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$94 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 32 \output_sr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type + wire width 32 \output_sr_op__insn$42 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -355689,9 +347117,7 @@ module \pipe_end attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 36 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next + wire width 7 \output_sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -355767,131 +347193,83 @@ module \pipe_end attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$9$next + wire width 7 \output_sr_op__insn_type$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry + wire \output_sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \logical_op__output_carry$15 + wire \output_sr_op__invert_in$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$15$next + wire \output_sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$90 + wire \output_sr_op__is_32bit$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok + wire \output_sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__rc__ok$7 + wire \output_sr_op__is_signed$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$7$next + wire \output_sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$82 + wire \output_sr_op__oe__oe$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc + wire \output_sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__rc__rc$6 + wire \output_sr_op__oe__ok$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$6$next + wire \output_sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$81 + wire \output_sr_op__output_carry$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 + wire \output_sr_op__output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \logical_op__write_cr0$14 + wire \output_sr_op__output_cr$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$14$next + wire \output_sr_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$89 + wire \output_sr_op__rc__ok$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a + wire \output_sr_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__zero_a$11 + wire \output_sr_op__rc__rc$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$11$next + wire \output_sr_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$86 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$76 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 34 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 54 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 55 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$96 + wire \output_sr_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next + wire width 2 \output_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a + wire width 2 \output_xer_ca$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$62 + wire \output_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len$58 + wire width 13 input 6 \sr_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -355907,7 +347285,9 @@ module \pipe_end attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_logical_op__fn_unit + wire width 13 output 34 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \sr_op__fn_unit$3$next attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -355923,31 +347303,59 @@ module \pipe_end attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_logical_op__fn_unit$43 + wire width 13 \sr_op__fn_unit$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data + wire width 64 input 7 \sr_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data$44 + wire width 64 output 35 \sr_op__imm_data__data$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok + wire width 64 \sr_op__imm_data__data$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok$45 + wire width 64 \sr_op__imm_data__data$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$57 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry + wire width 2 input 15 \sr_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry$52 + wire width 2 output 43 \sr_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn + wire width 2 \sr_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn$59 + wire width 2 \sr_op__input_carry$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$70 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -356023,7 +347431,7 @@ module \pipe_end attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type + wire width 7 input 5 \sr_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -356099,133 +347507,9 @@ module \pipe_end attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_muxid$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \output_stage_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \output_stage_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \output_stage_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \output_stage_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \output_stage_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_stage_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_stage_logical_op__data_len$38 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_stage_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \output_stage_logical_op__fn_unit$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__data$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__imm_data__ok$25 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_stage_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_stage_logical_op__input_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_stage_logical_op__insn + wire width 7 output 33 \sr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_stage_logical_op__insn$39 + wire width 7 \sr_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -356301,788 +347585,577 @@ module \pipe_end attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" + wire width 7 \sr_op__insn_type$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type$22 + wire input 14 \sr_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_in + wire output 42 \sr_op__invert_in$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_in$30 + wire \sr_op__invert_in$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_out + wire \sr_op__invert_in$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_out$33 + wire input 19 \sr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_32bit + wire output 47 \sr_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_32bit$36 + wire \sr_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_signed + wire \sr_op__is_32bit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_signed$37 + wire input 20 \sr_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__oe + wire output 48 \sr_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__oe$28 + wire \sr_op__is_signed$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__ok + wire \sr_op__is_signed$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__ok$29 + wire input 11 \sr_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__output_carry + wire \sr_op__oe__oe$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__output_carry$35 + wire output 39 \sr_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__ok + wire \sr_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__ok$27 + wire input 12 \sr_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__rc + wire \sr_op__oe__ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__rc$26 + wire output 40 \sr_op__oe__ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__write_cr0 + wire \sr_op__oe__ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__write_cr0$34 + wire input 16 \sr_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__zero_a + wire output 44 \sr_op__output_carry$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__zero_a$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_stage_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \output_stage_muxid$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_stage_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_stage_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 \output_stage_quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 \output_stage_remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_stage_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_stage_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \output_stage_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_stage_xer_so$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 input 31 \quotient_root - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 input 32 \remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 58 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$next + wire \sr_op__output_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 59 \xer_ov_ok + wire width 2 input 28 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$100 + wire width 2 output 54 \xer_ca$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$70 + wire width 2 \xer_ca$23$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 25 \xer_so + wire width 2 \xer_ca$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$101 + wire input 29 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 60 \xer_so$20 + wire output 55 \xer_ca_ok$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$20$next + wire \xer_ca_ok$24$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 61 \xer_so_ok + wire \xer_ca_ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$102 + wire \xer_ca_ok$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$71 + wire input 26 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$72 + wire input 27 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next + wire \xer_so_ok$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:175206$9841 + cell $and $and$libresoc.v:168633$9542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$73 + connect \A \p_valid_i$50 connect \B \p_ready_o - connect \Y $and$libresoc.v:175206$9841_Y + connect \Y $and$libresoc.v:168633$9542_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:175263.10-175266.4" - cell \n$82 \n + attribute \src "libresoc.v:168684.11-168687.4" + cell \n$117 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:175267.15-175319.4" - cell \output$83 \output + attribute \src "libresoc.v:168688.16-168736.4" + cell \output$118 \output connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$62 + connect \cr_a$21 \output_cr_a$45 connect \cr_a_ok \output_cr_a_ok - connect \logical_op__data_len \output_logical_op__data_len - connect \logical_op__data_len$18 \output_logical_op__data_len$58 - connect \logical_op__fn_unit \output_logical_op__fn_unit - connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 - connect \logical_op__imm_data__data \output_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$44 - connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$45 - connect \logical_op__input_carry \output_logical_op__input_carry - connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 - connect \logical_op__insn \output_logical_op__insn - connect \logical_op__insn$19 \output_logical_op__insn$59 - connect \logical_op__insn_type \output_logical_op__insn_type - connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 - connect \logical_op__invert_in \output_logical_op__invert_in - connect \logical_op__invert_in$10 \output_logical_op__invert_in$50 - connect \logical_op__invert_out \output_logical_op__invert_out - connect \logical_op__invert_out$13 \output_logical_op__invert_out$53 - connect \logical_op__is_32bit \output_logical_op__is_32bit - connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56 - connect \logical_op__is_signed \output_logical_op__is_signed - connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 - connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 - connect \logical_op__oe__ok \output_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$49 - connect \logical_op__output_carry \output_logical_op__output_carry - connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 - connect \logical_op__rc__ok \output_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$47 - connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 - connect \logical_op__write_cr0 \output_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 - connect \logical_op__zero_a \output_logical_op__zero_a - connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 connect \muxid \output_muxid - connect \muxid$1 \output_muxid$41 + connect \muxid$1 \output_muxid$25 connect \o \output_o - connect \o$20 \output_o$60 + connect \o$19 \output_o$43 connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$61 - connect \xer_ov \output_xer_ov - connect \xer_ov$23 \output_xer_ov$63 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so \output_xer_so - connect \xer_so$24 \output_xer_so$64 - connect \xer_so_ok \output_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:175320.16-175372.4" - cell \output_stage \output_stage - connect \div_by_zero \output_stage_div_by_zero - connect \dive_abs_ov32 \output_stage_dive_abs_ov32 - connect \dive_abs_ov64 \output_stage_dive_abs_ov64 - connect \dividend_neg \output_stage_dividend_neg - connect \divisor_neg \output_stage_divisor_neg - connect \logical_op__data_len \output_stage_logical_op__data_len - connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 - connect \logical_op__fn_unit \output_stage_logical_op__fn_unit - connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 - connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 - connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 - connect \logical_op__input_carry \output_stage_logical_op__input_carry - connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 - connect \logical_op__insn \output_stage_logical_op__insn - connect \logical_op__insn$19 \output_stage_logical_op__insn$39 - connect \logical_op__insn_type \output_stage_logical_op__insn_type - connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 - connect \logical_op__invert_in \output_stage_logical_op__invert_in - connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 - connect \logical_op__invert_out \output_stage_logical_op__invert_out - connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 - connect \logical_op__is_32bit \output_stage_logical_op__is_32bit - connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 - connect \logical_op__is_signed \output_stage_logical_op__is_signed - connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 - connect \logical_op__oe__oe \output_stage_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 - connect \logical_op__oe__ok \output_stage_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 - connect \logical_op__output_carry \output_stage_logical_op__output_carry - connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 - connect \logical_op__rc__ok \output_stage_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 - connect \logical_op__rc__rc \output_stage_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 - connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 - connect \logical_op__zero_a \output_stage_logical_op__zero_a - connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 - connect \muxid \output_stage_muxid - connect \muxid$1 \output_stage_muxid$21 - connect \o \output_stage_o - connect \o_ok \output_stage_o_ok - connect \quotient_root \output_stage_quotient_root - connect \remainder \output_stage_remainder - connect \xer_ov \output_stage_xer_ov - connect \xer_ov_ok \output_stage_xer_ov_ok - connect \xer_so \output_stage_xer_so - connect \xer_so$20 \output_stage_xer_so$40 + connect \o_ok$20 \output_o_ok$44 + connect \sr_op__fn_unit \output_sr_op__fn_unit + connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$27 + connect \sr_op__imm_data__data \output_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$28 + connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$29 + connect \sr_op__input_carry \output_sr_op__input_carry + connect \sr_op__input_carry$12 \output_sr_op__input_carry$36 + connect \sr_op__input_cr \output_sr_op__input_cr + connect \sr_op__input_cr$14 \output_sr_op__input_cr$38 + connect \sr_op__insn \output_sr_op__insn + connect \sr_op__insn$18 \output_sr_op__insn$42 + connect \sr_op__insn_type \output_sr_op__insn_type + connect \sr_op__insn_type$2 \output_sr_op__insn_type$26 + connect \sr_op__invert_in \output_sr_op__invert_in + connect \sr_op__invert_in$11 \output_sr_op__invert_in$35 + connect \sr_op__is_32bit \output_sr_op__is_32bit + connect \sr_op__is_32bit$16 \output_sr_op__is_32bit$40 + connect \sr_op__is_signed \output_sr_op__is_signed + connect \sr_op__is_signed$17 \output_sr_op__is_signed$41 + connect \sr_op__oe__oe \output_sr_op__oe__oe + connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$32 + connect \sr_op__oe__ok \output_sr_op__oe__ok + connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$33 + connect \sr_op__output_carry \output_sr_op__output_carry + connect \sr_op__output_carry$13 \output_sr_op__output_carry$37 + connect \sr_op__output_cr \output_sr_op__output_cr + connect \sr_op__output_cr$15 \output_sr_op__output_cr$39 + connect \sr_op__rc__ok \output_sr_op__rc__ok + connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$31 + connect \sr_op__rc__rc \output_sr_op__rc__rc + connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$30 + connect \sr_op__write_cr0 \output_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$34 + connect \xer_ca \output_xer_ca + connect \xer_ca$22 \output_xer_ca$46 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:175373.10-175376.4" - cell \p$81 \p + attribute \src "libresoc.v:168737.11-168740.4" + cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:174070.7-174070.20" - process $proc$libresoc.v:174070$9964 + attribute \src "libresoc.v:167828.7-167828.20" + process $proc$libresoc.v:167828$9658 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:174079.13-174079.24" - process $proc$libresoc.v:174079$9965 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "libresoc.v:174088.7-174088.21" - process $proc$libresoc.v:174088$9966 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:174111.13-174111.45" - process $proc$libresoc.v:174111$9967 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$9968 4'0000 - sync always - sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9968 - end - attribute \src "libresoc.v:174148.14-174148.48" - process $proc$libresoc.v:174148$9969 + attribute \src "libresoc.v:167839.13-167839.29" + process $proc$libresoc.v:167839$9659 assign { } { } - assign $0\logical_op__fn_unit$3[12:0]$9970 13'0000000000000 + assign $0\cr_a$21[3:0]$9660 4'0000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9970 + update \cr_a$21 $0\cr_a$21[3:0]$9660 end - attribute \src "libresoc.v:174171.14-174171.67" - process $proc$libresoc.v:174171$9971 + attribute \src "libresoc.v:167848.7-167848.26" + process $proc$libresoc.v:167848$9661 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9972 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\cr_a_ok$22[0:0]$9662 1'0 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9972 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9662 end - attribute \src "libresoc.v:174180.7-174180.42" - process $proc$libresoc.v:174180$9973 + attribute \src "libresoc.v:167859.13-167859.29" + process $proc$libresoc.v:167859$9663 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9974 1'0 + assign $0\muxid$1[1:0]$9664 2'00 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9974 + update \muxid$1 $0\muxid$1[1:0]$9664 end - attribute \src "libresoc.v:174197.13-174197.48" - process $proc$libresoc.v:174197$9975 + attribute \src "libresoc.v:167874.14-167874.43" + process $proc$libresoc.v:167874$9665 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9976 2'00 + assign $0\o$19[63:0]$9666 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9976 + update \o$19 $0\o$19[63:0]$9666 end - attribute \src "libresoc.v:174210.14-174210.43" - process $proc$libresoc.v:174210$9977 + attribute \src "libresoc.v:167883.7-167883.23" + process $proc$libresoc.v:167883$9667 assign { } { } - assign $0\logical_op__insn$19[31:0]$9978 0 + assign $0\o_ok$20[0:0]$9668 1'0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9978 + update \o_ok$20 $0\o_ok$20[0:0]$9668 end - attribute \src "libresoc.v:174367.13-174367.46" - process $proc$libresoc.v:174367$9979 + attribute \src "libresoc.v:168175.7-168175.20" + process $proc$libresoc.v:168175$9669 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9980 7'0000000 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9980 + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:174450.7-174450.40" - process $proc$libresoc.v:174450$9981 + attribute \src "libresoc.v:168210.14-168210.43" + process $proc$libresoc.v:168210$9670 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9982 1'0 + assign $0\sr_op__fn_unit$3[12:0]$9671 13'0000000000000 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9982 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9671 end - attribute \src "libresoc.v:174459.7-174459.41" - process $proc$libresoc.v:174459$9983 + attribute \src "libresoc.v:168233.14-168233.62" + process $proc$libresoc.v:168233$9672 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9984 1'0 + assign $0\sr_op__imm_data__data$4[63:0]$9673 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9984 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9673 end - attribute \src "libresoc.v:174468.7-174468.39" - process $proc$libresoc.v:174468$9985 + attribute \src "libresoc.v:168242.7-168242.37" + process $proc$libresoc.v:168242$9674 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9986 1'0 + assign $0\sr_op__imm_data__ok$5[0:0]$9675 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9986 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9675 end - attribute \src "libresoc.v:174477.7-174477.40" - process $proc$libresoc.v:174477$9987 + attribute \src "libresoc.v:168259.13-168259.43" + process $proc$libresoc.v:168259$9676 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9988 1'0 + assign $0\sr_op__input_carry$12[1:0]$9677 2'00 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9988 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9677 end - attribute \src "libresoc.v:174486.7-174486.36" - process $proc$libresoc.v:174486$9989 + attribute \src "libresoc.v:168272.7-168272.34" + process $proc$libresoc.v:168272$9678 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9990 1'0 + assign $0\sr_op__input_cr$14[0:0]$9679 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9990 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9679 end - attribute \src "libresoc.v:174497.7-174497.36" - process $proc$libresoc.v:174497$9991 + attribute \src "libresoc.v:168281.14-168281.38" + process $proc$libresoc.v:168281$9680 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9992 1'0 + assign $0\sr_op__insn$18[31:0]$9681 0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9992 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9681 end - attribute \src "libresoc.v:174504.7-174504.43" - process $proc$libresoc.v:174504$9993 + attribute \src "libresoc.v:168438.13-168438.41" + process $proc$libresoc.v:168438$9682 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9994 1'0 + assign $0\sr_op__insn_type$2[6:0]$9683 7'0000000 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9994 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9683 end - attribute \src "libresoc.v:174513.7-174513.36" - process $proc$libresoc.v:174513$9995 + attribute \src "libresoc.v:168521.7-168521.35" + process $proc$libresoc.v:168521$9684 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9996 1'0 + assign $0\sr_op__invert_in$11[0:0]$9685 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9996 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9685 end - attribute \src "libresoc.v:174522.7-174522.36" - process $proc$libresoc.v:174522$9997 + attribute \src "libresoc.v:168530.7-168530.34" + process $proc$libresoc.v:168530$9686 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9998 1'0 + assign $0\sr_op__is_32bit$16[0:0]$9687 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9998 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9687 end - attribute \src "libresoc.v:174531.7-174531.40" - process $proc$libresoc.v:174531$9999 + attribute \src "libresoc.v:168539.7-168539.35" + process $proc$libresoc.v:168539$9688 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$10000 1'0 + assign $0\sr_op__is_signed$17[0:0]$9689 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$10000 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9689 end - attribute \src "libresoc.v:174540.7-174540.37" - process $proc$libresoc.v:174540$10001 + attribute \src "libresoc.v:168550.7-168550.31" + process $proc$libresoc.v:168550$9690 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$10002 1'0 + assign $0\sr_op__oe__oe$8[0:0]$9691 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$10002 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9691 end - attribute \src "libresoc.v:174549.13-174549.29" - process $proc$libresoc.v:174549$10003 + attribute \src "libresoc.v:168559.7-168559.31" + process $proc$libresoc.v:168559$9692 assign { } { } - assign $0\muxid$1[1:0]$10004 2'00 + assign $0\sr_op__oe__ok$9[0:0]$9693 1'0 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$10004 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9693 end - attribute \src "libresoc.v:174562.14-174562.38" - process $proc$libresoc.v:174562$10005 + attribute \src "libresoc.v:168566.7-168566.38" + process $proc$libresoc.v:168566$9694 assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\sr_op__output_carry$13[0:0]$9695 1'0 sync always sync init - update \o $1\o[63:0] + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9695 end - attribute \src "libresoc.v:174569.7-174569.18" - process $proc$libresoc.v:174569$10006 + attribute \src "libresoc.v:168575.7-168575.35" + process $proc$libresoc.v:168575$9696 assign { } { } - assign $1\o_ok[0:0] 1'0 + assign $0\sr_op__output_cr$15[0:0]$9697 1'0 sync always sync init - update \o_ok $1\o_ok[0:0] + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9697 end - attribute \src "libresoc.v:175157.7-175157.20" - process $proc$libresoc.v:175157$10007 + attribute \src "libresoc.v:168586.7-168586.31" + process $proc$libresoc.v:168586$9698 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $0\sr_op__rc__ok$7[0:0]$9699 1'0 sync always sync init - update \r_busy $1\r_busy[0:0] + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9699 end - attribute \src "libresoc.v:175172.13-175172.26" - process $proc$libresoc.v:175172$10008 + attribute \src "libresoc.v:168595.7-168595.31" + process $proc$libresoc.v:168595$9700 assign { } { } - assign $1\xer_ov[1:0] 2'00 + assign $0\sr_op__rc__rc$6[0:0]$9701 1'0 sync always sync init - update \xer_ov $1\xer_ov[1:0] + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9701 end - attribute \src "libresoc.v:175179.7-175179.23" - process $proc$libresoc.v:175179$10009 + attribute \src "libresoc.v:168602.7-168602.35" + process $proc$libresoc.v:168602$9702 assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 + assign $0\sr_op__write_cr0$10[0:0]$9703 1'0 sync always sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9703 end - attribute \src "libresoc.v:175192.7-175192.25" - process $proc$libresoc.v:175192$10010 + attribute \src "libresoc.v:168611.13-168611.31" + process $proc$libresoc.v:168611$9704 assign { } { } - assign $0\xer_so$20[0:0]$10011 1'0 + assign $0\xer_ca$23[1:0]$9705 2'00 sync always sync init - update \xer_so$20 $0\xer_so$20[0:0]$10011 + update \xer_ca$23 $0\xer_ca$23[1:0]$9705 end - attribute \src "libresoc.v:175197.7-175197.23" - process $proc$libresoc.v:175197$10012 + attribute \src "libresoc.v:168620.7-168620.28" + process $proc$libresoc.v:168620$9706 assign { } { } - assign $1\xer_so_ok[0:0] 1'0 + assign $0\xer_ca_ok$24[0:0]$9707 1'0 sync always sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:175207.3-175208.37" - process $proc$libresoc.v:175207$9842 - assign { } { } - assign $0\xer_so$20[0:0]$9843 \xer_so$20$next - sync posedge \coresync_clk - update \xer_so$20 $0\xer_so$20[0:0]$9843 - end - attribute \src "libresoc.v:175209.3-175210.35" - process $proc$libresoc.v:175209$9844 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:175211.3-175212.29" - process $proc$libresoc.v:175211$9845 - assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9707 end - attribute \src "libresoc.v:175213.3-175214.35" - process $proc$libresoc.v:175213$9846 + attribute \src "libresoc.v:168634.3-168635.37" + process $proc$libresoc.v:168634$9543 assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + assign $0\xer_ca$23[1:0]$9544 \xer_ca$23$next sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] + update \xer_ca$23 $0\xer_ca$23[1:0]$9544 end - attribute \src "libresoc.v:175215.3-175216.25" - process $proc$libresoc.v:175215$9847 + attribute \src "libresoc.v:168636.3-168637.43" + process $proc$libresoc.v:168636$9545 assign { } { } - assign $0\cr_a[3:0] \cr_a$next + assign $0\xer_ca_ok$24[0:0]$9546 \xer_ca_ok$24$next sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9546 end - attribute \src "libresoc.v:175217.3-175218.31" - process $proc$libresoc.v:175217$9848 + attribute \src "libresoc.v:168638.3-168639.33" + process $proc$libresoc.v:168638$9547 assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next + assign $0\cr_a$21[3:0]$9548 \cr_a$21$next sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] + update \cr_a$21 $0\cr_a$21[3:0]$9548 end - attribute \src "libresoc.v:175219.3-175220.19" - process $proc$libresoc.v:175219$9849 + attribute \src "libresoc.v:168640.3-168641.39" + process $proc$libresoc.v:168640$9549 assign { } { } - assign $0\o[63:0] \o$next + assign $0\cr_a_ok$22[0:0]$9550 \cr_a_ok$22$next sync posedge \coresync_clk - update \o $0\o[63:0] + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9550 end - attribute \src "libresoc.v:175221.3-175222.25" - process $proc$libresoc.v:175221$9850 + attribute \src "libresoc.v:168642.3-168643.27" + process $proc$libresoc.v:168642$9551 assign { } { } - assign $0\o_ok[0:0] \o_ok$next + assign $0\o$19[63:0]$9552 \o$19$next sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + update \o$19 $0\o$19[63:0]$9552 end - attribute \src "libresoc.v:175223.3-175224.65" - process $proc$libresoc.v:175223$9851 + attribute \src "libresoc.v:168644.3-168645.33" + process $proc$libresoc.v:168644$9553 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9852 \logical_op__insn_type$2$next + assign $0\o_ok$20[0:0]$9554 \o_ok$20$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9852 + update \o_ok$20 $0\o_ok$20[0:0]$9554 end - attribute \src "libresoc.v:175225.3-175226.61" - process $proc$libresoc.v:175225$9853 + attribute \src "libresoc.v:168646.3-168647.55" + process $proc$libresoc.v:168646$9555 assign { } { } - assign $0\logical_op__fn_unit$3[12:0]$9854 \logical_op__fn_unit$3$next + assign $0\sr_op__insn_type$2[6:0]$9556 \sr_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9854 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9556 end - attribute \src "libresoc.v:175227.3-175228.75" - process $proc$libresoc.v:175227$9855 + attribute \src "libresoc.v:168648.3-168649.51" + process $proc$libresoc.v:168648$9557 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9856 \logical_op__imm_data__data$4$next + assign $0\sr_op__fn_unit$3[12:0]$9558 \sr_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9856 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9558 end - attribute \src "libresoc.v:175229.3-175230.71" - process $proc$libresoc.v:175229$9857 + attribute \src "libresoc.v:168650.3-168651.65" + process $proc$libresoc.v:168650$9559 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9858 \logical_op__imm_data__ok$5$next + assign $0\sr_op__imm_data__data$4[63:0]$9560 \sr_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9858 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9560 end - attribute \src "libresoc.v:175231.3-175232.59" - process $proc$libresoc.v:175231$9859 + attribute \src "libresoc.v:168652.3-168653.61" + process $proc$libresoc.v:168652$9561 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9860 \logical_op__rc__rc$6$next + assign $0\sr_op__imm_data__ok$5[0:0]$9562 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9860 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9562 end - attribute \src "libresoc.v:175233.3-175234.59" - process $proc$libresoc.v:175233$9861 + attribute \src "libresoc.v:168654.3-168655.49" + process $proc$libresoc.v:168654$9563 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9862 \logical_op__rc__ok$7$next + assign $0\sr_op__rc__rc$6[0:0]$9564 \sr_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9862 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9564 end - attribute \src "libresoc.v:175235.3-175236.59" - process $proc$libresoc.v:175235$9863 + attribute \src "libresoc.v:168656.3-168657.49" + process $proc$libresoc.v:168656$9565 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9864 \logical_op__oe__oe$8$next + assign $0\sr_op__rc__ok$7[0:0]$9566 \sr_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9864 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9566 end - attribute \src "libresoc.v:175237.3-175238.59" - process $proc$libresoc.v:175237$9865 + attribute \src "libresoc.v:168658.3-168659.49" + process $proc$libresoc.v:168658$9567 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9866 \logical_op__oe__ok$9$next + assign $0\sr_op__oe__oe$8[0:0]$9568 \sr_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9866 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9568 end - attribute \src "libresoc.v:175239.3-175240.67" - process $proc$libresoc.v:175239$9867 + attribute \src "libresoc.v:168660.3-168661.49" + process $proc$libresoc.v:168660$9569 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9868 \logical_op__invert_in$10$next + assign $0\sr_op__oe__ok$9[0:0]$9570 \sr_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9868 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9570 end - attribute \src "libresoc.v:175241.3-175242.61" - process $proc$libresoc.v:175241$9869 + attribute \src "libresoc.v:168662.3-168663.57" + process $proc$libresoc.v:168662$9571 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9870 \logical_op__zero_a$11$next + assign $0\sr_op__write_cr0$10[0:0]$9572 \sr_op__write_cr0$10$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9870 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9572 end - attribute \src "libresoc.v:175243.3-175244.71" - process $proc$libresoc.v:175243$9871 + attribute \src "libresoc.v:168664.3-168665.57" + process $proc$libresoc.v:168664$9573 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9872 \logical_op__input_carry$12$next + assign $0\sr_op__invert_in$11[0:0]$9574 \sr_op__invert_in$11$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9872 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9574 end - attribute \src "libresoc.v:175245.3-175246.69" - process $proc$libresoc.v:175245$9873 + attribute \src "libresoc.v:168666.3-168667.61" + process $proc$libresoc.v:168666$9575 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9874 \logical_op__invert_out$13$next + assign $0\sr_op__input_carry$12[1:0]$9576 \sr_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9874 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9576 end - attribute \src "libresoc.v:175247.3-175248.67" - process $proc$libresoc.v:175247$9875 + attribute \src "libresoc.v:168668.3-168669.63" + process $proc$libresoc.v:168668$9577 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9876 \logical_op__write_cr0$14$next + assign $0\sr_op__output_carry$13[0:0]$9578 \sr_op__output_carry$13$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9876 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9578 end - attribute \src "libresoc.v:175249.3-175250.73" - process $proc$libresoc.v:175249$9877 + attribute \src "libresoc.v:168670.3-168671.55" + process $proc$libresoc.v:168670$9579 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9878 \logical_op__output_carry$15$next + assign $0\sr_op__input_cr$14[0:0]$9580 \sr_op__input_cr$14$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9878 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9580 end - attribute \src "libresoc.v:175251.3-175252.65" - process $proc$libresoc.v:175251$9879 + attribute \src "libresoc.v:168672.3-168673.57" + process $proc$libresoc.v:168672$9581 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9880 \logical_op__is_32bit$16$next + assign $0\sr_op__output_cr$15[0:0]$9582 \sr_op__output_cr$15$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9880 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9582 end - attribute \src "libresoc.v:175253.3-175254.67" - process $proc$libresoc.v:175253$9881 + attribute \src "libresoc.v:168674.3-168675.55" + process $proc$libresoc.v:168674$9583 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9882 \logical_op__is_signed$17$next + assign $0\sr_op__is_32bit$16[0:0]$9584 \sr_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9882 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9584 end - attribute \src "libresoc.v:175255.3-175256.65" - process $proc$libresoc.v:175255$9883 + attribute \src "libresoc.v:168676.3-168677.57" + process $proc$libresoc.v:168676$9585 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9884 \logical_op__data_len$18$next + assign $0\sr_op__is_signed$17[0:0]$9586 \sr_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9884 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9586 end - attribute \src "libresoc.v:175257.3-175258.57" - process $proc$libresoc.v:175257$9885 + attribute \src "libresoc.v:168678.3-168679.47" + process $proc$libresoc.v:168678$9587 assign { } { } - assign $0\logical_op__insn$19[31:0]$9886 \logical_op__insn$19$next + assign $0\sr_op__insn$18[31:0]$9588 \sr_op__insn$18$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9886 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9588 end - attribute \src "libresoc.v:175259.3-175260.33" - process $proc$libresoc.v:175259$9887 + attribute \src "libresoc.v:168680.3-168681.33" + process $proc$libresoc.v:168680$9589 assign { } { } - assign $0\muxid$1[1:0]$9888 \muxid$1$next + assign $0\muxid$1[1:0]$9590 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9888 + update \muxid$1 $0\muxid$1[1:0]$9590 end - attribute \src "libresoc.v:175261.3-175262.29" - process $proc$libresoc.v:175261$9889 + attribute \src "libresoc.v:168682.3-168683.29" + process $proc$libresoc.v:168682$9591 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:175377.3-175395.6" - process $proc$libresoc.v:175377$9890 - assign { } { } + attribute \src "libresoc.v:168741.3-168758.6" + process $proc$libresoc.v:168741$9592 assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9891 $1\o$next[63:0]$9893 - assign { } { } - assign $0\o_ok$next[0:0]$9892 $2\o_ok$next[0:0]$9895 - attribute \src "libresoc.v:175378.5-175378.29" + assign $0\r_busy$next[0:0]$9593 $2\r_busy$next[0:0]$9595 + attribute \src "libresoc.v:168742.5-168742.29" switch \initial - attribute \src "libresoc.v:175378.9-175378.17" + attribute \src "libresoc.v:168742.9-168742.17" case 1'1 case end @@ -357091,42 +348164,34 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$9894 $1\o$next[63:0]$9893 } { \o_ok$96 \o$95 } + assign $1\r_busy$next[0:0]$9594 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$9894 $1\o$next[63:0]$9893 } { \o_ok$96 \o$95 } + assign $1\r_busy$next[0:0]$9594 1'0 case - assign $1\o$next[63:0]$9893 \o - assign $1\o_ok$next[0:0]$9894 \o_ok + assign $1\r_busy$next[0:0]$9594 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9895 1'0 + assign $2\r_busy$next[0:0]$9595 1'0 case - assign $2\o_ok$next[0:0]$9895 $1\o_ok$next[0:0]$9894 + assign $2\r_busy$next[0:0]$9595 $1\r_busy$next[0:0]$9594 end sync always - update \o$next $0\o$next[63:0]$9891 - update \o_ok$next $0\o_ok$next[0:0]$9892 + update \r_busy$next $0\r_busy$next[0:0]$9593 end - attribute \src "libresoc.v:175396.3-175414.6" - process $proc$libresoc.v:175396$9896 - assign { } { } + attribute \src "libresoc.v:168759.3-168771.6" + process $proc$libresoc.v:168759$9596 assign { } { } assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$9897 $1\cr_a$next[3:0]$9899 - assign { } { } - assign $0\cr_a_ok$next[0:0]$9898 $2\cr_a_ok$next[0:0]$9901 - attribute \src "libresoc.v:175397.5-175397.29" + assign $0\muxid$1$next[1:0]$9597 $1\muxid$1$next[1:0]$9598 + attribute \src "libresoc.v:168760.5-168760.29" switch \initial - attribute \src "libresoc.v:175397.9-175397.17" + attribute \src "libresoc.v:168760.9-168760.17" case 1'1 case end @@ -357135,42 +348200,79 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$9900 $1\cr_a$next[3:0]$9899 } { \cr_a_ok$98 \cr_a$97 } + assign $1\muxid$1$next[1:0]$9598 \muxid$53 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$9900 $1\cr_a$next[3:0]$9899 } { \cr_a_ok$98 \cr_a$97 } - case - assign $1\cr_a$next[3:0]$9899 \cr_a - assign $1\cr_a_ok$next[0:0]$9900 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$9901 1'0 + assign $1\muxid$1$next[1:0]$9598 \muxid$53 case - assign $2\cr_a_ok$next[0:0]$9901 $1\cr_a_ok$next[0:0]$9900 + assign $1\muxid$1$next[1:0]$9598 \muxid$1 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9897 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9898 + update \muxid$1$next $0\muxid$1$next[1:0]$9597 end - attribute \src "libresoc.v:175415.3-175433.6" - process $proc$libresoc.v:175415$9902 + attribute \src "libresoc.v:168772.3-168812.6" + process $proc$libresoc.v:168772$9599 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9903 $1\xer_ov$next[1:0]$9905 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9904 $2\xer_ov_ok$next[0:0]$9907 - attribute \src "libresoc.v:175416.5-175416.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$3$next[12:0]$9600 $1\sr_op__fn_unit$3$next[12:0]$9617 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$12$next[1:0]$9603 $1\sr_op__input_carry$12$next[1:0]$9620 + assign $0\sr_op__input_cr$14$next[0:0]$9604 $1\sr_op__input_cr$14$next[0:0]$9621 + assign $0\sr_op__insn$18$next[31:0]$9605 $1\sr_op__insn$18$next[31:0]$9622 + assign $0\sr_op__insn_type$2$next[6:0]$9606 $1\sr_op__insn_type$2$next[6:0]$9623 + assign $0\sr_op__invert_in$11$next[0:0]$9607 $1\sr_op__invert_in$11$next[0:0]$9624 + assign $0\sr_op__is_32bit$16$next[0:0]$9608 $1\sr_op__is_32bit$16$next[0:0]$9625 + assign $0\sr_op__is_signed$17$next[0:0]$9609 $1\sr_op__is_signed$17$next[0:0]$9626 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$13$next[0:0]$9612 $1\sr_op__output_carry$13$next[0:0]$9629 + assign $0\sr_op__output_cr$15$next[0:0]$9613 $1\sr_op__output_cr$15$next[0:0]$9630 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$10$next[0:0]$9616 $1\sr_op__write_cr0$10$next[0:0]$9633 + assign $0\sr_op__imm_data__data$4$next[63:0]$9601 $2\sr_op__imm_data__data$4$next[63:0]$9634 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9602 $2\sr_op__imm_data__ok$5$next[0:0]$9635 + assign $0\sr_op__oe__oe$8$next[0:0]$9610 $2\sr_op__oe__oe$8$next[0:0]$9636 + assign $0\sr_op__oe__ok$9$next[0:0]$9611 $2\sr_op__oe__ok$9$next[0:0]$9637 + assign $0\sr_op__rc__ok$7$next[0:0]$9614 $2\sr_op__rc__ok$7$next[0:0]$9638 + assign $0\sr_op__rc__rc$6$next[0:0]$9615 $2\sr_op__rc__rc$6$next[0:0]$9639 + attribute \src "libresoc.v:168773.5-168773.29" switch \initial - attribute \src "libresoc.v:175416.9-175416.17" + attribute \src "libresoc.v:168773.9-168773.17" case 1'1 case end @@ -357180,41 +348282,116 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9906 $1\xer_ov$next[1:0]$9905 } { \xer_ov_ok$100 \xer_ov$99 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$18$next[31:0]$9622 $1\sr_op__is_signed$17$next[0:0]$9626 $1\sr_op__is_32bit$16$next[0:0]$9625 $1\sr_op__output_cr$15$next[0:0]$9630 $1\sr_op__input_cr$14$next[0:0]$9621 $1\sr_op__output_carry$13$next[0:0]$9629 $1\sr_op__input_carry$12$next[1:0]$9620 $1\sr_op__invert_in$11$next[0:0]$9624 $1\sr_op__write_cr0$10$next[0:0]$9633 $1\sr_op__oe__ok$9$next[0:0]$9628 $1\sr_op__oe__oe$8$next[0:0]$9627 $1\sr_op__rc__ok$7$next[0:0]$9631 $1\sr_op__rc__rc$6$next[0:0]$9632 $1\sr_op__imm_data__ok$5$next[0:0]$9619 $1\sr_op__imm_data__data$4$next[63:0]$9618 $1\sr_op__fn_unit$3$next[12:0]$9617 $1\sr_op__insn_type$2$next[6:0]$9623 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9906 $1\xer_ov$next[1:0]$9905 } { \xer_ov_ok$100 \xer_ov$99 } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$18$next[31:0]$9622 $1\sr_op__is_signed$17$next[0:0]$9626 $1\sr_op__is_32bit$16$next[0:0]$9625 $1\sr_op__output_cr$15$next[0:0]$9630 $1\sr_op__input_cr$14$next[0:0]$9621 $1\sr_op__output_carry$13$next[0:0]$9629 $1\sr_op__input_carry$12$next[1:0]$9620 $1\sr_op__invert_in$11$next[0:0]$9624 $1\sr_op__write_cr0$10$next[0:0]$9633 $1\sr_op__oe__ok$9$next[0:0]$9628 $1\sr_op__oe__oe$8$next[0:0]$9627 $1\sr_op__rc__ok$7$next[0:0]$9631 $1\sr_op__rc__rc$6$next[0:0]$9632 $1\sr_op__imm_data__ok$5$next[0:0]$9619 $1\sr_op__imm_data__data$4$next[63:0]$9618 $1\sr_op__fn_unit$3$next[12:0]$9617 $1\sr_op__insn_type$2$next[6:0]$9623 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } case - assign $1\xer_ov$next[1:0]$9905 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9906 \xer_ov_ok + assign $1\sr_op__fn_unit$3$next[12:0]$9617 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9618 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9619 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9620 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9621 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9622 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9623 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9624 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9625 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9626 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9627 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9628 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9629 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9630 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9631 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9632 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9633 \sr_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9907 1'0 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$4$next[63:0]$9634 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9635 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9639 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9638 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9636 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9637 1'0 case - assign $2\xer_ov_ok$next[0:0]$9907 $1\xer_ov_ok$next[0:0]$9906 + assign $2\sr_op__imm_data__data$4$next[63:0]$9634 $1\sr_op__imm_data__data$4$next[63:0]$9618 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9635 $1\sr_op__imm_data__ok$5$next[0:0]$9619 + assign $2\sr_op__oe__oe$8$next[0:0]$9636 $1\sr_op__oe__oe$8$next[0:0]$9627 + assign $2\sr_op__oe__ok$9$next[0:0]$9637 $1\sr_op__oe__ok$9$next[0:0]$9628 + assign $2\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__ok$7$next[0:0]$9631 + assign $2\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__rc__rc$6$next[0:0]$9632 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9903 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9904 + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[12:0]$9600 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9601 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9602 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9603 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9604 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9605 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9606 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9607 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9608 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9609 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9610 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9611 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9612 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9613 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9614 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9615 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9616 end - attribute \src "libresoc.v:175434.3-175452.6" - process $proc$libresoc.v:175434$9908 + attribute \src "libresoc.v:168813.3-168831.6" + process $proc$libresoc.v:168813$9640 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\o$19$next[63:0]$9641 $1\o$19$next[63:0]$9643 assign { } { } - assign $0\xer_so$20$next[0:0]$9910 $1\xer_so$20$next[0:0]$9912 - assign $0\xer_so_ok$next[0:0]$9909 $2\xer_so_ok$next[0:0]$9913 - attribute \src "libresoc.v:175435.5-175435.29" + assign $0\o_ok$20$next[0:0]$9642 $2\o_ok$20$next[0:0]$9645 + attribute \src "libresoc.v:168814.5-168814.29" switch \initial - attribute \src "libresoc.v:175435.9-175435.17" + attribute \src "libresoc.v:168814.9-168814.17" case 1'1 case end @@ -357224,38 +348401,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9911 $1\xer_so$20$next[0:0]$9912 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\o_ok$20$next[0:0]$9644 $1\o$19$next[63:0]$9643 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9911 $1\xer_so$20$next[0:0]$9912 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\o_ok$20$next[0:0]$9644 $1\o$19$next[63:0]$9643 } { \o_ok$72 \o$71 } case - assign $1\xer_so_ok$next[0:0]$9911 \xer_so_ok - assign $1\xer_so$20$next[0:0]$9912 \xer_so$20 + assign $1\o$19$next[63:0]$9643 \o$19 + assign $1\o_ok$20$next[0:0]$9644 \o_ok$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9913 1'0 + assign $2\o_ok$20$next[0:0]$9645 1'0 case - assign $2\xer_so_ok$next[0:0]$9913 $1\xer_so_ok$next[0:0]$9911 + assign $2\o_ok$20$next[0:0]$9645 $1\o_ok$20$next[0:0]$9644 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9909 - update \xer_so$20$next $0\xer_so$20$next[0:0]$9910 + update \o$19$next $0\o$19$next[63:0]$9641 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9642 end - attribute \src "libresoc.v:175453.3-175470.6" - process $proc$libresoc.v:175453$9914 + attribute \src "libresoc.v:168832.3-168850.6" + process $proc$libresoc.v:168832$9646 + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9915 $2\r_busy$next[0:0]$9917 - attribute \src "libresoc.v:175454.5-175454.29" + assign $0\cr_a$21$next[3:0]$9647 $1\cr_a$21$next[3:0]$9649 + assign { } { } + assign $0\cr_a_ok$22$next[0:0]$9648 $2\cr_a_ok$22$next[0:0]$9651 + attribute \src "libresoc.v:168833.5-168833.29" switch \initial - attribute \src "libresoc.v:175454.9-175454.17" + attribute \src "libresoc.v:168833.9-168833.17" case 1'1 case end @@ -357264,118 +348444,42 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9916 1'1 + assign { } { } + assign { $1\cr_a_ok$22$next[0:0]$9650 $1\cr_a$21$next[3:0]$9649 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9916 1'0 + assign { } { } + assign { $1\cr_a_ok$22$next[0:0]$9650 $1\cr_a$21$next[3:0]$9649 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\r_busy$next[0:0]$9916 \r_busy + assign $1\cr_a$21$next[3:0]$9649 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9650 \cr_a_ok$22 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9917 1'0 - case - assign $2\r_busy$next[0:0]$9917 $1\r_busy$next[0:0]$9916 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$9915 - end - attribute \src "libresoc.v:175471.3-175483.6" - process $proc$libresoc.v:175471$9918 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$9919 $1\muxid$1$next[1:0]$9920 - attribute \src "libresoc.v:175472.5-175472.29" - switch \initial - attribute \src "libresoc.v:175472.9-175472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$9920 \muxid$76 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$9920 \muxid$76 + assign $2\cr_a_ok$22$next[0:0]$9651 1'0 case - assign $1\muxid$1$next[1:0]$9920 \muxid$1 + assign $2\cr_a_ok$22$next[0:0]$9651 $1\cr_a_ok$22$next[0:0]$9650 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9919 + update \cr_a$21$next $0\cr_a$21$next[3:0]$9647 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9648 end - attribute \src "libresoc.v:175484.3-175525.6" - process $proc$libresoc.v:175484$9921 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:168851.3-168869.6" + process $proc$libresoc.v:168851$9652 assign { } { } assign { } { } assign { } { } assign { } { } + assign $0\xer_ca$23$next[1:0]$9653 $1\xer_ca$23$next[1:0]$9655 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$9922 $1\logical_op__data_len$18$next[3:0]$9940 - assign $0\logical_op__fn_unit$3$next[12:0]$9923 $1\logical_op__fn_unit$3$next[12:0]$9941 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$9926 $1\logical_op__input_carry$12$next[1:0]$9944 - assign $0\logical_op__insn$19$next[31:0]$9927 $1\logical_op__insn$19$next[31:0]$9945 - assign $0\logical_op__insn_type$2$next[6:0]$9928 $1\logical_op__insn_type$2$next[6:0]$9946 - assign $0\logical_op__invert_in$10$next[0:0]$9929 $1\logical_op__invert_in$10$next[0:0]$9947 - assign $0\logical_op__invert_out$13$next[0:0]$9930 $1\logical_op__invert_out$13$next[0:0]$9948 - assign $0\logical_op__is_32bit$16$next[0:0]$9931 $1\logical_op__is_32bit$16$next[0:0]$9949 - assign $0\logical_op__is_signed$17$next[0:0]$9932 $1\logical_op__is_signed$17$next[0:0]$9950 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$9935 $1\logical_op__output_carry$15$next[0:0]$9953 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$9938 $1\logical_op__write_cr0$14$next[0:0]$9956 - assign $0\logical_op__zero_a$11$next[0:0]$9939 $1\logical_op__zero_a$11$next[0:0]$9957 - assign $0\logical_op__imm_data__data$4$next[63:0]$9924 $2\logical_op__imm_data__data$4$next[63:0]$9958 - assign $0\logical_op__imm_data__ok$5$next[0:0]$9925 $2\logical_op__imm_data__ok$5$next[0:0]$9959 - assign $0\logical_op__oe__oe$8$next[0:0]$9933 $2\logical_op__oe__oe$8$next[0:0]$9960 - assign $0\logical_op__oe__ok$9$next[0:0]$9934 $2\logical_op__oe__ok$9$next[0:0]$9961 - assign $0\logical_op__rc__ok$7$next[0:0]$9936 $2\logical_op__rc__ok$7$next[0:0]$9962 - assign $0\logical_op__rc__rc$6$next[0:0]$9937 $2\logical_op__rc__rc$6$next[0:0]$9963 - attribute \src "libresoc.v:175485.5-175485.29" + assign $0\xer_ca_ok$24$next[0:0]$9654 $2\xer_ca_ok$24$next[0:0]$9657 + attribute \src "libresoc.v:168852.5-168852.29" switch \initial - attribute \src "libresoc.v:175485.9-175485.17" + attribute \src "libresoc.v:168852.9-168852.17" case 1'1 case end @@ -357385,615 +348489,308 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9945 $1\logical_op__data_len$18$next[3:0]$9940 $1\logical_op__is_signed$17$next[0:0]$9950 $1\logical_op__is_32bit$16$next[0:0]$9949 $1\logical_op__output_carry$15$next[0:0]$9953 $1\logical_op__write_cr0$14$next[0:0]$9956 $1\logical_op__invert_out$13$next[0:0]$9948 $1\logical_op__input_carry$12$next[1:0]$9944 $1\logical_op__zero_a$11$next[0:0]$9957 $1\logical_op__invert_in$10$next[0:0]$9947 $1\logical_op__oe__ok$9$next[0:0]$9952 $1\logical_op__oe__oe$8$next[0:0]$9951 $1\logical_op__rc__ok$7$next[0:0]$9954 $1\logical_op__rc__rc$6$next[0:0]$9955 $1\logical_op__imm_data__ok$5$next[0:0]$9943 $1\logical_op__imm_data__data$4$next[63:0]$9942 $1\logical_op__fn_unit$3$next[12:0]$9941 $1\logical_op__insn_type$2$next[6:0]$9946 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\xer_ca_ok$24$next[0:0]$9656 $1\xer_ca$23$next[1:0]$9655 } { \xer_ca_ok$76 \xer_ca$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9945 $1\logical_op__data_len$18$next[3:0]$9940 $1\logical_op__is_signed$17$next[0:0]$9950 $1\logical_op__is_32bit$16$next[0:0]$9949 $1\logical_op__output_carry$15$next[0:0]$9953 $1\logical_op__write_cr0$14$next[0:0]$9956 $1\logical_op__invert_out$13$next[0:0]$9948 $1\logical_op__input_carry$12$next[1:0]$9944 $1\logical_op__zero_a$11$next[0:0]$9957 $1\logical_op__invert_in$10$next[0:0]$9947 $1\logical_op__oe__ok$9$next[0:0]$9952 $1\logical_op__oe__oe$8$next[0:0]$9951 $1\logical_op__rc__ok$7$next[0:0]$9954 $1\logical_op__rc__rc$6$next[0:0]$9955 $1\logical_op__imm_data__ok$5$next[0:0]$9943 $1\logical_op__imm_data__data$4$next[63:0]$9942 $1\logical_op__fn_unit$3$next[12:0]$9941 $1\logical_op__insn_type$2$next[6:0]$9946 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\xer_ca_ok$24$next[0:0]$9656 $1\xer_ca$23$next[1:0]$9655 } { \xer_ca_ok$76 \xer_ca$75 } case - assign $1\logical_op__data_len$18$next[3:0]$9940 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[12:0]$9941 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$9942 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$9943 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$9944 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$9945 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$9946 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$9947 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$9948 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$9949 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$9950 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$9951 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$9952 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$9953 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$9954 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$9955 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$9956 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$9957 \logical_op__zero_a$11 + assign $1\xer_ca$23$next[1:0]$9655 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9656 \xer_ca_ok$24 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$9958 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9959 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$9963 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$9962 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$9960 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$9961 1'0 + assign $2\xer_ca_ok$24$next[0:0]$9657 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$9958 $1\logical_op__imm_data__data$4$next[63:0]$9942 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9959 $1\logical_op__imm_data__ok$5$next[0:0]$9943 - assign $2\logical_op__oe__oe$8$next[0:0]$9960 $1\logical_op__oe__oe$8$next[0:0]$9951 - assign $2\logical_op__oe__ok$9$next[0:0]$9961 $1\logical_op__oe__ok$9$next[0:0]$9952 - assign $2\logical_op__rc__ok$7$next[0:0]$9962 $1\logical_op__rc__ok$7$next[0:0]$9954 - assign $2\logical_op__rc__rc$6$next[0:0]$9963 $1\logical_op__rc__rc$6$next[0:0]$9955 + assign $2\xer_ca_ok$24$next[0:0]$9657 $1\xer_ca_ok$24$next[0:0]$9656 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9922 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$9923 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9924 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9925 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9926 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9927 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9928 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9929 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9930 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9931 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9932 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9933 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9934 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9935 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9936 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9937 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9938 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9939 + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9653 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9654 end - connect \$74 $and$libresoc.v:175206$9841_Y - connect \cr_a$68 4'0000 - connect \cr_a_ok$69 1'0 - connect \xer_so_ok$72 1'0 + connect \$51 $and$libresoc.v:168633$9542_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy - connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } - connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } - connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } - connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } - connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } - connect \muxid$76 \output_muxid$41 - connect \p_valid_i_p_ready_o \$74 + connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$72 \o$71 } { \output_o_ok$44 \output_o$43 } + connect { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } { \output_sr_op__insn$42 \output_sr_op__is_signed$41 \output_sr_op__is_32bit$40 \output_sr_op__output_cr$39 \output_sr_op__input_cr$38 \output_sr_op__output_carry$37 \output_sr_op__input_carry$36 \output_sr_op__invert_in$35 \output_sr_op__write_cr0$34 \output_sr_op__oe__ok$33 \output_sr_op__oe__oe$32 \output_sr_op__rc__ok$31 \output_sr_op__rc__rc$30 \output_sr_op__imm_data__ok$29 \output_sr_op__imm_data__data$28 \output_sr_op__fn_unit$27 \output_sr_op__insn_type$26 } + connect \muxid$53 \output_muxid$25 + connect \p_valid_i_p_ready_o \$51 connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$73 \p_valid_i - connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } - connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } - connect { \cr_a_ok$67 \output_cr_a } 5'00000 - connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } - connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } - connect \output_muxid \output_stage_muxid$21 - connect \output_stage_remainder \remainder - connect \output_stage_quotient_root \quotient_root - connect \output_stage_div_by_zero \div_by_zero - connect \output_stage_dive_abs_ov64 \dive_abs_ov64 - connect \output_stage_dive_abs_ov32 \dive_abs_ov32 - connect \output_stage_dividend_neg \dividend_neg - connect \output_stage_divisor_neg \divisor_neg - connect \output_stage_xer_so \xer_so - connect \rb$66 \rb - connect \ra$65 \ra - connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \output_stage_muxid \muxid + connect \p_valid_i$50 \p_valid_i + connect { \xer_ca_ok$49 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \xer_so_ok$48 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$47 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \output_muxid \muxid end -attribute \src "libresoc.v:175562.1-176543.10" +attribute \src "libresoc.v:168890.1-169844.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" -module \pipe_middle_0 - attribute \src "libresoc.v:176468.3-176482.6" - wire $0\div_by_zero$54$next[0:0]$10192 - attribute \src "libresoc.v:176142.3-176143.47" - wire $0\div_by_zero$54[0:0]$10027 - attribute \src "libresoc.v:175585.7-175585.30" - wire $0\div_by_zero$54[0:0]$10209 - attribute \src "libresoc.v:176264.3-176275.6" - wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:176252.3-176263.6" - wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:176240.3-176251.6" - wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:176438.3-176452.6" - wire $0\dive_abs_ov32$52$next[0:0]$10184 - attribute \src "libresoc.v:176146.3-176147.51" - wire $0\dive_abs_ov32$52[0:0]$10031 - attribute \src "libresoc.v:175609.7-175609.32" - wire $0\dive_abs_ov32$52[0:0]$10211 - attribute \src "libresoc.v:176453.3-176467.6" - wire $0\dive_abs_ov64$53$next[0:0]$10188 - attribute \src "libresoc.v:176144.3-176145.51" - wire $0\dive_abs_ov64$53[0:0]$10029 - attribute \src "libresoc.v:175617.7-175617.32" - wire $0\dive_abs_ov64$53[0:0]$10213 - attribute \src "libresoc.v:176483.3-176497.6" - wire width 128 $0\dividend$68$next[127:0]$10196 - attribute \src "libresoc.v:176140.3-176141.41" - wire width 128 $0\dividend$68[127:0]$10025 - attribute \src "libresoc.v:175623.15-175623.68" - wire width 128 $0\dividend$68[127:0]$10215 - attribute \src "libresoc.v:176423.3-176437.6" - wire $0\dividend_neg$51$next[0:0]$10180 - attribute \src "libresoc.v:176148.3-176149.49" - wire $0\dividend_neg$51[0:0]$10033 - attribute \src "libresoc.v:175631.7-175631.31" - wire $0\dividend_neg$51[0:0]$10217 - attribute \src "libresoc.v:176408.3-176422.6" - wire $0\divisor_neg$50$next[0:0]$10176 - attribute \src "libresoc.v:176150.3-176151.47" - wire $0\divisor_neg$50[0:0]$10035 - attribute \src "libresoc.v:175639.7-175639.30" - wire $0\divisor_neg$50[0:0]$10219 - attribute \src "libresoc.v:176498.3-176512.6" - wire width 64 $0\divisor_radicand$65$next[63:0]$10200 - attribute \src "libresoc.v:176138.3-176139.57" - wire width 64 $0\divisor_radicand$65[63:0]$10023 - attribute \src "libresoc.v:175645.14-175645.58" - wire width 64 $0\divisor_radicand$65[63:0]$10221 - attribute \src "libresoc.v:176276.3-176303.6" - wire $0\empty$next[0:0]$10093 - attribute \src "libresoc.v:176196.3-176197.27" - wire $0\empty[0:0] - attribute \src "libresoc.v:175563.7-175563.20" +module \pipe2$35 + attribute \src "libresoc.v:169750.3-169768.6" + wire width 64 $0\fast1$11$next[63:0]$9776 + attribute \src "libresoc.v:169605.3-169606.35" + wire width 64 $0\fast1$11[63:0]$9717 + attribute \src "libresoc.v:168902.14-168902.47" + wire width 64 $0\fast1$11[63:0]$9800 + attribute \src "libresoc.v:169750.3-169768.6" + wire $0\fast1_ok$next[0:0]$9775 + attribute \src "libresoc.v:169607.3-169608.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:169769.3-169787.6" + wire width 64 $0\fast2$12$next[63:0]$9782 + attribute \src "libresoc.v:169601.3-169602.35" + wire width 64 $0\fast2$12[63:0]$9714 + attribute \src "libresoc.v:168918.14-168918.47" + wire width 64 $0\fast2$12[63:0]$9803 + attribute \src "libresoc.v:169769.3-169787.6" + wire $0\fast2_ok$next[0:0]$9781 + attribute \src "libresoc.v:169603.3-169604.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:168891.7-168891.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176319.3-176362.6" - wire width 4 $0\logical_op__data_len$45$next[3:0]$10103 - attribute \src "libresoc.v:176190.3-176191.65" - wire width 4 $0\logical_op__data_len$45[3:0]$10075 - attribute \src "libresoc.v:175657.13-175657.45" - wire width 4 $0\logical_op__data_len$45[3:0]$10224 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 13 $0\logical_op__fn_unit$30$next[12:0]$10104 - attribute \src "libresoc.v:176160.3-176161.63" - wire width 13 $0\logical_op__fn_unit$30[12:0]$10045 - attribute \src "libresoc.v:175707.14-175707.49" - wire width 13 $0\logical_op__fn_unit$30[12:0]$10226 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10105 - attribute \src "libresoc.v:176162.3-176163.77" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$10047 - attribute \src "libresoc.v:175713.14-175713.68" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$10228 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__imm_data__ok$32$next[0:0]$10106 - attribute \src "libresoc.v:176164.3-176165.73" - wire $0\logical_op__imm_data__ok$32[0:0]$10049 - attribute \src "libresoc.v:175721.7-175721.43" - wire $0\logical_op__imm_data__ok$32[0:0]$10230 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 2 $0\logical_op__input_carry$39$next[1:0]$10107 - attribute \src "libresoc.v:176178.3-176179.71" - wire width 2 $0\logical_op__input_carry$39[1:0]$10063 - attribute \src "libresoc.v:175743.13-175743.48" - wire width 2 $0\logical_op__input_carry$39[1:0]$10232 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 32 $0\logical_op__insn$46$next[31:0]$10108 - attribute \src "libresoc.v:176192.3-176193.57" - wire width 32 $0\logical_op__insn$46[31:0]$10077 - attribute \src "libresoc.v:175751.14-175751.43" - wire width 32 $0\logical_op__insn$46[31:0]$10234 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 7 $0\logical_op__insn_type$29$next[6:0]$10109 - attribute \src "libresoc.v:176158.3-176159.67" - wire width 7 $0\logical_op__insn_type$29[6:0]$10043 - attribute \src "libresoc.v:175981.13-175981.47" - wire width 7 $0\logical_op__insn_type$29[6:0]$10236 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__invert_in$37$next[0:0]$10110 - attribute \src "libresoc.v:176174.3-176175.67" - wire $0\logical_op__invert_in$37[0:0]$10059 - attribute \src "libresoc.v:175989.7-175989.40" - wire $0\logical_op__invert_in$37[0:0]$10238 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__invert_out$40$next[0:0]$10111 - attribute \src "libresoc.v:176180.3-176181.69" - wire $0\logical_op__invert_out$40[0:0]$10065 - attribute \src "libresoc.v:175997.7-175997.41" - wire $0\logical_op__invert_out$40[0:0]$10240 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__is_32bit$43$next[0:0]$10112 - attribute \src "libresoc.v:176186.3-176187.65" - wire $0\logical_op__is_32bit$43[0:0]$10071 - attribute \src "libresoc.v:176005.7-176005.39" - wire $0\logical_op__is_32bit$43[0:0]$10242 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__is_signed$44$next[0:0]$10113 - attribute \src "libresoc.v:176188.3-176189.67" - wire $0\logical_op__is_signed$44[0:0]$10073 - attribute \src "libresoc.v:176013.7-176013.40" - wire $0\logical_op__is_signed$44[0:0]$10244 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__oe__oe$35$next[0:0]$10114 - attribute \src "libresoc.v:176170.3-176171.61" - wire $0\logical_op__oe__oe$35[0:0]$10055 - attribute \src "libresoc.v:176019.7-176019.37" - wire $0\logical_op__oe__oe$35[0:0]$10246 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__oe__ok$36$next[0:0]$10115 - attribute \src "libresoc.v:176172.3-176173.61" - wire $0\logical_op__oe__ok$36[0:0]$10057 - attribute \src "libresoc.v:176027.7-176027.37" - wire $0\logical_op__oe__ok$36[0:0]$10248 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__output_carry$42$next[0:0]$10116 - attribute \src "libresoc.v:176184.3-176185.73" - wire $0\logical_op__output_carry$42[0:0]$10069 - attribute \src "libresoc.v:176037.7-176037.43" - wire $0\logical_op__output_carry$42[0:0]$10250 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__rc__ok$34$next[0:0]$10117 - attribute \src "libresoc.v:176168.3-176169.61" - wire $0\logical_op__rc__ok$34[0:0]$10053 - attribute \src "libresoc.v:176043.7-176043.37" - wire $0\logical_op__rc__ok$34[0:0]$10252 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__rc__rc$33$next[0:0]$10118 - attribute \src "libresoc.v:176166.3-176167.61" - wire $0\logical_op__rc__rc$33[0:0]$10051 - attribute \src "libresoc.v:176051.7-176051.37" - wire $0\logical_op__rc__rc$33[0:0]$10254 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__write_cr0$41$next[0:0]$10119 - attribute \src "libresoc.v:176182.3-176183.67" - wire $0\logical_op__write_cr0$41[0:0]$10067 - attribute \src "libresoc.v:176061.7-176061.40" - wire $0\logical_op__write_cr0$41[0:0]$10256 - attribute \src "libresoc.v:176319.3-176362.6" - wire $0\logical_op__zero_a$38$next[0:0]$10120 - attribute \src "libresoc.v:176176.3-176177.61" - wire $0\logical_op__zero_a$38[0:0]$10061 - attribute \src "libresoc.v:176069.7-176069.37" - wire $0\logical_op__zero_a$38[0:0]$10258 - attribute \src "libresoc.v:176304.3-176318.6" - wire width 2 $0\muxid$28$next[1:0]$10099 - attribute \src "libresoc.v:176194.3-176195.35" - wire width 2 $0\muxid$28[1:0]$10079 - attribute \src "libresoc.v:176077.13-176077.30" - wire width 2 $0\muxid$28[1:0]$10260 - attribute \src "libresoc.v:176513.3-176527.6" - wire width 2 $0\operation$69$next[1:0]$10204 - attribute \src "libresoc.v:176136.3-176137.43" - wire width 2 $0\operation$69[1:0]$10021 - attribute \src "libresoc.v:176087.13-176087.34" - wire width 2 $0\operation$69[1:0]$10262 - attribute \src "libresoc.v:176363.3-176377.6" - wire width 64 $0\ra$47$next[63:0]$10164 - attribute \src "libresoc.v:176156.3-176157.29" - wire width 64 $0\ra$47[63:0]$10041 - attribute \src "libresoc.v:176101.14-176101.44" - wire width 64 $0\ra$47[63:0]$10264 - attribute \src "libresoc.v:176378.3-176392.6" - wire width 64 $0\rb$48$next[63:0]$10168 - attribute \src "libresoc.v:176154.3-176155.29" - wire width 64 $0\rb$48[63:0]$10039 - attribute \src "libresoc.v:176109.14-176109.44" - wire width 64 $0\rb$48[63:0]$10266 - attribute \src "libresoc.v:176231.3-176239.6" - wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10087 - attribute \src "libresoc.v:176198.3-176199.75" - wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:176222.3-176230.6" - wire width 7 $0\saved_state_q_bits_known$next[6:0]$10084 - attribute \src "libresoc.v:176200.3-176201.65" - wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:176393.3-176407.6" - wire $0\xer_so$49$next[0:0]$10172 - attribute \src "libresoc.v:176152.3-176153.37" - wire $0\xer_so$49[0:0]$10037 - attribute \src "libresoc.v:176127.7-176127.25" - wire $0\xer_so$49[0:0]$10270 - attribute \src "libresoc.v:176468.3-176482.6" - wire $1\div_by_zero$54$next[0:0]$10193 - attribute \src "libresoc.v:176264.3-176275.6" - wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:176252.3-176263.6" - wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:176240.3-176251.6" - wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:176438.3-176452.6" - wire $1\dive_abs_ov32$52$next[0:0]$10185 - attribute \src "libresoc.v:176453.3-176467.6" - wire $1\dive_abs_ov64$53$next[0:0]$10189 - attribute \src "libresoc.v:176483.3-176497.6" - wire width 128 $1\dividend$68$next[127:0]$10197 - attribute \src "libresoc.v:176423.3-176437.6" - wire $1\dividend_neg$51$next[0:0]$10181 - attribute \src "libresoc.v:176408.3-176422.6" - wire $1\divisor_neg$50$next[0:0]$10177 - attribute \src "libresoc.v:176498.3-176512.6" - wire width 64 $1\divisor_radicand$65$next[63:0]$10201 - attribute \src "libresoc.v:176276.3-176303.6" - wire $1\empty$next[0:0]$10094 - attribute \src "libresoc.v:175649.7-175649.19" - wire $1\empty[0:0] - attribute \src "libresoc.v:176319.3-176362.6" - wire width 4 $1\logical_op__data_len$45$next[3:0]$10121 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 13 $1\logical_op__fn_unit$30$next[12:0]$10122 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10123 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__imm_data__ok$32$next[0:0]$10124 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 2 $1\logical_op__input_carry$39$next[1:0]$10125 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 32 $1\logical_op__insn$46$next[31:0]$10126 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 7 $1\logical_op__insn_type$29$next[6:0]$10127 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__invert_in$37$next[0:0]$10128 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__invert_out$40$next[0:0]$10129 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__is_32bit$43$next[0:0]$10130 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__is_signed$44$next[0:0]$10131 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__oe__oe$35$next[0:0]$10132 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__oe__ok$36$next[0:0]$10133 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__output_carry$42$next[0:0]$10134 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__rc__ok$34$next[0:0]$10135 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__rc__rc$33$next[0:0]$10136 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__write_cr0$41$next[0:0]$10137 - attribute \src "libresoc.v:176319.3-176362.6" - wire $1\logical_op__zero_a$38$next[0:0]$10138 - attribute \src "libresoc.v:176304.3-176318.6" - wire width 2 $1\muxid$28$next[1:0]$10100 - attribute \src "libresoc.v:176513.3-176527.6" - wire width 2 $1\operation$69$next[1:0]$10205 - attribute \src "libresoc.v:176363.3-176377.6" - wire width 64 $1\ra$47$next[63:0]$10165 - attribute \src "libresoc.v:176378.3-176392.6" - wire width 64 $1\rb$48$next[63:0]$10169 - attribute \src "libresoc.v:176231.3-176239.6" - wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10088 - attribute \src "libresoc.v:176115.15-176115.84" - wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:176222.3-176230.6" - wire width 7 $1\saved_state_q_bits_known$next[6:0]$10085 - attribute \src "libresoc.v:176119.13-176119.45" - wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:176393.3-176407.6" - wire $1\xer_so$49$next[0:0]$10173 - attribute \src "libresoc.v:176468.3-176482.6" - wire $2\div_by_zero$54$next[0:0]$10194 - attribute \src "libresoc.v:176438.3-176452.6" - wire $2\dive_abs_ov32$52$next[0:0]$10186 - attribute \src "libresoc.v:176453.3-176467.6" - wire $2\dive_abs_ov64$53$next[0:0]$10190 - attribute \src "libresoc.v:176483.3-176497.6" - wire width 128 $2\dividend$68$next[127:0]$10198 - attribute \src "libresoc.v:176423.3-176437.6" - wire $2\dividend_neg$51$next[0:0]$10182 - attribute \src "libresoc.v:176408.3-176422.6" - wire $2\divisor_neg$50$next[0:0]$10178 - attribute \src "libresoc.v:176498.3-176512.6" - wire width 64 $2\divisor_radicand$65$next[63:0]$10202 - attribute \src "libresoc.v:176276.3-176303.6" - wire $2\empty$next[0:0]$10095 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 4 $2\logical_op__data_len$45$next[3:0]$10139 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 13 $2\logical_op__fn_unit$30$next[12:0]$10140 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10141 - attribute \src "libresoc.v:176319.3-176362.6" - wire $2\logical_op__imm_data__ok$32$next[0:0]$10142 - attribute \src "libresoc.v:176319.3-176362.6" - wire width 2 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"/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$68$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire output 59 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$51$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire input 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire output 58 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$50$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 input 32 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$65$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" - wire \empty - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" - wire \empty$next - attribute \src "libresoc.v:175563.7-175563.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 32 \fast1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 34 \fast2$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 35 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$next + attribute \src "libresoc.v:168891.7-168891.15" wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast1$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast2$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 53 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45 + wire width 64 \main_trap_op__cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45$next + wire width 64 \main_trap_op__cia$18 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -358009,7 +348806,7 @@ module \pipe_middle_0 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 6 \logical_op__fn_unit + wire width 13 \main_trap_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -358025,7 +348822,257 @@ module \pipe_middle_0 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 38 \logical_op__fn_unit$3 + wire width 13 \main_trap_op__fn_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_trap_op__insn$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_trap_op__insn_type$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_trap_op__is_32bit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \main_trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \main_trap_op__ldst_exc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__msr$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \main_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \main_trap_op__traptype$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 20 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 19 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 18 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 36 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 30 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 15 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$6$next attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -358041,53 +349088,49 @@ module \pipe_middle_0 attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$30$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$31$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 39 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$32$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 13 input 6 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 47 \logical_op__input_carry$12 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" + wire width 13 output 22 \trap_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39 + wire width 13 \trap_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39$next + wire width 13 \trap_op__fn_unit$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn + wire width 32 input 7 \trap_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 54 \logical_op__insn$19 + wire width 32 \trap_op__insn$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46 + wire width 32 output 23 \trap_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46$next + wire width 32 \trap_op__insn$4$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -358163,7 +349206,7 @@ module \pipe_middle_0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type + wire width 7 input 5 \trap_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -358239,7 +349282,9 @@ module \pipe_middle_0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 37 \logical_op__insn_type$2 + wire width 7 output 21 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -358315,978 +349360,497 @@ module \pipe_middle_0 attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$37$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$40$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$43$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 52 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$44$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$35$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$36$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry + wire width 7 \trap_op__insn_type$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \logical_op__output_carry$15 + wire input 10 \trap_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$42 + wire \trap_op__is_32bit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$42$next + wire output 26 \trap_op__is_32bit$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok + wire \trap_op__is_32bit$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$34 + wire width 8 input 13 \trap_op__ldst_exc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$34$next + wire width 8 output 29 \trap_op__ldst_exc$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \logical_op__rc__ok$7 + wire width 8 \trap_op__ldst_exc$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc + wire width 8 \trap_op__ldst_exc$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$33 + wire width 64 input 8 \trap_op__msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$33$next + wire width 64 \trap_op__msr$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__rc__rc$6 + wire width 64 output 24 \trap_op__msr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 + wire width 64 \trap_op__msr$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \logical_op__write_cr0$14 + wire width 13 input 12 \trap_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$41 + wire width 13 \trap_op__trapaddr$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$41$next + wire width 13 output 28 \trap_op__trapaddr$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a + wire width 13 \trap_op__trapaddr$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \logical_op__zero_a$11 + wire width 8 input 11 \trap_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$38 + wire width 8 \trap_op__traptype$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$38$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 36 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$28$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 35 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 34 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 input 33 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$69$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 output 63 \quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 55 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$47$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 56 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$48$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 output 64 \remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \saved_state_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \saved_state_dividend_quotient$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \saved_state_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \saved_state_q_bits_known$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 57 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$49$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $and $and$libresoc.v:176134$10018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$59 - connect \B \$61 - connect \Y $and$libresoc.v:176134$10018_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - cell $and $and$libresoc.v:176135$10019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:176135$10019_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $extend$libresoc.v:176131$10014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 191 - parameter \Y_WIDTH 192 - connect \A \$56 - connect \Y $extend$libresoc.v:176131$10014_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:176133$10017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \saved_state_q_bits_known - connect \B 6'111111 - connect \Y $ge$libresoc.v:176133$10017_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $not $not$libresoc.v:176132$10016 + wire width 8 output 27 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$8$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:169592$9708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \empty - connect \Y $not$libresoc.v:176132$10016_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $pos$libresoc.v:176131$10015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:176131$10014_Y - connect \Y $pos$libresoc.v:176131$10015_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $sshl $sshl$libresoc.v:176130$10013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 191 - connect \A \div_state_next_o_dividend_quotient [127:64] - connect \B 7'1000000 - connect \Y $sshl$libresoc.v:176130$10013_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:176202.18-176206.4" - cell \div_state_init \div_state_init - connect \dividend \div_state_init_dividend - connect \o_dividend_quotient \div_state_init_o_dividend_quotient - connect \o_q_bits_known \div_state_init_o_q_bits_known + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$25 + connect \B \p_ready_o + connect \Y $and$libresoc.v:169592$9708_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:176207.18-176213.4" - cell \div_state_next \div_state_next - connect \divisor \div_state_next_divisor - connect \i_dividend_quotient \div_state_next_i_dividend_quotient - connect \i_q_bits_known \div_state_next_i_q_bits_known - connect \o_dividend_quotient \div_state_next_o_dividend_quotient - connect \o_q_bits_known \div_state_next_o_q_bits_known + attribute \src "libresoc.v:169635.13-169670.4" + cell \main$38 \main + connect \fast1 \main_fast1 + connect \fast1$11 \main_fast1$23 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$12 \main_fast2$24 + connect \fast2_ok \main_fast2_ok + connect \msr \main_msr + connect \msr_ok \main_msr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$13 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \trap_op__cia \main_trap_op__cia + connect \trap_op__cia$6 \main_trap_op__cia$18 + connect \trap_op__fn_unit \main_trap_op__fn_unit + connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$15 + connect \trap_op__insn \main_trap_op__insn + connect \trap_op__insn$4 \main_trap_op__insn$16 + connect \trap_op__insn_type \main_trap_op__insn_type + connect \trap_op__insn_type$2 \main_trap_op__insn_type$14 + connect \trap_op__is_32bit \main_trap_op__is_32bit + connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$19 + connect \trap_op__ldst_exc \main_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \main_trap_op__ldst_exc$22 + connect \trap_op__msr \main_trap_op__msr + connect \trap_op__msr$5 \main_trap_op__msr$17 + connect \trap_op__trapaddr \main_trap_op__trapaddr + connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$21 + connect \trap_op__traptype \main_trap_op__traptype + connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 - attribute \src "libresoc.v:176214.10-176217.4" - cell \n$80 \n + attribute \src "libresoc.v:169671.10-169674.4" + cell \n$37 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:176218.10-176221.4" - cell \p$79 \p + attribute \src "libresoc.v:169675.10-169678.4" + cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:175563.7-175563.20" - process $proc$libresoc.v:175563$10207 + attribute \src "libresoc.v:168891.7-168891.20" + process $proc$libresoc.v:168891$9798 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175585.7-175585.30" - process $proc$libresoc.v:175585$10208 - assign { } { } - assign $0\div_by_zero$54[0:0]$10209 1'0 - sync always - sync init - update \div_by_zero$54 $0\div_by_zero$54[0:0]$10209 - end - attribute \src "libresoc.v:175609.7-175609.32" - process $proc$libresoc.v:175609$10210 - assign { } { } - assign $0\dive_abs_ov32$52[0:0]$10211 1'0 - sync always - sync init - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10211 - end - attribute \src "libresoc.v:175617.7-175617.32" - process $proc$libresoc.v:175617$10212 - assign { } { } - assign $0\dive_abs_ov64$53[0:0]$10213 1'0 - sync always - sync init - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10213 - end - attribute \src "libresoc.v:175623.15-175623.68" - process $proc$libresoc.v:175623$10214 - assign { } { } - assign $0\dividend$68[127:0]$10215 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dividend$68 $0\dividend$68[127:0]$10215 - end - attribute \src "libresoc.v:175631.7-175631.31" - process $proc$libresoc.v:175631$10216 - assign { } { } - assign $0\dividend_neg$51[0:0]$10217 1'0 - sync always - sync init - update \dividend_neg$51 $0\dividend_neg$51[0:0]$10217 - end - attribute \src "libresoc.v:175639.7-175639.30" - process $proc$libresoc.v:175639$10218 - assign { } { } - assign $0\divisor_neg$50[0:0]$10219 1'0 - sync always - sync init - update \divisor_neg$50 $0\divisor_neg$50[0:0]$10219 - end - attribute \src "libresoc.v:175645.14-175645.58" - process $proc$libresoc.v:175645$10220 - assign { } { } - assign $0\divisor_radicand$65[63:0]$10221 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10221 - end - attribute \src "libresoc.v:175649.7-175649.19" - process $proc$libresoc.v:175649$10222 - assign { } { } - assign $1\empty[0:0] 1'1 - sync always - sync init - update \empty $1\empty[0:0] - end - attribute \src "libresoc.v:175657.13-175657.45" - process $proc$libresoc.v:175657$10223 - assign { } { } - assign $0\logical_op__data_len$45[3:0]$10224 4'0000 - sync always - sync init - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10224 - end - attribute \src "libresoc.v:175707.14-175707.49" - process $proc$libresoc.v:175707$10225 + attribute \src "libresoc.v:168902.14-168902.47" + process $proc$libresoc.v:168902$9799 assign { } { } - assign $0\logical_op__fn_unit$30[12:0]$10226 13'0000000000000 + assign $0\fast1$11[63:0]$9800 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$10226 + update \fast1$11 $0\fast1$11[63:0]$9800 end - attribute \src "libresoc.v:175713.14-175713.68" - process $proc$libresoc.v:175713$10227 + attribute \src "libresoc.v:168909.7-168909.22" + process $proc$libresoc.v:168909$9801 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$10228 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10228 - end - attribute \src "libresoc.v:175721.7-175721.43" - process $proc$libresoc.v:175721$10229 - assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$10230 1'0 - sync always - sync init - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10230 - end - attribute \src "libresoc.v:175743.13-175743.48" - process $proc$libresoc.v:175743$10231 - assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10232 2'00 - sync always - sync init - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10232 - end - attribute \src "libresoc.v:175751.14-175751.43" - process $proc$libresoc.v:175751$10233 - assign { } { } - assign $0\logical_op__insn$46[31:0]$10234 0 + assign $1\fast1_ok[0:0] 1'0 sync always sync init - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10234 + update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:175981.13-175981.47" - process $proc$libresoc.v:175981$10235 + attribute \src "libresoc.v:168918.14-168918.47" + process $proc$libresoc.v:168918$9802 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$10236 7'0000000 + assign $0\fast2$12[63:0]$9803 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10236 + update \fast2$12 $0\fast2$12[63:0]$9803 end - attribute \src "libresoc.v:175989.7-175989.40" - process $proc$libresoc.v:175989$10237 + attribute \src "libresoc.v:168925.7-168925.22" + process $proc$libresoc.v:168925$9804 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10238 1'0 + assign $1\fast2_ok[0:0] 1'0 sync always sync init - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10238 + update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:175997.7-175997.41" - process $proc$libresoc.v:175997$10239 + attribute \src "libresoc.v:169176.14-169176.40" + process $proc$libresoc.v:169176$9805 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10240 1'0 + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10240 + update \msr $1\msr[63:0] end - attribute \src "libresoc.v:176005.7-176005.39" - process $proc$libresoc.v:176005$10241 + attribute \src "libresoc.v:169183.7-169183.20" + process $proc$libresoc.v:169183$9806 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10242 1'0 + assign $1\msr_ok[0:0] 1'0 sync always sync init - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10242 + update \msr_ok $1\msr_ok[0:0] end - attribute \src "libresoc.v:176013.7-176013.40" - process $proc$libresoc.v:176013$10243 + attribute \src "libresoc.v:169192.13-169192.29" + process $proc$libresoc.v:169192$9807 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10244 1'0 + assign $0\muxid$1[1:0]$9808 2'00 sync always sync init - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10244 + update \muxid$1 $0\muxid$1[1:0]$9808 end - attribute \src "libresoc.v:176019.7-176019.37" - process $proc$libresoc.v:176019$10245 + attribute \src "libresoc.v:169205.14-169205.40" + process $proc$libresoc.v:169205$9809 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10246 1'0 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10246 + update \nia $1\nia[63:0] end - attribute \src "libresoc.v:176027.7-176027.37" - process $proc$libresoc.v:176027$10247 + attribute \src "libresoc.v:169212.7-169212.20" + process $proc$libresoc.v:169212$9810 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10248 1'0 + assign $1\nia_ok[0:0] 1'0 sync always sync init - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10248 + update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:176037.7-176037.43" - process $proc$libresoc.v:176037$10249 + attribute \src "libresoc.v:169219.14-169219.38" + process $proc$libresoc.v:169219$9811 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10250 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10250 + update \o $1\o[63:0] end - attribute \src "libresoc.v:176043.7-176043.37" - process $proc$libresoc.v:176043$10251 + attribute \src "libresoc.v:169226.7-169226.18" + process $proc$libresoc.v:169226$9812 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10252 1'0 + assign $1\o_ok[0:0] 1'0 sync always sync init - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10252 + update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:176051.7-176051.37" - process $proc$libresoc.v:176051$10253 + attribute \src "libresoc.v:169240.7-169240.20" + process $proc$libresoc.v:169240$9813 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10254 1'0 + assign $1\r_busy[0:0] 1'0 sync always sync init - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10254 + update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:176061.7-176061.40" - process $proc$libresoc.v:176061$10255 + attribute \src "libresoc.v:169253.14-169253.53" + process $proc$libresoc.v:169253$9814 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10256 1'0 + assign $0\trap_op__cia$6[63:0]$9815 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10256 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9815 end - attribute \src "libresoc.v:176069.7-176069.37" - process $proc$libresoc.v:176069$10257 + attribute \src "libresoc.v:169288.14-169288.45" + process $proc$libresoc.v:169288$9816 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10258 1'0 + assign $0\trap_op__fn_unit$3[12:0]$9817 13'0000000000000 sync always sync init - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10258 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9817 end - attribute \src "libresoc.v:176077.13-176077.30" - process $proc$libresoc.v:176077$10259 + attribute \src "libresoc.v:169313.14-169313.39" + process $proc$libresoc.v:169313$9818 assign { } { } - assign $0\muxid$28[1:0]$10260 2'00 + assign $0\trap_op__insn$4[31:0]$9819 0 sync always sync init - update \muxid$28 $0\muxid$28[1:0]$10260 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9819 end - attribute \src "libresoc.v:176087.13-176087.34" - process $proc$libresoc.v:176087$10261 + attribute \src "libresoc.v:169468.13-169468.43" + process $proc$libresoc.v:169468$9820 assign { } { } - assign $0\operation$69[1:0]$10262 2'00 + assign $0\trap_op__insn_type$2[6:0]$9821 7'0000000 sync always sync init - update \operation$69 $0\operation$69[1:0]$10262 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9821 end - attribute \src "libresoc.v:176101.14-176101.44" - process $proc$libresoc.v:176101$10263 + attribute \src "libresoc.v:169553.7-169553.35" + process $proc$libresoc.v:169553$9822 assign { } { } - assign $0\ra$47[63:0]$10264 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__is_32bit$7[0:0]$9823 1'0 sync always sync init - update \ra$47 $0\ra$47[63:0]$10264 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9823 end - attribute \src "libresoc.v:176109.14-176109.44" - process $proc$libresoc.v:176109$10265 + attribute \src "libresoc.v:169560.13-169560.43" + process $proc$libresoc.v:169560$9824 assign { } { } - assign $0\rb$48[63:0]$10266 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__ldst_exc$10[7:0]$9825 8'00000000 sync always sync init - update \rb$48 $0\rb$48[63:0]$10266 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9825 end - attribute \src "libresoc.v:176115.15-176115.84" - process $proc$libresoc.v:176115$10267 + attribute \src "libresoc.v:169571.14-169571.53" + process $proc$libresoc.v:169571$9826 assign { } { } - assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__msr$5[63:0]$9827 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9827 end - attribute \src "libresoc.v:176119.13-176119.45" - process $proc$libresoc.v:176119$10268 + attribute \src "libresoc.v:169580.14-169580.46" + process $proc$libresoc.v:169580$9828 assign { } { } - assign $1\saved_state_q_bits_known[6:0] 7'0000000 + assign $0\trap_op__trapaddr$9[12:0]$9829 13'0000000000000 sync always sync init - update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9829 end - attribute \src "libresoc.v:176127.7-176127.25" - process $proc$libresoc.v:176127$10269 + attribute \src "libresoc.v:169589.13-169589.42" + process $proc$libresoc.v:169589$9830 assign { } { } - assign $0\xer_so$49[0:0]$10270 1'0 + assign $0\trap_op__traptype$8[7:0]$9831 8'00000000 sync always sync init - update \xer_so$49 $0\xer_so$49[0:0]$10270 - end - attribute \src "libresoc.v:176136.3-176137.43" - process $proc$libresoc.v:176136$10020 - assign { } { } - assign $0\operation$69[1:0]$10021 \operation$69$next - sync posedge \coresync_clk - update \operation$69 $0\operation$69[1:0]$10021 - end - attribute \src "libresoc.v:176138.3-176139.57" - process $proc$libresoc.v:176138$10022 - assign { } { } - assign $0\divisor_radicand$65[63:0]$10023 \divisor_radicand$65$next - sync posedge \coresync_clk - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10023 - end - attribute \src "libresoc.v:176140.3-176141.41" - process $proc$libresoc.v:176140$10024 - assign { } { } - assign $0\dividend$68[127:0]$10025 \dividend$68$next - sync posedge \coresync_clk - update \dividend$68 $0\dividend$68[127:0]$10025 - end - attribute \src "libresoc.v:176142.3-176143.47" - process $proc$libresoc.v:176142$10026 - assign { } { } - assign $0\div_by_zero$54[0:0]$10027 \div_by_zero$54$next - sync posedge \coresync_clk - update \div_by_zero$54 $0\div_by_zero$54[0:0]$10027 - end - attribute \src "libresoc.v:176144.3-176145.51" - process $proc$libresoc.v:176144$10028 - assign { } { } - assign $0\dive_abs_ov64$53[0:0]$10029 \dive_abs_ov64$53$next - sync posedge \coresync_clk - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10029 - end - attribute \src "libresoc.v:176146.3-176147.51" - process $proc$libresoc.v:176146$10030 - assign { } { } - assign $0\dive_abs_ov32$52[0:0]$10031 \dive_abs_ov32$52$next - sync posedge \coresync_clk - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10031 - end - attribute \src "libresoc.v:176148.3-176149.49" - process $proc$libresoc.v:176148$10032 - assign { } { } - assign $0\dividend_neg$51[0:0]$10033 \dividend_neg$51$next - sync posedge \coresync_clk - update \dividend_neg$51 $0\dividend_neg$51[0:0]$10033 - end - attribute \src "libresoc.v:176150.3-176151.47" - process $proc$libresoc.v:176150$10034 - assign { } { } - assign $0\divisor_neg$50[0:0]$10035 \divisor_neg$50$next - sync posedge \coresync_clk - update \divisor_neg$50 $0\divisor_neg$50[0:0]$10035 - end - attribute \src "libresoc.v:176152.3-176153.37" - process $proc$libresoc.v:176152$10036 - assign { } { } - assign $0\xer_so$49[0:0]$10037 \xer_so$49$next - sync posedge \coresync_clk - update \xer_so$49 $0\xer_so$49[0:0]$10037 - end - attribute \src "libresoc.v:176154.3-176155.29" - process $proc$libresoc.v:176154$10038 - assign { } { } - assign $0\rb$48[63:0]$10039 \rb$48$next - sync posedge \coresync_clk - update \rb$48 $0\rb$48[63:0]$10039 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9831 end - attribute \src "libresoc.v:176156.3-176157.29" - process $proc$libresoc.v:176156$10040 + attribute \src "libresoc.v:169593.3-169594.23" + process $proc$libresoc.v:169593$9709 assign { } { } - assign $0\ra$47[63:0]$10041 \ra$47$next - sync posedge \coresync_clk - update \ra$47 $0\ra$47[63:0]$10041 - end - attribute \src "libresoc.v:176158.3-176159.67" - process $proc$libresoc.v:176158$10042 - assign { } { } - assign $0\logical_op__insn_type$29[6:0]$10043 \logical_op__insn_type$29$next - sync posedge \coresync_clk - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10043 - end - attribute \src "libresoc.v:176160.3-176161.63" - process $proc$libresoc.v:176160$10044 - assign { } { } - assign $0\logical_op__fn_unit$30[12:0]$10045 \logical_op__fn_unit$30$next + assign $0\msr[63:0] \msr$next sync posedge \coresync_clk - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$10045 + update \msr $0\msr[63:0] end - attribute \src "libresoc.v:176162.3-176163.77" - process $proc$libresoc.v:176162$10046 + attribute \src "libresoc.v:169595.3-169596.29" + process $proc$libresoc.v:169595$9710 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$10047 \logical_op__imm_data__data$31$next + assign $0\msr_ok[0:0] \msr_ok$next sync posedge \coresync_clk - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10047 + update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:176164.3-176165.73" - process $proc$libresoc.v:176164$10048 + attribute \src "libresoc.v:169597.3-169598.23" + process $proc$libresoc.v:169597$9711 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$10049 \logical_op__imm_data__ok$32$next + assign $0\nia[63:0] \nia$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10049 + update \nia $0\nia[63:0] end - attribute \src "libresoc.v:176166.3-176167.61" - process $proc$libresoc.v:176166$10050 + attribute \src "libresoc.v:169599.3-169600.29" + process $proc$libresoc.v:169599$9712 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10051 \logical_op__rc__rc$33$next + assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10051 + update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:176168.3-176169.61" - process $proc$libresoc.v:176168$10052 + attribute \src "libresoc.v:169601.3-169602.35" + process $proc$libresoc.v:169601$9713 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10053 \logical_op__rc__ok$34$next + assign $0\fast2$12[63:0]$9714 \fast2$12$next sync posedge \coresync_clk - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10053 + update \fast2$12 $0\fast2$12[63:0]$9714 end - attribute \src "libresoc.v:176170.3-176171.61" - process $proc$libresoc.v:176170$10054 + attribute \src "libresoc.v:169603.3-169604.33" + process $proc$libresoc.v:169603$9715 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10055 \logical_op__oe__oe$35$next + assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10055 + update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:176172.3-176173.61" - process $proc$libresoc.v:176172$10056 + attribute \src "libresoc.v:169605.3-169606.35" + process $proc$libresoc.v:169605$9716 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10057 \logical_op__oe__ok$36$next + assign $0\fast1$11[63:0]$9717 \fast1$11$next sync posedge \coresync_clk - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10057 + update \fast1$11 $0\fast1$11[63:0]$9717 end - attribute \src "libresoc.v:176174.3-176175.67" - process $proc$libresoc.v:176174$10058 + attribute \src "libresoc.v:169607.3-169608.33" + process $proc$libresoc.v:169607$9718 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10059 \logical_op__invert_in$37$next + assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10059 + update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:176176.3-176177.61" - process $proc$libresoc.v:176176$10060 + attribute \src "libresoc.v:169609.3-169610.19" + process $proc$libresoc.v:169609$9719 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10061 \logical_op__zero_a$38$next + assign $0\o[63:0] \o$next sync posedge \coresync_clk - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10061 + update \o $0\o[63:0] end - attribute \src "libresoc.v:176178.3-176179.71" - process $proc$libresoc.v:176178$10062 + attribute \src "libresoc.v:169611.3-169612.25" + process $proc$libresoc.v:169611$9720 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10063 \logical_op__input_carry$39$next + assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10063 + update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:176180.3-176181.69" - process $proc$libresoc.v:176180$10064 + attribute \src "libresoc.v:169613.3-169614.59" + process $proc$libresoc.v:169613$9721 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10065 \logical_op__invert_out$40$next + assign $0\trap_op__insn_type$2[6:0]$9722 \trap_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10065 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9722 end - attribute \src "libresoc.v:176182.3-176183.67" - process $proc$libresoc.v:176182$10066 + attribute \src "libresoc.v:169615.3-169616.55" + process $proc$libresoc.v:169615$9723 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10067 \logical_op__write_cr0$41$next + assign $0\trap_op__fn_unit$3[12:0]$9724 \trap_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10067 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9724 end - attribute \src "libresoc.v:176184.3-176185.73" - process $proc$libresoc.v:176184$10068 + attribute \src "libresoc.v:169617.3-169618.49" + process $proc$libresoc.v:169617$9725 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10069 \logical_op__output_carry$42$next + assign $0\trap_op__insn$4[31:0]$9726 \trap_op__insn$4$next sync posedge \coresync_clk - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10069 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9726 end - attribute \src "libresoc.v:176186.3-176187.65" - process $proc$libresoc.v:176186$10070 + attribute \src "libresoc.v:169619.3-169620.47" + process $proc$libresoc.v:169619$9727 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10071 \logical_op__is_32bit$43$next + assign $0\trap_op__msr$5[63:0]$9728 \trap_op__msr$5$next sync posedge \coresync_clk - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10071 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9728 end - attribute \src "libresoc.v:176188.3-176189.67" - process $proc$libresoc.v:176188$10072 + attribute \src "libresoc.v:169621.3-169622.47" + process $proc$libresoc.v:169621$9729 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10073 \logical_op__is_signed$44$next + assign $0\trap_op__cia$6[63:0]$9730 \trap_op__cia$6$next sync posedge \coresync_clk - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10073 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9730 end - attribute \src "libresoc.v:176190.3-176191.65" - process $proc$libresoc.v:176190$10074 + attribute \src "libresoc.v:169623.3-169624.57" + process $proc$libresoc.v:169623$9731 assign { } { } - assign $0\logical_op__data_len$45[3:0]$10075 \logical_op__data_len$45$next + assign $0\trap_op__is_32bit$7[0:0]$9732 \trap_op__is_32bit$7$next sync posedge \coresync_clk - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10075 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9732 end - attribute \src "libresoc.v:176192.3-176193.57" - process $proc$libresoc.v:176192$10076 + attribute \src "libresoc.v:169625.3-169626.57" + process $proc$libresoc.v:169625$9733 assign { } { } - assign $0\logical_op__insn$46[31:0]$10077 \logical_op__insn$46$next + assign $0\trap_op__traptype$8[7:0]$9734 \trap_op__traptype$8$next sync posedge \coresync_clk - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10077 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9734 end - attribute \src "libresoc.v:176194.3-176195.35" - process $proc$libresoc.v:176194$10078 + attribute \src "libresoc.v:169627.3-169628.57" + process $proc$libresoc.v:169627$9735 assign { } { } - assign $0\muxid$28[1:0]$10079 \muxid$28$next + assign $0\trap_op__trapaddr$9[12:0]$9736 \trap_op__trapaddr$9$next sync posedge \coresync_clk - update \muxid$28 $0\muxid$28[1:0]$10079 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9736 end - attribute \src "libresoc.v:176196.3-176197.27" - process $proc$libresoc.v:176196$10080 + attribute \src "libresoc.v:169629.3-169630.59" + process $proc$libresoc.v:169629$9737 assign { } { } - assign $0\empty[0:0] \empty$next + assign $0\trap_op__ldst_exc$10[7:0]$9738 \trap_op__ldst_exc$10$next sync posedge \coresync_clk - update \empty $0\empty[0:0] + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9738 end - attribute \src "libresoc.v:176198.3-176199.75" - process $proc$libresoc.v:176198$10081 + attribute \src "libresoc.v:169631.3-169632.33" + process $proc$libresoc.v:169631$9739 assign { } { } - assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next + assign $0\muxid$1[1:0]$9740 \muxid$1$next sync posedge \coresync_clk - update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] + update \muxid$1 $0\muxid$1[1:0]$9740 end - attribute \src "libresoc.v:176200.3-176201.65" - process $proc$libresoc.v:176200$10082 + attribute \src "libresoc.v:169633.3-169634.29" + process $proc$libresoc.v:169633$9741 assign { } { } - assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next + assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk - update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] - end - attribute \src "libresoc.v:176222.3-176230.6" - process $proc$libresoc.v:176222$10083 - assign { } { } - assign { } { } - assign $0\saved_state_q_bits_known$next[6:0]$10084 $1\saved_state_q_bits_known$next[6:0]$10085 - attribute \src "libresoc.v:176223.5-176223.29" - switch \initial - attribute \src "libresoc.v:176223.9-176223.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\saved_state_q_bits_known$next[6:0]$10085 7'0000000 - case - assign $1\saved_state_q_bits_known$next[6:0]$10085 \div_state_next_o_q_bits_known - end - sync always - update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10084 - end - attribute \src "libresoc.v:176231.3-176239.6" - process $proc$libresoc.v:176231$10086 - assign { } { } - assign { } { } - assign $0\saved_state_dividend_quotient$next[127:0]$10087 $1\saved_state_dividend_quotient$next[127:0]$10088 - attribute \src "libresoc.v:176232.5-176232.29" - switch \initial - attribute \src "libresoc.v:176232.9-176232.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\saved_state_dividend_quotient$next[127:0]$10088 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\saved_state_dividend_quotient$next[127:0]$10088 \div_state_next_o_dividend_quotient - end - sync always - update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10087 + update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:176240.3-176251.6" - process $proc$libresoc.v:176240$10089 + attribute \src "libresoc.v:169679.3-169696.6" + process $proc$libresoc.v:169679$9742 assign { } { } - assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:176241.5-176241.29" - switch \initial - attribute \src "libresoc.v:176241.9-176241.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known - end - sync always - update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] - end - attribute \src "libresoc.v:176252.3-176263.6" - process $proc$libresoc.v:176252$10090 assign { } { } - assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:176253.5-176253.29" - switch \initial - attribute \src "libresoc.v:176253.9-176253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient - end - sync always - update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] - end - attribute \src "libresoc.v:176264.3-176275.6" - process $proc$libresoc.v:176264$10091 assign { } { } - assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:176265.5-176265.29" + assign $0\r_busy$next[0:0]$9743 $2\r_busy$next[0:0]$9745 + attribute \src "libresoc.v:169680.5-169680.29" switch \initial - attribute \src "libresoc.v:176265.9-176265.17" + attribute \src "libresoc.v:169680.9-169680.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\div_state_next_divisor[63:0] \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case + case 2'-1 assign { } { } - assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 - end - sync always - update \div_state_next_divisor $0\div_state_next_divisor[63:0] - end - attribute \src "libresoc.v:176276.3-176303.6" - process $proc$libresoc.v:176276$10092 - assign { } { } - assign { } { } - assign { } { } - assign $0\empty$next[0:0]$10093 $4\empty$next[0:0]$10097 - attribute \src "libresoc.v:176277.5-176277.29" - switch \initial - attribute \src "libresoc.v:176277.9-176277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + assign $1\r_busy$next[0:0]$9744 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'1- assign { } { } - assign $1\empty$next[0:0]$10094 $2\empty$next[0:0]$10095 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\empty$next[0:0]$10095 1'0 - case - assign $2\empty$next[0:0]$10095 \empty - end - attribute \src "libresoc.v:0.0-0.0" + assign $1\r_busy$next[0:0]$9744 1'0 case - assign { } { } - assign $1\empty$next[0:0]$10094 $3\empty$next[0:0]$10096 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch \$66 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\empty$next[0:0]$10096 1'1 - case - assign $3\empty$next[0:0]$10096 \empty - end + assign $1\r_busy$next[0:0]$9744 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\empty$next[0:0]$10097 1'1 + assign $2\r_busy$next[0:0]$9745 1'0 case - assign $4\empty$next[0:0]$10097 $1\empty$next[0:0]$10094 + assign $2\r_busy$next[0:0]$9745 $1\r_busy$next[0:0]$9744 end sync always - update \empty$next $0\empty$next[0:0]$10093 + update \r_busy$next $0\r_busy$next[0:0]$9743 end - attribute \src "libresoc.v:176304.3-176318.6" - process $proc$libresoc.v:176304$10098 + attribute \src "libresoc.v:169697.3-169709.6" + process $proc$libresoc.v:169697$9746 assign { } { } assign { } { } - assign $0\muxid$28$next[1:0]$10099 $1\muxid$28$next[1:0]$10100 - attribute \src "libresoc.v:176305.5-176305.29" + assign $0\muxid$1$next[1:0]$9747 $1\muxid$1$next[1:0]$9748 + attribute \src "libresoc.v:169698.5-169698.29" switch \initial - attribute \src "libresoc.v:176305.9-176305.17" + attribute \src "libresoc.v:169698.9-169698.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\muxid$28$next[1:0]$10100 $2\muxid$28$next[1:0]$10101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\muxid$28$next[1:0]$10101 \muxid - case - assign $2\muxid$28$next[1:0]$10101 \muxid$28 - end + assign $1\muxid$1$next[1:0]$9748 \muxid$28 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9748 \muxid$28 case - assign $1\muxid$28$next[1:0]$10100 \muxid$28 + assign $1\muxid$1$next[1:0]$9748 \muxid$1 end sync always - update \muxid$28$next $0\muxid$28$next[1:0]$10099 + update \muxid$1$next $0\muxid$1$next[1:0]$9747 end - attribute \src "libresoc.v:176319.3-176362.6" - process $proc$libresoc.v:176319$10102 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:169710.3-169730.6" + process $proc$libresoc.v:169710$9749 assign { } { } assign { } { } assign { } { } @@ -359304,46 +349868,26 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$45$next[3:0]$10103 $1\logical_op__data_len$45$next[3:0]$10121 - assign $0\logical_op__fn_unit$30$next[12:0]$10104 $1\logical_op__fn_unit$30$next[12:0]$10122 assign { } { } - assign { } { } - assign $0\logical_op__input_carry$39$next[1:0]$10107 $1\logical_op__input_carry$39$next[1:0]$10125 - assign $0\logical_op__insn$46$next[31:0]$10108 $1\logical_op__insn$46$next[31:0]$10126 - assign $0\logical_op__insn_type$29$next[6:0]$10109 $1\logical_op__insn_type$29$next[6:0]$10127 - assign $0\logical_op__invert_in$37$next[0:0]$10110 $1\logical_op__invert_in$37$next[0:0]$10128 - assign $0\logical_op__invert_out$40$next[0:0]$10111 $1\logical_op__invert_out$40$next[0:0]$10129 - assign $0\logical_op__is_32bit$43$next[0:0]$10112 $1\logical_op__is_32bit$43$next[0:0]$10130 - assign $0\logical_op__is_signed$44$next[0:0]$10113 $1\logical_op__is_signed$44$next[0:0]$10131 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$42$next[0:0]$10116 $1\logical_op__output_carry$42$next[0:0]$10134 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$41$next[0:0]$10119 $1\logical_op__write_cr0$41$next[0:0]$10137 - assign $0\logical_op__zero_a$38$next[0:0]$10120 $1\logical_op__zero_a$38$next[0:0]$10138 - assign $0\logical_op__imm_data__data$31$next[63:0]$10105 $3\logical_op__imm_data__data$31$next[63:0]$10157 - assign $0\logical_op__imm_data__ok$32$next[0:0]$10106 $3\logical_op__imm_data__ok$32$next[0:0]$10158 - assign $0\logical_op__oe__oe$35$next[0:0]$10114 $3\logical_op__oe__oe$35$next[0:0]$10159 - assign $0\logical_op__oe__ok$36$next[0:0]$10115 $3\logical_op__oe__ok$36$next[0:0]$10160 - assign $0\logical_op__rc__ok$34$next[0:0]$10117 $3\logical_op__rc__ok$34$next[0:0]$10161 - assign $0\logical_op__rc__rc$33$next[0:0]$10118 $3\logical_op__rc__rc$33$next[0:0]$10162 - attribute \src "libresoc.v:176320.5-176320.29" + assign $0\trap_op__cia$6$next[63:0]$9750 $1\trap_op__cia$6$next[63:0]$9759 + assign $0\trap_op__fn_unit$3$next[12:0]$9751 $1\trap_op__fn_unit$3$next[12:0]$9760 + assign $0\trap_op__insn$4$next[31:0]$9752 $1\trap_op__insn$4$next[31:0]$9761 + assign $0\trap_op__insn_type$2$next[6:0]$9753 $1\trap_op__insn_type$2$next[6:0]$9762 + assign $0\trap_op__is_32bit$7$next[0:0]$9754 $1\trap_op__is_32bit$7$next[0:0]$9763 + assign $0\trap_op__ldst_exc$10$next[7:0]$9755 $1\trap_op__ldst_exc$10$next[7:0]$9764 + assign $0\trap_op__msr$5$next[63:0]$9756 $1\trap_op__msr$5$next[63:0]$9765 + assign $0\trap_op__trapaddr$9$next[12:0]$9757 $1\trap_op__trapaddr$9$next[12:0]$9766 + assign $0\trap_op__traptype$8$next[7:0]$9758 $1\trap_op__traptype$8$next[7:0]$9767 + attribute \src "libresoc.v:169711.5-169711.29" switch \initial - attribute \src "libresoc.v:176320.9-176320.17" + attribute \src "libresoc.v:169711.9-169711.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + case 2'-1 assign { } { } assign { } { } assign { } { } @@ -359353,833 +349897,580 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9764 $1\trap_op__trapaddr$9$next[12:0]$9766 $1\trap_op__traptype$8$next[7:0]$9767 $1\trap_op__is_32bit$7$next[0:0]$9763 $1\trap_op__cia$6$next[63:0]$9759 $1\trap_op__msr$5$next[63:0]$9765 $1\trap_op__insn$4$next[31:0]$9761 $1\trap_op__fn_unit$3$next[12:0]$9760 $1\trap_op__insn_type$2$next[6:0]$9762 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- assign { } { } assign { } { } assign { } { } - assign $1\logical_op__data_len$45$next[3:0]$10121 $2\logical_op__data_len$45$next[3:0]$10139 - assign $1\logical_op__fn_unit$30$next[12:0]$10122 $2\logical_op__fn_unit$30$next[12:0]$10140 - assign $1\logical_op__imm_data__data$31$next[63:0]$10123 $2\logical_op__imm_data__data$31$next[63:0]$10141 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10124 $2\logical_op__imm_data__ok$32$next[0:0]$10142 - assign $1\logical_op__input_carry$39$next[1:0]$10125 $2\logical_op__input_carry$39$next[1:0]$10143 - assign $1\logical_op__insn$46$next[31:0]$10126 $2\logical_op__insn$46$next[31:0]$10144 - assign $1\logical_op__insn_type$29$next[6:0]$10127 $2\logical_op__insn_type$29$next[6:0]$10145 - assign $1\logical_op__invert_in$37$next[0:0]$10128 $2\logical_op__invert_in$37$next[0:0]$10146 - assign $1\logical_op__invert_out$40$next[0:0]$10129 $2\logical_op__invert_out$40$next[0:0]$10147 - assign $1\logical_op__is_32bit$43$next[0:0]$10130 $2\logical_op__is_32bit$43$next[0:0]$10148 - assign $1\logical_op__is_signed$44$next[0:0]$10131 $2\logical_op__is_signed$44$next[0:0]$10149 - assign $1\logical_op__oe__oe$35$next[0:0]$10132 $2\logical_op__oe__oe$35$next[0:0]$10150 - assign $1\logical_op__oe__ok$36$next[0:0]$10133 $2\logical_op__oe__ok$36$next[0:0]$10151 - assign $1\logical_op__output_carry$42$next[0:0]$10134 $2\logical_op__output_carry$42$next[0:0]$10152 - assign $1\logical_op__rc__ok$34$next[0:0]$10135 $2\logical_op__rc__ok$34$next[0:0]$10153 - assign $1\logical_op__rc__rc$33$next[0:0]$10136 $2\logical_op__rc__rc$33$next[0:0]$10154 - assign $1\logical_op__write_cr0$41$next[0:0]$10137 $2\logical_op__write_cr0$41$next[0:0]$10155 - assign $1\logical_op__zero_a$38$next[0:0]$10138 $2\logical_op__zero_a$38$next[0:0]$10156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\logical_op__insn$46$next[31:0]$10144 $2\logical_op__data_len$45$next[3:0]$10139 $2\logical_op__is_signed$44$next[0:0]$10149 $2\logical_op__is_32bit$43$next[0:0]$10148 $2\logical_op__output_carry$42$next[0:0]$10152 $2\logical_op__write_cr0$41$next[0:0]$10155 $2\logical_op__invert_out$40$next[0:0]$10147 $2\logical_op__input_carry$39$next[1:0]$10143 $2\logical_op__zero_a$38$next[0:0]$10156 $2\logical_op__invert_in$37$next[0:0]$10146 $2\logical_op__oe__ok$36$next[0:0]$10151 $2\logical_op__oe__oe$35$next[0:0]$10150 $2\logical_op__rc__ok$34$next[0:0]$10153 $2\logical_op__rc__rc$33$next[0:0]$10154 $2\logical_op__imm_data__ok$32$next[0:0]$10142 $2\logical_op__imm_data__data$31$next[63:0]$10141 $2\logical_op__fn_unit$30$next[12:0]$10140 $2\logical_op__insn_type$29$next[6:0]$10145 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - case - assign $2\logical_op__data_len$45$next[3:0]$10139 \logical_op__data_len$45 - assign $2\logical_op__fn_unit$30$next[12:0]$10140 \logical_op__fn_unit$30 - assign $2\logical_op__imm_data__data$31$next[63:0]$10141 \logical_op__imm_data__data$31 - assign $2\logical_op__imm_data__ok$32$next[0:0]$10142 \logical_op__imm_data__ok$32 - assign $2\logical_op__input_carry$39$next[1:0]$10143 \logical_op__input_carry$39 - assign $2\logical_op__insn$46$next[31:0]$10144 \logical_op__insn$46 - assign $2\logical_op__insn_type$29$next[6:0]$10145 \logical_op__insn_type$29 - assign $2\logical_op__invert_in$37$next[0:0]$10146 \logical_op__invert_in$37 - assign $2\logical_op__invert_out$40$next[0:0]$10147 \logical_op__invert_out$40 - assign $2\logical_op__is_32bit$43$next[0:0]$10148 \logical_op__is_32bit$43 - assign $2\logical_op__is_signed$44$next[0:0]$10149 \logical_op__is_signed$44 - assign $2\logical_op__oe__oe$35$next[0:0]$10150 \logical_op__oe__oe$35 - assign $2\logical_op__oe__ok$36$next[0:0]$10151 \logical_op__oe__ok$36 - assign $2\logical_op__output_carry$42$next[0:0]$10152 \logical_op__output_carry$42 - assign $2\logical_op__rc__ok$34$next[0:0]$10153 \logical_op__rc__ok$34 - assign $2\logical_op__rc__rc$33$next[0:0]$10154 \logical_op__rc__rc$33 - assign $2\logical_op__write_cr0$41$next[0:0]$10155 \logical_op__write_cr0$41 - assign $2\logical_op__zero_a$38$next[0:0]$10156 \logical_op__zero_a$38 - end - case - assign $1\logical_op__data_len$45$next[3:0]$10121 \logical_op__data_len$45 - assign $1\logical_op__fn_unit$30$next[12:0]$10122 \logical_op__fn_unit$30 - assign $1\logical_op__imm_data__data$31$next[63:0]$10123 \logical_op__imm_data__data$31 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10124 \logical_op__imm_data__ok$32 - assign $1\logical_op__input_carry$39$next[1:0]$10125 \logical_op__input_carry$39 - assign $1\logical_op__insn$46$next[31:0]$10126 \logical_op__insn$46 - assign $1\logical_op__insn_type$29$next[6:0]$10127 \logical_op__insn_type$29 - assign $1\logical_op__invert_in$37$next[0:0]$10128 \logical_op__invert_in$37 - assign $1\logical_op__invert_out$40$next[0:0]$10129 \logical_op__invert_out$40 - assign $1\logical_op__is_32bit$43$next[0:0]$10130 \logical_op__is_32bit$43 - assign $1\logical_op__is_signed$44$next[0:0]$10131 \logical_op__is_signed$44 - assign $1\logical_op__oe__oe$35$next[0:0]$10132 \logical_op__oe__oe$35 - assign $1\logical_op__oe__ok$36$next[0:0]$10133 \logical_op__oe__ok$36 - assign $1\logical_op__output_carry$42$next[0:0]$10134 \logical_op__output_carry$42 - assign $1\logical_op__rc__ok$34$next[0:0]$10135 \logical_op__rc__ok$34 - assign $1\logical_op__rc__rc$33$next[0:0]$10136 \logical_op__rc__rc$33 - assign $1\logical_op__write_cr0$41$next[0:0]$10137 \logical_op__write_cr0$41 - assign $1\logical_op__zero_a$38$next[0:0]$10138 \logical_op__zero_a$38 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $3\logical_op__imm_data__data$31$next[63:0]$10157 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10158 1'0 - assign $3\logical_op__rc__rc$33$next[0:0]$10162 1'0 - assign $3\logical_op__rc__ok$34$next[0:0]$10161 1'0 - assign $3\logical_op__oe__oe$35$next[0:0]$10159 1'0 - assign $3\logical_op__oe__ok$36$next[0:0]$10160 1'0 + assign { $1\trap_op__ldst_exc$10$next[7:0]$9764 $1\trap_op__trapaddr$9$next[12:0]$9766 $1\trap_op__traptype$8$next[7:0]$9767 $1\trap_op__is_32bit$7$next[0:0]$9763 $1\trap_op__cia$6$next[63:0]$9759 $1\trap_op__msr$5$next[63:0]$9765 $1\trap_op__insn$4$next[31:0]$9761 $1\trap_op__fn_unit$3$next[12:0]$9760 $1\trap_op__insn_type$2$next[6:0]$9762 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } case - assign $3\logical_op__imm_data__data$31$next[63:0]$10157 $1\logical_op__imm_data__data$31$next[63:0]$10123 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10158 $1\logical_op__imm_data__ok$32$next[0:0]$10124 - assign $3\logical_op__oe__oe$35$next[0:0]$10159 $1\logical_op__oe__oe$35$next[0:0]$10132 - assign $3\logical_op__oe__ok$36$next[0:0]$10160 $1\logical_op__oe__ok$36$next[0:0]$10133 - assign $3\logical_op__rc__ok$34$next[0:0]$10161 $1\logical_op__rc__ok$34$next[0:0]$10135 - assign $3\logical_op__rc__rc$33$next[0:0]$10162 $1\logical_op__rc__rc$33$next[0:0]$10136 + assign $1\trap_op__cia$6$next[63:0]$9759 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[12:0]$9760 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9761 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9762 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9763 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9764 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9765 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9766 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9767 \trap_op__traptype$8 end sync always - update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10103 - update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[12:0]$10104 - update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10105 - update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10106 - update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10107 - update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10108 - update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10109 - update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10110 - update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10111 - update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10112 - update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10113 - update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10114 - update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10115 - update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10116 - update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10117 - update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10118 - update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10119 - update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10120 + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9750 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[12:0]$9751 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9752 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9753 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9754 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9755 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9756 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9757 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9758 end - attribute \src "libresoc.v:176363.3-176377.6" - process $proc$libresoc.v:176363$10163 + attribute \src "libresoc.v:169731.3-169749.6" + process $proc$libresoc.v:169731$9768 + assign { } { } assign { } { } assign { } { } - assign $0\ra$47$next[63:0]$10164 $1\ra$47$next[63:0]$10165 - attribute \src "libresoc.v:176364.5-176364.29" - switch \initial - attribute \src "libresoc.v:176364.9-176364.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ra$47$next[63:0]$10165 $2\ra$47$next[63:0]$10166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ra$47$next[63:0]$10166 \ra - case - assign $2\ra$47$next[63:0]$10166 \ra$47 - end - case - assign $1\ra$47$next[63:0]$10165 \ra$47 - end - sync always - update \ra$47$next $0\ra$47$next[63:0]$10164 - end - attribute \src "libresoc.v:176378.3-176392.6" - process $proc$libresoc.v:176378$10167 assign { } { } + assign $0\o$next[63:0]$9769 $1\o$next[63:0]$9771 assign { } { } - assign $0\rb$48$next[63:0]$10168 $1\rb$48$next[63:0]$10169 - attribute \src "libresoc.v:176379.5-176379.29" + assign $0\o_ok$next[0:0]$9770 $2\o_ok$next[0:0]$9773 + attribute \src "libresoc.v:169732.5-169732.29" switch \initial - attribute \src "libresoc.v:176379.9-176379.17" + attribute \src "libresoc.v:169732.9-169732.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\rb$48$next[63:0]$10169 $2\rb$48$next[63:0]$10170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\rb$48$next[63:0]$10170 \rb - case - assign $2\rb$48$next[63:0]$10170 \rb$48 - end - case - assign $1\rb$48$next[63:0]$10169 \rb$48 - end - sync always - update \rb$48$next $0\rb$48$next[63:0]$10168 - end - attribute \src "libresoc.v:176393.3-176407.6" - process $proc$libresoc.v:176393$10171 - assign { } { } - assign { } { } - assign $0\xer_so$49$next[0:0]$10172 $1\xer_so$49$next[0:0]$10173 - attribute \src "libresoc.v:176394.5-176394.29" - switch \initial - attribute \src "libresoc.v:176394.9-176394.17" - case 1'1 + assign { } { } + assign { $1\o_ok$next[0:0]$9772 $1\o$next[63:0]$9771 } { \o_ok$39 \o$38 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9772 $1\o$next[63:0]$9771 } { \o_ok$39 \o$38 } case + assign $1\o$next[63:0]$9771 \o + assign $1\o_ok$next[0:0]$9772 \o_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$49$next[0:0]$10173 $2\xer_so$49$next[0:0]$10174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so$49$next[0:0]$10174 \xer_so - case - assign $2\xer_so$49$next[0:0]$10174 \xer_so$49 - end + assign $2\o_ok$next[0:0]$9773 1'0 case - assign $1\xer_so$49$next[0:0]$10173 \xer_so$49 + assign $2\o_ok$next[0:0]$9773 $1\o_ok$next[0:0]$9772 end sync always - update \xer_so$49$next $0\xer_so$49$next[0:0]$10172 + update \o$next $0\o$next[63:0]$9769 + update \o_ok$next $0\o_ok$next[0:0]$9770 end - attribute \src "libresoc.v:176408.3-176422.6" - process $proc$libresoc.v:176408$10175 + attribute \src "libresoc.v:169750.3-169768.6" + process $proc$libresoc.v:169750$9774 + assign { } { } assign { } { } assign { } { } - assign $0\divisor_neg$50$next[0:0]$10176 $1\divisor_neg$50$next[0:0]$10177 - attribute \src "libresoc.v:176409.5-176409.29" + assign { } { } + assign { } { } + assign $0\fast1$11$next[63:0]$9776 $1\fast1$11$next[63:0]$9778 + assign $0\fast1_ok$next[0:0]$9775 $2\fast1_ok$next[0:0]$9779 + attribute \src "libresoc.v:169751.5-169751.29" switch \initial - attribute \src "libresoc.v:176409.9-176409.17" + attribute \src "libresoc.v:169751.9-169751.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\divisor_neg$50$next[0:0]$10177 $2\divisor_neg$50$next[0:0]$10178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\divisor_neg$50$next[0:0]$10178 \divisor_neg - case - assign $2\divisor_neg$50$next[0:0]$10178 \divisor_neg$50 - end - case - assign $1\divisor_neg$50$next[0:0]$10177 \divisor_neg$50 - end - sync always - update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10176 - end - attribute \src "libresoc.v:176423.3-176437.6" - process $proc$libresoc.v:176423$10179 - assign { } { } - assign { } { } - assign $0\dividend_neg$51$next[0:0]$10180 $1\dividend_neg$51$next[0:0]$10181 - attribute \src "libresoc.v:176424.5-176424.29" - switch \initial - attribute \src "libresoc.v:176424.9-176424.17" - case 1'1 + assign { } { } + assign { $1\fast1_ok$next[0:0]$9777 $1\fast1$11$next[63:0]$9778 } { \fast1_ok$41 \fast1$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$9777 $1\fast1$11$next[63:0]$9778 } { \fast1_ok$41 \fast1$40 } case + assign $1\fast1_ok$next[0:0]$9777 \fast1_ok + assign $1\fast1$11$next[63:0]$9778 \fast1$11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend_neg$51$next[0:0]$10181 $2\dividend_neg$51$next[0:0]$10182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dividend_neg$51$next[0:0]$10182 \dividend_neg - case - assign $2\dividend_neg$51$next[0:0]$10182 \dividend_neg$51 - end + assign $2\fast1_ok$next[0:0]$9779 1'0 case - assign $1\dividend_neg$51$next[0:0]$10181 \dividend_neg$51 + assign $2\fast1_ok$next[0:0]$9779 $1\fast1_ok$next[0:0]$9777 end sync always - update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10180 + update \fast1_ok$next $0\fast1_ok$next[0:0]$9775 + update \fast1$11$next $0\fast1$11$next[63:0]$9776 end - attribute \src "libresoc.v:176438.3-176452.6" - process $proc$libresoc.v:176438$10183 + attribute \src "libresoc.v:169769.3-169787.6" + process $proc$libresoc.v:169769$9780 + assign { } { } assign { } { } assign { } { } - assign $0\dive_abs_ov32$52$next[0:0]$10184 $1\dive_abs_ov32$52$next[0:0]$10185 - attribute \src "libresoc.v:176439.5-176439.29" + assign { } { } + assign { } { } + assign $0\fast2$12$next[63:0]$9782 $1\fast2$12$next[63:0]$9784 + assign $0\fast2_ok$next[0:0]$9781 $2\fast2_ok$next[0:0]$9785 + attribute \src "libresoc.v:169770.5-169770.29" switch \initial - attribute \src "libresoc.v:176439.9-176439.17" + attribute \src "libresoc.v:169770.9-169770.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\dive_abs_ov32$52$next[0:0]$10185 $2\dive_abs_ov32$52$next[0:0]$10186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dive_abs_ov32$52$next[0:0]$10186 \dive_abs_ov32 - case - assign $2\dive_abs_ov32$52$next[0:0]$10186 \dive_abs_ov32$52 - end - case - assign $1\dive_abs_ov32$52$next[0:0]$10185 \dive_abs_ov32$52 - end - sync always - update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10184 - end - attribute \src "libresoc.v:176453.3-176467.6" - process $proc$libresoc.v:176453$10187 - assign { } { } - assign { } { } - assign $0\dive_abs_ov64$53$next[0:0]$10188 $1\dive_abs_ov64$53$next[0:0]$10189 - attribute \src "libresoc.v:176454.5-176454.29" - switch \initial - attribute \src "libresoc.v:176454.9-176454.17" - case 1'1 + assign { } { } + assign { $1\fast2_ok$next[0:0]$9783 $1\fast2$12$next[63:0]$9784 } { \fast2_ok$43 \fast2$42 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$9783 $1\fast2$12$next[63:0]$9784 } { \fast2_ok$43 \fast2$42 } case + assign $1\fast2_ok$next[0:0]$9783 \fast2_ok + assign $1\fast2$12$next[63:0]$9784 \fast2$12 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov64$53$next[0:0]$10189 $2\dive_abs_ov64$53$next[0:0]$10190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dive_abs_ov64$53$next[0:0]$10190 \dive_abs_ov64 - case - assign $2\dive_abs_ov64$53$next[0:0]$10190 \dive_abs_ov64$53 - end + assign $2\fast2_ok$next[0:0]$9785 1'0 case - assign $1\dive_abs_ov64$53$next[0:0]$10189 \dive_abs_ov64$53 + assign $2\fast2_ok$next[0:0]$9785 $1\fast2_ok$next[0:0]$9783 end sync always - update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10188 + update \fast2_ok$next $0\fast2_ok$next[0:0]$9781 + update \fast2$12$next $0\fast2$12$next[63:0]$9782 end - attribute \src "libresoc.v:176468.3-176482.6" - process $proc$libresoc.v:176468$10191 + attribute \src "libresoc.v:169788.3-169806.6" + process $proc$libresoc.v:169788$9786 + assign { } { } assign { } { } assign { } { } - assign $0\div_by_zero$54$next[0:0]$10192 $1\div_by_zero$54$next[0:0]$10193 - attribute \src "libresoc.v:176469.5-176469.29" + assign { } { } + assign $0\nia$next[63:0]$9787 $1\nia$next[63:0]$9789 + assign { } { } + assign $0\nia_ok$next[0:0]$9788 $2\nia_ok$next[0:0]$9791 + attribute \src "libresoc.v:169789.5-169789.29" switch \initial - attribute \src "libresoc.v:176469.9-176469.17" + attribute \src "libresoc.v:169789.9-169789.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\div_by_zero$54$next[0:0]$10193 $2\div_by_zero$54$next[0:0]$10194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\div_by_zero$54$next[0:0]$10194 \div_by_zero - case - assign $2\div_by_zero$54$next[0:0]$10194 \div_by_zero$54 - end - case - assign $1\div_by_zero$54$next[0:0]$10193 \div_by_zero$54 - end - sync always - update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10192 - end - attribute \src "libresoc.v:176483.3-176497.6" - process $proc$libresoc.v:176483$10195 - assign { } { } - assign { } { } - assign $0\dividend$68$next[127:0]$10196 $1\dividend$68$next[127:0]$10197 - attribute \src "libresoc.v:176484.5-176484.29" - switch \initial - attribute \src "libresoc.v:176484.9-176484.17" - case 1'1 + assign { } { } + assign { $1\nia_ok$next[0:0]$9790 $1\nia$next[63:0]$9789 } { \nia_ok$45 \nia$44 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$9790 $1\nia$next[63:0]$9789 } { \nia_ok$45 \nia$44 } case + assign $1\nia$next[63:0]$9789 \nia + assign $1\nia_ok$next[0:0]$9790 \nia_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend$68$next[127:0]$10197 $2\dividend$68$next[127:0]$10198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dividend$68$next[127:0]$10198 \dividend - case - assign $2\dividend$68$next[127:0]$10198 \dividend$68 - end + assign $2\nia_ok$next[0:0]$9791 1'0 case - assign $1\dividend$68$next[127:0]$10197 \dividend$68 + assign $2\nia_ok$next[0:0]$9791 $1\nia_ok$next[0:0]$9790 end sync always - update \dividend$68$next $0\dividend$68$next[127:0]$10196 + update \nia$next $0\nia$next[63:0]$9787 + update \nia_ok$next $0\nia_ok$next[0:0]$9788 end - attribute \src "libresoc.v:176498.3-176512.6" - process $proc$libresoc.v:176498$10199 + attribute \src "libresoc.v:169807.3-169825.6" + process $proc$libresoc.v:169807$9792 + assign { } { } assign { } { } assign { } { } - assign $0\divisor_radicand$65$next[63:0]$10200 $1\divisor_radicand$65$next[63:0]$10201 - attribute \src "libresoc.v:176499.5-176499.29" + assign { } { } + assign $0\msr$next[63:0]$9793 $1\msr$next[63:0]$9795 + assign { } { } + assign $0\msr_ok$next[0:0]$9794 $2\msr_ok$next[0:0]$9797 + attribute \src "libresoc.v:169808.5-169808.29" switch \initial - attribute \src "libresoc.v:176499.9-176499.17" + attribute \src "libresoc.v:169808.9-169808.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\divisor_radicand$65$next[63:0]$10201 $2\divisor_radicand$65$next[63:0]$10202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\divisor_radicand$65$next[63:0]$10202 \divisor_radicand - case - assign $2\divisor_radicand$65$next[63:0]$10202 \divisor_radicand$65 - end - case - assign $1\divisor_radicand$65$next[63:0]$10201 \divisor_radicand$65 - end - sync always - update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10200 - end - attribute \src "libresoc.v:176513.3-176527.6" - process $proc$libresoc.v:176513$10203 - assign { } { } - assign { } { } - assign $0\operation$69$next[1:0]$10204 $1\operation$69$next[1:0]$10205 - attribute \src "libresoc.v:176514.5-176514.29" - switch \initial - attribute \src "libresoc.v:176514.9-176514.17" - case 1'1 + assign { } { } + assign { $1\msr_ok$next[0:0]$9796 $1\msr$next[63:0]$9795 } { \msr_ok$47 \msr$46 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$9796 $1\msr$next[63:0]$9795 } { \msr_ok$47 \msr$46 } case + assign $1\msr$next[63:0]$9795 \msr + assign $1\msr_ok$next[0:0]$9796 \msr_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\operation$69$next[1:0]$10205 $2\operation$69$next[1:0]$10206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\operation$69$next[1:0]$10206 \operation - case - assign $2\operation$69$next[1:0]$10206 \operation$69 - end + assign $2\msr_ok$next[0:0]$9797 1'0 case - assign $1\operation$69$next[1:0]$10205 \operation$69 + assign $2\msr_ok$next[0:0]$9797 $1\msr_ok$next[0:0]$9796 end sync always - update \operation$69$next $0\operation$69$next[1:0]$10204 + update \msr$next $0\msr$next[63:0]$9793 + update \msr_ok$next $0\msr_ok$next[0:0]$9794 end - connect \$56 $sshl$libresoc.v:176130$10013_Y - connect \$55 $pos$libresoc.v:176131$10015_Y - connect \$59 $not$libresoc.v:176132$10016_Y - connect \$61 $ge$libresoc.v:176133$10017_Y - connect \$63 $and$libresoc.v:176134$10018_Y - connect \$66 $and$libresoc.v:176135$10019_Y - connect \p_ready_o \empty - connect \n_valid_o \$63 - connect \remainder \$55 - connect \quotient_root \div_state_next_o_dividend_quotient [63:0] - connect \div_by_zero$27 \div_by_zero$54 - connect \dive_abs_ov64$26 \dive_abs_ov64$53 - connect \dive_abs_ov32$25 \dive_abs_ov32$52 - connect \dividend_neg$24 \dividend_neg$51 - connect \divisor_neg$23 \divisor_neg$50 - connect \xer_so$22 \xer_so$49 - connect \rb$21 \rb$48 - connect \ra$20 \ra$47 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } - connect \muxid$1 \muxid$28 - connect \div_state_init_dividend \dividend + connect \$26 $and$libresoc.v:169592$9708_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } + connect { \nia_ok$45 \nia$44 } { \main_nia_ok \main_nia } + connect { \fast2_ok$43 \fast2$42 } { \main_fast2_ok \main_fast2$24 } + connect { \fast1_ok$41 \fast1$40 } { \main_fast1_ok \main_fast1$23 } + connect { \o_ok$39 \o$38 } { \main_o_ok \main_o } + connect { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } { \main_trap_op__ldst_exc$22 \main_trap_op__trapaddr$21 \main_trap_op__traptype$20 \main_trap_op__is_32bit$19 \main_trap_op__cia$18 \main_trap_op__msr$17 \main_trap_op__insn$16 \main_trap_op__fn_unit$15 \main_trap_op__insn_type$14 } + connect \muxid$28 \main_muxid$13 + connect \p_valid_i_p_ready_o \$26 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$25 \p_valid_i + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect \main_rb \rb + connect \main_ra \ra + connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \main_muxid \muxid end -attribute \src "libresoc.v:176547.1-178078.10" +attribute \src "libresoc.v:169848.1-171337.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" -module \pipe_start - attribute \src "libresoc.v:177884.3-177896.6" - wire $0\div_by_zero$next[0:0]$10316 - attribute \src "libresoc.v:177670.3-177671.39" - wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:177858.3-177870.6" - wire $0\dive_abs_ov32$next[0:0]$10310 - attribute \src "libresoc.v:177674.3-177675.43" - wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:177871.3-177883.6" - wire $0\dive_abs_ov64$next[0:0]$10313 - attribute \src "libresoc.v:177672.3-177673.43" - wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:177897.3-177909.6" - wire width 128 $0\dividend$next[127:0]$10319 - attribute \src "libresoc.v:177668.3-177669.33" - wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:177845.3-177857.6" - wire $0\dividend_neg$next[0:0]$10307 - attribute \src "libresoc.v:177676.3-177677.41" - wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:177832.3-177844.6" - wire $0\divisor_neg$next[0:0]$10304 - attribute \src "libresoc.v:177678.3-177679.39" - wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:177910.3-177922.6" - wire width 64 $0\divisor_radicand$next[63:0]$10322 - attribute \src "libresoc.v:177666.3-177667.49" - wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:176548.7-176548.20" +module \pipe_end + attribute \src "libresoc.v:171175.3-171193.6" + wire width 4 $0\cr_a$next[3:0]$9888 + attribute \src "libresoc.v:170994.3-170995.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:171175.3-171193.6" + wire $0\cr_a_ok$next[0:0]$9889 + attribute \src "libresoc.v:170996.3-170997.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:169849.7-169849.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 4 $0\logical_op__data_len$next[3:0]$10335 - attribute \src "libresoc.v:177718.3-177719.57" - wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 13 $0\logical_op__fn_unit$next[12:0]$10336 - attribute \src "libresoc.v:177688.3-177689.55" - wire width 13 $0\logical_op__fn_unit[12:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$10337 - attribute \src "libresoc.v:177690.3-177691.69" - wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__imm_data__ok$next[0:0]$10338 - attribute \src "libresoc.v:177692.3-177693.65" - wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$10339 - attribute \src "libresoc.v:177706.3-177707.63" - wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 32 $0\logical_op__insn$next[31:0]$10340 - attribute \src "libresoc.v:177720.3-177721.49" - wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$10341 - attribute \src "libresoc.v:177686.3-177687.59" - wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__invert_in$next[0:0]$10342 - attribute \src "libresoc.v:177702.3-177703.59" - wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__invert_out$next[0:0]$10343 - attribute \src "libresoc.v:177708.3-177709.61" - wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__is_32bit$next[0:0]$10344 - attribute \src "libresoc.v:177714.3-177715.57" - wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__is_signed$next[0:0]$10345 - attribute \src "libresoc.v:177716.3-177717.59" - wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__oe__oe$next[0:0]$10346 - attribute \src "libresoc.v:177698.3-177699.53" - wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__oe__ok$next[0:0]$10347 - attribute \src "libresoc.v:177700.3-177701.53" - wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__output_carry$next[0:0]$10348 - attribute \src "libresoc.v:177712.3-177713.65" - wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__rc__ok$next[0:0]$10349 - attribute \src "libresoc.v:177696.3-177697.53" - wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__rc__rc$next[0:0]$10350 - attribute \src "libresoc.v:177694.3-177695.53" - wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__write_cr0$next[0:0]$10351 - attribute \src "libresoc.v:177710.3-177711.59" - wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $0\logical_op__zero_a$next[0:0]$10352 - attribute \src "libresoc.v:177704.3-177705.53" - wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:177954.3-177966.6" - wire width 2 $0\muxid$next[1:0]$10332 - attribute \src "libresoc.v:177722.3-177723.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:177923.3-177935.6" - wire width 2 $0\operation$next[1:0]$10325 - attribute \src "libresoc.v:177664.3-177665.35" - wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:177936.3-177953.6" - wire $0\r_busy$next[0:0]$10328 - attribute \src "libresoc.v:177724.3-177725.29" + attribute \src "libresoc.v:171263.3-171304.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9913 + attribute \src "libresoc.v:171034.3-171035.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9875 + attribute \src "libresoc.v:169890.13-169890.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9959 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 13 $0\logical_op__fn_unit$3$next[12:0]$9914 + attribute \src "libresoc.v:171004.3-171005.61" + wire width 13 $0\logical_op__fn_unit$3[12:0]$9845 + attribute \src "libresoc.v:169927.14-169927.48" + wire width 13 $0\logical_op__fn_unit$3[12:0]$9961 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9915 + attribute \src "libresoc.v:171006.3-171007.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9847 + attribute \src "libresoc.v:169950.14-169950.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9963 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9916 + attribute \src "libresoc.v:171008.3-171009.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9849 + attribute \src "libresoc.v:169959.7-169959.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9965 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9917 + attribute \src "libresoc.v:171022.3-171023.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9863 + attribute \src "libresoc.v:169976.13-169976.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9967 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9918 + attribute \src "libresoc.v:171036.3-171037.57" + wire width 32 $0\logical_op__insn$19[31:0]$9877 + attribute \src "libresoc.v:169989.14-169989.43" + wire width 32 $0\logical_op__insn$19[31:0]$9969 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9919 + attribute \src "libresoc.v:171002.3-171003.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9843 + attribute \src "libresoc.v:170146.13-170146.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9971 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__invert_in$10$next[0:0]$9920 + attribute \src "libresoc.v:171018.3-171019.67" + wire $0\logical_op__invert_in$10[0:0]$9859 + attribute \src "libresoc.v:170229.7-170229.40" + wire $0\logical_op__invert_in$10[0:0]$9973 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__invert_out$13$next[0:0]$9921 + attribute \src "libresoc.v:171024.3-171025.69" + wire $0\logical_op__invert_out$13[0:0]$9865 + attribute \src "libresoc.v:170238.7-170238.41" + wire $0\logical_op__invert_out$13[0:0]$9975 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9922 + attribute \src "libresoc.v:171030.3-171031.65" + wire $0\logical_op__is_32bit$16[0:0]$9871 + attribute \src "libresoc.v:170247.7-170247.39" + wire $0\logical_op__is_32bit$16[0:0]$9977 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__is_signed$17$next[0:0]$9923 + attribute \src "libresoc.v:171032.3-171033.67" + wire $0\logical_op__is_signed$17[0:0]$9873 + attribute \src "libresoc.v:170256.7-170256.40" + wire $0\logical_op__is_signed$17[0:0]$9979 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9924 + attribute \src "libresoc.v:171014.3-171015.59" + wire $0\logical_op__oe__oe$8[0:0]$9855 + attribute \src "libresoc.v:170265.7-170265.36" + wire $0\logical_op__oe__oe$8[0:0]$9981 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9925 + attribute \src "libresoc.v:171016.3-171017.59" + wire $0\logical_op__oe__ok$9[0:0]$9857 + attribute \src "libresoc.v:170276.7-170276.36" + wire $0\logical_op__oe__ok$9[0:0]$9983 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__output_carry$15$next[0:0]$9926 + attribute \src "libresoc.v:171028.3-171029.73" + wire $0\logical_op__output_carry$15[0:0]$9869 + attribute \src "libresoc.v:170283.7-170283.43" + wire $0\logical_op__output_carry$15[0:0]$9985 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9927 + attribute \src "libresoc.v:171012.3-171013.59" + wire $0\logical_op__rc__ok$7[0:0]$9853 + attribute \src "libresoc.v:170292.7-170292.36" + wire $0\logical_op__rc__ok$7[0:0]$9987 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9928 + attribute \src "libresoc.v:171010.3-171011.59" + wire $0\logical_op__rc__rc$6[0:0]$9851 + attribute \src "libresoc.v:170301.7-170301.36" + wire $0\logical_op__rc__rc$6[0:0]$9989 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9929 + attribute \src "libresoc.v:171026.3-171027.67" + wire $0\logical_op__write_cr0$14[0:0]$9867 + attribute \src "libresoc.v:170310.7-170310.40" + wire $0\logical_op__write_cr0$14[0:0]$9991 + attribute \src "libresoc.v:171263.3-171304.6" + wire $0\logical_op__zero_a$11$next[0:0]$9930 + attribute \src "libresoc.v:171020.3-171021.61" + wire $0\logical_op__zero_a$11[0:0]$9861 + attribute \src "libresoc.v:170319.7-170319.37" + wire $0\logical_op__zero_a$11[0:0]$9993 + attribute \src "libresoc.v:171250.3-171262.6" + wire width 2 $0\muxid$1$next[1:0]$9910 + attribute \src "libresoc.v:171038.3-171039.33" + wire width 2 $0\muxid$1[1:0]$9879 + attribute \src "libresoc.v:170328.13-170328.29" + wire width 2 $0\muxid$1[1:0]$9995 + attribute \src "libresoc.v:171156.3-171174.6" + wire width 64 $0\o$next[63:0]$9882 + attribute \src "libresoc.v:170998.3-170999.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:171156.3-171174.6" + wire $0\o_ok$next[0:0]$9883 + attribute \src "libresoc.v:171000.3-171001.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:171232.3-171249.6" + wire $0\r_busy$next[0:0]$9906 + attribute \src "libresoc.v:171040.3-171041.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:178009.3-178021.6" - wire width 64 $0\ra$next[63:0]$10378 - attribute \src "libresoc.v:177684.3-177685.21" - wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:178022.3-178034.6" - wire width 64 $0\rb$next[63:0]$10381 - attribute \src "libresoc.v:177682.3-177683.21" - wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:178035.3-178047.6" - wire $0\xer_so$next[0:0]$10384 - attribute \src "libresoc.v:177680.3-177681.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:177884.3-177896.6" - wire $1\div_by_zero$next[0:0]$10317 - attribute \src "libresoc.v:176557.7-176557.25" - wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:177858.3-177870.6" - wire $1\dive_abs_ov32$next[0:0]$10311 - attribute \src "libresoc.v:176564.7-176564.27" - wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:177871.3-177883.6" - wire $1\dive_abs_ov64$next[0:0]$10314 - attribute \src "libresoc.v:176571.7-176571.27" - wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:177897.3-177909.6" - wire width 128 $1\dividend$next[127:0]$10320 - attribute \src "libresoc.v:176578.15-176578.63" - wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:177845.3-177857.6" - wire $1\dividend_neg$next[0:0]$10308 - attribute \src "libresoc.v:176585.7-176585.26" - wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:177832.3-177844.6" - wire $1\divisor_neg$next[0:0]$10305 - attribute \src "libresoc.v:176592.7-176592.25" - wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:177910.3-177922.6" - wire width 64 $1\divisor_radicand$next[63:0]$10323 - attribute \src "libresoc.v:176599.14-176599.53" - wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 4 $1\logical_op__data_len$next[3:0]$10353 - attribute \src "libresoc.v:176878.13-176878.40" - wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 13 $1\logical_op__fn_unit$next[12:0]$10354 - attribute \src "libresoc.v:176901.14-176901.44" - wire width 13 $1\logical_op__fn_unit[12:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$10355 - attribute \src "libresoc.v:176938.14-176938.63" - wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__imm_data__ok$next[0:0]$10356 - attribute \src "libresoc.v:176947.7-176947.38" - wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$10357 - attribute \src "libresoc.v:176960.13-176960.43" - wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 32 $1\logical_op__insn$next[31:0]$10358 - attribute \src "libresoc.v:176977.14-176977.38" - wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$10359 - attribute \src "libresoc.v:177060.13-177060.42" - wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__invert_in$next[0:0]$10360 - attribute \src "libresoc.v:177217.7-177217.35" - wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__invert_out$next[0:0]$10361 - attribute \src "libresoc.v:177226.7-177226.36" - wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__is_32bit$next[0:0]$10362 - attribute \src "libresoc.v:177235.7-177235.34" - wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__is_signed$next[0:0]$10363 - attribute \src "libresoc.v:177244.7-177244.35" - wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__oe__oe$next[0:0]$10364 - attribute \src "libresoc.v:177253.7-177253.32" - wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__oe__ok$next[0:0]$10365 - attribute \src "libresoc.v:177262.7-177262.32" - wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__output_carry$next[0:0]$10366 - attribute \src "libresoc.v:177271.7-177271.38" - wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__rc__ok$next[0:0]$10367 - attribute \src "libresoc.v:177280.7-177280.32" - wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__rc__rc$next[0:0]$10368 - attribute \src "libresoc.v:177289.7-177289.32" - wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__write_cr0$next[0:0]$10369 - attribute \src "libresoc.v:177298.7-177298.35" - wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire $1\logical_op__zero_a$next[0:0]$10370 - attribute \src "libresoc.v:177307.7-177307.32" - wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:177954.3-177966.6" - wire width 2 $1\muxid$next[1:0]$10333 - attribute \src "libresoc.v:177316.13-177316.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:177923.3-177935.6" - wire width 2 $1\operation$next[1:0]$10326 - attribute \src "libresoc.v:177331.13-177331.29" - wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:177936.3-177953.6" - wire $1\r_busy$next[0:0]$10329 - attribute \src "libresoc.v:177345.7-177345.20" + attribute \src "libresoc.v:171194.3-171212.6" + wire width 2 $0\xer_ov$next[1:0]$9894 + attribute \src "libresoc.v:170990.3-170991.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:171194.3-171212.6" + wire $0\xer_ov_ok$next[0:0]$9895 + attribute \src "libresoc.v:170992.3-170993.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:171213.3-171231.6" + wire $0\xer_so$20$next[0:0]$9901 + attribute \src "libresoc.v:170971.7-170971.25" + wire $0\xer_so$20[0:0]$10002 + attribute \src "libresoc.v:170986.3-170987.37" + wire $0\xer_so$20[0:0]$9834 + attribute \src "libresoc.v:171213.3-171231.6" + wire $0\xer_so_ok$next[0:0]$9900 + attribute \src "libresoc.v:170988.3-170989.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:171175.3-171193.6" + wire width 4 $1\cr_a$next[3:0]$9890 + attribute \src "libresoc.v:169858.13-169858.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:171175.3-171193.6" + wire $1\cr_a_ok$next[0:0]$9891 + attribute \src "libresoc.v:169867.7-169867.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:171263.3-171304.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9931 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 13 $1\logical_op__fn_unit$3$next[12:0]$9932 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9933 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9934 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9935 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9936 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9937 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__invert_in$10$next[0:0]$9938 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__invert_out$13$next[0:0]$9939 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9940 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__is_signed$17$next[0:0]$9941 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9942 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9943 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__output_carry$15$next[0:0]$9944 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9945 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9946 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9947 + attribute \src "libresoc.v:171263.3-171304.6" + wire $1\logical_op__zero_a$11$next[0:0]$9948 + attribute \src "libresoc.v:171250.3-171262.6" + wire width 2 $1\muxid$1$next[1:0]$9911 + attribute \src "libresoc.v:171156.3-171174.6" + wire width 64 $1\o$next[63:0]$9884 + attribute \src "libresoc.v:170341.14-170341.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:171156.3-171174.6" + wire $1\o_ok$next[0:0]$9885 + attribute \src "libresoc.v:170348.7-170348.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:171232.3-171249.6" + wire $1\r_busy$next[0:0]$9907 + attribute \src "libresoc.v:170936.7-170936.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:178009.3-178021.6" - wire width 64 $1\ra$next[63:0]$10379 - attribute \src "libresoc.v:177350.14-177350.39" - wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:178022.3-178034.6" - wire width 64 $1\rb$next[63:0]$10382 - attribute \src "libresoc.v:177361.14-177361.39" - wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:178035.3-178047.6" - wire $1\xer_so$next[0:0]$10385 - attribute \src "libresoc.v:177656.7-177656.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:177967.3-178008.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$10371 - attribute \src "libresoc.v:177967.3-178008.6" - wire $2\logical_op__imm_data__ok$next[0:0]$10372 - attribute \src "libresoc.v:177967.3-178008.6" - wire $2\logical_op__oe__oe$next[0:0]$10373 - attribute \src "libresoc.v:177967.3-178008.6" - wire $2\logical_op__oe__ok$next[0:0]$10374 - attribute \src "libresoc.v:177967.3-178008.6" - wire $2\logical_op__rc__ok$next[0:0]$10375 - attribute \src "libresoc.v:177967.3-178008.6" - wire $2\logical_op__rc__rc$next[0:0]$10376 - attribute \src "libresoc.v:177936.3-177953.6" - wire $2\r_busy$next[0:0]$10330 - attribute \src "libresoc.v:177663.18-177663.118" - wire $and$libresoc.v:177663$10271_Y + attribute \src "libresoc.v:171194.3-171212.6" + wire width 2 $1\xer_ov$next[1:0]$9896 + attribute \src "libresoc.v:170951.13-170951.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:171194.3-171212.6" + wire $1\xer_ov_ok$next[0:0]$9897 + attribute \src "libresoc.v:170958.7-170958.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:171213.3-171231.6" + wire $1\xer_so$20$next[0:0]$9903 + attribute \src "libresoc.v:171213.3-171231.6" + wire $1\xer_so_ok$next[0:0]$9902 + attribute \src "libresoc.v:170976.7-170976.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:171175.3-171193.6" + wire $2\cr_a_ok$next[0:0]$9892 + attribute \src "libresoc.v:171263.3-171304.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9949 + attribute \src "libresoc.v:171263.3-171304.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9950 + attribute \src "libresoc.v:171263.3-171304.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9951 + attribute \src "libresoc.v:171263.3-171304.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9952 + attribute \src "libresoc.v:171263.3-171304.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9953 + attribute \src "libresoc.v:171263.3-171304.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9954 + attribute \src "libresoc.v:171156.3-171174.6" + wire $2\o_ok$next[0:0]$9886 + attribute \src "libresoc.v:171232.3-171249.6" + wire $2\r_busy$next[0:0]$9908 + attribute \src "libresoc.v:171194.3-171212.6" + wire $2\xer_ov_ok$next[0:0]$9898 + attribute \src "libresoc.v:171213.3-171231.6" + wire $2\xer_so_ok$next[0:0]$9904 + attribute \src "libresoc.v:170985.18-170985.118" + wire $and$libresoc.v:170985$9832_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" - wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 62 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire output 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire output 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$94 + wire input 30 \div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire output 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$95 + wire input 28 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 output 31 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire output 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$93 + wire input 29 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire output 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$92 + wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 output 32 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:176548.7-176548.15" + wire input 26 \divisor_neg + attribute \src "libresoc.v:169849.7-169849.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len + wire width 4 input 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len$40 + wire width 4 output 52 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$93 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -360195,7 +350486,7 @@ module \pipe_start attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_logical_op__fn_unit + wire width 13 input 6 \logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -360211,31 +350502,69 @@ module \pipe_start attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \input_logical_op__fn_unit$25 + wire width 13 output 37 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__data + wire width 13 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__data$26 + wire width 13 \logical_op__fn_unit$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__imm_data__ok + wire width 64 input 7 \logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__imm_data__ok$27 + wire width 64 output 38 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$80 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry + wire width 2 input 15 \logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry$34 + wire width 2 output 46 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn$41 + wire width 2 \logical_op__input_carry$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$94 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -360311,7 +350640,7 @@ module \pipe_start attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -360387,169 +350716,9 @@ module \pipe_start attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_in$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_out$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_32bit$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_signed$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__oe$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__ok$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__output_carry$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__rc$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__write_cr0$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__zero_a$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \input_muxid$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 53 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$next - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 6 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 38 \logical_op__fn_unit$3 - attribute \enum_base_type "Function" - attribute \enum_value_0000000000000 "NONE" - attribute \enum_value_0000000000010 "ALU" - attribute \enum_value_0000000000100 "LDST" - attribute \enum_value_0000000001000 "SHIFT_ROT" - attribute \enum_value_0000000010000 "LOGICAL" - attribute \enum_value_0000000100000 "BRANCH" - attribute \enum_value_0000001000000 "CR" - attribute \enum_value_0000010000000 "TRAP" - attribute \enum_value_0000100000000 "MUL" - attribute \enum_value_0001000000000 "DIV" - attribute \enum_value_0010000000000 "SPR" - attribute \enum_value_0100000000000 "MMU" - attribute \enum_value_1000000000000 "SV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \logical_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 39 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 47 \logical_op__input_carry$12 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 54 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$86 + wire width 7 output 36 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$next + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -360625,7 +350794,187 @@ module \pipe_start attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \logical_op__insn_type + wire width 7 \logical_op__insn_type$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$76 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$58 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_logical_op__fn_unit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$45 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$59 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -360701,7 +351050,7 @@ module \pipe_start attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 37 \logical_op__insn_type$2 + wire width 7 \output_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -360777,167 +351126,77 @@ module \pipe_start attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 48 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 51 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 52 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$76 + wire width 7 \output_logical_op__insn_type$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \logical_op__oe__ok$9 + wire \output_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$next + wire \output_logical_op__invert_in$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \logical_op__output_carry + wire \output_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 50 \logical_op__output_carry$15 + wire \output_logical_op__invert_out$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$82 + wire \output_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$next + wire \output_logical_op__is_32bit$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \logical_op__rc__ok + wire \output_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \logical_op__rc__ok$7 + wire \output_logical_op__is_signed$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$74 + wire \output_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$next + wire \output_logical_op__oe__oe$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \logical_op__rc__rc + wire \output_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \logical_op__rc__rc$6 + wire \output_logical_op__oe__ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$73 + wire \output_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$next + wire \output_logical_op__output_carry$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \logical_op__write_cr0 + wire \output_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 49 \logical_op__write_cr0$14 + wire \output_logical_op__rc__ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$81 + wire \output_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$next + wire \output_logical_op__rc__rc$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \logical_op__zero_a + wire \output_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \logical_op__zero_a$11 + wire \output_logical_op__write_cr0$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$78 + wire \output_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 input 36 \muxid$1 + wire \output_logical_op__zero_a$51 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$68 + wire width 2 \output_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 output 33 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" - wire output 35 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" - wire input 34 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" - wire \p_valid_i$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 55 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 56 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next + wire width 2 \output_muxid$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \setup_stage_div_by_zero + wire \output_stage_div_by_zero attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \setup_stage_dive_abs_ov32 + wire \output_stage_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \setup_stage_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \setup_stage_dividend + wire \output_stage_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \setup_stage_dividend_neg + wire \output_stage_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \setup_stage_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \setup_stage_divisor_radicand + wire \output_stage_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len + wire width 4 \output_stage_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len$62 + wire width 4 \output_stage_logical_op__data_len$38 attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -360953,7 +351212,7 @@ module \pipe_start attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \setup_stage_logical_op__fn_unit + wire width 13 \output_stage_logical_op__fn_unit attribute \enum_base_type "Function" attribute \enum_value_0000000000000 "NONE" attribute \enum_value_0000000000010 "ALU" @@ -360969,31 +351228,31 @@ module \pipe_start attribute \enum_value_0100000000000 "MMU" attribute \enum_value_1000000000000 "SV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \setup_stage_logical_op__fn_unit$47 + wire width 13 \output_stage_logical_op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__data + wire width 64 \output_stage_logical_op__imm_data__data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__data$48 + wire width 64 \output_stage_logical_op__imm_data__data$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__imm_data__ok + wire \output_stage_logical_op__imm_data__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__imm_data__ok$49 + wire \output_stage_logical_op__imm_data__ok$25 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \setup_stage_logical_op__input_carry + wire width 2 \output_stage_logical_op__input_carry attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \setup_stage_logical_op__input_carry$56 + wire width 2 \output_stage_logical_op__input_carry$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \setup_stage_logical_op__insn + wire width 32 \output_stage_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \setup_stage_logical_op__insn$63 + wire width 32 \output_stage_logical_op__insn$39 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -361069,7 +351328,7 @@ module \pipe_start attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \setup_stage_logical_op__insn_type + wire width 7 \output_stage_logical_op__insn_type attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -361145,7622 +351404,7908 @@ module \pipe_start attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \setup_stage_logical_op__insn_type$46 + wire width 7 \output_stage_logical_op__insn_type$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_in + wire \output_stage_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_in$54 + wire \output_stage_logical_op__invert_in$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_out + wire \output_stage_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_out$57 + wire \output_stage_logical_op__invert_out$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_32bit + wire \output_stage_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_32bit$60 + wire \output_stage_logical_op__is_32bit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_signed + wire \output_stage_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_signed$61 + wire \output_stage_logical_op__is_signed$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__oe + wire \output_stage_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__oe$52 + wire \output_stage_logical_op__oe__oe$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__ok + wire \output_stage_logical_op__oe__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__ok$53 + wire \output_stage_logical_op__oe__ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__output_carry + wire \output_stage_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__output_carry$59 + wire \output_stage_logical_op__output_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__ok + wire \output_stage_logical_op__rc__ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__ok$51 + wire \output_stage_logical_op__rc__ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__rc + wire \output_stage_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__rc$50 + wire \output_stage_logical_op__rc__rc$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__write_cr0 + wire \output_stage_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__write_cr0$58 + wire \output_stage_logical_op__write_cr0$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__zero_a + wire \output_stage_logical_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__zero_a$55 + wire \output_stage_logical_op__zero_a$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \setup_stage_muxid + wire width 2 \output_stage_muxid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" - wire width 2 \setup_stage_muxid$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \setup_stage_operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \setup_stage_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \setup_stage_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \setup_stage_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \setup_stage_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 57 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:177663$10271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$65 - connect \B \p_ready_o - connect \Y $and$libresoc.v:177663$10271_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:177726.14-177771.4" - cell \input$78 \input - connect \logical_op__data_len \input_logical_op__data_len - connect \logical_op__data_len$18 \input_logical_op__data_len$40 - connect \logical_op__fn_unit \input_logical_op__fn_unit - connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 - connect \logical_op__imm_data__data \input_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$26 - connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$27 - connect \logical_op__input_carry \input_logical_op__input_carry - connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 - connect \logical_op__insn \input_logical_op__insn - connect \logical_op__insn$19 \input_logical_op__insn$41 - connect \logical_op__insn_type \input_logical_op__insn_type - connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 - connect \logical_op__invert_in \input_logical_op__invert_in - connect \logical_op__invert_in$10 \input_logical_op__invert_in$32 - connect \logical_op__invert_out \input_logical_op__invert_out - connect \logical_op__invert_out$13 \input_logical_op__invert_out$35 - connect \logical_op__is_32bit \input_logical_op__is_32bit - connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38 - connect \logical_op__is_signed \input_logical_op__is_signed - connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 - connect \logical_op__oe__oe \input_logical_op__oe__oe - connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 - connect \logical_op__oe__ok \input_logical_op__oe__ok - connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 - connect \logical_op__output_carry \input_logical_op__output_carry - connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 - connect \logical_op__rc__ok \input_logical_op__rc__ok - connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 - connect \logical_op__rc__rc \input_logical_op__rc__rc - connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 - connect \logical_op__write_cr0 \input_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 - connect \logical_op__zero_a \input_logical_op__zero_a - connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$23 - connect \ra \input_ra - connect \ra$20 \input_ra$42 - connect \rb \input_rb - connect \rb$21 \input_rb$43 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$44 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:177772.10-177775.4" - cell \n$77 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:177776.10-177779.4" - cell \p$76 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:177780.15-177831.4" - cell \setup_stage \setup_stage - connect \div_by_zero \setup_stage_div_by_zero - connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 - connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 - connect \dividend \setup_stage_dividend - connect \dividend_neg \setup_stage_dividend_neg - connect \divisor_neg \setup_stage_divisor_neg - connect \divisor_radicand \setup_stage_divisor_radicand - connect \logical_op__data_len \setup_stage_logical_op__data_len - connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 - connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit - connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 - connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 - connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 - connect \logical_op__input_carry \setup_stage_logical_op__input_carry - connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 - connect \logical_op__insn \setup_stage_logical_op__insn - connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 - connect \logical_op__insn_type \setup_stage_logical_op__insn_type - connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 - connect \logical_op__invert_in \setup_stage_logical_op__invert_in - connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 - connect \logical_op__invert_out \setup_stage_logical_op__invert_out - connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 - connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit - connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 - connect \logical_op__is_signed \setup_stage_logical_op__is_signed - connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 - connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe - connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 - connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok - connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 - connect \logical_op__output_carry \setup_stage_logical_op__output_carry - connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 - connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok - connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 - connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc - connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 - connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 - connect \logical_op__zero_a \setup_stage_logical_op__zero_a - connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 - connect \muxid \setup_stage_muxid - connect \muxid$1 \setup_stage_muxid$45 - connect \operation \setup_stage_operation - connect \ra \setup_stage_ra - connect \rb \setup_stage_rb - connect \xer_so \setup_stage_xer_so - connect \xer_so$20 \setup_stage_xer_so$64 - end - attribute \src "libresoc.v:176548.7-176548.20" - process $proc$libresoc.v:176548$10386 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:176557.7-176557.25" - process $proc$libresoc.v:176557$10387 - assign { } { } - assign $1\div_by_zero[0:0] 1'0 - sync always - sync init - update \div_by_zero $1\div_by_zero[0:0] - end - attribute \src "libresoc.v:176564.7-176564.27" - process $proc$libresoc.v:176564$10388 - assign { } { } - assign $1\dive_abs_ov32[0:0] 1'0 - sync always - sync init - update \dive_abs_ov32 $1\dive_abs_ov32[0:0] - end - attribute \src "libresoc.v:176571.7-176571.27" - process $proc$libresoc.v:176571$10389 - assign { } { } - assign $1\dive_abs_ov64[0:0] 1'0 - sync always - sync init - update \dive_abs_ov64 $1\dive_abs_ov64[0:0] - end - attribute \src "libresoc.v:176578.15-176578.63" - process $proc$libresoc.v:176578$10390 - assign { } { } - assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dividend $1\dividend[127:0] - end - attribute \src "libresoc.v:176585.7-176585.26" - process $proc$libresoc.v:176585$10391 - assign { } { } - assign $1\dividend_neg[0:0] 1'0 - sync always - sync init - update \dividend_neg $1\dividend_neg[0:0] - end - attribute \src "libresoc.v:176592.7-176592.25" - process $proc$libresoc.v:176592$10392 - assign { } { } - assign $1\divisor_neg[0:0] 1'0 - sync always - sync init - update \divisor_neg $1\divisor_neg[0:0] - end - attribute \src "libresoc.v:176599.14-176599.53" - process $proc$libresoc.v:176599$10393 - assign { } { } - assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \divisor_radicand $1\divisor_radicand[63:0] - end - attribute \src "libresoc.v:176878.13-176878.40" - process $proc$libresoc.v:176878$10394 - assign { } { } - assign $1\logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \logical_op__data_len $1\logical_op__data_len[3:0] - end - attribute \src "libresoc.v:176901.14-176901.44" - process $proc$libresoc.v:176901$10395 - assign { } { } - assign $1\logical_op__fn_unit[12:0] 13'0000000000000 - sync always - sync init - update \logical_op__fn_unit $1\logical_op__fn_unit[12:0] - end - attribute \src "libresoc.v:176938.14-176938.63" - process $proc$libresoc.v:176938$10396 - assign { } { } - assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:176947.7-176947.38" - process $proc$libresoc.v:176947$10397 - assign { } { } - assign $1\logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:176960.13-176960.43" - process $proc$libresoc.v:176960$10398 - assign { } { } - assign $1\logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \logical_op__input_carry $1\logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:176977.14-176977.38" - process $proc$libresoc.v:176977$10399 - assign { } { } - assign $1\logical_op__insn[31:0] 0 - sync always - sync init - update \logical_op__insn $1\logical_op__insn[31:0] - end - attribute \src "libresoc.v:177060.13-177060.42" - process $proc$libresoc.v:177060$10400 - assign { } { } - assign $1\logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \logical_op__insn_type $1\logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:177217.7-177217.35" - process $proc$libresoc.v:177217$10401 - assign { } { } - assign $1\logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \logical_op__invert_in $1\logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:177226.7-177226.36" - process $proc$libresoc.v:177226$10402 - assign { } { } - assign $1\logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \logical_op__invert_out $1\logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:177235.7-177235.34" - process $proc$libresoc.v:177235$10403 - assign { } { } - assign $1\logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:177244.7-177244.35" - process $proc$libresoc.v:177244$10404 - assign { } { } - assign $1\logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \logical_op__is_signed $1\logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:177253.7-177253.32" - process $proc$libresoc.v:177253$10405 - assign { } { } - assign $1\logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:177262.7-177262.32" - process $proc$libresoc.v:177262$10406 - assign { } { } - assign $1\logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:177271.7-177271.38" - process $proc$libresoc.v:177271$10407 - assign { } { } - assign $1\logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \logical_op__output_carry $1\logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:177280.7-177280.32" - process $proc$libresoc.v:177280$10408 - assign { } { } - assign $1\logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:177289.7-177289.32" - process $proc$libresoc.v:177289$10409 - assign { } { } - assign $1\logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:177298.7-177298.35" - process $proc$libresoc.v:177298$10410 - assign { } { } - assign $1\logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:177307.7-177307.32" - process $proc$libresoc.v:177307$10411 - assign { } { } - assign $1\logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \logical_op__zero_a $1\logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:177316.13-177316.25" - process $proc$libresoc.v:177316$10412 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "libresoc.v:177331.13-177331.29" - process $proc$libresoc.v:177331$10413 - assign { } { } - assign $1\operation[1:0] 2'00 - sync always - sync init - update \operation $1\operation[1:0] - end - attribute \src "libresoc.v:177345.7-177345.20" - process $proc$libresoc.v:177345$10414 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:177350.14-177350.39" - process $proc$libresoc.v:177350$10415 - assign { } { } - assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ra $1\ra[63:0] - end - attribute \src "libresoc.v:177361.14-177361.39" - process $proc$libresoc.v:177361$10416 - assign { } { } - assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \rb $1\rb[63:0] - end - attribute \src "libresoc.v:177656.7-177656.20" - process $proc$libresoc.v:177656$10417 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "libresoc.v:177664.3-177665.35" - process $proc$libresoc.v:177664$10272 - assign { } { } - assign $0\operation[1:0] \operation$next - sync posedge \coresync_clk - update \operation $0\operation[1:0] - end - attribute \src "libresoc.v:177666.3-177667.49" - process $proc$libresoc.v:177666$10273 - assign { } { } - assign $0\divisor_radicand[63:0] \divisor_radicand$next - sync posedge \coresync_clk - update \divisor_radicand $0\divisor_radicand[63:0] - end - attribute \src "libresoc.v:177668.3-177669.33" - process $proc$libresoc.v:177668$10274 - assign { } { } - assign $0\dividend[127:0] \dividend$next - sync posedge \coresync_clk - update \dividend $0\dividend[127:0] - end - attribute \src "libresoc.v:177670.3-177671.39" - process $proc$libresoc.v:177670$10275 - assign { } { } - assign $0\div_by_zero[0:0] \div_by_zero$next - sync posedge \coresync_clk - update \div_by_zero $0\div_by_zero[0:0] - end - attribute \src "libresoc.v:177672.3-177673.43" - process $proc$libresoc.v:177672$10276 - assign { } { } - assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next - sync posedge \coresync_clk - update \dive_abs_ov64 $0\dive_abs_ov64[0:0] - end - attribute \src "libresoc.v:177674.3-177675.43" - process $proc$libresoc.v:177674$10277 - assign { } { } - assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next - sync posedge \coresync_clk - update \dive_abs_ov32 $0\dive_abs_ov32[0:0] - end - attribute \src "libresoc.v:177676.3-177677.41" - process $proc$libresoc.v:177676$10278 - assign { } { } - assign $0\dividend_neg[0:0] \dividend_neg$next - sync posedge \coresync_clk - update \dividend_neg $0\dividend_neg[0:0] - end - attribute \src "libresoc.v:177678.3-177679.39" - process $proc$libresoc.v:177678$10279 - assign { } { } - assign $0\divisor_neg[0:0] \divisor_neg$next - sync posedge \coresync_clk - update \divisor_neg $0\divisor_neg[0:0] - end - attribute \src "libresoc.v:177680.3-177681.29" - process $proc$libresoc.v:177680$10280 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:177682.3-177683.21" - process $proc$libresoc.v:177682$10281 - assign { } { } - assign $0\rb[63:0] \rb$next - sync posedge \coresync_clk - update \rb $0\rb[63:0] - end - attribute \src "libresoc.v:177684.3-177685.21" - process $proc$libresoc.v:177684$10282 - assign { } { } - assign $0\ra[63:0] \ra$next - sync posedge \coresync_clk - update \ra $0\ra[63:0] - end - attribute \src "libresoc.v:177686.3-177687.59" - process $proc$libresoc.v:177686$10283 - assign { } { } - assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next - sync posedge \coresync_clk - update \logical_op__insn_type $0\logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:177688.3-177689.55" - process $proc$libresoc.v:177688$10284 - assign { } { } - assign $0\logical_op__fn_unit[12:0] \logical_op__fn_unit$next - sync posedge \coresync_clk - update \logical_op__fn_unit $0\logical_op__fn_unit[12:0] - end - attribute \src "libresoc.v:177690.3-177691.69" - process $proc$libresoc.v:177690$10285 - assign { } { } - assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next - sync posedge \coresync_clk - update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:177692.3-177693.65" - process $proc$libresoc.v:177692$10286 - assign { } { } - assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:177694.3-177695.53" - process $proc$libresoc.v:177694$10287 - assign { } { } - assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next - sync posedge \coresync_clk - update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:177696.3-177697.53" - process $proc$libresoc.v:177696$10288 - assign { } { } - assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next - sync posedge \coresync_clk - update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:177698.3-177699.53" - process $proc$libresoc.v:177698$10289 - assign { } { } - assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next - sync posedge \coresync_clk - update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:177700.3-177701.53" - process $proc$libresoc.v:177700$10290 - assign { } { } - assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next - sync posedge \coresync_clk - update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:177702.3-177703.59" - process $proc$libresoc.v:177702$10291 - assign { } { } - assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next - sync posedge \coresync_clk - update \logical_op__invert_in $0\logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:177704.3-177705.53" - process $proc$libresoc.v:177704$10292 - assign { } { } - assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next - sync posedge \coresync_clk - update \logical_op__zero_a $0\logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:177706.3-177707.63" - process $proc$libresoc.v:177706$10293 - assign { } { } - assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next - sync posedge \coresync_clk - update \logical_op__input_carry $0\logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:177708.3-177709.61" - process $proc$libresoc.v:177708$10294 - assign { } { } - assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next - sync posedge \coresync_clk - update \logical_op__invert_out $0\logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:177710.3-177711.59" - process $proc$libresoc.v:177710$10295 - assign { } { } - assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next - sync posedge \coresync_clk - update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:177712.3-177713.65" - process $proc$libresoc.v:177712$10296 - assign { } { } - assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next - sync posedge \coresync_clk - update \logical_op__output_carry $0\logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:177714.3-177715.57" - process $proc$libresoc.v:177714$10297 - assign { } { } - assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next - sync posedge \coresync_clk - update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:177716.3-177717.59" - process $proc$libresoc.v:177716$10298 - assign { } { } - assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next - sync posedge \coresync_clk - update \logical_op__is_signed $0\logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:177718.3-177719.57" - process $proc$libresoc.v:177718$10299 - assign { } { } - assign $0\logical_op__data_len[3:0] \logical_op__data_len$next - sync posedge \coresync_clk - update \logical_op__data_len $0\logical_op__data_len[3:0] - end - attribute \src "libresoc.v:177720.3-177721.49" - process $proc$libresoc.v:177720$10300 - assign { } { } - assign $0\logical_op__insn[31:0] \logical_op__insn$next - sync posedge \coresync_clk - update \logical_op__insn $0\logical_op__insn[31:0] - end - attribute \src "libresoc.v:177722.3-177723.27" - process $proc$libresoc.v:177722$10301 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:177724.3-177725.29" - process $proc$libresoc.v:177724$10302 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:177832.3-177844.6" - process $proc$libresoc.v:177832$10303 - assign { } { } - assign { } { } - assign $0\divisor_neg$next[0:0]$10304 $1\divisor_neg$next[0:0]$10305 - attribute \src "libresoc.v:177833.5-177833.29" - switch \initial - attribute \src "libresoc.v:177833.9-177833.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\divisor_neg$next[0:0]$10305 \divisor_neg$92 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\divisor_neg$next[0:0]$10305 \divisor_neg$92 - case - assign $1\divisor_neg$next[0:0]$10305 \divisor_neg - end - sync always - update \divisor_neg$next $0\divisor_neg$next[0:0]$10304 - end - attribute \src "libresoc.v:177845.3-177857.6" - process $proc$libresoc.v:177845$10306 - assign { } { } - assign { } { } - assign $0\dividend_neg$next[0:0]$10307 $1\dividend_neg$next[0:0]$10308 - attribute \src "libresoc.v:177846.5-177846.29" - switch \initial - attribute \src "libresoc.v:177846.9-177846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dividend_neg$next[0:0]$10308 \dividend_neg$93 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dividend_neg$next[0:0]$10308 \dividend_neg$93 - case - assign $1\dividend_neg$next[0:0]$10308 \dividend_neg - end - sync always - update \dividend_neg$next $0\dividend_neg$next[0:0]$10307 - end - attribute \src "libresoc.v:177858.3-177870.6" - process $proc$libresoc.v:177858$10309 - assign { } { } - assign { } { } - assign $0\dive_abs_ov32$next[0:0]$10310 $1\dive_abs_ov32$next[0:0]$10311 - attribute \src "libresoc.v:177859.5-177859.29" - switch \initial - attribute \src "libresoc.v:177859.9-177859.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10311 \dive_abs_ov32$94 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10311 \dive_abs_ov32$94 - case - assign $1\dive_abs_ov32$next[0:0]$10311 \dive_abs_ov32 - end - sync always - update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10310 - end - attribute \src "libresoc.v:177871.3-177883.6" - process $proc$libresoc.v:177871$10312 - assign { } { } - assign { } { } - assign $0\dive_abs_ov64$next[0:0]$10313 $1\dive_abs_ov64$next[0:0]$10314 - attribute \src "libresoc.v:177872.5-177872.29" - switch \initial - attribute \src "libresoc.v:177872.9-177872.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10314 \dive_abs_ov64$95 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10314 \dive_abs_ov64$95 - case - assign $1\dive_abs_ov64$next[0:0]$10314 \dive_abs_ov64 - end - sync always - update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10313 - end - attribute \src "libresoc.v:177884.3-177896.6" - process $proc$libresoc.v:177884$10315 - assign { } { } - assign { } { } - assign $0\div_by_zero$next[0:0]$10316 $1\div_by_zero$next[0:0]$10317 - attribute \src "libresoc.v:177885.5-177885.29" - switch \initial - attribute \src "libresoc.v:177885.9-177885.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\div_by_zero$next[0:0]$10317 \div_by_zero$96 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\div_by_zero$next[0:0]$10317 \div_by_zero$96 - case - assign $1\div_by_zero$next[0:0]$10317 \div_by_zero - end - sync always - update \div_by_zero$next $0\div_by_zero$next[0:0]$10316 - end - attribute \src "libresoc.v:177897.3-177909.6" - process $proc$libresoc.v:177897$10318 - assign { } { } - assign { } { } - assign $0\dividend$next[127:0]$10319 $1\dividend$next[127:0]$10320 - attribute \src "libresoc.v:177898.5-177898.29" - switch \initial - attribute \src "libresoc.v:177898.9-177898.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\dividend$next[127:0]$10320 \dividend$97 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\dividend$next[127:0]$10320 \dividend$97 - case - assign $1\dividend$next[127:0]$10320 \dividend - end - sync always - update \dividend$next $0\dividend$next[127:0]$10319 + wire width 2 \output_stage_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_stage_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_stage_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \output_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \output_stage_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_stage_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_stage_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \output_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_stage_xer_so$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 31 \quotient_root + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 32 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 58 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 59 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 60 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 61 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:170985$9832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$73 + connect \B \p_ready_o + connect \Y $and$libresoc.v:170985$9832_Y end - attribute \src "libresoc.v:177910.3-177922.6" - process $proc$libresoc.v:177910$10321 - assign { } { } - assign { } { } - assign $0\divisor_radicand$next[63:0]$10322 $1\divisor_radicand$next[63:0]$10323 - attribute \src "libresoc.v:177911.5-177911.29" - switch \initial - attribute \src "libresoc.v:177911.9-177911.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\divisor_radicand$next[63:0]$10323 \divisor_radicand$98 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\divisor_radicand$next[63:0]$10323 \divisor_radicand$98 - case - assign $1\divisor_radicand$next[63:0]$10323 \divisor_radicand - end - sync always - update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10322 + attribute \module_not_derived 1 + attribute \src "libresoc.v:171042.10-171045.4" + cell \n$82 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end - attribute \src "libresoc.v:177923.3-177935.6" - process $proc$libresoc.v:177923$10324 - assign { } { } - assign { } { } - assign $0\operation$next[1:0]$10325 $1\operation$next[1:0]$10326 - attribute \src "libresoc.v:177924.5-177924.29" - switch \initial - attribute \src "libresoc.v:177924.9-177924.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\operation$next[1:0]$10326 \operation$99 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\operation$next[1:0]$10326 \operation$99 - case - assign $1\operation$next[1:0]$10326 \operation - end - sync always - update \operation$next $0\operation$next[1:0]$10325 + attribute \module_not_derived 1 + attribute \src "libresoc.v:171046.15-171098.4" + cell \output$83 \output + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$62 + connect \cr_a_ok \output_cr_a_ok + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__data_len$18 \output_logical_op__data_len$58 + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$44 + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$45 + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 + connect \logical_op__insn \output_logical_op__insn + connect \logical_op__insn$19 \output_logical_op__insn$59 + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__invert_in$10 \output_logical_op__invert_in$50 + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__invert_out$13 \output_logical_op__invert_out$53 + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56 + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 + connect \logical_op__oe__ok \output_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$49 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 + connect \logical_op__rc__ok \output_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$47 + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$41 + connect \o \output_o + connect \o$20 \output_o$60 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$61 + connect \xer_ov \output_xer_ov + connect \xer_ov$23 \output_xer_ov$63 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$24 \output_xer_so$64 + connect \xer_so_ok \output_xer_so_ok end - attribute \src "libresoc.v:177936.3-177953.6" - process $proc$libresoc.v:177936$10327 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$10328 $2\r_busy$next[0:0]$10330 - attribute \src "libresoc.v:177937.5-177937.29" - switch \initial - attribute \src "libresoc.v:177937.9-177937.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$10329 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$10329 1'0 - case - assign $1\r_busy$next[0:0]$10329 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$10330 1'0 - case - assign $2\r_busy$next[0:0]$10330 $1\r_busy$next[0:0]$10329 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$10328 + attribute \module_not_derived 1 + attribute \src "libresoc.v:171099.16-171151.4" + cell \output_stage \output_stage + connect \div_by_zero \output_stage_div_by_zero + connect \dive_abs_ov32 \output_stage_dive_abs_ov32 + connect \dive_abs_ov64 \output_stage_dive_abs_ov64 + connect \dividend_neg \output_stage_dividend_neg + connect \divisor_neg \output_stage_divisor_neg + connect \logical_op__data_len \output_stage_logical_op__data_len + connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 + connect \logical_op__fn_unit \output_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \output_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 + connect \logical_op__insn \output_stage_logical_op__insn + connect \logical_op__insn$19 \output_stage_logical_op__insn$39 + connect \logical_op__insn_type \output_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 + connect \logical_op__invert_in \output_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 + connect \logical_op__invert_out \output_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 + connect \logical_op__is_32bit \output_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 + connect \logical_op__is_signed \output_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 + connect \logical_op__oe__oe \output_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 + connect \logical_op__oe__ok \output_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 + connect \logical_op__output_carry \output_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 + connect \logical_op__rc__ok \output_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 + connect \logical_op__rc__rc \output_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 + connect \logical_op__zero_a \output_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 + connect \muxid \output_stage_muxid + connect \muxid$1 \output_stage_muxid$21 + connect \o \output_stage_o + connect \o_ok \output_stage_o_ok + connect \quotient_root \output_stage_quotient_root + connect \remainder \output_stage_remainder + connect \xer_ov \output_stage_xer_ov + connect \xer_ov_ok \output_stage_xer_ov_ok + connect \xer_so \output_stage_xer_so + connect \xer_so$20 \output_stage_xer_so$40 end - attribute \src "libresoc.v:177954.3-177966.6" - process $proc$libresoc.v:177954$10331 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$10332 $1\muxid$next[1:0]$10333 - attribute \src "libresoc.v:177955.5-177955.29" - switch \initial - attribute \src "libresoc.v:177955.9-177955.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$10333 \muxid$68 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$10333 \muxid$68 - case - assign $1\muxid$next[1:0]$10333 \muxid - end - sync always - update \muxid$next $0\muxid$next[1:0]$10332 + attribute \module_not_derived 1 + attribute \src "libresoc.v:171152.10-171155.4" + cell \p$81 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:177967.3-178008.6" - process $proc$libresoc.v:177967$10334 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:169849.7-169849.20" + process $proc$libresoc.v:169849$9955 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$next[3:0]$10335 $1\logical_op__data_len$next[3:0]$10353 - assign $0\logical_op__fn_unit$next[12:0]$10336 $1\logical_op__fn_unit$next[12:0]$10354 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$next[1:0]$10339 $1\logical_op__input_carry$next[1:0]$10357 - assign $0\logical_op__insn$next[31:0]$10340 $1\logical_op__insn$next[31:0]$10358 - assign $0\logical_op__insn_type$next[6:0]$10341 $1\logical_op__insn_type$next[6:0]$10359 - assign $0\logical_op__invert_in$next[0:0]$10342 $1\logical_op__invert_in$next[0:0]$10360 - assign $0\logical_op__invert_out$next[0:0]$10343 $1\logical_op__invert_out$next[0:0]$10361 - assign $0\logical_op__is_32bit$next[0:0]$10344 $1\logical_op__is_32bit$next[0:0]$10362 - assign $0\logical_op__is_signed$next[0:0]$10345 $1\logical_op__is_signed$next[0:0]$10363 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$next[0:0]$10348 $1\logical_op__output_carry$next[0:0]$10366 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$10351 $1\logical_op__write_cr0$next[0:0]$10369 - assign $0\logical_op__zero_a$next[0:0]$10352 $1\logical_op__zero_a$next[0:0]$10370 - assign $0\logical_op__imm_data__data$next[63:0]$10337 $2\logical_op__imm_data__data$next[63:0]$10371 - assign $0\logical_op__imm_data__ok$next[0:0]$10338 $2\logical_op__imm_data__ok$next[0:0]$10372 - assign $0\logical_op__oe__oe$next[0:0]$10346 $2\logical_op__oe__oe$next[0:0]$10373 - assign $0\logical_op__oe__ok$next[0:0]$10347 $2\logical_op__oe__ok$next[0:0]$10374 - assign $0\logical_op__rc__ok$next[0:0]$10349 $2\logical_op__rc__ok$next[0:0]$10375 - assign $0\logical_op__rc__rc$next[0:0]$10350 $2\logical_op__rc__rc$next[0:0]$10376 - attribute \src "libresoc.v:177968.5-177968.29" - switch \initial - attribute \src "libresoc.v:177968.9-177968.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$10358 $1\logical_op__data_len$next[3:0]$10353 $1\logical_op__is_signed$next[0:0]$10363 $1\logical_op__is_32bit$next[0:0]$10362 $1\logical_op__output_carry$next[0:0]$10366 $1\logical_op__write_cr0$next[0:0]$10369 $1\logical_op__invert_out$next[0:0]$10361 $1\logical_op__input_carry$next[1:0]$10357 $1\logical_op__zero_a$next[0:0]$10370 $1\logical_op__invert_in$next[0:0]$10360 $1\logical_op__oe__ok$next[0:0]$10365 $1\logical_op__oe__oe$next[0:0]$10364 $1\logical_op__rc__ok$next[0:0]$10367 $1\logical_op__rc__rc$next[0:0]$10368 $1\logical_op__imm_data__ok$next[0:0]$10356 $1\logical_op__imm_data__data$next[63:0]$10355 $1\logical_op__fn_unit$next[12:0]$10354 $1\logical_op__insn_type$next[6:0]$10359 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$10358 $1\logical_op__data_len$next[3:0]$10353 $1\logical_op__is_signed$next[0:0]$10363 $1\logical_op__is_32bit$next[0:0]$10362 $1\logical_op__output_carry$next[0:0]$10366 $1\logical_op__write_cr0$next[0:0]$10369 $1\logical_op__invert_out$next[0:0]$10361 $1\logical_op__input_carry$next[1:0]$10357 $1\logical_op__zero_a$next[0:0]$10370 $1\logical_op__invert_in$next[0:0]$10360 $1\logical_op__oe__ok$next[0:0]$10365 $1\logical_op__oe__oe$next[0:0]$10364 $1\logical_op__rc__ok$next[0:0]$10367 $1\logical_op__rc__rc$next[0:0]$10368 $1\logical_op__imm_data__ok$next[0:0]$10356 $1\logical_op__imm_data__data$next[63:0]$10355 $1\logical_op__fn_unit$next[12:0]$10354 $1\logical_op__insn_type$next[6:0]$10359 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } - case - assign $1\logical_op__data_len$next[3:0]$10353 \logical_op__data_len - assign $1\logical_op__fn_unit$next[12:0]$10354 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$10355 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$10356 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$10357 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$10358 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$10359 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$10360 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$10361 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$10362 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$10363 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$10364 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$10365 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$10366 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$10367 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$10368 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$10369 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$10370 \logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$10371 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$10372 1'0 - assign $2\logical_op__rc__rc$next[0:0]$10376 1'0 - assign $2\logical_op__rc__ok$next[0:0]$10375 1'0 - assign $2\logical_op__oe__oe$next[0:0]$10373 1'0 - assign $2\logical_op__oe__ok$next[0:0]$10374 1'0 - case - assign $2\logical_op__imm_data__data$next[63:0]$10371 $1\logical_op__imm_data__data$next[63:0]$10355 - assign $2\logical_op__imm_data__ok$next[0:0]$10372 $1\logical_op__imm_data__ok$next[0:0]$10356 - assign $2\logical_op__oe__oe$next[0:0]$10373 $1\logical_op__oe__oe$next[0:0]$10364 - assign $2\logical_op__oe__ok$next[0:0]$10374 $1\logical_op__oe__ok$next[0:0]$10365 - assign $2\logical_op__rc__ok$next[0:0]$10375 $1\logical_op__rc__ok$next[0:0]$10367 - assign $2\logical_op__rc__rc$next[0:0]$10376 $1\logical_op__rc__rc$next[0:0]$10368 - end + assign $0\initial[0:0] 1'0 sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10335 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$10336 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10337 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10338 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10339 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10340 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10341 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10342 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10343 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10344 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10345 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10346 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10347 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10348 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10349 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10350 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10351 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10352 + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:178009.3-178021.6" - process $proc$libresoc.v:178009$10377 - assign { } { } + attribute \src "libresoc.v:169858.13-169858.24" + process $proc$libresoc.v:169858$9956 assign { } { } - assign $0\ra$next[63:0]$10378 $1\ra$next[63:0]$10379 - attribute \src "libresoc.v:178010.5-178010.29" - switch \initial - attribute \src "libresoc.v:178010.9-178010.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ra$next[63:0]$10379 \ra$87 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ra$next[63:0]$10379 \ra$87 - case - assign $1\ra$next[63:0]$10379 \ra - end + assign $1\cr_a[3:0] 4'0000 sync always - update \ra$next $0\ra$next[63:0]$10378 + sync init + update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:178022.3-178034.6" - process $proc$libresoc.v:178022$10380 - assign { } { } + attribute \src "libresoc.v:169867.7-169867.21" + process $proc$libresoc.v:169867$9957 assign { } { } - assign $0\rb$next[63:0]$10381 $1\rb$next[63:0]$10382 - attribute \src "libresoc.v:178023.5-178023.29" - switch \initial - attribute \src "libresoc.v:178023.9-178023.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\rb$next[63:0]$10382 \rb$89 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\rb$next[63:0]$10382 \rb$89 - case - assign $1\rb$next[63:0]$10382 \rb - end + assign $1\cr_a_ok[0:0] 1'0 sync always - update \rb$next $0\rb$next[63:0]$10381 + sync init + update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:178035.3-178047.6" - process $proc$libresoc.v:178035$10383 - assign { } { } + attribute \src "libresoc.v:169890.13-169890.45" + process $proc$libresoc.v:169890$9958 assign { } { } - assign $0\xer_so$next[0:0]$10384 $1\xer_so$next[0:0]$10385 - attribute \src "libresoc.v:178036.5-178036.29" - switch \initial - attribute \src "libresoc.v:178036.9-178036.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\xer_so$next[0:0]$10385 \xer_so$91 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\xer_so$next[0:0]$10385 \xer_so$91 - case - assign $1\xer_so$next[0:0]$10385 \xer_so - end + assign $0\logical_op__data_len$18[3:0]$9959 4'0000 sync always - update \xer_so$next $0\xer_so$next[0:0]$10384 - end - connect \$66 $and$libresoc.v:177663$10271_Y - connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \operation$99 \setup_stage_operation - connect \divisor_radicand$98 \setup_stage_divisor_radicand - connect \dividend$97 \setup_stage_dividend - connect \div_by_zero$96 \setup_stage_div_by_zero - connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 - connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 - connect \dividend_neg$93 \setup_stage_dividend_neg - connect \divisor_neg$92 \setup_stage_divisor_neg - connect \xer_so$91 \setup_stage_xer_so$64 - connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 - connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } - connect \muxid$68 \setup_stage_muxid$45 - connect \p_valid_i_p_ready_o \$66 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$65 \p_valid_i - connect \setup_stage_xer_so \input_xer_so$44 - connect \setup_stage_rb \input_rb$43 - connect \setup_stage_ra \input_ra$42 - connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } - connect \setup_stage_muxid \input_muxid$23 - connect \input_xer_so \xer_so$22 - connect \input_rb \rb$21 - connect \input_ra \ra$20 - connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "libresoc.v:178082.1-178126.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.pll" -attribute \generator "nMigen" -module \pll - attribute \src "libresoc.v:178083.7-178083.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:178115.3-178124.6" - wire $0\pll_18_o[0:0] - attribute \src "libresoc.v:178105.3-178114.6" - wire $0\pll_lck_o[0:0] - attribute \src "libresoc.v:178115.3-178124.6" - wire $1\pll_18_o[0:0] - attribute \src "libresoc.v:178105.3-178114.6" - wire $1\pll_lck_o[0:0] - attribute \src "libresoc.v:178102.17-178102.105" - wire $eq$libresoc.v:178102$10418_Y - attribute \src "libresoc.v:178103.17-178103.105" - wire $eq$libresoc.v:178103$10419_Y - attribute \src "libresoc.v:178104.17-178104.98" - wire $not$libresoc.v:178104$10420_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" - wire input 1 \clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" - wire output 5 \clk_pll_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 3 \clk_sel_i - attribute \src "libresoc.v:178083.7-178083.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" - wire output 2 \pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 4 \pll_lck_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:178102$10418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \clk_sel_i - connect \B 2'00 - connect \Y $eq$libresoc.v:178102$10418_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:178103$10419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \clk_sel_i - connect \B 2'00 - connect \Y $eq$libresoc.v:178103$10419_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - cell $not $not$libresoc.v:178104$10420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk_24_i - connect \Y $not$libresoc.v:178104$10420_Y + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9959 end - attribute \src "libresoc.v:178083.7-178083.20" - process $proc$libresoc.v:178083$10423 + attribute \src "libresoc.v:169927.14-169927.48" + process $proc$libresoc.v:169927$9960 assign { } { } - assign $0\initial[0:0] 1'0 + assign $0\logical_op__fn_unit$3[12:0]$9961 13'0000000000000 sync always - update \initial $0\initial[0:0] sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9961 end - attribute \src "libresoc.v:178105.3-178114.6" - process $proc$libresoc.v:178105$10421 + attribute \src "libresoc.v:169950.14-169950.67" + process $proc$libresoc.v:169950$9962 assign { } { } - assign { } { } - assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] - attribute \src "libresoc.v:178106.5-178106.29" - switch \initial - attribute \src "libresoc.v:178106.9-178106.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pll_lck_o[0:0] \clk_24_i - case - assign $1\pll_lck_o[0:0] 1'0 - end + assign $0\logical_op__imm_data__data$4[63:0]$9963 64'0000000000000000000000000000000000000000000000000000000000000000 sync always - update \pll_lck_o $0\pll_lck_o[0:0] + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9963 end - attribute \src "libresoc.v:178115.3-178124.6" - process $proc$libresoc.v:178115$10422 - assign { } { } + attribute \src "libresoc.v:169959.7-169959.42" + process $proc$libresoc.v:169959$9964 assign { } { } - assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] - attribute \src "libresoc.v:178116.5-178116.29" - switch \initial - attribute \src "libresoc.v:178116.9-178116.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\pll_18_o[0:0] \$5 - case - assign $1\pll_18_o[0:0] 1'0 - end + assign $0\logical_op__imm_data__ok$5[0:0]$9965 1'0 sync always - update \pll_18_o $0\pll_18_o[0:0] - end - connect \$1 $eq$libresoc.v:178102$10418_Y - connect \$3 $eq$libresoc.v:178103$10419_Y - connect \$5 $not$libresoc.v:178104$10420_Y - connect \clk_pll_o \clk_24_i -end -attribute \src "libresoc.v:178130.1-178772.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" -attribute \generator "nMigen" -module \popcount - attribute \src "libresoc.v:178131.7-178131.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:178619.3-178645.6" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:178619.3-178645.6" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:178543.19-178543.132" - wire width 4 $add$libresoc.v:178543$10424_Y - attribute \src "libresoc.v:178544.19-178544.132" - wire width 4 $add$libresoc.v:178544$10425_Y - attribute \src "libresoc.v:178545.19-178545.132" - wire width 4 $add$libresoc.v:178545$10426_Y - attribute \src "libresoc.v:178546.19-178546.132" - wire width 4 $add$libresoc.v:178546$10427_Y - attribute \src "libresoc.v:178547.19-178547.134" - wire width 4 $add$libresoc.v:178547$10428_Y - attribute \src "libresoc.v:178548.19-178548.134" - wire width 4 $add$libresoc.v:178548$10429_Y - attribute \src "libresoc.v:178549.18-178549.125" - wire width 3 $add$libresoc.v:178549$10430_Y - attribute \src "libresoc.v:178550.19-178550.134" - wire width 4 $add$libresoc.v:178550$10431_Y - attribute \src "libresoc.v:178551.19-178551.134" - wire width 4 $add$libresoc.v:178551$10432_Y - attribute \src "libresoc.v:178552.19-178552.134" - wire width 4 $add$libresoc.v:178552$10433_Y - attribute \src "libresoc.v:178553.19-178553.134" - wire width 4 $add$libresoc.v:178553$10434_Y - attribute \src "libresoc.v:178554.19-178554.134" - wire width 4 $add$libresoc.v:178554$10435_Y - attribute \src "libresoc.v:178555.19-178555.134" - wire width 4 $add$libresoc.v:178555$10436_Y - attribute \src "libresoc.v:178556.19-178556.134" - wire width 4 $add$libresoc.v:178556$10437_Y - attribute \src "libresoc.v:178557.19-178557.134" - wire width 4 $add$libresoc.v:178557$10438_Y - attribute \src "libresoc.v:178558.19-178558.134" - wire width 4 $add$libresoc.v:178558$10439_Y - attribute \src "libresoc.v:178559.19-178559.132" - wire width 5 $add$libresoc.v:178559$10440_Y - attribute \src "libresoc.v:178560.18-178560.125" - wire width 3 $add$libresoc.v:178560$10441_Y - attribute \src "libresoc.v:178561.19-178561.132" - wire width 5 $add$libresoc.v:178561$10442_Y - attribute \src "libresoc.v:178562.19-178562.132" - wire width 5 $add$libresoc.v:178562$10443_Y - attribute \src "libresoc.v:178563.19-178563.132" - wire width 5 $add$libresoc.v:178563$10444_Y - attribute \src "libresoc.v:178564.19-178564.132" - wire width 5 $add$libresoc.v:178564$10445_Y - attribute \src "libresoc.v:178565.19-178565.134" - wire width 5 $add$libresoc.v:178565$10446_Y - attribute \src "libresoc.v:178566.19-178566.134" - wire width 5 $add$libresoc.v:178566$10447_Y - attribute \src "libresoc.v:178567.19-178567.134" - wire width 5 $add$libresoc.v:178567$10448_Y - attribute \src "libresoc.v:178568.19-178568.132" - wire width 6 $add$libresoc.v:178568$10449_Y - attribute \src "libresoc.v:178569.19-178569.132" - wire width 6 $add$libresoc.v:178569$10450_Y - attribute \src "libresoc.v:178570.19-178570.132" - wire width 6 $add$libresoc.v:178570$10451_Y - attribute \src "libresoc.v:178571.18-178571.127" - wire width 3 $add$libresoc.v:178571$10452_Y - attribute \src "libresoc.v:178572.19-178572.132" - wire width 6 $add$libresoc.v:178572$10453_Y - attribute \src "libresoc.v:178573.19-178573.132" - wire width 7 $add$libresoc.v:178573$10454_Y - attribute \src "libresoc.v:178574.19-178574.132" - wire width 7 $add$libresoc.v:178574$10455_Y - attribute \src "libresoc.v:178575.19-178575.132" - wire width 8 $add$libresoc.v:178575$10456_Y - attribute \src "libresoc.v:178586.18-178586.127" - wire width 3 $add$libresoc.v:178586$10475_Y - attribute \src "libresoc.v:178590.18-178590.127" - wire width 3 $add$libresoc.v:178590$10482_Y - attribute \src "libresoc.v:178591.18-178591.127" - wire width 3 $add$libresoc.v:178591$10483_Y - attribute \src "libresoc.v:178592.17-178592.124" - wire width 3 $add$libresoc.v:178592$10484_Y - attribute \src "libresoc.v:178593.18-178593.127" - wire width 3 $add$libresoc.v:178593$10485_Y - attribute \src "libresoc.v:178594.18-178594.127" - wire width 3 $add$libresoc.v:178594$10486_Y - attribute \src "libresoc.v:178595.18-178595.127" - wire width 3 $add$libresoc.v:178595$10487_Y - attribute \src "libresoc.v:178596.18-178596.127" - wire width 3 $add$libresoc.v:178596$10488_Y - attribute \src "libresoc.v:178597.18-178597.127" - wire width 3 $add$libresoc.v:178597$10489_Y - attribute \src "libresoc.v:178598.18-178598.127" - wire width 3 $add$libresoc.v:178598$10490_Y - attribute \src "libresoc.v:178599.18-178599.127" - wire width 3 $add$libresoc.v:178599$10491_Y - attribute \src "libresoc.v:178600.18-178600.127" - wire width 3 $add$libresoc.v:178600$10492_Y - attribute \src "libresoc.v:178601.18-178601.127" - wire width 3 $add$libresoc.v:178601$10493_Y - attribute \src "libresoc.v:178602.18-178602.127" - wire width 3 $add$libresoc.v:178602$10494_Y - attribute \src "libresoc.v:178603.17-178603.124" - wire width 3 $add$libresoc.v:178603$10495_Y - attribute \src "libresoc.v:178604.18-178604.127" - wire width 3 $add$libresoc.v:178604$10496_Y - attribute \src "libresoc.v:178605.18-178605.127" - wire width 3 $add$libresoc.v:178605$10497_Y - attribute \src "libresoc.v:178606.18-178606.127" - wire width 3 $add$libresoc.v:178606$10498_Y - attribute \src "libresoc.v:178607.18-178607.127" - wire width 3 $add$libresoc.v:178607$10499_Y - attribute \src "libresoc.v:178608.18-178608.127" - wire width 3 $add$libresoc.v:178608$10500_Y - attribute \src "libresoc.v:178609.18-178609.127" - wire width 3 $add$libresoc.v:178609$10501_Y - attribute \src "libresoc.v:178610.18-178610.127" - wire width 3 $add$libresoc.v:178610$10502_Y - attribute \src "libresoc.v:178611.18-178611.127" - wire width 3 $add$libresoc.v:178611$10503_Y - attribute \src "libresoc.v:178612.18-178612.127" - wire width 3 $add$libresoc.v:178612$10504_Y - attribute \src "libresoc.v:178613.18-178613.127" - wire width 3 $add$libresoc.v:178613$10505_Y - attribute \src "libresoc.v:178614.17-178614.124" - wire width 3 $add$libresoc.v:178614$10506_Y - attribute \src "libresoc.v:178615.18-178615.127" - wire width 3 $add$libresoc.v:178615$10507_Y - attribute \src "libresoc.v:178616.18-178616.127" - wire width 3 $add$libresoc.v:178616$10508_Y - attribute \src "libresoc.v:178617.18-178617.127" - wire width 3 $add$libresoc.v:178617$10509_Y - attribute \src "libresoc.v:178618.18-178618.131" - wire width 4 $add$libresoc.v:178618$10510_Y - attribute \src "libresoc.v:178576.19-178576.111" - wire $eq$libresoc.v:178576$10457_Y - attribute \src "libresoc.v:178577.19-178577.111" - wire $eq$libresoc.v:178577$10458_Y - attribute \src "libresoc.v:178578.19-178578.104" - wire width 8 $extend$libresoc.v:178578$10459_Y - attribute \src "libresoc.v:178579.19-178579.104" - wire width 8 $extend$libresoc.v:178579$10461_Y - attribute \src "libresoc.v:178580.19-178580.104" - wire width 8 $extend$libresoc.v:178580$10463_Y - attribute \src "libresoc.v:178581.19-178581.104" - wire width 8 $extend$libresoc.v:178581$10465_Y - attribute \src "libresoc.v:178582.19-178582.104" - wire width 8 $extend$libresoc.v:178582$10467_Y - attribute \src "libresoc.v:178583.19-178583.104" - wire width 8 $extend$libresoc.v:178583$10469_Y - attribute \src "libresoc.v:178584.19-178584.104" - wire width 8 $extend$libresoc.v:178584$10471_Y - attribute \src "libresoc.v:178585.19-178585.104" - wire width 8 $extend$libresoc.v:178585$10473_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 7 \pop_7_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178543$10424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_2 } - connect \B { 2'00 \pop_2_3 } - connect \Y $add$libresoc.v:178543$10424_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178544$10425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_4 } - connect \B { 2'00 \pop_2_5 } - connect \Y $add$libresoc.v:178544$10425_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178545$10426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_6 } - connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:178545$10426_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178546$10427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_8 } - connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:178546$10427_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178547$10428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_10 } - connect \B { 2'00 \pop_2_11 } - connect \Y $add$libresoc.v:178547$10428_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178548$10429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_12 } - connect \B { 2'00 \pop_2_13 } - connect \Y $add$libresoc.v:178548$10429_Y + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9965 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178549$10430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [6] } - connect \B { 2'00 \a [7] } - connect \Y $add$libresoc.v:178549$10430_Y + attribute \src "libresoc.v:169976.13-169976.48" + process $proc$libresoc.v:169976$9966 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9967 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9967 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178550$10431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_14 } - connect \B { 2'00 \pop_2_15 } - connect \Y $add$libresoc.v:178550$10431_Y + attribute \src "libresoc.v:169989.14-169989.43" + process $proc$libresoc.v:169989$9968 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9969 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9969 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178551$10432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_16 } - connect \B { 2'00 \pop_2_17 } - connect \Y $add$libresoc.v:178551$10432_Y + attribute \src "libresoc.v:170146.13-170146.46" + process $proc$libresoc.v:170146$9970 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9971 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9971 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178552$10433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_18 } - connect \B { 2'00 \pop_2_19 } - connect \Y $add$libresoc.v:178552$10433_Y + attribute \src "libresoc.v:170229.7-170229.40" + process $proc$libresoc.v:170229$9972 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9973 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9973 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178553$10434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_20 } - connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:178553$10434_Y + attribute \src "libresoc.v:170238.7-170238.41" + process $proc$libresoc.v:170238$9974 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9975 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9975 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178554$10435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_22 } - connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:178554$10435_Y + attribute \src "libresoc.v:170247.7-170247.39" + process $proc$libresoc.v:170247$9976 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9977 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9977 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178555$10436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_24 } - connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:178555$10436_Y + attribute \src "libresoc.v:170256.7-170256.40" + process $proc$libresoc.v:170256$9978 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9979 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9979 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178556$10437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_26 } - connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:178556$10437_Y + attribute \src "libresoc.v:170265.7-170265.36" + process $proc$libresoc.v:170265$9980 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9981 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9981 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178557$10438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_28 } - connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:178557$10438_Y + attribute \src "libresoc.v:170276.7-170276.36" + process $proc$libresoc.v:170276$9982 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9983 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9983 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178558$10439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_30 } - connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:178558$10439_Y + attribute \src "libresoc.v:170283.7-170283.43" + process $proc$libresoc.v:170283$9984 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9985 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9985 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178559$10440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_0 } - connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:178559$10440_Y + attribute \src "libresoc.v:170292.7-170292.36" + process $proc$libresoc.v:170292$9986 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9987 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9987 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178560$10441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [8] } - connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:178560$10441_Y + attribute \src "libresoc.v:170301.7-170301.36" + process $proc$libresoc.v:170301$9988 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9989 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9989 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178561$10442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_2 } - connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:178561$10442_Y + attribute \src "libresoc.v:170310.7-170310.40" + process $proc$libresoc.v:170310$9990 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9991 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9991 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178562$10443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_4 } - connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:178562$10443_Y + attribute \src "libresoc.v:170319.7-170319.37" + process $proc$libresoc.v:170319$9992 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$9993 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9993 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178563$10444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_6 } - connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:178563$10444_Y + attribute \src "libresoc.v:170328.13-170328.29" + process $proc$libresoc.v:170328$9994 + assign { } { } + assign $0\muxid$1[1:0]$9995 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9995 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178564$10445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_8 } - connect \B { 2'00 \pop_3_9 } - connect \Y $add$libresoc.v:178564$10445_Y + attribute \src "libresoc.v:170341.14-170341.38" + process $proc$libresoc.v:170341$9996 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178565$10446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_10 } - connect \B { 2'00 \pop_3_11 } - connect \Y $add$libresoc.v:178565$10446_Y + attribute \src "libresoc.v:170348.7-170348.18" + process $proc$libresoc.v:170348$9997 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178566$10447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_12 } - connect \B { 2'00 \pop_3_13 } - connect \Y $add$libresoc.v:178566$10447_Y + attribute \src "libresoc.v:170936.7-170936.20" + process $proc$libresoc.v:170936$9998 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178567$10448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_14 } - connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:178567$10448_Y + attribute \src "libresoc.v:170951.13-170951.26" + process $proc$libresoc.v:170951$9999 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178568$10449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_0 } - connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:178568$10449_Y + attribute \src "libresoc.v:170958.7-170958.23" + process $proc$libresoc.v:170958$10000 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178569$10450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_2 } - connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:178569$10450_Y + attribute \src "libresoc.v:170971.7-170971.25" + process $proc$libresoc.v:170971$10001 + assign { } { } + assign $0\xer_so$20[0:0]$10002 1'0 + sync always + sync init + update \xer_so$20 $0\xer_so$20[0:0]$10002 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178570$10451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_4 } - connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:178570$10451_Y + attribute \src "libresoc.v:170976.7-170976.23" + process $proc$libresoc.v:170976$10003 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178571$10452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [10] } - connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:178571$10452_Y + attribute \src "libresoc.v:170986.3-170987.37" + process $proc$libresoc.v:170986$9833 + assign { } { } + assign $0\xer_so$20[0:0]$9834 \xer_so$20$next + sync posedge \coresync_clk + update \xer_so$20 $0\xer_so$20[0:0]$9834 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178572$10453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_6 } - connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:178572$10453_Y + attribute \src "libresoc.v:170988.3-170989.35" + process $proc$libresoc.v:170988$9835 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178573$10454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { 2'00 \pop_5_0 } - connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:178573$10454_Y + attribute \src "libresoc.v:170990.3-170991.29" + process $proc$libresoc.v:170990$9836 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178574$10455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { 2'00 \pop_5_2 } - connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:178574$10455_Y + attribute \src "libresoc.v:170992.3-170993.35" + process $proc$libresoc.v:170992$9837 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178575$10456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { 2'00 \pop_6_0 } - connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:178575$10456_Y + attribute \src "libresoc.v:170994.3-170995.25" + process $proc$libresoc.v:170994$9838 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178586$10475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [12] } - connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:178586$10475_Y + attribute \src "libresoc.v:170996.3-170997.31" + process $proc$libresoc.v:170996$9839 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178590$10482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [14] } - connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:178590$10482_Y + attribute \src "libresoc.v:170998.3-170999.19" + process $proc$libresoc.v:170998$9840 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178591$10483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [16] } - connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:178591$10483_Y + attribute \src "libresoc.v:171000.3-171001.25" + process $proc$libresoc.v:171000$9841 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178592$10484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [0] } - connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:178592$10484_Y + attribute \src "libresoc.v:171002.3-171003.65" + process $proc$libresoc.v:171002$9842 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9843 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9843 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178593$10485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [18] } - connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:178593$10485_Y + attribute \src "libresoc.v:171004.3-171005.61" + process $proc$libresoc.v:171004$9844 + assign { } { } + assign $0\logical_op__fn_unit$3[12:0]$9845 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9845 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178594$10486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [20] } - connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:178594$10486_Y + attribute \src "libresoc.v:171006.3-171007.75" + process $proc$libresoc.v:171006$9846 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$9847 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9847 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178595$10487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [22] } - connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:178595$10487_Y + attribute \src "libresoc.v:171008.3-171009.71" + process $proc$libresoc.v:171008$9848 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$9849 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9849 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178596$10488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [24] } - connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:178596$10488_Y + attribute \src "libresoc.v:171010.3-171011.59" + process $proc$libresoc.v:171010$9850 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9851 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9851 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178597$10489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [26] } - connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:178597$10489_Y + attribute \src "libresoc.v:171012.3-171013.59" + process $proc$libresoc.v:171012$9852 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9853 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9853 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178598$10490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [28] } - connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:178598$10490_Y + attribute \src "libresoc.v:171014.3-171015.59" + process $proc$libresoc.v:171014$9854 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9855 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9855 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178599$10491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [30] } - connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:178599$10491_Y + attribute \src "libresoc.v:171016.3-171017.59" + process $proc$libresoc.v:171016$9856 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9857 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9857 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178600$10492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [32] } - connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:178600$10492_Y + attribute \src "libresoc.v:171018.3-171019.67" + process $proc$libresoc.v:171018$9858 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9859 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9859 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178601$10493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [34] } - connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:178601$10493_Y + attribute \src "libresoc.v:171020.3-171021.61" + process $proc$libresoc.v:171020$9860 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$9861 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9861 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178602$10494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [36] } - connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:178602$10494_Y + attribute \src "libresoc.v:171022.3-171023.71" + process $proc$libresoc.v:171022$9862 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9863 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9863 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178603$10495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [2] } - connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:178603$10495_Y + attribute \src "libresoc.v:171024.3-171025.69" + process $proc$libresoc.v:171024$9864 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9865 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9865 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178604$10496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [38] } - connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:178604$10496_Y + attribute \src "libresoc.v:171026.3-171027.67" + process $proc$libresoc.v:171026$9866 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9867 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9867 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178605$10497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [40] } - connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:178605$10497_Y + attribute \src "libresoc.v:171028.3-171029.73" + process $proc$libresoc.v:171028$9868 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9869 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9869 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178606$10498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [42] } - connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:178606$10498_Y + attribute \src "libresoc.v:171030.3-171031.65" + process $proc$libresoc.v:171030$9870 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9871 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9871 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178607$10499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [44] } - connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:178607$10499_Y + attribute \src "libresoc.v:171032.3-171033.67" + process $proc$libresoc.v:171032$9872 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9873 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9873 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178608$10500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [46] } - connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:178608$10500_Y + attribute \src "libresoc.v:171034.3-171035.65" + process $proc$libresoc.v:171034$9874 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$9875 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9875 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178609$10501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [48] } - connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:178609$10501_Y + attribute \src "libresoc.v:171036.3-171037.57" + process $proc$libresoc.v:171036$9876 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9877 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9877 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178610$10502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [50] } - connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:178610$10502_Y + attribute \src "libresoc.v:171038.3-171039.33" + process $proc$libresoc.v:171038$9878 + assign { } { } + assign $0\muxid$1[1:0]$9879 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9879 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178611$10503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [52] } - connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:178611$10503_Y + attribute \src "libresoc.v:171040.3-171041.29" + process $proc$libresoc.v:171040$9880 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178612$10504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [54] } - connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:178612$10504_Y + attribute \src "libresoc.v:171156.3-171174.6" + process $proc$libresoc.v:171156$9881 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9882 $1\o$next[63:0]$9884 + assign { } { } + assign $0\o_ok$next[0:0]$9883 $2\o_ok$next[0:0]$9886 + attribute \src "libresoc.v:171157.5-171157.29" + switch \initial + attribute \src "libresoc.v:171157.9-171157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9885 $1\o$next[63:0]$9884 } { \o_ok$96 \o$95 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9885 $1\o$next[63:0]$9884 } { \o_ok$96 \o$95 } + case + assign $1\o$next[63:0]$9884 \o + assign $1\o_ok$next[0:0]$9885 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9886 1'0 + case + assign $2\o_ok$next[0:0]$9886 $1\o_ok$next[0:0]$9885 + end + sync always + update \o$next $0\o$next[63:0]$9882 + update \o_ok$next $0\o_ok$next[0:0]$9883 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178613$10505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [56] } - connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:178613$10505_Y + attribute \src "libresoc.v:171175.3-171193.6" + process $proc$libresoc.v:171175$9887 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9888 $1\cr_a$next[3:0]$9890 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9889 $2\cr_a_ok$next[0:0]$9892 + attribute \src "libresoc.v:171176.5-171176.29" + switch \initial + attribute \src "libresoc.v:171176.9-171176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9891 $1\cr_a$next[3:0]$9890 } { \cr_a_ok$98 \cr_a$97 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9891 $1\cr_a$next[3:0]$9890 } { \cr_a_ok$98 \cr_a$97 } + case + assign $1\cr_a$next[3:0]$9890 \cr_a + assign $1\cr_a_ok$next[0:0]$9891 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9892 1'0 + case + assign $2\cr_a_ok$next[0:0]$9892 $1\cr_a_ok$next[0:0]$9891 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9888 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9889 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178614$10506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [4] } - connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:178614$10506_Y + attribute \src "libresoc.v:171194.3-171212.6" + process $proc$libresoc.v:171194$9893 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$9894 $1\xer_ov$next[1:0]$9896 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$9895 $2\xer_ov_ok$next[0:0]$9898 + attribute \src "libresoc.v:171195.5-171195.29" + switch \initial + attribute \src "libresoc.v:171195.9-171195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9897 $1\xer_ov$next[1:0]$9896 } { \xer_ov_ok$100 \xer_ov$99 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9897 $1\xer_ov$next[1:0]$9896 } { \xer_ov_ok$100 \xer_ov$99 } + case + assign $1\xer_ov$next[1:0]$9896 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9897 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$9898 1'0 + case + assign $2\xer_ov_ok$next[0:0]$9898 $1\xer_ov_ok$next[0:0]$9897 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$9894 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9895 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178615$10507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [58] } - connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:178615$10507_Y + attribute \src "libresoc.v:171213.3-171231.6" + process $proc$libresoc.v:171213$9899 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$20$next[0:0]$9901 $1\xer_so$20$next[0:0]$9903 + assign $0\xer_so_ok$next[0:0]$9900 $2\xer_so_ok$next[0:0]$9904 + attribute \src "libresoc.v:171214.5-171214.29" + switch \initial + attribute \src "libresoc.v:171214.9-171214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9902 $1\xer_so$20$next[0:0]$9903 } { \xer_so_ok$102 \xer_so$101 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9902 $1\xer_so$20$next[0:0]$9903 } { \xer_so_ok$102 \xer_so$101 } + case + assign $1\xer_so_ok$next[0:0]$9902 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9903 \xer_so$20 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9904 1'0 + case + assign $2\xer_so_ok$next[0:0]$9904 $1\xer_so_ok$next[0:0]$9902 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9900 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9901 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178616$10508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [60] } - connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:178616$10508_Y + attribute \src "libresoc.v:171232.3-171249.6" + process $proc$libresoc.v:171232$9905 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9906 $2\r_busy$next[0:0]$9908 + attribute \src "libresoc.v:171233.5-171233.29" + switch \initial + attribute \src "libresoc.v:171233.9-171233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9907 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9907 1'0 + case + assign $1\r_busy$next[0:0]$9907 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9908 1'0 + case + assign $2\r_busy$next[0:0]$9908 $1\r_busy$next[0:0]$9907 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9906 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178617$10509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [62] } - connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:178617$10509_Y + attribute \src "libresoc.v:171250.3-171262.6" + process $proc$libresoc.v:171250$9909 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9910 $1\muxid$1$next[1:0]$9911 + attribute \src "libresoc.v:171251.5-171251.29" + switch \initial + attribute \src "libresoc.v:171251.9-171251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9911 \muxid$76 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9911 \muxid$76 + case + assign $1\muxid$1$next[1:0]$9911 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9910 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:178618$10510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_0 } - connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:178618$10510_Y + attribute \src "libresoc.v:171263.3-171304.6" + process $proc$libresoc.v:171263$9912 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$9913 $1\logical_op__data_len$18$next[3:0]$9931 + assign $0\logical_op__fn_unit$3$next[12:0]$9914 $1\logical_op__fn_unit$3$next[12:0]$9932 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$9917 $1\logical_op__input_carry$12$next[1:0]$9935 + assign $0\logical_op__insn$19$next[31:0]$9918 $1\logical_op__insn$19$next[31:0]$9936 + assign $0\logical_op__insn_type$2$next[6:0]$9919 $1\logical_op__insn_type$2$next[6:0]$9937 + assign $0\logical_op__invert_in$10$next[0:0]$9920 $1\logical_op__invert_in$10$next[0:0]$9938 + assign $0\logical_op__invert_out$13$next[0:0]$9921 $1\logical_op__invert_out$13$next[0:0]$9939 + assign $0\logical_op__is_32bit$16$next[0:0]$9922 $1\logical_op__is_32bit$16$next[0:0]$9940 + assign $0\logical_op__is_signed$17$next[0:0]$9923 $1\logical_op__is_signed$17$next[0:0]$9941 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$9926 $1\logical_op__output_carry$15$next[0:0]$9944 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$9929 $1\logical_op__write_cr0$14$next[0:0]$9947 + assign $0\logical_op__zero_a$11$next[0:0]$9930 $1\logical_op__zero_a$11$next[0:0]$9948 + assign $0\logical_op__imm_data__data$4$next[63:0]$9915 $2\logical_op__imm_data__data$4$next[63:0]$9949 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9916 $2\logical_op__imm_data__ok$5$next[0:0]$9950 + assign $0\logical_op__oe__oe$8$next[0:0]$9924 $2\logical_op__oe__oe$8$next[0:0]$9951 + assign $0\logical_op__oe__ok$9$next[0:0]$9925 $2\logical_op__oe__ok$9$next[0:0]$9952 + assign $0\logical_op__rc__ok$7$next[0:0]$9927 $2\logical_op__rc__ok$7$next[0:0]$9953 + assign $0\logical_op__rc__rc$6$next[0:0]$9928 $2\logical_op__rc__rc$6$next[0:0]$9954 + attribute \src "libresoc.v:171264.5-171264.29" + switch \initial + attribute \src "libresoc.v:171264.9-171264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9936 $1\logical_op__data_len$18$next[3:0]$9931 $1\logical_op__is_signed$17$next[0:0]$9941 $1\logical_op__is_32bit$16$next[0:0]$9940 $1\logical_op__output_carry$15$next[0:0]$9944 $1\logical_op__write_cr0$14$next[0:0]$9947 $1\logical_op__invert_out$13$next[0:0]$9939 $1\logical_op__input_carry$12$next[1:0]$9935 $1\logical_op__zero_a$11$next[0:0]$9948 $1\logical_op__invert_in$10$next[0:0]$9938 $1\logical_op__oe__ok$9$next[0:0]$9943 $1\logical_op__oe__oe$8$next[0:0]$9942 $1\logical_op__rc__ok$7$next[0:0]$9945 $1\logical_op__rc__rc$6$next[0:0]$9946 $1\logical_op__imm_data__ok$5$next[0:0]$9934 $1\logical_op__imm_data__data$4$next[63:0]$9933 $1\logical_op__fn_unit$3$next[12:0]$9932 $1\logical_op__insn_type$2$next[6:0]$9937 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9936 $1\logical_op__data_len$18$next[3:0]$9931 $1\logical_op__is_signed$17$next[0:0]$9941 $1\logical_op__is_32bit$16$next[0:0]$9940 $1\logical_op__output_carry$15$next[0:0]$9944 $1\logical_op__write_cr0$14$next[0:0]$9947 $1\logical_op__invert_out$13$next[0:0]$9939 $1\logical_op__input_carry$12$next[1:0]$9935 $1\logical_op__zero_a$11$next[0:0]$9948 $1\logical_op__invert_in$10$next[0:0]$9938 $1\logical_op__oe__ok$9$next[0:0]$9943 $1\logical_op__oe__oe$8$next[0:0]$9942 $1\logical_op__rc__ok$7$next[0:0]$9945 $1\logical_op__rc__rc$6$next[0:0]$9946 $1\logical_op__imm_data__ok$5$next[0:0]$9934 $1\logical_op__imm_data__data$4$next[63:0]$9933 $1\logical_op__fn_unit$3$next[12:0]$9932 $1\logical_op__insn_type$2$next[6:0]$9937 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + case + assign $1\logical_op__data_len$18$next[3:0]$9931 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[12:0]$9932 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9933 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9934 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9935 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9936 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9937 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9938 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9939 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9940 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9941 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9942 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9943 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9944 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9945 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9946 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9947 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9948 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$9949 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9950 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9954 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9953 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9951 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9952 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$9949 $1\logical_op__imm_data__data$4$next[63:0]$9933 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9950 $1\logical_op__imm_data__ok$5$next[0:0]$9934 + assign $2\logical_op__oe__oe$8$next[0:0]$9951 $1\logical_op__oe__oe$8$next[0:0]$9942 + assign $2\logical_op__oe__ok$9$next[0:0]$9952 $1\logical_op__oe__ok$9$next[0:0]$9943 + assign $2\logical_op__rc__ok$7$next[0:0]$9953 $1\logical_op__rc__ok$7$next[0:0]$9945 + assign $2\logical_op__rc__rc$6$next[0:0]$9954 $1\logical_op__rc__rc$6$next[0:0]$9946 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9913 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$9914 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9915 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9916 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9917 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9918 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9919 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9920 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9921 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9922 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9923 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9924 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9925 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9926 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9927 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9928 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9929 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9930 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:178576$10457 + connect \$74 $and$libresoc.v:170985$9832_Y + connect \cr_a$68 4'0000 + connect \cr_a_ok$69 1'0 + connect \xer_so_ok$72 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } + connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } + connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } + connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } + connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } + connect \muxid$76 \output_muxid$41 + connect \p_valid_i_p_ready_o \$74 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$73 \p_valid_i + connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } + connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } + connect { \cr_a_ok$67 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } + connect \output_muxid \output_stage_muxid$21 + connect \output_stage_remainder \remainder + connect \output_stage_quotient_root \quotient_root + connect \output_stage_div_by_zero \div_by_zero + connect \output_stage_dive_abs_ov64 \dive_abs_ov64 + connect \output_stage_dive_abs_ov32 \dive_abs_ov32 + connect \output_stage_dividend_neg \dividend_neg + connect \output_stage_divisor_neg \divisor_neg + connect \output_stage_xer_so \xer_so + connect \rb$66 \rb + connect \ra$65 \ra + connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_stage_muxid \muxid +end +attribute \src "libresoc.v:171341.1-172322.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" +attribute \generator "nMigen" +module \pipe_middle_0 + attribute \src "libresoc.v:172247.3-172261.6" + wire $0\div_by_zero$54$next[0:0]$10183 + attribute \src "libresoc.v:171921.3-171922.47" + wire $0\div_by_zero$54[0:0]$10018 + attribute \src "libresoc.v:171364.7-171364.30" + wire $0\div_by_zero$54[0:0]$10200 + attribute \src "libresoc.v:172043.3-172054.6" + wire width 64 $0\div_state_next_divisor[63:0] + attribute \src "libresoc.v:172031.3-172042.6" + wire width 128 $0\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:172019.3-172030.6" + wire width 7 $0\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:172217.3-172231.6" + wire $0\dive_abs_ov32$52$next[0:0]$10175 + attribute \src "libresoc.v:171925.3-171926.51" + wire $0\dive_abs_ov32$52[0:0]$10022 + attribute \src "libresoc.v:171388.7-171388.32" + wire $0\dive_abs_ov32$52[0:0]$10202 + attribute \src "libresoc.v:172232.3-172246.6" + wire $0\dive_abs_ov64$53$next[0:0]$10179 + attribute \src "libresoc.v:171923.3-171924.51" + wire $0\dive_abs_ov64$53[0:0]$10020 + attribute \src "libresoc.v:171396.7-171396.32" + wire $0\dive_abs_ov64$53[0:0]$10204 + attribute \src "libresoc.v:172262.3-172276.6" + wire width 128 $0\dividend$68$next[127:0]$10187 + attribute \src "libresoc.v:171919.3-171920.41" + wire width 128 $0\dividend$68[127:0]$10016 + attribute \src "libresoc.v:171402.15-171402.68" + wire width 128 $0\dividend$68[127:0]$10206 + attribute \src "libresoc.v:172202.3-172216.6" + wire $0\dividend_neg$51$next[0:0]$10171 + attribute \src "libresoc.v:171927.3-171928.49" + wire $0\dividend_neg$51[0:0]$10024 + attribute \src "libresoc.v:171410.7-171410.31" + wire $0\dividend_neg$51[0:0]$10208 + attribute \src "libresoc.v:172187.3-172201.6" + wire $0\divisor_neg$50$next[0:0]$10167 + attribute \src "libresoc.v:171929.3-171930.47" + wire $0\divisor_neg$50[0:0]$10026 + attribute \src "libresoc.v:171418.7-171418.30" + wire $0\divisor_neg$50[0:0]$10210 + attribute \src "libresoc.v:172277.3-172291.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$10191 + attribute \src "libresoc.v:171917.3-171918.57" + wire width 64 $0\divisor_radicand$65[63:0]$10014 + attribute \src "libresoc.v:171424.14-171424.58" + wire width 64 $0\divisor_radicand$65[63:0]$10212 + attribute \src "libresoc.v:172055.3-172082.6" + wire $0\empty$next[0:0]$10084 + attribute \src "libresoc.v:171975.3-171976.27" + wire $0\empty[0:0] + attribute \src "libresoc.v:171342.7-171342.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172098.3-172141.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$10094 + attribute \src "libresoc.v:171969.3-171970.65" + wire width 4 $0\logical_op__data_len$45[3:0]$10066 + attribute \src "libresoc.v:171436.13-171436.45" + wire width 4 $0\logical_op__data_len$45[3:0]$10215 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 13 $0\logical_op__fn_unit$30$next[12:0]$10095 + attribute \src "libresoc.v:171939.3-171940.63" + wire width 13 $0\logical_op__fn_unit$30[12:0]$10036 + attribute \src "libresoc.v:171486.14-171486.49" + wire width 13 $0\logical_op__fn_unit$30[12:0]$10217 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10096 + attribute \src "libresoc.v:171941.3-171942.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10038 + attribute \src "libresoc.v:171492.14-171492.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10219 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$10097 + attribute \src "libresoc.v:171943.3-171944.73" + wire $0\logical_op__imm_data__ok$32[0:0]$10040 + attribute \src "libresoc.v:171500.7-171500.43" + wire $0\logical_op__imm_data__ok$32[0:0]$10221 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$10098 + attribute \src "libresoc.v:171957.3-171958.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$10054 + attribute \src "libresoc.v:171522.13-171522.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$10223 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$10099 + attribute \src "libresoc.v:171971.3-171972.57" + wire width 32 $0\logical_op__insn$46[31:0]$10068 + attribute \src "libresoc.v:171530.14-171530.43" + wire width 32 $0\logical_op__insn$46[31:0]$10225 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$10100 + attribute \src "libresoc.v:171937.3-171938.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$10034 + attribute \src "libresoc.v:171760.13-171760.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$10227 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__invert_in$37$next[0:0]$10101 + attribute \src "libresoc.v:171953.3-171954.67" + wire $0\logical_op__invert_in$37[0:0]$10050 + attribute \src "libresoc.v:171768.7-171768.40" + wire $0\logical_op__invert_in$37[0:0]$10229 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__invert_out$40$next[0:0]$10102 + attribute \src "libresoc.v:171959.3-171960.69" + wire $0\logical_op__invert_out$40[0:0]$10056 + attribute \src "libresoc.v:171776.7-171776.41" + wire $0\logical_op__invert_out$40[0:0]$10231 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__is_32bit$43$next[0:0]$10103 + attribute \src "libresoc.v:171965.3-171966.65" + wire $0\logical_op__is_32bit$43[0:0]$10062 + attribute \src "libresoc.v:171784.7-171784.39" + wire $0\logical_op__is_32bit$43[0:0]$10233 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__is_signed$44$next[0:0]$10104 + attribute \src "libresoc.v:171967.3-171968.67" + wire $0\logical_op__is_signed$44[0:0]$10064 + attribute \src "libresoc.v:171792.7-171792.40" + wire $0\logical_op__is_signed$44[0:0]$10235 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__oe__oe$35$next[0:0]$10105 + attribute \src "libresoc.v:171949.3-171950.61" + wire $0\logical_op__oe__oe$35[0:0]$10046 + attribute \src "libresoc.v:171798.7-171798.37" + wire $0\logical_op__oe__oe$35[0:0]$10237 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__oe__ok$36$next[0:0]$10106 + attribute \src "libresoc.v:171951.3-171952.61" + wire $0\logical_op__oe__ok$36[0:0]$10048 + attribute \src "libresoc.v:171806.7-171806.37" + wire $0\logical_op__oe__ok$36[0:0]$10239 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__output_carry$42$next[0:0]$10107 + attribute \src "libresoc.v:171963.3-171964.73" + wire $0\logical_op__output_carry$42[0:0]$10060 + attribute \src "libresoc.v:171816.7-171816.43" + wire $0\logical_op__output_carry$42[0:0]$10241 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__rc__ok$34$next[0:0]$10108 + attribute \src "libresoc.v:171947.3-171948.61" + wire $0\logical_op__rc__ok$34[0:0]$10044 + attribute \src "libresoc.v:171822.7-171822.37" + wire $0\logical_op__rc__ok$34[0:0]$10243 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__rc__rc$33$next[0:0]$10109 + attribute \src "libresoc.v:171945.3-171946.61" + wire $0\logical_op__rc__rc$33[0:0]$10042 + attribute \src "libresoc.v:171830.7-171830.37" + wire $0\logical_op__rc__rc$33[0:0]$10245 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__write_cr0$41$next[0:0]$10110 + attribute \src "libresoc.v:171961.3-171962.67" + wire $0\logical_op__write_cr0$41[0:0]$10058 + attribute \src "libresoc.v:171840.7-171840.40" + wire $0\logical_op__write_cr0$41[0:0]$10247 + attribute \src "libresoc.v:172098.3-172141.6" + wire $0\logical_op__zero_a$38$next[0:0]$10111 + attribute \src "libresoc.v:171955.3-171956.61" + wire $0\logical_op__zero_a$38[0:0]$10052 + attribute \src "libresoc.v:171848.7-171848.37" + wire $0\logical_op__zero_a$38[0:0]$10249 + attribute \src "libresoc.v:172083.3-172097.6" + wire width 2 $0\muxid$28$next[1:0]$10090 + attribute \src "libresoc.v:171973.3-171974.35" + wire width 2 $0\muxid$28[1:0]$10070 + attribute \src "libresoc.v:171856.13-171856.30" + wire width 2 $0\muxid$28[1:0]$10251 + attribute \src "libresoc.v:172292.3-172306.6" + wire width 2 $0\operation$69$next[1:0]$10195 + attribute \src "libresoc.v:171915.3-171916.43" + wire width 2 $0\operation$69[1:0]$10012 + attribute \src "libresoc.v:171866.13-171866.34" + wire width 2 $0\operation$69[1:0]$10253 + attribute \src "libresoc.v:172142.3-172156.6" + wire width 64 $0\ra$47$next[63:0]$10155 + attribute \src "libresoc.v:171935.3-171936.29" + wire width 64 $0\ra$47[63:0]$10032 + attribute \src "libresoc.v:171880.14-171880.44" + wire width 64 $0\ra$47[63:0]$10255 + attribute \src "libresoc.v:172157.3-172171.6" + wire width 64 $0\rb$48$next[63:0]$10159 + attribute \src "libresoc.v:171933.3-171934.29" + wire width 64 $0\rb$48[63:0]$10030 + attribute \src "libresoc.v:171888.14-171888.44" + wire width 64 $0\rb$48[63:0]$10257 + attribute \src "libresoc.v:172010.3-172018.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10078 + attribute \src "libresoc.v:171977.3-171978.75" + wire width 128 $0\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:172001.3-172009.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$10075 + attribute \src "libresoc.v:171979.3-171980.65" + wire width 7 $0\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:172172.3-172186.6" + wire $0\xer_so$49$next[0:0]$10163 + attribute \src "libresoc.v:171931.3-171932.37" + wire $0\xer_so$49[0:0]$10028 + attribute \src "libresoc.v:171906.7-171906.25" + wire $0\xer_so$49[0:0]$10261 + attribute \src "libresoc.v:172247.3-172261.6" + wire $1\div_by_zero$54$next[0:0]$10184 + attribute \src "libresoc.v:172043.3-172054.6" + wire width 64 $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:172031.3-172042.6" + wire width 128 $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:172019.3-172030.6" + wire width 7 $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:172217.3-172231.6" + wire $1\dive_abs_ov32$52$next[0:0]$10176 + attribute \src "libresoc.v:172232.3-172246.6" + wire $1\dive_abs_ov64$53$next[0:0]$10180 + attribute \src "libresoc.v:172262.3-172276.6" + wire width 128 $1\dividend$68$next[127:0]$10188 + attribute \src "libresoc.v:172202.3-172216.6" + wire $1\dividend_neg$51$next[0:0]$10172 + attribute \src "libresoc.v:172187.3-172201.6" + wire $1\divisor_neg$50$next[0:0]$10168 + attribute \src "libresoc.v:172277.3-172291.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$10192 + attribute \src "libresoc.v:172055.3-172082.6" + wire $1\empty$next[0:0]$10085 + attribute \src "libresoc.v:171428.7-171428.19" + wire $1\empty[0:0] + attribute \src "libresoc.v:172098.3-172141.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$10112 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 13 $1\logical_op__fn_unit$30$next[12:0]$10113 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10114 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$10115 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$10116 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$10117 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$10118 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__invert_in$37$next[0:0]$10119 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__invert_out$40$next[0:0]$10120 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__is_32bit$43$next[0:0]$10121 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__is_signed$44$next[0:0]$10122 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__oe__oe$35$next[0:0]$10123 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__oe__ok$36$next[0:0]$10124 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__output_carry$42$next[0:0]$10125 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__rc__ok$34$next[0:0]$10126 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__rc__rc$33$next[0:0]$10127 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__write_cr0$41$next[0:0]$10128 + attribute \src "libresoc.v:172098.3-172141.6" + wire $1\logical_op__zero_a$38$next[0:0]$10129 + attribute \src "libresoc.v:172083.3-172097.6" + wire width 2 $1\muxid$28$next[1:0]$10091 + attribute \src "libresoc.v:172292.3-172306.6" + wire width 2 $1\operation$69$next[1:0]$10196 + attribute \src "libresoc.v:172142.3-172156.6" + wire width 64 $1\ra$47$next[63:0]$10156 + attribute \src "libresoc.v:172157.3-172171.6" + wire width 64 $1\rb$48$next[63:0]$10160 + attribute \src "libresoc.v:172010.3-172018.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10079 + attribute \src "libresoc.v:171894.15-171894.84" + wire width 128 $1\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:172001.3-172009.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$10076 + attribute \src "libresoc.v:171898.13-171898.45" + wire width 7 $1\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:172172.3-172186.6" + wire $1\xer_so$49$next[0:0]$10164 + attribute \src "libresoc.v:172247.3-172261.6" + wire $2\div_by_zero$54$next[0:0]$10185 + attribute \src "libresoc.v:172217.3-172231.6" + wire $2\dive_abs_ov32$52$next[0:0]$10177 + attribute \src "libresoc.v:172232.3-172246.6" + wire $2\dive_abs_ov64$53$next[0:0]$10181 + attribute \src "libresoc.v:172262.3-172276.6" + wire width 128 $2\dividend$68$next[127:0]$10189 + attribute \src "libresoc.v:172202.3-172216.6" + wire $2\dividend_neg$51$next[0:0]$10173 + attribute \src "libresoc.v:172187.3-172201.6" + wire $2\divisor_neg$50$next[0:0]$10169 + attribute \src "libresoc.v:172277.3-172291.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$10193 + attribute \src "libresoc.v:172055.3-172082.6" + wire $2\empty$next[0:0]$10086 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$10130 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 13 $2\logical_op__fn_unit$30$next[12:0]$10131 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10132 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$10133 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$10134 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$10135 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$10136 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__invert_in$37$next[0:0]$10137 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__invert_out$40$next[0:0]$10138 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__is_32bit$43$next[0:0]$10139 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__is_signed$44$next[0:0]$10140 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__oe__oe$35$next[0:0]$10141 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__oe__ok$36$next[0:0]$10142 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__output_carry$42$next[0:0]$10143 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__rc__ok$34$next[0:0]$10144 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__rc__rc$33$next[0:0]$10145 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__write_cr0$41$next[0:0]$10146 + attribute \src "libresoc.v:172098.3-172141.6" + wire $2\logical_op__zero_a$38$next[0:0]$10147 + attribute \src "libresoc.v:172083.3-172097.6" + wire width 2 $2\muxid$28$next[1:0]$10092 + attribute \src "libresoc.v:172292.3-172306.6" + wire width 2 $2\operation$69$next[1:0]$10197 + attribute \src "libresoc.v:172142.3-172156.6" + wire width 64 $2\ra$47$next[63:0]$10157 + attribute \src "libresoc.v:172157.3-172171.6" + wire width 64 $2\rb$48$next[63:0]$10161 + attribute \src "libresoc.v:172172.3-172186.6" + wire $2\xer_so$49$next[0:0]$10165 + attribute \src "libresoc.v:172055.3-172082.6" + wire $3\empty$next[0:0]$10087 + attribute \src "libresoc.v:172098.3-172141.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10148 + attribute \src "libresoc.v:172098.3-172141.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$10149 + attribute \src "libresoc.v:172098.3-172141.6" + wire $3\logical_op__oe__oe$35$next[0:0]$10150 + attribute \src "libresoc.v:172098.3-172141.6" + wire $3\logical_op__oe__ok$36$next[0:0]$10151 + attribute \src "libresoc.v:172098.3-172141.6" + wire $3\logical_op__rc__ok$34$next[0:0]$10152 + attribute \src "libresoc.v:172098.3-172141.6" + wire $3\logical_op__rc__rc$33$next[0:0]$10153 + attribute \src "libresoc.v:172055.3-172082.6" + wire $4\empty$next[0:0]$10088 + attribute \src "libresoc.v:171913.18-171913.98" + wire $and$libresoc.v:171913$10009_Y + attribute \src "libresoc.v:171914.18-171914.107" + wire $and$libresoc.v:171914$10010_Y + attribute \src "libresoc.v:171910.18-171910.92" + wire width 192 $extend$libresoc.v:171910$10005_Y + attribute \src "libresoc.v:171912.18-171912.119" + wire $ge$libresoc.v:171912$10008_Y + attribute \src "libresoc.v:171911.18-171911.93" + wire $not$libresoc.v:171911$10007_Y + attribute \src "libresoc.v:171910.18-171910.92" + wire width 192 $pos$libresoc.v:171910$10006_Y + attribute \src "libresoc.v:171909.18-171909.138" + wire width 191 $sshl$libresoc.v:171909$10004_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + wire width 192 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + wire width 191 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 65 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 62 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 \div_state_init_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_init_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_init_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" + wire width 64 \div_state_next_divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_i_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 60 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 61 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 input 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 59 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 58 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 input 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" + wire \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" + wire \empty$next + attribute \src "libresoc.v:171342.7-171342.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$30$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 35 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 34 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 input 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 output 63 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 output 64 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 57 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $and $and$libresoc.v:171913$10009 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_len - connect \B 1'1 - connect \Y $eq$libresoc.v:178576$10457_Y + connect \A \$59 + connect \B \$61 + connect \Y $and$libresoc.v:171913$10009_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:178577$10458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + cell $and $and$libresoc.v:171914$10010 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_len - connect \B 3'100 - connect \Y $eq$libresoc.v:178577$10458_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178578$10459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_0 - connect \Y $extend$libresoc.v:178578$10459_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178579$10461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_1 - connect \Y $extend$libresoc.v:178579$10461_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178580$10463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_2 - connect \Y $extend$libresoc.v:178580$10463_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178581$10465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_3 - connect \Y $extend$libresoc.v:178581$10465_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178582$10467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_4 - connect \Y $extend$libresoc.v:178582$10467_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178583$10469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_5 - connect \Y $extend$libresoc.v:178583$10469_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178584$10471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_6 - connect \Y $extend$libresoc.v:178584$10471_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178585$10473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_7 - connect \Y $extend$libresoc.v:178585$10473_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178587$10476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 32 - connect \A \pop_6_0 - connect \Y $extend$libresoc.v:178587$10476_Y + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:171914$10010_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178588$10478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $extend$libresoc.v:171910$10005 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 32 - connect \A \pop_6_1 - connect \Y $extend$libresoc.v:178588$10478_Y + parameter \A_WIDTH 191 + parameter \Y_WIDTH 192 + connect \A \$56 + connect \Y $extend$libresoc.v:171910$10005_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:178589$10480 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:171912$10008 parameter \A_SIGNED 0 parameter \A_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \pop_7_0 - connect \Y $extend$libresoc.v:178589$10480_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178578$10460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:178578$10459_Y - connect \Y $pos$libresoc.v:178578$10460_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178579$10462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:178579$10461_Y - connect \Y $pos$libresoc.v:178579$10462_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178580$10464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:178580$10463_Y - connect \Y $pos$libresoc.v:178580$10464_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178581$10466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:178581$10465_Y - connect \Y $pos$libresoc.v:178581$10466_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \saved_state_q_bits_known + connect \B 6'111111 + connect \Y $ge$libresoc.v:171912$10008_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178582$10468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $not $not$libresoc.v:171911$10007 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:178582$10467_Y - connect \Y $pos$libresoc.v:178582$10468_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \empty + connect \Y $not$libresoc.v:171911$10007_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178583$10470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $pos$libresoc.v:171910$10006 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:178583$10469_Y - connect \Y $pos$libresoc.v:178583$10470_Y + parameter \A_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $extend$libresoc.v:171910$10005_Y + connect \Y $pos$libresoc.v:171910$10006_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178584$10472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $sshl $sshl$libresoc.v:171909$10004 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:178584$10471_Y - connect \Y $pos$libresoc.v:178584$10472_Y + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \div_state_next_o_dividend_quotient [127:64] + connect \B 7'1000000 + connect \Y $sshl$libresoc.v:171909$10004_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178585$10474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:178585$10473_Y - connect \Y $pos$libresoc.v:178585$10474_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:171981.18-171985.4" + cell \div_state_init \div_state_init + connect \dividend \div_state_init_dividend + connect \o_dividend_quotient \div_state_init_o_dividend_quotient + connect \o_q_bits_known \div_state_init_o_q_bits_known end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178587$10477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:178587$10476_Y - connect \Y $pos$libresoc.v:178587$10477_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:171986.18-171992.4" + cell \div_state_next \div_state_next + connect \divisor \div_state_next_divisor + connect \i_dividend_quotient \div_state_next_i_dividend_quotient + connect \i_q_bits_known \div_state_next_i_q_bits_known + connect \o_dividend_quotient \div_state_next_o_dividend_quotient + connect \o_q_bits_known \div_state_next_o_q_bits_known end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178588$10479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:178588$10478_Y - connect \Y $pos$libresoc.v:178588$10479_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:171993.10-171996.4" + cell \n$80 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:178589$10481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:178589$10480_Y - connect \Y $pos$libresoc.v:178589$10481_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:171997.10-172000.4" + cell \p$79 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:178131.7-178131.20" - process $proc$libresoc.v:178131$10512 + attribute \src "libresoc.v:171342.7-171342.20" + process $proc$libresoc.v:171342$10198 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178619.3-178645.6" - process $proc$libresoc.v:178619$10511 + attribute \src "libresoc.v:171364.7-171364.30" + process $proc$libresoc.v:171364$10199 assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:178620.5-178620.29" - switch \initial - attribute \src "libresoc.v:178620.9-178620.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - switch { \$192 \$190 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\o[63:0] [7:0] \$194 - assign $1\o[63:0] [15:8] \$196 - assign $1\o[63:0] [23:16] \$198 - assign $1\o[63:0] [31:24] \$200 - assign $1\o[63:0] [39:32] \$202 - assign $1\o[63:0] [47:40] \$204 - assign $1\o[63:0] [55:48] \$206 - assign $1\o[63:0] [63:56] \$208 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\o[63:0] [31:0] \$210 - assign $1\o[63:0] [63:32] \$212 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\o[63:0] \$214 - end + assign $0\div_by_zero$54[0:0]$10200 1'0 sync always - update \o $0\o[63:0] - end - connect \$101 $add$libresoc.v:178543$10424_Y - connect \$104 $add$libresoc.v:178544$10425_Y - connect \$107 $add$libresoc.v:178545$10426_Y - connect \$110 $add$libresoc.v:178546$10427_Y - connect \$113 $add$libresoc.v:178547$10428_Y - connect \$116 $add$libresoc.v:178548$10429_Y - connect \$11 $add$libresoc.v:178549$10430_Y - connect \$119 $add$libresoc.v:178550$10431_Y - connect \$122 $add$libresoc.v:178551$10432_Y - connect \$125 $add$libresoc.v:178552$10433_Y - connect \$128 $add$libresoc.v:178553$10434_Y - connect \$131 $add$libresoc.v:178554$10435_Y - connect \$134 $add$libresoc.v:178555$10436_Y - connect \$137 $add$libresoc.v:178556$10437_Y - connect \$140 $add$libresoc.v:178557$10438_Y - connect \$143 $add$libresoc.v:178558$10439_Y - connect \$146 $add$libresoc.v:178559$10440_Y - connect \$14 $add$libresoc.v:178560$10441_Y - connect \$149 $add$libresoc.v:178561$10442_Y - connect \$152 $add$libresoc.v:178562$10443_Y - connect \$155 $add$libresoc.v:178563$10444_Y - connect \$158 $add$libresoc.v:178564$10445_Y - connect \$161 $add$libresoc.v:178565$10446_Y - connect \$164 $add$libresoc.v:178566$10447_Y - connect \$167 $add$libresoc.v:178567$10448_Y - connect \$170 $add$libresoc.v:178568$10449_Y - connect \$173 $add$libresoc.v:178569$10450_Y - connect \$176 $add$libresoc.v:178570$10451_Y - connect \$17 $add$libresoc.v:178571$10452_Y - connect \$179 $add$libresoc.v:178572$10453_Y - connect \$182 $add$libresoc.v:178573$10454_Y - connect \$185 $add$libresoc.v:178574$10455_Y - connect \$188 $add$libresoc.v:178575$10456_Y - connect \$190 $eq$libresoc.v:178576$10457_Y - connect \$192 $eq$libresoc.v:178577$10458_Y - connect \$194 $pos$libresoc.v:178578$10460_Y - connect \$196 $pos$libresoc.v:178579$10462_Y - connect \$198 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\$29 - connect \$31 \$32 - connect \$34 \$35 - connect \$37 \$38 - connect \$40 \$41 - connect \$43 \$44 - connect \$46 \$47 - connect \$49 \$50 - connect \$52 \$53 - connect \$55 \$56 - connect \$58 \$59 - connect \$61 \$62 - connect \$64 \$65 - connect \$67 \$68 - connect \$70 \$71 - connect \$73 \$74 - connect \$76 \$77 - connect \$79 \$80 - connect \$82 \$83 - connect \$85 \$86 - connect \$88 \$89 - connect \$91 \$92 - connect \$94 \$95 - connect \$97 \$98 - connect \$100 \$101 - connect \$103 \$104 - connect \$106 \$107 - connect \$109 \$110 - connect \$112 \$113 - connect \$115 \$116 - connect \$118 \$119 - connect \$121 \$122 - connect \$124 \$125 - connect \$127 \$128 - connect \$130 \$131 - connect \$133 \$134 - connect \$136 \$137 - connect \$139 \$140 - connect \$142 \$143 - connect \$145 \$146 - connect \$148 \$149 - connect \$151 \$152 - connect \$154 \$155 - connect \$157 \$158 - connect \$160 \$161 - connect \$163 \$164 - connect \$166 \$167 - connect \$169 \$170 - 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[2:0] - connect \pop_3_2 \$104 [2:0] - connect \pop_3_1 \$101 [2:0] - connect \pop_3_0 \$98 [2:0] - connect \pop_2_31 \$95 [1:0] - connect \pop_2_30 \$92 [1:0] - connect \pop_2_29 \$89 [1:0] - connect \pop_2_28 \$86 [1:0] - connect \pop_2_27 \$83 [1:0] - connect \pop_2_26 \$80 [1:0] - connect \pop_2_25 \$77 [1:0] - connect \pop_2_24 \$74 [1:0] - connect \pop_2_23 \$71 [1:0] - connect \pop_2_22 \$68 [1:0] - connect \pop_2_21 \$65 [1:0] - connect \pop_2_20 \$62 [1:0] - connect \pop_2_19 \$59 [1:0] - connect \pop_2_18 \$56 [1:0] - connect \pop_2_17 \$53 [1:0] - connect \pop_2_16 \$50 [1:0] - connect \pop_2_15 \$47 [1:0] - connect \pop_2_14 \$44 [1:0] - connect \pop_2_13 \$41 [1:0] - connect \pop_2_12 \$38 [1:0] - connect \pop_2_11 \$35 [1:0] - connect \pop_2_10 \$32 [1:0] - connect \pop_2_9 \$29 [1:0] - connect \pop_2_8 \$26 [1:0] - connect \pop_2_7 \$23 [1:0] - connect \pop_2_6 \$20 [1:0] - connect \pop_2_5 \$17 [1:0] - connect \pop_2_4 \$14 [1:0] - connect \pop_2_3 \$11 [1:0] - connect \pop_2_2 \$8 [1:0] - connect \pop_2_1 \$5 [1:0] - connect \pop_2_0 \$2 [1:0] -end -attribute \src "libresoc.v:178776.1-178860.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick - attribute \src "libresoc.v:178833.17-178833.91" - wire $not$libresoc.v:178833$10513_Y - attribute \src "libresoc.v:178835.18-178835.93" - wire $not$libresoc.v:178835$10515_Y - attribute \src "libresoc.v:178837.18-178837.93" - wire $not$libresoc.v:178837$10517_Y - attribute \src "libresoc.v:178838.17-178838.138" - wire width 8 $not$libresoc.v:178838$10518_Y - attribute \src "libresoc.v:178840.18-178840.93" - wire $not$libresoc.v:178840$10520_Y - attribute \src "libresoc.v:178842.18-178842.93" - wire $not$libresoc.v:178842$10522_Y - attribute \src "libresoc.v:178844.18-178844.93" - wire $not$libresoc.v:178844$10524_Y - attribute \src "libresoc.v:178847.17-178847.91" - wire $not$libresoc.v:178847$10527_Y - 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178833$10513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:178833$10513_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178835$10515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:178835$10515_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178837$10517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:178837$10517_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:178838$10518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:178838$10518_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178840$10520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:178840$10520_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178842$10522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:178842$10522_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178844$10524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:178844$10524_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178847$10527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:178847$10527_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178834$10514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:178834$10514_Y + sync init + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10200 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178836$10516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:178836$10516_Y + attribute \src "libresoc.v:171388.7-171388.32" + process $proc$libresoc.v:171388$10201 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$10202 1'0 + sync always + sync init + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10202 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178839$10519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:178839$10519_Y + attribute \src "libresoc.v:171396.7-171396.32" + process $proc$libresoc.v:171396$10203 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$10204 1'0 + sync always + sync init + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10204 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178841$10521 - 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$0\dividend_neg$51[0:0]$10208 1'0 + sync always + sync init + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10208 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:178845$10525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:178845$10525_Y + attribute \src "libresoc.v:171418.7-171418.30" + process $proc$libresoc.v:171418$10209 + assign { } { } + assign $0\divisor_neg$50[0:0]$10210 1'0 + sync always + sync init + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10210 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178846$10526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:178846$10526_Y + attribute \src "libresoc.v:171424.14-171424.58" + process $proc$libresoc.v:171424$10211 + assign { } { } + assign $0\divisor_radicand$65[63:0]$10212 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10212 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178848$10528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:178848$10528_Y - end - connect \$7 $not$libresoc.v:178833$10513_Y - connect \$12 $reduce_or$libresoc.v:178834$10514_Y - connect \$11 $not$libresoc.v:178835$10515_Y - connect \$16 $reduce_or$libresoc.v:178836$10516_Y - connect \$15 $not$libresoc.v:178837$10517_Y - connect \$1 $not$libresoc.v:178838$10518_Y - connect \$20 $reduce_or$libresoc.v:178839$10519_Y - connect \$19 $not$libresoc.v:178840$10520_Y - connect \$24 $reduce_or$libresoc.v:178841$10521_Y - connect \$23 $not$libresoc.v:178842$10522_Y - connect \$28 $reduce_or$libresoc.v:178843$10523_Y - connect \$27 $not$libresoc.v:178844$10524_Y - connect \$31 $reduce_or$libresoc.v:178845$10525_Y - connect \$4 $reduce_or$libresoc.v:178846$10526_Y - connect \$3 $not$libresoc.v:178847$10527_Y - connect \$8 $reduce_or$libresoc.v:178848$10528_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:178864.1-178948.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$138 - attribute \src "libresoc.v:178921.17-178921.91" - wire $not$libresoc.v:178921$10529_Y - attribute \src "libresoc.v:178923.18-178923.93" - wire $not$libresoc.v:178923$10531_Y - attribute \src "libresoc.v:178925.18-178925.93" - wire $not$libresoc.v:178925$10533_Y - attribute \src "libresoc.v:178926.17-178926.138" - wire width 8 $not$libresoc.v:178926$10534_Y - attribute \src "libresoc.v:178928.18-178928.93" - wire $not$libresoc.v:178928$10536_Y - attribute \src "libresoc.v:178930.18-178930.93" - wire $not$libresoc.v:178930$10538_Y - attribute \src "libresoc.v:178932.18-178932.93" - wire $not$libresoc.v:178932$10540_Y - attribute \src "libresoc.v:178935.17-178935.91" - wire $not$libresoc.v:178935$10543_Y - attribute \src "libresoc.v:178922.18-178922.116" - wire $reduce_or$libresoc.v:178922$10530_Y - attribute \src "libresoc.v:178924.18-178924.122" - wire $reduce_or$libresoc.v:178924$10532_Y - attribute \src "libresoc.v:178927.18-178927.128" - wire $reduce_or$libresoc.v:178927$10535_Y - attribute \src "libresoc.v:178929.18-178929.134" - wire $reduce_or$libresoc.v:178929$10537_Y - attribute \src "libresoc.v:178931.18-178931.140" - wire $reduce_or$libresoc.v:178931$10539_Y - attribute \src "libresoc.v:178933.18-178933.90" - wire $reduce_or$libresoc.v:178933$10541_Y - attribute \src "libresoc.v:178934.17-178934.103" - wire $reduce_or$libresoc.v:178934$10542_Y - attribute \src "libresoc.v:178936.17-178936.109" - wire $reduce_or$libresoc.v:178936$10544_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178921$10529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:178921$10529_Y + attribute \src "libresoc.v:171428.7-171428.19" + process $proc$libresoc.v:171428$10213 + assign { } { } + assign $1\empty[0:0] 1'1 + sync always + sync init + update \empty $1\empty[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178923$10531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:178923$10531_Y + attribute \src "libresoc.v:171436.13-171436.45" + process $proc$libresoc.v:171436$10214 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$10215 4'0000 + sync always + sync init + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10215 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178925$10533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:178925$10533_Y + attribute \src "libresoc.v:171486.14-171486.49" + process $proc$libresoc.v:171486$10216 + assign { } { } + assign $0\logical_op__fn_unit$30[12:0]$10217 13'0000000000000 + sync always + sync init + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$10217 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:178926$10534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:178926$10534_Y + attribute \src "libresoc.v:171492.14-171492.68" + process $proc$libresoc.v:171492$10218 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$10219 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10219 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178928$10536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:178928$10536_Y + attribute \src "libresoc.v:171500.7-171500.43" + process $proc$libresoc.v:171500$10220 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$10221 1'0 + sync always + sync init + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10221 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178930$10538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:178930$10538_Y + attribute \src "libresoc.v:171522.13-171522.48" + process $proc$libresoc.v:171522$10222 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$10223 2'00 + sync always + sync init + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10223 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178932$10540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:178932$10540_Y + attribute \src "libresoc.v:171530.14-171530.43" + process $proc$libresoc.v:171530$10224 + assign { } { } + assign $0\logical_op__insn$46[31:0]$10225 0 + sync always + sync init + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10225 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:178935$10543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:178935$10543_Y + attribute \src "libresoc.v:171760.13-171760.47" + process $proc$libresoc.v:171760$10226 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$10227 7'0000000 + sync always + sync init + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10227 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178922$10530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:178922$10530_Y + attribute \src "libresoc.v:171768.7-171768.40" + process $proc$libresoc.v:171768$10228 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$10229 1'0 + sync always + sync init + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10229 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178924$10532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:178924$10532_Y + attribute \src "libresoc.v:171776.7-171776.41" + process $proc$libresoc.v:171776$10230 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$10231 1'0 + sync always + sync init + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10231 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178927$10535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:178927$10535_Y + attribute \src "libresoc.v:171784.7-171784.39" + process $proc$libresoc.v:171784$10232 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$10233 1'0 + sync always + sync init + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10233 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178929$10537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:178929$10537_Y + attribute \src "libresoc.v:171792.7-171792.40" + process $proc$libresoc.v:171792$10234 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$10235 1'0 + sync always + sync init + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10235 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178931$10539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:178931$10539_Y + attribute \src "libresoc.v:171798.7-171798.37" + process $proc$libresoc.v:171798$10236 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$10237 1'0 + sync always + sync init + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10237 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:178933$10541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:178933$10541_Y + attribute \src "libresoc.v:171806.7-171806.37" + process $proc$libresoc.v:171806$10238 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$10239 1'0 + sync always + sync init + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10239 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178934$10542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:178934$10542_Y + attribute \src "libresoc.v:171816.7-171816.43" + process $proc$libresoc.v:171816$10240 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$10241 1'0 + sync always + sync init + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10241 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:178936$10544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:178936$10544_Y - end - connect \$7 $not$libresoc.v:178921$10529_Y - connect \$12 $reduce_or$libresoc.v:178922$10530_Y - connect \$11 $not$libresoc.v:178923$10531_Y - connect \$16 $reduce_or$libresoc.v:178924$10532_Y - connect \$15 $not$libresoc.v:178925$10533_Y - connect \$1 $not$libresoc.v:178926$10534_Y - connect \$20 $reduce_or$libresoc.v:178927$10535_Y - connect \$19 $not$libresoc.v:178928$10536_Y - connect \$24 $reduce_or$libresoc.v:178929$10537_Y - connect \$23 $not$libresoc.v:178930$10538_Y - connect \$28 $reduce_or$libresoc.v:178931$10539_Y - connect \$27 $not$libresoc.v:178932$10540_Y - connect \$31 $reduce_or$libresoc.v:178933$10541_Y - connect \$4 $reduce_or$libresoc.v:178934$10542_Y - connect \$3 $not$libresoc.v:178935$10543_Y - connect \$8 $reduce_or$libresoc.v:178936$10544_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:178952.1-179036.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$143 - attribute \src "libresoc.v:179009.17-179009.91" - wire $not$libresoc.v:179009$10545_Y - attribute \src "libresoc.v:179011.18-179011.93" - wire $not$libresoc.v:179011$10547_Y - attribute \src "libresoc.v:179013.18-179013.93" - wire $not$libresoc.v:179013$10549_Y - attribute \src "libresoc.v:179014.17-179014.138" - wire width 8 $not$libresoc.v:179014$10550_Y - attribute \src "libresoc.v:179016.18-179016.93" - wire $not$libresoc.v:179016$10552_Y - attribute \src "libresoc.v:179018.18-179018.93" - wire $not$libresoc.v:179018$10554_Y - attribute \src "libresoc.v:179020.18-179020.93" - wire $not$libresoc.v:179020$10556_Y - attribute \src "libresoc.v:179023.17-179023.91" - wire $not$libresoc.v:179023$10559_Y - attribute \src "libresoc.v:179010.18-179010.116" - wire $reduce_or$libresoc.v:179010$10546_Y - attribute \src "libresoc.v:179012.18-179012.122" - wire $reduce_or$libresoc.v:179012$10548_Y - attribute \src "libresoc.v:179015.18-179015.128" - wire $reduce_or$libresoc.v:179015$10551_Y - attribute \src "libresoc.v:179017.18-179017.134" - wire $reduce_or$libresoc.v:179017$10553_Y - attribute \src "libresoc.v:179019.18-179019.140" - wire $reduce_or$libresoc.v:179019$10555_Y - attribute \src "libresoc.v:179021.18-179021.90" - wire $reduce_or$libresoc.v:179021$10557_Y - attribute \src "libresoc.v:179022.17-179022.103" - wire $reduce_or$libresoc.v:179022$10558_Y - attribute \src "libresoc.v:179024.17-179024.109" - wire $reduce_or$libresoc.v:179024$10560_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179009$10545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179009$10545_Y + attribute \src "libresoc.v:171822.7-171822.37" + process $proc$libresoc.v:171822$10242 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$10243 1'0 + sync always + sync init + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10243 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179011$10547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179011$10547_Y + attribute \src "libresoc.v:171830.7-171830.37" + process $proc$libresoc.v:171830$10244 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$10245 1'0 + sync always + sync init + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10245 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179013$10549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179013$10549_Y + attribute \src "libresoc.v:171840.7-171840.40" + process $proc$libresoc.v:171840$10246 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$10247 1'0 + sync always + sync init + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10247 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179014$10550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179014$10550_Y + attribute \src "libresoc.v:171848.7-171848.37" + process $proc$libresoc.v:171848$10248 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$10249 1'0 + sync always + sync init + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10249 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179016$10552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179016$10552_Y + attribute \src "libresoc.v:171856.13-171856.30" + process $proc$libresoc.v:171856$10250 + assign { } { } + assign $0\muxid$28[1:0]$10251 2'00 + sync always + sync init + update \muxid$28 $0\muxid$28[1:0]$10251 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179018$10554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179018$10554_Y + attribute \src "libresoc.v:171866.13-171866.34" + process $proc$libresoc.v:171866$10252 + assign { } { } + assign $0\operation$69[1:0]$10253 2'00 + sync always + sync init + update \operation$69 $0\operation$69[1:0]$10253 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179020$10556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179020$10556_Y + attribute \src "libresoc.v:171880.14-171880.44" + process $proc$libresoc.v:171880$10254 + assign { } { } + assign $0\ra$47[63:0]$10255 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra$47 $0\ra$47[63:0]$10255 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179023$10559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179023$10559_Y + attribute \src "libresoc.v:171888.14-171888.44" + process $proc$libresoc.v:171888$10256 + assign { } { } + assign $0\rb$48[63:0]$10257 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb$48 $0\rb$48[63:0]$10257 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179010$10546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179010$10546_Y + attribute \src "libresoc.v:171894.15-171894.84" + process $proc$libresoc.v:171894$10258 + assign { } { } + assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179012$10548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179012$10548_Y + attribute \src "libresoc.v:171898.13-171898.45" + process $proc$libresoc.v:171898$10259 + assign { } { } + assign $1\saved_state_q_bits_known[6:0] 7'0000000 + sync always + sync init + update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179015$10551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179015$10551_Y + attribute \src "libresoc.v:171906.7-171906.25" + process $proc$libresoc.v:171906$10260 + assign { } { } + assign $0\xer_so$49[0:0]$10261 1'0 + sync always + sync init + update \xer_so$49 $0\xer_so$49[0:0]$10261 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179017$10553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179017$10553_Y + attribute \src "libresoc.v:171915.3-171916.43" + process $proc$libresoc.v:171915$10011 + assign { } { } + assign $0\operation$69[1:0]$10012 \operation$69$next + sync posedge \coresync_clk + update \operation$69 $0\operation$69[1:0]$10012 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179019$10555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179019$10555_Y + attribute \src "libresoc.v:171917.3-171918.57" + process $proc$libresoc.v:171917$10013 + assign { } { } + assign $0\divisor_radicand$65[63:0]$10014 \divisor_radicand$65$next + sync posedge \coresync_clk + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10014 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179021$10557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179021$10557_Y + attribute \src "libresoc.v:171919.3-171920.41" + process $proc$libresoc.v:171919$10015 + assign { } { } + assign $0\dividend$68[127:0]$10016 \dividend$68$next + sync posedge \coresync_clk + update \dividend$68 $0\dividend$68[127:0]$10016 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179022$10558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179022$10558_Y + attribute \src "libresoc.v:171921.3-171922.47" + process $proc$libresoc.v:171921$10017 + assign { } { } + assign $0\div_by_zero$54[0:0]$10018 \div_by_zero$54$next + sync posedge \coresync_clk + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10018 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179024$10560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179024$10560_Y - end - connect \$7 $not$libresoc.v:179009$10545_Y - connect \$12 $reduce_or$libresoc.v:179010$10546_Y - connect \$11 $not$libresoc.v:179011$10547_Y - connect \$16 $reduce_or$libresoc.v:179012$10548_Y - connect \$15 $not$libresoc.v:179013$10549_Y - connect \$1 $not$libresoc.v:179014$10550_Y - connect \$20 $reduce_or$libresoc.v:179015$10551_Y - connect \$19 $not$libresoc.v:179016$10552_Y - connect \$24 $reduce_or$libresoc.v:179017$10553_Y - connect \$23 $not$libresoc.v:179018$10554_Y - connect \$28 $reduce_or$libresoc.v:179019$10555_Y - connect \$27 $not$libresoc.v:179020$10556_Y - connect \$31 $reduce_or$libresoc.v:179021$10557_Y - connect \$4 $reduce_or$libresoc.v:179022$10558_Y - connect \$3 $not$libresoc.v:179023$10559_Y - connect \$8 $reduce_or$libresoc.v:179024$10560_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:179040.1-179124.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$145 - attribute \src "libresoc.v:179097.17-179097.91" - wire $not$libresoc.v:179097$10561_Y - attribute \src "libresoc.v:179099.18-179099.93" - wire $not$libresoc.v:179099$10563_Y - attribute \src "libresoc.v:179101.18-179101.93" - wire $not$libresoc.v:179101$10565_Y - attribute \src "libresoc.v:179102.17-179102.138" - wire width 8 $not$libresoc.v:179102$10566_Y - attribute \src "libresoc.v:179104.18-179104.93" - wire $not$libresoc.v:179104$10568_Y - attribute \src "libresoc.v:179106.18-179106.93" - wire $not$libresoc.v:179106$10570_Y - attribute \src "libresoc.v:179108.18-179108.93" - wire $not$libresoc.v:179108$10572_Y - attribute \src "libresoc.v:179111.17-179111.91" - wire $not$libresoc.v:179111$10575_Y - attribute \src "libresoc.v:179098.18-179098.116" - wire $reduce_or$libresoc.v:179098$10562_Y - attribute \src "libresoc.v:179100.18-179100.122" - wire $reduce_or$libresoc.v:179100$10564_Y - attribute \src "libresoc.v:179103.18-179103.128" - wire $reduce_or$libresoc.v:179103$10567_Y - attribute \src "libresoc.v:179105.18-179105.134" - wire $reduce_or$libresoc.v:179105$10569_Y - attribute \src "libresoc.v:179107.18-179107.140" - wire $reduce_or$libresoc.v:179107$10571_Y - attribute \src "libresoc.v:179109.18-179109.90" - wire $reduce_or$libresoc.v:179109$10573_Y - attribute \src "libresoc.v:179110.17-179110.103" - wire $reduce_or$libresoc.v:179110$10574_Y - attribute \src "libresoc.v:179112.17-179112.109" - wire $reduce_or$libresoc.v:179112$10576_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179097$10561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179097$10561_Y + attribute \src "libresoc.v:171923.3-171924.51" + process $proc$libresoc.v:171923$10019 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$10020 \dive_abs_ov64$53$next + sync posedge \coresync_clk + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10020 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179099$10563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179099$10563_Y + attribute \src "libresoc.v:171925.3-171926.51" + process $proc$libresoc.v:171925$10021 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$10022 \dive_abs_ov32$52$next + sync posedge \coresync_clk + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10022 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179101$10565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179101$10565_Y + attribute \src "libresoc.v:171927.3-171928.49" + process $proc$libresoc.v:171927$10023 + assign { } { } + assign $0\dividend_neg$51[0:0]$10024 \dividend_neg$51$next + sync posedge \coresync_clk + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10024 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179102$10566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179102$10566_Y + attribute \src "libresoc.v:171929.3-171930.47" + process $proc$libresoc.v:171929$10025 + assign { } { } + assign $0\divisor_neg$50[0:0]$10026 \divisor_neg$50$next + sync posedge \coresync_clk + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10026 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179104$10568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179104$10568_Y + attribute \src "libresoc.v:171931.3-171932.37" + process $proc$libresoc.v:171931$10027 + assign { } { } + assign $0\xer_so$49[0:0]$10028 \xer_so$49$next + sync posedge \coresync_clk + update \xer_so$49 $0\xer_so$49[0:0]$10028 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179106$10570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179106$10570_Y + attribute \src "libresoc.v:171933.3-171934.29" + process $proc$libresoc.v:171933$10029 + assign { } { } + assign $0\rb$48[63:0]$10030 \rb$48$next + sync posedge \coresync_clk + update \rb$48 $0\rb$48[63:0]$10030 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179108$10572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179108$10572_Y + attribute \src "libresoc.v:171935.3-171936.29" + process $proc$libresoc.v:171935$10031 + assign { } { } + assign $0\ra$47[63:0]$10032 \ra$47$next + sync posedge \coresync_clk + update \ra$47 $0\ra$47[63:0]$10032 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179111$10575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179111$10575_Y + attribute \src "libresoc.v:171937.3-171938.67" + process $proc$libresoc.v:171937$10033 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$10034 \logical_op__insn_type$29$next + sync posedge \coresync_clk + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10034 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179098$10562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179098$10562_Y + attribute \src "libresoc.v:171939.3-171940.63" + process $proc$libresoc.v:171939$10035 + assign { } { } + assign $0\logical_op__fn_unit$30[12:0]$10036 \logical_op__fn_unit$30$next + sync posedge \coresync_clk + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$10036 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179100$10564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179100$10564_Y + attribute \src "libresoc.v:171941.3-171942.77" + process $proc$libresoc.v:171941$10037 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$10038 \logical_op__imm_data__data$31$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10038 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179103$10567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179103$10567_Y + attribute \src "libresoc.v:171943.3-171944.73" + process $proc$libresoc.v:171943$10039 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$10040 \logical_op__imm_data__ok$32$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10040 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179105$10569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179105$10569_Y + attribute \src "libresoc.v:171945.3-171946.61" + process $proc$libresoc.v:171945$10041 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$10042 \logical_op__rc__rc$33$next + sync posedge \coresync_clk + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10042 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179107$10571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179107$10571_Y + attribute \src "libresoc.v:171947.3-171948.61" + process $proc$libresoc.v:171947$10043 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$10044 \logical_op__rc__ok$34$next + sync posedge \coresync_clk + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10044 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179109$10573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179109$10573_Y + attribute \src "libresoc.v:171949.3-171950.61" + process $proc$libresoc.v:171949$10045 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$10046 \logical_op__oe__oe$35$next + sync posedge \coresync_clk + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10046 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179110$10574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179110$10574_Y + attribute \src "libresoc.v:171951.3-171952.61" + process $proc$libresoc.v:171951$10047 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$10048 \logical_op__oe__ok$36$next + sync posedge \coresync_clk + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10048 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179112$10576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179112$10576_Y - end - connect \$7 $not$libresoc.v:179097$10561_Y - connect \$12 $reduce_or$libresoc.v:179098$10562_Y - connect \$11 $not$libresoc.v:179099$10563_Y - connect \$16 $reduce_or$libresoc.v:179100$10564_Y - connect \$15 $not$libresoc.v:179101$10565_Y - connect \$1 $not$libresoc.v:179102$10566_Y - connect \$20 $reduce_or$libresoc.v:179103$10567_Y - connect \$19 $not$libresoc.v:179104$10568_Y - connect \$24 $reduce_or$libresoc.v:179105$10569_Y - connect \$23 $not$libresoc.v:179106$10570_Y - connect \$28 $reduce_or$libresoc.v:179107$10571_Y - connect \$27 $not$libresoc.v:179108$10572_Y - connect \$31 $reduce_or$libresoc.v:179109$10573_Y - connect \$4 $reduce_or$libresoc.v:179110$10574_Y - connect \$3 $not$libresoc.v:179111$10575_Y - connect \$8 $reduce_or$libresoc.v:179112$10576_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:179128.1-179212.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$150 - attribute \src "libresoc.v:179185.17-179185.91" - wire $not$libresoc.v:179185$10577_Y - attribute \src "libresoc.v:179187.18-179187.93" - wire $not$libresoc.v:179187$10579_Y - attribute \src "libresoc.v:179189.18-179189.93" - wire $not$libresoc.v:179189$10581_Y - attribute \src "libresoc.v:179190.17-179190.138" - wire width 8 $not$libresoc.v:179190$10582_Y - attribute \src "libresoc.v:179192.18-179192.93" - wire $not$libresoc.v:179192$10584_Y - attribute \src "libresoc.v:179194.18-179194.93" - wire $not$libresoc.v:179194$10586_Y - attribute \src "libresoc.v:179196.18-179196.93" - wire $not$libresoc.v:179196$10588_Y - attribute \src "libresoc.v:179199.17-179199.91" - wire $not$libresoc.v:179199$10591_Y - attribute \src "libresoc.v:179186.18-179186.116" - wire $reduce_or$libresoc.v:179186$10578_Y - attribute \src "libresoc.v:179188.18-179188.122" - wire $reduce_or$libresoc.v:179188$10580_Y - attribute \src "libresoc.v:179191.18-179191.128" - wire $reduce_or$libresoc.v:179191$10583_Y - attribute \src "libresoc.v:179193.18-179193.134" - wire $reduce_or$libresoc.v:179193$10585_Y - attribute \src "libresoc.v:179195.18-179195.140" - wire $reduce_or$libresoc.v:179195$10587_Y - attribute \src "libresoc.v:179197.18-179197.90" - wire $reduce_or$libresoc.v:179197$10589_Y - attribute \src "libresoc.v:179198.17-179198.103" - wire $reduce_or$libresoc.v:179198$10590_Y - attribute \src "libresoc.v:179200.17-179200.109" - wire $reduce_or$libresoc.v:179200$10592_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179185$10577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179185$10577_Y + attribute \src "libresoc.v:171953.3-171954.67" + process $proc$libresoc.v:171953$10049 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$10050 \logical_op__invert_in$37$next + sync posedge \coresync_clk + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10050 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179187$10579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179187$10579_Y + attribute \src "libresoc.v:171955.3-171956.61" + process $proc$libresoc.v:171955$10051 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$10052 \logical_op__zero_a$38$next + sync posedge \coresync_clk + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10052 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179189$10581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179189$10581_Y + attribute \src "libresoc.v:171957.3-171958.71" + process $proc$libresoc.v:171957$10053 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$10054 \logical_op__input_carry$39$next + sync posedge \coresync_clk + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10054 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179190$10582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179190$10582_Y + attribute \src "libresoc.v:171959.3-171960.69" + process $proc$libresoc.v:171959$10055 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$10056 \logical_op__invert_out$40$next + sync posedge \coresync_clk + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10056 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179192$10584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179192$10584_Y + attribute \src "libresoc.v:171961.3-171962.67" + process $proc$libresoc.v:171961$10057 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$10058 \logical_op__write_cr0$41$next + sync posedge \coresync_clk + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10058 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179194$10586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179194$10586_Y + attribute \src "libresoc.v:171963.3-171964.73" + process $proc$libresoc.v:171963$10059 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$10060 \logical_op__output_carry$42$next + sync posedge \coresync_clk + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10060 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179196$10588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179196$10588_Y + attribute \src "libresoc.v:171965.3-171966.65" + process $proc$libresoc.v:171965$10061 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$10062 \logical_op__is_32bit$43$next + sync posedge \coresync_clk + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10062 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179199$10591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179199$10591_Y + attribute \src "libresoc.v:171967.3-171968.67" + process $proc$libresoc.v:171967$10063 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$10064 \logical_op__is_signed$44$next + sync posedge \coresync_clk + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10064 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179186$10578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179186$10578_Y + attribute \src "libresoc.v:171969.3-171970.65" + process $proc$libresoc.v:171969$10065 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$10066 \logical_op__data_len$45$next + sync posedge \coresync_clk + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10066 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179188$10580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179188$10580_Y + attribute \src "libresoc.v:171971.3-171972.57" + process $proc$libresoc.v:171971$10067 + assign { } { } + assign $0\logical_op__insn$46[31:0]$10068 \logical_op__insn$46$next + sync posedge \coresync_clk + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10068 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179191$10583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179191$10583_Y + attribute \src "libresoc.v:171973.3-171974.35" + process $proc$libresoc.v:171973$10069 + assign { } { } + assign $0\muxid$28[1:0]$10070 \muxid$28$next + sync posedge \coresync_clk + update \muxid$28 $0\muxid$28[1:0]$10070 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179193$10585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179193$10585_Y + attribute \src "libresoc.v:171975.3-171976.27" + process $proc$libresoc.v:171975$10071 + assign { } { } + assign $0\empty[0:0] \empty$next + sync posedge \coresync_clk + update \empty $0\empty[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179195$10587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179195$10587_Y + attribute \src "libresoc.v:171977.3-171978.75" + process $proc$libresoc.v:171977$10072 + assign { } { } + assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next + sync posedge \coresync_clk + update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179197$10589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179197$10589_Y + attribute \src "libresoc.v:171979.3-171980.65" + process $proc$libresoc.v:171979$10073 + assign { } { } + assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next + sync posedge \coresync_clk + update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179198$10590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179198$10590_Y + attribute \src "libresoc.v:172001.3-172009.6" + process $proc$libresoc.v:172001$10074 + assign { } { } + assign { } { } + assign $0\saved_state_q_bits_known$next[6:0]$10075 $1\saved_state_q_bits_known$next[6:0]$10076 + attribute \src "libresoc.v:172002.5-172002.29" + switch \initial + attribute \src "libresoc.v:172002.9-172002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_q_bits_known$next[6:0]$10076 7'0000000 + case + assign $1\saved_state_q_bits_known$next[6:0]$10076 \div_state_next_o_q_bits_known + end + sync always + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10075 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179200$10592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179200$10592_Y - end - connect \$7 $not$libresoc.v:179185$10577_Y - connect \$12 $reduce_or$libresoc.v:179186$10578_Y - connect \$11 $not$libresoc.v:179187$10579_Y - connect \$16 $reduce_or$libresoc.v:179188$10580_Y - connect \$15 $not$libresoc.v:179189$10581_Y - connect \$1 $not$libresoc.v:179190$10582_Y - connect \$20 $reduce_or$libresoc.v:179191$10583_Y - connect \$19 $not$libresoc.v:179192$10584_Y - connect \$24 $reduce_or$libresoc.v:179193$10585_Y - connect \$23 $not$libresoc.v:179194$10586_Y - connect \$28 $reduce_or$libresoc.v:179195$10587_Y - connect \$27 $not$libresoc.v:179196$10588_Y - connect \$31 $reduce_or$libresoc.v:179197$10589_Y - connect \$4 $reduce_or$libresoc.v:179198$10590_Y - connect \$3 $not$libresoc.v:179199$10591_Y - connect \$8 $reduce_or$libresoc.v:179200$10592_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:179216.1-179300.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$152 - attribute \src "libresoc.v:179273.17-179273.91" - wire $not$libresoc.v:179273$10593_Y - attribute \src "libresoc.v:179275.18-179275.93" - wire $not$libresoc.v:179275$10595_Y - attribute \src "libresoc.v:179277.18-179277.93" - wire $not$libresoc.v:179277$10597_Y - attribute \src "libresoc.v:179278.17-179278.138" - wire width 8 $not$libresoc.v:179278$10598_Y - attribute \src "libresoc.v:179280.18-179280.93" - wire $not$libresoc.v:179280$10600_Y - attribute \src "libresoc.v:179282.18-179282.93" - wire $not$libresoc.v:179282$10602_Y - attribute \src "libresoc.v:179284.18-179284.93" - wire $not$libresoc.v:179284$10604_Y - attribute \src "libresoc.v:179287.17-179287.91" - wire $not$libresoc.v:179287$10607_Y - attribute \src "libresoc.v:179274.18-179274.116" - wire $reduce_or$libresoc.v:179274$10594_Y - attribute \src "libresoc.v:179276.18-179276.122" - wire $reduce_or$libresoc.v:179276$10596_Y - attribute \src "libresoc.v:179279.18-179279.128" - wire $reduce_or$libresoc.v:179279$10599_Y - attribute \src "libresoc.v:179281.18-179281.134" - wire $reduce_or$libresoc.v:179281$10601_Y - attribute \src "libresoc.v:179283.18-179283.140" - wire $reduce_or$libresoc.v:179283$10603_Y - attribute \src "libresoc.v:179285.18-179285.90" - wire $reduce_or$libresoc.v:179285$10605_Y - attribute \src "libresoc.v:179286.17-179286.103" - wire $reduce_or$libresoc.v:179286$10606_Y - attribute \src "libresoc.v:179288.17-179288.109" - wire $reduce_or$libresoc.v:179288$10608_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179273$10593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179273$10593_Y + attribute \src "libresoc.v:172010.3-172018.6" + process $proc$libresoc.v:172010$10077 + assign { } { } + assign { } { } + assign $0\saved_state_dividend_quotient$next[127:0]$10078 $1\saved_state_dividend_quotient$next[127:0]$10079 + attribute \src "libresoc.v:172011.5-172011.29" + switch \initial + attribute \src "libresoc.v:172011.9-172011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_dividend_quotient$next[127:0]$10079 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\saved_state_dividend_quotient$next[127:0]$10079 \div_state_next_o_dividend_quotient + end + sync always + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10078 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179275$10595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179275$10595_Y + attribute \src "libresoc.v:172019.3-172030.6" + process $proc$libresoc.v:172019$10080 + assign { } { } + assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:172020.5-172020.29" + switch \initial + attribute \src "libresoc.v:172020.9-172020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known + end + sync always + update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179277$10597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179277$10597_Y + attribute \src "libresoc.v:172031.3-172042.6" + process $proc$libresoc.v:172031$10081 + assign { } { } + assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:172032.5-172032.29" + switch \initial + attribute \src "libresoc.v:172032.9-172032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient + end + sync always + update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179278$10598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179278$10598_Y + attribute \src "libresoc.v:172043.3-172054.6" + process $proc$libresoc.v:172043$10082 + assign { } { } + assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:172044.5-172044.29" + switch \initial + attribute \src "libresoc.v:172044.9-172044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 + end + sync always + update \div_state_next_divisor $0\div_state_next_divisor[63:0] + end + attribute \src "libresoc.v:172055.3-172082.6" + process $proc$libresoc.v:172055$10083 + assign { } { } + assign { } { } + assign { } { } + assign $0\empty$next[0:0]$10084 $4\empty$next[0:0]$10088 + attribute \src "libresoc.v:172056.5-172056.29" + switch \initial + attribute \src "libresoc.v:172056.9-172056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\empty$next[0:0]$10085 $2\empty$next[0:0]$10086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\empty$next[0:0]$10086 1'0 + case + assign $2\empty$next[0:0]$10086 \empty + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\empty$next[0:0]$10085 $3\empty$next[0:0]$10087 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + switch \$66 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\empty$next[0:0]$10087 1'1 + case + assign $3\empty$next[0:0]$10087 \empty + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\empty$next[0:0]$10088 1'1 + case + assign $4\empty$next[0:0]$10088 $1\empty$next[0:0]$10085 + end + sync always + update \empty$next $0\empty$next[0:0]$10084 + end + attribute \src "libresoc.v:172083.3-172097.6" + process $proc$libresoc.v:172083$10089 + assign { } { } + assign { } { } + assign $0\muxid$28$next[1:0]$10090 $1\muxid$28$next[1:0]$10091 + attribute \src "libresoc.v:172084.5-172084.29" + switch \initial + attribute \src "libresoc.v:172084.9-172084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\muxid$28$next[1:0]$10091 $2\muxid$28$next[1:0]$10092 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\muxid$28$next[1:0]$10092 \muxid + case + assign $2\muxid$28$next[1:0]$10092 \muxid$28 + end + case + assign $1\muxid$28$next[1:0]$10091 \muxid$28 + end + sync always + update \muxid$28$next $0\muxid$28$next[1:0]$10090 + end + attribute \src "libresoc.v:172098.3-172141.6" + process $proc$libresoc.v:172098$10093 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$45$next[3:0]$10094 $1\logical_op__data_len$45$next[3:0]$10112 + assign $0\logical_op__fn_unit$30$next[12:0]$10095 $1\logical_op__fn_unit$30$next[12:0]$10113 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$39$next[1:0]$10098 $1\logical_op__input_carry$39$next[1:0]$10116 + assign $0\logical_op__insn$46$next[31:0]$10099 $1\logical_op__insn$46$next[31:0]$10117 + assign $0\logical_op__insn_type$29$next[6:0]$10100 $1\logical_op__insn_type$29$next[6:0]$10118 + assign $0\logical_op__invert_in$37$next[0:0]$10101 $1\logical_op__invert_in$37$next[0:0]$10119 + assign $0\logical_op__invert_out$40$next[0:0]$10102 $1\logical_op__invert_out$40$next[0:0]$10120 + assign $0\logical_op__is_32bit$43$next[0:0]$10103 $1\logical_op__is_32bit$43$next[0:0]$10121 + assign $0\logical_op__is_signed$44$next[0:0]$10104 $1\logical_op__is_signed$44$next[0:0]$10122 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$42$next[0:0]$10107 $1\logical_op__output_carry$42$next[0:0]$10125 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$41$next[0:0]$10110 $1\logical_op__write_cr0$41$next[0:0]$10128 + assign $0\logical_op__zero_a$38$next[0:0]$10111 $1\logical_op__zero_a$38$next[0:0]$10129 + assign $0\logical_op__imm_data__data$31$next[63:0]$10096 $3\logical_op__imm_data__data$31$next[63:0]$10148 + assign $0\logical_op__imm_data__ok$32$next[0:0]$10097 $3\logical_op__imm_data__ok$32$next[0:0]$10149 + assign $0\logical_op__oe__oe$35$next[0:0]$10105 $3\logical_op__oe__oe$35$next[0:0]$10150 + assign $0\logical_op__oe__ok$36$next[0:0]$10106 $3\logical_op__oe__ok$36$next[0:0]$10151 + assign $0\logical_op__rc__ok$34$next[0:0]$10108 $3\logical_op__rc__ok$34$next[0:0]$10152 + assign $0\logical_op__rc__rc$33$next[0:0]$10109 $3\logical_op__rc__rc$33$next[0:0]$10153 + attribute \src "libresoc.v:172099.5-172099.29" + switch \initial + attribute \src "libresoc.v:172099.9-172099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\logical_op__data_len$45$next[3:0]$10112 $2\logical_op__data_len$45$next[3:0]$10130 + assign $1\logical_op__fn_unit$30$next[12:0]$10113 $2\logical_op__fn_unit$30$next[12:0]$10131 + assign $1\logical_op__imm_data__data$31$next[63:0]$10114 $2\logical_op__imm_data__data$31$next[63:0]$10132 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10115 $2\logical_op__imm_data__ok$32$next[0:0]$10133 + assign $1\logical_op__input_carry$39$next[1:0]$10116 $2\logical_op__input_carry$39$next[1:0]$10134 + assign $1\logical_op__insn$46$next[31:0]$10117 $2\logical_op__insn$46$next[31:0]$10135 + assign $1\logical_op__insn_type$29$next[6:0]$10118 $2\logical_op__insn_type$29$next[6:0]$10136 + assign $1\logical_op__invert_in$37$next[0:0]$10119 $2\logical_op__invert_in$37$next[0:0]$10137 + assign $1\logical_op__invert_out$40$next[0:0]$10120 $2\logical_op__invert_out$40$next[0:0]$10138 + assign $1\logical_op__is_32bit$43$next[0:0]$10121 $2\logical_op__is_32bit$43$next[0:0]$10139 + assign $1\logical_op__is_signed$44$next[0:0]$10122 $2\logical_op__is_signed$44$next[0:0]$10140 + assign $1\logical_op__oe__oe$35$next[0:0]$10123 $2\logical_op__oe__oe$35$next[0:0]$10141 + assign $1\logical_op__oe__ok$36$next[0:0]$10124 $2\logical_op__oe__ok$36$next[0:0]$10142 + assign $1\logical_op__output_carry$42$next[0:0]$10125 $2\logical_op__output_carry$42$next[0:0]$10143 + assign $1\logical_op__rc__ok$34$next[0:0]$10126 $2\logical_op__rc__ok$34$next[0:0]$10144 + assign $1\logical_op__rc__rc$33$next[0:0]$10127 $2\logical_op__rc__rc$33$next[0:0]$10145 + assign $1\logical_op__write_cr0$41$next[0:0]$10128 $2\logical_op__write_cr0$41$next[0:0]$10146 + assign $1\logical_op__zero_a$38$next[0:0]$10129 $2\logical_op__zero_a$38$next[0:0]$10147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\logical_op__insn$46$next[31:0]$10135 $2\logical_op__data_len$45$next[3:0]$10130 $2\logical_op__is_signed$44$next[0:0]$10140 $2\logical_op__is_32bit$43$next[0:0]$10139 $2\logical_op__output_carry$42$next[0:0]$10143 $2\logical_op__write_cr0$41$next[0:0]$10146 $2\logical_op__invert_out$40$next[0:0]$10138 $2\logical_op__input_carry$39$next[1:0]$10134 $2\logical_op__zero_a$38$next[0:0]$10147 $2\logical_op__invert_in$37$next[0:0]$10137 $2\logical_op__oe__ok$36$next[0:0]$10142 $2\logical_op__oe__oe$35$next[0:0]$10141 $2\logical_op__rc__ok$34$next[0:0]$10144 $2\logical_op__rc__rc$33$next[0:0]$10145 $2\logical_op__imm_data__ok$32$next[0:0]$10133 $2\logical_op__imm_data__data$31$next[63:0]$10132 $2\logical_op__fn_unit$30$next[12:0]$10131 $2\logical_op__insn_type$29$next[6:0]$10136 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + case + assign $2\logical_op__data_len$45$next[3:0]$10130 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[12:0]$10131 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$10132 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$10133 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$10134 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$10135 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$10136 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$10137 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$10138 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$10139 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$10140 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$10141 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$10142 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$10143 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$10144 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$10145 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$10146 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$10147 \logical_op__zero_a$38 + end + case + assign $1\logical_op__data_len$45$next[3:0]$10112 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[12:0]$10113 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$10114 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10115 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$10116 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$10117 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$10118 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$10119 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$10120 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$10121 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$10122 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$10123 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$10124 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$10125 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$10126 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$10127 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$10128 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$10129 \logical_op__zero_a$38 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\logical_op__imm_data__data$31$next[63:0]$10148 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10149 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$10153 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$10152 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$10150 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$10151 1'0 + case + assign $3\logical_op__imm_data__data$31$next[63:0]$10148 $1\logical_op__imm_data__data$31$next[63:0]$10114 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10149 $1\logical_op__imm_data__ok$32$next[0:0]$10115 + assign $3\logical_op__oe__oe$35$next[0:0]$10150 $1\logical_op__oe__oe$35$next[0:0]$10123 + assign $3\logical_op__oe__ok$36$next[0:0]$10151 $1\logical_op__oe__ok$36$next[0:0]$10124 + assign $3\logical_op__rc__ok$34$next[0:0]$10152 $1\logical_op__rc__ok$34$next[0:0]$10126 + assign $3\logical_op__rc__rc$33$next[0:0]$10153 $1\logical_op__rc__rc$33$next[0:0]$10127 + end + sync always + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10094 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[12:0]$10095 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10096 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10097 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10098 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10099 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10100 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10101 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10102 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10103 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10104 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10105 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10106 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10107 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10108 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10109 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10110 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10111 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179280$10600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179280$10600_Y + attribute \src "libresoc.v:172142.3-172156.6" + process $proc$libresoc.v:172142$10154 + assign { } { } + assign { } { } + assign $0\ra$47$next[63:0]$10155 $1\ra$47$next[63:0]$10156 + attribute \src "libresoc.v:172143.5-172143.29" + switch \initial + attribute \src "libresoc.v:172143.9-172143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ra$47$next[63:0]$10156 $2\ra$47$next[63:0]$10157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ra$47$next[63:0]$10157 \ra + case + assign $2\ra$47$next[63:0]$10157 \ra$47 + end + case + assign $1\ra$47$next[63:0]$10156 \ra$47 + end + sync always + update \ra$47$next $0\ra$47$next[63:0]$10155 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179282$10602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179282$10602_Y + attribute \src "libresoc.v:172157.3-172171.6" + process $proc$libresoc.v:172157$10158 + assign { } { } + assign { } { } + assign $0\rb$48$next[63:0]$10159 $1\rb$48$next[63:0]$10160 + attribute \src "libresoc.v:172158.5-172158.29" + switch \initial + attribute \src "libresoc.v:172158.9-172158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rb$48$next[63:0]$10160 $2\rb$48$next[63:0]$10161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\rb$48$next[63:0]$10161 \rb + case + assign $2\rb$48$next[63:0]$10161 \rb$48 + end + case + assign $1\rb$48$next[63:0]$10160 \rb$48 + end + sync always + update \rb$48$next $0\rb$48$next[63:0]$10159 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179284$10604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179284$10604_Y + attribute \src "libresoc.v:172172.3-172186.6" + process $proc$libresoc.v:172172$10162 + assign { } { } + assign { } { } + assign $0\xer_so$49$next[0:0]$10163 $1\xer_so$49$next[0:0]$10164 + attribute \src "libresoc.v:172173.5-172173.29" + switch \initial + attribute \src "libresoc.v:172173.9-172173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$49$next[0:0]$10164 $2\xer_so$49$next[0:0]$10165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so$49$next[0:0]$10165 \xer_so + case + assign $2\xer_so$49$next[0:0]$10165 \xer_so$49 + end + case + assign $1\xer_so$49$next[0:0]$10164 \xer_so$49 + end + sync always + update \xer_so$49$next $0\xer_so$49$next[0:0]$10163 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179287$10607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179287$10607_Y + attribute \src "libresoc.v:172187.3-172201.6" + process $proc$libresoc.v:172187$10166 + assign { } { } + assign { } { } + assign $0\divisor_neg$50$next[0:0]$10167 $1\divisor_neg$50$next[0:0]$10168 + attribute \src "libresoc.v:172188.5-172188.29" + switch \initial + attribute \src "libresoc.v:172188.9-172188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_neg$50$next[0:0]$10168 $2\divisor_neg$50$next[0:0]$10169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_neg$50$next[0:0]$10169 \divisor_neg + case + assign $2\divisor_neg$50$next[0:0]$10169 \divisor_neg$50 + end + case + assign $1\divisor_neg$50$next[0:0]$10168 \divisor_neg$50 + end + sync always + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10167 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179274$10594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179274$10594_Y + attribute \src "libresoc.v:172202.3-172216.6" + process $proc$libresoc.v:172202$10170 + assign { } { } + assign { } { } + assign $0\dividend_neg$51$next[0:0]$10171 $1\dividend_neg$51$next[0:0]$10172 + attribute \src "libresoc.v:172203.5-172203.29" + switch \initial + attribute \src "libresoc.v:172203.9-172203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend_neg$51$next[0:0]$10172 $2\dividend_neg$51$next[0:0]$10173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend_neg$51$next[0:0]$10173 \dividend_neg + case + assign $2\dividend_neg$51$next[0:0]$10173 \dividend_neg$51 + end + case + assign $1\dividend_neg$51$next[0:0]$10172 \dividend_neg$51 + end + sync always + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10171 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179276$10596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179276$10596_Y + attribute \src "libresoc.v:172217.3-172231.6" + process $proc$libresoc.v:172217$10174 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$52$next[0:0]$10175 $1\dive_abs_ov32$52$next[0:0]$10176 + attribute \src "libresoc.v:172218.5-172218.29" + switch \initial + attribute \src "libresoc.v:172218.9-172218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov32$52$next[0:0]$10176 $2\dive_abs_ov32$52$next[0:0]$10177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov32$52$next[0:0]$10177 \dive_abs_ov32 + case + assign $2\dive_abs_ov32$52$next[0:0]$10177 \dive_abs_ov32$52 + end + case + assign $1\dive_abs_ov32$52$next[0:0]$10176 \dive_abs_ov32$52 + end + sync always + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10175 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179279$10599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179279$10599_Y + attribute \src "libresoc.v:172232.3-172246.6" + process $proc$libresoc.v:172232$10178 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$53$next[0:0]$10179 $1\dive_abs_ov64$53$next[0:0]$10180 + attribute \src "libresoc.v:172233.5-172233.29" + switch \initial + attribute \src "libresoc.v:172233.9-172233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov64$53$next[0:0]$10180 $2\dive_abs_ov64$53$next[0:0]$10181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov64$53$next[0:0]$10181 \dive_abs_ov64 + case + assign $2\dive_abs_ov64$53$next[0:0]$10181 \dive_abs_ov64$53 + end + case + assign $1\dive_abs_ov64$53$next[0:0]$10180 \dive_abs_ov64$53 + end + sync always + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10179 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179281$10601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179281$10601_Y + attribute \src "libresoc.v:172247.3-172261.6" + process $proc$libresoc.v:172247$10182 + assign { } { } + assign { } { } + assign $0\div_by_zero$54$next[0:0]$10183 $1\div_by_zero$54$next[0:0]$10184 + attribute \src "libresoc.v:172248.5-172248.29" + switch \initial + attribute \src "libresoc.v:172248.9-172248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_by_zero$54$next[0:0]$10184 $2\div_by_zero$54$next[0:0]$10185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\div_by_zero$54$next[0:0]$10185 \div_by_zero + case + assign $2\div_by_zero$54$next[0:0]$10185 \div_by_zero$54 + end + case + assign $1\div_by_zero$54$next[0:0]$10184 \div_by_zero$54 + end + sync always + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10183 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179283$10603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179283$10603_Y + attribute \src "libresoc.v:172262.3-172276.6" + process $proc$libresoc.v:172262$10186 + assign { } { } + assign { } { } + assign $0\dividend$68$next[127:0]$10187 $1\dividend$68$next[127:0]$10188 + attribute \src "libresoc.v:172263.5-172263.29" + switch \initial + attribute \src "libresoc.v:172263.9-172263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend$68$next[127:0]$10188 $2\dividend$68$next[127:0]$10189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend$68$next[127:0]$10189 \dividend + case + assign $2\dividend$68$next[127:0]$10189 \dividend$68 + end + case + assign $1\dividend$68$next[127:0]$10188 \dividend$68 + end + sync always + update \dividend$68$next $0\dividend$68$next[127:0]$10187 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179285$10605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179285$10605_Y + attribute \src "libresoc.v:172277.3-172291.6" + process $proc$libresoc.v:172277$10190 + assign { } { } + assign { } { } + assign $0\divisor_radicand$65$next[63:0]$10191 $1\divisor_radicand$65$next[63:0]$10192 + attribute \src "libresoc.v:172278.5-172278.29" + switch \initial + attribute \src "libresoc.v:172278.9-172278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_radicand$65$next[63:0]$10192 $2\divisor_radicand$65$next[63:0]$10193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_radicand$65$next[63:0]$10193 \divisor_radicand + case + assign $2\divisor_radicand$65$next[63:0]$10193 \divisor_radicand$65 + end + case + assign $1\divisor_radicand$65$next[63:0]$10192 \divisor_radicand$65 + end + sync always + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10191 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179286$10606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179286$10606_Y + attribute \src "libresoc.v:172292.3-172306.6" + process $proc$libresoc.v:172292$10194 + assign { } { } + assign { } { } + assign $0\operation$69$next[1:0]$10195 $1\operation$69$next[1:0]$10196 + attribute \src "libresoc.v:172293.5-172293.29" + switch \initial + attribute \src "libresoc.v:172293.9-172293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\operation$69$next[1:0]$10196 $2\operation$69$next[1:0]$10197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\operation$69$next[1:0]$10197 \operation + case + assign $2\operation$69$next[1:0]$10197 \operation$69 + end + case + assign $1\operation$69$next[1:0]$10196 \operation$69 + end + sync always + update \operation$69$next $0\operation$69$next[1:0]$10195 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179288$10608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179288$10608_Y - end - connect \$7 $not$libresoc.v:179273$10593_Y - connect \$12 $reduce_or$libresoc.v:179274$10594_Y - connect \$11 $not$libresoc.v:179275$10595_Y - connect \$16 $reduce_or$libresoc.v:179276$10596_Y - connect \$15 $not$libresoc.v:179277$10597_Y - connect \$1 $not$libresoc.v:179278$10598_Y - connect \$20 $reduce_or$libresoc.v:179279$10599_Y - connect \$19 $not$libresoc.v:179280$10600_Y - connect \$24 $reduce_or$libresoc.v:179281$10601_Y - connect \$23 $not$libresoc.v:179282$10602_Y - connect \$28 $reduce_or$libresoc.v:179283$10603_Y - connect \$27 $not$libresoc.v:179284$10604_Y - connect \$31 $reduce_or$libresoc.v:179285$10605_Y - connect \$4 $reduce_or$libresoc.v:179286$10606_Y - connect \$3 $not$libresoc.v:179287$10607_Y - connect \$8 $reduce_or$libresoc.v:179288$10608_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 + connect \$56 $sshl$libresoc.v:171909$10004_Y + connect \$55 $pos$libresoc.v:171910$10006_Y + connect \$59 $not$libresoc.v:171911$10007_Y + connect \$61 $ge$libresoc.v:171912$10008_Y + connect \$63 $and$libresoc.v:171913$10009_Y + connect \$66 $and$libresoc.v:171914$10010_Y + connect \p_ready_o \empty + connect \n_valid_o \$63 + connect \remainder \$55 + connect \quotient_root \div_state_next_o_dividend_quotient [63:0] + connect \div_by_zero$27 \div_by_zero$54 + connect \dive_abs_ov64$26 \dive_abs_ov64$53 + connect \dive_abs_ov32$25 \dive_abs_ov32$52 + connect \dividend_neg$24 \dividend_neg$51 + connect \divisor_neg$23 \divisor_neg$50 + connect \xer_so$22 \xer_so$49 + connect \rb$21 \rb$48 + connect \ra$20 \ra$47 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } + connect \muxid$1 \muxid$28 + connect \div_state_init_dividend \dividend end -attribute \src "libresoc.v:179304.1-179388.10" +attribute \src "libresoc.v:172326.1-173857.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" attribute \generator "nMigen" -module \ppick$158 - attribute \src "libresoc.v:179361.17-179361.91" - wire $not$libresoc.v:179361$10609_Y - attribute \src "libresoc.v:179363.18-179363.93" - wire $not$libresoc.v:179363$10611_Y - attribute \src "libresoc.v:179365.18-179365.93" - wire $not$libresoc.v:179365$10613_Y - attribute \src "libresoc.v:179366.17-179366.138" - wire width 8 $not$libresoc.v:179366$10614_Y - attribute \src "libresoc.v:179368.18-179368.93" - wire $not$libresoc.v:179368$10616_Y - attribute \src "libresoc.v:179370.18-179370.93" - wire $not$libresoc.v:179370$10618_Y - attribute \src "libresoc.v:179372.18-179372.93" - wire $not$libresoc.v:179372$10620_Y - attribute \src "libresoc.v:179375.17-179375.91" - wire $not$libresoc.v:179375$10623_Y - attribute \src "libresoc.v:179362.18-179362.116" - wire $reduce_or$libresoc.v:179362$10610_Y - attribute \src "libresoc.v:179364.18-179364.122" - wire $reduce_or$libresoc.v:179364$10612_Y - attribute \src "libresoc.v:179367.18-179367.128" - wire $reduce_or$libresoc.v:179367$10615_Y - attribute \src "libresoc.v:179369.18-179369.134" - wire $reduce_or$libresoc.v:179369$10617_Y - attribute \src "libresoc.v:179371.18-179371.140" - wire $reduce_or$libresoc.v:179371$10619_Y - attribute \src "libresoc.v:179373.18-179373.90" - wire $reduce_or$libresoc.v:179373$10621_Y - attribute \src "libresoc.v:179374.17-179374.103" - wire $reduce_or$libresoc.v:179374$10622_Y - attribute \src "libresoc.v:179376.17-179376.109" - wire $reduce_or$libresoc.v:179376$10624_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179361$10609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179361$10609_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179363$10611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179363$10611_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179365$10613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179365$10613_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179366$10614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179366$10614_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179368$10616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179368$10616_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179370$10618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179370$10618_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179372$10620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179372$10620_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179375$10623 +module \pipe_start + attribute \src "libresoc.v:173663.3-173675.6" + wire $0\div_by_zero$next[0:0]$10307 + attribute \src "libresoc.v:173449.3-173450.39" + wire $0\div_by_zero[0:0] + attribute \src "libresoc.v:173637.3-173649.6" + wire $0\dive_abs_ov32$next[0:0]$10301 + attribute \src "libresoc.v:173453.3-173454.43" + wire $0\dive_abs_ov32[0:0] + attribute \src "libresoc.v:173650.3-173662.6" + wire $0\dive_abs_ov64$next[0:0]$10304 + attribute \src "libresoc.v:173451.3-173452.43" + wire $0\dive_abs_ov64[0:0] + attribute \src "libresoc.v:173676.3-173688.6" + wire width 128 $0\dividend$next[127:0]$10310 + attribute \src "libresoc.v:173447.3-173448.33" + wire width 128 $0\dividend[127:0] + attribute \src "libresoc.v:173624.3-173636.6" + wire $0\dividend_neg$next[0:0]$10298 + attribute \src "libresoc.v:173455.3-173456.41" + wire $0\dividend_neg[0:0] + attribute \src "libresoc.v:173611.3-173623.6" + wire $0\divisor_neg$next[0:0]$10295 + attribute \src "libresoc.v:173457.3-173458.39" + wire $0\divisor_neg[0:0] + attribute \src "libresoc.v:173689.3-173701.6" + wire width 64 $0\divisor_radicand$next[63:0]$10313 + attribute \src "libresoc.v:173445.3-173446.49" + wire width 64 $0\divisor_radicand[63:0] + attribute \src "libresoc.v:172327.7-172327.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 4 $0\logical_op__data_len$next[3:0]$10326 + attribute \src "libresoc.v:173497.3-173498.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 13 $0\logical_op__fn_unit$next[12:0]$10327 + attribute \src "libresoc.v:173467.3-173468.55" + wire width 13 $0\logical_op__fn_unit[12:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$10328 + attribute \src "libresoc.v:173469.3-173470.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__imm_data__ok$next[0:0]$10329 + attribute \src "libresoc.v:173471.3-173472.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$10330 + attribute \src "libresoc.v:173485.3-173486.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 32 $0\logical_op__insn$next[31:0]$10331 + attribute \src "libresoc.v:173499.3-173500.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$10332 + attribute \src "libresoc.v:173465.3-173466.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__invert_in$next[0:0]$10333 + attribute \src "libresoc.v:173481.3-173482.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__invert_out$next[0:0]$10334 + attribute \src "libresoc.v:173487.3-173488.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__is_32bit$next[0:0]$10335 + attribute \src "libresoc.v:173493.3-173494.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__is_signed$next[0:0]$10336 + attribute \src "libresoc.v:173495.3-173496.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__oe__oe$next[0:0]$10337 + attribute \src "libresoc.v:173477.3-173478.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__oe__ok$next[0:0]$10338 + attribute \src "libresoc.v:173479.3-173480.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__output_carry$next[0:0]$10339 + attribute \src "libresoc.v:173491.3-173492.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__rc__ok$next[0:0]$10340 + attribute \src "libresoc.v:173475.3-173476.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__rc__rc$next[0:0]$10341 + attribute \src "libresoc.v:173473.3-173474.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__write_cr0$next[0:0]$10342 + attribute \src "libresoc.v:173489.3-173490.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $0\logical_op__zero_a$next[0:0]$10343 + attribute \src "libresoc.v:173483.3-173484.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "libresoc.v:173733.3-173745.6" + wire width 2 $0\muxid$next[1:0]$10323 + attribute \src "libresoc.v:173501.3-173502.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:173702.3-173714.6" + wire width 2 $0\operation$next[1:0]$10316 + attribute \src "libresoc.v:173443.3-173444.35" + wire width 2 $0\operation[1:0] + attribute \src "libresoc.v:173715.3-173732.6" + wire $0\r_busy$next[0:0]$10319 + attribute \src "libresoc.v:173503.3-173504.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:173788.3-173800.6" + wire width 64 $0\ra$next[63:0]$10369 + attribute \src "libresoc.v:173463.3-173464.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:173801.3-173813.6" + wire width 64 $0\rb$next[63:0]$10372 + attribute \src "libresoc.v:173461.3-173462.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:173814.3-173826.6" + wire $0\xer_so$next[0:0]$10375 + attribute \src "libresoc.v:173459.3-173460.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:173663.3-173675.6" + wire $1\div_by_zero$next[0:0]$10308 + attribute \src "libresoc.v:172336.7-172336.25" + wire $1\div_by_zero[0:0] + attribute \src "libresoc.v:173637.3-173649.6" + wire $1\dive_abs_ov32$next[0:0]$10302 + attribute \src "libresoc.v:172343.7-172343.27" + wire $1\dive_abs_ov32[0:0] + attribute \src "libresoc.v:173650.3-173662.6" + wire $1\dive_abs_ov64$next[0:0]$10305 + attribute \src "libresoc.v:172350.7-172350.27" + wire $1\dive_abs_ov64[0:0] + attribute \src "libresoc.v:173676.3-173688.6" + wire width 128 $1\dividend$next[127:0]$10311 + attribute \src "libresoc.v:172357.15-172357.63" + wire width 128 $1\dividend[127:0] + attribute \src "libresoc.v:173624.3-173636.6" + wire $1\dividend_neg$next[0:0]$10299 + attribute \src "libresoc.v:172364.7-172364.26" + wire $1\dividend_neg[0:0] + attribute \src "libresoc.v:173611.3-173623.6" + wire $1\divisor_neg$next[0:0]$10296 + attribute \src "libresoc.v:172371.7-172371.25" + wire $1\divisor_neg[0:0] + attribute \src "libresoc.v:173689.3-173701.6" + wire width 64 $1\divisor_radicand$next[63:0]$10314 + attribute \src "libresoc.v:172378.14-172378.53" + wire width 64 $1\divisor_radicand[63:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 4 $1\logical_op__data_len$next[3:0]$10344 + attribute \src "libresoc.v:172657.13-172657.40" + wire width 4 $1\logical_op__data_len[3:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 13 $1\logical_op__fn_unit$next[12:0]$10345 + attribute \src "libresoc.v:172680.14-172680.44" + wire width 13 $1\logical_op__fn_unit[12:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$10346 + attribute \src "libresoc.v:172717.14-172717.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__imm_data__ok$next[0:0]$10347 + attribute \src "libresoc.v:172726.7-172726.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$10348 + attribute \src "libresoc.v:172739.13-172739.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 32 $1\logical_op__insn$next[31:0]$10349 + attribute \src "libresoc.v:172756.14-172756.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$10350 + attribute \src "libresoc.v:172839.13-172839.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__invert_in$next[0:0]$10351 + attribute \src "libresoc.v:172996.7-172996.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__invert_out$next[0:0]$10352 + attribute \src "libresoc.v:173005.7-173005.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__is_32bit$next[0:0]$10353 + attribute \src "libresoc.v:173014.7-173014.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__is_signed$next[0:0]$10354 + attribute \src "libresoc.v:173023.7-173023.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__oe__oe$next[0:0]$10355 + attribute \src "libresoc.v:173032.7-173032.32" + wire $1\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__oe__ok$next[0:0]$10356 + attribute \src "libresoc.v:173041.7-173041.32" + wire $1\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__output_carry$next[0:0]$10357 + attribute \src "libresoc.v:173050.7-173050.38" + wire $1\logical_op__output_carry[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__rc__ok$next[0:0]$10358 + attribute \src "libresoc.v:173059.7-173059.32" + wire $1\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__rc__rc$next[0:0]$10359 + attribute \src "libresoc.v:173068.7-173068.32" + wire $1\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__write_cr0$next[0:0]$10360 + attribute \src "libresoc.v:173077.7-173077.35" + wire $1\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire $1\logical_op__zero_a$next[0:0]$10361 + attribute \src "libresoc.v:173086.7-173086.32" + wire $1\logical_op__zero_a[0:0] + attribute \src "libresoc.v:173733.3-173745.6" + wire width 2 $1\muxid$next[1:0]$10324 + attribute \src "libresoc.v:173095.13-173095.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:173702.3-173714.6" + wire width 2 $1\operation$next[1:0]$10317 + attribute \src "libresoc.v:173110.13-173110.29" + wire width 2 $1\operation[1:0] + attribute \src "libresoc.v:173715.3-173732.6" + wire $1\r_busy$next[0:0]$10320 + attribute \src "libresoc.v:173124.7-173124.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:173788.3-173800.6" + wire width 64 $1\ra$next[63:0]$10370 + attribute \src "libresoc.v:173129.14-173129.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:173801.3-173813.6" + wire width 64 $1\rb$next[63:0]$10373 + attribute \src "libresoc.v:173140.14-173140.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:173814.3-173826.6" + wire $1\xer_so$next[0:0]$10376 + attribute \src "libresoc.v:173435.7-173435.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:173746.3-173787.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$10362 + attribute \src "libresoc.v:173746.3-173787.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10363 + attribute \src "libresoc.v:173746.3-173787.6" + wire $2\logical_op__oe__oe$next[0:0]$10364 + attribute \src "libresoc.v:173746.3-173787.6" + wire $2\logical_op__oe__ok$next[0:0]$10365 + attribute \src "libresoc.v:173746.3-173787.6" + wire $2\logical_op__rc__ok$next[0:0]$10366 + attribute \src "libresoc.v:173746.3-173787.6" + wire $2\logical_op__rc__rc$next[0:0]$10367 + attribute \src "libresoc.v:173715.3-173732.6" + wire $2\r_busy$next[0:0]$10321 + attribute \src "libresoc.v:173442.18-173442.118" + wire $and$libresoc.v:173442$10262_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 output 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 output 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$next + attribute \src "libresoc.v:172327.7-172327.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$40 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_logical_op__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok$27 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$41 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$68 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 35 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 34 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \setup_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \setup_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \setup_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \setup_stage_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \setup_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \setup_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \setup_stage_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \setup_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \setup_stage_logical_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \setup_stage_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \setup_stage_logical_op__fn_unit$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \setup_stage_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \setup_stage_logical_op__imm_data__data$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \setup_stage_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \setup_stage_logical_op__input_carry$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \setup_stage_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \setup_stage_logical_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \setup_stage_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__invert_out$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__oe__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__write_cr0$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \setup_stage_logical_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \setup_stage_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \setup_stage_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \setup_stage_operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \setup_stage_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \setup_stage_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \setup_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \setup_stage_xer_so$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 57 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:173442$10262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179375$10623_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179362$10610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179362$10610_Y + connect \A \p_valid_i$65 + connect \B \p_ready_o + connect \Y $and$libresoc.v:173442$10262_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179364$10612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179364$10612_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:173505.14-173550.4" + cell \input$78 \input + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__data_len$18 \input_logical_op__data_len$40 + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$26 + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$27 + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 + connect \logical_op__insn \input_logical_op__insn + connect \logical_op__insn$19 \input_logical_op__insn$41 + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__invert_in$10 \input_logical_op__invert_in$32 + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__invert_out$13 \input_logical_op__invert_out$35 + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$23 + connect \ra \input_ra + connect \ra$20 \input_ra$42 + connect \rb \input_rb + connect \rb$21 \input_rb$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$44 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179367$10615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179367$10615_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:173551.10-173554.4" + cell \n$77 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179369$10617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179369$10617_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:173555.10-173558.4" + cell \p$76 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179371$10619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179371$10619_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:173559.15-173610.4" + cell \setup_stage \setup_stage + connect \div_by_zero \setup_stage_div_by_zero + connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 + connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 + connect \dividend \setup_stage_dividend + connect \dividend_neg \setup_stage_dividend_neg + connect \divisor_neg \setup_stage_divisor_neg + connect \divisor_radicand \setup_stage_divisor_radicand + connect \logical_op__data_len \setup_stage_logical_op__data_len + connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 + connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 + connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 + connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 + connect \logical_op__input_carry \setup_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 + connect \logical_op__insn \setup_stage_logical_op__insn + connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 + connect \logical_op__insn_type \setup_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 + connect \logical_op__invert_in \setup_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 + connect \logical_op__invert_out \setup_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 + connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 + connect \logical_op__is_signed \setup_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 + connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 + connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 + connect \logical_op__output_carry \setup_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 + connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 + connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 + connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 + connect \logical_op__zero_a \setup_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 + connect \muxid \setup_stage_muxid + connect \muxid$1 \setup_stage_muxid$45 + connect \operation \setup_stage_operation + connect \ra \setup_stage_ra + connect \rb \setup_stage_rb + connect \xer_so \setup_stage_xer_so + connect \xer_so$20 \setup_stage_xer_so$64 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179373$10621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179373$10621_Y + attribute \src "libresoc.v:172327.7-172327.20" + process $proc$libresoc.v:172327$10377 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179374$10622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179374$10622_Y + attribute \src "libresoc.v:172336.7-172336.25" + process $proc$libresoc.v:172336$10378 + assign { } { } + assign $1\div_by_zero[0:0] 1'0 + sync always + sync init + update \div_by_zero $1\div_by_zero[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179376$10624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179376$10624_Y - end - connect \$7 $not$libresoc.v:179361$10609_Y - connect \$12 $reduce_or$libresoc.v:179362$10610_Y - connect \$11 $not$libresoc.v:179363$10611_Y - connect \$16 $reduce_or$libresoc.v:179364$10612_Y - connect \$15 $not$libresoc.v:179365$10613_Y - connect \$1 $not$libresoc.v:179366$10614_Y - connect \$20 $reduce_or$libresoc.v:179367$10615_Y - connect \$19 $not$libresoc.v:179368$10616_Y - connect \$24 $reduce_or$libresoc.v:179369$10617_Y - connect \$23 $not$libresoc.v:179370$10618_Y - connect \$28 $reduce_or$libresoc.v:179371$10619_Y - connect \$27 $not$libresoc.v:179372$10620_Y - connect \$31 $reduce_or$libresoc.v:179373$10621_Y - connect \$4 $reduce_or$libresoc.v:179374$10622_Y - connect \$3 $not$libresoc.v:179375$10623_Y - connect \$8 $reduce_or$libresoc.v:179376$10624_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:179392.1-179476.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$160 - attribute \src "libresoc.v:179449.17-179449.91" - wire $not$libresoc.v:179449$10625_Y - attribute \src "libresoc.v:179451.18-179451.93" - wire $not$libresoc.v:179451$10627_Y - attribute \src "libresoc.v:179453.18-179453.93" - wire $not$libresoc.v:179453$10629_Y - attribute \src "libresoc.v:179454.17-179454.138" - wire width 8 $not$libresoc.v:179454$10630_Y - attribute \src "libresoc.v:179456.18-179456.93" - wire $not$libresoc.v:179456$10632_Y - attribute \src "libresoc.v:179458.18-179458.93" - wire $not$libresoc.v:179458$10634_Y - attribute \src "libresoc.v:179460.18-179460.93" - wire $not$libresoc.v:179460$10636_Y - attribute \src "libresoc.v:179463.17-179463.91" - wire $not$libresoc.v:179463$10639_Y - attribute \src "libresoc.v:179450.18-179450.116" - wire $reduce_or$libresoc.v:179450$10626_Y - attribute \src "libresoc.v:179452.18-179452.122" - wire $reduce_or$libresoc.v:179452$10628_Y - attribute \src "libresoc.v:179455.18-179455.128" - wire $reduce_or$libresoc.v:179455$10631_Y - attribute \src "libresoc.v:179457.18-179457.134" - wire $reduce_or$libresoc.v:179457$10633_Y - attribute \src "libresoc.v:179459.18-179459.140" - wire $reduce_or$libresoc.v:179459$10635_Y - attribute \src "libresoc.v:179461.18-179461.90" - wire $reduce_or$libresoc.v:179461$10637_Y - attribute \src "libresoc.v:179462.17-179462.103" - wire $reduce_or$libresoc.v:179462$10638_Y - attribute \src "libresoc.v:179464.17-179464.109" - wire $reduce_or$libresoc.v:179464$10640_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179449$10625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179449$10625_Y + attribute \src "libresoc.v:172343.7-172343.27" + process $proc$libresoc.v:172343$10379 + assign { } { } + assign $1\dive_abs_ov32[0:0] 1'0 + sync always + sync init + update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179451$10627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179451$10627_Y + attribute \src "libresoc.v:172350.7-172350.27" + process $proc$libresoc.v:172350$10380 + assign { } { } + assign $1\dive_abs_ov64[0:0] 1'0 + sync always + sync init + update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179453$10629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179453$10629_Y + attribute \src "libresoc.v:172357.15-172357.63" + process $proc$libresoc.v:172357$10381 + assign { } { } + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend $1\dividend[127:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179454$10630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179454$10630_Y + attribute \src "libresoc.v:172364.7-172364.26" + process $proc$libresoc.v:172364$10382 + assign { } { } + assign $1\dividend_neg[0:0] 1'0 + sync always + sync init + update \dividend_neg $1\dividend_neg[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179456$10632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179456$10632_Y + attribute \src "libresoc.v:172371.7-172371.25" + process $proc$libresoc.v:172371$10383 + assign { } { } + assign $1\divisor_neg[0:0] 1'0 + sync always + sync init + update \divisor_neg $1\divisor_neg[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179458$10634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179458$10634_Y + attribute \src "libresoc.v:172378.14-172378.53" + process $proc$libresoc.v:172378$10384 + assign { } { } + assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand $1\divisor_radicand[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179460$10636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179460$10636_Y + attribute \src "libresoc.v:172657.13-172657.40" + process $proc$libresoc.v:172657$10385 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179463$10639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179463$10639_Y + attribute \src "libresoc.v:172680.14-172680.44" + process $proc$libresoc.v:172680$10386 + assign { } { } + assign $1\logical_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[12:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179450$10626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179450$10626_Y + attribute \src "libresoc.v:172717.14-172717.63" + process $proc$libresoc.v:172717$10387 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179452$10628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179452$10628_Y + attribute \src "libresoc.v:172726.7-172726.38" + process $proc$libresoc.v:172726$10388 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179455$10631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179455$10631_Y + attribute \src "libresoc.v:172739.13-172739.43" + process $proc$libresoc.v:172739$10389 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179457$10633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179457$10633_Y + attribute \src "libresoc.v:172756.14-172756.38" + process $proc$libresoc.v:172756$10390 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179459$10635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179459$10635_Y + attribute \src "libresoc.v:172839.13-172839.42" + process $proc$libresoc.v:172839$10391 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179461$10637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179461$10637_Y + attribute \src "libresoc.v:172996.7-172996.35" + process $proc$libresoc.v:172996$10392 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179462$10638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179462$10638_Y + attribute \src "libresoc.v:173005.7-173005.36" + process $proc$libresoc.v:173005$10393 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179464$10640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179464$10640_Y - end - connect \$7 $not$libresoc.v:179449$10625_Y - connect \$12 $reduce_or$libresoc.v:179450$10626_Y - connect \$11 $not$libresoc.v:179451$10627_Y - connect \$16 $reduce_or$libresoc.v:179452$10628_Y - connect \$15 $not$libresoc.v:179453$10629_Y - connect \$1 $not$libresoc.v:179454$10630_Y - connect \$20 $reduce_or$libresoc.v:179455$10631_Y - connect \$19 $not$libresoc.v:179456$10632_Y - connect \$24 $reduce_or$libresoc.v:179457$10633_Y - connect \$23 $not$libresoc.v:179458$10634_Y - connect \$28 $reduce_or$libresoc.v:179459$10635_Y - connect \$27 $not$libresoc.v:179460$10636_Y - connect \$31 $reduce_or$libresoc.v:179461$10637_Y - connect \$4 $reduce_or$libresoc.v:179462$10638_Y - connect \$3 $not$libresoc.v:179463$10639_Y - connect \$8 $reduce_or$libresoc.v:179464$10640_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:179480.1-179564.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$167 - attribute \src "libresoc.v:179537.17-179537.91" - wire $not$libresoc.v:179537$10641_Y - attribute \src "libresoc.v:179539.18-179539.93" - wire $not$libresoc.v:179539$10643_Y - attribute \src "libresoc.v:179541.18-179541.93" - wire $not$libresoc.v:179541$10645_Y - attribute \src "libresoc.v:179542.17-179542.138" - wire width 8 $not$libresoc.v:179542$10646_Y - attribute \src "libresoc.v:179544.18-179544.93" - wire $not$libresoc.v:179544$10648_Y - attribute \src "libresoc.v:179546.18-179546.93" - wire $not$libresoc.v:179546$10650_Y - attribute \src "libresoc.v:179548.18-179548.93" - wire $not$libresoc.v:179548$10652_Y - attribute \src "libresoc.v:179551.17-179551.91" - wire $not$libresoc.v:179551$10655_Y - attribute \src "libresoc.v:179538.18-179538.116" - wire $reduce_or$libresoc.v:179538$10642_Y - attribute \src "libresoc.v:179540.18-179540.122" - wire $reduce_or$libresoc.v:179540$10644_Y - attribute \src "libresoc.v:179543.18-179543.128" - wire $reduce_or$libresoc.v:179543$10647_Y - attribute \src "libresoc.v:179545.18-179545.134" - wire $reduce_or$libresoc.v:179545$10649_Y - attribute \src "libresoc.v:179547.18-179547.140" - wire $reduce_or$libresoc.v:179547$10651_Y - attribute \src "libresoc.v:179549.18-179549.90" - wire $reduce_or$libresoc.v:179549$10653_Y - attribute \src "libresoc.v:179550.17-179550.103" - wire $reduce_or$libresoc.v:179550$10654_Y - attribute \src "libresoc.v:179552.17-179552.109" - wire $reduce_or$libresoc.v:179552$10656_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179537$10641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179537$10641_Y + attribute \src "libresoc.v:173014.7-173014.34" + process $proc$libresoc.v:173014$10394 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179539$10643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179539$10643_Y + attribute \src "libresoc.v:173023.7-173023.35" + process $proc$libresoc.v:173023$10395 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179541$10645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179541$10645_Y + attribute \src "libresoc.v:173032.7-173032.32" + process $proc$libresoc.v:173032$10396 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179542$10646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179542$10646_Y + attribute \src "libresoc.v:173041.7-173041.32" + process $proc$libresoc.v:173041$10397 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179544$10648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179544$10648_Y + attribute \src "libresoc.v:173050.7-173050.38" + process $proc$libresoc.v:173050$10398 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179546$10650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179546$10650_Y + attribute \src "libresoc.v:173059.7-173059.32" + process $proc$libresoc.v:173059$10399 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179548$10652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179548$10652_Y + attribute \src "libresoc.v:173068.7-173068.32" + process $proc$libresoc.v:173068$10400 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179551$10655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179551$10655_Y + attribute \src "libresoc.v:173077.7-173077.35" + process $proc$libresoc.v:173077$10401 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179538$10642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179538$10642_Y + attribute \src "libresoc.v:173086.7-173086.32" + process $proc$libresoc.v:173086$10402 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179540$10644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179540$10644_Y + attribute \src "libresoc.v:173095.13-173095.25" + process $proc$libresoc.v:173095$10403 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179543$10647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179543$10647_Y + attribute \src "libresoc.v:173110.13-173110.29" + process $proc$libresoc.v:173110$10404 + assign { } { } + assign $1\operation[1:0] 2'00 + sync always + sync init + update \operation $1\operation[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179545$10649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179545$10649_Y + attribute \src "libresoc.v:173124.7-173124.20" + process $proc$libresoc.v:173124$10405 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179547$10651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179547$10651_Y + attribute \src "libresoc.v:173129.14-173129.39" + process $proc$libresoc.v:173129$10406 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179549$10653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179549$10653_Y + attribute \src "libresoc.v:173140.14-173140.39" + process $proc$libresoc.v:173140$10407 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179550$10654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179550$10654_Y + attribute \src "libresoc.v:173435.7-173435.20" + process $proc$libresoc.v:173435$10408 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179552$10656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179552$10656_Y - end - connect \$7 $not$libresoc.v:179537$10641_Y - connect \$12 $reduce_or$libresoc.v:179538$10642_Y - connect \$11 $not$libresoc.v:179539$10643_Y - connect \$16 $reduce_or$libresoc.v:179540$10644_Y - connect \$15 $not$libresoc.v:179541$10645_Y - connect \$1 $not$libresoc.v:179542$10646_Y - connect \$20 $reduce_or$libresoc.v:179543$10647_Y - connect \$19 $not$libresoc.v:179544$10648_Y - connect \$24 $reduce_or$libresoc.v:179545$10649_Y - connect \$23 $not$libresoc.v:179546$10650_Y - connect \$28 $reduce_or$libresoc.v:179547$10651_Y - connect \$27 $not$libresoc.v:179548$10652_Y - connect \$31 $reduce_or$libresoc.v:179549$10653_Y - connect \$4 $reduce_or$libresoc.v:179550$10654_Y - connect \$3 $not$libresoc.v:179551$10655_Y - connect \$8 $reduce_or$libresoc.v:179552$10656_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:179568.1-179652.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$169 - attribute \src "libresoc.v:179625.17-179625.91" - wire $not$libresoc.v:179625$10657_Y - attribute \src "libresoc.v:179627.18-179627.93" - wire $not$libresoc.v:179627$10659_Y - attribute \src "libresoc.v:179629.18-179629.93" - wire $not$libresoc.v:179629$10661_Y - attribute \src "libresoc.v:179630.17-179630.138" - wire width 8 $not$libresoc.v:179630$10662_Y - attribute \src "libresoc.v:179632.18-179632.93" - wire $not$libresoc.v:179632$10664_Y - attribute \src "libresoc.v:179634.18-179634.93" - wire $not$libresoc.v:179634$10666_Y - attribute \src "libresoc.v:179636.18-179636.93" - wire $not$libresoc.v:179636$10668_Y - attribute \src "libresoc.v:179639.17-179639.91" - wire $not$libresoc.v:179639$10671_Y - attribute \src "libresoc.v:179626.18-179626.116" - wire $reduce_or$libresoc.v:179626$10658_Y - attribute \src "libresoc.v:179628.18-179628.122" - wire $reduce_or$libresoc.v:179628$10660_Y - attribute \src "libresoc.v:179631.18-179631.128" - wire $reduce_or$libresoc.v:179631$10663_Y - attribute \src "libresoc.v:179633.18-179633.134" - wire $reduce_or$libresoc.v:179633$10665_Y - attribute \src "libresoc.v:179635.18-179635.140" - wire $reduce_or$libresoc.v:179635$10667_Y - attribute \src "libresoc.v:179637.18-179637.90" - wire $reduce_or$libresoc.v:179637$10669_Y - attribute \src "libresoc.v:179638.17-179638.103" - wire $reduce_or$libresoc.v:179638$10670_Y - attribute \src "libresoc.v:179640.17-179640.109" - wire $reduce_or$libresoc.v:179640$10672_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179625$10657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179625$10657_Y + attribute \src "libresoc.v:173443.3-173444.35" + process $proc$libresoc.v:173443$10263 + assign { } { } + assign $0\operation[1:0] \operation$next + sync posedge \coresync_clk + update \operation $0\operation[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179627$10659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179627$10659_Y + attribute \src "libresoc.v:173445.3-173446.49" + process $proc$libresoc.v:173445$10264 + assign { } { } + assign $0\divisor_radicand[63:0] \divisor_radicand$next + sync posedge \coresync_clk + update \divisor_radicand $0\divisor_radicand[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179629$10661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179629$10661_Y + attribute \src "libresoc.v:173447.3-173448.33" + process $proc$libresoc.v:173447$10265 + assign { } { } + assign $0\dividend[127:0] \dividend$next + sync posedge \coresync_clk + update \dividend $0\dividend[127:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179630$10662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179630$10662_Y + attribute \src "libresoc.v:173449.3-173450.39" + process $proc$libresoc.v:173449$10266 + assign { } { } + assign $0\div_by_zero[0:0] \div_by_zero$next + sync posedge \coresync_clk + update \div_by_zero $0\div_by_zero[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179632$10664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179632$10664_Y + attribute \src "libresoc.v:173451.3-173452.43" + process $proc$libresoc.v:173451$10267 + assign { } { } + assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next + sync posedge \coresync_clk + update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179634$10666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179634$10666_Y + attribute \src "libresoc.v:173453.3-173454.43" + process $proc$libresoc.v:173453$10268 + assign { } { } + assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next + sync posedge \coresync_clk + update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179636$10668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179636$10668_Y + attribute \src "libresoc.v:173455.3-173456.41" + process $proc$libresoc.v:173455$10269 + assign { } { } + assign $0\dividend_neg[0:0] \dividend_neg$next + sync posedge \coresync_clk + update \dividend_neg $0\dividend_neg[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179639$10671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179639$10671_Y + attribute \src "libresoc.v:173457.3-173458.39" + process $proc$libresoc.v:173457$10270 + assign { } { } + assign $0\divisor_neg[0:0] \divisor_neg$next + sync posedge \coresync_clk + update \divisor_neg $0\divisor_neg[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179626$10658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179626$10658_Y + attribute \src "libresoc.v:173459.3-173460.29" + process $proc$libresoc.v:173459$10271 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179628$10660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179628$10660_Y + attribute \src "libresoc.v:173461.3-173462.21" + process $proc$libresoc.v:173461$10272 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179631$10663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179631$10663_Y + attribute \src "libresoc.v:173463.3-173464.21" + process $proc$libresoc.v:173463$10273 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179633$10665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179633$10665_Y + attribute \src "libresoc.v:173465.3-173466.59" + process $proc$libresoc.v:173465$10274 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179635$10667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179635$10667_Y + attribute \src "libresoc.v:173467.3-173468.55" + process $proc$libresoc.v:173467$10275 + assign { } { } + assign $0\logical_op__fn_unit[12:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[12:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179637$10669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179637$10669_Y + attribute \src "libresoc.v:173469.3-173470.69" + process $proc$libresoc.v:173469$10276 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179638$10670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179638$10670_Y + attribute \src "libresoc.v:173471.3-173472.65" + process $proc$libresoc.v:173471$10277 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179640$10672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179640$10672_Y - end - connect \$7 $not$libresoc.v:179625$10657_Y - connect \$12 $reduce_or$libresoc.v:179626$10658_Y - connect \$11 $not$libresoc.v:179627$10659_Y - connect \$16 $reduce_or$libresoc.v:179628$10660_Y - connect \$15 $not$libresoc.v:179629$10661_Y - connect \$1 $not$libresoc.v:179630$10662_Y - connect \$20 $reduce_or$libresoc.v:179631$10663_Y - connect \$19 $not$libresoc.v:179632$10664_Y - connect \$24 $reduce_or$libresoc.v:179633$10665_Y - connect \$23 $not$libresoc.v:179634$10666_Y - connect \$28 $reduce_or$libresoc.v:179635$10667_Y - connect \$27 $not$libresoc.v:179636$10668_Y - connect \$31 $reduce_or$libresoc.v:179637$10669_Y - connect \$4 $reduce_or$libresoc.v:179638$10670_Y - connect \$3 $not$libresoc.v:179639$10671_Y - connect \$8 $reduce_or$libresoc.v:179640$10672_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:179656.1-179740.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$174 - attribute \src "libresoc.v:179713.17-179713.91" - wire $not$libresoc.v:179713$10673_Y - attribute \src "libresoc.v:179715.18-179715.93" - wire $not$libresoc.v:179715$10675_Y - attribute \src "libresoc.v:179717.18-179717.93" - wire $not$libresoc.v:179717$10677_Y - attribute \src "libresoc.v:179718.17-179718.138" - wire width 8 $not$libresoc.v:179718$10678_Y - attribute \src "libresoc.v:179720.18-179720.93" - wire $not$libresoc.v:179720$10680_Y - attribute \src "libresoc.v:179722.18-179722.93" - wire $not$libresoc.v:179722$10682_Y - attribute \src "libresoc.v:179724.18-179724.93" - wire $not$libresoc.v:179724$10684_Y - attribute \src "libresoc.v:179727.17-179727.91" - wire $not$libresoc.v:179727$10687_Y - attribute \src "libresoc.v:179714.18-179714.116" - wire $reduce_or$libresoc.v:179714$10674_Y - attribute \src "libresoc.v:179716.18-179716.122" - wire $reduce_or$libresoc.v:179716$10676_Y - attribute \src "libresoc.v:179719.18-179719.128" - wire $reduce_or$libresoc.v:179719$10679_Y - attribute \src "libresoc.v:179721.18-179721.134" - wire $reduce_or$libresoc.v:179721$10681_Y - attribute \src "libresoc.v:179723.18-179723.140" - wire $reduce_or$libresoc.v:179723$10683_Y - attribute \src "libresoc.v:179725.18-179725.90" - wire $reduce_or$libresoc.v:179725$10685_Y - attribute \src "libresoc.v:179726.17-179726.103" - wire $reduce_or$libresoc.v:179726$10686_Y - attribute \src "libresoc.v:179728.17-179728.109" - wire $reduce_or$libresoc.v:179728$10688_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179713$10673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179713$10673_Y + attribute \src "libresoc.v:173473.3-173474.53" + process $proc$libresoc.v:173473$10278 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179715$10675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179715$10675_Y + attribute \src "libresoc.v:173475.3-173476.53" + process $proc$libresoc.v:173475$10279 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179717$10677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179717$10677_Y + attribute \src "libresoc.v:173477.3-173478.53" + process $proc$libresoc.v:173477$10280 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179718$10678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179718$10678_Y + attribute \src "libresoc.v:173479.3-173480.53" + process $proc$libresoc.v:173479$10281 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179720$10680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179720$10680_Y + attribute \src "libresoc.v:173481.3-173482.59" + process $proc$libresoc.v:173481$10282 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179722$10682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179722$10682_Y + attribute \src "libresoc.v:173483.3-173484.53" + process $proc$libresoc.v:173483$10283 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179724$10684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179724$10684_Y + attribute \src "libresoc.v:173485.3-173486.63" + process $proc$libresoc.v:173485$10284 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179727$10687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179727$10687_Y + attribute \src "libresoc.v:173487.3-173488.61" + process $proc$libresoc.v:173487$10285 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179714$10674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179714$10674_Y + attribute \src "libresoc.v:173489.3-173490.59" + process $proc$libresoc.v:173489$10286 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179716$10676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179716$10676_Y + attribute \src "libresoc.v:173491.3-173492.65" + process $proc$libresoc.v:173491$10287 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179719$10679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179719$10679_Y + attribute \src "libresoc.v:173493.3-173494.57" + process $proc$libresoc.v:173493$10288 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179721$10681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179721$10681_Y + attribute \src "libresoc.v:173495.3-173496.59" + process $proc$libresoc.v:173495$10289 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179723$10683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179723$10683_Y + attribute \src "libresoc.v:173497.3-173498.57" + process $proc$libresoc.v:173497$10290 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179725$10685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179725$10685_Y + attribute \src "libresoc.v:173499.3-173500.49" + process $proc$libresoc.v:173499$10291 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179726$10686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179726$10686_Y + attribute \src "libresoc.v:173501.3-173502.27" + process $proc$libresoc.v:173501$10292 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179728$10688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179728$10688_Y - end - connect \$7 $not$libresoc.v:179713$10673_Y - connect \$12 $reduce_or$libresoc.v:179714$10674_Y - connect \$11 $not$libresoc.v:179715$10675_Y - connect \$16 $reduce_or$libresoc.v:179716$10676_Y - connect \$15 $not$libresoc.v:179717$10677_Y - connect \$1 $not$libresoc.v:179718$10678_Y - connect \$20 $reduce_or$libresoc.v:179719$10679_Y - connect \$19 $not$libresoc.v:179720$10680_Y - connect \$24 $reduce_or$libresoc.v:179721$10681_Y - connect \$23 $not$libresoc.v:179722$10682_Y - connect \$28 $reduce_or$libresoc.v:179723$10683_Y - connect \$27 $not$libresoc.v:179724$10684_Y - connect \$31 $reduce_or$libresoc.v:179725$10685_Y - connect \$4 $reduce_or$libresoc.v:179726$10686_Y - connect \$3 $not$libresoc.v:179727$10687_Y - connect \$8 $reduce_or$libresoc.v:179728$10688_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:179744.1-179828.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$176 - attribute \src "libresoc.v:179801.17-179801.91" - wire $not$libresoc.v:179801$10689_Y - attribute \src "libresoc.v:179803.18-179803.93" - wire $not$libresoc.v:179803$10691_Y - attribute \src "libresoc.v:179805.18-179805.93" - wire $not$libresoc.v:179805$10693_Y - attribute \src "libresoc.v:179806.17-179806.138" - wire width 8 $not$libresoc.v:179806$10694_Y - attribute \src "libresoc.v:179808.18-179808.93" - wire $not$libresoc.v:179808$10696_Y - attribute \src "libresoc.v:179810.18-179810.93" - wire $not$libresoc.v:179810$10698_Y - attribute \src "libresoc.v:179812.18-179812.93" - wire $not$libresoc.v:179812$10700_Y - attribute \src "libresoc.v:179815.17-179815.91" - wire $not$libresoc.v:179815$10703_Y - attribute \src "libresoc.v:179802.18-179802.116" - wire $reduce_or$libresoc.v:179802$10690_Y - attribute \src "libresoc.v:179804.18-179804.122" - wire $reduce_or$libresoc.v:179804$10692_Y - attribute \src "libresoc.v:179807.18-179807.128" - wire $reduce_or$libresoc.v:179807$10695_Y - attribute \src "libresoc.v:179809.18-179809.134" - wire $reduce_or$libresoc.v:179809$10697_Y - attribute \src "libresoc.v:179811.18-179811.140" - wire $reduce_or$libresoc.v:179811$10699_Y - attribute \src "libresoc.v:179813.18-179813.90" - wire $reduce_or$libresoc.v:179813$10701_Y - attribute \src "libresoc.v:179814.17-179814.103" - wire $reduce_or$libresoc.v:179814$10702_Y - attribute \src "libresoc.v:179816.17-179816.109" - wire $reduce_or$libresoc.v:179816$10704_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179801$10689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179801$10689_Y + attribute \src "libresoc.v:173503.3-173504.29" + process $proc$libresoc.v:173503$10293 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179803$10691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179803$10691_Y + attribute \src "libresoc.v:173611.3-173623.6" + process $proc$libresoc.v:173611$10294 + assign { } { } + assign { } { } + assign $0\divisor_neg$next[0:0]$10295 $1\divisor_neg$next[0:0]$10296 + attribute \src "libresoc.v:173612.5-173612.29" + switch \initial + attribute \src "libresoc.v:173612.9-173612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_neg$next[0:0]$10296 \divisor_neg$92 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_neg$next[0:0]$10296 \divisor_neg$92 + case + assign $1\divisor_neg$next[0:0]$10296 \divisor_neg + end + sync always + update \divisor_neg$next $0\divisor_neg$next[0:0]$10295 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179805$10693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179805$10693_Y + attribute \src "libresoc.v:173624.3-173636.6" + process $proc$libresoc.v:173624$10297 + assign { } { } + assign { } { } + assign $0\dividend_neg$next[0:0]$10298 $1\dividend_neg$next[0:0]$10299 + attribute \src "libresoc.v:173625.5-173625.29" + switch \initial + attribute \src "libresoc.v:173625.9-173625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend_neg$next[0:0]$10299 \dividend_neg$93 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend_neg$next[0:0]$10299 \dividend_neg$93 + case + assign $1\dividend_neg$next[0:0]$10299 \dividend_neg + end + sync always + update \dividend_neg$next $0\dividend_neg$next[0:0]$10298 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179806$10694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179806$10694_Y + attribute \src "libresoc.v:173637.3-173649.6" + process $proc$libresoc.v:173637$10300 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$next[0:0]$10301 $1\dive_abs_ov32$next[0:0]$10302 + attribute \src "libresoc.v:173638.5-173638.29" + switch \initial + attribute \src "libresoc.v:173638.9-173638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$10302 \dive_abs_ov32$94 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$10302 \dive_abs_ov32$94 + case + assign $1\dive_abs_ov32$next[0:0]$10302 \dive_abs_ov32 + end + sync always + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10301 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179808$10696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179808$10696_Y + attribute \src "libresoc.v:173650.3-173662.6" + process $proc$libresoc.v:173650$10303 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$next[0:0]$10304 $1\dive_abs_ov64$next[0:0]$10305 + attribute \src "libresoc.v:173651.5-173651.29" + switch \initial + attribute \src "libresoc.v:173651.9-173651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$10305 \dive_abs_ov64$95 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$10305 \dive_abs_ov64$95 + case + assign $1\dive_abs_ov64$next[0:0]$10305 \dive_abs_ov64 + end + sync always + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10304 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179810$10698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179810$10698_Y + attribute \src "libresoc.v:173663.3-173675.6" + process $proc$libresoc.v:173663$10306 + assign { } { } + assign { } { } + assign $0\div_by_zero$next[0:0]$10307 $1\div_by_zero$next[0:0]$10308 + attribute \src "libresoc.v:173664.5-173664.29" + switch \initial + attribute \src "libresoc.v:173664.9-173664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\div_by_zero$next[0:0]$10308 \div_by_zero$96 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\div_by_zero$next[0:0]$10308 \div_by_zero$96 + case + assign $1\div_by_zero$next[0:0]$10308 \div_by_zero + end + sync always + update \div_by_zero$next $0\div_by_zero$next[0:0]$10307 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179812$10700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179812$10700_Y + attribute \src "libresoc.v:173676.3-173688.6" + process $proc$libresoc.v:173676$10309 + assign { } { } + assign { } { } + assign $0\dividend$next[127:0]$10310 $1\dividend$next[127:0]$10311 + attribute \src "libresoc.v:173677.5-173677.29" + switch \initial + attribute \src "libresoc.v:173677.9-173677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend$next[127:0]$10311 \dividend$97 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend$next[127:0]$10311 \dividend$97 + case + assign $1\dividend$next[127:0]$10311 \dividend + end + sync always + update \dividend$next $0\dividend$next[127:0]$10310 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179815$10703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179815$10703_Y + attribute \src "libresoc.v:173689.3-173701.6" + process $proc$libresoc.v:173689$10312 + assign { } { } + assign { } { } + assign $0\divisor_radicand$next[63:0]$10313 $1\divisor_radicand$next[63:0]$10314 + attribute \src "libresoc.v:173690.5-173690.29" + switch \initial + attribute \src "libresoc.v:173690.9-173690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_radicand$next[63:0]$10314 \divisor_radicand$98 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_radicand$next[63:0]$10314 \divisor_radicand$98 + case + assign $1\divisor_radicand$next[63:0]$10314 \divisor_radicand + end + sync always + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10313 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179802$10690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179802$10690_Y + attribute \src "libresoc.v:173702.3-173714.6" + process $proc$libresoc.v:173702$10315 + assign { } { } + assign { } { } + assign $0\operation$next[1:0]$10316 $1\operation$next[1:0]$10317 + attribute \src "libresoc.v:173703.5-173703.29" + switch \initial + attribute \src "libresoc.v:173703.9-173703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\operation$next[1:0]$10317 \operation$99 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\operation$next[1:0]$10317 \operation$99 + case + assign $1\operation$next[1:0]$10317 \operation + end + sync always + update \operation$next $0\operation$next[1:0]$10316 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179804$10692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179804$10692_Y + attribute \src "libresoc.v:173715.3-173732.6" + process $proc$libresoc.v:173715$10318 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$10319 $2\r_busy$next[0:0]$10321 + attribute \src "libresoc.v:173716.5-173716.29" + switch \initial + attribute \src "libresoc.v:173716.9-173716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$10320 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$10320 1'0 + case + assign $1\r_busy$next[0:0]$10320 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$10321 1'0 + case + assign $2\r_busy$next[0:0]$10321 $1\r_busy$next[0:0]$10320 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$10319 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179807$10695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179807$10695_Y + attribute \src "libresoc.v:173733.3-173745.6" + process $proc$libresoc.v:173733$10322 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$10323 $1\muxid$next[1:0]$10324 + attribute \src "libresoc.v:173734.5-173734.29" + switch \initial + attribute \src "libresoc.v:173734.9-173734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$10324 \muxid$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$10324 \muxid$68 + case + assign $1\muxid$next[1:0]$10324 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$10323 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179809$10697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179809$10697_Y + attribute \src "libresoc.v:173746.3-173787.6" + process $proc$libresoc.v:173746$10325 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$10326 $1\logical_op__data_len$next[3:0]$10344 + assign $0\logical_op__fn_unit$next[12:0]$10327 $1\logical_op__fn_unit$next[12:0]$10345 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$10330 $1\logical_op__input_carry$next[1:0]$10348 + assign $0\logical_op__insn$next[31:0]$10331 $1\logical_op__insn$next[31:0]$10349 + assign $0\logical_op__insn_type$next[6:0]$10332 $1\logical_op__insn_type$next[6:0]$10350 + assign $0\logical_op__invert_in$next[0:0]$10333 $1\logical_op__invert_in$next[0:0]$10351 + assign $0\logical_op__invert_out$next[0:0]$10334 $1\logical_op__invert_out$next[0:0]$10352 + assign $0\logical_op__is_32bit$next[0:0]$10335 $1\logical_op__is_32bit$next[0:0]$10353 + assign $0\logical_op__is_signed$next[0:0]$10336 $1\logical_op__is_signed$next[0:0]$10354 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$10339 $1\logical_op__output_carry$next[0:0]$10357 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$10342 $1\logical_op__write_cr0$next[0:0]$10360 + assign $0\logical_op__zero_a$next[0:0]$10343 $1\logical_op__zero_a$next[0:0]$10361 + assign $0\logical_op__imm_data__data$next[63:0]$10328 $2\logical_op__imm_data__data$next[63:0]$10362 + assign $0\logical_op__imm_data__ok$next[0:0]$10329 $2\logical_op__imm_data__ok$next[0:0]$10363 + assign $0\logical_op__oe__oe$next[0:0]$10337 $2\logical_op__oe__oe$next[0:0]$10364 + assign $0\logical_op__oe__ok$next[0:0]$10338 $2\logical_op__oe__ok$next[0:0]$10365 + assign $0\logical_op__rc__ok$next[0:0]$10340 $2\logical_op__rc__ok$next[0:0]$10366 + assign $0\logical_op__rc__rc$next[0:0]$10341 $2\logical_op__rc__rc$next[0:0]$10367 + attribute \src "libresoc.v:173747.5-173747.29" + switch \initial + attribute \src "libresoc.v:173747.9-173747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$10349 $1\logical_op__data_len$next[3:0]$10344 $1\logical_op__is_signed$next[0:0]$10354 $1\logical_op__is_32bit$next[0:0]$10353 $1\logical_op__output_carry$next[0:0]$10357 $1\logical_op__write_cr0$next[0:0]$10360 $1\logical_op__invert_out$next[0:0]$10352 $1\logical_op__input_carry$next[1:0]$10348 $1\logical_op__zero_a$next[0:0]$10361 $1\logical_op__invert_in$next[0:0]$10351 $1\logical_op__oe__ok$next[0:0]$10356 $1\logical_op__oe__oe$next[0:0]$10355 $1\logical_op__rc__ok$next[0:0]$10358 $1\logical_op__rc__rc$next[0:0]$10359 $1\logical_op__imm_data__ok$next[0:0]$10347 $1\logical_op__imm_data__data$next[63:0]$10346 $1\logical_op__fn_unit$next[12:0]$10345 $1\logical_op__insn_type$next[6:0]$10350 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$10349 $1\logical_op__data_len$next[3:0]$10344 $1\logical_op__is_signed$next[0:0]$10354 $1\logical_op__is_32bit$next[0:0]$10353 $1\logical_op__output_carry$next[0:0]$10357 $1\logical_op__write_cr0$next[0:0]$10360 $1\logical_op__invert_out$next[0:0]$10352 $1\logical_op__input_carry$next[1:0]$10348 $1\logical_op__zero_a$next[0:0]$10361 $1\logical_op__invert_in$next[0:0]$10351 $1\logical_op__oe__ok$next[0:0]$10356 $1\logical_op__oe__oe$next[0:0]$10355 $1\logical_op__rc__ok$next[0:0]$10358 $1\logical_op__rc__rc$next[0:0]$10359 $1\logical_op__imm_data__ok$next[0:0]$10347 $1\logical_op__imm_data__data$next[63:0]$10346 $1\logical_op__fn_unit$next[12:0]$10345 $1\logical_op__insn_type$next[6:0]$10350 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + case + assign $1\logical_op__data_len$next[3:0]$10344 \logical_op__data_len + assign $1\logical_op__fn_unit$next[12:0]$10345 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$10346 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$10347 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$10348 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$10349 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$10350 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$10351 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$10352 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$10353 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$10354 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$10355 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$10356 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$10357 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$10358 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$10359 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$10360 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$10361 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$10362 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10363 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10367 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10366 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10364 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10365 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$10362 $1\logical_op__imm_data__data$next[63:0]$10346 + assign $2\logical_op__imm_data__ok$next[0:0]$10363 $1\logical_op__imm_data__ok$next[0:0]$10347 + assign $2\logical_op__oe__oe$next[0:0]$10364 $1\logical_op__oe__oe$next[0:0]$10355 + assign $2\logical_op__oe__ok$next[0:0]$10365 $1\logical_op__oe__ok$next[0:0]$10356 + assign $2\logical_op__rc__ok$next[0:0]$10366 $1\logical_op__rc__ok$next[0:0]$10358 + assign $2\logical_op__rc__rc$next[0:0]$10367 $1\logical_op__rc__rc$next[0:0]$10359 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10326 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$10327 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10328 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10329 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10330 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10331 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10332 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10333 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10334 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10335 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10336 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10337 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10338 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10339 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10340 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10341 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10342 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10343 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179811$10699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179811$10699_Y + attribute \src "libresoc.v:173788.3-173800.6" + process $proc$libresoc.v:173788$10368 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$10369 $1\ra$next[63:0]$10370 + attribute \src "libresoc.v:173789.5-173789.29" + switch \initial + attribute \src "libresoc.v:173789.9-173789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$10370 \ra$87 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$10370 \ra$87 + case + assign $1\ra$next[63:0]$10370 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$10369 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179813$10701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179813$10701_Y + attribute \src "libresoc.v:173801.3-173813.6" + process $proc$libresoc.v:173801$10371 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$10372 $1\rb$next[63:0]$10373 + attribute \src "libresoc.v:173802.5-173802.29" + switch \initial + attribute \src "libresoc.v:173802.9-173802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$10373 \rb$89 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$10373 \rb$89 + case + assign $1\rb$next[63:0]$10373 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$10372 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179814$10702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179814$10702_Y + attribute \src "libresoc.v:173814.3-173826.6" + process $proc$libresoc.v:173814$10374 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$10375 $1\xer_so$next[0:0]$10376 + attribute \src "libresoc.v:173815.5-173815.29" + switch \initial + attribute \src "libresoc.v:173815.9-173815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$10376 \xer_so$91 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$10376 \xer_so$91 + case + assign $1\xer_so$next[0:0]$10376 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$10375 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179816$10704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179816$10704_Y - end - connect \$7 $not$libresoc.v:179801$10689_Y - connect \$12 $reduce_or$libresoc.v:179802$10690_Y - connect \$11 $not$libresoc.v:179803$10691_Y - connect \$16 $reduce_or$libresoc.v:179804$10692_Y - connect \$15 $not$libresoc.v:179805$10693_Y - connect \$1 $not$libresoc.v:179806$10694_Y - connect \$20 $reduce_or$libresoc.v:179807$10695_Y - connect \$19 $not$libresoc.v:179808$10696_Y - connect \$24 $reduce_or$libresoc.v:179809$10697_Y - connect \$23 $not$libresoc.v:179810$10698_Y - connect \$28 $reduce_or$libresoc.v:179811$10699_Y - connect \$27 $not$libresoc.v:179812$10700_Y - connect \$31 $reduce_or$libresoc.v:179813$10701_Y - connect \$4 $reduce_or$libresoc.v:179814$10702_Y - connect \$3 $not$libresoc.v:179815$10703_Y - connect \$8 $reduce_or$libresoc.v:179816$10704_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 + connect \$66 $and$libresoc.v:173442$10262_Y + connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \operation$99 \setup_stage_operation + connect \divisor_radicand$98 \setup_stage_divisor_radicand + connect \dividend$97 \setup_stage_dividend + connect \div_by_zero$96 \setup_stage_div_by_zero + connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 + connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 + connect \dividend_neg$93 \setup_stage_dividend_neg + connect \divisor_neg$92 \setup_stage_divisor_neg + connect \xer_so$91 \setup_stage_xer_so$64 + connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 + connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } + connect \muxid$68 \setup_stage_muxid$45 + connect \p_valid_i_p_ready_o \$66 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$65 \p_valid_i + connect \setup_stage_xer_so \input_xer_so$44 + connect \setup_stage_rb \input_rb$43 + connect \setup_stage_ra \input_ra$42 + connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } + connect \setup_stage_muxid \input_muxid$23 + connect \input_xer_so \xer_so$22 + connect \input_rb \rb$21 + connect \input_ra \ra$20 + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:179832.1-179916.10" +attribute \src "libresoc.v:173861.1-173905.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.pll" attribute \generator "nMigen" -module \ppick$183 - attribute \src "libresoc.v:179889.17-179889.91" - wire $not$libresoc.v:179889$10705_Y - attribute \src "libresoc.v:179891.18-179891.93" - wire $not$libresoc.v:179891$10707_Y - attribute \src "libresoc.v:179893.18-179893.93" - wire $not$libresoc.v:179893$10709_Y - attribute \src "libresoc.v:179894.17-179894.138" - wire width 8 $not$libresoc.v:179894$10710_Y - attribute \src "libresoc.v:179896.18-179896.93" - wire $not$libresoc.v:179896$10712_Y - attribute \src "libresoc.v:179898.18-179898.93" - wire $not$libresoc.v:179898$10714_Y - attribute \src "libresoc.v:179900.18-179900.93" - wire $not$libresoc.v:179900$10716_Y - attribute \src "libresoc.v:179903.17-179903.91" - wire $not$libresoc.v:179903$10719_Y - attribute \src "libresoc.v:179890.18-179890.116" - wire $reduce_or$libresoc.v:179890$10706_Y - attribute \src "libresoc.v:179892.18-179892.122" - wire $reduce_or$libresoc.v:179892$10708_Y - attribute \src "libresoc.v:179895.18-179895.128" - wire $reduce_or$libresoc.v:179895$10711_Y - attribute \src "libresoc.v:179897.18-179897.134" - wire $reduce_or$libresoc.v:179897$10713_Y - attribute \src "libresoc.v:179899.18-179899.140" - wire $reduce_or$libresoc.v:179899$10715_Y - attribute \src "libresoc.v:179901.18-179901.90" - wire $reduce_or$libresoc.v:179901$10717_Y - attribute \src "libresoc.v:179902.17-179902.103" - wire $reduce_or$libresoc.v:179902$10718_Y - attribute \src "libresoc.v:179904.17-179904.109" - wire $reduce_or$libresoc.v:179904$10720_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" +module \pll + attribute \src "libresoc.v:173862.7-173862.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:173894.3-173903.6" + wire $0\pll_18_o[0:0] + attribute \src "libresoc.v:173884.3-173893.6" + wire $0\pll_lck_o[0:0] + attribute \src "libresoc.v:173894.3-173903.6" + wire $1\pll_18_o[0:0] + attribute \src "libresoc.v:173884.3-173893.6" + wire $1\pll_lck_o[0:0] + attribute \src "libresoc.v:173881.17-173881.105" + wire $eq$libresoc.v:173881$10409_Y + attribute \src "libresoc.v:173882.17-173882.105" + wire $eq$libresoc.v:173882$10410_Y + attribute \src "libresoc.v:173883.17-173883.98" + wire $not$libresoc.v:173883$10411_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179889$10705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179889$10705_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179891$10707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire output 5 \clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 3 \clk_sel_i + attribute \src "libresoc.v:173862.7-173862.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire output 2 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 4 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:173881$10409 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179891$10707_Y + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:173881$10409_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179893$10709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:173882$10410 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179893$10709_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179894$10710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179894$10710_Y + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:173882$10410_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179896$10712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + cell $not $not$libresoc.v:173883$10411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179896$10712_Y + connect \A \clk_24_i + connect \Y $not$libresoc.v:173883$10411_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179898$10714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179898$10714_Y + attribute \src "libresoc.v:173862.7-173862.20" + process $proc$libresoc.v:173862$10414 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179900$10716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179900$10716_Y + attribute \src "libresoc.v:173884.3-173893.6" + process $proc$libresoc.v:173884$10412 + assign { } { } + assign { } { } + assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] + attribute \src "libresoc.v:173885.5-173885.29" + switch \initial + attribute \src "libresoc.v:173885.9-173885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_lck_o[0:0] \clk_24_i + case + assign $1\pll_lck_o[0:0] 1'0 + end + sync always + update \pll_lck_o $0\pll_lck_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179903$10719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179903$10719_Y + attribute \src "libresoc.v:173894.3-173903.6" + process $proc$libresoc.v:173894$10413 + assign { } { } + assign { } { } + assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] + attribute \src "libresoc.v:173895.5-173895.29" + switch \initial + attribute \src "libresoc.v:173895.9-173895.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_18_o[0:0] \$5 + case + assign $1\pll_18_o[0:0] 1'0 + end + sync always + update \pll_18_o $0\pll_18_o[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179890$10706 + connect \$1 $eq$libresoc.v:173881$10409_Y + connect \$3 $eq$libresoc.v:173882$10410_Y + connect \$5 $not$libresoc.v:173883$10411_Y + connect \clk_pll_o \clk_24_i +end +attribute \src "libresoc.v:173909.1-174551.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" +attribute \generator "nMigen" +module \popcount + attribute \src "libresoc.v:173910.7-173910.20" + wire $0\initial[0:0] + attribute \src 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width 2 \pop_2_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_2 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 6 \pop_6_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 6 \pop_6_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 7 \pop_7_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174322$10415 parameter \A_SIGNED 0 parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179890$10706_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179892$10708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179892$10708_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_2 } + connect \B { 2'00 \pop_2_3 } + connect \Y $add$libresoc.v:174322$10415_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179895$10711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174323$10416 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179895$10711_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_4 } + connect \B { 2'00 \pop_2_5 } + connect \Y $add$libresoc.v:174323$10416_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179897$10713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174324$10417 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179897$10713_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_6 } + connect \B { 2'00 \pop_2_7 } + connect \Y $add$libresoc.v:174324$10417_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179899$10715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174325$10418 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179899$10715_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_8 } + connect \B { 2'00 \pop_2_9 } + connect \Y $add$libresoc.v:174325$10418_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179901$10717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174326$10419 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179901$10717_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_10 } + connect \B { 2'00 \pop_2_11 } + connect \Y $add$libresoc.v:174326$10419_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179902$10718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174327$10420 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179902$10718_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_12 } + connect \B { 2'00 \pop_2_13 } + connect \Y $add$libresoc.v:174327$10420_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179904$10720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174328$10421 parameter \A_SIGNED 0 parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179904$10720_Y - end - connect \$7 $not$libresoc.v:179889$10705_Y - connect \$12 $reduce_or$libresoc.v:179890$10706_Y - connect \$11 $not$libresoc.v:179891$10707_Y - connect \$16 $reduce_or$libresoc.v:179892$10708_Y - connect \$15 $not$libresoc.v:179893$10709_Y - connect \$1 $not$libresoc.v:179894$10710_Y - connect \$20 $reduce_or$libresoc.v:179895$10711_Y - connect \$19 $not$libresoc.v:179896$10712_Y - connect \$24 $reduce_or$libresoc.v:179897$10713_Y - connect \$23 $not$libresoc.v:179898$10714_Y - connect \$28 $reduce_or$libresoc.v:179899$10715_Y - connect \$27 $not$libresoc.v:179900$10716_Y - connect \$31 $reduce_or$libresoc.v:179901$10717_Y - connect \$4 $reduce_or$libresoc.v:179902$10718_Y - connect \$3 $not$libresoc.v:179903$10719_Y - connect \$8 $reduce_or$libresoc.v:179904$10720_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:179920.1-180004.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$185 - attribute \src "libresoc.v:179977.17-179977.91" - wire $not$libresoc.v:179977$10721_Y - attribute \src "libresoc.v:179979.18-179979.93" - wire $not$libresoc.v:179979$10723_Y - attribute \src "libresoc.v:179981.18-179981.93" - wire $not$libresoc.v:179981$10725_Y - attribute \src "libresoc.v:179982.17-179982.138" - wire width 8 $not$libresoc.v:179982$10726_Y - attribute \src "libresoc.v:179984.18-179984.93" - wire $not$libresoc.v:179984$10728_Y - attribute \src "libresoc.v:179986.18-179986.93" - wire $not$libresoc.v:179986$10730_Y - attribute \src "libresoc.v:179988.18-179988.93" - wire $not$libresoc.v:179988$10732_Y - attribute \src "libresoc.v:179991.17-179991.91" - wire $not$libresoc.v:179991$10735_Y - attribute \src "libresoc.v:179978.18-179978.116" - wire $reduce_or$libresoc.v:179978$10722_Y - attribute \src "libresoc.v:179980.18-179980.122" - wire $reduce_or$libresoc.v:179980$10724_Y - attribute \src "libresoc.v:179983.18-179983.128" - wire $reduce_or$libresoc.v:179983$10727_Y - attribute \src "libresoc.v:179985.18-179985.134" - wire $reduce_or$libresoc.v:179985$10729_Y - attribute \src "libresoc.v:179987.18-179987.140" - wire $reduce_or$libresoc.v:179987$10731_Y - attribute \src "libresoc.v:179989.18-179989.90" - wire $reduce_or$libresoc.v:179989$10733_Y - attribute \src "libresoc.v:179990.17-179990.103" - wire $reduce_or$libresoc.v:179990$10734_Y - attribute \src "libresoc.v:179992.17-179992.109" - wire $reduce_or$libresoc.v:179992$10736_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179977$10721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:179977$10721_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179979$10723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:179979$10723_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [6] } + connect \B { 2'00 \a [7] } + connect \Y $add$libresoc.v:174328$10421_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179981$10725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174329$10422 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:179981$10725_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_14 } + connect \B { 2'00 \pop_2_15 } + connect \Y $add$libresoc.v:174329$10422_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:179982$10726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174330$10423 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:179982$10726_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_16 } + connect \B { 2'00 \pop_2_17 } + connect \Y $add$libresoc.v:174330$10423_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179984$10728 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174331$10424 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:179984$10728_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_18 } + connect \B { 2'00 \pop_2_19 } + connect \Y $add$libresoc.v:174331$10424_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179986$10730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174332$10425 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:179986$10730_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_20 } + connect \B { 2'00 \pop_2_21 } + connect \Y $add$libresoc.v:174332$10425_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179988$10732 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174333$10426 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:179988$10732_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_22 } + connect \B { 2'00 \pop_2_23 } + connect \Y $add$libresoc.v:174333$10426_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:179991$10735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174334$10427 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:179991$10735_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_24 } + connect \B { 2'00 \pop_2_25 } + connect \Y $add$libresoc.v:174334$10427_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179978$10722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174335$10428 parameter \A_SIGNED 0 parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:179978$10722_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_26 } + connect \B { 2'00 \pop_2_27 } + connect \Y $add$libresoc.v:174335$10428_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179980$10724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174336$10429 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:179980$10724_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_28 } + connect \B { 2'00 \pop_2_29 } + connect \Y $add$libresoc.v:174336$10429_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179983$10727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174337$10430 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:179983$10727_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_30 } + connect \B { 2'00 \pop_2_31 } + connect \Y $add$libresoc.v:174337$10430_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179985$10729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174338$10431 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:179985$10729_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_0 } + connect \B { 2'00 \pop_3_1 } + connect \Y $add$libresoc.v:174338$10431_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179987$10731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174339$10432 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:179987$10731_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [8] } + connect \B { 2'00 \a [9] } + connect \Y $add$libresoc.v:174339$10432_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:179989$10733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174340$10433 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:179989$10733_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_2 } + connect \B { 2'00 \pop_3_3 } + connect \Y $add$libresoc.v:174340$10433_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179990$10734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174341$10434 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:179990$10734_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_4 } + connect \B { 2'00 \pop_3_5 } + connect \Y $add$libresoc.v:174341$10434_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:179992$10736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:179992$10736_Y - end - connect \$7 $not$libresoc.v:179977$10721_Y - connect \$12 $reduce_or$libresoc.v:179978$10722_Y - connect \$11 $not$libresoc.v:179979$10723_Y - connect \$16 $reduce_or$libresoc.v:179980$10724_Y - connect \$15 $not$libresoc.v:179981$10725_Y - connect \$1 $not$libresoc.v:179982$10726_Y - connect \$20 $reduce_or$libresoc.v:179983$10727_Y - connect \$19 $not$libresoc.v:179984$10728_Y - connect \$24 $reduce_or$libresoc.v:179985$10729_Y - connect \$23 $not$libresoc.v:179986$10730_Y - connect \$28 $reduce_or$libresoc.v:179987$10731_Y - connect \$27 $not$libresoc.v:179988$10732_Y - connect \$31 $reduce_or$libresoc.v:179989$10733_Y - connect \$4 $reduce_or$libresoc.v:179990$10734_Y - connect \$3 $not$libresoc.v:179991$10735_Y - connect \$8 $reduce_or$libresoc.v:179992$10736_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:180008.1-180092.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$191 - attribute \src "libresoc.v:180065.17-180065.91" - wire $not$libresoc.v:180065$10737_Y - attribute \src "libresoc.v:180067.18-180067.93" - wire $not$libresoc.v:180067$10739_Y - attribute \src "libresoc.v:180069.18-180069.93" - wire $not$libresoc.v:180069$10741_Y - attribute \src "libresoc.v:180070.17-180070.138" - wire width 8 $not$libresoc.v:180070$10742_Y - attribute \src "libresoc.v:180072.18-180072.93" - wire $not$libresoc.v:180072$10744_Y - attribute \src "libresoc.v:180074.18-180074.93" - wire $not$libresoc.v:180074$10746_Y - attribute \src "libresoc.v:180076.18-180076.93" - wire $not$libresoc.v:180076$10748_Y - attribute \src "libresoc.v:180079.17-180079.91" - wire $not$libresoc.v:180079$10751_Y - attribute \src "libresoc.v:180066.18-180066.116" - wire $reduce_or$libresoc.v:180066$10738_Y - attribute \src "libresoc.v:180068.18-180068.122" - wire $reduce_or$libresoc.v:180068$10740_Y - attribute \src "libresoc.v:180071.18-180071.128" - wire $reduce_or$libresoc.v:180071$10743_Y - attribute \src "libresoc.v:180073.18-180073.134" - wire $reduce_or$libresoc.v:180073$10745_Y - attribute \src "libresoc.v:180075.18-180075.140" - wire $reduce_or$libresoc.v:180075$10747_Y - attribute \src "libresoc.v:180077.18-180077.90" - wire $reduce_or$libresoc.v:180077$10749_Y - attribute \src "libresoc.v:180078.17-180078.103" - wire $reduce_or$libresoc.v:180078$10750_Y - attribute \src "libresoc.v:180080.17-180080.109" - wire $reduce_or$libresoc.v:180080$10752_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180065$10737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174342$10435 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:180065$10737_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_6 } + connect \B { 2'00 \pop_3_7 } + connect \Y $add$libresoc.v:174342$10435_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180067$10739 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174343$10436 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:180067$10739_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_8 } + connect \B { 2'00 \pop_3_9 } + connect \Y $add$libresoc.v:174343$10436_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180069$10741 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174344$10437 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:180069$10741_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_10 } + connect \B { 2'00 \pop_3_11 } + connect \Y $add$libresoc.v:174344$10437_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180070$10742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174345$10438 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:180070$10742_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_12 } + connect \B { 2'00 \pop_3_13 } + connect \Y $add$libresoc.v:174345$10438_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180072$10744 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174346$10439 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:180072$10744_Y + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_14 } + connect \B { 2'00 \pop_3_15 } + connect \Y $add$libresoc.v:174346$10439_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180074$10746 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174347$10440 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:180074$10746_Y + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_0 } + connect \B { 2'00 \pop_4_1 } + connect \Y $add$libresoc.v:174347$10440_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180076$10748 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174348$10441 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:180076$10748_Y + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_2 } + connect \B { 2'00 \pop_4_3 } + connect \Y $add$libresoc.v:174348$10441_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180079$10751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174349$10442 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:180079$10751_Y + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_4 } + connect \B { 2'00 \pop_4_5 } + connect \Y $add$libresoc.v:174349$10442_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180066$10738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174350$10443 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:180066$10738_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [10] } + connect \B { 2'00 \a [11] } + connect \Y $add$libresoc.v:174350$10443_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180068$10740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174351$10444 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:180068$10740_Y + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_6 } + connect \B { 2'00 \pop_4_7 } + connect \Y $add$libresoc.v:174351$10444_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180071$10743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174352$10445 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:180071$10743_Y + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_0 } + connect \B { 2'00 \pop_5_1 } + connect \Y $add$libresoc.v:174352$10445_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180073$10745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174353$10446 parameter \A_SIGNED 0 parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:180073$10745_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_2 } + connect \B { 2'00 \pop_5_3 } + connect \Y $add$libresoc.v:174353$10446_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180075$10747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174354$10447 parameter \A_SIGNED 0 parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:180075$10747_Y + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { 2'00 \pop_6_0 } + connect \B { 2'00 \pop_6_1 } + connect \Y $add$libresoc.v:174354$10447_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180077$10749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174365$10466 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:180077$10749_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [12] } + connect \B { 2'00 \a [13] } + connect \Y $add$libresoc.v:174365$10466_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180078$10750 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174369$10473 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:180078$10750_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [14] } + connect \B { 2'00 \a [15] } + connect \Y $add$libresoc.v:174369$10473_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180080$10752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174370$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:180080$10752_Y - end - connect \$7 $not$libresoc.v:180065$10737_Y - connect \$12 $reduce_or$libresoc.v:180066$10738_Y - connect \$11 $not$libresoc.v:180067$10739_Y - connect \$16 $reduce_or$libresoc.v:180068$10740_Y - connect \$15 $not$libresoc.v:180069$10741_Y - connect \$1 $not$libresoc.v:180070$10742_Y - connect \$20 $reduce_or$libresoc.v:180071$10743_Y - connect \$19 $not$libresoc.v:180072$10744_Y - connect \$24 $reduce_or$libresoc.v:180073$10745_Y - connect \$23 $not$libresoc.v:180074$10746_Y - connect \$28 $reduce_or$libresoc.v:180075$10747_Y - connect \$27 $not$libresoc.v:180076$10748_Y - connect \$31 $reduce_or$libresoc.v:180077$10749_Y - connect \$4 $reduce_or$libresoc.v:180078$10750_Y - connect \$3 $not$libresoc.v:180079$10751_Y - connect \$8 $reduce_or$libresoc.v:180080$10752_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:180096.1-180180.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$193 - attribute \src "libresoc.v:180153.17-180153.91" - wire $not$libresoc.v:180153$10753_Y - attribute \src "libresoc.v:180155.18-180155.93" - wire $not$libresoc.v:180155$10755_Y - attribute \src "libresoc.v:180157.18-180157.93" - wire $not$libresoc.v:180157$10757_Y - attribute \src "libresoc.v:180158.17-180158.138" - wire width 8 $not$libresoc.v:180158$10758_Y - attribute \src "libresoc.v:180160.18-180160.93" - wire $not$libresoc.v:180160$10760_Y - attribute \src "libresoc.v:180162.18-180162.93" - wire $not$libresoc.v:180162$10762_Y - attribute \src "libresoc.v:180164.18-180164.93" - wire $not$libresoc.v:180164$10764_Y - attribute \src "libresoc.v:180167.17-180167.91" - wire $not$libresoc.v:180167$10767_Y - attribute \src "libresoc.v:180154.18-180154.116" - wire $reduce_or$libresoc.v:180154$10754_Y - attribute \src "libresoc.v:180156.18-180156.122" - wire $reduce_or$libresoc.v:180156$10756_Y - attribute \src "libresoc.v:180159.18-180159.128" - wire $reduce_or$libresoc.v:180159$10759_Y - attribute \src "libresoc.v:180161.18-180161.134" - wire $reduce_or$libresoc.v:180161$10761_Y - attribute \src "libresoc.v:180163.18-180163.140" - wire $reduce_or$libresoc.v:180163$10763_Y - attribute \src "libresoc.v:180165.18-180165.90" - wire $reduce_or$libresoc.v:180165$10765_Y - attribute \src "libresoc.v:180166.17-180166.103" - wire $reduce_or$libresoc.v:180166$10766_Y - attribute \src "libresoc.v:180168.17-180168.109" - wire $reduce_or$libresoc.v:180168$10768_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180153$10753 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [16] } + connect \B { 2'00 \a [17] } + connect \Y $add$libresoc.v:174370$10474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174371$10475 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:180153$10753_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [0] } + connect \B { 2'00 \a [1] } + connect \Y $add$libresoc.v:174371$10475_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180155$10755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174372$10476 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:180155$10755_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [18] } + connect \B { 2'00 \a [19] } + connect \Y $add$libresoc.v:174372$10476_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180157$10757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174373$10477 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:180157$10757_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [20] } + connect \B { 2'00 \a [21] } + connect \Y $add$libresoc.v:174373$10477_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180158$10758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174374$10478 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:180158$10758_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [22] } + connect \B { 2'00 \a [23] } + connect \Y $add$libresoc.v:174374$10478_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180160$10760 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174375$10479 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:180160$10760_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [24] } + connect \B { 2'00 \a [25] } + connect \Y $add$libresoc.v:174375$10479_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180162$10762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174376$10480 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:180162$10762_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [26] } + connect \B { 2'00 \a [27] } + connect \Y $add$libresoc.v:174376$10480_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180164$10764 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174377$10481 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:180164$10764_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [28] } + connect \B { 2'00 \a [29] } + connect \Y $add$libresoc.v:174377$10481_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180167$10767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174378$10482 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:180167$10767_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [30] } + connect \B { 2'00 \a [31] } + connect \Y $add$libresoc.v:174378$10482_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180154$10754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174379$10483 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:180154$10754_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [32] } + connect \B { 2'00 \a [33] } + connect \Y $add$libresoc.v:174379$10483_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180156$10756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174380$10484 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:180156$10756_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [34] } + connect \B { 2'00 \a [35] } + connect \Y $add$libresoc.v:174380$10484_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180159$10759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174381$10485 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:180159$10759_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [36] } + connect \B { 2'00 \a [37] } + connect \Y $add$libresoc.v:174381$10485_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180161$10761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174382$10486 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:180161$10761_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [2] } + connect \B { 2'00 \a [3] } + connect \Y $add$libresoc.v:174382$10486_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180163$10763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174383$10487 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:180163$10763_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [38] } + connect \B { 2'00 \a [39] } + connect \Y $add$libresoc.v:174383$10487_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180165$10765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174384$10488 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:180165$10765_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [40] } + connect \B { 2'00 \a [41] } + connect \Y $add$libresoc.v:174384$10488_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180166$10766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174385$10489 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:180166$10766_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [42] } + connect \B { 2'00 \a [43] } + connect \Y $add$libresoc.v:174385$10489_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180168$10768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174386$10490 parameter \A_SIGNED 0 parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:180168$10768_Y - end - connect \$7 $not$libresoc.v:180153$10753_Y - connect \$12 $reduce_or$libresoc.v:180154$10754_Y - connect \$11 $not$libresoc.v:180155$10755_Y - connect \$16 $reduce_or$libresoc.v:180156$10756_Y - connect \$15 $not$libresoc.v:180157$10757_Y - connect \$1 $not$libresoc.v:180158$10758_Y - connect \$20 $reduce_or$libresoc.v:180159$10759_Y - connect \$19 $not$libresoc.v:180160$10760_Y - connect \$24 $reduce_or$libresoc.v:180161$10761_Y - connect \$23 $not$libresoc.v:180162$10762_Y - connect \$28 $reduce_or$libresoc.v:180163$10763_Y - connect \$27 $not$libresoc.v:180164$10764_Y - connect \$31 $reduce_or$libresoc.v:180165$10765_Y - connect \$4 $reduce_or$libresoc.v:180166$10766_Y - connect \$3 $not$libresoc.v:180167$10767_Y - connect \$8 $reduce_or$libresoc.v:180168$10768_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:180184.1-180268.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$199 - attribute \src "libresoc.v:180241.17-180241.91" - wire $not$libresoc.v:180241$10769_Y - attribute \src "libresoc.v:180243.18-180243.93" - wire $not$libresoc.v:180243$10771_Y - attribute \src "libresoc.v:180245.18-180245.93" - wire $not$libresoc.v:180245$10773_Y - attribute \src "libresoc.v:180246.17-180246.138" - wire width 8 $not$libresoc.v:180246$10774_Y - attribute \src "libresoc.v:180248.18-180248.93" - wire $not$libresoc.v:180248$10776_Y - attribute \src "libresoc.v:180250.18-180250.93" - wire $not$libresoc.v:180250$10778_Y - attribute \src "libresoc.v:180252.18-180252.93" - wire $not$libresoc.v:180252$10780_Y - attribute \src "libresoc.v:180255.17-180255.91" - wire $not$libresoc.v:180255$10783_Y - attribute \src "libresoc.v:180242.18-180242.116" - wire $reduce_or$libresoc.v:180242$10770_Y - attribute \src "libresoc.v:180244.18-180244.122" - wire $reduce_or$libresoc.v:180244$10772_Y - attribute \src "libresoc.v:180247.18-180247.128" - wire $reduce_or$libresoc.v:180247$10775_Y - attribute \src "libresoc.v:180249.18-180249.134" - wire $reduce_or$libresoc.v:180249$10777_Y - attribute \src "libresoc.v:180251.18-180251.140" - wire $reduce_or$libresoc.v:180251$10779_Y - attribute \src "libresoc.v:180253.18-180253.90" - wire $reduce_or$libresoc.v:180253$10781_Y - attribute \src "libresoc.v:180254.17-180254.103" - wire $reduce_or$libresoc.v:180254$10782_Y - attribute \src "libresoc.v:180256.17-180256.109" - wire $reduce_or$libresoc.v:180256$10784_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180241$10769 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [44] } + connect \B { 2'00 \a [45] } + connect \Y $add$libresoc.v:174386$10490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174387$10491 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:180241$10769_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [46] } + connect \B { 2'00 \a [47] } + connect \Y $add$libresoc.v:174387$10491_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180243$10771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174388$10492 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:180243$10771_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [48] } + connect \B { 2'00 \a [49] } + connect \Y $add$libresoc.v:174388$10492_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180245$10773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174389$10493 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:180245$10773_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [50] } + connect \B { 2'00 \a [51] } + connect \Y $add$libresoc.v:174389$10493_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180246$10774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174390$10494 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:180246$10774_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [52] } + connect \B { 2'00 \a [53] } + connect \Y $add$libresoc.v:174390$10494_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180248$10776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174391$10495 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:180248$10776_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [54] } + connect \B { 2'00 \a [55] } + connect \Y $add$libresoc.v:174391$10495_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180250$10778 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174392$10496 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:180250$10778_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [56] } + connect \B { 2'00 \a [57] } + connect \Y $add$libresoc.v:174392$10496_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180252$10780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174393$10497 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:180252$10780_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [4] } + connect \B { 2'00 \a [5] } + connect \Y $add$libresoc.v:174393$10497_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180255$10783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174394$10498 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:180255$10783_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [58] } + connect \B { 2'00 \a [59] } + connect \Y $add$libresoc.v:174394$10498_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180242$10770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174395$10499 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:180242$10770_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [60] } + connect \B { 2'00 \a [61] } + connect \Y $add$libresoc.v:174395$10499_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180244$10772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174396$10500 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:180244$10772_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [62] } + connect \B { 2'00 \a [63] } + connect \Y $add$libresoc.v:174396$10500_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180247$10775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:174397$10501 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:180247$10775_Y + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_0 } + connect \B { 2'00 \pop_2_1 } + connect \Y $add$libresoc.v:174397$10501_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180249$10777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + cell $eq $eq$libresoc.v:174355$10448 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:180249$10777_Y + connect \A \data_len + connect \B 1'1 + connect \Y $eq$libresoc.v:174355$10448_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180251$10779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" + cell $eq $eq$libresoc.v:174356$10449 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:180251$10779_Y + connect \A \data_len + connect \B 3'100 + connect \Y $eq$libresoc.v:174356$10449_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180253$10781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174357$10450 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:180253$10781_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_0 + connect \Y $extend$libresoc.v:174357$10450_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180254$10782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174358$10452 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:180254$10782_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_1 + connect \Y $extend$libresoc.v:174358$10452_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180256$10784 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174359$10454 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:180256$10784_Y - end - connect \$7 $not$libresoc.v:180241$10769_Y - connect \$12 $reduce_or$libresoc.v:180242$10770_Y - connect \$11 $not$libresoc.v:180243$10771_Y - connect \$16 $reduce_or$libresoc.v:180244$10772_Y - connect \$15 $not$libresoc.v:180245$10773_Y - connect \$1 $not$libresoc.v:180246$10774_Y - connect \$20 $reduce_or$libresoc.v:180247$10775_Y - connect \$19 $not$libresoc.v:180248$10776_Y - connect \$24 $reduce_or$libresoc.v:180249$10777_Y - connect \$23 $not$libresoc.v:180250$10778_Y - connect \$28 $reduce_or$libresoc.v:180251$10779_Y - connect \$27 $not$libresoc.v:180252$10780_Y - connect \$31 $reduce_or$libresoc.v:180253$10781_Y - connect \$4 $reduce_or$libresoc.v:180254$10782_Y - connect \$3 $not$libresoc.v:180255$10783_Y - connect \$8 $reduce_or$libresoc.v:180256$10784_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:180272.1-180356.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$201 - attribute \src "libresoc.v:180329.17-180329.91" - wire $not$libresoc.v:180329$10785_Y - attribute \src "libresoc.v:180331.18-180331.93" - wire $not$libresoc.v:180331$10787_Y - attribute \src "libresoc.v:180333.18-180333.93" - wire $not$libresoc.v:180333$10789_Y - attribute \src "libresoc.v:180334.17-180334.138" - wire width 8 $not$libresoc.v:180334$10790_Y - attribute \src "libresoc.v:180336.18-180336.93" - wire $not$libresoc.v:180336$10792_Y - attribute \src "libresoc.v:180338.18-180338.93" - wire $not$libresoc.v:180338$10794_Y - attribute \src "libresoc.v:180340.18-180340.93" - wire $not$libresoc.v:180340$10796_Y - attribute \src "libresoc.v:180343.17-180343.91" - wire $not$libresoc.v:180343$10799_Y - attribute \src "libresoc.v:180330.18-180330.116" - wire $reduce_or$libresoc.v:180330$10786_Y - attribute \src "libresoc.v:180332.18-180332.122" - wire $reduce_or$libresoc.v:180332$10788_Y - attribute \src "libresoc.v:180335.18-180335.128" - wire $reduce_or$libresoc.v:180335$10791_Y - attribute \src "libresoc.v:180337.18-180337.134" - wire $reduce_or$libresoc.v:180337$10793_Y - attribute \src "libresoc.v:180339.18-180339.140" - wire $reduce_or$libresoc.v:180339$10795_Y - attribute \src "libresoc.v:180341.18-180341.90" - wire $reduce_or$libresoc.v:180341$10797_Y - attribute \src "libresoc.v:180342.17-180342.103" - wire $reduce_or$libresoc.v:180342$10798_Y - attribute \src "libresoc.v:180344.17-180344.109" - wire $reduce_or$libresoc.v:180344$10800_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180329$10785 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_2 + connect \Y $extend$libresoc.v:174359$10454_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174360$10456 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:180329$10785_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_3 + connect \Y $extend$libresoc.v:174360$10456_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180331$10787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174361$10458 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:180331$10787_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_4 + connect \Y $extend$libresoc.v:174361$10458_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180333$10789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174362$10460 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:180333$10789_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_5 + connect \Y $extend$libresoc.v:174362$10460_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180334$10790 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174363$10462 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 4 parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:180334$10790_Y + connect \A \pop_4_6 + connect \Y $extend$libresoc.v:174363$10462_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180336$10792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174364$10464 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:180336$10792_Y + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_7 + connect \Y $extend$libresoc.v:174364$10464_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180338$10794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174366$10467 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:180338$10794_Y + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_0 + connect \Y $extend$libresoc.v:174366$10467_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180340$10796 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174367$10469 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:180340$10796_Y + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_1 + connect \Y $extend$libresoc.v:174367$10469_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180343$10799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:174368$10471 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:180343$10799_Y + parameter \A_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \pop_7_0 + connect \Y $extend$libresoc.v:174368$10471_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180330$10786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174357$10451 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:180330$10786_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174357$10450_Y + connect \Y $pos$libresoc.v:174357$10451_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180332$10788 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174358$10453 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:180332$10788_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174358$10452_Y + connect \Y $pos$libresoc.v:174358$10453_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180335$10791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174359$10455 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:180335$10791_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174359$10454_Y + connect \Y $pos$libresoc.v:174359$10455_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180337$10793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174360$10457 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:180337$10793_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174360$10456_Y + connect \Y $pos$libresoc.v:174360$10457_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180339$10795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174361$10459 parameter \A_SIGNED 0 parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:180339$10795_Y + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174361$10458_Y + connect \Y $pos$libresoc.v:174361$10459_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180341$10797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174362$10461 parameter \A_SIGNED 0 parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:180341$10797_Y + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174362$10460_Y + connect \Y $pos$libresoc.v:174362$10461_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180342$10798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174363$10463 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:180342$10798_Y + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174363$10462_Y + connect \Y $pos$libresoc.v:174363$10463_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180344$10800 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174364$10465 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:180344$10800_Y - end - connect \$7 $not$libresoc.v:180329$10785_Y - connect \$12 $reduce_or$libresoc.v:180330$10786_Y - connect \$11 $not$libresoc.v:180331$10787_Y - connect \$16 $reduce_or$libresoc.v:180332$10788_Y - connect \$15 $not$libresoc.v:180333$10789_Y - connect \$1 $not$libresoc.v:180334$10790_Y - connect \$20 $reduce_or$libresoc.v:180335$10791_Y - connect \$19 $not$libresoc.v:180336$10792_Y - connect \$24 $reduce_or$libresoc.v:180337$10793_Y - connect \$23 $not$libresoc.v:180338$10794_Y - connect \$28 $reduce_or$libresoc.v:180339$10795_Y - connect \$27 $not$libresoc.v:180340$10796_Y - connect \$31 $reduce_or$libresoc.v:180341$10797_Y - connect \$4 $reduce_or$libresoc.v:180342$10798_Y - connect \$3 $not$libresoc.v:180343$10799_Y - connect \$8 $reduce_or$libresoc.v:180344$10800_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:174364$10464_Y + connect \Y $pos$libresoc.v:174364$10465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174366$10468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:174366$10467_Y + connect \Y $pos$libresoc.v:174366$10468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174367$10470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:174367$10469_Y + connect \Y $pos$libresoc.v:174367$10470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:174368$10472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:174368$10471_Y + connect \Y $pos$libresoc.v:174368$10472_Y + end + attribute \src "libresoc.v:173910.7-173910.20" + process $proc$libresoc.v:173910$10503 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174398.3-174424.6" + process $proc$libresoc.v:174398$10502 + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:174399.5-174399.29" + switch \initial + attribute \src "libresoc.v:174399.9-174399.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + switch { \$192 \$190 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o[63:0] [7:0] \$194 + assign $1\o[63:0] [15:8] \$196 + assign $1\o[63:0] [23:16] \$198 + assign $1\o[63:0] [31:24] \$200 + assign $1\o[63:0] [39:32] \$202 + assign $1\o[63:0] [47:40] \$204 + assign $1\o[63:0] [55:48] \$206 + assign $1\o[63:0] [63:56] \$208 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o[63:0] [31:0] \$210 + assign $1\o[63:0] [63:32] \$212 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] \$214 + end + sync always + update \o $0\o[63:0] + end + connect \$101 $add$libresoc.v:174322$10415_Y + connect \$104 $add$libresoc.v:174323$10416_Y + connect \$107 $add$libresoc.v:174324$10417_Y + connect \$110 $add$libresoc.v:174325$10418_Y + connect \$113 $add$libresoc.v:174326$10419_Y + connect \$116 $add$libresoc.v:174327$10420_Y + connect \$11 $add$libresoc.v:174328$10421_Y + connect \$119 $add$libresoc.v:174329$10422_Y + connect \$122 $add$libresoc.v:174330$10423_Y + connect \$125 $add$libresoc.v:174331$10424_Y + connect \$128 $add$libresoc.v:174332$10425_Y + connect \$131 $add$libresoc.v:174333$10426_Y + connect \$134 $add$libresoc.v:174334$10427_Y + connect \$137 $add$libresoc.v:174335$10428_Y + connect \$140 $add$libresoc.v:174336$10429_Y + connect \$143 $add$libresoc.v:174337$10430_Y + connect \$146 $add$libresoc.v:174338$10431_Y + connect \$14 $add$libresoc.v:174339$10432_Y + connect \$149 $add$libresoc.v:174340$10433_Y + connect \$152 $add$libresoc.v:174341$10434_Y + connect \$155 $add$libresoc.v:174342$10435_Y + connect \$158 $add$libresoc.v:174343$10436_Y + connect \$161 $add$libresoc.v:174344$10437_Y + connect \$164 $add$libresoc.v:174345$10438_Y + connect \$167 $add$libresoc.v:174346$10439_Y + connect \$170 $add$libresoc.v:174347$10440_Y + connect \$173 $add$libresoc.v:174348$10441_Y + connect \$176 $add$libresoc.v:174349$10442_Y + connect \$17 $add$libresoc.v:174350$10443_Y + connect \$179 $add$libresoc.v:174351$10444_Y + connect \$182 $add$libresoc.v:174352$10445_Y + connect \$185 $add$libresoc.v:174353$10446_Y + connect \$188 $add$libresoc.v:174354$10447_Y + connect \$190 $eq$libresoc.v:174355$10448_Y + connect \$192 $eq$libresoc.v:174356$10449_Y + connect \$194 $pos$libresoc.v:174357$10451_Y + connect \$196 $pos$libresoc.v:174358$10453_Y + connect \$198 $pos$libresoc.v:174359$10455_Y + connect \$200 $pos$libresoc.v:174360$10457_Y + connect \$202 $pos$libresoc.v:174361$10459_Y + connect \$204 $pos$libresoc.v:174362$10461_Y + connect \$206 $pos$libresoc.v:174363$10463_Y + connect \$208 $pos$libresoc.v:174364$10465_Y + connect \$20 $add$libresoc.v:174365$10466_Y + connect \$210 $pos$libresoc.v:174366$10468_Y + connect \$212 $pos$libresoc.v:174367$10470_Y + connect \$214 $pos$libresoc.v:174368$10472_Y + connect \$23 $add$libresoc.v:174369$10473_Y + connect \$26 $add$libresoc.v:174370$10474_Y + connect \$2 $add$libresoc.v:174371$10475_Y + connect \$29 $add$libresoc.v:174372$10476_Y + connect \$32 $add$libresoc.v:174373$10477_Y + connect \$35 $add$libresoc.v:174374$10478_Y + connect \$38 $add$libresoc.v:174375$10479_Y + connect \$41 $add$libresoc.v:174376$10480_Y + connect \$44 $add$libresoc.v:174377$10481_Y + connect \$47 $add$libresoc.v:174378$10482_Y + connect \$50 $add$libresoc.v:174379$10483_Y + connect \$53 $add$libresoc.v:174380$10484_Y + connect \$56 $add$libresoc.v:174381$10485_Y + connect \$5 $add$libresoc.v:174382$10486_Y + connect \$59 $add$libresoc.v:174383$10487_Y + connect \$62 $add$libresoc.v:174384$10488_Y + connect \$65 $add$libresoc.v:174385$10489_Y + connect \$68 $add$libresoc.v:174386$10490_Y + connect \$71 $add$libresoc.v:174387$10491_Y + connect \$74 $add$libresoc.v:174388$10492_Y + connect \$77 $add$libresoc.v:174389$10493_Y + connect \$80 $add$libresoc.v:174390$10494_Y + connect \$83 $add$libresoc.v:174391$10495_Y + connect \$86 $add$libresoc.v:174392$10496_Y + connect \$8 $add$libresoc.v:174393$10497_Y + connect \$89 $add$libresoc.v:174394$10498_Y + connect \$92 $add$libresoc.v:174395$10499_Y + connect \$95 $add$libresoc.v:174396$10500_Y + connect \$98 $add$libresoc.v:174397$10501_Y + connect \$1 \$2 + connect \$4 \$5 + connect \$7 \$8 + connect \$10 \$11 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 + connect \$25 \$26 + connect \$28 \$29 + connect \$31 \$32 + connect \$34 \$35 + connect \$37 \$38 + connect \$40 \$41 + connect \$43 \$44 + connect \$46 \$47 + connect \$49 \$50 + connect \$52 \$53 + connect \$55 \$56 + connect \$58 \$59 + connect \$61 \$62 + connect \$64 \$65 + connect \$67 \$68 + connect \$70 \$71 + connect \$73 \$74 + connect \$76 \$77 + connect \$79 \$80 + connect \$82 \$83 + connect \$85 \$86 + connect \$88 \$89 + connect \$91 \$92 + connect \$94 \$95 + connect \$97 \$98 + connect \$100 \$101 + connect \$103 \$104 + connect \$106 \$107 + connect \$109 \$110 + connect \$112 \$113 + connect \$115 \$116 + connect \$118 \$119 + connect \$121 \$122 + connect \$124 \$125 + connect \$127 \$128 + connect \$130 \$131 + connect \$133 \$134 + connect \$136 \$137 + connect \$139 \$140 + connect \$142 \$143 + connect \$145 \$146 + connect \$148 \$149 + connect \$151 \$152 + connect \$154 \$155 + connect \$157 \$158 + connect \$160 \$161 + connect \$163 \$164 + connect \$166 \$167 + connect \$169 \$170 + connect \$172 \$173 + connect \$175 \$176 + connect \$178 \$179 + connect \$181 \$182 + connect \$184 \$185 + connect \$187 \$188 + connect \pop_7_0 \$188 [6:0] + connect \pop_6_1 \$185 [5:0] + connect \pop_6_0 \$182 [5:0] + connect \pop_5_3 \$179 [4:0] + connect \pop_5_2 \$176 [4:0] + connect \pop_5_1 \$173 [4:0] + connect \pop_5_0 \$170 [4:0] + connect \pop_4_7 \$167 [3:0] + connect \pop_4_6 \$164 [3:0] + connect \pop_4_5 \$161 [3:0] + connect \pop_4_4 \$158 [3:0] + connect \pop_4_3 \$155 [3:0] + connect \pop_4_2 \$152 [3:0] + connect \pop_4_1 \$149 [3:0] + connect \pop_4_0 \$146 [3:0] + connect \pop_3_15 \$143 [2:0] + connect \pop_3_14 \$140 [2:0] + connect \pop_3_13 \$137 [2:0] + connect \pop_3_12 \$134 [2:0] + connect \pop_3_11 \$131 [2:0] + connect \pop_3_10 \$128 [2:0] + connect \pop_3_9 \$125 [2:0] + connect \pop_3_8 \$122 [2:0] + connect \pop_3_7 \$119 [2:0] + connect \pop_3_6 \$116 [2:0] + connect \pop_3_5 \$113 [2:0] + connect \pop_3_4 \$110 [2:0] + connect \pop_3_3 \$107 [2:0] + connect \pop_3_2 \$104 [2:0] + connect \pop_3_1 \$101 [2:0] + connect \pop_3_0 \$98 [2:0] + connect \pop_2_31 \$95 [1:0] + connect \pop_2_30 \$92 [1:0] + connect \pop_2_29 \$89 [1:0] + connect \pop_2_28 \$86 [1:0] + connect \pop_2_27 \$83 [1:0] + connect \pop_2_26 \$80 [1:0] + connect \pop_2_25 \$77 [1:0] + connect \pop_2_24 \$74 [1:0] + connect \pop_2_23 \$71 [1:0] + connect \pop_2_22 \$68 [1:0] + connect \pop_2_21 \$65 [1:0] + connect \pop_2_20 \$62 [1:0] + connect \pop_2_19 \$59 [1:0] + connect \pop_2_18 \$56 [1:0] + connect \pop_2_17 \$53 [1:0] + connect \pop_2_16 \$50 [1:0] + connect \pop_2_15 \$47 [1:0] + connect \pop_2_14 \$44 [1:0] + connect \pop_2_13 \$41 [1:0] + connect \pop_2_12 \$38 [1:0] + connect \pop_2_11 \$35 [1:0] + connect \pop_2_10 \$32 [1:0] + connect \pop_2_9 \$29 [1:0] + connect \pop_2_8 \$26 [1:0] + connect \pop_2_7 \$23 [1:0] + connect \pop_2_6 \$20 [1:0] + connect \pop_2_5 \$17 [1:0] + connect \pop_2_4 \$14 [1:0] + connect \pop_2_3 \$11 [1:0] + connect \pop_2_2 \$8 [1:0] + connect \pop_2_1 \$5 [1:0] + connect \pop_2_0 \$2 [1:0] end -attribute \src "libresoc.v:180360.1-180444.10" +attribute \src "libresoc.v:174555.1-174639.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" -module \ppick$208 - attribute \src "libresoc.v:180417.17-180417.91" - wire $not$libresoc.v:180417$10801_Y - attribute \src "libresoc.v:180419.18-180419.93" - wire $not$libresoc.v:180419$10803_Y - attribute \src "libresoc.v:180421.18-180421.93" - wire $not$libresoc.v:180421$10805_Y - attribute \src "libresoc.v:180422.17-180422.138" - wire width 8 $not$libresoc.v:180422$10806_Y - attribute \src "libresoc.v:180424.18-180424.93" - wire $not$libresoc.v:180424$10808_Y - attribute \src "libresoc.v:180426.18-180426.93" - wire $not$libresoc.v:180426$10810_Y - attribute \src "libresoc.v:180428.18-180428.93" - wire $not$libresoc.v:180428$10812_Y - attribute \src "libresoc.v:180431.17-180431.91" - wire $not$libresoc.v:180431$10815_Y - attribute \src "libresoc.v:180418.18-180418.116" - wire $reduce_or$libresoc.v:180418$10802_Y - attribute \src "libresoc.v:180420.18-180420.122" - wire $reduce_or$libresoc.v:180420$10804_Y - attribute \src "libresoc.v:180423.18-180423.128" - wire $reduce_or$libresoc.v:180423$10807_Y - attribute \src "libresoc.v:180425.18-180425.134" - wire $reduce_or$libresoc.v:180425$10809_Y - attribute \src "libresoc.v:180427.18-180427.140" - wire $reduce_or$libresoc.v:180427$10811_Y - attribute \src "libresoc.v:180429.18-180429.90" - wire $reduce_or$libresoc.v:180429$10813_Y - attribute \src "libresoc.v:180430.17-180430.103" - wire $reduce_or$libresoc.v:180430$10814_Y - attribute \src "libresoc.v:180432.17-180432.109" - wire $reduce_or$libresoc.v:180432$10816_Y +module \ppick + attribute \src "libresoc.v:174612.17-174612.91" + wire $not$libresoc.v:174612$10504_Y + attribute \src "libresoc.v:174614.18-174614.93" + wire $not$libresoc.v:174614$10506_Y + attribute \src "libresoc.v:174616.18-174616.93" + wire $not$libresoc.v:174616$10508_Y + attribute \src "libresoc.v:174617.17-174617.138" + wire width 8 $not$libresoc.v:174617$10509_Y + attribute \src "libresoc.v:174619.18-174619.93" + wire $not$libresoc.v:174619$10511_Y + attribute \src "libresoc.v:174621.18-174621.93" + wire $not$libresoc.v:174621$10513_Y + attribute \src "libresoc.v:174623.18-174623.93" + wire $not$libresoc.v:174623$10515_Y + attribute \src "libresoc.v:174626.17-174626.91" + wire $not$libresoc.v:174626$10518_Y + attribute \src "libresoc.v:174613.18-174613.116" + wire $reduce_or$libresoc.v:174613$10505_Y + attribute \src "libresoc.v:174615.18-174615.122" + wire $reduce_or$libresoc.v:174615$10507_Y + attribute \src "libresoc.v:174618.18-174618.128" + wire $reduce_or$libresoc.v:174618$10510_Y + attribute \src "libresoc.v:174620.18-174620.134" + wire $reduce_or$libresoc.v:174620$10512_Y + attribute \src "libresoc.v:174622.18-174622.140" + wire $reduce_or$libresoc.v:174622$10514_Y + attribute \src "libresoc.v:174624.18-174624.90" + wire $reduce_or$libresoc.v:174624$10516_Y + attribute \src "libresoc.v:174625.17-174625.103" + wire $reduce_or$libresoc.v:174625$10517_Y + attribute \src "libresoc.v:174627.17-174627.109" + wire $reduce_or$libresoc.v:174627$10519_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -368818,149 +359363,149 @@ module \ppick$208 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180417$10801 + cell $not $not$libresoc.v:174612$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:180417$10801_Y + connect \Y $not$libresoc.v:174612$10504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180419$10803 + cell $not $not$libresoc.v:174614$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:180419$10803_Y + connect \Y $not$libresoc.v:174614$10506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180421$10805 + cell $not $not$libresoc.v:174616$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:180421$10805_Y + connect \Y $not$libresoc.v:174616$10508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180422$10806 + cell $not $not$libresoc.v:174617$10509 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:180422$10806_Y + connect \Y $not$libresoc.v:174617$10509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180424$10808 + cell $not $not$libresoc.v:174619$10511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:180424$10808_Y + connect \Y $not$libresoc.v:174619$10511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180426$10810 + cell $not $not$libresoc.v:174621$10513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:180426$10810_Y + connect \Y $not$libresoc.v:174621$10513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180428$10812 + cell $not $not$libresoc.v:174623$10515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:180428$10812_Y + connect \Y $not$libresoc.v:174623$10515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180431$10815 + cell $not $not$libresoc.v:174626$10518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:180431$10815_Y + connect \Y $not$libresoc.v:174626$10518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180418$10802 + cell $reduce_or $reduce_or$libresoc.v:174613$10505 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:180418$10802_Y + connect \Y $reduce_or$libresoc.v:174613$10505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180420$10804 + cell $reduce_or $reduce_or$libresoc.v:174615$10507 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:180420$10804_Y + connect \Y $reduce_or$libresoc.v:174615$10507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180423$10807 + cell $reduce_or $reduce_or$libresoc.v:174618$10510 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:180423$10807_Y + connect \Y $reduce_or$libresoc.v:174618$10510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180425$10809 + cell $reduce_or $reduce_or$libresoc.v:174620$10512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:180425$10809_Y + connect \Y $reduce_or$libresoc.v:174620$10512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180427$10811 + cell $reduce_or $reduce_or$libresoc.v:174622$10514 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:180427$10811_Y + connect \Y $reduce_or$libresoc.v:174622$10514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180429$10813 + cell $reduce_or $reduce_or$libresoc.v:174624$10516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180429$10813_Y + connect \Y $reduce_or$libresoc.v:174624$10516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180430$10814 + cell $reduce_or $reduce_or$libresoc.v:174625$10517 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:180430$10814_Y + connect \Y $reduce_or$libresoc.v:174625$10517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180432$10816 + cell $reduce_or $reduce_or$libresoc.v:174627$10519 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:180432$10816_Y - end - connect \$7 $not$libresoc.v:180417$10801_Y - connect \$12 $reduce_or$libresoc.v:180418$10802_Y - connect \$11 $not$libresoc.v:180419$10803_Y - connect \$16 $reduce_or$libresoc.v:180420$10804_Y - connect \$15 $not$libresoc.v:180421$10805_Y - connect \$1 $not$libresoc.v:180422$10806_Y - connect \$20 $reduce_or$libresoc.v:180423$10807_Y - connect \$19 $not$libresoc.v:180424$10808_Y - connect \$24 $reduce_or$libresoc.v:180425$10809_Y - connect \$23 $not$libresoc.v:180426$10810_Y - connect \$28 $reduce_or$libresoc.v:180427$10811_Y - connect \$27 $not$libresoc.v:180428$10812_Y - connect \$31 $reduce_or$libresoc.v:180429$10813_Y - connect \$4 $reduce_or$libresoc.v:180430$10814_Y - connect \$3 $not$libresoc.v:180431$10815_Y - connect \$8 $reduce_or$libresoc.v:180432$10816_Y + connect \Y $reduce_or$libresoc.v:174627$10519_Y + end + connect \$7 $not$libresoc.v:174612$10504_Y + connect \$12 $reduce_or$libresoc.v:174613$10505_Y + connect \$11 $not$libresoc.v:174614$10506_Y + connect \$16 $reduce_or$libresoc.v:174615$10507_Y + connect \$15 $not$libresoc.v:174616$10508_Y + connect \$1 $not$libresoc.v:174617$10509_Y + connect \$20 $reduce_or$libresoc.v:174618$10510_Y + connect \$19 $not$libresoc.v:174619$10511_Y + connect \$24 $reduce_or$libresoc.v:174620$10512_Y + connect \$23 $not$libresoc.v:174621$10513_Y + connect \$28 $reduce_or$libresoc.v:174622$10514_Y + connect \$27 $not$libresoc.v:174623$10515_Y + connect \$31 $reduce_or$libresoc.v:174624$10516_Y + connect \$4 $reduce_or$libresoc.v:174625$10517_Y + connect \$3 $not$libresoc.v:174626$10518_Y + connect \$8 $reduce_or$libresoc.v:174627$10519_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -368973,43 +359518,43 @@ module \ppick$208 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:180448.1-180532.10" +attribute \src "libresoc.v:174643.1-174727.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" -module \ppick$210 - attribute \src "libresoc.v:180505.17-180505.91" - wire $not$libresoc.v:180505$10817_Y - attribute \src "libresoc.v:180507.18-180507.93" - wire $not$libresoc.v:180507$10819_Y - attribute \src "libresoc.v:180509.18-180509.93" - wire $not$libresoc.v:180509$10821_Y - attribute \src "libresoc.v:180510.17-180510.138" - wire width 8 $not$libresoc.v:180510$10822_Y - attribute \src "libresoc.v:180512.18-180512.93" - wire $not$libresoc.v:180512$10824_Y - attribute \src "libresoc.v:180514.18-180514.93" - wire $not$libresoc.v:180514$10826_Y - attribute \src "libresoc.v:180516.18-180516.93" - wire $not$libresoc.v:180516$10828_Y - attribute \src "libresoc.v:180519.17-180519.91" - wire $not$libresoc.v:180519$10831_Y - attribute \src "libresoc.v:180506.18-180506.116" - wire $reduce_or$libresoc.v:180506$10818_Y - attribute \src "libresoc.v:180508.18-180508.122" - wire $reduce_or$libresoc.v:180508$10820_Y - attribute \src "libresoc.v:180511.18-180511.128" - wire $reduce_or$libresoc.v:180511$10823_Y - attribute \src "libresoc.v:180513.18-180513.134" - wire $reduce_or$libresoc.v:180513$10825_Y - attribute \src "libresoc.v:180515.18-180515.140" - wire $reduce_or$libresoc.v:180515$10827_Y - attribute \src "libresoc.v:180517.18-180517.90" - wire $reduce_or$libresoc.v:180517$10829_Y - attribute \src "libresoc.v:180518.17-180518.103" - wire $reduce_or$libresoc.v:180518$10830_Y - attribute \src "libresoc.v:180520.17-180520.109" - wire $reduce_or$libresoc.v:180520$10832_Y +module \ppick$175 + attribute \src "libresoc.v:174700.17-174700.91" + wire $not$libresoc.v:174700$10520_Y + attribute \src "libresoc.v:174702.18-174702.93" + wire $not$libresoc.v:174702$10522_Y + attribute \src "libresoc.v:174704.18-174704.93" + wire $not$libresoc.v:174704$10524_Y + attribute \src "libresoc.v:174705.17-174705.138" + wire width 8 $not$libresoc.v:174705$10525_Y + attribute \src "libresoc.v:174707.18-174707.93" + wire $not$libresoc.v:174707$10527_Y + attribute \src "libresoc.v:174709.18-174709.93" + wire $not$libresoc.v:174709$10529_Y + attribute \src "libresoc.v:174711.18-174711.93" + wire $not$libresoc.v:174711$10531_Y + attribute \src "libresoc.v:174714.17-174714.91" + wire $not$libresoc.v:174714$10534_Y + attribute \src "libresoc.v:174701.18-174701.116" + wire $reduce_or$libresoc.v:174701$10521_Y + attribute \src "libresoc.v:174703.18-174703.122" + wire $reduce_or$libresoc.v:174703$10523_Y + attribute \src "libresoc.v:174706.18-174706.128" + wire $reduce_or$libresoc.v:174706$10526_Y + attribute \src "libresoc.v:174708.18-174708.134" + wire $reduce_or$libresoc.v:174708$10528_Y + attribute \src "libresoc.v:174710.18-174710.140" + wire $reduce_or$libresoc.v:174710$10530_Y + attribute \src "libresoc.v:174712.18-174712.90" + wire $reduce_or$libresoc.v:174712$10532_Y + attribute \src "libresoc.v:174713.17-174713.103" + wire $reduce_or$libresoc.v:174713$10533_Y + attribute \src "libresoc.v:174715.17-174715.109" + wire $reduce_or$libresoc.v:174715$10535_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -369067,149 +359612,149 @@ module \ppick$210 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180505$10817 + cell $not $not$libresoc.v:174700$10520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:180505$10817_Y + connect \Y $not$libresoc.v:174700$10520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180507$10819 + cell $not $not$libresoc.v:174702$10522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:180507$10819_Y + connect \Y $not$libresoc.v:174702$10522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180509$10821 + cell $not $not$libresoc.v:174704$10524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:180509$10821_Y + connect \Y $not$libresoc.v:174704$10524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180510$10822 + cell $not $not$libresoc.v:174705$10525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:180510$10822_Y + connect \Y $not$libresoc.v:174705$10525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180512$10824 + cell $not $not$libresoc.v:174707$10527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:180512$10824_Y + connect \Y $not$libresoc.v:174707$10527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180514$10826 + cell $not $not$libresoc.v:174709$10529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:180514$10826_Y + connect \Y $not$libresoc.v:174709$10529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180516$10828 + cell $not $not$libresoc.v:174711$10531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:180516$10828_Y + connect \Y $not$libresoc.v:174711$10531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180519$10831 + cell $not $not$libresoc.v:174714$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:180519$10831_Y + connect \Y $not$libresoc.v:174714$10534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180506$10818 + cell $reduce_or $reduce_or$libresoc.v:174701$10521 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:180506$10818_Y + connect \Y $reduce_or$libresoc.v:174701$10521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180508$10820 + cell $reduce_or $reduce_or$libresoc.v:174703$10523 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:180508$10820_Y + connect \Y $reduce_or$libresoc.v:174703$10523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180511$10823 + cell $reduce_or $reduce_or$libresoc.v:174706$10526 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:180511$10823_Y + connect \Y $reduce_or$libresoc.v:174706$10526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180513$10825 + cell $reduce_or $reduce_or$libresoc.v:174708$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:180513$10825_Y + connect \Y $reduce_or$libresoc.v:174708$10528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180515$10827 + cell $reduce_or $reduce_or$libresoc.v:174710$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:180515$10827_Y + connect \Y $reduce_or$libresoc.v:174710$10530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180517$10829 + cell $reduce_or $reduce_or$libresoc.v:174712$10532 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180517$10829_Y + connect \Y $reduce_or$libresoc.v:174712$10532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180518$10830 + cell $reduce_or $reduce_or$libresoc.v:174713$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:180518$10830_Y + connect \Y $reduce_or$libresoc.v:174713$10533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180520$10832 + cell $reduce_or $reduce_or$libresoc.v:174715$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:180520$10832_Y - end - connect \$7 $not$libresoc.v:180505$10817_Y - connect \$12 $reduce_or$libresoc.v:180506$10818_Y - connect \$11 $not$libresoc.v:180507$10819_Y - connect \$16 $reduce_or$libresoc.v:180508$10820_Y - connect \$15 $not$libresoc.v:180509$10821_Y - connect \$1 $not$libresoc.v:180510$10822_Y - connect \$20 $reduce_or$libresoc.v:180511$10823_Y - connect \$19 $not$libresoc.v:180512$10824_Y - connect \$24 $reduce_or$libresoc.v:180513$10825_Y - connect \$23 $not$libresoc.v:180514$10826_Y - connect \$28 $reduce_or$libresoc.v:180515$10827_Y - connect \$27 $not$libresoc.v:180516$10828_Y - connect \$31 $reduce_or$libresoc.v:180517$10829_Y - connect \$4 $reduce_or$libresoc.v:180518$10830_Y - connect \$3 $not$libresoc.v:180519$10831_Y - connect \$8 $reduce_or$libresoc.v:180520$10832_Y + connect \Y $reduce_or$libresoc.v:174715$10535_Y + end + connect \$7 $not$libresoc.v:174700$10520_Y + connect \$12 $reduce_or$libresoc.v:174701$10521_Y + connect \$11 $not$libresoc.v:174702$10522_Y + connect \$16 $reduce_or$libresoc.v:174703$10523_Y + connect \$15 $not$libresoc.v:174704$10524_Y + connect \$1 $not$libresoc.v:174705$10525_Y + connect \$20 $reduce_or$libresoc.v:174706$10526_Y + connect \$19 $not$libresoc.v:174707$10527_Y + connect \$24 $reduce_or$libresoc.v:174708$10528_Y + connect \$23 $not$libresoc.v:174709$10529_Y + connect \$28 $reduce_or$libresoc.v:174710$10530_Y + connect \$27 $not$libresoc.v:174711$10531_Y + connect \$31 $reduce_or$libresoc.v:174712$10532_Y + connect \$4 $reduce_or$libresoc.v:174713$10533_Y + connect \$3 $not$libresoc.v:174714$10534_Y + connect \$8 $reduce_or$libresoc.v:174715$10535_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -369222,19 +359767,19 @@ module \ppick$210 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:180536.1-180566.10" +attribute \src "libresoc.v:174731.1-174761.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a - attribute \src "libresoc.v:180557.17-180557.89" - wire width 2 $not$libresoc.v:180557$10833_Y - attribute \src "libresoc.v:180559.17-180559.91" - wire $not$libresoc.v:180559$10835_Y - attribute \src "libresoc.v:180558.17-180558.103" - wire $reduce_or$libresoc.v:180558$10834_Y - attribute \src "libresoc.v:180560.17-180560.89" - wire $reduce_or$libresoc.v:180560$10836_Y + attribute \src "libresoc.v:174752.17-174752.89" + wire width 2 $not$libresoc.v:174752$10536_Y + attribute \src "libresoc.v:174754.17-174754.91" + wire $not$libresoc.v:174754$10538_Y + attribute \src "libresoc.v:174753.17-174753.103" + wire $reduce_or$libresoc.v:174753$10537_Y + attribute \src "libresoc.v:174755.17-174755.89" + wire $reduce_or$libresoc.v:174755$10539_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -369256,56 +359801,56 @@ module \rdpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180557$10833 + cell $not $not$libresoc.v:174752$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:180557$10833_Y + connect \Y $not$libresoc.v:174752$10536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180559$10835 + cell $not $not$libresoc.v:174754$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:180559$10835_Y + connect \Y $not$libresoc.v:174754$10538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180558$10834 + cell $reduce_or $reduce_or$libresoc.v:174753$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:180558$10834_Y + connect \Y $reduce_or$libresoc.v:174753$10537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180560$10836 + cell $reduce_or $reduce_or$libresoc.v:174755$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180560$10836_Y + connect \Y $reduce_or$libresoc.v:174755$10539_Y end - connect \$1 $not$libresoc.v:180557$10833_Y - connect \$4 $reduce_or$libresoc.v:180558$10834_Y - connect \$3 $not$libresoc.v:180559$10835_Y - connect \$7 $reduce_or$libresoc.v:180560$10836_Y + connect \$1 $not$libresoc.v:174752$10536_Y + connect \$4 $reduce_or$libresoc.v:174753$10537_Y + connect \$3 $not$libresoc.v:174754$10538_Y + connect \$7 $reduce_or$libresoc.v:174755$10539_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:180570.1-180591.10" +attribute \src "libresoc.v:174765.1-174786.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b - attribute \src "libresoc.v:180585.17-180585.89" - wire $not$libresoc.v:180585$10837_Y - attribute \src "libresoc.v:180586.17-180586.89" - wire $reduce_or$libresoc.v:180586$10838_Y + attribute \src "libresoc.v:174780.17-174780.89" + wire $not$libresoc.v:174780$10540_Y + attribute \src "libresoc.v:174781.17-174781.89" + wire $reduce_or$libresoc.v:174781$10541_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -369321,37 +359866,37 @@ module \rdpick_CR_cr_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180585$10837 + cell $not $not$libresoc.v:174780$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:180585$10837_Y + connect \Y $not$libresoc.v:174780$10540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180586$10838 + cell $reduce_or $reduce_or$libresoc.v:174781$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180586$10838_Y + connect \Y $reduce_or$libresoc.v:174781$10541_Y end - connect \$1 $not$libresoc.v:180585$10837_Y - connect \$3 $reduce_or$libresoc.v:180586$10838_Y + connect \$1 $not$libresoc.v:174780$10540_Y + connect \$3 $reduce_or$libresoc.v:174781$10541_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:180595.1-180616.10" +attribute \src "libresoc.v:174790.1-174811.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c - attribute \src "libresoc.v:180610.17-180610.89" - wire $not$libresoc.v:180610$10839_Y - attribute \src "libresoc.v:180611.17-180611.89" - wire $reduce_or$libresoc.v:180611$10840_Y + attribute \src "libresoc.v:174805.17-174805.89" + wire $not$libresoc.v:174805$10542_Y + attribute \src "libresoc.v:174806.17-174806.89" + wire $reduce_or$libresoc.v:174806$10543_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -369367,37 +359912,37 @@ module \rdpick_CR_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180610$10839 + cell $not $not$libresoc.v:174805$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:180610$10839_Y + connect \Y $not$libresoc.v:174805$10542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180611$10840 + cell $reduce_or $reduce_or$libresoc.v:174806$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180611$10840_Y + connect \Y $reduce_or$libresoc.v:174806$10543_Y end - connect \$1 $not$libresoc.v:180610$10839_Y - connect \$3 $reduce_or$libresoc.v:180611$10840_Y + connect \$1 $not$libresoc.v:174805$10542_Y + connect \$3 $reduce_or$libresoc.v:174806$10543_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:180620.1-180641.10" +attribute \src "libresoc.v:174815.1-174836.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr - attribute \src "libresoc.v:180635.17-180635.89" - wire $not$libresoc.v:180635$10841_Y - attribute \src "libresoc.v:180636.17-180636.89" - wire $reduce_or$libresoc.v:180636$10842_Y + attribute \src "libresoc.v:174830.17-174830.89" + wire $not$libresoc.v:174830$10544_Y + attribute \src "libresoc.v:174831.17-174831.89" + wire $reduce_or$libresoc.v:174831$10545_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -369413,45 +359958,45 @@ module \rdpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180635$10841 + cell $not $not$libresoc.v:174830$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:180635$10841_Y + connect \Y $not$libresoc.v:174830$10544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180636$10842 + cell $reduce_or $reduce_or$libresoc.v:174831$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180636$10842_Y + connect \Y $reduce_or$libresoc.v:174831$10545_Y end - connect \$1 $not$libresoc.v:180635$10841_Y - connect \$3 $reduce_or$libresoc.v:180636$10842_Y + connect \$1 $not$libresoc.v:174830$10544_Y + connect \$3 $reduce_or$libresoc.v:174831$10545_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:180645.1-180684.10" +attribute \src "libresoc.v:174840.1-174879.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 - attribute \src "libresoc.v:180672.17-180672.91" - wire $not$libresoc.v:180672$10843_Y - attribute \src "libresoc.v:180674.17-180674.89" - wire width 3 $not$libresoc.v:180674$10845_Y - attribute \src "libresoc.v:180676.17-180676.91" - wire $not$libresoc.v:180676$10847_Y - attribute \src "libresoc.v:180673.18-180673.90" - wire $reduce_or$libresoc.v:180673$10844_Y - attribute \src "libresoc.v:180675.17-180675.103" - wire $reduce_or$libresoc.v:180675$10846_Y - attribute \src "libresoc.v:180677.17-180677.105" - wire $reduce_or$libresoc.v:180677$10848_Y + attribute \src "libresoc.v:174867.17-174867.91" + wire $not$libresoc.v:174867$10546_Y + attribute \src "libresoc.v:174869.17-174869.89" + wire width 3 $not$libresoc.v:174869$10548_Y + attribute \src "libresoc.v:174871.17-174871.91" + wire $not$libresoc.v:174871$10550_Y + attribute \src "libresoc.v:174868.18-174868.90" + wire $reduce_or$libresoc.v:174868$10547_Y + attribute \src "libresoc.v:174870.17-174870.103" + wire $reduce_or$libresoc.v:174870$10549_Y + attribute \src "libresoc.v:174872.17-174872.105" + wire $reduce_or$libresoc.v:174872$10551_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -369479,59 +360024,59 @@ module \rdpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180672$10843 + cell $not $not$libresoc.v:174867$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:180672$10843_Y + connect \Y $not$libresoc.v:174867$10546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180674$10845 + cell $not $not$libresoc.v:174869$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:180674$10845_Y + connect \Y $not$libresoc.v:174869$10548_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180676$10847 + cell $not $not$libresoc.v:174871$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:180676$10847_Y + connect \Y $not$libresoc.v:174871$10550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180673$10844 + cell $reduce_or $reduce_or$libresoc.v:174868$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180673$10844_Y + connect \Y $reduce_or$libresoc.v:174868$10547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180675$10846 + cell $reduce_or $reduce_or$libresoc.v:174870$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:180675$10846_Y + connect \Y $reduce_or$libresoc.v:174870$10549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180677$10848 + cell $reduce_or $reduce_or$libresoc.v:174872$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:180677$10848_Y - end - connect \$7 $not$libresoc.v:180672$10843_Y - connect \$11 $reduce_or$libresoc.v:180673$10844_Y - connect \$1 $not$libresoc.v:180674$10845_Y - connect \$4 $reduce_or$libresoc.v:180675$10846_Y - connect \$3 $not$libresoc.v:180676$10847_Y - connect \$8 $reduce_or$libresoc.v:180677$10848_Y + connect \Y $reduce_or$libresoc.v:174872$10551_Y + end + connect \$7 $not$libresoc.v:174867$10546_Y + connect \$11 $reduce_or$libresoc.v:174868$10547_Y + connect \$1 $not$libresoc.v:174869$10548_Y + connect \$4 $reduce_or$libresoc.v:174870$10549_Y + connect \$3 $not$libresoc.v:174871$10550_Y + connect \$8 $reduce_or$libresoc.v:174872$10551_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -369539,19 +360084,19 @@ module \rdpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:180688.1-180718.10" +attribute \src "libresoc.v:174883.1-174913.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" attribute \generator "nMigen" module \rdpick_FAST_fast2 - attribute \src "libresoc.v:180709.17-180709.89" - wire width 2 $not$libresoc.v:180709$10849_Y - attribute \src "libresoc.v:180711.17-180711.91" - wire $not$libresoc.v:180711$10851_Y - attribute \src "libresoc.v:180710.17-180710.103" - wire $reduce_or$libresoc.v:180710$10850_Y - attribute \src "libresoc.v:180712.17-180712.89" - wire $reduce_or$libresoc.v:180712$10852_Y + attribute \src "libresoc.v:174904.17-174904.89" + wire width 2 $not$libresoc.v:174904$10552_Y + attribute \src "libresoc.v:174906.17-174906.91" + wire $not$libresoc.v:174906$10554_Y + attribute \src "libresoc.v:174905.17-174905.103" + wire $reduce_or$libresoc.v:174905$10553_Y + attribute \src "libresoc.v:174907.17-174907.89" + wire $reduce_or$libresoc.v:174907$10555_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -369573,88 +360118,88 @@ module \rdpick_FAST_fast2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180709$10849 + cell $not $not$libresoc.v:174904$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:180709$10849_Y + connect \Y $not$libresoc.v:174904$10552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180711$10851 + cell $not $not$libresoc.v:174906$10554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:180711$10851_Y + connect \Y $not$libresoc.v:174906$10554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180710$10850 + cell $reduce_or $reduce_or$libresoc.v:174905$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:180710$10850_Y + connect \Y $reduce_or$libresoc.v:174905$10553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180712$10852 + cell $reduce_or $reduce_or$libresoc.v:174907$10555 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180712$10852_Y + connect \Y $reduce_or$libresoc.v:174907$10555_Y end - connect \$1 $not$libresoc.v:180709$10849_Y - connect \$4 $reduce_or$libresoc.v:180710$10850_Y - connect \$3 $not$libresoc.v:180711$10851_Y - connect \$7 $reduce_or$libresoc.v:180712$10852_Y + connect \$1 $not$libresoc.v:174904$10552_Y + connect \$4 $reduce_or$libresoc.v:174905$10553_Y + connect \$3 $not$libresoc.v:174906$10554_Y + connect \$7 $reduce_or$libresoc.v:174907$10555_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:180722.1-180815.10" +attribute \src "libresoc.v:174917.1-175010.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" attribute \generator "nMigen" module \rdpick_INT_ra - attribute \src "libresoc.v:180785.17-180785.91" - wire $not$libresoc.v:180785$10853_Y - attribute \src "libresoc.v:180787.18-180787.93" - wire $not$libresoc.v:180787$10855_Y - attribute \src "libresoc.v:180789.18-180789.93" - wire $not$libresoc.v:180789$10857_Y - attribute \src "libresoc.v:180790.17-180790.89" - wire width 9 $not$libresoc.v:180790$10858_Y - attribute \src "libresoc.v:180792.18-180792.93" - wire $not$libresoc.v:180792$10860_Y - attribute \src "libresoc.v:180794.18-180794.93" - wire $not$libresoc.v:180794$10862_Y - attribute \src "libresoc.v:180796.18-180796.93" - wire $not$libresoc.v:180796$10864_Y - attribute \src "libresoc.v:180798.18-180798.93" - wire $not$libresoc.v:180798$10866_Y - attribute \src "libresoc.v:180801.17-180801.91" - wire $not$libresoc.v:180801$10869_Y - attribute \src "libresoc.v:180786.18-180786.106" - wire $reduce_or$libresoc.v:180786$10854_Y - attribute \src "libresoc.v:180788.18-180788.106" - wire $reduce_or$libresoc.v:180788$10856_Y - attribute \src "libresoc.v:180791.18-180791.106" - wire $reduce_or$libresoc.v:180791$10859_Y - attribute \src "libresoc.v:180793.18-180793.106" - wire $reduce_or$libresoc.v:180793$10861_Y - attribute \src "libresoc.v:180795.18-180795.106" - wire $reduce_or$libresoc.v:180795$10863_Y - attribute \src "libresoc.v:180797.18-180797.106" - wire $reduce_or$libresoc.v:180797$10865_Y - attribute \src "libresoc.v:180799.18-180799.90" - wire $reduce_or$libresoc.v:180799$10867_Y - attribute \src "libresoc.v:180800.17-180800.103" - wire $reduce_or$libresoc.v:180800$10868_Y - attribute \src "libresoc.v:180802.17-180802.105" - wire $reduce_or$libresoc.v:180802$10870_Y + attribute \src "libresoc.v:174980.17-174980.91" + wire $not$libresoc.v:174980$10556_Y + attribute \src "libresoc.v:174982.18-174982.93" + wire $not$libresoc.v:174982$10558_Y + attribute \src "libresoc.v:174984.18-174984.93" + wire $not$libresoc.v:174984$10560_Y + attribute \src "libresoc.v:174985.17-174985.89" + wire width 9 $not$libresoc.v:174985$10561_Y + attribute \src "libresoc.v:174987.18-174987.93" + wire $not$libresoc.v:174987$10563_Y + attribute \src "libresoc.v:174989.18-174989.93" + wire $not$libresoc.v:174989$10565_Y + attribute \src "libresoc.v:174991.18-174991.93" + wire $not$libresoc.v:174991$10567_Y + attribute \src "libresoc.v:174993.18-174993.93" + wire $not$libresoc.v:174993$10569_Y + attribute \src "libresoc.v:174996.17-174996.91" + wire $not$libresoc.v:174996$10572_Y + attribute \src "libresoc.v:174981.18-174981.106" + wire $reduce_or$libresoc.v:174981$10557_Y + attribute \src "libresoc.v:174983.18-174983.106" + wire $reduce_or$libresoc.v:174983$10559_Y + attribute \src "libresoc.v:174986.18-174986.106" + wire $reduce_or$libresoc.v:174986$10562_Y + attribute \src "libresoc.v:174988.18-174988.106" + wire $reduce_or$libresoc.v:174988$10564_Y + attribute \src "libresoc.v:174990.18-174990.106" + wire $reduce_or$libresoc.v:174990$10566_Y + attribute \src "libresoc.v:174992.18-174992.106" + wire $reduce_or$libresoc.v:174992$10568_Y + attribute \src "libresoc.v:174994.18-174994.90" + wire $reduce_or$libresoc.v:174994$10570_Y + attribute \src "libresoc.v:174995.17-174995.103" + wire $reduce_or$libresoc.v:174995$10571_Y + attribute \src "libresoc.v:174997.17-174997.105" + wire $reduce_or$libresoc.v:174997$10573_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 9 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -369718,167 +360263,167 @@ module \rdpick_INT_ra attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180785$10853 + cell $not $not$libresoc.v:174980$10556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:180785$10853_Y + connect \Y $not$libresoc.v:174980$10556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180787$10855 + cell $not $not$libresoc.v:174982$10558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:180787$10855_Y + connect \Y $not$libresoc.v:174982$10558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180789$10857 + cell $not $not$libresoc.v:174984$10560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:180789$10857_Y + connect \Y $not$libresoc.v:174984$10560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180790$10858 + cell $not $not$libresoc.v:174985$10561 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 9 connect \A \i - connect \Y $not$libresoc.v:180790$10858_Y + connect \Y $not$libresoc.v:174985$10561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180792$10860 + cell $not $not$libresoc.v:174987$10563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:180792$10860_Y + connect \Y $not$libresoc.v:174987$10563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180794$10862 + cell $not $not$libresoc.v:174989$10565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:180794$10862_Y + connect \Y $not$libresoc.v:174989$10565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180796$10864 + cell $not $not$libresoc.v:174991$10567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:180796$10864_Y + connect \Y $not$libresoc.v:174991$10567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180798$10866 + cell $not $not$libresoc.v:174993$10569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:180798$10866_Y + connect \Y $not$libresoc.v:174993$10569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180801$10869 + cell $not $not$libresoc.v:174996$10572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:180801$10869_Y + connect \Y $not$libresoc.v:174996$10572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180786$10854 + cell $reduce_or $reduce_or$libresoc.v:174981$10557 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:180786$10854_Y + connect \Y $reduce_or$libresoc.v:174981$10557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180788$10856 + cell $reduce_or $reduce_or$libresoc.v:174983$10559 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:180788$10856_Y + connect \Y $reduce_or$libresoc.v:174983$10559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180791$10859 + cell $reduce_or $reduce_or$libresoc.v:174986$10562 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:180791$10859_Y + connect \Y $reduce_or$libresoc.v:174986$10562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180793$10861 + cell $reduce_or $reduce_or$libresoc.v:174988$10564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:180793$10861_Y + connect \Y $reduce_or$libresoc.v:174988$10564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180795$10863 + cell $reduce_or $reduce_or$libresoc.v:174990$10566 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:180795$10863_Y + connect \Y $reduce_or$libresoc.v:174990$10566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180797$10865 + cell $reduce_or $reduce_or$libresoc.v:174992$10568 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:180797$10865_Y + connect \Y $reduce_or$libresoc.v:174992$10568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180799$10867 + cell $reduce_or $reduce_or$libresoc.v:174994$10570 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180799$10867_Y + connect \Y $reduce_or$libresoc.v:174994$10570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180800$10868 + cell $reduce_or $reduce_or$libresoc.v:174995$10571 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:180800$10868_Y + connect \Y $reduce_or$libresoc.v:174995$10571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180802$10870 + cell $reduce_or $reduce_or$libresoc.v:174997$10573 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:180802$10870_Y - end - connect \$7 $not$libresoc.v:180785$10853_Y - connect \$12 $reduce_or$libresoc.v:180786$10854_Y - connect \$11 $not$libresoc.v:180787$10855_Y - connect \$16 $reduce_or$libresoc.v:180788$10856_Y - connect \$15 $not$libresoc.v:180789$10857_Y - connect \$1 $not$libresoc.v:180790$10858_Y - connect \$20 $reduce_or$libresoc.v:180791$10859_Y - connect \$19 $not$libresoc.v:180792$10860_Y - connect \$24 $reduce_or$libresoc.v:180793$10861_Y - connect \$23 $not$libresoc.v:180794$10862_Y - connect \$28 $reduce_or$libresoc.v:180795$10863_Y - connect \$27 $not$libresoc.v:180796$10864_Y - connect \$32 $reduce_or$libresoc.v:180797$10865_Y - connect \$31 $not$libresoc.v:180798$10866_Y - connect \$35 $reduce_or$libresoc.v:180799$10867_Y - connect \$4 $reduce_or$libresoc.v:180800$10868_Y - connect \$3 $not$libresoc.v:180801$10869_Y - connect \$8 $reduce_or$libresoc.v:180802$10870_Y + connect \Y $reduce_or$libresoc.v:174997$10573_Y + end + connect \$7 $not$libresoc.v:174980$10556_Y + connect \$12 $reduce_or$libresoc.v:174981$10557_Y + connect \$11 $not$libresoc.v:174982$10558_Y + connect \$16 $reduce_or$libresoc.v:174983$10559_Y + connect \$15 $not$libresoc.v:174984$10560_Y + connect \$1 $not$libresoc.v:174985$10561_Y + connect \$20 $reduce_or$libresoc.v:174986$10562_Y + connect \$19 $not$libresoc.v:174987$10563_Y + connect \$24 $reduce_or$libresoc.v:174988$10564_Y + connect \$23 $not$libresoc.v:174989$10565_Y + connect \$28 $reduce_or$libresoc.v:174990$10566_Y + connect \$27 $not$libresoc.v:174991$10567_Y + connect \$32 $reduce_or$libresoc.v:174992$10568_Y + connect \$31 $not$libresoc.v:174993$10569_Y + connect \$35 $reduce_or$libresoc.v:174994$10570_Y + connect \$4 $reduce_or$libresoc.v:174995$10571_Y + connect \$3 $not$libresoc.v:174996$10572_Y + connect \$8 $reduce_or$libresoc.v:174997$10573_Y connect \en_o \$35 connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t8 \$31 @@ -369892,43 +360437,43 @@ module \rdpick_INT_ra connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:180819.1-180903.10" +attribute \src "libresoc.v:175014.1-175098.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" attribute \generator "nMigen" module \rdpick_INT_rb - attribute \src "libresoc.v:180876.17-180876.91" - wire $not$libresoc.v:180876$10871_Y - attribute \src "libresoc.v:180878.18-180878.93" - wire $not$libresoc.v:180878$10873_Y - attribute \src "libresoc.v:180880.18-180880.93" - wire $not$libresoc.v:180880$10875_Y - attribute \src "libresoc.v:180881.17-180881.89" - wire width 8 $not$libresoc.v:180881$10876_Y - attribute \src "libresoc.v:180883.18-180883.93" - wire $not$libresoc.v:180883$10878_Y - attribute \src "libresoc.v:180885.18-180885.93" - wire $not$libresoc.v:180885$10880_Y - attribute \src "libresoc.v:180887.18-180887.93" - wire $not$libresoc.v:180887$10882_Y - attribute \src "libresoc.v:180890.17-180890.91" - wire $not$libresoc.v:180890$10885_Y - attribute \src "libresoc.v:180877.18-180877.106" - wire $reduce_or$libresoc.v:180877$10872_Y - attribute \src "libresoc.v:180879.18-180879.106" - wire $reduce_or$libresoc.v:180879$10874_Y - attribute \src "libresoc.v:180882.18-180882.106" - wire $reduce_or$libresoc.v:180882$10877_Y - attribute \src "libresoc.v:180884.18-180884.106" - wire $reduce_or$libresoc.v:180884$10879_Y - attribute \src "libresoc.v:180886.18-180886.106" - wire $reduce_or$libresoc.v:180886$10881_Y - attribute \src "libresoc.v:180888.18-180888.90" - wire $reduce_or$libresoc.v:180888$10883_Y - attribute \src "libresoc.v:180889.17-180889.103" - wire $reduce_or$libresoc.v:180889$10884_Y - attribute \src "libresoc.v:180891.17-180891.105" - wire $reduce_or$libresoc.v:180891$10886_Y + attribute \src "libresoc.v:175071.17-175071.91" + wire $not$libresoc.v:175071$10574_Y + attribute \src "libresoc.v:175073.18-175073.93" + wire $not$libresoc.v:175073$10576_Y + attribute \src "libresoc.v:175075.18-175075.93" + wire $not$libresoc.v:175075$10578_Y + attribute \src "libresoc.v:175076.17-175076.89" + wire width 8 $not$libresoc.v:175076$10579_Y + attribute \src "libresoc.v:175078.18-175078.93" + wire $not$libresoc.v:175078$10581_Y + attribute \src "libresoc.v:175080.18-175080.93" + wire $not$libresoc.v:175080$10583_Y + attribute \src "libresoc.v:175082.18-175082.93" + wire $not$libresoc.v:175082$10585_Y + attribute \src "libresoc.v:175085.17-175085.91" + wire $not$libresoc.v:175085$10588_Y + attribute \src "libresoc.v:175072.18-175072.106" + wire $reduce_or$libresoc.v:175072$10575_Y + attribute \src "libresoc.v:175074.18-175074.106" + wire $reduce_or$libresoc.v:175074$10577_Y + attribute \src "libresoc.v:175077.18-175077.106" + wire $reduce_or$libresoc.v:175077$10580_Y + attribute \src "libresoc.v:175079.18-175079.106" + wire $reduce_or$libresoc.v:175079$10582_Y + attribute \src "libresoc.v:175081.18-175081.106" + wire $reduce_or$libresoc.v:175081$10584_Y + attribute \src "libresoc.v:175083.18-175083.90" + wire $reduce_or$libresoc.v:175083$10586_Y + attribute \src "libresoc.v:175084.17-175084.103" + wire $reduce_or$libresoc.v:175084$10587_Y + attribute \src "libresoc.v:175086.17-175086.105" + wire $reduce_or$libresoc.v:175086$10589_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -369986,149 +360531,149 @@ module \rdpick_INT_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180876$10871 + cell $not $not$libresoc.v:175071$10574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:180876$10871_Y + connect \Y $not$libresoc.v:175071$10574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180878$10873 + cell $not $not$libresoc.v:175073$10576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:180878$10873_Y + connect \Y $not$libresoc.v:175073$10576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180880$10875 + cell $not $not$libresoc.v:175075$10578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:180880$10875_Y + connect \Y $not$libresoc.v:175075$10578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180881$10876 + cell $not $not$libresoc.v:175076$10579 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A \i - connect \Y $not$libresoc.v:180881$10876_Y + connect \Y $not$libresoc.v:175076$10579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180883$10878 + cell $not $not$libresoc.v:175078$10581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:180883$10878_Y + connect \Y $not$libresoc.v:175078$10581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180885$10880 + cell $not $not$libresoc.v:175080$10583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:180885$10880_Y + connect \Y $not$libresoc.v:175080$10583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180887$10882 + cell $not $not$libresoc.v:175082$10585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:180887$10882_Y + connect \Y $not$libresoc.v:175082$10585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180890$10885 + cell $not $not$libresoc.v:175085$10588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:180890$10885_Y + connect \Y $not$libresoc.v:175085$10588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180877$10872 + cell $reduce_or $reduce_or$libresoc.v:175072$10575 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:180877$10872_Y + connect \Y $reduce_or$libresoc.v:175072$10575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180879$10874 + cell $reduce_or $reduce_or$libresoc.v:175074$10577 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:180879$10874_Y + connect \Y $reduce_or$libresoc.v:175074$10577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180882$10877 + cell $reduce_or $reduce_or$libresoc.v:175077$10580 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:180882$10877_Y + connect \Y $reduce_or$libresoc.v:175077$10580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180884$10879 + cell $reduce_or $reduce_or$libresoc.v:175079$10582 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:180884$10879_Y + connect \Y $reduce_or$libresoc.v:175079$10582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180886$10881 + cell $reduce_or $reduce_or$libresoc.v:175081$10584 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:180886$10881_Y + connect \Y $reduce_or$libresoc.v:175081$10584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180888$10883 + cell $reduce_or $reduce_or$libresoc.v:175083$10586 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180888$10883_Y + connect \Y $reduce_or$libresoc.v:175083$10586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180889$10884 + cell $reduce_or $reduce_or$libresoc.v:175084$10587 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:180889$10884_Y + connect \Y $reduce_or$libresoc.v:175084$10587_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180891$10886 + cell $reduce_or $reduce_or$libresoc.v:175086$10589 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:180891$10886_Y - end - connect \$7 $not$libresoc.v:180876$10871_Y - connect \$12 $reduce_or$libresoc.v:180877$10872_Y - connect \$11 $not$libresoc.v:180878$10873_Y - connect \$16 $reduce_or$libresoc.v:180879$10874_Y - connect \$15 $not$libresoc.v:180880$10875_Y - connect \$1 $not$libresoc.v:180881$10876_Y - connect \$20 $reduce_or$libresoc.v:180882$10877_Y - connect \$19 $not$libresoc.v:180883$10878_Y - connect \$24 $reduce_or$libresoc.v:180884$10879_Y - connect \$23 $not$libresoc.v:180885$10880_Y - connect \$28 $reduce_or$libresoc.v:180886$10881_Y - connect \$27 $not$libresoc.v:180887$10882_Y - connect \$31 $reduce_or$libresoc.v:180888$10883_Y - connect \$4 $reduce_or$libresoc.v:180889$10884_Y - connect \$3 $not$libresoc.v:180890$10885_Y - connect \$8 $reduce_or$libresoc.v:180891$10886_Y + connect \Y $reduce_or$libresoc.v:175086$10589_Y + end + connect \$7 $not$libresoc.v:175071$10574_Y + connect \$12 $reduce_or$libresoc.v:175072$10575_Y + connect \$11 $not$libresoc.v:175073$10576_Y + connect \$16 $reduce_or$libresoc.v:175074$10577_Y + connect \$15 $not$libresoc.v:175075$10578_Y + connect \$1 $not$libresoc.v:175076$10579_Y + connect \$20 $reduce_or$libresoc.v:175077$10580_Y + connect \$19 $not$libresoc.v:175078$10581_Y + connect \$24 $reduce_or$libresoc.v:175079$10582_Y + connect \$23 $not$libresoc.v:175080$10583_Y + connect \$28 $reduce_or$libresoc.v:175081$10584_Y + connect \$27 $not$libresoc.v:175082$10585_Y + connect \$31 $reduce_or$libresoc.v:175083$10586_Y + connect \$4 $reduce_or$libresoc.v:175084$10587_Y + connect \$3 $not$libresoc.v:175085$10588_Y + connect \$8 $reduce_or$libresoc.v:175086$10589_Y connect \en_o \$31 connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t7 \$27 @@ -370141,19 +360686,19 @@ module \rdpick_INT_rb connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:180907.1-180937.10" +attribute \src "libresoc.v:175102.1-175132.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" attribute \generator "nMigen" module \rdpick_INT_rc - attribute \src "libresoc.v:180928.17-180928.89" - wire width 2 $not$libresoc.v:180928$10887_Y - attribute \src "libresoc.v:180930.17-180930.91" - wire $not$libresoc.v:180930$10889_Y - attribute \src "libresoc.v:180929.17-180929.103" - wire $reduce_or$libresoc.v:180929$10888_Y - attribute \src "libresoc.v:180931.17-180931.89" - wire $reduce_or$libresoc.v:180931$10890_Y + attribute \src "libresoc.v:175123.17-175123.89" + wire width 2 $not$libresoc.v:175123$10590_Y + attribute \src "libresoc.v:175125.17-175125.91" + wire $not$libresoc.v:175125$10592_Y + attribute \src "libresoc.v:175124.17-175124.103" + wire $reduce_or$libresoc.v:175124$10591_Y + attribute \src "libresoc.v:175126.17-175126.89" + wire $reduce_or$libresoc.v:175126$10593_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -370175,56 +360720,56 @@ module \rdpick_INT_rc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180928$10887 + cell $not $not$libresoc.v:175123$10590 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:180928$10887_Y + connect \Y $not$libresoc.v:175123$10590_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180930$10889 + cell $not $not$libresoc.v:175125$10592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:180930$10889_Y + connect \Y $not$libresoc.v:175125$10592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180929$10888 + cell $reduce_or $reduce_or$libresoc.v:175124$10591 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:180929$10888_Y + connect \Y $reduce_or$libresoc.v:175124$10591_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180931$10890 + cell $reduce_or $reduce_or$libresoc.v:175126$10593 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180931$10890_Y + connect \Y $reduce_or$libresoc.v:175126$10593_Y end - connect \$1 $not$libresoc.v:180928$10887_Y - connect \$4 $reduce_or$libresoc.v:180929$10888_Y - connect \$3 $not$libresoc.v:180930$10889_Y - connect \$7 $reduce_or$libresoc.v:180931$10890_Y + connect \$1 $not$libresoc.v:175123$10590_Y + connect \$4 $reduce_or$libresoc.v:175124$10591_Y + connect \$3 $not$libresoc.v:175125$10592_Y + connect \$7 $reduce_or$libresoc.v:175126$10593_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:180941.1-180962.10" +attribute \src "libresoc.v:175136.1-175157.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 - attribute \src "libresoc.v:180956.17-180956.89" - wire $not$libresoc.v:180956$10891_Y - attribute \src "libresoc.v:180957.17-180957.89" - wire $reduce_or$libresoc.v:180957$10892_Y + attribute \src "libresoc.v:175151.17-175151.89" + wire $not$libresoc.v:175151$10594_Y + attribute \src "libresoc.v:175152.17-175152.89" + wire $reduce_or$libresoc.v:175152$10595_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -370240,45 +360785,45 @@ module \rdpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180956$10891 + cell $not $not$libresoc.v:175151$10594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:180956$10891_Y + connect \Y $not$libresoc.v:175151$10594_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180957$10892 + cell $reduce_or $reduce_or$libresoc.v:175152$10595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180957$10892_Y + connect \Y $reduce_or$libresoc.v:175152$10595_Y end - connect \$1 $not$libresoc.v:180956$10891_Y - connect \$3 $reduce_or$libresoc.v:180957$10892_Y + connect \$1 $not$libresoc.v:175151$10594_Y + connect \$3 $reduce_or$libresoc.v:175152$10595_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:180966.1-181005.10" +attribute \src "libresoc.v:175161.1-175200.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca - attribute \src "libresoc.v:180993.17-180993.91" - wire $not$libresoc.v:180993$10893_Y - attribute \src "libresoc.v:180995.17-180995.89" - wire width 3 $not$libresoc.v:180995$10895_Y - attribute \src "libresoc.v:180997.17-180997.91" - wire $not$libresoc.v:180997$10897_Y - attribute \src "libresoc.v:180994.18-180994.90" - wire $reduce_or$libresoc.v:180994$10894_Y - attribute \src "libresoc.v:180996.17-180996.103" - wire $reduce_or$libresoc.v:180996$10896_Y - attribute \src "libresoc.v:180998.17-180998.105" - wire $reduce_or$libresoc.v:180998$10898_Y + attribute \src "libresoc.v:175188.17-175188.91" + wire $not$libresoc.v:175188$10596_Y + attribute \src "libresoc.v:175190.17-175190.89" + wire width 3 $not$libresoc.v:175190$10598_Y + attribute \src "libresoc.v:175192.17-175192.91" + wire $not$libresoc.v:175192$10600_Y + attribute \src "libresoc.v:175189.18-175189.90" + wire $reduce_or$libresoc.v:175189$10597_Y + attribute \src "libresoc.v:175191.17-175191.103" + wire $reduce_or$libresoc.v:175191$10599_Y + attribute \src "libresoc.v:175193.17-175193.105" + wire $reduce_or$libresoc.v:175193$10601_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -370306,59 +360851,59 @@ module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180993$10893 + cell $not $not$libresoc.v:175188$10596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:180993$10893_Y + connect \Y $not$libresoc.v:175188$10596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:180995$10895 + cell $not $not$libresoc.v:175190$10598 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:180995$10895_Y + connect \Y $not$libresoc.v:175190$10598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:180997$10897 + cell $not $not$libresoc.v:175192$10600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:180997$10897_Y + connect \Y $not$libresoc.v:175192$10600_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:180994$10894 + cell $reduce_or $reduce_or$libresoc.v:175189$10597 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:180994$10894_Y + connect \Y $reduce_or$libresoc.v:175189$10597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180996$10896 + cell $reduce_or $reduce_or$libresoc.v:175191$10599 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:180996$10896_Y + connect \Y $reduce_or$libresoc.v:175191$10599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:180998$10898 + cell $reduce_or $reduce_or$libresoc.v:175193$10601 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:180998$10898_Y - end - connect \$7 $not$libresoc.v:180993$10893_Y - connect \$11 $reduce_or$libresoc.v:180994$10894_Y - connect \$1 $not$libresoc.v:180995$10895_Y - connect \$4 $reduce_or$libresoc.v:180996$10896_Y - connect \$3 $not$libresoc.v:180997$10897_Y - connect \$8 $reduce_or$libresoc.v:180998$10898_Y + connect \Y $reduce_or$libresoc.v:175193$10601_Y + end + connect \$7 $not$libresoc.v:175188$10596_Y + connect \$11 $reduce_or$libresoc.v:175189$10597_Y + connect \$1 $not$libresoc.v:175190$10598_Y + connect \$4 $reduce_or$libresoc.v:175191$10599_Y + connect \$3 $not$libresoc.v:175192$10600_Y + connect \$8 $reduce_or$libresoc.v:175193$10601_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -370366,15 +360911,15 @@ module \rdpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:181009.1-181030.10" +attribute \src "libresoc.v:175204.1-175225.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov - attribute \src "libresoc.v:181024.17-181024.89" - wire $not$libresoc.v:181024$10899_Y - attribute \src "libresoc.v:181025.17-181025.89" - wire $reduce_or$libresoc.v:181025$10900_Y + attribute \src "libresoc.v:175219.17-175219.89" + wire $not$libresoc.v:175219$10602_Y + attribute \src "libresoc.v:175220.17-175220.89" + wire $reduce_or$libresoc.v:175220$10603_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -370390,57 +360935,57 @@ module \rdpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:181024$10899 + cell $not $not$libresoc.v:175219$10602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:181024$10899_Y + connect \Y $not$libresoc.v:175219$10602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:181025$10900 + cell $reduce_or $reduce_or$libresoc.v:175220$10603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:181025$10900_Y + connect \Y $reduce_or$libresoc.v:175220$10603_Y end - connect \$1 $not$libresoc.v:181024$10899_Y - connect \$3 $reduce_or$libresoc.v:181025$10900_Y + connect \$1 $not$libresoc.v:175219$10602_Y + connect \$3 $reduce_or$libresoc.v:175220$10603_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:181034.1-181100.10" +attribute \src "libresoc.v:175229.1-175295.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so - attribute \src "libresoc.v:181079.17-181079.91" - wire $not$libresoc.v:181079$10901_Y - attribute \src "libresoc.v:181081.18-181081.93" - wire $not$libresoc.v:181081$10903_Y - attribute \src "libresoc.v:181083.18-181083.93" - wire $not$libresoc.v:181083$10905_Y - attribute \src "libresoc.v:181084.17-181084.89" - wire width 6 $not$libresoc.v:181084$10906_Y - attribute \src "libresoc.v:181086.18-181086.93" - wire $not$libresoc.v:181086$10908_Y - attribute \src "libresoc.v:181089.17-181089.91" - wire $not$libresoc.v:181089$10911_Y - attribute \src "libresoc.v:181080.18-181080.106" - wire $reduce_or$libresoc.v:181080$10902_Y - attribute \src "libresoc.v:181082.18-181082.106" - wire $reduce_or$libresoc.v:181082$10904_Y - attribute \src "libresoc.v:181085.18-181085.106" - wire $reduce_or$libresoc.v:181085$10907_Y - attribute \src "libresoc.v:181087.18-181087.90" - wire $reduce_or$libresoc.v:181087$10909_Y - attribute \src "libresoc.v:181088.17-181088.103" - wire $reduce_or$libresoc.v:181088$10910_Y - attribute \src "libresoc.v:181090.17-181090.105" - wire $reduce_or$libresoc.v:181090$10912_Y + attribute \src "libresoc.v:175274.17-175274.91" + wire $not$libresoc.v:175274$10604_Y + attribute \src "libresoc.v:175276.18-175276.93" + wire $not$libresoc.v:175276$10606_Y + attribute \src "libresoc.v:175278.18-175278.93" + wire $not$libresoc.v:175278$10608_Y + attribute \src "libresoc.v:175279.17-175279.89" + wire width 6 $not$libresoc.v:175279$10609_Y + attribute \src "libresoc.v:175281.18-175281.93" + wire $not$libresoc.v:175281$10611_Y + attribute \src "libresoc.v:175284.17-175284.91" + wire $not$libresoc.v:175284$10614_Y + attribute \src "libresoc.v:175275.18-175275.106" + wire $reduce_or$libresoc.v:175275$10605_Y + attribute \src "libresoc.v:175277.18-175277.106" + wire $reduce_or$libresoc.v:175277$10607_Y + attribute \src "libresoc.v:175280.18-175280.106" + wire $reduce_or$libresoc.v:175280$10610_Y + attribute \src "libresoc.v:175282.18-175282.90" + wire $reduce_or$libresoc.v:175282$10612_Y + attribute \src "libresoc.v:175283.17-175283.103" + wire $reduce_or$libresoc.v:175283$10613_Y + attribute \src "libresoc.v:175285.17-175285.105" + wire $reduce_or$libresoc.v:175285$10615_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -370486,113 +361031,113 @@ module \rdpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:181079$10901 + cell $not $not$libresoc.v:175274$10604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:181079$10901_Y + connect \Y $not$libresoc.v:175274$10604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:181081$10903 + cell $not $not$libresoc.v:175276$10606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:181081$10903_Y + connect \Y $not$libresoc.v:175276$10606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:181083$10905 + cell $not $not$libresoc.v:175278$10608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:181083$10905_Y + connect \Y $not$libresoc.v:175278$10608_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:181084$10906 + cell $not $not$libresoc.v:175279$10609 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:181084$10906_Y + connect \Y $not$libresoc.v:175279$10609_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:181086$10908 + cell $not $not$libresoc.v:175281$10611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:181086$10908_Y + connect \Y $not$libresoc.v:175281$10611_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:181089$10911 + cell $not $not$libresoc.v:175284$10614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:181089$10911_Y + connect \Y $not$libresoc.v:175284$10614_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:181080$10902 + cell $reduce_or $reduce_or$libresoc.v:175275$10605 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:181080$10902_Y + connect \Y $reduce_or$libresoc.v:175275$10605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:181082$10904 + cell $reduce_or $reduce_or$libresoc.v:175277$10607 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:181082$10904_Y + connect \Y $reduce_or$libresoc.v:175277$10607_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:181085$10907 + cell $reduce_or $reduce_or$libresoc.v:175280$10610 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:181085$10907_Y + connect \Y $reduce_or$libresoc.v:175280$10610_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:181087$10909 + cell $reduce_or $reduce_or$libresoc.v:175282$10612 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:181087$10909_Y + connect \Y $reduce_or$libresoc.v:175282$10612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:181088$10910 + cell $reduce_or $reduce_or$libresoc.v:175283$10613 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:181088$10910_Y + connect \Y $reduce_or$libresoc.v:175283$10613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:181090$10912 + cell $reduce_or $reduce_or$libresoc.v:175285$10615 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:181090$10912_Y - end - connect \$7 $not$libresoc.v:181079$10901_Y - connect \$12 $reduce_or$libresoc.v:181080$10902_Y - connect \$11 $not$libresoc.v:181081$10903_Y - connect \$16 $reduce_or$libresoc.v:181082$10904_Y - connect \$15 $not$libresoc.v:181083$10905_Y - connect \$1 $not$libresoc.v:181084$10906_Y - connect \$20 $reduce_or$libresoc.v:181085$10907_Y - connect \$19 $not$libresoc.v:181086$10908_Y - connect \$23 $reduce_or$libresoc.v:181087$10909_Y - connect \$4 $reduce_or$libresoc.v:181088$10910_Y - connect \$3 $not$libresoc.v:181089$10911_Y - connect \$8 $reduce_or$libresoc.v:181090$10912_Y + connect \Y $reduce_or$libresoc.v:175285$10615_Y + end + connect \$7 $not$libresoc.v:175274$10604_Y + connect \$12 $reduce_or$libresoc.v:175275$10605_Y + connect \$11 $not$libresoc.v:175276$10606_Y + connect \$16 $reduce_or$libresoc.v:175277$10607_Y + connect \$15 $not$libresoc.v:175278$10608_Y + connect \$1 $not$libresoc.v:175279$10609_Y + connect \$20 $reduce_or$libresoc.v:175280$10610_Y + connect \$19 $not$libresoc.v:175281$10611_Y + connect \$23 $reduce_or$libresoc.v:175282$10612_Y + connect \$4 $reduce_or$libresoc.v:175283$10613_Y + connect \$3 $not$libresoc.v:175284$10614_Y + connect \$8 $reduce_or$libresoc.v:175285$10615_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -370603,177 +361148,177 @@ module \rdpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:181104.1-181575.10" +attribute \src "libresoc.v:175299.1-175770.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 - attribute \src "libresoc.v:181105.7-181105.20" + attribute \src "libresoc.v:175300.7-175300.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181435.3-181474.6" - wire width 4 $0\r0__data_o$next[3:0]$10968 - attribute \src "libresoc.v:181190.3-181191.37" + attribute \src "libresoc.v:175630.3-175669.6" + wire width 4 $0\r0__data_o$next[3:0]$10671 + attribute \src "libresoc.v:175385.3-175386.37" wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:181505.3-181544.6" - wire width 4 $0\r20__data_o$next[3:0]$10982 - attribute \src "libresoc.v:181188.3-181189.39" + attribute \src "libresoc.v:175700.3-175739.6" + wire width 4 $0\r20__data_o$next[3:0]$10685 + attribute \src "libresoc.v:175383.3-175384.39" wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:181268.3-181294.6" - wire width 4 $0\reg$next[3:0]$10934 - attribute \src "libresoc.v:181186.3-181187.25" + attribute \src "libresoc.v:175463.3-175489.6" + wire width 4 $0\reg$next[3:0]$10637 + attribute \src "libresoc.v:175381.3-175382.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:181198.3-181237.6" - wire width 4 $0\src10__data_o$next[3:0]$10925 - attribute \src "libresoc.v:181196.3-181197.43" + attribute \src "libresoc.v:175393.3-175432.6" + wire width 4 $0\src10__data_o$next[3:0]$10628 + attribute \src "libresoc.v:175391.3-175392.43" wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:181295.3-181334.6" - wire width 4 $0\src20__data_o$next[3:0]$10940 - attribute \src "libresoc.v:181194.3-181195.43" + attribute \src "libresoc.v:175490.3-175529.6" + wire width 4 $0\src20__data_o$next[3:0]$10643 + attribute \src "libresoc.v:175389.3-175390.43" wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:181365.3-181404.6" - wire width 4 $0\src30__data_o$next[3:0]$10954 - attribute \src "libresoc.v:181192.3-181193.43" + attribute \src "libresoc.v:175560.3-175599.6" + wire width 4 $0\src30__data_o$next[3:0]$10657 + attribute \src "libresoc.v:175387.3-175388.43" wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:181475.3-181504.6" - wire $0\wr_detect$10[0:0]$10976 - attribute \src "libresoc.v:181545.3-181574.6" - wire $0\wr_detect$13[0:0]$10990 - attribute \src "libresoc.v:181335.3-181364.6" - wire $0\wr_detect$4[0:0]$10948 - attribute \src "libresoc.v:181405.3-181434.6" - wire $0\wr_detect$7[0:0]$10962 - attribute \src "libresoc.v:181238.3-181267.6" + attribute \src "libresoc.v:175670.3-175699.6" + wire $0\wr_detect$10[0:0]$10679 + attribute \src "libresoc.v:175740.3-175769.6" + wire $0\wr_detect$13[0:0]$10693 + attribute \src "libresoc.v:175530.3-175559.6" + wire $0\wr_detect$4[0:0]$10651 + attribute \src "libresoc.v:175600.3-175629.6" + wire $0\wr_detect$7[0:0]$10665 + attribute \src "libresoc.v:175433.3-175462.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:181435.3-181474.6" - wire width 4 $1\r0__data_o$next[3:0]$10969 - attribute \src "libresoc.v:181130.13-181130.30" + attribute \src "libresoc.v:175630.3-175669.6" + wire width 4 $1\r0__data_o$next[3:0]$10672 + attribute \src "libresoc.v:175325.13-175325.30" wire width 4 $1\r0__data_o[3:0] - attribute \src "libresoc.v:181505.3-181544.6" - wire width 4 $1\r20__data_o$next[3:0]$10983 - attribute \src "libresoc.v:181137.13-181137.31" + attribute \src "libresoc.v:175700.3-175739.6" + wire width 4 $1\r20__data_o$next[3:0]$10686 + attribute \src "libresoc.v:175332.13-175332.31" wire width 4 $1\r20__data_o[3:0] - attribute \src "libresoc.v:181268.3-181294.6" - wire width 4 $1\reg$next[3:0]$10935 - attribute \src "libresoc.v:181143.13-181143.25" + attribute \src "libresoc.v:175463.3-175489.6" + wire width 4 $1\reg$next[3:0]$10638 + attribute \src "libresoc.v:175338.13-175338.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:181198.3-181237.6" - wire width 4 $1\src10__data_o$next[3:0]$10926 - attribute \src "libresoc.v:181148.13-181148.33" + attribute \src "libresoc.v:175393.3-175432.6" + wire width 4 $1\src10__data_o$next[3:0]$10629 + attribute \src "libresoc.v:175343.13-175343.33" wire width 4 $1\src10__data_o[3:0] - attribute \src "libresoc.v:181295.3-181334.6" - wire width 4 $1\src20__data_o$next[3:0]$10941 - attribute \src "libresoc.v:181155.13-181155.33" + attribute \src "libresoc.v:175490.3-175529.6" + wire width 4 $1\src20__data_o$next[3:0]$10644 + attribute \src "libresoc.v:175350.13-175350.33" wire width 4 $1\src20__data_o[3:0] - attribute \src "libresoc.v:181365.3-181404.6" - wire width 4 $1\src30__data_o$next[3:0]$10955 - attribute \src "libresoc.v:181162.13-181162.33" + attribute \src "libresoc.v:175560.3-175599.6" + wire width 4 $1\src30__data_o$next[3:0]$10658 + attribute \src "libresoc.v:175357.13-175357.33" wire width 4 $1\src30__data_o[3:0] - attribute \src "libresoc.v:181475.3-181504.6" - wire $1\wr_detect$10[0:0]$10977 - attribute \src "libresoc.v:181545.3-181574.6" - wire $1\wr_detect$13[0:0]$10991 - attribute \src "libresoc.v:181335.3-181364.6" - wire $1\wr_detect$4[0:0]$10949 - attribute \src "libresoc.v:181405.3-181434.6" - wire $1\wr_detect$7[0:0]$10963 - attribute \src "libresoc.v:181238.3-181267.6" + attribute \src "libresoc.v:175670.3-175699.6" + wire $1\wr_detect$10[0:0]$10680 + attribute \src "libresoc.v:175740.3-175769.6" + wire $1\wr_detect$13[0:0]$10694 + attribute \src "libresoc.v:175530.3-175559.6" + wire $1\wr_detect$4[0:0]$10652 + attribute \src "libresoc.v:175600.3-175629.6" + wire $1\wr_detect$7[0:0]$10666 + attribute \src "libresoc.v:175433.3-175462.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:181435.3-181474.6" - wire width 4 $2\r0__data_o$next[3:0]$10970 - attribute \src "libresoc.v:181505.3-181544.6" - wire width 4 $2\r20__data_o$next[3:0]$10984 - attribute \src "libresoc.v:181268.3-181294.6" - wire width 4 $2\reg$next[3:0]$10936 - attribute \src "libresoc.v:181198.3-181237.6" - wire width 4 $2\src10__data_o$next[3:0]$10927 - attribute \src "libresoc.v:181295.3-181334.6" - wire width 4 $2\src20__data_o$next[3:0]$10942 - attribute \src "libresoc.v:181365.3-181404.6" - wire width 4 $2\src30__data_o$next[3:0]$10956 - attribute \src "libresoc.v:181475.3-181504.6" - wire $2\wr_detect$10[0:0]$10978 - attribute \src "libresoc.v:181545.3-181574.6" - wire $2\wr_detect$13[0:0]$10992 - attribute \src "libresoc.v:181335.3-181364.6" - wire $2\wr_detect$4[0:0]$10950 - attribute \src "libresoc.v:181405.3-181434.6" - wire $2\wr_detect$7[0:0]$10964 - attribute \src "libresoc.v:181238.3-181267.6" + attribute \src "libresoc.v:175630.3-175669.6" + wire width 4 $2\r0__data_o$next[3:0]$10673 + attribute \src "libresoc.v:175700.3-175739.6" + wire width 4 $2\r20__data_o$next[3:0]$10687 + attribute \src "libresoc.v:175463.3-175489.6" + wire width 4 $2\reg$next[3:0]$10639 + attribute \src "libresoc.v:175393.3-175432.6" + wire width 4 $2\src10__data_o$next[3:0]$10630 + attribute \src "libresoc.v:175490.3-175529.6" + wire width 4 $2\src20__data_o$next[3:0]$10645 + attribute \src "libresoc.v:175560.3-175599.6" + wire width 4 $2\src30__data_o$next[3:0]$10659 + attribute \src "libresoc.v:175670.3-175699.6" + wire $2\wr_detect$10[0:0]$10681 + attribute \src "libresoc.v:175740.3-175769.6" + wire $2\wr_detect$13[0:0]$10695 + attribute \src "libresoc.v:175530.3-175559.6" + wire $2\wr_detect$4[0:0]$10653 + attribute \src "libresoc.v:175600.3-175629.6" + wire $2\wr_detect$7[0:0]$10667 + attribute \src "libresoc.v:175433.3-175462.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:181435.3-181474.6" - wire width 4 $3\r0__data_o$next[3:0]$10971 - attribute \src "libresoc.v:181505.3-181544.6" - wire width 4 $3\r20__data_o$next[3:0]$10985 - attribute \src "libresoc.v:181268.3-181294.6" - wire width 4 $3\reg$next[3:0]$10937 - attribute \src "libresoc.v:181198.3-181237.6" - wire width 4 $3\src10__data_o$next[3:0]$10928 - attribute \src "libresoc.v:181295.3-181334.6" - wire width 4 $3\src20__data_o$next[3:0]$10943 - attribute \src "libresoc.v:181365.3-181404.6" - wire width 4 $3\src30__data_o$next[3:0]$10957 - attribute \src "libresoc.v:181475.3-181504.6" - wire $3\wr_detect$10[0:0]$10979 - attribute \src "libresoc.v:181545.3-181574.6" - wire $3\wr_detect$13[0:0]$10993 - attribute \src "libresoc.v:181335.3-181364.6" - wire $3\wr_detect$4[0:0]$10951 - attribute \src "libresoc.v:181405.3-181434.6" - wire $3\wr_detect$7[0:0]$10965 - attribute \src "libresoc.v:181238.3-181267.6" + attribute \src "libresoc.v:175630.3-175669.6" + wire width 4 $3\r0__data_o$next[3:0]$10674 + attribute \src "libresoc.v:175700.3-175739.6" + wire width 4 $3\r20__data_o$next[3:0]$10688 + attribute \src "libresoc.v:175463.3-175489.6" + wire width 4 $3\reg$next[3:0]$10640 + attribute \src "libresoc.v:175393.3-175432.6" + wire width 4 $3\src10__data_o$next[3:0]$10631 + attribute \src "libresoc.v:175490.3-175529.6" + wire width 4 $3\src20__data_o$next[3:0]$10646 + attribute \src "libresoc.v:175560.3-175599.6" + wire width 4 $3\src30__data_o$next[3:0]$10660 + attribute \src "libresoc.v:175670.3-175699.6" + wire $3\wr_detect$10[0:0]$10682 + attribute \src "libresoc.v:175740.3-175769.6" + wire $3\wr_detect$13[0:0]$10696 + attribute \src "libresoc.v:175530.3-175559.6" + wire $3\wr_detect$4[0:0]$10654 + attribute \src "libresoc.v:175600.3-175629.6" + wire $3\wr_detect$7[0:0]$10668 + attribute \src "libresoc.v:175433.3-175462.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:181435.3-181474.6" - wire width 4 $4\r0__data_o$next[3:0]$10972 - attribute \src "libresoc.v:181505.3-181544.6" - wire width 4 $4\r20__data_o$next[3:0]$10986 - attribute \src "libresoc.v:181268.3-181294.6" - wire width 4 $4\reg$next[3:0]$10938 - attribute \src "libresoc.v:181198.3-181237.6" - wire width 4 $4\src10__data_o$next[3:0]$10929 - attribute \src "libresoc.v:181295.3-181334.6" - wire width 4 $4\src20__data_o$next[3:0]$10944 - attribute \src "libresoc.v:181365.3-181404.6" - wire width 4 $4\src30__data_o$next[3:0]$10958 - attribute \src "libresoc.v:181475.3-181504.6" - wire $4\wr_detect$10[0:0]$10980 - attribute \src "libresoc.v:181545.3-181574.6" - wire $4\wr_detect$13[0:0]$10994 - attribute \src "libresoc.v:181335.3-181364.6" - wire $4\wr_detect$4[0:0]$10952 - attribute \src "libresoc.v:181405.3-181434.6" - wire $4\wr_detect$7[0:0]$10966 - attribute \src "libresoc.v:181238.3-181267.6" + attribute \src "libresoc.v:175630.3-175669.6" + wire width 4 $4\r0__data_o$next[3:0]$10675 + attribute \src "libresoc.v:175700.3-175739.6" + wire width 4 $4\r20__data_o$next[3:0]$10689 + attribute \src "libresoc.v:175463.3-175489.6" + wire width 4 $4\reg$next[3:0]$10641 + attribute \src "libresoc.v:175393.3-175432.6" + wire width 4 $4\src10__data_o$next[3:0]$10632 + attribute \src "libresoc.v:175490.3-175529.6" + wire width 4 $4\src20__data_o$next[3:0]$10647 + attribute \src "libresoc.v:175560.3-175599.6" + wire width 4 $4\src30__data_o$next[3:0]$10661 + attribute \src "libresoc.v:175670.3-175699.6" + wire $4\wr_detect$10[0:0]$10683 + attribute \src "libresoc.v:175740.3-175769.6" + wire $4\wr_detect$13[0:0]$10697 + attribute \src "libresoc.v:175530.3-175559.6" + wire $4\wr_detect$4[0:0]$10655 + attribute \src "libresoc.v:175600.3-175629.6" + wire $4\wr_detect$7[0:0]$10669 + attribute \src "libresoc.v:175433.3-175462.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:181435.3-181474.6" - wire width 4 $5\r0__data_o$next[3:0]$10973 - attribute \src "libresoc.v:181505.3-181544.6" - wire width 4 $5\r20__data_o$next[3:0]$10987 - attribute \src "libresoc.v:181198.3-181237.6" - wire width 4 $5\src10__data_o$next[3:0]$10930 - attribute \src "libresoc.v:181295.3-181334.6" - wire width 4 $5\src20__data_o$next[3:0]$10945 - attribute \src "libresoc.v:181365.3-181404.6" - wire width 4 $5\src30__data_o$next[3:0]$10959 - attribute \src "libresoc.v:181435.3-181474.6" - wire width 4 $6\r0__data_o$next[3:0]$10974 - attribute \src "libresoc.v:181505.3-181544.6" - wire width 4 $6\r20__data_o$next[3:0]$10988 - attribute \src "libresoc.v:181198.3-181237.6" - wire width 4 $6\src10__data_o$next[3:0]$10931 - attribute \src "libresoc.v:181295.3-181334.6" - wire width 4 $6\src20__data_o$next[3:0]$10946 - attribute \src "libresoc.v:181365.3-181404.6" - wire width 4 $6\src30__data_o$next[3:0]$10960 - attribute \src "libresoc.v:181181.17-181181.104" - wire $not$libresoc.v:181181$10913_Y - attribute \src "libresoc.v:181182.18-181182.105" - wire $not$libresoc.v:181182$10914_Y - attribute \src "libresoc.v:181183.17-181183.100" - wire $not$libresoc.v:181183$10915_Y - attribute \src "libresoc.v:181184.17-181184.103" - wire $not$libresoc.v:181184$10916_Y - attribute \src "libresoc.v:181185.17-181185.103" - wire $not$libresoc.v:181185$10917_Y + attribute \src "libresoc.v:175630.3-175669.6" + wire width 4 $5\r0__data_o$next[3:0]$10676 + attribute \src "libresoc.v:175700.3-175739.6" + wire width 4 $5\r20__data_o$next[3:0]$10690 + attribute \src "libresoc.v:175393.3-175432.6" + wire width 4 $5\src10__data_o$next[3:0]$10633 + attribute \src "libresoc.v:175490.3-175529.6" + wire width 4 $5\src20__data_o$next[3:0]$10648 + attribute \src "libresoc.v:175560.3-175599.6" + wire width 4 $5\src30__data_o$next[3:0]$10662 + attribute \src "libresoc.v:175630.3-175669.6" + wire width 4 $6\r0__data_o$next[3:0]$10677 + attribute \src "libresoc.v:175700.3-175739.6" + wire width 4 $6\r20__data_o$next[3:0]$10691 + attribute \src "libresoc.v:175393.3-175432.6" + wire width 4 $6\src10__data_o$next[3:0]$10634 + attribute \src "libresoc.v:175490.3-175529.6" + wire width 4 $6\src20__data_o$next[3:0]$10649 + attribute \src "libresoc.v:175560.3-175599.6" + wire width 4 $6\src30__data_o$next[3:0]$10663 + attribute \src "libresoc.v:175376.17-175376.104" + wire $not$libresoc.v:175376$10616_Y + attribute \src "libresoc.v:175377.18-175377.105" + wire $not$libresoc.v:175377$10617_Y + attribute \src "libresoc.v:175378.17-175378.100" + wire $not$libresoc.v:175378$10618_Y + attribute \src "libresoc.v:175379.17-175379.103" + wire $not$libresoc.v:175379$10619_Y + attribute \src "libresoc.v:175380.17-175380.103" + wire $not$libresoc.v:175380$10620_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -370784,9 +361329,9 @@ module \reg_0 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest10__data_i @@ -370796,7 +361341,7 @@ module \reg_0 wire width 4 input 11 \dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest20__wen - attribute \src "libresoc.v:181105.7-181105.15" + attribute \src "libresoc.v:175300.7-175300.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r0__data_o @@ -370847,152 +361392,152 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181181$10913 + cell $not $not$libresoc.v:175376$10616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:181181$10913_Y + connect \Y $not$libresoc.v:175376$10616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181182$10914 + cell $not $not$libresoc.v:175377$10617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:181182$10914_Y + connect \Y $not$libresoc.v:175377$10617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181183$10915 + cell $not $not$libresoc.v:175378$10618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:181183$10915_Y + connect \Y $not$libresoc.v:175378$10618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181184$10916 + cell $not $not$libresoc.v:175379$10619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:181184$10916_Y + connect \Y $not$libresoc.v:175379$10619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181185$10917 + cell $not $not$libresoc.v:175380$10620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:181185$10917_Y + connect \Y $not$libresoc.v:175380$10620_Y end - attribute \src "libresoc.v:181105.7-181105.20" - process $proc$libresoc.v:181105$10995 + attribute \src "libresoc.v:175300.7-175300.20" + process $proc$libresoc.v:175300$10698 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181130.13-181130.30" - process $proc$libresoc.v:181130$10996 + attribute \src "libresoc.v:175325.13-175325.30" + process $proc$libresoc.v:175325$10699 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end - attribute \src "libresoc.v:181137.13-181137.31" - process $proc$libresoc.v:181137$10997 + attribute \src "libresoc.v:175332.13-175332.31" + process $proc$libresoc.v:175332$10700 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end - attribute \src "libresoc.v:181143.13-181143.25" - process $proc$libresoc.v:181143$10998 + attribute \src "libresoc.v:175338.13-175338.25" + process $proc$libresoc.v:175338$10701 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:181148.13-181148.33" - process $proc$libresoc.v:181148$10999 + attribute \src "libresoc.v:175343.13-175343.33" + process $proc$libresoc.v:175343$10702 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end - attribute \src "libresoc.v:181155.13-181155.33" - process $proc$libresoc.v:181155$11000 + attribute \src "libresoc.v:175350.13-175350.33" + process $proc$libresoc.v:175350$10703 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end - attribute \src "libresoc.v:181162.13-181162.33" - process $proc$libresoc.v:181162$11001 + attribute \src "libresoc.v:175357.13-175357.33" + process $proc$libresoc.v:175357$10704 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end - attribute \src "libresoc.v:181186.3-181187.25" - process $proc$libresoc.v:181186$10918 + attribute \src "libresoc.v:175381.3-175382.25" + process $proc$libresoc.v:175381$10621 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:181188.3-181189.39" - process $proc$libresoc.v:181188$10919 + attribute \src "libresoc.v:175383.3-175384.39" + process $proc$libresoc.v:175383$10622 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end - attribute \src "libresoc.v:181190.3-181191.37" - process $proc$libresoc.v:181190$10920 + attribute \src "libresoc.v:175385.3-175386.37" + process $proc$libresoc.v:175385$10623 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end - attribute \src "libresoc.v:181192.3-181193.43" - process $proc$libresoc.v:181192$10921 + attribute \src "libresoc.v:175387.3-175388.43" + process $proc$libresoc.v:175387$10624 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end - attribute \src "libresoc.v:181194.3-181195.43" - process $proc$libresoc.v:181194$10922 + attribute \src "libresoc.v:175389.3-175390.43" + process $proc$libresoc.v:175389$10625 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end - attribute \src "libresoc.v:181196.3-181197.43" - process $proc$libresoc.v:181196$10923 + attribute \src "libresoc.v:175391.3-175392.43" + process $proc$libresoc.v:175391$10626 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end - attribute \src "libresoc.v:181198.3-181237.6" - process $proc$libresoc.v:181198$10924 + attribute \src "libresoc.v:175393.3-175432.6" + process $proc$libresoc.v:175393$10627 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[3:0]$10925 $6\src10__data_o$next[3:0]$10931 - attribute \src "libresoc.v:181199.5-181199.29" + assign $0\src10__data_o$next[3:0]$10628 $6\src10__data_o$next[3:0]$10634 + attribute \src "libresoc.v:175394.5-175394.29" switch \initial - attribute \src "libresoc.v:181199.9-181199.17" + attribute \src "libresoc.v:175394.9-175394.17" case 1'1 case end @@ -371004,66 +361549,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[3:0]$10926 $5\src10__data_o$next[3:0]$10930 + assign $1\src10__data_o$next[3:0]$10629 $5\src10__data_o$next[3:0]$10633 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[3:0]$10927 \dest10__data_i + assign $2\src10__data_o$next[3:0]$10630 \dest10__data_i case - assign $2\src10__data_o$next[3:0]$10927 4'0000 + assign $2\src10__data_o$next[3:0]$10630 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[3:0]$10928 \dest20__data_i + assign $3\src10__data_o$next[3:0]$10631 \dest20__data_i case - assign $3\src10__data_o$next[3:0]$10928 $2\src10__data_o$next[3:0]$10927 + assign $3\src10__data_o$next[3:0]$10631 $2\src10__data_o$next[3:0]$10630 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[3:0]$10929 \w0__data_i + assign $4\src10__data_o$next[3:0]$10632 \w0__data_i case - assign $4\src10__data_o$next[3:0]$10929 $3\src10__data_o$next[3:0]$10928 + assign $4\src10__data_o$next[3:0]$10632 $3\src10__data_o$next[3:0]$10631 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[3:0]$10930 \reg + assign $5\src10__data_o$next[3:0]$10633 \reg case - assign $5\src10__data_o$next[3:0]$10930 $4\src10__data_o$next[3:0]$10929 + assign $5\src10__data_o$next[3:0]$10633 $4\src10__data_o$next[3:0]$10632 end case - assign $1\src10__data_o$next[3:0]$10926 4'0000 + assign $1\src10__data_o$next[3:0]$10629 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[3:0]$10931 4'0000 + assign $6\src10__data_o$next[3:0]$10634 4'0000 case - assign $6\src10__data_o$next[3:0]$10931 $1\src10__data_o$next[3:0]$10926 + assign $6\src10__data_o$next[3:0]$10634 $1\src10__data_o$next[3:0]$10629 end sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$10925 + update \src10__data_o$next $0\src10__data_o$next[3:0]$10628 end - attribute \src "libresoc.v:181238.3-181267.6" - process $proc$libresoc.v:181238$10932 + attribute \src "libresoc.v:175433.3-175462.6" + process $proc$libresoc.v:175433$10635 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181239.5-181239.29" + attribute \src "libresoc.v:175434.5-175434.29" switch \initial - attribute \src "libresoc.v:181239.9-181239.17" + attribute \src "libresoc.v:175434.9-175434.17" case 1'1 case end @@ -371109,17 +361654,17 @@ module \reg_0 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181268.3-181294.6" - process $proc$libresoc.v:181268$10933 + attribute \src "libresoc.v:175463.3-175489.6" + process $proc$libresoc.v:175463$10636 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10934 $4\reg$next[3:0]$10938 - attribute \src "libresoc.v:181269.5-181269.29" + assign $0\reg$next[3:0]$10637 $4\reg$next[3:0]$10641 + attribute \src "libresoc.v:175464.5-175464.29" switch \initial - attribute \src "libresoc.v:181269.9-181269.17" + attribute \src "libresoc.v:175464.9-175464.17" case 1'1 case end @@ -371128,49 +361673,49 @@ module \reg_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10935 \dest10__data_i + assign $1\reg$next[3:0]$10638 \dest10__data_i case - assign $1\reg$next[3:0]$10935 \reg + assign $1\reg$next[3:0]$10638 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10936 \dest20__data_i + assign $2\reg$next[3:0]$10639 \dest20__data_i case - assign $2\reg$next[3:0]$10936 $1\reg$next[3:0]$10935 + assign $2\reg$next[3:0]$10639 $1\reg$next[3:0]$10638 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10937 \w0__data_i + assign $3\reg$next[3:0]$10640 \w0__data_i case - assign $3\reg$next[3:0]$10937 $2\reg$next[3:0]$10936 + assign $3\reg$next[3:0]$10640 $2\reg$next[3:0]$10639 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10938 4'0000 + assign $4\reg$next[3:0]$10641 4'0000 case - assign $4\reg$next[3:0]$10938 $3\reg$next[3:0]$10937 + assign $4\reg$next[3:0]$10641 $3\reg$next[3:0]$10640 end sync always - update \reg$next $0\reg$next[3:0]$10934 + update \reg$next $0\reg$next[3:0]$10637 end - attribute \src "libresoc.v:181295.3-181334.6" - process $proc$libresoc.v:181295$10939 + attribute \src "libresoc.v:175490.3-175529.6" + process $proc$libresoc.v:175490$10642 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[3:0]$10940 $6\src20__data_o$next[3:0]$10946 - attribute \src "libresoc.v:181296.5-181296.29" + assign $0\src20__data_o$next[3:0]$10643 $6\src20__data_o$next[3:0]$10649 + attribute \src "libresoc.v:175491.5-175491.29" switch \initial - attribute \src "libresoc.v:181296.9-181296.17" + attribute \src "libresoc.v:175491.9-175491.17" case 1'1 case end @@ -371182,66 +361727,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[3:0]$10941 $5\src20__data_o$next[3:0]$10945 + assign $1\src20__data_o$next[3:0]$10644 $5\src20__data_o$next[3:0]$10648 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[3:0]$10942 \dest10__data_i + assign $2\src20__data_o$next[3:0]$10645 \dest10__data_i case - assign $2\src20__data_o$next[3:0]$10942 4'0000 + assign $2\src20__data_o$next[3:0]$10645 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[3:0]$10943 \dest20__data_i + assign $3\src20__data_o$next[3:0]$10646 \dest20__data_i case - assign $3\src20__data_o$next[3:0]$10943 $2\src20__data_o$next[3:0]$10942 + assign $3\src20__data_o$next[3:0]$10646 $2\src20__data_o$next[3:0]$10645 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[3:0]$10944 \w0__data_i + assign $4\src20__data_o$next[3:0]$10647 \w0__data_i case - assign $4\src20__data_o$next[3:0]$10944 $3\src20__data_o$next[3:0]$10943 + assign $4\src20__data_o$next[3:0]$10647 $3\src20__data_o$next[3:0]$10646 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[3:0]$10945 \reg + assign $5\src20__data_o$next[3:0]$10648 \reg case - assign $5\src20__data_o$next[3:0]$10945 $4\src20__data_o$next[3:0]$10944 + assign $5\src20__data_o$next[3:0]$10648 $4\src20__data_o$next[3:0]$10647 end case - assign $1\src20__data_o$next[3:0]$10941 4'0000 + assign $1\src20__data_o$next[3:0]$10644 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[3:0]$10946 4'0000 + assign $6\src20__data_o$next[3:0]$10649 4'0000 case - assign $6\src20__data_o$next[3:0]$10946 $1\src20__data_o$next[3:0]$10941 + assign $6\src20__data_o$next[3:0]$10649 $1\src20__data_o$next[3:0]$10644 end sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$10940 + update \src20__data_o$next $0\src20__data_o$next[3:0]$10643 end - attribute \src "libresoc.v:181335.3-181364.6" - process $proc$libresoc.v:181335$10947 + attribute \src "libresoc.v:175530.3-175559.6" + process $proc$libresoc.v:175530$10650 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10948 $1\wr_detect$4[0:0]$10949 - attribute \src "libresoc.v:181336.5-181336.29" + assign $0\wr_detect$4[0:0]$10651 $1\wr_detect$4[0:0]$10652 + attribute \src "libresoc.v:175531.5-175531.29" switch \initial - attribute \src "libresoc.v:181336.9-181336.17" + attribute \src "libresoc.v:175531.9-175531.17" case 1'1 case end @@ -371253,49 +361798,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10949 $4\wr_detect$4[0:0]$10952 + assign $1\wr_detect$4[0:0]$10652 $4\wr_detect$4[0:0]$10655 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10950 1'1 + assign $2\wr_detect$4[0:0]$10653 1'1 case - assign $2\wr_detect$4[0:0]$10950 1'0 + assign $2\wr_detect$4[0:0]$10653 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10951 1'1 + assign $3\wr_detect$4[0:0]$10654 1'1 case - assign $3\wr_detect$4[0:0]$10951 $2\wr_detect$4[0:0]$10950 + assign $3\wr_detect$4[0:0]$10654 $2\wr_detect$4[0:0]$10653 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10952 1'1 + assign $4\wr_detect$4[0:0]$10655 1'1 case - assign $4\wr_detect$4[0:0]$10952 $3\wr_detect$4[0:0]$10951 + assign $4\wr_detect$4[0:0]$10655 $3\wr_detect$4[0:0]$10654 end case - assign $1\wr_detect$4[0:0]$10949 1'0 + assign $1\wr_detect$4[0:0]$10652 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10948 + update \wr_detect$4 $0\wr_detect$4[0:0]$10651 end - attribute \src "libresoc.v:181365.3-181404.6" - process $proc$libresoc.v:181365$10953 + attribute \src "libresoc.v:175560.3-175599.6" + process $proc$libresoc.v:175560$10656 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[3:0]$10954 $6\src30__data_o$next[3:0]$10960 - attribute \src "libresoc.v:181366.5-181366.29" + assign $0\src30__data_o$next[3:0]$10657 $6\src30__data_o$next[3:0]$10663 + attribute \src "libresoc.v:175561.5-175561.29" switch \initial - attribute \src "libresoc.v:181366.9-181366.17" + attribute \src "libresoc.v:175561.9-175561.17" case 1'1 case end @@ -371307,66 +361852,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[3:0]$10955 $5\src30__data_o$next[3:0]$10959 + assign $1\src30__data_o$next[3:0]$10658 $5\src30__data_o$next[3:0]$10662 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[3:0]$10956 \dest10__data_i + assign $2\src30__data_o$next[3:0]$10659 \dest10__data_i case - assign $2\src30__data_o$next[3:0]$10956 4'0000 + assign $2\src30__data_o$next[3:0]$10659 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[3:0]$10957 \dest20__data_i + assign $3\src30__data_o$next[3:0]$10660 \dest20__data_i case - assign $3\src30__data_o$next[3:0]$10957 $2\src30__data_o$next[3:0]$10956 + assign $3\src30__data_o$next[3:0]$10660 $2\src30__data_o$next[3:0]$10659 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[3:0]$10958 \w0__data_i + assign $4\src30__data_o$next[3:0]$10661 \w0__data_i case - assign $4\src30__data_o$next[3:0]$10958 $3\src30__data_o$next[3:0]$10957 + assign $4\src30__data_o$next[3:0]$10661 $3\src30__data_o$next[3:0]$10660 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[3:0]$10959 \reg + assign $5\src30__data_o$next[3:0]$10662 \reg case - assign $5\src30__data_o$next[3:0]$10959 $4\src30__data_o$next[3:0]$10958 + assign $5\src30__data_o$next[3:0]$10662 $4\src30__data_o$next[3:0]$10661 end case - assign $1\src30__data_o$next[3:0]$10955 4'0000 + assign $1\src30__data_o$next[3:0]$10658 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[3:0]$10960 4'0000 + assign $6\src30__data_o$next[3:0]$10663 4'0000 case - assign $6\src30__data_o$next[3:0]$10960 $1\src30__data_o$next[3:0]$10955 + assign $6\src30__data_o$next[3:0]$10663 $1\src30__data_o$next[3:0]$10658 end sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$10954 + update \src30__data_o$next $0\src30__data_o$next[3:0]$10657 end - attribute \src "libresoc.v:181405.3-181434.6" - process $proc$libresoc.v:181405$10961 + attribute \src "libresoc.v:175600.3-175629.6" + process $proc$libresoc.v:175600$10664 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10962 $1\wr_detect$7[0:0]$10963 - attribute \src "libresoc.v:181406.5-181406.29" + assign $0\wr_detect$7[0:0]$10665 $1\wr_detect$7[0:0]$10666 + attribute \src "libresoc.v:175601.5-175601.29" switch \initial - attribute \src "libresoc.v:181406.9-181406.17" + attribute \src "libresoc.v:175601.9-175601.17" case 1'1 case end @@ -371378,49 +361923,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10963 $4\wr_detect$7[0:0]$10966 + assign $1\wr_detect$7[0:0]$10666 $4\wr_detect$7[0:0]$10669 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10964 1'1 + assign $2\wr_detect$7[0:0]$10667 1'1 case - assign $2\wr_detect$7[0:0]$10964 1'0 + assign $2\wr_detect$7[0:0]$10667 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10965 1'1 + assign $3\wr_detect$7[0:0]$10668 1'1 case - assign $3\wr_detect$7[0:0]$10965 $2\wr_detect$7[0:0]$10964 + assign $3\wr_detect$7[0:0]$10668 $2\wr_detect$7[0:0]$10667 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10966 1'1 + assign $4\wr_detect$7[0:0]$10669 1'1 case - assign $4\wr_detect$7[0:0]$10966 $3\wr_detect$7[0:0]$10965 + assign $4\wr_detect$7[0:0]$10669 $3\wr_detect$7[0:0]$10668 end case - assign $1\wr_detect$7[0:0]$10963 1'0 + assign $1\wr_detect$7[0:0]$10666 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10962 + update \wr_detect$7 $0\wr_detect$7[0:0]$10665 end - attribute \src "libresoc.v:181435.3-181474.6" - process $proc$libresoc.v:181435$10967 + attribute \src "libresoc.v:175630.3-175669.6" + process $proc$libresoc.v:175630$10670 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[3:0]$10968 $6\r0__data_o$next[3:0]$10974 - attribute \src "libresoc.v:181436.5-181436.29" + assign $0\r0__data_o$next[3:0]$10671 $6\r0__data_o$next[3:0]$10677 + attribute \src "libresoc.v:175631.5-175631.29" switch \initial - attribute \src "libresoc.v:181436.9-181436.17" + attribute \src "libresoc.v:175631.9-175631.17" case 1'1 case end @@ -371432,66 +361977,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[3:0]$10969 $5\r0__data_o$next[3:0]$10973 + assign $1\r0__data_o$next[3:0]$10672 $5\r0__data_o$next[3:0]$10676 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[3:0]$10970 \dest10__data_i + assign $2\r0__data_o$next[3:0]$10673 \dest10__data_i case - assign $2\r0__data_o$next[3:0]$10970 4'0000 + assign $2\r0__data_o$next[3:0]$10673 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[3:0]$10971 \dest20__data_i + assign $3\r0__data_o$next[3:0]$10674 \dest20__data_i case - assign $3\r0__data_o$next[3:0]$10971 $2\r0__data_o$next[3:0]$10970 + assign $3\r0__data_o$next[3:0]$10674 $2\r0__data_o$next[3:0]$10673 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[3:0]$10972 \w0__data_i + assign $4\r0__data_o$next[3:0]$10675 \w0__data_i case - assign $4\r0__data_o$next[3:0]$10972 $3\r0__data_o$next[3:0]$10971 + assign $4\r0__data_o$next[3:0]$10675 $3\r0__data_o$next[3:0]$10674 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[3:0]$10973 \reg + assign $5\r0__data_o$next[3:0]$10676 \reg case - assign $5\r0__data_o$next[3:0]$10973 $4\r0__data_o$next[3:0]$10972 + assign $5\r0__data_o$next[3:0]$10676 $4\r0__data_o$next[3:0]$10675 end case - assign $1\r0__data_o$next[3:0]$10969 4'0000 + assign $1\r0__data_o$next[3:0]$10672 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[3:0]$10974 4'0000 + assign $6\r0__data_o$next[3:0]$10677 4'0000 case - assign $6\r0__data_o$next[3:0]$10974 $1\r0__data_o$next[3:0]$10969 + assign $6\r0__data_o$next[3:0]$10677 $1\r0__data_o$next[3:0]$10672 end sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$10968 + update \r0__data_o$next $0\r0__data_o$next[3:0]$10671 end - attribute \src "libresoc.v:181475.3-181504.6" - process $proc$libresoc.v:181475$10975 + attribute \src "libresoc.v:175670.3-175699.6" + process $proc$libresoc.v:175670$10678 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10976 $1\wr_detect$10[0:0]$10977 - attribute \src "libresoc.v:181476.5-181476.29" + assign $0\wr_detect$10[0:0]$10679 $1\wr_detect$10[0:0]$10680 + attribute \src "libresoc.v:175671.5-175671.29" switch \initial - attribute \src "libresoc.v:181476.9-181476.17" + attribute \src "libresoc.v:175671.9-175671.17" case 1'1 case end @@ -371503,49 +362048,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10977 $4\wr_detect$10[0:0]$10980 + assign $1\wr_detect$10[0:0]$10680 $4\wr_detect$10[0:0]$10683 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10978 1'1 + assign $2\wr_detect$10[0:0]$10681 1'1 case - assign $2\wr_detect$10[0:0]$10978 1'0 + assign $2\wr_detect$10[0:0]$10681 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10979 1'1 + assign $3\wr_detect$10[0:0]$10682 1'1 case - assign $3\wr_detect$10[0:0]$10979 $2\wr_detect$10[0:0]$10978 + assign $3\wr_detect$10[0:0]$10682 $2\wr_detect$10[0:0]$10681 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10980 1'1 + assign $4\wr_detect$10[0:0]$10683 1'1 case - assign $4\wr_detect$10[0:0]$10980 $3\wr_detect$10[0:0]$10979 + assign $4\wr_detect$10[0:0]$10683 $3\wr_detect$10[0:0]$10682 end case - assign $1\wr_detect$10[0:0]$10977 1'0 + assign $1\wr_detect$10[0:0]$10680 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10976 + update \wr_detect$10 $0\wr_detect$10[0:0]$10679 end - attribute \src "libresoc.v:181505.3-181544.6" - process $proc$libresoc.v:181505$10981 + attribute \src "libresoc.v:175700.3-175739.6" + process $proc$libresoc.v:175700$10684 assign { } { } assign { } { } assign { } { } - assign $0\r20__data_o$next[3:0]$10982 $6\r20__data_o$next[3:0]$10988 - attribute \src "libresoc.v:181506.5-181506.29" + assign $0\r20__data_o$next[3:0]$10685 $6\r20__data_o$next[3:0]$10691 + attribute \src "libresoc.v:175701.5-175701.29" switch \initial - attribute \src "libresoc.v:181506.9-181506.17" + attribute \src "libresoc.v:175701.9-175701.17" case 1'1 case end @@ -371557,66 +362102,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r20__data_o$next[3:0]$10983 $5\r20__data_o$next[3:0]$10987 + assign $1\r20__data_o$next[3:0]$10686 $5\r20__data_o$next[3:0]$10690 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r20__data_o$next[3:0]$10984 \dest10__data_i + assign $2\r20__data_o$next[3:0]$10687 \dest10__data_i case - assign $2\r20__data_o$next[3:0]$10984 4'0000 + assign $2\r20__data_o$next[3:0]$10687 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r20__data_o$next[3:0]$10985 \dest20__data_i + assign $3\r20__data_o$next[3:0]$10688 \dest20__data_i case - assign $3\r20__data_o$next[3:0]$10985 $2\r20__data_o$next[3:0]$10984 + assign $3\r20__data_o$next[3:0]$10688 $2\r20__data_o$next[3:0]$10687 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r20__data_o$next[3:0]$10986 \w0__data_i + assign $4\r20__data_o$next[3:0]$10689 \w0__data_i case - assign $4\r20__data_o$next[3:0]$10986 $3\r20__data_o$next[3:0]$10985 + assign $4\r20__data_o$next[3:0]$10689 $3\r20__data_o$next[3:0]$10688 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r20__data_o$next[3:0]$10987 \reg + assign $5\r20__data_o$next[3:0]$10690 \reg case - assign $5\r20__data_o$next[3:0]$10987 $4\r20__data_o$next[3:0]$10986 + assign $5\r20__data_o$next[3:0]$10690 $4\r20__data_o$next[3:0]$10689 end case - assign $1\r20__data_o$next[3:0]$10983 4'0000 + assign $1\r20__data_o$next[3:0]$10686 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r20__data_o$next[3:0]$10988 4'0000 + assign $6\r20__data_o$next[3:0]$10691 4'0000 case - assign $6\r20__data_o$next[3:0]$10988 $1\r20__data_o$next[3:0]$10983 + assign $6\r20__data_o$next[3:0]$10691 $1\r20__data_o$next[3:0]$10686 end sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$10982 + update \r20__data_o$next $0\r20__data_o$next[3:0]$10685 end - attribute \src "libresoc.v:181545.3-181574.6" - process $proc$libresoc.v:181545$10989 + attribute \src "libresoc.v:175740.3-175769.6" + process $proc$libresoc.v:175740$10692 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10990 $1\wr_detect$13[0:0]$10991 - attribute \src "libresoc.v:181546.5-181546.29" + assign $0\wr_detect$13[0:0]$10693 $1\wr_detect$13[0:0]$10694 + attribute \src "libresoc.v:175741.5-175741.29" switch \initial - attribute \src "libresoc.v:181546.9-181546.17" + attribute \src "libresoc.v:175741.9-175741.17" case 1'1 case end @@ -371628,205 +362173,205 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10991 $4\wr_detect$13[0:0]$10994 + assign $1\wr_detect$13[0:0]$10694 $4\wr_detect$13[0:0]$10697 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10992 1'1 + assign $2\wr_detect$13[0:0]$10695 1'1 case - assign $2\wr_detect$13[0:0]$10992 1'0 + assign $2\wr_detect$13[0:0]$10695 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10993 1'1 + assign $3\wr_detect$13[0:0]$10696 1'1 case - assign $3\wr_detect$13[0:0]$10993 $2\wr_detect$13[0:0]$10992 + assign $3\wr_detect$13[0:0]$10696 $2\wr_detect$13[0:0]$10695 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10994 1'1 + assign $4\wr_detect$13[0:0]$10697 1'1 case - assign $4\wr_detect$13[0:0]$10994 $3\wr_detect$13[0:0]$10993 + assign $4\wr_detect$13[0:0]$10697 $3\wr_detect$13[0:0]$10696 end case - assign $1\wr_detect$13[0:0]$10991 1'0 + assign $1\wr_detect$13[0:0]$10694 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10990 + update \wr_detect$13 $0\wr_detect$13[0:0]$10693 end - connect \$9 $not$libresoc.v:181181$10913_Y - connect \$12 $not$libresoc.v:181182$10914_Y - connect \$1 $not$libresoc.v:181183$10915_Y - connect \$3 $not$libresoc.v:181184$10916_Y - connect \$6 $not$libresoc.v:181185$10917_Y + connect \$9 $not$libresoc.v:175376$10616_Y + connect \$12 $not$libresoc.v:175377$10617_Y + connect \$1 $not$libresoc.v:175378$10618_Y + connect \$3 $not$libresoc.v:175379$10619_Y + connect \$6 $not$libresoc.v:175380$10620_Y end -attribute \src "libresoc.v:181579.1-182024.10" +attribute \src "libresoc.v:175774.1-176219.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" module \reg_0$132 - attribute \src "libresoc.v:181580.7-181580.20" + attribute \src "libresoc.v:175775.7-175775.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181909.3-181954.6" - wire width 2 $0\r0__data_o$next[1:0]$11054 - attribute \src "libresoc.v:181655.3-181656.37" + attribute \src "libresoc.v:176104.3-176149.6" + wire width 2 $0\r0__data_o$next[1:0]$10757 + attribute \src "libresoc.v:175850.3-175851.37" wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:181991.3-182023.6" - wire width 2 $0\reg$next[1:0]$11070 - attribute \src "libresoc.v:181653.3-181654.25" + attribute \src "libresoc.v:176186.3-176218.6" + wire width 2 $0\reg$next[1:0]$10773 + attribute \src "libresoc.v:175848.3-175849.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:181663.3-181708.6" - wire width 2 $0\src10__data_o$next[1:0]$11012 - attribute \src "libresoc.v:181661.3-181662.43" + attribute \src "libresoc.v:175858.3-175903.6" + wire width 2 $0\src10__data_o$next[1:0]$10715 + attribute \src "libresoc.v:175856.3-175857.43" wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:181745.3-181790.6" - wire width 2 $0\src20__data_o$next[1:0]$11022 - attribute \src "libresoc.v:181659.3-181660.43" + attribute \src "libresoc.v:175940.3-175985.6" + wire width 2 $0\src20__data_o$next[1:0]$10725 + attribute \src "libresoc.v:175854.3-175855.43" wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:181827.3-181872.6" - wire width 2 $0\src30__data_o$next[1:0]$11038 - attribute \src "libresoc.v:181657.3-181658.43" + attribute \src "libresoc.v:176022.3-176067.6" + wire width 2 $0\src30__data_o$next[1:0]$10741 + attribute \src "libresoc.v:175852.3-175853.43" wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:181955.3-181990.6" - wire $0\wr_detect$10[0:0]$11063 - attribute \src "libresoc.v:181791.3-181826.6" - wire $0\wr_detect$4[0:0]$11031 - attribute \src "libresoc.v:181873.3-181908.6" - wire $0\wr_detect$7[0:0]$11047 - attribute \src "libresoc.v:181709.3-181744.6" + attribute \src "libresoc.v:176150.3-176185.6" + wire $0\wr_detect$10[0:0]$10766 + attribute \src "libresoc.v:175986.3-176021.6" + wire $0\wr_detect$4[0:0]$10734 + attribute \src "libresoc.v:176068.3-176103.6" + wire $0\wr_detect$7[0:0]$10750 + attribute \src "libresoc.v:175904.3-175939.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:181909.3-181954.6" - wire width 2 $1\r0__data_o$next[1:0]$11055 - attribute \src "libresoc.v:181607.13-181607.30" + attribute \src "libresoc.v:176104.3-176149.6" + wire width 2 $1\r0__data_o$next[1:0]$10758 + attribute \src "libresoc.v:175802.13-175802.30" wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:181991.3-182023.6" - wire width 2 $1\reg$next[1:0]$11071 - attribute \src "libresoc.v:181613.13-181613.25" + attribute \src "libresoc.v:176186.3-176218.6" + wire width 2 $1\reg$next[1:0]$10774 + attribute \src "libresoc.v:175808.13-175808.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:181663.3-181708.6" - wire width 2 $1\src10__data_o$next[1:0]$11013 - attribute \src "libresoc.v:181618.13-181618.33" + attribute \src "libresoc.v:175858.3-175903.6" + wire width 2 $1\src10__data_o$next[1:0]$10716 + attribute \src "libresoc.v:175813.13-175813.33" wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:181745.3-181790.6" - wire width 2 $1\src20__data_o$next[1:0]$11023 - attribute \src "libresoc.v:181625.13-181625.33" + attribute \src "libresoc.v:175940.3-175985.6" + wire width 2 $1\src20__data_o$next[1:0]$10726 + attribute \src "libresoc.v:175820.13-175820.33" wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:181827.3-181872.6" - wire width 2 $1\src30__data_o$next[1:0]$11039 - attribute \src "libresoc.v:181632.13-181632.33" + attribute \src "libresoc.v:176022.3-176067.6" + wire width 2 $1\src30__data_o$next[1:0]$10742 + attribute \src "libresoc.v:175827.13-175827.33" wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:181955.3-181990.6" - wire $1\wr_detect$10[0:0]$11064 - attribute \src "libresoc.v:181791.3-181826.6" - wire $1\wr_detect$4[0:0]$11032 - attribute \src "libresoc.v:181873.3-181908.6" - wire $1\wr_detect$7[0:0]$11048 - attribute \src "libresoc.v:181709.3-181744.6" + attribute \src "libresoc.v:176150.3-176185.6" + wire $1\wr_detect$10[0:0]$10767 + attribute \src "libresoc.v:175986.3-176021.6" + wire $1\wr_detect$4[0:0]$10735 + attribute \src "libresoc.v:176068.3-176103.6" + wire $1\wr_detect$7[0:0]$10751 + attribute \src "libresoc.v:175904.3-175939.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:181909.3-181954.6" - wire width 2 $2\r0__data_o$next[1:0]$11056 - attribute \src "libresoc.v:181991.3-182023.6" - wire width 2 $2\reg$next[1:0]$11072 - attribute \src "libresoc.v:181663.3-181708.6" - wire width 2 $2\src10__data_o$next[1:0]$11014 - attribute \src "libresoc.v:181745.3-181790.6" - wire width 2 $2\src20__data_o$next[1:0]$11024 - attribute \src "libresoc.v:181827.3-181872.6" - wire width 2 $2\src30__data_o$next[1:0]$11040 - attribute \src "libresoc.v:181955.3-181990.6" - wire $2\wr_detect$10[0:0]$11065 - attribute \src "libresoc.v:181791.3-181826.6" - wire $2\wr_detect$4[0:0]$11033 - attribute \src "libresoc.v:181873.3-181908.6" - wire $2\wr_detect$7[0:0]$11049 - attribute \src "libresoc.v:181709.3-181744.6" + attribute \src "libresoc.v:176104.3-176149.6" + wire width 2 $2\r0__data_o$next[1:0]$10759 + attribute \src "libresoc.v:176186.3-176218.6" + wire width 2 $2\reg$next[1:0]$10775 + attribute \src "libresoc.v:175858.3-175903.6" + wire width 2 $2\src10__data_o$next[1:0]$10717 + attribute \src "libresoc.v:175940.3-175985.6" + wire width 2 $2\src20__data_o$next[1:0]$10727 + attribute \src "libresoc.v:176022.3-176067.6" + wire width 2 $2\src30__data_o$next[1:0]$10743 + attribute \src "libresoc.v:176150.3-176185.6" + wire $2\wr_detect$10[0:0]$10768 + attribute \src "libresoc.v:175986.3-176021.6" + wire $2\wr_detect$4[0:0]$10736 + attribute \src "libresoc.v:176068.3-176103.6" + wire $2\wr_detect$7[0:0]$10752 + attribute \src "libresoc.v:175904.3-175939.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:181909.3-181954.6" - wire width 2 $3\r0__data_o$next[1:0]$11057 - attribute \src "libresoc.v:181991.3-182023.6" - wire width 2 $3\reg$next[1:0]$11073 - attribute \src "libresoc.v:181663.3-181708.6" - wire width 2 $3\src10__data_o$next[1:0]$11015 - attribute \src "libresoc.v:181745.3-181790.6" - wire width 2 $3\src20__data_o$next[1:0]$11025 - attribute \src "libresoc.v:181827.3-181872.6" - wire width 2 $3\src30__data_o$next[1:0]$11041 - attribute \src "libresoc.v:181955.3-181990.6" - wire $3\wr_detect$10[0:0]$11066 - attribute \src "libresoc.v:181791.3-181826.6" - wire $3\wr_detect$4[0:0]$11034 - attribute \src "libresoc.v:181873.3-181908.6" - wire $3\wr_detect$7[0:0]$11050 - attribute \src "libresoc.v:181709.3-181744.6" + attribute \src "libresoc.v:176104.3-176149.6" + wire width 2 $3\r0__data_o$next[1:0]$10760 + attribute \src "libresoc.v:176186.3-176218.6" + wire width 2 $3\reg$next[1:0]$10776 + attribute \src "libresoc.v:175858.3-175903.6" + wire width 2 $3\src10__data_o$next[1:0]$10718 + attribute \src "libresoc.v:175940.3-175985.6" + wire width 2 $3\src20__data_o$next[1:0]$10728 + attribute \src "libresoc.v:176022.3-176067.6" + wire width 2 $3\src30__data_o$next[1:0]$10744 + attribute \src "libresoc.v:176150.3-176185.6" + wire $3\wr_detect$10[0:0]$10769 + attribute \src "libresoc.v:175986.3-176021.6" + wire $3\wr_detect$4[0:0]$10737 + attribute \src "libresoc.v:176068.3-176103.6" + wire $3\wr_detect$7[0:0]$10753 + attribute \src "libresoc.v:175904.3-175939.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:181909.3-181954.6" - wire width 2 $4\r0__data_o$next[1:0]$11058 - attribute \src "libresoc.v:181991.3-182023.6" - wire width 2 $4\reg$next[1:0]$11074 - attribute \src "libresoc.v:181663.3-181708.6" - wire width 2 $4\src10__data_o$next[1:0]$11016 - attribute \src "libresoc.v:181745.3-181790.6" - wire width 2 $4\src20__data_o$next[1:0]$11026 - attribute \src "libresoc.v:181827.3-181872.6" - wire width 2 $4\src30__data_o$next[1:0]$11042 - attribute \src "libresoc.v:181955.3-181990.6" - wire $4\wr_detect$10[0:0]$11067 - attribute \src "libresoc.v:181791.3-181826.6" - wire $4\wr_detect$4[0:0]$11035 - attribute \src "libresoc.v:181873.3-181908.6" - wire $4\wr_detect$7[0:0]$11051 - attribute \src "libresoc.v:181709.3-181744.6" + attribute \src "libresoc.v:176104.3-176149.6" + wire width 2 $4\r0__data_o$next[1:0]$10761 + attribute \src "libresoc.v:176186.3-176218.6" + wire width 2 $4\reg$next[1:0]$10777 + attribute \src "libresoc.v:175858.3-175903.6" + wire width 2 $4\src10__data_o$next[1:0]$10719 + attribute \src "libresoc.v:175940.3-175985.6" + wire width 2 $4\src20__data_o$next[1:0]$10729 + attribute \src "libresoc.v:176022.3-176067.6" + wire width 2 $4\src30__data_o$next[1:0]$10745 + attribute \src "libresoc.v:176150.3-176185.6" + wire $4\wr_detect$10[0:0]$10770 + attribute \src "libresoc.v:175986.3-176021.6" + wire $4\wr_detect$4[0:0]$10738 + attribute \src "libresoc.v:176068.3-176103.6" + wire $4\wr_detect$7[0:0]$10754 + attribute \src "libresoc.v:175904.3-175939.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:181909.3-181954.6" - wire width 2 $5\r0__data_o$next[1:0]$11059 - attribute \src "libresoc.v:181991.3-182023.6" - wire width 2 $5\reg$next[1:0]$11075 - attribute \src "libresoc.v:181663.3-181708.6" - wire width 2 $5\src10__data_o$next[1:0]$11017 - attribute \src "libresoc.v:181745.3-181790.6" - wire width 2 $5\src20__data_o$next[1:0]$11027 - attribute \src "libresoc.v:181827.3-181872.6" - wire width 2 $5\src30__data_o$next[1:0]$11043 - attribute \src "libresoc.v:181955.3-181990.6" - wire $5\wr_detect$10[0:0]$11068 - attribute \src "libresoc.v:181791.3-181826.6" - wire $5\wr_detect$4[0:0]$11036 - attribute \src "libresoc.v:181873.3-181908.6" - wire $5\wr_detect$7[0:0]$11052 - attribute \src "libresoc.v:181709.3-181744.6" + attribute \src "libresoc.v:176104.3-176149.6" + wire width 2 $5\r0__data_o$next[1:0]$10762 + attribute \src "libresoc.v:176186.3-176218.6" + wire width 2 $5\reg$next[1:0]$10778 + attribute \src "libresoc.v:175858.3-175903.6" + wire width 2 $5\src10__data_o$next[1:0]$10720 + attribute \src "libresoc.v:175940.3-175985.6" + wire width 2 $5\src20__data_o$next[1:0]$10730 + attribute \src "libresoc.v:176022.3-176067.6" + wire width 2 $5\src30__data_o$next[1:0]$10746 + attribute \src "libresoc.v:176150.3-176185.6" + wire $5\wr_detect$10[0:0]$10771 + attribute \src "libresoc.v:175986.3-176021.6" + wire $5\wr_detect$4[0:0]$10739 + attribute \src "libresoc.v:176068.3-176103.6" + wire $5\wr_detect$7[0:0]$10755 + attribute \src "libresoc.v:175904.3-175939.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:181909.3-181954.6" - wire width 2 $6\r0__data_o$next[1:0]$11060 - attribute \src "libresoc.v:181663.3-181708.6" - wire width 2 $6\src10__data_o$next[1:0]$11018 - attribute \src "libresoc.v:181745.3-181790.6" - wire width 2 $6\src20__data_o$next[1:0]$11028 - attribute \src "libresoc.v:181827.3-181872.6" - wire width 2 $6\src30__data_o$next[1:0]$11044 - attribute \src "libresoc.v:181909.3-181954.6" - wire width 2 $7\r0__data_o$next[1:0]$11061 - attribute \src "libresoc.v:181663.3-181708.6" - wire width 2 $7\src10__data_o$next[1:0]$11019 - attribute \src "libresoc.v:181745.3-181790.6" - wire width 2 $7\src20__data_o$next[1:0]$11029 - attribute \src "libresoc.v:181827.3-181872.6" - wire width 2 $7\src30__data_o$next[1:0]$11045 - attribute \src "libresoc.v:181649.17-181649.104" - wire $not$libresoc.v:181649$11002_Y - attribute \src "libresoc.v:181650.17-181650.100" - wire $not$libresoc.v:181650$11003_Y - attribute \src "libresoc.v:181651.17-181651.103" - wire $not$libresoc.v:181651$11004_Y - attribute \src "libresoc.v:181652.17-181652.103" - wire $not$libresoc.v:181652$11005_Y + attribute \src "libresoc.v:176104.3-176149.6" + wire width 2 $6\r0__data_o$next[1:0]$10763 + attribute \src "libresoc.v:175858.3-175903.6" + wire width 2 $6\src10__data_o$next[1:0]$10721 + attribute \src "libresoc.v:175940.3-175985.6" + wire width 2 $6\src20__data_o$next[1:0]$10731 + attribute \src "libresoc.v:176022.3-176067.6" + wire width 2 $6\src30__data_o$next[1:0]$10747 + attribute \src "libresoc.v:176104.3-176149.6" + wire width 2 $7\r0__data_o$next[1:0]$10764 + attribute \src "libresoc.v:175858.3-175903.6" + wire width 2 $7\src10__data_o$next[1:0]$10722 + attribute \src "libresoc.v:175940.3-175985.6" + wire width 2 $7\src20__data_o$next[1:0]$10732 + attribute \src "libresoc.v:176022.3-176067.6" + wire width 2 $7\src30__data_o$next[1:0]$10748 + attribute \src "libresoc.v:175844.17-175844.104" + wire $not$libresoc.v:175844$10705_Y + attribute \src "libresoc.v:175845.17-175845.100" + wire $not$libresoc.v:175845$10706_Y + attribute \src "libresoc.v:175846.17-175846.103" + wire $not$libresoc.v:175846$10707_Y + attribute \src "libresoc.v:175847.17-175847.103" + wire $not$libresoc.v:175847$10708_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -371835,9 +362380,9 @@ module \reg_0$132 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest10__data_i @@ -371851,7 +362396,7 @@ module \reg_0$132 wire width 2 input 13 \dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest30__wen - attribute \src "libresoc.v:181580.7-181580.15" + attribute \src "libresoc.v:175775.7-175775.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r0__data_o @@ -371894,129 +362439,129 @@ module \reg_0$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181649$11002 + cell $not $not$libresoc.v:175844$10705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:181649$11002_Y + connect \Y $not$libresoc.v:175844$10705_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181650$11003 + cell $not $not$libresoc.v:175845$10706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:181650$11003_Y + connect \Y $not$libresoc.v:175845$10706_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181651$11004 + cell $not $not$libresoc.v:175846$10707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:181651$11004_Y + connect \Y $not$libresoc.v:175846$10707_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181652$11005 + cell $not $not$libresoc.v:175847$10708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:181652$11005_Y + connect \Y $not$libresoc.v:175847$10708_Y end - attribute \src "libresoc.v:181580.7-181580.20" - process $proc$libresoc.v:181580$11076 + attribute \src "libresoc.v:175775.7-175775.20" + process $proc$libresoc.v:175775$10779 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181607.13-181607.30" - process $proc$libresoc.v:181607$11077 + attribute \src "libresoc.v:175802.13-175802.30" + process $proc$libresoc.v:175802$10780 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end - attribute \src "libresoc.v:181613.13-181613.25" - process $proc$libresoc.v:181613$11078 + attribute \src "libresoc.v:175808.13-175808.25" + process $proc$libresoc.v:175808$10781 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:181618.13-181618.33" - process $proc$libresoc.v:181618$11079 + attribute \src "libresoc.v:175813.13-175813.33" + process $proc$libresoc.v:175813$10782 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end - attribute \src "libresoc.v:181625.13-181625.33" - process $proc$libresoc.v:181625$11080 + attribute \src "libresoc.v:175820.13-175820.33" + process $proc$libresoc.v:175820$10783 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end - attribute \src "libresoc.v:181632.13-181632.33" - process $proc$libresoc.v:181632$11081 + attribute \src "libresoc.v:175827.13-175827.33" + process $proc$libresoc.v:175827$10784 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end - attribute \src "libresoc.v:181653.3-181654.25" - process $proc$libresoc.v:181653$11006 + attribute \src "libresoc.v:175848.3-175849.25" + process $proc$libresoc.v:175848$10709 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:181655.3-181656.37" - process $proc$libresoc.v:181655$11007 + attribute \src "libresoc.v:175850.3-175851.37" + process $proc$libresoc.v:175850$10710 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end - attribute \src "libresoc.v:181657.3-181658.43" - process $proc$libresoc.v:181657$11008 + attribute \src "libresoc.v:175852.3-175853.43" + process $proc$libresoc.v:175852$10711 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end - attribute \src "libresoc.v:181659.3-181660.43" - process $proc$libresoc.v:181659$11009 + attribute \src "libresoc.v:175854.3-175855.43" + process $proc$libresoc.v:175854$10712 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end - attribute \src "libresoc.v:181661.3-181662.43" - process $proc$libresoc.v:181661$11010 + attribute \src "libresoc.v:175856.3-175857.43" + process $proc$libresoc.v:175856$10713 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end - attribute \src "libresoc.v:181663.3-181708.6" - process $proc$libresoc.v:181663$11011 + attribute \src "libresoc.v:175858.3-175903.6" + process $proc$libresoc.v:175858$10714 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[1:0]$11012 $7\src10__data_o$next[1:0]$11019 - attribute \src "libresoc.v:181664.5-181664.29" + assign $0\src10__data_o$next[1:0]$10715 $7\src10__data_o$next[1:0]$10722 + attribute \src "libresoc.v:175859.5-175859.29" switch \initial - attribute \src "libresoc.v:181664.9-181664.17" + attribute \src "libresoc.v:175859.9-175859.17" case 1'1 case end @@ -372029,75 +362574,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[1:0]$11013 $6\src10__data_o$next[1:0]$11018 + assign $1\src10__data_o$next[1:0]$10716 $6\src10__data_o$next[1:0]$10721 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[1:0]$11014 \dest10__data_i + assign $2\src10__data_o$next[1:0]$10717 \dest10__data_i case - assign $2\src10__data_o$next[1:0]$11014 2'00 + assign $2\src10__data_o$next[1:0]$10717 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[1:0]$11015 \dest20__data_i + assign $3\src10__data_o$next[1:0]$10718 \dest20__data_i case - assign $3\src10__data_o$next[1:0]$11015 $2\src10__data_o$next[1:0]$11014 + assign $3\src10__data_o$next[1:0]$10718 $2\src10__data_o$next[1:0]$10717 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[1:0]$11016 \dest30__data_i + assign $4\src10__data_o$next[1:0]$10719 \dest30__data_i case - assign $4\src10__data_o$next[1:0]$11016 $3\src10__data_o$next[1:0]$11015 + assign $4\src10__data_o$next[1:0]$10719 $3\src10__data_o$next[1:0]$10718 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[1:0]$11017 \w0__data_i + assign $5\src10__data_o$next[1:0]$10720 \w0__data_i case - assign $5\src10__data_o$next[1:0]$11017 $4\src10__data_o$next[1:0]$11016 + assign $5\src10__data_o$next[1:0]$10720 $4\src10__data_o$next[1:0]$10719 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[1:0]$11018 \reg + assign $6\src10__data_o$next[1:0]$10721 \reg case - assign $6\src10__data_o$next[1:0]$11018 $5\src10__data_o$next[1:0]$11017 + assign $6\src10__data_o$next[1:0]$10721 $5\src10__data_o$next[1:0]$10720 end case - assign $1\src10__data_o$next[1:0]$11013 2'00 + assign $1\src10__data_o$next[1:0]$10716 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src10__data_o$next[1:0]$11019 2'00 + assign $7\src10__data_o$next[1:0]$10722 2'00 case - assign $7\src10__data_o$next[1:0]$11019 $1\src10__data_o$next[1:0]$11013 + assign $7\src10__data_o$next[1:0]$10722 $1\src10__data_o$next[1:0]$10716 end sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$11012 + update \src10__data_o$next $0\src10__data_o$next[1:0]$10715 end - attribute \src "libresoc.v:181709.3-181744.6" - process $proc$libresoc.v:181709$11020 + attribute \src "libresoc.v:175904.3-175939.6" + process $proc$libresoc.v:175904$10723 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181710.5-181710.29" + attribute \src "libresoc.v:175905.5-175905.29" switch \initial - attribute \src "libresoc.v:181710.9-181710.17" + attribute \src "libresoc.v:175905.9-175905.17" case 1'1 case end @@ -372153,15 +362698,15 @@ module \reg_0$132 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181745.3-181790.6" - process $proc$libresoc.v:181745$11021 + attribute \src "libresoc.v:175940.3-175985.6" + process $proc$libresoc.v:175940$10724 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[1:0]$11022 $7\src20__data_o$next[1:0]$11029 - attribute \src "libresoc.v:181746.5-181746.29" + assign $0\src20__data_o$next[1:0]$10725 $7\src20__data_o$next[1:0]$10732 + attribute \src "libresoc.v:175941.5-175941.29" switch \initial - attribute \src "libresoc.v:181746.9-181746.17" + attribute \src "libresoc.v:175941.9-175941.17" case 1'1 case end @@ -372174,75 +362719,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[1:0]$11023 $6\src20__data_o$next[1:0]$11028 + assign $1\src20__data_o$next[1:0]$10726 $6\src20__data_o$next[1:0]$10731 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[1:0]$11024 \dest10__data_i + assign $2\src20__data_o$next[1:0]$10727 \dest10__data_i case - assign $2\src20__data_o$next[1:0]$11024 2'00 + assign $2\src20__data_o$next[1:0]$10727 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[1:0]$11025 \dest20__data_i + assign $3\src20__data_o$next[1:0]$10728 \dest20__data_i case - assign $3\src20__data_o$next[1:0]$11025 $2\src20__data_o$next[1:0]$11024 + assign $3\src20__data_o$next[1:0]$10728 $2\src20__data_o$next[1:0]$10727 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[1:0]$11026 \dest30__data_i + assign $4\src20__data_o$next[1:0]$10729 \dest30__data_i case - assign $4\src20__data_o$next[1:0]$11026 $3\src20__data_o$next[1:0]$11025 + assign $4\src20__data_o$next[1:0]$10729 $3\src20__data_o$next[1:0]$10728 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[1:0]$11027 \w0__data_i + assign $5\src20__data_o$next[1:0]$10730 \w0__data_i case - assign $5\src20__data_o$next[1:0]$11027 $4\src20__data_o$next[1:0]$11026 + assign $5\src20__data_o$next[1:0]$10730 $4\src20__data_o$next[1:0]$10729 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[1:0]$11028 \reg + assign $6\src20__data_o$next[1:0]$10731 \reg case - assign $6\src20__data_o$next[1:0]$11028 $5\src20__data_o$next[1:0]$11027 + assign $6\src20__data_o$next[1:0]$10731 $5\src20__data_o$next[1:0]$10730 end case - assign $1\src20__data_o$next[1:0]$11023 2'00 + assign $1\src20__data_o$next[1:0]$10726 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src20__data_o$next[1:0]$11029 2'00 + assign $7\src20__data_o$next[1:0]$10732 2'00 case - assign $7\src20__data_o$next[1:0]$11029 $1\src20__data_o$next[1:0]$11023 + assign $7\src20__data_o$next[1:0]$10732 $1\src20__data_o$next[1:0]$10726 end sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$11022 + update \src20__data_o$next $0\src20__data_o$next[1:0]$10725 end - attribute \src "libresoc.v:181791.3-181826.6" - process $proc$libresoc.v:181791$11030 + attribute \src "libresoc.v:175986.3-176021.6" + process $proc$libresoc.v:175986$10733 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11031 $1\wr_detect$4[0:0]$11032 - attribute \src "libresoc.v:181792.5-181792.29" + assign $0\wr_detect$4[0:0]$10734 $1\wr_detect$4[0:0]$10735 + attribute \src "libresoc.v:175987.5-175987.29" switch \initial - attribute \src "libresoc.v:181792.9-181792.17" + attribute \src "libresoc.v:175987.9-175987.17" case 1'1 case end @@ -372255,58 +362800,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11032 $5\wr_detect$4[0:0]$11036 + assign $1\wr_detect$4[0:0]$10735 $5\wr_detect$4[0:0]$10739 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11033 1'1 + assign $2\wr_detect$4[0:0]$10736 1'1 case - assign $2\wr_detect$4[0:0]$11033 1'0 + assign $2\wr_detect$4[0:0]$10736 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11034 1'1 + assign $3\wr_detect$4[0:0]$10737 1'1 case - assign $3\wr_detect$4[0:0]$11034 $2\wr_detect$4[0:0]$11033 + assign $3\wr_detect$4[0:0]$10737 $2\wr_detect$4[0:0]$10736 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11035 1'1 + assign $4\wr_detect$4[0:0]$10738 1'1 case - assign $4\wr_detect$4[0:0]$11035 $3\wr_detect$4[0:0]$11034 + assign $4\wr_detect$4[0:0]$10738 $3\wr_detect$4[0:0]$10737 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11036 1'1 + assign $5\wr_detect$4[0:0]$10739 1'1 case - assign $5\wr_detect$4[0:0]$11036 $4\wr_detect$4[0:0]$11035 + assign $5\wr_detect$4[0:0]$10739 $4\wr_detect$4[0:0]$10738 end case - assign $1\wr_detect$4[0:0]$11032 1'0 + assign $1\wr_detect$4[0:0]$10735 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11031 + update \wr_detect$4 $0\wr_detect$4[0:0]$10734 end - attribute \src "libresoc.v:181827.3-181872.6" - process $proc$libresoc.v:181827$11037 + attribute \src "libresoc.v:176022.3-176067.6" + process $proc$libresoc.v:176022$10740 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[1:0]$11038 $7\src30__data_o$next[1:0]$11045 - attribute \src "libresoc.v:181828.5-181828.29" + assign $0\src30__data_o$next[1:0]$10741 $7\src30__data_o$next[1:0]$10748 + attribute \src "libresoc.v:176023.5-176023.29" switch \initial - attribute \src "libresoc.v:181828.9-181828.17" + attribute \src "libresoc.v:176023.9-176023.17" case 1'1 case end @@ -372319,75 +362864,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[1:0]$11039 $6\src30__data_o$next[1:0]$11044 + assign $1\src30__data_o$next[1:0]$10742 $6\src30__data_o$next[1:0]$10747 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[1:0]$11040 \dest10__data_i + assign $2\src30__data_o$next[1:0]$10743 \dest10__data_i case - assign $2\src30__data_o$next[1:0]$11040 2'00 + assign $2\src30__data_o$next[1:0]$10743 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[1:0]$11041 \dest20__data_i + assign $3\src30__data_o$next[1:0]$10744 \dest20__data_i case - assign $3\src30__data_o$next[1:0]$11041 $2\src30__data_o$next[1:0]$11040 + assign $3\src30__data_o$next[1:0]$10744 $2\src30__data_o$next[1:0]$10743 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[1:0]$11042 \dest30__data_i + assign $4\src30__data_o$next[1:0]$10745 \dest30__data_i case - assign $4\src30__data_o$next[1:0]$11042 $3\src30__data_o$next[1:0]$11041 + assign $4\src30__data_o$next[1:0]$10745 $3\src30__data_o$next[1:0]$10744 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[1:0]$11043 \w0__data_i + assign $5\src30__data_o$next[1:0]$10746 \w0__data_i case - assign $5\src30__data_o$next[1:0]$11043 $4\src30__data_o$next[1:0]$11042 + assign $5\src30__data_o$next[1:0]$10746 $4\src30__data_o$next[1:0]$10745 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[1:0]$11044 \reg + assign $6\src30__data_o$next[1:0]$10747 \reg case - assign $6\src30__data_o$next[1:0]$11044 $5\src30__data_o$next[1:0]$11043 + assign $6\src30__data_o$next[1:0]$10747 $5\src30__data_o$next[1:0]$10746 end case - assign $1\src30__data_o$next[1:0]$11039 2'00 + assign $1\src30__data_o$next[1:0]$10742 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src30__data_o$next[1:0]$11045 2'00 + assign $7\src30__data_o$next[1:0]$10748 2'00 case - assign $7\src30__data_o$next[1:0]$11045 $1\src30__data_o$next[1:0]$11039 + assign $7\src30__data_o$next[1:0]$10748 $1\src30__data_o$next[1:0]$10742 end sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$11038 + update \src30__data_o$next $0\src30__data_o$next[1:0]$10741 end - attribute \src "libresoc.v:181873.3-181908.6" - process $proc$libresoc.v:181873$11046 + attribute \src "libresoc.v:176068.3-176103.6" + process $proc$libresoc.v:176068$10749 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11047 $1\wr_detect$7[0:0]$11048 - attribute \src "libresoc.v:181874.5-181874.29" + assign $0\wr_detect$7[0:0]$10750 $1\wr_detect$7[0:0]$10751 + attribute \src "libresoc.v:176069.5-176069.29" switch \initial - attribute \src "libresoc.v:181874.9-181874.17" + attribute \src "libresoc.v:176069.9-176069.17" case 1'1 case end @@ -372400,58 +362945,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11048 $5\wr_detect$7[0:0]$11052 + assign $1\wr_detect$7[0:0]$10751 $5\wr_detect$7[0:0]$10755 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11049 1'1 + assign $2\wr_detect$7[0:0]$10752 1'1 case - assign $2\wr_detect$7[0:0]$11049 1'0 + assign $2\wr_detect$7[0:0]$10752 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11050 1'1 + assign $3\wr_detect$7[0:0]$10753 1'1 case - assign $3\wr_detect$7[0:0]$11050 $2\wr_detect$7[0:0]$11049 + assign $3\wr_detect$7[0:0]$10753 $2\wr_detect$7[0:0]$10752 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11051 1'1 + assign $4\wr_detect$7[0:0]$10754 1'1 case - assign $4\wr_detect$7[0:0]$11051 $3\wr_detect$7[0:0]$11050 + assign $4\wr_detect$7[0:0]$10754 $3\wr_detect$7[0:0]$10753 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11052 1'1 + assign $5\wr_detect$7[0:0]$10755 1'1 case - assign $5\wr_detect$7[0:0]$11052 $4\wr_detect$7[0:0]$11051 + assign $5\wr_detect$7[0:0]$10755 $4\wr_detect$7[0:0]$10754 end case - assign $1\wr_detect$7[0:0]$11048 1'0 + assign $1\wr_detect$7[0:0]$10751 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11047 + update \wr_detect$7 $0\wr_detect$7[0:0]$10750 end - attribute \src "libresoc.v:181909.3-181954.6" - process $proc$libresoc.v:181909$11053 + attribute \src "libresoc.v:176104.3-176149.6" + process $proc$libresoc.v:176104$10756 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[1:0]$11054 $7\r0__data_o$next[1:0]$11061 - attribute \src "libresoc.v:181910.5-181910.29" + assign $0\r0__data_o$next[1:0]$10757 $7\r0__data_o$next[1:0]$10764 + attribute \src "libresoc.v:176105.5-176105.29" switch \initial - attribute \src "libresoc.v:181910.9-181910.17" + attribute \src "libresoc.v:176105.9-176105.17" case 1'1 case end @@ -372464,75 +363009,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[1:0]$11055 $6\r0__data_o$next[1:0]$11060 + assign $1\r0__data_o$next[1:0]$10758 $6\r0__data_o$next[1:0]$10763 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[1:0]$11056 \dest10__data_i + assign $2\r0__data_o$next[1:0]$10759 \dest10__data_i case - assign $2\r0__data_o$next[1:0]$11056 2'00 + assign $2\r0__data_o$next[1:0]$10759 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[1:0]$11057 \dest20__data_i + assign $3\r0__data_o$next[1:0]$10760 \dest20__data_i case - assign $3\r0__data_o$next[1:0]$11057 $2\r0__data_o$next[1:0]$11056 + assign $3\r0__data_o$next[1:0]$10760 $2\r0__data_o$next[1:0]$10759 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[1:0]$11058 \dest30__data_i + assign $4\r0__data_o$next[1:0]$10761 \dest30__data_i case - assign $4\r0__data_o$next[1:0]$11058 $3\r0__data_o$next[1:0]$11057 + assign $4\r0__data_o$next[1:0]$10761 $3\r0__data_o$next[1:0]$10760 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[1:0]$11059 \w0__data_i + assign $5\r0__data_o$next[1:0]$10762 \w0__data_i case - assign $5\r0__data_o$next[1:0]$11059 $4\r0__data_o$next[1:0]$11058 + assign $5\r0__data_o$next[1:0]$10762 $4\r0__data_o$next[1:0]$10761 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[1:0]$11060 \reg + assign $6\r0__data_o$next[1:0]$10763 \reg case - assign $6\r0__data_o$next[1:0]$11060 $5\r0__data_o$next[1:0]$11059 + assign $6\r0__data_o$next[1:0]$10763 $5\r0__data_o$next[1:0]$10762 end case - assign $1\r0__data_o$next[1:0]$11055 2'00 + assign $1\r0__data_o$next[1:0]$10758 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r0__data_o$next[1:0]$11061 2'00 + assign $7\r0__data_o$next[1:0]$10764 2'00 case - assign $7\r0__data_o$next[1:0]$11061 $1\r0__data_o$next[1:0]$11055 + assign $7\r0__data_o$next[1:0]$10764 $1\r0__data_o$next[1:0]$10758 end sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$11054 + update \r0__data_o$next $0\r0__data_o$next[1:0]$10757 end - attribute \src "libresoc.v:181955.3-181990.6" - process $proc$libresoc.v:181955$11062 + attribute \src "libresoc.v:176150.3-176185.6" + process $proc$libresoc.v:176150$10765 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11063 $1\wr_detect$10[0:0]$11064 - attribute \src "libresoc.v:181956.5-181956.29" + assign $0\wr_detect$10[0:0]$10766 $1\wr_detect$10[0:0]$10767 + attribute \src "libresoc.v:176151.5-176151.29" switch \initial - attribute \src "libresoc.v:181956.9-181956.17" + attribute \src "libresoc.v:176151.9-176151.17" case 1'1 case end @@ -372545,61 +363090,61 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11064 $5\wr_detect$10[0:0]$11068 + assign $1\wr_detect$10[0:0]$10767 $5\wr_detect$10[0:0]$10771 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11065 1'1 + assign $2\wr_detect$10[0:0]$10768 1'1 case - assign $2\wr_detect$10[0:0]$11065 1'0 + assign $2\wr_detect$10[0:0]$10768 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11066 1'1 + assign $3\wr_detect$10[0:0]$10769 1'1 case - assign $3\wr_detect$10[0:0]$11066 $2\wr_detect$10[0:0]$11065 + assign $3\wr_detect$10[0:0]$10769 $2\wr_detect$10[0:0]$10768 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11067 1'1 + assign $4\wr_detect$10[0:0]$10770 1'1 case - assign $4\wr_detect$10[0:0]$11067 $3\wr_detect$10[0:0]$11066 + assign $4\wr_detect$10[0:0]$10770 $3\wr_detect$10[0:0]$10769 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11068 1'1 + assign $5\wr_detect$10[0:0]$10771 1'1 case - assign $5\wr_detect$10[0:0]$11068 $4\wr_detect$10[0:0]$11067 + assign $5\wr_detect$10[0:0]$10771 $4\wr_detect$10[0:0]$10770 end case - assign $1\wr_detect$10[0:0]$11064 1'0 + assign $1\wr_detect$10[0:0]$10767 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11063 + update \wr_detect$10 $0\wr_detect$10[0:0]$10766 end - attribute \src "libresoc.v:181991.3-182023.6" - process $proc$libresoc.v:181991$11069 + attribute \src "libresoc.v:176186.3-176218.6" + process $proc$libresoc.v:176186$10772 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11070 $5\reg$next[1:0]$11075 - attribute \src "libresoc.v:181992.5-181992.29" + assign $0\reg$next[1:0]$10773 $5\reg$next[1:0]$10778 + attribute \src "libresoc.v:176187.5-176187.29" switch \initial - attribute \src "libresoc.v:181992.9-181992.17" + attribute \src "libresoc.v:176187.9-176187.17" case 1'1 case end @@ -372608,179 +363153,179 @@ module \reg_0$132 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11071 \dest10__data_i + assign $1\reg$next[1:0]$10774 \dest10__data_i case - assign $1\reg$next[1:0]$11071 \reg + assign $1\reg$next[1:0]$10774 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11072 \dest20__data_i + assign $2\reg$next[1:0]$10775 \dest20__data_i case - assign $2\reg$next[1:0]$11072 $1\reg$next[1:0]$11071 + assign $2\reg$next[1:0]$10775 $1\reg$next[1:0]$10774 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11073 \dest30__data_i + assign $3\reg$next[1:0]$10776 \dest30__data_i case - assign $3\reg$next[1:0]$11073 $2\reg$next[1:0]$11072 + assign $3\reg$next[1:0]$10776 $2\reg$next[1:0]$10775 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11074 \w0__data_i + assign $4\reg$next[1:0]$10777 \w0__data_i case - assign $4\reg$next[1:0]$11074 $3\reg$next[1:0]$11073 + assign $4\reg$next[1:0]$10777 $3\reg$next[1:0]$10776 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11075 2'00 + assign $5\reg$next[1:0]$10778 2'00 case - assign $5\reg$next[1:0]$11075 $4\reg$next[1:0]$11074 + assign $5\reg$next[1:0]$10778 $4\reg$next[1:0]$10777 end sync always - update \reg$next $0\reg$next[1:0]$11070 + update \reg$next $0\reg$next[1:0]$10773 end - connect \$9 $not$libresoc.v:181649$11002_Y - connect \$1 $not$libresoc.v:181650$11003_Y - connect \$3 $not$libresoc.v:181651$11004_Y - connect \$6 $not$libresoc.v:181652$11005_Y + connect \$9 $not$libresoc.v:175844$10705_Y + connect \$1 $not$libresoc.v:175845$10706_Y + connect \$3 $not$libresoc.v:175846$10707_Y + connect \$6 $not$libresoc.v:175847$10708_Y end -attribute \src "libresoc.v:182028.1-182377.10" +attribute \src "libresoc.v:176223.1-176572.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" module \reg_0$135 - attribute \src "libresoc.v:182098.3-182143.6" - wire width 64 $0\cia0__data_o$next[63:0]$11090 - attribute \src "libresoc.v:182096.3-182097.41" + attribute \src "libresoc.v:176293.3-176338.6" + wire width 64 $0\cia0__data_o$next[63:0]$10793 + attribute \src "libresoc.v:176291.3-176292.41" wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:182029.7-182029.20" + attribute \src "libresoc.v:176224.7-176224.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182180.3-182225.6" - wire width 64 $0\msr0__data_o$next[63:0]$11100 - attribute \src "libresoc.v:182094.3-182095.41" + attribute \src "libresoc.v:176375.3-176420.6" + wire width 64 $0\msr0__data_o$next[63:0]$10803 + attribute \src "libresoc.v:176289.3-176290.41" wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:182344.3-182376.6" - wire width 64 $0\reg$next[63:0]$11132 - attribute \src "libresoc.v:182090.3-182091.25" + attribute \src "libresoc.v:176539.3-176571.6" + wire width 64 $0\reg$next[63:0]$10835 + attribute \src "libresoc.v:176285.3-176286.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:182262.3-182307.6" - wire width 64 $0\sv0__data_o$next[63:0]$11116 - attribute \src "libresoc.v:182092.3-182093.39" + attribute \src "libresoc.v:176457.3-176502.6" + wire width 64 $0\sv0__data_o$next[63:0]$10819 + attribute \src "libresoc.v:176287.3-176288.39" wire width 64 $0\sv0__data_o[63:0] - attribute \src "libresoc.v:182226.3-182261.6" - wire $0\wr_detect$4[0:0]$11109 - attribute \src "libresoc.v:182308.3-182343.6" - wire $0\wr_detect$7[0:0]$11125 - attribute \src "libresoc.v:182144.3-182179.6" + attribute \src "libresoc.v:176421.3-176456.6" + wire $0\wr_detect$4[0:0]$10812 + attribute \src "libresoc.v:176503.3-176538.6" + wire $0\wr_detect$7[0:0]$10828 + attribute \src "libresoc.v:176339.3-176374.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:182098.3-182143.6" - wire width 64 $1\cia0__data_o$next[63:0]$11091 - attribute \src "libresoc.v:182038.14-182038.49" + attribute \src "libresoc.v:176293.3-176338.6" + wire width 64 $1\cia0__data_o$next[63:0]$10794 + attribute \src "libresoc.v:176233.14-176233.49" wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:182180.3-182225.6" - wire width 64 $1\msr0__data_o$next[63:0]$11101 - attribute \src "libresoc.v:182055.14-182055.49" + attribute \src "libresoc.v:176375.3-176420.6" + wire width 64 $1\msr0__data_o$next[63:0]$10804 + attribute \src "libresoc.v:176250.14-176250.49" wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:182344.3-182376.6" - wire width 64 $1\reg$next[63:0]$11133 - attribute \src "libresoc.v:182067.14-182067.42" + attribute \src "libresoc.v:176539.3-176571.6" + wire width 64 $1\reg$next[63:0]$10836 + attribute \src "libresoc.v:176262.14-176262.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:182262.3-182307.6" - wire width 64 $1\sv0__data_o$next[63:0]$11117 - attribute \src "libresoc.v:182074.14-182074.48" + attribute \src "libresoc.v:176457.3-176502.6" + wire width 64 $1\sv0__data_o$next[63:0]$10820 + attribute \src "libresoc.v:176269.14-176269.48" wire width 64 $1\sv0__data_o[63:0] - attribute \src "libresoc.v:182226.3-182261.6" - wire $1\wr_detect$4[0:0]$11110 - attribute \src "libresoc.v:182308.3-182343.6" - wire $1\wr_detect$7[0:0]$11126 - attribute \src "libresoc.v:182144.3-182179.6" + attribute \src "libresoc.v:176421.3-176456.6" + wire $1\wr_detect$4[0:0]$10813 + attribute \src "libresoc.v:176503.3-176538.6" + wire $1\wr_detect$7[0:0]$10829 + attribute \src "libresoc.v:176339.3-176374.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:182098.3-182143.6" - wire width 64 $2\cia0__data_o$next[63:0]$11092 - attribute \src "libresoc.v:182180.3-182225.6" - wire width 64 $2\msr0__data_o$next[63:0]$11102 - attribute \src "libresoc.v:182344.3-182376.6" - wire width 64 $2\reg$next[63:0]$11134 - attribute \src "libresoc.v:182262.3-182307.6" - wire width 64 $2\sv0__data_o$next[63:0]$11118 - attribute \src "libresoc.v:182226.3-182261.6" - wire $2\wr_detect$4[0:0]$11111 - attribute \src "libresoc.v:182308.3-182343.6" - wire $2\wr_detect$7[0:0]$11127 - attribute \src "libresoc.v:182144.3-182179.6" + attribute \src "libresoc.v:176293.3-176338.6" + wire width 64 $2\cia0__data_o$next[63:0]$10795 + attribute \src "libresoc.v:176375.3-176420.6" + wire width 64 $2\msr0__data_o$next[63:0]$10805 + attribute \src "libresoc.v:176539.3-176571.6" + wire width 64 $2\reg$next[63:0]$10837 + attribute \src "libresoc.v:176457.3-176502.6" + wire width 64 $2\sv0__data_o$next[63:0]$10821 + attribute \src "libresoc.v:176421.3-176456.6" + wire $2\wr_detect$4[0:0]$10814 + attribute \src "libresoc.v:176503.3-176538.6" + wire $2\wr_detect$7[0:0]$10830 + attribute \src "libresoc.v:176339.3-176374.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:182098.3-182143.6" - wire width 64 $3\cia0__data_o$next[63:0]$11093 - attribute \src "libresoc.v:182180.3-182225.6" - wire width 64 $3\msr0__data_o$next[63:0]$11103 - attribute \src "libresoc.v:182344.3-182376.6" - wire width 64 $3\reg$next[63:0]$11135 - attribute \src "libresoc.v:182262.3-182307.6" - wire width 64 $3\sv0__data_o$next[63:0]$11119 - attribute \src "libresoc.v:182226.3-182261.6" - wire $3\wr_detect$4[0:0]$11112 - attribute \src "libresoc.v:182308.3-182343.6" - wire $3\wr_detect$7[0:0]$11128 - attribute \src "libresoc.v:182144.3-182179.6" + attribute \src "libresoc.v:176293.3-176338.6" + wire width 64 $3\cia0__data_o$next[63:0]$10796 + attribute \src "libresoc.v:176375.3-176420.6" + wire width 64 $3\msr0__data_o$next[63:0]$10806 + attribute \src "libresoc.v:176539.3-176571.6" + wire width 64 $3\reg$next[63:0]$10838 + attribute \src "libresoc.v:176457.3-176502.6" + wire width 64 $3\sv0__data_o$next[63:0]$10822 + attribute \src "libresoc.v:176421.3-176456.6" + wire $3\wr_detect$4[0:0]$10815 + attribute \src "libresoc.v:176503.3-176538.6" + wire $3\wr_detect$7[0:0]$10831 + attribute \src "libresoc.v:176339.3-176374.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:182098.3-182143.6" - wire width 64 $4\cia0__data_o$next[63:0]$11094 - attribute \src "libresoc.v:182180.3-182225.6" - wire width 64 $4\msr0__data_o$next[63:0]$11104 - attribute \src "libresoc.v:182344.3-182376.6" - wire width 64 $4\reg$next[63:0]$11136 - attribute \src "libresoc.v:182262.3-182307.6" - wire width 64 $4\sv0__data_o$next[63:0]$11120 - attribute \src "libresoc.v:182226.3-182261.6" - wire $4\wr_detect$4[0:0]$11113 - attribute \src "libresoc.v:182308.3-182343.6" - wire $4\wr_detect$7[0:0]$11129 - attribute \src "libresoc.v:182144.3-182179.6" + attribute \src "libresoc.v:176293.3-176338.6" + wire width 64 $4\cia0__data_o$next[63:0]$10797 + attribute \src "libresoc.v:176375.3-176420.6" + wire width 64 $4\msr0__data_o$next[63:0]$10807 + attribute \src "libresoc.v:176539.3-176571.6" + wire width 64 $4\reg$next[63:0]$10839 + attribute \src "libresoc.v:176457.3-176502.6" + wire width 64 $4\sv0__data_o$next[63:0]$10823 + attribute \src "libresoc.v:176421.3-176456.6" + wire $4\wr_detect$4[0:0]$10816 + attribute \src "libresoc.v:176503.3-176538.6" + wire $4\wr_detect$7[0:0]$10832 + attribute \src "libresoc.v:176339.3-176374.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:182098.3-182143.6" - wire width 64 $5\cia0__data_o$next[63:0]$11095 - attribute \src "libresoc.v:182180.3-182225.6" - wire width 64 $5\msr0__data_o$next[63:0]$11105 - attribute \src "libresoc.v:182344.3-182376.6" - wire width 64 $5\reg$next[63:0]$11137 - attribute \src "libresoc.v:182262.3-182307.6" - wire width 64 $5\sv0__data_o$next[63:0]$11121 - attribute \src "libresoc.v:182226.3-182261.6" - wire $5\wr_detect$4[0:0]$11114 - attribute \src "libresoc.v:182308.3-182343.6" - wire $5\wr_detect$7[0:0]$11130 - attribute \src "libresoc.v:182144.3-182179.6" + attribute \src "libresoc.v:176293.3-176338.6" + wire width 64 $5\cia0__data_o$next[63:0]$10798 + attribute \src "libresoc.v:176375.3-176420.6" + wire width 64 $5\msr0__data_o$next[63:0]$10808 + attribute \src "libresoc.v:176539.3-176571.6" + wire width 64 $5\reg$next[63:0]$10840 + attribute \src "libresoc.v:176457.3-176502.6" + wire width 64 $5\sv0__data_o$next[63:0]$10824 + attribute \src "libresoc.v:176421.3-176456.6" + wire $5\wr_detect$4[0:0]$10817 + attribute \src "libresoc.v:176503.3-176538.6" + wire $5\wr_detect$7[0:0]$10833 + attribute \src "libresoc.v:176339.3-176374.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:182098.3-182143.6" - wire width 64 $6\cia0__data_o$next[63:0]$11096 - attribute \src "libresoc.v:182180.3-182225.6" - wire width 64 $6\msr0__data_o$next[63:0]$11106 - attribute \src "libresoc.v:182262.3-182307.6" - wire width 64 $6\sv0__data_o$next[63:0]$11122 - attribute \src "libresoc.v:182098.3-182143.6" - wire width 64 $7\cia0__data_o$next[63:0]$11097 - attribute \src "libresoc.v:182180.3-182225.6" - wire width 64 $7\msr0__data_o$next[63:0]$11107 - attribute \src "libresoc.v:182262.3-182307.6" - wire width 64 $7\sv0__data_o$next[63:0]$11123 - attribute \src "libresoc.v:182087.17-182087.100" - wire $not$libresoc.v:182087$11082_Y - attribute \src "libresoc.v:182088.17-182088.103" - wire $not$libresoc.v:182088$11083_Y - attribute \src "libresoc.v:182089.17-182089.103" - wire $not$libresoc.v:182089$11084_Y + attribute \src "libresoc.v:176293.3-176338.6" + wire width 64 $6\cia0__data_o$next[63:0]$10799 + attribute \src "libresoc.v:176375.3-176420.6" + wire width 64 $6\msr0__data_o$next[63:0]$10809 + attribute \src "libresoc.v:176457.3-176502.6" + wire width 64 $6\sv0__data_o$next[63:0]$10825 + attribute \src "libresoc.v:176293.3-176338.6" + wire width 64 $7\cia0__data_o$next[63:0]$10800 + attribute \src "libresoc.v:176375.3-176420.6" + wire width 64 $7\msr0__data_o$next[63:0]$10810 + attribute \src "libresoc.v:176457.3-176502.6" + wire width 64 $7\sv0__data_o$next[63:0]$10826 + attribute \src "libresoc.v:176282.17-176282.100" + wire $not$libresoc.v:176282$10785_Y + attribute \src "libresoc.v:176283.17-176283.103" + wire $not$libresoc.v:176283$10786_Y + attribute \src "libresoc.v:176284.17-176284.103" + wire $not$libresoc.v:176284$10787_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -372793,15 +363338,15 @@ module \reg_0$135 wire width 64 \cia0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr10__wen - attribute \src "libresoc.v:182029.7-182029.15" + attribute \src "libresoc.v:176224.7-176224.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr0__data_i @@ -372838,106 +363383,106 @@ module \reg_0$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182087$11082 + cell $not $not$libresoc.v:176282$10785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182087$11082_Y + connect \Y $not$libresoc.v:176282$10785_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182088$11083 + cell $not $not$libresoc.v:176283$10786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182088$11083_Y + connect \Y $not$libresoc.v:176283$10786_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182089$11084 + cell $not $not$libresoc.v:176284$10787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182089$11084_Y + connect \Y $not$libresoc.v:176284$10787_Y end - attribute \src "libresoc.v:182029.7-182029.20" - process $proc$libresoc.v:182029$11138 + attribute \src "libresoc.v:176224.7-176224.20" + process $proc$libresoc.v:176224$10841 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182038.14-182038.49" - process $proc$libresoc.v:182038$11139 + attribute \src "libresoc.v:176233.14-176233.49" + process $proc$libresoc.v:176233$10842 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end - attribute \src "libresoc.v:182055.14-182055.49" - process $proc$libresoc.v:182055$11140 + attribute \src "libresoc.v:176250.14-176250.49" + process $proc$libresoc.v:176250$10843 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end - attribute \src "libresoc.v:182067.14-182067.42" - process $proc$libresoc.v:182067$11141 + attribute \src "libresoc.v:176262.14-176262.42" + process $proc$libresoc.v:176262$10844 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:182074.14-182074.48" - process $proc$libresoc.v:182074$11142 + attribute \src "libresoc.v:176269.14-176269.48" + process $proc$libresoc.v:176269$10845 assign { } { } assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv0__data_o $1\sv0__data_o[63:0] end - attribute \src "libresoc.v:182090.3-182091.25" - process $proc$libresoc.v:182090$11085 + attribute \src "libresoc.v:176285.3-176286.25" + process $proc$libresoc.v:176285$10788 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:182092.3-182093.39" - process $proc$libresoc.v:182092$11086 + attribute \src "libresoc.v:176287.3-176288.39" + process $proc$libresoc.v:176287$10789 assign { } { } assign $0\sv0__data_o[63:0] \sv0__data_o$next sync posedge \coresync_clk update \sv0__data_o $0\sv0__data_o[63:0] end - attribute \src "libresoc.v:182094.3-182095.41" - process $proc$libresoc.v:182094$11087 + attribute \src "libresoc.v:176289.3-176290.41" + process $proc$libresoc.v:176289$10790 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end - attribute \src "libresoc.v:182096.3-182097.41" - process $proc$libresoc.v:182096$11088 + attribute \src "libresoc.v:176291.3-176292.41" + process $proc$libresoc.v:176291$10791 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end - attribute \src "libresoc.v:182098.3-182143.6" - process $proc$libresoc.v:182098$11089 + attribute \src "libresoc.v:176293.3-176338.6" + process $proc$libresoc.v:176293$10792 assign { } { } assign { } { } assign { } { } - assign $0\cia0__data_o$next[63:0]$11090 $7\cia0__data_o$next[63:0]$11097 - attribute \src "libresoc.v:182099.5-182099.29" + assign $0\cia0__data_o$next[63:0]$10793 $7\cia0__data_o$next[63:0]$10800 + attribute \src "libresoc.v:176294.5-176294.29" switch \initial - attribute \src "libresoc.v:182099.9-182099.17" + attribute \src "libresoc.v:176294.9-176294.17" case 1'1 case end @@ -372950,75 +363495,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\cia0__data_o$next[63:0]$11091 $6\cia0__data_o$next[63:0]$11096 + assign $1\cia0__data_o$next[63:0]$10794 $6\cia0__data_o$next[63:0]$10799 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia0__data_o$next[63:0]$11092 \nia0__data_i + assign $2\cia0__data_o$next[63:0]$10795 \nia0__data_i case - assign $2\cia0__data_o$next[63:0]$11092 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia0__data_o$next[63:0]$10795 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia0__data_o$next[63:0]$11093 \msr0__data_i + assign $3\cia0__data_o$next[63:0]$10796 \msr0__data_i case - assign $3\cia0__data_o$next[63:0]$11093 $2\cia0__data_o$next[63:0]$11092 + assign $3\cia0__data_o$next[63:0]$10796 $2\cia0__data_o$next[63:0]$10795 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia0__data_o$next[63:0]$11094 \sv0__data_i + assign $4\cia0__data_o$next[63:0]$10797 \sv0__data_i case - assign $4\cia0__data_o$next[63:0]$11094 $3\cia0__data_o$next[63:0]$11093 + assign $4\cia0__data_o$next[63:0]$10797 $3\cia0__data_o$next[63:0]$10796 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia0__data_o$next[63:0]$11095 \d_wr10__data_i + assign $5\cia0__data_o$next[63:0]$10798 \d_wr10__data_i case - assign $5\cia0__data_o$next[63:0]$11095 $4\cia0__data_o$next[63:0]$11094 + assign $5\cia0__data_o$next[63:0]$10798 $4\cia0__data_o$next[63:0]$10797 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia0__data_o$next[63:0]$11096 \reg + assign $6\cia0__data_o$next[63:0]$10799 \reg case - assign $6\cia0__data_o$next[63:0]$11096 $5\cia0__data_o$next[63:0]$11095 + assign $6\cia0__data_o$next[63:0]$10799 $5\cia0__data_o$next[63:0]$10798 end case - assign $1\cia0__data_o$next[63:0]$11091 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia0__data_o$next[63:0]$10794 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia0__data_o$next[63:0]$11097 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia0__data_o$next[63:0]$10800 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia0__data_o$next[63:0]$11097 $1\cia0__data_o$next[63:0]$11091 + assign $7\cia0__data_o$next[63:0]$10800 $1\cia0__data_o$next[63:0]$10794 end sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$11090 + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10793 end - attribute \src "libresoc.v:182144.3-182179.6" - process $proc$libresoc.v:182144$11098 + attribute \src "libresoc.v:176339.3-176374.6" + process $proc$libresoc.v:176339$10801 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182145.5-182145.29" + attribute \src "libresoc.v:176340.5-176340.29" switch \initial - attribute \src "libresoc.v:182145.9-182145.17" + attribute \src "libresoc.v:176340.9-176340.17" case 1'1 case end @@ -373074,15 +363619,15 @@ module \reg_0$135 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:182180.3-182225.6" - process $proc$libresoc.v:182180$11099 + attribute \src "libresoc.v:176375.3-176420.6" + process $proc$libresoc.v:176375$10802 assign { } { } assign { } { } assign { } { } - assign $0\msr0__data_o$next[63:0]$11100 $7\msr0__data_o$next[63:0]$11107 - attribute \src "libresoc.v:182181.5-182181.29" + assign $0\msr0__data_o$next[63:0]$10803 $7\msr0__data_o$next[63:0]$10810 + attribute \src "libresoc.v:176376.5-176376.29" switch \initial - attribute \src "libresoc.v:182181.9-182181.17" + attribute \src "libresoc.v:176376.9-176376.17" case 1'1 case end @@ -373095,75 +363640,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\msr0__data_o$next[63:0]$11101 $6\msr0__data_o$next[63:0]$11106 + assign $1\msr0__data_o$next[63:0]$10804 $6\msr0__data_o$next[63:0]$10809 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr0__data_o$next[63:0]$11102 \nia0__data_i + assign $2\msr0__data_o$next[63:0]$10805 \nia0__data_i case - assign $2\msr0__data_o$next[63:0]$11102 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr0__data_o$next[63:0]$10805 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr0__data_o$next[63:0]$11103 \msr0__data_i + assign $3\msr0__data_o$next[63:0]$10806 \msr0__data_i case - assign $3\msr0__data_o$next[63:0]$11103 $2\msr0__data_o$next[63:0]$11102 + assign $3\msr0__data_o$next[63:0]$10806 $2\msr0__data_o$next[63:0]$10805 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr0__data_o$next[63:0]$11104 \sv0__data_i + assign $4\msr0__data_o$next[63:0]$10807 \sv0__data_i case - assign $4\msr0__data_o$next[63:0]$11104 $3\msr0__data_o$next[63:0]$11103 + assign $4\msr0__data_o$next[63:0]$10807 $3\msr0__data_o$next[63:0]$10806 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr0__data_o$next[63:0]$11105 \d_wr10__data_i + assign $5\msr0__data_o$next[63:0]$10808 \d_wr10__data_i case - assign $5\msr0__data_o$next[63:0]$11105 $4\msr0__data_o$next[63:0]$11104 + assign $5\msr0__data_o$next[63:0]$10808 $4\msr0__data_o$next[63:0]$10807 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr0__data_o$next[63:0]$11106 \reg + assign $6\msr0__data_o$next[63:0]$10809 \reg case - assign $6\msr0__data_o$next[63:0]$11106 $5\msr0__data_o$next[63:0]$11105 + assign $6\msr0__data_o$next[63:0]$10809 $5\msr0__data_o$next[63:0]$10808 end case - assign $1\msr0__data_o$next[63:0]$11101 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr0__data_o$next[63:0]$10804 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr0__data_o$next[63:0]$11107 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr0__data_o$next[63:0]$10810 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr0__data_o$next[63:0]$11107 $1\msr0__data_o$next[63:0]$11101 + assign $7\msr0__data_o$next[63:0]$10810 $1\msr0__data_o$next[63:0]$10804 end sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$11100 + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10803 end - attribute \src "libresoc.v:182226.3-182261.6" - process $proc$libresoc.v:182226$11108 + attribute \src "libresoc.v:176421.3-176456.6" + process $proc$libresoc.v:176421$10811 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11109 $1\wr_detect$4[0:0]$11110 - attribute \src "libresoc.v:182227.5-182227.29" + assign $0\wr_detect$4[0:0]$10812 $1\wr_detect$4[0:0]$10813 + attribute \src "libresoc.v:176422.5-176422.29" switch \initial - attribute \src "libresoc.v:182227.9-182227.17" + attribute \src "libresoc.v:176422.9-176422.17" case 1'1 case end @@ -373176,58 +363721,58 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11110 $5\wr_detect$4[0:0]$11114 + assign $1\wr_detect$4[0:0]$10813 $5\wr_detect$4[0:0]$10817 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11111 1'1 + assign $2\wr_detect$4[0:0]$10814 1'1 case - assign $2\wr_detect$4[0:0]$11111 1'0 + assign $2\wr_detect$4[0:0]$10814 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11112 1'1 + assign $3\wr_detect$4[0:0]$10815 1'1 case - assign $3\wr_detect$4[0:0]$11112 $2\wr_detect$4[0:0]$11111 + assign $3\wr_detect$4[0:0]$10815 $2\wr_detect$4[0:0]$10814 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11113 1'1 + assign $4\wr_detect$4[0:0]$10816 1'1 case - assign $4\wr_detect$4[0:0]$11113 $3\wr_detect$4[0:0]$11112 + assign $4\wr_detect$4[0:0]$10816 $3\wr_detect$4[0:0]$10815 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11114 1'1 + assign $5\wr_detect$4[0:0]$10817 1'1 case - assign $5\wr_detect$4[0:0]$11114 $4\wr_detect$4[0:0]$11113 + assign $5\wr_detect$4[0:0]$10817 $4\wr_detect$4[0:0]$10816 end case - assign $1\wr_detect$4[0:0]$11110 1'0 + assign $1\wr_detect$4[0:0]$10813 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11109 + update \wr_detect$4 $0\wr_detect$4[0:0]$10812 end - attribute \src "libresoc.v:182262.3-182307.6" - process $proc$libresoc.v:182262$11115 + attribute \src "libresoc.v:176457.3-176502.6" + process $proc$libresoc.v:176457$10818 assign { } { } assign { } { } assign { } { } - assign $0\sv0__data_o$next[63:0]$11116 $7\sv0__data_o$next[63:0]$11123 - attribute \src "libresoc.v:182263.5-182263.29" + assign $0\sv0__data_o$next[63:0]$10819 $7\sv0__data_o$next[63:0]$10826 + attribute \src "libresoc.v:176458.5-176458.29" switch \initial - attribute \src "libresoc.v:182263.9-182263.17" + attribute \src "libresoc.v:176458.9-176458.17" case 1'1 case end @@ -373240,75 +363785,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\sv0__data_o$next[63:0]$11117 $6\sv0__data_o$next[63:0]$11122 + assign $1\sv0__data_o$next[63:0]$10820 $6\sv0__data_o$next[63:0]$10825 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv0__data_o$next[63:0]$11118 \nia0__data_i + assign $2\sv0__data_o$next[63:0]$10821 \nia0__data_i case - assign $2\sv0__data_o$next[63:0]$11118 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv0__data_o$next[63:0]$10821 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv0__data_o$next[63:0]$11119 \msr0__data_i + assign $3\sv0__data_o$next[63:0]$10822 \msr0__data_i case - assign $3\sv0__data_o$next[63:0]$11119 $2\sv0__data_o$next[63:0]$11118 + assign $3\sv0__data_o$next[63:0]$10822 $2\sv0__data_o$next[63:0]$10821 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv0__data_o$next[63:0]$11120 \sv0__data_i + assign $4\sv0__data_o$next[63:0]$10823 \sv0__data_i case - assign $4\sv0__data_o$next[63:0]$11120 $3\sv0__data_o$next[63:0]$11119 + assign $4\sv0__data_o$next[63:0]$10823 $3\sv0__data_o$next[63:0]$10822 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv0__data_o$next[63:0]$11121 \d_wr10__data_i + assign $5\sv0__data_o$next[63:0]$10824 \d_wr10__data_i case - assign $5\sv0__data_o$next[63:0]$11121 $4\sv0__data_o$next[63:0]$11120 + assign $5\sv0__data_o$next[63:0]$10824 $4\sv0__data_o$next[63:0]$10823 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv0__data_o$next[63:0]$11122 \reg + assign $6\sv0__data_o$next[63:0]$10825 \reg case - assign $6\sv0__data_o$next[63:0]$11122 $5\sv0__data_o$next[63:0]$11121 + assign $6\sv0__data_o$next[63:0]$10825 $5\sv0__data_o$next[63:0]$10824 end case - assign $1\sv0__data_o$next[63:0]$11117 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv0__data_o$next[63:0]$10820 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv0__data_o$next[63:0]$11123 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv0__data_o$next[63:0]$10826 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv0__data_o$next[63:0]$11123 $1\sv0__data_o$next[63:0]$11117 + assign $7\sv0__data_o$next[63:0]$10826 $1\sv0__data_o$next[63:0]$10820 end sync always - update \sv0__data_o$next $0\sv0__data_o$next[63:0]$11116 + update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10819 end - attribute \src "libresoc.v:182308.3-182343.6" - process $proc$libresoc.v:182308$11124 + attribute \src "libresoc.v:176503.3-176538.6" + process $proc$libresoc.v:176503$10827 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11125 $1\wr_detect$7[0:0]$11126 - attribute \src "libresoc.v:182309.5-182309.29" + assign $0\wr_detect$7[0:0]$10828 $1\wr_detect$7[0:0]$10829 + attribute \src "libresoc.v:176504.5-176504.29" switch \initial - attribute \src "libresoc.v:182309.9-182309.17" + attribute \src "libresoc.v:176504.9-176504.17" case 1'1 case end @@ -373321,61 +363866,61 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11126 $5\wr_detect$7[0:0]$11130 + assign $1\wr_detect$7[0:0]$10829 $5\wr_detect$7[0:0]$10833 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11127 1'1 + assign $2\wr_detect$7[0:0]$10830 1'1 case - assign $2\wr_detect$7[0:0]$11127 1'0 + assign $2\wr_detect$7[0:0]$10830 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11128 1'1 + assign $3\wr_detect$7[0:0]$10831 1'1 case - assign $3\wr_detect$7[0:0]$11128 $2\wr_detect$7[0:0]$11127 + assign $3\wr_detect$7[0:0]$10831 $2\wr_detect$7[0:0]$10830 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11129 1'1 + assign $4\wr_detect$7[0:0]$10832 1'1 case - assign $4\wr_detect$7[0:0]$11129 $3\wr_detect$7[0:0]$11128 + assign $4\wr_detect$7[0:0]$10832 $3\wr_detect$7[0:0]$10831 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11130 1'1 + assign $5\wr_detect$7[0:0]$10833 1'1 case - assign $5\wr_detect$7[0:0]$11130 $4\wr_detect$7[0:0]$11129 + assign $5\wr_detect$7[0:0]$10833 $4\wr_detect$7[0:0]$10832 end case - assign $1\wr_detect$7[0:0]$11126 1'0 + assign $1\wr_detect$7[0:0]$10829 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11125 + update \wr_detect$7 $0\wr_detect$7[0:0]$10828 end - attribute \src "libresoc.v:182344.3-182376.6" - process $proc$libresoc.v:182344$11131 + attribute \src "libresoc.v:176539.3-176571.6" + process $proc$libresoc.v:176539$10834 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11132 $5\reg$next[63:0]$11137 - attribute \src "libresoc.v:182345.5-182345.29" + assign $0\reg$next[63:0]$10835 $5\reg$next[63:0]$10840 + attribute \src "libresoc.v:176540.5-176540.29" switch \initial - attribute \src "libresoc.v:182345.9-182345.17" + attribute \src "libresoc.v:176540.9-176540.17" case 1'1 case end @@ -373384,224 +363929,224 @@ module \reg_0$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11133 \nia0__data_i + assign $1\reg$next[63:0]$10836 \nia0__data_i case - assign $1\reg$next[63:0]$11133 \reg + assign $1\reg$next[63:0]$10836 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11134 \msr0__data_i + assign $2\reg$next[63:0]$10837 \msr0__data_i case - assign $2\reg$next[63:0]$11134 $1\reg$next[63:0]$11133 + assign $2\reg$next[63:0]$10837 $1\reg$next[63:0]$10836 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11135 \sv0__data_i + assign $3\reg$next[63:0]$10838 \sv0__data_i case - assign $3\reg$next[63:0]$11135 $2\reg$next[63:0]$11134 + assign $3\reg$next[63:0]$10838 $2\reg$next[63:0]$10837 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11136 \d_wr10__data_i + assign $4\reg$next[63:0]$10839 \d_wr10__data_i case - assign $4\reg$next[63:0]$11136 $3\reg$next[63:0]$11135 + assign $4\reg$next[63:0]$10839 $3\reg$next[63:0]$10838 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11137 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$10840 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11137 $4\reg$next[63:0]$11136 + assign $5\reg$next[63:0]$10840 $4\reg$next[63:0]$10839 end sync always - update \reg$next $0\reg$next[63:0]$11132 + update \reg$next $0\reg$next[63:0]$10835 end - connect \$1 $not$libresoc.v:182087$11082_Y - connect \$3 $not$libresoc.v:182088$11083_Y - connect \$6 $not$libresoc.v:182089$11084_Y + connect \$1 $not$libresoc.v:176282$10785_Y + connect \$3 $not$libresoc.v:176283$10786_Y + connect \$6 $not$libresoc.v:176284$10787_Y end -attribute \src "libresoc.v:182381.1-182852.10" +attribute \src "libresoc.v:176576.1-177047.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 - attribute \src "libresoc.v:182382.7-182382.20" + attribute \src "libresoc.v:176577.7-176577.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182712.3-182751.6" - wire width 4 $0\r1__data_o$next[3:0]$11198 - attribute \src "libresoc.v:182467.3-182468.37" + attribute \src "libresoc.v:176907.3-176946.6" + wire width 4 $0\r1__data_o$next[3:0]$10901 + attribute \src "libresoc.v:176662.3-176663.37" wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:182782.3-182821.6" - wire width 4 $0\r21__data_o$next[3:0]$11212 - attribute \src "libresoc.v:182465.3-182466.39" + attribute \src "libresoc.v:176977.3-177016.6" + wire width 4 $0\r21__data_o$next[3:0]$10915 + attribute \src "libresoc.v:176660.3-176661.39" wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:182545.3-182571.6" - wire width 4 $0\reg$next[3:0]$11164 - attribute \src "libresoc.v:182463.3-182464.25" + attribute \src "libresoc.v:176740.3-176766.6" + wire width 4 $0\reg$next[3:0]$10867 + attribute \src "libresoc.v:176658.3-176659.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:182475.3-182514.6" - wire width 4 $0\src11__data_o$next[3:0]$11155 - attribute \src "libresoc.v:182473.3-182474.43" + attribute \src "libresoc.v:176670.3-176709.6" + wire width 4 $0\src11__data_o$next[3:0]$10858 + attribute \src "libresoc.v:176668.3-176669.43" wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:182572.3-182611.6" - wire width 4 $0\src21__data_o$next[3:0]$11170 - attribute \src "libresoc.v:182471.3-182472.43" + attribute \src "libresoc.v:176767.3-176806.6" + wire width 4 $0\src21__data_o$next[3:0]$10873 + attribute \src "libresoc.v:176666.3-176667.43" wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:182642.3-182681.6" - wire width 4 $0\src31__data_o$next[3:0]$11184 - attribute \src "libresoc.v:182469.3-182470.43" + attribute \src "libresoc.v:176837.3-176876.6" + wire width 4 $0\src31__data_o$next[3:0]$10887 + attribute \src "libresoc.v:176664.3-176665.43" wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:182752.3-182781.6" - wire $0\wr_detect$10[0:0]$11206 - attribute \src "libresoc.v:182822.3-182851.6" - wire $0\wr_detect$13[0:0]$11220 - attribute \src "libresoc.v:182612.3-182641.6" - wire $0\wr_detect$4[0:0]$11178 - attribute \src "libresoc.v:182682.3-182711.6" - wire $0\wr_detect$7[0:0]$11192 - attribute \src "libresoc.v:182515.3-182544.6" + attribute \src "libresoc.v:176947.3-176976.6" + wire $0\wr_detect$10[0:0]$10909 + attribute \src "libresoc.v:177017.3-177046.6" + wire $0\wr_detect$13[0:0]$10923 + attribute \src "libresoc.v:176807.3-176836.6" + wire $0\wr_detect$4[0:0]$10881 + attribute \src "libresoc.v:176877.3-176906.6" + wire $0\wr_detect$7[0:0]$10895 + attribute \src "libresoc.v:176710.3-176739.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:182712.3-182751.6" - wire width 4 $1\r1__data_o$next[3:0]$11199 - attribute \src "libresoc.v:182407.13-182407.30" + attribute \src "libresoc.v:176907.3-176946.6" + wire width 4 $1\r1__data_o$next[3:0]$10902 + attribute \src "libresoc.v:176602.13-176602.30" wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:182782.3-182821.6" - wire width 4 $1\r21__data_o$next[3:0]$11213 - attribute \src "libresoc.v:182414.13-182414.31" + attribute \src "libresoc.v:176977.3-177016.6" + wire width 4 $1\r21__data_o$next[3:0]$10916 + attribute \src "libresoc.v:176609.13-176609.31" wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:182545.3-182571.6" - wire width 4 $1\reg$next[3:0]$11165 - attribute \src "libresoc.v:182420.13-182420.25" + attribute \src "libresoc.v:176740.3-176766.6" + wire width 4 $1\reg$next[3:0]$10868 + attribute \src "libresoc.v:176615.13-176615.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:182475.3-182514.6" - wire width 4 $1\src11__data_o$next[3:0]$11156 - attribute \src "libresoc.v:182425.13-182425.33" + attribute \src "libresoc.v:176670.3-176709.6" + wire width 4 $1\src11__data_o$next[3:0]$10859 + attribute \src "libresoc.v:176620.13-176620.33" wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:182572.3-182611.6" - wire width 4 $1\src21__data_o$next[3:0]$11171 - attribute \src "libresoc.v:182432.13-182432.33" + attribute \src "libresoc.v:176767.3-176806.6" + wire width 4 $1\src21__data_o$next[3:0]$10874 + attribute \src "libresoc.v:176627.13-176627.33" wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:182642.3-182681.6" - wire width 4 $1\src31__data_o$next[3:0]$11185 - attribute \src "libresoc.v:182439.13-182439.33" + attribute \src "libresoc.v:176837.3-176876.6" + wire width 4 $1\src31__data_o$next[3:0]$10888 + attribute \src "libresoc.v:176634.13-176634.33" wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:182752.3-182781.6" - wire $1\wr_detect$10[0:0]$11207 - attribute \src "libresoc.v:182822.3-182851.6" - wire $1\wr_detect$13[0:0]$11221 - attribute \src "libresoc.v:182612.3-182641.6" - wire $1\wr_detect$4[0:0]$11179 - attribute \src "libresoc.v:182682.3-182711.6" - wire $1\wr_detect$7[0:0]$11193 - attribute \src "libresoc.v:182515.3-182544.6" + attribute \src "libresoc.v:176947.3-176976.6" + wire $1\wr_detect$10[0:0]$10910 + attribute \src "libresoc.v:177017.3-177046.6" + wire $1\wr_detect$13[0:0]$10924 + attribute \src "libresoc.v:176807.3-176836.6" + wire $1\wr_detect$4[0:0]$10882 + attribute \src "libresoc.v:176877.3-176906.6" + wire $1\wr_detect$7[0:0]$10896 + attribute \src "libresoc.v:176710.3-176739.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:182712.3-182751.6" - wire width 4 $2\r1__data_o$next[3:0]$11200 - attribute \src "libresoc.v:182782.3-182821.6" - wire width 4 $2\r21__data_o$next[3:0]$11214 - attribute \src "libresoc.v:182545.3-182571.6" - wire width 4 $2\reg$next[3:0]$11166 - attribute \src "libresoc.v:182475.3-182514.6" - wire width 4 $2\src11__data_o$next[3:0]$11157 - attribute \src "libresoc.v:182572.3-182611.6" - wire width 4 $2\src21__data_o$next[3:0]$11172 - attribute \src "libresoc.v:182642.3-182681.6" - wire width 4 $2\src31__data_o$next[3:0]$11186 - attribute \src "libresoc.v:182752.3-182781.6" - wire $2\wr_detect$10[0:0]$11208 - attribute \src "libresoc.v:182822.3-182851.6" - wire $2\wr_detect$13[0:0]$11222 - attribute \src "libresoc.v:182612.3-182641.6" - wire $2\wr_detect$4[0:0]$11180 - attribute \src "libresoc.v:182682.3-182711.6" - wire $2\wr_detect$7[0:0]$11194 - attribute \src "libresoc.v:182515.3-182544.6" + attribute \src "libresoc.v:176907.3-176946.6" + wire width 4 $2\r1__data_o$next[3:0]$10903 + attribute \src "libresoc.v:176977.3-177016.6" + wire width 4 $2\r21__data_o$next[3:0]$10917 + attribute \src "libresoc.v:176740.3-176766.6" + wire width 4 $2\reg$next[3:0]$10869 + attribute \src "libresoc.v:176670.3-176709.6" + wire width 4 $2\src11__data_o$next[3:0]$10860 + attribute \src "libresoc.v:176767.3-176806.6" + wire width 4 $2\src21__data_o$next[3:0]$10875 + attribute \src "libresoc.v:176837.3-176876.6" + wire width 4 $2\src31__data_o$next[3:0]$10889 + attribute \src "libresoc.v:176947.3-176976.6" + wire $2\wr_detect$10[0:0]$10911 + attribute \src "libresoc.v:177017.3-177046.6" + wire $2\wr_detect$13[0:0]$10925 + attribute \src "libresoc.v:176807.3-176836.6" + wire $2\wr_detect$4[0:0]$10883 + attribute \src "libresoc.v:176877.3-176906.6" + wire $2\wr_detect$7[0:0]$10897 + attribute \src "libresoc.v:176710.3-176739.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:182712.3-182751.6" - wire width 4 $3\r1__data_o$next[3:0]$11201 - attribute \src "libresoc.v:182782.3-182821.6" - wire width 4 $3\r21__data_o$next[3:0]$11215 - attribute \src "libresoc.v:182545.3-182571.6" - wire width 4 $3\reg$next[3:0]$11167 - attribute \src "libresoc.v:182475.3-182514.6" - wire width 4 $3\src11__data_o$next[3:0]$11158 - attribute \src "libresoc.v:182572.3-182611.6" - wire width 4 $3\src21__data_o$next[3:0]$11173 - attribute \src "libresoc.v:182642.3-182681.6" - wire width 4 $3\src31__data_o$next[3:0]$11187 - attribute \src "libresoc.v:182752.3-182781.6" - wire $3\wr_detect$10[0:0]$11209 - attribute \src "libresoc.v:182822.3-182851.6" - wire $3\wr_detect$13[0:0]$11223 - attribute \src "libresoc.v:182612.3-182641.6" - wire $3\wr_detect$4[0:0]$11181 - attribute \src "libresoc.v:182682.3-182711.6" - wire $3\wr_detect$7[0:0]$11195 - attribute \src "libresoc.v:182515.3-182544.6" + attribute \src "libresoc.v:176907.3-176946.6" + wire width 4 $3\r1__data_o$next[3:0]$10904 + attribute \src "libresoc.v:176977.3-177016.6" + wire width 4 $3\r21__data_o$next[3:0]$10918 + attribute \src "libresoc.v:176740.3-176766.6" + wire width 4 $3\reg$next[3:0]$10870 + attribute \src "libresoc.v:176670.3-176709.6" + wire width 4 $3\src11__data_o$next[3:0]$10861 + attribute \src "libresoc.v:176767.3-176806.6" + wire width 4 $3\src21__data_o$next[3:0]$10876 + attribute \src "libresoc.v:176837.3-176876.6" + wire width 4 $3\src31__data_o$next[3:0]$10890 + attribute \src "libresoc.v:176947.3-176976.6" + wire $3\wr_detect$10[0:0]$10912 + attribute \src "libresoc.v:177017.3-177046.6" + wire $3\wr_detect$13[0:0]$10926 + attribute \src "libresoc.v:176807.3-176836.6" + wire $3\wr_detect$4[0:0]$10884 + attribute \src "libresoc.v:176877.3-176906.6" + wire $3\wr_detect$7[0:0]$10898 + attribute \src "libresoc.v:176710.3-176739.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:182712.3-182751.6" - wire width 4 $4\r1__data_o$next[3:0]$11202 - attribute \src "libresoc.v:182782.3-182821.6" - wire width 4 $4\r21__data_o$next[3:0]$11216 - attribute \src "libresoc.v:182545.3-182571.6" - wire width 4 $4\reg$next[3:0]$11168 - attribute \src "libresoc.v:182475.3-182514.6" - wire width 4 $4\src11__data_o$next[3:0]$11159 - attribute \src "libresoc.v:182572.3-182611.6" - wire width 4 $4\src21__data_o$next[3:0]$11174 - attribute \src "libresoc.v:182642.3-182681.6" - wire width 4 $4\src31__data_o$next[3:0]$11188 - attribute \src "libresoc.v:182752.3-182781.6" - wire $4\wr_detect$10[0:0]$11210 - attribute \src "libresoc.v:182822.3-182851.6" - wire $4\wr_detect$13[0:0]$11224 - attribute \src "libresoc.v:182612.3-182641.6" - wire $4\wr_detect$4[0:0]$11182 - attribute \src "libresoc.v:182682.3-182711.6" - wire $4\wr_detect$7[0:0]$11196 - attribute \src "libresoc.v:182515.3-182544.6" + attribute \src "libresoc.v:176907.3-176946.6" + wire width 4 $4\r1__data_o$next[3:0]$10905 + attribute \src "libresoc.v:176977.3-177016.6" + wire width 4 $4\r21__data_o$next[3:0]$10919 + attribute \src "libresoc.v:176740.3-176766.6" + wire width 4 $4\reg$next[3:0]$10871 + attribute \src "libresoc.v:176670.3-176709.6" + wire width 4 $4\src11__data_o$next[3:0]$10862 + attribute \src "libresoc.v:176767.3-176806.6" + wire width 4 $4\src21__data_o$next[3:0]$10877 + attribute \src "libresoc.v:176837.3-176876.6" + wire width 4 $4\src31__data_o$next[3:0]$10891 + attribute \src "libresoc.v:176947.3-176976.6" + wire $4\wr_detect$10[0:0]$10913 + attribute \src "libresoc.v:177017.3-177046.6" + wire $4\wr_detect$13[0:0]$10927 + attribute \src "libresoc.v:176807.3-176836.6" + wire $4\wr_detect$4[0:0]$10885 + attribute \src "libresoc.v:176877.3-176906.6" + wire $4\wr_detect$7[0:0]$10899 + attribute \src "libresoc.v:176710.3-176739.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:182712.3-182751.6" - wire width 4 $5\r1__data_o$next[3:0]$11203 - attribute \src "libresoc.v:182782.3-182821.6" - wire width 4 $5\r21__data_o$next[3:0]$11217 - attribute \src "libresoc.v:182475.3-182514.6" - wire width 4 $5\src11__data_o$next[3:0]$11160 - attribute \src "libresoc.v:182572.3-182611.6" - wire width 4 $5\src21__data_o$next[3:0]$11175 - attribute \src "libresoc.v:182642.3-182681.6" - wire width 4 $5\src31__data_o$next[3:0]$11189 - attribute \src "libresoc.v:182712.3-182751.6" - wire width 4 $6\r1__data_o$next[3:0]$11204 - attribute \src "libresoc.v:182782.3-182821.6" - wire width 4 $6\r21__data_o$next[3:0]$11218 - attribute \src "libresoc.v:182475.3-182514.6" - wire width 4 $6\src11__data_o$next[3:0]$11161 - attribute \src "libresoc.v:182572.3-182611.6" - wire width 4 $6\src21__data_o$next[3:0]$11176 - attribute \src "libresoc.v:182642.3-182681.6" - wire width 4 $6\src31__data_o$next[3:0]$11190 - attribute \src "libresoc.v:182458.17-182458.104" - wire $not$libresoc.v:182458$11143_Y - attribute \src "libresoc.v:182459.18-182459.105" - wire $not$libresoc.v:182459$11144_Y - attribute \src "libresoc.v:182460.17-182460.100" - wire $not$libresoc.v:182460$11145_Y - attribute \src "libresoc.v:182461.17-182461.103" - wire $not$libresoc.v:182461$11146_Y - attribute \src "libresoc.v:182462.17-182462.103" - wire $not$libresoc.v:182462$11147_Y + attribute \src "libresoc.v:176907.3-176946.6" + wire width 4 $5\r1__data_o$next[3:0]$10906 + attribute \src "libresoc.v:176977.3-177016.6" + wire width 4 $5\r21__data_o$next[3:0]$10920 + attribute \src "libresoc.v:176670.3-176709.6" + wire width 4 $5\src11__data_o$next[3:0]$10863 + attribute \src "libresoc.v:176767.3-176806.6" + wire width 4 $5\src21__data_o$next[3:0]$10878 + attribute \src "libresoc.v:176837.3-176876.6" + wire width 4 $5\src31__data_o$next[3:0]$10892 + attribute \src "libresoc.v:176907.3-176946.6" + wire width 4 $6\r1__data_o$next[3:0]$10907 + attribute \src "libresoc.v:176977.3-177016.6" + wire width 4 $6\r21__data_o$next[3:0]$10921 + attribute \src "libresoc.v:176670.3-176709.6" + wire width 4 $6\src11__data_o$next[3:0]$10864 + attribute \src "libresoc.v:176767.3-176806.6" + wire width 4 $6\src21__data_o$next[3:0]$10879 + attribute \src "libresoc.v:176837.3-176876.6" + wire width 4 $6\src31__data_o$next[3:0]$10893 + attribute \src "libresoc.v:176653.17-176653.104" + wire $not$libresoc.v:176653$10846_Y + attribute \src "libresoc.v:176654.18-176654.105" + wire $not$libresoc.v:176654$10847_Y + attribute \src "libresoc.v:176655.17-176655.100" + wire $not$libresoc.v:176655$10848_Y + attribute \src "libresoc.v:176656.17-176656.103" + wire $not$libresoc.v:176656$10849_Y + attribute \src "libresoc.v:176657.17-176657.103" + wire $not$libresoc.v:176657$10850_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -373612,9 +364157,9 @@ module \reg_1 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest11__data_i @@ -373624,7 +364169,7 @@ module \reg_1 wire width 4 input 11 \dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest21__wen - attribute \src "libresoc.v:182382.7-182382.15" + attribute \src "libresoc.v:176577.7-176577.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 12 \r1__data_o @@ -373675,152 +364220,152 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182458$11143 + cell $not $not$libresoc.v:176653$10846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:182458$11143_Y + connect \Y $not$libresoc.v:176653$10846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182459$11144 + cell $not $not$libresoc.v:176654$10847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:182459$11144_Y + connect \Y $not$libresoc.v:176654$10847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182460$11145 + cell $not $not$libresoc.v:176655$10848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182460$11145_Y + connect \Y $not$libresoc.v:176655$10848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182461$11146 + cell $not $not$libresoc.v:176656$10849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182461$11146_Y + connect \Y $not$libresoc.v:176656$10849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182462$11147 + cell $not $not$libresoc.v:176657$10850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182462$11147_Y + connect \Y $not$libresoc.v:176657$10850_Y end - attribute \src "libresoc.v:182382.7-182382.20" - process $proc$libresoc.v:182382$11225 + attribute \src "libresoc.v:176577.7-176577.20" + process $proc$libresoc.v:176577$10928 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182407.13-182407.30" - process $proc$libresoc.v:182407$11226 + attribute \src "libresoc.v:176602.13-176602.30" + process $proc$libresoc.v:176602$10929 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end - attribute \src "libresoc.v:182414.13-182414.31" - process $proc$libresoc.v:182414$11227 + attribute \src "libresoc.v:176609.13-176609.31" + process $proc$libresoc.v:176609$10930 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end - attribute \src "libresoc.v:182420.13-182420.25" - process $proc$libresoc.v:182420$11228 + attribute \src "libresoc.v:176615.13-176615.25" + process $proc$libresoc.v:176615$10931 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:182425.13-182425.33" - process $proc$libresoc.v:182425$11229 + attribute \src "libresoc.v:176620.13-176620.33" + process $proc$libresoc.v:176620$10932 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end - attribute \src "libresoc.v:182432.13-182432.33" - process $proc$libresoc.v:182432$11230 + attribute \src "libresoc.v:176627.13-176627.33" + process $proc$libresoc.v:176627$10933 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end - attribute \src "libresoc.v:182439.13-182439.33" - process $proc$libresoc.v:182439$11231 + attribute \src "libresoc.v:176634.13-176634.33" + process $proc$libresoc.v:176634$10934 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end - attribute \src "libresoc.v:182463.3-182464.25" - process $proc$libresoc.v:182463$11148 + attribute \src "libresoc.v:176658.3-176659.25" + process $proc$libresoc.v:176658$10851 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:182465.3-182466.39" - process $proc$libresoc.v:182465$11149 + attribute \src "libresoc.v:176660.3-176661.39" + process $proc$libresoc.v:176660$10852 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end - attribute \src "libresoc.v:182467.3-182468.37" - process $proc$libresoc.v:182467$11150 + attribute \src "libresoc.v:176662.3-176663.37" + process $proc$libresoc.v:176662$10853 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end - attribute \src "libresoc.v:182469.3-182470.43" - process $proc$libresoc.v:182469$11151 + attribute \src "libresoc.v:176664.3-176665.43" + process $proc$libresoc.v:176664$10854 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end - attribute \src "libresoc.v:182471.3-182472.43" - process $proc$libresoc.v:182471$11152 + attribute \src "libresoc.v:176666.3-176667.43" + process $proc$libresoc.v:176666$10855 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end - attribute \src "libresoc.v:182473.3-182474.43" - process $proc$libresoc.v:182473$11153 + attribute \src "libresoc.v:176668.3-176669.43" + process $proc$libresoc.v:176668$10856 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end - attribute \src "libresoc.v:182475.3-182514.6" - process $proc$libresoc.v:182475$11154 + attribute \src "libresoc.v:176670.3-176709.6" + process $proc$libresoc.v:176670$10857 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[3:0]$11155 $6\src11__data_o$next[3:0]$11161 - attribute \src "libresoc.v:182476.5-182476.29" + assign $0\src11__data_o$next[3:0]$10858 $6\src11__data_o$next[3:0]$10864 + attribute \src "libresoc.v:176671.5-176671.29" switch \initial - attribute \src "libresoc.v:182476.9-182476.17" + attribute \src "libresoc.v:176671.9-176671.17" case 1'1 case end @@ -373832,66 +364377,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[3:0]$11156 $5\src11__data_o$next[3:0]$11160 + assign $1\src11__data_o$next[3:0]$10859 $5\src11__data_o$next[3:0]$10863 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[3:0]$11157 \dest11__data_i + assign $2\src11__data_o$next[3:0]$10860 \dest11__data_i case - assign $2\src11__data_o$next[3:0]$11157 4'0000 + assign $2\src11__data_o$next[3:0]$10860 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[3:0]$11158 \dest21__data_i + assign $3\src11__data_o$next[3:0]$10861 \dest21__data_i case - assign $3\src11__data_o$next[3:0]$11158 $2\src11__data_o$next[3:0]$11157 + assign $3\src11__data_o$next[3:0]$10861 $2\src11__data_o$next[3:0]$10860 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[3:0]$11159 \w1__data_i + assign $4\src11__data_o$next[3:0]$10862 \w1__data_i case - assign $4\src11__data_o$next[3:0]$11159 $3\src11__data_o$next[3:0]$11158 + assign $4\src11__data_o$next[3:0]$10862 $3\src11__data_o$next[3:0]$10861 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[3:0]$11160 \reg + assign $5\src11__data_o$next[3:0]$10863 \reg case - assign $5\src11__data_o$next[3:0]$11160 $4\src11__data_o$next[3:0]$11159 + assign $5\src11__data_o$next[3:0]$10863 $4\src11__data_o$next[3:0]$10862 end case - assign $1\src11__data_o$next[3:0]$11156 4'0000 + assign $1\src11__data_o$next[3:0]$10859 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[3:0]$11161 4'0000 + assign $6\src11__data_o$next[3:0]$10864 4'0000 case - assign $6\src11__data_o$next[3:0]$11161 $1\src11__data_o$next[3:0]$11156 + assign $6\src11__data_o$next[3:0]$10864 $1\src11__data_o$next[3:0]$10859 end sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$11155 + update \src11__data_o$next $0\src11__data_o$next[3:0]$10858 end - attribute \src "libresoc.v:182515.3-182544.6" - process $proc$libresoc.v:182515$11162 + attribute \src "libresoc.v:176710.3-176739.6" + process $proc$libresoc.v:176710$10865 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182516.5-182516.29" + attribute \src "libresoc.v:176711.5-176711.29" switch \initial - attribute \src "libresoc.v:182516.9-182516.17" + attribute \src "libresoc.v:176711.9-176711.17" case 1'1 case end @@ -373937,17 +364482,17 @@ module \reg_1 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:182545.3-182571.6" - process $proc$libresoc.v:182545$11163 + attribute \src "libresoc.v:176740.3-176766.6" + process $proc$libresoc.v:176740$10866 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11164 $4\reg$next[3:0]$11168 - attribute \src "libresoc.v:182546.5-182546.29" + assign $0\reg$next[3:0]$10867 $4\reg$next[3:0]$10871 + attribute \src "libresoc.v:176741.5-176741.29" switch \initial - attribute \src "libresoc.v:182546.9-182546.17" + attribute \src "libresoc.v:176741.9-176741.17" case 1'1 case end @@ -373956,49 +364501,49 @@ module \reg_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11165 \dest11__data_i + assign $1\reg$next[3:0]$10868 \dest11__data_i case - assign $1\reg$next[3:0]$11165 \reg + assign $1\reg$next[3:0]$10868 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11166 \dest21__data_i + assign $2\reg$next[3:0]$10869 \dest21__data_i case - assign $2\reg$next[3:0]$11166 $1\reg$next[3:0]$11165 + assign $2\reg$next[3:0]$10869 $1\reg$next[3:0]$10868 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11167 \w1__data_i + assign $3\reg$next[3:0]$10870 \w1__data_i case - assign $3\reg$next[3:0]$11167 $2\reg$next[3:0]$11166 + assign $3\reg$next[3:0]$10870 $2\reg$next[3:0]$10869 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11168 4'0000 + assign $4\reg$next[3:0]$10871 4'0000 case - assign $4\reg$next[3:0]$11168 $3\reg$next[3:0]$11167 + assign $4\reg$next[3:0]$10871 $3\reg$next[3:0]$10870 end sync always - update \reg$next $0\reg$next[3:0]$11164 + update \reg$next $0\reg$next[3:0]$10867 end - attribute \src "libresoc.v:182572.3-182611.6" - process $proc$libresoc.v:182572$11169 + attribute \src "libresoc.v:176767.3-176806.6" + process $proc$libresoc.v:176767$10872 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[3:0]$11170 $6\src21__data_o$next[3:0]$11176 - attribute \src "libresoc.v:182573.5-182573.29" + assign $0\src21__data_o$next[3:0]$10873 $6\src21__data_o$next[3:0]$10879 + attribute \src "libresoc.v:176768.5-176768.29" switch \initial - attribute \src "libresoc.v:182573.9-182573.17" + attribute \src "libresoc.v:176768.9-176768.17" case 1'1 case end @@ -374010,66 +364555,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[3:0]$11171 $5\src21__data_o$next[3:0]$11175 + assign $1\src21__data_o$next[3:0]$10874 $5\src21__data_o$next[3:0]$10878 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[3:0]$11172 \dest11__data_i + assign $2\src21__data_o$next[3:0]$10875 \dest11__data_i case - assign $2\src21__data_o$next[3:0]$11172 4'0000 + assign $2\src21__data_o$next[3:0]$10875 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[3:0]$11173 \dest21__data_i + assign $3\src21__data_o$next[3:0]$10876 \dest21__data_i case - assign $3\src21__data_o$next[3:0]$11173 $2\src21__data_o$next[3:0]$11172 + assign $3\src21__data_o$next[3:0]$10876 $2\src21__data_o$next[3:0]$10875 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[3:0]$11174 \w1__data_i + assign $4\src21__data_o$next[3:0]$10877 \w1__data_i case - assign $4\src21__data_o$next[3:0]$11174 $3\src21__data_o$next[3:0]$11173 + assign $4\src21__data_o$next[3:0]$10877 $3\src21__data_o$next[3:0]$10876 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[3:0]$11175 \reg + assign $5\src21__data_o$next[3:0]$10878 \reg case - assign $5\src21__data_o$next[3:0]$11175 $4\src21__data_o$next[3:0]$11174 + assign $5\src21__data_o$next[3:0]$10878 $4\src21__data_o$next[3:0]$10877 end case - assign $1\src21__data_o$next[3:0]$11171 4'0000 + assign $1\src21__data_o$next[3:0]$10874 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[3:0]$11176 4'0000 + assign $6\src21__data_o$next[3:0]$10879 4'0000 case - assign $6\src21__data_o$next[3:0]$11176 $1\src21__data_o$next[3:0]$11171 + assign $6\src21__data_o$next[3:0]$10879 $1\src21__data_o$next[3:0]$10874 end sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$11170 + update \src21__data_o$next $0\src21__data_o$next[3:0]$10873 end - attribute \src "libresoc.v:182612.3-182641.6" - process $proc$libresoc.v:182612$11177 + attribute \src "libresoc.v:176807.3-176836.6" + process $proc$libresoc.v:176807$10880 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11178 $1\wr_detect$4[0:0]$11179 - attribute \src "libresoc.v:182613.5-182613.29" + assign $0\wr_detect$4[0:0]$10881 $1\wr_detect$4[0:0]$10882 + attribute \src "libresoc.v:176808.5-176808.29" switch \initial - attribute \src "libresoc.v:182613.9-182613.17" + attribute \src "libresoc.v:176808.9-176808.17" case 1'1 case end @@ -374081,49 +364626,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11179 $4\wr_detect$4[0:0]$11182 + assign $1\wr_detect$4[0:0]$10882 $4\wr_detect$4[0:0]$10885 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11180 1'1 + assign $2\wr_detect$4[0:0]$10883 1'1 case - assign $2\wr_detect$4[0:0]$11180 1'0 + assign $2\wr_detect$4[0:0]$10883 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11181 1'1 + assign $3\wr_detect$4[0:0]$10884 1'1 case - assign $3\wr_detect$4[0:0]$11181 $2\wr_detect$4[0:0]$11180 + assign $3\wr_detect$4[0:0]$10884 $2\wr_detect$4[0:0]$10883 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11182 1'1 + assign $4\wr_detect$4[0:0]$10885 1'1 case - assign $4\wr_detect$4[0:0]$11182 $3\wr_detect$4[0:0]$11181 + assign $4\wr_detect$4[0:0]$10885 $3\wr_detect$4[0:0]$10884 end case - assign $1\wr_detect$4[0:0]$11179 1'0 + assign $1\wr_detect$4[0:0]$10882 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11178 + update \wr_detect$4 $0\wr_detect$4[0:0]$10881 end - attribute \src "libresoc.v:182642.3-182681.6" - process $proc$libresoc.v:182642$11183 + attribute \src "libresoc.v:176837.3-176876.6" + process $proc$libresoc.v:176837$10886 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[3:0]$11184 $6\src31__data_o$next[3:0]$11190 - attribute \src "libresoc.v:182643.5-182643.29" + assign $0\src31__data_o$next[3:0]$10887 $6\src31__data_o$next[3:0]$10893 + attribute \src "libresoc.v:176838.5-176838.29" switch \initial - attribute \src "libresoc.v:182643.9-182643.17" + attribute \src "libresoc.v:176838.9-176838.17" case 1'1 case end @@ -374135,66 +364680,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[3:0]$11185 $5\src31__data_o$next[3:0]$11189 + assign $1\src31__data_o$next[3:0]$10888 $5\src31__data_o$next[3:0]$10892 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[3:0]$11186 \dest11__data_i + assign $2\src31__data_o$next[3:0]$10889 \dest11__data_i case - assign $2\src31__data_o$next[3:0]$11186 4'0000 + assign $2\src31__data_o$next[3:0]$10889 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[3:0]$11187 \dest21__data_i + assign $3\src31__data_o$next[3:0]$10890 \dest21__data_i case - assign $3\src31__data_o$next[3:0]$11187 $2\src31__data_o$next[3:0]$11186 + assign $3\src31__data_o$next[3:0]$10890 $2\src31__data_o$next[3:0]$10889 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[3:0]$11188 \w1__data_i + assign $4\src31__data_o$next[3:0]$10891 \w1__data_i case - assign $4\src31__data_o$next[3:0]$11188 $3\src31__data_o$next[3:0]$11187 + assign $4\src31__data_o$next[3:0]$10891 $3\src31__data_o$next[3:0]$10890 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[3:0]$11189 \reg + assign $5\src31__data_o$next[3:0]$10892 \reg case - assign $5\src31__data_o$next[3:0]$11189 $4\src31__data_o$next[3:0]$11188 + assign $5\src31__data_o$next[3:0]$10892 $4\src31__data_o$next[3:0]$10891 end case - assign $1\src31__data_o$next[3:0]$11185 4'0000 + assign $1\src31__data_o$next[3:0]$10888 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[3:0]$11190 4'0000 + assign $6\src31__data_o$next[3:0]$10893 4'0000 case - assign $6\src31__data_o$next[3:0]$11190 $1\src31__data_o$next[3:0]$11185 + assign $6\src31__data_o$next[3:0]$10893 $1\src31__data_o$next[3:0]$10888 end sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$11184 + update \src31__data_o$next $0\src31__data_o$next[3:0]$10887 end - attribute \src "libresoc.v:182682.3-182711.6" - process $proc$libresoc.v:182682$11191 + attribute \src "libresoc.v:176877.3-176906.6" + process $proc$libresoc.v:176877$10894 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11192 $1\wr_detect$7[0:0]$11193 - attribute \src "libresoc.v:182683.5-182683.29" + assign $0\wr_detect$7[0:0]$10895 $1\wr_detect$7[0:0]$10896 + attribute \src "libresoc.v:176878.5-176878.29" switch \initial - attribute \src "libresoc.v:182683.9-182683.17" + attribute \src "libresoc.v:176878.9-176878.17" case 1'1 case end @@ -374206,49 +364751,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11193 $4\wr_detect$7[0:0]$11196 + assign $1\wr_detect$7[0:0]$10896 $4\wr_detect$7[0:0]$10899 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11194 1'1 + assign $2\wr_detect$7[0:0]$10897 1'1 case - assign $2\wr_detect$7[0:0]$11194 1'0 + assign $2\wr_detect$7[0:0]$10897 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11195 1'1 + assign $3\wr_detect$7[0:0]$10898 1'1 case - assign $3\wr_detect$7[0:0]$11195 $2\wr_detect$7[0:0]$11194 + assign $3\wr_detect$7[0:0]$10898 $2\wr_detect$7[0:0]$10897 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11196 1'1 + assign $4\wr_detect$7[0:0]$10899 1'1 case - assign $4\wr_detect$7[0:0]$11196 $3\wr_detect$7[0:0]$11195 + assign $4\wr_detect$7[0:0]$10899 $3\wr_detect$7[0:0]$10898 end case - assign $1\wr_detect$7[0:0]$11193 1'0 + assign $1\wr_detect$7[0:0]$10896 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11192 + update \wr_detect$7 $0\wr_detect$7[0:0]$10895 end - attribute \src "libresoc.v:182712.3-182751.6" - process $proc$libresoc.v:182712$11197 + attribute \src "libresoc.v:176907.3-176946.6" + process $proc$libresoc.v:176907$10900 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[3:0]$11198 $6\r1__data_o$next[3:0]$11204 - attribute \src "libresoc.v:182713.5-182713.29" + assign $0\r1__data_o$next[3:0]$10901 $6\r1__data_o$next[3:0]$10907 + attribute \src "libresoc.v:176908.5-176908.29" switch \initial - attribute \src "libresoc.v:182713.9-182713.17" + attribute \src "libresoc.v:176908.9-176908.17" case 1'1 case end @@ -374260,66 +364805,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[3:0]$11199 $5\r1__data_o$next[3:0]$11203 + assign $1\r1__data_o$next[3:0]$10902 $5\r1__data_o$next[3:0]$10906 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[3:0]$11200 \dest11__data_i + assign $2\r1__data_o$next[3:0]$10903 \dest11__data_i case - assign $2\r1__data_o$next[3:0]$11200 4'0000 + assign $2\r1__data_o$next[3:0]$10903 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[3:0]$11201 \dest21__data_i + assign $3\r1__data_o$next[3:0]$10904 \dest21__data_i case - assign $3\r1__data_o$next[3:0]$11201 $2\r1__data_o$next[3:0]$11200 + assign $3\r1__data_o$next[3:0]$10904 $2\r1__data_o$next[3:0]$10903 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[3:0]$11202 \w1__data_i + assign $4\r1__data_o$next[3:0]$10905 \w1__data_i case - assign $4\r1__data_o$next[3:0]$11202 $3\r1__data_o$next[3:0]$11201 + assign $4\r1__data_o$next[3:0]$10905 $3\r1__data_o$next[3:0]$10904 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[3:0]$11203 \reg + assign $5\r1__data_o$next[3:0]$10906 \reg case - assign $5\r1__data_o$next[3:0]$11203 $4\r1__data_o$next[3:0]$11202 + assign $5\r1__data_o$next[3:0]$10906 $4\r1__data_o$next[3:0]$10905 end case - assign $1\r1__data_o$next[3:0]$11199 4'0000 + assign $1\r1__data_o$next[3:0]$10902 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[3:0]$11204 4'0000 + assign $6\r1__data_o$next[3:0]$10907 4'0000 case - assign $6\r1__data_o$next[3:0]$11204 $1\r1__data_o$next[3:0]$11199 + assign $6\r1__data_o$next[3:0]$10907 $1\r1__data_o$next[3:0]$10902 end sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$11198 + update \r1__data_o$next $0\r1__data_o$next[3:0]$10901 end - attribute \src "libresoc.v:182752.3-182781.6" - process $proc$libresoc.v:182752$11205 + attribute \src "libresoc.v:176947.3-176976.6" + process $proc$libresoc.v:176947$10908 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11206 $1\wr_detect$10[0:0]$11207 - attribute \src "libresoc.v:182753.5-182753.29" + assign $0\wr_detect$10[0:0]$10909 $1\wr_detect$10[0:0]$10910 + attribute \src "libresoc.v:176948.5-176948.29" switch \initial - attribute \src "libresoc.v:182753.9-182753.17" + attribute \src "libresoc.v:176948.9-176948.17" case 1'1 case end @@ -374331,49 +364876,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11207 $4\wr_detect$10[0:0]$11210 + assign $1\wr_detect$10[0:0]$10910 $4\wr_detect$10[0:0]$10913 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11208 1'1 + assign $2\wr_detect$10[0:0]$10911 1'1 case - assign $2\wr_detect$10[0:0]$11208 1'0 + assign $2\wr_detect$10[0:0]$10911 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11209 1'1 + assign $3\wr_detect$10[0:0]$10912 1'1 case - assign $3\wr_detect$10[0:0]$11209 $2\wr_detect$10[0:0]$11208 + assign $3\wr_detect$10[0:0]$10912 $2\wr_detect$10[0:0]$10911 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11210 1'1 + assign $4\wr_detect$10[0:0]$10913 1'1 case - assign $4\wr_detect$10[0:0]$11210 $3\wr_detect$10[0:0]$11209 + assign $4\wr_detect$10[0:0]$10913 $3\wr_detect$10[0:0]$10912 end case - assign $1\wr_detect$10[0:0]$11207 1'0 + assign $1\wr_detect$10[0:0]$10910 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11206 + update \wr_detect$10 $0\wr_detect$10[0:0]$10909 end - attribute \src "libresoc.v:182782.3-182821.6" - process $proc$libresoc.v:182782$11211 + attribute \src "libresoc.v:176977.3-177016.6" + process $proc$libresoc.v:176977$10914 assign { } { } assign { } { } assign { } { } - assign $0\r21__data_o$next[3:0]$11212 $6\r21__data_o$next[3:0]$11218 - attribute \src "libresoc.v:182783.5-182783.29" + assign $0\r21__data_o$next[3:0]$10915 $6\r21__data_o$next[3:0]$10921 + attribute \src "libresoc.v:176978.5-176978.29" switch \initial - attribute \src "libresoc.v:182783.9-182783.17" + attribute \src "libresoc.v:176978.9-176978.17" case 1'1 case end @@ -374385,66 +364930,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r21__data_o$next[3:0]$11213 $5\r21__data_o$next[3:0]$11217 + assign $1\r21__data_o$next[3:0]$10916 $5\r21__data_o$next[3:0]$10920 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r21__data_o$next[3:0]$11214 \dest11__data_i + assign $2\r21__data_o$next[3:0]$10917 \dest11__data_i case - assign $2\r21__data_o$next[3:0]$11214 4'0000 + assign $2\r21__data_o$next[3:0]$10917 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r21__data_o$next[3:0]$11215 \dest21__data_i + assign $3\r21__data_o$next[3:0]$10918 \dest21__data_i case - assign $3\r21__data_o$next[3:0]$11215 $2\r21__data_o$next[3:0]$11214 + assign $3\r21__data_o$next[3:0]$10918 $2\r21__data_o$next[3:0]$10917 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r21__data_o$next[3:0]$11216 \w1__data_i + assign $4\r21__data_o$next[3:0]$10919 \w1__data_i case - assign $4\r21__data_o$next[3:0]$11216 $3\r21__data_o$next[3:0]$11215 + assign $4\r21__data_o$next[3:0]$10919 $3\r21__data_o$next[3:0]$10918 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r21__data_o$next[3:0]$11217 \reg + assign $5\r21__data_o$next[3:0]$10920 \reg case - assign $5\r21__data_o$next[3:0]$11217 $4\r21__data_o$next[3:0]$11216 + assign $5\r21__data_o$next[3:0]$10920 $4\r21__data_o$next[3:0]$10919 end case - assign $1\r21__data_o$next[3:0]$11213 4'0000 + assign $1\r21__data_o$next[3:0]$10916 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r21__data_o$next[3:0]$11218 4'0000 + assign $6\r21__data_o$next[3:0]$10921 4'0000 case - assign $6\r21__data_o$next[3:0]$11218 $1\r21__data_o$next[3:0]$11213 + assign $6\r21__data_o$next[3:0]$10921 $1\r21__data_o$next[3:0]$10916 end sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$11212 + update \r21__data_o$next $0\r21__data_o$next[3:0]$10915 end - attribute \src "libresoc.v:182822.3-182851.6" - process $proc$libresoc.v:182822$11219 + attribute \src "libresoc.v:177017.3-177046.6" + process $proc$libresoc.v:177017$10922 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11220 $1\wr_detect$13[0:0]$11221 - attribute \src "libresoc.v:182823.5-182823.29" + assign $0\wr_detect$13[0:0]$10923 $1\wr_detect$13[0:0]$10924 + attribute \src "libresoc.v:177018.5-177018.29" switch \initial - attribute \src "libresoc.v:182823.9-182823.17" + attribute \src "libresoc.v:177018.9-177018.17" case 1'1 case end @@ -374456,205 +365001,205 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11221 $4\wr_detect$13[0:0]$11224 + assign $1\wr_detect$13[0:0]$10924 $4\wr_detect$13[0:0]$10927 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11222 1'1 + assign $2\wr_detect$13[0:0]$10925 1'1 case - assign $2\wr_detect$13[0:0]$11222 1'0 + assign $2\wr_detect$13[0:0]$10925 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11223 1'1 + assign $3\wr_detect$13[0:0]$10926 1'1 case - assign $3\wr_detect$13[0:0]$11223 $2\wr_detect$13[0:0]$11222 + assign $3\wr_detect$13[0:0]$10926 $2\wr_detect$13[0:0]$10925 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11224 1'1 + assign $4\wr_detect$13[0:0]$10927 1'1 case - assign $4\wr_detect$13[0:0]$11224 $3\wr_detect$13[0:0]$11223 + assign $4\wr_detect$13[0:0]$10927 $3\wr_detect$13[0:0]$10926 end case - assign $1\wr_detect$13[0:0]$11221 1'0 + assign $1\wr_detect$13[0:0]$10924 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11220 + update \wr_detect$13 $0\wr_detect$13[0:0]$10923 end - connect \$9 $not$libresoc.v:182458$11143_Y - connect \$12 $not$libresoc.v:182459$11144_Y - connect \$1 $not$libresoc.v:182460$11145_Y - connect \$3 $not$libresoc.v:182461$11146_Y - connect \$6 $not$libresoc.v:182462$11147_Y + connect \$9 $not$libresoc.v:176653$10846_Y + connect \$12 $not$libresoc.v:176654$10847_Y + connect \$1 $not$libresoc.v:176655$10848_Y + connect \$3 $not$libresoc.v:176656$10849_Y + connect \$6 $not$libresoc.v:176657$10850_Y end -attribute \src "libresoc.v:182856.1-183301.10" +attribute \src "libresoc.v:177051.1-177496.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" module \reg_1$133 - attribute \src "libresoc.v:182857.7-182857.20" + attribute \src "libresoc.v:177052.7-177052.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183186.3-183231.6" - wire width 2 $0\r1__data_o$next[1:0]$11284 - attribute \src "libresoc.v:182932.3-182933.37" + attribute \src "libresoc.v:177381.3-177426.6" + wire width 2 $0\r1__data_o$next[1:0]$10987 + attribute \src "libresoc.v:177127.3-177128.37" wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:183268.3-183300.6" - wire width 2 $0\reg$next[1:0]$11300 - attribute \src "libresoc.v:182930.3-182931.25" + attribute \src "libresoc.v:177463.3-177495.6" + wire width 2 $0\reg$next[1:0]$11003 + attribute \src "libresoc.v:177125.3-177126.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:182940.3-182985.6" - wire width 2 $0\src11__data_o$next[1:0]$11242 - attribute \src "libresoc.v:182938.3-182939.43" + attribute \src "libresoc.v:177135.3-177180.6" + wire width 2 $0\src11__data_o$next[1:0]$10945 + attribute \src "libresoc.v:177133.3-177134.43" wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:183022.3-183067.6" - wire width 2 $0\src21__data_o$next[1:0]$11252 - attribute \src "libresoc.v:182936.3-182937.43" + attribute \src "libresoc.v:177217.3-177262.6" + wire width 2 $0\src21__data_o$next[1:0]$10955 + attribute \src "libresoc.v:177131.3-177132.43" wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:183104.3-183149.6" - wire width 2 $0\src31__data_o$next[1:0]$11268 - attribute \src "libresoc.v:182934.3-182935.43" + attribute \src "libresoc.v:177299.3-177344.6" + wire width 2 $0\src31__data_o$next[1:0]$10971 + attribute \src "libresoc.v:177129.3-177130.43" wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:183232.3-183267.6" - wire $0\wr_detect$10[0:0]$11293 - attribute \src "libresoc.v:183068.3-183103.6" - wire $0\wr_detect$4[0:0]$11261 - attribute \src "libresoc.v:183150.3-183185.6" - wire $0\wr_detect$7[0:0]$11277 - attribute \src "libresoc.v:182986.3-183021.6" + attribute \src "libresoc.v:177427.3-177462.6" + wire $0\wr_detect$10[0:0]$10996 + attribute \src "libresoc.v:177263.3-177298.6" + wire $0\wr_detect$4[0:0]$10964 + attribute \src "libresoc.v:177345.3-177380.6" + wire $0\wr_detect$7[0:0]$10980 + attribute \src "libresoc.v:177181.3-177216.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:183186.3-183231.6" - wire width 2 $1\r1__data_o$next[1:0]$11285 - attribute \src "libresoc.v:182884.13-182884.30" + attribute \src "libresoc.v:177381.3-177426.6" + wire width 2 $1\r1__data_o$next[1:0]$10988 + attribute \src "libresoc.v:177079.13-177079.30" wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:183268.3-183300.6" - wire width 2 $1\reg$next[1:0]$11301 - attribute \src "libresoc.v:182890.13-182890.25" + attribute \src "libresoc.v:177463.3-177495.6" + wire width 2 $1\reg$next[1:0]$11004 + attribute \src "libresoc.v:177085.13-177085.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:182940.3-182985.6" - wire width 2 $1\src11__data_o$next[1:0]$11243 - attribute \src "libresoc.v:182895.13-182895.33" + attribute \src "libresoc.v:177135.3-177180.6" + wire width 2 $1\src11__data_o$next[1:0]$10946 + attribute \src "libresoc.v:177090.13-177090.33" wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:183022.3-183067.6" - wire width 2 $1\src21__data_o$next[1:0]$11253 - attribute \src "libresoc.v:182902.13-182902.33" + attribute \src "libresoc.v:177217.3-177262.6" + wire width 2 $1\src21__data_o$next[1:0]$10956 + attribute \src "libresoc.v:177097.13-177097.33" wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:183104.3-183149.6" - wire width 2 $1\src31__data_o$next[1:0]$11269 - attribute \src "libresoc.v:182909.13-182909.33" + attribute \src "libresoc.v:177299.3-177344.6" + wire width 2 $1\src31__data_o$next[1:0]$10972 + attribute \src "libresoc.v:177104.13-177104.33" wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:183232.3-183267.6" - wire $1\wr_detect$10[0:0]$11294 - attribute \src "libresoc.v:183068.3-183103.6" - wire $1\wr_detect$4[0:0]$11262 - attribute \src "libresoc.v:183150.3-183185.6" - wire $1\wr_detect$7[0:0]$11278 - attribute \src "libresoc.v:182986.3-183021.6" + attribute \src "libresoc.v:177427.3-177462.6" + wire $1\wr_detect$10[0:0]$10997 + attribute \src "libresoc.v:177263.3-177298.6" + wire $1\wr_detect$4[0:0]$10965 + attribute \src "libresoc.v:177345.3-177380.6" + wire $1\wr_detect$7[0:0]$10981 + attribute \src "libresoc.v:177181.3-177216.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:183186.3-183231.6" - wire width 2 $2\r1__data_o$next[1:0]$11286 - attribute \src "libresoc.v:183268.3-183300.6" - wire width 2 $2\reg$next[1:0]$11302 - attribute \src "libresoc.v:182940.3-182985.6" - wire width 2 $2\src11__data_o$next[1:0]$11244 - attribute \src "libresoc.v:183022.3-183067.6" - wire width 2 $2\src21__data_o$next[1:0]$11254 - attribute \src "libresoc.v:183104.3-183149.6" - wire width 2 $2\src31__data_o$next[1:0]$11270 - attribute \src "libresoc.v:183232.3-183267.6" - wire $2\wr_detect$10[0:0]$11295 - attribute \src "libresoc.v:183068.3-183103.6" - wire $2\wr_detect$4[0:0]$11263 - attribute \src "libresoc.v:183150.3-183185.6" - wire $2\wr_detect$7[0:0]$11279 - attribute \src "libresoc.v:182986.3-183021.6" + attribute \src "libresoc.v:177381.3-177426.6" + wire width 2 $2\r1__data_o$next[1:0]$10989 + attribute \src "libresoc.v:177463.3-177495.6" + wire width 2 $2\reg$next[1:0]$11005 + attribute \src "libresoc.v:177135.3-177180.6" + wire width 2 $2\src11__data_o$next[1:0]$10947 + attribute \src "libresoc.v:177217.3-177262.6" + wire width 2 $2\src21__data_o$next[1:0]$10957 + attribute \src "libresoc.v:177299.3-177344.6" + wire width 2 $2\src31__data_o$next[1:0]$10973 + attribute \src "libresoc.v:177427.3-177462.6" + wire $2\wr_detect$10[0:0]$10998 + attribute \src "libresoc.v:177263.3-177298.6" + wire $2\wr_detect$4[0:0]$10966 + attribute \src "libresoc.v:177345.3-177380.6" + wire $2\wr_detect$7[0:0]$10982 + attribute \src "libresoc.v:177181.3-177216.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:183186.3-183231.6" - wire width 2 $3\r1__data_o$next[1:0]$11287 - attribute \src "libresoc.v:183268.3-183300.6" - wire width 2 $3\reg$next[1:0]$11303 - attribute \src "libresoc.v:182940.3-182985.6" - wire width 2 $3\src11__data_o$next[1:0]$11245 - attribute \src "libresoc.v:183022.3-183067.6" - wire width 2 $3\src21__data_o$next[1:0]$11255 - attribute \src "libresoc.v:183104.3-183149.6" - wire width 2 $3\src31__data_o$next[1:0]$11271 - attribute \src "libresoc.v:183232.3-183267.6" - wire $3\wr_detect$10[0:0]$11296 - attribute \src "libresoc.v:183068.3-183103.6" - wire $3\wr_detect$4[0:0]$11264 - attribute \src "libresoc.v:183150.3-183185.6" - wire $3\wr_detect$7[0:0]$11280 - attribute \src "libresoc.v:182986.3-183021.6" + attribute \src "libresoc.v:177381.3-177426.6" + wire width 2 $3\r1__data_o$next[1:0]$10990 + attribute \src "libresoc.v:177463.3-177495.6" + wire width 2 $3\reg$next[1:0]$11006 + attribute \src "libresoc.v:177135.3-177180.6" + wire width 2 $3\src11__data_o$next[1:0]$10948 + attribute \src "libresoc.v:177217.3-177262.6" + wire width 2 $3\src21__data_o$next[1:0]$10958 + attribute \src "libresoc.v:177299.3-177344.6" + wire width 2 $3\src31__data_o$next[1:0]$10974 + attribute \src "libresoc.v:177427.3-177462.6" + wire $3\wr_detect$10[0:0]$10999 + attribute \src "libresoc.v:177263.3-177298.6" + wire $3\wr_detect$4[0:0]$10967 + attribute \src "libresoc.v:177345.3-177380.6" + wire $3\wr_detect$7[0:0]$10983 + attribute \src "libresoc.v:177181.3-177216.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:183186.3-183231.6" - wire width 2 $4\r1__data_o$next[1:0]$11288 - attribute \src "libresoc.v:183268.3-183300.6" - wire width 2 $4\reg$next[1:0]$11304 - attribute \src "libresoc.v:182940.3-182985.6" - wire width 2 $4\src11__data_o$next[1:0]$11246 - attribute \src "libresoc.v:183022.3-183067.6" - wire width 2 $4\src21__data_o$next[1:0]$11256 - attribute \src "libresoc.v:183104.3-183149.6" - wire width 2 $4\src31__data_o$next[1:0]$11272 - attribute \src "libresoc.v:183232.3-183267.6" - wire $4\wr_detect$10[0:0]$11297 - attribute \src "libresoc.v:183068.3-183103.6" - wire $4\wr_detect$4[0:0]$11265 - attribute \src "libresoc.v:183150.3-183185.6" - wire $4\wr_detect$7[0:0]$11281 - attribute \src "libresoc.v:182986.3-183021.6" + attribute \src "libresoc.v:177381.3-177426.6" + wire width 2 $4\r1__data_o$next[1:0]$10991 + attribute \src "libresoc.v:177463.3-177495.6" + wire width 2 $4\reg$next[1:0]$11007 + attribute \src "libresoc.v:177135.3-177180.6" + wire width 2 $4\src11__data_o$next[1:0]$10949 + attribute \src "libresoc.v:177217.3-177262.6" + wire width 2 $4\src21__data_o$next[1:0]$10959 + attribute \src "libresoc.v:177299.3-177344.6" + wire width 2 $4\src31__data_o$next[1:0]$10975 + attribute \src "libresoc.v:177427.3-177462.6" + wire $4\wr_detect$10[0:0]$11000 + attribute \src "libresoc.v:177263.3-177298.6" + wire $4\wr_detect$4[0:0]$10968 + attribute \src "libresoc.v:177345.3-177380.6" + wire $4\wr_detect$7[0:0]$10984 + attribute \src "libresoc.v:177181.3-177216.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:183186.3-183231.6" - wire width 2 $5\r1__data_o$next[1:0]$11289 - attribute \src "libresoc.v:183268.3-183300.6" - wire width 2 $5\reg$next[1:0]$11305 - attribute \src "libresoc.v:182940.3-182985.6" - wire width 2 $5\src11__data_o$next[1:0]$11247 - attribute \src "libresoc.v:183022.3-183067.6" - wire width 2 $5\src21__data_o$next[1:0]$11257 - attribute \src "libresoc.v:183104.3-183149.6" - wire width 2 $5\src31__data_o$next[1:0]$11273 - attribute \src "libresoc.v:183232.3-183267.6" - wire $5\wr_detect$10[0:0]$11298 - attribute \src "libresoc.v:183068.3-183103.6" - wire $5\wr_detect$4[0:0]$11266 - attribute \src "libresoc.v:183150.3-183185.6" - wire $5\wr_detect$7[0:0]$11282 - attribute \src "libresoc.v:182986.3-183021.6" + attribute \src "libresoc.v:177381.3-177426.6" + wire width 2 $5\r1__data_o$next[1:0]$10992 + attribute \src "libresoc.v:177463.3-177495.6" + wire width 2 $5\reg$next[1:0]$11008 + attribute \src "libresoc.v:177135.3-177180.6" + wire width 2 $5\src11__data_o$next[1:0]$10950 + attribute \src "libresoc.v:177217.3-177262.6" + wire width 2 $5\src21__data_o$next[1:0]$10960 + attribute \src "libresoc.v:177299.3-177344.6" + wire width 2 $5\src31__data_o$next[1:0]$10976 + attribute \src "libresoc.v:177427.3-177462.6" + wire $5\wr_detect$10[0:0]$11001 + attribute \src "libresoc.v:177263.3-177298.6" + wire $5\wr_detect$4[0:0]$10969 + attribute \src "libresoc.v:177345.3-177380.6" + wire $5\wr_detect$7[0:0]$10985 + attribute \src "libresoc.v:177181.3-177216.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:183186.3-183231.6" - wire width 2 $6\r1__data_o$next[1:0]$11290 - attribute \src "libresoc.v:182940.3-182985.6" - wire width 2 $6\src11__data_o$next[1:0]$11248 - attribute \src "libresoc.v:183022.3-183067.6" - wire width 2 $6\src21__data_o$next[1:0]$11258 - attribute \src "libresoc.v:183104.3-183149.6" - wire width 2 $6\src31__data_o$next[1:0]$11274 - attribute \src "libresoc.v:183186.3-183231.6" - wire width 2 $7\r1__data_o$next[1:0]$11291 - attribute \src "libresoc.v:182940.3-182985.6" - wire width 2 $7\src11__data_o$next[1:0]$11249 - attribute \src "libresoc.v:183022.3-183067.6" - wire width 2 $7\src21__data_o$next[1:0]$11259 - attribute \src "libresoc.v:183104.3-183149.6" - wire width 2 $7\src31__data_o$next[1:0]$11275 - attribute \src "libresoc.v:182926.17-182926.104" - wire $not$libresoc.v:182926$11232_Y - attribute \src "libresoc.v:182927.17-182927.100" - wire $not$libresoc.v:182927$11233_Y - attribute \src "libresoc.v:182928.17-182928.103" - wire $not$libresoc.v:182928$11234_Y - attribute \src "libresoc.v:182929.17-182929.103" - wire $not$libresoc.v:182929$11235_Y + attribute \src "libresoc.v:177381.3-177426.6" + wire width 2 $6\r1__data_o$next[1:0]$10993 + attribute \src "libresoc.v:177135.3-177180.6" + wire width 2 $6\src11__data_o$next[1:0]$10951 + attribute \src "libresoc.v:177217.3-177262.6" + wire width 2 $6\src21__data_o$next[1:0]$10961 + attribute \src "libresoc.v:177299.3-177344.6" + wire width 2 $6\src31__data_o$next[1:0]$10977 + attribute \src "libresoc.v:177381.3-177426.6" + wire width 2 $7\r1__data_o$next[1:0]$10994 + attribute \src "libresoc.v:177135.3-177180.6" + wire width 2 $7\src11__data_o$next[1:0]$10952 + attribute \src "libresoc.v:177217.3-177262.6" + wire width 2 $7\src21__data_o$next[1:0]$10962 + attribute \src "libresoc.v:177299.3-177344.6" + wire width 2 $7\src31__data_o$next[1:0]$10978 + attribute \src "libresoc.v:177121.17-177121.104" + wire $not$libresoc.v:177121$10935_Y + attribute \src "libresoc.v:177122.17-177122.100" + wire $not$libresoc.v:177122$10936_Y + attribute \src "libresoc.v:177123.17-177123.103" + wire $not$libresoc.v:177123$10937_Y + attribute \src "libresoc.v:177124.17-177124.103" + wire $not$libresoc.v:177124$10938_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -374663,9 +365208,9 @@ module \reg_1$133 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest11__data_i @@ -374679,7 +365224,7 @@ module \reg_1$133 wire width 2 input 13 \dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest31__wen - attribute \src "libresoc.v:182857.7-182857.15" + attribute \src "libresoc.v:177052.7-177052.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r1__data_o @@ -374722,129 +365267,129 @@ module \reg_1$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182926$11232 + cell $not $not$libresoc.v:177121$10935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:182926$11232_Y + connect \Y $not$libresoc.v:177121$10935_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182927$11233 + cell $not $not$libresoc.v:177122$10936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182927$11233_Y + connect \Y $not$libresoc.v:177122$10936_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182928$11234 + cell $not $not$libresoc.v:177123$10937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182928$11234_Y + connect \Y $not$libresoc.v:177123$10937_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182929$11235 + cell $not $not$libresoc.v:177124$10938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182929$11235_Y + connect \Y $not$libresoc.v:177124$10938_Y end - attribute \src "libresoc.v:182857.7-182857.20" - process $proc$libresoc.v:182857$11306 + attribute \src "libresoc.v:177052.7-177052.20" + process $proc$libresoc.v:177052$11009 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182884.13-182884.30" - process $proc$libresoc.v:182884$11307 + attribute \src "libresoc.v:177079.13-177079.30" + process $proc$libresoc.v:177079$11010 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end - attribute \src "libresoc.v:182890.13-182890.25" - process $proc$libresoc.v:182890$11308 + attribute \src "libresoc.v:177085.13-177085.25" + process $proc$libresoc.v:177085$11011 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:182895.13-182895.33" - process $proc$libresoc.v:182895$11309 + attribute \src "libresoc.v:177090.13-177090.33" + process $proc$libresoc.v:177090$11012 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end - attribute \src "libresoc.v:182902.13-182902.33" - process $proc$libresoc.v:182902$11310 + attribute \src "libresoc.v:177097.13-177097.33" + process $proc$libresoc.v:177097$11013 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end - attribute \src "libresoc.v:182909.13-182909.33" - process $proc$libresoc.v:182909$11311 + attribute \src "libresoc.v:177104.13-177104.33" + process $proc$libresoc.v:177104$11014 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end - attribute \src "libresoc.v:182930.3-182931.25" - process $proc$libresoc.v:182930$11236 + attribute \src "libresoc.v:177125.3-177126.25" + process $proc$libresoc.v:177125$10939 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:182932.3-182933.37" - process $proc$libresoc.v:182932$11237 + attribute \src "libresoc.v:177127.3-177128.37" + process $proc$libresoc.v:177127$10940 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end - attribute \src "libresoc.v:182934.3-182935.43" - process $proc$libresoc.v:182934$11238 + attribute \src "libresoc.v:177129.3-177130.43" + process $proc$libresoc.v:177129$10941 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end - attribute \src "libresoc.v:182936.3-182937.43" - process $proc$libresoc.v:182936$11239 + attribute \src "libresoc.v:177131.3-177132.43" + process $proc$libresoc.v:177131$10942 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end - attribute \src "libresoc.v:182938.3-182939.43" - process $proc$libresoc.v:182938$11240 + attribute \src "libresoc.v:177133.3-177134.43" + process $proc$libresoc.v:177133$10943 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end - attribute \src "libresoc.v:182940.3-182985.6" - process $proc$libresoc.v:182940$11241 + attribute \src "libresoc.v:177135.3-177180.6" + process $proc$libresoc.v:177135$10944 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[1:0]$11242 $7\src11__data_o$next[1:0]$11249 - attribute \src "libresoc.v:182941.5-182941.29" + assign $0\src11__data_o$next[1:0]$10945 $7\src11__data_o$next[1:0]$10952 + attribute \src "libresoc.v:177136.5-177136.29" switch \initial - attribute \src "libresoc.v:182941.9-182941.17" + attribute \src "libresoc.v:177136.9-177136.17" case 1'1 case end @@ -374857,75 +365402,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[1:0]$11243 $6\src11__data_o$next[1:0]$11248 + assign $1\src11__data_o$next[1:0]$10946 $6\src11__data_o$next[1:0]$10951 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[1:0]$11244 \dest11__data_i + assign $2\src11__data_o$next[1:0]$10947 \dest11__data_i case - assign $2\src11__data_o$next[1:0]$11244 2'00 + assign $2\src11__data_o$next[1:0]$10947 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[1:0]$11245 \dest21__data_i + assign $3\src11__data_o$next[1:0]$10948 \dest21__data_i case - assign $3\src11__data_o$next[1:0]$11245 $2\src11__data_o$next[1:0]$11244 + assign $3\src11__data_o$next[1:0]$10948 $2\src11__data_o$next[1:0]$10947 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[1:0]$11246 \dest31__data_i + assign $4\src11__data_o$next[1:0]$10949 \dest31__data_i case - assign $4\src11__data_o$next[1:0]$11246 $3\src11__data_o$next[1:0]$11245 + assign $4\src11__data_o$next[1:0]$10949 $3\src11__data_o$next[1:0]$10948 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[1:0]$11247 \w1__data_i + assign $5\src11__data_o$next[1:0]$10950 \w1__data_i case - assign $5\src11__data_o$next[1:0]$11247 $4\src11__data_o$next[1:0]$11246 + assign $5\src11__data_o$next[1:0]$10950 $4\src11__data_o$next[1:0]$10949 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[1:0]$11248 \reg + assign $6\src11__data_o$next[1:0]$10951 \reg case - assign $6\src11__data_o$next[1:0]$11248 $5\src11__data_o$next[1:0]$11247 + assign $6\src11__data_o$next[1:0]$10951 $5\src11__data_o$next[1:0]$10950 end case - assign $1\src11__data_o$next[1:0]$11243 2'00 + assign $1\src11__data_o$next[1:0]$10946 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src11__data_o$next[1:0]$11249 2'00 + assign $7\src11__data_o$next[1:0]$10952 2'00 case - assign $7\src11__data_o$next[1:0]$11249 $1\src11__data_o$next[1:0]$11243 + assign $7\src11__data_o$next[1:0]$10952 $1\src11__data_o$next[1:0]$10946 end sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$11242 + update \src11__data_o$next $0\src11__data_o$next[1:0]$10945 end - attribute \src "libresoc.v:182986.3-183021.6" - process $proc$libresoc.v:182986$11250 + attribute \src "libresoc.v:177181.3-177216.6" + process $proc$libresoc.v:177181$10953 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182987.5-182987.29" + attribute \src "libresoc.v:177182.5-177182.29" switch \initial - attribute \src "libresoc.v:182987.9-182987.17" + attribute \src "libresoc.v:177182.9-177182.17" case 1'1 case end @@ -374981,15 +365526,15 @@ module \reg_1$133 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:183022.3-183067.6" - process $proc$libresoc.v:183022$11251 + attribute \src "libresoc.v:177217.3-177262.6" + process $proc$libresoc.v:177217$10954 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[1:0]$11252 $7\src21__data_o$next[1:0]$11259 - attribute \src "libresoc.v:183023.5-183023.29" + assign $0\src21__data_o$next[1:0]$10955 $7\src21__data_o$next[1:0]$10962 + attribute \src "libresoc.v:177218.5-177218.29" switch \initial - attribute \src "libresoc.v:183023.9-183023.17" + attribute \src "libresoc.v:177218.9-177218.17" case 1'1 case end @@ -375002,75 +365547,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[1:0]$11253 $6\src21__data_o$next[1:0]$11258 + assign $1\src21__data_o$next[1:0]$10956 $6\src21__data_o$next[1:0]$10961 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[1:0]$11254 \dest11__data_i + assign $2\src21__data_o$next[1:0]$10957 \dest11__data_i case - assign $2\src21__data_o$next[1:0]$11254 2'00 + assign $2\src21__data_o$next[1:0]$10957 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[1:0]$11255 \dest21__data_i + assign $3\src21__data_o$next[1:0]$10958 \dest21__data_i case - assign $3\src21__data_o$next[1:0]$11255 $2\src21__data_o$next[1:0]$11254 + assign $3\src21__data_o$next[1:0]$10958 $2\src21__data_o$next[1:0]$10957 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[1:0]$11256 \dest31__data_i + assign $4\src21__data_o$next[1:0]$10959 \dest31__data_i case - assign $4\src21__data_o$next[1:0]$11256 $3\src21__data_o$next[1:0]$11255 + assign $4\src21__data_o$next[1:0]$10959 $3\src21__data_o$next[1:0]$10958 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[1:0]$11257 \w1__data_i + assign $5\src21__data_o$next[1:0]$10960 \w1__data_i case - assign $5\src21__data_o$next[1:0]$11257 $4\src21__data_o$next[1:0]$11256 + assign $5\src21__data_o$next[1:0]$10960 $4\src21__data_o$next[1:0]$10959 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[1:0]$11258 \reg + assign $6\src21__data_o$next[1:0]$10961 \reg case - assign $6\src21__data_o$next[1:0]$11258 $5\src21__data_o$next[1:0]$11257 + assign $6\src21__data_o$next[1:0]$10961 $5\src21__data_o$next[1:0]$10960 end case - assign $1\src21__data_o$next[1:0]$11253 2'00 + assign $1\src21__data_o$next[1:0]$10956 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src21__data_o$next[1:0]$11259 2'00 + assign $7\src21__data_o$next[1:0]$10962 2'00 case - assign $7\src21__data_o$next[1:0]$11259 $1\src21__data_o$next[1:0]$11253 + assign $7\src21__data_o$next[1:0]$10962 $1\src21__data_o$next[1:0]$10956 end sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$11252 + update \src21__data_o$next $0\src21__data_o$next[1:0]$10955 end - attribute \src "libresoc.v:183068.3-183103.6" - process $proc$libresoc.v:183068$11260 + attribute \src "libresoc.v:177263.3-177298.6" + process $proc$libresoc.v:177263$10963 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11261 $1\wr_detect$4[0:0]$11262 - attribute \src "libresoc.v:183069.5-183069.29" + assign $0\wr_detect$4[0:0]$10964 $1\wr_detect$4[0:0]$10965 + attribute \src "libresoc.v:177264.5-177264.29" switch \initial - attribute \src "libresoc.v:183069.9-183069.17" + attribute \src "libresoc.v:177264.9-177264.17" case 1'1 case end @@ -375083,58 +365628,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11262 $5\wr_detect$4[0:0]$11266 + assign $1\wr_detect$4[0:0]$10965 $5\wr_detect$4[0:0]$10969 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11263 1'1 + assign $2\wr_detect$4[0:0]$10966 1'1 case - assign $2\wr_detect$4[0:0]$11263 1'0 + assign $2\wr_detect$4[0:0]$10966 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11264 1'1 + assign $3\wr_detect$4[0:0]$10967 1'1 case - assign $3\wr_detect$4[0:0]$11264 $2\wr_detect$4[0:0]$11263 + assign $3\wr_detect$4[0:0]$10967 $2\wr_detect$4[0:0]$10966 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11265 1'1 + assign $4\wr_detect$4[0:0]$10968 1'1 case - assign $4\wr_detect$4[0:0]$11265 $3\wr_detect$4[0:0]$11264 + assign $4\wr_detect$4[0:0]$10968 $3\wr_detect$4[0:0]$10967 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11266 1'1 + assign $5\wr_detect$4[0:0]$10969 1'1 case - assign $5\wr_detect$4[0:0]$11266 $4\wr_detect$4[0:0]$11265 + assign $5\wr_detect$4[0:0]$10969 $4\wr_detect$4[0:0]$10968 end case - assign $1\wr_detect$4[0:0]$11262 1'0 + assign $1\wr_detect$4[0:0]$10965 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11261 + update \wr_detect$4 $0\wr_detect$4[0:0]$10964 end - attribute \src "libresoc.v:183104.3-183149.6" - process $proc$libresoc.v:183104$11267 + attribute \src "libresoc.v:177299.3-177344.6" + process $proc$libresoc.v:177299$10970 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[1:0]$11268 $7\src31__data_o$next[1:0]$11275 - attribute \src "libresoc.v:183105.5-183105.29" + assign $0\src31__data_o$next[1:0]$10971 $7\src31__data_o$next[1:0]$10978 + attribute \src "libresoc.v:177300.5-177300.29" switch \initial - attribute \src "libresoc.v:183105.9-183105.17" + attribute \src "libresoc.v:177300.9-177300.17" case 1'1 case end @@ -375147,75 +365692,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[1:0]$11269 $6\src31__data_o$next[1:0]$11274 + assign $1\src31__data_o$next[1:0]$10972 $6\src31__data_o$next[1:0]$10977 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[1:0]$11270 \dest11__data_i + assign $2\src31__data_o$next[1:0]$10973 \dest11__data_i case - assign $2\src31__data_o$next[1:0]$11270 2'00 + assign $2\src31__data_o$next[1:0]$10973 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[1:0]$11271 \dest21__data_i + assign $3\src31__data_o$next[1:0]$10974 \dest21__data_i case - assign $3\src31__data_o$next[1:0]$11271 $2\src31__data_o$next[1:0]$11270 + assign $3\src31__data_o$next[1:0]$10974 $2\src31__data_o$next[1:0]$10973 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[1:0]$11272 \dest31__data_i + assign $4\src31__data_o$next[1:0]$10975 \dest31__data_i case - assign $4\src31__data_o$next[1:0]$11272 $3\src31__data_o$next[1:0]$11271 + assign $4\src31__data_o$next[1:0]$10975 $3\src31__data_o$next[1:0]$10974 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[1:0]$11273 \w1__data_i + assign $5\src31__data_o$next[1:0]$10976 \w1__data_i case - assign $5\src31__data_o$next[1:0]$11273 $4\src31__data_o$next[1:0]$11272 + assign $5\src31__data_o$next[1:0]$10976 $4\src31__data_o$next[1:0]$10975 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[1:0]$11274 \reg + assign $6\src31__data_o$next[1:0]$10977 \reg case - assign $6\src31__data_o$next[1:0]$11274 $5\src31__data_o$next[1:0]$11273 + assign $6\src31__data_o$next[1:0]$10977 $5\src31__data_o$next[1:0]$10976 end case - assign $1\src31__data_o$next[1:0]$11269 2'00 + assign $1\src31__data_o$next[1:0]$10972 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src31__data_o$next[1:0]$11275 2'00 + assign $7\src31__data_o$next[1:0]$10978 2'00 case - assign $7\src31__data_o$next[1:0]$11275 $1\src31__data_o$next[1:0]$11269 + assign $7\src31__data_o$next[1:0]$10978 $1\src31__data_o$next[1:0]$10972 end sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$11268 + update \src31__data_o$next $0\src31__data_o$next[1:0]$10971 end - attribute \src "libresoc.v:183150.3-183185.6" - process $proc$libresoc.v:183150$11276 + attribute \src "libresoc.v:177345.3-177380.6" + process $proc$libresoc.v:177345$10979 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11277 $1\wr_detect$7[0:0]$11278 - attribute \src "libresoc.v:183151.5-183151.29" + assign $0\wr_detect$7[0:0]$10980 $1\wr_detect$7[0:0]$10981 + attribute \src "libresoc.v:177346.5-177346.29" switch \initial - attribute \src "libresoc.v:183151.9-183151.17" + attribute \src "libresoc.v:177346.9-177346.17" case 1'1 case end @@ -375228,58 +365773,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11278 $5\wr_detect$7[0:0]$11282 + assign $1\wr_detect$7[0:0]$10981 $5\wr_detect$7[0:0]$10985 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11279 1'1 + assign $2\wr_detect$7[0:0]$10982 1'1 case - assign $2\wr_detect$7[0:0]$11279 1'0 + assign $2\wr_detect$7[0:0]$10982 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11280 1'1 + assign $3\wr_detect$7[0:0]$10983 1'1 case - assign $3\wr_detect$7[0:0]$11280 $2\wr_detect$7[0:0]$11279 + assign $3\wr_detect$7[0:0]$10983 $2\wr_detect$7[0:0]$10982 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11281 1'1 + assign $4\wr_detect$7[0:0]$10984 1'1 case - assign $4\wr_detect$7[0:0]$11281 $3\wr_detect$7[0:0]$11280 + assign $4\wr_detect$7[0:0]$10984 $3\wr_detect$7[0:0]$10983 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11282 1'1 + assign $5\wr_detect$7[0:0]$10985 1'1 case - assign $5\wr_detect$7[0:0]$11282 $4\wr_detect$7[0:0]$11281 + assign $5\wr_detect$7[0:0]$10985 $4\wr_detect$7[0:0]$10984 end case - assign $1\wr_detect$7[0:0]$11278 1'0 + assign $1\wr_detect$7[0:0]$10981 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11277 + update \wr_detect$7 $0\wr_detect$7[0:0]$10980 end - attribute \src "libresoc.v:183186.3-183231.6" - process $proc$libresoc.v:183186$11283 + attribute \src "libresoc.v:177381.3-177426.6" + process $proc$libresoc.v:177381$10986 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[1:0]$11284 $7\r1__data_o$next[1:0]$11291 - attribute \src "libresoc.v:183187.5-183187.29" + assign $0\r1__data_o$next[1:0]$10987 $7\r1__data_o$next[1:0]$10994 + attribute \src "libresoc.v:177382.5-177382.29" switch \initial - attribute \src "libresoc.v:183187.9-183187.17" + attribute \src "libresoc.v:177382.9-177382.17" case 1'1 case end @@ -375292,75 +365837,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[1:0]$11285 $6\r1__data_o$next[1:0]$11290 + assign $1\r1__data_o$next[1:0]$10988 $6\r1__data_o$next[1:0]$10993 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[1:0]$11286 \dest11__data_i + assign $2\r1__data_o$next[1:0]$10989 \dest11__data_i case - assign $2\r1__data_o$next[1:0]$11286 2'00 + assign $2\r1__data_o$next[1:0]$10989 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[1:0]$11287 \dest21__data_i + assign $3\r1__data_o$next[1:0]$10990 \dest21__data_i case - assign $3\r1__data_o$next[1:0]$11287 $2\r1__data_o$next[1:0]$11286 + assign $3\r1__data_o$next[1:0]$10990 $2\r1__data_o$next[1:0]$10989 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[1:0]$11288 \dest31__data_i + assign $4\r1__data_o$next[1:0]$10991 \dest31__data_i case - assign $4\r1__data_o$next[1:0]$11288 $3\r1__data_o$next[1:0]$11287 + assign $4\r1__data_o$next[1:0]$10991 $3\r1__data_o$next[1:0]$10990 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[1:0]$11289 \w1__data_i + assign $5\r1__data_o$next[1:0]$10992 \w1__data_i case - assign $5\r1__data_o$next[1:0]$11289 $4\r1__data_o$next[1:0]$11288 + assign $5\r1__data_o$next[1:0]$10992 $4\r1__data_o$next[1:0]$10991 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[1:0]$11290 \reg + assign $6\r1__data_o$next[1:0]$10993 \reg case - assign $6\r1__data_o$next[1:0]$11290 $5\r1__data_o$next[1:0]$11289 + assign $6\r1__data_o$next[1:0]$10993 $5\r1__data_o$next[1:0]$10992 end case - assign $1\r1__data_o$next[1:0]$11285 2'00 + assign $1\r1__data_o$next[1:0]$10988 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r1__data_o$next[1:0]$11291 2'00 + assign $7\r1__data_o$next[1:0]$10994 2'00 case - assign $7\r1__data_o$next[1:0]$11291 $1\r1__data_o$next[1:0]$11285 + assign $7\r1__data_o$next[1:0]$10994 $1\r1__data_o$next[1:0]$10988 end sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$11284 + update \r1__data_o$next $0\r1__data_o$next[1:0]$10987 end - attribute \src "libresoc.v:183232.3-183267.6" - process $proc$libresoc.v:183232$11292 + attribute \src "libresoc.v:177427.3-177462.6" + process $proc$libresoc.v:177427$10995 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11293 $1\wr_detect$10[0:0]$11294 - attribute \src "libresoc.v:183233.5-183233.29" + assign $0\wr_detect$10[0:0]$10996 $1\wr_detect$10[0:0]$10997 + attribute \src "libresoc.v:177428.5-177428.29" switch \initial - attribute \src "libresoc.v:183233.9-183233.17" + attribute \src "libresoc.v:177428.9-177428.17" case 1'1 case end @@ -375373,61 +365918,61 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11294 $5\wr_detect$10[0:0]$11298 + assign $1\wr_detect$10[0:0]$10997 $5\wr_detect$10[0:0]$11001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11295 1'1 + assign $2\wr_detect$10[0:0]$10998 1'1 case - assign $2\wr_detect$10[0:0]$11295 1'0 + assign $2\wr_detect$10[0:0]$10998 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11296 1'1 + assign $3\wr_detect$10[0:0]$10999 1'1 case - assign $3\wr_detect$10[0:0]$11296 $2\wr_detect$10[0:0]$11295 + assign $3\wr_detect$10[0:0]$10999 $2\wr_detect$10[0:0]$10998 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11297 1'1 + assign $4\wr_detect$10[0:0]$11000 1'1 case - assign $4\wr_detect$10[0:0]$11297 $3\wr_detect$10[0:0]$11296 + assign $4\wr_detect$10[0:0]$11000 $3\wr_detect$10[0:0]$10999 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11298 1'1 + assign $5\wr_detect$10[0:0]$11001 1'1 case - assign $5\wr_detect$10[0:0]$11298 $4\wr_detect$10[0:0]$11297 + assign $5\wr_detect$10[0:0]$11001 $4\wr_detect$10[0:0]$11000 end case - assign $1\wr_detect$10[0:0]$11294 1'0 + assign $1\wr_detect$10[0:0]$10997 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11293 + update \wr_detect$10 $0\wr_detect$10[0:0]$10996 end - attribute \src "libresoc.v:183268.3-183300.6" - process $proc$libresoc.v:183268$11299 + attribute \src "libresoc.v:177463.3-177495.6" + process $proc$libresoc.v:177463$11002 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11300 $5\reg$next[1:0]$11305 - attribute \src "libresoc.v:183269.5-183269.29" + assign $0\reg$next[1:0]$11003 $5\reg$next[1:0]$11008 + attribute \src "libresoc.v:177464.5-177464.29" switch \initial - attribute \src "libresoc.v:183269.9-183269.17" + attribute \src "libresoc.v:177464.9-177464.17" case 1'1 case end @@ -375436,179 +365981,179 @@ module \reg_1$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11301 \dest11__data_i + assign $1\reg$next[1:0]$11004 \dest11__data_i case - assign $1\reg$next[1:0]$11301 \reg + assign $1\reg$next[1:0]$11004 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11302 \dest21__data_i + assign $2\reg$next[1:0]$11005 \dest21__data_i case - assign $2\reg$next[1:0]$11302 $1\reg$next[1:0]$11301 + assign $2\reg$next[1:0]$11005 $1\reg$next[1:0]$11004 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11303 \dest31__data_i + assign $3\reg$next[1:0]$11006 \dest31__data_i case - assign $3\reg$next[1:0]$11303 $2\reg$next[1:0]$11302 + assign $3\reg$next[1:0]$11006 $2\reg$next[1:0]$11005 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11304 \w1__data_i + assign $4\reg$next[1:0]$11007 \w1__data_i case - assign $4\reg$next[1:0]$11304 $3\reg$next[1:0]$11303 + assign $4\reg$next[1:0]$11007 $3\reg$next[1:0]$11006 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11305 2'00 + assign $5\reg$next[1:0]$11008 2'00 case - assign $5\reg$next[1:0]$11305 $4\reg$next[1:0]$11304 + assign $5\reg$next[1:0]$11008 $4\reg$next[1:0]$11007 end sync always - update \reg$next $0\reg$next[1:0]$11300 + update \reg$next $0\reg$next[1:0]$11003 end - connect \$9 $not$libresoc.v:182926$11232_Y - connect \$1 $not$libresoc.v:182927$11233_Y - connect \$3 $not$libresoc.v:182928$11234_Y - connect \$6 $not$libresoc.v:182929$11235_Y + connect \$9 $not$libresoc.v:177121$10935_Y + connect \$1 $not$libresoc.v:177122$10936_Y + connect \$3 $not$libresoc.v:177123$10937_Y + connect \$6 $not$libresoc.v:177124$10938_Y end -attribute \src "libresoc.v:183305.1-183654.10" +attribute \src "libresoc.v:177500.1-177849.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" module \reg_1$136 - attribute \src "libresoc.v:183375.3-183420.6" - wire width 64 $0\cia1__data_o$next[63:0]$11320 - attribute \src "libresoc.v:183373.3-183374.41" + attribute \src "libresoc.v:177570.3-177615.6" + wire width 64 $0\cia1__data_o$next[63:0]$11023 + attribute \src "libresoc.v:177568.3-177569.41" wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:183306.7-183306.20" + attribute \src "libresoc.v:177501.7-177501.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183457.3-183502.6" - wire width 64 $0\msr1__data_o$next[63:0]$11330 - attribute \src "libresoc.v:183371.3-183372.41" + attribute \src "libresoc.v:177652.3-177697.6" + wire width 64 $0\msr1__data_o$next[63:0]$11033 + attribute \src "libresoc.v:177566.3-177567.41" wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:183621.3-183653.6" - wire width 64 $0\reg$next[63:0]$11362 - attribute \src "libresoc.v:183367.3-183368.25" + attribute \src "libresoc.v:177816.3-177848.6" + wire width 64 $0\reg$next[63:0]$11065 + attribute \src "libresoc.v:177562.3-177563.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:183539.3-183584.6" - wire width 64 $0\sv1__data_o$next[63:0]$11346 - attribute \src "libresoc.v:183369.3-183370.39" + attribute \src "libresoc.v:177734.3-177779.6" + wire width 64 $0\sv1__data_o$next[63:0]$11049 + attribute \src "libresoc.v:177564.3-177565.39" wire width 64 $0\sv1__data_o[63:0] - attribute \src "libresoc.v:183503.3-183538.6" - wire $0\wr_detect$4[0:0]$11339 - attribute \src "libresoc.v:183585.3-183620.6" - wire $0\wr_detect$7[0:0]$11355 - attribute \src "libresoc.v:183421.3-183456.6" + attribute \src "libresoc.v:177698.3-177733.6" + wire $0\wr_detect$4[0:0]$11042 + attribute \src "libresoc.v:177780.3-177815.6" + wire $0\wr_detect$7[0:0]$11058 + attribute \src "libresoc.v:177616.3-177651.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:183375.3-183420.6" - wire width 64 $1\cia1__data_o$next[63:0]$11321 - attribute \src "libresoc.v:183315.14-183315.49" + attribute \src "libresoc.v:177570.3-177615.6" + wire width 64 $1\cia1__data_o$next[63:0]$11024 + attribute \src "libresoc.v:177510.14-177510.49" wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:183457.3-183502.6" - wire width 64 $1\msr1__data_o$next[63:0]$11331 - attribute \src "libresoc.v:183332.14-183332.49" + attribute \src "libresoc.v:177652.3-177697.6" + wire width 64 $1\msr1__data_o$next[63:0]$11034 + attribute \src "libresoc.v:177527.14-177527.49" wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:183621.3-183653.6" - wire width 64 $1\reg$next[63:0]$11363 - attribute \src "libresoc.v:183344.14-183344.42" + attribute \src "libresoc.v:177816.3-177848.6" + wire width 64 $1\reg$next[63:0]$11066 + attribute \src "libresoc.v:177539.14-177539.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:183539.3-183584.6" - wire width 64 $1\sv1__data_o$next[63:0]$11347 - attribute \src "libresoc.v:183351.14-183351.48" + attribute \src "libresoc.v:177734.3-177779.6" + wire width 64 $1\sv1__data_o$next[63:0]$11050 + attribute \src "libresoc.v:177546.14-177546.48" wire width 64 $1\sv1__data_o[63:0] - attribute \src "libresoc.v:183503.3-183538.6" - wire $1\wr_detect$4[0:0]$11340 - attribute \src "libresoc.v:183585.3-183620.6" - wire $1\wr_detect$7[0:0]$11356 - attribute \src "libresoc.v:183421.3-183456.6" + attribute \src "libresoc.v:177698.3-177733.6" + wire $1\wr_detect$4[0:0]$11043 + attribute \src "libresoc.v:177780.3-177815.6" + wire $1\wr_detect$7[0:0]$11059 + attribute \src "libresoc.v:177616.3-177651.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:183375.3-183420.6" - wire width 64 $2\cia1__data_o$next[63:0]$11322 - attribute \src "libresoc.v:183457.3-183502.6" - wire width 64 $2\msr1__data_o$next[63:0]$11332 - attribute \src "libresoc.v:183621.3-183653.6" - wire width 64 $2\reg$next[63:0]$11364 - attribute \src "libresoc.v:183539.3-183584.6" - wire width 64 $2\sv1__data_o$next[63:0]$11348 - attribute \src "libresoc.v:183503.3-183538.6" - wire $2\wr_detect$4[0:0]$11341 - attribute \src "libresoc.v:183585.3-183620.6" - wire $2\wr_detect$7[0:0]$11357 - attribute \src "libresoc.v:183421.3-183456.6" + attribute \src "libresoc.v:177570.3-177615.6" + wire width 64 $2\cia1__data_o$next[63:0]$11025 + attribute \src "libresoc.v:177652.3-177697.6" + wire width 64 $2\msr1__data_o$next[63:0]$11035 + attribute \src "libresoc.v:177816.3-177848.6" + wire width 64 $2\reg$next[63:0]$11067 + attribute \src "libresoc.v:177734.3-177779.6" + wire width 64 $2\sv1__data_o$next[63:0]$11051 + attribute \src "libresoc.v:177698.3-177733.6" + wire $2\wr_detect$4[0:0]$11044 + attribute \src "libresoc.v:177780.3-177815.6" + wire $2\wr_detect$7[0:0]$11060 + attribute \src "libresoc.v:177616.3-177651.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:183375.3-183420.6" - wire width 64 $3\cia1__data_o$next[63:0]$11323 - attribute \src "libresoc.v:183457.3-183502.6" - wire width 64 $3\msr1__data_o$next[63:0]$11333 - attribute \src "libresoc.v:183621.3-183653.6" - wire width 64 $3\reg$next[63:0]$11365 - attribute \src "libresoc.v:183539.3-183584.6" - wire width 64 $3\sv1__data_o$next[63:0]$11349 - attribute \src "libresoc.v:183503.3-183538.6" - wire $3\wr_detect$4[0:0]$11342 - attribute \src "libresoc.v:183585.3-183620.6" - wire $3\wr_detect$7[0:0]$11358 - attribute \src "libresoc.v:183421.3-183456.6" + attribute \src "libresoc.v:177570.3-177615.6" + wire width 64 $3\cia1__data_o$next[63:0]$11026 + attribute \src "libresoc.v:177652.3-177697.6" + wire width 64 $3\msr1__data_o$next[63:0]$11036 + attribute \src "libresoc.v:177816.3-177848.6" + wire width 64 $3\reg$next[63:0]$11068 + attribute \src "libresoc.v:177734.3-177779.6" + wire width 64 $3\sv1__data_o$next[63:0]$11052 + attribute \src "libresoc.v:177698.3-177733.6" + wire $3\wr_detect$4[0:0]$11045 + attribute \src "libresoc.v:177780.3-177815.6" + wire $3\wr_detect$7[0:0]$11061 + attribute \src "libresoc.v:177616.3-177651.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:183375.3-183420.6" - wire width 64 $4\cia1__data_o$next[63:0]$11324 - attribute \src "libresoc.v:183457.3-183502.6" - wire width 64 $4\msr1__data_o$next[63:0]$11334 - attribute \src "libresoc.v:183621.3-183653.6" - wire width 64 $4\reg$next[63:0]$11366 - attribute \src "libresoc.v:183539.3-183584.6" - wire width 64 $4\sv1__data_o$next[63:0]$11350 - attribute \src "libresoc.v:183503.3-183538.6" - wire $4\wr_detect$4[0:0]$11343 - attribute \src "libresoc.v:183585.3-183620.6" - wire $4\wr_detect$7[0:0]$11359 - attribute \src "libresoc.v:183421.3-183456.6" + attribute \src "libresoc.v:177570.3-177615.6" + wire width 64 $4\cia1__data_o$next[63:0]$11027 + attribute \src "libresoc.v:177652.3-177697.6" + wire width 64 $4\msr1__data_o$next[63:0]$11037 + attribute \src "libresoc.v:177816.3-177848.6" + wire width 64 $4\reg$next[63:0]$11069 + attribute \src "libresoc.v:177734.3-177779.6" + wire width 64 $4\sv1__data_o$next[63:0]$11053 + attribute \src "libresoc.v:177698.3-177733.6" + wire $4\wr_detect$4[0:0]$11046 + attribute \src "libresoc.v:177780.3-177815.6" + wire $4\wr_detect$7[0:0]$11062 + attribute \src "libresoc.v:177616.3-177651.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:183375.3-183420.6" - wire width 64 $5\cia1__data_o$next[63:0]$11325 - attribute \src "libresoc.v:183457.3-183502.6" - wire width 64 $5\msr1__data_o$next[63:0]$11335 - attribute \src "libresoc.v:183621.3-183653.6" - wire width 64 $5\reg$next[63:0]$11367 - attribute \src "libresoc.v:183539.3-183584.6" - wire width 64 $5\sv1__data_o$next[63:0]$11351 - attribute \src "libresoc.v:183503.3-183538.6" - wire $5\wr_detect$4[0:0]$11344 - attribute \src "libresoc.v:183585.3-183620.6" - wire $5\wr_detect$7[0:0]$11360 - attribute \src "libresoc.v:183421.3-183456.6" + attribute \src "libresoc.v:177570.3-177615.6" + wire width 64 $5\cia1__data_o$next[63:0]$11028 + attribute \src "libresoc.v:177652.3-177697.6" + wire width 64 $5\msr1__data_o$next[63:0]$11038 + attribute \src "libresoc.v:177816.3-177848.6" + wire width 64 $5\reg$next[63:0]$11070 + attribute \src "libresoc.v:177734.3-177779.6" + wire width 64 $5\sv1__data_o$next[63:0]$11054 + attribute \src "libresoc.v:177698.3-177733.6" + wire $5\wr_detect$4[0:0]$11047 + attribute \src "libresoc.v:177780.3-177815.6" + wire $5\wr_detect$7[0:0]$11063 + attribute \src "libresoc.v:177616.3-177651.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:183375.3-183420.6" - wire width 64 $6\cia1__data_o$next[63:0]$11326 - attribute \src "libresoc.v:183457.3-183502.6" - wire width 64 $6\msr1__data_o$next[63:0]$11336 - attribute \src "libresoc.v:183539.3-183584.6" - wire width 64 $6\sv1__data_o$next[63:0]$11352 - attribute \src "libresoc.v:183375.3-183420.6" - wire width 64 $7\cia1__data_o$next[63:0]$11327 - attribute \src "libresoc.v:183457.3-183502.6" - wire width 64 $7\msr1__data_o$next[63:0]$11337 - attribute \src "libresoc.v:183539.3-183584.6" - wire width 64 $7\sv1__data_o$next[63:0]$11353 - attribute \src "libresoc.v:183364.17-183364.100" - wire $not$libresoc.v:183364$11312_Y - attribute \src "libresoc.v:183365.17-183365.103" - wire $not$libresoc.v:183365$11313_Y - attribute \src "libresoc.v:183366.17-183366.103" - wire $not$libresoc.v:183366$11314_Y + attribute \src "libresoc.v:177570.3-177615.6" + wire width 64 $6\cia1__data_o$next[63:0]$11029 + attribute \src "libresoc.v:177652.3-177697.6" + wire width 64 $6\msr1__data_o$next[63:0]$11039 + attribute \src "libresoc.v:177734.3-177779.6" + wire width 64 $6\sv1__data_o$next[63:0]$11055 + attribute \src "libresoc.v:177570.3-177615.6" + wire width 64 $7\cia1__data_o$next[63:0]$11030 + attribute \src "libresoc.v:177652.3-177697.6" + wire width 64 $7\msr1__data_o$next[63:0]$11040 + attribute \src "libresoc.v:177734.3-177779.6" + wire width 64 $7\sv1__data_o$next[63:0]$11056 + attribute \src "libresoc.v:177559.17-177559.100" + wire $not$libresoc.v:177559$11015_Y + attribute \src "libresoc.v:177560.17-177560.103" + wire $not$libresoc.v:177560$11016_Y + attribute \src "libresoc.v:177561.17-177561.103" + wire $not$libresoc.v:177561$11017_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -375621,15 +366166,15 @@ module \reg_1$136 wire width 64 \cia1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr11__wen - attribute \src "libresoc.v:183306.7-183306.15" + attribute \src "libresoc.v:177501.7-177501.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr1__data_i @@ -375666,106 +366211,106 @@ module \reg_1$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183364$11312 + cell $not $not$libresoc.v:177559$11015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:183364$11312_Y + connect \Y $not$libresoc.v:177559$11015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183365$11313 + cell $not $not$libresoc.v:177560$11016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:183365$11313_Y + connect \Y $not$libresoc.v:177560$11016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183366$11314 + cell $not $not$libresoc.v:177561$11017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:183366$11314_Y + connect \Y $not$libresoc.v:177561$11017_Y end - attribute \src "libresoc.v:183306.7-183306.20" - process $proc$libresoc.v:183306$11368 + attribute \src "libresoc.v:177501.7-177501.20" + process $proc$libresoc.v:177501$11071 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183315.14-183315.49" - process $proc$libresoc.v:183315$11369 + attribute \src "libresoc.v:177510.14-177510.49" + process $proc$libresoc.v:177510$11072 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end - attribute \src "libresoc.v:183332.14-183332.49" - process $proc$libresoc.v:183332$11370 + attribute \src "libresoc.v:177527.14-177527.49" + process $proc$libresoc.v:177527$11073 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end - attribute \src "libresoc.v:183344.14-183344.42" - process $proc$libresoc.v:183344$11371 + attribute \src "libresoc.v:177539.14-177539.42" + process $proc$libresoc.v:177539$11074 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:183351.14-183351.48" - process $proc$libresoc.v:183351$11372 + attribute \src "libresoc.v:177546.14-177546.48" + process $proc$libresoc.v:177546$11075 assign { } { } assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv1__data_o $1\sv1__data_o[63:0] end - attribute \src "libresoc.v:183367.3-183368.25" - process $proc$libresoc.v:183367$11315 + attribute \src "libresoc.v:177562.3-177563.25" + process $proc$libresoc.v:177562$11018 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:183369.3-183370.39" - process $proc$libresoc.v:183369$11316 + attribute \src "libresoc.v:177564.3-177565.39" + process $proc$libresoc.v:177564$11019 assign { } { } assign $0\sv1__data_o[63:0] \sv1__data_o$next sync posedge \coresync_clk update \sv1__data_o $0\sv1__data_o[63:0] end - attribute \src "libresoc.v:183371.3-183372.41" - process $proc$libresoc.v:183371$11317 + attribute \src "libresoc.v:177566.3-177567.41" + process $proc$libresoc.v:177566$11020 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end - attribute \src "libresoc.v:183373.3-183374.41" - process $proc$libresoc.v:183373$11318 + attribute \src "libresoc.v:177568.3-177569.41" + process $proc$libresoc.v:177568$11021 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end - attribute \src "libresoc.v:183375.3-183420.6" - process $proc$libresoc.v:183375$11319 + attribute \src "libresoc.v:177570.3-177615.6" + process $proc$libresoc.v:177570$11022 assign { } { } assign { } { } assign { } { } - assign $0\cia1__data_o$next[63:0]$11320 $7\cia1__data_o$next[63:0]$11327 - attribute \src "libresoc.v:183376.5-183376.29" + assign $0\cia1__data_o$next[63:0]$11023 $7\cia1__data_o$next[63:0]$11030 + attribute \src "libresoc.v:177571.5-177571.29" switch \initial - attribute \src "libresoc.v:183376.9-183376.17" + attribute \src "libresoc.v:177571.9-177571.17" case 1'1 case end @@ -375778,75 +366323,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\cia1__data_o$next[63:0]$11321 $6\cia1__data_o$next[63:0]$11326 + assign $1\cia1__data_o$next[63:0]$11024 $6\cia1__data_o$next[63:0]$11029 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia1__data_o$next[63:0]$11322 \nia1__data_i + assign $2\cia1__data_o$next[63:0]$11025 \nia1__data_i case - assign $2\cia1__data_o$next[63:0]$11322 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia1__data_o$next[63:0]$11025 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia1__data_o$next[63:0]$11323 \msr1__data_i + assign $3\cia1__data_o$next[63:0]$11026 \msr1__data_i case - assign $3\cia1__data_o$next[63:0]$11323 $2\cia1__data_o$next[63:0]$11322 + assign $3\cia1__data_o$next[63:0]$11026 $2\cia1__data_o$next[63:0]$11025 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia1__data_o$next[63:0]$11324 \sv1__data_i + assign $4\cia1__data_o$next[63:0]$11027 \sv1__data_i case - assign $4\cia1__data_o$next[63:0]$11324 $3\cia1__data_o$next[63:0]$11323 + assign $4\cia1__data_o$next[63:0]$11027 $3\cia1__data_o$next[63:0]$11026 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia1__data_o$next[63:0]$11325 \d_wr11__data_i + assign $5\cia1__data_o$next[63:0]$11028 \d_wr11__data_i case - assign $5\cia1__data_o$next[63:0]$11325 $4\cia1__data_o$next[63:0]$11324 + assign $5\cia1__data_o$next[63:0]$11028 $4\cia1__data_o$next[63:0]$11027 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia1__data_o$next[63:0]$11326 \reg + assign $6\cia1__data_o$next[63:0]$11029 \reg case - assign $6\cia1__data_o$next[63:0]$11326 $5\cia1__data_o$next[63:0]$11325 + assign $6\cia1__data_o$next[63:0]$11029 $5\cia1__data_o$next[63:0]$11028 end case - assign $1\cia1__data_o$next[63:0]$11321 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia1__data_o$next[63:0]$11024 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia1__data_o$next[63:0]$11327 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia1__data_o$next[63:0]$11030 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia1__data_o$next[63:0]$11327 $1\cia1__data_o$next[63:0]$11321 + assign $7\cia1__data_o$next[63:0]$11030 $1\cia1__data_o$next[63:0]$11024 end sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11320 + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11023 end - attribute \src "libresoc.v:183421.3-183456.6" - process $proc$libresoc.v:183421$11328 + attribute \src "libresoc.v:177616.3-177651.6" + process $proc$libresoc.v:177616$11031 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:183422.5-183422.29" + attribute \src "libresoc.v:177617.5-177617.29" switch \initial - attribute \src "libresoc.v:183422.9-183422.17" + attribute \src "libresoc.v:177617.9-177617.17" case 1'1 case end @@ -375902,15 +366447,15 @@ module \reg_1$136 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:183457.3-183502.6" - process $proc$libresoc.v:183457$11329 + attribute \src "libresoc.v:177652.3-177697.6" + process $proc$libresoc.v:177652$11032 assign { } { } assign { } { } assign { } { } - assign $0\msr1__data_o$next[63:0]$11330 $7\msr1__data_o$next[63:0]$11337 - attribute \src "libresoc.v:183458.5-183458.29" + assign $0\msr1__data_o$next[63:0]$11033 $7\msr1__data_o$next[63:0]$11040 + attribute \src "libresoc.v:177653.5-177653.29" switch \initial - attribute \src "libresoc.v:183458.9-183458.17" + attribute \src "libresoc.v:177653.9-177653.17" case 1'1 case end @@ -375923,75 +366468,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\msr1__data_o$next[63:0]$11331 $6\msr1__data_o$next[63:0]$11336 + assign $1\msr1__data_o$next[63:0]$11034 $6\msr1__data_o$next[63:0]$11039 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr1__data_o$next[63:0]$11332 \nia1__data_i + assign $2\msr1__data_o$next[63:0]$11035 \nia1__data_i case - assign $2\msr1__data_o$next[63:0]$11332 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr1__data_o$next[63:0]$11035 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr1__data_o$next[63:0]$11333 \msr1__data_i + assign $3\msr1__data_o$next[63:0]$11036 \msr1__data_i case - assign $3\msr1__data_o$next[63:0]$11333 $2\msr1__data_o$next[63:0]$11332 + assign $3\msr1__data_o$next[63:0]$11036 $2\msr1__data_o$next[63:0]$11035 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr1__data_o$next[63:0]$11334 \sv1__data_i + assign $4\msr1__data_o$next[63:0]$11037 \sv1__data_i case - assign $4\msr1__data_o$next[63:0]$11334 $3\msr1__data_o$next[63:0]$11333 + assign $4\msr1__data_o$next[63:0]$11037 $3\msr1__data_o$next[63:0]$11036 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr1__data_o$next[63:0]$11335 \d_wr11__data_i + assign $5\msr1__data_o$next[63:0]$11038 \d_wr11__data_i case - assign $5\msr1__data_o$next[63:0]$11335 $4\msr1__data_o$next[63:0]$11334 + assign $5\msr1__data_o$next[63:0]$11038 $4\msr1__data_o$next[63:0]$11037 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr1__data_o$next[63:0]$11336 \reg + assign $6\msr1__data_o$next[63:0]$11039 \reg case - assign $6\msr1__data_o$next[63:0]$11336 $5\msr1__data_o$next[63:0]$11335 + assign $6\msr1__data_o$next[63:0]$11039 $5\msr1__data_o$next[63:0]$11038 end case - assign $1\msr1__data_o$next[63:0]$11331 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr1__data_o$next[63:0]$11034 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr1__data_o$next[63:0]$11337 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr1__data_o$next[63:0]$11040 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr1__data_o$next[63:0]$11337 $1\msr1__data_o$next[63:0]$11331 + assign $7\msr1__data_o$next[63:0]$11040 $1\msr1__data_o$next[63:0]$11034 end sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11330 + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11033 end - attribute \src "libresoc.v:183503.3-183538.6" - process $proc$libresoc.v:183503$11338 + attribute \src "libresoc.v:177698.3-177733.6" + process $proc$libresoc.v:177698$11041 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11339 $1\wr_detect$4[0:0]$11340 - attribute \src "libresoc.v:183504.5-183504.29" + assign $0\wr_detect$4[0:0]$11042 $1\wr_detect$4[0:0]$11043 + attribute \src "libresoc.v:177699.5-177699.29" switch \initial - attribute \src "libresoc.v:183504.9-183504.17" + attribute \src "libresoc.v:177699.9-177699.17" case 1'1 case end @@ -376004,58 +366549,58 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11340 $5\wr_detect$4[0:0]$11344 + assign $1\wr_detect$4[0:0]$11043 $5\wr_detect$4[0:0]$11047 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11341 1'1 + assign $2\wr_detect$4[0:0]$11044 1'1 case - assign $2\wr_detect$4[0:0]$11341 1'0 + assign $2\wr_detect$4[0:0]$11044 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11342 1'1 + assign $3\wr_detect$4[0:0]$11045 1'1 case - assign $3\wr_detect$4[0:0]$11342 $2\wr_detect$4[0:0]$11341 + assign $3\wr_detect$4[0:0]$11045 $2\wr_detect$4[0:0]$11044 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11343 1'1 + assign $4\wr_detect$4[0:0]$11046 1'1 case - assign $4\wr_detect$4[0:0]$11343 $3\wr_detect$4[0:0]$11342 + assign $4\wr_detect$4[0:0]$11046 $3\wr_detect$4[0:0]$11045 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11344 1'1 + assign $5\wr_detect$4[0:0]$11047 1'1 case - assign $5\wr_detect$4[0:0]$11344 $4\wr_detect$4[0:0]$11343 + assign $5\wr_detect$4[0:0]$11047 $4\wr_detect$4[0:0]$11046 end case - assign $1\wr_detect$4[0:0]$11340 1'0 + assign $1\wr_detect$4[0:0]$11043 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11339 + update \wr_detect$4 $0\wr_detect$4[0:0]$11042 end - attribute \src "libresoc.v:183539.3-183584.6" - process $proc$libresoc.v:183539$11345 + attribute \src "libresoc.v:177734.3-177779.6" + process $proc$libresoc.v:177734$11048 assign { } { } assign { } { } assign { } { } - assign $0\sv1__data_o$next[63:0]$11346 $7\sv1__data_o$next[63:0]$11353 - attribute \src "libresoc.v:183540.5-183540.29" + assign $0\sv1__data_o$next[63:0]$11049 $7\sv1__data_o$next[63:0]$11056 + attribute \src "libresoc.v:177735.5-177735.29" switch \initial - attribute \src "libresoc.v:183540.9-183540.17" + attribute \src "libresoc.v:177735.9-177735.17" case 1'1 case end @@ -376068,75 +366613,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\sv1__data_o$next[63:0]$11347 $6\sv1__data_o$next[63:0]$11352 + assign $1\sv1__data_o$next[63:0]$11050 $6\sv1__data_o$next[63:0]$11055 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv1__data_o$next[63:0]$11348 \nia1__data_i + assign $2\sv1__data_o$next[63:0]$11051 \nia1__data_i case - assign $2\sv1__data_o$next[63:0]$11348 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv1__data_o$next[63:0]$11051 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv1__data_o$next[63:0]$11349 \msr1__data_i + assign $3\sv1__data_o$next[63:0]$11052 \msr1__data_i case - assign $3\sv1__data_o$next[63:0]$11349 $2\sv1__data_o$next[63:0]$11348 + assign $3\sv1__data_o$next[63:0]$11052 $2\sv1__data_o$next[63:0]$11051 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv1__data_o$next[63:0]$11350 \sv1__data_i + assign $4\sv1__data_o$next[63:0]$11053 \sv1__data_i case - assign $4\sv1__data_o$next[63:0]$11350 $3\sv1__data_o$next[63:0]$11349 + assign $4\sv1__data_o$next[63:0]$11053 $3\sv1__data_o$next[63:0]$11052 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv1__data_o$next[63:0]$11351 \d_wr11__data_i + assign $5\sv1__data_o$next[63:0]$11054 \d_wr11__data_i case - assign $5\sv1__data_o$next[63:0]$11351 $4\sv1__data_o$next[63:0]$11350 + assign $5\sv1__data_o$next[63:0]$11054 $4\sv1__data_o$next[63:0]$11053 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv1__data_o$next[63:0]$11352 \reg + assign $6\sv1__data_o$next[63:0]$11055 \reg case - assign $6\sv1__data_o$next[63:0]$11352 $5\sv1__data_o$next[63:0]$11351 + assign $6\sv1__data_o$next[63:0]$11055 $5\sv1__data_o$next[63:0]$11054 end case - assign $1\sv1__data_o$next[63:0]$11347 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv1__data_o$next[63:0]$11050 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv1__data_o$next[63:0]$11353 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv1__data_o$next[63:0]$11056 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv1__data_o$next[63:0]$11353 $1\sv1__data_o$next[63:0]$11347 + assign $7\sv1__data_o$next[63:0]$11056 $1\sv1__data_o$next[63:0]$11050 end sync always - update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11346 + update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11049 end - attribute \src "libresoc.v:183585.3-183620.6" - process $proc$libresoc.v:183585$11354 + attribute \src "libresoc.v:177780.3-177815.6" + process $proc$libresoc.v:177780$11057 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11355 $1\wr_detect$7[0:0]$11356 - attribute \src "libresoc.v:183586.5-183586.29" + assign $0\wr_detect$7[0:0]$11058 $1\wr_detect$7[0:0]$11059 + attribute \src "libresoc.v:177781.5-177781.29" switch \initial - attribute \src "libresoc.v:183586.9-183586.17" + attribute \src "libresoc.v:177781.9-177781.17" case 1'1 case end @@ -376149,61 +366694,61 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11356 $5\wr_detect$7[0:0]$11360 + assign $1\wr_detect$7[0:0]$11059 $5\wr_detect$7[0:0]$11063 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11357 1'1 + assign $2\wr_detect$7[0:0]$11060 1'1 case - assign $2\wr_detect$7[0:0]$11357 1'0 + assign $2\wr_detect$7[0:0]$11060 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11358 1'1 + assign $3\wr_detect$7[0:0]$11061 1'1 case - assign $3\wr_detect$7[0:0]$11358 $2\wr_detect$7[0:0]$11357 + assign $3\wr_detect$7[0:0]$11061 $2\wr_detect$7[0:0]$11060 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11359 1'1 + assign $4\wr_detect$7[0:0]$11062 1'1 case - assign $4\wr_detect$7[0:0]$11359 $3\wr_detect$7[0:0]$11358 + assign $4\wr_detect$7[0:0]$11062 $3\wr_detect$7[0:0]$11061 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11360 1'1 + assign $5\wr_detect$7[0:0]$11063 1'1 case - assign $5\wr_detect$7[0:0]$11360 $4\wr_detect$7[0:0]$11359 + assign $5\wr_detect$7[0:0]$11063 $4\wr_detect$7[0:0]$11062 end case - assign $1\wr_detect$7[0:0]$11356 1'0 + assign $1\wr_detect$7[0:0]$11059 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11355 + update \wr_detect$7 $0\wr_detect$7[0:0]$11058 end - attribute \src "libresoc.v:183621.3-183653.6" - process $proc$libresoc.v:183621$11361 + attribute \src "libresoc.v:177816.3-177848.6" + process $proc$libresoc.v:177816$11064 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11362 $5\reg$next[63:0]$11367 - attribute \src "libresoc.v:183622.5-183622.29" + assign $0\reg$next[63:0]$11065 $5\reg$next[63:0]$11070 + attribute \src "libresoc.v:177817.5-177817.29" switch \initial - attribute \src "libresoc.v:183622.9-183622.17" + attribute \src "libresoc.v:177817.9-177817.17" case 1'1 case end @@ -376212,224 +366757,224 @@ module \reg_1$136 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11363 \nia1__data_i + assign $1\reg$next[63:0]$11066 \nia1__data_i case - assign $1\reg$next[63:0]$11363 \reg + assign $1\reg$next[63:0]$11066 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11364 \msr1__data_i + assign $2\reg$next[63:0]$11067 \msr1__data_i case - assign $2\reg$next[63:0]$11364 $1\reg$next[63:0]$11363 + assign $2\reg$next[63:0]$11067 $1\reg$next[63:0]$11066 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11365 \sv1__data_i + assign $3\reg$next[63:0]$11068 \sv1__data_i case - assign $3\reg$next[63:0]$11365 $2\reg$next[63:0]$11364 + assign $3\reg$next[63:0]$11068 $2\reg$next[63:0]$11067 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11366 \d_wr11__data_i + assign $4\reg$next[63:0]$11069 \d_wr11__data_i case - assign $4\reg$next[63:0]$11366 $3\reg$next[63:0]$11365 + assign $4\reg$next[63:0]$11069 $3\reg$next[63:0]$11068 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11367 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11070 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11367 $4\reg$next[63:0]$11366 + assign $5\reg$next[63:0]$11070 $4\reg$next[63:0]$11069 end sync always - update \reg$next $0\reg$next[63:0]$11362 + update \reg$next $0\reg$next[63:0]$11065 end - connect \$1 $not$libresoc.v:183364$11312_Y - connect \$3 $not$libresoc.v:183365$11313_Y - connect \$6 $not$libresoc.v:183366$11314_Y + connect \$1 $not$libresoc.v:177559$11015_Y + connect \$3 $not$libresoc.v:177560$11016_Y + connect \$6 $not$libresoc.v:177561$11017_Y end -attribute \src "libresoc.v:183658.1-184129.10" +attribute \src "libresoc.v:177853.1-178324.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 - attribute \src "libresoc.v:183659.7-183659.20" + attribute \src "libresoc.v:177854.7-177854.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184059.3-184098.6" - wire width 4 $0\r22__data_o$next[3:0]$11442 - attribute \src "libresoc.v:183742.3-183743.39" + attribute \src "libresoc.v:178254.3-178293.6" + wire width 4 $0\r22__data_o$next[3:0]$11145 + attribute \src "libresoc.v:177937.3-177938.39" wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:183989.3-184028.6" - wire width 4 $0\r2__data_o$next[3:0]$11428 - attribute \src "libresoc.v:183744.3-183745.37" + attribute \src "libresoc.v:178184.3-178223.6" + wire width 4 $0\r2__data_o$next[3:0]$11131 + attribute \src "libresoc.v:177939.3-177940.37" wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:183822.3-183848.6" - wire width 4 $0\reg$next[3:0]$11394 - attribute \src "libresoc.v:183740.3-183741.25" + attribute \src "libresoc.v:178017.3-178043.6" + wire width 4 $0\reg$next[3:0]$11097 + attribute \src "libresoc.v:177935.3-177936.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:183752.3-183791.6" - wire width 4 $0\src12__data_o$next[3:0]$11385 - attribute \src "libresoc.v:183750.3-183751.43" + attribute \src "libresoc.v:177947.3-177986.6" + wire width 4 $0\src12__data_o$next[3:0]$11088 + attribute \src "libresoc.v:177945.3-177946.43" wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:183849.3-183888.6" - wire width 4 $0\src22__data_o$next[3:0]$11400 - attribute \src "libresoc.v:183748.3-183749.43" + attribute \src "libresoc.v:178044.3-178083.6" + wire width 4 $0\src22__data_o$next[3:0]$11103 + attribute \src "libresoc.v:177943.3-177944.43" wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:183919.3-183958.6" - wire width 4 $0\src32__data_o$next[3:0]$11414 - attribute \src "libresoc.v:183746.3-183747.43" + attribute \src "libresoc.v:178114.3-178153.6" + wire width 4 $0\src32__data_o$next[3:0]$11117 + attribute \src "libresoc.v:177941.3-177942.43" wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:184029.3-184058.6" - wire $0\wr_detect$10[0:0]$11436 - attribute \src "libresoc.v:184099.3-184128.6" - wire $0\wr_detect$13[0:0]$11450 - attribute \src "libresoc.v:183889.3-183918.6" - wire $0\wr_detect$4[0:0]$11408 - attribute \src "libresoc.v:183959.3-183988.6" - wire $0\wr_detect$7[0:0]$11422 - attribute \src "libresoc.v:183792.3-183821.6" + attribute \src "libresoc.v:178224.3-178253.6" + wire $0\wr_detect$10[0:0]$11139 + attribute \src "libresoc.v:178294.3-178323.6" + wire $0\wr_detect$13[0:0]$11153 + attribute \src "libresoc.v:178084.3-178113.6" + wire $0\wr_detect$4[0:0]$11111 + attribute \src "libresoc.v:178154.3-178183.6" + wire $0\wr_detect$7[0:0]$11125 + attribute \src "libresoc.v:177987.3-178016.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:184059.3-184098.6" - wire width 4 $1\r22__data_o$next[3:0]$11443 - attribute \src "libresoc.v:183684.13-183684.31" + attribute \src "libresoc.v:178254.3-178293.6" + wire width 4 $1\r22__data_o$next[3:0]$11146 + attribute \src "libresoc.v:177879.13-177879.31" wire width 4 $1\r22__data_o[3:0] - attribute \src "libresoc.v:183989.3-184028.6" - wire width 4 $1\r2__data_o$next[3:0]$11429 - attribute \src "libresoc.v:183691.13-183691.30" + attribute \src "libresoc.v:178184.3-178223.6" + wire width 4 $1\r2__data_o$next[3:0]$11132 + attribute \src "libresoc.v:177886.13-177886.30" wire width 4 $1\r2__data_o[3:0] - attribute \src "libresoc.v:183822.3-183848.6" - wire width 4 $1\reg$next[3:0]$11395 - attribute \src "libresoc.v:183697.13-183697.25" + attribute \src "libresoc.v:178017.3-178043.6" + wire width 4 $1\reg$next[3:0]$11098 + attribute \src "libresoc.v:177892.13-177892.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:183752.3-183791.6" - wire width 4 $1\src12__data_o$next[3:0]$11386 - attribute \src "libresoc.v:183702.13-183702.33" + attribute \src "libresoc.v:177947.3-177986.6" + wire width 4 $1\src12__data_o$next[3:0]$11089 + attribute \src "libresoc.v:177897.13-177897.33" wire width 4 $1\src12__data_o[3:0] - attribute \src "libresoc.v:183849.3-183888.6" - wire width 4 $1\src22__data_o$next[3:0]$11401 - attribute \src "libresoc.v:183709.13-183709.33" + attribute \src "libresoc.v:178044.3-178083.6" + wire width 4 $1\src22__data_o$next[3:0]$11104 + attribute \src "libresoc.v:177904.13-177904.33" wire width 4 $1\src22__data_o[3:0] - attribute \src "libresoc.v:183919.3-183958.6" - wire width 4 $1\src32__data_o$next[3:0]$11415 - attribute \src "libresoc.v:183716.13-183716.33" + attribute \src "libresoc.v:178114.3-178153.6" + wire width 4 $1\src32__data_o$next[3:0]$11118 + attribute \src "libresoc.v:177911.13-177911.33" wire width 4 $1\src32__data_o[3:0] - attribute \src "libresoc.v:184029.3-184058.6" - wire $1\wr_detect$10[0:0]$11437 - attribute \src "libresoc.v:184099.3-184128.6" - wire $1\wr_detect$13[0:0]$11451 - attribute \src "libresoc.v:183889.3-183918.6" - wire $1\wr_detect$4[0:0]$11409 - attribute \src "libresoc.v:183959.3-183988.6" - wire $1\wr_detect$7[0:0]$11423 - attribute \src "libresoc.v:183792.3-183821.6" + attribute \src "libresoc.v:178224.3-178253.6" + wire $1\wr_detect$10[0:0]$11140 + attribute \src "libresoc.v:178294.3-178323.6" + wire $1\wr_detect$13[0:0]$11154 + attribute \src "libresoc.v:178084.3-178113.6" + wire $1\wr_detect$4[0:0]$11112 + attribute \src "libresoc.v:178154.3-178183.6" + wire $1\wr_detect$7[0:0]$11126 + attribute \src "libresoc.v:177987.3-178016.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:184059.3-184098.6" - wire width 4 $2\r22__data_o$next[3:0]$11444 - attribute \src "libresoc.v:183989.3-184028.6" - wire width 4 $2\r2__data_o$next[3:0]$11430 - attribute \src "libresoc.v:183822.3-183848.6" - wire width 4 $2\reg$next[3:0]$11396 - attribute \src "libresoc.v:183752.3-183791.6" - wire width 4 $2\src12__data_o$next[3:0]$11387 - attribute \src "libresoc.v:183849.3-183888.6" - wire width 4 $2\src22__data_o$next[3:0]$11402 - attribute \src "libresoc.v:183919.3-183958.6" - wire width 4 $2\src32__data_o$next[3:0]$11416 - attribute \src "libresoc.v:184029.3-184058.6" - wire $2\wr_detect$10[0:0]$11438 - attribute \src "libresoc.v:184099.3-184128.6" - wire $2\wr_detect$13[0:0]$11452 - attribute \src "libresoc.v:183889.3-183918.6" - wire $2\wr_detect$4[0:0]$11410 - attribute \src "libresoc.v:183959.3-183988.6" - wire $2\wr_detect$7[0:0]$11424 - attribute \src "libresoc.v:183792.3-183821.6" + attribute \src "libresoc.v:178254.3-178293.6" + wire width 4 $2\r22__data_o$next[3:0]$11147 + attribute \src "libresoc.v:178184.3-178223.6" + wire width 4 $2\r2__data_o$next[3:0]$11133 + attribute \src "libresoc.v:178017.3-178043.6" + wire width 4 $2\reg$next[3:0]$11099 + attribute \src "libresoc.v:177947.3-177986.6" + wire width 4 $2\src12__data_o$next[3:0]$11090 + attribute \src "libresoc.v:178044.3-178083.6" + wire width 4 $2\src22__data_o$next[3:0]$11105 + attribute \src "libresoc.v:178114.3-178153.6" + wire width 4 $2\src32__data_o$next[3:0]$11119 + attribute \src "libresoc.v:178224.3-178253.6" + wire $2\wr_detect$10[0:0]$11141 + attribute \src "libresoc.v:178294.3-178323.6" + wire $2\wr_detect$13[0:0]$11155 + attribute \src "libresoc.v:178084.3-178113.6" + wire $2\wr_detect$4[0:0]$11113 + attribute \src "libresoc.v:178154.3-178183.6" + wire $2\wr_detect$7[0:0]$11127 + attribute \src "libresoc.v:177987.3-178016.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:184059.3-184098.6" - wire width 4 $3\r22__data_o$next[3:0]$11445 - attribute \src "libresoc.v:183989.3-184028.6" - wire width 4 $3\r2__data_o$next[3:0]$11431 - attribute \src "libresoc.v:183822.3-183848.6" - wire width 4 $3\reg$next[3:0]$11397 - attribute \src "libresoc.v:183752.3-183791.6" - wire width 4 $3\src12__data_o$next[3:0]$11388 - attribute \src "libresoc.v:183849.3-183888.6" - wire width 4 $3\src22__data_o$next[3:0]$11403 - attribute \src "libresoc.v:183919.3-183958.6" - wire width 4 $3\src32__data_o$next[3:0]$11417 - attribute \src "libresoc.v:184029.3-184058.6" - wire $3\wr_detect$10[0:0]$11439 - attribute \src "libresoc.v:184099.3-184128.6" - wire $3\wr_detect$13[0:0]$11453 - attribute \src "libresoc.v:183889.3-183918.6" - wire $3\wr_detect$4[0:0]$11411 - attribute \src "libresoc.v:183959.3-183988.6" - wire $3\wr_detect$7[0:0]$11425 - attribute \src "libresoc.v:183792.3-183821.6" + attribute \src "libresoc.v:178254.3-178293.6" + wire width 4 $3\r22__data_o$next[3:0]$11148 + attribute \src "libresoc.v:178184.3-178223.6" + wire width 4 $3\r2__data_o$next[3:0]$11134 + attribute \src "libresoc.v:178017.3-178043.6" + wire width 4 $3\reg$next[3:0]$11100 + attribute \src "libresoc.v:177947.3-177986.6" + wire width 4 $3\src12__data_o$next[3:0]$11091 + attribute \src "libresoc.v:178044.3-178083.6" + wire width 4 $3\src22__data_o$next[3:0]$11106 + attribute \src "libresoc.v:178114.3-178153.6" + wire width 4 $3\src32__data_o$next[3:0]$11120 + attribute \src "libresoc.v:178224.3-178253.6" + wire $3\wr_detect$10[0:0]$11142 + attribute \src "libresoc.v:178294.3-178323.6" + wire $3\wr_detect$13[0:0]$11156 + attribute \src "libresoc.v:178084.3-178113.6" + wire $3\wr_detect$4[0:0]$11114 + attribute \src "libresoc.v:178154.3-178183.6" + wire $3\wr_detect$7[0:0]$11128 + attribute \src "libresoc.v:177987.3-178016.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:184059.3-184098.6" - wire width 4 $4\r22__data_o$next[3:0]$11446 - attribute \src "libresoc.v:183989.3-184028.6" - wire width 4 $4\r2__data_o$next[3:0]$11432 - attribute \src "libresoc.v:183822.3-183848.6" - wire width 4 $4\reg$next[3:0]$11398 - attribute \src "libresoc.v:183752.3-183791.6" - wire width 4 $4\src12__data_o$next[3:0]$11389 - attribute \src "libresoc.v:183849.3-183888.6" - wire width 4 $4\src22__data_o$next[3:0]$11404 - attribute \src "libresoc.v:183919.3-183958.6" - wire width 4 $4\src32__data_o$next[3:0]$11418 - attribute \src "libresoc.v:184029.3-184058.6" - wire $4\wr_detect$10[0:0]$11440 - attribute \src "libresoc.v:184099.3-184128.6" - wire $4\wr_detect$13[0:0]$11454 - attribute \src "libresoc.v:183889.3-183918.6" - wire $4\wr_detect$4[0:0]$11412 - attribute \src "libresoc.v:183959.3-183988.6" - wire $4\wr_detect$7[0:0]$11426 - attribute \src "libresoc.v:183792.3-183821.6" + attribute \src "libresoc.v:178254.3-178293.6" + wire width 4 $4\r22__data_o$next[3:0]$11149 + attribute \src "libresoc.v:178184.3-178223.6" + wire width 4 $4\r2__data_o$next[3:0]$11135 + attribute \src "libresoc.v:178017.3-178043.6" + wire width 4 $4\reg$next[3:0]$11101 + attribute \src "libresoc.v:177947.3-177986.6" + wire width 4 $4\src12__data_o$next[3:0]$11092 + attribute \src "libresoc.v:178044.3-178083.6" + wire width 4 $4\src22__data_o$next[3:0]$11107 + attribute \src "libresoc.v:178114.3-178153.6" + wire width 4 $4\src32__data_o$next[3:0]$11121 + attribute \src "libresoc.v:178224.3-178253.6" + wire $4\wr_detect$10[0:0]$11143 + attribute \src "libresoc.v:178294.3-178323.6" + wire $4\wr_detect$13[0:0]$11157 + attribute \src "libresoc.v:178084.3-178113.6" + wire $4\wr_detect$4[0:0]$11115 + attribute \src "libresoc.v:178154.3-178183.6" + wire $4\wr_detect$7[0:0]$11129 + attribute \src "libresoc.v:177987.3-178016.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:184059.3-184098.6" - wire width 4 $5\r22__data_o$next[3:0]$11447 - attribute \src "libresoc.v:183989.3-184028.6" - wire width 4 $5\r2__data_o$next[3:0]$11433 - attribute \src "libresoc.v:183752.3-183791.6" - wire width 4 $5\src12__data_o$next[3:0]$11390 - attribute \src "libresoc.v:183849.3-183888.6" - wire width 4 $5\src22__data_o$next[3:0]$11405 - attribute \src "libresoc.v:183919.3-183958.6" - wire width 4 $5\src32__data_o$next[3:0]$11419 - attribute \src "libresoc.v:184059.3-184098.6" - wire width 4 $6\r22__data_o$next[3:0]$11448 - attribute \src "libresoc.v:183989.3-184028.6" - wire width 4 $6\r2__data_o$next[3:0]$11434 - attribute \src "libresoc.v:183752.3-183791.6" - wire width 4 $6\src12__data_o$next[3:0]$11391 - attribute \src "libresoc.v:183849.3-183888.6" - wire width 4 $6\src22__data_o$next[3:0]$11406 - attribute \src "libresoc.v:183919.3-183958.6" - wire width 4 $6\src32__data_o$next[3:0]$11420 - attribute \src "libresoc.v:183735.17-183735.104" - wire $not$libresoc.v:183735$11373_Y - attribute \src "libresoc.v:183736.18-183736.105" - wire $not$libresoc.v:183736$11374_Y - attribute \src "libresoc.v:183737.17-183737.100" - wire $not$libresoc.v:183737$11375_Y - attribute \src "libresoc.v:183738.17-183738.103" - wire $not$libresoc.v:183738$11376_Y - attribute \src "libresoc.v:183739.17-183739.103" - wire $not$libresoc.v:183739$11377_Y + attribute \src "libresoc.v:178254.3-178293.6" + wire width 4 $5\r22__data_o$next[3:0]$11150 + attribute \src "libresoc.v:178184.3-178223.6" + wire width 4 $5\r2__data_o$next[3:0]$11136 + attribute \src "libresoc.v:177947.3-177986.6" + wire width 4 $5\src12__data_o$next[3:0]$11093 + attribute \src "libresoc.v:178044.3-178083.6" + wire width 4 $5\src22__data_o$next[3:0]$11108 + attribute \src "libresoc.v:178114.3-178153.6" + wire width 4 $5\src32__data_o$next[3:0]$11122 + attribute \src "libresoc.v:178254.3-178293.6" + wire width 4 $6\r22__data_o$next[3:0]$11151 + attribute \src "libresoc.v:178184.3-178223.6" + wire width 4 $6\r2__data_o$next[3:0]$11137 + attribute \src "libresoc.v:177947.3-177986.6" + wire width 4 $6\src12__data_o$next[3:0]$11094 + attribute \src "libresoc.v:178044.3-178083.6" + wire width 4 $6\src22__data_o$next[3:0]$11109 + attribute \src "libresoc.v:178114.3-178153.6" + wire width 4 $6\src32__data_o$next[3:0]$11123 + attribute \src "libresoc.v:177930.17-177930.104" + wire $not$libresoc.v:177930$11076_Y + attribute \src "libresoc.v:177931.18-177931.105" + wire $not$libresoc.v:177931$11077_Y + attribute \src "libresoc.v:177932.17-177932.100" + wire $not$libresoc.v:177932$11078_Y + attribute \src "libresoc.v:177933.17-177933.103" + wire $not$libresoc.v:177933$11079_Y + attribute \src "libresoc.v:177934.17-177934.103" + wire $not$libresoc.v:177934$11080_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -376440,9 +366985,9 @@ module \reg_2 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest12__data_i @@ -376452,7 +366997,7 @@ module \reg_2 wire width 4 input 11 \dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest22__wen - attribute \src "libresoc.v:183659.7-183659.15" + attribute \src "libresoc.v:177854.7-177854.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r22__data_o @@ -376503,152 +367048,152 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183735$11373 + cell $not $not$libresoc.v:177930$11076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:183735$11373_Y + connect \Y $not$libresoc.v:177930$11076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183736$11374 + cell $not $not$libresoc.v:177931$11077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:183736$11374_Y + connect \Y $not$libresoc.v:177931$11077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183737$11375 + cell $not $not$libresoc.v:177932$11078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:183737$11375_Y + connect \Y $not$libresoc.v:177932$11078_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183738$11376 + cell $not $not$libresoc.v:177933$11079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:183738$11376_Y + connect \Y $not$libresoc.v:177933$11079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183739$11377 + cell $not $not$libresoc.v:177934$11080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:183739$11377_Y + connect \Y $not$libresoc.v:177934$11080_Y end - attribute \src "libresoc.v:183659.7-183659.20" - process $proc$libresoc.v:183659$11455 + attribute \src "libresoc.v:177854.7-177854.20" + process $proc$libresoc.v:177854$11158 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183684.13-183684.31" - process $proc$libresoc.v:183684$11456 + attribute \src "libresoc.v:177879.13-177879.31" + process $proc$libresoc.v:177879$11159 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end - attribute \src "libresoc.v:183691.13-183691.30" - process $proc$libresoc.v:183691$11457 + attribute \src "libresoc.v:177886.13-177886.30" + process $proc$libresoc.v:177886$11160 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end - attribute \src "libresoc.v:183697.13-183697.25" - process $proc$libresoc.v:183697$11458 + attribute \src "libresoc.v:177892.13-177892.25" + process $proc$libresoc.v:177892$11161 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:183702.13-183702.33" - process $proc$libresoc.v:183702$11459 + attribute \src "libresoc.v:177897.13-177897.33" + process $proc$libresoc.v:177897$11162 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end - attribute \src "libresoc.v:183709.13-183709.33" - process $proc$libresoc.v:183709$11460 + attribute \src "libresoc.v:177904.13-177904.33" + process $proc$libresoc.v:177904$11163 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end - attribute \src "libresoc.v:183716.13-183716.33" - process $proc$libresoc.v:183716$11461 + attribute \src "libresoc.v:177911.13-177911.33" + process $proc$libresoc.v:177911$11164 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end - attribute \src "libresoc.v:183740.3-183741.25" - process $proc$libresoc.v:183740$11378 + attribute \src "libresoc.v:177935.3-177936.25" + process $proc$libresoc.v:177935$11081 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:183742.3-183743.39" - process $proc$libresoc.v:183742$11379 + attribute \src "libresoc.v:177937.3-177938.39" + process $proc$libresoc.v:177937$11082 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end - attribute \src "libresoc.v:183744.3-183745.37" - process $proc$libresoc.v:183744$11380 + attribute \src "libresoc.v:177939.3-177940.37" + process $proc$libresoc.v:177939$11083 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end - attribute \src "libresoc.v:183746.3-183747.43" - process $proc$libresoc.v:183746$11381 + attribute \src "libresoc.v:177941.3-177942.43" + process $proc$libresoc.v:177941$11084 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end - attribute \src "libresoc.v:183748.3-183749.43" - process $proc$libresoc.v:183748$11382 + attribute \src "libresoc.v:177943.3-177944.43" + process $proc$libresoc.v:177943$11085 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end - attribute \src "libresoc.v:183750.3-183751.43" - process $proc$libresoc.v:183750$11383 + attribute \src "libresoc.v:177945.3-177946.43" + process $proc$libresoc.v:177945$11086 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end - attribute \src "libresoc.v:183752.3-183791.6" - process $proc$libresoc.v:183752$11384 + attribute \src "libresoc.v:177947.3-177986.6" + process $proc$libresoc.v:177947$11087 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[3:0]$11385 $6\src12__data_o$next[3:0]$11391 - attribute \src "libresoc.v:183753.5-183753.29" + assign $0\src12__data_o$next[3:0]$11088 $6\src12__data_o$next[3:0]$11094 + attribute \src "libresoc.v:177948.5-177948.29" switch \initial - attribute \src "libresoc.v:183753.9-183753.17" + attribute \src "libresoc.v:177948.9-177948.17" case 1'1 case end @@ -376660,66 +367205,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[3:0]$11386 $5\src12__data_o$next[3:0]$11390 + assign $1\src12__data_o$next[3:0]$11089 $5\src12__data_o$next[3:0]$11093 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[3:0]$11387 \dest12__data_i + assign $2\src12__data_o$next[3:0]$11090 \dest12__data_i case - assign $2\src12__data_o$next[3:0]$11387 4'0000 + assign $2\src12__data_o$next[3:0]$11090 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[3:0]$11388 \dest22__data_i + assign $3\src12__data_o$next[3:0]$11091 \dest22__data_i case - assign $3\src12__data_o$next[3:0]$11388 $2\src12__data_o$next[3:0]$11387 + assign $3\src12__data_o$next[3:0]$11091 $2\src12__data_o$next[3:0]$11090 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[3:0]$11389 \w2__data_i + assign $4\src12__data_o$next[3:0]$11092 \w2__data_i case - assign $4\src12__data_o$next[3:0]$11389 $3\src12__data_o$next[3:0]$11388 + assign $4\src12__data_o$next[3:0]$11092 $3\src12__data_o$next[3:0]$11091 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[3:0]$11390 \reg + assign $5\src12__data_o$next[3:0]$11093 \reg case - assign $5\src12__data_o$next[3:0]$11390 $4\src12__data_o$next[3:0]$11389 + assign $5\src12__data_o$next[3:0]$11093 $4\src12__data_o$next[3:0]$11092 end case - assign $1\src12__data_o$next[3:0]$11386 4'0000 + assign $1\src12__data_o$next[3:0]$11089 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[3:0]$11391 4'0000 + assign $6\src12__data_o$next[3:0]$11094 4'0000 case - assign $6\src12__data_o$next[3:0]$11391 $1\src12__data_o$next[3:0]$11386 + assign $6\src12__data_o$next[3:0]$11094 $1\src12__data_o$next[3:0]$11089 end sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$11385 + update \src12__data_o$next $0\src12__data_o$next[3:0]$11088 end - attribute \src "libresoc.v:183792.3-183821.6" - process $proc$libresoc.v:183792$11392 + attribute \src "libresoc.v:177987.3-178016.6" + process $proc$libresoc.v:177987$11095 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:183793.5-183793.29" + attribute \src "libresoc.v:177988.5-177988.29" switch \initial - attribute \src "libresoc.v:183793.9-183793.17" + attribute \src "libresoc.v:177988.9-177988.17" case 1'1 case end @@ -376765,17 +367310,17 @@ module \reg_2 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:183822.3-183848.6" - process $proc$libresoc.v:183822$11393 + attribute \src "libresoc.v:178017.3-178043.6" + process $proc$libresoc.v:178017$11096 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11394 $4\reg$next[3:0]$11398 - attribute \src "libresoc.v:183823.5-183823.29" + assign $0\reg$next[3:0]$11097 $4\reg$next[3:0]$11101 + attribute \src "libresoc.v:178018.5-178018.29" switch \initial - attribute \src "libresoc.v:183823.9-183823.17" + attribute \src "libresoc.v:178018.9-178018.17" case 1'1 case end @@ -376784,49 +367329,49 @@ module \reg_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11395 \dest12__data_i + assign $1\reg$next[3:0]$11098 \dest12__data_i case - assign $1\reg$next[3:0]$11395 \reg + assign $1\reg$next[3:0]$11098 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11396 \dest22__data_i + assign $2\reg$next[3:0]$11099 \dest22__data_i case - assign $2\reg$next[3:0]$11396 $1\reg$next[3:0]$11395 + assign $2\reg$next[3:0]$11099 $1\reg$next[3:0]$11098 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11397 \w2__data_i + assign $3\reg$next[3:0]$11100 \w2__data_i case - assign $3\reg$next[3:0]$11397 $2\reg$next[3:0]$11396 + assign $3\reg$next[3:0]$11100 $2\reg$next[3:0]$11099 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11398 4'0000 + assign $4\reg$next[3:0]$11101 4'0000 case - assign $4\reg$next[3:0]$11398 $3\reg$next[3:0]$11397 + assign $4\reg$next[3:0]$11101 $3\reg$next[3:0]$11100 end sync always - update \reg$next $0\reg$next[3:0]$11394 + update \reg$next $0\reg$next[3:0]$11097 end - attribute \src "libresoc.v:183849.3-183888.6" - process $proc$libresoc.v:183849$11399 + attribute \src "libresoc.v:178044.3-178083.6" + process $proc$libresoc.v:178044$11102 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[3:0]$11400 $6\src22__data_o$next[3:0]$11406 - attribute \src "libresoc.v:183850.5-183850.29" + assign $0\src22__data_o$next[3:0]$11103 $6\src22__data_o$next[3:0]$11109 + attribute \src "libresoc.v:178045.5-178045.29" switch \initial - attribute \src "libresoc.v:183850.9-183850.17" + attribute \src "libresoc.v:178045.9-178045.17" case 1'1 case end @@ -376838,66 +367383,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[3:0]$11401 $5\src22__data_o$next[3:0]$11405 + assign $1\src22__data_o$next[3:0]$11104 $5\src22__data_o$next[3:0]$11108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[3:0]$11402 \dest12__data_i + assign $2\src22__data_o$next[3:0]$11105 \dest12__data_i case - assign $2\src22__data_o$next[3:0]$11402 4'0000 + assign $2\src22__data_o$next[3:0]$11105 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[3:0]$11403 \dest22__data_i + assign $3\src22__data_o$next[3:0]$11106 \dest22__data_i case - assign $3\src22__data_o$next[3:0]$11403 $2\src22__data_o$next[3:0]$11402 + assign $3\src22__data_o$next[3:0]$11106 $2\src22__data_o$next[3:0]$11105 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[3:0]$11404 \w2__data_i + assign $4\src22__data_o$next[3:0]$11107 \w2__data_i case - assign $4\src22__data_o$next[3:0]$11404 $3\src22__data_o$next[3:0]$11403 + assign $4\src22__data_o$next[3:0]$11107 $3\src22__data_o$next[3:0]$11106 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[3:0]$11405 \reg + assign $5\src22__data_o$next[3:0]$11108 \reg case - assign $5\src22__data_o$next[3:0]$11405 $4\src22__data_o$next[3:0]$11404 + assign $5\src22__data_o$next[3:0]$11108 $4\src22__data_o$next[3:0]$11107 end case - assign $1\src22__data_o$next[3:0]$11401 4'0000 + assign $1\src22__data_o$next[3:0]$11104 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[3:0]$11406 4'0000 + assign $6\src22__data_o$next[3:0]$11109 4'0000 case - assign $6\src22__data_o$next[3:0]$11406 $1\src22__data_o$next[3:0]$11401 + assign $6\src22__data_o$next[3:0]$11109 $1\src22__data_o$next[3:0]$11104 end sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$11400 + update \src22__data_o$next $0\src22__data_o$next[3:0]$11103 end - attribute \src "libresoc.v:183889.3-183918.6" - process $proc$libresoc.v:183889$11407 + attribute \src "libresoc.v:178084.3-178113.6" + process $proc$libresoc.v:178084$11110 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11408 $1\wr_detect$4[0:0]$11409 - attribute \src "libresoc.v:183890.5-183890.29" + assign $0\wr_detect$4[0:0]$11111 $1\wr_detect$4[0:0]$11112 + attribute \src "libresoc.v:178085.5-178085.29" switch \initial - attribute \src "libresoc.v:183890.9-183890.17" + attribute \src "libresoc.v:178085.9-178085.17" case 1'1 case end @@ -376909,49 +367454,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11409 $4\wr_detect$4[0:0]$11412 + assign $1\wr_detect$4[0:0]$11112 $4\wr_detect$4[0:0]$11115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11410 1'1 + assign $2\wr_detect$4[0:0]$11113 1'1 case - assign $2\wr_detect$4[0:0]$11410 1'0 + assign $2\wr_detect$4[0:0]$11113 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11411 1'1 + assign $3\wr_detect$4[0:0]$11114 1'1 case - assign $3\wr_detect$4[0:0]$11411 $2\wr_detect$4[0:0]$11410 + assign $3\wr_detect$4[0:0]$11114 $2\wr_detect$4[0:0]$11113 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11412 1'1 + assign $4\wr_detect$4[0:0]$11115 1'1 case - assign $4\wr_detect$4[0:0]$11412 $3\wr_detect$4[0:0]$11411 + assign $4\wr_detect$4[0:0]$11115 $3\wr_detect$4[0:0]$11114 end case - assign $1\wr_detect$4[0:0]$11409 1'0 + assign $1\wr_detect$4[0:0]$11112 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11408 + update \wr_detect$4 $0\wr_detect$4[0:0]$11111 end - attribute \src "libresoc.v:183919.3-183958.6" - process $proc$libresoc.v:183919$11413 + attribute \src "libresoc.v:178114.3-178153.6" + process $proc$libresoc.v:178114$11116 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[3:0]$11414 $6\src32__data_o$next[3:0]$11420 - attribute \src "libresoc.v:183920.5-183920.29" + assign $0\src32__data_o$next[3:0]$11117 $6\src32__data_o$next[3:0]$11123 + attribute \src "libresoc.v:178115.5-178115.29" switch \initial - attribute \src "libresoc.v:183920.9-183920.17" + attribute \src "libresoc.v:178115.9-178115.17" case 1'1 case end @@ -376963,66 +367508,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[3:0]$11415 $5\src32__data_o$next[3:0]$11419 + assign $1\src32__data_o$next[3:0]$11118 $5\src32__data_o$next[3:0]$11122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[3:0]$11416 \dest12__data_i + assign $2\src32__data_o$next[3:0]$11119 \dest12__data_i case - assign $2\src32__data_o$next[3:0]$11416 4'0000 + assign $2\src32__data_o$next[3:0]$11119 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[3:0]$11417 \dest22__data_i + assign $3\src32__data_o$next[3:0]$11120 \dest22__data_i case - assign $3\src32__data_o$next[3:0]$11417 $2\src32__data_o$next[3:0]$11416 + assign $3\src32__data_o$next[3:0]$11120 $2\src32__data_o$next[3:0]$11119 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[3:0]$11418 \w2__data_i + assign $4\src32__data_o$next[3:0]$11121 \w2__data_i case - assign $4\src32__data_o$next[3:0]$11418 $3\src32__data_o$next[3:0]$11417 + assign $4\src32__data_o$next[3:0]$11121 $3\src32__data_o$next[3:0]$11120 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[3:0]$11419 \reg + assign $5\src32__data_o$next[3:0]$11122 \reg case - assign $5\src32__data_o$next[3:0]$11419 $4\src32__data_o$next[3:0]$11418 + assign $5\src32__data_o$next[3:0]$11122 $4\src32__data_o$next[3:0]$11121 end case - assign $1\src32__data_o$next[3:0]$11415 4'0000 + assign $1\src32__data_o$next[3:0]$11118 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[3:0]$11420 4'0000 + assign $6\src32__data_o$next[3:0]$11123 4'0000 case - assign $6\src32__data_o$next[3:0]$11420 $1\src32__data_o$next[3:0]$11415 + assign $6\src32__data_o$next[3:0]$11123 $1\src32__data_o$next[3:0]$11118 end sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$11414 + update \src32__data_o$next $0\src32__data_o$next[3:0]$11117 end - attribute \src "libresoc.v:183959.3-183988.6" - process $proc$libresoc.v:183959$11421 + attribute \src "libresoc.v:178154.3-178183.6" + process $proc$libresoc.v:178154$11124 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11422 $1\wr_detect$7[0:0]$11423 - attribute \src "libresoc.v:183960.5-183960.29" + assign $0\wr_detect$7[0:0]$11125 $1\wr_detect$7[0:0]$11126 + attribute \src "libresoc.v:178155.5-178155.29" switch \initial - attribute \src "libresoc.v:183960.9-183960.17" + attribute \src "libresoc.v:178155.9-178155.17" case 1'1 case end @@ -377034,49 +367579,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11423 $4\wr_detect$7[0:0]$11426 + assign $1\wr_detect$7[0:0]$11126 $4\wr_detect$7[0:0]$11129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11424 1'1 + assign $2\wr_detect$7[0:0]$11127 1'1 case - assign $2\wr_detect$7[0:0]$11424 1'0 + assign $2\wr_detect$7[0:0]$11127 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11425 1'1 + assign $3\wr_detect$7[0:0]$11128 1'1 case - assign $3\wr_detect$7[0:0]$11425 $2\wr_detect$7[0:0]$11424 + assign $3\wr_detect$7[0:0]$11128 $2\wr_detect$7[0:0]$11127 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11426 1'1 + assign $4\wr_detect$7[0:0]$11129 1'1 case - assign $4\wr_detect$7[0:0]$11426 $3\wr_detect$7[0:0]$11425 + assign $4\wr_detect$7[0:0]$11129 $3\wr_detect$7[0:0]$11128 end case - assign $1\wr_detect$7[0:0]$11423 1'0 + assign $1\wr_detect$7[0:0]$11126 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11422 + update \wr_detect$7 $0\wr_detect$7[0:0]$11125 end - attribute \src "libresoc.v:183989.3-184028.6" - process $proc$libresoc.v:183989$11427 + attribute \src "libresoc.v:178184.3-178223.6" + process $proc$libresoc.v:178184$11130 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[3:0]$11428 $6\r2__data_o$next[3:0]$11434 - attribute \src "libresoc.v:183990.5-183990.29" + assign $0\r2__data_o$next[3:0]$11131 $6\r2__data_o$next[3:0]$11137 + attribute \src "libresoc.v:178185.5-178185.29" switch \initial - attribute \src "libresoc.v:183990.9-183990.17" + attribute \src "libresoc.v:178185.9-178185.17" case 1'1 case end @@ -377088,66 +367633,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[3:0]$11429 $5\r2__data_o$next[3:0]$11433 + assign $1\r2__data_o$next[3:0]$11132 $5\r2__data_o$next[3:0]$11136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[3:0]$11430 \dest12__data_i + assign $2\r2__data_o$next[3:0]$11133 \dest12__data_i case - assign $2\r2__data_o$next[3:0]$11430 4'0000 + assign $2\r2__data_o$next[3:0]$11133 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[3:0]$11431 \dest22__data_i + assign $3\r2__data_o$next[3:0]$11134 \dest22__data_i case - assign $3\r2__data_o$next[3:0]$11431 $2\r2__data_o$next[3:0]$11430 + assign $3\r2__data_o$next[3:0]$11134 $2\r2__data_o$next[3:0]$11133 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[3:0]$11432 \w2__data_i + assign $4\r2__data_o$next[3:0]$11135 \w2__data_i case - assign $4\r2__data_o$next[3:0]$11432 $3\r2__data_o$next[3:0]$11431 + assign $4\r2__data_o$next[3:0]$11135 $3\r2__data_o$next[3:0]$11134 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[3:0]$11433 \reg + assign $5\r2__data_o$next[3:0]$11136 \reg case - assign $5\r2__data_o$next[3:0]$11433 $4\r2__data_o$next[3:0]$11432 + assign $5\r2__data_o$next[3:0]$11136 $4\r2__data_o$next[3:0]$11135 end case - assign $1\r2__data_o$next[3:0]$11429 4'0000 + assign $1\r2__data_o$next[3:0]$11132 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[3:0]$11434 4'0000 + assign $6\r2__data_o$next[3:0]$11137 4'0000 case - assign $6\r2__data_o$next[3:0]$11434 $1\r2__data_o$next[3:0]$11429 + assign $6\r2__data_o$next[3:0]$11137 $1\r2__data_o$next[3:0]$11132 end sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$11428 + update \r2__data_o$next $0\r2__data_o$next[3:0]$11131 end - attribute \src "libresoc.v:184029.3-184058.6" - process $proc$libresoc.v:184029$11435 + attribute \src "libresoc.v:178224.3-178253.6" + process $proc$libresoc.v:178224$11138 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11436 $1\wr_detect$10[0:0]$11437 - attribute \src "libresoc.v:184030.5-184030.29" + assign $0\wr_detect$10[0:0]$11139 $1\wr_detect$10[0:0]$11140 + attribute \src "libresoc.v:178225.5-178225.29" switch \initial - attribute \src "libresoc.v:184030.9-184030.17" + attribute \src "libresoc.v:178225.9-178225.17" case 1'1 case end @@ -377159,49 +367704,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11437 $4\wr_detect$10[0:0]$11440 + assign $1\wr_detect$10[0:0]$11140 $4\wr_detect$10[0:0]$11143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11438 1'1 + assign $2\wr_detect$10[0:0]$11141 1'1 case - assign $2\wr_detect$10[0:0]$11438 1'0 + assign $2\wr_detect$10[0:0]$11141 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11439 1'1 + assign $3\wr_detect$10[0:0]$11142 1'1 case - assign $3\wr_detect$10[0:0]$11439 $2\wr_detect$10[0:0]$11438 + assign $3\wr_detect$10[0:0]$11142 $2\wr_detect$10[0:0]$11141 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11440 1'1 + assign $4\wr_detect$10[0:0]$11143 1'1 case - assign $4\wr_detect$10[0:0]$11440 $3\wr_detect$10[0:0]$11439 + assign $4\wr_detect$10[0:0]$11143 $3\wr_detect$10[0:0]$11142 end case - assign $1\wr_detect$10[0:0]$11437 1'0 + assign $1\wr_detect$10[0:0]$11140 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11436 + update \wr_detect$10 $0\wr_detect$10[0:0]$11139 end - attribute \src "libresoc.v:184059.3-184098.6" - process $proc$libresoc.v:184059$11441 + attribute \src "libresoc.v:178254.3-178293.6" + process $proc$libresoc.v:178254$11144 assign { } { } assign { } { } assign { } { } - assign $0\r22__data_o$next[3:0]$11442 $6\r22__data_o$next[3:0]$11448 - attribute \src "libresoc.v:184060.5-184060.29" + assign $0\r22__data_o$next[3:0]$11145 $6\r22__data_o$next[3:0]$11151 + attribute \src "libresoc.v:178255.5-178255.29" switch \initial - attribute \src "libresoc.v:184060.9-184060.17" + attribute \src "libresoc.v:178255.9-178255.17" case 1'1 case end @@ -377213,66 +367758,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r22__data_o$next[3:0]$11443 $5\r22__data_o$next[3:0]$11447 + assign $1\r22__data_o$next[3:0]$11146 $5\r22__data_o$next[3:0]$11150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r22__data_o$next[3:0]$11444 \dest12__data_i + assign $2\r22__data_o$next[3:0]$11147 \dest12__data_i case - assign $2\r22__data_o$next[3:0]$11444 4'0000 + assign $2\r22__data_o$next[3:0]$11147 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r22__data_o$next[3:0]$11445 \dest22__data_i + assign $3\r22__data_o$next[3:0]$11148 \dest22__data_i case - assign $3\r22__data_o$next[3:0]$11445 $2\r22__data_o$next[3:0]$11444 + assign $3\r22__data_o$next[3:0]$11148 $2\r22__data_o$next[3:0]$11147 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r22__data_o$next[3:0]$11446 \w2__data_i + assign $4\r22__data_o$next[3:0]$11149 \w2__data_i case - assign $4\r22__data_o$next[3:0]$11446 $3\r22__data_o$next[3:0]$11445 + assign $4\r22__data_o$next[3:0]$11149 $3\r22__data_o$next[3:0]$11148 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r22__data_o$next[3:0]$11447 \reg + assign $5\r22__data_o$next[3:0]$11150 \reg case - assign $5\r22__data_o$next[3:0]$11447 $4\r22__data_o$next[3:0]$11446 + assign $5\r22__data_o$next[3:0]$11150 $4\r22__data_o$next[3:0]$11149 end case - assign $1\r22__data_o$next[3:0]$11443 4'0000 + assign $1\r22__data_o$next[3:0]$11146 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r22__data_o$next[3:0]$11448 4'0000 + assign $6\r22__data_o$next[3:0]$11151 4'0000 case - assign $6\r22__data_o$next[3:0]$11448 $1\r22__data_o$next[3:0]$11443 + assign $6\r22__data_o$next[3:0]$11151 $1\r22__data_o$next[3:0]$11146 end sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$11442 + update \r22__data_o$next $0\r22__data_o$next[3:0]$11145 end - attribute \src "libresoc.v:184099.3-184128.6" - process $proc$libresoc.v:184099$11449 + attribute \src "libresoc.v:178294.3-178323.6" + process $proc$libresoc.v:178294$11152 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11450 $1\wr_detect$13[0:0]$11451 - attribute \src "libresoc.v:184100.5-184100.29" + assign $0\wr_detect$13[0:0]$11153 $1\wr_detect$13[0:0]$11154 + attribute \src "libresoc.v:178295.5-178295.29" switch \initial - attribute \src "libresoc.v:184100.9-184100.17" + attribute \src "libresoc.v:178295.9-178295.17" case 1'1 case end @@ -377284,205 +367829,205 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11451 $4\wr_detect$13[0:0]$11454 + assign $1\wr_detect$13[0:0]$11154 $4\wr_detect$13[0:0]$11157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11452 1'1 + assign $2\wr_detect$13[0:0]$11155 1'1 case - assign $2\wr_detect$13[0:0]$11452 1'0 + assign $2\wr_detect$13[0:0]$11155 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11453 1'1 + assign $3\wr_detect$13[0:0]$11156 1'1 case - assign $3\wr_detect$13[0:0]$11453 $2\wr_detect$13[0:0]$11452 + assign $3\wr_detect$13[0:0]$11156 $2\wr_detect$13[0:0]$11155 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11454 1'1 + assign $4\wr_detect$13[0:0]$11157 1'1 case - assign $4\wr_detect$13[0:0]$11454 $3\wr_detect$13[0:0]$11453 + assign $4\wr_detect$13[0:0]$11157 $3\wr_detect$13[0:0]$11156 end case - assign $1\wr_detect$13[0:0]$11451 1'0 + assign $1\wr_detect$13[0:0]$11154 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11450 + update \wr_detect$13 $0\wr_detect$13[0:0]$11153 end - connect \$9 $not$libresoc.v:183735$11373_Y - connect \$12 $not$libresoc.v:183736$11374_Y - connect \$1 $not$libresoc.v:183737$11375_Y - connect \$3 $not$libresoc.v:183738$11376_Y - connect \$6 $not$libresoc.v:183739$11377_Y + connect \$9 $not$libresoc.v:177930$11076_Y + connect \$12 $not$libresoc.v:177931$11077_Y + connect \$1 $not$libresoc.v:177932$11078_Y + connect \$3 $not$libresoc.v:177933$11079_Y + connect \$6 $not$libresoc.v:177934$11080_Y end -attribute \src "libresoc.v:184133.1-184578.10" +attribute \src "libresoc.v:178328.1-178773.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" module \reg_2$134 - attribute \src "libresoc.v:184134.7-184134.20" + attribute \src "libresoc.v:178329.7-178329.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184463.3-184508.6" - wire width 2 $0\r2__data_o$next[1:0]$11514 - attribute \src "libresoc.v:184209.3-184210.37" + attribute \src "libresoc.v:178658.3-178703.6" + wire width 2 $0\r2__data_o$next[1:0]$11217 + attribute \src "libresoc.v:178404.3-178405.37" wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:184545.3-184577.6" - wire width 2 $0\reg$next[1:0]$11530 - attribute \src "libresoc.v:184207.3-184208.25" + attribute \src "libresoc.v:178740.3-178772.6" + wire width 2 $0\reg$next[1:0]$11233 + attribute \src "libresoc.v:178402.3-178403.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:184217.3-184262.6" - wire width 2 $0\src12__data_o$next[1:0]$11472 - attribute \src "libresoc.v:184215.3-184216.43" + attribute \src "libresoc.v:178412.3-178457.6" + wire width 2 $0\src12__data_o$next[1:0]$11175 + attribute \src "libresoc.v:178410.3-178411.43" wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:184299.3-184344.6" - wire width 2 $0\src22__data_o$next[1:0]$11482 - attribute \src "libresoc.v:184213.3-184214.43" + attribute \src "libresoc.v:178494.3-178539.6" + wire width 2 $0\src22__data_o$next[1:0]$11185 + attribute \src "libresoc.v:178408.3-178409.43" wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:184381.3-184426.6" - wire width 2 $0\src32__data_o$next[1:0]$11498 - attribute \src "libresoc.v:184211.3-184212.43" + attribute \src "libresoc.v:178576.3-178621.6" + wire width 2 $0\src32__data_o$next[1:0]$11201 + attribute \src "libresoc.v:178406.3-178407.43" wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:184509.3-184544.6" - wire $0\wr_detect$10[0:0]$11523 - attribute \src "libresoc.v:184345.3-184380.6" - wire $0\wr_detect$4[0:0]$11491 - attribute \src "libresoc.v:184427.3-184462.6" - wire $0\wr_detect$7[0:0]$11507 - attribute \src "libresoc.v:184263.3-184298.6" + attribute \src "libresoc.v:178704.3-178739.6" + wire $0\wr_detect$10[0:0]$11226 + attribute \src "libresoc.v:178540.3-178575.6" + wire $0\wr_detect$4[0:0]$11194 + attribute \src "libresoc.v:178622.3-178657.6" + wire $0\wr_detect$7[0:0]$11210 + attribute \src "libresoc.v:178458.3-178493.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:184463.3-184508.6" - wire width 2 $1\r2__data_o$next[1:0]$11515 - attribute \src "libresoc.v:184161.13-184161.30" + attribute \src "libresoc.v:178658.3-178703.6" + wire width 2 $1\r2__data_o$next[1:0]$11218 + attribute \src "libresoc.v:178356.13-178356.30" wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:184545.3-184577.6" - wire width 2 $1\reg$next[1:0]$11531 - attribute \src "libresoc.v:184167.13-184167.25" + attribute \src "libresoc.v:178740.3-178772.6" + wire width 2 $1\reg$next[1:0]$11234 + attribute \src "libresoc.v:178362.13-178362.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:184217.3-184262.6" - wire width 2 $1\src12__data_o$next[1:0]$11473 - attribute \src "libresoc.v:184172.13-184172.33" + attribute \src "libresoc.v:178412.3-178457.6" + wire width 2 $1\src12__data_o$next[1:0]$11176 + attribute \src "libresoc.v:178367.13-178367.33" wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:184299.3-184344.6" - wire width 2 $1\src22__data_o$next[1:0]$11483 - attribute \src "libresoc.v:184179.13-184179.33" + attribute \src "libresoc.v:178494.3-178539.6" + wire width 2 $1\src22__data_o$next[1:0]$11186 + attribute \src "libresoc.v:178374.13-178374.33" wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:184381.3-184426.6" - wire width 2 $1\src32__data_o$next[1:0]$11499 - attribute \src "libresoc.v:184186.13-184186.33" + attribute \src "libresoc.v:178576.3-178621.6" + wire width 2 $1\src32__data_o$next[1:0]$11202 + attribute \src "libresoc.v:178381.13-178381.33" wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:184509.3-184544.6" - wire $1\wr_detect$10[0:0]$11524 - attribute \src "libresoc.v:184345.3-184380.6" - wire $1\wr_detect$4[0:0]$11492 - attribute \src "libresoc.v:184427.3-184462.6" - wire $1\wr_detect$7[0:0]$11508 - attribute \src "libresoc.v:184263.3-184298.6" + attribute \src "libresoc.v:178704.3-178739.6" + wire $1\wr_detect$10[0:0]$11227 + attribute \src "libresoc.v:178540.3-178575.6" + wire $1\wr_detect$4[0:0]$11195 + attribute \src "libresoc.v:178622.3-178657.6" + wire $1\wr_detect$7[0:0]$11211 + attribute \src "libresoc.v:178458.3-178493.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:184463.3-184508.6" - wire width 2 $2\r2__data_o$next[1:0]$11516 - attribute \src "libresoc.v:184545.3-184577.6" - wire width 2 $2\reg$next[1:0]$11532 - attribute \src "libresoc.v:184217.3-184262.6" - wire width 2 $2\src12__data_o$next[1:0]$11474 - attribute \src "libresoc.v:184299.3-184344.6" - wire width 2 $2\src22__data_o$next[1:0]$11484 - attribute \src "libresoc.v:184381.3-184426.6" - wire width 2 $2\src32__data_o$next[1:0]$11500 - attribute \src "libresoc.v:184509.3-184544.6" - wire $2\wr_detect$10[0:0]$11525 - attribute \src "libresoc.v:184345.3-184380.6" - wire $2\wr_detect$4[0:0]$11493 - attribute \src "libresoc.v:184427.3-184462.6" - wire $2\wr_detect$7[0:0]$11509 - attribute \src "libresoc.v:184263.3-184298.6" + attribute \src "libresoc.v:178658.3-178703.6" + wire width 2 $2\r2__data_o$next[1:0]$11219 + attribute \src "libresoc.v:178740.3-178772.6" + wire width 2 $2\reg$next[1:0]$11235 + attribute \src "libresoc.v:178412.3-178457.6" + wire width 2 $2\src12__data_o$next[1:0]$11177 + attribute \src "libresoc.v:178494.3-178539.6" + wire width 2 $2\src22__data_o$next[1:0]$11187 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 2 $2\src32__data_o$next[1:0]$11203 + attribute \src "libresoc.v:178704.3-178739.6" + wire $2\wr_detect$10[0:0]$11228 + attribute \src "libresoc.v:178540.3-178575.6" + wire $2\wr_detect$4[0:0]$11196 + attribute \src "libresoc.v:178622.3-178657.6" + wire $2\wr_detect$7[0:0]$11212 + attribute \src "libresoc.v:178458.3-178493.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:184463.3-184508.6" - wire width 2 $3\r2__data_o$next[1:0]$11517 - attribute \src "libresoc.v:184545.3-184577.6" - wire width 2 $3\reg$next[1:0]$11533 - attribute \src "libresoc.v:184217.3-184262.6" - wire width 2 $3\src12__data_o$next[1:0]$11475 - attribute \src "libresoc.v:184299.3-184344.6" - wire width 2 $3\src22__data_o$next[1:0]$11485 - attribute \src "libresoc.v:184381.3-184426.6" - wire width 2 $3\src32__data_o$next[1:0]$11501 - attribute \src "libresoc.v:184509.3-184544.6" - wire $3\wr_detect$10[0:0]$11526 - attribute \src "libresoc.v:184345.3-184380.6" - wire $3\wr_detect$4[0:0]$11494 - attribute \src "libresoc.v:184427.3-184462.6" - wire $3\wr_detect$7[0:0]$11510 - attribute \src "libresoc.v:184263.3-184298.6" + attribute \src "libresoc.v:178658.3-178703.6" + wire width 2 $3\r2__data_o$next[1:0]$11220 + attribute \src "libresoc.v:178740.3-178772.6" + wire width 2 $3\reg$next[1:0]$11236 + attribute \src "libresoc.v:178412.3-178457.6" + wire width 2 $3\src12__data_o$next[1:0]$11178 + attribute \src "libresoc.v:178494.3-178539.6" + wire width 2 $3\src22__data_o$next[1:0]$11188 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 2 $3\src32__data_o$next[1:0]$11204 + attribute \src "libresoc.v:178704.3-178739.6" + wire $3\wr_detect$10[0:0]$11229 + attribute \src "libresoc.v:178540.3-178575.6" + wire $3\wr_detect$4[0:0]$11197 + attribute \src "libresoc.v:178622.3-178657.6" + wire $3\wr_detect$7[0:0]$11213 + attribute \src "libresoc.v:178458.3-178493.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:184463.3-184508.6" - wire width 2 $4\r2__data_o$next[1:0]$11518 - attribute \src "libresoc.v:184545.3-184577.6" - wire width 2 $4\reg$next[1:0]$11534 - attribute \src "libresoc.v:184217.3-184262.6" - wire width 2 $4\src12__data_o$next[1:0]$11476 - attribute \src "libresoc.v:184299.3-184344.6" - wire width 2 $4\src22__data_o$next[1:0]$11486 - attribute \src "libresoc.v:184381.3-184426.6" - wire width 2 $4\src32__data_o$next[1:0]$11502 - attribute \src "libresoc.v:184509.3-184544.6" - wire $4\wr_detect$10[0:0]$11527 - attribute \src "libresoc.v:184345.3-184380.6" - wire $4\wr_detect$4[0:0]$11495 - attribute \src "libresoc.v:184427.3-184462.6" - wire $4\wr_detect$7[0:0]$11511 - attribute \src "libresoc.v:184263.3-184298.6" + attribute \src "libresoc.v:178658.3-178703.6" + wire width 2 $4\r2__data_o$next[1:0]$11221 + attribute \src "libresoc.v:178740.3-178772.6" + wire width 2 $4\reg$next[1:0]$11237 + attribute \src "libresoc.v:178412.3-178457.6" + wire width 2 $4\src12__data_o$next[1:0]$11179 + attribute \src "libresoc.v:178494.3-178539.6" + wire width 2 $4\src22__data_o$next[1:0]$11189 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 2 $4\src32__data_o$next[1:0]$11205 + attribute \src "libresoc.v:178704.3-178739.6" + wire $4\wr_detect$10[0:0]$11230 + attribute \src "libresoc.v:178540.3-178575.6" + wire $4\wr_detect$4[0:0]$11198 + attribute \src "libresoc.v:178622.3-178657.6" + wire $4\wr_detect$7[0:0]$11214 + attribute \src "libresoc.v:178458.3-178493.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:184463.3-184508.6" - wire width 2 $5\r2__data_o$next[1:0]$11519 - attribute \src "libresoc.v:184545.3-184577.6" - wire width 2 $5\reg$next[1:0]$11535 - attribute \src "libresoc.v:184217.3-184262.6" - wire width 2 $5\src12__data_o$next[1:0]$11477 - attribute \src "libresoc.v:184299.3-184344.6" - wire width 2 $5\src22__data_o$next[1:0]$11487 - attribute \src "libresoc.v:184381.3-184426.6" - wire width 2 $5\src32__data_o$next[1:0]$11503 - attribute \src "libresoc.v:184509.3-184544.6" - wire $5\wr_detect$10[0:0]$11528 - attribute \src "libresoc.v:184345.3-184380.6" - wire $5\wr_detect$4[0:0]$11496 - attribute \src "libresoc.v:184427.3-184462.6" - wire $5\wr_detect$7[0:0]$11512 - attribute \src "libresoc.v:184263.3-184298.6" + attribute \src "libresoc.v:178658.3-178703.6" + wire width 2 $5\r2__data_o$next[1:0]$11222 + attribute \src "libresoc.v:178740.3-178772.6" + wire width 2 $5\reg$next[1:0]$11238 + attribute \src "libresoc.v:178412.3-178457.6" + wire width 2 $5\src12__data_o$next[1:0]$11180 + attribute \src "libresoc.v:178494.3-178539.6" + wire width 2 $5\src22__data_o$next[1:0]$11190 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 2 $5\src32__data_o$next[1:0]$11206 + attribute \src "libresoc.v:178704.3-178739.6" + wire $5\wr_detect$10[0:0]$11231 + attribute \src "libresoc.v:178540.3-178575.6" + wire $5\wr_detect$4[0:0]$11199 + attribute \src "libresoc.v:178622.3-178657.6" + wire $5\wr_detect$7[0:0]$11215 + attribute \src "libresoc.v:178458.3-178493.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:184463.3-184508.6" - wire width 2 $6\r2__data_o$next[1:0]$11520 - attribute \src "libresoc.v:184217.3-184262.6" - wire width 2 $6\src12__data_o$next[1:0]$11478 - attribute \src "libresoc.v:184299.3-184344.6" - wire width 2 $6\src22__data_o$next[1:0]$11488 - attribute \src "libresoc.v:184381.3-184426.6" - wire width 2 $6\src32__data_o$next[1:0]$11504 - attribute \src "libresoc.v:184463.3-184508.6" - wire width 2 $7\r2__data_o$next[1:0]$11521 - attribute \src "libresoc.v:184217.3-184262.6" - wire width 2 $7\src12__data_o$next[1:0]$11479 - attribute \src "libresoc.v:184299.3-184344.6" - wire width 2 $7\src22__data_o$next[1:0]$11489 - attribute \src "libresoc.v:184381.3-184426.6" - wire width 2 $7\src32__data_o$next[1:0]$11505 - attribute \src "libresoc.v:184203.17-184203.104" - wire $not$libresoc.v:184203$11462_Y - attribute \src "libresoc.v:184204.17-184204.100" - wire $not$libresoc.v:184204$11463_Y - attribute \src "libresoc.v:184205.17-184205.103" - wire $not$libresoc.v:184205$11464_Y - attribute \src "libresoc.v:184206.17-184206.103" - wire $not$libresoc.v:184206$11465_Y + attribute \src "libresoc.v:178658.3-178703.6" + wire width 2 $6\r2__data_o$next[1:0]$11223 + attribute \src "libresoc.v:178412.3-178457.6" + wire width 2 $6\src12__data_o$next[1:0]$11181 + attribute \src "libresoc.v:178494.3-178539.6" + wire width 2 $6\src22__data_o$next[1:0]$11191 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 2 $6\src32__data_o$next[1:0]$11207 + attribute \src "libresoc.v:178658.3-178703.6" + wire width 2 $7\r2__data_o$next[1:0]$11224 + attribute \src "libresoc.v:178412.3-178457.6" + wire width 2 $7\src12__data_o$next[1:0]$11182 + attribute \src "libresoc.v:178494.3-178539.6" + wire width 2 $7\src22__data_o$next[1:0]$11192 + attribute \src "libresoc.v:178576.3-178621.6" + wire width 2 $7\src32__data_o$next[1:0]$11208 + attribute \src "libresoc.v:178398.17-178398.104" + wire $not$libresoc.v:178398$11165_Y + attribute \src "libresoc.v:178399.17-178399.100" + wire $not$libresoc.v:178399$11166_Y + attribute \src "libresoc.v:178400.17-178400.103" + wire $not$libresoc.v:178400$11167_Y + attribute \src "libresoc.v:178401.17-178401.103" + wire $not$libresoc.v:178401$11168_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -377491,9 +368036,9 @@ module \reg_2$134 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest12__data_i @@ -377507,7 +368052,7 @@ module \reg_2$134 wire width 2 input 13 \dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest32__wen - attribute \src "libresoc.v:184134.7-184134.15" + attribute \src "libresoc.v:178329.7-178329.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r2__data_o @@ -377550,129 +368095,129 @@ module \reg_2$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:184203$11462 + cell $not $not$libresoc.v:178398$11165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:184203$11462_Y + connect \Y $not$libresoc.v:178398$11165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:184204$11463 + cell $not $not$libresoc.v:178399$11166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:184204$11463_Y + connect \Y $not$libresoc.v:178399$11166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:184205$11464 + cell $not $not$libresoc.v:178400$11167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:184205$11464_Y + connect \Y $not$libresoc.v:178400$11167_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:184206$11465 + cell $not $not$libresoc.v:178401$11168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:184206$11465_Y + connect \Y $not$libresoc.v:178401$11168_Y end - attribute \src "libresoc.v:184134.7-184134.20" - process $proc$libresoc.v:184134$11536 + attribute \src "libresoc.v:178329.7-178329.20" + process $proc$libresoc.v:178329$11239 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184161.13-184161.30" - process $proc$libresoc.v:184161$11537 + attribute \src "libresoc.v:178356.13-178356.30" + process $proc$libresoc.v:178356$11240 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end - attribute \src "libresoc.v:184167.13-184167.25" - process $proc$libresoc.v:184167$11538 + attribute \src "libresoc.v:178362.13-178362.25" + process $proc$libresoc.v:178362$11241 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:184172.13-184172.33" - process $proc$libresoc.v:184172$11539 + attribute \src "libresoc.v:178367.13-178367.33" + process $proc$libresoc.v:178367$11242 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end - attribute \src "libresoc.v:184179.13-184179.33" - process $proc$libresoc.v:184179$11540 + attribute \src "libresoc.v:178374.13-178374.33" + process $proc$libresoc.v:178374$11243 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end - attribute \src "libresoc.v:184186.13-184186.33" - process $proc$libresoc.v:184186$11541 + attribute \src "libresoc.v:178381.13-178381.33" + process $proc$libresoc.v:178381$11244 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end - attribute \src "libresoc.v:184207.3-184208.25" - process $proc$libresoc.v:184207$11466 + attribute \src "libresoc.v:178402.3-178403.25" + process $proc$libresoc.v:178402$11169 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:184209.3-184210.37" - process $proc$libresoc.v:184209$11467 + attribute \src "libresoc.v:178404.3-178405.37" + process $proc$libresoc.v:178404$11170 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end - attribute \src "libresoc.v:184211.3-184212.43" - process $proc$libresoc.v:184211$11468 + attribute \src "libresoc.v:178406.3-178407.43" + process $proc$libresoc.v:178406$11171 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end - attribute \src "libresoc.v:184213.3-184214.43" - process $proc$libresoc.v:184213$11469 + attribute \src "libresoc.v:178408.3-178409.43" + process $proc$libresoc.v:178408$11172 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end - attribute \src "libresoc.v:184215.3-184216.43" - process $proc$libresoc.v:184215$11470 + attribute \src "libresoc.v:178410.3-178411.43" + process $proc$libresoc.v:178410$11173 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end - attribute \src "libresoc.v:184217.3-184262.6" - process $proc$libresoc.v:184217$11471 + attribute \src "libresoc.v:178412.3-178457.6" + process $proc$libresoc.v:178412$11174 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[1:0]$11472 $7\src12__data_o$next[1:0]$11479 - attribute \src "libresoc.v:184218.5-184218.29" + assign $0\src12__data_o$next[1:0]$11175 $7\src12__data_o$next[1:0]$11182 + attribute \src "libresoc.v:178413.5-178413.29" switch \initial - attribute \src "libresoc.v:184218.9-184218.17" + attribute \src "libresoc.v:178413.9-178413.17" case 1'1 case end @@ -377685,75 +368230,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[1:0]$11473 $6\src12__data_o$next[1:0]$11478 + assign $1\src12__data_o$next[1:0]$11176 $6\src12__data_o$next[1:0]$11181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[1:0]$11474 \dest12__data_i + assign $2\src12__data_o$next[1:0]$11177 \dest12__data_i case - assign $2\src12__data_o$next[1:0]$11474 2'00 + assign $2\src12__data_o$next[1:0]$11177 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[1:0]$11475 \dest22__data_i + assign $3\src12__data_o$next[1:0]$11178 \dest22__data_i case - assign $3\src12__data_o$next[1:0]$11475 $2\src12__data_o$next[1:0]$11474 + assign $3\src12__data_o$next[1:0]$11178 $2\src12__data_o$next[1:0]$11177 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[1:0]$11476 \dest32__data_i + assign $4\src12__data_o$next[1:0]$11179 \dest32__data_i case - assign $4\src12__data_o$next[1:0]$11476 $3\src12__data_o$next[1:0]$11475 + assign $4\src12__data_o$next[1:0]$11179 $3\src12__data_o$next[1:0]$11178 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[1:0]$11477 \w2__data_i + assign $5\src12__data_o$next[1:0]$11180 \w2__data_i case - assign $5\src12__data_o$next[1:0]$11477 $4\src12__data_o$next[1:0]$11476 + assign $5\src12__data_o$next[1:0]$11180 $4\src12__data_o$next[1:0]$11179 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[1:0]$11478 \reg + assign $6\src12__data_o$next[1:0]$11181 \reg case - assign $6\src12__data_o$next[1:0]$11478 $5\src12__data_o$next[1:0]$11477 + assign $6\src12__data_o$next[1:0]$11181 $5\src12__data_o$next[1:0]$11180 end case - assign $1\src12__data_o$next[1:0]$11473 2'00 + assign $1\src12__data_o$next[1:0]$11176 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src12__data_o$next[1:0]$11479 2'00 + assign $7\src12__data_o$next[1:0]$11182 2'00 case - assign $7\src12__data_o$next[1:0]$11479 $1\src12__data_o$next[1:0]$11473 + assign $7\src12__data_o$next[1:0]$11182 $1\src12__data_o$next[1:0]$11176 end sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$11472 + update \src12__data_o$next $0\src12__data_o$next[1:0]$11175 end - attribute \src "libresoc.v:184263.3-184298.6" - process $proc$libresoc.v:184263$11480 + attribute \src "libresoc.v:178458.3-178493.6" + process $proc$libresoc.v:178458$11183 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:184264.5-184264.29" + attribute \src "libresoc.v:178459.5-178459.29" switch \initial - attribute \src "libresoc.v:184264.9-184264.17" + attribute \src "libresoc.v:178459.9-178459.17" case 1'1 case end @@ -377809,15 +368354,15 @@ module \reg_2$134 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:184299.3-184344.6" - process $proc$libresoc.v:184299$11481 + attribute \src "libresoc.v:178494.3-178539.6" + process $proc$libresoc.v:178494$11184 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[1:0]$11482 $7\src22__data_o$next[1:0]$11489 - attribute \src "libresoc.v:184300.5-184300.29" + assign $0\src22__data_o$next[1:0]$11185 $7\src22__data_o$next[1:0]$11192 + attribute \src "libresoc.v:178495.5-178495.29" switch \initial - attribute \src "libresoc.v:184300.9-184300.17" + attribute \src "libresoc.v:178495.9-178495.17" case 1'1 case end @@ -377830,75 +368375,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[1:0]$11483 $6\src22__data_o$next[1:0]$11488 + assign $1\src22__data_o$next[1:0]$11186 $6\src22__data_o$next[1:0]$11191 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[1:0]$11484 \dest12__data_i + assign $2\src22__data_o$next[1:0]$11187 \dest12__data_i case - assign $2\src22__data_o$next[1:0]$11484 2'00 + assign $2\src22__data_o$next[1:0]$11187 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[1:0]$11485 \dest22__data_i + assign $3\src22__data_o$next[1:0]$11188 \dest22__data_i case - assign $3\src22__data_o$next[1:0]$11485 $2\src22__data_o$next[1:0]$11484 + assign $3\src22__data_o$next[1:0]$11188 $2\src22__data_o$next[1:0]$11187 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[1:0]$11486 \dest32__data_i + assign $4\src22__data_o$next[1:0]$11189 \dest32__data_i case - assign $4\src22__data_o$next[1:0]$11486 $3\src22__data_o$next[1:0]$11485 + assign $4\src22__data_o$next[1:0]$11189 $3\src22__data_o$next[1:0]$11188 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[1:0]$11487 \w2__data_i + assign $5\src22__data_o$next[1:0]$11190 \w2__data_i case - assign $5\src22__data_o$next[1:0]$11487 $4\src22__data_o$next[1:0]$11486 + assign $5\src22__data_o$next[1:0]$11190 $4\src22__data_o$next[1:0]$11189 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[1:0]$11488 \reg + assign $6\src22__data_o$next[1:0]$11191 \reg case - assign $6\src22__data_o$next[1:0]$11488 $5\src22__data_o$next[1:0]$11487 + assign $6\src22__data_o$next[1:0]$11191 $5\src22__data_o$next[1:0]$11190 end case - assign $1\src22__data_o$next[1:0]$11483 2'00 + assign $1\src22__data_o$next[1:0]$11186 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src22__data_o$next[1:0]$11489 2'00 + assign $7\src22__data_o$next[1:0]$11192 2'00 case - assign $7\src22__data_o$next[1:0]$11489 $1\src22__data_o$next[1:0]$11483 + assign $7\src22__data_o$next[1:0]$11192 $1\src22__data_o$next[1:0]$11186 end sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$11482 + update \src22__data_o$next $0\src22__data_o$next[1:0]$11185 end - attribute \src "libresoc.v:184345.3-184380.6" - process $proc$libresoc.v:184345$11490 + attribute \src "libresoc.v:178540.3-178575.6" + process $proc$libresoc.v:178540$11193 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11491 $1\wr_detect$4[0:0]$11492 - attribute \src "libresoc.v:184346.5-184346.29" + assign $0\wr_detect$4[0:0]$11194 $1\wr_detect$4[0:0]$11195 + attribute \src "libresoc.v:178541.5-178541.29" switch \initial - attribute \src "libresoc.v:184346.9-184346.17" + attribute \src "libresoc.v:178541.9-178541.17" case 1'1 case end @@ -377911,58 +368456,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11492 $5\wr_detect$4[0:0]$11496 + assign $1\wr_detect$4[0:0]$11195 $5\wr_detect$4[0:0]$11199 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11493 1'1 + assign $2\wr_detect$4[0:0]$11196 1'1 case - assign $2\wr_detect$4[0:0]$11493 1'0 + assign $2\wr_detect$4[0:0]$11196 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11494 1'1 + assign $3\wr_detect$4[0:0]$11197 1'1 case - assign $3\wr_detect$4[0:0]$11494 $2\wr_detect$4[0:0]$11493 + assign $3\wr_detect$4[0:0]$11197 $2\wr_detect$4[0:0]$11196 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11495 1'1 + assign $4\wr_detect$4[0:0]$11198 1'1 case - assign $4\wr_detect$4[0:0]$11495 $3\wr_detect$4[0:0]$11494 + assign $4\wr_detect$4[0:0]$11198 $3\wr_detect$4[0:0]$11197 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11496 1'1 + assign $5\wr_detect$4[0:0]$11199 1'1 case - assign $5\wr_detect$4[0:0]$11496 $4\wr_detect$4[0:0]$11495 + assign $5\wr_detect$4[0:0]$11199 $4\wr_detect$4[0:0]$11198 end case - assign $1\wr_detect$4[0:0]$11492 1'0 + assign $1\wr_detect$4[0:0]$11195 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11491 + update \wr_detect$4 $0\wr_detect$4[0:0]$11194 end - attribute \src "libresoc.v:184381.3-184426.6" - process $proc$libresoc.v:184381$11497 + attribute \src "libresoc.v:178576.3-178621.6" + process $proc$libresoc.v:178576$11200 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[1:0]$11498 $7\src32__data_o$next[1:0]$11505 - attribute \src "libresoc.v:184382.5-184382.29" + assign $0\src32__data_o$next[1:0]$11201 $7\src32__data_o$next[1:0]$11208 + attribute \src "libresoc.v:178577.5-178577.29" switch \initial - attribute \src "libresoc.v:184382.9-184382.17" + attribute \src "libresoc.v:178577.9-178577.17" case 1'1 case end @@ -377975,75 +368520,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[1:0]$11499 $6\src32__data_o$next[1:0]$11504 + assign $1\src32__data_o$next[1:0]$11202 $6\src32__data_o$next[1:0]$11207 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[1:0]$11500 \dest12__data_i + assign $2\src32__data_o$next[1:0]$11203 \dest12__data_i case - assign $2\src32__data_o$next[1:0]$11500 2'00 + assign $2\src32__data_o$next[1:0]$11203 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[1:0]$11501 \dest22__data_i + assign $3\src32__data_o$next[1:0]$11204 \dest22__data_i case - assign $3\src32__data_o$next[1:0]$11501 $2\src32__data_o$next[1:0]$11500 + assign $3\src32__data_o$next[1:0]$11204 $2\src32__data_o$next[1:0]$11203 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[1:0]$11502 \dest32__data_i + assign $4\src32__data_o$next[1:0]$11205 \dest32__data_i case - assign $4\src32__data_o$next[1:0]$11502 $3\src32__data_o$next[1:0]$11501 + assign $4\src32__data_o$next[1:0]$11205 $3\src32__data_o$next[1:0]$11204 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[1:0]$11503 \w2__data_i + assign $5\src32__data_o$next[1:0]$11206 \w2__data_i case - assign $5\src32__data_o$next[1:0]$11503 $4\src32__data_o$next[1:0]$11502 + assign $5\src32__data_o$next[1:0]$11206 $4\src32__data_o$next[1:0]$11205 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[1:0]$11504 \reg + assign $6\src32__data_o$next[1:0]$11207 \reg case - assign $6\src32__data_o$next[1:0]$11504 $5\src32__data_o$next[1:0]$11503 + assign $6\src32__data_o$next[1:0]$11207 $5\src32__data_o$next[1:0]$11206 end case - assign $1\src32__data_o$next[1:0]$11499 2'00 + assign $1\src32__data_o$next[1:0]$11202 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src32__data_o$next[1:0]$11505 2'00 + assign $7\src32__data_o$next[1:0]$11208 2'00 case - assign $7\src32__data_o$next[1:0]$11505 $1\src32__data_o$next[1:0]$11499 + assign $7\src32__data_o$next[1:0]$11208 $1\src32__data_o$next[1:0]$11202 end sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$11498 + update \src32__data_o$next $0\src32__data_o$next[1:0]$11201 end - attribute \src "libresoc.v:184427.3-184462.6" - process $proc$libresoc.v:184427$11506 + attribute \src "libresoc.v:178622.3-178657.6" + process $proc$libresoc.v:178622$11209 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11507 $1\wr_detect$7[0:0]$11508 - attribute \src "libresoc.v:184428.5-184428.29" + assign $0\wr_detect$7[0:0]$11210 $1\wr_detect$7[0:0]$11211 + attribute \src "libresoc.v:178623.5-178623.29" switch \initial - attribute \src "libresoc.v:184428.9-184428.17" + attribute \src "libresoc.v:178623.9-178623.17" case 1'1 case end @@ -378056,58 +368601,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11508 $5\wr_detect$7[0:0]$11512 + assign $1\wr_detect$7[0:0]$11211 $5\wr_detect$7[0:0]$11215 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11509 1'1 + assign $2\wr_detect$7[0:0]$11212 1'1 case - assign $2\wr_detect$7[0:0]$11509 1'0 + assign $2\wr_detect$7[0:0]$11212 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11510 1'1 + assign $3\wr_detect$7[0:0]$11213 1'1 case - assign $3\wr_detect$7[0:0]$11510 $2\wr_detect$7[0:0]$11509 + assign $3\wr_detect$7[0:0]$11213 $2\wr_detect$7[0:0]$11212 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11511 1'1 + assign $4\wr_detect$7[0:0]$11214 1'1 case - assign $4\wr_detect$7[0:0]$11511 $3\wr_detect$7[0:0]$11510 + assign $4\wr_detect$7[0:0]$11214 $3\wr_detect$7[0:0]$11213 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11512 1'1 + assign $5\wr_detect$7[0:0]$11215 1'1 case - assign $5\wr_detect$7[0:0]$11512 $4\wr_detect$7[0:0]$11511 + assign $5\wr_detect$7[0:0]$11215 $4\wr_detect$7[0:0]$11214 end case - assign $1\wr_detect$7[0:0]$11508 1'0 + assign $1\wr_detect$7[0:0]$11211 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11507 + update \wr_detect$7 $0\wr_detect$7[0:0]$11210 end - attribute \src "libresoc.v:184463.3-184508.6" - process $proc$libresoc.v:184463$11513 + attribute \src "libresoc.v:178658.3-178703.6" + process $proc$libresoc.v:178658$11216 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[1:0]$11514 $7\r2__data_o$next[1:0]$11521 - attribute \src "libresoc.v:184464.5-184464.29" + assign $0\r2__data_o$next[1:0]$11217 $7\r2__data_o$next[1:0]$11224 + attribute \src "libresoc.v:178659.5-178659.29" switch \initial - attribute \src "libresoc.v:184464.9-184464.17" + attribute \src "libresoc.v:178659.9-178659.17" case 1'1 case end @@ -378120,75 +368665,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[1:0]$11515 $6\r2__data_o$next[1:0]$11520 + assign $1\r2__data_o$next[1:0]$11218 $6\r2__data_o$next[1:0]$11223 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[1:0]$11516 \dest12__data_i + assign $2\r2__data_o$next[1:0]$11219 \dest12__data_i case - assign $2\r2__data_o$next[1:0]$11516 2'00 + assign $2\r2__data_o$next[1:0]$11219 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[1:0]$11517 \dest22__data_i + assign $3\r2__data_o$next[1:0]$11220 \dest22__data_i case - assign $3\r2__data_o$next[1:0]$11517 $2\r2__data_o$next[1:0]$11516 + assign $3\r2__data_o$next[1:0]$11220 $2\r2__data_o$next[1:0]$11219 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[1:0]$11518 \dest32__data_i + assign $4\r2__data_o$next[1:0]$11221 \dest32__data_i case - assign $4\r2__data_o$next[1:0]$11518 $3\r2__data_o$next[1:0]$11517 + assign $4\r2__data_o$next[1:0]$11221 $3\r2__data_o$next[1:0]$11220 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[1:0]$11519 \w2__data_i + assign $5\r2__data_o$next[1:0]$11222 \w2__data_i case - assign $5\r2__data_o$next[1:0]$11519 $4\r2__data_o$next[1:0]$11518 + assign $5\r2__data_o$next[1:0]$11222 $4\r2__data_o$next[1:0]$11221 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[1:0]$11520 \reg + assign $6\r2__data_o$next[1:0]$11223 \reg case - assign $6\r2__data_o$next[1:0]$11520 $5\r2__data_o$next[1:0]$11519 + assign $6\r2__data_o$next[1:0]$11223 $5\r2__data_o$next[1:0]$11222 end case - assign $1\r2__data_o$next[1:0]$11515 2'00 + assign $1\r2__data_o$next[1:0]$11218 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r2__data_o$next[1:0]$11521 2'00 + assign $7\r2__data_o$next[1:0]$11224 2'00 case - assign $7\r2__data_o$next[1:0]$11521 $1\r2__data_o$next[1:0]$11515 + assign $7\r2__data_o$next[1:0]$11224 $1\r2__data_o$next[1:0]$11218 end sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$11514 + update \r2__data_o$next $0\r2__data_o$next[1:0]$11217 end - attribute \src "libresoc.v:184509.3-184544.6" - process $proc$libresoc.v:184509$11522 + attribute \src "libresoc.v:178704.3-178739.6" + process $proc$libresoc.v:178704$11225 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11523 $1\wr_detect$10[0:0]$11524 - attribute \src "libresoc.v:184510.5-184510.29" + assign $0\wr_detect$10[0:0]$11226 $1\wr_detect$10[0:0]$11227 + attribute \src "libresoc.v:178705.5-178705.29" switch \initial - attribute \src "libresoc.v:184510.9-184510.17" + attribute \src "libresoc.v:178705.9-178705.17" case 1'1 case end @@ -378201,61 +368746,61 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11524 $5\wr_detect$10[0:0]$11528 + assign $1\wr_detect$10[0:0]$11227 $5\wr_detect$10[0:0]$11231 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11525 1'1 + assign $2\wr_detect$10[0:0]$11228 1'1 case - assign $2\wr_detect$10[0:0]$11525 1'0 + assign $2\wr_detect$10[0:0]$11228 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11526 1'1 + assign $3\wr_detect$10[0:0]$11229 1'1 case - assign $3\wr_detect$10[0:0]$11526 $2\wr_detect$10[0:0]$11525 + assign $3\wr_detect$10[0:0]$11229 $2\wr_detect$10[0:0]$11228 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11527 1'1 + assign $4\wr_detect$10[0:0]$11230 1'1 case - assign $4\wr_detect$10[0:0]$11527 $3\wr_detect$10[0:0]$11526 + assign $4\wr_detect$10[0:0]$11230 $3\wr_detect$10[0:0]$11229 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11528 1'1 + assign $5\wr_detect$10[0:0]$11231 1'1 case - assign $5\wr_detect$10[0:0]$11528 $4\wr_detect$10[0:0]$11527 + assign $5\wr_detect$10[0:0]$11231 $4\wr_detect$10[0:0]$11230 end case - assign $1\wr_detect$10[0:0]$11524 1'0 + assign $1\wr_detect$10[0:0]$11227 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11523 + update \wr_detect$10 $0\wr_detect$10[0:0]$11226 end - attribute \src "libresoc.v:184545.3-184577.6" - process $proc$libresoc.v:184545$11529 + attribute \src "libresoc.v:178740.3-178772.6" + process $proc$libresoc.v:178740$11232 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11530 $5\reg$next[1:0]$11535 - attribute \src "libresoc.v:184546.5-184546.29" + assign $0\reg$next[1:0]$11233 $5\reg$next[1:0]$11238 + attribute \src "libresoc.v:178741.5-178741.29" switch \initial - attribute \src "libresoc.v:184546.9-184546.17" + attribute \src "libresoc.v:178741.9-178741.17" case 1'1 case end @@ -378264,179 +368809,179 @@ module \reg_2$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11531 \dest12__data_i + assign $1\reg$next[1:0]$11234 \dest12__data_i case - assign $1\reg$next[1:0]$11531 \reg + assign $1\reg$next[1:0]$11234 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11532 \dest22__data_i + assign $2\reg$next[1:0]$11235 \dest22__data_i case - assign $2\reg$next[1:0]$11532 $1\reg$next[1:0]$11531 + assign $2\reg$next[1:0]$11235 $1\reg$next[1:0]$11234 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11533 \dest32__data_i + assign $3\reg$next[1:0]$11236 \dest32__data_i case - assign $3\reg$next[1:0]$11533 $2\reg$next[1:0]$11532 + assign $3\reg$next[1:0]$11236 $2\reg$next[1:0]$11235 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11534 \w2__data_i + assign $4\reg$next[1:0]$11237 \w2__data_i case - assign $4\reg$next[1:0]$11534 $3\reg$next[1:0]$11533 + assign $4\reg$next[1:0]$11237 $3\reg$next[1:0]$11236 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11535 2'00 + assign $5\reg$next[1:0]$11238 2'00 case - assign $5\reg$next[1:0]$11535 $4\reg$next[1:0]$11534 + assign $5\reg$next[1:0]$11238 $4\reg$next[1:0]$11237 end sync always - update \reg$next $0\reg$next[1:0]$11530 + update \reg$next $0\reg$next[1:0]$11233 end - connect \$9 $not$libresoc.v:184203$11462_Y - connect \$1 $not$libresoc.v:184204$11463_Y - connect \$3 $not$libresoc.v:184205$11464_Y - connect \$6 $not$libresoc.v:184206$11465_Y + connect \$9 $not$libresoc.v:178398$11165_Y + connect \$1 $not$libresoc.v:178399$11166_Y + connect \$3 $not$libresoc.v:178400$11167_Y + connect \$6 $not$libresoc.v:178401$11168_Y end -attribute \src "libresoc.v:184582.1-184931.10" +attribute \src "libresoc.v:178777.1-179126.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" attribute \generator "nMigen" module \reg_2$137 - attribute \src "libresoc.v:184652.3-184697.6" - wire width 64 $0\cia2__data_o$next[63:0]$11550 - attribute \src "libresoc.v:184650.3-184651.41" + attribute \src "libresoc.v:178847.3-178892.6" + wire width 64 $0\cia2__data_o$next[63:0]$11253 + attribute \src "libresoc.v:178845.3-178846.41" wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:184583.7-184583.20" + attribute \src "libresoc.v:178778.7-178778.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184734.3-184779.6" - wire width 64 $0\msr2__data_o$next[63:0]$11560 - attribute \src "libresoc.v:184648.3-184649.41" + attribute \src "libresoc.v:178929.3-178974.6" + wire width 64 $0\msr2__data_o$next[63:0]$11263 + attribute \src "libresoc.v:178843.3-178844.41" wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:184898.3-184930.6" - wire width 64 $0\reg$next[63:0]$11592 - attribute \src "libresoc.v:184644.3-184645.25" + attribute \src "libresoc.v:179093.3-179125.6" + wire width 64 $0\reg$next[63:0]$11295 + attribute \src "libresoc.v:178839.3-178840.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:184816.3-184861.6" - wire width 64 $0\sv2__data_o$next[63:0]$11576 - attribute \src "libresoc.v:184646.3-184647.39" + attribute \src "libresoc.v:179011.3-179056.6" + wire width 64 $0\sv2__data_o$next[63:0]$11279 + attribute \src "libresoc.v:178841.3-178842.39" wire width 64 $0\sv2__data_o[63:0] - attribute \src "libresoc.v:184780.3-184815.6" - wire $0\wr_detect$4[0:0]$11569 - attribute \src "libresoc.v:184862.3-184897.6" - wire $0\wr_detect$7[0:0]$11585 - attribute \src "libresoc.v:184698.3-184733.6" + attribute \src "libresoc.v:178975.3-179010.6" + wire $0\wr_detect$4[0:0]$11272 + attribute \src "libresoc.v:179057.3-179092.6" + wire $0\wr_detect$7[0:0]$11288 + attribute \src "libresoc.v:178893.3-178928.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:184652.3-184697.6" - wire width 64 $1\cia2__data_o$next[63:0]$11551 - attribute \src "libresoc.v:184592.14-184592.49" + attribute \src "libresoc.v:178847.3-178892.6" + wire width 64 $1\cia2__data_o$next[63:0]$11254 + attribute \src "libresoc.v:178787.14-178787.49" wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:184734.3-184779.6" - wire width 64 $1\msr2__data_o$next[63:0]$11561 - attribute \src "libresoc.v:184609.14-184609.49" + attribute \src "libresoc.v:178929.3-178974.6" + wire width 64 $1\msr2__data_o$next[63:0]$11264 + attribute \src "libresoc.v:178804.14-178804.49" wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:184898.3-184930.6" - wire width 64 $1\reg$next[63:0]$11593 - attribute \src "libresoc.v:184621.14-184621.42" + attribute \src "libresoc.v:179093.3-179125.6" + wire width 64 $1\reg$next[63:0]$11296 + attribute \src "libresoc.v:178816.14-178816.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:184816.3-184861.6" - wire width 64 $1\sv2__data_o$next[63:0]$11577 - attribute \src "libresoc.v:184628.14-184628.48" + attribute \src "libresoc.v:179011.3-179056.6" + wire width 64 $1\sv2__data_o$next[63:0]$11280 + attribute \src "libresoc.v:178823.14-178823.48" wire width 64 $1\sv2__data_o[63:0] - attribute \src "libresoc.v:184780.3-184815.6" - wire $1\wr_detect$4[0:0]$11570 - attribute \src "libresoc.v:184862.3-184897.6" - wire $1\wr_detect$7[0:0]$11586 - attribute \src "libresoc.v:184698.3-184733.6" + attribute \src "libresoc.v:178975.3-179010.6" + wire $1\wr_detect$4[0:0]$11273 + attribute \src "libresoc.v:179057.3-179092.6" + wire $1\wr_detect$7[0:0]$11289 + attribute \src "libresoc.v:178893.3-178928.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:184652.3-184697.6" - wire width 64 $2\cia2__data_o$next[63:0]$11552 - attribute \src "libresoc.v:184734.3-184779.6" - wire width 64 $2\msr2__data_o$next[63:0]$11562 - attribute \src "libresoc.v:184898.3-184930.6" - wire width 64 $2\reg$next[63:0]$11594 - attribute \src "libresoc.v:184816.3-184861.6" - wire width 64 $2\sv2__data_o$next[63:0]$11578 - attribute \src "libresoc.v:184780.3-184815.6" - wire $2\wr_detect$4[0:0]$11571 - attribute \src "libresoc.v:184862.3-184897.6" - wire $2\wr_detect$7[0:0]$11587 - attribute \src "libresoc.v:184698.3-184733.6" + attribute \src "libresoc.v:178847.3-178892.6" + wire width 64 $2\cia2__data_o$next[63:0]$11255 + attribute \src "libresoc.v:178929.3-178974.6" + wire width 64 $2\msr2__data_o$next[63:0]$11265 + attribute \src "libresoc.v:179093.3-179125.6" + wire width 64 $2\reg$next[63:0]$11297 + attribute \src "libresoc.v:179011.3-179056.6" + wire width 64 $2\sv2__data_o$next[63:0]$11281 + attribute \src "libresoc.v:178975.3-179010.6" + wire $2\wr_detect$4[0:0]$11274 + attribute \src "libresoc.v:179057.3-179092.6" + wire $2\wr_detect$7[0:0]$11290 + attribute \src "libresoc.v:178893.3-178928.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:184652.3-184697.6" - wire width 64 $3\cia2__data_o$next[63:0]$11553 - attribute \src "libresoc.v:184734.3-184779.6" - wire width 64 $3\msr2__data_o$next[63:0]$11563 - attribute \src "libresoc.v:184898.3-184930.6" - wire width 64 $3\reg$next[63:0]$11595 - attribute \src "libresoc.v:184816.3-184861.6" - wire width 64 $3\sv2__data_o$next[63:0]$11579 - attribute \src "libresoc.v:184780.3-184815.6" - wire $3\wr_detect$4[0:0]$11572 - attribute \src "libresoc.v:184862.3-184897.6" - wire $3\wr_detect$7[0:0]$11588 - attribute \src "libresoc.v:184698.3-184733.6" + attribute \src "libresoc.v:178847.3-178892.6" + wire width 64 $3\cia2__data_o$next[63:0]$11256 + attribute \src "libresoc.v:178929.3-178974.6" + wire width 64 $3\msr2__data_o$next[63:0]$11266 + attribute \src "libresoc.v:179093.3-179125.6" + wire width 64 $3\reg$next[63:0]$11298 + attribute \src "libresoc.v:179011.3-179056.6" + wire width 64 $3\sv2__data_o$next[63:0]$11282 + attribute \src "libresoc.v:178975.3-179010.6" + wire $3\wr_detect$4[0:0]$11275 + attribute \src "libresoc.v:179057.3-179092.6" + wire $3\wr_detect$7[0:0]$11291 + attribute \src "libresoc.v:178893.3-178928.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:184652.3-184697.6" - wire width 64 $4\cia2__data_o$next[63:0]$11554 - attribute \src "libresoc.v:184734.3-184779.6" - wire width 64 $4\msr2__data_o$next[63:0]$11564 - attribute \src "libresoc.v:184898.3-184930.6" - wire width 64 $4\reg$next[63:0]$11596 - attribute \src "libresoc.v:184816.3-184861.6" - wire width 64 $4\sv2__data_o$next[63:0]$11580 - attribute \src "libresoc.v:184780.3-184815.6" - wire $4\wr_detect$4[0:0]$11573 - attribute \src "libresoc.v:184862.3-184897.6" - wire $4\wr_detect$7[0:0]$11589 - attribute \src "libresoc.v:184698.3-184733.6" + attribute \src "libresoc.v:178847.3-178892.6" + wire width 64 $4\cia2__data_o$next[63:0]$11257 + attribute \src "libresoc.v:178929.3-178974.6" + wire width 64 $4\msr2__data_o$next[63:0]$11267 + attribute \src "libresoc.v:179093.3-179125.6" + wire width 64 $4\reg$next[63:0]$11299 + attribute \src "libresoc.v:179011.3-179056.6" + wire width 64 $4\sv2__data_o$next[63:0]$11283 + attribute \src "libresoc.v:178975.3-179010.6" + wire $4\wr_detect$4[0:0]$11276 + attribute \src "libresoc.v:179057.3-179092.6" + wire $4\wr_detect$7[0:0]$11292 + attribute \src "libresoc.v:178893.3-178928.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:184652.3-184697.6" - wire width 64 $5\cia2__data_o$next[63:0]$11555 - attribute \src "libresoc.v:184734.3-184779.6" - wire width 64 $5\msr2__data_o$next[63:0]$11565 - attribute \src "libresoc.v:184898.3-184930.6" - wire width 64 $5\reg$next[63:0]$11597 - attribute \src "libresoc.v:184816.3-184861.6" - wire width 64 $5\sv2__data_o$next[63:0]$11581 - attribute \src "libresoc.v:184780.3-184815.6" - wire $5\wr_detect$4[0:0]$11574 - attribute \src "libresoc.v:184862.3-184897.6" - wire $5\wr_detect$7[0:0]$11590 - attribute \src "libresoc.v:184698.3-184733.6" + attribute \src "libresoc.v:178847.3-178892.6" + wire width 64 $5\cia2__data_o$next[63:0]$11258 + attribute \src "libresoc.v:178929.3-178974.6" + wire width 64 $5\msr2__data_o$next[63:0]$11268 + attribute \src "libresoc.v:179093.3-179125.6" + wire width 64 $5\reg$next[63:0]$11300 + attribute \src "libresoc.v:179011.3-179056.6" + wire width 64 $5\sv2__data_o$next[63:0]$11284 + attribute \src "libresoc.v:178975.3-179010.6" + wire $5\wr_detect$4[0:0]$11277 + attribute \src "libresoc.v:179057.3-179092.6" + wire $5\wr_detect$7[0:0]$11293 + attribute \src "libresoc.v:178893.3-178928.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:184652.3-184697.6" - wire width 64 $6\cia2__data_o$next[63:0]$11556 - attribute \src "libresoc.v:184734.3-184779.6" - wire width 64 $6\msr2__data_o$next[63:0]$11566 - attribute \src "libresoc.v:184816.3-184861.6" - wire width 64 $6\sv2__data_o$next[63:0]$11582 - attribute \src "libresoc.v:184652.3-184697.6" - wire width 64 $7\cia2__data_o$next[63:0]$11557 - attribute \src "libresoc.v:184734.3-184779.6" - wire width 64 $7\msr2__data_o$next[63:0]$11567 - attribute \src "libresoc.v:184816.3-184861.6" - wire width 64 $7\sv2__data_o$next[63:0]$11583 - attribute \src "libresoc.v:184641.17-184641.100" - wire $not$libresoc.v:184641$11542_Y - attribute \src "libresoc.v:184642.17-184642.103" - wire $not$libresoc.v:184642$11543_Y - attribute \src "libresoc.v:184643.17-184643.103" - wire $not$libresoc.v:184643$11544_Y + attribute \src "libresoc.v:178847.3-178892.6" + wire width 64 $6\cia2__data_o$next[63:0]$11259 + attribute \src "libresoc.v:178929.3-178974.6" + wire width 64 $6\msr2__data_o$next[63:0]$11269 + attribute \src "libresoc.v:179011.3-179056.6" + wire width 64 $6\sv2__data_o$next[63:0]$11285 + attribute \src "libresoc.v:178847.3-178892.6" + wire width 64 $7\cia2__data_o$next[63:0]$11260 + attribute \src "libresoc.v:178929.3-178974.6" + wire width 64 $7\msr2__data_o$next[63:0]$11270 + attribute \src "libresoc.v:179011.3-179056.6" + wire width 64 $7\sv2__data_o$next[63:0]$11286 + attribute \src "libresoc.v:178836.17-178836.100" + wire $not$libresoc.v:178836$11245_Y + attribute \src "libresoc.v:178837.17-178837.103" + wire $not$libresoc.v:178837$11246_Y + attribute \src "libresoc.v:178838.17-178838.103" + wire $not$libresoc.v:178838$11247_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -378449,15 +368994,15 @@ module \reg_2$137 wire width 64 \cia2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr12__wen - attribute \src "libresoc.v:184583.7-184583.15" + attribute \src "libresoc.v:178778.7-178778.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr2__data_i @@ -378494,106 +369039,106 @@ module \reg_2$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:184641$11542 + cell $not $not$libresoc.v:178836$11245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:184641$11542_Y + connect \Y $not$libresoc.v:178836$11245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:184642$11543 + cell $not $not$libresoc.v:178837$11246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:184642$11543_Y + connect \Y $not$libresoc.v:178837$11246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:184643$11544 + cell $not $not$libresoc.v:178838$11247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:184643$11544_Y + connect \Y $not$libresoc.v:178838$11247_Y end - attribute \src "libresoc.v:184583.7-184583.20" - process $proc$libresoc.v:184583$11598 + attribute \src "libresoc.v:178778.7-178778.20" + process $proc$libresoc.v:178778$11301 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184592.14-184592.49" - process $proc$libresoc.v:184592$11599 + attribute \src "libresoc.v:178787.14-178787.49" + process $proc$libresoc.v:178787$11302 assign { } { } assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia2__data_o $1\cia2__data_o[63:0] end - attribute \src "libresoc.v:184609.14-184609.49" - process $proc$libresoc.v:184609$11600 + attribute \src "libresoc.v:178804.14-178804.49" + process $proc$libresoc.v:178804$11303 assign { } { } assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr2__data_o $1\msr2__data_o[63:0] end - attribute \src "libresoc.v:184621.14-184621.42" - process $proc$libresoc.v:184621$11601 + attribute \src "libresoc.v:178816.14-178816.42" + process $proc$libresoc.v:178816$11304 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:184628.14-184628.48" - process $proc$libresoc.v:184628$11602 + attribute \src "libresoc.v:178823.14-178823.48" + process $proc$libresoc.v:178823$11305 assign { } { } assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv2__data_o $1\sv2__data_o[63:0] end - attribute \src "libresoc.v:184644.3-184645.25" - process $proc$libresoc.v:184644$11545 + attribute \src "libresoc.v:178839.3-178840.25" + process $proc$libresoc.v:178839$11248 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:184646.3-184647.39" - process $proc$libresoc.v:184646$11546 + attribute \src "libresoc.v:178841.3-178842.39" + process $proc$libresoc.v:178841$11249 assign { } { } assign $0\sv2__data_o[63:0] \sv2__data_o$next sync posedge \coresync_clk update \sv2__data_o $0\sv2__data_o[63:0] end - attribute \src "libresoc.v:184648.3-184649.41" - process $proc$libresoc.v:184648$11547 + attribute \src "libresoc.v:178843.3-178844.41" + process $proc$libresoc.v:178843$11250 assign { } { } assign $0\msr2__data_o[63:0] \msr2__data_o$next sync posedge \coresync_clk update \msr2__data_o $0\msr2__data_o[63:0] end - attribute \src "libresoc.v:184650.3-184651.41" - process $proc$libresoc.v:184650$11548 + attribute \src "libresoc.v:178845.3-178846.41" + process $proc$libresoc.v:178845$11251 assign { } { } assign $0\cia2__data_o[63:0] \cia2__data_o$next sync posedge \coresync_clk update \cia2__data_o $0\cia2__data_o[63:0] end - attribute \src "libresoc.v:184652.3-184697.6" - process $proc$libresoc.v:184652$11549 + attribute \src "libresoc.v:178847.3-178892.6" + process $proc$libresoc.v:178847$11252 assign { } { } assign { } { } assign { } { } - assign $0\cia2__data_o$next[63:0]$11550 $7\cia2__data_o$next[63:0]$11557 - attribute \src "libresoc.v:184653.5-184653.29" + assign $0\cia2__data_o$next[63:0]$11253 $7\cia2__data_o$next[63:0]$11260 + attribute \src "libresoc.v:178848.5-178848.29" switch \initial - attribute \src "libresoc.v:184653.9-184653.17" + attribute \src "libresoc.v:178848.9-178848.17" case 1'1 case end @@ -378606,75 +369151,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\cia2__data_o$next[63:0]$11551 $6\cia2__data_o$next[63:0]$11556 + assign $1\cia2__data_o$next[63:0]$11254 $6\cia2__data_o$next[63:0]$11259 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia2__data_o$next[63:0]$11552 \nia2__data_i + assign $2\cia2__data_o$next[63:0]$11255 \nia2__data_i case - assign $2\cia2__data_o$next[63:0]$11552 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia2__data_o$next[63:0]$11255 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia2__data_o$next[63:0]$11553 \msr2__data_i + assign $3\cia2__data_o$next[63:0]$11256 \msr2__data_i case - assign $3\cia2__data_o$next[63:0]$11553 $2\cia2__data_o$next[63:0]$11552 + assign $3\cia2__data_o$next[63:0]$11256 $2\cia2__data_o$next[63:0]$11255 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia2__data_o$next[63:0]$11554 \sv2__data_i + assign $4\cia2__data_o$next[63:0]$11257 \sv2__data_i case - assign $4\cia2__data_o$next[63:0]$11554 $3\cia2__data_o$next[63:0]$11553 + assign $4\cia2__data_o$next[63:0]$11257 $3\cia2__data_o$next[63:0]$11256 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia2__data_o$next[63:0]$11555 \d_wr12__data_i + assign $5\cia2__data_o$next[63:0]$11258 \d_wr12__data_i case - assign $5\cia2__data_o$next[63:0]$11555 $4\cia2__data_o$next[63:0]$11554 + assign $5\cia2__data_o$next[63:0]$11258 $4\cia2__data_o$next[63:0]$11257 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia2__data_o$next[63:0]$11556 \reg + assign $6\cia2__data_o$next[63:0]$11259 \reg case - assign $6\cia2__data_o$next[63:0]$11556 $5\cia2__data_o$next[63:0]$11555 + assign $6\cia2__data_o$next[63:0]$11259 $5\cia2__data_o$next[63:0]$11258 end case - assign $1\cia2__data_o$next[63:0]$11551 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia2__data_o$next[63:0]$11254 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia2__data_o$next[63:0]$11557 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia2__data_o$next[63:0]$11260 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia2__data_o$next[63:0]$11557 $1\cia2__data_o$next[63:0]$11551 + assign $7\cia2__data_o$next[63:0]$11260 $1\cia2__data_o$next[63:0]$11254 end sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11550 + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11253 end - attribute \src "libresoc.v:184698.3-184733.6" - process $proc$libresoc.v:184698$11558 + attribute \src "libresoc.v:178893.3-178928.6" + process $proc$libresoc.v:178893$11261 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:184699.5-184699.29" + attribute \src "libresoc.v:178894.5-178894.29" switch \initial - attribute \src "libresoc.v:184699.9-184699.17" + attribute \src "libresoc.v:178894.9-178894.17" case 1'1 case end @@ -378730,15 +369275,15 @@ module \reg_2$137 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:184734.3-184779.6" - process $proc$libresoc.v:184734$11559 + attribute \src "libresoc.v:178929.3-178974.6" + process $proc$libresoc.v:178929$11262 assign { } { } assign { } { } assign { } { } - assign $0\msr2__data_o$next[63:0]$11560 $7\msr2__data_o$next[63:0]$11567 - attribute \src "libresoc.v:184735.5-184735.29" + assign $0\msr2__data_o$next[63:0]$11263 $7\msr2__data_o$next[63:0]$11270 + attribute \src "libresoc.v:178930.5-178930.29" switch \initial - attribute \src "libresoc.v:184735.9-184735.17" + attribute \src "libresoc.v:178930.9-178930.17" case 1'1 case end @@ -378751,75 +369296,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\msr2__data_o$next[63:0]$11561 $6\msr2__data_o$next[63:0]$11566 + assign $1\msr2__data_o$next[63:0]$11264 $6\msr2__data_o$next[63:0]$11269 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr2__data_o$next[63:0]$11562 \nia2__data_i + assign $2\msr2__data_o$next[63:0]$11265 \nia2__data_i case - assign $2\msr2__data_o$next[63:0]$11562 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr2__data_o$next[63:0]$11265 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr2__data_o$next[63:0]$11563 \msr2__data_i + assign $3\msr2__data_o$next[63:0]$11266 \msr2__data_i case - assign $3\msr2__data_o$next[63:0]$11563 $2\msr2__data_o$next[63:0]$11562 + assign $3\msr2__data_o$next[63:0]$11266 $2\msr2__data_o$next[63:0]$11265 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr2__data_o$next[63:0]$11564 \sv2__data_i + assign $4\msr2__data_o$next[63:0]$11267 \sv2__data_i case - assign $4\msr2__data_o$next[63:0]$11564 $3\msr2__data_o$next[63:0]$11563 + assign $4\msr2__data_o$next[63:0]$11267 $3\msr2__data_o$next[63:0]$11266 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr2__data_o$next[63:0]$11565 \d_wr12__data_i + assign $5\msr2__data_o$next[63:0]$11268 \d_wr12__data_i case - assign $5\msr2__data_o$next[63:0]$11565 $4\msr2__data_o$next[63:0]$11564 + assign $5\msr2__data_o$next[63:0]$11268 $4\msr2__data_o$next[63:0]$11267 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr2__data_o$next[63:0]$11566 \reg + assign $6\msr2__data_o$next[63:0]$11269 \reg case - assign $6\msr2__data_o$next[63:0]$11566 $5\msr2__data_o$next[63:0]$11565 + assign $6\msr2__data_o$next[63:0]$11269 $5\msr2__data_o$next[63:0]$11268 end case - assign $1\msr2__data_o$next[63:0]$11561 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr2__data_o$next[63:0]$11264 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr2__data_o$next[63:0]$11567 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr2__data_o$next[63:0]$11270 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr2__data_o$next[63:0]$11567 $1\msr2__data_o$next[63:0]$11561 + assign $7\msr2__data_o$next[63:0]$11270 $1\msr2__data_o$next[63:0]$11264 end sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11560 + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11263 end - attribute \src "libresoc.v:184780.3-184815.6" - process $proc$libresoc.v:184780$11568 + attribute \src "libresoc.v:178975.3-179010.6" + process $proc$libresoc.v:178975$11271 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11569 $1\wr_detect$4[0:0]$11570 - attribute \src "libresoc.v:184781.5-184781.29" + assign $0\wr_detect$4[0:0]$11272 $1\wr_detect$4[0:0]$11273 + attribute \src "libresoc.v:178976.5-178976.29" switch \initial - attribute \src "libresoc.v:184781.9-184781.17" + attribute \src "libresoc.v:178976.9-178976.17" case 1'1 case end @@ -378832,58 +369377,58 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11570 $5\wr_detect$4[0:0]$11574 + assign $1\wr_detect$4[0:0]$11273 $5\wr_detect$4[0:0]$11277 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11571 1'1 + assign $2\wr_detect$4[0:0]$11274 1'1 case - assign $2\wr_detect$4[0:0]$11571 1'0 + assign $2\wr_detect$4[0:0]$11274 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11572 1'1 + assign $3\wr_detect$4[0:0]$11275 1'1 case - assign $3\wr_detect$4[0:0]$11572 $2\wr_detect$4[0:0]$11571 + assign $3\wr_detect$4[0:0]$11275 $2\wr_detect$4[0:0]$11274 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11573 1'1 + assign $4\wr_detect$4[0:0]$11276 1'1 case - assign $4\wr_detect$4[0:0]$11573 $3\wr_detect$4[0:0]$11572 + assign $4\wr_detect$4[0:0]$11276 $3\wr_detect$4[0:0]$11275 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11574 1'1 + assign $5\wr_detect$4[0:0]$11277 1'1 case - assign $5\wr_detect$4[0:0]$11574 $4\wr_detect$4[0:0]$11573 + assign $5\wr_detect$4[0:0]$11277 $4\wr_detect$4[0:0]$11276 end case - assign $1\wr_detect$4[0:0]$11570 1'0 + assign $1\wr_detect$4[0:0]$11273 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11569 + update \wr_detect$4 $0\wr_detect$4[0:0]$11272 end - attribute \src "libresoc.v:184816.3-184861.6" - process $proc$libresoc.v:184816$11575 + attribute \src "libresoc.v:179011.3-179056.6" + process $proc$libresoc.v:179011$11278 assign { } { } assign { } { } assign { } { } - assign $0\sv2__data_o$next[63:0]$11576 $7\sv2__data_o$next[63:0]$11583 - attribute \src "libresoc.v:184817.5-184817.29" + assign $0\sv2__data_o$next[63:0]$11279 $7\sv2__data_o$next[63:0]$11286 + attribute \src "libresoc.v:179012.5-179012.29" switch \initial - attribute \src "libresoc.v:184817.9-184817.17" + attribute \src "libresoc.v:179012.9-179012.17" case 1'1 case end @@ -378896,75 +369441,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\sv2__data_o$next[63:0]$11577 $6\sv2__data_o$next[63:0]$11582 + assign $1\sv2__data_o$next[63:0]$11280 $6\sv2__data_o$next[63:0]$11285 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv2__data_o$next[63:0]$11578 \nia2__data_i + assign $2\sv2__data_o$next[63:0]$11281 \nia2__data_i case - assign $2\sv2__data_o$next[63:0]$11578 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv2__data_o$next[63:0]$11281 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv2__data_o$next[63:0]$11579 \msr2__data_i + assign $3\sv2__data_o$next[63:0]$11282 \msr2__data_i case - assign $3\sv2__data_o$next[63:0]$11579 $2\sv2__data_o$next[63:0]$11578 + assign $3\sv2__data_o$next[63:0]$11282 $2\sv2__data_o$next[63:0]$11281 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv2__data_o$next[63:0]$11580 \sv2__data_i + assign $4\sv2__data_o$next[63:0]$11283 \sv2__data_i case - assign $4\sv2__data_o$next[63:0]$11580 $3\sv2__data_o$next[63:0]$11579 + assign $4\sv2__data_o$next[63:0]$11283 $3\sv2__data_o$next[63:0]$11282 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv2__data_o$next[63:0]$11581 \d_wr12__data_i + assign $5\sv2__data_o$next[63:0]$11284 \d_wr12__data_i case - assign $5\sv2__data_o$next[63:0]$11581 $4\sv2__data_o$next[63:0]$11580 + assign $5\sv2__data_o$next[63:0]$11284 $4\sv2__data_o$next[63:0]$11283 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv2__data_o$next[63:0]$11582 \reg + assign $6\sv2__data_o$next[63:0]$11285 \reg case - assign $6\sv2__data_o$next[63:0]$11582 $5\sv2__data_o$next[63:0]$11581 + assign $6\sv2__data_o$next[63:0]$11285 $5\sv2__data_o$next[63:0]$11284 end case - assign $1\sv2__data_o$next[63:0]$11577 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv2__data_o$next[63:0]$11280 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv2__data_o$next[63:0]$11583 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv2__data_o$next[63:0]$11286 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv2__data_o$next[63:0]$11583 $1\sv2__data_o$next[63:0]$11577 + assign $7\sv2__data_o$next[63:0]$11286 $1\sv2__data_o$next[63:0]$11280 end sync always - update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11576 + update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11279 end - attribute \src "libresoc.v:184862.3-184897.6" - process $proc$libresoc.v:184862$11584 + attribute \src "libresoc.v:179057.3-179092.6" + process $proc$libresoc.v:179057$11287 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11585 $1\wr_detect$7[0:0]$11586 - attribute \src "libresoc.v:184863.5-184863.29" + assign $0\wr_detect$7[0:0]$11288 $1\wr_detect$7[0:0]$11289 + attribute \src "libresoc.v:179058.5-179058.29" switch \initial - attribute \src "libresoc.v:184863.9-184863.17" + attribute \src "libresoc.v:179058.9-179058.17" case 1'1 case end @@ -378977,61 +369522,61 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11586 $5\wr_detect$7[0:0]$11590 + assign $1\wr_detect$7[0:0]$11289 $5\wr_detect$7[0:0]$11293 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11587 1'1 + assign $2\wr_detect$7[0:0]$11290 1'1 case - assign $2\wr_detect$7[0:0]$11587 1'0 + assign $2\wr_detect$7[0:0]$11290 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11588 1'1 + assign $3\wr_detect$7[0:0]$11291 1'1 case - assign $3\wr_detect$7[0:0]$11588 $2\wr_detect$7[0:0]$11587 + assign $3\wr_detect$7[0:0]$11291 $2\wr_detect$7[0:0]$11290 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11589 1'1 + assign $4\wr_detect$7[0:0]$11292 1'1 case - assign $4\wr_detect$7[0:0]$11589 $3\wr_detect$7[0:0]$11588 + assign $4\wr_detect$7[0:0]$11292 $3\wr_detect$7[0:0]$11291 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11590 1'1 + assign $5\wr_detect$7[0:0]$11293 1'1 case - assign $5\wr_detect$7[0:0]$11590 $4\wr_detect$7[0:0]$11589 + assign $5\wr_detect$7[0:0]$11293 $4\wr_detect$7[0:0]$11292 end case - assign $1\wr_detect$7[0:0]$11586 1'0 + assign $1\wr_detect$7[0:0]$11289 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11585 + update \wr_detect$7 $0\wr_detect$7[0:0]$11288 end - attribute \src "libresoc.v:184898.3-184930.6" - process $proc$libresoc.v:184898$11591 + attribute \src "libresoc.v:179093.3-179125.6" + process $proc$libresoc.v:179093$11294 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11592 $5\reg$next[63:0]$11597 - attribute \src "libresoc.v:184899.5-184899.29" + assign $0\reg$next[63:0]$11295 $5\reg$next[63:0]$11300 + attribute \src "libresoc.v:179094.5-179094.29" switch \initial - attribute \src "libresoc.v:184899.9-184899.17" + attribute \src "libresoc.v:179094.9-179094.17" case 1'1 case end @@ -379040,224 +369585,224 @@ module \reg_2$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11593 \nia2__data_i + assign $1\reg$next[63:0]$11296 \nia2__data_i case - assign $1\reg$next[63:0]$11593 \reg + assign $1\reg$next[63:0]$11296 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11594 \msr2__data_i + assign $2\reg$next[63:0]$11297 \msr2__data_i case - assign $2\reg$next[63:0]$11594 $1\reg$next[63:0]$11593 + assign $2\reg$next[63:0]$11297 $1\reg$next[63:0]$11296 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11595 \sv2__data_i + assign $3\reg$next[63:0]$11298 \sv2__data_i case - assign $3\reg$next[63:0]$11595 $2\reg$next[63:0]$11594 + assign $3\reg$next[63:0]$11298 $2\reg$next[63:0]$11297 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11596 \d_wr12__data_i + assign $4\reg$next[63:0]$11299 \d_wr12__data_i case - assign $4\reg$next[63:0]$11596 $3\reg$next[63:0]$11595 + assign $4\reg$next[63:0]$11299 $3\reg$next[63:0]$11298 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11597 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11300 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11597 $4\reg$next[63:0]$11596 + assign $5\reg$next[63:0]$11300 $4\reg$next[63:0]$11299 end sync always - update \reg$next $0\reg$next[63:0]$11592 + update \reg$next $0\reg$next[63:0]$11295 end - connect \$1 $not$libresoc.v:184641$11542_Y - connect \$3 $not$libresoc.v:184642$11543_Y - connect \$6 $not$libresoc.v:184643$11544_Y + connect \$1 $not$libresoc.v:178836$11245_Y + connect \$3 $not$libresoc.v:178837$11246_Y + connect \$6 $not$libresoc.v:178838$11247_Y end -attribute \src "libresoc.v:184935.1-185406.10" +attribute \src "libresoc.v:179130.1-179601.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 - attribute \src "libresoc.v:184936.7-184936.20" + attribute \src "libresoc.v:179131.7-179131.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185336.3-185375.6" - wire width 4 $0\r23__data_o$next[3:0]$11672 - attribute \src "libresoc.v:185019.3-185020.39" + attribute \src "libresoc.v:179531.3-179570.6" + wire width 4 $0\r23__data_o$next[3:0]$11375 + attribute \src "libresoc.v:179214.3-179215.39" wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:185266.3-185305.6" - wire width 4 $0\r3__data_o$next[3:0]$11658 - attribute \src "libresoc.v:185021.3-185022.37" + attribute \src "libresoc.v:179461.3-179500.6" + wire width 4 $0\r3__data_o$next[3:0]$11361 + attribute \src "libresoc.v:179216.3-179217.37" wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:185099.3-185125.6" - wire width 4 $0\reg$next[3:0]$11624 - attribute \src "libresoc.v:185017.3-185018.25" + attribute \src "libresoc.v:179294.3-179320.6" + wire width 4 $0\reg$next[3:0]$11327 + attribute \src "libresoc.v:179212.3-179213.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:185029.3-185068.6" - wire width 4 $0\src13__data_o$next[3:0]$11615 - attribute \src "libresoc.v:185027.3-185028.43" + attribute \src "libresoc.v:179224.3-179263.6" + wire width 4 $0\src13__data_o$next[3:0]$11318 + attribute \src "libresoc.v:179222.3-179223.43" wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:185126.3-185165.6" - wire width 4 $0\src23__data_o$next[3:0]$11630 - attribute \src "libresoc.v:185025.3-185026.43" + attribute \src "libresoc.v:179321.3-179360.6" + wire width 4 $0\src23__data_o$next[3:0]$11333 + attribute \src "libresoc.v:179220.3-179221.43" wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:185196.3-185235.6" - wire width 4 $0\src33__data_o$next[3:0]$11644 - attribute \src "libresoc.v:185023.3-185024.43" + attribute \src "libresoc.v:179391.3-179430.6" + wire width 4 $0\src33__data_o$next[3:0]$11347 + attribute \src "libresoc.v:179218.3-179219.43" wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:185306.3-185335.6" - wire $0\wr_detect$10[0:0]$11666 - attribute \src "libresoc.v:185376.3-185405.6" - wire $0\wr_detect$13[0:0]$11680 - attribute \src "libresoc.v:185166.3-185195.6" - wire $0\wr_detect$4[0:0]$11638 - attribute \src "libresoc.v:185236.3-185265.6" - wire $0\wr_detect$7[0:0]$11652 - attribute \src "libresoc.v:185069.3-185098.6" + attribute \src "libresoc.v:179501.3-179530.6" + wire $0\wr_detect$10[0:0]$11369 + attribute \src "libresoc.v:179571.3-179600.6" + wire $0\wr_detect$13[0:0]$11383 + attribute \src "libresoc.v:179361.3-179390.6" + wire $0\wr_detect$4[0:0]$11341 + attribute \src "libresoc.v:179431.3-179460.6" + wire $0\wr_detect$7[0:0]$11355 + attribute \src "libresoc.v:179264.3-179293.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:185336.3-185375.6" - wire width 4 $1\r23__data_o$next[3:0]$11673 - attribute \src "libresoc.v:184961.13-184961.31" + attribute \src "libresoc.v:179531.3-179570.6" + wire width 4 $1\r23__data_o$next[3:0]$11376 + attribute \src "libresoc.v:179156.13-179156.31" wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:185266.3-185305.6" - wire width 4 $1\r3__data_o$next[3:0]$11659 - attribute \src "libresoc.v:184968.13-184968.30" + attribute \src "libresoc.v:179461.3-179500.6" + wire width 4 $1\r3__data_o$next[3:0]$11362 + attribute \src "libresoc.v:179163.13-179163.30" wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:185099.3-185125.6" - wire width 4 $1\reg$next[3:0]$11625 - attribute \src "libresoc.v:184974.13-184974.25" + attribute \src "libresoc.v:179294.3-179320.6" + wire width 4 $1\reg$next[3:0]$11328 + attribute \src "libresoc.v:179169.13-179169.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:185029.3-185068.6" - wire width 4 $1\src13__data_o$next[3:0]$11616 - attribute \src "libresoc.v:184979.13-184979.33" + attribute \src "libresoc.v:179224.3-179263.6" + wire width 4 $1\src13__data_o$next[3:0]$11319 + attribute \src "libresoc.v:179174.13-179174.33" wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:185126.3-185165.6" - wire width 4 $1\src23__data_o$next[3:0]$11631 - attribute \src "libresoc.v:184986.13-184986.33" + attribute \src "libresoc.v:179321.3-179360.6" + wire width 4 $1\src23__data_o$next[3:0]$11334 + attribute \src "libresoc.v:179181.13-179181.33" wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:185196.3-185235.6" - wire width 4 $1\src33__data_o$next[3:0]$11645 - attribute \src "libresoc.v:184993.13-184993.33" + attribute \src "libresoc.v:179391.3-179430.6" + wire width 4 $1\src33__data_o$next[3:0]$11348 + attribute \src "libresoc.v:179188.13-179188.33" wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:185306.3-185335.6" - wire $1\wr_detect$10[0:0]$11667 - attribute \src "libresoc.v:185376.3-185405.6" - wire $1\wr_detect$13[0:0]$11681 - attribute \src "libresoc.v:185166.3-185195.6" - wire $1\wr_detect$4[0:0]$11639 - attribute \src "libresoc.v:185236.3-185265.6" - wire $1\wr_detect$7[0:0]$11653 - attribute \src "libresoc.v:185069.3-185098.6" + attribute \src "libresoc.v:179501.3-179530.6" + wire $1\wr_detect$10[0:0]$11370 + attribute \src "libresoc.v:179571.3-179600.6" + wire $1\wr_detect$13[0:0]$11384 + attribute \src "libresoc.v:179361.3-179390.6" + wire $1\wr_detect$4[0:0]$11342 + attribute \src "libresoc.v:179431.3-179460.6" + wire $1\wr_detect$7[0:0]$11356 + attribute \src "libresoc.v:179264.3-179293.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:185336.3-185375.6" - wire width 4 $2\r23__data_o$next[3:0]$11674 - attribute \src "libresoc.v:185266.3-185305.6" - wire width 4 $2\r3__data_o$next[3:0]$11660 - attribute \src "libresoc.v:185099.3-185125.6" - wire width 4 $2\reg$next[3:0]$11626 - attribute \src "libresoc.v:185029.3-185068.6" - wire width 4 $2\src13__data_o$next[3:0]$11617 - attribute \src "libresoc.v:185126.3-185165.6" - wire width 4 $2\src23__data_o$next[3:0]$11632 - attribute \src "libresoc.v:185196.3-185235.6" - wire width 4 $2\src33__data_o$next[3:0]$11646 - attribute \src "libresoc.v:185306.3-185335.6" - wire $2\wr_detect$10[0:0]$11668 - attribute \src "libresoc.v:185376.3-185405.6" - wire $2\wr_detect$13[0:0]$11682 - attribute \src "libresoc.v:185166.3-185195.6" - wire $2\wr_detect$4[0:0]$11640 - attribute \src "libresoc.v:185236.3-185265.6" - wire $2\wr_detect$7[0:0]$11654 - attribute \src "libresoc.v:185069.3-185098.6" + attribute \src "libresoc.v:179531.3-179570.6" + wire width 4 $2\r23__data_o$next[3:0]$11377 + attribute \src "libresoc.v:179461.3-179500.6" + wire width 4 $2\r3__data_o$next[3:0]$11363 + attribute \src "libresoc.v:179294.3-179320.6" + wire width 4 $2\reg$next[3:0]$11329 + attribute \src "libresoc.v:179224.3-179263.6" + wire width 4 $2\src13__data_o$next[3:0]$11320 + attribute \src "libresoc.v:179321.3-179360.6" + wire width 4 $2\src23__data_o$next[3:0]$11335 + attribute \src "libresoc.v:179391.3-179430.6" + wire width 4 $2\src33__data_o$next[3:0]$11349 + attribute \src "libresoc.v:179501.3-179530.6" + wire $2\wr_detect$10[0:0]$11371 + attribute \src "libresoc.v:179571.3-179600.6" + wire $2\wr_detect$13[0:0]$11385 + attribute \src "libresoc.v:179361.3-179390.6" + wire $2\wr_detect$4[0:0]$11343 + attribute \src "libresoc.v:179431.3-179460.6" + wire $2\wr_detect$7[0:0]$11357 + attribute \src "libresoc.v:179264.3-179293.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:185336.3-185375.6" - wire width 4 $3\r23__data_o$next[3:0]$11675 - attribute \src "libresoc.v:185266.3-185305.6" - wire width 4 $3\r3__data_o$next[3:0]$11661 - attribute \src "libresoc.v:185099.3-185125.6" - wire width 4 $3\reg$next[3:0]$11627 - attribute \src "libresoc.v:185029.3-185068.6" - wire width 4 $3\src13__data_o$next[3:0]$11618 - attribute \src "libresoc.v:185126.3-185165.6" - wire width 4 $3\src23__data_o$next[3:0]$11633 - attribute \src "libresoc.v:185196.3-185235.6" - wire width 4 $3\src33__data_o$next[3:0]$11647 - attribute \src "libresoc.v:185306.3-185335.6" - wire $3\wr_detect$10[0:0]$11669 - attribute \src "libresoc.v:185376.3-185405.6" - wire $3\wr_detect$13[0:0]$11683 - attribute \src "libresoc.v:185166.3-185195.6" - wire $3\wr_detect$4[0:0]$11641 - attribute \src "libresoc.v:185236.3-185265.6" - wire $3\wr_detect$7[0:0]$11655 - attribute \src "libresoc.v:185069.3-185098.6" + attribute \src "libresoc.v:179531.3-179570.6" + wire width 4 $3\r23__data_o$next[3:0]$11378 + attribute \src "libresoc.v:179461.3-179500.6" + wire width 4 $3\r3__data_o$next[3:0]$11364 + attribute \src "libresoc.v:179294.3-179320.6" + wire width 4 $3\reg$next[3:0]$11330 + attribute \src "libresoc.v:179224.3-179263.6" + wire width 4 $3\src13__data_o$next[3:0]$11321 + attribute \src "libresoc.v:179321.3-179360.6" + wire width 4 $3\src23__data_o$next[3:0]$11336 + attribute \src "libresoc.v:179391.3-179430.6" + wire width 4 $3\src33__data_o$next[3:0]$11350 + attribute \src "libresoc.v:179501.3-179530.6" + wire $3\wr_detect$10[0:0]$11372 + attribute \src "libresoc.v:179571.3-179600.6" + wire $3\wr_detect$13[0:0]$11386 + attribute \src "libresoc.v:179361.3-179390.6" + wire $3\wr_detect$4[0:0]$11344 + attribute \src "libresoc.v:179431.3-179460.6" + wire $3\wr_detect$7[0:0]$11358 + attribute \src "libresoc.v:179264.3-179293.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:185336.3-185375.6" - wire width 4 $4\r23__data_o$next[3:0]$11676 - attribute \src "libresoc.v:185266.3-185305.6" - wire width 4 $4\r3__data_o$next[3:0]$11662 - attribute \src "libresoc.v:185099.3-185125.6" - wire width 4 $4\reg$next[3:0]$11628 - attribute \src "libresoc.v:185029.3-185068.6" - wire width 4 $4\src13__data_o$next[3:0]$11619 - attribute \src "libresoc.v:185126.3-185165.6" - wire width 4 $4\src23__data_o$next[3:0]$11634 - attribute \src "libresoc.v:185196.3-185235.6" - wire width 4 $4\src33__data_o$next[3:0]$11648 - attribute \src "libresoc.v:185306.3-185335.6" - wire $4\wr_detect$10[0:0]$11670 - attribute \src "libresoc.v:185376.3-185405.6" - wire $4\wr_detect$13[0:0]$11684 - attribute \src "libresoc.v:185166.3-185195.6" - wire $4\wr_detect$4[0:0]$11642 - attribute \src "libresoc.v:185236.3-185265.6" - wire $4\wr_detect$7[0:0]$11656 - attribute \src "libresoc.v:185069.3-185098.6" + attribute \src "libresoc.v:179531.3-179570.6" + wire width 4 $4\r23__data_o$next[3:0]$11379 + attribute \src "libresoc.v:179461.3-179500.6" + wire width 4 $4\r3__data_o$next[3:0]$11365 + attribute \src "libresoc.v:179294.3-179320.6" + wire width 4 $4\reg$next[3:0]$11331 + attribute \src "libresoc.v:179224.3-179263.6" + wire width 4 $4\src13__data_o$next[3:0]$11322 + attribute \src "libresoc.v:179321.3-179360.6" + wire width 4 $4\src23__data_o$next[3:0]$11337 + attribute \src "libresoc.v:179391.3-179430.6" + wire width 4 $4\src33__data_o$next[3:0]$11351 + attribute \src "libresoc.v:179501.3-179530.6" + wire $4\wr_detect$10[0:0]$11373 + attribute \src "libresoc.v:179571.3-179600.6" + wire $4\wr_detect$13[0:0]$11387 + attribute \src "libresoc.v:179361.3-179390.6" + wire $4\wr_detect$4[0:0]$11345 + attribute \src "libresoc.v:179431.3-179460.6" + wire $4\wr_detect$7[0:0]$11359 + attribute \src "libresoc.v:179264.3-179293.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:185336.3-185375.6" - wire width 4 $5\r23__data_o$next[3:0]$11677 - attribute \src "libresoc.v:185266.3-185305.6" - wire width 4 $5\r3__data_o$next[3:0]$11663 - attribute \src "libresoc.v:185029.3-185068.6" - wire width 4 $5\src13__data_o$next[3:0]$11620 - attribute \src "libresoc.v:185126.3-185165.6" - wire width 4 $5\src23__data_o$next[3:0]$11635 - attribute \src "libresoc.v:185196.3-185235.6" - wire width 4 $5\src33__data_o$next[3:0]$11649 - attribute \src "libresoc.v:185336.3-185375.6" - wire width 4 $6\r23__data_o$next[3:0]$11678 - attribute \src "libresoc.v:185266.3-185305.6" - wire width 4 $6\r3__data_o$next[3:0]$11664 - attribute \src "libresoc.v:185029.3-185068.6" - wire width 4 $6\src13__data_o$next[3:0]$11621 - attribute \src "libresoc.v:185126.3-185165.6" - wire width 4 $6\src23__data_o$next[3:0]$11636 - attribute \src "libresoc.v:185196.3-185235.6" - wire width 4 $6\src33__data_o$next[3:0]$11650 - attribute \src "libresoc.v:185012.17-185012.104" - wire $not$libresoc.v:185012$11603_Y - attribute \src "libresoc.v:185013.18-185013.105" - wire $not$libresoc.v:185013$11604_Y - attribute \src "libresoc.v:185014.17-185014.100" - wire $not$libresoc.v:185014$11605_Y - attribute \src "libresoc.v:185015.17-185015.103" - wire $not$libresoc.v:185015$11606_Y - attribute \src "libresoc.v:185016.17-185016.103" - wire $not$libresoc.v:185016$11607_Y + attribute \src "libresoc.v:179531.3-179570.6" + wire width 4 $5\r23__data_o$next[3:0]$11380 + attribute \src "libresoc.v:179461.3-179500.6" + wire width 4 $5\r3__data_o$next[3:0]$11366 + attribute \src "libresoc.v:179224.3-179263.6" + wire width 4 $5\src13__data_o$next[3:0]$11323 + attribute \src "libresoc.v:179321.3-179360.6" + wire width 4 $5\src23__data_o$next[3:0]$11338 + attribute \src "libresoc.v:179391.3-179430.6" + wire width 4 $5\src33__data_o$next[3:0]$11352 + attribute \src "libresoc.v:179531.3-179570.6" + wire width 4 $6\r23__data_o$next[3:0]$11381 + attribute \src "libresoc.v:179461.3-179500.6" + wire width 4 $6\r3__data_o$next[3:0]$11367 + attribute \src "libresoc.v:179224.3-179263.6" + wire width 4 $6\src13__data_o$next[3:0]$11324 + attribute \src "libresoc.v:179321.3-179360.6" + wire width 4 $6\src23__data_o$next[3:0]$11339 + attribute \src "libresoc.v:179391.3-179430.6" + wire width 4 $6\src33__data_o$next[3:0]$11353 + attribute \src "libresoc.v:179207.17-179207.104" + wire $not$libresoc.v:179207$11306_Y + attribute \src "libresoc.v:179208.18-179208.105" + wire $not$libresoc.v:179208$11307_Y + attribute \src "libresoc.v:179209.17-179209.100" + wire $not$libresoc.v:179209$11308_Y + attribute \src "libresoc.v:179210.17-179210.103" + wire $not$libresoc.v:179210$11309_Y + attribute \src "libresoc.v:179211.17-179211.103" + wire $not$libresoc.v:179211$11310_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -379268,9 +369813,9 @@ module \reg_3 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest13__data_i @@ -379280,7 +369825,7 @@ module \reg_3 wire width 4 input 11 \dest23__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest23__wen - attribute \src "libresoc.v:184936.7-184936.15" + attribute \src "libresoc.v:179131.7-179131.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r23__data_o @@ -379331,152 +369876,152 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185012$11603 + cell $not $not$libresoc.v:179207$11306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:185012$11603_Y + connect \Y $not$libresoc.v:179207$11306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185013$11604 + cell $not $not$libresoc.v:179208$11307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:185013$11604_Y + connect \Y $not$libresoc.v:179208$11307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185014$11605 + cell $not $not$libresoc.v:179209$11308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:185014$11605_Y + connect \Y $not$libresoc.v:179209$11308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185015$11606 + cell $not $not$libresoc.v:179210$11309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:185015$11606_Y + connect \Y $not$libresoc.v:179210$11309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185016$11607 + cell $not $not$libresoc.v:179211$11310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:185016$11607_Y + connect \Y $not$libresoc.v:179211$11310_Y end - attribute \src "libresoc.v:184936.7-184936.20" - process $proc$libresoc.v:184936$11685 + attribute \src "libresoc.v:179131.7-179131.20" + process $proc$libresoc.v:179131$11388 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184961.13-184961.31" - process $proc$libresoc.v:184961$11686 + attribute \src "libresoc.v:179156.13-179156.31" + process $proc$libresoc.v:179156$11389 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end - attribute \src "libresoc.v:184968.13-184968.30" - process $proc$libresoc.v:184968$11687 + attribute \src "libresoc.v:179163.13-179163.30" + process $proc$libresoc.v:179163$11390 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end - attribute \src "libresoc.v:184974.13-184974.25" - process $proc$libresoc.v:184974$11688 + attribute \src "libresoc.v:179169.13-179169.25" + process $proc$libresoc.v:179169$11391 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:184979.13-184979.33" - process $proc$libresoc.v:184979$11689 + attribute \src "libresoc.v:179174.13-179174.33" + process $proc$libresoc.v:179174$11392 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end - attribute \src "libresoc.v:184986.13-184986.33" - process $proc$libresoc.v:184986$11690 + attribute \src "libresoc.v:179181.13-179181.33" + process $proc$libresoc.v:179181$11393 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end - attribute \src "libresoc.v:184993.13-184993.33" - process $proc$libresoc.v:184993$11691 + attribute \src "libresoc.v:179188.13-179188.33" + process $proc$libresoc.v:179188$11394 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end - attribute \src "libresoc.v:185017.3-185018.25" - process $proc$libresoc.v:185017$11608 + attribute \src "libresoc.v:179212.3-179213.25" + process $proc$libresoc.v:179212$11311 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:185019.3-185020.39" - process $proc$libresoc.v:185019$11609 + attribute \src "libresoc.v:179214.3-179215.39" + process $proc$libresoc.v:179214$11312 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end - attribute \src "libresoc.v:185021.3-185022.37" - process $proc$libresoc.v:185021$11610 + attribute \src "libresoc.v:179216.3-179217.37" + process $proc$libresoc.v:179216$11313 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end - attribute \src "libresoc.v:185023.3-185024.43" - process $proc$libresoc.v:185023$11611 + attribute \src "libresoc.v:179218.3-179219.43" + process $proc$libresoc.v:179218$11314 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end - attribute \src "libresoc.v:185025.3-185026.43" - process $proc$libresoc.v:185025$11612 + attribute \src "libresoc.v:179220.3-179221.43" + process $proc$libresoc.v:179220$11315 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end - attribute \src "libresoc.v:185027.3-185028.43" - process $proc$libresoc.v:185027$11613 + attribute \src "libresoc.v:179222.3-179223.43" + process $proc$libresoc.v:179222$11316 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end - attribute \src "libresoc.v:185029.3-185068.6" - process $proc$libresoc.v:185029$11614 + attribute \src "libresoc.v:179224.3-179263.6" + process $proc$libresoc.v:179224$11317 assign { } { } assign { } { } assign { } { } - assign $0\src13__data_o$next[3:0]$11615 $6\src13__data_o$next[3:0]$11621 - attribute \src "libresoc.v:185030.5-185030.29" + assign $0\src13__data_o$next[3:0]$11318 $6\src13__data_o$next[3:0]$11324 + attribute \src "libresoc.v:179225.5-179225.29" switch \initial - attribute \src "libresoc.v:185030.9-185030.17" + attribute \src "libresoc.v:179225.9-179225.17" case 1'1 case end @@ -379488,66 +370033,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src13__data_o$next[3:0]$11616 $5\src13__data_o$next[3:0]$11620 + assign $1\src13__data_o$next[3:0]$11319 $5\src13__data_o$next[3:0]$11323 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src13__data_o$next[3:0]$11617 \dest13__data_i + assign $2\src13__data_o$next[3:0]$11320 \dest13__data_i case - assign $2\src13__data_o$next[3:0]$11617 4'0000 + assign $2\src13__data_o$next[3:0]$11320 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src13__data_o$next[3:0]$11618 \dest23__data_i + assign $3\src13__data_o$next[3:0]$11321 \dest23__data_i case - assign $3\src13__data_o$next[3:0]$11618 $2\src13__data_o$next[3:0]$11617 + assign $3\src13__data_o$next[3:0]$11321 $2\src13__data_o$next[3:0]$11320 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src13__data_o$next[3:0]$11619 \w3__data_i + assign $4\src13__data_o$next[3:0]$11322 \w3__data_i case - assign $4\src13__data_o$next[3:0]$11619 $3\src13__data_o$next[3:0]$11618 + assign $4\src13__data_o$next[3:0]$11322 $3\src13__data_o$next[3:0]$11321 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src13__data_o$next[3:0]$11620 \reg + assign $5\src13__data_o$next[3:0]$11323 \reg case - assign $5\src13__data_o$next[3:0]$11620 $4\src13__data_o$next[3:0]$11619 + assign $5\src13__data_o$next[3:0]$11323 $4\src13__data_o$next[3:0]$11322 end case - assign $1\src13__data_o$next[3:0]$11616 4'0000 + assign $1\src13__data_o$next[3:0]$11319 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src13__data_o$next[3:0]$11621 4'0000 + assign $6\src13__data_o$next[3:0]$11324 4'0000 case - assign $6\src13__data_o$next[3:0]$11621 $1\src13__data_o$next[3:0]$11616 + assign $6\src13__data_o$next[3:0]$11324 $1\src13__data_o$next[3:0]$11319 end sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$11615 + update \src13__data_o$next $0\src13__data_o$next[3:0]$11318 end - attribute \src "libresoc.v:185069.3-185098.6" - process $proc$libresoc.v:185069$11622 + attribute \src "libresoc.v:179264.3-179293.6" + process $proc$libresoc.v:179264$11325 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:185070.5-185070.29" + attribute \src "libresoc.v:179265.5-179265.29" switch \initial - attribute \src "libresoc.v:185070.9-185070.17" + attribute \src "libresoc.v:179265.9-179265.17" case 1'1 case end @@ -379593,17 +370138,17 @@ module \reg_3 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:185099.3-185125.6" - process $proc$libresoc.v:185099$11623 + attribute \src "libresoc.v:179294.3-179320.6" + process $proc$libresoc.v:179294$11326 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11624 $4\reg$next[3:0]$11628 - attribute \src "libresoc.v:185100.5-185100.29" + assign $0\reg$next[3:0]$11327 $4\reg$next[3:0]$11331 + attribute \src "libresoc.v:179295.5-179295.29" switch \initial - attribute \src "libresoc.v:185100.9-185100.17" + attribute \src "libresoc.v:179295.9-179295.17" case 1'1 case end @@ -379612,49 +370157,49 @@ module \reg_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11625 \dest13__data_i + assign $1\reg$next[3:0]$11328 \dest13__data_i case - assign $1\reg$next[3:0]$11625 \reg + assign $1\reg$next[3:0]$11328 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11626 \dest23__data_i + assign $2\reg$next[3:0]$11329 \dest23__data_i case - assign $2\reg$next[3:0]$11626 $1\reg$next[3:0]$11625 + assign $2\reg$next[3:0]$11329 $1\reg$next[3:0]$11328 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11627 \w3__data_i + assign $3\reg$next[3:0]$11330 \w3__data_i case - assign $3\reg$next[3:0]$11627 $2\reg$next[3:0]$11626 + assign $3\reg$next[3:0]$11330 $2\reg$next[3:0]$11329 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11628 4'0000 + assign $4\reg$next[3:0]$11331 4'0000 case - assign $4\reg$next[3:0]$11628 $3\reg$next[3:0]$11627 + assign $4\reg$next[3:0]$11331 $3\reg$next[3:0]$11330 end sync always - update \reg$next $0\reg$next[3:0]$11624 + update \reg$next $0\reg$next[3:0]$11327 end - attribute \src "libresoc.v:185126.3-185165.6" - process $proc$libresoc.v:185126$11629 + attribute \src "libresoc.v:179321.3-179360.6" + process $proc$libresoc.v:179321$11332 assign { } { } assign { } { } assign { } { } - assign $0\src23__data_o$next[3:0]$11630 $6\src23__data_o$next[3:0]$11636 - attribute \src "libresoc.v:185127.5-185127.29" + assign $0\src23__data_o$next[3:0]$11333 $6\src23__data_o$next[3:0]$11339 + attribute \src "libresoc.v:179322.5-179322.29" switch \initial - attribute \src "libresoc.v:185127.9-185127.17" + attribute \src "libresoc.v:179322.9-179322.17" case 1'1 case end @@ -379666,66 +370211,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src23__data_o$next[3:0]$11631 $5\src23__data_o$next[3:0]$11635 + assign $1\src23__data_o$next[3:0]$11334 $5\src23__data_o$next[3:0]$11338 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src23__data_o$next[3:0]$11632 \dest13__data_i + assign $2\src23__data_o$next[3:0]$11335 \dest13__data_i case - assign $2\src23__data_o$next[3:0]$11632 4'0000 + assign $2\src23__data_o$next[3:0]$11335 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src23__data_o$next[3:0]$11633 \dest23__data_i + assign $3\src23__data_o$next[3:0]$11336 \dest23__data_i case - assign $3\src23__data_o$next[3:0]$11633 $2\src23__data_o$next[3:0]$11632 + assign $3\src23__data_o$next[3:0]$11336 $2\src23__data_o$next[3:0]$11335 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src23__data_o$next[3:0]$11634 \w3__data_i + assign $4\src23__data_o$next[3:0]$11337 \w3__data_i case - assign $4\src23__data_o$next[3:0]$11634 $3\src23__data_o$next[3:0]$11633 + assign $4\src23__data_o$next[3:0]$11337 $3\src23__data_o$next[3:0]$11336 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src23__data_o$next[3:0]$11635 \reg + assign $5\src23__data_o$next[3:0]$11338 \reg case - assign $5\src23__data_o$next[3:0]$11635 $4\src23__data_o$next[3:0]$11634 + assign $5\src23__data_o$next[3:0]$11338 $4\src23__data_o$next[3:0]$11337 end case - assign $1\src23__data_o$next[3:0]$11631 4'0000 + assign $1\src23__data_o$next[3:0]$11334 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src23__data_o$next[3:0]$11636 4'0000 + assign $6\src23__data_o$next[3:0]$11339 4'0000 case - assign $6\src23__data_o$next[3:0]$11636 $1\src23__data_o$next[3:0]$11631 + assign $6\src23__data_o$next[3:0]$11339 $1\src23__data_o$next[3:0]$11334 end sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$11630 + update \src23__data_o$next $0\src23__data_o$next[3:0]$11333 end - attribute \src "libresoc.v:185166.3-185195.6" - process $proc$libresoc.v:185166$11637 + attribute \src "libresoc.v:179361.3-179390.6" + process $proc$libresoc.v:179361$11340 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11638 $1\wr_detect$4[0:0]$11639 - attribute \src "libresoc.v:185167.5-185167.29" + assign $0\wr_detect$4[0:0]$11341 $1\wr_detect$4[0:0]$11342 + attribute \src "libresoc.v:179362.5-179362.29" switch \initial - attribute \src "libresoc.v:185167.9-185167.17" + attribute \src "libresoc.v:179362.9-179362.17" case 1'1 case end @@ -379737,49 +370282,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11639 $4\wr_detect$4[0:0]$11642 + assign $1\wr_detect$4[0:0]$11342 $4\wr_detect$4[0:0]$11345 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11640 1'1 + assign $2\wr_detect$4[0:0]$11343 1'1 case - assign $2\wr_detect$4[0:0]$11640 1'0 + assign $2\wr_detect$4[0:0]$11343 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11641 1'1 + assign $3\wr_detect$4[0:0]$11344 1'1 case - assign $3\wr_detect$4[0:0]$11641 $2\wr_detect$4[0:0]$11640 + assign $3\wr_detect$4[0:0]$11344 $2\wr_detect$4[0:0]$11343 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11642 1'1 + assign $4\wr_detect$4[0:0]$11345 1'1 case - assign $4\wr_detect$4[0:0]$11642 $3\wr_detect$4[0:0]$11641 + assign $4\wr_detect$4[0:0]$11345 $3\wr_detect$4[0:0]$11344 end case - assign $1\wr_detect$4[0:0]$11639 1'0 + assign $1\wr_detect$4[0:0]$11342 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11638 + update \wr_detect$4 $0\wr_detect$4[0:0]$11341 end - attribute \src "libresoc.v:185196.3-185235.6" - process $proc$libresoc.v:185196$11643 + attribute \src "libresoc.v:179391.3-179430.6" + process $proc$libresoc.v:179391$11346 assign { } { } assign { } { } assign { } { } - assign $0\src33__data_o$next[3:0]$11644 $6\src33__data_o$next[3:0]$11650 - attribute \src "libresoc.v:185197.5-185197.29" + assign $0\src33__data_o$next[3:0]$11347 $6\src33__data_o$next[3:0]$11353 + attribute \src "libresoc.v:179392.5-179392.29" switch \initial - attribute \src "libresoc.v:185197.9-185197.17" + attribute \src "libresoc.v:179392.9-179392.17" case 1'1 case end @@ -379791,66 +370336,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src33__data_o$next[3:0]$11645 $5\src33__data_o$next[3:0]$11649 + assign $1\src33__data_o$next[3:0]$11348 $5\src33__data_o$next[3:0]$11352 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src33__data_o$next[3:0]$11646 \dest13__data_i + assign $2\src33__data_o$next[3:0]$11349 \dest13__data_i case - assign $2\src33__data_o$next[3:0]$11646 4'0000 + assign $2\src33__data_o$next[3:0]$11349 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src33__data_o$next[3:0]$11647 \dest23__data_i + assign $3\src33__data_o$next[3:0]$11350 \dest23__data_i case - assign $3\src33__data_o$next[3:0]$11647 $2\src33__data_o$next[3:0]$11646 + assign $3\src33__data_o$next[3:0]$11350 $2\src33__data_o$next[3:0]$11349 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src33__data_o$next[3:0]$11648 \w3__data_i + assign $4\src33__data_o$next[3:0]$11351 \w3__data_i case - assign $4\src33__data_o$next[3:0]$11648 $3\src33__data_o$next[3:0]$11647 + assign $4\src33__data_o$next[3:0]$11351 $3\src33__data_o$next[3:0]$11350 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src33__data_o$next[3:0]$11649 \reg + assign $5\src33__data_o$next[3:0]$11352 \reg case - assign $5\src33__data_o$next[3:0]$11649 $4\src33__data_o$next[3:0]$11648 + assign $5\src33__data_o$next[3:0]$11352 $4\src33__data_o$next[3:0]$11351 end case - assign $1\src33__data_o$next[3:0]$11645 4'0000 + assign $1\src33__data_o$next[3:0]$11348 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src33__data_o$next[3:0]$11650 4'0000 + assign $6\src33__data_o$next[3:0]$11353 4'0000 case - assign $6\src33__data_o$next[3:0]$11650 $1\src33__data_o$next[3:0]$11645 + assign $6\src33__data_o$next[3:0]$11353 $1\src33__data_o$next[3:0]$11348 end sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$11644 + update \src33__data_o$next $0\src33__data_o$next[3:0]$11347 end - attribute \src "libresoc.v:185236.3-185265.6" - process $proc$libresoc.v:185236$11651 + attribute \src "libresoc.v:179431.3-179460.6" + process $proc$libresoc.v:179431$11354 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11652 $1\wr_detect$7[0:0]$11653 - attribute \src "libresoc.v:185237.5-185237.29" + assign $0\wr_detect$7[0:0]$11355 $1\wr_detect$7[0:0]$11356 + attribute \src "libresoc.v:179432.5-179432.29" switch \initial - attribute \src "libresoc.v:185237.9-185237.17" + attribute \src "libresoc.v:179432.9-179432.17" case 1'1 case end @@ -379862,49 +370407,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11653 $4\wr_detect$7[0:0]$11656 + assign $1\wr_detect$7[0:0]$11356 $4\wr_detect$7[0:0]$11359 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11654 1'1 + assign $2\wr_detect$7[0:0]$11357 1'1 case - assign $2\wr_detect$7[0:0]$11654 1'0 + assign $2\wr_detect$7[0:0]$11357 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11655 1'1 + assign $3\wr_detect$7[0:0]$11358 1'1 case - assign $3\wr_detect$7[0:0]$11655 $2\wr_detect$7[0:0]$11654 + assign $3\wr_detect$7[0:0]$11358 $2\wr_detect$7[0:0]$11357 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11656 1'1 + assign $4\wr_detect$7[0:0]$11359 1'1 case - assign $4\wr_detect$7[0:0]$11656 $3\wr_detect$7[0:0]$11655 + assign $4\wr_detect$7[0:0]$11359 $3\wr_detect$7[0:0]$11358 end case - assign $1\wr_detect$7[0:0]$11653 1'0 + assign $1\wr_detect$7[0:0]$11356 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11652 + update \wr_detect$7 $0\wr_detect$7[0:0]$11355 end - attribute \src "libresoc.v:185266.3-185305.6" - process $proc$libresoc.v:185266$11657 + attribute \src "libresoc.v:179461.3-179500.6" + process $proc$libresoc.v:179461$11360 assign { } { } assign { } { } assign { } { } - assign $0\r3__data_o$next[3:0]$11658 $6\r3__data_o$next[3:0]$11664 - attribute \src "libresoc.v:185267.5-185267.29" + assign $0\r3__data_o$next[3:0]$11361 $6\r3__data_o$next[3:0]$11367 + attribute \src "libresoc.v:179462.5-179462.29" switch \initial - attribute \src "libresoc.v:185267.9-185267.17" + attribute \src "libresoc.v:179462.9-179462.17" case 1'1 case end @@ -379916,66 +370461,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r3__data_o$next[3:0]$11659 $5\r3__data_o$next[3:0]$11663 + assign $1\r3__data_o$next[3:0]$11362 $5\r3__data_o$next[3:0]$11366 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r3__data_o$next[3:0]$11660 \dest13__data_i + assign $2\r3__data_o$next[3:0]$11363 \dest13__data_i case - assign $2\r3__data_o$next[3:0]$11660 4'0000 + assign $2\r3__data_o$next[3:0]$11363 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r3__data_o$next[3:0]$11661 \dest23__data_i + assign $3\r3__data_o$next[3:0]$11364 \dest23__data_i case - assign $3\r3__data_o$next[3:0]$11661 $2\r3__data_o$next[3:0]$11660 + assign $3\r3__data_o$next[3:0]$11364 $2\r3__data_o$next[3:0]$11363 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r3__data_o$next[3:0]$11662 \w3__data_i + assign $4\r3__data_o$next[3:0]$11365 \w3__data_i case - assign $4\r3__data_o$next[3:0]$11662 $3\r3__data_o$next[3:0]$11661 + assign $4\r3__data_o$next[3:0]$11365 $3\r3__data_o$next[3:0]$11364 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r3__data_o$next[3:0]$11663 \reg + assign $5\r3__data_o$next[3:0]$11366 \reg case - assign $5\r3__data_o$next[3:0]$11663 $4\r3__data_o$next[3:0]$11662 + assign $5\r3__data_o$next[3:0]$11366 $4\r3__data_o$next[3:0]$11365 end case - assign $1\r3__data_o$next[3:0]$11659 4'0000 + assign $1\r3__data_o$next[3:0]$11362 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r3__data_o$next[3:0]$11664 4'0000 + assign $6\r3__data_o$next[3:0]$11367 4'0000 case - assign $6\r3__data_o$next[3:0]$11664 $1\r3__data_o$next[3:0]$11659 + assign $6\r3__data_o$next[3:0]$11367 $1\r3__data_o$next[3:0]$11362 end sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$11658 + update \r3__data_o$next $0\r3__data_o$next[3:0]$11361 end - attribute \src "libresoc.v:185306.3-185335.6" - process $proc$libresoc.v:185306$11665 + attribute \src "libresoc.v:179501.3-179530.6" + process $proc$libresoc.v:179501$11368 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11666 $1\wr_detect$10[0:0]$11667 - attribute \src "libresoc.v:185307.5-185307.29" + assign $0\wr_detect$10[0:0]$11369 $1\wr_detect$10[0:0]$11370 + attribute \src "libresoc.v:179502.5-179502.29" switch \initial - attribute \src "libresoc.v:185307.9-185307.17" + attribute \src "libresoc.v:179502.9-179502.17" case 1'1 case end @@ -379987,49 +370532,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11667 $4\wr_detect$10[0:0]$11670 + assign $1\wr_detect$10[0:0]$11370 $4\wr_detect$10[0:0]$11373 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11668 1'1 + assign $2\wr_detect$10[0:0]$11371 1'1 case - assign $2\wr_detect$10[0:0]$11668 1'0 + assign $2\wr_detect$10[0:0]$11371 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11669 1'1 + assign $3\wr_detect$10[0:0]$11372 1'1 case - assign $3\wr_detect$10[0:0]$11669 $2\wr_detect$10[0:0]$11668 + assign $3\wr_detect$10[0:0]$11372 $2\wr_detect$10[0:0]$11371 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11670 1'1 + assign $4\wr_detect$10[0:0]$11373 1'1 case - assign $4\wr_detect$10[0:0]$11670 $3\wr_detect$10[0:0]$11669 + assign $4\wr_detect$10[0:0]$11373 $3\wr_detect$10[0:0]$11372 end case - assign $1\wr_detect$10[0:0]$11667 1'0 + assign $1\wr_detect$10[0:0]$11370 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11666 + update \wr_detect$10 $0\wr_detect$10[0:0]$11369 end - attribute \src "libresoc.v:185336.3-185375.6" - process $proc$libresoc.v:185336$11671 + attribute \src "libresoc.v:179531.3-179570.6" + process $proc$libresoc.v:179531$11374 assign { } { } assign { } { } assign { } { } - assign $0\r23__data_o$next[3:0]$11672 $6\r23__data_o$next[3:0]$11678 - attribute \src "libresoc.v:185337.5-185337.29" + assign $0\r23__data_o$next[3:0]$11375 $6\r23__data_o$next[3:0]$11381 + attribute \src "libresoc.v:179532.5-179532.29" switch \initial - attribute \src "libresoc.v:185337.9-185337.17" + attribute \src "libresoc.v:179532.9-179532.17" case 1'1 case end @@ -380041,66 +370586,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r23__data_o$next[3:0]$11673 $5\r23__data_o$next[3:0]$11677 + assign $1\r23__data_o$next[3:0]$11376 $5\r23__data_o$next[3:0]$11380 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r23__data_o$next[3:0]$11674 \dest13__data_i + assign $2\r23__data_o$next[3:0]$11377 \dest13__data_i case - assign $2\r23__data_o$next[3:0]$11674 4'0000 + assign $2\r23__data_o$next[3:0]$11377 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r23__data_o$next[3:0]$11675 \dest23__data_i + assign $3\r23__data_o$next[3:0]$11378 \dest23__data_i case - assign $3\r23__data_o$next[3:0]$11675 $2\r23__data_o$next[3:0]$11674 + assign $3\r23__data_o$next[3:0]$11378 $2\r23__data_o$next[3:0]$11377 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r23__data_o$next[3:0]$11676 \w3__data_i + assign $4\r23__data_o$next[3:0]$11379 \w3__data_i case - assign $4\r23__data_o$next[3:0]$11676 $3\r23__data_o$next[3:0]$11675 + assign $4\r23__data_o$next[3:0]$11379 $3\r23__data_o$next[3:0]$11378 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r23__data_o$next[3:0]$11677 \reg + assign $5\r23__data_o$next[3:0]$11380 \reg case - assign $5\r23__data_o$next[3:0]$11677 $4\r23__data_o$next[3:0]$11676 + assign $5\r23__data_o$next[3:0]$11380 $4\r23__data_o$next[3:0]$11379 end case - assign $1\r23__data_o$next[3:0]$11673 4'0000 + assign $1\r23__data_o$next[3:0]$11376 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r23__data_o$next[3:0]$11678 4'0000 + assign $6\r23__data_o$next[3:0]$11381 4'0000 case - assign $6\r23__data_o$next[3:0]$11678 $1\r23__data_o$next[3:0]$11673 + assign $6\r23__data_o$next[3:0]$11381 $1\r23__data_o$next[3:0]$11376 end sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$11672 + update \r23__data_o$next $0\r23__data_o$next[3:0]$11375 end - attribute \src "libresoc.v:185376.3-185405.6" - process $proc$libresoc.v:185376$11679 + attribute \src "libresoc.v:179571.3-179600.6" + process $proc$libresoc.v:179571$11382 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11680 $1\wr_detect$13[0:0]$11681 - attribute \src "libresoc.v:185377.5-185377.29" + assign $0\wr_detect$13[0:0]$11383 $1\wr_detect$13[0:0]$11384 + attribute \src "libresoc.v:179572.5-179572.29" switch \initial - attribute \src "libresoc.v:185377.9-185377.17" + attribute \src "libresoc.v:179572.9-179572.17" case 1'1 case end @@ -380112,217 +370657,217 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11681 $4\wr_detect$13[0:0]$11684 + assign $1\wr_detect$13[0:0]$11384 $4\wr_detect$13[0:0]$11387 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11682 1'1 + assign $2\wr_detect$13[0:0]$11385 1'1 case - assign $2\wr_detect$13[0:0]$11682 1'0 + assign $2\wr_detect$13[0:0]$11385 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11683 1'1 + assign $3\wr_detect$13[0:0]$11386 1'1 case - assign $3\wr_detect$13[0:0]$11683 $2\wr_detect$13[0:0]$11682 + assign $3\wr_detect$13[0:0]$11386 $2\wr_detect$13[0:0]$11385 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11684 1'1 + assign $4\wr_detect$13[0:0]$11387 1'1 case - assign $4\wr_detect$13[0:0]$11684 $3\wr_detect$13[0:0]$11683 + assign $4\wr_detect$13[0:0]$11387 $3\wr_detect$13[0:0]$11386 end case - assign $1\wr_detect$13[0:0]$11681 1'0 + assign $1\wr_detect$13[0:0]$11384 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11680 + update \wr_detect$13 $0\wr_detect$13[0:0]$11383 end - connect \$9 $not$libresoc.v:185012$11603_Y - connect \$12 $not$libresoc.v:185013$11604_Y - connect \$1 $not$libresoc.v:185014$11605_Y - connect \$3 $not$libresoc.v:185015$11606_Y - connect \$6 $not$libresoc.v:185016$11607_Y + connect \$9 $not$libresoc.v:179207$11306_Y + connect \$12 $not$libresoc.v:179208$11307_Y + connect \$1 $not$libresoc.v:179209$11308_Y + connect \$3 $not$libresoc.v:179210$11309_Y + connect \$6 $not$libresoc.v:179211$11310_Y end -attribute \src "libresoc.v:185410.1-185881.10" +attribute \src "libresoc.v:179605.1-180076.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 - attribute \src "libresoc.v:185411.7-185411.20" + attribute \src "libresoc.v:179606.7-179606.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185811.3-185850.6" - wire width 4 $0\r24__data_o$next[3:0]$11761 - attribute \src "libresoc.v:185494.3-185495.39" + attribute \src "libresoc.v:180006.3-180045.6" + wire width 4 $0\r24__data_o$next[3:0]$11464 + attribute \src "libresoc.v:179689.3-179690.39" wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:185741.3-185780.6" - wire width 4 $0\r4__data_o$next[3:0]$11747 - attribute \src "libresoc.v:185496.3-185497.37" + attribute \src "libresoc.v:179936.3-179975.6" + wire width 4 $0\r4__data_o$next[3:0]$11450 + attribute \src "libresoc.v:179691.3-179692.37" wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:185574.3-185600.6" - wire width 4 $0\reg$next[3:0]$11713 - attribute \src "libresoc.v:185492.3-185493.25" + attribute \src "libresoc.v:179769.3-179795.6" + wire width 4 $0\reg$next[3:0]$11416 + attribute \src "libresoc.v:179687.3-179688.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:185504.3-185543.6" - wire width 4 $0\src14__data_o$next[3:0]$11704 - attribute \src "libresoc.v:185502.3-185503.43" + attribute \src "libresoc.v:179699.3-179738.6" + wire width 4 $0\src14__data_o$next[3:0]$11407 + attribute \src "libresoc.v:179697.3-179698.43" wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:185601.3-185640.6" - wire width 4 $0\src24__data_o$next[3:0]$11719 - attribute \src "libresoc.v:185500.3-185501.43" + attribute \src "libresoc.v:179796.3-179835.6" + wire width 4 $0\src24__data_o$next[3:0]$11422 + attribute \src "libresoc.v:179695.3-179696.43" wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:185671.3-185710.6" - wire width 4 $0\src34__data_o$next[3:0]$11733 - attribute \src "libresoc.v:185498.3-185499.43" + attribute \src "libresoc.v:179866.3-179905.6" + wire width 4 $0\src34__data_o$next[3:0]$11436 + attribute \src "libresoc.v:179693.3-179694.43" wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:185781.3-185810.6" - wire $0\wr_detect$10[0:0]$11755 - attribute \src "libresoc.v:185851.3-185880.6" - wire $0\wr_detect$13[0:0]$11769 - attribute \src "libresoc.v:185641.3-185670.6" - wire $0\wr_detect$4[0:0]$11727 - attribute \src "libresoc.v:185711.3-185740.6" - wire $0\wr_detect$7[0:0]$11741 - attribute \src "libresoc.v:185544.3-185573.6" + attribute \src "libresoc.v:179976.3-180005.6" + wire $0\wr_detect$10[0:0]$11458 + attribute \src "libresoc.v:180046.3-180075.6" + wire $0\wr_detect$13[0:0]$11472 + attribute \src "libresoc.v:179836.3-179865.6" + wire $0\wr_detect$4[0:0]$11430 + attribute \src "libresoc.v:179906.3-179935.6" + wire $0\wr_detect$7[0:0]$11444 + attribute \src "libresoc.v:179739.3-179768.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:185811.3-185850.6" - wire width 4 $1\r24__data_o$next[3:0]$11762 - attribute \src "libresoc.v:185436.13-185436.31" + attribute \src "libresoc.v:180006.3-180045.6" + wire width 4 $1\r24__data_o$next[3:0]$11465 + attribute \src "libresoc.v:179631.13-179631.31" wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:185741.3-185780.6" - wire width 4 $1\r4__data_o$next[3:0]$11748 - attribute \src "libresoc.v:185443.13-185443.30" + attribute \src "libresoc.v:179936.3-179975.6" + wire width 4 $1\r4__data_o$next[3:0]$11451 + attribute \src "libresoc.v:179638.13-179638.30" wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:185574.3-185600.6" - wire width 4 $1\reg$next[3:0]$11714 - attribute \src "libresoc.v:185449.13-185449.25" + attribute \src "libresoc.v:179769.3-179795.6" + wire width 4 $1\reg$next[3:0]$11417 + attribute \src "libresoc.v:179644.13-179644.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:185504.3-185543.6" - wire width 4 $1\src14__data_o$next[3:0]$11705 - attribute \src "libresoc.v:185454.13-185454.33" + attribute \src "libresoc.v:179699.3-179738.6" + wire width 4 $1\src14__data_o$next[3:0]$11408 + attribute \src "libresoc.v:179649.13-179649.33" wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:185601.3-185640.6" - wire width 4 $1\src24__data_o$next[3:0]$11720 - attribute \src "libresoc.v:185461.13-185461.33" + attribute \src "libresoc.v:179796.3-179835.6" + wire width 4 $1\src24__data_o$next[3:0]$11423 + attribute \src "libresoc.v:179656.13-179656.33" wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:185671.3-185710.6" - wire width 4 $1\src34__data_o$next[3:0]$11734 - attribute \src "libresoc.v:185468.13-185468.33" + attribute \src "libresoc.v:179866.3-179905.6" + wire width 4 $1\src34__data_o$next[3:0]$11437 + attribute \src "libresoc.v:179663.13-179663.33" wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:185781.3-185810.6" - wire $1\wr_detect$10[0:0]$11756 - attribute \src "libresoc.v:185851.3-185880.6" - wire $1\wr_detect$13[0:0]$11770 - attribute \src "libresoc.v:185641.3-185670.6" - wire $1\wr_detect$4[0:0]$11728 - attribute \src "libresoc.v:185711.3-185740.6" - wire $1\wr_detect$7[0:0]$11742 - attribute \src "libresoc.v:185544.3-185573.6" + attribute \src "libresoc.v:179976.3-180005.6" + wire $1\wr_detect$10[0:0]$11459 + attribute \src "libresoc.v:180046.3-180075.6" + wire $1\wr_detect$13[0:0]$11473 + attribute \src "libresoc.v:179836.3-179865.6" + wire $1\wr_detect$4[0:0]$11431 + attribute \src "libresoc.v:179906.3-179935.6" + wire $1\wr_detect$7[0:0]$11445 + attribute \src "libresoc.v:179739.3-179768.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:185811.3-185850.6" - wire width 4 $2\r24__data_o$next[3:0]$11763 - attribute \src "libresoc.v:185741.3-185780.6" - wire width 4 $2\r4__data_o$next[3:0]$11749 - attribute \src "libresoc.v:185574.3-185600.6" - wire width 4 $2\reg$next[3:0]$11715 - attribute \src "libresoc.v:185504.3-185543.6" - wire width 4 $2\src14__data_o$next[3:0]$11706 - attribute \src "libresoc.v:185601.3-185640.6" - wire width 4 $2\src24__data_o$next[3:0]$11721 - attribute \src "libresoc.v:185671.3-185710.6" - wire width 4 $2\src34__data_o$next[3:0]$11735 - attribute \src "libresoc.v:185781.3-185810.6" - wire $2\wr_detect$10[0:0]$11757 - attribute \src "libresoc.v:185851.3-185880.6" - wire $2\wr_detect$13[0:0]$11771 - attribute \src "libresoc.v:185641.3-185670.6" - wire $2\wr_detect$4[0:0]$11729 - attribute \src "libresoc.v:185711.3-185740.6" - wire $2\wr_detect$7[0:0]$11743 - attribute \src "libresoc.v:185544.3-185573.6" + attribute \src "libresoc.v:180006.3-180045.6" + wire width 4 $2\r24__data_o$next[3:0]$11466 + attribute \src "libresoc.v:179936.3-179975.6" + wire width 4 $2\r4__data_o$next[3:0]$11452 + attribute \src "libresoc.v:179769.3-179795.6" + wire width 4 $2\reg$next[3:0]$11418 + attribute \src "libresoc.v:179699.3-179738.6" + wire width 4 $2\src14__data_o$next[3:0]$11409 + attribute \src "libresoc.v:179796.3-179835.6" + wire width 4 $2\src24__data_o$next[3:0]$11424 + attribute \src "libresoc.v:179866.3-179905.6" + wire width 4 $2\src34__data_o$next[3:0]$11438 + attribute \src "libresoc.v:179976.3-180005.6" + wire $2\wr_detect$10[0:0]$11460 + attribute \src "libresoc.v:180046.3-180075.6" + wire $2\wr_detect$13[0:0]$11474 + attribute \src "libresoc.v:179836.3-179865.6" + wire $2\wr_detect$4[0:0]$11432 + attribute \src "libresoc.v:179906.3-179935.6" + wire $2\wr_detect$7[0:0]$11446 + attribute \src "libresoc.v:179739.3-179768.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:185811.3-185850.6" - wire width 4 $3\r24__data_o$next[3:0]$11764 - attribute \src "libresoc.v:185741.3-185780.6" - wire width 4 $3\r4__data_o$next[3:0]$11750 - attribute \src "libresoc.v:185574.3-185600.6" - wire width 4 $3\reg$next[3:0]$11716 - attribute \src "libresoc.v:185504.3-185543.6" - wire width 4 $3\src14__data_o$next[3:0]$11707 - attribute \src "libresoc.v:185601.3-185640.6" - wire width 4 $3\src24__data_o$next[3:0]$11722 - attribute \src "libresoc.v:185671.3-185710.6" - wire width 4 $3\src34__data_o$next[3:0]$11736 - attribute \src "libresoc.v:185781.3-185810.6" - wire $3\wr_detect$10[0:0]$11758 - attribute \src "libresoc.v:185851.3-185880.6" - wire $3\wr_detect$13[0:0]$11772 - attribute \src "libresoc.v:185641.3-185670.6" - wire $3\wr_detect$4[0:0]$11730 - attribute \src "libresoc.v:185711.3-185740.6" - wire $3\wr_detect$7[0:0]$11744 - attribute \src "libresoc.v:185544.3-185573.6" + attribute \src "libresoc.v:180006.3-180045.6" + wire width 4 $3\r24__data_o$next[3:0]$11467 + attribute \src "libresoc.v:179936.3-179975.6" + wire width 4 $3\r4__data_o$next[3:0]$11453 + attribute \src "libresoc.v:179769.3-179795.6" + wire width 4 $3\reg$next[3:0]$11419 + attribute \src "libresoc.v:179699.3-179738.6" + wire width 4 $3\src14__data_o$next[3:0]$11410 + attribute \src "libresoc.v:179796.3-179835.6" + wire width 4 $3\src24__data_o$next[3:0]$11425 + attribute \src "libresoc.v:179866.3-179905.6" + wire width 4 $3\src34__data_o$next[3:0]$11439 + attribute \src "libresoc.v:179976.3-180005.6" + wire $3\wr_detect$10[0:0]$11461 + attribute \src "libresoc.v:180046.3-180075.6" + wire $3\wr_detect$13[0:0]$11475 + attribute \src "libresoc.v:179836.3-179865.6" + wire $3\wr_detect$4[0:0]$11433 + attribute \src "libresoc.v:179906.3-179935.6" + wire $3\wr_detect$7[0:0]$11447 + attribute \src "libresoc.v:179739.3-179768.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:185811.3-185850.6" - wire width 4 $4\r24__data_o$next[3:0]$11765 - attribute \src "libresoc.v:185741.3-185780.6" - wire width 4 $4\r4__data_o$next[3:0]$11751 - attribute \src "libresoc.v:185574.3-185600.6" - wire width 4 $4\reg$next[3:0]$11717 - attribute \src "libresoc.v:185504.3-185543.6" - wire width 4 $4\src14__data_o$next[3:0]$11708 - attribute \src "libresoc.v:185601.3-185640.6" - wire width 4 $4\src24__data_o$next[3:0]$11723 - attribute \src "libresoc.v:185671.3-185710.6" - wire width 4 $4\src34__data_o$next[3:0]$11737 - attribute \src "libresoc.v:185781.3-185810.6" - wire $4\wr_detect$10[0:0]$11759 - attribute \src "libresoc.v:185851.3-185880.6" - wire $4\wr_detect$13[0:0]$11773 - attribute \src "libresoc.v:185641.3-185670.6" - wire $4\wr_detect$4[0:0]$11731 - attribute \src "libresoc.v:185711.3-185740.6" - wire $4\wr_detect$7[0:0]$11745 - attribute \src "libresoc.v:185544.3-185573.6" + attribute \src "libresoc.v:180006.3-180045.6" + wire width 4 $4\r24__data_o$next[3:0]$11468 + attribute \src "libresoc.v:179936.3-179975.6" + wire width 4 $4\r4__data_o$next[3:0]$11454 + attribute \src "libresoc.v:179769.3-179795.6" + wire width 4 $4\reg$next[3:0]$11420 + attribute \src "libresoc.v:179699.3-179738.6" + wire width 4 $4\src14__data_o$next[3:0]$11411 + attribute \src "libresoc.v:179796.3-179835.6" + wire width 4 $4\src24__data_o$next[3:0]$11426 + attribute \src "libresoc.v:179866.3-179905.6" + wire width 4 $4\src34__data_o$next[3:0]$11440 + attribute \src "libresoc.v:179976.3-180005.6" + wire $4\wr_detect$10[0:0]$11462 + attribute \src "libresoc.v:180046.3-180075.6" + wire $4\wr_detect$13[0:0]$11476 + attribute \src "libresoc.v:179836.3-179865.6" + wire $4\wr_detect$4[0:0]$11434 + attribute \src "libresoc.v:179906.3-179935.6" + wire $4\wr_detect$7[0:0]$11448 + attribute \src "libresoc.v:179739.3-179768.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:185811.3-185850.6" - wire width 4 $5\r24__data_o$next[3:0]$11766 - attribute \src "libresoc.v:185741.3-185780.6" - wire width 4 $5\r4__data_o$next[3:0]$11752 - attribute \src "libresoc.v:185504.3-185543.6" - wire width 4 $5\src14__data_o$next[3:0]$11709 - attribute \src "libresoc.v:185601.3-185640.6" - wire width 4 $5\src24__data_o$next[3:0]$11724 - attribute \src "libresoc.v:185671.3-185710.6" - wire width 4 $5\src34__data_o$next[3:0]$11738 - attribute \src "libresoc.v:185811.3-185850.6" - wire width 4 $6\r24__data_o$next[3:0]$11767 - attribute \src "libresoc.v:185741.3-185780.6" - wire width 4 $6\r4__data_o$next[3:0]$11753 - attribute \src "libresoc.v:185504.3-185543.6" - wire width 4 $6\src14__data_o$next[3:0]$11710 - attribute \src "libresoc.v:185601.3-185640.6" - wire width 4 $6\src24__data_o$next[3:0]$11725 - attribute \src "libresoc.v:185671.3-185710.6" - wire width 4 $6\src34__data_o$next[3:0]$11739 - attribute \src "libresoc.v:185487.17-185487.104" - wire $not$libresoc.v:185487$11692_Y - attribute \src "libresoc.v:185488.18-185488.105" - wire $not$libresoc.v:185488$11693_Y - attribute \src "libresoc.v:185489.17-185489.100" - wire $not$libresoc.v:185489$11694_Y - attribute \src "libresoc.v:185490.17-185490.103" - wire $not$libresoc.v:185490$11695_Y - attribute \src "libresoc.v:185491.17-185491.103" - wire $not$libresoc.v:185491$11696_Y + attribute \src "libresoc.v:180006.3-180045.6" + wire width 4 $5\r24__data_o$next[3:0]$11469 + attribute \src "libresoc.v:179936.3-179975.6" + wire width 4 $5\r4__data_o$next[3:0]$11455 + attribute \src "libresoc.v:179699.3-179738.6" + wire width 4 $5\src14__data_o$next[3:0]$11412 + attribute \src "libresoc.v:179796.3-179835.6" + wire width 4 $5\src24__data_o$next[3:0]$11427 + attribute \src "libresoc.v:179866.3-179905.6" + wire width 4 $5\src34__data_o$next[3:0]$11441 + attribute \src "libresoc.v:180006.3-180045.6" + wire width 4 $6\r24__data_o$next[3:0]$11470 + attribute \src "libresoc.v:179936.3-179975.6" + wire width 4 $6\r4__data_o$next[3:0]$11456 + attribute \src "libresoc.v:179699.3-179738.6" + wire width 4 $6\src14__data_o$next[3:0]$11413 + attribute \src "libresoc.v:179796.3-179835.6" + wire width 4 $6\src24__data_o$next[3:0]$11428 + attribute \src "libresoc.v:179866.3-179905.6" + wire width 4 $6\src34__data_o$next[3:0]$11442 + attribute \src "libresoc.v:179682.17-179682.104" + wire $not$libresoc.v:179682$11395_Y + attribute \src "libresoc.v:179683.18-179683.105" + wire $not$libresoc.v:179683$11396_Y + attribute \src "libresoc.v:179684.17-179684.100" + wire $not$libresoc.v:179684$11397_Y + attribute \src "libresoc.v:179685.17-179685.103" + wire $not$libresoc.v:179685$11398_Y + attribute \src "libresoc.v:179686.17-179686.103" + wire $not$libresoc.v:179686$11399_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -380333,9 +370878,9 @@ module \reg_4 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest14__data_i @@ -380345,7 +370890,7 @@ module \reg_4 wire width 4 input 11 \dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest24__wen - attribute \src "libresoc.v:185411.7-185411.15" + attribute \src "libresoc.v:179606.7-179606.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r24__data_o @@ -380396,152 +370941,152 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185487$11692 + cell $not $not$libresoc.v:179682$11395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:185487$11692_Y + connect \Y $not$libresoc.v:179682$11395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185488$11693 + cell $not $not$libresoc.v:179683$11396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:185488$11693_Y + connect \Y $not$libresoc.v:179683$11396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185489$11694 + cell $not $not$libresoc.v:179684$11397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:185489$11694_Y + connect \Y $not$libresoc.v:179684$11397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185490$11695 + cell $not $not$libresoc.v:179685$11398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:185490$11695_Y + connect \Y $not$libresoc.v:179685$11398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185491$11696 + cell $not $not$libresoc.v:179686$11399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:185491$11696_Y + connect \Y $not$libresoc.v:179686$11399_Y end - attribute \src "libresoc.v:185411.7-185411.20" - process $proc$libresoc.v:185411$11774 + attribute \src "libresoc.v:179606.7-179606.20" + process $proc$libresoc.v:179606$11477 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185436.13-185436.31" - process $proc$libresoc.v:185436$11775 + attribute \src "libresoc.v:179631.13-179631.31" + process $proc$libresoc.v:179631$11478 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end - attribute \src "libresoc.v:185443.13-185443.30" - process $proc$libresoc.v:185443$11776 + attribute \src "libresoc.v:179638.13-179638.30" + process $proc$libresoc.v:179638$11479 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end - attribute \src "libresoc.v:185449.13-185449.25" - process $proc$libresoc.v:185449$11777 + attribute \src "libresoc.v:179644.13-179644.25" + process $proc$libresoc.v:179644$11480 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:185454.13-185454.33" - process $proc$libresoc.v:185454$11778 + attribute \src "libresoc.v:179649.13-179649.33" + process $proc$libresoc.v:179649$11481 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end - attribute \src "libresoc.v:185461.13-185461.33" - process $proc$libresoc.v:185461$11779 + attribute \src "libresoc.v:179656.13-179656.33" + process $proc$libresoc.v:179656$11482 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end - attribute \src "libresoc.v:185468.13-185468.33" - process $proc$libresoc.v:185468$11780 + attribute \src "libresoc.v:179663.13-179663.33" + process $proc$libresoc.v:179663$11483 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end - attribute \src "libresoc.v:185492.3-185493.25" - process $proc$libresoc.v:185492$11697 + attribute \src "libresoc.v:179687.3-179688.25" + process $proc$libresoc.v:179687$11400 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:185494.3-185495.39" - process $proc$libresoc.v:185494$11698 + attribute \src "libresoc.v:179689.3-179690.39" + process $proc$libresoc.v:179689$11401 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end - attribute \src "libresoc.v:185496.3-185497.37" - process $proc$libresoc.v:185496$11699 + attribute \src "libresoc.v:179691.3-179692.37" + process $proc$libresoc.v:179691$11402 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end - attribute \src "libresoc.v:185498.3-185499.43" - process $proc$libresoc.v:185498$11700 + attribute \src "libresoc.v:179693.3-179694.43" + process $proc$libresoc.v:179693$11403 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end - attribute \src "libresoc.v:185500.3-185501.43" - process $proc$libresoc.v:185500$11701 + attribute \src "libresoc.v:179695.3-179696.43" + process $proc$libresoc.v:179695$11404 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end - attribute \src "libresoc.v:185502.3-185503.43" - process $proc$libresoc.v:185502$11702 + attribute \src "libresoc.v:179697.3-179698.43" + process $proc$libresoc.v:179697$11405 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end - attribute \src "libresoc.v:185504.3-185543.6" - process $proc$libresoc.v:185504$11703 + attribute \src "libresoc.v:179699.3-179738.6" + process $proc$libresoc.v:179699$11406 assign { } { } assign { } { } assign { } { } - assign $0\src14__data_o$next[3:0]$11704 $6\src14__data_o$next[3:0]$11710 - attribute \src "libresoc.v:185505.5-185505.29" + assign $0\src14__data_o$next[3:0]$11407 $6\src14__data_o$next[3:0]$11413 + attribute \src "libresoc.v:179700.5-179700.29" switch \initial - attribute \src "libresoc.v:185505.9-185505.17" + attribute \src "libresoc.v:179700.9-179700.17" case 1'1 case end @@ -380553,66 +371098,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src14__data_o$next[3:0]$11705 $5\src14__data_o$next[3:0]$11709 + assign $1\src14__data_o$next[3:0]$11408 $5\src14__data_o$next[3:0]$11412 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src14__data_o$next[3:0]$11706 \dest14__data_i + assign $2\src14__data_o$next[3:0]$11409 \dest14__data_i case - assign $2\src14__data_o$next[3:0]$11706 4'0000 + assign $2\src14__data_o$next[3:0]$11409 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src14__data_o$next[3:0]$11707 \dest24__data_i + assign $3\src14__data_o$next[3:0]$11410 \dest24__data_i case - assign $3\src14__data_o$next[3:0]$11707 $2\src14__data_o$next[3:0]$11706 + assign $3\src14__data_o$next[3:0]$11410 $2\src14__data_o$next[3:0]$11409 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src14__data_o$next[3:0]$11708 \w4__data_i + assign $4\src14__data_o$next[3:0]$11411 \w4__data_i case - assign $4\src14__data_o$next[3:0]$11708 $3\src14__data_o$next[3:0]$11707 + assign $4\src14__data_o$next[3:0]$11411 $3\src14__data_o$next[3:0]$11410 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src14__data_o$next[3:0]$11709 \reg + assign $5\src14__data_o$next[3:0]$11412 \reg case - assign $5\src14__data_o$next[3:0]$11709 $4\src14__data_o$next[3:0]$11708 + assign $5\src14__data_o$next[3:0]$11412 $4\src14__data_o$next[3:0]$11411 end case - assign $1\src14__data_o$next[3:0]$11705 4'0000 + assign $1\src14__data_o$next[3:0]$11408 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src14__data_o$next[3:0]$11710 4'0000 + assign $6\src14__data_o$next[3:0]$11413 4'0000 case - assign $6\src14__data_o$next[3:0]$11710 $1\src14__data_o$next[3:0]$11705 + assign $6\src14__data_o$next[3:0]$11413 $1\src14__data_o$next[3:0]$11408 end sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$11704 + update \src14__data_o$next $0\src14__data_o$next[3:0]$11407 end - attribute \src "libresoc.v:185544.3-185573.6" - process $proc$libresoc.v:185544$11711 + attribute \src "libresoc.v:179739.3-179768.6" + process $proc$libresoc.v:179739$11414 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:185545.5-185545.29" + attribute \src "libresoc.v:179740.5-179740.29" switch \initial - attribute \src "libresoc.v:185545.9-185545.17" + attribute \src "libresoc.v:179740.9-179740.17" case 1'1 case end @@ -380658,17 +371203,17 @@ module \reg_4 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:185574.3-185600.6" - process $proc$libresoc.v:185574$11712 + attribute \src "libresoc.v:179769.3-179795.6" + process $proc$libresoc.v:179769$11415 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11713 $4\reg$next[3:0]$11717 - attribute \src "libresoc.v:185575.5-185575.29" + assign $0\reg$next[3:0]$11416 $4\reg$next[3:0]$11420 + attribute \src "libresoc.v:179770.5-179770.29" switch \initial - attribute \src "libresoc.v:185575.9-185575.17" + attribute \src "libresoc.v:179770.9-179770.17" case 1'1 case end @@ -380677,49 +371222,49 @@ module \reg_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11714 \dest14__data_i + assign $1\reg$next[3:0]$11417 \dest14__data_i case - assign $1\reg$next[3:0]$11714 \reg + assign $1\reg$next[3:0]$11417 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11715 \dest24__data_i + assign $2\reg$next[3:0]$11418 \dest24__data_i case - assign $2\reg$next[3:0]$11715 $1\reg$next[3:0]$11714 + assign $2\reg$next[3:0]$11418 $1\reg$next[3:0]$11417 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11716 \w4__data_i + assign $3\reg$next[3:0]$11419 \w4__data_i case - assign $3\reg$next[3:0]$11716 $2\reg$next[3:0]$11715 + assign $3\reg$next[3:0]$11419 $2\reg$next[3:0]$11418 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11717 4'0000 + assign $4\reg$next[3:0]$11420 4'0000 case - assign $4\reg$next[3:0]$11717 $3\reg$next[3:0]$11716 + assign $4\reg$next[3:0]$11420 $3\reg$next[3:0]$11419 end sync always - update \reg$next $0\reg$next[3:0]$11713 + update \reg$next $0\reg$next[3:0]$11416 end - attribute \src "libresoc.v:185601.3-185640.6" - process $proc$libresoc.v:185601$11718 + attribute \src "libresoc.v:179796.3-179835.6" + process $proc$libresoc.v:179796$11421 assign { } { } assign { } { } assign { } { } - assign $0\src24__data_o$next[3:0]$11719 $6\src24__data_o$next[3:0]$11725 - attribute \src "libresoc.v:185602.5-185602.29" + assign $0\src24__data_o$next[3:0]$11422 $6\src24__data_o$next[3:0]$11428 + attribute \src "libresoc.v:179797.5-179797.29" switch \initial - attribute \src "libresoc.v:185602.9-185602.17" + attribute \src "libresoc.v:179797.9-179797.17" case 1'1 case end @@ -380731,66 +371276,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src24__data_o$next[3:0]$11720 $5\src24__data_o$next[3:0]$11724 + assign $1\src24__data_o$next[3:0]$11423 $5\src24__data_o$next[3:0]$11427 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src24__data_o$next[3:0]$11721 \dest14__data_i + assign $2\src24__data_o$next[3:0]$11424 \dest14__data_i case - assign $2\src24__data_o$next[3:0]$11721 4'0000 + assign $2\src24__data_o$next[3:0]$11424 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src24__data_o$next[3:0]$11722 \dest24__data_i + assign $3\src24__data_o$next[3:0]$11425 \dest24__data_i case - assign $3\src24__data_o$next[3:0]$11722 $2\src24__data_o$next[3:0]$11721 + assign $3\src24__data_o$next[3:0]$11425 $2\src24__data_o$next[3:0]$11424 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src24__data_o$next[3:0]$11723 \w4__data_i + assign $4\src24__data_o$next[3:0]$11426 \w4__data_i case - assign $4\src24__data_o$next[3:0]$11723 $3\src24__data_o$next[3:0]$11722 + assign $4\src24__data_o$next[3:0]$11426 $3\src24__data_o$next[3:0]$11425 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src24__data_o$next[3:0]$11724 \reg + assign $5\src24__data_o$next[3:0]$11427 \reg case - assign $5\src24__data_o$next[3:0]$11724 $4\src24__data_o$next[3:0]$11723 + assign $5\src24__data_o$next[3:0]$11427 $4\src24__data_o$next[3:0]$11426 end case - assign $1\src24__data_o$next[3:0]$11720 4'0000 + assign $1\src24__data_o$next[3:0]$11423 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src24__data_o$next[3:0]$11725 4'0000 + assign $6\src24__data_o$next[3:0]$11428 4'0000 case - assign $6\src24__data_o$next[3:0]$11725 $1\src24__data_o$next[3:0]$11720 + assign $6\src24__data_o$next[3:0]$11428 $1\src24__data_o$next[3:0]$11423 end sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$11719 + update \src24__data_o$next $0\src24__data_o$next[3:0]$11422 end - attribute \src "libresoc.v:185641.3-185670.6" - process $proc$libresoc.v:185641$11726 + attribute \src "libresoc.v:179836.3-179865.6" + process $proc$libresoc.v:179836$11429 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11727 $1\wr_detect$4[0:0]$11728 - attribute \src "libresoc.v:185642.5-185642.29" + assign $0\wr_detect$4[0:0]$11430 $1\wr_detect$4[0:0]$11431 + attribute \src "libresoc.v:179837.5-179837.29" switch \initial - attribute \src "libresoc.v:185642.9-185642.17" + attribute \src "libresoc.v:179837.9-179837.17" case 1'1 case end @@ -380802,49 +371347,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11728 $4\wr_detect$4[0:0]$11731 + assign $1\wr_detect$4[0:0]$11431 $4\wr_detect$4[0:0]$11434 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11729 1'1 + assign $2\wr_detect$4[0:0]$11432 1'1 case - assign $2\wr_detect$4[0:0]$11729 1'0 + assign $2\wr_detect$4[0:0]$11432 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11730 1'1 + assign $3\wr_detect$4[0:0]$11433 1'1 case - assign $3\wr_detect$4[0:0]$11730 $2\wr_detect$4[0:0]$11729 + assign $3\wr_detect$4[0:0]$11433 $2\wr_detect$4[0:0]$11432 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11731 1'1 + assign $4\wr_detect$4[0:0]$11434 1'1 case - assign $4\wr_detect$4[0:0]$11731 $3\wr_detect$4[0:0]$11730 + assign $4\wr_detect$4[0:0]$11434 $3\wr_detect$4[0:0]$11433 end case - assign $1\wr_detect$4[0:0]$11728 1'0 + assign $1\wr_detect$4[0:0]$11431 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11727 + update \wr_detect$4 $0\wr_detect$4[0:0]$11430 end - attribute \src "libresoc.v:185671.3-185710.6" - process $proc$libresoc.v:185671$11732 + attribute \src "libresoc.v:179866.3-179905.6" + process $proc$libresoc.v:179866$11435 assign { } { } assign { } { } assign { } { } - assign $0\src34__data_o$next[3:0]$11733 $6\src34__data_o$next[3:0]$11739 - attribute \src "libresoc.v:185672.5-185672.29" + assign $0\src34__data_o$next[3:0]$11436 $6\src34__data_o$next[3:0]$11442 + attribute \src "libresoc.v:179867.5-179867.29" switch \initial - attribute \src "libresoc.v:185672.9-185672.17" + attribute \src "libresoc.v:179867.9-179867.17" case 1'1 case end @@ -380856,66 +371401,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src34__data_o$next[3:0]$11734 $5\src34__data_o$next[3:0]$11738 + assign $1\src34__data_o$next[3:0]$11437 $5\src34__data_o$next[3:0]$11441 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src34__data_o$next[3:0]$11735 \dest14__data_i + assign $2\src34__data_o$next[3:0]$11438 \dest14__data_i case - assign $2\src34__data_o$next[3:0]$11735 4'0000 + assign $2\src34__data_o$next[3:0]$11438 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src34__data_o$next[3:0]$11736 \dest24__data_i + assign $3\src34__data_o$next[3:0]$11439 \dest24__data_i case - assign $3\src34__data_o$next[3:0]$11736 $2\src34__data_o$next[3:0]$11735 + assign $3\src34__data_o$next[3:0]$11439 $2\src34__data_o$next[3:0]$11438 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src34__data_o$next[3:0]$11737 \w4__data_i + assign $4\src34__data_o$next[3:0]$11440 \w4__data_i case - assign $4\src34__data_o$next[3:0]$11737 $3\src34__data_o$next[3:0]$11736 + assign $4\src34__data_o$next[3:0]$11440 $3\src34__data_o$next[3:0]$11439 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src34__data_o$next[3:0]$11738 \reg + assign $5\src34__data_o$next[3:0]$11441 \reg case - assign $5\src34__data_o$next[3:0]$11738 $4\src34__data_o$next[3:0]$11737 + assign $5\src34__data_o$next[3:0]$11441 $4\src34__data_o$next[3:0]$11440 end case - assign $1\src34__data_o$next[3:0]$11734 4'0000 + assign $1\src34__data_o$next[3:0]$11437 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src34__data_o$next[3:0]$11739 4'0000 + assign $6\src34__data_o$next[3:0]$11442 4'0000 case - assign $6\src34__data_o$next[3:0]$11739 $1\src34__data_o$next[3:0]$11734 + assign $6\src34__data_o$next[3:0]$11442 $1\src34__data_o$next[3:0]$11437 end sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$11733 + update \src34__data_o$next $0\src34__data_o$next[3:0]$11436 end - attribute \src "libresoc.v:185711.3-185740.6" - process $proc$libresoc.v:185711$11740 + attribute \src "libresoc.v:179906.3-179935.6" + process $proc$libresoc.v:179906$11443 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11741 $1\wr_detect$7[0:0]$11742 - attribute \src "libresoc.v:185712.5-185712.29" + assign $0\wr_detect$7[0:0]$11444 $1\wr_detect$7[0:0]$11445 + attribute \src "libresoc.v:179907.5-179907.29" switch \initial - attribute \src "libresoc.v:185712.9-185712.17" + attribute \src "libresoc.v:179907.9-179907.17" case 1'1 case end @@ -380927,49 +371472,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11742 $4\wr_detect$7[0:0]$11745 + assign $1\wr_detect$7[0:0]$11445 $4\wr_detect$7[0:0]$11448 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11743 1'1 + assign $2\wr_detect$7[0:0]$11446 1'1 case - assign $2\wr_detect$7[0:0]$11743 1'0 + assign $2\wr_detect$7[0:0]$11446 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11744 1'1 + assign $3\wr_detect$7[0:0]$11447 1'1 case - assign $3\wr_detect$7[0:0]$11744 $2\wr_detect$7[0:0]$11743 + assign $3\wr_detect$7[0:0]$11447 $2\wr_detect$7[0:0]$11446 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11745 1'1 + assign $4\wr_detect$7[0:0]$11448 1'1 case - assign $4\wr_detect$7[0:0]$11745 $3\wr_detect$7[0:0]$11744 + assign $4\wr_detect$7[0:0]$11448 $3\wr_detect$7[0:0]$11447 end case - assign $1\wr_detect$7[0:0]$11742 1'0 + assign $1\wr_detect$7[0:0]$11445 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11741 + update \wr_detect$7 $0\wr_detect$7[0:0]$11444 end - attribute \src "libresoc.v:185741.3-185780.6" - process $proc$libresoc.v:185741$11746 + attribute \src "libresoc.v:179936.3-179975.6" + process $proc$libresoc.v:179936$11449 assign { } { } assign { } { } assign { } { } - assign $0\r4__data_o$next[3:0]$11747 $6\r4__data_o$next[3:0]$11753 - attribute \src "libresoc.v:185742.5-185742.29" + assign $0\r4__data_o$next[3:0]$11450 $6\r4__data_o$next[3:0]$11456 + attribute \src "libresoc.v:179937.5-179937.29" switch \initial - attribute \src "libresoc.v:185742.9-185742.17" + attribute \src "libresoc.v:179937.9-179937.17" case 1'1 case end @@ -380981,66 +371526,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r4__data_o$next[3:0]$11748 $5\r4__data_o$next[3:0]$11752 + assign $1\r4__data_o$next[3:0]$11451 $5\r4__data_o$next[3:0]$11455 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r4__data_o$next[3:0]$11749 \dest14__data_i + assign $2\r4__data_o$next[3:0]$11452 \dest14__data_i case - assign $2\r4__data_o$next[3:0]$11749 4'0000 + assign $2\r4__data_o$next[3:0]$11452 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r4__data_o$next[3:0]$11750 \dest24__data_i + assign $3\r4__data_o$next[3:0]$11453 \dest24__data_i case - assign $3\r4__data_o$next[3:0]$11750 $2\r4__data_o$next[3:0]$11749 + assign $3\r4__data_o$next[3:0]$11453 $2\r4__data_o$next[3:0]$11452 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r4__data_o$next[3:0]$11751 \w4__data_i + assign $4\r4__data_o$next[3:0]$11454 \w4__data_i case - assign $4\r4__data_o$next[3:0]$11751 $3\r4__data_o$next[3:0]$11750 + assign $4\r4__data_o$next[3:0]$11454 $3\r4__data_o$next[3:0]$11453 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r4__data_o$next[3:0]$11752 \reg + assign $5\r4__data_o$next[3:0]$11455 \reg case - assign $5\r4__data_o$next[3:0]$11752 $4\r4__data_o$next[3:0]$11751 + assign $5\r4__data_o$next[3:0]$11455 $4\r4__data_o$next[3:0]$11454 end case - assign $1\r4__data_o$next[3:0]$11748 4'0000 + assign $1\r4__data_o$next[3:0]$11451 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r4__data_o$next[3:0]$11753 4'0000 + assign $6\r4__data_o$next[3:0]$11456 4'0000 case - assign $6\r4__data_o$next[3:0]$11753 $1\r4__data_o$next[3:0]$11748 + assign $6\r4__data_o$next[3:0]$11456 $1\r4__data_o$next[3:0]$11451 end sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$11747 + update \r4__data_o$next $0\r4__data_o$next[3:0]$11450 end - attribute \src "libresoc.v:185781.3-185810.6" - process $proc$libresoc.v:185781$11754 + attribute \src "libresoc.v:179976.3-180005.6" + process $proc$libresoc.v:179976$11457 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11755 $1\wr_detect$10[0:0]$11756 - attribute \src "libresoc.v:185782.5-185782.29" + assign $0\wr_detect$10[0:0]$11458 $1\wr_detect$10[0:0]$11459 + attribute \src "libresoc.v:179977.5-179977.29" switch \initial - attribute \src "libresoc.v:185782.9-185782.17" + attribute \src "libresoc.v:179977.9-179977.17" case 1'1 case end @@ -381052,49 +371597,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11756 $4\wr_detect$10[0:0]$11759 + assign $1\wr_detect$10[0:0]$11459 $4\wr_detect$10[0:0]$11462 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11757 1'1 + assign $2\wr_detect$10[0:0]$11460 1'1 case - assign $2\wr_detect$10[0:0]$11757 1'0 + assign $2\wr_detect$10[0:0]$11460 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11758 1'1 + assign $3\wr_detect$10[0:0]$11461 1'1 case - assign $3\wr_detect$10[0:0]$11758 $2\wr_detect$10[0:0]$11757 + assign $3\wr_detect$10[0:0]$11461 $2\wr_detect$10[0:0]$11460 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11759 1'1 + assign $4\wr_detect$10[0:0]$11462 1'1 case - assign $4\wr_detect$10[0:0]$11759 $3\wr_detect$10[0:0]$11758 + assign $4\wr_detect$10[0:0]$11462 $3\wr_detect$10[0:0]$11461 end case - assign $1\wr_detect$10[0:0]$11756 1'0 + assign $1\wr_detect$10[0:0]$11459 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11755 + update \wr_detect$10 $0\wr_detect$10[0:0]$11458 end - attribute \src "libresoc.v:185811.3-185850.6" - process $proc$libresoc.v:185811$11760 + attribute \src "libresoc.v:180006.3-180045.6" + process $proc$libresoc.v:180006$11463 assign { } { } assign { } { } assign { } { } - assign $0\r24__data_o$next[3:0]$11761 $6\r24__data_o$next[3:0]$11767 - attribute \src "libresoc.v:185812.5-185812.29" + assign $0\r24__data_o$next[3:0]$11464 $6\r24__data_o$next[3:0]$11470 + attribute \src "libresoc.v:180007.5-180007.29" switch \initial - attribute \src "libresoc.v:185812.9-185812.17" + attribute \src "libresoc.v:180007.9-180007.17" case 1'1 case end @@ -381106,66 +371651,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r24__data_o$next[3:0]$11762 $5\r24__data_o$next[3:0]$11766 + assign $1\r24__data_o$next[3:0]$11465 $5\r24__data_o$next[3:0]$11469 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r24__data_o$next[3:0]$11763 \dest14__data_i + assign $2\r24__data_o$next[3:0]$11466 \dest14__data_i case - assign $2\r24__data_o$next[3:0]$11763 4'0000 + assign $2\r24__data_o$next[3:0]$11466 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r24__data_o$next[3:0]$11764 \dest24__data_i + assign $3\r24__data_o$next[3:0]$11467 \dest24__data_i case - assign $3\r24__data_o$next[3:0]$11764 $2\r24__data_o$next[3:0]$11763 + assign $3\r24__data_o$next[3:0]$11467 $2\r24__data_o$next[3:0]$11466 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r24__data_o$next[3:0]$11765 \w4__data_i + assign $4\r24__data_o$next[3:0]$11468 \w4__data_i case - assign $4\r24__data_o$next[3:0]$11765 $3\r24__data_o$next[3:0]$11764 + assign $4\r24__data_o$next[3:0]$11468 $3\r24__data_o$next[3:0]$11467 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r24__data_o$next[3:0]$11766 \reg + assign $5\r24__data_o$next[3:0]$11469 \reg case - assign $5\r24__data_o$next[3:0]$11766 $4\r24__data_o$next[3:0]$11765 + assign $5\r24__data_o$next[3:0]$11469 $4\r24__data_o$next[3:0]$11468 end case - assign $1\r24__data_o$next[3:0]$11762 4'0000 + assign $1\r24__data_o$next[3:0]$11465 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r24__data_o$next[3:0]$11767 4'0000 + assign $6\r24__data_o$next[3:0]$11470 4'0000 case - assign $6\r24__data_o$next[3:0]$11767 $1\r24__data_o$next[3:0]$11762 + assign $6\r24__data_o$next[3:0]$11470 $1\r24__data_o$next[3:0]$11465 end sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$11761 + update \r24__data_o$next $0\r24__data_o$next[3:0]$11464 end - attribute \src "libresoc.v:185851.3-185880.6" - process $proc$libresoc.v:185851$11768 + attribute \src "libresoc.v:180046.3-180075.6" + process $proc$libresoc.v:180046$11471 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11769 $1\wr_detect$13[0:0]$11770 - attribute \src "libresoc.v:185852.5-185852.29" + assign $0\wr_detect$13[0:0]$11472 $1\wr_detect$13[0:0]$11473 + attribute \src "libresoc.v:180047.5-180047.29" switch \initial - attribute \src "libresoc.v:185852.9-185852.17" + attribute \src "libresoc.v:180047.9-180047.17" case 1'1 case end @@ -381177,217 +371722,217 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11770 $4\wr_detect$13[0:0]$11773 + assign $1\wr_detect$13[0:0]$11473 $4\wr_detect$13[0:0]$11476 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11771 1'1 + assign $2\wr_detect$13[0:0]$11474 1'1 case - assign $2\wr_detect$13[0:0]$11771 1'0 + assign $2\wr_detect$13[0:0]$11474 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11772 1'1 + assign $3\wr_detect$13[0:0]$11475 1'1 case - assign $3\wr_detect$13[0:0]$11772 $2\wr_detect$13[0:0]$11771 + assign $3\wr_detect$13[0:0]$11475 $2\wr_detect$13[0:0]$11474 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11773 1'1 + assign $4\wr_detect$13[0:0]$11476 1'1 case - assign $4\wr_detect$13[0:0]$11773 $3\wr_detect$13[0:0]$11772 + assign $4\wr_detect$13[0:0]$11476 $3\wr_detect$13[0:0]$11475 end case - assign $1\wr_detect$13[0:0]$11770 1'0 + assign $1\wr_detect$13[0:0]$11473 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11769 + update \wr_detect$13 $0\wr_detect$13[0:0]$11472 end - connect \$9 $not$libresoc.v:185487$11692_Y - connect \$12 $not$libresoc.v:185488$11693_Y - connect \$1 $not$libresoc.v:185489$11694_Y - connect \$3 $not$libresoc.v:185490$11695_Y - connect \$6 $not$libresoc.v:185491$11696_Y + connect \$9 $not$libresoc.v:179682$11395_Y + connect \$12 $not$libresoc.v:179683$11396_Y + connect \$1 $not$libresoc.v:179684$11397_Y + connect \$3 $not$libresoc.v:179685$11398_Y + connect \$6 $not$libresoc.v:179686$11399_Y end -attribute \src "libresoc.v:185885.1-186356.10" +attribute \src "libresoc.v:180080.1-180551.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 - attribute \src "libresoc.v:185886.7-185886.20" + attribute \src "libresoc.v:180081.7-180081.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186286.3-186325.6" - wire width 4 $0\r25__data_o$next[3:0]$11850 - attribute \src "libresoc.v:185969.3-185970.39" + attribute \src "libresoc.v:180481.3-180520.6" + wire width 4 $0\r25__data_o$next[3:0]$11553 + attribute \src "libresoc.v:180164.3-180165.39" wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:186216.3-186255.6" - wire width 4 $0\r5__data_o$next[3:0]$11836 - attribute \src "libresoc.v:185971.3-185972.37" + attribute \src "libresoc.v:180411.3-180450.6" + wire width 4 $0\r5__data_o$next[3:0]$11539 + attribute \src "libresoc.v:180166.3-180167.37" wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:186049.3-186075.6" - wire width 4 $0\reg$next[3:0]$11802 - attribute \src "libresoc.v:185967.3-185968.25" + attribute \src "libresoc.v:180244.3-180270.6" + wire width 4 $0\reg$next[3:0]$11505 + attribute \src "libresoc.v:180162.3-180163.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:185979.3-186018.6" - wire width 4 $0\src15__data_o$next[3:0]$11793 - attribute \src "libresoc.v:185977.3-185978.43" + attribute \src "libresoc.v:180174.3-180213.6" + wire width 4 $0\src15__data_o$next[3:0]$11496 + attribute \src "libresoc.v:180172.3-180173.43" wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:186076.3-186115.6" - wire width 4 $0\src25__data_o$next[3:0]$11808 - attribute \src "libresoc.v:185975.3-185976.43" + attribute \src "libresoc.v:180271.3-180310.6" + wire width 4 $0\src25__data_o$next[3:0]$11511 + attribute \src "libresoc.v:180170.3-180171.43" wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:186146.3-186185.6" - wire width 4 $0\src35__data_o$next[3:0]$11822 - attribute \src "libresoc.v:185973.3-185974.43" + attribute \src "libresoc.v:180341.3-180380.6" + wire width 4 $0\src35__data_o$next[3:0]$11525 + attribute \src "libresoc.v:180168.3-180169.43" wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:186256.3-186285.6" - wire $0\wr_detect$10[0:0]$11844 - attribute \src "libresoc.v:186326.3-186355.6" - wire $0\wr_detect$13[0:0]$11858 - attribute \src "libresoc.v:186116.3-186145.6" - wire $0\wr_detect$4[0:0]$11816 - attribute \src "libresoc.v:186186.3-186215.6" - wire $0\wr_detect$7[0:0]$11830 - attribute \src "libresoc.v:186019.3-186048.6" + attribute \src "libresoc.v:180451.3-180480.6" + wire $0\wr_detect$10[0:0]$11547 + attribute \src "libresoc.v:180521.3-180550.6" + wire $0\wr_detect$13[0:0]$11561 + attribute \src "libresoc.v:180311.3-180340.6" + wire $0\wr_detect$4[0:0]$11519 + attribute \src "libresoc.v:180381.3-180410.6" + wire $0\wr_detect$7[0:0]$11533 + attribute \src "libresoc.v:180214.3-180243.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:186286.3-186325.6" - wire width 4 $1\r25__data_o$next[3:0]$11851 - attribute \src "libresoc.v:185911.13-185911.31" + attribute \src "libresoc.v:180481.3-180520.6" + wire width 4 $1\r25__data_o$next[3:0]$11554 + attribute \src "libresoc.v:180106.13-180106.31" wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:186216.3-186255.6" - wire width 4 $1\r5__data_o$next[3:0]$11837 - attribute \src "libresoc.v:185918.13-185918.30" + attribute \src "libresoc.v:180411.3-180450.6" + wire width 4 $1\r5__data_o$next[3:0]$11540 + attribute \src "libresoc.v:180113.13-180113.30" wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:186049.3-186075.6" - wire width 4 $1\reg$next[3:0]$11803 - attribute \src "libresoc.v:185924.13-185924.25" + attribute \src "libresoc.v:180244.3-180270.6" + wire width 4 $1\reg$next[3:0]$11506 + attribute \src "libresoc.v:180119.13-180119.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:185979.3-186018.6" - wire width 4 $1\src15__data_o$next[3:0]$11794 - attribute \src "libresoc.v:185929.13-185929.33" + attribute \src "libresoc.v:180174.3-180213.6" + wire width 4 $1\src15__data_o$next[3:0]$11497 + attribute \src "libresoc.v:180124.13-180124.33" wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:186076.3-186115.6" - wire width 4 $1\src25__data_o$next[3:0]$11809 - attribute \src "libresoc.v:185936.13-185936.33" + attribute \src "libresoc.v:180271.3-180310.6" + wire width 4 $1\src25__data_o$next[3:0]$11512 + attribute \src "libresoc.v:180131.13-180131.33" wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:186146.3-186185.6" - wire width 4 $1\src35__data_o$next[3:0]$11823 - attribute \src "libresoc.v:185943.13-185943.33" + attribute \src "libresoc.v:180341.3-180380.6" + wire width 4 $1\src35__data_o$next[3:0]$11526 + attribute \src "libresoc.v:180138.13-180138.33" wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:186256.3-186285.6" - wire $1\wr_detect$10[0:0]$11845 - attribute \src "libresoc.v:186326.3-186355.6" - wire $1\wr_detect$13[0:0]$11859 - attribute \src "libresoc.v:186116.3-186145.6" - wire $1\wr_detect$4[0:0]$11817 - attribute \src "libresoc.v:186186.3-186215.6" - wire $1\wr_detect$7[0:0]$11831 - attribute \src "libresoc.v:186019.3-186048.6" + attribute \src "libresoc.v:180451.3-180480.6" + wire $1\wr_detect$10[0:0]$11548 + attribute \src "libresoc.v:180521.3-180550.6" + wire $1\wr_detect$13[0:0]$11562 + attribute \src "libresoc.v:180311.3-180340.6" + wire $1\wr_detect$4[0:0]$11520 + attribute \src "libresoc.v:180381.3-180410.6" + wire $1\wr_detect$7[0:0]$11534 + attribute \src "libresoc.v:180214.3-180243.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:186286.3-186325.6" - wire width 4 $2\r25__data_o$next[3:0]$11852 - attribute \src "libresoc.v:186216.3-186255.6" - wire width 4 $2\r5__data_o$next[3:0]$11838 - attribute \src "libresoc.v:186049.3-186075.6" - wire width 4 $2\reg$next[3:0]$11804 - attribute \src "libresoc.v:185979.3-186018.6" - wire width 4 $2\src15__data_o$next[3:0]$11795 - attribute \src "libresoc.v:186076.3-186115.6" - wire width 4 $2\src25__data_o$next[3:0]$11810 - attribute \src "libresoc.v:186146.3-186185.6" - wire width 4 $2\src35__data_o$next[3:0]$11824 - attribute \src "libresoc.v:186256.3-186285.6" - wire $2\wr_detect$10[0:0]$11846 - attribute \src "libresoc.v:186326.3-186355.6" - wire $2\wr_detect$13[0:0]$11860 - attribute \src "libresoc.v:186116.3-186145.6" - wire $2\wr_detect$4[0:0]$11818 - attribute \src "libresoc.v:186186.3-186215.6" - wire $2\wr_detect$7[0:0]$11832 - attribute \src "libresoc.v:186019.3-186048.6" + attribute \src "libresoc.v:180481.3-180520.6" + wire width 4 $2\r25__data_o$next[3:0]$11555 + attribute \src "libresoc.v:180411.3-180450.6" + wire width 4 $2\r5__data_o$next[3:0]$11541 + attribute \src "libresoc.v:180244.3-180270.6" + wire width 4 $2\reg$next[3:0]$11507 + attribute \src "libresoc.v:180174.3-180213.6" + wire width 4 $2\src15__data_o$next[3:0]$11498 + attribute \src "libresoc.v:180271.3-180310.6" + wire width 4 $2\src25__data_o$next[3:0]$11513 + attribute \src "libresoc.v:180341.3-180380.6" + wire width 4 $2\src35__data_o$next[3:0]$11527 + attribute \src "libresoc.v:180451.3-180480.6" + wire $2\wr_detect$10[0:0]$11549 + attribute \src "libresoc.v:180521.3-180550.6" + wire $2\wr_detect$13[0:0]$11563 + attribute \src "libresoc.v:180311.3-180340.6" + wire $2\wr_detect$4[0:0]$11521 + attribute \src "libresoc.v:180381.3-180410.6" + wire $2\wr_detect$7[0:0]$11535 + attribute \src "libresoc.v:180214.3-180243.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:186286.3-186325.6" - wire width 4 $3\r25__data_o$next[3:0]$11853 - attribute \src "libresoc.v:186216.3-186255.6" - wire width 4 $3\r5__data_o$next[3:0]$11839 - attribute \src "libresoc.v:186049.3-186075.6" - wire width 4 $3\reg$next[3:0]$11805 - attribute \src "libresoc.v:185979.3-186018.6" - wire width 4 $3\src15__data_o$next[3:0]$11796 - attribute \src "libresoc.v:186076.3-186115.6" - wire width 4 $3\src25__data_o$next[3:0]$11811 - attribute \src "libresoc.v:186146.3-186185.6" - wire width 4 $3\src35__data_o$next[3:0]$11825 - attribute \src "libresoc.v:186256.3-186285.6" - wire $3\wr_detect$10[0:0]$11847 - attribute \src "libresoc.v:186326.3-186355.6" - wire $3\wr_detect$13[0:0]$11861 - attribute \src "libresoc.v:186116.3-186145.6" - wire $3\wr_detect$4[0:0]$11819 - attribute \src "libresoc.v:186186.3-186215.6" - wire $3\wr_detect$7[0:0]$11833 - attribute \src "libresoc.v:186019.3-186048.6" + attribute \src "libresoc.v:180481.3-180520.6" + wire width 4 $3\r25__data_o$next[3:0]$11556 + attribute \src "libresoc.v:180411.3-180450.6" + wire width 4 $3\r5__data_o$next[3:0]$11542 + attribute \src "libresoc.v:180244.3-180270.6" + wire width 4 $3\reg$next[3:0]$11508 + attribute \src "libresoc.v:180174.3-180213.6" + wire width 4 $3\src15__data_o$next[3:0]$11499 + attribute \src "libresoc.v:180271.3-180310.6" + wire width 4 $3\src25__data_o$next[3:0]$11514 + attribute \src "libresoc.v:180341.3-180380.6" + wire width 4 $3\src35__data_o$next[3:0]$11528 + attribute \src "libresoc.v:180451.3-180480.6" + wire $3\wr_detect$10[0:0]$11550 + attribute \src "libresoc.v:180521.3-180550.6" + wire $3\wr_detect$13[0:0]$11564 + attribute \src "libresoc.v:180311.3-180340.6" + wire $3\wr_detect$4[0:0]$11522 + attribute \src "libresoc.v:180381.3-180410.6" + wire $3\wr_detect$7[0:0]$11536 + attribute \src "libresoc.v:180214.3-180243.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:186286.3-186325.6" - wire width 4 $4\r25__data_o$next[3:0]$11854 - attribute \src "libresoc.v:186216.3-186255.6" - wire width 4 $4\r5__data_o$next[3:0]$11840 - attribute \src "libresoc.v:186049.3-186075.6" - wire width 4 $4\reg$next[3:0]$11806 - attribute \src "libresoc.v:185979.3-186018.6" - wire width 4 $4\src15__data_o$next[3:0]$11797 - attribute \src "libresoc.v:186076.3-186115.6" - wire width 4 $4\src25__data_o$next[3:0]$11812 - attribute \src "libresoc.v:186146.3-186185.6" - wire width 4 $4\src35__data_o$next[3:0]$11826 - attribute \src "libresoc.v:186256.3-186285.6" - wire $4\wr_detect$10[0:0]$11848 - attribute \src "libresoc.v:186326.3-186355.6" - wire $4\wr_detect$13[0:0]$11862 - attribute \src "libresoc.v:186116.3-186145.6" - wire $4\wr_detect$4[0:0]$11820 - attribute \src "libresoc.v:186186.3-186215.6" - wire $4\wr_detect$7[0:0]$11834 - attribute \src "libresoc.v:186019.3-186048.6" + attribute \src "libresoc.v:180481.3-180520.6" + wire width 4 $4\r25__data_o$next[3:0]$11557 + attribute \src "libresoc.v:180411.3-180450.6" + wire width 4 $4\r5__data_o$next[3:0]$11543 + attribute \src "libresoc.v:180244.3-180270.6" + wire width 4 $4\reg$next[3:0]$11509 + attribute \src "libresoc.v:180174.3-180213.6" + wire width 4 $4\src15__data_o$next[3:0]$11500 + attribute \src "libresoc.v:180271.3-180310.6" + wire width 4 $4\src25__data_o$next[3:0]$11515 + attribute \src "libresoc.v:180341.3-180380.6" + wire width 4 $4\src35__data_o$next[3:0]$11529 + attribute \src "libresoc.v:180451.3-180480.6" + wire $4\wr_detect$10[0:0]$11551 + attribute \src "libresoc.v:180521.3-180550.6" + wire $4\wr_detect$13[0:0]$11565 + attribute \src "libresoc.v:180311.3-180340.6" + wire $4\wr_detect$4[0:0]$11523 + attribute \src "libresoc.v:180381.3-180410.6" + wire $4\wr_detect$7[0:0]$11537 + attribute \src "libresoc.v:180214.3-180243.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:186286.3-186325.6" - wire width 4 $5\r25__data_o$next[3:0]$11855 - attribute \src "libresoc.v:186216.3-186255.6" - wire width 4 $5\r5__data_o$next[3:0]$11841 - attribute \src "libresoc.v:185979.3-186018.6" - wire width 4 $5\src15__data_o$next[3:0]$11798 - attribute \src "libresoc.v:186076.3-186115.6" - wire width 4 $5\src25__data_o$next[3:0]$11813 - attribute \src "libresoc.v:186146.3-186185.6" - wire width 4 $5\src35__data_o$next[3:0]$11827 - attribute \src "libresoc.v:186286.3-186325.6" - wire width 4 $6\r25__data_o$next[3:0]$11856 - attribute \src "libresoc.v:186216.3-186255.6" - wire width 4 $6\r5__data_o$next[3:0]$11842 - attribute \src "libresoc.v:185979.3-186018.6" - wire width 4 $6\src15__data_o$next[3:0]$11799 - attribute \src "libresoc.v:186076.3-186115.6" - wire width 4 $6\src25__data_o$next[3:0]$11814 - attribute \src "libresoc.v:186146.3-186185.6" - wire width 4 $6\src35__data_o$next[3:0]$11828 - attribute \src "libresoc.v:185962.17-185962.104" - wire $not$libresoc.v:185962$11781_Y - attribute \src "libresoc.v:185963.18-185963.105" - wire $not$libresoc.v:185963$11782_Y - attribute \src "libresoc.v:185964.17-185964.100" - wire $not$libresoc.v:185964$11783_Y - attribute \src "libresoc.v:185965.17-185965.103" - wire $not$libresoc.v:185965$11784_Y - attribute \src "libresoc.v:185966.17-185966.103" - wire $not$libresoc.v:185966$11785_Y + attribute \src "libresoc.v:180481.3-180520.6" + wire width 4 $5\r25__data_o$next[3:0]$11558 + attribute \src "libresoc.v:180411.3-180450.6" + wire width 4 $5\r5__data_o$next[3:0]$11544 + attribute \src "libresoc.v:180174.3-180213.6" + wire width 4 $5\src15__data_o$next[3:0]$11501 + attribute \src "libresoc.v:180271.3-180310.6" + wire width 4 $5\src25__data_o$next[3:0]$11516 + attribute \src "libresoc.v:180341.3-180380.6" + wire width 4 $5\src35__data_o$next[3:0]$11530 + attribute \src "libresoc.v:180481.3-180520.6" + wire width 4 $6\r25__data_o$next[3:0]$11559 + attribute \src "libresoc.v:180411.3-180450.6" + wire width 4 $6\r5__data_o$next[3:0]$11545 + attribute \src "libresoc.v:180174.3-180213.6" + wire width 4 $6\src15__data_o$next[3:0]$11502 + attribute \src "libresoc.v:180271.3-180310.6" + wire width 4 $6\src25__data_o$next[3:0]$11517 + attribute \src "libresoc.v:180341.3-180380.6" + wire width 4 $6\src35__data_o$next[3:0]$11531 + attribute \src "libresoc.v:180157.17-180157.104" + wire $not$libresoc.v:180157$11484_Y + attribute \src "libresoc.v:180158.18-180158.105" + wire $not$libresoc.v:180158$11485_Y + attribute \src "libresoc.v:180159.17-180159.100" + wire $not$libresoc.v:180159$11486_Y + attribute \src "libresoc.v:180160.17-180160.103" + wire $not$libresoc.v:180160$11487_Y + attribute \src "libresoc.v:180161.17-180161.103" + wire $not$libresoc.v:180161$11488_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -381398,9 +371943,9 @@ module \reg_5 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest15__data_i @@ -381410,7 +371955,7 @@ module \reg_5 wire width 4 input 11 \dest25__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest25__wen - attribute \src "libresoc.v:185886.7-185886.15" + attribute \src "libresoc.v:180081.7-180081.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r25__data_o @@ -381461,152 +372006,152 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185962$11781 + cell $not $not$libresoc.v:180157$11484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:185962$11781_Y + connect \Y $not$libresoc.v:180157$11484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185963$11782 + cell $not $not$libresoc.v:180158$11485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:185963$11782_Y + connect \Y $not$libresoc.v:180158$11485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185964$11783 + cell $not $not$libresoc.v:180159$11486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:185964$11783_Y + connect \Y $not$libresoc.v:180159$11486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185965$11784 + cell $not $not$libresoc.v:180160$11487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:185965$11784_Y + connect \Y $not$libresoc.v:180160$11487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:185966$11785 + cell $not $not$libresoc.v:180161$11488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:185966$11785_Y + connect \Y $not$libresoc.v:180161$11488_Y end - attribute \src "libresoc.v:185886.7-185886.20" - process $proc$libresoc.v:185886$11863 + attribute \src "libresoc.v:180081.7-180081.20" + process $proc$libresoc.v:180081$11566 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185911.13-185911.31" - process $proc$libresoc.v:185911$11864 + attribute \src "libresoc.v:180106.13-180106.31" + process $proc$libresoc.v:180106$11567 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end - attribute \src "libresoc.v:185918.13-185918.30" - process $proc$libresoc.v:185918$11865 + attribute \src "libresoc.v:180113.13-180113.30" + process $proc$libresoc.v:180113$11568 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end - attribute \src "libresoc.v:185924.13-185924.25" - process $proc$libresoc.v:185924$11866 + attribute \src "libresoc.v:180119.13-180119.25" + process $proc$libresoc.v:180119$11569 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:185929.13-185929.33" - process $proc$libresoc.v:185929$11867 + attribute \src "libresoc.v:180124.13-180124.33" + process $proc$libresoc.v:180124$11570 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end - attribute \src "libresoc.v:185936.13-185936.33" - process $proc$libresoc.v:185936$11868 + attribute \src "libresoc.v:180131.13-180131.33" + process $proc$libresoc.v:180131$11571 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end - attribute \src "libresoc.v:185943.13-185943.33" - process $proc$libresoc.v:185943$11869 + attribute \src "libresoc.v:180138.13-180138.33" + process $proc$libresoc.v:180138$11572 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end - attribute \src "libresoc.v:185967.3-185968.25" - process $proc$libresoc.v:185967$11786 + attribute \src "libresoc.v:180162.3-180163.25" + process $proc$libresoc.v:180162$11489 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:185969.3-185970.39" - process $proc$libresoc.v:185969$11787 + attribute \src "libresoc.v:180164.3-180165.39" + process $proc$libresoc.v:180164$11490 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end - attribute \src "libresoc.v:185971.3-185972.37" - process $proc$libresoc.v:185971$11788 + attribute \src "libresoc.v:180166.3-180167.37" + process $proc$libresoc.v:180166$11491 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end - attribute \src "libresoc.v:185973.3-185974.43" - process $proc$libresoc.v:185973$11789 + attribute \src "libresoc.v:180168.3-180169.43" + process $proc$libresoc.v:180168$11492 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end - attribute \src "libresoc.v:185975.3-185976.43" - process $proc$libresoc.v:185975$11790 + attribute \src "libresoc.v:180170.3-180171.43" + process $proc$libresoc.v:180170$11493 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end - attribute \src "libresoc.v:185977.3-185978.43" - process $proc$libresoc.v:185977$11791 + attribute \src "libresoc.v:180172.3-180173.43" + process $proc$libresoc.v:180172$11494 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end - attribute \src "libresoc.v:185979.3-186018.6" - process $proc$libresoc.v:185979$11792 + attribute \src "libresoc.v:180174.3-180213.6" + process $proc$libresoc.v:180174$11495 assign { } { } assign { } { } assign { } { } - assign $0\src15__data_o$next[3:0]$11793 $6\src15__data_o$next[3:0]$11799 - attribute \src "libresoc.v:185980.5-185980.29" + assign $0\src15__data_o$next[3:0]$11496 $6\src15__data_o$next[3:0]$11502 + attribute \src "libresoc.v:180175.5-180175.29" switch \initial - attribute \src "libresoc.v:185980.9-185980.17" + attribute \src "libresoc.v:180175.9-180175.17" case 1'1 case end @@ -381618,66 +372163,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src15__data_o$next[3:0]$11794 $5\src15__data_o$next[3:0]$11798 + assign $1\src15__data_o$next[3:0]$11497 $5\src15__data_o$next[3:0]$11501 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src15__data_o$next[3:0]$11795 \dest15__data_i + assign $2\src15__data_o$next[3:0]$11498 \dest15__data_i case - assign $2\src15__data_o$next[3:0]$11795 4'0000 + assign $2\src15__data_o$next[3:0]$11498 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src15__data_o$next[3:0]$11796 \dest25__data_i + assign $3\src15__data_o$next[3:0]$11499 \dest25__data_i case - assign $3\src15__data_o$next[3:0]$11796 $2\src15__data_o$next[3:0]$11795 + assign $3\src15__data_o$next[3:0]$11499 $2\src15__data_o$next[3:0]$11498 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src15__data_o$next[3:0]$11797 \w5__data_i + assign $4\src15__data_o$next[3:0]$11500 \w5__data_i case - assign $4\src15__data_o$next[3:0]$11797 $3\src15__data_o$next[3:0]$11796 + assign $4\src15__data_o$next[3:0]$11500 $3\src15__data_o$next[3:0]$11499 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src15__data_o$next[3:0]$11798 \reg + assign $5\src15__data_o$next[3:0]$11501 \reg case - assign $5\src15__data_o$next[3:0]$11798 $4\src15__data_o$next[3:0]$11797 + assign $5\src15__data_o$next[3:0]$11501 $4\src15__data_o$next[3:0]$11500 end case - assign $1\src15__data_o$next[3:0]$11794 4'0000 + assign $1\src15__data_o$next[3:0]$11497 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src15__data_o$next[3:0]$11799 4'0000 + assign $6\src15__data_o$next[3:0]$11502 4'0000 case - assign $6\src15__data_o$next[3:0]$11799 $1\src15__data_o$next[3:0]$11794 + assign $6\src15__data_o$next[3:0]$11502 $1\src15__data_o$next[3:0]$11497 end sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$11793 + update \src15__data_o$next $0\src15__data_o$next[3:0]$11496 end - attribute \src "libresoc.v:186019.3-186048.6" - process $proc$libresoc.v:186019$11800 + attribute \src "libresoc.v:180214.3-180243.6" + process $proc$libresoc.v:180214$11503 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:186020.5-186020.29" + attribute \src "libresoc.v:180215.5-180215.29" switch \initial - attribute \src "libresoc.v:186020.9-186020.17" + attribute \src "libresoc.v:180215.9-180215.17" case 1'1 case end @@ -381723,17 +372268,17 @@ module \reg_5 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:186049.3-186075.6" - process $proc$libresoc.v:186049$11801 + attribute \src "libresoc.v:180244.3-180270.6" + process $proc$libresoc.v:180244$11504 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11802 $4\reg$next[3:0]$11806 - attribute \src "libresoc.v:186050.5-186050.29" + assign $0\reg$next[3:0]$11505 $4\reg$next[3:0]$11509 + attribute \src "libresoc.v:180245.5-180245.29" switch \initial - attribute \src "libresoc.v:186050.9-186050.17" + attribute \src "libresoc.v:180245.9-180245.17" case 1'1 case end @@ -381742,49 +372287,49 @@ module \reg_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11803 \dest15__data_i + assign $1\reg$next[3:0]$11506 \dest15__data_i case - assign $1\reg$next[3:0]$11803 \reg + assign $1\reg$next[3:0]$11506 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11804 \dest25__data_i + assign $2\reg$next[3:0]$11507 \dest25__data_i case - assign $2\reg$next[3:0]$11804 $1\reg$next[3:0]$11803 + assign $2\reg$next[3:0]$11507 $1\reg$next[3:0]$11506 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11805 \w5__data_i + assign $3\reg$next[3:0]$11508 \w5__data_i case - assign $3\reg$next[3:0]$11805 $2\reg$next[3:0]$11804 + assign $3\reg$next[3:0]$11508 $2\reg$next[3:0]$11507 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11806 4'0000 + assign $4\reg$next[3:0]$11509 4'0000 case - assign $4\reg$next[3:0]$11806 $3\reg$next[3:0]$11805 + assign $4\reg$next[3:0]$11509 $3\reg$next[3:0]$11508 end sync always - update \reg$next $0\reg$next[3:0]$11802 + update \reg$next $0\reg$next[3:0]$11505 end - attribute \src "libresoc.v:186076.3-186115.6" - process $proc$libresoc.v:186076$11807 + attribute \src "libresoc.v:180271.3-180310.6" + process $proc$libresoc.v:180271$11510 assign { } { } assign { } { } assign { } { } - assign $0\src25__data_o$next[3:0]$11808 $6\src25__data_o$next[3:0]$11814 - attribute \src "libresoc.v:186077.5-186077.29" + assign $0\src25__data_o$next[3:0]$11511 $6\src25__data_o$next[3:0]$11517 + attribute \src "libresoc.v:180272.5-180272.29" switch \initial - attribute \src "libresoc.v:186077.9-186077.17" + attribute \src "libresoc.v:180272.9-180272.17" case 1'1 case end @@ -381796,66 +372341,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src25__data_o$next[3:0]$11809 $5\src25__data_o$next[3:0]$11813 + assign $1\src25__data_o$next[3:0]$11512 $5\src25__data_o$next[3:0]$11516 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src25__data_o$next[3:0]$11810 \dest15__data_i + assign $2\src25__data_o$next[3:0]$11513 \dest15__data_i case - assign $2\src25__data_o$next[3:0]$11810 4'0000 + assign $2\src25__data_o$next[3:0]$11513 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src25__data_o$next[3:0]$11811 \dest25__data_i + assign $3\src25__data_o$next[3:0]$11514 \dest25__data_i case - assign $3\src25__data_o$next[3:0]$11811 $2\src25__data_o$next[3:0]$11810 + assign $3\src25__data_o$next[3:0]$11514 $2\src25__data_o$next[3:0]$11513 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src25__data_o$next[3:0]$11812 \w5__data_i + assign $4\src25__data_o$next[3:0]$11515 \w5__data_i case - assign $4\src25__data_o$next[3:0]$11812 $3\src25__data_o$next[3:0]$11811 + assign $4\src25__data_o$next[3:0]$11515 $3\src25__data_o$next[3:0]$11514 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src25__data_o$next[3:0]$11813 \reg + assign $5\src25__data_o$next[3:0]$11516 \reg case - assign $5\src25__data_o$next[3:0]$11813 $4\src25__data_o$next[3:0]$11812 + assign $5\src25__data_o$next[3:0]$11516 $4\src25__data_o$next[3:0]$11515 end case - assign $1\src25__data_o$next[3:0]$11809 4'0000 + assign $1\src25__data_o$next[3:0]$11512 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src25__data_o$next[3:0]$11814 4'0000 + assign $6\src25__data_o$next[3:0]$11517 4'0000 case - assign $6\src25__data_o$next[3:0]$11814 $1\src25__data_o$next[3:0]$11809 + assign $6\src25__data_o$next[3:0]$11517 $1\src25__data_o$next[3:0]$11512 end sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$11808 + update \src25__data_o$next $0\src25__data_o$next[3:0]$11511 end - attribute \src "libresoc.v:186116.3-186145.6" - process $proc$libresoc.v:186116$11815 + attribute \src "libresoc.v:180311.3-180340.6" + process $proc$libresoc.v:180311$11518 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11816 $1\wr_detect$4[0:0]$11817 - attribute \src "libresoc.v:186117.5-186117.29" + assign $0\wr_detect$4[0:0]$11519 $1\wr_detect$4[0:0]$11520 + attribute \src "libresoc.v:180312.5-180312.29" switch \initial - attribute \src "libresoc.v:186117.9-186117.17" + attribute \src "libresoc.v:180312.9-180312.17" case 1'1 case end @@ -381867,49 +372412,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11817 $4\wr_detect$4[0:0]$11820 + assign $1\wr_detect$4[0:0]$11520 $4\wr_detect$4[0:0]$11523 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11818 1'1 + assign $2\wr_detect$4[0:0]$11521 1'1 case - assign $2\wr_detect$4[0:0]$11818 1'0 + assign $2\wr_detect$4[0:0]$11521 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11819 1'1 + assign $3\wr_detect$4[0:0]$11522 1'1 case - assign $3\wr_detect$4[0:0]$11819 $2\wr_detect$4[0:0]$11818 + assign $3\wr_detect$4[0:0]$11522 $2\wr_detect$4[0:0]$11521 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11820 1'1 + assign $4\wr_detect$4[0:0]$11523 1'1 case - assign $4\wr_detect$4[0:0]$11820 $3\wr_detect$4[0:0]$11819 + assign $4\wr_detect$4[0:0]$11523 $3\wr_detect$4[0:0]$11522 end case - assign $1\wr_detect$4[0:0]$11817 1'0 + assign $1\wr_detect$4[0:0]$11520 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11816 + update \wr_detect$4 $0\wr_detect$4[0:0]$11519 end - attribute \src "libresoc.v:186146.3-186185.6" - process $proc$libresoc.v:186146$11821 + attribute \src "libresoc.v:180341.3-180380.6" + process $proc$libresoc.v:180341$11524 assign { } { } assign { } { } assign { } { } - assign $0\src35__data_o$next[3:0]$11822 $6\src35__data_o$next[3:0]$11828 - attribute \src "libresoc.v:186147.5-186147.29" + assign $0\src35__data_o$next[3:0]$11525 $6\src35__data_o$next[3:0]$11531 + attribute \src "libresoc.v:180342.5-180342.29" switch \initial - attribute \src "libresoc.v:186147.9-186147.17" + attribute \src "libresoc.v:180342.9-180342.17" case 1'1 case end @@ -381921,66 +372466,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src35__data_o$next[3:0]$11823 $5\src35__data_o$next[3:0]$11827 + assign $1\src35__data_o$next[3:0]$11526 $5\src35__data_o$next[3:0]$11530 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src35__data_o$next[3:0]$11824 \dest15__data_i + assign $2\src35__data_o$next[3:0]$11527 \dest15__data_i case - assign $2\src35__data_o$next[3:0]$11824 4'0000 + assign $2\src35__data_o$next[3:0]$11527 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src35__data_o$next[3:0]$11825 \dest25__data_i + assign $3\src35__data_o$next[3:0]$11528 \dest25__data_i case - assign $3\src35__data_o$next[3:0]$11825 $2\src35__data_o$next[3:0]$11824 + assign $3\src35__data_o$next[3:0]$11528 $2\src35__data_o$next[3:0]$11527 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src35__data_o$next[3:0]$11826 \w5__data_i + assign $4\src35__data_o$next[3:0]$11529 \w5__data_i case - assign $4\src35__data_o$next[3:0]$11826 $3\src35__data_o$next[3:0]$11825 + assign $4\src35__data_o$next[3:0]$11529 $3\src35__data_o$next[3:0]$11528 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src35__data_o$next[3:0]$11827 \reg + assign $5\src35__data_o$next[3:0]$11530 \reg case - assign $5\src35__data_o$next[3:0]$11827 $4\src35__data_o$next[3:0]$11826 + assign $5\src35__data_o$next[3:0]$11530 $4\src35__data_o$next[3:0]$11529 end case - assign $1\src35__data_o$next[3:0]$11823 4'0000 + assign $1\src35__data_o$next[3:0]$11526 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src35__data_o$next[3:0]$11828 4'0000 + assign $6\src35__data_o$next[3:0]$11531 4'0000 case - assign $6\src35__data_o$next[3:0]$11828 $1\src35__data_o$next[3:0]$11823 + assign $6\src35__data_o$next[3:0]$11531 $1\src35__data_o$next[3:0]$11526 end sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$11822 + update \src35__data_o$next $0\src35__data_o$next[3:0]$11525 end - attribute \src "libresoc.v:186186.3-186215.6" - process $proc$libresoc.v:186186$11829 + attribute \src "libresoc.v:180381.3-180410.6" + process $proc$libresoc.v:180381$11532 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11830 $1\wr_detect$7[0:0]$11831 - attribute \src "libresoc.v:186187.5-186187.29" + assign $0\wr_detect$7[0:0]$11533 $1\wr_detect$7[0:0]$11534 + attribute \src "libresoc.v:180382.5-180382.29" switch \initial - attribute \src "libresoc.v:186187.9-186187.17" + attribute \src "libresoc.v:180382.9-180382.17" case 1'1 case end @@ -381992,49 +372537,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11831 $4\wr_detect$7[0:0]$11834 + assign $1\wr_detect$7[0:0]$11534 $4\wr_detect$7[0:0]$11537 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11832 1'1 + assign $2\wr_detect$7[0:0]$11535 1'1 case - assign $2\wr_detect$7[0:0]$11832 1'0 + assign $2\wr_detect$7[0:0]$11535 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11833 1'1 + assign $3\wr_detect$7[0:0]$11536 1'1 case - assign $3\wr_detect$7[0:0]$11833 $2\wr_detect$7[0:0]$11832 + assign $3\wr_detect$7[0:0]$11536 $2\wr_detect$7[0:0]$11535 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11834 1'1 + assign $4\wr_detect$7[0:0]$11537 1'1 case - assign $4\wr_detect$7[0:0]$11834 $3\wr_detect$7[0:0]$11833 + assign $4\wr_detect$7[0:0]$11537 $3\wr_detect$7[0:0]$11536 end case - assign $1\wr_detect$7[0:0]$11831 1'0 + assign $1\wr_detect$7[0:0]$11534 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11830 + update \wr_detect$7 $0\wr_detect$7[0:0]$11533 end - attribute \src "libresoc.v:186216.3-186255.6" - process $proc$libresoc.v:186216$11835 + attribute \src "libresoc.v:180411.3-180450.6" + process $proc$libresoc.v:180411$11538 assign { } { } assign { } { } assign { } { } - assign $0\r5__data_o$next[3:0]$11836 $6\r5__data_o$next[3:0]$11842 - attribute \src "libresoc.v:186217.5-186217.29" + assign $0\r5__data_o$next[3:0]$11539 $6\r5__data_o$next[3:0]$11545 + attribute \src "libresoc.v:180412.5-180412.29" switch \initial - attribute \src "libresoc.v:186217.9-186217.17" + attribute \src "libresoc.v:180412.9-180412.17" case 1'1 case end @@ -382046,66 +372591,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r5__data_o$next[3:0]$11837 $5\r5__data_o$next[3:0]$11841 + assign $1\r5__data_o$next[3:0]$11540 $5\r5__data_o$next[3:0]$11544 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r5__data_o$next[3:0]$11838 \dest15__data_i + assign $2\r5__data_o$next[3:0]$11541 \dest15__data_i case - assign $2\r5__data_o$next[3:0]$11838 4'0000 + assign $2\r5__data_o$next[3:0]$11541 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r5__data_o$next[3:0]$11839 \dest25__data_i + assign $3\r5__data_o$next[3:0]$11542 \dest25__data_i case - assign $3\r5__data_o$next[3:0]$11839 $2\r5__data_o$next[3:0]$11838 + assign $3\r5__data_o$next[3:0]$11542 $2\r5__data_o$next[3:0]$11541 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r5__data_o$next[3:0]$11840 \w5__data_i + assign $4\r5__data_o$next[3:0]$11543 \w5__data_i case - assign $4\r5__data_o$next[3:0]$11840 $3\r5__data_o$next[3:0]$11839 + assign $4\r5__data_o$next[3:0]$11543 $3\r5__data_o$next[3:0]$11542 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r5__data_o$next[3:0]$11841 \reg + assign $5\r5__data_o$next[3:0]$11544 \reg case - assign $5\r5__data_o$next[3:0]$11841 $4\r5__data_o$next[3:0]$11840 + assign $5\r5__data_o$next[3:0]$11544 $4\r5__data_o$next[3:0]$11543 end case - assign $1\r5__data_o$next[3:0]$11837 4'0000 + assign $1\r5__data_o$next[3:0]$11540 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r5__data_o$next[3:0]$11842 4'0000 + assign $6\r5__data_o$next[3:0]$11545 4'0000 case - assign $6\r5__data_o$next[3:0]$11842 $1\r5__data_o$next[3:0]$11837 + assign $6\r5__data_o$next[3:0]$11545 $1\r5__data_o$next[3:0]$11540 end sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$11836 + update \r5__data_o$next $0\r5__data_o$next[3:0]$11539 end - attribute \src "libresoc.v:186256.3-186285.6" - process $proc$libresoc.v:186256$11843 + attribute \src "libresoc.v:180451.3-180480.6" + process $proc$libresoc.v:180451$11546 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11844 $1\wr_detect$10[0:0]$11845 - attribute \src "libresoc.v:186257.5-186257.29" + assign $0\wr_detect$10[0:0]$11547 $1\wr_detect$10[0:0]$11548 + attribute \src "libresoc.v:180452.5-180452.29" switch \initial - attribute \src "libresoc.v:186257.9-186257.17" + attribute \src "libresoc.v:180452.9-180452.17" case 1'1 case end @@ -382117,49 +372662,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11845 $4\wr_detect$10[0:0]$11848 + assign $1\wr_detect$10[0:0]$11548 $4\wr_detect$10[0:0]$11551 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11846 1'1 + assign $2\wr_detect$10[0:0]$11549 1'1 case - assign $2\wr_detect$10[0:0]$11846 1'0 + assign $2\wr_detect$10[0:0]$11549 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11847 1'1 + assign $3\wr_detect$10[0:0]$11550 1'1 case - assign $3\wr_detect$10[0:0]$11847 $2\wr_detect$10[0:0]$11846 + assign $3\wr_detect$10[0:0]$11550 $2\wr_detect$10[0:0]$11549 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11848 1'1 + assign $4\wr_detect$10[0:0]$11551 1'1 case - assign $4\wr_detect$10[0:0]$11848 $3\wr_detect$10[0:0]$11847 + assign $4\wr_detect$10[0:0]$11551 $3\wr_detect$10[0:0]$11550 end case - assign $1\wr_detect$10[0:0]$11845 1'0 + assign $1\wr_detect$10[0:0]$11548 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11844 + update \wr_detect$10 $0\wr_detect$10[0:0]$11547 end - attribute \src "libresoc.v:186286.3-186325.6" - process $proc$libresoc.v:186286$11849 + attribute \src "libresoc.v:180481.3-180520.6" + process $proc$libresoc.v:180481$11552 assign { } { } assign { } { } assign { } { } - assign $0\r25__data_o$next[3:0]$11850 $6\r25__data_o$next[3:0]$11856 - attribute \src "libresoc.v:186287.5-186287.29" + assign $0\r25__data_o$next[3:0]$11553 $6\r25__data_o$next[3:0]$11559 + attribute \src "libresoc.v:180482.5-180482.29" switch \initial - attribute \src "libresoc.v:186287.9-186287.17" + attribute \src "libresoc.v:180482.9-180482.17" case 1'1 case end @@ -382171,66 +372716,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r25__data_o$next[3:0]$11851 $5\r25__data_o$next[3:0]$11855 + assign $1\r25__data_o$next[3:0]$11554 $5\r25__data_o$next[3:0]$11558 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r25__data_o$next[3:0]$11852 \dest15__data_i + assign $2\r25__data_o$next[3:0]$11555 \dest15__data_i case - assign $2\r25__data_o$next[3:0]$11852 4'0000 + assign $2\r25__data_o$next[3:0]$11555 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r25__data_o$next[3:0]$11853 \dest25__data_i + assign $3\r25__data_o$next[3:0]$11556 \dest25__data_i case - assign $3\r25__data_o$next[3:0]$11853 $2\r25__data_o$next[3:0]$11852 + assign $3\r25__data_o$next[3:0]$11556 $2\r25__data_o$next[3:0]$11555 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r25__data_o$next[3:0]$11854 \w5__data_i + assign $4\r25__data_o$next[3:0]$11557 \w5__data_i case - assign $4\r25__data_o$next[3:0]$11854 $3\r25__data_o$next[3:0]$11853 + assign $4\r25__data_o$next[3:0]$11557 $3\r25__data_o$next[3:0]$11556 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r25__data_o$next[3:0]$11855 \reg + assign $5\r25__data_o$next[3:0]$11558 \reg case - assign $5\r25__data_o$next[3:0]$11855 $4\r25__data_o$next[3:0]$11854 + assign $5\r25__data_o$next[3:0]$11558 $4\r25__data_o$next[3:0]$11557 end case - assign $1\r25__data_o$next[3:0]$11851 4'0000 + assign $1\r25__data_o$next[3:0]$11554 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r25__data_o$next[3:0]$11856 4'0000 + assign $6\r25__data_o$next[3:0]$11559 4'0000 case - assign $6\r25__data_o$next[3:0]$11856 $1\r25__data_o$next[3:0]$11851 + assign $6\r25__data_o$next[3:0]$11559 $1\r25__data_o$next[3:0]$11554 end sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$11850 + update \r25__data_o$next $0\r25__data_o$next[3:0]$11553 end - attribute \src "libresoc.v:186326.3-186355.6" - process $proc$libresoc.v:186326$11857 + attribute \src "libresoc.v:180521.3-180550.6" + process $proc$libresoc.v:180521$11560 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11858 $1\wr_detect$13[0:0]$11859 - attribute \src "libresoc.v:186327.5-186327.29" + assign $0\wr_detect$13[0:0]$11561 $1\wr_detect$13[0:0]$11562 + attribute \src "libresoc.v:180522.5-180522.29" switch \initial - attribute \src "libresoc.v:186327.9-186327.17" + attribute \src "libresoc.v:180522.9-180522.17" case 1'1 case end @@ -382242,217 +372787,217 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11859 $4\wr_detect$13[0:0]$11862 + assign $1\wr_detect$13[0:0]$11562 $4\wr_detect$13[0:0]$11565 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11860 1'1 + assign $2\wr_detect$13[0:0]$11563 1'1 case - assign $2\wr_detect$13[0:0]$11860 1'0 + assign $2\wr_detect$13[0:0]$11563 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11861 1'1 + assign $3\wr_detect$13[0:0]$11564 1'1 case - assign $3\wr_detect$13[0:0]$11861 $2\wr_detect$13[0:0]$11860 + assign $3\wr_detect$13[0:0]$11564 $2\wr_detect$13[0:0]$11563 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11862 1'1 + assign $4\wr_detect$13[0:0]$11565 1'1 case - assign $4\wr_detect$13[0:0]$11862 $3\wr_detect$13[0:0]$11861 + assign $4\wr_detect$13[0:0]$11565 $3\wr_detect$13[0:0]$11564 end case - assign $1\wr_detect$13[0:0]$11859 1'0 + assign $1\wr_detect$13[0:0]$11562 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11858 + update \wr_detect$13 $0\wr_detect$13[0:0]$11561 end - connect \$9 $not$libresoc.v:185962$11781_Y - connect \$12 $not$libresoc.v:185963$11782_Y - connect \$1 $not$libresoc.v:185964$11783_Y - connect \$3 $not$libresoc.v:185965$11784_Y - connect \$6 $not$libresoc.v:185966$11785_Y + connect \$9 $not$libresoc.v:180157$11484_Y + connect \$12 $not$libresoc.v:180158$11485_Y + connect \$1 $not$libresoc.v:180159$11486_Y + connect \$3 $not$libresoc.v:180160$11487_Y + connect \$6 $not$libresoc.v:180161$11488_Y end -attribute \src "libresoc.v:186360.1-186831.10" +attribute \src "libresoc.v:180555.1-181026.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 - attribute \src "libresoc.v:186361.7-186361.20" + attribute \src "libresoc.v:180556.7-180556.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186761.3-186800.6" - wire width 4 $0\r26__data_o$next[3:0]$11939 - attribute \src "libresoc.v:186444.3-186445.39" + attribute \src "libresoc.v:180956.3-180995.6" + wire width 4 $0\r26__data_o$next[3:0]$11642 + attribute \src "libresoc.v:180639.3-180640.39" wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:186691.3-186730.6" - wire width 4 $0\r6__data_o$next[3:0]$11925 - attribute \src "libresoc.v:186446.3-186447.37" + attribute \src "libresoc.v:180886.3-180925.6" + wire width 4 $0\r6__data_o$next[3:0]$11628 + attribute \src "libresoc.v:180641.3-180642.37" wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:186524.3-186550.6" - wire width 4 $0\reg$next[3:0]$11891 - attribute \src "libresoc.v:186442.3-186443.25" + attribute \src "libresoc.v:180719.3-180745.6" + wire width 4 $0\reg$next[3:0]$11594 + attribute \src "libresoc.v:180637.3-180638.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:186454.3-186493.6" - wire width 4 $0\src16__data_o$next[3:0]$11882 - attribute \src "libresoc.v:186452.3-186453.43" + attribute \src "libresoc.v:180649.3-180688.6" + wire width 4 $0\src16__data_o$next[3:0]$11585 + attribute \src "libresoc.v:180647.3-180648.43" wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:186551.3-186590.6" - wire width 4 $0\src26__data_o$next[3:0]$11897 - attribute \src "libresoc.v:186450.3-186451.43" + attribute \src "libresoc.v:180746.3-180785.6" + wire width 4 $0\src26__data_o$next[3:0]$11600 + attribute \src "libresoc.v:180645.3-180646.43" wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:186621.3-186660.6" - wire width 4 $0\src36__data_o$next[3:0]$11911 - attribute \src "libresoc.v:186448.3-186449.43" + attribute \src "libresoc.v:180816.3-180855.6" + wire width 4 $0\src36__data_o$next[3:0]$11614 + attribute \src "libresoc.v:180643.3-180644.43" wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:186731.3-186760.6" - wire $0\wr_detect$10[0:0]$11933 - attribute \src "libresoc.v:186801.3-186830.6" - wire $0\wr_detect$13[0:0]$11947 - attribute \src "libresoc.v:186591.3-186620.6" - wire $0\wr_detect$4[0:0]$11905 - attribute \src "libresoc.v:186661.3-186690.6" - wire $0\wr_detect$7[0:0]$11919 - attribute \src "libresoc.v:186494.3-186523.6" + attribute \src "libresoc.v:180926.3-180955.6" + wire $0\wr_detect$10[0:0]$11636 + attribute \src "libresoc.v:180996.3-181025.6" + wire $0\wr_detect$13[0:0]$11650 + attribute \src "libresoc.v:180786.3-180815.6" + wire $0\wr_detect$4[0:0]$11608 + attribute \src "libresoc.v:180856.3-180885.6" + wire $0\wr_detect$7[0:0]$11622 + attribute \src "libresoc.v:180689.3-180718.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:186761.3-186800.6" - wire width 4 $1\r26__data_o$next[3:0]$11940 - attribute \src "libresoc.v:186386.13-186386.31" + attribute \src "libresoc.v:180956.3-180995.6" + wire width 4 $1\r26__data_o$next[3:0]$11643 + attribute \src "libresoc.v:180581.13-180581.31" wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:186691.3-186730.6" - wire width 4 $1\r6__data_o$next[3:0]$11926 - attribute \src "libresoc.v:186393.13-186393.30" + attribute \src "libresoc.v:180886.3-180925.6" + wire width 4 $1\r6__data_o$next[3:0]$11629 + attribute \src "libresoc.v:180588.13-180588.30" wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:186524.3-186550.6" - wire width 4 $1\reg$next[3:0]$11892 - attribute \src "libresoc.v:186399.13-186399.25" + attribute \src "libresoc.v:180719.3-180745.6" + wire width 4 $1\reg$next[3:0]$11595 + attribute \src "libresoc.v:180594.13-180594.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:186454.3-186493.6" - wire width 4 $1\src16__data_o$next[3:0]$11883 - attribute \src "libresoc.v:186404.13-186404.33" + attribute \src "libresoc.v:180649.3-180688.6" + wire width 4 $1\src16__data_o$next[3:0]$11586 + attribute \src "libresoc.v:180599.13-180599.33" wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:186551.3-186590.6" - wire width 4 $1\src26__data_o$next[3:0]$11898 - attribute \src "libresoc.v:186411.13-186411.33" + attribute \src "libresoc.v:180746.3-180785.6" + wire width 4 $1\src26__data_o$next[3:0]$11601 + attribute \src "libresoc.v:180606.13-180606.33" wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:186621.3-186660.6" - wire width 4 $1\src36__data_o$next[3:0]$11912 - attribute \src "libresoc.v:186418.13-186418.33" + attribute \src "libresoc.v:180816.3-180855.6" + wire width 4 $1\src36__data_o$next[3:0]$11615 + attribute \src "libresoc.v:180613.13-180613.33" wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:186731.3-186760.6" - wire $1\wr_detect$10[0:0]$11934 - attribute \src "libresoc.v:186801.3-186830.6" - wire $1\wr_detect$13[0:0]$11948 - attribute \src "libresoc.v:186591.3-186620.6" - wire $1\wr_detect$4[0:0]$11906 - attribute \src "libresoc.v:186661.3-186690.6" - wire $1\wr_detect$7[0:0]$11920 - attribute \src "libresoc.v:186494.3-186523.6" + attribute \src "libresoc.v:180926.3-180955.6" + wire $1\wr_detect$10[0:0]$11637 + attribute \src "libresoc.v:180996.3-181025.6" + wire $1\wr_detect$13[0:0]$11651 + attribute \src "libresoc.v:180786.3-180815.6" + wire $1\wr_detect$4[0:0]$11609 + attribute \src "libresoc.v:180856.3-180885.6" + wire $1\wr_detect$7[0:0]$11623 + attribute \src "libresoc.v:180689.3-180718.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:186761.3-186800.6" - wire width 4 $2\r26__data_o$next[3:0]$11941 - attribute \src "libresoc.v:186691.3-186730.6" - wire width 4 $2\r6__data_o$next[3:0]$11927 - attribute \src "libresoc.v:186524.3-186550.6" - wire width 4 $2\reg$next[3:0]$11893 - attribute \src "libresoc.v:186454.3-186493.6" - wire width 4 $2\src16__data_o$next[3:0]$11884 - attribute \src "libresoc.v:186551.3-186590.6" - wire width 4 $2\src26__data_o$next[3:0]$11899 - attribute \src "libresoc.v:186621.3-186660.6" - wire width 4 $2\src36__data_o$next[3:0]$11913 - attribute \src "libresoc.v:186731.3-186760.6" - wire $2\wr_detect$10[0:0]$11935 - attribute \src "libresoc.v:186801.3-186830.6" - wire $2\wr_detect$13[0:0]$11949 - attribute \src "libresoc.v:186591.3-186620.6" - wire $2\wr_detect$4[0:0]$11907 - attribute \src "libresoc.v:186661.3-186690.6" - wire $2\wr_detect$7[0:0]$11921 - attribute \src "libresoc.v:186494.3-186523.6" + attribute \src "libresoc.v:180956.3-180995.6" + wire width 4 $2\r26__data_o$next[3:0]$11644 + attribute \src "libresoc.v:180886.3-180925.6" + wire width 4 $2\r6__data_o$next[3:0]$11630 + attribute \src "libresoc.v:180719.3-180745.6" + wire width 4 $2\reg$next[3:0]$11596 + attribute \src "libresoc.v:180649.3-180688.6" + wire width 4 $2\src16__data_o$next[3:0]$11587 + attribute \src "libresoc.v:180746.3-180785.6" + wire width 4 $2\src26__data_o$next[3:0]$11602 + attribute \src "libresoc.v:180816.3-180855.6" + wire width 4 $2\src36__data_o$next[3:0]$11616 + attribute \src "libresoc.v:180926.3-180955.6" + wire $2\wr_detect$10[0:0]$11638 + attribute \src "libresoc.v:180996.3-181025.6" + wire $2\wr_detect$13[0:0]$11652 + attribute \src "libresoc.v:180786.3-180815.6" + wire $2\wr_detect$4[0:0]$11610 + attribute \src "libresoc.v:180856.3-180885.6" + wire $2\wr_detect$7[0:0]$11624 + attribute \src "libresoc.v:180689.3-180718.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:186761.3-186800.6" - wire width 4 $3\r26__data_o$next[3:0]$11942 - attribute \src "libresoc.v:186691.3-186730.6" - wire width 4 $3\r6__data_o$next[3:0]$11928 - attribute \src "libresoc.v:186524.3-186550.6" - wire width 4 $3\reg$next[3:0]$11894 - attribute \src "libresoc.v:186454.3-186493.6" - wire width 4 $3\src16__data_o$next[3:0]$11885 - attribute \src "libresoc.v:186551.3-186590.6" - wire width 4 $3\src26__data_o$next[3:0]$11900 - attribute \src "libresoc.v:186621.3-186660.6" - wire width 4 $3\src36__data_o$next[3:0]$11914 - attribute \src "libresoc.v:186731.3-186760.6" - wire $3\wr_detect$10[0:0]$11936 - attribute \src "libresoc.v:186801.3-186830.6" - wire $3\wr_detect$13[0:0]$11950 - attribute \src "libresoc.v:186591.3-186620.6" - wire $3\wr_detect$4[0:0]$11908 - attribute \src "libresoc.v:186661.3-186690.6" - wire $3\wr_detect$7[0:0]$11922 - attribute \src "libresoc.v:186494.3-186523.6" + attribute \src "libresoc.v:180956.3-180995.6" + wire width 4 $3\r26__data_o$next[3:0]$11645 + attribute \src "libresoc.v:180886.3-180925.6" + wire width 4 $3\r6__data_o$next[3:0]$11631 + attribute \src "libresoc.v:180719.3-180745.6" + wire width 4 $3\reg$next[3:0]$11597 + attribute \src "libresoc.v:180649.3-180688.6" + wire width 4 $3\src16__data_o$next[3:0]$11588 + attribute \src "libresoc.v:180746.3-180785.6" + wire width 4 $3\src26__data_o$next[3:0]$11603 + attribute \src "libresoc.v:180816.3-180855.6" + wire width 4 $3\src36__data_o$next[3:0]$11617 + attribute \src "libresoc.v:180926.3-180955.6" + wire $3\wr_detect$10[0:0]$11639 + attribute \src "libresoc.v:180996.3-181025.6" + wire $3\wr_detect$13[0:0]$11653 + attribute \src "libresoc.v:180786.3-180815.6" + wire $3\wr_detect$4[0:0]$11611 + attribute \src "libresoc.v:180856.3-180885.6" + wire $3\wr_detect$7[0:0]$11625 + attribute \src "libresoc.v:180689.3-180718.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:186761.3-186800.6" - wire width 4 $4\r26__data_o$next[3:0]$11943 - attribute \src "libresoc.v:186691.3-186730.6" - wire width 4 $4\r6__data_o$next[3:0]$11929 - attribute \src "libresoc.v:186524.3-186550.6" - wire width 4 $4\reg$next[3:0]$11895 - attribute \src "libresoc.v:186454.3-186493.6" - wire width 4 $4\src16__data_o$next[3:0]$11886 - attribute \src "libresoc.v:186551.3-186590.6" - wire width 4 $4\src26__data_o$next[3:0]$11901 - attribute \src "libresoc.v:186621.3-186660.6" - wire width 4 $4\src36__data_o$next[3:0]$11915 - attribute \src "libresoc.v:186731.3-186760.6" - wire $4\wr_detect$10[0:0]$11937 - attribute \src "libresoc.v:186801.3-186830.6" - wire $4\wr_detect$13[0:0]$11951 - attribute \src "libresoc.v:186591.3-186620.6" - wire $4\wr_detect$4[0:0]$11909 - attribute \src "libresoc.v:186661.3-186690.6" - wire $4\wr_detect$7[0:0]$11923 - attribute \src "libresoc.v:186494.3-186523.6" + attribute \src "libresoc.v:180956.3-180995.6" + wire width 4 $4\r26__data_o$next[3:0]$11646 + attribute \src "libresoc.v:180886.3-180925.6" + wire width 4 $4\r6__data_o$next[3:0]$11632 + attribute \src "libresoc.v:180719.3-180745.6" + wire width 4 $4\reg$next[3:0]$11598 + attribute \src "libresoc.v:180649.3-180688.6" + wire width 4 $4\src16__data_o$next[3:0]$11589 + attribute \src "libresoc.v:180746.3-180785.6" + wire width 4 $4\src26__data_o$next[3:0]$11604 + attribute \src "libresoc.v:180816.3-180855.6" + wire width 4 $4\src36__data_o$next[3:0]$11618 + attribute \src "libresoc.v:180926.3-180955.6" + wire $4\wr_detect$10[0:0]$11640 + attribute \src "libresoc.v:180996.3-181025.6" + wire $4\wr_detect$13[0:0]$11654 + attribute \src "libresoc.v:180786.3-180815.6" + wire $4\wr_detect$4[0:0]$11612 + attribute \src "libresoc.v:180856.3-180885.6" + wire $4\wr_detect$7[0:0]$11626 + attribute \src "libresoc.v:180689.3-180718.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:186761.3-186800.6" - wire width 4 $5\r26__data_o$next[3:0]$11944 - attribute \src "libresoc.v:186691.3-186730.6" - wire width 4 $5\r6__data_o$next[3:0]$11930 - attribute \src "libresoc.v:186454.3-186493.6" - wire width 4 $5\src16__data_o$next[3:0]$11887 - attribute \src "libresoc.v:186551.3-186590.6" - wire width 4 $5\src26__data_o$next[3:0]$11902 - attribute \src "libresoc.v:186621.3-186660.6" - wire width 4 $5\src36__data_o$next[3:0]$11916 - attribute \src "libresoc.v:186761.3-186800.6" - wire width 4 $6\r26__data_o$next[3:0]$11945 - attribute \src "libresoc.v:186691.3-186730.6" - wire width 4 $6\r6__data_o$next[3:0]$11931 - attribute \src "libresoc.v:186454.3-186493.6" - wire width 4 $6\src16__data_o$next[3:0]$11888 - attribute \src "libresoc.v:186551.3-186590.6" - wire width 4 $6\src26__data_o$next[3:0]$11903 - attribute \src "libresoc.v:186621.3-186660.6" - wire width 4 $6\src36__data_o$next[3:0]$11917 - attribute \src "libresoc.v:186437.17-186437.104" - wire $not$libresoc.v:186437$11870_Y - attribute \src "libresoc.v:186438.18-186438.105" - wire $not$libresoc.v:186438$11871_Y - attribute \src "libresoc.v:186439.17-186439.100" - wire $not$libresoc.v:186439$11872_Y - attribute \src "libresoc.v:186440.17-186440.103" - wire $not$libresoc.v:186440$11873_Y - attribute \src "libresoc.v:186441.17-186441.103" - wire $not$libresoc.v:186441$11874_Y + attribute \src "libresoc.v:180956.3-180995.6" + wire width 4 $5\r26__data_o$next[3:0]$11647 + attribute \src "libresoc.v:180886.3-180925.6" + wire width 4 $5\r6__data_o$next[3:0]$11633 + attribute \src "libresoc.v:180649.3-180688.6" + wire width 4 $5\src16__data_o$next[3:0]$11590 + attribute \src "libresoc.v:180746.3-180785.6" + wire width 4 $5\src26__data_o$next[3:0]$11605 + attribute \src "libresoc.v:180816.3-180855.6" + wire width 4 $5\src36__data_o$next[3:0]$11619 + attribute \src "libresoc.v:180956.3-180995.6" + wire width 4 $6\r26__data_o$next[3:0]$11648 + attribute \src "libresoc.v:180886.3-180925.6" + wire width 4 $6\r6__data_o$next[3:0]$11634 + attribute \src "libresoc.v:180649.3-180688.6" + wire width 4 $6\src16__data_o$next[3:0]$11591 + attribute \src "libresoc.v:180746.3-180785.6" + wire width 4 $6\src26__data_o$next[3:0]$11606 + attribute \src "libresoc.v:180816.3-180855.6" + wire width 4 $6\src36__data_o$next[3:0]$11620 + attribute \src "libresoc.v:180632.17-180632.104" + wire $not$libresoc.v:180632$11573_Y + attribute \src "libresoc.v:180633.18-180633.105" + wire $not$libresoc.v:180633$11574_Y + attribute \src "libresoc.v:180634.17-180634.100" + wire $not$libresoc.v:180634$11575_Y + attribute \src "libresoc.v:180635.17-180635.103" + wire $not$libresoc.v:180635$11576_Y + attribute \src "libresoc.v:180636.17-180636.103" + wire $not$libresoc.v:180636$11577_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -382463,9 +373008,9 @@ module \reg_6 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest16__data_i @@ -382475,7 +373020,7 @@ module \reg_6 wire width 4 input 11 \dest26__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest26__wen - attribute \src "libresoc.v:186361.7-186361.15" + attribute \src "libresoc.v:180556.7-180556.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r26__data_o @@ -382526,152 +373071,152 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:186437$11870 + cell $not $not$libresoc.v:180632$11573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:186437$11870_Y + connect \Y $not$libresoc.v:180632$11573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:186438$11871 + cell $not $not$libresoc.v:180633$11574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:186438$11871_Y + connect \Y $not$libresoc.v:180633$11574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:186439$11872 + cell $not $not$libresoc.v:180634$11575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:186439$11872_Y + connect \Y $not$libresoc.v:180634$11575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:186440$11873 + cell $not $not$libresoc.v:180635$11576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:186440$11873_Y + connect \Y $not$libresoc.v:180635$11576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:186441$11874 + cell $not $not$libresoc.v:180636$11577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:186441$11874_Y + connect \Y $not$libresoc.v:180636$11577_Y end - attribute \src "libresoc.v:186361.7-186361.20" - process $proc$libresoc.v:186361$11952 + attribute \src "libresoc.v:180556.7-180556.20" + process $proc$libresoc.v:180556$11655 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186386.13-186386.31" - process $proc$libresoc.v:186386$11953 + attribute \src "libresoc.v:180581.13-180581.31" + process $proc$libresoc.v:180581$11656 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end - attribute \src "libresoc.v:186393.13-186393.30" - process $proc$libresoc.v:186393$11954 + attribute \src "libresoc.v:180588.13-180588.30" + process $proc$libresoc.v:180588$11657 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end - attribute \src "libresoc.v:186399.13-186399.25" - process $proc$libresoc.v:186399$11955 + attribute \src "libresoc.v:180594.13-180594.25" + process $proc$libresoc.v:180594$11658 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:186404.13-186404.33" - process $proc$libresoc.v:186404$11956 + attribute \src "libresoc.v:180599.13-180599.33" + process $proc$libresoc.v:180599$11659 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end - attribute \src "libresoc.v:186411.13-186411.33" - process $proc$libresoc.v:186411$11957 + attribute \src "libresoc.v:180606.13-180606.33" + process $proc$libresoc.v:180606$11660 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end - attribute \src "libresoc.v:186418.13-186418.33" - process $proc$libresoc.v:186418$11958 + attribute \src "libresoc.v:180613.13-180613.33" + process $proc$libresoc.v:180613$11661 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end - attribute \src "libresoc.v:186442.3-186443.25" - process $proc$libresoc.v:186442$11875 + attribute \src "libresoc.v:180637.3-180638.25" + process $proc$libresoc.v:180637$11578 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:186444.3-186445.39" - process $proc$libresoc.v:186444$11876 + attribute \src "libresoc.v:180639.3-180640.39" + process $proc$libresoc.v:180639$11579 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end - attribute \src "libresoc.v:186446.3-186447.37" - process $proc$libresoc.v:186446$11877 + attribute \src "libresoc.v:180641.3-180642.37" + process $proc$libresoc.v:180641$11580 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end - attribute \src "libresoc.v:186448.3-186449.43" - process $proc$libresoc.v:186448$11878 + attribute \src "libresoc.v:180643.3-180644.43" + process $proc$libresoc.v:180643$11581 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end - attribute \src "libresoc.v:186450.3-186451.43" - process $proc$libresoc.v:186450$11879 + attribute \src "libresoc.v:180645.3-180646.43" + process $proc$libresoc.v:180645$11582 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end - attribute \src "libresoc.v:186452.3-186453.43" - process $proc$libresoc.v:186452$11880 + attribute \src "libresoc.v:180647.3-180648.43" + process $proc$libresoc.v:180647$11583 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end - attribute \src "libresoc.v:186454.3-186493.6" - process $proc$libresoc.v:186454$11881 + attribute \src "libresoc.v:180649.3-180688.6" + process $proc$libresoc.v:180649$11584 assign { } { } assign { } { } assign { } { } - assign $0\src16__data_o$next[3:0]$11882 $6\src16__data_o$next[3:0]$11888 - attribute \src "libresoc.v:186455.5-186455.29" + assign $0\src16__data_o$next[3:0]$11585 $6\src16__data_o$next[3:0]$11591 + attribute \src "libresoc.v:180650.5-180650.29" switch \initial - attribute \src "libresoc.v:186455.9-186455.17" + attribute \src "libresoc.v:180650.9-180650.17" case 1'1 case end @@ -382683,66 +373228,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src16__data_o$next[3:0]$11883 $5\src16__data_o$next[3:0]$11887 + assign $1\src16__data_o$next[3:0]$11586 $5\src16__data_o$next[3:0]$11590 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src16__data_o$next[3:0]$11884 \dest16__data_i + assign $2\src16__data_o$next[3:0]$11587 \dest16__data_i case - assign $2\src16__data_o$next[3:0]$11884 4'0000 + assign $2\src16__data_o$next[3:0]$11587 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src16__data_o$next[3:0]$11885 \dest26__data_i + assign $3\src16__data_o$next[3:0]$11588 \dest26__data_i case - assign $3\src16__data_o$next[3:0]$11885 $2\src16__data_o$next[3:0]$11884 + assign $3\src16__data_o$next[3:0]$11588 $2\src16__data_o$next[3:0]$11587 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src16__data_o$next[3:0]$11886 \w6__data_i + assign $4\src16__data_o$next[3:0]$11589 \w6__data_i case - assign $4\src16__data_o$next[3:0]$11886 $3\src16__data_o$next[3:0]$11885 + assign $4\src16__data_o$next[3:0]$11589 $3\src16__data_o$next[3:0]$11588 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src16__data_o$next[3:0]$11887 \reg + assign $5\src16__data_o$next[3:0]$11590 \reg case - assign $5\src16__data_o$next[3:0]$11887 $4\src16__data_o$next[3:0]$11886 + assign $5\src16__data_o$next[3:0]$11590 $4\src16__data_o$next[3:0]$11589 end case - assign $1\src16__data_o$next[3:0]$11883 4'0000 + assign $1\src16__data_o$next[3:0]$11586 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src16__data_o$next[3:0]$11888 4'0000 + assign $6\src16__data_o$next[3:0]$11591 4'0000 case - assign $6\src16__data_o$next[3:0]$11888 $1\src16__data_o$next[3:0]$11883 + assign $6\src16__data_o$next[3:0]$11591 $1\src16__data_o$next[3:0]$11586 end sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$11882 + update \src16__data_o$next $0\src16__data_o$next[3:0]$11585 end - attribute \src "libresoc.v:186494.3-186523.6" - process $proc$libresoc.v:186494$11889 + attribute \src "libresoc.v:180689.3-180718.6" + process $proc$libresoc.v:180689$11592 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:186495.5-186495.29" + attribute \src "libresoc.v:180690.5-180690.29" switch \initial - attribute \src "libresoc.v:186495.9-186495.17" + attribute \src "libresoc.v:180690.9-180690.17" case 1'1 case end @@ -382788,17 +373333,17 @@ module \reg_6 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:186524.3-186550.6" - process $proc$libresoc.v:186524$11890 + attribute \src "libresoc.v:180719.3-180745.6" + process $proc$libresoc.v:180719$11593 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11891 $4\reg$next[3:0]$11895 - attribute \src "libresoc.v:186525.5-186525.29" + assign $0\reg$next[3:0]$11594 $4\reg$next[3:0]$11598 + attribute \src "libresoc.v:180720.5-180720.29" switch \initial - attribute \src "libresoc.v:186525.9-186525.17" + attribute \src "libresoc.v:180720.9-180720.17" case 1'1 case end @@ -382807,49 +373352,49 @@ module \reg_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11892 \dest16__data_i + assign $1\reg$next[3:0]$11595 \dest16__data_i case - assign $1\reg$next[3:0]$11892 \reg + assign $1\reg$next[3:0]$11595 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11893 \dest26__data_i + assign $2\reg$next[3:0]$11596 \dest26__data_i case - assign $2\reg$next[3:0]$11893 $1\reg$next[3:0]$11892 + assign $2\reg$next[3:0]$11596 $1\reg$next[3:0]$11595 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11894 \w6__data_i + assign $3\reg$next[3:0]$11597 \w6__data_i case - assign $3\reg$next[3:0]$11894 $2\reg$next[3:0]$11893 + assign $3\reg$next[3:0]$11597 $2\reg$next[3:0]$11596 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11895 4'0000 + assign $4\reg$next[3:0]$11598 4'0000 case - assign $4\reg$next[3:0]$11895 $3\reg$next[3:0]$11894 + assign $4\reg$next[3:0]$11598 $3\reg$next[3:0]$11597 end sync always - update \reg$next $0\reg$next[3:0]$11891 + update \reg$next $0\reg$next[3:0]$11594 end - attribute \src "libresoc.v:186551.3-186590.6" - process $proc$libresoc.v:186551$11896 + attribute \src "libresoc.v:180746.3-180785.6" + process $proc$libresoc.v:180746$11599 assign { } { } assign { } { } assign { } { } - assign $0\src26__data_o$next[3:0]$11897 $6\src26__data_o$next[3:0]$11903 - attribute \src "libresoc.v:186552.5-186552.29" + assign $0\src26__data_o$next[3:0]$11600 $6\src26__data_o$next[3:0]$11606 + attribute \src "libresoc.v:180747.5-180747.29" switch \initial - attribute \src "libresoc.v:186552.9-186552.17" + attribute \src "libresoc.v:180747.9-180747.17" case 1'1 case end @@ -382861,66 +373406,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src26__data_o$next[3:0]$11898 $5\src26__data_o$next[3:0]$11902 + assign $1\src26__data_o$next[3:0]$11601 $5\src26__data_o$next[3:0]$11605 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src26__data_o$next[3:0]$11899 \dest16__data_i + assign $2\src26__data_o$next[3:0]$11602 \dest16__data_i case - assign $2\src26__data_o$next[3:0]$11899 4'0000 + assign $2\src26__data_o$next[3:0]$11602 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src26__data_o$next[3:0]$11900 \dest26__data_i + assign $3\src26__data_o$next[3:0]$11603 \dest26__data_i case - assign $3\src26__data_o$next[3:0]$11900 $2\src26__data_o$next[3:0]$11899 + assign $3\src26__data_o$next[3:0]$11603 $2\src26__data_o$next[3:0]$11602 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src26__data_o$next[3:0]$11901 \w6__data_i + assign $4\src26__data_o$next[3:0]$11604 \w6__data_i case - assign $4\src26__data_o$next[3:0]$11901 $3\src26__data_o$next[3:0]$11900 + assign $4\src26__data_o$next[3:0]$11604 $3\src26__data_o$next[3:0]$11603 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src26__data_o$next[3:0]$11902 \reg + assign $5\src26__data_o$next[3:0]$11605 \reg case - assign $5\src26__data_o$next[3:0]$11902 $4\src26__data_o$next[3:0]$11901 + assign $5\src26__data_o$next[3:0]$11605 $4\src26__data_o$next[3:0]$11604 end case - assign $1\src26__data_o$next[3:0]$11898 4'0000 + assign $1\src26__data_o$next[3:0]$11601 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src26__data_o$next[3:0]$11903 4'0000 + assign $6\src26__data_o$next[3:0]$11606 4'0000 case - assign $6\src26__data_o$next[3:0]$11903 $1\src26__data_o$next[3:0]$11898 + assign $6\src26__data_o$next[3:0]$11606 $1\src26__data_o$next[3:0]$11601 end sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$11897 + update \src26__data_o$next $0\src26__data_o$next[3:0]$11600 end - attribute \src "libresoc.v:186591.3-186620.6" - process $proc$libresoc.v:186591$11904 + attribute \src "libresoc.v:180786.3-180815.6" + process $proc$libresoc.v:180786$11607 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11905 $1\wr_detect$4[0:0]$11906 - attribute \src "libresoc.v:186592.5-186592.29" + assign $0\wr_detect$4[0:0]$11608 $1\wr_detect$4[0:0]$11609 + attribute \src "libresoc.v:180787.5-180787.29" switch \initial - attribute \src "libresoc.v:186592.9-186592.17" + attribute \src "libresoc.v:180787.9-180787.17" case 1'1 case end @@ -382932,49 +373477,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11906 $4\wr_detect$4[0:0]$11909 + assign $1\wr_detect$4[0:0]$11609 $4\wr_detect$4[0:0]$11612 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11907 1'1 + assign $2\wr_detect$4[0:0]$11610 1'1 case - assign $2\wr_detect$4[0:0]$11907 1'0 + assign $2\wr_detect$4[0:0]$11610 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11908 1'1 + assign $3\wr_detect$4[0:0]$11611 1'1 case - assign $3\wr_detect$4[0:0]$11908 $2\wr_detect$4[0:0]$11907 + assign $3\wr_detect$4[0:0]$11611 $2\wr_detect$4[0:0]$11610 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11909 1'1 + assign $4\wr_detect$4[0:0]$11612 1'1 case - assign $4\wr_detect$4[0:0]$11909 $3\wr_detect$4[0:0]$11908 + assign $4\wr_detect$4[0:0]$11612 $3\wr_detect$4[0:0]$11611 end case - assign $1\wr_detect$4[0:0]$11906 1'0 + assign $1\wr_detect$4[0:0]$11609 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11905 + update \wr_detect$4 $0\wr_detect$4[0:0]$11608 end - attribute \src "libresoc.v:186621.3-186660.6" - process $proc$libresoc.v:186621$11910 + attribute \src "libresoc.v:180816.3-180855.6" + process $proc$libresoc.v:180816$11613 assign { } { } assign { } { } assign { } { } - assign $0\src36__data_o$next[3:0]$11911 $6\src36__data_o$next[3:0]$11917 - attribute \src "libresoc.v:186622.5-186622.29" + assign $0\src36__data_o$next[3:0]$11614 $6\src36__data_o$next[3:0]$11620 + attribute \src "libresoc.v:180817.5-180817.29" switch \initial - attribute \src "libresoc.v:186622.9-186622.17" + attribute \src "libresoc.v:180817.9-180817.17" case 1'1 case end @@ -382986,66 +373531,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src36__data_o$next[3:0]$11912 $5\src36__data_o$next[3:0]$11916 + assign $1\src36__data_o$next[3:0]$11615 $5\src36__data_o$next[3:0]$11619 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src36__data_o$next[3:0]$11913 \dest16__data_i + assign $2\src36__data_o$next[3:0]$11616 \dest16__data_i case - assign $2\src36__data_o$next[3:0]$11913 4'0000 + assign $2\src36__data_o$next[3:0]$11616 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src36__data_o$next[3:0]$11914 \dest26__data_i + assign $3\src36__data_o$next[3:0]$11617 \dest26__data_i case - assign $3\src36__data_o$next[3:0]$11914 $2\src36__data_o$next[3:0]$11913 + assign $3\src36__data_o$next[3:0]$11617 $2\src36__data_o$next[3:0]$11616 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src36__data_o$next[3:0]$11915 \w6__data_i + assign $4\src36__data_o$next[3:0]$11618 \w6__data_i case - assign $4\src36__data_o$next[3:0]$11915 $3\src36__data_o$next[3:0]$11914 + assign $4\src36__data_o$next[3:0]$11618 $3\src36__data_o$next[3:0]$11617 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src36__data_o$next[3:0]$11916 \reg + assign $5\src36__data_o$next[3:0]$11619 \reg case - assign $5\src36__data_o$next[3:0]$11916 $4\src36__data_o$next[3:0]$11915 + assign $5\src36__data_o$next[3:0]$11619 $4\src36__data_o$next[3:0]$11618 end case - assign $1\src36__data_o$next[3:0]$11912 4'0000 + assign $1\src36__data_o$next[3:0]$11615 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src36__data_o$next[3:0]$11917 4'0000 + assign $6\src36__data_o$next[3:0]$11620 4'0000 case - assign $6\src36__data_o$next[3:0]$11917 $1\src36__data_o$next[3:0]$11912 + assign $6\src36__data_o$next[3:0]$11620 $1\src36__data_o$next[3:0]$11615 end sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$11911 + update \src36__data_o$next $0\src36__data_o$next[3:0]$11614 end - attribute \src "libresoc.v:186661.3-186690.6" - process $proc$libresoc.v:186661$11918 + attribute \src "libresoc.v:180856.3-180885.6" + process $proc$libresoc.v:180856$11621 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11919 $1\wr_detect$7[0:0]$11920 - attribute \src "libresoc.v:186662.5-186662.29" + assign $0\wr_detect$7[0:0]$11622 $1\wr_detect$7[0:0]$11623 + attribute \src "libresoc.v:180857.5-180857.29" switch \initial - attribute \src "libresoc.v:186662.9-186662.17" + attribute \src "libresoc.v:180857.9-180857.17" case 1'1 case end @@ -383057,49 +373602,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11920 $4\wr_detect$7[0:0]$11923 + assign $1\wr_detect$7[0:0]$11623 $4\wr_detect$7[0:0]$11626 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11921 1'1 + assign $2\wr_detect$7[0:0]$11624 1'1 case - assign $2\wr_detect$7[0:0]$11921 1'0 + assign $2\wr_detect$7[0:0]$11624 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11922 1'1 + assign $3\wr_detect$7[0:0]$11625 1'1 case - assign $3\wr_detect$7[0:0]$11922 $2\wr_detect$7[0:0]$11921 + assign $3\wr_detect$7[0:0]$11625 $2\wr_detect$7[0:0]$11624 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11923 1'1 + assign $4\wr_detect$7[0:0]$11626 1'1 case - assign $4\wr_detect$7[0:0]$11923 $3\wr_detect$7[0:0]$11922 + assign $4\wr_detect$7[0:0]$11626 $3\wr_detect$7[0:0]$11625 end case - assign $1\wr_detect$7[0:0]$11920 1'0 + assign $1\wr_detect$7[0:0]$11623 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11919 + update \wr_detect$7 $0\wr_detect$7[0:0]$11622 end - attribute \src "libresoc.v:186691.3-186730.6" - process $proc$libresoc.v:186691$11924 + attribute \src "libresoc.v:180886.3-180925.6" + process $proc$libresoc.v:180886$11627 assign { } { } assign { } { } assign { } { } - assign $0\r6__data_o$next[3:0]$11925 $6\r6__data_o$next[3:0]$11931 - attribute \src "libresoc.v:186692.5-186692.29" + assign $0\r6__data_o$next[3:0]$11628 $6\r6__data_o$next[3:0]$11634 + attribute \src "libresoc.v:180887.5-180887.29" switch \initial - attribute \src "libresoc.v:186692.9-186692.17" + attribute \src "libresoc.v:180887.9-180887.17" case 1'1 case end @@ -383111,66 +373656,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r6__data_o$next[3:0]$11926 $5\r6__data_o$next[3:0]$11930 + assign $1\r6__data_o$next[3:0]$11629 $5\r6__data_o$next[3:0]$11633 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r6__data_o$next[3:0]$11927 \dest16__data_i + assign $2\r6__data_o$next[3:0]$11630 \dest16__data_i case - assign $2\r6__data_o$next[3:0]$11927 4'0000 + assign $2\r6__data_o$next[3:0]$11630 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r6__data_o$next[3:0]$11928 \dest26__data_i + assign $3\r6__data_o$next[3:0]$11631 \dest26__data_i case - assign $3\r6__data_o$next[3:0]$11928 $2\r6__data_o$next[3:0]$11927 + assign $3\r6__data_o$next[3:0]$11631 $2\r6__data_o$next[3:0]$11630 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r6__data_o$next[3:0]$11929 \w6__data_i + assign $4\r6__data_o$next[3:0]$11632 \w6__data_i case - assign $4\r6__data_o$next[3:0]$11929 $3\r6__data_o$next[3:0]$11928 + assign $4\r6__data_o$next[3:0]$11632 $3\r6__data_o$next[3:0]$11631 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r6__data_o$next[3:0]$11930 \reg + assign $5\r6__data_o$next[3:0]$11633 \reg case - assign $5\r6__data_o$next[3:0]$11930 $4\r6__data_o$next[3:0]$11929 + assign $5\r6__data_o$next[3:0]$11633 $4\r6__data_o$next[3:0]$11632 end case - assign $1\r6__data_o$next[3:0]$11926 4'0000 + assign $1\r6__data_o$next[3:0]$11629 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r6__data_o$next[3:0]$11931 4'0000 + assign $6\r6__data_o$next[3:0]$11634 4'0000 case - assign $6\r6__data_o$next[3:0]$11931 $1\r6__data_o$next[3:0]$11926 + assign $6\r6__data_o$next[3:0]$11634 $1\r6__data_o$next[3:0]$11629 end sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$11925 + update \r6__data_o$next $0\r6__data_o$next[3:0]$11628 end - attribute \src "libresoc.v:186731.3-186760.6" - process $proc$libresoc.v:186731$11932 + attribute \src "libresoc.v:180926.3-180955.6" + process $proc$libresoc.v:180926$11635 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11933 $1\wr_detect$10[0:0]$11934 - attribute \src "libresoc.v:186732.5-186732.29" + assign $0\wr_detect$10[0:0]$11636 $1\wr_detect$10[0:0]$11637 + attribute \src "libresoc.v:180927.5-180927.29" switch \initial - attribute \src "libresoc.v:186732.9-186732.17" + attribute \src "libresoc.v:180927.9-180927.17" case 1'1 case end @@ -383182,49 +373727,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11934 $4\wr_detect$10[0:0]$11937 + assign $1\wr_detect$10[0:0]$11637 $4\wr_detect$10[0:0]$11640 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11935 1'1 + assign $2\wr_detect$10[0:0]$11638 1'1 case - assign $2\wr_detect$10[0:0]$11935 1'0 + assign $2\wr_detect$10[0:0]$11638 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11936 1'1 + assign $3\wr_detect$10[0:0]$11639 1'1 case - assign $3\wr_detect$10[0:0]$11936 $2\wr_detect$10[0:0]$11935 + assign $3\wr_detect$10[0:0]$11639 $2\wr_detect$10[0:0]$11638 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11937 1'1 + assign $4\wr_detect$10[0:0]$11640 1'1 case - assign $4\wr_detect$10[0:0]$11937 $3\wr_detect$10[0:0]$11936 + assign $4\wr_detect$10[0:0]$11640 $3\wr_detect$10[0:0]$11639 end case - assign $1\wr_detect$10[0:0]$11934 1'0 + assign $1\wr_detect$10[0:0]$11637 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11933 + update \wr_detect$10 $0\wr_detect$10[0:0]$11636 end - attribute \src "libresoc.v:186761.3-186800.6" - process $proc$libresoc.v:186761$11938 + attribute \src "libresoc.v:180956.3-180995.6" + process $proc$libresoc.v:180956$11641 assign { } { } assign { } { } assign { } { } - assign $0\r26__data_o$next[3:0]$11939 $6\r26__data_o$next[3:0]$11945 - attribute \src "libresoc.v:186762.5-186762.29" + assign $0\r26__data_o$next[3:0]$11642 $6\r26__data_o$next[3:0]$11648 + attribute \src "libresoc.v:180957.5-180957.29" switch \initial - attribute \src "libresoc.v:186762.9-186762.17" + attribute \src "libresoc.v:180957.9-180957.17" case 1'1 case end @@ -383236,66 +373781,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r26__data_o$next[3:0]$11940 $5\r26__data_o$next[3:0]$11944 + assign $1\r26__data_o$next[3:0]$11643 $5\r26__data_o$next[3:0]$11647 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r26__data_o$next[3:0]$11941 \dest16__data_i + assign $2\r26__data_o$next[3:0]$11644 \dest16__data_i case - assign $2\r26__data_o$next[3:0]$11941 4'0000 + assign $2\r26__data_o$next[3:0]$11644 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r26__data_o$next[3:0]$11942 \dest26__data_i + assign $3\r26__data_o$next[3:0]$11645 \dest26__data_i case - assign $3\r26__data_o$next[3:0]$11942 $2\r26__data_o$next[3:0]$11941 + assign $3\r26__data_o$next[3:0]$11645 $2\r26__data_o$next[3:0]$11644 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r26__data_o$next[3:0]$11943 \w6__data_i + assign $4\r26__data_o$next[3:0]$11646 \w6__data_i case - assign $4\r26__data_o$next[3:0]$11943 $3\r26__data_o$next[3:0]$11942 + assign $4\r26__data_o$next[3:0]$11646 $3\r26__data_o$next[3:0]$11645 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r26__data_o$next[3:0]$11944 \reg + assign $5\r26__data_o$next[3:0]$11647 \reg case - assign $5\r26__data_o$next[3:0]$11944 $4\r26__data_o$next[3:0]$11943 + assign $5\r26__data_o$next[3:0]$11647 $4\r26__data_o$next[3:0]$11646 end case - assign $1\r26__data_o$next[3:0]$11940 4'0000 + assign $1\r26__data_o$next[3:0]$11643 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r26__data_o$next[3:0]$11945 4'0000 + assign $6\r26__data_o$next[3:0]$11648 4'0000 case - assign $6\r26__data_o$next[3:0]$11945 $1\r26__data_o$next[3:0]$11940 + assign $6\r26__data_o$next[3:0]$11648 $1\r26__data_o$next[3:0]$11643 end sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$11939 + update \r26__data_o$next $0\r26__data_o$next[3:0]$11642 end - attribute \src "libresoc.v:186801.3-186830.6" - process $proc$libresoc.v:186801$11946 + attribute \src "libresoc.v:180996.3-181025.6" + process $proc$libresoc.v:180996$11649 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11947 $1\wr_detect$13[0:0]$11948 - attribute \src "libresoc.v:186802.5-186802.29" + assign $0\wr_detect$13[0:0]$11650 $1\wr_detect$13[0:0]$11651 + attribute \src "libresoc.v:180997.5-180997.29" switch \initial - attribute \src "libresoc.v:186802.9-186802.17" + attribute \src "libresoc.v:180997.9-180997.17" case 1'1 case end @@ -383307,217 +373852,217 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11948 $4\wr_detect$13[0:0]$11951 + assign $1\wr_detect$13[0:0]$11651 $4\wr_detect$13[0:0]$11654 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11949 1'1 + assign $2\wr_detect$13[0:0]$11652 1'1 case - assign $2\wr_detect$13[0:0]$11949 1'0 + assign $2\wr_detect$13[0:0]$11652 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11950 1'1 + assign $3\wr_detect$13[0:0]$11653 1'1 case - assign $3\wr_detect$13[0:0]$11950 $2\wr_detect$13[0:0]$11949 + assign $3\wr_detect$13[0:0]$11653 $2\wr_detect$13[0:0]$11652 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11951 1'1 + assign $4\wr_detect$13[0:0]$11654 1'1 case - assign $4\wr_detect$13[0:0]$11951 $3\wr_detect$13[0:0]$11950 + assign $4\wr_detect$13[0:0]$11654 $3\wr_detect$13[0:0]$11653 end case - assign $1\wr_detect$13[0:0]$11948 1'0 + assign $1\wr_detect$13[0:0]$11651 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11947 + update \wr_detect$13 $0\wr_detect$13[0:0]$11650 end - connect \$9 $not$libresoc.v:186437$11870_Y - connect \$12 $not$libresoc.v:186438$11871_Y - connect \$1 $not$libresoc.v:186439$11872_Y - connect \$3 $not$libresoc.v:186440$11873_Y - connect \$6 $not$libresoc.v:186441$11874_Y + connect \$9 $not$libresoc.v:180632$11573_Y + connect \$12 $not$libresoc.v:180633$11574_Y + connect \$1 $not$libresoc.v:180634$11575_Y + connect \$3 $not$libresoc.v:180635$11576_Y + connect \$6 $not$libresoc.v:180636$11577_Y end -attribute \src "libresoc.v:186835.1-187306.10" +attribute \src "libresoc.v:181030.1-181501.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 - attribute \src "libresoc.v:186836.7-186836.20" + attribute \src "libresoc.v:181031.7-181031.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187236.3-187275.6" - wire width 4 $0\r27__data_o$next[3:0]$12028 - attribute \src "libresoc.v:186919.3-186920.39" + attribute \src "libresoc.v:181431.3-181470.6" + wire width 4 $0\r27__data_o$next[3:0]$11731 + attribute \src "libresoc.v:181114.3-181115.39" wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:187166.3-187205.6" - wire width 4 $0\r7__data_o$next[3:0]$12014 - attribute \src "libresoc.v:186921.3-186922.37" + attribute \src "libresoc.v:181361.3-181400.6" + wire width 4 $0\r7__data_o$next[3:0]$11717 + attribute \src "libresoc.v:181116.3-181117.37" wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:186999.3-187025.6" - wire width 4 $0\reg$next[3:0]$11980 - attribute \src "libresoc.v:186917.3-186918.25" + attribute \src "libresoc.v:181194.3-181220.6" + wire width 4 $0\reg$next[3:0]$11683 + attribute \src "libresoc.v:181112.3-181113.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:186929.3-186968.6" - wire width 4 $0\src17__data_o$next[3:0]$11971 - attribute \src "libresoc.v:186927.3-186928.43" + attribute \src "libresoc.v:181124.3-181163.6" + wire width 4 $0\src17__data_o$next[3:0]$11674 + attribute \src "libresoc.v:181122.3-181123.43" wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:187026.3-187065.6" - wire width 4 $0\src27__data_o$next[3:0]$11986 - attribute \src "libresoc.v:186925.3-186926.43" + attribute \src "libresoc.v:181221.3-181260.6" + wire width 4 $0\src27__data_o$next[3:0]$11689 + attribute \src "libresoc.v:181120.3-181121.43" wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:187096.3-187135.6" - wire width 4 $0\src37__data_o$next[3:0]$12000 - attribute \src "libresoc.v:186923.3-186924.43" + attribute \src "libresoc.v:181291.3-181330.6" + wire width 4 $0\src37__data_o$next[3:0]$11703 + attribute \src "libresoc.v:181118.3-181119.43" wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:187206.3-187235.6" - wire $0\wr_detect$10[0:0]$12022 - attribute \src "libresoc.v:187276.3-187305.6" - wire $0\wr_detect$13[0:0]$12036 - attribute \src "libresoc.v:187066.3-187095.6" - wire $0\wr_detect$4[0:0]$11994 - attribute \src "libresoc.v:187136.3-187165.6" - wire $0\wr_detect$7[0:0]$12008 - attribute \src "libresoc.v:186969.3-186998.6" + attribute \src "libresoc.v:181401.3-181430.6" + wire $0\wr_detect$10[0:0]$11725 + attribute \src "libresoc.v:181471.3-181500.6" + wire $0\wr_detect$13[0:0]$11739 + attribute \src "libresoc.v:181261.3-181290.6" + wire $0\wr_detect$4[0:0]$11697 + attribute \src "libresoc.v:181331.3-181360.6" + wire $0\wr_detect$7[0:0]$11711 + attribute \src "libresoc.v:181164.3-181193.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:187236.3-187275.6" - wire width 4 $1\r27__data_o$next[3:0]$12029 - attribute \src "libresoc.v:186861.13-186861.31" + attribute \src "libresoc.v:181431.3-181470.6" + wire width 4 $1\r27__data_o$next[3:0]$11732 + attribute \src "libresoc.v:181056.13-181056.31" wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:187166.3-187205.6" - wire width 4 $1\r7__data_o$next[3:0]$12015 - attribute \src "libresoc.v:186868.13-186868.30" + attribute \src "libresoc.v:181361.3-181400.6" + wire width 4 $1\r7__data_o$next[3:0]$11718 + attribute \src "libresoc.v:181063.13-181063.30" wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:186999.3-187025.6" - wire width 4 $1\reg$next[3:0]$11981 - attribute \src "libresoc.v:186874.13-186874.25" + attribute \src "libresoc.v:181194.3-181220.6" + wire width 4 $1\reg$next[3:0]$11684 + attribute \src "libresoc.v:181069.13-181069.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:186929.3-186968.6" - wire width 4 $1\src17__data_o$next[3:0]$11972 - attribute \src "libresoc.v:186879.13-186879.33" + attribute \src "libresoc.v:181124.3-181163.6" + wire width 4 $1\src17__data_o$next[3:0]$11675 + attribute \src "libresoc.v:181074.13-181074.33" wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:187026.3-187065.6" - wire width 4 $1\src27__data_o$next[3:0]$11987 - attribute \src "libresoc.v:186886.13-186886.33" + attribute \src "libresoc.v:181221.3-181260.6" + wire width 4 $1\src27__data_o$next[3:0]$11690 + attribute \src "libresoc.v:181081.13-181081.33" wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:187096.3-187135.6" - wire width 4 $1\src37__data_o$next[3:0]$12001 - attribute \src "libresoc.v:186893.13-186893.33" + attribute \src "libresoc.v:181291.3-181330.6" + wire width 4 $1\src37__data_o$next[3:0]$11704 + attribute \src "libresoc.v:181088.13-181088.33" wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:187206.3-187235.6" - wire $1\wr_detect$10[0:0]$12023 - attribute \src "libresoc.v:187276.3-187305.6" - wire $1\wr_detect$13[0:0]$12037 - attribute \src "libresoc.v:187066.3-187095.6" - wire $1\wr_detect$4[0:0]$11995 - attribute \src "libresoc.v:187136.3-187165.6" - wire $1\wr_detect$7[0:0]$12009 - attribute \src "libresoc.v:186969.3-186998.6" + attribute \src "libresoc.v:181401.3-181430.6" + wire $1\wr_detect$10[0:0]$11726 + attribute \src "libresoc.v:181471.3-181500.6" + wire $1\wr_detect$13[0:0]$11740 + attribute \src "libresoc.v:181261.3-181290.6" + wire $1\wr_detect$4[0:0]$11698 + attribute \src "libresoc.v:181331.3-181360.6" + wire $1\wr_detect$7[0:0]$11712 + attribute \src "libresoc.v:181164.3-181193.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:187236.3-187275.6" - wire width 4 $2\r27__data_o$next[3:0]$12030 - attribute \src "libresoc.v:187166.3-187205.6" - wire width 4 $2\r7__data_o$next[3:0]$12016 - attribute \src "libresoc.v:186999.3-187025.6" - wire width 4 $2\reg$next[3:0]$11982 - attribute \src "libresoc.v:186929.3-186968.6" - wire width 4 $2\src17__data_o$next[3:0]$11973 - attribute \src "libresoc.v:187026.3-187065.6" - wire width 4 $2\src27__data_o$next[3:0]$11988 - attribute \src "libresoc.v:187096.3-187135.6" - wire width 4 $2\src37__data_o$next[3:0]$12002 - attribute \src "libresoc.v:187206.3-187235.6" - wire $2\wr_detect$10[0:0]$12024 - attribute \src "libresoc.v:187276.3-187305.6" - wire $2\wr_detect$13[0:0]$12038 - attribute \src "libresoc.v:187066.3-187095.6" - wire $2\wr_detect$4[0:0]$11996 - attribute \src "libresoc.v:187136.3-187165.6" - wire $2\wr_detect$7[0:0]$12010 - attribute \src "libresoc.v:186969.3-186998.6" + attribute \src "libresoc.v:181431.3-181470.6" + wire width 4 $2\r27__data_o$next[3:0]$11733 + attribute \src "libresoc.v:181361.3-181400.6" + wire width 4 $2\r7__data_o$next[3:0]$11719 + attribute \src "libresoc.v:181194.3-181220.6" + wire width 4 $2\reg$next[3:0]$11685 + attribute \src "libresoc.v:181124.3-181163.6" + wire width 4 $2\src17__data_o$next[3:0]$11676 + attribute \src "libresoc.v:181221.3-181260.6" + wire width 4 $2\src27__data_o$next[3:0]$11691 + attribute \src "libresoc.v:181291.3-181330.6" + wire width 4 $2\src37__data_o$next[3:0]$11705 + attribute \src "libresoc.v:181401.3-181430.6" + wire $2\wr_detect$10[0:0]$11727 + attribute \src "libresoc.v:181471.3-181500.6" + wire $2\wr_detect$13[0:0]$11741 + attribute \src "libresoc.v:181261.3-181290.6" + wire $2\wr_detect$4[0:0]$11699 + attribute \src "libresoc.v:181331.3-181360.6" + wire $2\wr_detect$7[0:0]$11713 + attribute \src "libresoc.v:181164.3-181193.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:187236.3-187275.6" - wire width 4 $3\r27__data_o$next[3:0]$12031 - attribute \src "libresoc.v:187166.3-187205.6" - wire width 4 $3\r7__data_o$next[3:0]$12017 - attribute \src "libresoc.v:186999.3-187025.6" - wire width 4 $3\reg$next[3:0]$11983 - attribute \src "libresoc.v:186929.3-186968.6" - wire width 4 $3\src17__data_o$next[3:0]$11974 - attribute \src "libresoc.v:187026.3-187065.6" - wire width 4 $3\src27__data_o$next[3:0]$11989 - attribute \src "libresoc.v:187096.3-187135.6" - wire width 4 $3\src37__data_o$next[3:0]$12003 - attribute \src "libresoc.v:187206.3-187235.6" - wire $3\wr_detect$10[0:0]$12025 - attribute \src "libresoc.v:187276.3-187305.6" - wire $3\wr_detect$13[0:0]$12039 - attribute \src "libresoc.v:187066.3-187095.6" - wire $3\wr_detect$4[0:0]$11997 - attribute \src "libresoc.v:187136.3-187165.6" - wire $3\wr_detect$7[0:0]$12011 - attribute \src "libresoc.v:186969.3-186998.6" + attribute \src "libresoc.v:181431.3-181470.6" + wire width 4 $3\r27__data_o$next[3:0]$11734 + attribute \src "libresoc.v:181361.3-181400.6" + wire width 4 $3\r7__data_o$next[3:0]$11720 + attribute \src "libresoc.v:181194.3-181220.6" + wire width 4 $3\reg$next[3:0]$11686 + attribute \src "libresoc.v:181124.3-181163.6" + wire width 4 $3\src17__data_o$next[3:0]$11677 + attribute \src "libresoc.v:181221.3-181260.6" + wire width 4 $3\src27__data_o$next[3:0]$11692 + attribute \src "libresoc.v:181291.3-181330.6" + wire width 4 $3\src37__data_o$next[3:0]$11706 + attribute \src "libresoc.v:181401.3-181430.6" + wire $3\wr_detect$10[0:0]$11728 + attribute \src "libresoc.v:181471.3-181500.6" + wire $3\wr_detect$13[0:0]$11742 + attribute \src "libresoc.v:181261.3-181290.6" + wire $3\wr_detect$4[0:0]$11700 + attribute \src "libresoc.v:181331.3-181360.6" + wire $3\wr_detect$7[0:0]$11714 + attribute \src "libresoc.v:181164.3-181193.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:187236.3-187275.6" - wire width 4 $4\r27__data_o$next[3:0]$12032 - attribute \src "libresoc.v:187166.3-187205.6" - wire width 4 $4\r7__data_o$next[3:0]$12018 - attribute \src "libresoc.v:186999.3-187025.6" - wire width 4 $4\reg$next[3:0]$11984 - attribute \src "libresoc.v:186929.3-186968.6" - wire width 4 $4\src17__data_o$next[3:0]$11975 - attribute \src "libresoc.v:187026.3-187065.6" - wire width 4 $4\src27__data_o$next[3:0]$11990 - attribute \src "libresoc.v:187096.3-187135.6" - wire width 4 $4\src37__data_o$next[3:0]$12004 - attribute \src "libresoc.v:187206.3-187235.6" - wire $4\wr_detect$10[0:0]$12026 - attribute \src "libresoc.v:187276.3-187305.6" - wire $4\wr_detect$13[0:0]$12040 - attribute \src "libresoc.v:187066.3-187095.6" - wire $4\wr_detect$4[0:0]$11998 - attribute \src "libresoc.v:187136.3-187165.6" - wire $4\wr_detect$7[0:0]$12012 - attribute \src "libresoc.v:186969.3-186998.6" + attribute \src "libresoc.v:181431.3-181470.6" + wire width 4 $4\r27__data_o$next[3:0]$11735 + attribute \src "libresoc.v:181361.3-181400.6" + wire width 4 $4\r7__data_o$next[3:0]$11721 + attribute \src "libresoc.v:181194.3-181220.6" + wire width 4 $4\reg$next[3:0]$11687 + attribute \src "libresoc.v:181124.3-181163.6" + wire width 4 $4\src17__data_o$next[3:0]$11678 + attribute \src "libresoc.v:181221.3-181260.6" + wire width 4 $4\src27__data_o$next[3:0]$11693 + attribute \src "libresoc.v:181291.3-181330.6" + wire width 4 $4\src37__data_o$next[3:0]$11707 + attribute \src "libresoc.v:181401.3-181430.6" + wire $4\wr_detect$10[0:0]$11729 + attribute \src "libresoc.v:181471.3-181500.6" + wire $4\wr_detect$13[0:0]$11743 + attribute \src "libresoc.v:181261.3-181290.6" + wire $4\wr_detect$4[0:0]$11701 + attribute \src "libresoc.v:181331.3-181360.6" + wire $4\wr_detect$7[0:0]$11715 + attribute \src "libresoc.v:181164.3-181193.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:187236.3-187275.6" - wire width 4 $5\r27__data_o$next[3:0]$12033 - attribute \src "libresoc.v:187166.3-187205.6" - wire width 4 $5\r7__data_o$next[3:0]$12019 - attribute \src "libresoc.v:186929.3-186968.6" - wire width 4 $5\src17__data_o$next[3:0]$11976 - attribute \src "libresoc.v:187026.3-187065.6" - wire width 4 $5\src27__data_o$next[3:0]$11991 - attribute \src "libresoc.v:187096.3-187135.6" - wire width 4 $5\src37__data_o$next[3:0]$12005 - attribute \src "libresoc.v:187236.3-187275.6" - wire width 4 $6\r27__data_o$next[3:0]$12034 - attribute \src "libresoc.v:187166.3-187205.6" - wire width 4 $6\r7__data_o$next[3:0]$12020 - attribute \src "libresoc.v:186929.3-186968.6" - wire width 4 $6\src17__data_o$next[3:0]$11977 - attribute \src "libresoc.v:187026.3-187065.6" - wire width 4 $6\src27__data_o$next[3:0]$11992 - attribute \src "libresoc.v:187096.3-187135.6" - wire width 4 $6\src37__data_o$next[3:0]$12006 - attribute \src "libresoc.v:186912.17-186912.104" - wire $not$libresoc.v:186912$11959_Y - attribute \src "libresoc.v:186913.18-186913.105" - wire $not$libresoc.v:186913$11960_Y - attribute \src "libresoc.v:186914.17-186914.100" - wire $not$libresoc.v:186914$11961_Y - attribute \src "libresoc.v:186915.17-186915.103" - wire $not$libresoc.v:186915$11962_Y - attribute \src "libresoc.v:186916.17-186916.103" - wire $not$libresoc.v:186916$11963_Y + attribute \src "libresoc.v:181431.3-181470.6" + wire width 4 $5\r27__data_o$next[3:0]$11736 + attribute \src "libresoc.v:181361.3-181400.6" + wire width 4 $5\r7__data_o$next[3:0]$11722 + attribute \src "libresoc.v:181124.3-181163.6" + wire width 4 $5\src17__data_o$next[3:0]$11679 + attribute \src "libresoc.v:181221.3-181260.6" + wire width 4 $5\src27__data_o$next[3:0]$11694 + attribute \src "libresoc.v:181291.3-181330.6" + wire width 4 $5\src37__data_o$next[3:0]$11708 + attribute \src "libresoc.v:181431.3-181470.6" + wire width 4 $6\r27__data_o$next[3:0]$11737 + attribute \src "libresoc.v:181361.3-181400.6" + wire width 4 $6\r7__data_o$next[3:0]$11723 + attribute \src "libresoc.v:181124.3-181163.6" + wire width 4 $6\src17__data_o$next[3:0]$11680 + attribute \src "libresoc.v:181221.3-181260.6" + wire width 4 $6\src27__data_o$next[3:0]$11695 + attribute \src "libresoc.v:181291.3-181330.6" + wire width 4 $6\src37__data_o$next[3:0]$11709 + attribute \src "libresoc.v:181107.17-181107.104" + wire $not$libresoc.v:181107$11662_Y + attribute \src "libresoc.v:181108.18-181108.105" + wire $not$libresoc.v:181108$11663_Y + attribute \src "libresoc.v:181109.17-181109.100" + wire $not$libresoc.v:181109$11664_Y + attribute \src "libresoc.v:181110.17-181110.103" + wire $not$libresoc.v:181110$11665_Y + attribute \src "libresoc.v:181111.17-181111.103" + wire $not$libresoc.v:181111$11666_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -383528,9 +374073,9 @@ module \reg_7 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 input 9 \dest17__data_i @@ -383540,7 +374085,7 @@ module \reg_7 wire width 4 input 11 \dest27__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 10 \dest27__wen - attribute \src "libresoc.v:186836.7-186836.15" + attribute \src "libresoc.v:181031.7-181031.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r27__data_o @@ -383591,152 +374136,152 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:186912$11959 + cell $not $not$libresoc.v:181107$11662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:186912$11959_Y + connect \Y $not$libresoc.v:181107$11662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:186913$11960 + cell $not $not$libresoc.v:181108$11663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:186913$11960_Y + connect \Y $not$libresoc.v:181108$11663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:186914$11961 + cell $not $not$libresoc.v:181109$11664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:186914$11961_Y + connect \Y $not$libresoc.v:181109$11664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:186915$11962 + cell $not $not$libresoc.v:181110$11665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:186915$11962_Y + connect \Y $not$libresoc.v:181110$11665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:186916$11963 + cell $not $not$libresoc.v:181111$11666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:186916$11963_Y + connect \Y $not$libresoc.v:181111$11666_Y end - attribute \src "libresoc.v:186836.7-186836.20" - process $proc$libresoc.v:186836$12041 + attribute \src "libresoc.v:181031.7-181031.20" + process $proc$libresoc.v:181031$11744 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186861.13-186861.31" - process $proc$libresoc.v:186861$12042 + attribute \src "libresoc.v:181056.13-181056.31" + process $proc$libresoc.v:181056$11745 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end - attribute \src "libresoc.v:186868.13-186868.30" - process $proc$libresoc.v:186868$12043 + attribute \src "libresoc.v:181063.13-181063.30" + process $proc$libresoc.v:181063$11746 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end - attribute \src "libresoc.v:186874.13-186874.25" - process $proc$libresoc.v:186874$12044 + attribute \src "libresoc.v:181069.13-181069.25" + process $proc$libresoc.v:181069$11747 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:186879.13-186879.33" - process $proc$libresoc.v:186879$12045 + attribute \src "libresoc.v:181074.13-181074.33" + process $proc$libresoc.v:181074$11748 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end - attribute \src "libresoc.v:186886.13-186886.33" - process $proc$libresoc.v:186886$12046 + attribute \src "libresoc.v:181081.13-181081.33" + process $proc$libresoc.v:181081$11749 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end - attribute \src "libresoc.v:186893.13-186893.33" - process $proc$libresoc.v:186893$12047 + attribute \src "libresoc.v:181088.13-181088.33" + process $proc$libresoc.v:181088$11750 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end - attribute \src "libresoc.v:186917.3-186918.25" - process $proc$libresoc.v:186917$11964 + attribute \src "libresoc.v:181112.3-181113.25" + process $proc$libresoc.v:181112$11667 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:186919.3-186920.39" - process $proc$libresoc.v:186919$11965 + attribute \src "libresoc.v:181114.3-181115.39" + process $proc$libresoc.v:181114$11668 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end - attribute \src "libresoc.v:186921.3-186922.37" - process $proc$libresoc.v:186921$11966 + attribute \src "libresoc.v:181116.3-181117.37" + process $proc$libresoc.v:181116$11669 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end - attribute \src "libresoc.v:186923.3-186924.43" - process $proc$libresoc.v:186923$11967 + attribute \src "libresoc.v:181118.3-181119.43" + process $proc$libresoc.v:181118$11670 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end - attribute \src "libresoc.v:186925.3-186926.43" - process $proc$libresoc.v:186925$11968 + attribute \src "libresoc.v:181120.3-181121.43" + process $proc$libresoc.v:181120$11671 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end - attribute \src "libresoc.v:186927.3-186928.43" - process $proc$libresoc.v:186927$11969 + attribute \src "libresoc.v:181122.3-181123.43" + process $proc$libresoc.v:181122$11672 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end - attribute \src "libresoc.v:186929.3-186968.6" - process $proc$libresoc.v:186929$11970 + attribute \src "libresoc.v:181124.3-181163.6" + process $proc$libresoc.v:181124$11673 assign { } { } assign { } { } assign { } { } - assign $0\src17__data_o$next[3:0]$11971 $6\src17__data_o$next[3:0]$11977 - attribute \src "libresoc.v:186930.5-186930.29" + assign $0\src17__data_o$next[3:0]$11674 $6\src17__data_o$next[3:0]$11680 + attribute \src "libresoc.v:181125.5-181125.29" switch \initial - attribute \src "libresoc.v:186930.9-186930.17" + attribute \src "libresoc.v:181125.9-181125.17" case 1'1 case end @@ -383748,66 +374293,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src17__data_o$next[3:0]$11972 $5\src17__data_o$next[3:0]$11976 + assign $1\src17__data_o$next[3:0]$11675 $5\src17__data_o$next[3:0]$11679 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src17__data_o$next[3:0]$11973 \dest17__data_i + assign $2\src17__data_o$next[3:0]$11676 \dest17__data_i case - assign $2\src17__data_o$next[3:0]$11973 4'0000 + assign $2\src17__data_o$next[3:0]$11676 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src17__data_o$next[3:0]$11974 \dest27__data_i + assign $3\src17__data_o$next[3:0]$11677 \dest27__data_i case - assign $3\src17__data_o$next[3:0]$11974 $2\src17__data_o$next[3:0]$11973 + assign $3\src17__data_o$next[3:0]$11677 $2\src17__data_o$next[3:0]$11676 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src17__data_o$next[3:0]$11975 \w7__data_i + assign $4\src17__data_o$next[3:0]$11678 \w7__data_i case - assign $4\src17__data_o$next[3:0]$11975 $3\src17__data_o$next[3:0]$11974 + assign $4\src17__data_o$next[3:0]$11678 $3\src17__data_o$next[3:0]$11677 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src17__data_o$next[3:0]$11976 \reg + assign $5\src17__data_o$next[3:0]$11679 \reg case - assign $5\src17__data_o$next[3:0]$11976 $4\src17__data_o$next[3:0]$11975 + assign $5\src17__data_o$next[3:0]$11679 $4\src17__data_o$next[3:0]$11678 end case - assign $1\src17__data_o$next[3:0]$11972 4'0000 + assign $1\src17__data_o$next[3:0]$11675 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src17__data_o$next[3:0]$11977 4'0000 + assign $6\src17__data_o$next[3:0]$11680 4'0000 case - assign $6\src17__data_o$next[3:0]$11977 $1\src17__data_o$next[3:0]$11972 + assign $6\src17__data_o$next[3:0]$11680 $1\src17__data_o$next[3:0]$11675 end sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$11971 + update \src17__data_o$next $0\src17__data_o$next[3:0]$11674 end - attribute \src "libresoc.v:186969.3-186998.6" - process $proc$libresoc.v:186969$11978 + attribute \src "libresoc.v:181164.3-181193.6" + process $proc$libresoc.v:181164$11681 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:186970.5-186970.29" + attribute \src "libresoc.v:181165.5-181165.29" switch \initial - attribute \src "libresoc.v:186970.9-186970.17" + attribute \src "libresoc.v:181165.9-181165.17" case 1'1 case end @@ -383853,17 +374398,17 @@ module \reg_7 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:186999.3-187025.6" - process $proc$libresoc.v:186999$11979 + attribute \src "libresoc.v:181194.3-181220.6" + process $proc$libresoc.v:181194$11682 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11980 $4\reg$next[3:0]$11984 - attribute \src "libresoc.v:187000.5-187000.29" + assign $0\reg$next[3:0]$11683 $4\reg$next[3:0]$11687 + attribute \src "libresoc.v:181195.5-181195.29" switch \initial - attribute \src "libresoc.v:187000.9-187000.17" + attribute \src "libresoc.v:181195.9-181195.17" case 1'1 case end @@ -383872,49 +374417,49 @@ module \reg_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11981 \dest17__data_i + assign $1\reg$next[3:0]$11684 \dest17__data_i case - assign $1\reg$next[3:0]$11981 \reg + assign $1\reg$next[3:0]$11684 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11982 \dest27__data_i + assign $2\reg$next[3:0]$11685 \dest27__data_i case - assign $2\reg$next[3:0]$11982 $1\reg$next[3:0]$11981 + assign $2\reg$next[3:0]$11685 $1\reg$next[3:0]$11684 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11983 \w7__data_i + assign $3\reg$next[3:0]$11686 \w7__data_i case - assign $3\reg$next[3:0]$11983 $2\reg$next[3:0]$11982 + assign $3\reg$next[3:0]$11686 $2\reg$next[3:0]$11685 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11984 4'0000 + assign $4\reg$next[3:0]$11687 4'0000 case - assign $4\reg$next[3:0]$11984 $3\reg$next[3:0]$11983 + assign $4\reg$next[3:0]$11687 $3\reg$next[3:0]$11686 end sync always - update \reg$next $0\reg$next[3:0]$11980 + update \reg$next $0\reg$next[3:0]$11683 end - attribute \src "libresoc.v:187026.3-187065.6" - process $proc$libresoc.v:187026$11985 + attribute \src "libresoc.v:181221.3-181260.6" + process $proc$libresoc.v:181221$11688 assign { } { } assign { } { } assign { } { } - assign $0\src27__data_o$next[3:0]$11986 $6\src27__data_o$next[3:0]$11992 - attribute \src "libresoc.v:187027.5-187027.29" + assign $0\src27__data_o$next[3:0]$11689 $6\src27__data_o$next[3:0]$11695 + attribute \src "libresoc.v:181222.5-181222.29" switch \initial - attribute \src "libresoc.v:187027.9-187027.17" + attribute \src "libresoc.v:181222.9-181222.17" case 1'1 case end @@ -383926,66 +374471,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src27__data_o$next[3:0]$11987 $5\src27__data_o$next[3:0]$11991 + assign $1\src27__data_o$next[3:0]$11690 $5\src27__data_o$next[3:0]$11694 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src27__data_o$next[3:0]$11988 \dest17__data_i + assign $2\src27__data_o$next[3:0]$11691 \dest17__data_i case - assign $2\src27__data_o$next[3:0]$11988 4'0000 + assign $2\src27__data_o$next[3:0]$11691 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src27__data_o$next[3:0]$11989 \dest27__data_i + assign $3\src27__data_o$next[3:0]$11692 \dest27__data_i case - assign $3\src27__data_o$next[3:0]$11989 $2\src27__data_o$next[3:0]$11988 + assign $3\src27__data_o$next[3:0]$11692 $2\src27__data_o$next[3:0]$11691 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src27__data_o$next[3:0]$11990 \w7__data_i + assign $4\src27__data_o$next[3:0]$11693 \w7__data_i case - assign $4\src27__data_o$next[3:0]$11990 $3\src27__data_o$next[3:0]$11989 + assign $4\src27__data_o$next[3:0]$11693 $3\src27__data_o$next[3:0]$11692 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src27__data_o$next[3:0]$11991 \reg + assign $5\src27__data_o$next[3:0]$11694 \reg case - assign $5\src27__data_o$next[3:0]$11991 $4\src27__data_o$next[3:0]$11990 + assign $5\src27__data_o$next[3:0]$11694 $4\src27__data_o$next[3:0]$11693 end case - assign $1\src27__data_o$next[3:0]$11987 4'0000 + assign $1\src27__data_o$next[3:0]$11690 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src27__data_o$next[3:0]$11992 4'0000 + assign $6\src27__data_o$next[3:0]$11695 4'0000 case - assign $6\src27__data_o$next[3:0]$11992 $1\src27__data_o$next[3:0]$11987 + assign $6\src27__data_o$next[3:0]$11695 $1\src27__data_o$next[3:0]$11690 end sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$11986 + update \src27__data_o$next $0\src27__data_o$next[3:0]$11689 end - attribute \src "libresoc.v:187066.3-187095.6" - process $proc$libresoc.v:187066$11993 + attribute \src "libresoc.v:181261.3-181290.6" + process $proc$libresoc.v:181261$11696 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11994 $1\wr_detect$4[0:0]$11995 - attribute \src "libresoc.v:187067.5-187067.29" + assign $0\wr_detect$4[0:0]$11697 $1\wr_detect$4[0:0]$11698 + attribute \src "libresoc.v:181262.5-181262.29" switch \initial - attribute \src "libresoc.v:187067.9-187067.17" + attribute \src "libresoc.v:181262.9-181262.17" case 1'1 case end @@ -383997,49 +374542,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11995 $4\wr_detect$4[0:0]$11998 + assign $1\wr_detect$4[0:0]$11698 $4\wr_detect$4[0:0]$11701 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11996 1'1 + assign $2\wr_detect$4[0:0]$11699 1'1 case - assign $2\wr_detect$4[0:0]$11996 1'0 + assign $2\wr_detect$4[0:0]$11699 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11997 1'1 + assign $3\wr_detect$4[0:0]$11700 1'1 case - assign $3\wr_detect$4[0:0]$11997 $2\wr_detect$4[0:0]$11996 + assign $3\wr_detect$4[0:0]$11700 $2\wr_detect$4[0:0]$11699 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11998 1'1 + assign $4\wr_detect$4[0:0]$11701 1'1 case - assign $4\wr_detect$4[0:0]$11998 $3\wr_detect$4[0:0]$11997 + assign $4\wr_detect$4[0:0]$11701 $3\wr_detect$4[0:0]$11700 end case - assign $1\wr_detect$4[0:0]$11995 1'0 + assign $1\wr_detect$4[0:0]$11698 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11994 + update \wr_detect$4 $0\wr_detect$4[0:0]$11697 end - attribute \src "libresoc.v:187096.3-187135.6" - process $proc$libresoc.v:187096$11999 + attribute \src "libresoc.v:181291.3-181330.6" + process $proc$libresoc.v:181291$11702 assign { } { } assign { } { } assign { } { } - assign $0\src37__data_o$next[3:0]$12000 $6\src37__data_o$next[3:0]$12006 - attribute \src "libresoc.v:187097.5-187097.29" + assign $0\src37__data_o$next[3:0]$11703 $6\src37__data_o$next[3:0]$11709 + attribute \src "libresoc.v:181292.5-181292.29" switch \initial - attribute \src "libresoc.v:187097.9-187097.17" + attribute \src "libresoc.v:181292.9-181292.17" case 1'1 case end @@ -384051,66 +374596,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src37__data_o$next[3:0]$12001 $5\src37__data_o$next[3:0]$12005 + assign $1\src37__data_o$next[3:0]$11704 $5\src37__data_o$next[3:0]$11708 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src37__data_o$next[3:0]$12002 \dest17__data_i + assign $2\src37__data_o$next[3:0]$11705 \dest17__data_i case - assign $2\src37__data_o$next[3:0]$12002 4'0000 + assign $2\src37__data_o$next[3:0]$11705 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src37__data_o$next[3:0]$12003 \dest27__data_i + assign $3\src37__data_o$next[3:0]$11706 \dest27__data_i case - assign $3\src37__data_o$next[3:0]$12003 $2\src37__data_o$next[3:0]$12002 + assign $3\src37__data_o$next[3:0]$11706 $2\src37__data_o$next[3:0]$11705 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src37__data_o$next[3:0]$12004 \w7__data_i + assign $4\src37__data_o$next[3:0]$11707 \w7__data_i case - assign $4\src37__data_o$next[3:0]$12004 $3\src37__data_o$next[3:0]$12003 + assign $4\src37__data_o$next[3:0]$11707 $3\src37__data_o$next[3:0]$11706 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src37__data_o$next[3:0]$12005 \reg + assign $5\src37__data_o$next[3:0]$11708 \reg case - assign $5\src37__data_o$next[3:0]$12005 $4\src37__data_o$next[3:0]$12004 + assign $5\src37__data_o$next[3:0]$11708 $4\src37__data_o$next[3:0]$11707 end case - assign $1\src37__data_o$next[3:0]$12001 4'0000 + assign $1\src37__data_o$next[3:0]$11704 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src37__data_o$next[3:0]$12006 4'0000 + assign $6\src37__data_o$next[3:0]$11709 4'0000 case - assign $6\src37__data_o$next[3:0]$12006 $1\src37__data_o$next[3:0]$12001 + assign $6\src37__data_o$next[3:0]$11709 $1\src37__data_o$next[3:0]$11704 end sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$12000 + update \src37__data_o$next $0\src37__data_o$next[3:0]$11703 end - attribute \src "libresoc.v:187136.3-187165.6" - process $proc$libresoc.v:187136$12007 + attribute \src "libresoc.v:181331.3-181360.6" + process $proc$libresoc.v:181331$11710 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$12008 $1\wr_detect$7[0:0]$12009 - attribute \src "libresoc.v:187137.5-187137.29" + assign $0\wr_detect$7[0:0]$11711 $1\wr_detect$7[0:0]$11712 + attribute \src "libresoc.v:181332.5-181332.29" switch \initial - attribute \src "libresoc.v:187137.9-187137.17" + attribute \src "libresoc.v:181332.9-181332.17" case 1'1 case end @@ -384122,49 +374667,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$12009 $4\wr_detect$7[0:0]$12012 + assign $1\wr_detect$7[0:0]$11712 $4\wr_detect$7[0:0]$11715 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$12010 1'1 + assign $2\wr_detect$7[0:0]$11713 1'1 case - assign $2\wr_detect$7[0:0]$12010 1'0 + assign $2\wr_detect$7[0:0]$11713 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$12011 1'1 + assign $3\wr_detect$7[0:0]$11714 1'1 case - assign $3\wr_detect$7[0:0]$12011 $2\wr_detect$7[0:0]$12010 + assign $3\wr_detect$7[0:0]$11714 $2\wr_detect$7[0:0]$11713 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$12012 1'1 + assign $4\wr_detect$7[0:0]$11715 1'1 case - assign $4\wr_detect$7[0:0]$12012 $3\wr_detect$7[0:0]$12011 + assign $4\wr_detect$7[0:0]$11715 $3\wr_detect$7[0:0]$11714 end case - assign $1\wr_detect$7[0:0]$12009 1'0 + assign $1\wr_detect$7[0:0]$11712 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$12008 + update \wr_detect$7 $0\wr_detect$7[0:0]$11711 end - attribute \src "libresoc.v:187166.3-187205.6" - process $proc$libresoc.v:187166$12013 + attribute \src "libresoc.v:181361.3-181400.6" + process $proc$libresoc.v:181361$11716 assign { } { } assign { } { } assign { } { } - assign $0\r7__data_o$next[3:0]$12014 $6\r7__data_o$next[3:0]$12020 - attribute \src "libresoc.v:187167.5-187167.29" + assign $0\r7__data_o$next[3:0]$11717 $6\r7__data_o$next[3:0]$11723 + attribute \src "libresoc.v:181362.5-181362.29" switch \initial - attribute \src "libresoc.v:187167.9-187167.17" + attribute \src "libresoc.v:181362.9-181362.17" case 1'1 case end @@ -384176,66 +374721,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r7__data_o$next[3:0]$12015 $5\r7__data_o$next[3:0]$12019 + assign $1\r7__data_o$next[3:0]$11718 $5\r7__data_o$next[3:0]$11722 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r7__data_o$next[3:0]$12016 \dest17__data_i + assign $2\r7__data_o$next[3:0]$11719 \dest17__data_i case - assign $2\r7__data_o$next[3:0]$12016 4'0000 + assign $2\r7__data_o$next[3:0]$11719 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r7__data_o$next[3:0]$12017 \dest27__data_i + assign $3\r7__data_o$next[3:0]$11720 \dest27__data_i case - assign $3\r7__data_o$next[3:0]$12017 $2\r7__data_o$next[3:0]$12016 + assign $3\r7__data_o$next[3:0]$11720 $2\r7__data_o$next[3:0]$11719 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r7__data_o$next[3:0]$12018 \w7__data_i + assign $4\r7__data_o$next[3:0]$11721 \w7__data_i case - assign $4\r7__data_o$next[3:0]$12018 $3\r7__data_o$next[3:0]$12017 + assign $4\r7__data_o$next[3:0]$11721 $3\r7__data_o$next[3:0]$11720 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r7__data_o$next[3:0]$12019 \reg + assign $5\r7__data_o$next[3:0]$11722 \reg case - assign $5\r7__data_o$next[3:0]$12019 $4\r7__data_o$next[3:0]$12018 + assign $5\r7__data_o$next[3:0]$11722 $4\r7__data_o$next[3:0]$11721 end case - assign $1\r7__data_o$next[3:0]$12015 4'0000 + assign $1\r7__data_o$next[3:0]$11718 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r7__data_o$next[3:0]$12020 4'0000 + assign $6\r7__data_o$next[3:0]$11723 4'0000 case - assign $6\r7__data_o$next[3:0]$12020 $1\r7__data_o$next[3:0]$12015 + assign $6\r7__data_o$next[3:0]$11723 $1\r7__data_o$next[3:0]$11718 end sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$12014 + update \r7__data_o$next $0\r7__data_o$next[3:0]$11717 end - attribute \src "libresoc.v:187206.3-187235.6" - process $proc$libresoc.v:187206$12021 + attribute \src "libresoc.v:181401.3-181430.6" + process $proc$libresoc.v:181401$11724 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$12022 $1\wr_detect$10[0:0]$12023 - attribute \src "libresoc.v:187207.5-187207.29" + assign $0\wr_detect$10[0:0]$11725 $1\wr_detect$10[0:0]$11726 + attribute \src "libresoc.v:181402.5-181402.29" switch \initial - attribute \src "libresoc.v:187207.9-187207.17" + attribute \src "libresoc.v:181402.9-181402.17" case 1'1 case end @@ -384247,49 +374792,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$12023 $4\wr_detect$10[0:0]$12026 + assign $1\wr_detect$10[0:0]$11726 $4\wr_detect$10[0:0]$11729 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$12024 1'1 + assign $2\wr_detect$10[0:0]$11727 1'1 case - assign $2\wr_detect$10[0:0]$12024 1'0 + assign $2\wr_detect$10[0:0]$11727 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$12025 1'1 + assign $3\wr_detect$10[0:0]$11728 1'1 case - assign $3\wr_detect$10[0:0]$12025 $2\wr_detect$10[0:0]$12024 + assign $3\wr_detect$10[0:0]$11728 $2\wr_detect$10[0:0]$11727 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$12026 1'1 + assign $4\wr_detect$10[0:0]$11729 1'1 case - assign $4\wr_detect$10[0:0]$12026 $3\wr_detect$10[0:0]$12025 + assign $4\wr_detect$10[0:0]$11729 $3\wr_detect$10[0:0]$11728 end case - assign $1\wr_detect$10[0:0]$12023 1'0 + assign $1\wr_detect$10[0:0]$11726 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$12022 + update \wr_detect$10 $0\wr_detect$10[0:0]$11725 end - attribute \src "libresoc.v:187236.3-187275.6" - process $proc$libresoc.v:187236$12027 + attribute \src "libresoc.v:181431.3-181470.6" + process $proc$libresoc.v:181431$11730 assign { } { } assign { } { } assign { } { } - assign $0\r27__data_o$next[3:0]$12028 $6\r27__data_o$next[3:0]$12034 - attribute \src "libresoc.v:187237.5-187237.29" + assign $0\r27__data_o$next[3:0]$11731 $6\r27__data_o$next[3:0]$11737 + attribute \src "libresoc.v:181432.5-181432.29" switch \initial - attribute \src "libresoc.v:187237.9-187237.17" + attribute \src "libresoc.v:181432.9-181432.17" case 1'1 case end @@ -384301,66 +374846,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r27__data_o$next[3:0]$12029 $5\r27__data_o$next[3:0]$12033 + assign $1\r27__data_o$next[3:0]$11732 $5\r27__data_o$next[3:0]$11736 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r27__data_o$next[3:0]$12030 \dest17__data_i + assign $2\r27__data_o$next[3:0]$11733 \dest17__data_i case - assign $2\r27__data_o$next[3:0]$12030 4'0000 + assign $2\r27__data_o$next[3:0]$11733 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r27__data_o$next[3:0]$12031 \dest27__data_i + assign $3\r27__data_o$next[3:0]$11734 \dest27__data_i case - assign $3\r27__data_o$next[3:0]$12031 $2\r27__data_o$next[3:0]$12030 + assign $3\r27__data_o$next[3:0]$11734 $2\r27__data_o$next[3:0]$11733 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r27__data_o$next[3:0]$12032 \w7__data_i + assign $4\r27__data_o$next[3:0]$11735 \w7__data_i case - assign $4\r27__data_o$next[3:0]$12032 $3\r27__data_o$next[3:0]$12031 + assign $4\r27__data_o$next[3:0]$11735 $3\r27__data_o$next[3:0]$11734 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r27__data_o$next[3:0]$12033 \reg + assign $5\r27__data_o$next[3:0]$11736 \reg case - assign $5\r27__data_o$next[3:0]$12033 $4\r27__data_o$next[3:0]$12032 + assign $5\r27__data_o$next[3:0]$11736 $4\r27__data_o$next[3:0]$11735 end case - assign $1\r27__data_o$next[3:0]$12029 4'0000 + assign $1\r27__data_o$next[3:0]$11732 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r27__data_o$next[3:0]$12034 4'0000 + assign $6\r27__data_o$next[3:0]$11737 4'0000 case - assign $6\r27__data_o$next[3:0]$12034 $1\r27__data_o$next[3:0]$12029 + assign $6\r27__data_o$next[3:0]$11737 $1\r27__data_o$next[3:0]$11732 end sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$12028 + update \r27__data_o$next $0\r27__data_o$next[3:0]$11731 end - attribute \src "libresoc.v:187276.3-187305.6" - process $proc$libresoc.v:187276$12035 + attribute \src "libresoc.v:181471.3-181500.6" + process $proc$libresoc.v:181471$11738 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$12036 $1\wr_detect$13[0:0]$12037 - attribute \src "libresoc.v:187277.5-187277.29" + assign $0\wr_detect$13[0:0]$11739 $1\wr_detect$13[0:0]$11740 + attribute \src "libresoc.v:181472.5-181472.29" switch \initial - attribute \src "libresoc.v:187277.9-187277.17" + attribute \src "libresoc.v:181472.9-181472.17" case 1'1 case end @@ -384372,77 +374917,77 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$12037 $4\wr_detect$13[0:0]$12040 + assign $1\wr_detect$13[0:0]$11740 $4\wr_detect$13[0:0]$11743 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$12038 1'1 + assign $2\wr_detect$13[0:0]$11741 1'1 case - assign $2\wr_detect$13[0:0]$12038 1'0 + assign $2\wr_detect$13[0:0]$11741 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$12039 1'1 + assign $3\wr_detect$13[0:0]$11742 1'1 case - assign $3\wr_detect$13[0:0]$12039 $2\wr_detect$13[0:0]$12038 + assign $3\wr_detect$13[0:0]$11742 $2\wr_detect$13[0:0]$11741 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$12040 1'1 + assign $4\wr_detect$13[0:0]$11743 1'1 case - assign $4\wr_detect$13[0:0]$12040 $3\wr_detect$13[0:0]$12039 + assign $4\wr_detect$13[0:0]$11743 $3\wr_detect$13[0:0]$11742 end case - assign $1\wr_detect$13[0:0]$12037 1'0 + assign $1\wr_detect$13[0:0]$11740 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$12036 + update \wr_detect$13 $0\wr_detect$13[0:0]$11739 end - connect \$9 $not$libresoc.v:186912$11959_Y - connect \$12 $not$libresoc.v:186913$11960_Y - connect \$1 $not$libresoc.v:186914$11961_Y - connect \$3 $not$libresoc.v:186915$11962_Y - connect \$6 $not$libresoc.v:186916$11963_Y + connect \$9 $not$libresoc.v:181107$11662_Y + connect \$12 $not$libresoc.v:181108$11663_Y + connect \$1 $not$libresoc.v:181109$11664_Y + connect \$3 $not$libresoc.v:181110$11665_Y + connect \$6 $not$libresoc.v:181111$11666_Y end -attribute \src "libresoc.v:187310.1-187368.10" +attribute \src "libresoc.v:181505.1-181563.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l - attribute \src "libresoc.v:187311.7-187311.20" + attribute \src "libresoc.v:181506.7-181506.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187356.3-187364.6" - wire width 5 $0\q_int$next[4:0]$12058 - attribute \src "libresoc.v:187354.3-187355.27" + attribute \src "libresoc.v:181551.3-181559.6" + wire width 5 $0\q_int$next[4:0]$11761 + attribute \src "libresoc.v:181549.3-181550.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:187356.3-187364.6" - wire width 5 $1\q_int$next[4:0]$12059 - attribute \src "libresoc.v:187333.13-187333.26" + attribute \src "libresoc.v:181551.3-181559.6" + wire width 5 $1\q_int$next[4:0]$11762 + attribute \src "libresoc.v:181528.13-181528.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:187346.17-187346.96" - wire width 5 $and$libresoc.v:187346$12048_Y - attribute \src "libresoc.v:187351.17-187351.96" - wire width 5 $and$libresoc.v:187351$12053_Y - attribute \src "libresoc.v:187348.18-187348.93" - wire width 5 $not$libresoc.v:187348$12050_Y - attribute \src "libresoc.v:187350.17-187350.92" - wire width 5 $not$libresoc.v:187350$12052_Y - attribute \src "libresoc.v:187353.17-187353.92" - wire width 5 $not$libresoc.v:187353$12055_Y - attribute \src "libresoc.v:187347.18-187347.98" - wire width 5 $or$libresoc.v:187347$12049_Y - attribute \src "libresoc.v:187349.18-187349.99" - wire width 5 $or$libresoc.v:187349$12051_Y - attribute \src "libresoc.v:187352.17-187352.97" - wire width 5 $or$libresoc.v:187352$12054_Y + attribute \src "libresoc.v:181541.17-181541.96" + wire width 5 $and$libresoc.v:181541$11751_Y + attribute \src "libresoc.v:181546.17-181546.96" + wire width 5 $and$libresoc.v:181546$11756_Y + attribute \src "libresoc.v:181543.18-181543.93" + wire width 5 $not$libresoc.v:181543$11753_Y + attribute \src "libresoc.v:181545.17-181545.92" + wire width 5 $not$libresoc.v:181545$11755_Y + attribute \src "libresoc.v:181548.17-181548.92" + wire width 5 $not$libresoc.v:181548$11758_Y + attribute \src "libresoc.v:181542.18-181542.98" + wire width 5 $or$libresoc.v:181542$11752_Y + attribute \src "libresoc.v:181544.18-181544.99" + wire width 5 $or$libresoc.v:181544$11754_Y + attribute \src "libresoc.v:181547.17-181547.97" + wire width 5 $or$libresoc.v:181547$11757_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -384459,11 +375004,11 @@ module \req_l wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187311.7-187311.15" + attribute \src "libresoc.v:181506.7-181506.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -384480,7 +375025,7 @@ module \req_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187346$12048 + cell $and $and$libresoc.v:181541$11751 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -384488,10 +375033,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187346$12048_Y + connect \Y $and$libresoc.v:181541$11751_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187351$12053 + cell $and $and$libresoc.v:181546$11756 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -384499,34 +375044,34 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187351$12053_Y + connect \Y $and$libresoc.v:181546$11756_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187348$12050 + cell $not $not$libresoc.v:181543$11753 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:187348$12050_Y + connect \Y $not$libresoc.v:181543$11753_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187350$12052 + cell $not $not$libresoc.v:181545$11755 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:187350$12052_Y + connect \Y $not$libresoc.v:181545$11755_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187353$12055 + cell $not $not$libresoc.v:181548$11758 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:187353$12055_Y + connect \Y $not$libresoc.v:181548$11758_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187347$12049 + cell $or $or$libresoc.v:181542$11752 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -384534,10 +375079,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:187347$12049_Y + connect \Y $or$libresoc.v:181542$11752_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187349$12051 + cell $or $or$libresoc.v:181544$11754 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -384545,10 +375090,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:187349$12051_Y + connect \Y $or$libresoc.v:181544$11754_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187352$12054 + cell $or $or$libresoc.v:181547$11757 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -384556,39 +375101,39 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:187352$12054_Y + connect \Y $or$libresoc.v:181547$11757_Y end - attribute \src "libresoc.v:187311.7-187311.20" - process $proc$libresoc.v:187311$12060 + attribute \src "libresoc.v:181506.7-181506.20" + process $proc$libresoc.v:181506$11763 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187333.13-187333.26" - process $proc$libresoc.v:187333$12061 + attribute \src "libresoc.v:181528.13-181528.26" + process $proc$libresoc.v:181528$11764 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:187354.3-187355.27" - process $proc$libresoc.v:187354$12056 + attribute \src "libresoc.v:181549.3-181550.27" + process $proc$libresoc.v:181549$11759 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:187356.3-187364.6" - process $proc$libresoc.v:187356$12057 + attribute \src "libresoc.v:181551.3-181559.6" + process $proc$libresoc.v:181551$11760 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$12058 $1\q_int$next[4:0]$12059 - attribute \src "libresoc.v:187357.5-187357.29" + assign $0\q_int$next[4:0]$11761 $1\q_int$next[4:0]$11762 + attribute \src "libresoc.v:181552.5-181552.29" switch \initial - attribute \src "libresoc.v:187357.9-187357.17" + attribute \src "libresoc.v:181552.9-181552.17" case 1'1 case end @@ -384597,56 +375142,56 @@ module \req_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$12059 5'00000 + assign $1\q_int$next[4:0]$11762 5'00000 case - assign $1\q_int$next[4:0]$12059 \$5 + assign $1\q_int$next[4:0]$11762 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$12058 + update \q_int$next $0\q_int$next[4:0]$11761 end - connect \$9 $and$libresoc.v:187346$12048_Y - connect \$11 $or$libresoc.v:187347$12049_Y - connect \$13 $not$libresoc.v:187348$12050_Y - connect \$15 $or$libresoc.v:187349$12051_Y - connect \$1 $not$libresoc.v:187350$12052_Y - connect \$3 $and$libresoc.v:187351$12053_Y - connect \$5 $or$libresoc.v:187352$12054_Y - connect \$7 $not$libresoc.v:187353$12055_Y + connect \$9 $and$libresoc.v:181541$11751_Y + connect \$11 $or$libresoc.v:181542$11752_Y + connect \$13 $not$libresoc.v:181543$11753_Y + connect \$15 $or$libresoc.v:181544$11754_Y + connect \$1 $not$libresoc.v:181545$11755_Y + connect \$3 $and$libresoc.v:181546$11756_Y + connect \$5 $or$libresoc.v:181547$11757_Y + connect \$7 $not$libresoc.v:181548$11758_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:187372.1-187430.10" +attribute \src "libresoc.v:181567.1-181625.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" module \req_l$103 - attribute \src "libresoc.v:187373.7-187373.20" + attribute \src "libresoc.v:181568.7-181568.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187418.3-187426.6" - wire width 4 $0\q_int$next[3:0]$12072 - attribute \src "libresoc.v:187416.3-187417.27" + attribute \src "libresoc.v:181613.3-181621.6" + wire width 4 $0\q_int$next[3:0]$11775 + attribute \src "libresoc.v:181611.3-181612.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:187418.3-187426.6" - wire width 4 $1\q_int$next[3:0]$12073 - attribute \src "libresoc.v:187395.13-187395.25" + attribute \src "libresoc.v:181613.3-181621.6" + wire width 4 $1\q_int$next[3:0]$11776 + attribute \src "libresoc.v:181590.13-181590.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:187408.17-187408.96" - wire width 4 $and$libresoc.v:187408$12062_Y - attribute \src "libresoc.v:187413.17-187413.96" - wire width 4 $and$libresoc.v:187413$12067_Y - attribute \src "libresoc.v:187410.18-187410.93" - wire width 4 $not$libresoc.v:187410$12064_Y - attribute \src "libresoc.v:187412.17-187412.92" - wire width 4 $not$libresoc.v:187412$12066_Y - attribute \src "libresoc.v:187415.17-187415.92" - wire width 4 $not$libresoc.v:187415$12069_Y - attribute \src "libresoc.v:187409.18-187409.98" - wire width 4 $or$libresoc.v:187409$12063_Y - attribute \src "libresoc.v:187411.18-187411.99" - wire width 4 $or$libresoc.v:187411$12065_Y - attribute \src "libresoc.v:187414.17-187414.97" - wire width 4 $or$libresoc.v:187414$12068_Y + attribute \src "libresoc.v:181603.17-181603.96" + wire width 4 $and$libresoc.v:181603$11765_Y + attribute \src "libresoc.v:181608.17-181608.96" + wire width 4 $and$libresoc.v:181608$11770_Y + attribute \src "libresoc.v:181605.18-181605.93" + wire width 4 $not$libresoc.v:181605$11767_Y + attribute \src "libresoc.v:181607.17-181607.92" + wire width 4 $not$libresoc.v:181607$11769_Y + attribute \src "libresoc.v:181610.17-181610.92" + wire width 4 $not$libresoc.v:181610$11772_Y + attribute \src "libresoc.v:181604.18-181604.98" + wire width 4 $or$libresoc.v:181604$11766_Y + attribute \src "libresoc.v:181606.18-181606.99" + wire width 4 $or$libresoc.v:181606$11768_Y + attribute \src "libresoc.v:181609.17-181609.97" + wire width 4 $or$libresoc.v:181609$11771_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -384663,11 +375208,11 @@ module \req_l$103 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187373.7-187373.15" + attribute \src "libresoc.v:181568.7-181568.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -384684,7 +375229,7 @@ module \req_l$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187408$12062 + cell $and $and$libresoc.v:181603$11765 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -384692,10 +375237,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187408$12062_Y + connect \Y $and$libresoc.v:181603$11765_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187413$12067 + cell $and $and$libresoc.v:181608$11770 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -384703,34 +375248,34 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187413$12067_Y + connect \Y $and$libresoc.v:181608$11770_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187410$12064 + cell $not $not$libresoc.v:181605$11767 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:187410$12064_Y + connect \Y $not$libresoc.v:181605$11767_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187412$12066 + cell $not $not$libresoc.v:181607$11769 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:187412$12066_Y + connect \Y $not$libresoc.v:181607$11769_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187415$12069 + cell $not $not$libresoc.v:181610$11772 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:187415$12069_Y + connect \Y $not$libresoc.v:181610$11772_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187409$12063 + cell $or $or$libresoc.v:181604$11766 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -384738,10 +375283,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:187409$12063_Y + connect \Y $or$libresoc.v:181604$11766_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187411$12065 + cell $or $or$libresoc.v:181606$11768 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -384749,10 +375294,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:187411$12065_Y + connect \Y $or$libresoc.v:181606$11768_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187414$12068 + cell $or $or$libresoc.v:181609$11771 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -384760,39 +375305,39 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:187414$12068_Y + connect \Y $or$libresoc.v:181609$11771_Y end - attribute \src "libresoc.v:187373.7-187373.20" - process $proc$libresoc.v:187373$12074 + attribute \src "libresoc.v:181568.7-181568.20" + process $proc$libresoc.v:181568$11777 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187395.13-187395.25" - process $proc$libresoc.v:187395$12075 + attribute \src "libresoc.v:181590.13-181590.25" + process $proc$libresoc.v:181590$11778 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:187416.3-187417.27" - process $proc$libresoc.v:187416$12070 + attribute \src "libresoc.v:181611.3-181612.27" + process $proc$libresoc.v:181611$11773 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:187418.3-187426.6" - process $proc$libresoc.v:187418$12071 + attribute \src "libresoc.v:181613.3-181621.6" + process $proc$libresoc.v:181613$11774 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$12072 $1\q_int$next[3:0]$12073 - attribute \src "libresoc.v:187419.5-187419.29" + assign $0\q_int$next[3:0]$11775 $1\q_int$next[3:0]$11776 + attribute \src "libresoc.v:181614.5-181614.29" switch \initial - attribute \src "libresoc.v:187419.9-187419.17" + attribute \src "libresoc.v:181614.9-181614.17" case 1'1 case end @@ -384801,56 +375346,56 @@ module \req_l$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$12073 4'0000 + assign $1\q_int$next[3:0]$11776 4'0000 case - assign $1\q_int$next[3:0]$12073 \$5 + assign $1\q_int$next[3:0]$11776 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$12072 + update \q_int$next $0\q_int$next[3:0]$11775 end - connect \$9 $and$libresoc.v:187408$12062_Y - connect \$11 $or$libresoc.v:187409$12063_Y - connect \$13 $not$libresoc.v:187410$12064_Y - connect \$15 $or$libresoc.v:187411$12065_Y - connect \$1 $not$libresoc.v:187412$12066_Y - connect \$3 $and$libresoc.v:187413$12067_Y - connect \$5 $or$libresoc.v:187414$12068_Y - connect \$7 $not$libresoc.v:187415$12069_Y + connect \$9 $and$libresoc.v:181603$11765_Y + connect \$11 $or$libresoc.v:181604$11766_Y + connect \$13 $not$libresoc.v:181605$11767_Y + connect \$15 $or$libresoc.v:181606$11768_Y + connect \$1 $not$libresoc.v:181607$11769_Y + connect \$3 $and$libresoc.v:181608$11770_Y + connect \$5 $or$libresoc.v:181609$11771_Y + connect \$7 $not$libresoc.v:181610$11772_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:187434.1-187492.10" +attribute \src "libresoc.v:181629.1-181687.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" module \req_l$12 - attribute \src "libresoc.v:187435.7-187435.20" + attribute \src "libresoc.v:181630.7-181630.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187480.3-187488.6" - wire width 3 $0\q_int$next[2:0]$12086 - attribute \src "libresoc.v:187478.3-187479.27" + attribute \src "libresoc.v:181675.3-181683.6" + wire width 3 $0\q_int$next[2:0]$11789 + attribute \src "libresoc.v:181673.3-181674.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:187480.3-187488.6" - wire width 3 $1\q_int$next[2:0]$12087 - attribute \src "libresoc.v:187457.13-187457.25" + attribute \src "libresoc.v:181675.3-181683.6" + wire width 3 $1\q_int$next[2:0]$11790 + attribute \src "libresoc.v:181652.13-181652.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:187470.17-187470.96" - wire width 3 $and$libresoc.v:187470$12076_Y - attribute \src "libresoc.v:187475.17-187475.96" - wire width 3 $and$libresoc.v:187475$12081_Y - attribute \src "libresoc.v:187472.18-187472.93" - wire width 3 $not$libresoc.v:187472$12078_Y - attribute \src "libresoc.v:187474.17-187474.92" - wire width 3 $not$libresoc.v:187474$12080_Y - attribute \src "libresoc.v:187477.17-187477.92" - wire width 3 $not$libresoc.v:187477$12083_Y - attribute \src "libresoc.v:187471.18-187471.98" - wire width 3 $or$libresoc.v:187471$12077_Y - attribute \src "libresoc.v:187473.18-187473.99" - wire width 3 $or$libresoc.v:187473$12079_Y - attribute \src "libresoc.v:187476.17-187476.97" - wire width 3 $or$libresoc.v:187476$12082_Y + attribute \src "libresoc.v:181665.17-181665.96" + wire width 3 $and$libresoc.v:181665$11779_Y + attribute \src "libresoc.v:181670.17-181670.96" + wire width 3 $and$libresoc.v:181670$11784_Y + attribute \src "libresoc.v:181667.18-181667.93" + wire width 3 $not$libresoc.v:181667$11781_Y + attribute \src "libresoc.v:181669.17-181669.92" + wire width 3 $not$libresoc.v:181669$11783_Y + attribute \src "libresoc.v:181672.17-181672.92" + wire width 3 $not$libresoc.v:181672$11786_Y + attribute \src "libresoc.v:181666.18-181666.98" + wire width 3 $or$libresoc.v:181666$11780_Y + attribute \src "libresoc.v:181668.18-181668.99" + wire width 3 $or$libresoc.v:181668$11782_Y + attribute \src "libresoc.v:181671.17-181671.97" + wire width 3 $or$libresoc.v:181671$11785_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -384867,11 +375412,11 @@ module \req_l$12 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187435.7-187435.15" + attribute \src "libresoc.v:181630.7-181630.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -384888,7 +375433,7 @@ module \req_l$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187470$12076 + cell $and $and$libresoc.v:181665$11779 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -384896,10 +375441,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187470$12076_Y + connect \Y $and$libresoc.v:181665$11779_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187475$12081 + cell $and $and$libresoc.v:181670$11784 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -384907,34 +375452,34 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187475$12081_Y + connect \Y $and$libresoc.v:181670$11784_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187472$12078 + cell $not $not$libresoc.v:181667$11781 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:187472$12078_Y + connect \Y $not$libresoc.v:181667$11781_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187474$12080 + cell $not $not$libresoc.v:181669$11783 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:187474$12080_Y + connect \Y $not$libresoc.v:181669$11783_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187477$12083 + cell $not $not$libresoc.v:181672$11786 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:187477$12083_Y + connect \Y $not$libresoc.v:181672$11786_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187471$12077 + cell $or $or$libresoc.v:181666$11780 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -384942,10 +375487,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:187471$12077_Y + connect \Y $or$libresoc.v:181666$11780_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187473$12079 + cell $or $or$libresoc.v:181668$11782 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -384953,10 +375498,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:187473$12079_Y + connect \Y $or$libresoc.v:181668$11782_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187476$12082 + cell $or $or$libresoc.v:181671$11785 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -384964,39 +375509,39 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:187476$12082_Y + connect \Y $or$libresoc.v:181671$11785_Y end - attribute \src "libresoc.v:187435.7-187435.20" - process $proc$libresoc.v:187435$12088 + attribute \src "libresoc.v:181630.7-181630.20" + process $proc$libresoc.v:181630$11791 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187457.13-187457.25" - process $proc$libresoc.v:187457$12089 + attribute \src "libresoc.v:181652.13-181652.25" + process $proc$libresoc.v:181652$11792 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:187478.3-187479.27" - process $proc$libresoc.v:187478$12084 + attribute \src "libresoc.v:181673.3-181674.27" + process $proc$libresoc.v:181673$11787 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:187480.3-187488.6" - process $proc$libresoc.v:187480$12085 + attribute \src "libresoc.v:181675.3-181683.6" + process $proc$libresoc.v:181675$11788 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12086 $1\q_int$next[2:0]$12087 - attribute \src "libresoc.v:187481.5-187481.29" + assign $0\q_int$next[2:0]$11789 $1\q_int$next[2:0]$11790 + attribute \src "libresoc.v:181676.5-181676.29" switch \initial - attribute \src "libresoc.v:187481.9-187481.17" + attribute \src "libresoc.v:181676.9-181676.17" case 1'1 case end @@ -385005,56 +375550,56 @@ module \req_l$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12087 3'000 + assign $1\q_int$next[2:0]$11790 3'000 case - assign $1\q_int$next[2:0]$12087 \$5 + assign $1\q_int$next[2:0]$11790 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12086 + update \q_int$next $0\q_int$next[2:0]$11789 end - connect \$9 $and$libresoc.v:187470$12076_Y - connect \$11 $or$libresoc.v:187471$12077_Y - connect \$13 $not$libresoc.v:187472$12078_Y - connect \$15 $or$libresoc.v:187473$12079_Y - connect \$1 $not$libresoc.v:187474$12080_Y - connect \$3 $and$libresoc.v:187475$12081_Y - connect \$5 $or$libresoc.v:187476$12082_Y - connect \$7 $not$libresoc.v:187477$12083_Y + connect \$9 $and$libresoc.v:181665$11779_Y + connect \$11 $or$libresoc.v:181666$11780_Y + connect \$13 $not$libresoc.v:181667$11781_Y + connect \$15 $or$libresoc.v:181668$11782_Y + connect \$1 $not$libresoc.v:181669$11783_Y + connect \$3 $and$libresoc.v:181670$11784_Y + connect \$5 $or$libresoc.v:181671$11785_Y + connect \$7 $not$libresoc.v:181672$11786_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:187496.1-187554.10" +attribute \src "libresoc.v:181691.1-181749.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" module \req_l$121 - attribute \src "libresoc.v:187497.7-187497.20" + attribute \src "libresoc.v:181692.7-181692.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187542.3-187550.6" - wire width 3 $0\q_int$next[2:0]$12100 - attribute \src "libresoc.v:187540.3-187541.27" + attribute \src "libresoc.v:181737.3-181745.6" + wire width 3 $0\q_int$next[2:0]$11803 + attribute \src "libresoc.v:181735.3-181736.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:187542.3-187550.6" - wire width 3 $1\q_int$next[2:0]$12101 - attribute \src "libresoc.v:187519.13-187519.25" + attribute \src "libresoc.v:181737.3-181745.6" + wire width 3 $1\q_int$next[2:0]$11804 + attribute \src "libresoc.v:181714.13-181714.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:187532.17-187532.96" - wire width 3 $and$libresoc.v:187532$12090_Y - attribute \src "libresoc.v:187537.17-187537.96" - wire width 3 $and$libresoc.v:187537$12095_Y - attribute \src "libresoc.v:187534.18-187534.93" - wire width 3 $not$libresoc.v:187534$12092_Y - attribute \src "libresoc.v:187536.17-187536.92" - wire width 3 $not$libresoc.v:187536$12094_Y - attribute \src "libresoc.v:187539.17-187539.92" - wire width 3 $not$libresoc.v:187539$12097_Y - attribute \src "libresoc.v:187533.18-187533.98" - wire width 3 $or$libresoc.v:187533$12091_Y - attribute \src "libresoc.v:187535.18-187535.99" - wire width 3 $or$libresoc.v:187535$12093_Y - attribute \src "libresoc.v:187538.17-187538.97" - wire width 3 $or$libresoc.v:187538$12096_Y + attribute \src "libresoc.v:181727.17-181727.96" + wire width 3 $and$libresoc.v:181727$11793_Y + attribute \src "libresoc.v:181732.17-181732.96" + wire width 3 $and$libresoc.v:181732$11798_Y + attribute \src "libresoc.v:181729.18-181729.93" + wire width 3 $not$libresoc.v:181729$11795_Y + attribute \src "libresoc.v:181731.17-181731.92" + wire width 3 $not$libresoc.v:181731$11797_Y + attribute \src "libresoc.v:181734.17-181734.92" + wire width 3 $not$libresoc.v:181734$11800_Y + attribute \src "libresoc.v:181728.18-181728.98" + wire width 3 $or$libresoc.v:181728$11794_Y + attribute \src "libresoc.v:181730.18-181730.99" + wire width 3 $or$libresoc.v:181730$11796_Y + attribute \src "libresoc.v:181733.17-181733.97" + wire width 3 $or$libresoc.v:181733$11799_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385071,11 +375616,11 @@ module \req_l$121 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187497.7-187497.15" + attribute \src "libresoc.v:181692.7-181692.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -385092,7 +375637,7 @@ module \req_l$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187532$12090 + cell $and $and$libresoc.v:181727$11793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385100,10 +375645,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187532$12090_Y + connect \Y $and$libresoc.v:181727$11793_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187537$12095 + cell $and $and$libresoc.v:181732$11798 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385111,34 +375656,34 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187537$12095_Y + connect \Y $and$libresoc.v:181732$11798_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187534$12092 + cell $not $not$libresoc.v:181729$11795 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:187534$12092_Y + connect \Y $not$libresoc.v:181729$11795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187536$12094 + cell $not $not$libresoc.v:181731$11797 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:187536$12094_Y + connect \Y $not$libresoc.v:181731$11797_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187539$12097 + cell $not $not$libresoc.v:181734$11800 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:187539$12097_Y + connect \Y $not$libresoc.v:181734$11800_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187533$12091 + cell $or $or$libresoc.v:181728$11794 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385146,10 +375691,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:187533$12091_Y + connect \Y $or$libresoc.v:181728$11794_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187535$12093 + cell $or $or$libresoc.v:181730$11796 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385157,10 +375702,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:187535$12093_Y + connect \Y $or$libresoc.v:181730$11796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187538$12096 + cell $or $or$libresoc.v:181733$11799 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385168,39 +375713,39 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:187538$12096_Y + connect \Y $or$libresoc.v:181733$11799_Y end - attribute \src "libresoc.v:187497.7-187497.20" - process $proc$libresoc.v:187497$12102 + attribute \src "libresoc.v:181692.7-181692.20" + process $proc$libresoc.v:181692$11805 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187519.13-187519.25" - process $proc$libresoc.v:187519$12103 + attribute \src "libresoc.v:181714.13-181714.25" + process $proc$libresoc.v:181714$11806 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:187540.3-187541.27" - process $proc$libresoc.v:187540$12098 + attribute \src "libresoc.v:181735.3-181736.27" + process $proc$libresoc.v:181735$11801 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:187542.3-187550.6" - process $proc$libresoc.v:187542$12099 + attribute \src "libresoc.v:181737.3-181745.6" + process $proc$libresoc.v:181737$11802 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12100 $1\q_int$next[2:0]$12101 - attribute \src "libresoc.v:187543.5-187543.29" + assign $0\q_int$next[2:0]$11803 $1\q_int$next[2:0]$11804 + attribute \src "libresoc.v:181738.5-181738.29" switch \initial - attribute \src "libresoc.v:187543.9-187543.17" + attribute \src "libresoc.v:181738.9-181738.17" case 1'1 case end @@ -385209,56 +375754,56 @@ module \req_l$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12101 3'000 + assign $1\q_int$next[2:0]$11804 3'000 case - assign $1\q_int$next[2:0]$12101 \$5 + assign $1\q_int$next[2:0]$11804 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12100 + update \q_int$next $0\q_int$next[2:0]$11803 end - connect \$9 $and$libresoc.v:187532$12090_Y - connect \$11 $or$libresoc.v:187533$12091_Y - connect \$13 $not$libresoc.v:187534$12092_Y - connect \$15 $or$libresoc.v:187535$12093_Y - connect \$1 $not$libresoc.v:187536$12094_Y - connect \$3 $and$libresoc.v:187537$12095_Y - connect \$5 $or$libresoc.v:187538$12096_Y - connect \$7 $not$libresoc.v:187539$12097_Y + connect \$9 $and$libresoc.v:181727$11793_Y + connect \$11 $or$libresoc.v:181728$11794_Y + connect \$13 $not$libresoc.v:181729$11795_Y + connect \$15 $or$libresoc.v:181730$11796_Y + connect \$1 $not$libresoc.v:181731$11797_Y + connect \$3 $and$libresoc.v:181732$11798_Y + connect \$5 $or$libresoc.v:181733$11799_Y + connect \$7 $not$libresoc.v:181734$11800_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:187558.1-187616.10" +attribute \src "libresoc.v:181753.1-181811.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 - attribute \src "libresoc.v:187559.7-187559.20" + attribute \src "libresoc.v:181754.7-181754.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187604.3-187612.6" - wire width 3 $0\q_int$next[2:0]$12114 - attribute \src "libresoc.v:187602.3-187603.27" + attribute \src "libresoc.v:181799.3-181807.6" + wire width 3 $0\q_int$next[2:0]$11817 + attribute \src "libresoc.v:181797.3-181798.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:187604.3-187612.6" - wire width 3 $1\q_int$next[2:0]$12115 - attribute \src "libresoc.v:187581.13-187581.25" + attribute \src "libresoc.v:181799.3-181807.6" + wire width 3 $1\q_int$next[2:0]$11818 + attribute \src "libresoc.v:181776.13-181776.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:187594.17-187594.96" - wire width 3 $and$libresoc.v:187594$12104_Y - attribute \src "libresoc.v:187599.17-187599.96" - wire width 3 $and$libresoc.v:187599$12109_Y - attribute \src "libresoc.v:187596.18-187596.93" - wire width 3 $not$libresoc.v:187596$12106_Y - attribute \src "libresoc.v:187598.17-187598.92" - wire width 3 $not$libresoc.v:187598$12108_Y - attribute \src "libresoc.v:187601.17-187601.92" - wire width 3 $not$libresoc.v:187601$12111_Y - attribute \src "libresoc.v:187595.18-187595.98" - wire width 3 $or$libresoc.v:187595$12105_Y - attribute \src "libresoc.v:187597.18-187597.99" - wire width 3 $or$libresoc.v:187597$12107_Y - attribute \src "libresoc.v:187600.17-187600.97" - wire width 3 $or$libresoc.v:187600$12110_Y + attribute \src "libresoc.v:181789.17-181789.96" + wire width 3 $and$libresoc.v:181789$11807_Y + attribute \src "libresoc.v:181794.17-181794.96" + wire width 3 $and$libresoc.v:181794$11812_Y + attribute \src "libresoc.v:181791.18-181791.93" + wire width 3 $not$libresoc.v:181791$11809_Y + attribute \src "libresoc.v:181793.17-181793.92" + wire width 3 $not$libresoc.v:181793$11811_Y + attribute \src "libresoc.v:181796.17-181796.92" + wire width 3 $not$libresoc.v:181796$11814_Y + attribute \src "libresoc.v:181790.18-181790.98" + wire width 3 $or$libresoc.v:181790$11808_Y + attribute \src "libresoc.v:181792.18-181792.99" + wire width 3 $or$libresoc.v:181792$11810_Y + attribute \src "libresoc.v:181795.17-181795.97" + wire width 3 $or$libresoc.v:181795$11813_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385275,11 +375820,11 @@ module \req_l$25 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187559.7-187559.15" + attribute \src "libresoc.v:181754.7-181754.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -385296,7 +375841,7 @@ module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187594$12104 + cell $and $and$libresoc.v:181789$11807 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385304,10 +375849,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187594$12104_Y + connect \Y $and$libresoc.v:181789$11807_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187599$12109 + cell $and $and$libresoc.v:181794$11812 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385315,34 +375860,34 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187599$12109_Y + connect \Y $and$libresoc.v:181794$11812_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187596$12106 + cell $not $not$libresoc.v:181791$11809 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:187596$12106_Y + connect \Y $not$libresoc.v:181791$11809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187598$12108 + cell $not $not$libresoc.v:181793$11811 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:187598$12108_Y + connect \Y $not$libresoc.v:181793$11811_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187601$12111 + cell $not $not$libresoc.v:181796$11814 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:187601$12111_Y + connect \Y $not$libresoc.v:181796$11814_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187595$12105 + cell $or $or$libresoc.v:181790$11808 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385350,10 +375895,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:187595$12105_Y + connect \Y $or$libresoc.v:181790$11808_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187597$12107 + cell $or $or$libresoc.v:181792$11810 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385361,10 +375906,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:187597$12107_Y + connect \Y $or$libresoc.v:181792$11810_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187600$12110 + cell $or $or$libresoc.v:181795$11813 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385372,39 +375917,39 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:187600$12110_Y + connect \Y $or$libresoc.v:181795$11813_Y end - attribute \src "libresoc.v:187559.7-187559.20" - process $proc$libresoc.v:187559$12116 + attribute \src "libresoc.v:181754.7-181754.20" + process $proc$libresoc.v:181754$11819 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187581.13-187581.25" - process $proc$libresoc.v:187581$12117 + attribute \src "libresoc.v:181776.13-181776.25" + process $proc$libresoc.v:181776$11820 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:187602.3-187603.27" - process $proc$libresoc.v:187602$12112 + attribute \src "libresoc.v:181797.3-181798.27" + process $proc$libresoc.v:181797$11815 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:187604.3-187612.6" - process $proc$libresoc.v:187604$12113 + attribute \src "libresoc.v:181799.3-181807.6" + process $proc$libresoc.v:181799$11816 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$12114 $1\q_int$next[2:0]$12115 - attribute \src "libresoc.v:187605.5-187605.29" + assign $0\q_int$next[2:0]$11817 $1\q_int$next[2:0]$11818 + attribute \src "libresoc.v:181800.5-181800.29" switch \initial - attribute \src "libresoc.v:187605.9-187605.17" + attribute \src "libresoc.v:181800.9-181800.17" case 1'1 case end @@ -385413,56 +375958,56 @@ module \req_l$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$12115 3'000 + assign $1\q_int$next[2:0]$11818 3'000 case - assign $1\q_int$next[2:0]$12115 \$5 + assign $1\q_int$next[2:0]$11818 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$12114 + update \q_int$next $0\q_int$next[2:0]$11817 end - connect \$9 $and$libresoc.v:187594$12104_Y - connect \$11 $or$libresoc.v:187595$12105_Y - connect \$13 $not$libresoc.v:187596$12106_Y - connect \$15 $or$libresoc.v:187597$12107_Y - connect \$1 $not$libresoc.v:187598$12108_Y - connect \$3 $and$libresoc.v:187599$12109_Y - connect \$5 $or$libresoc.v:187600$12110_Y - connect \$7 $not$libresoc.v:187601$12111_Y + connect \$9 $and$libresoc.v:181789$11807_Y + connect \$11 $or$libresoc.v:181790$11808_Y + connect \$13 $not$libresoc.v:181791$11809_Y + connect \$15 $or$libresoc.v:181792$11810_Y + connect \$1 $not$libresoc.v:181793$11811_Y + connect \$3 $and$libresoc.v:181794$11812_Y + connect \$5 $or$libresoc.v:181795$11813_Y + connect \$7 $not$libresoc.v:181796$11814_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:187620.1-187678.10" +attribute \src "libresoc.v:181815.1-181873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" module \req_l$41 - attribute \src "libresoc.v:187621.7-187621.20" + attribute \src "libresoc.v:181816.7-181816.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187666.3-187674.6" - wire width 5 $0\q_int$next[4:0]$12128 - attribute \src "libresoc.v:187664.3-187665.27" + attribute \src "libresoc.v:181861.3-181869.6" + wire width 5 $0\q_int$next[4:0]$11831 + attribute \src "libresoc.v:181859.3-181860.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:187666.3-187674.6" - wire width 5 $1\q_int$next[4:0]$12129 - attribute \src "libresoc.v:187643.13-187643.26" + attribute \src "libresoc.v:181861.3-181869.6" + wire width 5 $1\q_int$next[4:0]$11832 + attribute \src "libresoc.v:181838.13-181838.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:187656.17-187656.96" - wire width 5 $and$libresoc.v:187656$12118_Y - attribute \src "libresoc.v:187661.17-187661.96" - wire width 5 $and$libresoc.v:187661$12123_Y - attribute \src "libresoc.v:187658.18-187658.93" - wire width 5 $not$libresoc.v:187658$12120_Y - attribute \src "libresoc.v:187660.17-187660.92" - wire width 5 $not$libresoc.v:187660$12122_Y - attribute \src "libresoc.v:187663.17-187663.92" - wire width 5 $not$libresoc.v:187663$12125_Y - attribute \src "libresoc.v:187657.18-187657.98" - wire width 5 $or$libresoc.v:187657$12119_Y - attribute \src "libresoc.v:187659.18-187659.99" - wire width 5 $or$libresoc.v:187659$12121_Y - attribute \src "libresoc.v:187662.17-187662.97" - wire width 5 $or$libresoc.v:187662$12124_Y + attribute \src "libresoc.v:181851.17-181851.96" + wire width 5 $and$libresoc.v:181851$11821_Y + attribute \src "libresoc.v:181856.17-181856.96" + wire width 5 $and$libresoc.v:181856$11826_Y + attribute \src "libresoc.v:181853.18-181853.93" + wire width 5 $not$libresoc.v:181853$11823_Y + attribute \src "libresoc.v:181855.17-181855.92" + wire width 5 $not$libresoc.v:181855$11825_Y + attribute \src "libresoc.v:181858.17-181858.92" + wire width 5 $not$libresoc.v:181858$11828_Y + attribute \src "libresoc.v:181852.18-181852.98" + wire width 5 $or$libresoc.v:181852$11822_Y + attribute \src "libresoc.v:181854.18-181854.99" + wire width 5 $or$libresoc.v:181854$11824_Y + attribute \src "libresoc.v:181857.17-181857.97" + wire width 5 $or$libresoc.v:181857$11827_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385479,11 +376024,11 @@ module \req_l$41 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187621.7-187621.15" + attribute \src "libresoc.v:181816.7-181816.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -385500,7 +376045,7 @@ module \req_l$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187656$12118 + cell $and $and$libresoc.v:181851$11821 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385508,10 +376053,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187656$12118_Y + connect \Y $and$libresoc.v:181851$11821_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187661$12123 + cell $and $and$libresoc.v:181856$11826 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385519,34 +376064,34 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187661$12123_Y + connect \Y $and$libresoc.v:181856$11826_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187658$12120 + cell $not $not$libresoc.v:181853$11823 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:187658$12120_Y + connect \Y $not$libresoc.v:181853$11823_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187660$12122 + cell $not $not$libresoc.v:181855$11825 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:187660$12122_Y + connect \Y $not$libresoc.v:181855$11825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187663$12125 + cell $not $not$libresoc.v:181858$11828 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:187663$12125_Y + connect \Y $not$libresoc.v:181858$11828_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187657$12119 + cell $or $or$libresoc.v:181852$11822 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385554,10 +376099,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:187657$12119_Y + connect \Y $or$libresoc.v:181852$11822_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187659$12121 + cell $or $or$libresoc.v:181854$11824 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385565,10 +376110,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:187659$12121_Y + connect \Y $or$libresoc.v:181854$11824_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187662$12124 + cell $or $or$libresoc.v:181857$11827 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385576,39 +376121,39 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:187662$12124_Y + connect \Y $or$libresoc.v:181857$11827_Y end - attribute \src "libresoc.v:187621.7-187621.20" - process $proc$libresoc.v:187621$12130 + attribute \src "libresoc.v:181816.7-181816.20" + process $proc$libresoc.v:181816$11833 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187643.13-187643.26" - process $proc$libresoc.v:187643$12131 + attribute \src "libresoc.v:181838.13-181838.26" + process $proc$libresoc.v:181838$11834 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:187664.3-187665.27" - process $proc$libresoc.v:187664$12126 + attribute \src "libresoc.v:181859.3-181860.27" + process $proc$libresoc.v:181859$11829 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:187666.3-187674.6" - process $proc$libresoc.v:187666$12127 + attribute \src "libresoc.v:181861.3-181869.6" + process $proc$libresoc.v:181861$11830 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$12128 $1\q_int$next[4:0]$12129 - attribute \src "libresoc.v:187667.5-187667.29" + assign $0\q_int$next[4:0]$11831 $1\q_int$next[4:0]$11832 + attribute \src "libresoc.v:181862.5-181862.29" switch \initial - attribute \src "libresoc.v:187667.9-187667.17" + attribute \src "libresoc.v:181862.9-181862.17" case 1'1 case end @@ -385617,56 +376162,56 @@ module \req_l$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$12129 5'00000 + assign $1\q_int$next[4:0]$11832 5'00000 case - assign $1\q_int$next[4:0]$12129 \$5 + assign $1\q_int$next[4:0]$11832 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$12128 + update \q_int$next $0\q_int$next[4:0]$11831 end - connect \$9 $and$libresoc.v:187656$12118_Y - connect \$11 $or$libresoc.v:187657$12119_Y - connect \$13 $not$libresoc.v:187658$12120_Y - connect \$15 $or$libresoc.v:187659$12121_Y - connect \$1 $not$libresoc.v:187660$12122_Y - connect \$3 $and$libresoc.v:187661$12123_Y - connect \$5 $or$libresoc.v:187662$12124_Y - connect \$7 $not$libresoc.v:187663$12125_Y + connect \$9 $and$libresoc.v:181851$11821_Y + connect \$11 $or$libresoc.v:181852$11822_Y + connect \$13 $not$libresoc.v:181853$11823_Y + connect \$15 $or$libresoc.v:181854$11824_Y + connect \$1 $not$libresoc.v:181855$11825_Y + connect \$3 $and$libresoc.v:181856$11826_Y + connect \$5 $or$libresoc.v:181857$11827_Y + connect \$7 $not$libresoc.v:181858$11828_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:187682.1-187740.10" +attribute \src "libresoc.v:181877.1-181935.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" module \req_l$57 - attribute \src "libresoc.v:187683.7-187683.20" + attribute \src "libresoc.v:181878.7-181878.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187728.3-187736.6" - wire width 2 $0\q_int$next[1:0]$12142 - attribute \src "libresoc.v:187726.3-187727.27" + attribute \src "libresoc.v:181923.3-181931.6" + wire width 2 $0\q_int$next[1:0]$11845 + attribute \src "libresoc.v:181921.3-181922.27" wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:187728.3-187736.6" - wire width 2 $1\q_int$next[1:0]$12143 - attribute \src "libresoc.v:187705.13-187705.25" + attribute \src "libresoc.v:181923.3-181931.6" + wire width 2 $1\q_int$next[1:0]$11846 + attribute \src "libresoc.v:181900.13-181900.25" wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:187718.17-187718.96" - wire width 2 $and$libresoc.v:187718$12132_Y - attribute \src "libresoc.v:187723.17-187723.96" - wire width 2 $and$libresoc.v:187723$12137_Y - attribute \src "libresoc.v:187720.18-187720.93" - wire width 2 $not$libresoc.v:187720$12134_Y - attribute \src "libresoc.v:187722.17-187722.92" - wire width 2 $not$libresoc.v:187722$12136_Y - attribute \src "libresoc.v:187725.17-187725.92" - wire width 2 $not$libresoc.v:187725$12139_Y - attribute \src "libresoc.v:187719.18-187719.98" - wire width 2 $or$libresoc.v:187719$12133_Y - attribute \src "libresoc.v:187721.18-187721.99" - wire width 2 $or$libresoc.v:187721$12135_Y - attribute \src "libresoc.v:187724.17-187724.97" - wire width 2 $or$libresoc.v:187724$12138_Y + attribute \src "libresoc.v:181913.17-181913.96" + wire width 2 $and$libresoc.v:181913$11835_Y + attribute \src "libresoc.v:181918.17-181918.96" + wire width 2 $and$libresoc.v:181918$11840_Y + attribute \src "libresoc.v:181915.18-181915.93" + wire width 2 $not$libresoc.v:181915$11837_Y + attribute \src "libresoc.v:181917.17-181917.92" + wire width 2 $not$libresoc.v:181917$11839_Y + attribute \src "libresoc.v:181920.17-181920.92" + wire width 2 $not$libresoc.v:181920$11842_Y + attribute \src "libresoc.v:181914.18-181914.98" + wire width 2 $or$libresoc.v:181914$11836_Y + attribute \src "libresoc.v:181916.18-181916.99" + wire width 2 $or$libresoc.v:181916$11838_Y + attribute \src "libresoc.v:181919.17-181919.97" + wire width 2 $or$libresoc.v:181919$11841_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385683,11 +376228,11 @@ module \req_l$57 wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187683.7-187683.15" + attribute \src "libresoc.v:181878.7-181878.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int @@ -385704,7 +376249,7 @@ module \req_l$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187718$12132 + cell $and $and$libresoc.v:181913$11835 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -385712,10 +376257,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187718$12132_Y + connect \Y $and$libresoc.v:181913$11835_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187723$12137 + cell $and $and$libresoc.v:181918$11840 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -385723,34 +376268,34 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187723$12137_Y + connect \Y $and$libresoc.v:181918$11840_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187720$12134 + cell $not $not$libresoc.v:181915$11837 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req - connect \Y $not$libresoc.v:187720$12134_Y + connect \Y $not$libresoc.v:181915$11837_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187722$12136 + cell $not $not$libresoc.v:181917$11839 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:187722$12136_Y + connect \Y $not$libresoc.v:181917$11839_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187725$12139 + cell $not $not$libresoc.v:181920$11842 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:187725$12139_Y + connect \Y $not$libresoc.v:181920$11842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187719$12133 + cell $or $or$libresoc.v:181914$11836 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -385758,10 +376303,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:187719$12133_Y + connect \Y $or$libresoc.v:181914$11836_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187721$12135 + cell $or $or$libresoc.v:181916$11838 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -385769,10 +376314,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:187721$12135_Y + connect \Y $or$libresoc.v:181916$11838_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187724$12138 + cell $or $or$libresoc.v:181919$11841 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -385780,39 +376325,39 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:187724$12138_Y + connect \Y $or$libresoc.v:181919$11841_Y end - attribute \src "libresoc.v:187683.7-187683.20" - process $proc$libresoc.v:187683$12144 + attribute \src "libresoc.v:181878.7-181878.20" + process $proc$libresoc.v:181878$11847 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187705.13-187705.25" - process $proc$libresoc.v:187705$12145 + attribute \src "libresoc.v:181900.13-181900.25" + process $proc$libresoc.v:181900$11848 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end - attribute \src "libresoc.v:187726.3-187727.27" - process $proc$libresoc.v:187726$12140 + attribute \src "libresoc.v:181921.3-181922.27" + process $proc$libresoc.v:181921$11843 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end - attribute \src "libresoc.v:187728.3-187736.6" - process $proc$libresoc.v:187728$12141 + attribute \src "libresoc.v:181923.3-181931.6" + process $proc$libresoc.v:181923$11844 assign { } { } assign { } { } - assign $0\q_int$next[1:0]$12142 $1\q_int$next[1:0]$12143 - attribute \src "libresoc.v:187729.5-187729.29" + assign $0\q_int$next[1:0]$11845 $1\q_int$next[1:0]$11846 + attribute \src "libresoc.v:181924.5-181924.29" switch \initial - attribute \src "libresoc.v:187729.9-187729.17" + attribute \src "libresoc.v:181924.9-181924.17" case 1'1 case end @@ -385821,56 +376366,56 @@ module \req_l$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[1:0]$12143 2'00 + assign $1\q_int$next[1:0]$11846 2'00 case - assign $1\q_int$next[1:0]$12143 \$5 + assign $1\q_int$next[1:0]$11846 \$5 end sync always - update \q_int$next $0\q_int$next[1:0]$12142 + update \q_int$next $0\q_int$next[1:0]$11845 end - connect \$9 $and$libresoc.v:187718$12132_Y - connect \$11 $or$libresoc.v:187719$12133_Y - connect \$13 $not$libresoc.v:187720$12134_Y - connect \$15 $or$libresoc.v:187721$12135_Y - connect \$1 $not$libresoc.v:187722$12136_Y - connect \$3 $and$libresoc.v:187723$12137_Y - connect \$5 $or$libresoc.v:187724$12138_Y - connect \$7 $not$libresoc.v:187725$12139_Y + connect \$9 $and$libresoc.v:181913$11835_Y + connect \$11 $or$libresoc.v:181914$11836_Y + connect \$13 $not$libresoc.v:181915$11837_Y + connect \$15 $or$libresoc.v:181916$11838_Y + connect \$1 $not$libresoc.v:181917$11839_Y + connect \$3 $and$libresoc.v:181918$11840_Y + connect \$5 $or$libresoc.v:181919$11841_Y + connect \$7 $not$libresoc.v:181920$11842_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:187744.1-187802.10" +attribute \src "libresoc.v:181939.1-181997.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" module \req_l$69 - attribute \src "libresoc.v:187745.7-187745.20" + attribute \src "libresoc.v:181940.7-181940.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187790.3-187798.6" - wire width 6 $0\q_int$next[5:0]$12156 - attribute \src "libresoc.v:187788.3-187789.27" + attribute \src "libresoc.v:181985.3-181993.6" + wire width 6 $0\q_int$next[5:0]$11859 + attribute \src "libresoc.v:181983.3-181984.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:187790.3-187798.6" - wire width 6 $1\q_int$next[5:0]$12157 - attribute \src "libresoc.v:187767.13-187767.26" + attribute \src "libresoc.v:181985.3-181993.6" + wire width 6 $1\q_int$next[5:0]$11860 + attribute \src "libresoc.v:181962.13-181962.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:187780.17-187780.96" - wire width 6 $and$libresoc.v:187780$12146_Y - attribute \src "libresoc.v:187785.17-187785.96" - wire width 6 $and$libresoc.v:187785$12151_Y - attribute \src "libresoc.v:187782.18-187782.93" - wire width 6 $not$libresoc.v:187782$12148_Y - attribute \src "libresoc.v:187784.17-187784.92" - wire width 6 $not$libresoc.v:187784$12150_Y - attribute \src "libresoc.v:187787.17-187787.92" - wire width 6 $not$libresoc.v:187787$12153_Y - attribute \src "libresoc.v:187781.18-187781.98" - wire width 6 $or$libresoc.v:187781$12147_Y - attribute \src "libresoc.v:187783.18-187783.99" - wire width 6 $or$libresoc.v:187783$12149_Y - attribute \src "libresoc.v:187786.17-187786.97" - wire width 6 $or$libresoc.v:187786$12152_Y + attribute \src "libresoc.v:181975.17-181975.96" + wire width 6 $and$libresoc.v:181975$11849_Y + attribute \src "libresoc.v:181980.17-181980.96" + wire width 6 $and$libresoc.v:181980$11854_Y + attribute \src "libresoc.v:181977.18-181977.93" + wire width 6 $not$libresoc.v:181977$11851_Y + attribute \src "libresoc.v:181979.17-181979.92" + wire width 6 $not$libresoc.v:181979$11853_Y + attribute \src "libresoc.v:181982.17-181982.92" + wire width 6 $not$libresoc.v:181982$11856_Y + attribute \src "libresoc.v:181976.18-181976.98" + wire width 6 $or$libresoc.v:181976$11850_Y + attribute \src "libresoc.v:181978.18-181978.99" + wire width 6 $or$libresoc.v:181978$11852_Y + attribute \src "libresoc.v:181981.17-181981.97" + wire width 6 $or$libresoc.v:181981$11855_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385887,11 +376432,11 @@ module \req_l$69 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187745.7-187745.15" + attribute \src "libresoc.v:181940.7-181940.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -385908,7 +376453,7 @@ module \req_l$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187780$12146 + cell $and $and$libresoc.v:181975$11849 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -385916,10 +376461,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187780$12146_Y + connect \Y $and$libresoc.v:181975$11849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187785$12151 + cell $and $and$libresoc.v:181980$11854 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -385927,34 +376472,34 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187785$12151_Y + connect \Y $and$libresoc.v:181980$11854_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187782$12148 + cell $not $not$libresoc.v:181977$11851 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req - connect \Y $not$libresoc.v:187782$12148_Y + connect \Y $not$libresoc.v:181977$11851_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187784$12150 + cell $not $not$libresoc.v:181979$11853 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:187784$12150_Y + connect \Y $not$libresoc.v:181979$11853_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187787$12153 + cell $not $not$libresoc.v:181982$11856 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:187787$12153_Y + connect \Y $not$libresoc.v:181982$11856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187781$12147 + cell $or $or$libresoc.v:181976$11850 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -385962,10 +376507,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:187781$12147_Y + connect \Y $or$libresoc.v:181976$11850_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187783$12149 + cell $or $or$libresoc.v:181978$11852 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -385973,10 +376518,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:187783$12149_Y + connect \Y $or$libresoc.v:181978$11852_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187786$12152 + cell $or $or$libresoc.v:181981$11855 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -385984,39 +376529,39 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:187786$12152_Y + connect \Y $or$libresoc.v:181981$11855_Y end - attribute \src "libresoc.v:187745.7-187745.20" - process $proc$libresoc.v:187745$12158 + attribute \src "libresoc.v:181940.7-181940.20" + process $proc$libresoc.v:181940$11861 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187767.13-187767.26" - process $proc$libresoc.v:187767$12159 + attribute \src "libresoc.v:181962.13-181962.26" + process $proc$libresoc.v:181962$11862 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:187788.3-187789.27" - process $proc$libresoc.v:187788$12154 + attribute \src "libresoc.v:181983.3-181984.27" + process $proc$libresoc.v:181983$11857 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:187790.3-187798.6" - process $proc$libresoc.v:187790$12155 + attribute \src "libresoc.v:181985.3-181993.6" + process $proc$libresoc.v:181985$11858 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$12156 $1\q_int$next[5:0]$12157 - attribute \src "libresoc.v:187791.5-187791.29" + assign $0\q_int$next[5:0]$11859 $1\q_int$next[5:0]$11860 + attribute \src "libresoc.v:181986.5-181986.29" switch \initial - attribute \src "libresoc.v:187791.9-187791.17" + attribute \src "libresoc.v:181986.9-181986.17" case 1'1 case end @@ -386025,56 +376570,56 @@ module \req_l$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$12157 6'000000 + assign $1\q_int$next[5:0]$11860 6'000000 case - assign $1\q_int$next[5:0]$12157 \$5 + assign $1\q_int$next[5:0]$11860 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$12156 + update \q_int$next $0\q_int$next[5:0]$11859 end - connect \$9 $and$libresoc.v:187780$12146_Y - connect \$11 $or$libresoc.v:187781$12147_Y - connect \$13 $not$libresoc.v:187782$12148_Y - connect \$15 $or$libresoc.v:187783$12149_Y - connect \$1 $not$libresoc.v:187784$12150_Y - connect \$3 $and$libresoc.v:187785$12151_Y - connect \$5 $or$libresoc.v:187786$12152_Y - connect \$7 $not$libresoc.v:187787$12153_Y + connect \$9 $and$libresoc.v:181975$11849_Y + connect \$11 $or$libresoc.v:181976$11850_Y + connect \$13 $not$libresoc.v:181977$11851_Y + connect \$15 $or$libresoc.v:181978$11852_Y + connect \$1 $not$libresoc.v:181979$11853_Y + connect \$3 $and$libresoc.v:181980$11854_Y + connect \$5 $or$libresoc.v:181981$11855_Y + connect \$7 $not$libresoc.v:181982$11856_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:187806.1-187864.10" +attribute \src "libresoc.v:182001.1-182059.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" module \req_l$86 - attribute \src "libresoc.v:187807.7-187807.20" + attribute \src "libresoc.v:182002.7-182002.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187852.3-187860.6" - wire width 4 $0\q_int$next[3:0]$12170 - attribute \src "libresoc.v:187850.3-187851.27" + attribute \src "libresoc.v:182047.3-182055.6" + wire width 4 $0\q_int$next[3:0]$11873 + attribute \src "libresoc.v:182045.3-182046.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:187852.3-187860.6" - wire width 4 $1\q_int$next[3:0]$12171 - attribute \src "libresoc.v:187829.13-187829.25" + attribute \src "libresoc.v:182047.3-182055.6" + wire width 4 $1\q_int$next[3:0]$11874 + attribute \src "libresoc.v:182024.13-182024.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:187842.17-187842.96" - wire width 4 $and$libresoc.v:187842$12160_Y - attribute \src "libresoc.v:187847.17-187847.96" - wire width 4 $and$libresoc.v:187847$12165_Y - attribute \src "libresoc.v:187844.18-187844.93" - wire width 4 $not$libresoc.v:187844$12162_Y - attribute \src "libresoc.v:187846.17-187846.92" - wire width 4 $not$libresoc.v:187846$12164_Y - attribute \src "libresoc.v:187849.17-187849.92" - wire width 4 $not$libresoc.v:187849$12167_Y - attribute \src "libresoc.v:187843.18-187843.98" - wire width 4 $or$libresoc.v:187843$12161_Y - attribute \src "libresoc.v:187845.18-187845.99" - wire width 4 $or$libresoc.v:187845$12163_Y - attribute \src "libresoc.v:187848.17-187848.97" - wire width 4 $or$libresoc.v:187848$12166_Y + attribute \src "libresoc.v:182037.17-182037.96" + wire width 4 $and$libresoc.v:182037$11863_Y + attribute \src "libresoc.v:182042.17-182042.96" + wire width 4 $and$libresoc.v:182042$11868_Y + attribute \src "libresoc.v:182039.18-182039.93" + wire width 4 $not$libresoc.v:182039$11865_Y + attribute \src "libresoc.v:182041.17-182041.92" + wire width 4 $not$libresoc.v:182041$11867_Y + attribute \src "libresoc.v:182044.17-182044.92" + wire width 4 $not$libresoc.v:182044$11870_Y + attribute \src "libresoc.v:182038.18-182038.98" + wire width 4 $or$libresoc.v:182038$11864_Y + attribute \src "libresoc.v:182040.18-182040.99" + wire width 4 $or$libresoc.v:182040$11866_Y + attribute \src "libresoc.v:182043.17-182043.97" + wire width 4 $or$libresoc.v:182043$11869_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386091,11 +376636,11 @@ module \req_l$86 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187807.7-187807.15" + attribute \src "libresoc.v:182002.7-182002.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -386112,7 +376657,7 @@ module \req_l$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:187842$12160 + cell $and $and$libresoc.v:182037$11863 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -386120,10 +376665,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:187842$12160_Y + connect \Y $and$libresoc.v:182037$11863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187847$12165 + cell $and $and$libresoc.v:182042$11868 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -386131,34 +376676,34 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187847$12165_Y + connect \Y $and$libresoc.v:182042$11868_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187844$12162 + cell $not $not$libresoc.v:182039$11865 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:187844$12162_Y + connect \Y $not$libresoc.v:182039$11865_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187846$12164 + cell $not $not$libresoc.v:182041$11867 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:187846$12164_Y + connect \Y $not$libresoc.v:182041$11867_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:187849$12167 + cell $not $not$libresoc.v:182044$11870 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:187849$12167_Y + connect \Y $not$libresoc.v:182044$11870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:187843$12161 + cell $or $or$libresoc.v:182038$11864 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -386166,10 +376711,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:187843$12161_Y + connect \Y $or$libresoc.v:182038$11864_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187845$12163 + cell $or $or$libresoc.v:182040$11866 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -386177,10 +376722,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:187845$12163_Y + connect \Y $or$libresoc.v:182040$11866_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187848$12166 + cell $or $or$libresoc.v:182043$11869 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -386188,39 +376733,39 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:187848$12166_Y + connect \Y $or$libresoc.v:182043$11869_Y end - attribute \src "libresoc.v:187807.7-187807.20" - process $proc$libresoc.v:187807$12172 + attribute \src "libresoc.v:182002.7-182002.20" + process $proc$libresoc.v:182002$11875 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187829.13-187829.25" - process $proc$libresoc.v:187829$12173 + attribute \src "libresoc.v:182024.13-182024.25" + process $proc$libresoc.v:182024$11876 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:187850.3-187851.27" - process $proc$libresoc.v:187850$12168 + attribute \src "libresoc.v:182045.3-182046.27" + process $proc$libresoc.v:182045$11871 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:187852.3-187860.6" - process $proc$libresoc.v:187852$12169 + attribute \src "libresoc.v:182047.3-182055.6" + process $proc$libresoc.v:182047$11872 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$12170 $1\q_int$next[3:0]$12171 - attribute \src "libresoc.v:187853.5-187853.29" + assign $0\q_int$next[3:0]$11873 $1\q_int$next[3:0]$11874 + attribute \src "libresoc.v:182048.5-182048.29" switch \initial - attribute \src "libresoc.v:187853.9-187853.17" + attribute \src "libresoc.v:182048.9-182048.17" case 1'1 case end @@ -386229,50 +376774,50 @@ module \req_l$86 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$12171 4'0000 + assign $1\q_int$next[3:0]$11874 4'0000 case - assign $1\q_int$next[3:0]$12171 \$5 + assign $1\q_int$next[3:0]$11874 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$12170 + update \q_int$next $0\q_int$next[3:0]$11873 end - connect \$9 $and$libresoc.v:187842$12160_Y - connect \$11 $or$libresoc.v:187843$12161_Y - connect \$13 $not$libresoc.v:187844$12162_Y - connect \$15 $or$libresoc.v:187845$12163_Y - connect \$1 $not$libresoc.v:187846$12164_Y - connect \$3 $and$libresoc.v:187847$12165_Y - connect \$5 $or$libresoc.v:187848$12166_Y - connect \$7 $not$libresoc.v:187849$12167_Y + connect \$9 $and$libresoc.v:182037$11863_Y + connect \$11 $or$libresoc.v:182038$11864_Y + connect \$13 $not$libresoc.v:182039$11865_Y + connect \$15 $or$libresoc.v:182040$11866_Y + connect \$1 $not$libresoc.v:182041$11867_Y + connect \$3 $and$libresoc.v:182042$11868_Y + connect \$5 $or$libresoc.v:182043$11869_Y + connect \$7 $not$libresoc.v:182044$11870_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:187868.1-187917.10" +attribute \src "libresoc.v:182063.1-182112.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l - attribute \src "libresoc.v:187869.7-187869.20" + attribute \src "libresoc.v:182064.7-182064.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187905.3-187913.6" - wire $0\q_int$next[0:0]$12181 - attribute \src "libresoc.v:187903.3-187904.27" + attribute \src "libresoc.v:182100.3-182108.6" + wire $0\q_int$next[0:0]$11884 + attribute \src "libresoc.v:182098.3-182099.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:187905.3-187913.6" - wire $1\q_int$next[0:0]$12182 - attribute \src "libresoc.v:187885.7-187885.19" + attribute \src "libresoc.v:182100.3-182108.6" + wire $1\q_int$next[0:0]$11885 + attribute \src "libresoc.v:182080.7-182080.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:187900.17-187900.96" - wire $and$libresoc.v:187900$12176_Y - attribute \src "libresoc.v:187899.17-187899.94" - wire $not$libresoc.v:187899$12175_Y - attribute \src "libresoc.v:187902.17-187902.94" - wire $not$libresoc.v:187902$12178_Y - attribute \src "libresoc.v:187898.17-187898.100" - wire $or$libresoc.v:187898$12174_Y - attribute \src "libresoc.v:187901.17-187901.99" - wire $or$libresoc.v:187901$12177_Y + attribute \src "libresoc.v:182095.17-182095.96" + wire $and$libresoc.v:182095$11879_Y + attribute \src "libresoc.v:182094.17-182094.94" + wire $not$libresoc.v:182094$11878_Y + attribute \src "libresoc.v:182097.17-182097.94" + wire $not$libresoc.v:182097$11881_Y + attribute \src "libresoc.v:182093.17-182093.100" + wire $or$libresoc.v:182093$11877_Y + attribute \src "libresoc.v:182096.17-182096.99" + wire $or$libresoc.v:182096$11880_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -386283,11 +376828,11 @@ module \reset_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187869.7-187869.15" + attribute \src "libresoc.v:182064.7-182064.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386304,7 +376849,7 @@ module \reset_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187900$12176 + cell $and $and$libresoc.v:182095$11879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386312,26 +376857,26 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187900$12176_Y + connect \Y $and$libresoc.v:182095$11879_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187899$12175 + cell $not $not$libresoc.v:182094$11878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:187899$12175_Y + connect \Y $not$libresoc.v:182094$11878_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187902$12178 + cell $not $not$libresoc.v:182097$11881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:187902$12178_Y + connect \Y $not$libresoc.v:182097$11881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187898$12174 + cell $or $or$libresoc.v:182093$11877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386339,10 +376884,10 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:187898$12174_Y + connect \Y $or$libresoc.v:182093$11877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187901$12177 + cell $or $or$libresoc.v:182096$11880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386350,39 +376895,39 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:187901$12177_Y + connect \Y $or$libresoc.v:182096$11880_Y end - attribute \src "libresoc.v:187869.7-187869.20" - process $proc$libresoc.v:187869$12183 + attribute \src "libresoc.v:182064.7-182064.20" + process $proc$libresoc.v:182064$11886 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187885.7-187885.19" - process $proc$libresoc.v:187885$12184 + attribute \src "libresoc.v:182080.7-182080.19" + process $proc$libresoc.v:182080$11887 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:187903.3-187904.27" - process $proc$libresoc.v:187903$12179 + attribute \src "libresoc.v:182098.3-182099.27" + process $proc$libresoc.v:182098$11882 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:187905.3-187913.6" - process $proc$libresoc.v:187905$12180 + attribute \src "libresoc.v:182100.3-182108.6" + process $proc$libresoc.v:182100$11883 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12181 $1\q_int$next[0:0]$12182 - attribute \src "libresoc.v:187906.5-187906.29" + assign $0\q_int$next[0:0]$11884 $1\q_int$next[0:0]$11885 + attribute \src "libresoc.v:182101.5-182101.29" switch \initial - attribute \src "libresoc.v:187906.9-187906.17" + attribute \src "libresoc.v:182101.9-182101.17" case 1'1 case end @@ -386391,47 +376936,47 @@ module \reset_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12182 1'0 + assign $1\q_int$next[0:0]$11885 1'0 case - assign $1\q_int$next[0:0]$12182 \$5 + assign $1\q_int$next[0:0]$11885 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12181 + update \q_int$next $0\q_int$next[0:0]$11884 end - connect \$9 $or$libresoc.v:187898$12174_Y - connect \$1 $not$libresoc.v:187899$12175_Y - connect \$3 $and$libresoc.v:187900$12176_Y - connect \$5 $or$libresoc.v:187901$12177_Y - connect \$7 $not$libresoc.v:187902$12178_Y + connect \$9 $or$libresoc.v:182093$11877_Y + connect \$1 $not$libresoc.v:182094$11878_Y + connect \$3 $and$libresoc.v:182095$11879_Y + connect \$5 $or$libresoc.v:182096$11880_Y + connect \$7 $not$libresoc.v:182097$11881_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:187921.1-187970.10" +attribute \src "libresoc.v:182116.1-182165.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" module \reset_l$131 - attribute \src "libresoc.v:187922.7-187922.20" + attribute \src "libresoc.v:182117.7-182117.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187958.3-187966.6" - wire $0\q_int$next[0:0]$12192 - attribute \src "libresoc.v:187956.3-187957.27" + attribute \src "libresoc.v:182153.3-182161.6" + wire $0\q_int$next[0:0]$11895 + attribute \src "libresoc.v:182151.3-182152.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:187958.3-187966.6" - wire $1\q_int$next[0:0]$12193 - attribute \src "libresoc.v:187938.7-187938.19" + attribute \src "libresoc.v:182153.3-182161.6" + wire $1\q_int$next[0:0]$11896 + attribute \src "libresoc.v:182133.7-182133.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:187953.17-187953.96" - wire $and$libresoc.v:187953$12187_Y - attribute \src "libresoc.v:187952.17-187952.94" - wire $not$libresoc.v:187952$12186_Y - attribute \src "libresoc.v:187955.17-187955.94" - wire $not$libresoc.v:187955$12189_Y - attribute \src "libresoc.v:187951.17-187951.100" - wire $or$libresoc.v:187951$12185_Y - attribute \src "libresoc.v:187954.17-187954.99" - wire $or$libresoc.v:187954$12188_Y + attribute \src "libresoc.v:182148.17-182148.96" + wire $and$libresoc.v:182148$11890_Y + attribute \src "libresoc.v:182147.17-182147.94" + wire $not$libresoc.v:182147$11889_Y + attribute \src "libresoc.v:182150.17-182150.94" + wire $not$libresoc.v:182150$11892_Y + attribute \src "libresoc.v:182146.17-182146.100" + wire $or$libresoc.v:182146$11888_Y + attribute \src "libresoc.v:182149.17-182149.99" + wire $or$libresoc.v:182149$11891_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -386442,11 +376987,11 @@ module \reset_l$131 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:187922.7-187922.15" + attribute \src "libresoc.v:182117.7-182117.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386463,7 +377008,7 @@ module \reset_l$131 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:187953$12187 + cell $and $and$libresoc.v:182148$11890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386471,26 +377016,26 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:187953$12187_Y + connect \Y $and$libresoc.v:182148$11890_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:187952$12186 + cell $not $not$libresoc.v:182147$11889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:187952$12186_Y + connect \Y $not$libresoc.v:182147$11889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:187955$12189 + cell $not $not$libresoc.v:182150$11892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:187955$12189_Y + connect \Y $not$libresoc.v:182150$11892_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:187951$12185 + cell $or $or$libresoc.v:182146$11888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386498,10 +377043,10 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:187951$12185_Y + connect \Y $or$libresoc.v:182146$11888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:187954$12188 + cell $or $or$libresoc.v:182149$11891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386509,39 +377054,39 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:187954$12188_Y + connect \Y $or$libresoc.v:182149$11891_Y end - attribute \src "libresoc.v:187922.7-187922.20" - process $proc$libresoc.v:187922$12194 + attribute \src "libresoc.v:182117.7-182117.20" + process $proc$libresoc.v:182117$11897 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187938.7-187938.19" - process $proc$libresoc.v:187938$12195 + attribute \src "libresoc.v:182133.7-182133.19" + process $proc$libresoc.v:182133$11898 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:187956.3-187957.27" - process $proc$libresoc.v:187956$12190 + attribute \src "libresoc.v:182151.3-182152.27" + process $proc$libresoc.v:182151$11893 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:187958.3-187966.6" - process $proc$libresoc.v:187958$12191 + attribute \src "libresoc.v:182153.3-182161.6" + process $proc$libresoc.v:182153$11894 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12192 $1\q_int$next[0:0]$12193 - attribute \src "libresoc.v:187959.5-187959.29" + assign $0\q_int$next[0:0]$11895 $1\q_int$next[0:0]$11896 + attribute \src "libresoc.v:182154.5-182154.29" switch \initial - attribute \src "libresoc.v:187959.9-187959.17" + attribute \src "libresoc.v:182154.9-182154.17" case 1'1 case end @@ -386550,287 +377095,287 @@ module \reset_l$131 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12193 1'0 + assign $1\q_int$next[0:0]$11896 1'0 case - assign $1\q_int$next[0:0]$12193 \$5 + assign $1\q_int$next[0:0]$11896 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12192 + update \q_int$next $0\q_int$next[0:0]$11895 end - connect \$9 $or$libresoc.v:187951$12185_Y - connect \$1 $not$libresoc.v:187952$12186_Y - connect \$3 $and$libresoc.v:187953$12187_Y - connect \$5 $or$libresoc.v:187954$12188_Y - connect \$7 $not$libresoc.v:187955$12189_Y + connect \$9 $or$libresoc.v:182146$11888_Y + connect \$1 $not$libresoc.v:182147$11889_Y + connect \$3 $and$libresoc.v:182148$11890_Y + connect \$5 $or$libresoc.v:182149$11891_Y + connect \$7 $not$libresoc.v:182150$11892_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:187974.1-188561.10" +attribute \src "libresoc.v:182169.1-182756.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask - attribute \src "libresoc.v:187975.7-187975.20" + attribute \src "libresoc.v:182170.7-182170.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $10\mask[9:9] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $11\mask[10:10] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $12\mask[11:11] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $13\mask[12:12] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $14\mask[13:13] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $15\mask[14:14] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $16\mask[15:15] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $17\mask[16:16] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $18\mask[17:17] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $19\mask[18:18] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $1\mask[0:0] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $20\mask[19:19] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $21\mask[20:20] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $22\mask[21:21] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $23\mask[22:22] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $24\mask[23:23] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $25\mask[24:24] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $26\mask[25:25] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $27\mask[26:26] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $28\mask[27:27] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $29\mask[28:28] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $2\mask[1:1] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $30\mask[29:29] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $31\mask[30:30] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $32\mask[31:31] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $33\mask[32:32] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $34\mask[33:33] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $35\mask[34:34] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $36\mask[35:35] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $37\mask[36:36] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $38\mask[37:37] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $39\mask[38:38] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $3\mask[2:2] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $40\mask[39:39] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $41\mask[40:40] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $42\mask[41:41] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $43\mask[42:42] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $44\mask[43:43] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $45\mask[44:44] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $46\mask[45:45] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $47\mask[46:46] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $48\mask[47:47] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $49\mask[48:48] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $4\mask[3:3] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $50\mask[49:49] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $51\mask[50:50] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $52\mask[51:51] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $53\mask[52:52] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $54\mask[53:53] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $55\mask[54:54] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $56\mask[55:55] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $57\mask[56:56] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $58\mask[57:57] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $59\mask[58:58] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $5\mask[4:4] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $60\mask[59:59] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $61\mask[60:60] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $62\mask[61:61] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $63\mask[62:62] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $64\mask[63:63] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $6\mask[5:5] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $7\mask[6:6] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $8\mask[7:7] - attribute \src "libresoc.v:188173.3-188560.6" + attribute \src "libresoc.v:182368.3-182755.6" wire $9\mask[8:8] - attribute \src "libresoc.v:188109.17-188109.96" - wire $gt$libresoc.v:188109$12196_Y - attribute \src "libresoc.v:188110.18-188110.98" - wire $gt$libresoc.v:188110$12197_Y - attribute \src "libresoc.v:188111.19-188111.99" - wire $gt$libresoc.v:188111$12198_Y - attribute \src "libresoc.v:188112.19-188112.99" - wire $gt$libresoc.v:188112$12199_Y - attribute \src "libresoc.v:188113.19-188113.99" - wire $gt$libresoc.v:188113$12200_Y - attribute \src "libresoc.v:188114.19-188114.99" - wire $gt$libresoc.v:188114$12201_Y - attribute \src "libresoc.v:188115.19-188115.99" - wire $gt$libresoc.v:188115$12202_Y - attribute \src "libresoc.v:188116.19-188116.99" - wire $gt$libresoc.v:188116$12203_Y - attribute \src "libresoc.v:188117.19-188117.99" - wire $gt$libresoc.v:188117$12204_Y - attribute \src "libresoc.v:188118.19-188118.99" - wire $gt$libresoc.v:188118$12205_Y - attribute \src "libresoc.v:188119.19-188119.99" - wire $gt$libresoc.v:188119$12206_Y - attribute \src "libresoc.v:188120.18-188120.97" - wire $gt$libresoc.v:188120$12207_Y - attribute \src "libresoc.v:188121.19-188121.99" - wire $gt$libresoc.v:188121$12208_Y - attribute \src "libresoc.v:188122.19-188122.99" - wire $gt$libresoc.v:188122$12209_Y - attribute \src "libresoc.v:188123.19-188123.99" - wire $gt$libresoc.v:188123$12210_Y - attribute \src "libresoc.v:188124.19-188124.99" - wire $gt$libresoc.v:188124$12211_Y - attribute \src "libresoc.v:188125.19-188125.99" - wire $gt$libresoc.v:188125$12212_Y - attribute \src "libresoc.v:188126.18-188126.97" - wire $gt$libresoc.v:188126$12213_Y - attribute \src "libresoc.v:188127.18-188127.97" - wire $gt$libresoc.v:188127$12214_Y - attribute \src "libresoc.v:188128.18-188128.97" - wire $gt$libresoc.v:188128$12215_Y - attribute \src "libresoc.v:188129.17-188129.96" - wire $gt$libresoc.v:188129$12216_Y - attribute \src "libresoc.v:188130.18-188130.97" - wire $gt$libresoc.v:188130$12217_Y - attribute \src "libresoc.v:188131.18-188131.97" - wire $gt$libresoc.v:188131$12218_Y - attribute \src "libresoc.v:188132.18-188132.97" - wire $gt$libresoc.v:188132$12219_Y - attribute \src "libresoc.v:188133.18-188133.97" - wire $gt$libresoc.v:188133$12220_Y - attribute \src "libresoc.v:188134.18-188134.97" - wire $gt$libresoc.v:188134$12221_Y - attribute \src "libresoc.v:188135.18-188135.97" - wire $gt$libresoc.v:188135$12222_Y - attribute \src "libresoc.v:188136.18-188136.97" - wire $gt$libresoc.v:188136$12223_Y - attribute \src "libresoc.v:188137.18-188137.98" - wire $gt$libresoc.v:188137$12224_Y - attribute \src "libresoc.v:188138.18-188138.98" - wire $gt$libresoc.v:188138$12225_Y - attribute \src "libresoc.v:188139.18-188139.98" - wire $gt$libresoc.v:188139$12226_Y - attribute \src "libresoc.v:188140.17-188140.96" - wire $gt$libresoc.v:188140$12227_Y - attribute \src "libresoc.v:188141.18-188141.98" - wire $gt$libresoc.v:188141$12228_Y - attribute \src "libresoc.v:188142.18-188142.98" - wire $gt$libresoc.v:188142$12229_Y - attribute \src "libresoc.v:188143.18-188143.98" - wire $gt$libresoc.v:188143$12230_Y - attribute \src "libresoc.v:188144.18-188144.98" - wire $gt$libresoc.v:188144$12231_Y - attribute \src "libresoc.v:188145.18-188145.98" - wire $gt$libresoc.v:188145$12232_Y - attribute \src "libresoc.v:188146.18-188146.98" - wire $gt$libresoc.v:188146$12233_Y - attribute \src "libresoc.v:188147.18-188147.98" - wire $gt$libresoc.v:188147$12234_Y - attribute \src "libresoc.v:188148.18-188148.98" - wire $gt$libresoc.v:188148$12235_Y - attribute \src "libresoc.v:188149.18-188149.98" - wire $gt$libresoc.v:188149$12236_Y - attribute \src "libresoc.v:188150.18-188150.98" - wire $gt$libresoc.v:188150$12237_Y - attribute \src "libresoc.v:188151.17-188151.96" - wire $gt$libresoc.v:188151$12238_Y - attribute \src "libresoc.v:188152.18-188152.98" - wire $gt$libresoc.v:188152$12239_Y - attribute \src "libresoc.v:188153.18-188153.98" - wire $gt$libresoc.v:188153$12240_Y - attribute \src "libresoc.v:188154.18-188154.98" - wire $gt$libresoc.v:188154$12241_Y - attribute \src "libresoc.v:188155.18-188155.98" - wire $gt$libresoc.v:188155$12242_Y - attribute \src "libresoc.v:188156.18-188156.98" - wire $gt$libresoc.v:188156$12243_Y - attribute \src "libresoc.v:188157.18-188157.98" - wire $gt$libresoc.v:188157$12244_Y - attribute \src "libresoc.v:188158.18-188158.98" - wire $gt$libresoc.v:188158$12245_Y - attribute \src "libresoc.v:188159.18-188159.98" - wire $gt$libresoc.v:188159$12246_Y - attribute \src "libresoc.v:188160.18-188160.98" - wire $gt$libresoc.v:188160$12247_Y - attribute \src "libresoc.v:188161.18-188161.98" - wire $gt$libresoc.v:188161$12248_Y - attribute \src "libresoc.v:188162.17-188162.96" - wire $gt$libresoc.v:188162$12249_Y - attribute \src "libresoc.v:188163.18-188163.98" - wire $gt$libresoc.v:188163$12250_Y - attribute \src "libresoc.v:188164.18-188164.98" - wire $gt$libresoc.v:188164$12251_Y - attribute \src "libresoc.v:188165.18-188165.98" - wire $gt$libresoc.v:188165$12252_Y - attribute \src "libresoc.v:188166.18-188166.98" - wire $gt$libresoc.v:188166$12253_Y - attribute \src "libresoc.v:188167.18-188167.98" - wire $gt$libresoc.v:188167$12254_Y - attribute \src "libresoc.v:188168.18-188168.98" - wire $gt$libresoc.v:188168$12255_Y - attribute \src "libresoc.v:188169.18-188169.98" - wire $gt$libresoc.v:188169$12256_Y - attribute \src "libresoc.v:188170.18-188170.98" - wire $gt$libresoc.v:188170$12257_Y - attribute \src "libresoc.v:188171.18-188171.98" - wire $gt$libresoc.v:188171$12258_Y - attribute \src "libresoc.v:188172.18-188172.98" - wire $gt$libresoc.v:188172$12259_Y + attribute \src "libresoc.v:182304.17-182304.96" + wire $gt$libresoc.v:182304$11899_Y + attribute \src "libresoc.v:182305.18-182305.98" + wire $gt$libresoc.v:182305$11900_Y + attribute \src "libresoc.v:182306.19-182306.99" + wire $gt$libresoc.v:182306$11901_Y + attribute \src "libresoc.v:182307.19-182307.99" + wire $gt$libresoc.v:182307$11902_Y + attribute \src "libresoc.v:182308.19-182308.99" + wire $gt$libresoc.v:182308$11903_Y + attribute \src "libresoc.v:182309.19-182309.99" + wire $gt$libresoc.v:182309$11904_Y + attribute \src "libresoc.v:182310.19-182310.99" + wire $gt$libresoc.v:182310$11905_Y + attribute \src "libresoc.v:182311.19-182311.99" + wire $gt$libresoc.v:182311$11906_Y + attribute \src "libresoc.v:182312.19-182312.99" + wire $gt$libresoc.v:182312$11907_Y + attribute \src "libresoc.v:182313.19-182313.99" + wire $gt$libresoc.v:182313$11908_Y + attribute \src "libresoc.v:182314.19-182314.99" + wire $gt$libresoc.v:182314$11909_Y + attribute \src "libresoc.v:182315.18-182315.97" + wire $gt$libresoc.v:182315$11910_Y + attribute \src "libresoc.v:182316.19-182316.99" + wire $gt$libresoc.v:182316$11911_Y + attribute \src "libresoc.v:182317.19-182317.99" + wire $gt$libresoc.v:182317$11912_Y + attribute \src "libresoc.v:182318.19-182318.99" + wire $gt$libresoc.v:182318$11913_Y + attribute \src "libresoc.v:182319.19-182319.99" + wire $gt$libresoc.v:182319$11914_Y + attribute \src "libresoc.v:182320.19-182320.99" + wire $gt$libresoc.v:182320$11915_Y + attribute \src "libresoc.v:182321.18-182321.97" + wire $gt$libresoc.v:182321$11916_Y + attribute \src "libresoc.v:182322.18-182322.97" + wire $gt$libresoc.v:182322$11917_Y + attribute \src "libresoc.v:182323.18-182323.97" + wire $gt$libresoc.v:182323$11918_Y + attribute \src "libresoc.v:182324.17-182324.96" + wire $gt$libresoc.v:182324$11919_Y + attribute \src "libresoc.v:182325.18-182325.97" + wire $gt$libresoc.v:182325$11920_Y + attribute \src "libresoc.v:182326.18-182326.97" + wire $gt$libresoc.v:182326$11921_Y + attribute \src "libresoc.v:182327.18-182327.97" + wire $gt$libresoc.v:182327$11922_Y + attribute \src "libresoc.v:182328.18-182328.97" + wire $gt$libresoc.v:182328$11923_Y + attribute \src "libresoc.v:182329.18-182329.97" + wire $gt$libresoc.v:182329$11924_Y + attribute \src "libresoc.v:182330.18-182330.97" + wire $gt$libresoc.v:182330$11925_Y + attribute \src "libresoc.v:182331.18-182331.97" + wire $gt$libresoc.v:182331$11926_Y + attribute \src "libresoc.v:182332.18-182332.98" + wire $gt$libresoc.v:182332$11927_Y + attribute \src "libresoc.v:182333.18-182333.98" + wire $gt$libresoc.v:182333$11928_Y + attribute \src "libresoc.v:182334.18-182334.98" + wire $gt$libresoc.v:182334$11929_Y + attribute \src "libresoc.v:182335.17-182335.96" + wire $gt$libresoc.v:182335$11930_Y + attribute \src "libresoc.v:182336.18-182336.98" + wire $gt$libresoc.v:182336$11931_Y + attribute \src "libresoc.v:182337.18-182337.98" + wire $gt$libresoc.v:182337$11932_Y + attribute \src "libresoc.v:182338.18-182338.98" + wire $gt$libresoc.v:182338$11933_Y + attribute \src "libresoc.v:182339.18-182339.98" + wire $gt$libresoc.v:182339$11934_Y + attribute \src "libresoc.v:182340.18-182340.98" + wire $gt$libresoc.v:182340$11935_Y + attribute \src "libresoc.v:182341.18-182341.98" + wire $gt$libresoc.v:182341$11936_Y + attribute \src "libresoc.v:182342.18-182342.98" + wire $gt$libresoc.v:182342$11937_Y + attribute \src "libresoc.v:182343.18-182343.98" + wire $gt$libresoc.v:182343$11938_Y + attribute \src "libresoc.v:182344.18-182344.98" + wire $gt$libresoc.v:182344$11939_Y + attribute \src "libresoc.v:182345.18-182345.98" + wire $gt$libresoc.v:182345$11940_Y + attribute \src "libresoc.v:182346.17-182346.96" + wire $gt$libresoc.v:182346$11941_Y + attribute \src "libresoc.v:182347.18-182347.98" + wire $gt$libresoc.v:182347$11942_Y + attribute \src "libresoc.v:182348.18-182348.98" + wire $gt$libresoc.v:182348$11943_Y + attribute \src "libresoc.v:182349.18-182349.98" + wire $gt$libresoc.v:182349$11944_Y + attribute \src "libresoc.v:182350.18-182350.98" + wire $gt$libresoc.v:182350$11945_Y + attribute \src "libresoc.v:182351.18-182351.98" + wire $gt$libresoc.v:182351$11946_Y + attribute \src "libresoc.v:182352.18-182352.98" + wire $gt$libresoc.v:182352$11947_Y + attribute \src "libresoc.v:182353.18-182353.98" + wire $gt$libresoc.v:182353$11948_Y + attribute \src "libresoc.v:182354.18-182354.98" + wire $gt$libresoc.v:182354$11949_Y + attribute \src "libresoc.v:182355.18-182355.98" + wire $gt$libresoc.v:182355$11950_Y + attribute \src "libresoc.v:182356.18-182356.98" + wire $gt$libresoc.v:182356$11951_Y + attribute \src "libresoc.v:182357.17-182357.96" + wire $gt$libresoc.v:182357$11952_Y + attribute \src "libresoc.v:182358.18-182358.98" + wire $gt$libresoc.v:182358$11953_Y + attribute \src "libresoc.v:182359.18-182359.98" + wire $gt$libresoc.v:182359$11954_Y + attribute \src "libresoc.v:182360.18-182360.98" + wire $gt$libresoc.v:182360$11955_Y + attribute \src "libresoc.v:182361.18-182361.98" + wire $gt$libresoc.v:182361$11956_Y + attribute \src "libresoc.v:182362.18-182362.98" + wire $gt$libresoc.v:182362$11957_Y + attribute \src "libresoc.v:182363.18-182363.98" + wire $gt$libresoc.v:182363$11958_Y + attribute \src "libresoc.v:182364.18-182364.98" + wire $gt$libresoc.v:182364$11959_Y + attribute \src "libresoc.v:182365.18-182365.98" + wire $gt$libresoc.v:182365$11960_Y + attribute \src "libresoc.v:182366.18-182366.98" + wire $gt$libresoc.v:182366$11961_Y + attribute \src "libresoc.v:182367.18-182367.98" + wire $gt$libresoc.v:182367$11962_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -386959,14 +377504,14 @@ module \right_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:187975.7-187975.15" + attribute \src "libresoc.v:182170.7-182170.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188109$12196 + cell $gt $gt$libresoc.v:182304$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -386974,10 +377519,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:188109$12196_Y + connect \Y $gt$libresoc.v:182304$11899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188110$12197 + cell $gt $gt$libresoc.v:182305$11900 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -386985,10 +377530,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:188110$12197_Y + connect \Y $gt$libresoc.v:182305$11900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188111$12198 + cell $gt $gt$libresoc.v:182306$11901 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -386996,10 +377541,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:188111$12198_Y + connect \Y $gt$libresoc.v:182306$11901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188112$12199 + cell $gt $gt$libresoc.v:182307$11902 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387007,10 +377552,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:188112$12199_Y + connect \Y $gt$libresoc.v:182307$11902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188113$12200 + cell $gt $gt$libresoc.v:182308$11903 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387018,10 +377563,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:188113$12200_Y + connect \Y $gt$libresoc.v:182308$11903_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188114$12201 + cell $gt $gt$libresoc.v:182309$11904 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387029,10 +377574,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:188114$12201_Y + connect \Y $gt$libresoc.v:182309$11904_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188115$12202 + cell $gt $gt$libresoc.v:182310$11905 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387040,10 +377585,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:188115$12202_Y + connect \Y $gt$libresoc.v:182310$11905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188116$12203 + cell $gt $gt$libresoc.v:182311$11906 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387051,10 +377596,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:188116$12203_Y + connect \Y $gt$libresoc.v:182311$11906_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188117$12204 + cell $gt $gt$libresoc.v:182312$11907 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387062,10 +377607,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:188117$12204_Y + connect \Y $gt$libresoc.v:182312$11907_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188118$12205 + cell $gt $gt$libresoc.v:182313$11908 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387073,10 +377618,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:188118$12205_Y + connect \Y $gt$libresoc.v:182313$11908_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188119$12206 + cell $gt $gt$libresoc.v:182314$11909 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387084,10 +377629,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:188119$12206_Y + connect \Y $gt$libresoc.v:182314$11909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188120$12207 + cell $gt $gt$libresoc.v:182315$11910 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387095,10 +377640,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:188120$12207_Y + connect \Y $gt$libresoc.v:182315$11910_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188121$12208 + cell $gt $gt$libresoc.v:182316$11911 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387106,10 +377651,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:188121$12208_Y + connect \Y $gt$libresoc.v:182316$11911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188122$12209 + cell $gt $gt$libresoc.v:182317$11912 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387117,10 +377662,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:188122$12209_Y + connect \Y $gt$libresoc.v:182317$11912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188123$12210 + cell $gt $gt$libresoc.v:182318$11913 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387128,10 +377673,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:188123$12210_Y + connect \Y $gt$libresoc.v:182318$11913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188124$12211 + cell $gt $gt$libresoc.v:182319$11914 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387139,10 +377684,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:188124$12211_Y + connect \Y $gt$libresoc.v:182319$11914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188125$12212 + cell $gt $gt$libresoc.v:182320$11915 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387150,10 +377695,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:188125$12212_Y + connect \Y $gt$libresoc.v:182320$11915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188126$12213 + cell $gt $gt$libresoc.v:182321$11916 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387161,10 +377706,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:188126$12213_Y + connect \Y $gt$libresoc.v:182321$11916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188127$12214 + cell $gt $gt$libresoc.v:182322$11917 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387172,10 +377717,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:188127$12214_Y + connect \Y $gt$libresoc.v:182322$11917_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188128$12215 + cell $gt $gt$libresoc.v:182323$11918 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387183,10 +377728,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:188128$12215_Y + connect \Y $gt$libresoc.v:182323$11918_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188129$12216 + cell $gt $gt$libresoc.v:182324$11919 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387194,10 +377739,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:188129$12216_Y + connect \Y $gt$libresoc.v:182324$11919_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188130$12217 + cell $gt $gt$libresoc.v:182325$11920 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387205,10 +377750,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:188130$12217_Y + connect \Y $gt$libresoc.v:182325$11920_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188131$12218 + cell $gt $gt$libresoc.v:182326$11921 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387216,10 +377761,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:188131$12218_Y + connect \Y $gt$libresoc.v:182326$11921_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188132$12219 + cell $gt $gt$libresoc.v:182327$11922 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387227,10 +377772,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:188132$12219_Y + connect \Y $gt$libresoc.v:182327$11922_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188133$12220 + cell $gt $gt$libresoc.v:182328$11923 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387238,10 +377783,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:188133$12220_Y + connect \Y $gt$libresoc.v:182328$11923_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188134$12221 + cell $gt $gt$libresoc.v:182329$11924 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387249,10 +377794,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:188134$12221_Y + connect \Y $gt$libresoc.v:182329$11924_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188135$12222 + cell $gt $gt$libresoc.v:182330$11925 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387260,10 +377805,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:188135$12222_Y + connect \Y $gt$libresoc.v:182330$11925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188136$12223 + cell $gt $gt$libresoc.v:182331$11926 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387271,10 +377816,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:188136$12223_Y + connect \Y $gt$libresoc.v:182331$11926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188137$12224 + cell $gt $gt$libresoc.v:182332$11927 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387282,10 +377827,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:188137$12224_Y + connect \Y $gt$libresoc.v:182332$11927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188138$12225 + cell $gt $gt$libresoc.v:182333$11928 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387293,10 +377838,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:188138$12225_Y + connect \Y $gt$libresoc.v:182333$11928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188139$12226 + cell $gt $gt$libresoc.v:182334$11929 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387304,10 +377849,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:188139$12226_Y + connect \Y $gt$libresoc.v:182334$11929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188140$12227 + cell $gt $gt$libresoc.v:182335$11930 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387315,10 +377860,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:188140$12227_Y + connect \Y $gt$libresoc.v:182335$11930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188141$12228 + cell $gt $gt$libresoc.v:182336$11931 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387326,10 +377871,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:188141$12228_Y + connect \Y $gt$libresoc.v:182336$11931_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188142$12229 + cell $gt $gt$libresoc.v:182337$11932 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387337,10 +377882,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:188142$12229_Y + connect \Y $gt$libresoc.v:182337$11932_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188143$12230 + cell $gt $gt$libresoc.v:182338$11933 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387348,10 +377893,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:188143$12230_Y + connect \Y $gt$libresoc.v:182338$11933_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188144$12231 + cell $gt $gt$libresoc.v:182339$11934 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387359,10 +377904,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:188144$12231_Y + connect \Y $gt$libresoc.v:182339$11934_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188145$12232 + cell $gt $gt$libresoc.v:182340$11935 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387370,10 +377915,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:188145$12232_Y + connect \Y $gt$libresoc.v:182340$11935_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188146$12233 + cell $gt $gt$libresoc.v:182341$11936 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387381,10 +377926,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:188146$12233_Y + connect \Y $gt$libresoc.v:182341$11936_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188147$12234 + cell $gt $gt$libresoc.v:182342$11937 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387392,10 +377937,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:188147$12234_Y + connect \Y $gt$libresoc.v:182342$11937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188148$12235 + cell $gt $gt$libresoc.v:182343$11938 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387403,10 +377948,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:188148$12235_Y + connect \Y $gt$libresoc.v:182343$11938_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188149$12236 + cell $gt $gt$libresoc.v:182344$11939 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387414,10 +377959,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:188149$12236_Y + connect \Y $gt$libresoc.v:182344$11939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188150$12237 + cell $gt $gt$libresoc.v:182345$11940 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387425,10 +377970,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:188150$12237_Y + connect \Y $gt$libresoc.v:182345$11940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188151$12238 + cell $gt $gt$libresoc.v:182346$11941 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387436,10 +377981,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:188151$12238_Y + connect \Y $gt$libresoc.v:182346$11941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188152$12239 + cell $gt $gt$libresoc.v:182347$11942 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387447,10 +377992,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:188152$12239_Y + connect \Y $gt$libresoc.v:182347$11942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188153$12240 + cell $gt $gt$libresoc.v:182348$11943 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387458,10 +378003,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:188153$12240_Y + connect \Y $gt$libresoc.v:182348$11943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188154$12241 + cell $gt $gt$libresoc.v:182349$11944 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387469,10 +378014,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:188154$12241_Y + connect \Y $gt$libresoc.v:182349$11944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188155$12242 + cell $gt $gt$libresoc.v:182350$11945 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387480,10 +378025,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:188155$12242_Y + connect \Y $gt$libresoc.v:182350$11945_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188156$12243 + cell $gt $gt$libresoc.v:182351$11946 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387491,10 +378036,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:188156$12243_Y + connect \Y $gt$libresoc.v:182351$11946_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188157$12244 + cell $gt $gt$libresoc.v:182352$11947 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387502,10 +378047,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:188157$12244_Y + connect \Y $gt$libresoc.v:182352$11947_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188158$12245 + cell $gt $gt$libresoc.v:182353$11948 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387513,10 +378058,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:188158$12245_Y + connect \Y $gt$libresoc.v:182353$11948_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188159$12246 + cell $gt $gt$libresoc.v:182354$11949 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387524,10 +378069,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:188159$12246_Y + connect \Y $gt$libresoc.v:182354$11949_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188160$12247 + cell $gt $gt$libresoc.v:182355$11950 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387535,10 +378080,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:188160$12247_Y + connect \Y $gt$libresoc.v:182355$11950_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188161$12248 + cell $gt $gt$libresoc.v:182356$11951 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387546,10 +378091,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:188161$12248_Y + connect \Y $gt$libresoc.v:182356$11951_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188162$12249 + cell $gt $gt$libresoc.v:182357$11952 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387557,10 +378102,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:188162$12249_Y + connect \Y $gt$libresoc.v:182357$11952_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188163$12250 + cell $gt $gt$libresoc.v:182358$11953 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387568,10 +378113,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:188163$12250_Y + connect \Y $gt$libresoc.v:182358$11953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188164$12251 + cell $gt $gt$libresoc.v:182359$11954 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387579,10 +378124,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:188164$12251_Y + connect \Y $gt$libresoc.v:182359$11954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188165$12252 + cell $gt $gt$libresoc.v:182360$11955 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387590,10 +378135,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:188165$12252_Y + connect \Y $gt$libresoc.v:182360$11955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188166$12253 + cell $gt $gt$libresoc.v:182361$11956 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387601,10 +378146,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:188166$12253_Y + connect \Y $gt$libresoc.v:182361$11956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188167$12254 + cell $gt $gt$libresoc.v:182362$11957 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387612,10 +378157,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:188167$12254_Y + connect \Y $gt$libresoc.v:182362$11957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188168$12255 + cell $gt $gt$libresoc.v:182363$11958 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387623,10 +378168,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:188168$12255_Y + connect \Y $gt$libresoc.v:182363$11958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188169$12256 + cell $gt $gt$libresoc.v:182364$11959 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387634,10 +378179,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:188169$12256_Y + connect \Y $gt$libresoc.v:182364$11959_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188170$12257 + cell $gt $gt$libresoc.v:182365$11960 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387645,10 +378190,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:188170$12257_Y + connect \Y $gt$libresoc.v:182365$11960_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188171$12258 + cell $gt $gt$libresoc.v:182366$11961 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387656,10 +378201,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:188171$12258_Y + connect \Y $gt$libresoc.v:182366$11961_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:188172$12259 + cell $gt $gt$libresoc.v:182367$11962 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387667,18 +378212,18 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:188172$12259_Y + connect \Y $gt$libresoc.v:182367$11962_Y end - attribute \src "libresoc.v:187975.7-187975.20" - process $proc$libresoc.v:187975$12261 + attribute \src "libresoc.v:182170.7-182170.20" + process $proc$libresoc.v:182170$11964 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188173.3-188560.6" - process $proc$libresoc.v:188173$12260 + attribute \src "libresoc.v:182368.3-182755.6" + process $proc$libresoc.v:182368$11963 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -387745,9 +378290,9 @@ module \right_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:188174.5-188174.29" + attribute \src "libresoc.v:182369.5-182369.29" switch \initial - attribute \src "libresoc.v:188174.9-188174.17" + attribute \src "libresoc.v:182369.9-182369.17" case 1'1 case end @@ -388330,102 +378875,102 @@ module \right_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:188109$12196_Y - connect \$99 $gt$libresoc.v:188110$12197_Y - connect \$101 $gt$libresoc.v:188111$12198_Y - connect \$103 $gt$libresoc.v:188112$12199_Y - connect \$105 $gt$libresoc.v:188113$12200_Y - connect \$107 $gt$libresoc.v:188114$12201_Y - connect \$109 $gt$libresoc.v:188115$12202_Y - connect \$111 $gt$libresoc.v:188116$12203_Y - connect \$113 $gt$libresoc.v:188117$12204_Y - connect \$115 $gt$libresoc.v:188118$12205_Y - connect \$117 $gt$libresoc.v:188119$12206_Y - connect \$11 $gt$libresoc.v:188120$12207_Y - connect \$119 $gt$libresoc.v:188121$12208_Y - connect \$121 $gt$libresoc.v:188122$12209_Y - connect \$123 $gt$libresoc.v:188123$12210_Y - connect \$125 $gt$libresoc.v:188124$12211_Y - connect \$127 $gt$libresoc.v:188125$12212_Y - connect \$13 $gt$libresoc.v:188126$12213_Y - connect \$15 $gt$libresoc.v:188127$12214_Y - connect \$17 $gt$libresoc.v:188128$12215_Y - connect \$1 $gt$libresoc.v:188129$12216_Y - connect \$19 $gt$libresoc.v:188130$12217_Y - connect \$21 $gt$libresoc.v:188131$12218_Y - connect \$23 $gt$libresoc.v:188132$12219_Y - connect \$25 $gt$libresoc.v:188133$12220_Y - connect \$27 $gt$libresoc.v:188134$12221_Y - connect \$29 $gt$libresoc.v:188135$12222_Y - connect \$31 $gt$libresoc.v:188136$12223_Y - connect \$33 $gt$libresoc.v:188137$12224_Y - connect \$35 $gt$libresoc.v:188138$12225_Y - connect \$37 $gt$libresoc.v:188139$12226_Y - connect \$3 $gt$libresoc.v:188140$12227_Y - connect \$39 $gt$libresoc.v:188141$12228_Y - connect \$41 $gt$libresoc.v:188142$12229_Y - connect \$43 $gt$libresoc.v:188143$12230_Y - connect \$45 $gt$libresoc.v:188144$12231_Y - connect \$47 $gt$libresoc.v:188145$12232_Y - connect \$49 $gt$libresoc.v:188146$12233_Y - connect \$51 $gt$libresoc.v:188147$12234_Y - connect \$53 $gt$libresoc.v:188148$12235_Y - connect \$55 $gt$libresoc.v:188149$12236_Y - connect \$57 $gt$libresoc.v:188150$12237_Y - connect \$5 $gt$libresoc.v:188151$12238_Y - connect \$59 $gt$libresoc.v:188152$12239_Y - connect \$61 $gt$libresoc.v:188153$12240_Y - connect \$63 $gt$libresoc.v:188154$12241_Y - connect \$65 $gt$libresoc.v:188155$12242_Y - connect \$67 $gt$libresoc.v:188156$12243_Y - connect \$69 $gt$libresoc.v:188157$12244_Y - connect \$71 $gt$libresoc.v:188158$12245_Y - connect \$73 $gt$libresoc.v:188159$12246_Y - connect \$75 $gt$libresoc.v:188160$12247_Y - connect \$77 $gt$libresoc.v:188161$12248_Y - connect \$7 $gt$libresoc.v:188162$12249_Y - connect \$79 $gt$libresoc.v:188163$12250_Y - connect \$81 $gt$libresoc.v:188164$12251_Y - connect \$83 $gt$libresoc.v:188165$12252_Y - connect \$85 $gt$libresoc.v:188166$12253_Y - connect \$87 $gt$libresoc.v:188167$12254_Y - connect \$89 $gt$libresoc.v:188168$12255_Y - connect \$91 $gt$libresoc.v:188169$12256_Y - connect \$93 $gt$libresoc.v:188170$12257_Y - connect \$95 $gt$libresoc.v:188171$12258_Y - connect \$97 $gt$libresoc.v:188172$12259_Y + connect \$9 $gt$libresoc.v:182304$11899_Y + connect \$99 $gt$libresoc.v:182305$11900_Y + connect \$101 $gt$libresoc.v:182306$11901_Y + connect \$103 $gt$libresoc.v:182307$11902_Y + connect \$105 $gt$libresoc.v:182308$11903_Y + connect \$107 $gt$libresoc.v:182309$11904_Y + connect \$109 $gt$libresoc.v:182310$11905_Y + connect \$111 $gt$libresoc.v:182311$11906_Y + connect \$113 $gt$libresoc.v:182312$11907_Y + connect \$115 $gt$libresoc.v:182313$11908_Y + connect \$117 $gt$libresoc.v:182314$11909_Y + connect \$11 $gt$libresoc.v:182315$11910_Y + connect \$119 $gt$libresoc.v:182316$11911_Y + connect \$121 $gt$libresoc.v:182317$11912_Y + connect \$123 $gt$libresoc.v:182318$11913_Y + connect \$125 $gt$libresoc.v:182319$11914_Y + connect \$127 $gt$libresoc.v:182320$11915_Y + connect \$13 $gt$libresoc.v:182321$11916_Y + connect \$15 $gt$libresoc.v:182322$11917_Y + connect \$17 $gt$libresoc.v:182323$11918_Y + connect \$1 $gt$libresoc.v:182324$11919_Y + connect \$19 $gt$libresoc.v:182325$11920_Y + connect \$21 $gt$libresoc.v:182326$11921_Y + connect \$23 $gt$libresoc.v:182327$11922_Y + connect \$25 $gt$libresoc.v:182328$11923_Y + connect \$27 $gt$libresoc.v:182329$11924_Y + connect \$29 $gt$libresoc.v:182330$11925_Y + connect \$31 $gt$libresoc.v:182331$11926_Y + connect \$33 $gt$libresoc.v:182332$11927_Y + connect \$35 $gt$libresoc.v:182333$11928_Y + connect \$37 $gt$libresoc.v:182334$11929_Y + connect \$3 $gt$libresoc.v:182335$11930_Y + connect \$39 $gt$libresoc.v:182336$11931_Y + connect \$41 $gt$libresoc.v:182337$11932_Y + connect \$43 $gt$libresoc.v:182338$11933_Y + connect \$45 $gt$libresoc.v:182339$11934_Y + connect \$47 $gt$libresoc.v:182340$11935_Y + connect \$49 $gt$libresoc.v:182341$11936_Y + connect \$51 $gt$libresoc.v:182342$11937_Y + connect \$53 $gt$libresoc.v:182343$11938_Y + connect \$55 $gt$libresoc.v:182344$11939_Y + connect \$57 $gt$libresoc.v:182345$11940_Y + connect \$5 $gt$libresoc.v:182346$11941_Y + connect \$59 $gt$libresoc.v:182347$11942_Y + connect \$61 $gt$libresoc.v:182348$11943_Y + connect \$63 $gt$libresoc.v:182349$11944_Y + connect \$65 $gt$libresoc.v:182350$11945_Y + connect \$67 $gt$libresoc.v:182351$11946_Y + connect \$69 $gt$libresoc.v:182352$11947_Y + connect \$71 $gt$libresoc.v:182353$11948_Y + connect \$73 $gt$libresoc.v:182354$11949_Y + connect \$75 $gt$libresoc.v:182355$11950_Y + connect \$77 $gt$libresoc.v:182356$11951_Y + connect \$7 $gt$libresoc.v:182357$11952_Y + connect \$79 $gt$libresoc.v:182358$11953_Y + connect \$81 $gt$libresoc.v:182359$11954_Y + connect \$83 $gt$libresoc.v:182360$11955_Y + connect \$85 $gt$libresoc.v:182361$11956_Y + connect \$87 $gt$libresoc.v:182362$11957_Y + connect \$89 $gt$libresoc.v:182363$11958_Y + connect \$91 $gt$libresoc.v:182364$11959_Y + connect \$93 $gt$libresoc.v:182365$11960_Y + connect \$95 $gt$libresoc.v:182366$11961_Y + connect \$97 $gt$libresoc.v:182367$11962_Y end -attribute \src "libresoc.v:188565.1-188623.10" +attribute \src "libresoc.v:182760.1-182818.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l - attribute \src "libresoc.v:188566.7-188566.20" + attribute \src "libresoc.v:182761.7-182761.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188611.3-188619.6" - wire $0\q_int$next[0:0]$12272 - attribute \src "libresoc.v:188609.3-188610.27" + attribute \src "libresoc.v:182806.3-182814.6" + wire $0\q_int$next[0:0]$11975 + attribute \src "libresoc.v:182804.3-182805.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188611.3-188619.6" - wire $1\q_int$next[0:0]$12273 - attribute \src "libresoc.v:188588.7-188588.19" + attribute \src "libresoc.v:182806.3-182814.6" + wire $1\q_int$next[0:0]$11976 + attribute \src "libresoc.v:182783.7-182783.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188601.17-188601.96" - wire $and$libresoc.v:188601$12262_Y - attribute \src "libresoc.v:188606.17-188606.96" - wire $and$libresoc.v:188606$12267_Y - attribute \src "libresoc.v:188603.18-188603.94" - wire $not$libresoc.v:188603$12264_Y - attribute \src "libresoc.v:188605.17-188605.93" - wire $not$libresoc.v:188605$12266_Y - attribute \src "libresoc.v:188608.17-188608.93" - wire $not$libresoc.v:188608$12269_Y - attribute \src "libresoc.v:188602.18-188602.99" - wire $or$libresoc.v:188602$12263_Y - attribute \src "libresoc.v:188604.18-188604.100" - wire $or$libresoc.v:188604$12265_Y - attribute \src "libresoc.v:188607.17-188607.98" - wire $or$libresoc.v:188607$12268_Y + attribute \src "libresoc.v:182796.17-182796.96" + wire $and$libresoc.v:182796$11965_Y + attribute \src "libresoc.v:182801.17-182801.96" + wire $and$libresoc.v:182801$11970_Y + attribute \src "libresoc.v:182798.18-182798.94" + wire $not$libresoc.v:182798$11967_Y + attribute \src "libresoc.v:182800.17-182800.93" + wire $not$libresoc.v:182800$11969_Y + attribute \src "libresoc.v:182803.17-182803.93" + wire $not$libresoc.v:182803$11972_Y + attribute \src "libresoc.v:182797.18-182797.99" + wire $or$libresoc.v:182797$11966_Y + attribute \src "libresoc.v:182799.18-182799.100" + wire $or$libresoc.v:182799$11968_Y + attribute \src "libresoc.v:182802.17-182802.98" + wire $or$libresoc.v:182802$11971_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -388442,11 +378987,11 @@ module \rok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:188566.7-188566.15" + attribute \src "libresoc.v:182761.7-182761.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -388463,7 +379008,7 @@ module \rok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:188601$12262 + cell $and $and$libresoc.v:182796$11965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388471,10 +379016,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188601$12262_Y + connect \Y $and$libresoc.v:182796$11965_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:188606$12267 + cell $and $and$libresoc.v:182801$11970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388482,34 +379027,34 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188606$12267_Y + connect \Y $and$libresoc.v:182801$11970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:188603$12264 + cell $not $not$libresoc.v:182798$11967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:188603$12264_Y + connect \Y $not$libresoc.v:182798$11967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:188605$12266 + cell $not $not$libresoc.v:182800$11969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188605$12266_Y + connect \Y $not$libresoc.v:182800$11969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:188608$12269 + cell $not $not$libresoc.v:182803$11972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188608$12269_Y + connect \Y $not$libresoc.v:182803$11972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:188602$12263 + cell $or $or$libresoc.v:182797$11966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388517,10 +379062,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:188602$12263_Y + connect \Y $or$libresoc.v:182797$11966_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:188604$12265 + cell $or $or$libresoc.v:182799$11968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388528,10 +379073,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:188604$12265_Y + connect \Y $or$libresoc.v:182799$11968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:188607$12268 + cell $or $or$libresoc.v:182802$11971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388539,39 +379084,39 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:188607$12268_Y + connect \Y $or$libresoc.v:182802$11971_Y end - attribute \src "libresoc.v:188566.7-188566.20" - process $proc$libresoc.v:188566$12274 + attribute \src "libresoc.v:182761.7-182761.20" + process $proc$libresoc.v:182761$11977 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188588.7-188588.19" - process $proc$libresoc.v:188588$12275 + attribute \src "libresoc.v:182783.7-182783.19" + process $proc$libresoc.v:182783$11978 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188609.3-188610.27" - process $proc$libresoc.v:188609$12270 + attribute \src "libresoc.v:182804.3-182805.27" + process $proc$libresoc.v:182804$11973 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188611.3-188619.6" - process $proc$libresoc.v:188611$12271 + attribute \src "libresoc.v:182806.3-182814.6" + process $proc$libresoc.v:182806$11974 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12272 $1\q_int$next[0:0]$12273 - attribute \src "libresoc.v:188612.5-188612.29" + assign $0\q_int$next[0:0]$11975 $1\q_int$next[0:0]$11976 + attribute \src "libresoc.v:182807.5-182807.29" switch \initial - attribute \src "libresoc.v:188612.9-188612.17" + attribute \src "libresoc.v:182807.9-182807.17" case 1'1 case end @@ -388580,56 +379125,56 @@ module \rok_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12273 1'0 + assign $1\q_int$next[0:0]$11976 1'0 case - assign $1\q_int$next[0:0]$12273 \$5 + assign $1\q_int$next[0:0]$11976 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12272 + update \q_int$next $0\q_int$next[0:0]$11975 end - connect \$9 $and$libresoc.v:188601$12262_Y - connect \$11 $or$libresoc.v:188602$12263_Y - connect \$13 $not$libresoc.v:188603$12264_Y - connect \$15 $or$libresoc.v:188604$12265_Y - connect \$1 $not$libresoc.v:188605$12266_Y - connect \$3 $and$libresoc.v:188606$12267_Y - connect \$5 $or$libresoc.v:188607$12268_Y - connect \$7 $not$libresoc.v:188608$12269_Y + connect \$9 $and$libresoc.v:182796$11965_Y + connect \$11 $or$libresoc.v:182797$11966_Y + connect \$13 $not$libresoc.v:182798$11967_Y + connect \$15 $or$libresoc.v:182799$11968_Y + connect \$1 $not$libresoc.v:182800$11969_Y + connect \$3 $and$libresoc.v:182801$11970_Y + connect \$5 $or$libresoc.v:182802$11971_Y + connect \$7 $not$libresoc.v:182803$11972_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:188627.1-188685.10" +attribute \src "libresoc.v:182822.1-182880.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" module \rok_l$105 - attribute \src "libresoc.v:188628.7-188628.20" + attribute \src "libresoc.v:182823.7-182823.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188673.3-188681.6" - wire $0\q_int$next[0:0]$12286 - attribute \src "libresoc.v:188671.3-188672.27" + attribute \src "libresoc.v:182868.3-182876.6" + wire $0\q_int$next[0:0]$11989 + attribute \src "libresoc.v:182866.3-182867.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188673.3-188681.6" - wire $1\q_int$next[0:0]$12287 - attribute \src "libresoc.v:188650.7-188650.19" + attribute \src "libresoc.v:182868.3-182876.6" + wire $1\q_int$next[0:0]$11990 + attribute \src "libresoc.v:182845.7-182845.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188663.17-188663.96" - wire $and$libresoc.v:188663$12276_Y - attribute \src "libresoc.v:188668.17-188668.96" - wire $and$libresoc.v:188668$12281_Y - attribute \src "libresoc.v:188665.18-188665.94" - wire $not$libresoc.v:188665$12278_Y - attribute \src "libresoc.v:188667.17-188667.93" - wire $not$libresoc.v:188667$12280_Y - attribute \src "libresoc.v:188670.17-188670.93" - wire $not$libresoc.v:188670$12283_Y - attribute \src "libresoc.v:188664.18-188664.99" - wire $or$libresoc.v:188664$12277_Y - attribute \src "libresoc.v:188666.18-188666.100" - wire $or$libresoc.v:188666$12279_Y - attribute \src "libresoc.v:188669.17-188669.98" - wire $or$libresoc.v:188669$12282_Y + attribute \src "libresoc.v:182858.17-182858.96" + wire $and$libresoc.v:182858$11979_Y + attribute \src "libresoc.v:182863.17-182863.96" + wire $and$libresoc.v:182863$11984_Y + attribute \src "libresoc.v:182860.18-182860.94" + wire $not$libresoc.v:182860$11981_Y + attribute \src "libresoc.v:182862.17-182862.93" + wire $not$libresoc.v:182862$11983_Y + attribute \src "libresoc.v:182865.17-182865.93" + wire $not$libresoc.v:182865$11986_Y + attribute \src "libresoc.v:182859.18-182859.99" + wire $or$libresoc.v:182859$11980_Y + attribute \src "libresoc.v:182861.18-182861.100" + wire $or$libresoc.v:182861$11982_Y + attribute \src "libresoc.v:182864.17-182864.98" + wire $or$libresoc.v:182864$11985_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -388646,11 +379191,11 @@ module \rok_l$105 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:188628.7-188628.15" + attribute \src "libresoc.v:182823.7-182823.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -388667,7 +379212,7 @@ module \rok_l$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:188663$12276 + cell $and $and$libresoc.v:182858$11979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388675,10 +379220,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188663$12276_Y + connect \Y $and$libresoc.v:182858$11979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:188668$12281 + cell $and $and$libresoc.v:182863$11984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388686,34 +379231,34 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188668$12281_Y + connect \Y $and$libresoc.v:182863$11984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:188665$12278 + cell $not $not$libresoc.v:182860$11981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:188665$12278_Y + connect \Y $not$libresoc.v:182860$11981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:188667$12280 + cell $not $not$libresoc.v:182862$11983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188667$12280_Y + connect \Y $not$libresoc.v:182862$11983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:188670$12283 + cell $not $not$libresoc.v:182865$11986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188670$12283_Y + connect \Y $not$libresoc.v:182865$11986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:188664$12277 + cell $or $or$libresoc.v:182859$11980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388721,10 +379266,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:188664$12277_Y + connect \Y $or$libresoc.v:182859$11980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:188666$12279 + cell $or $or$libresoc.v:182861$11982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388732,10 +379277,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:188666$12279_Y + connect \Y $or$libresoc.v:182861$11982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:188669$12282 + cell $or $or$libresoc.v:182864$11985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388743,39 +379288,39 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:188669$12282_Y + connect \Y $or$libresoc.v:182864$11985_Y end - attribute \src "libresoc.v:188628.7-188628.20" - process $proc$libresoc.v:188628$12288 + attribute \src "libresoc.v:182823.7-182823.20" + process $proc$libresoc.v:182823$11991 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188650.7-188650.19" - process $proc$libresoc.v:188650$12289 + attribute \src "libresoc.v:182845.7-182845.19" + process $proc$libresoc.v:182845$11992 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188671.3-188672.27" - process $proc$libresoc.v:188671$12284 + attribute \src "libresoc.v:182866.3-182867.27" + process $proc$libresoc.v:182866$11987 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188673.3-188681.6" - process $proc$libresoc.v:188673$12285 + attribute \src "libresoc.v:182868.3-182876.6" + process $proc$libresoc.v:182868$11988 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12286 $1\q_int$next[0:0]$12287 - attribute \src "libresoc.v:188674.5-188674.29" + assign $0\q_int$next[0:0]$11989 $1\q_int$next[0:0]$11990 + attribute \src "libresoc.v:182869.5-182869.29" switch \initial - attribute \src "libresoc.v:188674.9-188674.17" + attribute \src "libresoc.v:182869.9-182869.17" case 1'1 case end @@ -388784,56 +379329,56 @@ module \rok_l$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12287 1'0 + assign $1\q_int$next[0:0]$11990 1'0 case - assign $1\q_int$next[0:0]$12287 \$5 + assign $1\q_int$next[0:0]$11990 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12286 + update \q_int$next $0\q_int$next[0:0]$11989 end - connect \$9 $and$libresoc.v:188663$12276_Y - connect \$11 $or$libresoc.v:188664$12277_Y - connect \$13 $not$libresoc.v:188665$12278_Y - connect \$15 $or$libresoc.v:188666$12279_Y - connect \$1 $not$libresoc.v:188667$12280_Y - connect \$3 $and$libresoc.v:188668$12281_Y - connect \$5 $or$libresoc.v:188669$12282_Y - connect \$7 $not$libresoc.v:188670$12283_Y + connect \$9 $and$libresoc.v:182858$11979_Y + connect \$11 $or$libresoc.v:182859$11980_Y + connect \$13 $not$libresoc.v:182860$11981_Y + connect \$15 $or$libresoc.v:182861$11982_Y + connect \$1 $not$libresoc.v:182862$11983_Y + connect \$3 $and$libresoc.v:182863$11984_Y + connect \$5 $or$libresoc.v:182864$11985_Y + connect \$7 $not$libresoc.v:182865$11986_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:188689.1-188747.10" +attribute \src "libresoc.v:182884.1-182942.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" module \rok_l$123 - attribute \src "libresoc.v:188690.7-188690.20" + attribute \src "libresoc.v:182885.7-182885.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188735.3-188743.6" - wire $0\q_int$next[0:0]$12300 - attribute \src "libresoc.v:188733.3-188734.27" + attribute \src "libresoc.v:182930.3-182938.6" + wire $0\q_int$next[0:0]$12003 + attribute \src "libresoc.v:182928.3-182929.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188735.3-188743.6" - wire $1\q_int$next[0:0]$12301 - attribute \src "libresoc.v:188712.7-188712.19" + attribute \src "libresoc.v:182930.3-182938.6" + wire $1\q_int$next[0:0]$12004 + attribute \src "libresoc.v:182907.7-182907.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188725.17-188725.96" - wire $and$libresoc.v:188725$12290_Y - attribute \src "libresoc.v:188730.17-188730.96" - wire $and$libresoc.v:188730$12295_Y - attribute \src "libresoc.v:188727.18-188727.94" - wire $not$libresoc.v:188727$12292_Y - attribute \src "libresoc.v:188729.17-188729.93" - wire $not$libresoc.v:188729$12294_Y - attribute \src "libresoc.v:188732.17-188732.93" - wire $not$libresoc.v:188732$12297_Y - attribute \src "libresoc.v:188726.18-188726.99" - wire $or$libresoc.v:188726$12291_Y - attribute \src "libresoc.v:188728.18-188728.100" - wire $or$libresoc.v:188728$12293_Y - attribute \src "libresoc.v:188731.17-188731.98" - wire $or$libresoc.v:188731$12296_Y + attribute \src "libresoc.v:182920.17-182920.96" + wire $and$libresoc.v:182920$11993_Y + attribute \src "libresoc.v:182925.17-182925.96" + wire $and$libresoc.v:182925$11998_Y + attribute \src "libresoc.v:182922.18-182922.94" + wire $not$libresoc.v:182922$11995_Y + attribute \src "libresoc.v:182924.17-182924.93" + wire $not$libresoc.v:182924$11997_Y + attribute \src "libresoc.v:182927.17-182927.93" + wire $not$libresoc.v:182927$12000_Y + attribute \src "libresoc.v:182921.18-182921.99" + wire $or$libresoc.v:182921$11994_Y + attribute \src "libresoc.v:182923.18-182923.100" + wire $or$libresoc.v:182923$11996_Y + attribute \src "libresoc.v:182926.17-182926.98" + wire $or$libresoc.v:182926$11999_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -388850,11 +379395,11 @@ module \rok_l$123 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:188690.7-188690.15" + attribute \src "libresoc.v:182885.7-182885.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -388871,7 +379416,7 @@ module \rok_l$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:188725$12290 + cell $and $and$libresoc.v:182920$11993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388879,10 +379424,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188725$12290_Y + connect \Y $and$libresoc.v:182920$11993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:188730$12295 + cell $and $and$libresoc.v:182925$11998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388890,34 +379435,34 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188730$12295_Y + connect \Y $and$libresoc.v:182925$11998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:188727$12292 + cell $not $not$libresoc.v:182922$11995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:188727$12292_Y + connect \Y $not$libresoc.v:182922$11995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:188729$12294 + cell $not $not$libresoc.v:182924$11997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188729$12294_Y + connect \Y $not$libresoc.v:182924$11997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:188732$12297 + cell $not $not$libresoc.v:182927$12000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188732$12297_Y + connect \Y $not$libresoc.v:182927$12000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:188726$12291 + cell $or $or$libresoc.v:182921$11994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388925,10 +379470,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:188726$12291_Y + connect \Y $or$libresoc.v:182921$11994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:188728$12293 + cell $or $or$libresoc.v:182923$11996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388936,10 +379481,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:188728$12293_Y + connect \Y $or$libresoc.v:182923$11996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:188731$12296 + cell $or $or$libresoc.v:182926$11999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388947,39 +379492,39 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:188731$12296_Y + connect \Y $or$libresoc.v:182926$11999_Y end - attribute \src "libresoc.v:188690.7-188690.20" - process $proc$libresoc.v:188690$12302 + attribute \src "libresoc.v:182885.7-182885.20" + process $proc$libresoc.v:182885$12005 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188712.7-188712.19" - process $proc$libresoc.v:188712$12303 + attribute \src "libresoc.v:182907.7-182907.19" + process $proc$libresoc.v:182907$12006 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188733.3-188734.27" - process $proc$libresoc.v:188733$12298 + attribute \src "libresoc.v:182928.3-182929.27" + process $proc$libresoc.v:182928$12001 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188735.3-188743.6" - process $proc$libresoc.v:188735$12299 + attribute \src "libresoc.v:182930.3-182938.6" + process $proc$libresoc.v:182930$12002 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12300 $1\q_int$next[0:0]$12301 - attribute \src "libresoc.v:188736.5-188736.29" + assign $0\q_int$next[0:0]$12003 $1\q_int$next[0:0]$12004 + attribute \src "libresoc.v:182931.5-182931.29" switch \initial - attribute \src "libresoc.v:188736.9-188736.17" + attribute \src "libresoc.v:182931.9-182931.17" case 1'1 case end @@ -388988,56 +379533,56 @@ module \rok_l$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12301 1'0 + assign $1\q_int$next[0:0]$12004 1'0 case - assign $1\q_int$next[0:0]$12301 \$5 + assign $1\q_int$next[0:0]$12004 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12300 + update \q_int$next $0\q_int$next[0:0]$12003 end - connect \$9 $and$libresoc.v:188725$12290_Y - connect \$11 $or$libresoc.v:188726$12291_Y - connect \$13 $not$libresoc.v:188727$12292_Y - connect \$15 $or$libresoc.v:188728$12293_Y - connect \$1 $not$libresoc.v:188729$12294_Y - connect \$3 $and$libresoc.v:188730$12295_Y - connect \$5 $or$libresoc.v:188731$12296_Y - connect \$7 $not$libresoc.v:188732$12297_Y + connect \$9 $and$libresoc.v:182920$11993_Y + connect \$11 $or$libresoc.v:182921$11994_Y + connect \$13 $not$libresoc.v:182922$11995_Y + connect \$15 $or$libresoc.v:182923$11996_Y + connect \$1 $not$libresoc.v:182924$11997_Y + connect \$3 $and$libresoc.v:182925$11998_Y + connect \$5 $or$libresoc.v:182926$11999_Y + connect \$7 $not$libresoc.v:182927$12000_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:188751.1-188809.10" +attribute \src "libresoc.v:182946.1-183004.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 - attribute \src "libresoc.v:188752.7-188752.20" + attribute \src "libresoc.v:182947.7-182947.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188797.3-188805.6" - wire $0\q_int$next[0:0]$12314 - attribute \src "libresoc.v:188795.3-188796.27" + attribute \src "libresoc.v:182992.3-183000.6" + wire $0\q_int$next[0:0]$12017 + attribute \src "libresoc.v:182990.3-182991.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188797.3-188805.6" - wire $1\q_int$next[0:0]$12315 - attribute \src "libresoc.v:188774.7-188774.19" + attribute \src "libresoc.v:182992.3-183000.6" + wire $1\q_int$next[0:0]$12018 + attribute \src "libresoc.v:182969.7-182969.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188787.17-188787.96" - wire $and$libresoc.v:188787$12304_Y - attribute \src "libresoc.v:188792.17-188792.96" - wire $and$libresoc.v:188792$12309_Y - attribute \src "libresoc.v:188789.18-188789.94" - wire $not$libresoc.v:188789$12306_Y - attribute \src "libresoc.v:188791.17-188791.93" - wire $not$libresoc.v:188791$12308_Y - attribute \src "libresoc.v:188794.17-188794.93" - wire $not$libresoc.v:188794$12311_Y - attribute \src "libresoc.v:188788.18-188788.99" - wire $or$libresoc.v:188788$12305_Y - attribute \src "libresoc.v:188790.18-188790.100" - wire $or$libresoc.v:188790$12307_Y - attribute \src "libresoc.v:188793.17-188793.98" - wire $or$libresoc.v:188793$12310_Y + attribute \src "libresoc.v:182982.17-182982.96" + wire $and$libresoc.v:182982$12007_Y + attribute \src "libresoc.v:182987.17-182987.96" + wire $and$libresoc.v:182987$12012_Y + attribute \src "libresoc.v:182984.18-182984.94" + wire $not$libresoc.v:182984$12009_Y + attribute \src "libresoc.v:182986.17-182986.93" + wire $not$libresoc.v:182986$12011_Y + attribute \src "libresoc.v:182989.17-182989.93" + wire $not$libresoc.v:182989$12014_Y + attribute \src "libresoc.v:182983.18-182983.99" + wire $or$libresoc.v:182983$12008_Y + attribute \src "libresoc.v:182985.18-182985.100" + wire $or$libresoc.v:182985$12010_Y + attribute \src "libresoc.v:182988.17-182988.98" + wire $or$libresoc.v:182988$12013_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -389054,11 +379599,11 @@ module \rok_l$14 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:188752.7-188752.15" + attribute \src "libresoc.v:182947.7-182947.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -389075,7 +379620,7 @@ module \rok_l$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:188787$12304 + cell $and $and$libresoc.v:182982$12007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389083,10 +379628,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188787$12304_Y + connect \Y $and$libresoc.v:182982$12007_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:188792$12309 + cell $and $and$libresoc.v:182987$12012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389094,34 +379639,34 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188792$12309_Y + connect \Y $and$libresoc.v:182987$12012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:188789$12306 + cell $not $not$libresoc.v:182984$12009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:188789$12306_Y + connect \Y $not$libresoc.v:182984$12009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:188791$12308 + cell $not $not$libresoc.v:182986$12011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188791$12308_Y + connect \Y $not$libresoc.v:182986$12011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:188794$12311 + cell $not $not$libresoc.v:182989$12014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188794$12311_Y + connect \Y $not$libresoc.v:182989$12014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:188788$12305 + cell $or $or$libresoc.v:182983$12008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389129,10 +379674,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:188788$12305_Y + connect \Y $or$libresoc.v:182983$12008_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:188790$12307 + cell $or $or$libresoc.v:182985$12010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389140,10 +379685,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:188790$12307_Y + connect \Y $or$libresoc.v:182985$12010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:188793$12310 + cell $or $or$libresoc.v:182988$12013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389151,39 +379696,39 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:188793$12310_Y + connect \Y $or$libresoc.v:182988$12013_Y end - attribute \src "libresoc.v:188752.7-188752.20" - process $proc$libresoc.v:188752$12316 + attribute \src "libresoc.v:182947.7-182947.20" + process $proc$libresoc.v:182947$12019 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188774.7-188774.19" - process $proc$libresoc.v:188774$12317 + attribute \src "libresoc.v:182969.7-182969.19" + process $proc$libresoc.v:182969$12020 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188795.3-188796.27" - process $proc$libresoc.v:188795$12312 + attribute \src "libresoc.v:182990.3-182991.27" + process $proc$libresoc.v:182990$12015 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188797.3-188805.6" - process $proc$libresoc.v:188797$12313 + attribute \src "libresoc.v:182992.3-183000.6" + process $proc$libresoc.v:182992$12016 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12314 $1\q_int$next[0:0]$12315 - attribute \src "libresoc.v:188798.5-188798.29" + assign $0\q_int$next[0:0]$12017 $1\q_int$next[0:0]$12018 + attribute \src "libresoc.v:182993.5-182993.29" switch \initial - attribute \src "libresoc.v:188798.9-188798.17" + attribute \src "libresoc.v:182993.9-182993.17" case 1'1 case end @@ -389192,56 +379737,56 @@ module \rok_l$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12315 1'0 + assign $1\q_int$next[0:0]$12018 1'0 case - assign $1\q_int$next[0:0]$12315 \$5 + assign $1\q_int$next[0:0]$12018 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12314 + update \q_int$next $0\q_int$next[0:0]$12017 end - connect \$9 $and$libresoc.v:188787$12304_Y - connect \$11 $or$libresoc.v:188788$12305_Y - connect \$13 $not$libresoc.v:188789$12306_Y - connect \$15 $or$libresoc.v:188790$12307_Y - connect \$1 $not$libresoc.v:188791$12308_Y - connect \$3 $and$libresoc.v:188792$12309_Y - connect \$5 $or$libresoc.v:188793$12310_Y - connect \$7 $not$libresoc.v:188794$12311_Y + connect \$9 $and$libresoc.v:182982$12007_Y + connect \$11 $or$libresoc.v:182983$12008_Y + connect \$13 $not$libresoc.v:182984$12009_Y + connect \$15 $or$libresoc.v:182985$12010_Y + connect \$1 $not$libresoc.v:182986$12011_Y + connect \$3 $and$libresoc.v:182987$12012_Y + connect \$5 $or$libresoc.v:182988$12013_Y + connect \$7 $not$libresoc.v:182989$12014_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:188813.1-188871.10" +attribute \src "libresoc.v:183008.1-183066.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 - attribute \src "libresoc.v:188814.7-188814.20" + attribute \src "libresoc.v:183009.7-183009.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188859.3-188867.6" - wire $0\q_int$next[0:0]$12328 - attribute \src "libresoc.v:188857.3-188858.27" + attribute \src "libresoc.v:183054.3-183062.6" + wire $0\q_int$next[0:0]$12031 + attribute \src "libresoc.v:183052.3-183053.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188859.3-188867.6" - wire $1\q_int$next[0:0]$12329 - attribute \src "libresoc.v:188836.7-188836.19" + attribute \src "libresoc.v:183054.3-183062.6" + wire $1\q_int$next[0:0]$12032 + attribute \src "libresoc.v:183031.7-183031.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188849.17-188849.96" - wire $and$libresoc.v:188849$12318_Y - attribute \src "libresoc.v:188854.17-188854.96" - wire $and$libresoc.v:188854$12323_Y - attribute \src "libresoc.v:188851.18-188851.94" - wire $not$libresoc.v:188851$12320_Y - attribute \src "libresoc.v:188853.17-188853.93" - wire $not$libresoc.v:188853$12322_Y - attribute \src "libresoc.v:188856.17-188856.93" - wire $not$libresoc.v:188856$12325_Y - attribute \src "libresoc.v:188850.18-188850.99" - wire $or$libresoc.v:188850$12319_Y - attribute \src "libresoc.v:188852.18-188852.100" - wire $or$libresoc.v:188852$12321_Y - attribute \src "libresoc.v:188855.17-188855.98" - wire $or$libresoc.v:188855$12324_Y + attribute \src "libresoc.v:183044.17-183044.96" + wire $and$libresoc.v:183044$12021_Y + attribute \src "libresoc.v:183049.17-183049.96" + wire $and$libresoc.v:183049$12026_Y + attribute \src "libresoc.v:183046.18-183046.94" + wire $not$libresoc.v:183046$12023_Y + attribute \src "libresoc.v:183048.17-183048.93" + wire $not$libresoc.v:183048$12025_Y + attribute \src "libresoc.v:183051.17-183051.93" + wire $not$libresoc.v:183051$12028_Y + attribute \src "libresoc.v:183045.18-183045.99" + wire $or$libresoc.v:183045$12022_Y + attribute \src "libresoc.v:183047.18-183047.100" + wire $or$libresoc.v:183047$12024_Y + attribute \src "libresoc.v:183050.17-183050.98" + wire $or$libresoc.v:183050$12027_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -389258,11 +379803,11 @@ module \rok_l$27 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:188814.7-188814.15" + attribute \src "libresoc.v:183009.7-183009.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -389279,7 +379824,7 @@ module \rok_l$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:188849$12318 + cell $and $and$libresoc.v:183044$12021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389287,10 +379832,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188849$12318_Y + connect \Y $and$libresoc.v:183044$12021_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:188854$12323 + cell $and $and$libresoc.v:183049$12026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389298,34 +379843,34 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188854$12323_Y + connect \Y $and$libresoc.v:183049$12026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:188851$12320 + cell $not $not$libresoc.v:183046$12023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:188851$12320_Y + connect \Y $not$libresoc.v:183046$12023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:188853$12322 + cell $not $not$libresoc.v:183048$12025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188853$12322_Y + connect \Y $not$libresoc.v:183048$12025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:188856$12325 + cell $not $not$libresoc.v:183051$12028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188856$12325_Y + connect \Y $not$libresoc.v:183051$12028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:188850$12319 + cell $or $or$libresoc.v:183045$12022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389333,10 +379878,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:188850$12319_Y + connect \Y $or$libresoc.v:183045$12022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:188852$12321 + cell $or $or$libresoc.v:183047$12024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389344,10 +379889,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:188852$12321_Y + connect \Y $or$libresoc.v:183047$12024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:188855$12324 + cell $or $or$libresoc.v:183050$12027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389355,39 +379900,39 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:188855$12324_Y + connect \Y $or$libresoc.v:183050$12027_Y end - attribute \src "libresoc.v:188814.7-188814.20" - process $proc$libresoc.v:188814$12330 + attribute \src "libresoc.v:183009.7-183009.20" + process $proc$libresoc.v:183009$12033 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188836.7-188836.19" - process $proc$libresoc.v:188836$12331 + attribute \src "libresoc.v:183031.7-183031.19" + process $proc$libresoc.v:183031$12034 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188857.3-188858.27" - process $proc$libresoc.v:188857$12326 + attribute \src "libresoc.v:183052.3-183053.27" + process $proc$libresoc.v:183052$12029 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188859.3-188867.6" - process $proc$libresoc.v:188859$12327 + attribute \src "libresoc.v:183054.3-183062.6" + process $proc$libresoc.v:183054$12030 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12328 $1\q_int$next[0:0]$12329 - attribute \src "libresoc.v:188860.5-188860.29" + assign $0\q_int$next[0:0]$12031 $1\q_int$next[0:0]$12032 + attribute \src "libresoc.v:183055.5-183055.29" switch \initial - attribute \src "libresoc.v:188860.9-188860.17" + attribute \src "libresoc.v:183055.9-183055.17" case 1'1 case end @@ -389396,56 +379941,56 @@ module \rok_l$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12329 1'0 + assign $1\q_int$next[0:0]$12032 1'0 case - assign $1\q_int$next[0:0]$12329 \$5 + assign $1\q_int$next[0:0]$12032 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12328 + update \q_int$next $0\q_int$next[0:0]$12031 end - connect \$9 $and$libresoc.v:188849$12318_Y - connect \$11 $or$libresoc.v:188850$12319_Y - connect \$13 $not$libresoc.v:188851$12320_Y - connect \$15 $or$libresoc.v:188852$12321_Y - connect \$1 $not$libresoc.v:188853$12322_Y - connect \$3 $and$libresoc.v:188854$12323_Y - connect \$5 $or$libresoc.v:188855$12324_Y - connect \$7 $not$libresoc.v:188856$12325_Y + connect \$9 $and$libresoc.v:183044$12021_Y + connect \$11 $or$libresoc.v:183045$12022_Y + connect \$13 $not$libresoc.v:183046$12023_Y + connect \$15 $or$libresoc.v:183047$12024_Y + connect \$1 $not$libresoc.v:183048$12025_Y + connect \$3 $and$libresoc.v:183049$12026_Y + connect \$5 $or$libresoc.v:183050$12027_Y + connect \$7 $not$libresoc.v:183051$12028_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:188875.1-188933.10" +attribute \src "libresoc.v:183070.1-183128.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" module \rok_l$43 - attribute \src "libresoc.v:188876.7-188876.20" + attribute \src "libresoc.v:183071.7-183071.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188921.3-188929.6" - wire $0\q_int$next[0:0]$12342 - attribute \src "libresoc.v:188919.3-188920.27" + attribute \src "libresoc.v:183116.3-183124.6" + wire $0\q_int$next[0:0]$12045 + attribute \src "libresoc.v:183114.3-183115.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188921.3-188929.6" - wire $1\q_int$next[0:0]$12343 - attribute \src "libresoc.v:188898.7-188898.19" + attribute \src "libresoc.v:183116.3-183124.6" + wire $1\q_int$next[0:0]$12046 + attribute \src "libresoc.v:183093.7-183093.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188911.17-188911.96" - wire $and$libresoc.v:188911$12332_Y - attribute \src "libresoc.v:188916.17-188916.96" - wire $and$libresoc.v:188916$12337_Y - attribute \src "libresoc.v:188913.18-188913.94" - wire $not$libresoc.v:188913$12334_Y - attribute \src "libresoc.v:188915.17-188915.93" - wire $not$libresoc.v:188915$12336_Y - attribute \src "libresoc.v:188918.17-188918.93" - wire $not$libresoc.v:188918$12339_Y - attribute \src "libresoc.v:188912.18-188912.99" - wire $or$libresoc.v:188912$12333_Y - attribute \src "libresoc.v:188914.18-188914.100" - wire $or$libresoc.v:188914$12335_Y - attribute \src "libresoc.v:188917.17-188917.98" - wire $or$libresoc.v:188917$12338_Y + attribute \src "libresoc.v:183106.17-183106.96" + wire $and$libresoc.v:183106$12035_Y + attribute \src "libresoc.v:183111.17-183111.96" + wire $and$libresoc.v:183111$12040_Y + attribute \src "libresoc.v:183108.18-183108.94" + wire $not$libresoc.v:183108$12037_Y + attribute \src "libresoc.v:183110.17-183110.93" + wire $not$libresoc.v:183110$12039_Y + attribute \src "libresoc.v:183113.17-183113.93" + wire $not$libresoc.v:183113$12042_Y + attribute \src "libresoc.v:183107.18-183107.99" + wire $or$libresoc.v:183107$12036_Y + attribute \src "libresoc.v:183109.18-183109.100" + wire $or$libresoc.v:183109$12038_Y + attribute \src "libresoc.v:183112.17-183112.98" + wire $or$libresoc.v:183112$12041_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -389462,11 +380007,11 @@ module \rok_l$43 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:188876.7-188876.15" + attribute \src "libresoc.v:183071.7-183071.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -389483,7 +380028,7 @@ module \rok_l$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:188911$12332 + cell $and $and$libresoc.v:183106$12035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389491,10 +380036,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188911$12332_Y + connect \Y $and$libresoc.v:183106$12035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:188916$12337 + cell $and $and$libresoc.v:183111$12040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389502,34 +380047,34 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188916$12337_Y + connect \Y $and$libresoc.v:183111$12040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:188913$12334 + cell $not $not$libresoc.v:183108$12037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:188913$12334_Y + connect \Y $not$libresoc.v:183108$12037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:188915$12336 + cell $not $not$libresoc.v:183110$12039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188915$12336_Y + connect \Y $not$libresoc.v:183110$12039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:188918$12339 + cell $not $not$libresoc.v:183113$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188918$12339_Y + connect \Y $not$libresoc.v:183113$12042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:188912$12333 + cell $or $or$libresoc.v:183107$12036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389537,10 +380082,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:188912$12333_Y + connect \Y $or$libresoc.v:183107$12036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:188914$12335 + cell $or $or$libresoc.v:183109$12038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389548,10 +380093,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:188914$12335_Y + connect \Y $or$libresoc.v:183109$12038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:188917$12338 + cell $or $or$libresoc.v:183112$12041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389559,39 +380104,39 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:188917$12338_Y + connect \Y $or$libresoc.v:183112$12041_Y end - attribute \src "libresoc.v:188876.7-188876.20" - process $proc$libresoc.v:188876$12344 + attribute \src "libresoc.v:183071.7-183071.20" + process $proc$libresoc.v:183071$12047 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188898.7-188898.19" - process $proc$libresoc.v:188898$12345 + attribute \src "libresoc.v:183093.7-183093.19" + process $proc$libresoc.v:183093$12048 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188919.3-188920.27" - process $proc$libresoc.v:188919$12340 + attribute \src "libresoc.v:183114.3-183115.27" + process $proc$libresoc.v:183114$12043 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188921.3-188929.6" - process $proc$libresoc.v:188921$12341 + attribute \src "libresoc.v:183116.3-183124.6" + process $proc$libresoc.v:183116$12044 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12342 $1\q_int$next[0:0]$12343 - attribute \src "libresoc.v:188922.5-188922.29" + assign $0\q_int$next[0:0]$12045 $1\q_int$next[0:0]$12046 + attribute \src "libresoc.v:183117.5-183117.29" switch \initial - attribute \src "libresoc.v:188922.9-188922.17" + attribute \src "libresoc.v:183117.9-183117.17" case 1'1 case end @@ -389600,56 +380145,56 @@ module \rok_l$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12343 1'0 + assign $1\q_int$next[0:0]$12046 1'0 case - assign $1\q_int$next[0:0]$12343 \$5 + assign $1\q_int$next[0:0]$12046 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12342 + update \q_int$next $0\q_int$next[0:0]$12045 end - connect \$9 $and$libresoc.v:188911$12332_Y - connect \$11 $or$libresoc.v:188912$12333_Y - connect \$13 $not$libresoc.v:188913$12334_Y - connect \$15 $or$libresoc.v:188914$12335_Y - connect \$1 $not$libresoc.v:188915$12336_Y - connect \$3 $and$libresoc.v:188916$12337_Y - connect \$5 $or$libresoc.v:188917$12338_Y - connect \$7 $not$libresoc.v:188918$12339_Y + connect \$9 $and$libresoc.v:183106$12035_Y + connect \$11 $or$libresoc.v:183107$12036_Y + connect \$13 $not$libresoc.v:183108$12037_Y + connect \$15 $or$libresoc.v:183109$12038_Y + connect \$1 $not$libresoc.v:183110$12039_Y + connect \$3 $and$libresoc.v:183111$12040_Y + connect \$5 $or$libresoc.v:183112$12041_Y + connect \$7 $not$libresoc.v:183113$12042_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:188937.1-188995.10" +attribute \src "libresoc.v:183132.1-183190.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" module \rok_l$59 - attribute \src "libresoc.v:188938.7-188938.20" + attribute \src "libresoc.v:183133.7-183133.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188983.3-188991.6" - wire $0\q_int$next[0:0]$12356 - attribute \src "libresoc.v:188981.3-188982.27" + attribute \src "libresoc.v:183178.3-183186.6" + wire $0\q_int$next[0:0]$12059 + attribute \src "libresoc.v:183176.3-183177.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:188983.3-188991.6" - wire $1\q_int$next[0:0]$12357 - attribute \src "libresoc.v:188960.7-188960.19" + attribute \src "libresoc.v:183178.3-183186.6" + wire $1\q_int$next[0:0]$12060 + attribute \src "libresoc.v:183155.7-183155.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:188973.17-188973.96" - wire $and$libresoc.v:188973$12346_Y - attribute \src "libresoc.v:188978.17-188978.96" - wire $and$libresoc.v:188978$12351_Y - attribute \src "libresoc.v:188975.18-188975.94" - wire $not$libresoc.v:188975$12348_Y - attribute \src "libresoc.v:188977.17-188977.93" - wire $not$libresoc.v:188977$12350_Y - attribute \src "libresoc.v:188980.17-188980.93" - wire $not$libresoc.v:188980$12353_Y - attribute \src "libresoc.v:188974.18-188974.99" - wire $or$libresoc.v:188974$12347_Y - attribute \src "libresoc.v:188976.18-188976.100" - wire $or$libresoc.v:188976$12349_Y - attribute \src "libresoc.v:188979.17-188979.98" - wire $or$libresoc.v:188979$12352_Y + attribute \src "libresoc.v:183168.17-183168.96" + wire $and$libresoc.v:183168$12049_Y + attribute \src "libresoc.v:183173.17-183173.96" + wire $and$libresoc.v:183173$12054_Y + attribute \src "libresoc.v:183170.18-183170.94" + wire $not$libresoc.v:183170$12051_Y + attribute \src "libresoc.v:183172.17-183172.93" + wire $not$libresoc.v:183172$12053_Y + attribute \src "libresoc.v:183175.17-183175.93" + wire $not$libresoc.v:183175$12056_Y + attribute \src "libresoc.v:183169.18-183169.99" + wire $or$libresoc.v:183169$12050_Y + attribute \src "libresoc.v:183171.18-183171.100" + wire $or$libresoc.v:183171$12052_Y + attribute \src "libresoc.v:183174.17-183174.98" + wire $or$libresoc.v:183174$12055_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -389666,11 +380211,11 @@ module \rok_l$59 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:188938.7-188938.15" + attribute \src "libresoc.v:183133.7-183133.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -389687,7 +380232,7 @@ module \rok_l$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:188973$12346 + cell $and $and$libresoc.v:183168$12049 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389695,10 +380240,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:188973$12346_Y + connect \Y $and$libresoc.v:183168$12049_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:188978$12351 + cell $and $and$libresoc.v:183173$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389706,34 +380251,34 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:188978$12351_Y + connect \Y $and$libresoc.v:183173$12054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:188975$12348 + cell $not $not$libresoc.v:183170$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:188975$12348_Y + connect \Y $not$libresoc.v:183170$12051_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:188977$12350 + cell $not $not$libresoc.v:183172$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188977$12350_Y + connect \Y $not$libresoc.v:183172$12053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:188980$12353 + cell $not $not$libresoc.v:183175$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:188980$12353_Y + connect \Y $not$libresoc.v:183175$12056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:188974$12347 + cell $or $or$libresoc.v:183169$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389741,10 +380286,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:188974$12347_Y + connect \Y $or$libresoc.v:183169$12050_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:188976$12349 + cell $or $or$libresoc.v:183171$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389752,10 +380297,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:188976$12349_Y + connect \Y $or$libresoc.v:183171$12052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:188979$12352 + cell $or $or$libresoc.v:183174$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389763,39 +380308,39 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:188979$12352_Y + connect \Y $or$libresoc.v:183174$12055_Y end - attribute \src "libresoc.v:188938.7-188938.20" - process $proc$libresoc.v:188938$12358 + attribute \src "libresoc.v:183133.7-183133.20" + process $proc$libresoc.v:183133$12061 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188960.7-188960.19" - process $proc$libresoc.v:188960$12359 + attribute \src "libresoc.v:183155.7-183155.19" + process $proc$libresoc.v:183155$12062 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:188981.3-188982.27" - process $proc$libresoc.v:188981$12354 + attribute \src "libresoc.v:183176.3-183177.27" + process $proc$libresoc.v:183176$12057 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:188983.3-188991.6" - process $proc$libresoc.v:188983$12355 + attribute \src "libresoc.v:183178.3-183186.6" + process $proc$libresoc.v:183178$12058 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12356 $1\q_int$next[0:0]$12357 - attribute \src "libresoc.v:188984.5-188984.29" + assign $0\q_int$next[0:0]$12059 $1\q_int$next[0:0]$12060 + attribute \src "libresoc.v:183179.5-183179.29" switch \initial - attribute \src "libresoc.v:188984.9-188984.17" + attribute \src "libresoc.v:183179.9-183179.17" case 1'1 case end @@ -389804,56 +380349,56 @@ module \rok_l$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12357 1'0 + assign $1\q_int$next[0:0]$12060 1'0 case - assign $1\q_int$next[0:0]$12357 \$5 + assign $1\q_int$next[0:0]$12060 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12356 + update \q_int$next $0\q_int$next[0:0]$12059 end - connect \$9 $and$libresoc.v:188973$12346_Y - connect \$11 $or$libresoc.v:188974$12347_Y - connect \$13 $not$libresoc.v:188975$12348_Y - connect \$15 $or$libresoc.v:188976$12349_Y - connect \$1 $not$libresoc.v:188977$12350_Y - connect \$3 $and$libresoc.v:188978$12351_Y - connect \$5 $or$libresoc.v:188979$12352_Y - connect \$7 $not$libresoc.v:188980$12353_Y + connect \$9 $and$libresoc.v:183168$12049_Y + connect \$11 $or$libresoc.v:183169$12050_Y + connect \$13 $not$libresoc.v:183170$12051_Y + connect \$15 $or$libresoc.v:183171$12052_Y + connect \$1 $not$libresoc.v:183172$12053_Y + connect \$3 $and$libresoc.v:183173$12054_Y + connect \$5 $or$libresoc.v:183174$12055_Y + connect \$7 $not$libresoc.v:183175$12056_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:188999.1-189057.10" +attribute \src "libresoc.v:183194.1-183252.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" module \rok_l$71 - attribute \src "libresoc.v:189000.7-189000.20" + attribute \src "libresoc.v:183195.7-183195.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189045.3-189053.6" - wire $0\q_int$next[0:0]$12370 - attribute \src "libresoc.v:189043.3-189044.27" + attribute \src "libresoc.v:183240.3-183248.6" + wire $0\q_int$next[0:0]$12073 + attribute \src "libresoc.v:183238.3-183239.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:189045.3-189053.6" - wire $1\q_int$next[0:0]$12371 - attribute \src "libresoc.v:189022.7-189022.19" + attribute \src "libresoc.v:183240.3-183248.6" + wire $1\q_int$next[0:0]$12074 + attribute \src "libresoc.v:183217.7-183217.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:189035.17-189035.96" - wire $and$libresoc.v:189035$12360_Y - attribute \src "libresoc.v:189040.17-189040.96" - wire $and$libresoc.v:189040$12365_Y - attribute \src "libresoc.v:189037.18-189037.94" - wire $not$libresoc.v:189037$12362_Y - attribute \src "libresoc.v:189039.17-189039.93" - wire $not$libresoc.v:189039$12364_Y - attribute \src "libresoc.v:189042.17-189042.93" - wire $not$libresoc.v:189042$12367_Y - attribute \src "libresoc.v:189036.18-189036.99" - wire $or$libresoc.v:189036$12361_Y - attribute \src "libresoc.v:189038.18-189038.100" - wire $or$libresoc.v:189038$12363_Y - attribute \src "libresoc.v:189041.17-189041.98" - wire $or$libresoc.v:189041$12366_Y + attribute \src "libresoc.v:183230.17-183230.96" + wire $and$libresoc.v:183230$12063_Y + attribute \src "libresoc.v:183235.17-183235.96" + wire $and$libresoc.v:183235$12068_Y + attribute \src "libresoc.v:183232.18-183232.94" + wire $not$libresoc.v:183232$12065_Y + attribute \src "libresoc.v:183234.17-183234.93" + wire $not$libresoc.v:183234$12067_Y + attribute \src "libresoc.v:183237.17-183237.93" + wire $not$libresoc.v:183237$12070_Y + attribute \src "libresoc.v:183231.18-183231.99" + wire $or$libresoc.v:183231$12064_Y + attribute \src "libresoc.v:183233.18-183233.100" + wire $or$libresoc.v:183233$12066_Y + attribute \src "libresoc.v:183236.17-183236.98" + wire $or$libresoc.v:183236$12069_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -389870,11 +380415,11 @@ module \rok_l$71 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189000.7-189000.15" + attribute \src "libresoc.v:183195.7-183195.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -389891,7 +380436,7 @@ module \rok_l$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:189035$12360 + cell $and $and$libresoc.v:183230$12063 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389899,10 +380444,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:189035$12360_Y + connect \Y $and$libresoc.v:183230$12063_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:189040$12365 + cell $and $and$libresoc.v:183235$12068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389910,34 +380455,34 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:189040$12365_Y + connect \Y $and$libresoc.v:183235$12068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:189037$12362 + cell $not $not$libresoc.v:183232$12065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:189037$12362_Y + connect \Y $not$libresoc.v:183232$12065_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:189039$12364 + cell $not $not$libresoc.v:183234$12067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:189039$12364_Y + connect \Y $not$libresoc.v:183234$12067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:189042$12367 + cell $not $not$libresoc.v:183237$12070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:189042$12367_Y + connect \Y $not$libresoc.v:183237$12070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:189036$12361 + cell $or $or$libresoc.v:183231$12064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389945,10 +380490,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:189036$12361_Y + connect \Y $or$libresoc.v:183231$12064_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:189038$12363 + cell $or $or$libresoc.v:183233$12066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389956,10 +380501,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:189038$12363_Y + connect \Y $or$libresoc.v:183233$12066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:189041$12366 + cell $or $or$libresoc.v:183236$12069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389967,39 +380512,39 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:189041$12366_Y + connect \Y $or$libresoc.v:183236$12069_Y end - attribute \src "libresoc.v:189000.7-189000.20" - process $proc$libresoc.v:189000$12372 + attribute \src "libresoc.v:183195.7-183195.20" + process $proc$libresoc.v:183195$12075 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189022.7-189022.19" - process $proc$libresoc.v:189022$12373 + attribute \src "libresoc.v:183217.7-183217.19" + process $proc$libresoc.v:183217$12076 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:189043.3-189044.27" - process $proc$libresoc.v:189043$12368 + attribute \src "libresoc.v:183238.3-183239.27" + process $proc$libresoc.v:183238$12071 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:189045.3-189053.6" - process $proc$libresoc.v:189045$12369 + attribute \src "libresoc.v:183240.3-183248.6" + process $proc$libresoc.v:183240$12072 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12370 $1\q_int$next[0:0]$12371 - attribute \src "libresoc.v:189046.5-189046.29" + assign $0\q_int$next[0:0]$12073 $1\q_int$next[0:0]$12074 + attribute \src "libresoc.v:183241.5-183241.29" switch \initial - attribute \src "libresoc.v:189046.9-189046.17" + attribute \src "libresoc.v:183241.9-183241.17" case 1'1 case end @@ -390008,56 +380553,56 @@ module \rok_l$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12371 1'0 + assign $1\q_int$next[0:0]$12074 1'0 case - assign $1\q_int$next[0:0]$12371 \$5 + assign $1\q_int$next[0:0]$12074 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12370 + update \q_int$next $0\q_int$next[0:0]$12073 end - connect \$9 $and$libresoc.v:189035$12360_Y - connect \$11 $or$libresoc.v:189036$12361_Y - connect \$13 $not$libresoc.v:189037$12362_Y - connect \$15 $or$libresoc.v:189038$12363_Y - connect \$1 $not$libresoc.v:189039$12364_Y - connect \$3 $and$libresoc.v:189040$12365_Y - connect \$5 $or$libresoc.v:189041$12366_Y - connect \$7 $not$libresoc.v:189042$12367_Y + connect \$9 $and$libresoc.v:183230$12063_Y + connect \$11 $or$libresoc.v:183231$12064_Y + connect \$13 $not$libresoc.v:183232$12065_Y + connect \$15 $or$libresoc.v:183233$12066_Y + connect \$1 $not$libresoc.v:183234$12067_Y + connect \$3 $and$libresoc.v:183235$12068_Y + connect \$5 $or$libresoc.v:183236$12069_Y + connect \$7 $not$libresoc.v:183237$12070_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:189061.1-189119.10" +attribute \src "libresoc.v:183256.1-183314.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" module \rok_l$88 - attribute \src "libresoc.v:189062.7-189062.20" + attribute \src "libresoc.v:183257.7-183257.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189107.3-189115.6" - wire $0\q_int$next[0:0]$12384 - attribute \src "libresoc.v:189105.3-189106.27" + attribute \src "libresoc.v:183302.3-183310.6" + wire $0\q_int$next[0:0]$12087 + attribute \src "libresoc.v:183300.3-183301.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:189107.3-189115.6" - wire $1\q_int$next[0:0]$12385 - attribute \src "libresoc.v:189084.7-189084.19" + attribute \src "libresoc.v:183302.3-183310.6" + wire $1\q_int$next[0:0]$12088 + attribute \src "libresoc.v:183279.7-183279.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:189097.17-189097.96" - wire $and$libresoc.v:189097$12374_Y - attribute \src "libresoc.v:189102.17-189102.96" - wire $and$libresoc.v:189102$12379_Y - attribute \src "libresoc.v:189099.18-189099.94" - wire $not$libresoc.v:189099$12376_Y - attribute \src "libresoc.v:189101.17-189101.93" - wire $not$libresoc.v:189101$12378_Y - attribute \src "libresoc.v:189104.17-189104.93" - wire $not$libresoc.v:189104$12381_Y - attribute \src "libresoc.v:189098.18-189098.99" - wire $or$libresoc.v:189098$12375_Y - attribute \src "libresoc.v:189100.18-189100.100" - wire $or$libresoc.v:189100$12377_Y - attribute \src "libresoc.v:189103.17-189103.98" - wire $or$libresoc.v:189103$12380_Y + attribute \src "libresoc.v:183292.17-183292.96" + wire $and$libresoc.v:183292$12077_Y + attribute \src "libresoc.v:183297.17-183297.96" + wire $and$libresoc.v:183297$12082_Y + attribute \src "libresoc.v:183294.18-183294.94" + wire $not$libresoc.v:183294$12079_Y + attribute \src "libresoc.v:183296.17-183296.93" + wire $not$libresoc.v:183296$12081_Y + attribute \src "libresoc.v:183299.17-183299.93" + wire $not$libresoc.v:183299$12084_Y + attribute \src "libresoc.v:183293.18-183293.99" + wire $or$libresoc.v:183293$12078_Y + attribute \src "libresoc.v:183295.18-183295.100" + wire $or$libresoc.v:183295$12080_Y + attribute \src "libresoc.v:183298.17-183298.98" + wire $or$libresoc.v:183298$12083_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -390074,11 +380619,11 @@ module \rok_l$88 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189062.7-189062.15" + attribute \src "libresoc.v:183257.7-183257.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -390095,7 +380640,7 @@ module \rok_l$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:189097$12374 + cell $and $and$libresoc.v:183292$12077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390103,10 +380648,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:189097$12374_Y + connect \Y $and$libresoc.v:183292$12077_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:189102$12379 + cell $and $and$libresoc.v:183297$12082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390114,34 +380659,34 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:189102$12379_Y + connect \Y $and$libresoc.v:183297$12082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:189099$12376 + cell $not $not$libresoc.v:183294$12079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:189099$12376_Y + connect \Y $not$libresoc.v:183294$12079_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:189101$12378 + cell $not $not$libresoc.v:183296$12081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:189101$12378_Y + connect \Y $not$libresoc.v:183296$12081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:189104$12381 + cell $not $not$libresoc.v:183299$12084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:189104$12381_Y + connect \Y $not$libresoc.v:183299$12084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:189098$12375 + cell $or $or$libresoc.v:183293$12078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390149,10 +380694,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:189098$12375_Y + connect \Y $or$libresoc.v:183293$12078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:189100$12377 + cell $or $or$libresoc.v:183295$12080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390160,10 +380705,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:189100$12377_Y + connect \Y $or$libresoc.v:183295$12080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:189103$12380 + cell $or $or$libresoc.v:183298$12083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390171,39 +380716,39 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:189103$12380_Y + connect \Y $or$libresoc.v:183298$12083_Y end - attribute \src "libresoc.v:189062.7-189062.20" - process $proc$libresoc.v:189062$12386 + attribute \src "libresoc.v:183257.7-183257.20" + process $proc$libresoc.v:183257$12089 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189084.7-189084.19" - process $proc$libresoc.v:189084$12387 + attribute \src "libresoc.v:183279.7-183279.19" + process $proc$libresoc.v:183279$12090 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:189105.3-189106.27" - process $proc$libresoc.v:189105$12382 + attribute \src "libresoc.v:183300.3-183301.27" + process $proc$libresoc.v:183300$12085 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:189107.3-189115.6" - process $proc$libresoc.v:189107$12383 + attribute \src "libresoc.v:183302.3-183310.6" + process $proc$libresoc.v:183302$12086 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12384 $1\q_int$next[0:0]$12385 - attribute \src "libresoc.v:189108.5-189108.29" + assign $0\q_int$next[0:0]$12087 $1\q_int$next[0:0]$12088 + attribute \src "libresoc.v:183303.5-183303.29" switch \initial - attribute \src "libresoc.v:189108.9-189108.17" + attribute \src "libresoc.v:183303.9-183303.17" case 1'1 case end @@ -390212,150 +380757,150 @@ module \rok_l$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12385 1'0 + assign $1\q_int$next[0:0]$12088 1'0 case - assign $1\q_int$next[0:0]$12385 \$5 + assign $1\q_int$next[0:0]$12088 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12384 + update \q_int$next $0\q_int$next[0:0]$12087 end - connect \$9 $and$libresoc.v:189097$12374_Y - connect \$11 $or$libresoc.v:189098$12375_Y - connect \$13 $not$libresoc.v:189099$12376_Y - connect \$15 $or$libresoc.v:189100$12377_Y - connect \$1 $not$libresoc.v:189101$12378_Y - connect \$3 $and$libresoc.v:189102$12379_Y - connect \$5 $or$libresoc.v:189103$12380_Y - connect \$7 $not$libresoc.v:189104$12381_Y + connect \$9 $and$libresoc.v:183292$12077_Y + connect \$11 $or$libresoc.v:183293$12078_Y + connect \$13 $not$libresoc.v:183294$12079_Y + connect \$15 $or$libresoc.v:183295$12080_Y + connect \$1 $not$libresoc.v:183296$12081_Y + connect \$3 $and$libresoc.v:183297$12082_Y + connect \$5 $or$libresoc.v:183298$12083_Y + connect \$7 $not$libresoc.v:183299$12084_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:189123.1-189474.10" +attribute \src "libresoc.v:183318.1-183669.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator - attribute \src "libresoc.v:189392.3-189401.6" + attribute \src "libresoc.v:183587.3-183596.6" wire $0\carry_out_o[0:0] - attribute \src "libresoc.v:189324.3-189338.6" + attribute \src "libresoc.v:183519.3-183533.6" wire width 32 $0\hi32[31:0] - attribute \src "libresoc.v:189124.7-189124.20" + attribute \src "libresoc.v:183319.7-183319.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189414.3-189447.6" - wire width 7 $0\mb$8[6:0]$12435 - attribute \src "libresoc.v:189448.3-189462.6" - wire width 7 $0\me$13[6:0]$12440 - attribute \src "libresoc.v:189349.3-189360.6" + attribute \src "libresoc.v:183609.3-183642.6" + wire width 7 $0\mb$8[6:0]$12138 + attribute \src "libresoc.v:183643.3-183657.6" + wire width 7 $0\me$13[6:0]$12143 + attribute \src "libresoc.v:183544.3-183555.6" wire width 64 $0\mr[63:0] - attribute \src "libresoc.v:189361.3-189372.6" + attribute \src "libresoc.v:183556.3-183567.6" wire width 2 $0\output_mode[1:0] - attribute \src "libresoc.v:189373.3-189391.6" + attribute \src "libresoc.v:183568.3-183586.6" wire width 64 $0\result_o[63:0] - attribute \src "libresoc.v:189339.3-189348.6" + attribute \src "libresoc.v:183534.3-183543.6" wire width 7 $0\right_mask_shift[6:0] - attribute \src "libresoc.v:189402.3-189413.6" + attribute \src "libresoc.v:183597.3-183608.6" wire width 6 $0\rot_count[5:0] - attribute \src "libresoc.v:189392.3-189401.6" + attribute \src "libresoc.v:183587.3-183596.6" wire $1\carry_out_o[0:0] - attribute \src "libresoc.v:189324.3-189338.6" + attribute \src "libresoc.v:183519.3-183533.6" wire width 32 $1\hi32[31:0] - attribute \src "libresoc.v:189414.3-189447.6" - wire width 7 $1\mb$8[6:0]$12436 - attribute \src "libresoc.v:189448.3-189462.6" - wire width 7 $1\me$13[6:0]$12441 - attribute \src "libresoc.v:189349.3-189360.6" + attribute \src "libresoc.v:183609.3-183642.6" + wire width 7 $1\mb$8[6:0]$12139 + attribute \src "libresoc.v:183643.3-183657.6" + wire width 7 $1\me$13[6:0]$12144 + attribute \src "libresoc.v:183544.3-183555.6" wire width 64 $1\mr[63:0] - attribute \src "libresoc.v:189361.3-189372.6" + attribute \src "libresoc.v:183556.3-183567.6" wire width 2 $1\output_mode[1:0] - attribute \src "libresoc.v:189373.3-189391.6" + attribute \src "libresoc.v:183568.3-183586.6" wire width 64 $1\result_o[63:0] - attribute \src "libresoc.v:189339.3-189348.6" + attribute \src "libresoc.v:183534.3-183543.6" wire width 7 $1\right_mask_shift[6:0] - attribute \src "libresoc.v:189402.3-189413.6" + attribute \src "libresoc.v:183597.3-183608.6" wire width 6 $1\rot_count[5:0] - attribute \src "libresoc.v:189414.3-189447.6" - wire width 2 $2\mb$8[6:5]$12437 - attribute \src "libresoc.v:189414.3-189447.6" - wire width 2 $3\mb$8[6:5]$12438 - attribute \src "libresoc.v:189275.18-189275.118" - wire $and$libresoc.v:189275$12391_Y - attribute \src "libresoc.v:189277.18-189277.114" - wire $and$libresoc.v:189277$12393_Y - attribute \src "libresoc.v:189286.18-189286.113" - wire $and$libresoc.v:189286$12402_Y - attribute \src "libresoc.v:189288.18-189288.114" - wire $and$libresoc.v:189288$12404_Y - attribute \src "libresoc.v:189290.18-189290.114" - wire $and$libresoc.v:189290$12406_Y - attribute \src "libresoc.v:189291.18-189291.103" - wire width 64 $and$libresoc.v:189291$12407_Y - attribute \src "libresoc.v:189292.18-189292.106" - wire width 64 $and$libresoc.v:189292$12408_Y - attribute \src "libresoc.v:189294.18-189294.103" - wire width 64 $and$libresoc.v:189294$12410_Y - attribute \src "libresoc.v:189296.18-189296.105" - wire width 64 $and$libresoc.v:189296$12412_Y - attribute \src "libresoc.v:189299.18-189299.106" - wire width 64 $and$libresoc.v:189299$12415_Y - attribute \src "libresoc.v:189302.18-189302.105" - wire width 64 $and$libresoc.v:189302$12418_Y - attribute \src "libresoc.v:189304.17-189304.109" - wire $and$libresoc.v:189304$12420_Y - attribute \src "libresoc.v:189305.18-189305.104" - wire width 64 $and$libresoc.v:189305$12421_Y - attribute \src "libresoc.v:189309.18-189309.105" - wire width 64 $and$libresoc.v:189309$12425_Y - attribute \src "libresoc.v:189273.17-189273.98" - wire width 7 $extend$libresoc.v:189273$12388_Y - attribute \src "libresoc.v:189289.18-189289.122" - wire $gt$libresoc.v:189289$12405_Y - attribute \src "libresoc.v:189279.18-189279.111" - wire $le$libresoc.v:189279$12395_Y - attribute \src "libresoc.v:189281.18-189281.111" - wire $le$libresoc.v:189281$12397_Y - attribute \src "libresoc.v:189282.17-189282.117" - wire width 7 $neg$libresoc.v:189282$12398_Y - attribute \src "libresoc.v:189274.18-189274.103" - wire $not$libresoc.v:189274$12390_Y - attribute \src "libresoc.v:189276.18-189276.108" - wire $not$libresoc.v:189276$12392_Y - attribute \src "libresoc.v:189278.18-189278.105" - wire width 6 $not$libresoc.v:189278$12394_Y - attribute \src "libresoc.v:189284.18-189284.112" - wire width 64 $not$libresoc.v:189284$12400_Y - attribute \src "libresoc.v:189285.18-189285.109" - wire $not$libresoc.v:189285$12401_Y - attribute \src "libresoc.v:189293.17-189293.105" - wire $not$libresoc.v:189293$12409_Y - attribute \src "libresoc.v:189295.18-189295.102" - wire width 64 $not$libresoc.v:189295$12411_Y - attribute \src "libresoc.v:189301.18-189301.102" - wire width 64 $not$libresoc.v:189301$12417_Y - attribute \src "libresoc.v:189306.18-189306.100" - wire width 64 $not$libresoc.v:189306$12422_Y - attribute \src "libresoc.v:189308.18-189308.100" - wire width 64 $not$libresoc.v:189308$12424_Y - attribute \src "libresoc.v:189287.18-189287.115" - wire $or$libresoc.v:189287$12403_Y - attribute \src "libresoc.v:189297.18-189297.108" - wire width 64 $or$libresoc.v:189297$12413_Y - attribute \src "libresoc.v:189298.18-189298.103" - wire width 64 $or$libresoc.v:189298$12414_Y - attribute \src "libresoc.v:189300.18-189300.103" - wire width 64 $or$libresoc.v:189300$12416_Y - attribute \src "libresoc.v:189303.18-189303.108" - wire width 64 $or$libresoc.v:189303$12419_Y - attribute \src "libresoc.v:189307.18-189307.106" - wire width 64 $or$libresoc.v:189307$12423_Y - attribute \src "libresoc.v:189273.17-189273.98" - wire width 7 $pos$libresoc.v:189273$12389_Y - attribute \src "libresoc.v:189310.18-189310.102" - wire $reduce_or$libresoc.v:189310$12426_Y - attribute \src "libresoc.v:189280.18-189280.109" - wire width 8 $sub$libresoc.v:189280$12396_Y - attribute \src "libresoc.v:189283.18-189283.110" - wire width 8 $sub$libresoc.v:189283$12399_Y + attribute \src "libresoc.v:183609.3-183642.6" + wire width 2 $2\mb$8[6:5]$12140 + attribute \src "libresoc.v:183609.3-183642.6" + wire width 2 $3\mb$8[6:5]$12141 + attribute \src "libresoc.v:183470.18-183470.118" + wire $and$libresoc.v:183470$12094_Y + attribute \src "libresoc.v:183472.18-183472.114" + wire $and$libresoc.v:183472$12096_Y + attribute \src "libresoc.v:183481.18-183481.113" + wire $and$libresoc.v:183481$12105_Y + attribute \src "libresoc.v:183483.18-183483.114" + wire $and$libresoc.v:183483$12107_Y + attribute \src "libresoc.v:183485.18-183485.114" + wire $and$libresoc.v:183485$12109_Y + attribute \src "libresoc.v:183486.18-183486.103" + wire width 64 $and$libresoc.v:183486$12110_Y + attribute \src "libresoc.v:183487.18-183487.106" + wire width 64 $and$libresoc.v:183487$12111_Y + attribute \src "libresoc.v:183489.18-183489.103" + wire width 64 $and$libresoc.v:183489$12113_Y + attribute \src "libresoc.v:183491.18-183491.105" + wire width 64 $and$libresoc.v:183491$12115_Y + attribute \src "libresoc.v:183494.18-183494.106" + wire width 64 $and$libresoc.v:183494$12118_Y + attribute \src "libresoc.v:183497.18-183497.105" + wire width 64 $and$libresoc.v:183497$12121_Y + attribute \src "libresoc.v:183499.17-183499.109" + wire $and$libresoc.v:183499$12123_Y + attribute \src "libresoc.v:183500.18-183500.104" + wire width 64 $and$libresoc.v:183500$12124_Y + attribute \src "libresoc.v:183504.18-183504.105" + wire width 64 $and$libresoc.v:183504$12128_Y + attribute \src "libresoc.v:183468.17-183468.98" + wire width 7 $extend$libresoc.v:183468$12091_Y + attribute \src "libresoc.v:183484.18-183484.122" + wire $gt$libresoc.v:183484$12108_Y + attribute \src "libresoc.v:183474.18-183474.111" + wire $le$libresoc.v:183474$12098_Y + attribute \src "libresoc.v:183476.18-183476.111" + wire $le$libresoc.v:183476$12100_Y + attribute \src "libresoc.v:183477.17-183477.117" + wire width 7 $neg$libresoc.v:183477$12101_Y + attribute \src "libresoc.v:183469.18-183469.103" + wire $not$libresoc.v:183469$12093_Y + attribute \src "libresoc.v:183471.18-183471.108" + wire $not$libresoc.v:183471$12095_Y + attribute \src "libresoc.v:183473.18-183473.105" + wire width 6 $not$libresoc.v:183473$12097_Y + attribute \src "libresoc.v:183479.18-183479.112" + wire width 64 $not$libresoc.v:183479$12103_Y + attribute \src "libresoc.v:183480.18-183480.109" + wire $not$libresoc.v:183480$12104_Y + attribute \src "libresoc.v:183488.17-183488.105" + wire $not$libresoc.v:183488$12112_Y + attribute \src "libresoc.v:183490.18-183490.102" + wire width 64 $not$libresoc.v:183490$12114_Y + attribute \src "libresoc.v:183496.18-183496.102" + wire width 64 $not$libresoc.v:183496$12120_Y + attribute \src "libresoc.v:183501.18-183501.100" + wire width 64 $not$libresoc.v:183501$12125_Y + attribute \src "libresoc.v:183503.18-183503.100" + wire width 64 $not$libresoc.v:183503$12127_Y + attribute \src "libresoc.v:183482.18-183482.115" + wire $or$libresoc.v:183482$12106_Y + attribute \src "libresoc.v:183492.18-183492.108" + wire width 64 $or$libresoc.v:183492$12116_Y + attribute \src "libresoc.v:183493.18-183493.103" + wire width 64 $or$libresoc.v:183493$12117_Y + attribute \src "libresoc.v:183495.18-183495.103" + wire width 64 $or$libresoc.v:183495$12119_Y + attribute \src "libresoc.v:183498.18-183498.108" + wire width 64 $or$libresoc.v:183498$12122_Y + attribute \src "libresoc.v:183502.18-183502.106" + wire width 64 $or$libresoc.v:183502$12126_Y + attribute \src "libresoc.v:183468.17-183468.98" + wire width 7 $pos$libresoc.v:183468$12092_Y + attribute \src "libresoc.v:183505.18-183505.102" + wire $reduce_or$libresoc.v:183505$12129_Y + attribute \src "libresoc.v:183475.18-183475.109" + wire width 8 $sub$libresoc.v:183475$12099_Y + attribute \src "libresoc.v:183478.18-183478.110" + wire width 8 $sub$libresoc.v:183478$12102_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" @@ -390448,7 +380993,7 @@ module \rotator wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 - attribute \src "libresoc.v:189124.7-189124.15" + attribute \src "libresoc.v:183319.7-183319.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit @@ -390505,7 +381050,7 @@ module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $and$libresoc.v:189275$12391 + cell $and $and$libresoc.v:183470$12094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390513,10 +381058,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit - connect \Y $and$libresoc.v:189275$12391_Y + connect \Y $and$libresoc.v:183470$12094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $and$libresoc.v:189277$12393 + cell $and $and$libresoc.v:183472$12096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390524,10 +381069,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 - connect \Y $and$libresoc.v:189277$12393_Y + connect \Y $and$libresoc.v:183472$12096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $and$libresoc.v:189286$12402 + cell $and $and$libresoc.v:183481$12105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390535,10 +381080,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 - connect \Y $and$libresoc.v:189286$12402_Y + connect \Y $and$libresoc.v:183481$12105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$libresoc.v:189288$12404 + cell $and $and$libresoc.v:183483$12107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390546,10 +381091,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] - connect \Y $and$libresoc.v:189288$12404_Y + connect \Y $and$libresoc.v:183483$12107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$libresoc.v:189290$12406 + cell $and $and$libresoc.v:183485$12109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390557,10 +381102,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 - connect \Y $and$libresoc.v:189290$12406_Y + connect \Y $and$libresoc.v:183485$12109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:189291$12407 + cell $and $and$libresoc.v:183486$12110 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390568,10 +381113,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:189291$12407_Y + connect \Y $and$libresoc.v:183486$12110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:189292$12408 + cell $and $and$libresoc.v:183487$12111 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390579,10 +381124,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 - connect \Y $and$libresoc.v:189292$12408_Y + connect \Y $and$libresoc.v:183487$12111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:189294$12410 + cell $and $and$libresoc.v:183489$12113 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390590,10 +381135,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:189294$12410_Y + connect \Y $and$libresoc.v:183489$12113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:189296$12412 + cell $and $and$libresoc.v:183491$12115 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390601,10 +381146,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 - connect \Y $and$libresoc.v:189296$12412_Y + connect \Y $and$libresoc.v:183491$12115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:189299$12415 + cell $and $and$libresoc.v:183494$12118 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390612,10 +381157,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 - connect \Y $and$libresoc.v:189299$12415_Y + connect \Y $and$libresoc.v:183494$12118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:189302$12418 + cell $and $and$libresoc.v:183497$12121 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390623,10 +381168,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 - connect \Y $and$libresoc.v:189302$12418_Y + connect \Y $and$libresoc.v:183497$12121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$libresoc.v:189304$12420 + cell $and $and$libresoc.v:183499$12123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390634,10 +381179,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 - connect \Y $and$libresoc.v:189304$12420_Y + connect \Y $and$libresoc.v:183499$12123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$libresoc.v:189305$12421 + cell $and $and$libresoc.v:183500$12124 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390645,10 +381190,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \mr - connect \Y $and$libresoc.v:189305$12421_Y + connect \Y $and$libresoc.v:183500$12124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:189309$12425 + cell $and $and$libresoc.v:183504$12128 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390656,18 +381201,18 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 - connect \Y $and$libresoc.v:189309$12425_Y + connect \Y $and$libresoc.v:183504$12128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:189273$12388 + cell $pos $extend$libresoc.v:183468$12091 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb - connect \Y $extend$libresoc.v:189273$12388_Y + connect \Y $extend$libresoc.v:183468$12091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:189289$12405 + cell $gt $gt$libresoc.v:183484$12108 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390675,10 +381220,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:189289$12405_Y + connect \Y $gt$libresoc.v:183484$12108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:189279$12395 + cell $le $le$libresoc.v:183474$12098 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -390686,10 +381231,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:189279$12395_Y + connect \Y $le$libresoc.v:183474$12098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:189281$12397 + cell $le $le$libresoc.v:183476$12100 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -390697,98 +381242,98 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:189281$12397_Y + connect \Y $le$libresoc.v:183476$12100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$libresoc.v:189282$12398 + cell $neg $neg$libresoc.v:183477$12101 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$libresoc.v:189282$12398_Y + connect \Y $neg$libresoc.v:183477$12101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$libresoc.v:189274$12390 + cell $not $not$libresoc.v:183469$12093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] - connect \Y $not$libresoc.v:189274$12390_Y + connect \Y $not$libresoc.v:183469$12093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:189276$12392 + cell $not $not$libresoc.v:183471$12095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left - connect \Y $not$libresoc.v:189276$12392_Y + connect \Y $not$libresoc.v:183471$12095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:189278$12394 + cell $not $not$libresoc.v:183473$12097 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] - connect \Y $not$libresoc.v:189278$12394_Y + connect \Y $not$libresoc.v:183473$12097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:189284$12400 + cell $not $not$libresoc.v:183479$12103 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask - connect \Y $not$libresoc.v:189284$12400_Y + connect \Y $not$libresoc.v:183479$12103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$libresoc.v:189285$12401 + cell $not $not$libresoc.v:183480$12104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right - connect \Y $not$libresoc.v:189285$12401_Y + connect \Y $not$libresoc.v:183480$12104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$libresoc.v:189293$12409 + cell $not $not$libresoc.v:183488$12112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit - connect \Y $not$libresoc.v:189293$12409_Y + connect \Y $not$libresoc.v:183488$12112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$libresoc.v:189295$12411 + cell $not $not$libresoc.v:183490$12114 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 - connect \Y $not$libresoc.v:189295$12411_Y + connect \Y $not$libresoc.v:183490$12114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$libresoc.v:189301$12417 + cell $not $not$libresoc.v:183496$12120 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 - connect \Y $not$libresoc.v:189301$12417_Y + connect \Y $not$libresoc.v:183496$12120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:189306$12422 + cell $not $not$libresoc.v:183501$12125 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr - connect \Y $not$libresoc.v:189306$12422_Y + connect \Y $not$libresoc.v:183501$12125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:189308$12424 + cell $not $not$libresoc.v:183503$12127 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml - connect \Y $not$libresoc.v:189308$12424_Y + connect \Y $not$libresoc.v:183503$12127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:189287$12403 + cell $or $or$libresoc.v:183482$12106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390796,10 +381341,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift - connect \Y $or$libresoc.v:189287$12403_Y + connect \Y $or$libresoc.v:183482$12106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:189297$12413 + cell $or $or$libresoc.v:183492$12116 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390807,10 +381352,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 - connect \Y $or$libresoc.v:189297$12413_Y + connect \Y $or$libresoc.v:183492$12116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:189298$12414 + cell $or $or$libresoc.v:183493$12117 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390818,10 +381363,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:189298$12414_Y + connect \Y $or$libresoc.v:183493$12117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:189300$12416 + cell $or $or$libresoc.v:183495$12119 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390829,10 +381374,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:189300$12416_Y + connect \Y $or$libresoc.v:183495$12119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:189303$12419 + cell $or $or$libresoc.v:183498$12122 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390840,10 +381385,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 - connect \Y $or$libresoc.v:189303$12419_Y + connect \Y $or$libresoc.v:183498$12122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:189307$12423 + cell $or $or$libresoc.v:183502$12126 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -390851,26 +381396,26 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 - connect \Y $or$libresoc.v:189307$12423_Y + connect \Y $or$libresoc.v:183502$12126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:189273$12389 + cell $pos $pos$libresoc.v:183468$12092 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:189273$12388_Y - connect \Y $pos$libresoc.v:189273$12389_Y + connect \A $extend$libresoc.v:183468$12091_Y + connect \Y $pos$libresoc.v:183468$12092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:189310$12426 + cell $reduce_or $reduce_or$libresoc.v:183505$12129 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 - connect \Y $reduce_or$libresoc.v:189310$12426_Y + connect \Y $reduce_or$libresoc.v:183505$12129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:189280$12396 + cell $sub $sub$libresoc.v:183475$12099 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -390878,10 +381423,10 @@ module \rotator parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 - connect \Y $sub$libresoc.v:189280$12396_Y + connect \Y $sub$libresoc.v:183475$12099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:189283$12399 + cell $sub $sub$libresoc.v:183478$12102 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390889,42 +381434,42 @@ module \rotator parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 - connect \Y $sub$libresoc.v:189283$12399_Y + connect \Y $sub$libresoc.v:183478$12102_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189311.13-189314.4" + attribute \src "libresoc.v:183506.13-183509.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:189315.14-189318.4" + attribute \src "libresoc.v:183510.14-183513.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:189319.8-189323.4" + attribute \src "libresoc.v:183514.8-183518.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end - attribute \src "libresoc.v:189124.7-189124.20" - process $proc$libresoc.v:189124$12442 + attribute \src "libresoc.v:183319.7-183319.20" + process $proc$libresoc.v:183319$12145 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189324.3-189338.6" - process $proc$libresoc.v:189324$12427 + attribute \src "libresoc.v:183519.3-183533.6" + process $proc$libresoc.v:183519$12130 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:189325.5-189325.29" + attribute \src "libresoc.v:183520.5-183520.29" switch \initial - attribute \src "libresoc.v:189325.9-189325.17" + attribute \src "libresoc.v:183520.9-183520.17" case 1'1 case end @@ -390946,14 +381491,14 @@ module \rotator sync always update \hi32 $0\hi32[31:0] end - attribute \src "libresoc.v:189339.3-189348.6" - process $proc$libresoc.v:189339$12428 + attribute \src "libresoc.v:183534.3-183543.6" + process $proc$libresoc.v:183534$12131 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:189340.5-189340.29" + attribute \src "libresoc.v:183535.5-183535.29" switch \initial - attribute \src "libresoc.v:189340.9-189340.17" + attribute \src "libresoc.v:183535.9-183535.17" case 1'1 case end @@ -390969,13 +381514,13 @@ module \rotator sync always update \right_mask_shift $0\right_mask_shift[6:0] end - attribute \src "libresoc.v:189349.3-189360.6" - process $proc$libresoc.v:189349$12429 + attribute \src "libresoc.v:183544.3-183555.6" + process $proc$libresoc.v:183544$12132 assign { } { } assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:189350.5-189350.29" + attribute \src "libresoc.v:183545.5-183545.29" switch \initial - attribute \src "libresoc.v:189350.9-189350.17" + attribute \src "libresoc.v:183545.9-183545.17" case 1'1 case end @@ -390993,13 +381538,13 @@ module \rotator sync always update \mr $0\mr[63:0] end - attribute \src "libresoc.v:189361.3-189372.6" - process $proc$libresoc.v:189361$12430 + attribute \src "libresoc.v:183556.3-183567.6" + process $proc$libresoc.v:183556$12133 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:189362.5-189362.29" + attribute \src "libresoc.v:183557.5-183557.29" switch \initial - attribute \src "libresoc.v:189362.9-189362.17" + attribute \src "libresoc.v:183557.9-183557.17" case 1'1 case end @@ -391017,14 +381562,14 @@ module \rotator sync always update \output_mode $0\output_mode[1:0] end - attribute \src "libresoc.v:189373.3-189391.6" - process $proc$libresoc.v:189373$12431 + attribute \src "libresoc.v:183568.3-183586.6" + process $proc$libresoc.v:183568$12134 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:189374.5-189374.29" + attribute \src "libresoc.v:183569.5-183569.29" switch \initial - attribute \src "libresoc.v:189374.9-189374.17" + attribute \src "libresoc.v:183569.9-183569.17" case 1'1 case end @@ -391052,14 +381597,14 @@ module \rotator sync always update \result_o $0\result_o[63:0] end - attribute \src "libresoc.v:189392.3-189401.6" - process $proc$libresoc.v:189392$12432 + attribute \src "libresoc.v:183587.3-183596.6" + process $proc$libresoc.v:183587$12135 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:189393.5-189393.29" + attribute \src "libresoc.v:183588.5-183588.29" switch \initial - attribute \src "libresoc.v:189393.9-189393.17" + attribute \src "libresoc.v:183588.9-183588.17" case 1'1 case end @@ -391075,13 +381620,13 @@ module \rotator sync always update \carry_out_o $0\carry_out_o[0:0] end - attribute \src "libresoc.v:189402.3-189413.6" - process $proc$libresoc.v:189402$12433 + attribute \src "libresoc.v:183597.3-183608.6" + process $proc$libresoc.v:183597$12136 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:189403.5-189403.29" + attribute \src "libresoc.v:183598.5-183598.29" switch \initial - attribute \src "libresoc.v:189403.9-189403.17" + attribute \src "libresoc.v:183598.9-183598.17" case 1'1 case end @@ -391099,13 +381644,13 @@ module \rotator sync always update \rot_count $0\rot_count[5:0] end - attribute \src "libresoc.v:189414.3-189447.6" - process $proc$libresoc.v:189414$12434 + attribute \src "libresoc.v:183609.3-183642.6" + process $proc$libresoc.v:183609$12137 assign { } { } - assign $0\mb$8[6:0]$12435 $1\mb$8[6:0]$12436 - attribute \src "libresoc.v:189415.5-189415.29" + assign $0\mb$8[6:0]$12138 $1\mb$8[6:0]$12139 + attribute \src "libresoc.v:183610.5-183610.29" switch \initial - attribute \src "libresoc.v:189415.9-189415.17" + attribute \src "libresoc.v:183610.9-183610.17" case 1'1 case end @@ -391114,48 +381659,48 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\mb$8[6:0]$12436 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$12436 [6:5] $2\mb$8[6:5]$12437 + assign $1\mb$8[6:0]$12139 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$12139 [6:5] $2\mb$8[6:5]$12140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\mb$8[6:5]$12437 2'01 + assign $2\mb$8[6:5]$12140 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\mb$8[6:5]$12437 { 1'0 \mb_extra } + assign $2\mb$8[6:5]$12140 { 1'0 \mb_extra } end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\mb$8[6:0]$12436 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$12436 [6:5] $3\mb$8[6:5]$12438 + assign $1\mb$8[6:0]$12139 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$12139 [6:5] $3\mb$8[6:5]$12141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\mb$8[6:5]$12438 { \sh [5] \$11 } + assign $3\mb$8[6:5]$12141 { \sh [5] \$11 } case - assign $3\mb$8[6:5]$12438 \sh [6:5] + assign $3\mb$8[6:5]$12141 \sh [6:5] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\mb$8[6:0]$12436 { 1'0 \is_32bit 5'00000 } + assign $1\mb$8[6:0]$12139 { 1'0 \is_32bit 5'00000 } end sync always - update \mb$8 $0\mb$8[6:0]$12435 + update \mb$8 $0\mb$8[6:0]$12138 end - attribute \src "libresoc.v:189448.3-189462.6" - process $proc$libresoc.v:189448$12439 + attribute \src "libresoc.v:183643.3-183657.6" + process $proc$libresoc.v:183643$12142 assign { } { } - assign $0\me$13[6:0]$12440 $1\me$13[6:0]$12441 - attribute \src "libresoc.v:189449.5-189449.29" + assign $0\me$13[6:0]$12143 $1\me$13[6:0]$12144 + attribute \src "libresoc.v:183644.5-183644.29" switch \initial - attribute \src "libresoc.v:189449.9-189449.17" + attribute \src "libresoc.v:183644.9-183644.17" case 1'1 case end @@ -391164,57 +381709,57 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\me$13[6:0]$12441 { 2'01 \me } + assign $1\me$13[6:0]$12144 { 2'01 \me } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\me$13[6:0]$12441 { 1'0 \mb_extra \mb } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$12441 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$12440 - end - connect \$9 $pos$libresoc.v:189273$12389_Y - connect \$11 $not$libresoc.v:189274$12390_Y - connect \$14 $and$libresoc.v:189275$12391_Y - connect \$16 $not$libresoc.v:189276$12392_Y - connect \$18 $and$libresoc.v:189277$12393_Y - connect \$20 $not$libresoc.v:189278$12394_Y - connect \$22 $le$libresoc.v:189279$12395_Y - connect \$25 $sub$libresoc.v:189280$12396_Y - connect \$27 $le$libresoc.v:189281$12397_Y - connect \$2 $neg$libresoc.v:189282$12398_Y - connect \$30 $sub$libresoc.v:189283$12399_Y - connect \$32 $not$libresoc.v:189284$12400_Y - connect \$34 $not$libresoc.v:189285$12401_Y - connect \$36 $and$libresoc.v:189286$12402_Y - connect \$38 $or$libresoc.v:189287$12403_Y - connect \$40 $and$libresoc.v:189288$12404_Y - connect \$42 $gt$libresoc.v:189289$12405_Y - connect \$44 $and$libresoc.v:189290$12406_Y - connect \$46 $and$libresoc.v:189291$12407_Y - connect \$48 $and$libresoc.v:189292$12408_Y - connect \$4 $not$libresoc.v:189293$12409_Y - connect \$51 $and$libresoc.v:189294$12410_Y - connect \$50 $not$libresoc.v:189295$12411_Y - connect \$54 $and$libresoc.v:189296$12412_Y - connect \$56 $or$libresoc.v:189297$12413_Y - connect \$58 $or$libresoc.v:189298$12414_Y - connect \$60 $and$libresoc.v:189299$12415_Y - connect \$63 $or$libresoc.v:189300$12416_Y - connect \$62 $not$libresoc.v:189301$12417_Y - connect \$66 $and$libresoc.v:189302$12418_Y - connect \$68 $or$libresoc.v:189303$12419_Y - connect \$6 $and$libresoc.v:189304$12420_Y - connect \$70 $and$libresoc.v:189305$12421_Y - connect \$72 $not$libresoc.v:189306$12422_Y - connect \$74 $or$libresoc.v:189307$12423_Y - connect \$77 $not$libresoc.v:189308$12424_Y - connect \$79 $and$libresoc.v:189309$12425_Y - connect \$76 $reduce_or$libresoc.v:189310$12426_Y + assign $1\me$13[6:0]$12144 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12144 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12143 + end + connect \$9 $pos$libresoc.v:183468$12092_Y + connect \$11 $not$libresoc.v:183469$12093_Y + connect \$14 $and$libresoc.v:183470$12094_Y + connect \$16 $not$libresoc.v:183471$12095_Y + connect \$18 $and$libresoc.v:183472$12096_Y + connect \$20 $not$libresoc.v:183473$12097_Y + connect \$22 $le$libresoc.v:183474$12098_Y + connect \$25 $sub$libresoc.v:183475$12099_Y + connect \$27 $le$libresoc.v:183476$12100_Y + connect \$2 $neg$libresoc.v:183477$12101_Y + connect \$30 $sub$libresoc.v:183478$12102_Y + connect \$32 $not$libresoc.v:183479$12103_Y + connect \$34 $not$libresoc.v:183480$12104_Y + connect \$36 $and$libresoc.v:183481$12105_Y + connect \$38 $or$libresoc.v:183482$12106_Y + connect \$40 $and$libresoc.v:183483$12107_Y + connect \$42 $gt$libresoc.v:183484$12108_Y + connect \$44 $and$libresoc.v:183485$12109_Y + connect \$46 $and$libresoc.v:183486$12110_Y + connect \$48 $and$libresoc.v:183487$12111_Y + connect \$4 $not$libresoc.v:183488$12112_Y + connect \$51 $and$libresoc.v:183489$12113_Y + connect \$50 $not$libresoc.v:183490$12114_Y + connect \$54 $and$libresoc.v:183491$12115_Y + connect \$56 $or$libresoc.v:183492$12116_Y + connect \$58 $or$libresoc.v:183493$12117_Y + connect \$60 $and$libresoc.v:183494$12118_Y + connect \$63 $or$libresoc.v:183495$12119_Y + connect \$62 $not$libresoc.v:183496$12120_Y + connect \$66 $and$libresoc.v:183497$12121_Y + connect \$68 $or$libresoc.v:183498$12122_Y + connect \$6 $and$libresoc.v:183499$12123_Y + connect \$70 $and$libresoc.v:183500$12124_Y + connect \$72 $not$libresoc.v:183501$12125_Y + connect \$74 $or$libresoc.v:183502$12126_Y + connect \$77 $not$libresoc.v:183503$12127_Y + connect \$79 $and$libresoc.v:183504$12128_Y + connect \$76 $reduce_or$libresoc.v:183505$12129_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 @@ -391227,15 +381772,15 @@ module \rotator connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end -attribute \src "libresoc.v:189478.1-189492.10" +attribute \src "libresoc.v:183673.1-183687.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl - attribute \src "libresoc.v:189490.17-189490.32" - wire width 128 $shr$libresoc.v:189490$12444_Y - attribute \src "libresoc.v:189489.17-189489.100" - wire width 8 $sub$libresoc.v:189489$12443_Y + attribute \src "libresoc.v:183685.17-183685.32" + wire width 128 $shr$libresoc.v:183685$12147_Y + attribute \src "libresoc.v:183684.17-183684.100" + wire width 8 $sub$libresoc.v:183684$12146_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" @@ -391246,8 +381791,8 @@ module \rotl wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o - attribute \src "libresoc.v:189490.17-189490.32" - cell $shr $shr$libresoc.v:189490$12444 + attribute \src "libresoc.v:183685.17-183685.32" + cell $shr $shr$libresoc.v:183685$12147 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -391255,10 +381800,10 @@ module \rotl parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 - connect \Y $shr$libresoc.v:189490$12444_Y + connect \Y $shr$libresoc.v:183685$12147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:189489$12443 + cell $sub $sub$libresoc.v:183684$12146 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -391266,43 +381811,43 @@ module \rotl parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b - connect \Y $sub$libresoc.v:189489$12443_Y + connect \Y $sub$libresoc.v:183684$12146_Y end - connect \$2 $sub$libresoc.v:189489$12443_Y - connect \$1 $shr$libresoc.v:189490$12444_Y [63:0] + connect \$2 $sub$libresoc.v:183684$12146_Y + connect \$1 $shr$libresoc.v:183685$12147_Y [63:0] connect \o \$1 end -attribute \src "libresoc.v:189496.1-189554.10" +attribute \src "libresoc.v:183691.1-183749.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l - attribute \src "libresoc.v:189497.7-189497.20" + attribute \src "libresoc.v:183692.7-183692.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189542.3-189550.6" - wire $0\q_int$next[0:0]$12455 - attribute \src "libresoc.v:189540.3-189541.27" + attribute \src "libresoc.v:183737.3-183745.6" + wire $0\q_int$next[0:0]$12158 + attribute \src "libresoc.v:183735.3-183736.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:189542.3-189550.6" - wire $1\q_int$next[0:0]$12456 - attribute \src "libresoc.v:189519.7-189519.19" + attribute \src "libresoc.v:183737.3-183745.6" + wire $1\q_int$next[0:0]$12159 + attribute \src "libresoc.v:183714.7-183714.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:189532.17-189532.96" - wire $and$libresoc.v:189532$12445_Y - attribute \src "libresoc.v:189537.17-189537.96" - wire $and$libresoc.v:189537$12450_Y - attribute \src "libresoc.v:189534.18-189534.93" - wire $not$libresoc.v:189534$12447_Y - attribute \src "libresoc.v:189536.17-189536.92" - wire $not$libresoc.v:189536$12449_Y - attribute \src "libresoc.v:189539.17-189539.92" - wire $not$libresoc.v:189539$12452_Y - attribute \src "libresoc.v:189533.18-189533.98" - wire $or$libresoc.v:189533$12446_Y - attribute \src "libresoc.v:189535.18-189535.99" - wire $or$libresoc.v:189535$12448_Y - attribute \src "libresoc.v:189538.17-189538.97" - wire $or$libresoc.v:189538$12451_Y + attribute \src "libresoc.v:183727.17-183727.96" + wire $and$libresoc.v:183727$12148_Y + attribute \src "libresoc.v:183732.17-183732.96" + wire $and$libresoc.v:183732$12153_Y + attribute \src "libresoc.v:183729.18-183729.93" + wire $not$libresoc.v:183729$12150_Y + attribute \src "libresoc.v:183731.17-183731.92" + wire $not$libresoc.v:183731$12152_Y + attribute \src "libresoc.v:183734.17-183734.92" + wire $not$libresoc.v:183734$12155_Y + attribute \src "libresoc.v:183728.18-183728.98" + wire $or$libresoc.v:183728$12149_Y + attribute \src "libresoc.v:183730.18-183730.99" + wire $or$libresoc.v:183730$12151_Y + attribute \src "libresoc.v:183733.17-183733.97" + wire $or$libresoc.v:183733$12154_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -391319,11 +381864,11 @@ module \rst_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189497.7-189497.15" + attribute \src "libresoc.v:183692.7-183692.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -391340,7 +381885,7 @@ module \rst_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:189532$12445 + cell $and $and$libresoc.v:183727$12148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391348,10 +381893,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:189532$12445_Y + connect \Y $and$libresoc.v:183727$12148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:189537$12450 + cell $and $and$libresoc.v:183732$12153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391359,34 +381904,34 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:189537$12450_Y + connect \Y $and$libresoc.v:183732$12153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:189534$12447 + cell $not $not$libresoc.v:183729$12150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:189534$12447_Y + connect \Y $not$libresoc.v:183729$12150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:189536$12449 + cell $not $not$libresoc.v:183731$12152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189536$12449_Y + connect \Y $not$libresoc.v:183731$12152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:189539$12452 + cell $not $not$libresoc.v:183734$12155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189539$12452_Y + connect \Y $not$libresoc.v:183734$12155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:189533$12446 + cell $or $or$libresoc.v:183728$12149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391394,10 +381939,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:189533$12446_Y + connect \Y $or$libresoc.v:183728$12149_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:189535$12448 + cell $or $or$libresoc.v:183730$12151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391405,10 +381950,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:189535$12448_Y + connect \Y $or$libresoc.v:183730$12151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:189538$12451 + cell $or $or$libresoc.v:183733$12154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391416,39 +381961,39 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:189538$12451_Y + connect \Y $or$libresoc.v:183733$12154_Y end - attribute \src "libresoc.v:189497.7-189497.20" - process $proc$libresoc.v:189497$12457 + attribute \src "libresoc.v:183692.7-183692.20" + process $proc$libresoc.v:183692$12160 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189519.7-189519.19" - process $proc$libresoc.v:189519$12458 + attribute \src "libresoc.v:183714.7-183714.19" + process $proc$libresoc.v:183714$12161 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:189540.3-189541.27" - process $proc$libresoc.v:189540$12453 + attribute \src "libresoc.v:183735.3-183736.27" + process $proc$libresoc.v:183735$12156 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:189542.3-189550.6" - process $proc$libresoc.v:189542$12454 + attribute \src "libresoc.v:183737.3-183745.6" + process $proc$libresoc.v:183737$12157 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12455 $1\q_int$next[0:0]$12456 - attribute \src "libresoc.v:189543.5-189543.29" + assign $0\q_int$next[0:0]$12158 $1\q_int$next[0:0]$12159 + attribute \src "libresoc.v:183738.5-183738.29" switch \initial - attribute \src "libresoc.v:189543.9-189543.17" + attribute \src "libresoc.v:183738.9-183738.17" case 1'1 case end @@ -391457,56 +382002,56 @@ module \rst_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12456 1'0 + assign $1\q_int$next[0:0]$12159 1'0 case - assign $1\q_int$next[0:0]$12456 \$5 + assign $1\q_int$next[0:0]$12159 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12455 + update \q_int$next $0\q_int$next[0:0]$12158 end - connect \$9 $and$libresoc.v:189532$12445_Y - connect \$11 $or$libresoc.v:189533$12446_Y - connect \$13 $not$libresoc.v:189534$12447_Y - connect \$15 $or$libresoc.v:189535$12448_Y - connect \$1 $not$libresoc.v:189536$12449_Y - connect \$3 $and$libresoc.v:189537$12450_Y - connect \$5 $or$libresoc.v:189538$12451_Y - connect \$7 $not$libresoc.v:189539$12452_Y + connect \$9 $and$libresoc.v:183727$12148_Y + connect \$11 $or$libresoc.v:183728$12149_Y + connect \$13 $not$libresoc.v:183729$12150_Y + connect \$15 $or$libresoc.v:183730$12151_Y + connect \$1 $not$libresoc.v:183731$12152_Y + connect \$3 $and$libresoc.v:183732$12153_Y + connect \$5 $or$libresoc.v:183733$12154_Y + connect \$7 $not$libresoc.v:183734$12155_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:189558.1-189616.10" +attribute \src "libresoc.v:183753.1-183811.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" module \rst_l$104 - attribute \src "libresoc.v:189559.7-189559.20" + attribute \src "libresoc.v:183754.7-183754.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189604.3-189612.6" - wire $0\q_int$next[0:0]$12469 - attribute \src "libresoc.v:189602.3-189603.27" + attribute \src "libresoc.v:183799.3-183807.6" + wire $0\q_int$next[0:0]$12172 + attribute \src "libresoc.v:183797.3-183798.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:189604.3-189612.6" - wire $1\q_int$next[0:0]$12470 - attribute \src "libresoc.v:189581.7-189581.19" + attribute \src "libresoc.v:183799.3-183807.6" + wire $1\q_int$next[0:0]$12173 + attribute \src "libresoc.v:183776.7-183776.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:189594.17-189594.96" - wire $and$libresoc.v:189594$12459_Y - attribute \src "libresoc.v:189599.17-189599.96" - wire $and$libresoc.v:189599$12464_Y - attribute \src "libresoc.v:189596.18-189596.93" - wire $not$libresoc.v:189596$12461_Y - attribute \src "libresoc.v:189598.17-189598.92" - wire $not$libresoc.v:189598$12463_Y - attribute \src "libresoc.v:189601.17-189601.92" - wire $not$libresoc.v:189601$12466_Y - attribute \src "libresoc.v:189595.18-189595.98" - wire $or$libresoc.v:189595$12460_Y - attribute \src "libresoc.v:189597.18-189597.99" - wire $or$libresoc.v:189597$12462_Y - attribute \src "libresoc.v:189600.17-189600.97" - wire $or$libresoc.v:189600$12465_Y + attribute \src "libresoc.v:183789.17-183789.96" + wire $and$libresoc.v:183789$12162_Y + attribute \src "libresoc.v:183794.17-183794.96" + wire $and$libresoc.v:183794$12167_Y + attribute \src "libresoc.v:183791.18-183791.93" + wire $not$libresoc.v:183791$12164_Y + attribute \src "libresoc.v:183793.17-183793.92" + wire $not$libresoc.v:183793$12166_Y + attribute \src "libresoc.v:183796.17-183796.92" + wire $not$libresoc.v:183796$12169_Y + attribute \src "libresoc.v:183790.18-183790.98" + wire $or$libresoc.v:183790$12163_Y + attribute \src "libresoc.v:183792.18-183792.99" + wire $or$libresoc.v:183792$12165_Y + attribute \src "libresoc.v:183795.17-183795.97" + wire $or$libresoc.v:183795$12168_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -391523,11 +382068,11 @@ module \rst_l$104 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189559.7-189559.15" + attribute \src "libresoc.v:183754.7-183754.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -391544,7 +382089,7 @@ module \rst_l$104 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:189594$12459 + cell $and $and$libresoc.v:183789$12162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391552,10 +382097,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:189594$12459_Y + connect \Y $and$libresoc.v:183789$12162_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:189599$12464 + cell $and $and$libresoc.v:183794$12167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391563,34 +382108,34 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:189599$12464_Y + connect \Y $and$libresoc.v:183794$12167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:189596$12461 + cell $not $not$libresoc.v:183791$12164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:189596$12461_Y + connect \Y $not$libresoc.v:183791$12164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:189598$12463 + cell $not $not$libresoc.v:183793$12166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189598$12463_Y + connect \Y $not$libresoc.v:183793$12166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:189601$12466 + cell $not $not$libresoc.v:183796$12169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189601$12466_Y + connect \Y $not$libresoc.v:183796$12169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:189595$12460 + cell $or $or$libresoc.v:183790$12163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391598,10 +382143,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:189595$12460_Y + connect \Y $or$libresoc.v:183790$12163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:189597$12462 + cell $or $or$libresoc.v:183792$12165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391609,10 +382154,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:189597$12462_Y + connect \Y $or$libresoc.v:183792$12165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:189600$12465 + cell $or $or$libresoc.v:183795$12168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391620,39 +382165,39 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:189600$12465_Y + connect \Y $or$libresoc.v:183795$12168_Y end - attribute \src "libresoc.v:189559.7-189559.20" - process $proc$libresoc.v:189559$12471 + attribute \src "libresoc.v:183754.7-183754.20" + process $proc$libresoc.v:183754$12174 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189581.7-189581.19" - process $proc$libresoc.v:189581$12472 + attribute \src "libresoc.v:183776.7-183776.19" + process $proc$libresoc.v:183776$12175 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:189602.3-189603.27" - process $proc$libresoc.v:189602$12467 + attribute \src "libresoc.v:183797.3-183798.27" + process $proc$libresoc.v:183797$12170 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:189604.3-189612.6" - process $proc$libresoc.v:189604$12468 + attribute \src "libresoc.v:183799.3-183807.6" + process $proc$libresoc.v:183799$12171 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12469 $1\q_int$next[0:0]$12470 - attribute \src "libresoc.v:189605.5-189605.29" + assign $0\q_int$next[0:0]$12172 $1\q_int$next[0:0]$12173 + attribute \src "libresoc.v:183800.5-183800.29" switch \initial - attribute \src "libresoc.v:189605.9-189605.17" + attribute \src "libresoc.v:183800.9-183800.17" case 1'1 case end @@ -391661,56 +382206,56 @@ module \rst_l$104 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12470 1'0 + assign $1\q_int$next[0:0]$12173 1'0 case - assign $1\q_int$next[0:0]$12470 \$5 + assign $1\q_int$next[0:0]$12173 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12469 + update \q_int$next $0\q_int$next[0:0]$12172 end - connect \$9 $and$libresoc.v:189594$12459_Y - connect \$11 $or$libresoc.v:189595$12460_Y - connect \$13 $not$libresoc.v:189596$12461_Y - connect \$15 $or$libresoc.v:189597$12462_Y - connect \$1 $not$libresoc.v:189598$12463_Y - connect \$3 $and$libresoc.v:189599$12464_Y - connect \$5 $or$libresoc.v:189600$12465_Y - connect \$7 $not$libresoc.v:189601$12466_Y + connect \$9 $and$libresoc.v:183789$12162_Y + connect \$11 $or$libresoc.v:183790$12163_Y + connect \$13 $not$libresoc.v:183791$12164_Y + connect \$15 $or$libresoc.v:183792$12165_Y + connect \$1 $not$libresoc.v:183793$12166_Y + connect \$3 $and$libresoc.v:183794$12167_Y + connect \$5 $or$libresoc.v:183795$12168_Y + connect \$7 $not$libresoc.v:183796$12169_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:189620.1-189678.10" +attribute \src "libresoc.v:183815.1-183873.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" module \rst_l$122 - attribute \src "libresoc.v:189621.7-189621.20" + attribute \src "libresoc.v:183816.7-183816.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189666.3-189674.6" - wire $0\q_int$next[0:0]$12483 - attribute \src "libresoc.v:189664.3-189665.27" + attribute \src "libresoc.v:183861.3-183869.6" + wire $0\q_int$next[0:0]$12186 + attribute \src "libresoc.v:183859.3-183860.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:189666.3-189674.6" - wire $1\q_int$next[0:0]$12484 - attribute \src "libresoc.v:189643.7-189643.19" + attribute \src "libresoc.v:183861.3-183869.6" + wire $1\q_int$next[0:0]$12187 + attribute \src "libresoc.v:183838.7-183838.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:189656.17-189656.96" - wire $and$libresoc.v:189656$12473_Y - attribute \src "libresoc.v:189661.17-189661.96" - wire $and$libresoc.v:189661$12478_Y - attribute \src "libresoc.v:189658.18-189658.93" - wire $not$libresoc.v:189658$12475_Y - attribute \src "libresoc.v:189660.17-189660.92" - wire $not$libresoc.v:189660$12477_Y - attribute \src "libresoc.v:189663.17-189663.92" - wire $not$libresoc.v:189663$12480_Y - attribute \src "libresoc.v:189657.18-189657.98" - wire $or$libresoc.v:189657$12474_Y - attribute \src "libresoc.v:189659.18-189659.99" - wire $or$libresoc.v:189659$12476_Y - attribute \src "libresoc.v:189662.17-189662.97" - wire $or$libresoc.v:189662$12479_Y + attribute \src "libresoc.v:183851.17-183851.96" + wire $and$libresoc.v:183851$12176_Y + attribute \src "libresoc.v:183856.17-183856.96" + wire $and$libresoc.v:183856$12181_Y + attribute \src "libresoc.v:183853.18-183853.93" + wire $not$libresoc.v:183853$12178_Y + attribute \src "libresoc.v:183855.17-183855.92" + wire $not$libresoc.v:183855$12180_Y + attribute \src "libresoc.v:183858.17-183858.92" + wire $not$libresoc.v:183858$12183_Y + attribute \src "libresoc.v:183852.18-183852.98" + wire $or$libresoc.v:183852$12177_Y + attribute \src "libresoc.v:183854.18-183854.99" + wire $or$libresoc.v:183854$12179_Y + attribute \src "libresoc.v:183857.17-183857.97" + wire $or$libresoc.v:183857$12182_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -391727,11 +382272,11 @@ module \rst_l$122 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189621.7-189621.15" + attribute \src "libresoc.v:183816.7-183816.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -391748,7 +382293,7 @@ module \rst_l$122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:189656$12473 + cell $and $and$libresoc.v:183851$12176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391756,10 +382301,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:189656$12473_Y + connect \Y $and$libresoc.v:183851$12176_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:189661$12478 + cell $and $and$libresoc.v:183856$12181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391767,34 +382312,34 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:189661$12478_Y + connect \Y $and$libresoc.v:183856$12181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:189658$12475 + cell $not $not$libresoc.v:183853$12178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:189658$12475_Y + connect \Y $not$libresoc.v:183853$12178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:189660$12477 + cell $not $not$libresoc.v:183855$12180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189660$12477_Y + connect \Y $not$libresoc.v:183855$12180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:189663$12480 + cell $not $not$libresoc.v:183858$12183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189663$12480_Y + connect \Y $not$libresoc.v:183858$12183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:189657$12474 + cell $or $or$libresoc.v:183852$12177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391802,10 +382347,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:189657$12474_Y + connect \Y $or$libresoc.v:183852$12177_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:189659$12476 + cell $or $or$libresoc.v:183854$12179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391813,10 +382358,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:189659$12476_Y + connect \Y $or$libresoc.v:183854$12179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:189662$12479 + cell $or $or$libresoc.v:183857$12182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391824,39 +382369,39 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:189662$12479_Y + connect \Y $or$libresoc.v:183857$12182_Y end - attribute \src "libresoc.v:189621.7-189621.20" - process $proc$libresoc.v:189621$12485 + attribute \src "libresoc.v:183816.7-183816.20" + process $proc$libresoc.v:183816$12188 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189643.7-189643.19" - process $proc$libresoc.v:189643$12486 + attribute \src "libresoc.v:183838.7-183838.19" + process $proc$libresoc.v:183838$12189 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:189664.3-189665.27" - process $proc$libresoc.v:189664$12481 + attribute \src "libresoc.v:183859.3-183860.27" + process $proc$libresoc.v:183859$12184 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:189666.3-189674.6" - process $proc$libresoc.v:189666$12482 + attribute \src "libresoc.v:183861.3-183869.6" + process $proc$libresoc.v:183861$12185 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12483 $1\q_int$next[0:0]$12484 - attribute \src "libresoc.v:189667.5-189667.29" + assign $0\q_int$next[0:0]$12186 $1\q_int$next[0:0]$12187 + attribute \src "libresoc.v:183862.5-183862.29" switch \initial - attribute \src "libresoc.v:189667.9-189667.17" + attribute \src "libresoc.v:183862.9-183862.17" case 1'1 case end @@ -391865,56 +382410,56 @@ module \rst_l$122 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12484 1'0 + assign $1\q_int$next[0:0]$12187 1'0 case - assign $1\q_int$next[0:0]$12484 \$5 + assign $1\q_int$next[0:0]$12187 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12483 + update \q_int$next $0\q_int$next[0:0]$12186 end - connect \$9 $and$libresoc.v:189656$12473_Y - connect \$11 $or$libresoc.v:189657$12474_Y - connect \$13 $not$libresoc.v:189658$12475_Y - connect \$15 $or$libresoc.v:189659$12476_Y - connect \$1 $not$libresoc.v:189660$12477_Y - connect \$3 $and$libresoc.v:189661$12478_Y - connect \$5 $or$libresoc.v:189662$12479_Y - connect \$7 $not$libresoc.v:189663$12480_Y + connect \$9 $and$libresoc.v:183851$12176_Y + connect \$11 $or$libresoc.v:183852$12177_Y + connect \$13 $not$libresoc.v:183853$12178_Y + connect \$15 $or$libresoc.v:183854$12179_Y + connect \$1 $not$libresoc.v:183855$12180_Y + connect \$3 $and$libresoc.v:183856$12181_Y + connect \$5 $or$libresoc.v:183857$12182_Y + connect \$7 $not$libresoc.v:183858$12183_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:189682.1-189740.10" +attribute \src "libresoc.v:183877.1-183935.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" module \rst_l$129 - attribute \src "libresoc.v:189683.7-189683.20" + attribute \src "libresoc.v:183878.7-183878.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189728.3-189736.6" - wire $0\q_int$next[0:0]$12497 - attribute \src "libresoc.v:189726.3-189727.27" + attribute \src "libresoc.v:183923.3-183931.6" + wire $0\q_int$next[0:0]$12200 + attribute \src "libresoc.v:183921.3-183922.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:189728.3-189736.6" - wire $1\q_int$next[0:0]$12498 - attribute \src "libresoc.v:189705.7-189705.19" + attribute \src "libresoc.v:183923.3-183931.6" + wire $1\q_int$next[0:0]$12201 + attribute \src "libresoc.v:183900.7-183900.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:189718.17-189718.96" - wire $and$libresoc.v:189718$12487_Y - attribute \src "libresoc.v:189723.17-189723.96" - wire $and$libresoc.v:189723$12492_Y - attribute \src "libresoc.v:189720.18-189720.93" - wire $not$libresoc.v:189720$12489_Y - attribute \src "libresoc.v:189722.17-189722.92" - wire $not$libresoc.v:189722$12491_Y - attribute \src "libresoc.v:189725.17-189725.92" - wire $not$libresoc.v:189725$12494_Y - attribute \src "libresoc.v:189719.18-189719.98" - wire $or$libresoc.v:189719$12488_Y - attribute \src "libresoc.v:189721.18-189721.99" - wire $or$libresoc.v:189721$12490_Y - attribute \src "libresoc.v:189724.17-189724.97" - wire $or$libresoc.v:189724$12493_Y + attribute \src "libresoc.v:183913.17-183913.96" + wire $and$libresoc.v:183913$12190_Y + attribute \src "libresoc.v:183918.17-183918.96" + wire $and$libresoc.v:183918$12195_Y + attribute \src "libresoc.v:183915.18-183915.93" + wire $not$libresoc.v:183915$12192_Y + attribute \src "libresoc.v:183917.17-183917.92" + wire $not$libresoc.v:183917$12194_Y + attribute \src "libresoc.v:183920.17-183920.92" + wire $not$libresoc.v:183920$12197_Y + attribute \src "libresoc.v:183914.18-183914.98" + wire $or$libresoc.v:183914$12191_Y + attribute \src "libresoc.v:183916.18-183916.99" + wire $or$libresoc.v:183916$12193_Y + attribute \src "libresoc.v:183919.17-183919.97" + wire $or$libresoc.v:183919$12196_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -391931,11 +382476,11 @@ module \rst_l$129 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189683.7-189683.15" + attribute \src "libresoc.v:183878.7-183878.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -391952,7 +382497,7 @@ module \rst_l$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:189718$12487 + cell $and $and$libresoc.v:183913$12190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391960,10 +382505,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:189718$12487_Y + connect \Y $and$libresoc.v:183913$12190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:189723$12492 + cell $and $and$libresoc.v:183918$12195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391971,34 +382516,34 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:189723$12492_Y + connect \Y $and$libresoc.v:183918$12195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:189720$12489 + cell $not $not$libresoc.v:183915$12192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:189720$12489_Y + connect \Y $not$libresoc.v:183915$12192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:189722$12491 + cell $not $not$libresoc.v:183917$12194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189722$12491_Y + connect \Y $not$libresoc.v:183917$12194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:189725$12494 + cell $not $not$libresoc.v:183920$12197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189725$12494_Y + connect \Y $not$libresoc.v:183920$12197_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:189719$12488 + cell $or $or$libresoc.v:183914$12191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392006,10 +382551,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:189719$12488_Y + connect \Y $or$libresoc.v:183914$12191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:189721$12490 + cell $or $or$libresoc.v:183916$12193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392017,10 +382562,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:189721$12490_Y + connect \Y $or$libresoc.v:183916$12193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:189724$12493 + cell $or $or$libresoc.v:183919$12196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392028,39 +382573,39 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:189724$12493_Y + connect \Y $or$libresoc.v:183919$12196_Y end - attribute \src "libresoc.v:189683.7-189683.20" - process $proc$libresoc.v:189683$12499 + attribute \src "libresoc.v:183878.7-183878.20" + process $proc$libresoc.v:183878$12202 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189705.7-189705.19" - process $proc$libresoc.v:189705$12500 + attribute \src "libresoc.v:183900.7-183900.19" + process $proc$libresoc.v:183900$12203 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:189726.3-189727.27" - process $proc$libresoc.v:189726$12495 + attribute \src "libresoc.v:183921.3-183922.27" + process $proc$libresoc.v:183921$12198 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:189728.3-189736.6" - process $proc$libresoc.v:189728$12496 + attribute \src "libresoc.v:183923.3-183931.6" + process $proc$libresoc.v:183923$12199 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12497 $1\q_int$next[0:0]$12498 - attribute \src "libresoc.v:189729.5-189729.29" + assign $0\q_int$next[0:0]$12200 $1\q_int$next[0:0]$12201 + attribute \src "libresoc.v:183924.5-183924.29" switch \initial - attribute \src "libresoc.v:189729.9-189729.17" + attribute \src "libresoc.v:183924.9-183924.17" case 1'1 case end @@ -392069,56 +382614,56 @@ module \rst_l$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12498 1'0 + assign $1\q_int$next[0:0]$12201 1'0 case - assign $1\q_int$next[0:0]$12498 \$5 + assign $1\q_int$next[0:0]$12201 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12497 + update \q_int$next $0\q_int$next[0:0]$12200 end - connect \$9 $and$libresoc.v:189718$12487_Y - connect \$11 $or$libresoc.v:189719$12488_Y - connect \$13 $not$libresoc.v:189720$12489_Y - connect \$15 $or$libresoc.v:189721$12490_Y - connect \$1 $not$libresoc.v:189722$12491_Y - connect \$3 $and$libresoc.v:189723$12492_Y - connect \$5 $or$libresoc.v:189724$12493_Y - connect \$7 $not$libresoc.v:189725$12494_Y + connect \$9 $and$libresoc.v:183913$12190_Y + connect \$11 $or$libresoc.v:183914$12191_Y + connect \$13 $not$libresoc.v:183915$12192_Y + connect \$15 $or$libresoc.v:183916$12193_Y + connect \$1 $not$libresoc.v:183917$12194_Y + connect \$3 $and$libresoc.v:183918$12195_Y + connect \$5 $or$libresoc.v:183919$12196_Y + connect \$7 $not$libresoc.v:183920$12197_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:189744.1-189802.10" +attribute \src "libresoc.v:183939.1-183997.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 - attribute \src "libresoc.v:189745.7-189745.20" + attribute \src "libresoc.v:183940.7-183940.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189790.3-189798.6" - wire $0\q_int$next[0:0]$12511 - attribute \src "libresoc.v:189788.3-189789.27" + attribute \src "libresoc.v:183985.3-183993.6" + wire $0\q_int$next[0:0]$12214 + attribute \src "libresoc.v:183983.3-183984.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:189790.3-189798.6" - wire $1\q_int$next[0:0]$12512 - attribute \src "libresoc.v:189767.7-189767.19" + attribute \src "libresoc.v:183985.3-183993.6" + wire $1\q_int$next[0:0]$12215 + attribute \src "libresoc.v:183962.7-183962.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:189780.17-189780.96" - wire $and$libresoc.v:189780$12501_Y - attribute \src "libresoc.v:189785.17-189785.96" - wire $and$libresoc.v:189785$12506_Y - attribute \src "libresoc.v:189782.18-189782.93" - wire $not$libresoc.v:189782$12503_Y - attribute \src "libresoc.v:189784.17-189784.92" - wire $not$libresoc.v:189784$12505_Y - attribute \src "libresoc.v:189787.17-189787.92" - wire $not$libresoc.v:189787$12508_Y - attribute \src "libresoc.v:189781.18-189781.98" - wire $or$libresoc.v:189781$12502_Y - attribute \src "libresoc.v:189783.18-189783.99" - wire $or$libresoc.v:189783$12504_Y - attribute \src "libresoc.v:189786.17-189786.97" - wire $or$libresoc.v:189786$12507_Y + attribute \src "libresoc.v:183975.17-183975.96" + wire $and$libresoc.v:183975$12204_Y + attribute \src "libresoc.v:183980.17-183980.96" + wire $and$libresoc.v:183980$12209_Y + attribute \src "libresoc.v:183977.18-183977.93" + wire $not$libresoc.v:183977$12206_Y + attribute \src "libresoc.v:183979.17-183979.92" + wire $not$libresoc.v:183979$12208_Y + attribute \src "libresoc.v:183982.17-183982.92" + wire $not$libresoc.v:183982$12211_Y + attribute \src "libresoc.v:183976.18-183976.98" + wire $or$libresoc.v:183976$12205_Y + attribute \src "libresoc.v:183978.18-183978.99" + wire $or$libresoc.v:183978$12207_Y + attribute \src "libresoc.v:183981.17-183981.97" + wire $or$libresoc.v:183981$12210_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -392135,11 +382680,11 @@ module \rst_l$13 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189745.7-189745.15" + attribute \src "libresoc.v:183940.7-183940.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -392156,7 +382701,7 @@ module \rst_l$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:189780$12501 + cell $and $and$libresoc.v:183975$12204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392164,10 +382709,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:189780$12501_Y + connect \Y $and$libresoc.v:183975$12204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:189785$12506 + cell $and $and$libresoc.v:183980$12209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392175,34 +382720,34 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:189785$12506_Y + connect \Y $and$libresoc.v:183980$12209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:189782$12503 + cell $not $not$libresoc.v:183977$12206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:189782$12503_Y + connect \Y $not$libresoc.v:183977$12206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:189784$12505 + cell $not $not$libresoc.v:183979$12208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189784$12505_Y + connect \Y $not$libresoc.v:183979$12208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:189787$12508 + cell $not $not$libresoc.v:183982$12211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189787$12508_Y + connect \Y $not$libresoc.v:183982$12211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:189781$12502 + cell $or $or$libresoc.v:183976$12205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392210,10 +382755,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:189781$12502_Y + connect \Y $or$libresoc.v:183976$12205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:189783$12504 + cell $or $or$libresoc.v:183978$12207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392221,10 +382766,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:189783$12504_Y + connect \Y $or$libresoc.v:183978$12207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:189786$12507 + cell $or $or$libresoc.v:183981$12210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392232,39 +382777,39 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:189786$12507_Y + connect \Y $or$libresoc.v:183981$12210_Y end - attribute \src "libresoc.v:189745.7-189745.20" - process $proc$libresoc.v:189745$12513 + attribute \src "libresoc.v:183940.7-183940.20" + process $proc$libresoc.v:183940$12216 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189767.7-189767.19" - process $proc$libresoc.v:189767$12514 + attribute \src "libresoc.v:183962.7-183962.19" + process $proc$libresoc.v:183962$12217 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:189788.3-189789.27" - process $proc$libresoc.v:189788$12509 + attribute \src "libresoc.v:183983.3-183984.27" + process $proc$libresoc.v:183983$12212 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:189790.3-189798.6" - process $proc$libresoc.v:189790$12510 + attribute \src "libresoc.v:183985.3-183993.6" + process $proc$libresoc.v:183985$12213 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12511 $1\q_int$next[0:0]$12512 - attribute \src "libresoc.v:189791.5-189791.29" + assign $0\q_int$next[0:0]$12214 $1\q_int$next[0:0]$12215 + attribute \src "libresoc.v:183986.5-183986.29" switch \initial - attribute \src "libresoc.v:189791.9-189791.17" + attribute \src "libresoc.v:183986.9-183986.17" case 1'1 case end @@ -392273,56 +382818,56 @@ module \rst_l$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12512 1'0 + assign $1\q_int$next[0:0]$12215 1'0 case - assign $1\q_int$next[0:0]$12512 \$5 + assign $1\q_int$next[0:0]$12215 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12511 + update \q_int$next $0\q_int$next[0:0]$12214 end - connect \$9 $and$libresoc.v:189780$12501_Y - connect \$11 $or$libresoc.v:189781$12502_Y - connect \$13 $not$libresoc.v:189782$12503_Y - connect \$15 $or$libresoc.v:189783$12504_Y - connect \$1 $not$libresoc.v:189784$12505_Y - connect \$3 $and$libresoc.v:189785$12506_Y - connect \$5 $or$libresoc.v:189786$12507_Y - connect \$7 $not$libresoc.v:189787$12508_Y + connect \$9 $and$libresoc.v:183975$12204_Y + connect \$11 $or$libresoc.v:183976$12205_Y + connect \$13 $not$libresoc.v:183977$12206_Y + connect \$15 $or$libresoc.v:183978$12207_Y + connect \$1 $not$libresoc.v:183979$12208_Y + connect \$3 $and$libresoc.v:183980$12209_Y + connect \$5 $or$libresoc.v:183981$12210_Y + connect \$7 $not$libresoc.v:183982$12211_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:189806.1-189864.10" +attribute \src "libresoc.v:184001.1-184059.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 - attribute \src "libresoc.v:189807.7-189807.20" + attribute \src "libresoc.v:184002.7-184002.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189852.3-189860.6" - wire $0\q_int$next[0:0]$12525 - attribute \src "libresoc.v:189850.3-189851.27" + attribute \src "libresoc.v:184047.3-184055.6" + wire $0\q_int$next[0:0]$12228 + attribute \src "libresoc.v:184045.3-184046.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:189852.3-189860.6" - wire $1\q_int$next[0:0]$12526 - attribute \src "libresoc.v:189829.7-189829.19" + attribute \src "libresoc.v:184047.3-184055.6" + wire $1\q_int$next[0:0]$12229 + attribute \src "libresoc.v:184024.7-184024.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:189842.17-189842.96" - wire $and$libresoc.v:189842$12515_Y - attribute \src "libresoc.v:189847.17-189847.96" - wire $and$libresoc.v:189847$12520_Y - attribute \src "libresoc.v:189844.18-189844.93" - wire $not$libresoc.v:189844$12517_Y - attribute \src "libresoc.v:189846.17-189846.92" - wire $not$libresoc.v:189846$12519_Y - attribute \src "libresoc.v:189849.17-189849.92" - wire $not$libresoc.v:189849$12522_Y - attribute \src "libresoc.v:189843.18-189843.98" - wire $or$libresoc.v:189843$12516_Y - attribute \src "libresoc.v:189845.18-189845.99" - wire $or$libresoc.v:189845$12518_Y - attribute \src "libresoc.v:189848.17-189848.97" - wire $or$libresoc.v:189848$12521_Y + attribute \src "libresoc.v:184037.17-184037.96" + wire $and$libresoc.v:184037$12218_Y + attribute \src "libresoc.v:184042.17-184042.96" + wire $and$libresoc.v:184042$12223_Y + attribute \src "libresoc.v:184039.18-184039.93" + wire $not$libresoc.v:184039$12220_Y + attribute \src "libresoc.v:184041.17-184041.92" + wire $not$libresoc.v:184041$12222_Y + attribute \src "libresoc.v:184044.17-184044.92" + wire $not$libresoc.v:184044$12225_Y + attribute \src "libresoc.v:184038.18-184038.98" + wire $or$libresoc.v:184038$12219_Y + attribute \src "libresoc.v:184040.18-184040.99" + wire $or$libresoc.v:184040$12221_Y + attribute \src "libresoc.v:184043.17-184043.97" + wire $or$libresoc.v:184043$12224_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -392339,11 +382884,11 @@ module \rst_l$26 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189807.7-189807.15" + attribute \src "libresoc.v:184002.7-184002.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -392360,7 +382905,7 @@ module \rst_l$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:189842$12515 + cell $and $and$libresoc.v:184037$12218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392368,10 +382913,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:189842$12515_Y + connect \Y $and$libresoc.v:184037$12218_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:189847$12520 + cell $and $and$libresoc.v:184042$12223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392379,34 +382924,34 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:189847$12520_Y + connect \Y $and$libresoc.v:184042$12223_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:189844$12517 + cell $not $not$libresoc.v:184039$12220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:189844$12517_Y + connect \Y $not$libresoc.v:184039$12220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:189846$12519 + cell $not $not$libresoc.v:184041$12222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189846$12519_Y + connect \Y $not$libresoc.v:184041$12222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:189849$12522 + cell $not $not$libresoc.v:184044$12225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189849$12522_Y + connect \Y $not$libresoc.v:184044$12225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:189843$12516 + cell $or $or$libresoc.v:184038$12219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392414,10 +382959,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:189843$12516_Y + connect \Y $or$libresoc.v:184038$12219_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:189845$12518 + cell $or $or$libresoc.v:184040$12221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392425,10 +382970,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:189845$12518_Y + connect \Y $or$libresoc.v:184040$12221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:189848$12521 + cell $or $or$libresoc.v:184043$12224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392436,39 +382981,39 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:189848$12521_Y + connect \Y $or$libresoc.v:184043$12224_Y end - attribute \src "libresoc.v:189807.7-189807.20" - process $proc$libresoc.v:189807$12527 + attribute \src "libresoc.v:184002.7-184002.20" + process $proc$libresoc.v:184002$12230 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189829.7-189829.19" - process $proc$libresoc.v:189829$12528 + attribute \src "libresoc.v:184024.7-184024.19" + process $proc$libresoc.v:184024$12231 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:189850.3-189851.27" - process $proc$libresoc.v:189850$12523 + attribute \src "libresoc.v:184045.3-184046.27" + process $proc$libresoc.v:184045$12226 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:189852.3-189860.6" - process $proc$libresoc.v:189852$12524 + attribute \src "libresoc.v:184047.3-184055.6" + process $proc$libresoc.v:184047$12227 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12525 $1\q_int$next[0:0]$12526 - attribute \src "libresoc.v:189853.5-189853.29" + assign $0\q_int$next[0:0]$12228 $1\q_int$next[0:0]$12229 + attribute \src "libresoc.v:184048.5-184048.29" switch \initial - attribute \src "libresoc.v:189853.9-189853.17" + attribute \src "libresoc.v:184048.9-184048.17" case 1'1 case end @@ -392477,56 +383022,56 @@ module \rst_l$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12526 1'0 + assign $1\q_int$next[0:0]$12229 1'0 case - assign $1\q_int$next[0:0]$12526 \$5 + assign $1\q_int$next[0:0]$12229 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12525 + update \q_int$next $0\q_int$next[0:0]$12228 end - connect \$9 $and$libresoc.v:189842$12515_Y - connect \$11 $or$libresoc.v:189843$12516_Y - connect \$13 $not$libresoc.v:189844$12517_Y - connect \$15 $or$libresoc.v:189845$12518_Y - connect \$1 $not$libresoc.v:189846$12519_Y - connect \$3 $and$libresoc.v:189847$12520_Y - connect \$5 $or$libresoc.v:189848$12521_Y - connect \$7 $not$libresoc.v:189849$12522_Y + connect \$9 $and$libresoc.v:184037$12218_Y + connect \$11 $or$libresoc.v:184038$12219_Y + connect \$13 $not$libresoc.v:184039$12220_Y + connect \$15 $or$libresoc.v:184040$12221_Y + connect \$1 $not$libresoc.v:184041$12222_Y + connect \$3 $and$libresoc.v:184042$12223_Y + connect \$5 $or$libresoc.v:184043$12224_Y + connect \$7 $not$libresoc.v:184044$12225_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:189868.1-189926.10" +attribute \src "libresoc.v:184063.1-184121.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" module \rst_l$42 - attribute \src "libresoc.v:189869.7-189869.20" + attribute \src "libresoc.v:184064.7-184064.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189914.3-189922.6" - wire $0\q_int$next[0:0]$12539 - attribute \src "libresoc.v:189912.3-189913.27" + attribute \src "libresoc.v:184109.3-184117.6" + wire $0\q_int$next[0:0]$12242 + attribute \src "libresoc.v:184107.3-184108.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:189914.3-189922.6" - wire $1\q_int$next[0:0]$12540 - attribute \src "libresoc.v:189891.7-189891.19" + attribute \src "libresoc.v:184109.3-184117.6" + wire $1\q_int$next[0:0]$12243 + attribute \src "libresoc.v:184086.7-184086.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:189904.17-189904.96" - wire $and$libresoc.v:189904$12529_Y - attribute \src "libresoc.v:189909.17-189909.96" - wire $and$libresoc.v:189909$12534_Y - attribute \src "libresoc.v:189906.18-189906.93" - wire $not$libresoc.v:189906$12531_Y - attribute \src "libresoc.v:189908.17-189908.92" - wire $not$libresoc.v:189908$12533_Y - attribute \src "libresoc.v:189911.17-189911.92" - wire $not$libresoc.v:189911$12536_Y - attribute \src "libresoc.v:189905.18-189905.98" - wire $or$libresoc.v:189905$12530_Y - attribute \src "libresoc.v:189907.18-189907.99" - wire $or$libresoc.v:189907$12532_Y - attribute \src "libresoc.v:189910.17-189910.97" - wire $or$libresoc.v:189910$12535_Y + attribute \src "libresoc.v:184099.17-184099.96" + wire $and$libresoc.v:184099$12232_Y + attribute \src "libresoc.v:184104.17-184104.96" + wire $and$libresoc.v:184104$12237_Y + attribute \src "libresoc.v:184101.18-184101.93" + wire $not$libresoc.v:184101$12234_Y + attribute \src "libresoc.v:184103.17-184103.92" + wire $not$libresoc.v:184103$12236_Y + attribute \src "libresoc.v:184106.17-184106.92" + wire $not$libresoc.v:184106$12239_Y + attribute \src "libresoc.v:184100.18-184100.98" + wire $or$libresoc.v:184100$12233_Y + attribute \src "libresoc.v:184102.18-184102.99" + wire $or$libresoc.v:184102$12235_Y + attribute \src "libresoc.v:184105.17-184105.97" + wire $or$libresoc.v:184105$12238_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -392543,11 +383088,11 @@ module \rst_l$42 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189869.7-189869.15" + attribute \src "libresoc.v:184064.7-184064.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -392564,7 +383109,7 @@ module \rst_l$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:189904$12529 + cell $and $and$libresoc.v:184099$12232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392572,10 +383117,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:189904$12529_Y + connect \Y $and$libresoc.v:184099$12232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:189909$12534 + cell $and $and$libresoc.v:184104$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392583,34 +383128,34 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:189909$12534_Y + connect \Y $and$libresoc.v:184104$12237_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:189906$12531 + cell $not $not$libresoc.v:184101$12234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:189906$12531_Y + connect \Y $not$libresoc.v:184101$12234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:189908$12533 + cell $not $not$libresoc.v:184103$12236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189908$12533_Y + connect \Y $not$libresoc.v:184103$12236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:189911$12536 + cell $not $not$libresoc.v:184106$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189911$12536_Y + connect \Y $not$libresoc.v:184106$12239_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:189905$12530 + cell $or $or$libresoc.v:184100$12233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392618,10 +383163,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:189905$12530_Y + connect \Y $or$libresoc.v:184100$12233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:189907$12532 + cell $or $or$libresoc.v:184102$12235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392629,10 +383174,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:189907$12532_Y + connect \Y $or$libresoc.v:184102$12235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:189910$12535 + cell $or $or$libresoc.v:184105$12238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392640,39 +383185,39 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:189910$12535_Y + connect \Y $or$libresoc.v:184105$12238_Y end - attribute \src "libresoc.v:189869.7-189869.20" - process $proc$libresoc.v:189869$12541 + attribute \src "libresoc.v:184064.7-184064.20" + process $proc$libresoc.v:184064$12244 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189891.7-189891.19" - process $proc$libresoc.v:189891$12542 + attribute \src "libresoc.v:184086.7-184086.19" + process $proc$libresoc.v:184086$12245 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:189912.3-189913.27" - process $proc$libresoc.v:189912$12537 + attribute \src "libresoc.v:184107.3-184108.27" + process $proc$libresoc.v:184107$12240 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:189914.3-189922.6" - process $proc$libresoc.v:189914$12538 + attribute \src "libresoc.v:184109.3-184117.6" + process $proc$libresoc.v:184109$12241 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12539 $1\q_int$next[0:0]$12540 - attribute \src "libresoc.v:189915.5-189915.29" + assign $0\q_int$next[0:0]$12242 $1\q_int$next[0:0]$12243 + attribute \src "libresoc.v:184110.5-184110.29" switch \initial - attribute \src "libresoc.v:189915.9-189915.17" + attribute \src "libresoc.v:184110.9-184110.17" case 1'1 case end @@ -392681,56 +383226,56 @@ module \rst_l$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12540 1'0 + assign $1\q_int$next[0:0]$12243 1'0 case - assign $1\q_int$next[0:0]$12540 \$5 + assign $1\q_int$next[0:0]$12243 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12539 + update \q_int$next $0\q_int$next[0:0]$12242 end - connect \$9 $and$libresoc.v:189904$12529_Y - connect \$11 $or$libresoc.v:189905$12530_Y - connect \$13 $not$libresoc.v:189906$12531_Y - connect \$15 $or$libresoc.v:189907$12532_Y - connect \$1 $not$libresoc.v:189908$12533_Y - connect \$3 $and$libresoc.v:189909$12534_Y - connect \$5 $or$libresoc.v:189910$12535_Y - connect \$7 $not$libresoc.v:189911$12536_Y + connect \$9 $and$libresoc.v:184099$12232_Y + connect \$11 $or$libresoc.v:184100$12233_Y + connect \$13 $not$libresoc.v:184101$12234_Y + connect \$15 $or$libresoc.v:184102$12235_Y + connect \$1 $not$libresoc.v:184103$12236_Y + connect \$3 $and$libresoc.v:184104$12237_Y + connect \$5 $or$libresoc.v:184105$12238_Y + connect \$7 $not$libresoc.v:184106$12239_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:189930.1-189988.10" +attribute \src "libresoc.v:184125.1-184183.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" module \rst_l$58 - attribute \src "libresoc.v:189931.7-189931.20" + attribute \src "libresoc.v:184126.7-184126.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189976.3-189984.6" - wire $0\q_int$next[0:0]$12553 - attribute \src "libresoc.v:189974.3-189975.27" + attribute \src "libresoc.v:184171.3-184179.6" + wire $0\q_int$next[0:0]$12256 + attribute \src "libresoc.v:184169.3-184170.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:189976.3-189984.6" - wire $1\q_int$next[0:0]$12554 - attribute \src "libresoc.v:189953.7-189953.19" + attribute \src "libresoc.v:184171.3-184179.6" + wire $1\q_int$next[0:0]$12257 + attribute \src "libresoc.v:184148.7-184148.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:189966.17-189966.96" - wire $and$libresoc.v:189966$12543_Y - attribute \src "libresoc.v:189971.17-189971.96" - wire $and$libresoc.v:189971$12548_Y - attribute \src "libresoc.v:189968.18-189968.93" - wire $not$libresoc.v:189968$12545_Y - attribute \src "libresoc.v:189970.17-189970.92" - wire $not$libresoc.v:189970$12547_Y - attribute \src "libresoc.v:189973.17-189973.92" - wire $not$libresoc.v:189973$12550_Y - attribute \src "libresoc.v:189967.18-189967.98" - wire $or$libresoc.v:189967$12544_Y - attribute \src "libresoc.v:189969.18-189969.99" - wire $or$libresoc.v:189969$12546_Y - attribute \src "libresoc.v:189972.17-189972.97" - wire $or$libresoc.v:189972$12549_Y + attribute \src "libresoc.v:184161.17-184161.96" + wire $and$libresoc.v:184161$12246_Y + attribute \src "libresoc.v:184166.17-184166.96" + wire $and$libresoc.v:184166$12251_Y + attribute \src "libresoc.v:184163.18-184163.93" + wire $not$libresoc.v:184163$12248_Y + attribute \src "libresoc.v:184165.17-184165.92" + wire $not$libresoc.v:184165$12250_Y + attribute \src "libresoc.v:184168.17-184168.92" + wire $not$libresoc.v:184168$12253_Y + attribute \src "libresoc.v:184162.18-184162.98" + wire $or$libresoc.v:184162$12247_Y + attribute \src "libresoc.v:184164.18-184164.99" + wire $or$libresoc.v:184164$12249_Y + attribute \src "libresoc.v:184167.17-184167.97" + wire $or$libresoc.v:184167$12252_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -392747,11 +383292,11 @@ module \rst_l$58 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189931.7-189931.15" + attribute \src "libresoc.v:184126.7-184126.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -392768,7 +383313,7 @@ module \rst_l$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:189966$12543 + cell $and $and$libresoc.v:184161$12246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392776,10 +383321,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:189966$12543_Y + connect \Y $and$libresoc.v:184161$12246_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:189971$12548 + cell $and $and$libresoc.v:184166$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392787,34 +383332,34 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:189971$12548_Y + connect \Y $and$libresoc.v:184166$12251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:189968$12545 + cell $not $not$libresoc.v:184163$12248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:189968$12545_Y + connect \Y $not$libresoc.v:184163$12248_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:189970$12547 + cell $not $not$libresoc.v:184165$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189970$12547_Y + connect \Y $not$libresoc.v:184165$12250_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:189973$12550 + cell $not $not$libresoc.v:184168$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:189973$12550_Y + connect \Y $not$libresoc.v:184168$12253_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:189967$12544 + cell $or $or$libresoc.v:184162$12247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392822,10 +383367,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:189967$12544_Y + connect \Y $or$libresoc.v:184162$12247_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:189969$12546 + cell $or $or$libresoc.v:184164$12249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392833,10 +383378,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:189969$12546_Y + connect \Y $or$libresoc.v:184164$12249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:189972$12549 + cell $or $or$libresoc.v:184167$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392844,39 +383389,39 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:189972$12549_Y + connect \Y $or$libresoc.v:184167$12252_Y end - attribute \src "libresoc.v:189931.7-189931.20" - process $proc$libresoc.v:189931$12555 + attribute \src "libresoc.v:184126.7-184126.20" + process $proc$libresoc.v:184126$12258 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189953.7-189953.19" - process $proc$libresoc.v:189953$12556 + attribute \src "libresoc.v:184148.7-184148.19" + process $proc$libresoc.v:184148$12259 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:189974.3-189975.27" - process $proc$libresoc.v:189974$12551 + attribute \src "libresoc.v:184169.3-184170.27" + process $proc$libresoc.v:184169$12254 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:189976.3-189984.6" - process $proc$libresoc.v:189976$12552 + attribute \src "libresoc.v:184171.3-184179.6" + process $proc$libresoc.v:184171$12255 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12553 $1\q_int$next[0:0]$12554 - attribute \src "libresoc.v:189977.5-189977.29" + assign $0\q_int$next[0:0]$12256 $1\q_int$next[0:0]$12257 + attribute \src "libresoc.v:184172.5-184172.29" switch \initial - attribute \src "libresoc.v:189977.9-189977.17" + attribute \src "libresoc.v:184172.9-184172.17" case 1'1 case end @@ -392885,56 +383430,56 @@ module \rst_l$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12554 1'0 + assign $1\q_int$next[0:0]$12257 1'0 case - assign $1\q_int$next[0:0]$12554 \$5 + assign $1\q_int$next[0:0]$12257 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12553 + update \q_int$next $0\q_int$next[0:0]$12256 end - connect \$9 $and$libresoc.v:189966$12543_Y - connect \$11 $or$libresoc.v:189967$12544_Y - connect \$13 $not$libresoc.v:189968$12545_Y - connect \$15 $or$libresoc.v:189969$12546_Y - connect \$1 $not$libresoc.v:189970$12547_Y - connect \$3 $and$libresoc.v:189971$12548_Y - connect \$5 $or$libresoc.v:189972$12549_Y - connect \$7 $not$libresoc.v:189973$12550_Y + connect \$9 $and$libresoc.v:184161$12246_Y + connect \$11 $or$libresoc.v:184162$12247_Y + connect \$13 $not$libresoc.v:184163$12248_Y + connect \$15 $or$libresoc.v:184164$12249_Y + connect \$1 $not$libresoc.v:184165$12250_Y + connect \$3 $and$libresoc.v:184166$12251_Y + connect \$5 $or$libresoc.v:184167$12252_Y + connect \$7 $not$libresoc.v:184168$12253_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:189992.1-190050.10" +attribute \src "libresoc.v:184187.1-184245.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" module \rst_l$70 - attribute \src "libresoc.v:189993.7-189993.20" + attribute \src "libresoc.v:184188.7-184188.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190038.3-190046.6" - wire $0\q_int$next[0:0]$12567 - attribute \src "libresoc.v:190036.3-190037.27" + attribute \src "libresoc.v:184233.3-184241.6" + wire $0\q_int$next[0:0]$12270 + attribute \src "libresoc.v:184231.3-184232.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:190038.3-190046.6" - wire $1\q_int$next[0:0]$12568 - attribute \src "libresoc.v:190015.7-190015.19" + attribute \src "libresoc.v:184233.3-184241.6" + wire $1\q_int$next[0:0]$12271 + attribute \src "libresoc.v:184210.7-184210.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:190028.17-190028.96" - wire $and$libresoc.v:190028$12557_Y - attribute \src "libresoc.v:190033.17-190033.96" - wire $and$libresoc.v:190033$12562_Y - attribute \src "libresoc.v:190030.18-190030.93" - wire $not$libresoc.v:190030$12559_Y - attribute \src "libresoc.v:190032.17-190032.92" - wire $not$libresoc.v:190032$12561_Y - attribute \src "libresoc.v:190035.17-190035.92" - wire $not$libresoc.v:190035$12564_Y - attribute \src "libresoc.v:190029.18-190029.98" - wire $or$libresoc.v:190029$12558_Y - attribute \src "libresoc.v:190031.18-190031.99" - wire $or$libresoc.v:190031$12560_Y - attribute \src "libresoc.v:190034.17-190034.97" - wire $or$libresoc.v:190034$12563_Y + attribute \src "libresoc.v:184223.17-184223.96" + wire $and$libresoc.v:184223$12260_Y + attribute \src "libresoc.v:184228.17-184228.96" + wire $and$libresoc.v:184228$12265_Y + attribute \src "libresoc.v:184225.18-184225.93" + wire $not$libresoc.v:184225$12262_Y + attribute \src "libresoc.v:184227.17-184227.92" + wire $not$libresoc.v:184227$12264_Y + attribute \src "libresoc.v:184230.17-184230.92" + wire $not$libresoc.v:184230$12267_Y + attribute \src "libresoc.v:184224.18-184224.98" + wire $or$libresoc.v:184224$12261_Y + attribute \src "libresoc.v:184226.18-184226.99" + wire $or$libresoc.v:184226$12263_Y + attribute \src "libresoc.v:184229.17-184229.97" + wire $or$libresoc.v:184229$12266_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -392951,11 +383496,11 @@ module \rst_l$70 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:189993.7-189993.15" + attribute \src "libresoc.v:184188.7-184188.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -392972,7 +383517,7 @@ module \rst_l$70 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190028$12557 + cell $and $and$libresoc.v:184223$12260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392980,10 +383525,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190028$12557_Y + connect \Y $and$libresoc.v:184223$12260_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190033$12562 + cell $and $and$libresoc.v:184228$12265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -392991,34 +383536,34 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190033$12562_Y + connect \Y $and$libresoc.v:184228$12265_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190030$12559 + cell $not $not$libresoc.v:184225$12262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:190030$12559_Y + connect \Y $not$libresoc.v:184225$12262_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190032$12561 + cell $not $not$libresoc.v:184227$12264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:190032$12561_Y + connect \Y $not$libresoc.v:184227$12264_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190035$12564 + cell $not $not$libresoc.v:184230$12267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:190035$12564_Y + connect \Y $not$libresoc.v:184230$12267_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190029$12558 + cell $or $or$libresoc.v:184224$12261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393026,10 +383571,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:190029$12558_Y + connect \Y $or$libresoc.v:184224$12261_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190031$12560 + cell $or $or$libresoc.v:184226$12263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393037,10 +383582,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:190031$12560_Y + connect \Y $or$libresoc.v:184226$12263_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190034$12563 + cell $or $or$libresoc.v:184229$12266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393048,39 +383593,39 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:190034$12563_Y + connect \Y $or$libresoc.v:184229$12266_Y end - attribute \src "libresoc.v:189993.7-189993.20" - process $proc$libresoc.v:189993$12569 + attribute \src "libresoc.v:184188.7-184188.20" + process $proc$libresoc.v:184188$12272 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190015.7-190015.19" - process $proc$libresoc.v:190015$12570 + attribute \src "libresoc.v:184210.7-184210.19" + process $proc$libresoc.v:184210$12273 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:190036.3-190037.27" - process $proc$libresoc.v:190036$12565 + attribute \src "libresoc.v:184231.3-184232.27" + process $proc$libresoc.v:184231$12268 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:190038.3-190046.6" - process $proc$libresoc.v:190038$12566 + attribute \src "libresoc.v:184233.3-184241.6" + process $proc$libresoc.v:184233$12269 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12567 $1\q_int$next[0:0]$12568 - attribute \src "libresoc.v:190039.5-190039.29" + assign $0\q_int$next[0:0]$12270 $1\q_int$next[0:0]$12271 + attribute \src "libresoc.v:184234.5-184234.29" switch \initial - attribute \src "libresoc.v:190039.9-190039.17" + attribute \src "libresoc.v:184234.9-184234.17" case 1'1 case end @@ -393089,56 +383634,56 @@ module \rst_l$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12568 1'0 + assign $1\q_int$next[0:0]$12271 1'0 case - assign $1\q_int$next[0:0]$12568 \$5 + assign $1\q_int$next[0:0]$12271 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12567 + update \q_int$next $0\q_int$next[0:0]$12270 end - connect \$9 $and$libresoc.v:190028$12557_Y - connect \$11 $or$libresoc.v:190029$12558_Y - connect \$13 $not$libresoc.v:190030$12559_Y - connect \$15 $or$libresoc.v:190031$12560_Y - connect \$1 $not$libresoc.v:190032$12561_Y - connect \$3 $and$libresoc.v:190033$12562_Y - connect \$5 $or$libresoc.v:190034$12563_Y - connect \$7 $not$libresoc.v:190035$12564_Y + connect \$9 $and$libresoc.v:184223$12260_Y + connect \$11 $or$libresoc.v:184224$12261_Y + connect \$13 $not$libresoc.v:184225$12262_Y + connect \$15 $or$libresoc.v:184226$12263_Y + connect \$1 $not$libresoc.v:184227$12264_Y + connect \$3 $and$libresoc.v:184228$12265_Y + connect \$5 $or$libresoc.v:184229$12266_Y + connect \$7 $not$libresoc.v:184230$12267_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:190054.1-190112.10" +attribute \src "libresoc.v:184249.1-184307.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" module \rst_l$87 - attribute \src "libresoc.v:190055.7-190055.20" + attribute \src "libresoc.v:184250.7-184250.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190100.3-190108.6" - wire $0\q_int$next[0:0]$12581 - attribute \src "libresoc.v:190098.3-190099.27" + attribute \src "libresoc.v:184295.3-184303.6" + wire $0\q_int$next[0:0]$12284 + attribute \src "libresoc.v:184293.3-184294.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:190100.3-190108.6" - wire $1\q_int$next[0:0]$12582 - attribute \src "libresoc.v:190077.7-190077.19" + attribute \src "libresoc.v:184295.3-184303.6" + wire $1\q_int$next[0:0]$12285 + attribute \src "libresoc.v:184272.7-184272.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:190090.17-190090.96" - wire $and$libresoc.v:190090$12571_Y - attribute \src "libresoc.v:190095.17-190095.96" - wire $and$libresoc.v:190095$12576_Y - attribute \src "libresoc.v:190092.18-190092.93" - wire $not$libresoc.v:190092$12573_Y - attribute \src "libresoc.v:190094.17-190094.92" - wire $not$libresoc.v:190094$12575_Y - attribute \src "libresoc.v:190097.17-190097.92" - wire $not$libresoc.v:190097$12578_Y - attribute \src "libresoc.v:190091.18-190091.98" - wire $or$libresoc.v:190091$12572_Y - attribute \src "libresoc.v:190093.18-190093.99" - wire $or$libresoc.v:190093$12574_Y - attribute \src "libresoc.v:190096.17-190096.97" - wire $or$libresoc.v:190096$12577_Y + attribute \src "libresoc.v:184285.17-184285.96" + wire $and$libresoc.v:184285$12274_Y + attribute \src "libresoc.v:184290.17-184290.96" + wire $and$libresoc.v:184290$12279_Y + attribute \src "libresoc.v:184287.18-184287.93" + wire $not$libresoc.v:184287$12276_Y + attribute \src "libresoc.v:184289.17-184289.92" + wire $not$libresoc.v:184289$12278_Y + attribute \src "libresoc.v:184292.17-184292.92" + wire $not$libresoc.v:184292$12281_Y + attribute \src "libresoc.v:184286.18-184286.98" + wire $or$libresoc.v:184286$12275_Y + attribute \src "libresoc.v:184288.18-184288.99" + wire $or$libresoc.v:184288$12277_Y + attribute \src "libresoc.v:184291.17-184291.97" + wire $or$libresoc.v:184291$12280_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -393155,11 +383700,11 @@ module \rst_l$87 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:190055.7-190055.15" + attribute \src "libresoc.v:184250.7-184250.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -393176,7 +383721,7 @@ module \rst_l$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:190090$12571 + cell $and $and$libresoc.v:184285$12274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393184,10 +383729,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:190090$12571_Y + connect \Y $and$libresoc.v:184285$12274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:190095$12576 + cell $and $and$libresoc.v:184290$12279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393195,34 +383740,34 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:190095$12576_Y + connect \Y $and$libresoc.v:184290$12279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:190092$12573 + cell $not $not$libresoc.v:184287$12276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:190092$12573_Y + connect \Y $not$libresoc.v:184287$12276_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:190094$12575 + cell $not $not$libresoc.v:184289$12278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:190094$12575_Y + connect \Y $not$libresoc.v:184289$12278_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:190097$12578 + cell $not $not$libresoc.v:184292$12281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:190097$12578_Y + connect \Y $not$libresoc.v:184292$12281_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:190091$12572 + cell $or $or$libresoc.v:184286$12275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393230,10 +383775,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:190091$12572_Y + connect \Y $or$libresoc.v:184286$12275_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:190093$12574 + cell $or $or$libresoc.v:184288$12277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393241,10 +383786,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:190093$12574_Y + connect \Y $or$libresoc.v:184288$12277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:190096$12577 + cell $or $or$libresoc.v:184291$12280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393252,39 +383797,39 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:190096$12577_Y + connect \Y $or$libresoc.v:184291$12280_Y end - attribute \src "libresoc.v:190055.7-190055.20" - process $proc$libresoc.v:190055$12583 + attribute \src "libresoc.v:184250.7-184250.20" + process $proc$libresoc.v:184250$12286 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190077.7-190077.19" - process $proc$libresoc.v:190077$12584 + attribute \src "libresoc.v:184272.7-184272.19" + process $proc$libresoc.v:184272$12287 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:190098.3-190099.27" - process $proc$libresoc.v:190098$12579 + attribute \src "libresoc.v:184293.3-184294.27" + process $proc$libresoc.v:184293$12282 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:190100.3-190108.6" - process $proc$libresoc.v:190100$12580 + attribute \src "libresoc.v:184295.3-184303.6" + process $proc$libresoc.v:184295$12283 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12581 $1\q_int$next[0:0]$12582 - attribute \src "libresoc.v:190101.5-190101.29" + assign $0\q_int$next[0:0]$12284 $1\q_int$next[0:0]$12285 + attribute \src "libresoc.v:184296.5-184296.29" switch \initial - attribute \src "libresoc.v:190101.9-190101.17" + attribute \src "libresoc.v:184296.9-184296.17" case 1'1 case end @@ -393293,92 +383838,92 @@ module \rst_l$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12582 1'0 + assign $1\q_int$next[0:0]$12285 1'0 case - assign $1\q_int$next[0:0]$12582 \$5 + assign $1\q_int$next[0:0]$12285 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12581 + update \q_int$next $0\q_int$next[0:0]$12284 end - connect \$9 $and$libresoc.v:190090$12571_Y - connect \$11 $or$libresoc.v:190091$12572_Y - connect \$13 $not$libresoc.v:190092$12573_Y - connect \$15 $or$libresoc.v:190093$12574_Y - connect \$1 $not$libresoc.v:190094$12575_Y - connect \$3 $and$libresoc.v:190095$12576_Y - connect \$5 $or$libresoc.v:190096$12577_Y - connect \$7 $not$libresoc.v:190097$12578_Y + connect \$9 $and$libresoc.v:184285$12274_Y + connect \$11 $or$libresoc.v:184286$12275_Y + connect \$13 $not$libresoc.v:184287$12276_Y + connect \$15 $or$libresoc.v:184288$12277_Y + connect \$1 $not$libresoc.v:184289$12278_Y + connect \$3 $and$libresoc.v:184290$12279_Y + connect \$5 $or$libresoc.v:184291$12280_Y + connect \$7 $not$libresoc.v:184292$12281_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:190116.1-190521.10" +attribute \src "libresoc.v:184311.1-184716.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage - attribute \src "libresoc.v:190479.3-190504.6" + attribute \src "libresoc.v:184674.3-184699.6" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:190117.7-190117.20" + attribute \src "libresoc.v:184312.7-184312.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190479.3-190504.6" + attribute \src "libresoc.v:184674.3-184699.6" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:190479.3-190504.6" + attribute \src "libresoc.v:184674.3-184699.6" wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:190458.18-190458.122" - wire $and$libresoc.v:190458$12586_Y - attribute \src "libresoc.v:190460.18-190460.122" - wire $and$libresoc.v:190460$12588_Y - attribute \src "libresoc.v:190469.18-190469.105" - wire $and$libresoc.v:190469$12601_Y - attribute \src "libresoc.v:190472.18-190472.105" - wire $and$libresoc.v:190472$12604_Y - attribute \src "libresoc.v:190468.18-190468.123" - wire $eq$libresoc.v:190468$12600_Y - attribute \src "libresoc.v:190471.18-190471.123" - wire $eq$libresoc.v:190471$12603_Y - attribute \src "libresoc.v:190474.18-190474.117" - wire $eq$libresoc.v:190474$12606_Y - attribute \src "libresoc.v:190461.18-190461.97" - wire width 65 $extend$libresoc.v:190461$12589_Y - attribute \src "libresoc.v:190462.18-190462.91" - wire width 65 $extend$libresoc.v:190462$12591_Y - attribute \src "libresoc.v:190464.18-190464.97" - wire width 65 $extend$libresoc.v:190464$12594_Y - attribute \src "libresoc.v:190465.18-190465.91" - wire width 65 $extend$libresoc.v:190465$12596_Y - attribute \src "libresoc.v:190477.18-190477.99" - wire width 128 $extend$libresoc.v:190477$12609_Y - attribute \src "libresoc.v:190467.18-190467.112" - wire $ge$libresoc.v:190467$12599_Y - attribute \src "libresoc.v:190470.18-190470.124" - wire $ge$libresoc.v:190470$12602_Y - attribute \src "libresoc.v:190461.18-190461.97" - wire width 65 $neg$libresoc.v:190461$12590_Y - attribute \src "libresoc.v:190464.18-190464.97" - wire width 65 $neg$libresoc.v:190464$12595_Y - attribute \src "libresoc.v:190462.18-190462.91" - wire width 65 $pos$libresoc.v:190462$12592_Y - attribute \src "libresoc.v:190465.18-190465.91" - wire width 65 $pos$libresoc.v:190465$12597_Y - attribute \src "libresoc.v:190477.18-190477.99" - wire width 128 $pos$libresoc.v:190477$12610_Y - attribute \src "libresoc.v:190476.18-190476.117" - wire width 95 $sshl$libresoc.v:190476$12608_Y - attribute \src "libresoc.v:190478.18-190478.111" - wire width 191 $sshl$libresoc.v:190478$12611_Y - attribute \src "libresoc.v:190457.18-190457.131" - wire $ternary$libresoc.v:190457$12585_Y - attribute \src "libresoc.v:190459.18-190459.131" - wire $ternary$libresoc.v:190459$12587_Y - attribute \src "libresoc.v:190463.18-190463.119" - wire width 65 $ternary$libresoc.v:190463$12593_Y - attribute \src "libresoc.v:190466.18-190466.120" - wire width 65 $ternary$libresoc.v:190466$12598_Y - attribute \src "libresoc.v:190473.18-190473.130" - wire width 32 $ternary$libresoc.v:190473$12605_Y - attribute \src "libresoc.v:190475.18-190475.131" - wire width 32 $ternary$libresoc.v:190475$12607_Y + attribute \src "libresoc.v:184653.18-184653.122" + wire $and$libresoc.v:184653$12289_Y + attribute \src "libresoc.v:184655.18-184655.122" + wire $and$libresoc.v:184655$12291_Y + attribute \src "libresoc.v:184664.18-184664.105" + wire $and$libresoc.v:184664$12304_Y + attribute \src "libresoc.v:184667.18-184667.105" + wire $and$libresoc.v:184667$12307_Y + attribute \src "libresoc.v:184663.18-184663.123" + wire $eq$libresoc.v:184663$12303_Y + attribute \src "libresoc.v:184666.18-184666.123" + wire $eq$libresoc.v:184666$12306_Y + attribute \src "libresoc.v:184669.18-184669.117" + wire $eq$libresoc.v:184669$12309_Y + attribute \src "libresoc.v:184656.18-184656.97" + wire width 65 $extend$libresoc.v:184656$12292_Y + attribute \src "libresoc.v:184657.18-184657.91" + wire width 65 $extend$libresoc.v:184657$12294_Y + attribute \src "libresoc.v:184659.18-184659.97" + wire width 65 $extend$libresoc.v:184659$12297_Y + attribute \src "libresoc.v:184660.18-184660.91" + wire width 65 $extend$libresoc.v:184660$12299_Y + attribute \src "libresoc.v:184672.18-184672.99" + wire width 128 $extend$libresoc.v:184672$12312_Y + attribute \src "libresoc.v:184662.18-184662.112" + wire $ge$libresoc.v:184662$12302_Y + attribute \src "libresoc.v:184665.18-184665.124" + wire $ge$libresoc.v:184665$12305_Y + attribute \src "libresoc.v:184656.18-184656.97" + wire width 65 $neg$libresoc.v:184656$12293_Y + attribute \src "libresoc.v:184659.18-184659.97" + wire width 65 $neg$libresoc.v:184659$12298_Y + attribute \src "libresoc.v:184657.18-184657.91" + wire width 65 $pos$libresoc.v:184657$12295_Y + attribute \src "libresoc.v:184660.18-184660.91" + wire width 65 $pos$libresoc.v:184660$12300_Y + attribute \src "libresoc.v:184672.18-184672.99" + wire width 128 $pos$libresoc.v:184672$12313_Y + attribute \src "libresoc.v:184671.18-184671.117" + wire width 95 $sshl$libresoc.v:184671$12311_Y + attribute \src "libresoc.v:184673.18-184673.111" + wire width 191 $sshl$libresoc.v:184673$12314_Y + attribute \src "libresoc.v:184652.18-184652.131" + wire $ternary$libresoc.v:184652$12288_Y + attribute \src "libresoc.v:184654.18-184654.131" + wire $ternary$libresoc.v:184654$12290_Y + attribute \src "libresoc.v:184658.18-184658.119" + wire width 65 $ternary$libresoc.v:184658$12296_Y + attribute \src "libresoc.v:184661.18-184661.120" + wire width 65 $ternary$libresoc.v:184661$12301_Y + attribute \src "libresoc.v:184668.18-184668.130" + wire width 32 $ternary$libresoc.v:184668$12308_Y + attribute \src "libresoc.v:184670.18-184670.131" + wire width 32 $ternary$libresoc.v:184670$12310_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" @@ -393447,7 +383992,7 @@ module \setup_stage wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:190117.7-190117.15" + attribute \src "libresoc.v:184312.7-184312.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -393720,7 +384265,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:190458$12586 + cell $and $and$libresoc.v:184653$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393728,10 +384273,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:190458$12586_Y + connect \Y $and$libresoc.v:184653$12289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:190460$12588 + cell $and $and$libresoc.v:184655$12291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393739,10 +384284,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:190460$12588_Y + connect \Y $and$libresoc.v:184655$12291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:190469$12601 + cell $and $and$libresoc.v:184664$12304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393750,10 +384295,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 - connect \Y $and$libresoc.v:190469$12601_Y + connect \Y $and$libresoc.v:184664$12304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:190472$12604 + cell $and $and$libresoc.v:184667$12307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393761,10 +384306,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:190472$12604_Y + connect \Y $and$libresoc.v:184667$12307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:190468$12600 + cell $eq $eq$libresoc.v:184663$12303 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -393772,10 +384317,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:190468$12600_Y + connect \Y $eq$libresoc.v:184663$12303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:190471$12603 + cell $eq $eq$libresoc.v:184666$12306 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -393783,10 +384328,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:190471$12603_Y + connect \Y $eq$libresoc.v:184666$12306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:190474$12606 + cell $eq $eq$libresoc.v:184669$12309 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -393794,50 +384339,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 - connect \Y $eq$libresoc.v:190474$12606_Y + connect \Y $eq$libresoc.v:184669$12309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:190461$12589 + cell $pos $extend$libresoc.v:184656$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:190461$12589_Y + connect \Y $extend$libresoc.v:184656$12292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:190462$12591 + cell $pos $extend$libresoc.v:184657$12294 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:190462$12591_Y + connect \Y $extend$libresoc.v:184657$12294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:190464$12594 + cell $pos $extend$libresoc.v:184659$12297 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:190464$12594_Y + connect \Y $extend$libresoc.v:184659$12297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:190465$12596 + cell $pos $extend$libresoc.v:184660$12299 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:190465$12596_Y + connect \Y $extend$libresoc.v:184660$12299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:190477$12609 + cell $pos $extend$libresoc.v:184672$12312 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 - connect \Y $extend$libresoc.v:190477$12609_Y + connect \Y $extend$libresoc.v:184672$12312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:190467$12599 + cell $ge $ge$libresoc.v:184662$12302 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -393845,10 +384390,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor - connect \Y $ge$libresoc.v:190467$12599_Y + connect \Y $ge$libresoc.v:184662$12302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:190470$12602 + cell $ge $ge$libresoc.v:184665$12305 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -393856,50 +384401,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:190470$12602_Y + connect \Y $ge$libresoc.v:184665$12305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:190461$12590 + cell $neg $neg$libresoc.v:184656$12293 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:190461$12589_Y - connect \Y $neg$libresoc.v:190461$12590_Y + connect \A $extend$libresoc.v:184656$12292_Y + connect \Y $neg$libresoc.v:184656$12293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:190464$12595 + cell $neg $neg$libresoc.v:184659$12298 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:190464$12594_Y - connect \Y $neg$libresoc.v:190464$12595_Y + connect \A $extend$libresoc.v:184659$12297_Y + connect \Y $neg$libresoc.v:184659$12298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:190462$12592 + cell $pos $pos$libresoc.v:184657$12295 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:190462$12591_Y - connect \Y $pos$libresoc.v:190462$12592_Y + connect \A $extend$libresoc.v:184657$12294_Y + connect \Y $pos$libresoc.v:184657$12295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:190465$12597 + cell $pos $pos$libresoc.v:184660$12300 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:190465$12596_Y - connect \Y $pos$libresoc.v:190465$12597_Y + connect \A $extend$libresoc.v:184660$12299_Y + connect \Y $pos$libresoc.v:184660$12300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:190477$12610 + cell $pos $pos$libresoc.v:184672$12313 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:190477$12609_Y - connect \Y $pos$libresoc.v:190477$12610_Y + connect \A $extend$libresoc.v:184672$12312_Y + connect \Y $pos$libresoc.v:184672$12313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:190476$12608 + cell $sshl $sshl$libresoc.v:184671$12311 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -393907,10 +384452,10 @@ module \setup_stage parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 - connect \Y $sshl$libresoc.v:190476$12608_Y + connect \Y $sshl$libresoc.v:184671$12311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:190478$12611 + cell $sshl $sshl$libresoc.v:184673$12314 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -393918,72 +384463,72 @@ module \setup_stage parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 - connect \Y $sshl$libresoc.v:190478$12611_Y + connect \Y $sshl$libresoc.v:184673$12314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:190457$12585 + cell $mux $ternary$libresoc.v:184652$12288 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:190457$12585_Y + connect \Y $ternary$libresoc.v:184652$12288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:190459$12587 + cell $mux $ternary$libresoc.v:184654$12290 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:190459$12587_Y + connect \Y $ternary$libresoc.v:184654$12290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:190463$12593 + cell $mux $ternary$libresoc.v:184658$12296 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg - connect \Y $ternary$libresoc.v:190463$12593_Y + connect \Y $ternary$libresoc.v:184658$12296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:190466$12598 + cell $mux $ternary$libresoc.v:184661$12301 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg - connect \Y $ternary$libresoc.v:190466$12598_Y + connect \Y $ternary$libresoc.v:184661$12301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:190473$12605 + cell $mux $ternary$libresoc.v:184668$12308 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:190473$12605_Y + connect \Y $ternary$libresoc.v:184668$12308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:190475$12607 + cell $mux $ternary$libresoc.v:184670$12310 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:190475$12607_Y + connect \Y $ternary$libresoc.v:184670$12310_Y end - attribute \src "libresoc.v:190117.7-190117.20" - process $proc$libresoc.v:190117$12613 + attribute \src "libresoc.v:184312.7-184312.20" + process $proc$libresoc.v:184312$12316 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190479.3-190504.6" - process $proc$libresoc.v:190479$12612 + attribute \src "libresoc.v:184674.3-184699.6" + process $proc$libresoc.v:184674$12315 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:190480.5-190480.29" + attribute \src "libresoc.v:184675.5-184675.29" switch \initial - attribute \src "libresoc.v:190480.9-190480.17" + attribute \src "libresoc.v:184675.9-184675.17" case 1'1 case end @@ -394015,28 +384560,28 @@ module \setup_stage sync always update \dividend $0\dividend[127:0] end - connect \$21 $ternary$libresoc.v:190457$12585_Y - connect \$23 $and$libresoc.v:190458$12586_Y - connect \$25 $ternary$libresoc.v:190459$12587_Y - connect \$27 $and$libresoc.v:190460$12588_Y - connect \$30 $neg$libresoc.v:190461$12590_Y - connect \$32 $pos$libresoc.v:190462$12592_Y - connect \$34 $ternary$libresoc.v:190463$12593_Y - connect \$37 $neg$libresoc.v:190464$12595_Y - connect \$39 $pos$libresoc.v:190465$12597_Y - connect \$41 $ternary$libresoc.v:190466$12598_Y - connect \$43 $ge$libresoc.v:190467$12599_Y - connect \$45 $eq$libresoc.v:190468$12600_Y - connect \$47 $and$libresoc.v:190469$12601_Y - connect \$49 $ge$libresoc.v:190470$12602_Y - connect \$51 $eq$libresoc.v:190471$12603_Y - connect \$53 $and$libresoc.v:190472$12604_Y - connect \$55 $ternary$libresoc.v:190473$12605_Y - connect \$57 $eq$libresoc.v:190474$12606_Y - connect \$59 $ternary$libresoc.v:190475$12607_Y - connect \$62 $sshl$libresoc.v:190476$12608_Y - connect \$61 $pos$libresoc.v:190477$12610_Y - connect \$66 $sshl$libresoc.v:190478$12611_Y + connect \$21 $ternary$libresoc.v:184652$12288_Y + connect \$23 $and$libresoc.v:184653$12289_Y + connect \$25 $ternary$libresoc.v:184654$12290_Y + connect \$27 $and$libresoc.v:184655$12291_Y + connect \$30 $neg$libresoc.v:184656$12293_Y + connect \$32 $pos$libresoc.v:184657$12295_Y + connect \$34 $ternary$libresoc.v:184658$12296_Y + connect \$37 $neg$libresoc.v:184659$12298_Y + connect \$39 $pos$libresoc.v:184660$12300_Y + connect \$41 $ternary$libresoc.v:184661$12301_Y + connect \$43 $ge$libresoc.v:184662$12302_Y + connect \$45 $eq$libresoc.v:184663$12303_Y + connect \$47 $and$libresoc.v:184664$12304_Y + connect \$49 $ge$libresoc.v:184665$12305_Y + connect \$51 $eq$libresoc.v:184666$12306_Y + connect \$53 $and$libresoc.v:184667$12307_Y + connect \$55 $ternary$libresoc.v:184668$12308_Y + connect \$57 $eq$libresoc.v:184669$12309_Y + connect \$59 $ternary$libresoc.v:184670$12310_Y + connect \$62 $sshl$libresoc.v:184671$12311_Y + connect \$61 $pos$libresoc.v:184672$12313_Y + connect \$66 $sshl$libresoc.v:184673$12314_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 @@ -394054,513 +384599,513 @@ module \setup_stage connect \dividend_neg \$23 connect \operation 2'01 end -attribute \src "libresoc.v:190525.1-191728.10" +attribute \src "libresoc.v:184720.1-185923.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 - attribute \src "libresoc.v:191299.3-191300.25" + attribute \src "libresoc.v:185494.3-185495.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:191297.3-191298.46" + attribute \src "libresoc.v:185492.3-185493.46" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:191648.3-191656.6" - wire $0\alu_l_r_alu$next[0:0]$12831 - attribute \src "libresoc.v:191215.3-191216.39" + attribute \src "libresoc.v:185843.3-185851.6" + wire $0\alu_l_r_alu$next[0:0]$12534 + attribute \src "libresoc.v:185410.3-185411.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 13 $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12748 - attribute \src "libresoc.v:191243.3-191244.75" + attribute \src "libresoc.v:185680.3-185717.6" + wire width 13 $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12451 + attribute \src "libresoc.v:185438.3-185439.75" wire width 13 $0\alu_shift_rot0_sr_op__fn_unit[12:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12749 - attribute \src "libresoc.v:191245.3-191246.89" + attribute \src "libresoc.v:185680.3-185717.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12452 + attribute \src "libresoc.v:185440.3-185441.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12750 - attribute \src "libresoc.v:191247.3-191248.85" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12453 + attribute \src "libresoc.v:185442.3-185443.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12751 - attribute \src "libresoc.v:191261.3-191262.83" + attribute \src "libresoc.v:185680.3-185717.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12454 + attribute \src "libresoc.v:185456.3-185457.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12752 - attribute \src "libresoc.v:191265.3-191266.77" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12455 + attribute \src "libresoc.v:185460.3-185461.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12753 - attribute \src "libresoc.v:191273.3-191274.69" + attribute \src "libresoc.v:185680.3-185717.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12456 + attribute \src "libresoc.v:185468.3-185469.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12754 - attribute \src "libresoc.v:191241.3-191242.79" + attribute \src "libresoc.v:185680.3-185717.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12457 + attribute \src "libresoc.v:185436.3-185437.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12755 - attribute \src "libresoc.v:191259.3-191260.79" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12458 + attribute \src "libresoc.v:185454.3-185455.79" wire $0\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12756 - attribute \src "libresoc.v:191269.3-191270.77" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12459 + attribute \src "libresoc.v:185464.3-185465.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12757 - attribute \src "libresoc.v:191271.3-191272.79" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12460 + attribute \src "libresoc.v:185466.3-185467.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12758 - attribute \src "libresoc.v:191253.3-191254.73" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12461 + attribute \src "libresoc.v:185448.3-185449.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12759 - attribute \src "libresoc.v:191255.3-191256.73" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12462 + attribute \src "libresoc.v:185450.3-185451.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12760 - attribute \src "libresoc.v:191263.3-191264.85" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12463 + attribute \src "libresoc.v:185458.3-185459.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12761 - attribute \src "libresoc.v:191267.3-191268.79" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12464 + attribute \src "libresoc.v:185462.3-185463.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12762 - attribute \src "libresoc.v:191251.3-191252.73" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12465 + attribute \src "libresoc.v:185446.3-185447.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12763 - attribute \src "libresoc.v:191249.3-191250.73" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12466 + attribute \src "libresoc.v:185444.3-185445.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12764 - attribute \src "libresoc.v:191257.3-191258.79" + attribute \src "libresoc.v:185680.3-185717.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12467 + attribute \src "libresoc.v:185452.3-185453.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:191639.3-191647.6" - wire $0\alui_l_r_alui$next[0:0]$12828 - attribute \src "libresoc.v:191217.3-191218.43" + attribute \src "libresoc.v:185834.3-185842.6" + wire $0\alui_l_r_alui$next[0:0]$12531 + attribute \src "libresoc.v:185412.3-185413.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:191523.3-191544.6" - wire width 64 $0\data_r0__o$next[63:0]$12789 - attribute \src "libresoc.v:191237.3-191238.37" + attribute \src "libresoc.v:185718.3-185739.6" + wire width 64 $0\data_r0__o$next[63:0]$12492 + attribute \src "libresoc.v:185432.3-185433.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:191523.3-191544.6" - wire $0\data_r0__o_ok$next[0:0]$12790 - attribute \src "libresoc.v:191239.3-191240.43" + attribute \src "libresoc.v:185718.3-185739.6" + wire $0\data_r0__o_ok$next[0:0]$12493 + attribute \src "libresoc.v:185434.3-185435.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:191545.3-191566.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$12797 - attribute \src "libresoc.v:191233.3-191234.43" + attribute \src "libresoc.v:185740.3-185761.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12500 + attribute \src "libresoc.v:185428.3-185429.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:191545.3-191566.6" - wire $0\data_r1__cr_a_ok$next[0:0]$12798 - attribute \src "libresoc.v:191235.3-191236.49" + attribute \src "libresoc.v:185740.3-185761.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12501 + attribute \src "libresoc.v:185430.3-185431.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:191567.3-191588.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$12805 - attribute \src "libresoc.v:191229.3-191230.47" + attribute \src "libresoc.v:185762.3-185783.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12508 + attribute \src "libresoc.v:185424.3-185425.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:191567.3-191588.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$12806 - attribute \src "libresoc.v:191231.3-191232.53" + attribute \src "libresoc.v:185762.3-185783.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12509 + attribute \src "libresoc.v:185426.3-185427.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:191657.3-191666.6" + attribute \src "libresoc.v:185852.3-185861.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:191667.3-191676.6" + attribute \src "libresoc.v:185862.3-185871.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:191677.3-191686.6" + attribute \src "libresoc.v:185872.3-185881.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:190526.7-190526.20" + attribute \src "libresoc.v:184721.7-184721.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191440.3-191448.6" - wire $0\opc_l_r_opc$next[0:0]$12733 - attribute \src "libresoc.v:191283.3-191284.39" + attribute \src "libresoc.v:185635.3-185643.6" + wire $0\opc_l_r_opc$next[0:0]$12436 + attribute \src "libresoc.v:185478.3-185479.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:191431.3-191439.6" - wire $0\opc_l_s_opc$next[0:0]$12730 - attribute \src "libresoc.v:191285.3-191286.39" + attribute \src "libresoc.v:185626.3-185634.6" + wire $0\opc_l_s_opc$next[0:0]$12433 + attribute \src "libresoc.v:185480.3-185481.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:191687.3-191695.6" - wire width 3 $0\prev_wr_go$next[2:0]$12837 - attribute \src "libresoc.v:191295.3-191296.37" + attribute \src "libresoc.v:185882.3-185890.6" + wire width 3 $0\prev_wr_go$next[2:0]$12540 + attribute \src "libresoc.v:185490.3-185491.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:191385.3-191394.6" + attribute \src "libresoc.v:185580.3-185589.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:191476.3-191484.6" - wire width 3 $0\req_l_r_req$next[2:0]$12745 - attribute \src "libresoc.v:191275.3-191276.39" + attribute \src "libresoc.v:185671.3-185679.6" + wire width 3 $0\req_l_r_req$next[2:0]$12448 + attribute \src "libresoc.v:185470.3-185471.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:191467.3-191475.6" - wire width 3 $0\req_l_s_req$next[2:0]$12742 - attribute \src "libresoc.v:191277.3-191278.39" + attribute \src "libresoc.v:185662.3-185670.6" + wire width 3 $0\req_l_s_req$next[2:0]$12445 + attribute \src "libresoc.v:185472.3-185473.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:191404.3-191412.6" - wire $0\rok_l_r_rdok$next[0:0]$12721 - attribute \src "libresoc.v:191291.3-191292.41" + attribute \src "libresoc.v:185599.3-185607.6" + wire $0\rok_l_r_rdok$next[0:0]$12424 + attribute \src "libresoc.v:185486.3-185487.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:191395.3-191403.6" - wire $0\rok_l_s_rdok$next[0:0]$12718 - attribute \src "libresoc.v:191293.3-191294.41" + attribute \src "libresoc.v:185590.3-185598.6" + wire $0\rok_l_s_rdok$next[0:0]$12421 + attribute \src "libresoc.v:185488.3-185489.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:191422.3-191430.6" - wire $0\rst_l_r_rst$next[0:0]$12727 - attribute \src "libresoc.v:191287.3-191288.39" + attribute \src "libresoc.v:185617.3-185625.6" + wire $0\rst_l_r_rst$next[0:0]$12430 + attribute \src "libresoc.v:185482.3-185483.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:191413.3-191421.6" - wire $0\rst_l_s_rst$next[0:0]$12724 - attribute \src "libresoc.v:191289.3-191290.39" + attribute \src "libresoc.v:185608.3-185616.6" + wire $0\rst_l_s_rst$next[0:0]$12427 + attribute \src "libresoc.v:185484.3-185485.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:191458.3-191466.6" - wire width 5 $0\src_l_r_src$next[4:0]$12739 - attribute \src "libresoc.v:191279.3-191280.39" + attribute \src "libresoc.v:185653.3-185661.6" + wire width 5 $0\src_l_r_src$next[4:0]$12442 + attribute \src "libresoc.v:185474.3-185475.39" wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:191449.3-191457.6" - wire width 5 $0\src_l_s_src$next[4:0]$12736 - attribute \src "libresoc.v:191281.3-191282.39" + attribute \src "libresoc.v:185644.3-185652.6" + wire width 5 $0\src_l_s_src$next[4:0]$12439 + attribute \src "libresoc.v:185476.3-185477.39" wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:191589.3-191598.6" - wire width 64 $0\src_r0$next[63:0]$12813 - attribute \src "libresoc.v:191227.3-191228.29" + attribute \src "libresoc.v:185784.3-185793.6" + wire width 64 $0\src_r0$next[63:0]$12516 + attribute \src "libresoc.v:185422.3-185423.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:191599.3-191608.6" - wire width 64 $0\src_r1$next[63:0]$12816 - attribute \src "libresoc.v:191225.3-191226.29" + attribute \src "libresoc.v:185794.3-185803.6" + wire width 64 $0\src_r1$next[63:0]$12519 + attribute \src "libresoc.v:185420.3-185421.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:191609.3-191618.6" - wire width 64 $0\src_r2$next[63:0]$12819 - attribute \src "libresoc.v:191223.3-191224.29" + attribute \src "libresoc.v:185804.3-185813.6" + wire width 64 $0\src_r2$next[63:0]$12522 + attribute \src "libresoc.v:185418.3-185419.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:191619.3-191628.6" - wire $0\src_r3$next[0:0]$12822 - attribute \src "libresoc.v:191221.3-191222.29" + attribute \src "libresoc.v:185814.3-185823.6" + wire $0\src_r3$next[0:0]$12525 + attribute \src "libresoc.v:185416.3-185417.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:191629.3-191638.6" - wire width 2 $0\src_r4$next[1:0]$12825 - attribute \src "libresoc.v:191219.3-191220.29" + attribute \src "libresoc.v:185824.3-185833.6" + wire width 2 $0\src_r4$next[1:0]$12528 + attribute \src "libresoc.v:185414.3-185415.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:190648.7-190648.24" + attribute \src "libresoc.v:184843.7-184843.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:190658.7-190658.26" + attribute \src "libresoc.v:184853.7-184853.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:191648.3-191656.6" - wire $1\alu_l_r_alu$next[0:0]$12832 - attribute \src "libresoc.v:190666.7-190666.25" + attribute \src "libresoc.v:185843.3-185851.6" + wire $1\alu_l_r_alu$next[0:0]$12535 + attribute \src "libresoc.v:184861.7-184861.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 13 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12765 - attribute \src "libresoc.v:190708.14-190708.54" + attribute \src "libresoc.v:185680.3-185717.6" + wire width 13 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12468 + attribute \src "libresoc.v:184903.14-184903.54" wire width 13 $1\alu_shift_rot0_sr_op__fn_unit[12:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12766 - attribute \src "libresoc.v:190712.14-190712.73" + attribute \src "libresoc.v:185680.3-185717.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12469 + attribute \src "libresoc.v:184907.14-184907.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12767 - attribute \src "libresoc.v:190716.7-190716.48" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12470 + attribute \src "libresoc.v:184911.7-184911.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12768 - attribute \src "libresoc.v:190724.13-190724.53" + attribute \src "libresoc.v:185680.3-185717.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12471 + attribute \src "libresoc.v:184919.13-184919.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12769 - attribute \src "libresoc.v:190728.7-190728.44" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12472 + attribute \src "libresoc.v:184923.7-184923.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12770 - attribute \src "libresoc.v:190732.14-190732.48" + attribute \src "libresoc.v:185680.3-185717.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12473 + attribute \src "libresoc.v:184927.14-184927.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12771 - attribute \src "libresoc.v:190810.13-190810.52" + attribute \src "libresoc.v:185680.3-185717.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12474 + attribute \src "libresoc.v:185005.13-185005.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12772 - attribute \src "libresoc.v:190814.7-190814.45" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12475 + attribute \src "libresoc.v:185009.7-185009.45" wire $1\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12773 - attribute \src "libresoc.v:190818.7-190818.44" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12476 + attribute \src "libresoc.v:185013.7-185013.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12774 - attribute \src "libresoc.v:190822.7-190822.45" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12477 + attribute \src "libresoc.v:185017.7-185017.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12775 - attribute \src "libresoc.v:190826.7-190826.42" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12478 + attribute \src "libresoc.v:185021.7-185021.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12776 - attribute \src "libresoc.v:190830.7-190830.42" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12479 + attribute \src "libresoc.v:185025.7-185025.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12777 - attribute \src "libresoc.v:190834.7-190834.48" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12480 + attribute \src "libresoc.v:185029.7-185029.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12778 - attribute \src "libresoc.v:190838.7-190838.45" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12481 + attribute \src "libresoc.v:185033.7-185033.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12779 - attribute \src "libresoc.v:190842.7-190842.42" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12482 + attribute \src "libresoc.v:185037.7-185037.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12780 - attribute \src "libresoc.v:190846.7-190846.42" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12483 + attribute \src "libresoc.v:185041.7-185041.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12781 - attribute \src "libresoc.v:190850.7-190850.45" + attribute \src "libresoc.v:185680.3-185717.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12484 + attribute \src "libresoc.v:185045.7-185045.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:191639.3-191647.6" - wire $1\alui_l_r_alui$next[0:0]$12829 - attribute \src "libresoc.v:190862.7-190862.27" + attribute \src "libresoc.v:185834.3-185842.6" + wire $1\alui_l_r_alui$next[0:0]$12532 + attribute \src "libresoc.v:185057.7-185057.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:191523.3-191544.6" - wire width 64 $1\data_r0__o$next[63:0]$12791 - attribute \src "libresoc.v:190896.14-190896.47" + attribute \src "libresoc.v:185718.3-185739.6" + wire width 64 $1\data_r0__o$next[63:0]$12494 + attribute \src "libresoc.v:185091.14-185091.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:191523.3-191544.6" - wire $1\data_r0__o_ok$next[0:0]$12792 - attribute \src "libresoc.v:190900.7-190900.27" + attribute \src "libresoc.v:185718.3-185739.6" + wire $1\data_r0__o_ok$next[0:0]$12495 + attribute \src "libresoc.v:185095.7-185095.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:191545.3-191566.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$12799 - attribute \src "libresoc.v:190904.13-190904.33" + attribute \src "libresoc.v:185740.3-185761.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12502 + attribute \src "libresoc.v:185099.13-185099.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:191545.3-191566.6" - wire $1\data_r1__cr_a_ok$next[0:0]$12800 - attribute \src "libresoc.v:190908.7-190908.30" + attribute \src "libresoc.v:185740.3-185761.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12503 + attribute \src "libresoc.v:185103.7-185103.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:191567.3-191588.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$12807 - attribute \src "libresoc.v:190912.13-190912.35" + attribute \src "libresoc.v:185762.3-185783.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12510 + attribute \src "libresoc.v:185107.13-185107.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:191567.3-191588.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$12808 - attribute \src "libresoc.v:190916.7-190916.32" + attribute \src "libresoc.v:185762.3-185783.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12511 + attribute \src "libresoc.v:185111.7-185111.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:191657.3-191666.6" + attribute \src "libresoc.v:185852.3-185861.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:191667.3-191676.6" + attribute \src "libresoc.v:185862.3-185871.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:191677.3-191686.6" + attribute \src "libresoc.v:185872.3-185881.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:191440.3-191448.6" - wire $1\opc_l_r_opc$next[0:0]$12734 - attribute \src "libresoc.v:190933.7-190933.25" + attribute \src "libresoc.v:185635.3-185643.6" + wire $1\opc_l_r_opc$next[0:0]$12437 + attribute \src "libresoc.v:185128.7-185128.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:191431.3-191439.6" - wire $1\opc_l_s_opc$next[0:0]$12731 - attribute \src "libresoc.v:190937.7-190937.25" + attribute \src "libresoc.v:185626.3-185634.6" + wire $1\opc_l_s_opc$next[0:0]$12434 + attribute \src "libresoc.v:185132.7-185132.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:191687.3-191695.6" - wire width 3 $1\prev_wr_go$next[2:0]$12838 - attribute \src "libresoc.v:191067.13-191067.30" + attribute \src "libresoc.v:185882.3-185890.6" + wire width 3 $1\prev_wr_go$next[2:0]$12541 + attribute \src "libresoc.v:185262.13-185262.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:191385.3-191394.6" + attribute \src "libresoc.v:185580.3-185589.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:191476.3-191484.6" - wire width 3 $1\req_l_r_req$next[2:0]$12746 - attribute \src "libresoc.v:191075.13-191075.31" + attribute \src "libresoc.v:185671.3-185679.6" + wire width 3 $1\req_l_r_req$next[2:0]$12449 + attribute \src "libresoc.v:185270.13-185270.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:191467.3-191475.6" - wire width 3 $1\req_l_s_req$next[2:0]$12743 - attribute \src "libresoc.v:191079.13-191079.31" + attribute \src "libresoc.v:185662.3-185670.6" + wire width 3 $1\req_l_s_req$next[2:0]$12446 + attribute \src "libresoc.v:185274.13-185274.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:191404.3-191412.6" - wire $1\rok_l_r_rdok$next[0:0]$12722 - attribute \src "libresoc.v:191091.7-191091.26" + attribute \src "libresoc.v:185599.3-185607.6" + wire $1\rok_l_r_rdok$next[0:0]$12425 + attribute \src "libresoc.v:185286.7-185286.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:191395.3-191403.6" - wire $1\rok_l_s_rdok$next[0:0]$12719 - attribute \src "libresoc.v:191095.7-191095.26" + attribute \src "libresoc.v:185590.3-185598.6" + wire $1\rok_l_s_rdok$next[0:0]$12422 + attribute \src "libresoc.v:185290.7-185290.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:191422.3-191430.6" - wire $1\rst_l_r_rst$next[0:0]$12728 - attribute \src "libresoc.v:191099.7-191099.25" + attribute \src "libresoc.v:185617.3-185625.6" + wire $1\rst_l_r_rst$next[0:0]$12431 + attribute \src "libresoc.v:185294.7-185294.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:191413.3-191421.6" - wire $1\rst_l_s_rst$next[0:0]$12725 - attribute \src "libresoc.v:191103.7-191103.25" + attribute \src "libresoc.v:185608.3-185616.6" + wire $1\rst_l_s_rst$next[0:0]$12428 + attribute \src "libresoc.v:185298.7-185298.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:191458.3-191466.6" - wire width 5 $1\src_l_r_src$next[4:0]$12740 - attribute \src "libresoc.v:191121.13-191121.32" + attribute \src "libresoc.v:185653.3-185661.6" + wire width 5 $1\src_l_r_src$next[4:0]$12443 + attribute \src "libresoc.v:185316.13-185316.32" wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:191449.3-191457.6" - wire width 5 $1\src_l_s_src$next[4:0]$12737 - attribute \src "libresoc.v:191125.13-191125.32" + attribute \src "libresoc.v:185644.3-185652.6" + wire width 5 $1\src_l_s_src$next[4:0]$12440 + attribute \src "libresoc.v:185320.13-185320.32" wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:191589.3-191598.6" - wire width 64 $1\src_r0$next[63:0]$12814 - attribute \src "libresoc.v:191131.14-191131.43" + attribute \src "libresoc.v:185784.3-185793.6" + wire width 64 $1\src_r0$next[63:0]$12517 + attribute \src "libresoc.v:185326.14-185326.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:191599.3-191608.6" - wire width 64 $1\src_r1$next[63:0]$12817 - attribute \src "libresoc.v:191135.14-191135.43" + attribute \src "libresoc.v:185794.3-185803.6" + wire width 64 $1\src_r1$next[63:0]$12520 + attribute \src "libresoc.v:185330.14-185330.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:191609.3-191618.6" - wire width 64 $1\src_r2$next[63:0]$12820 - attribute \src "libresoc.v:191139.14-191139.43" + attribute \src "libresoc.v:185804.3-185813.6" + wire width 64 $1\src_r2$next[63:0]$12523 + attribute \src "libresoc.v:185334.14-185334.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:191619.3-191628.6" - wire $1\src_r3$next[0:0]$12823 - attribute \src "libresoc.v:191143.7-191143.20" + attribute \src "libresoc.v:185814.3-185823.6" + wire $1\src_r3$next[0:0]$12526 + attribute \src "libresoc.v:185338.7-185338.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:191629.3-191638.6" - wire width 2 $1\src_r4$next[1:0]$12826 - attribute \src "libresoc.v:191147.13-191147.26" + attribute \src "libresoc.v:185824.3-185833.6" + wire width 2 $1\src_r4$next[1:0]$12529 + attribute \src "libresoc.v:185342.13-185342.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:191485.3-191522.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12782 - attribute \src "libresoc.v:191485.3-191522.6" - wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12783 - attribute \src "libresoc.v:191485.3-191522.6" - wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12784 - attribute \src "libresoc.v:191485.3-191522.6" - wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12785 - attribute \src "libresoc.v:191485.3-191522.6" - wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12786 - attribute \src "libresoc.v:191485.3-191522.6" - wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12787 - attribute \src "libresoc.v:191523.3-191544.6" - wire width 64 $2\data_r0__o$next[63:0]$12793 - attribute \src "libresoc.v:191523.3-191544.6" - wire $2\data_r0__o_ok$next[0:0]$12794 - attribute \src "libresoc.v:191545.3-191566.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$12801 - attribute \src "libresoc.v:191545.3-191566.6" - wire $2\data_r1__cr_a_ok$next[0:0]$12802 - attribute \src "libresoc.v:191567.3-191588.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$12809 - attribute \src "libresoc.v:191567.3-191588.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$12810 - attribute \src "libresoc.v:191523.3-191544.6" - wire $3\data_r0__o_ok$next[0:0]$12795 - attribute \src "libresoc.v:191545.3-191566.6" - wire $3\data_r1__cr_a_ok$next[0:0]$12803 - attribute \src "libresoc.v:191567.3-191588.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$12811 - attribute \src "libresoc.v:191157.19-191157.114" - wire width 5 $and$libresoc.v:191157$12615_Y - attribute \src "libresoc.v:191158.19-191158.125" - wire $and$libresoc.v:191158$12616_Y - attribute \src "libresoc.v:191159.19-191159.125" - wire $and$libresoc.v:191159$12617_Y - attribute \src "libresoc.v:191160.19-191160.125" - wire $and$libresoc.v:191160$12618_Y - attribute \src "libresoc.v:191161.18-191161.110" - wire $and$libresoc.v:191161$12619_Y - attribute \src "libresoc.v:191162.19-191162.141" - wire width 3 $and$libresoc.v:191162$12620_Y - attribute \src "libresoc.v:191163.19-191163.121" - wire width 3 $and$libresoc.v:191163$12621_Y - attribute \src "libresoc.v:191164.19-191164.127" - wire $and$libresoc.v:191164$12622_Y - attribute \src "libresoc.v:191165.19-191165.127" - wire $and$libresoc.v:191165$12623_Y - attribute \src "libresoc.v:191166.19-191166.127" - wire $and$libresoc.v:191166$12624_Y - attribute \src "libresoc.v:191168.18-191168.98" - wire $and$libresoc.v:191168$12626_Y - attribute \src "libresoc.v:191170.18-191170.100" - wire $and$libresoc.v:191170$12628_Y - attribute \src "libresoc.v:191171.18-191171.149" - wire width 3 $and$libresoc.v:191171$12629_Y - attribute \src "libresoc.v:191173.18-191173.119" - wire width 3 $and$libresoc.v:191173$12631_Y - attribute \src "libresoc.v:191176.17-191176.123" - wire $and$libresoc.v:191176$12634_Y - attribute \src "libresoc.v:191177.18-191177.116" - wire $and$libresoc.v:191177$12635_Y - attribute \src "libresoc.v:191182.18-191182.113" - wire $and$libresoc.v:191182$12640_Y - attribute \src "libresoc.v:191183.18-191183.125" - wire width 3 $and$libresoc.v:191183$12641_Y - attribute \src "libresoc.v:191185.18-191185.112" - wire $and$libresoc.v:191185$12643_Y - attribute \src "libresoc.v:191187.18-191187.132" - wire $and$libresoc.v:191187$12645_Y - attribute \src "libresoc.v:191188.18-191188.132" - wire $and$libresoc.v:191188$12646_Y - attribute \src "libresoc.v:191189.18-191189.117" - wire $and$libresoc.v:191189$12647_Y - attribute \src "libresoc.v:191195.18-191195.136" - wire $and$libresoc.v:191195$12653_Y - attribute \src "libresoc.v:191196.18-191196.124" - wire width 3 $and$libresoc.v:191196$12654_Y - attribute \src "libresoc.v:191198.18-191198.116" - wire $and$libresoc.v:191198$12656_Y - attribute \src "libresoc.v:191199.18-191199.119" - wire $and$libresoc.v:191199$12657_Y - attribute \src "libresoc.v:191200.18-191200.121" - wire $and$libresoc.v:191200$12658_Y - attribute \src "libresoc.v:191210.18-191210.140" - wire $and$libresoc.v:191210$12668_Y - attribute \src "libresoc.v:191211.18-191211.138" - wire $and$libresoc.v:191211$12669_Y - attribute \src "libresoc.v:191212.18-191212.171" - wire width 5 $and$libresoc.v:191212$12670_Y - attribute \src "libresoc.v:191214.18-191214.129" - wire width 5 $and$libresoc.v:191214$12672_Y - attribute \src "libresoc.v:191184.18-191184.113" - wire $eq$libresoc.v:191184$12642_Y - attribute \src "libresoc.v:191186.18-191186.119" - wire $eq$libresoc.v:191186$12644_Y - attribute \src "libresoc.v:191156.19-191156.115" - wire width 5 $not$libresoc.v:191156$12614_Y - attribute \src "libresoc.v:191167.18-191167.97" - wire $not$libresoc.v:191167$12625_Y - attribute \src "libresoc.v:191169.18-191169.99" - wire $not$libresoc.v:191169$12627_Y - attribute \src "libresoc.v:191172.18-191172.113" - wire width 3 $not$libresoc.v:191172$12630_Y - attribute \src "libresoc.v:191175.18-191175.106" - wire $not$libresoc.v:191175$12633_Y - attribute \src "libresoc.v:191181.18-191181.126" - wire $not$libresoc.v:191181$12639_Y - attribute \src "libresoc.v:191192.17-191192.113" - wire width 5 $not$libresoc.v:191192$12650_Y - attribute \src "libresoc.v:191213.18-191213.136" - wire $not$libresoc.v:191213$12671_Y - attribute \src "libresoc.v:191180.18-191180.112" - wire $or$libresoc.v:191180$12638_Y - attribute \src "libresoc.v:191190.18-191190.122" - wire $or$libresoc.v:191190$12648_Y - attribute \src "libresoc.v:191191.18-191191.124" - wire $or$libresoc.v:191191$12649_Y - attribute \src "libresoc.v:191193.18-191193.155" - wire width 3 $or$libresoc.v:191193$12651_Y - attribute \src "libresoc.v:191194.18-191194.181" - wire width 5 $or$libresoc.v:191194$12652_Y - attribute \src "libresoc.v:191197.18-191197.120" - wire width 3 $or$libresoc.v:191197$12655_Y - attribute \src "libresoc.v:191203.17-191203.117" - wire width 5 $or$libresoc.v:191203$12661_Y - attribute \src "libresoc.v:191209.17-191209.104" - wire $reduce_and$libresoc.v:191209$12667_Y - attribute \src "libresoc.v:191174.18-191174.106" - wire $reduce_or$libresoc.v:191174$12632_Y - attribute \src "libresoc.v:191178.18-191178.113" - wire $reduce_or$libresoc.v:191178$12636_Y - attribute \src "libresoc.v:191179.18-191179.112" - wire $reduce_or$libresoc.v:191179$12637_Y - attribute \src "libresoc.v:191201.18-191201.165" - wire $ternary$libresoc.v:191201$12659_Y - attribute \src "libresoc.v:191202.18-191202.182" - wire width 64 $ternary$libresoc.v:191202$12660_Y - attribute \src "libresoc.v:191204.18-191204.118" - wire width 64 $ternary$libresoc.v:191204$12662_Y - attribute \src "libresoc.v:191205.18-191205.115" - wire width 64 $ternary$libresoc.v:191205$12663_Y - attribute \src "libresoc.v:191206.18-191206.118" - wire width 64 $ternary$libresoc.v:191206$12664_Y - attribute \src "libresoc.v:191207.18-191207.118" - wire $ternary$libresoc.v:191207$12665_Y - attribute \src "libresoc.v:191208.18-191208.118" - wire width 2 $ternary$libresoc.v:191208$12666_Y + attribute \src "libresoc.v:185680.3-185717.6" + wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12485 + attribute \src "libresoc.v:185680.3-185717.6" + wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12486 + attribute \src "libresoc.v:185680.3-185717.6" + wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12487 + attribute \src "libresoc.v:185680.3-185717.6" + wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12488 + attribute \src "libresoc.v:185680.3-185717.6" + wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12489 + attribute \src "libresoc.v:185680.3-185717.6" + wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12490 + attribute \src "libresoc.v:185718.3-185739.6" + wire width 64 $2\data_r0__o$next[63:0]$12496 + attribute \src "libresoc.v:185718.3-185739.6" + wire $2\data_r0__o_ok$next[0:0]$12497 + attribute \src "libresoc.v:185740.3-185761.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$12504 + attribute \src "libresoc.v:185740.3-185761.6" + wire $2\data_r1__cr_a_ok$next[0:0]$12505 + attribute \src "libresoc.v:185762.3-185783.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$12512 + attribute \src "libresoc.v:185762.3-185783.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$12513 + attribute \src "libresoc.v:185718.3-185739.6" + wire $3\data_r0__o_ok$next[0:0]$12498 + attribute \src "libresoc.v:185740.3-185761.6" + wire $3\data_r1__cr_a_ok$next[0:0]$12506 + attribute \src "libresoc.v:185762.3-185783.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$12514 + attribute \src "libresoc.v:185352.19-185352.114" + wire width 5 $and$libresoc.v:185352$12318_Y + attribute \src "libresoc.v:185353.19-185353.125" + wire $and$libresoc.v:185353$12319_Y + attribute \src "libresoc.v:185354.19-185354.125" + wire $and$libresoc.v:185354$12320_Y + attribute \src "libresoc.v:185355.19-185355.125" + wire $and$libresoc.v:185355$12321_Y + attribute \src "libresoc.v:185356.18-185356.110" + wire $and$libresoc.v:185356$12322_Y + attribute \src "libresoc.v:185357.19-185357.141" + wire width 3 $and$libresoc.v:185357$12323_Y + attribute \src "libresoc.v:185358.19-185358.121" + wire width 3 $and$libresoc.v:185358$12324_Y + attribute \src "libresoc.v:185359.19-185359.127" + wire $and$libresoc.v:185359$12325_Y + attribute \src "libresoc.v:185360.19-185360.127" + wire $and$libresoc.v:185360$12326_Y + attribute \src "libresoc.v:185361.19-185361.127" + wire $and$libresoc.v:185361$12327_Y + attribute \src "libresoc.v:185363.18-185363.98" + wire $and$libresoc.v:185363$12329_Y + attribute \src "libresoc.v:185365.18-185365.100" + wire $and$libresoc.v:185365$12331_Y + attribute \src "libresoc.v:185366.18-185366.149" + wire width 3 $and$libresoc.v:185366$12332_Y + attribute \src "libresoc.v:185368.18-185368.119" + wire width 3 $and$libresoc.v:185368$12334_Y + attribute \src "libresoc.v:185371.17-185371.123" + wire $and$libresoc.v:185371$12337_Y + attribute \src "libresoc.v:185372.18-185372.116" + wire $and$libresoc.v:185372$12338_Y + attribute \src "libresoc.v:185377.18-185377.113" + wire $and$libresoc.v:185377$12343_Y + attribute \src "libresoc.v:185378.18-185378.125" + wire width 3 $and$libresoc.v:185378$12344_Y + attribute \src "libresoc.v:185380.18-185380.112" + wire $and$libresoc.v:185380$12346_Y + attribute \src "libresoc.v:185382.18-185382.132" + wire $and$libresoc.v:185382$12348_Y + attribute \src "libresoc.v:185383.18-185383.132" + wire $and$libresoc.v:185383$12349_Y + attribute \src "libresoc.v:185384.18-185384.117" + wire $and$libresoc.v:185384$12350_Y + attribute \src "libresoc.v:185390.18-185390.136" + wire $and$libresoc.v:185390$12356_Y + attribute \src "libresoc.v:185391.18-185391.124" + wire width 3 $and$libresoc.v:185391$12357_Y + attribute \src "libresoc.v:185393.18-185393.116" + wire $and$libresoc.v:185393$12359_Y + attribute \src "libresoc.v:185394.18-185394.119" + wire $and$libresoc.v:185394$12360_Y + attribute \src "libresoc.v:185395.18-185395.121" + wire $and$libresoc.v:185395$12361_Y + attribute \src "libresoc.v:185405.18-185405.140" + wire $and$libresoc.v:185405$12371_Y + attribute \src "libresoc.v:185406.18-185406.138" + wire $and$libresoc.v:185406$12372_Y + attribute \src "libresoc.v:185407.18-185407.171" + wire width 5 $and$libresoc.v:185407$12373_Y + attribute \src "libresoc.v:185409.18-185409.129" + wire width 5 $and$libresoc.v:185409$12375_Y + attribute \src "libresoc.v:185379.18-185379.113" + wire $eq$libresoc.v:185379$12345_Y + attribute \src "libresoc.v:185381.18-185381.119" + wire $eq$libresoc.v:185381$12347_Y + attribute \src "libresoc.v:185351.19-185351.115" + wire width 5 $not$libresoc.v:185351$12317_Y + attribute \src "libresoc.v:185362.18-185362.97" + wire $not$libresoc.v:185362$12328_Y + attribute \src "libresoc.v:185364.18-185364.99" + wire $not$libresoc.v:185364$12330_Y + attribute \src "libresoc.v:185367.18-185367.113" + wire width 3 $not$libresoc.v:185367$12333_Y + attribute \src "libresoc.v:185370.18-185370.106" + wire $not$libresoc.v:185370$12336_Y + attribute \src "libresoc.v:185376.18-185376.126" + wire $not$libresoc.v:185376$12342_Y + attribute \src "libresoc.v:185387.17-185387.113" + wire width 5 $not$libresoc.v:185387$12353_Y + attribute \src "libresoc.v:185408.18-185408.136" + wire $not$libresoc.v:185408$12374_Y + attribute \src "libresoc.v:185375.18-185375.112" + wire $or$libresoc.v:185375$12341_Y + attribute \src "libresoc.v:185385.18-185385.122" + wire $or$libresoc.v:185385$12351_Y + attribute \src "libresoc.v:185386.18-185386.124" + wire $or$libresoc.v:185386$12352_Y + attribute \src "libresoc.v:185388.18-185388.155" + wire width 3 $or$libresoc.v:185388$12354_Y + attribute \src "libresoc.v:185389.18-185389.181" + wire width 5 $or$libresoc.v:185389$12355_Y + attribute \src "libresoc.v:185392.18-185392.120" + wire width 3 $or$libresoc.v:185392$12358_Y + attribute \src "libresoc.v:185398.17-185398.117" + wire width 5 $or$libresoc.v:185398$12364_Y + attribute \src "libresoc.v:185404.17-185404.104" + wire $reduce_and$libresoc.v:185404$12370_Y + attribute \src "libresoc.v:185369.18-185369.106" + wire $reduce_or$libresoc.v:185369$12335_Y + attribute \src "libresoc.v:185373.18-185373.113" + wire $reduce_or$libresoc.v:185373$12339_Y + attribute \src "libresoc.v:185374.18-185374.112" + wire $reduce_or$libresoc.v:185374$12340_Y + attribute \src "libresoc.v:185396.18-185396.165" + wire $ternary$libresoc.v:185396$12362_Y + attribute \src "libresoc.v:185397.18-185397.182" + wire width 64 $ternary$libresoc.v:185397$12363_Y + attribute \src "libresoc.v:185399.18-185399.118" + wire width 64 $ternary$libresoc.v:185399$12365_Y + attribute \src "libresoc.v:185400.18-185400.115" + wire width 64 $ternary$libresoc.v:185400$12366_Y + attribute \src "libresoc.v:185401.18-185401.118" + wire width 64 $ternary$libresoc.v:185401$12367_Y + attribute \src "libresoc.v:185402.18-185402.118" + wire $ternary$libresoc.v:185402$12368_Y + attribute \src "libresoc.v:185403.18-185403.118" + wire width 2 $ternary$libresoc.v:185403$12369_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -394901,9 +385446,9 @@ module \shiftrot0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 37 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -394959,7 +385504,7 @@ module \shiftrot0 wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o - attribute \src "libresoc.v:190526.7-190526.15" + attribute \src "libresoc.v:184721.7-184721.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \o_ok @@ -395190,7 +385735,7 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:191157$12615 + cell $and $and$libresoc.v:185352$12318 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -395198,10 +385743,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 - connect \Y $and$libresoc.v:191157$12615_Y + connect \Y $and$libresoc.v:185352$12318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:191158$12616 + cell $and $and$libresoc.v:185353$12319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395209,10 +385754,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:191158$12616_Y + connect \Y $and$libresoc.v:185353$12319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:191159$12617 + cell $and $and$libresoc.v:185354$12320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395220,10 +385765,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:191159$12617_Y + connect \Y $and$libresoc.v:185354$12320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:191160$12618 + cell $and $and$libresoc.v:185355$12321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395231,10 +385776,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:191160$12618_Y + connect \Y $and$libresoc.v:185355$12321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:191161$12619 + cell $and $and$libresoc.v:185356$12322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395242,10 +385787,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:191161$12619_Y + connect \Y $and$libresoc.v:185356$12322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:191162$12620 + cell $and $and$libresoc.v:185357$12323 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -395253,10 +385798,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } - connect \Y $and$libresoc.v:191162$12620_Y + connect \Y $and$libresoc.v:185357$12323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:191163$12621 + cell $and $and$libresoc.v:185358$12324 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -395264,10 +385809,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:191163$12621_Y + connect \Y $and$libresoc.v:185358$12324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:191164$12622 + cell $and $and$libresoc.v:185359$12325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395275,10 +385820,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:191164$12622_Y + connect \Y $and$libresoc.v:185359$12325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:191165$12623 + cell $and $and$libresoc.v:185360$12326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395286,10 +385831,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:191165$12623_Y + connect \Y $and$libresoc.v:185360$12326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:191166$12624 + cell $and $and$libresoc.v:185361$12327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395297,10 +385842,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:191166$12624_Y + connect \Y $and$libresoc.v:185361$12327_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:191168$12626 + cell $and $and$libresoc.v:185363$12329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395308,10 +385853,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:191168$12626_Y + connect \Y $and$libresoc.v:185363$12329_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:191170$12628 + cell $and $and$libresoc.v:185365$12331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395319,10 +385864,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:191170$12628_Y + connect \Y $and$libresoc.v:185365$12331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:191171$12629 + cell $and $and$libresoc.v:185366$12332 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -395330,10 +385875,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:191171$12629_Y + connect \Y $and$libresoc.v:185366$12332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:191173$12631 + cell $and $and$libresoc.v:185368$12334 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -395341,10 +385886,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:191173$12631_Y + connect \Y $and$libresoc.v:185368$12334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:191176$12634 + cell $and $and$libresoc.v:185371$12337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395352,10 +385897,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:191176$12634_Y + connect \Y $and$libresoc.v:185371$12337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:191177$12635 + cell $and $and$libresoc.v:185372$12338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395363,10 +385908,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:191177$12635_Y + connect \Y $and$libresoc.v:185372$12338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:191182$12640 + cell $and $and$libresoc.v:185377$12343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395374,10 +385919,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:191182$12640_Y + connect \Y $and$libresoc.v:185377$12343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:191183$12641 + cell $and $and$libresoc.v:185378$12344 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -395385,10 +385930,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:191183$12641_Y + connect \Y $and$libresoc.v:185378$12344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:191185$12643 + cell $and $and$libresoc.v:185380$12346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395396,10 +385941,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:191185$12643_Y + connect \Y $and$libresoc.v:185380$12346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:191187$12645 + cell $and $and$libresoc.v:185382$12348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395407,10 +385952,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$libresoc.v:191187$12645_Y + connect \Y $and$libresoc.v:185382$12348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:191188$12646 + cell $and $and$libresoc.v:185383$12349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395418,10 +385963,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$libresoc.v:191188$12646_Y + connect \Y $and$libresoc.v:185383$12349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:191189$12647 + cell $and $and$libresoc.v:185384$12350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395429,10 +385974,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:191189$12647_Y + connect \Y $and$libresoc.v:185384$12350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:191195$12653 + cell $and $and$libresoc.v:185390$12356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395440,10 +385985,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:191195$12653_Y + connect \Y $and$libresoc.v:185390$12356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:191196$12654 + cell $and $and$libresoc.v:185391$12357 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -395451,10 +385996,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:191196$12654_Y + connect \Y $and$libresoc.v:185391$12357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:191198$12656 + cell $and $and$libresoc.v:185393$12359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395462,10 +386007,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:191198$12656_Y + connect \Y $and$libresoc.v:185393$12359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:191199$12657 + cell $and $and$libresoc.v:185394$12360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395473,10 +386018,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:191199$12657_Y + connect \Y $and$libresoc.v:185394$12360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:191200$12658 + cell $and $and$libresoc.v:185395$12361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395484,10 +386029,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:191200$12658_Y + connect \Y $and$libresoc.v:185395$12361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:191210$12668 + cell $and $and$libresoc.v:185405$12371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395495,10 +386040,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:191210$12668_Y + connect \Y $and$libresoc.v:185405$12371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:191211$12669 + cell $and $and$libresoc.v:185406$12372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395506,10 +386051,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:191211$12669_Y + connect \Y $and$libresoc.v:185406$12372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:191212$12670 + cell $and $and$libresoc.v:185407$12373 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -395517,10 +386062,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:191212$12670_Y + connect \Y $and$libresoc.v:185407$12373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:191214$12672 + cell $and $and$libresoc.v:185409$12375 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -395528,10 +386073,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:191214$12672_Y + connect \Y $and$libresoc.v:185409$12375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:191184$12642 + cell $eq $eq$libresoc.v:185379$12345 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -395539,10 +386084,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:191184$12642_Y + connect \Y $eq$libresoc.v:185379$12345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:191186$12644 + cell $eq $eq$libresoc.v:185381$12347 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -395550,74 +386095,74 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:191186$12644_Y + connect \Y $eq$libresoc.v:185381$12347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:191156$12614 + cell $not $not$libresoc.v:185351$12317 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:191156$12614_Y + connect \Y $not$libresoc.v:185351$12317_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:191167$12625 + cell $not $not$libresoc.v:185362$12328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:191167$12625_Y + connect \Y $not$libresoc.v:185362$12328_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:191169$12627 + cell $not $not$libresoc.v:185364$12330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:191169$12627_Y + connect \Y $not$libresoc.v:185364$12330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:191172$12630 + cell $not $not$libresoc.v:185367$12333 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:191172$12630_Y + connect \Y $not$libresoc.v:185367$12333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:191175$12633 + cell $not $not$libresoc.v:185370$12336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:191175$12633_Y + connect \Y $not$libresoc.v:185370$12336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:191181$12639 + cell $not $not$libresoc.v:185376$12342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:191181$12639_Y + connect \Y $not$libresoc.v:185376$12342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:191192$12650 + cell $not $not$libresoc.v:185387$12353 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:191192$12650_Y + connect \Y $not$libresoc.v:185387$12353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:191213$12671 + cell $not $not$libresoc.v:185408$12374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:191213$12671_Y + connect \Y $not$libresoc.v:185408$12374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:191180$12638 + cell $or $or$libresoc.v:185375$12341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395625,10 +386170,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:191180$12638_Y + connect \Y $or$libresoc.v:185375$12341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:191190$12648 + cell $or $or$libresoc.v:185385$12351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395636,10 +386181,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:191190$12648_Y + connect \Y $or$libresoc.v:185385$12351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:191191$12649 + cell $or $or$libresoc.v:185386$12352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -395647,10 +386192,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:191191$12649_Y + connect \Y $or$libresoc.v:185386$12352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:191193$12651 + cell $or $or$libresoc.v:185388$12354 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -395658,10 +386203,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:191193$12651_Y + connect \Y $or$libresoc.v:185388$12354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:191194$12652 + cell $or $or$libresoc.v:185389$12355 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -395669,10 +386214,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:191194$12652_Y + connect \Y $or$libresoc.v:185389$12355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:191197$12655 + cell $or $or$libresoc.v:185392$12358 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -395680,10 +386225,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:191197$12655_Y + connect \Y $or$libresoc.v:185392$12358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:191203$12661 + cell $or $or$libresoc.v:185398$12364 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -395691,98 +386236,98 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:191203$12661_Y + connect \Y $or$libresoc.v:185398$12364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:191209$12667 + cell $reduce_and $reduce_and$libresoc.v:185404$12370 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:191209$12667_Y + connect \Y $reduce_and$libresoc.v:185404$12370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:191174$12632 + cell $reduce_or $reduce_or$libresoc.v:185369$12335 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:191174$12632_Y + connect \Y $reduce_or$libresoc.v:185369$12335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:191178$12636 + cell $reduce_or $reduce_or$libresoc.v:185373$12339 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:191178$12636_Y + connect \Y $reduce_or$libresoc.v:185373$12339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:191179$12637 + cell $reduce_or $reduce_or$libresoc.v:185374$12340 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:191179$12637_Y + connect \Y $reduce_or$libresoc.v:185374$12340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:191201$12659 + cell $mux $ternary$libresoc.v:185396$12362 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:191201$12659_Y + connect \Y $ternary$libresoc.v:185396$12362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:191202$12660 + cell $mux $ternary$libresoc.v:185397$12363 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:191202$12660_Y + connect \Y $ternary$libresoc.v:185397$12363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:191204$12662 + cell $mux $ternary$libresoc.v:185399$12365 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:191204$12662_Y + connect \Y $ternary$libresoc.v:185399$12365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:191205$12663 + cell $mux $ternary$libresoc.v:185400$12366 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:191205$12663_Y + connect \Y $ternary$libresoc.v:185400$12366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:191206$12664 + cell $mux $ternary$libresoc.v:185401$12367 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:191206$12664_Y + connect \Y $ternary$libresoc.v:185401$12367_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:191207$12665 + cell $mux $ternary$libresoc.v:185402$12368 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:191207$12665_Y + connect \Y $ternary$libresoc.v:185402$12368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:191208$12666 + cell $mux $ternary$libresoc.v:185403$12369 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:191208$12666_Y + connect \Y $ternary$libresoc.v:185403$12369_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:191301.15-191307.4" + attribute \src "libresoc.v:185496.15-185502.4" cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -395791,7 +386336,7 @@ module \shiftrot0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:191308.18-191343.4" + attribute \src "libresoc.v:185503.18-185538.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -395829,7 +386374,7 @@ module \shiftrot0 connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:191344.16-191350.4" + attribute \src "libresoc.v:185539.16-185545.4" cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -395838,7 +386383,7 @@ module \shiftrot0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:191351.15-191357.4" + attribute \src "libresoc.v:185546.15-185552.4" cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -395847,7 +386392,7 @@ module \shiftrot0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:191358.15-191364.4" + attribute \src "libresoc.v:185553.15-185559.4" cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -395856,7 +386401,7 @@ module \shiftrot0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:191365.15-191371.4" + attribute \src "libresoc.v:185560.15-185566.4" cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -395865,7 +386410,7 @@ module \shiftrot0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:191372.15-191377.4" + attribute \src "libresoc.v:185567.15-185572.4" cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -395873,7 +386418,7 @@ module \shiftrot0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:191378.15-191384.4" + attribute \src "libresoc.v:185573.15-185579.4" cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -395881,667 +386426,667 @@ module \shiftrot0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:190526.7-190526.20" - process $proc$libresoc.v:190526$12839 + attribute \src "libresoc.v:184721.7-184721.20" + process $proc$libresoc.v:184721$12542 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190648.7-190648.24" - process $proc$libresoc.v:190648$12840 + attribute \src "libresoc.v:184843.7-184843.24" + process $proc$libresoc.v:184843$12543 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:190658.7-190658.26" - process $proc$libresoc.v:190658$12841 + attribute \src "libresoc.v:184853.7-184853.26" + process $proc$libresoc.v:184853$12544 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:190666.7-190666.25" - process $proc$libresoc.v:190666$12842 + attribute \src "libresoc.v:184861.7-184861.25" + process $proc$libresoc.v:184861$12545 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:190708.14-190708.54" - process $proc$libresoc.v:190708$12843 + attribute \src "libresoc.v:184903.14-184903.54" + process $proc$libresoc.v:184903$12546 assign { } { } assign $1\alu_shift_rot0_sr_op__fn_unit[12:0] 13'0000000000000 sync always sync init update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[12:0] end - attribute \src "libresoc.v:190712.14-190712.73" - process $proc$libresoc.v:190712$12844 + attribute \src "libresoc.v:184907.14-184907.73" + process $proc$libresoc.v:184907$12547 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:190716.7-190716.48" - process $proc$libresoc.v:190716$12845 + attribute \src "libresoc.v:184911.7-184911.48" + process $proc$libresoc.v:184911$12548 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:190724.13-190724.53" - process $proc$libresoc.v:190724$12846 + attribute \src "libresoc.v:184919.13-184919.53" + process $proc$libresoc.v:184919$12549 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:190728.7-190728.44" - process $proc$libresoc.v:190728$12847 + attribute \src "libresoc.v:184923.7-184923.44" + process $proc$libresoc.v:184923$12550 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:190732.14-190732.48" - process $proc$libresoc.v:190732$12848 + attribute \src "libresoc.v:184927.14-184927.48" + process $proc$libresoc.v:184927$12551 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:190810.13-190810.52" - process $proc$libresoc.v:190810$12849 + attribute \src "libresoc.v:185005.13-185005.52" + process $proc$libresoc.v:185005$12552 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:190814.7-190814.45" - process $proc$libresoc.v:190814$12850 + attribute \src "libresoc.v:185009.7-185009.45" + process $proc$libresoc.v:185009$12553 assign { } { } assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:190818.7-190818.44" - process $proc$libresoc.v:190818$12851 + attribute \src "libresoc.v:185013.7-185013.44" + process $proc$libresoc.v:185013$12554 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:190822.7-190822.45" - process $proc$libresoc.v:190822$12852 + attribute \src "libresoc.v:185017.7-185017.45" + process $proc$libresoc.v:185017$12555 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:190826.7-190826.42" - process $proc$libresoc.v:190826$12853 + attribute \src "libresoc.v:185021.7-185021.42" + process $proc$libresoc.v:185021$12556 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:190830.7-190830.42" - process $proc$libresoc.v:190830$12854 + attribute \src "libresoc.v:185025.7-185025.42" + process $proc$libresoc.v:185025$12557 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:190834.7-190834.48" - process $proc$libresoc.v:190834$12855 + attribute \src "libresoc.v:185029.7-185029.48" + process $proc$libresoc.v:185029$12558 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:190838.7-190838.45" - process $proc$libresoc.v:190838$12856 + attribute \src "libresoc.v:185033.7-185033.45" + process $proc$libresoc.v:185033$12559 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:190842.7-190842.42" - process $proc$libresoc.v:190842$12857 + attribute \src "libresoc.v:185037.7-185037.42" + process $proc$libresoc.v:185037$12560 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:190846.7-190846.42" - process $proc$libresoc.v:190846$12858 + attribute \src "libresoc.v:185041.7-185041.42" + process $proc$libresoc.v:185041$12561 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:190850.7-190850.45" - process $proc$libresoc.v:190850$12859 + attribute \src "libresoc.v:185045.7-185045.45" + process $proc$libresoc.v:185045$12562 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:190862.7-190862.27" - process $proc$libresoc.v:190862$12860 + attribute \src "libresoc.v:185057.7-185057.27" + process $proc$libresoc.v:185057$12563 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:190896.14-190896.47" - process $proc$libresoc.v:190896$12861 + attribute \src "libresoc.v:185091.14-185091.47" + process $proc$libresoc.v:185091$12564 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:190900.7-190900.27" - process $proc$libresoc.v:190900$12862 + attribute \src "libresoc.v:185095.7-185095.27" + process $proc$libresoc.v:185095$12565 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:190904.13-190904.33" - process $proc$libresoc.v:190904$12863 + attribute \src "libresoc.v:185099.13-185099.33" + process $proc$libresoc.v:185099$12566 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:190908.7-190908.30" - process $proc$libresoc.v:190908$12864 + attribute \src "libresoc.v:185103.7-185103.30" + process $proc$libresoc.v:185103$12567 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:190912.13-190912.35" - process $proc$libresoc.v:190912$12865 + attribute \src "libresoc.v:185107.13-185107.35" + process $proc$libresoc.v:185107$12568 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:190916.7-190916.32" - process $proc$libresoc.v:190916$12866 + attribute \src "libresoc.v:185111.7-185111.32" + process $proc$libresoc.v:185111$12569 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:190933.7-190933.25" - process $proc$libresoc.v:190933$12867 + attribute \src "libresoc.v:185128.7-185128.25" + process $proc$libresoc.v:185128$12570 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:190937.7-190937.25" - process $proc$libresoc.v:190937$12868 + attribute \src "libresoc.v:185132.7-185132.25" + process $proc$libresoc.v:185132$12571 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:191067.13-191067.30" - process $proc$libresoc.v:191067$12869 + attribute \src "libresoc.v:185262.13-185262.30" + process $proc$libresoc.v:185262$12572 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:191075.13-191075.31" - process $proc$libresoc.v:191075$12870 + attribute \src "libresoc.v:185270.13-185270.31" + process $proc$libresoc.v:185270$12573 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:191079.13-191079.31" - process $proc$libresoc.v:191079$12871 + attribute \src "libresoc.v:185274.13-185274.31" + process $proc$libresoc.v:185274$12574 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:191091.7-191091.26" - process $proc$libresoc.v:191091$12872 + attribute \src "libresoc.v:185286.7-185286.26" + process $proc$libresoc.v:185286$12575 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:191095.7-191095.26" - process $proc$libresoc.v:191095$12873 + attribute \src "libresoc.v:185290.7-185290.26" + process $proc$libresoc.v:185290$12576 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:191099.7-191099.25" - process $proc$libresoc.v:191099$12874 + attribute \src "libresoc.v:185294.7-185294.25" + process $proc$libresoc.v:185294$12577 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:191103.7-191103.25" - process $proc$libresoc.v:191103$12875 + attribute \src "libresoc.v:185298.7-185298.25" + process $proc$libresoc.v:185298$12578 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:191121.13-191121.32" - process $proc$libresoc.v:191121$12876 + attribute \src "libresoc.v:185316.13-185316.32" + process $proc$libresoc.v:185316$12579 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end - attribute \src "libresoc.v:191125.13-191125.32" - process $proc$libresoc.v:191125$12877 + attribute \src "libresoc.v:185320.13-185320.32" + process $proc$libresoc.v:185320$12580 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end - attribute \src "libresoc.v:191131.14-191131.43" - process $proc$libresoc.v:191131$12878 + attribute \src "libresoc.v:185326.14-185326.43" + process $proc$libresoc.v:185326$12581 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:191135.14-191135.43" - process $proc$libresoc.v:191135$12879 + attribute \src "libresoc.v:185330.14-185330.43" + process $proc$libresoc.v:185330$12582 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:191139.14-191139.43" - process $proc$libresoc.v:191139$12880 + attribute \src "libresoc.v:185334.14-185334.43" + process $proc$libresoc.v:185334$12583 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:191143.7-191143.20" - process $proc$libresoc.v:191143$12881 + attribute \src "libresoc.v:185338.7-185338.20" + process $proc$libresoc.v:185338$12584 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:191147.13-191147.26" - process $proc$libresoc.v:191147$12882 + attribute \src "libresoc.v:185342.13-185342.26" + process $proc$libresoc.v:185342$12585 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:191215.3-191216.39" - process $proc$libresoc.v:191215$12673 + attribute \src "libresoc.v:185410.3-185411.39" + process $proc$libresoc.v:185410$12376 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:191217.3-191218.43" - process $proc$libresoc.v:191217$12674 + attribute \src "libresoc.v:185412.3-185413.43" + process $proc$libresoc.v:185412$12377 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:191219.3-191220.29" - process $proc$libresoc.v:191219$12675 + attribute \src "libresoc.v:185414.3-185415.29" + process $proc$libresoc.v:185414$12378 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:191221.3-191222.29" - process $proc$libresoc.v:191221$12676 + attribute \src "libresoc.v:185416.3-185417.29" + process $proc$libresoc.v:185416$12379 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:191223.3-191224.29" - process $proc$libresoc.v:191223$12677 + attribute \src "libresoc.v:185418.3-185419.29" + process $proc$libresoc.v:185418$12380 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:191225.3-191226.29" - process $proc$libresoc.v:191225$12678 + attribute \src "libresoc.v:185420.3-185421.29" + process $proc$libresoc.v:185420$12381 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:191227.3-191228.29" - process $proc$libresoc.v:191227$12679 + attribute \src "libresoc.v:185422.3-185423.29" + process $proc$libresoc.v:185422$12382 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:191229.3-191230.47" - process $proc$libresoc.v:191229$12680 + attribute \src "libresoc.v:185424.3-185425.47" + process $proc$libresoc.v:185424$12383 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:191231.3-191232.53" - process $proc$libresoc.v:191231$12681 + attribute \src "libresoc.v:185426.3-185427.53" + process $proc$libresoc.v:185426$12384 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:191233.3-191234.43" - process $proc$libresoc.v:191233$12682 + attribute \src "libresoc.v:185428.3-185429.43" + process $proc$libresoc.v:185428$12385 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:191235.3-191236.49" - process $proc$libresoc.v:191235$12683 + attribute \src "libresoc.v:185430.3-185431.49" + process $proc$libresoc.v:185430$12386 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:191237.3-191238.37" - process $proc$libresoc.v:191237$12684 + attribute \src "libresoc.v:185432.3-185433.37" + process $proc$libresoc.v:185432$12387 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:191239.3-191240.43" - process $proc$libresoc.v:191239$12685 + attribute \src "libresoc.v:185434.3-185435.43" + process $proc$libresoc.v:185434$12388 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:191241.3-191242.79" - process $proc$libresoc.v:191241$12686 + attribute \src "libresoc.v:185436.3-185437.79" + process $proc$libresoc.v:185436$12389 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:191243.3-191244.75" - process $proc$libresoc.v:191243$12687 + attribute \src "libresoc.v:185438.3-185439.75" + process $proc$libresoc.v:185438$12390 assign { } { } assign $0\alu_shift_rot0_sr_op__fn_unit[12:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[12:0] end - attribute \src "libresoc.v:191245.3-191246.89" - process $proc$libresoc.v:191245$12688 + attribute \src "libresoc.v:185440.3-185441.89" + process $proc$libresoc.v:185440$12391 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:191247.3-191248.85" - process $proc$libresoc.v:191247$12689 + attribute \src "libresoc.v:185442.3-185443.85" + process $proc$libresoc.v:185442$12392 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:191249.3-191250.73" - process $proc$libresoc.v:191249$12690 + attribute \src "libresoc.v:185444.3-185445.73" + process $proc$libresoc.v:185444$12393 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:191251.3-191252.73" - process $proc$libresoc.v:191251$12691 + attribute \src "libresoc.v:185446.3-185447.73" + process $proc$libresoc.v:185446$12394 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:191253.3-191254.73" - process $proc$libresoc.v:191253$12692 + attribute \src "libresoc.v:185448.3-185449.73" + process $proc$libresoc.v:185448$12395 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:191255.3-191256.73" - process $proc$libresoc.v:191255$12693 + attribute \src "libresoc.v:185450.3-185451.73" + process $proc$libresoc.v:185450$12396 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:191257.3-191258.79" - process $proc$libresoc.v:191257$12694 + attribute \src "libresoc.v:185452.3-185453.79" + process $proc$libresoc.v:185452$12397 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:191259.3-191260.79" - process $proc$libresoc.v:191259$12695 + attribute \src "libresoc.v:185454.3-185455.79" + process $proc$libresoc.v:185454$12398 assign { } { } assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:191261.3-191262.83" - process $proc$libresoc.v:191261$12696 + attribute \src "libresoc.v:185456.3-185457.83" + process $proc$libresoc.v:185456$12399 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:191263.3-191264.85" - process $proc$libresoc.v:191263$12697 + attribute \src "libresoc.v:185458.3-185459.85" + process $proc$libresoc.v:185458$12400 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:191265.3-191266.77" - process $proc$libresoc.v:191265$12698 + attribute \src "libresoc.v:185460.3-185461.77" + process $proc$libresoc.v:185460$12401 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:191267.3-191268.79" - process $proc$libresoc.v:191267$12699 + attribute \src "libresoc.v:185462.3-185463.79" + process $proc$libresoc.v:185462$12402 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:191269.3-191270.77" - process $proc$libresoc.v:191269$12700 + attribute \src "libresoc.v:185464.3-185465.77" + process $proc$libresoc.v:185464$12403 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:191271.3-191272.79" - process $proc$libresoc.v:191271$12701 + attribute \src "libresoc.v:185466.3-185467.79" + process $proc$libresoc.v:185466$12404 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:191273.3-191274.69" - process $proc$libresoc.v:191273$12702 + attribute \src "libresoc.v:185468.3-185469.69" + process $proc$libresoc.v:185468$12405 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:191275.3-191276.39" - process $proc$libresoc.v:191275$12703 + attribute \src "libresoc.v:185470.3-185471.39" + process $proc$libresoc.v:185470$12406 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:191277.3-191278.39" - process $proc$libresoc.v:191277$12704 + attribute \src "libresoc.v:185472.3-185473.39" + process $proc$libresoc.v:185472$12407 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:191279.3-191280.39" - process $proc$libresoc.v:191279$12705 + attribute \src "libresoc.v:185474.3-185475.39" + process $proc$libresoc.v:185474$12408 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end - attribute \src "libresoc.v:191281.3-191282.39" - process $proc$libresoc.v:191281$12706 + attribute \src "libresoc.v:185476.3-185477.39" + process $proc$libresoc.v:185476$12409 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end - attribute \src "libresoc.v:191283.3-191284.39" - process $proc$libresoc.v:191283$12707 + attribute \src "libresoc.v:185478.3-185479.39" + process $proc$libresoc.v:185478$12410 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:191285.3-191286.39" - process $proc$libresoc.v:191285$12708 + attribute \src "libresoc.v:185480.3-185481.39" + process $proc$libresoc.v:185480$12411 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:191287.3-191288.39" - process $proc$libresoc.v:191287$12709 + attribute \src "libresoc.v:185482.3-185483.39" + process $proc$libresoc.v:185482$12412 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:191289.3-191290.39" - process $proc$libresoc.v:191289$12710 + attribute \src "libresoc.v:185484.3-185485.39" + process $proc$libresoc.v:185484$12413 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:191291.3-191292.41" - process $proc$libresoc.v:191291$12711 + attribute \src "libresoc.v:185486.3-185487.41" + process $proc$libresoc.v:185486$12414 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:191293.3-191294.41" - process $proc$libresoc.v:191293$12712 + attribute \src "libresoc.v:185488.3-185489.41" + process $proc$libresoc.v:185488$12415 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:191295.3-191296.37" - process $proc$libresoc.v:191295$12713 + attribute \src "libresoc.v:185490.3-185491.37" + process $proc$libresoc.v:185490$12416 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:191297.3-191298.46" - process $proc$libresoc.v:191297$12714 + attribute \src "libresoc.v:185492.3-185493.46" + process $proc$libresoc.v:185492$12417 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:191299.3-191300.25" - process $proc$libresoc.v:191299$12715 + attribute \src "libresoc.v:185494.3-185495.25" + process $proc$libresoc.v:185494$12418 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:191385.3-191394.6" - process $proc$libresoc.v:191385$12716 + attribute \src "libresoc.v:185580.3-185589.6" + process $proc$libresoc.v:185580$12419 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:191386.5-191386.29" + attribute \src "libresoc.v:185581.5-185581.29" switch \initial - attribute \src "libresoc.v:191386.9-191386.17" + attribute \src "libresoc.v:185581.9-185581.17" case 1'1 case end @@ -396557,14 +387102,14 @@ module \shiftrot0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:191395.3-191403.6" - process $proc$libresoc.v:191395$12717 + attribute \src "libresoc.v:185590.3-185598.6" + process $proc$libresoc.v:185590$12420 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12718 $1\rok_l_s_rdok$next[0:0]$12719 - attribute \src "libresoc.v:191396.5-191396.29" + assign $0\rok_l_s_rdok$next[0:0]$12421 $1\rok_l_s_rdok$next[0:0]$12422 + attribute \src "libresoc.v:185591.5-185591.29" switch \initial - attribute \src "libresoc.v:191396.9-191396.17" + attribute \src "libresoc.v:185591.9-185591.17" case 1'1 case end @@ -396573,21 +387118,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12719 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12422 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12719 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12422 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12718 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12421 end - attribute \src "libresoc.v:191404.3-191412.6" - process $proc$libresoc.v:191404$12720 + attribute \src "libresoc.v:185599.3-185607.6" + process $proc$libresoc.v:185599$12423 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12721 $1\rok_l_r_rdok$next[0:0]$12722 - attribute \src "libresoc.v:191405.5-191405.29" + assign $0\rok_l_r_rdok$next[0:0]$12424 $1\rok_l_r_rdok$next[0:0]$12425 + attribute \src "libresoc.v:185600.5-185600.29" switch \initial - attribute \src "libresoc.v:191405.9-191405.17" + attribute \src "libresoc.v:185600.9-185600.17" case 1'1 case end @@ -396596,21 +387141,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12722 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12425 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12722 \$64 + assign $1\rok_l_r_rdok$next[0:0]$12425 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12721 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12424 end - attribute \src "libresoc.v:191413.3-191421.6" - process $proc$libresoc.v:191413$12723 + attribute \src "libresoc.v:185608.3-185616.6" + process $proc$libresoc.v:185608$12426 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12724 $1\rst_l_s_rst$next[0:0]$12725 - attribute \src "libresoc.v:191414.5-191414.29" + assign $0\rst_l_s_rst$next[0:0]$12427 $1\rst_l_s_rst$next[0:0]$12428 + attribute \src "libresoc.v:185609.5-185609.29" switch \initial - attribute \src "libresoc.v:191414.9-191414.17" + attribute \src "libresoc.v:185609.9-185609.17" case 1'1 case end @@ -396619,21 +387164,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12725 1'0 + assign $1\rst_l_s_rst$next[0:0]$12428 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12725 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12428 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12724 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12427 end - attribute \src "libresoc.v:191422.3-191430.6" - process $proc$libresoc.v:191422$12726 + attribute \src "libresoc.v:185617.3-185625.6" + process $proc$libresoc.v:185617$12429 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12727 $1\rst_l_r_rst$next[0:0]$12728 - attribute \src "libresoc.v:191423.5-191423.29" + assign $0\rst_l_r_rst$next[0:0]$12430 $1\rst_l_r_rst$next[0:0]$12431 + attribute \src "libresoc.v:185618.5-185618.29" switch \initial - attribute \src "libresoc.v:191423.9-191423.17" + attribute \src "libresoc.v:185618.9-185618.17" case 1'1 case end @@ -396642,21 +387187,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12728 1'1 + assign $1\rst_l_r_rst$next[0:0]$12431 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12728 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12431 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12727 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12430 end - attribute \src "libresoc.v:191431.3-191439.6" - process $proc$libresoc.v:191431$12729 + attribute \src "libresoc.v:185626.3-185634.6" + process $proc$libresoc.v:185626$12432 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12730 $1\opc_l_s_opc$next[0:0]$12731 - attribute \src "libresoc.v:191432.5-191432.29" + assign $0\opc_l_s_opc$next[0:0]$12433 $1\opc_l_s_opc$next[0:0]$12434 + attribute \src "libresoc.v:185627.5-185627.29" switch \initial - attribute \src "libresoc.v:191432.9-191432.17" + attribute \src "libresoc.v:185627.9-185627.17" case 1'1 case end @@ -396665,21 +387210,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12731 1'0 + assign $1\opc_l_s_opc$next[0:0]$12434 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12731 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12434 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12730 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12433 end - attribute \src "libresoc.v:191440.3-191448.6" - process $proc$libresoc.v:191440$12732 + attribute \src "libresoc.v:185635.3-185643.6" + process $proc$libresoc.v:185635$12435 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12733 $1\opc_l_r_opc$next[0:0]$12734 - attribute \src "libresoc.v:191441.5-191441.29" + assign $0\opc_l_r_opc$next[0:0]$12436 $1\opc_l_r_opc$next[0:0]$12437 + attribute \src "libresoc.v:185636.5-185636.29" switch \initial - attribute \src "libresoc.v:191441.9-191441.17" + attribute \src "libresoc.v:185636.9-185636.17" case 1'1 case end @@ -396688,21 +387233,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12734 1'1 + assign $1\opc_l_r_opc$next[0:0]$12437 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12734 \req_done + assign $1\opc_l_r_opc$next[0:0]$12437 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12733 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12436 end - attribute \src "libresoc.v:191449.3-191457.6" - process $proc$libresoc.v:191449$12735 + attribute \src "libresoc.v:185644.3-185652.6" + process $proc$libresoc.v:185644$12438 assign { } { } assign { } { } - assign $0\src_l_s_src$next[4:0]$12736 $1\src_l_s_src$next[4:0]$12737 - attribute \src "libresoc.v:191450.5-191450.29" + assign $0\src_l_s_src$next[4:0]$12439 $1\src_l_s_src$next[4:0]$12440 + attribute \src "libresoc.v:185645.5-185645.29" switch \initial - attribute \src "libresoc.v:191450.9-191450.17" + attribute \src "libresoc.v:185645.9-185645.17" case 1'1 case end @@ -396711,21 +387256,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[4:0]$12737 5'00000 + assign $1\src_l_s_src$next[4:0]$12440 5'00000 case - assign $1\src_l_s_src$next[4:0]$12737 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[4:0]$12440 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12736 + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12439 end - attribute \src "libresoc.v:191458.3-191466.6" - process $proc$libresoc.v:191458$12738 + attribute \src "libresoc.v:185653.3-185661.6" + process $proc$libresoc.v:185653$12441 assign { } { } assign { } { } - assign $0\src_l_r_src$next[4:0]$12739 $1\src_l_r_src$next[4:0]$12740 - attribute \src "libresoc.v:191459.5-191459.29" + assign $0\src_l_r_src$next[4:0]$12442 $1\src_l_r_src$next[4:0]$12443 + attribute \src "libresoc.v:185654.5-185654.29" switch \initial - attribute \src "libresoc.v:191459.9-191459.17" + attribute \src "libresoc.v:185654.9-185654.17" case 1'1 case end @@ -396734,21 +387279,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[4:0]$12740 5'11111 + assign $1\src_l_r_src$next[4:0]$12443 5'11111 case - assign $1\src_l_r_src$next[4:0]$12740 \reset_r + assign $1\src_l_r_src$next[4:0]$12443 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12739 + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12442 end - attribute \src "libresoc.v:191467.3-191475.6" - process $proc$libresoc.v:191467$12741 + attribute \src "libresoc.v:185662.3-185670.6" + process $proc$libresoc.v:185662$12444 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$12742 $1\req_l_s_req$next[2:0]$12743 - attribute \src "libresoc.v:191468.5-191468.29" + assign $0\req_l_s_req$next[2:0]$12445 $1\req_l_s_req$next[2:0]$12446 + attribute \src "libresoc.v:185663.5-185663.29" switch \initial - attribute \src "libresoc.v:191468.9-191468.17" + attribute \src "libresoc.v:185663.9-185663.17" case 1'1 case end @@ -396757,21 +387302,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$12743 3'000 + assign $1\req_l_s_req$next[2:0]$12446 3'000 case - assign $1\req_l_s_req$next[2:0]$12743 \$66 + assign $1\req_l_s_req$next[2:0]$12446 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12742 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12445 end - attribute \src "libresoc.v:191476.3-191484.6" - process $proc$libresoc.v:191476$12744 + attribute \src "libresoc.v:185671.3-185679.6" + process $proc$libresoc.v:185671$12447 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$12745 $1\req_l_r_req$next[2:0]$12746 - attribute \src "libresoc.v:191477.5-191477.29" + assign $0\req_l_r_req$next[2:0]$12448 $1\req_l_r_req$next[2:0]$12449 + attribute \src "libresoc.v:185672.5-185672.29" switch \initial - attribute \src "libresoc.v:191477.9-191477.17" + attribute \src "libresoc.v:185672.9-185672.17" case 1'1 case end @@ -396780,15 +387325,15 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$12746 3'111 + assign $1\req_l_r_req$next[2:0]$12449 3'111 case - assign $1\req_l_r_req$next[2:0]$12746 \$68 + assign $1\req_l_r_req$next[2:0]$12449 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12745 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12448 end - attribute \src "libresoc.v:191485.3-191522.6" - process $proc$libresoc.v:191485$12747 + attribute \src "libresoc.v:185680.3-185717.6" + process $proc$libresoc.v:185680$12450 assign { } { } assign { } { } assign { } { } @@ -396823,32 +387368,32 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12748 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12765 + assign $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12451 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12468 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12751 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12768 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12752 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12769 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12753 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12770 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12754 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12771 - assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12755 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12772 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12756 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12773 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12757 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12774 + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12454 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12471 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12455 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12472 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12456 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12473 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12457 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12474 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12458 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12475 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12459 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12476 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12460 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12477 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12760 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12777 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12761 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12778 + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12463 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12480 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12464 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12481 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12764 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12781 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12749 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12782 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12750 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12783 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12758 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12784 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12759 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12785 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12762 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12786 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12763 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12787 - attribute \src "libresoc.v:191486.5-191486.29" + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12467 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12484 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12452 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12485 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12453 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12486 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12461 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12487 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12462 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12488 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12465 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12489 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12466 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12490 + attribute \src "libresoc.v:185681.5-185681.29" switch \initial - attribute \src "libresoc.v:191486.9-191486.17" + attribute \src "libresoc.v:185681.9-185681.17" case 1'1 case end @@ -396873,25 +387418,25 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12770 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12774 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12773 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12778 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12769 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12777 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12768 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12772 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12781 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12776 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12775 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12779 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12780 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12767 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12766 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12765 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12771 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12473 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12477 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12476 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12481 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12472 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12480 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12471 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12475 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12484 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12479 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12478 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12482 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12483 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12470 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12469 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12468 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12474 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12765 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12766 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12767 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12768 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12769 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12770 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12771 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12772 \alu_shift_rot0_sr_op__invert_in - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12773 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12774 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12775 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12776 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12777 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12778 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12779 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12780 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12781 \alu_shift_rot0_sr_op__write_cr0 + assign $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12468 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12469 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12470 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12471 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12472 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12473 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12474 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12475 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12476 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12477 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12478 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12479 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12480 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12481 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12482 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12483 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12484 \alu_shift_rot0_sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -396903,53 +387448,53 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12782 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12783 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12787 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12786 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12784 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12785 1'0 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12485 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12486 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12490 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12489 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12487 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12488 1'0 case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12782 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12766 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12783 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12767 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12784 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12775 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12785 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12776 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12786 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12779 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12787 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12780 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12485 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12469 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12486 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12470 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12487 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12478 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12488 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12479 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12489 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12482 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12490 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12483 end sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12748 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12749 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12750 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12751 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12752 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12753 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12754 - update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12755 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12756 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12757 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12758 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12759 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12760 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12761 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12762 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12763 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12764 + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12451 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12452 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12453 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12454 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12455 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12456 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12457 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12458 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12459 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12460 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12461 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12462 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12463 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12464 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12465 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12466 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12467 end - attribute \src "libresoc.v:191523.3-191544.6" - process $proc$libresoc.v:191523$12788 + attribute \src "libresoc.v:185718.3-185739.6" + process $proc$libresoc.v:185718$12491 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12789 $2\data_r0__o$next[63:0]$12793 + assign $0\data_r0__o$next[63:0]$12492 $2\data_r0__o$next[63:0]$12496 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12790 $3\data_r0__o_ok$next[0:0]$12795 - attribute \src "libresoc.v:191524.5-191524.29" + assign $0\data_r0__o_ok$next[0:0]$12493 $3\data_r0__o_ok$next[0:0]$12498 + attribute \src "libresoc.v:185719.5-185719.29" switch \initial - attribute \src "libresoc.v:191524.9-191524.17" + attribute \src "libresoc.v:185719.9-185719.17" case 1'1 case end @@ -396959,10 +387504,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12792 $1\data_r0__o$next[63:0]$12791 } { \o_ok \alu_shift_rot0_o } + assign { $1\data_r0__o_ok$next[0:0]$12495 $1\data_r0__o$next[63:0]$12494 } { \o_ok \alu_shift_rot0_o } case - assign $1\data_r0__o$next[63:0]$12791 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12792 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12494 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12495 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -396970,38 +387515,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12794 $2\data_r0__o$next[63:0]$12793 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12497 $2\data_r0__o$next[63:0]$12496 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12793 $1\data_r0__o$next[63:0]$12791 - assign $2\data_r0__o_ok$next[0:0]$12794 $1\data_r0__o_ok$next[0:0]$12792 + assign $2\data_r0__o$next[63:0]$12496 $1\data_r0__o$next[63:0]$12494 + assign $2\data_r0__o_ok$next[0:0]$12497 $1\data_r0__o_ok$next[0:0]$12495 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12795 1'0 + assign $3\data_r0__o_ok$next[0:0]$12498 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12795 $2\data_r0__o_ok$next[0:0]$12794 + assign $3\data_r0__o_ok$next[0:0]$12498 $2\data_r0__o_ok$next[0:0]$12497 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12789 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12790 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12492 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12493 end - attribute \src "libresoc.v:191545.3-191566.6" - process $proc$libresoc.v:191545$12796 + attribute \src "libresoc.v:185740.3-185761.6" + process $proc$libresoc.v:185740$12499 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$12797 $2\data_r1__cr_a$next[3:0]$12801 + assign $0\data_r1__cr_a$next[3:0]$12500 $2\data_r1__cr_a$next[3:0]$12504 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$12798 $3\data_r1__cr_a_ok$next[0:0]$12803 - attribute \src "libresoc.v:191546.5-191546.29" + assign $0\data_r1__cr_a_ok$next[0:0]$12501 $3\data_r1__cr_a_ok$next[0:0]$12506 + attribute \src "libresoc.v:185741.5-185741.29" switch \initial - attribute \src "libresoc.v:191546.9-191546.17" + attribute \src "libresoc.v:185741.9-185741.17" case 1'1 case end @@ -397011,10 +387556,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$12800 $1\data_r1__cr_a$next[3:0]$12799 } { \cr_a_ok \alu_shift_rot0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$12503 $1\data_r1__cr_a$next[3:0]$12502 } { \cr_a_ok \alu_shift_rot0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$12799 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$12800 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$12502 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12503 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -397022,38 +387567,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$12802 $2\data_r1__cr_a$next[3:0]$12801 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$12505 $2\data_r1__cr_a$next[3:0]$12504 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$12801 $1\data_r1__cr_a$next[3:0]$12799 - assign $2\data_r1__cr_a_ok$next[0:0]$12802 $1\data_r1__cr_a_ok$next[0:0]$12800 + assign $2\data_r1__cr_a$next[3:0]$12504 $1\data_r1__cr_a$next[3:0]$12502 + assign $2\data_r1__cr_a_ok$next[0:0]$12505 $1\data_r1__cr_a_ok$next[0:0]$12503 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$12803 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$12506 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$12803 $2\data_r1__cr_a_ok$next[0:0]$12802 + assign $3\data_r1__cr_a_ok$next[0:0]$12506 $2\data_r1__cr_a_ok$next[0:0]$12505 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12797 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12798 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12500 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12501 end - attribute \src "libresoc.v:191567.3-191588.6" - process $proc$libresoc.v:191567$12804 + attribute \src "libresoc.v:185762.3-185783.6" + process $proc$libresoc.v:185762$12507 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$12805 $2\data_r2__xer_ca$next[1:0]$12809 + assign $0\data_r2__xer_ca$next[1:0]$12508 $2\data_r2__xer_ca$next[1:0]$12512 assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$12806 $3\data_r2__xer_ca_ok$next[0:0]$12811 - attribute \src "libresoc.v:191568.5-191568.29" + assign $0\data_r2__xer_ca_ok$next[0:0]$12509 $3\data_r2__xer_ca_ok$next[0:0]$12514 + attribute \src "libresoc.v:185763.5-185763.29" switch \initial - attribute \src "libresoc.v:191568.9-191568.17" + attribute \src "libresoc.v:185763.9-185763.17" case 1'1 case end @@ -397063,10 +387608,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$12808 $1\data_r2__xer_ca$next[1:0]$12807 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12511 $1\data_r2__xer_ca$next[1:0]$12510 } { \xer_ca_ok \alu_shift_rot0_xer_ca } case - assign $1\data_r2__xer_ca$next[1:0]$12807 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$12808 \data_r2__xer_ca_ok + assign $1\data_r2__xer_ca$next[1:0]$12510 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12511 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -397074,32 +387619,32 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$12810 $2\data_r2__xer_ca$next[1:0]$12809 } 3'000 + assign { $2\data_r2__xer_ca_ok$next[0:0]$12513 $2\data_r2__xer_ca$next[1:0]$12512 } 3'000 case - assign $2\data_r2__xer_ca$next[1:0]$12809 $1\data_r2__xer_ca$next[1:0]$12807 - assign $2\data_r2__xer_ca_ok$next[0:0]$12810 $1\data_r2__xer_ca_ok$next[0:0]$12808 + assign $2\data_r2__xer_ca$next[1:0]$12512 $1\data_r2__xer_ca$next[1:0]$12510 + assign $2\data_r2__xer_ca_ok$next[0:0]$12513 $1\data_r2__xer_ca_ok$next[0:0]$12511 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$12811 1'0 + assign $3\data_r2__xer_ca_ok$next[0:0]$12514 1'0 case - assign $3\data_r2__xer_ca_ok$next[0:0]$12811 $2\data_r2__xer_ca_ok$next[0:0]$12810 + assign $3\data_r2__xer_ca_ok$next[0:0]$12514 $2\data_r2__xer_ca_ok$next[0:0]$12513 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12805 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12806 + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12508 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12509 end - attribute \src "libresoc.v:191589.3-191598.6" - process $proc$libresoc.v:191589$12812 + attribute \src "libresoc.v:185784.3-185793.6" + process $proc$libresoc.v:185784$12515 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12813 $1\src_r0$next[63:0]$12814 - attribute \src "libresoc.v:191590.5-191590.29" + assign $0\src_r0$next[63:0]$12516 $1\src_r0$next[63:0]$12517 + attribute \src "libresoc.v:185785.5-185785.29" switch \initial - attribute \src "libresoc.v:191590.9-191590.17" + attribute \src "libresoc.v:185785.9-185785.17" case 1'1 case end @@ -397108,21 +387653,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12814 \src1_i + assign $1\src_r0$next[63:0]$12517 \src1_i case - assign $1\src_r0$next[63:0]$12814 \src_r0 + assign $1\src_r0$next[63:0]$12517 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12813 + update \src_r0$next $0\src_r0$next[63:0]$12516 end - attribute \src "libresoc.v:191599.3-191608.6" - process $proc$libresoc.v:191599$12815 + attribute \src "libresoc.v:185794.3-185803.6" + process $proc$libresoc.v:185794$12518 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12816 $1\src_r1$next[63:0]$12817 - attribute \src "libresoc.v:191600.5-191600.29" + assign $0\src_r1$next[63:0]$12519 $1\src_r1$next[63:0]$12520 + attribute \src "libresoc.v:185795.5-185795.29" switch \initial - attribute \src "libresoc.v:191600.9-191600.17" + attribute \src "libresoc.v:185795.9-185795.17" case 1'1 case end @@ -397131,21 +387676,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12817 \src_or_imm + assign $1\src_r1$next[63:0]$12520 \src_or_imm case - assign $1\src_r1$next[63:0]$12817 \src_r1 + assign $1\src_r1$next[63:0]$12520 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12816 + update \src_r1$next $0\src_r1$next[63:0]$12519 end - attribute \src "libresoc.v:191609.3-191618.6" - process $proc$libresoc.v:191609$12818 + attribute \src "libresoc.v:185804.3-185813.6" + process $proc$libresoc.v:185804$12521 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12819 $1\src_r2$next[63:0]$12820 - attribute \src "libresoc.v:191610.5-191610.29" + assign $0\src_r2$next[63:0]$12522 $1\src_r2$next[63:0]$12523 + attribute \src "libresoc.v:185805.5-185805.29" switch \initial - attribute \src "libresoc.v:191610.9-191610.17" + attribute \src "libresoc.v:185805.9-185805.17" case 1'1 case end @@ -397154,21 +387699,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12820 \src3_i + assign $1\src_r2$next[63:0]$12523 \src3_i case - assign $1\src_r2$next[63:0]$12820 \src_r2 + assign $1\src_r2$next[63:0]$12523 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12819 + update \src_r2$next $0\src_r2$next[63:0]$12522 end - attribute \src "libresoc.v:191619.3-191628.6" - process $proc$libresoc.v:191619$12821 + attribute \src "libresoc.v:185814.3-185823.6" + process $proc$libresoc.v:185814$12524 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12822 $1\src_r3$next[0:0]$12823 - attribute \src "libresoc.v:191620.5-191620.29" + assign $0\src_r3$next[0:0]$12525 $1\src_r3$next[0:0]$12526 + attribute \src "libresoc.v:185815.5-185815.29" switch \initial - attribute \src "libresoc.v:191620.9-191620.17" + attribute \src "libresoc.v:185815.9-185815.17" case 1'1 case end @@ -397177,21 +387722,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12823 \src4_i + assign $1\src_r3$next[0:0]$12526 \src4_i case - assign $1\src_r3$next[0:0]$12823 \src_r3 + assign $1\src_r3$next[0:0]$12526 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12822 + update \src_r3$next $0\src_r3$next[0:0]$12525 end - attribute \src "libresoc.v:191629.3-191638.6" - process $proc$libresoc.v:191629$12824 + attribute \src "libresoc.v:185824.3-185833.6" + process $proc$libresoc.v:185824$12527 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12825 $1\src_r4$next[1:0]$12826 - attribute \src "libresoc.v:191630.5-191630.29" + assign $0\src_r4$next[1:0]$12528 $1\src_r4$next[1:0]$12529 + attribute \src "libresoc.v:185825.5-185825.29" switch \initial - attribute \src "libresoc.v:191630.9-191630.17" + attribute \src "libresoc.v:185825.9-185825.17" case 1'1 case end @@ -397200,21 +387745,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12826 \src5_i + assign $1\src_r4$next[1:0]$12529 \src5_i case - assign $1\src_r4$next[1:0]$12826 \src_r4 + assign $1\src_r4$next[1:0]$12529 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12825 + update \src_r4$next $0\src_r4$next[1:0]$12528 end - attribute \src "libresoc.v:191639.3-191647.6" - process $proc$libresoc.v:191639$12827 + attribute \src "libresoc.v:185834.3-185842.6" + process $proc$libresoc.v:185834$12530 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12828 $1\alui_l_r_alui$next[0:0]$12829 - attribute \src "libresoc.v:191640.5-191640.29" + assign $0\alui_l_r_alui$next[0:0]$12531 $1\alui_l_r_alui$next[0:0]$12532 + attribute \src "libresoc.v:185835.5-185835.29" switch \initial - attribute \src "libresoc.v:191640.9-191640.17" + attribute \src "libresoc.v:185835.9-185835.17" case 1'1 case end @@ -397223,21 +387768,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12829 1'1 + assign $1\alui_l_r_alui$next[0:0]$12532 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12829 \$90 + assign $1\alui_l_r_alui$next[0:0]$12532 \$90 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12828 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12531 end - attribute \src "libresoc.v:191648.3-191656.6" - process $proc$libresoc.v:191648$12830 + attribute \src "libresoc.v:185843.3-185851.6" + process $proc$libresoc.v:185843$12533 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12831 $1\alu_l_r_alu$next[0:0]$12832 - attribute \src "libresoc.v:191649.5-191649.29" + assign $0\alu_l_r_alu$next[0:0]$12534 $1\alu_l_r_alu$next[0:0]$12535 + attribute \src "libresoc.v:185844.5-185844.29" switch \initial - attribute \src "libresoc.v:191649.9-191649.17" + attribute \src "libresoc.v:185844.9-185844.17" case 1'1 case end @@ -397246,21 +387791,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12832 1'1 + assign $1\alu_l_r_alu$next[0:0]$12535 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12832 \$92 + assign $1\alu_l_r_alu$next[0:0]$12535 \$92 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12831 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12534 end - attribute \src "libresoc.v:191657.3-191666.6" - process $proc$libresoc.v:191657$12833 + attribute \src "libresoc.v:185852.3-185861.6" + process $proc$libresoc.v:185852$12536 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:191658.5-191658.29" + attribute \src "libresoc.v:185853.5-185853.29" switch \initial - attribute \src "libresoc.v:191658.9-191658.17" + attribute \src "libresoc.v:185853.9-185853.17" case 1'1 case end @@ -397276,14 +387821,14 @@ module \shiftrot0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:191667.3-191676.6" - process $proc$libresoc.v:191667$12834 + attribute \src "libresoc.v:185862.3-185871.6" + process $proc$libresoc.v:185862$12537 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:191668.5-191668.29" + attribute \src "libresoc.v:185863.5-185863.29" switch \initial - attribute \src "libresoc.v:191668.9-191668.17" + attribute \src "libresoc.v:185863.9-185863.17" case 1'1 case end @@ -397299,14 +387844,14 @@ module \shiftrot0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:191677.3-191686.6" - process $proc$libresoc.v:191677$12835 + attribute \src "libresoc.v:185872.3-185881.6" + process $proc$libresoc.v:185872$12538 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:191678.5-191678.29" + attribute \src "libresoc.v:185873.5-185873.29" switch \initial - attribute \src "libresoc.v:191678.9-191678.17" + attribute \src "libresoc.v:185873.9-185873.17" case 1'1 case end @@ -397322,14 +387867,14 @@ module \shiftrot0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:191687.3-191695.6" - process $proc$libresoc.v:191687$12836 + attribute \src "libresoc.v:185882.3-185890.6" + process $proc$libresoc.v:185882$12539 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$12837 $1\prev_wr_go$next[2:0]$12838 - attribute \src "libresoc.v:191688.5-191688.29" + assign $0\prev_wr_go$next[2:0]$12540 $1\prev_wr_go$next[2:0]$12541 + attribute \src "libresoc.v:185883.5-185883.29" switch \initial - attribute \src "libresoc.v:191688.9-191688.17" + attribute \src "libresoc.v:185883.9-185883.17" case 1'1 case end @@ -397338,72 +387883,72 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$12838 3'000 - case - assign $1\prev_wr_go$next[2:0]$12838 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12837 - end - connect \$100 $not$libresoc.v:191156$12614_Y - connect \$102 $and$libresoc.v:191157$12615_Y - connect \$104 $and$libresoc.v:191158$12616_Y - connect \$106 $and$libresoc.v:191159$12617_Y - connect \$108 $and$libresoc.v:191160$12618_Y - connect \$10 $and$libresoc.v:191161$12619_Y - connect \$110 $and$libresoc.v:191162$12620_Y - connect \$112 $and$libresoc.v:191163$12621_Y - connect \$114 $and$libresoc.v:191164$12622_Y - connect \$116 $and$libresoc.v:191165$12623_Y - connect \$118 $and$libresoc.v:191166$12624_Y - connect \$12 $not$libresoc.v:191167$12625_Y - connect \$14 $and$libresoc.v:191168$12626_Y - connect \$16 $not$libresoc.v:191169$12627_Y - connect \$18 $and$libresoc.v:191170$12628_Y - connect \$20 $and$libresoc.v:191171$12629_Y - connect \$24 $not$libresoc.v:191172$12630_Y - connect \$26 $and$libresoc.v:191173$12631_Y - connect \$23 $reduce_or$libresoc.v:191174$12632_Y - connect \$22 $not$libresoc.v:191175$12633_Y - connect \$2 $and$libresoc.v:191176$12634_Y - connect \$30 $and$libresoc.v:191177$12635_Y - connect \$32 $reduce_or$libresoc.v:191178$12636_Y - connect \$34 $reduce_or$libresoc.v:191179$12637_Y - connect \$36 $or$libresoc.v:191180$12638_Y - connect \$38 $not$libresoc.v:191181$12639_Y - connect \$40 $and$libresoc.v:191182$12640_Y - connect \$42 $and$libresoc.v:191183$12641_Y - connect \$44 $eq$libresoc.v:191184$12642_Y - connect \$46 $and$libresoc.v:191185$12643_Y - connect \$48 $eq$libresoc.v:191186$12644_Y - connect \$50 $and$libresoc.v:191187$12645_Y - connect \$52 $and$libresoc.v:191188$12646_Y - connect \$54 $and$libresoc.v:191189$12647_Y - connect \$56 $or$libresoc.v:191190$12648_Y - connect \$58 $or$libresoc.v:191191$12649_Y - connect \$5 $not$libresoc.v:191192$12650_Y - connect \$60 $or$libresoc.v:191193$12651_Y - connect \$62 $or$libresoc.v:191194$12652_Y - connect \$64 $and$libresoc.v:191195$12653_Y - connect \$66 $and$libresoc.v:191196$12654_Y - connect \$68 $or$libresoc.v:191197$12655_Y - connect \$70 $and$libresoc.v:191198$12656_Y - connect \$72 $and$libresoc.v:191199$12657_Y - connect \$74 $and$libresoc.v:191200$12658_Y - connect \$76 $ternary$libresoc.v:191201$12659_Y - connect \$78 $ternary$libresoc.v:191202$12660_Y - connect \$7 $or$libresoc.v:191203$12661_Y - connect \$80 $ternary$libresoc.v:191204$12662_Y - connect \$82 $ternary$libresoc.v:191205$12663_Y - connect \$84 $ternary$libresoc.v:191206$12664_Y - connect \$86 $ternary$libresoc.v:191207$12665_Y - connect \$88 $ternary$libresoc.v:191208$12666_Y - connect \$4 $reduce_and$libresoc.v:191209$12667_Y - connect \$90 $and$libresoc.v:191210$12668_Y - connect \$92 $and$libresoc.v:191211$12669_Y - connect \$94 $and$libresoc.v:191212$12670_Y - connect \$96 $not$libresoc.v:191213$12671_Y - connect \$98 $and$libresoc.v:191214$12672_Y + assign $1\prev_wr_go$next[2:0]$12541 3'000 + case + assign $1\prev_wr_go$next[2:0]$12541 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12540 + end + connect \$100 $not$libresoc.v:185351$12317_Y + connect \$102 $and$libresoc.v:185352$12318_Y + connect \$104 $and$libresoc.v:185353$12319_Y + connect \$106 $and$libresoc.v:185354$12320_Y + connect \$108 $and$libresoc.v:185355$12321_Y + connect \$10 $and$libresoc.v:185356$12322_Y + connect \$110 $and$libresoc.v:185357$12323_Y + connect \$112 $and$libresoc.v:185358$12324_Y + connect \$114 $and$libresoc.v:185359$12325_Y + connect \$116 $and$libresoc.v:185360$12326_Y + connect \$118 $and$libresoc.v:185361$12327_Y + connect \$12 $not$libresoc.v:185362$12328_Y + connect \$14 $and$libresoc.v:185363$12329_Y + connect \$16 $not$libresoc.v:185364$12330_Y + connect \$18 $and$libresoc.v:185365$12331_Y + connect \$20 $and$libresoc.v:185366$12332_Y + connect \$24 $not$libresoc.v:185367$12333_Y + connect \$26 $and$libresoc.v:185368$12334_Y + connect \$23 $reduce_or$libresoc.v:185369$12335_Y + connect \$22 $not$libresoc.v:185370$12336_Y + connect \$2 $and$libresoc.v:185371$12337_Y + connect \$30 $and$libresoc.v:185372$12338_Y + connect \$32 $reduce_or$libresoc.v:185373$12339_Y + connect \$34 $reduce_or$libresoc.v:185374$12340_Y + connect \$36 $or$libresoc.v:185375$12341_Y + connect \$38 $not$libresoc.v:185376$12342_Y + connect \$40 $and$libresoc.v:185377$12343_Y + connect \$42 $and$libresoc.v:185378$12344_Y + connect \$44 $eq$libresoc.v:185379$12345_Y + connect \$46 $and$libresoc.v:185380$12346_Y + connect \$48 $eq$libresoc.v:185381$12347_Y + connect \$50 $and$libresoc.v:185382$12348_Y + connect \$52 $and$libresoc.v:185383$12349_Y + connect \$54 $and$libresoc.v:185384$12350_Y + connect \$56 $or$libresoc.v:185385$12351_Y + connect \$58 $or$libresoc.v:185386$12352_Y + connect \$5 $not$libresoc.v:185387$12353_Y + connect \$60 $or$libresoc.v:185388$12354_Y + connect \$62 $or$libresoc.v:185389$12355_Y + connect \$64 $and$libresoc.v:185390$12356_Y + connect \$66 $and$libresoc.v:185391$12357_Y + connect \$68 $or$libresoc.v:185392$12358_Y + connect \$70 $and$libresoc.v:185393$12359_Y + connect \$72 $and$libresoc.v:185394$12360_Y + connect \$74 $and$libresoc.v:185395$12361_Y + connect \$76 $ternary$libresoc.v:185396$12362_Y + connect \$78 $ternary$libresoc.v:185397$12363_Y + connect \$7 $or$libresoc.v:185398$12364_Y + connect \$80 $ternary$libresoc.v:185399$12365_Y + connect \$82 $ternary$libresoc.v:185400$12366_Y + connect \$84 $ternary$libresoc.v:185401$12367_Y + connect \$86 $ternary$libresoc.v:185402$12368_Y + connect \$88 $ternary$libresoc.v:185403$12369_Y + connect \$4 $reduce_and$libresoc.v:185404$12370_Y + connect \$90 $and$libresoc.v:185405$12371_Y + connect \$92 $and$libresoc.v:185406$12372_Y + connect \$94 $and$libresoc.v:185407$12373_Y + connect \$96 $not$libresoc.v:185408$12374_Y + connect \$98 $and$libresoc.v:185409$12375_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -397437,48 +387982,48 @@ module \shiftrot0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:191732.1-191911.10" +attribute \src "libresoc.v:185927.1-186107.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr - attribute \src "libresoc.v:191883.3-191886.6" - wire width 7 $0$memwr$\memory$libresoc.v:191885$12995_ADDR[6:0]$12998 - attribute \src "libresoc.v:191883.3-191886.6" - wire width 64 $0$memwr$\memory$libresoc.v:191885$12995_DATA[63:0]$12999 - attribute \src "libresoc.v:191883.3-191886.6" - wire width 64 $0$memwr$\memory$libresoc.v:191885$12995_EN[63:0]$13000 - attribute \src "libresoc.v:191883.3-191886.6" + attribute \src "libresoc.v:186079.3-186082.6" + wire width 7 $0$memwr$\memory$libresoc.v:186081$12699_ADDR[6:0]$12702 + attribute \src "libresoc.v:186079.3-186082.6" + wire width 64 $0$memwr$\memory$libresoc.v:186081$12699_DATA[63:0]$12703 + attribute \src "libresoc.v:186079.3-186082.6" + wire width 64 $0$memwr$\memory$libresoc.v:186081$12699_EN[63:0]$12704 + attribute \src "libresoc.v:186079.3-186082.6" wire width 7 $0\_0_[6:0] - attribute \src "libresoc.v:191733.7-191733.20" + attribute \src "libresoc.v:185928.7-185928.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191888.3-191896.6" - wire $0\ren_delay$next[0:0]$13003 - attribute \src "libresoc.v:191765.3-191766.35" + attribute \src "libresoc.v:186084.3-186092.6" + wire $0\ren_delay$next[0:0]$12707 + attribute \src "libresoc.v:185960.3-185961.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:191897.3-191906.6" + attribute \src "libresoc.v:186093.3-186102.6" wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:191888.3-191896.6" - wire $1\ren_delay$next[0:0]$13004 - attribute \src "libresoc.v:191749.7-191749.23" + attribute \src "libresoc.v:186084.3-186092.6" + wire $1\ren_delay$next[0:0]$12708 + attribute \src "libresoc.v:185944.7-185944.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:191897.3-191906.6" + attribute \src "libresoc.v:186093.3-186102.6" wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:191887.26-191887.32" - wire width 64 $memrd$\memory$libresoc.v:191887$13001_DATA + attribute \src "libresoc.v:186083.26-186083.32" + wire width 64 $memrd$\memory$libresoc.v:186083$12705_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 7 $memwr$\memory$libresoc.v:191885$12995_ADDR + wire width 7 $memwr$\memory$libresoc.v:186081$12699_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:191885$12995_DATA + wire width 64 $memwr$\memory$libresoc.v:186081$12699_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:191885$12995_EN - attribute \src "libresoc.v:191882.13-191882.16" + wire width 64 $memwr$\memory$libresoc.v:186081$12699_EN + attribute \src "libresoc.v:186078.13-186078.16" wire width 7 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:191733.7-191733.15" + attribute \src "libresoc.v:185928.7-185928.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 7 \memory_r_addr @@ -397506,1130 +388051,1140 @@ module \spr wire input 4 \spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \spr1__wen - attribute \src "libresoc.v:191767.14-191767.20" - memory width 64 size 112 \memory + attribute \src "libresoc.v:185962.14-185962.20" + memory width 64 size 113 \memory attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13006 + cell $meminit $meminit$\memory$libresoc.v:0$12710 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13006 + parameter \PRIORITY 12710 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13007 + cell $meminit $meminit$\memory$libresoc.v:0$12711 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13007 + parameter \PRIORITY 12711 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13008 + cell $meminit $meminit$\memory$libresoc.v:0$12712 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13008 + parameter \PRIORITY 12712 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13009 + cell $meminit $meminit$\memory$libresoc.v:0$12713 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13009 + parameter \PRIORITY 12713 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13010 + cell $meminit $meminit$\memory$libresoc.v:0$12714 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13010 + parameter \PRIORITY 12714 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13011 + cell $meminit $meminit$\memory$libresoc.v:0$12715 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13011 + parameter \PRIORITY 12715 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13012 + cell $meminit $meminit$\memory$libresoc.v:0$12716 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13012 + parameter \PRIORITY 12716 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13013 + cell $meminit $meminit$\memory$libresoc.v:0$12717 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13013 + parameter \PRIORITY 12717 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13014 + cell $meminit $meminit$\memory$libresoc.v:0$12718 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13014 + parameter \PRIORITY 12718 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13015 + cell $meminit $meminit$\memory$libresoc.v:0$12719 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13015 + parameter \PRIORITY 12719 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13016 + cell $meminit $meminit$\memory$libresoc.v:0$12720 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13016 + parameter \PRIORITY 12720 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13017 + cell $meminit $meminit$\memory$libresoc.v:0$12721 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13017 + parameter \PRIORITY 12721 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13018 + cell $meminit $meminit$\memory$libresoc.v:0$12722 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13018 + parameter \PRIORITY 12722 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13019 + cell $meminit $meminit$\memory$libresoc.v:0$12723 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13019 + parameter \PRIORITY 12723 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13020 + cell $meminit $meminit$\memory$libresoc.v:0$12724 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13020 + parameter \PRIORITY 12724 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13021 + cell $meminit $meminit$\memory$libresoc.v:0$12725 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13021 + parameter \PRIORITY 12725 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13022 + cell $meminit $meminit$\memory$libresoc.v:0$12726 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13022 + parameter \PRIORITY 12726 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13023 + cell $meminit $meminit$\memory$libresoc.v:0$12727 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13023 + parameter \PRIORITY 12727 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13024 + cell $meminit $meminit$\memory$libresoc.v:0$12728 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13024 + parameter \PRIORITY 12728 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13025 + cell $meminit $meminit$\memory$libresoc.v:0$12729 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13025 + parameter \PRIORITY 12729 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13026 + cell $meminit $meminit$\memory$libresoc.v:0$12730 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13026 + parameter \PRIORITY 12730 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13027 + cell $meminit $meminit$\memory$libresoc.v:0$12731 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13027 + parameter \PRIORITY 12731 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13028 + cell $meminit $meminit$\memory$libresoc.v:0$12732 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13028 + parameter \PRIORITY 12732 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13029 + cell $meminit $meminit$\memory$libresoc.v:0$12733 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13029 + parameter \PRIORITY 12733 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13030 + cell $meminit $meminit$\memory$libresoc.v:0$12734 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13030 + parameter \PRIORITY 12734 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13031 + cell $meminit $meminit$\memory$libresoc.v:0$12735 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13031 + parameter \PRIORITY 12735 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13032 + cell $meminit $meminit$\memory$libresoc.v:0$12736 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13032 + parameter \PRIORITY 12736 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13033 + cell $meminit $meminit$\memory$libresoc.v:0$12737 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13033 + parameter \PRIORITY 12737 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13034 + cell $meminit $meminit$\memory$libresoc.v:0$12738 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13034 + parameter \PRIORITY 12738 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13035 + cell $meminit $meminit$\memory$libresoc.v:0$12739 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13035 + parameter \PRIORITY 12739 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13036 + cell $meminit $meminit$\memory$libresoc.v:0$12740 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13036 + parameter \PRIORITY 12740 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13037 + cell $meminit $meminit$\memory$libresoc.v:0$12741 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13037 + parameter \PRIORITY 12741 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13038 + cell $meminit $meminit$\memory$libresoc.v:0$12742 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13038 + parameter \PRIORITY 12742 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 32 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13039 + cell $meminit $meminit$\memory$libresoc.v:0$12743 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13039 + parameter \PRIORITY 12743 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 33 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13040 + cell $meminit $meminit$\memory$libresoc.v:0$12744 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13040 + parameter \PRIORITY 12744 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 34 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13041 + cell $meminit $meminit$\memory$libresoc.v:0$12745 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13041 + parameter \PRIORITY 12745 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 35 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13042 + cell $meminit $meminit$\memory$libresoc.v:0$12746 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13042 + parameter \PRIORITY 12746 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 36 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13043 + cell $meminit $meminit$\memory$libresoc.v:0$12747 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13043 + parameter \PRIORITY 12747 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 37 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13044 + cell $meminit $meminit$\memory$libresoc.v:0$12748 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13044 + parameter \PRIORITY 12748 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 38 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13045 + cell $meminit $meminit$\memory$libresoc.v:0$12749 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13045 + parameter \PRIORITY 12749 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 39 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13046 + cell $meminit $meminit$\memory$libresoc.v:0$12750 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13046 + parameter \PRIORITY 12750 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 40 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13047 + cell $meminit $meminit$\memory$libresoc.v:0$12751 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13047 + parameter \PRIORITY 12751 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 41 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13048 + cell $meminit $meminit$\memory$libresoc.v:0$12752 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13048 + parameter \PRIORITY 12752 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 42 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13049 + cell $meminit $meminit$\memory$libresoc.v:0$12753 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13049 + parameter \PRIORITY 12753 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 43 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13050 + cell $meminit $meminit$\memory$libresoc.v:0$12754 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13050 + parameter \PRIORITY 12754 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 44 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13051 + cell $meminit $meminit$\memory$libresoc.v:0$12755 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13051 + parameter \PRIORITY 12755 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 45 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13052 + cell $meminit $meminit$\memory$libresoc.v:0$12756 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13052 + parameter \PRIORITY 12756 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 46 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13053 + cell $meminit $meminit$\memory$libresoc.v:0$12757 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13053 + parameter \PRIORITY 12757 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 47 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13054 + cell $meminit $meminit$\memory$libresoc.v:0$12758 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13054 + parameter \PRIORITY 12758 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 48 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13055 + cell $meminit $meminit$\memory$libresoc.v:0$12759 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13055 + parameter \PRIORITY 12759 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 49 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13056 + cell $meminit $meminit$\memory$libresoc.v:0$12760 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13056 + parameter \PRIORITY 12760 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 50 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13057 + cell $meminit $meminit$\memory$libresoc.v:0$12761 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13057 + parameter \PRIORITY 12761 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 51 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13058 + cell $meminit $meminit$\memory$libresoc.v:0$12762 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13058 + parameter \PRIORITY 12762 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 52 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13059 + cell $meminit $meminit$\memory$libresoc.v:0$12763 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13059 + parameter \PRIORITY 12763 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 53 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13060 + cell $meminit $meminit$\memory$libresoc.v:0$12764 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13060 + parameter \PRIORITY 12764 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 54 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13061 + cell $meminit $meminit$\memory$libresoc.v:0$12765 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13061 + parameter \PRIORITY 12765 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 55 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13062 + cell $meminit $meminit$\memory$libresoc.v:0$12766 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13062 + parameter \PRIORITY 12766 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 56 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13063 + cell $meminit $meminit$\memory$libresoc.v:0$12767 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13063 + parameter \PRIORITY 12767 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 57 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13064 + cell $meminit $meminit$\memory$libresoc.v:0$12768 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13064 + parameter \PRIORITY 12768 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 58 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13065 + cell $meminit $meminit$\memory$libresoc.v:0$12769 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13065 + parameter \PRIORITY 12769 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 59 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13066 + cell $meminit $meminit$\memory$libresoc.v:0$12770 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13066 + parameter \PRIORITY 12770 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 60 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13067 + cell $meminit $meminit$\memory$libresoc.v:0$12771 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13067 + parameter \PRIORITY 12771 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 61 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13068 + cell $meminit $meminit$\memory$libresoc.v:0$12772 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13068 + parameter \PRIORITY 12772 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 62 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13069 + cell $meminit $meminit$\memory$libresoc.v:0$12773 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13069 + parameter \PRIORITY 12773 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 63 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13070 + cell $meminit $meminit$\memory$libresoc.v:0$12774 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13070 + parameter \PRIORITY 12774 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 64 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13071 + cell $meminit $meminit$\memory$libresoc.v:0$12775 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13071 + parameter \PRIORITY 12775 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 65 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13072 + cell $meminit $meminit$\memory$libresoc.v:0$12776 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13072 + parameter \PRIORITY 12776 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 66 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13073 + cell $meminit $meminit$\memory$libresoc.v:0$12777 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13073 + parameter \PRIORITY 12777 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 67 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13074 + cell $meminit $meminit$\memory$libresoc.v:0$12778 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13074 + parameter \PRIORITY 12778 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 68 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13075 + cell $meminit $meminit$\memory$libresoc.v:0$12779 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13075 + parameter \PRIORITY 12779 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 69 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13076 + cell $meminit $meminit$\memory$libresoc.v:0$12780 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13076 + parameter \PRIORITY 12780 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 70 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13077 + cell $meminit $meminit$\memory$libresoc.v:0$12781 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13077 + parameter \PRIORITY 12781 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 71 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13078 + cell $meminit $meminit$\memory$libresoc.v:0$12782 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13078 + parameter \PRIORITY 12782 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 72 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13079 + cell $meminit $meminit$\memory$libresoc.v:0$12783 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13079 + parameter \PRIORITY 12783 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 73 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13080 + cell $meminit $meminit$\memory$libresoc.v:0$12784 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13080 + parameter \PRIORITY 12784 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 74 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13081 + cell $meminit $meminit$\memory$libresoc.v:0$12785 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13081 + parameter \PRIORITY 12785 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 75 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13082 + cell $meminit $meminit$\memory$libresoc.v:0$12786 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13082 + parameter \PRIORITY 12786 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 76 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13083 + cell $meminit $meminit$\memory$libresoc.v:0$12787 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13083 + parameter \PRIORITY 12787 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 77 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13084 + cell $meminit $meminit$\memory$libresoc.v:0$12788 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13084 + parameter \PRIORITY 12788 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 78 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13085 + cell $meminit $meminit$\memory$libresoc.v:0$12789 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13085 + parameter \PRIORITY 12789 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 79 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13086 + cell $meminit $meminit$\memory$libresoc.v:0$12790 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13086 + parameter \PRIORITY 12790 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 80 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13087 + cell $meminit $meminit$\memory$libresoc.v:0$12791 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13087 + parameter \PRIORITY 12791 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 81 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13088 + cell $meminit $meminit$\memory$libresoc.v:0$12792 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13088 + parameter \PRIORITY 12792 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 82 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13089 + cell $meminit $meminit$\memory$libresoc.v:0$12793 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13089 + parameter \PRIORITY 12793 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 83 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13090 + cell $meminit $meminit$\memory$libresoc.v:0$12794 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13090 + parameter \PRIORITY 12794 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 84 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13091 + cell $meminit $meminit$\memory$libresoc.v:0$12795 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13091 + parameter \PRIORITY 12795 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 85 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13092 + cell $meminit $meminit$\memory$libresoc.v:0$12796 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13092 + parameter \PRIORITY 12796 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 86 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13093 + cell $meminit $meminit$\memory$libresoc.v:0$12797 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13093 + parameter \PRIORITY 12797 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 87 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13094 + cell $meminit $meminit$\memory$libresoc.v:0$12798 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13094 + parameter \PRIORITY 12798 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 88 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13095 + cell $meminit $meminit$\memory$libresoc.v:0$12799 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13095 + parameter \PRIORITY 12799 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 89 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13096 + cell $meminit $meminit$\memory$libresoc.v:0$12800 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13096 + parameter \PRIORITY 12800 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 90 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13097 + cell $meminit $meminit$\memory$libresoc.v:0$12801 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13097 + parameter \PRIORITY 12801 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 91 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13098 + cell $meminit $meminit$\memory$libresoc.v:0$12802 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13098 + parameter \PRIORITY 12802 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 92 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13099 + cell $meminit $meminit$\memory$libresoc.v:0$12803 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13099 + parameter \PRIORITY 12803 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 93 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13100 + cell $meminit $meminit$\memory$libresoc.v:0$12804 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13100 + parameter \PRIORITY 12804 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 94 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13101 + cell $meminit $meminit$\memory$libresoc.v:0$12805 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13101 + parameter \PRIORITY 12805 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 95 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13102 + cell $meminit $meminit$\memory$libresoc.v:0$12806 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13102 + parameter \PRIORITY 12806 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 96 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13103 + cell $meminit $meminit$\memory$libresoc.v:0$12807 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13103 + parameter \PRIORITY 12807 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 97 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13104 + cell $meminit $meminit$\memory$libresoc.v:0$12808 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13104 + parameter \PRIORITY 12808 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 98 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13105 + cell $meminit $meminit$\memory$libresoc.v:0$12809 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13105 + parameter \PRIORITY 12809 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 99 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13106 + cell $meminit $meminit$\memory$libresoc.v:0$12810 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13106 + parameter \PRIORITY 12810 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 100 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13107 + cell $meminit $meminit$\memory$libresoc.v:0$12811 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13107 + parameter \PRIORITY 12811 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 101 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13108 + cell $meminit $meminit$\memory$libresoc.v:0$12812 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13108 + parameter \PRIORITY 12812 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 102 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13109 + cell $meminit $meminit$\memory$libresoc.v:0$12813 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13109 + parameter \PRIORITY 12813 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 103 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13110 + cell $meminit $meminit$\memory$libresoc.v:0$12814 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13110 + parameter \PRIORITY 12814 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 104 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13111 + cell $meminit $meminit$\memory$libresoc.v:0$12815 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13111 + parameter \PRIORITY 12815 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 105 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13112 + cell $meminit $meminit$\memory$libresoc.v:0$12816 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13112 + parameter \PRIORITY 12816 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 106 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13113 + cell $meminit $meminit$\memory$libresoc.v:0$12817 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13113 + parameter \PRIORITY 12817 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 107 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13114 + cell $meminit $meminit$\memory$libresoc.v:0$12818 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13114 + parameter \PRIORITY 12818 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 108 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13115 + cell $meminit $meminit$\memory$libresoc.v:0$12819 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13115 + parameter \PRIORITY 12819 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 109 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13116 + cell $meminit $meminit$\memory$libresoc.v:0$12820 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13116 + parameter \PRIORITY 12820 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 110 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$13117 + cell $meminit $meminit$\memory$libresoc.v:0$12821 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 13117 + parameter \PRIORITY 12821 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 111 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:191887.26-191887.32" - cell $memrd $memrd$\memory$libresoc.v:191887$13001 + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$12822 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 12822 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 112 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:186083.26-186083.32" + cell $memrd $memrd$\memory$libresoc.v:186083$12705 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -398638,83 +389193,83 @@ module \spr parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:191887$13001_DATA + connect \DATA $memrd$\memory$libresoc.v:186083$12705_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$13118 + cell $memwr $memwr$\memory$libresoc.v:0$12823 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\memory" - parameter \PRIORITY 13118 + parameter \PRIORITY 12823 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:191885$12995_ADDR + connect \ADDR $memwr$\memory$libresoc.v:186081$12699_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:191885$12995_DATA - connect \EN $memwr$\memory$libresoc.v:191885$12995_EN + connect \DATA $memwr$\memory$libresoc.v:186081$12699_DATA + connect \EN $memwr$\memory$libresoc.v:186081$12699_EN end attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$13121 + process $proc$libresoc.v:0$12826 sync always sync init end - attribute \src "libresoc.v:191733.7-191733.20" - process $proc$libresoc.v:191733$13119 + attribute \src "libresoc.v:185928.7-185928.20" + process $proc$libresoc.v:185928$12824 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191749.7-191749.23" - process $proc$libresoc.v:191749$13120 + attribute \src "libresoc.v:185944.7-185944.23" + process $proc$libresoc.v:185944$12825 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:191765.3-191766.35" - process $proc$libresoc.v:191765$12996 + attribute \src "libresoc.v:185960.3-185961.35" + process $proc$libresoc.v:185960$12700 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:191883.3-191886.6" - process $proc$libresoc.v:191883$12997 + attribute \src "libresoc.v:186079.3-186082.6" + process $proc$libresoc.v:186079$12701 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:191885$12995_ADDR[6:0]$12998 7'xxxxxxx - assign $0$memwr$\memory$libresoc.v:191885$12995_DATA[63:0]$12999 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:191885$12995_EN[63:0]$13000 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:186081$12699_ADDR[6:0]$12702 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:186081$12699_DATA[63:0]$12703 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:186081$12699_EN[63:0]$12704 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[6:0] \spr1__addr - attribute \src "libresoc.v:191885.5-191885.59" + attribute \src "libresoc.v:186081.5-186081.59" switch \spr1__wen - attribute \src "libresoc.v:191885.9-191885.18" + attribute \src "libresoc.v:186081.9-186081.18" case 1'1 - assign $0$memwr$\memory$libresoc.v:191885$12995_ADDR[6:0]$12998 \spr1__addr$1 - assign $0$memwr$\memory$libresoc.v:191885$12995_DATA[63:0]$12999 \spr1__data_i - assign $0$memwr$\memory$libresoc.v:191885$12995_EN[63:0]$13000 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:186081$12699_ADDR[6:0]$12702 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:186081$12699_DATA[63:0]$12703 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:186081$12699_EN[63:0]$12704 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[6:0] - update $memwr$\memory$libresoc.v:191885$12995_ADDR $0$memwr$\memory$libresoc.v:191885$12995_ADDR[6:0]$12998 - update $memwr$\memory$libresoc.v:191885$12995_DATA $0$memwr$\memory$libresoc.v:191885$12995_DATA[63:0]$12999 - update $memwr$\memory$libresoc.v:191885$12995_EN $0$memwr$\memory$libresoc.v:191885$12995_EN[63:0]$13000 + update $memwr$\memory$libresoc.v:186081$12699_ADDR $0$memwr$\memory$libresoc.v:186081$12699_ADDR[6:0]$12702 + update $memwr$\memory$libresoc.v:186081$12699_DATA $0$memwr$\memory$libresoc.v:186081$12699_DATA[63:0]$12703 + update $memwr$\memory$libresoc.v:186081$12699_EN $0$memwr$\memory$libresoc.v:186081$12699_EN[63:0]$12704 end - attribute \src "libresoc.v:191888.3-191896.6" - process $proc$libresoc.v:191888$13002 + attribute \src "libresoc.v:186084.3-186092.6" + process $proc$libresoc.v:186084$12706 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$13003 $1\ren_delay$next[0:0]$13004 - attribute \src "libresoc.v:191889.5-191889.29" + assign $0\ren_delay$next[0:0]$12707 $1\ren_delay$next[0:0]$12708 + attribute \src "libresoc.v:186085.5-186085.29" switch \initial - attribute \src "libresoc.v:191889.9-191889.17" + attribute \src "libresoc.v:186085.9-186085.17" case 1'1 case end @@ -398723,21 +389278,21 @@ module \spr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$13004 1'0 + assign $1\ren_delay$next[0:0]$12708 1'0 case - assign $1\ren_delay$next[0:0]$13004 \spr1__ren + assign $1\ren_delay$next[0:0]$12708 \spr1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$13003 + update \ren_delay$next $0\ren_delay$next[0:0]$12707 end - attribute \src "libresoc.v:191897.3-191906.6" - process $proc$libresoc.v:191897$13005 + attribute \src "libresoc.v:186093.3-186102.6" + process $proc$libresoc.v:186093$12709 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:191898.5-191898.29" + attribute \src "libresoc.v:186094.5-186094.29" switch \initial - attribute \src "libresoc.v:191898.9-191898.17" + attribute \src "libresoc.v:186094.9-186094.17" case 1'1 case end @@ -398753,503 +389308,503 @@ module \spr sync always update \spr1__data_o $0\spr1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:191887$13001_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:186083$12705_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end -attribute \src "libresoc.v:191915.1-193164.10" +attribute \src "libresoc.v:186111.1-187360.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 - attribute \src "libresoc.v:192661.3-192662.25" + attribute \src "libresoc.v:186857.3-186858.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:192659.3-192660.40" + attribute \src "libresoc.v:186855.3-186856.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:193055.3-193063.6" - wire $0\alu_l_r_alu$next[0:0]$13335 - attribute \src "libresoc.v:192589.3-192590.39" + attribute \src "libresoc.v:187251.3-187259.6" + wire $0\alu_l_r_alu$next[0:0]$13040 + attribute \src "libresoc.v:186785.3-186786.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:192841.3-192853.6" - wire width 13 $0\alu_spr0_spr_op__fn_unit$next[12:0]$13257 - attribute \src "libresoc.v:192631.3-192632.65" + attribute \src "libresoc.v:187037.3-187049.6" + wire width 13 $0\alu_spr0_spr_op__fn_unit$next[12:0]$12962 + attribute \src "libresoc.v:186827.3-186828.65" wire width 13 $0\alu_spr0_spr_op__fn_unit[12:0] - attribute \src "libresoc.v:192841.3-192853.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$13258 - attribute \src "libresoc.v:192633.3-192634.59" + attribute \src "libresoc.v:187037.3-187049.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12963 + attribute \src "libresoc.v:186829.3-186830.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:192841.3-192853.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$13259 - attribute \src "libresoc.v:192629.3-192630.69" + attribute \src "libresoc.v:187037.3-187049.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12964 + attribute \src "libresoc.v:186825.3-186826.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:192841.3-192853.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$13260 - attribute \src "libresoc.v:192635.3-192636.67" + attribute \src "libresoc.v:187037.3-187049.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12965 + attribute \src "libresoc.v:186831.3-186832.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:193046.3-193054.6" - wire $0\alui_l_r_alui$next[0:0]$13332 - attribute \src "libresoc.v:192591.3-192592.43" + attribute \src "libresoc.v:187242.3-187250.6" + wire $0\alui_l_r_alui$next[0:0]$13037 + attribute \src "libresoc.v:186787.3-186788.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:192854.3-192875.6" - wire width 64 $0\data_r0__o$next[63:0]$13266 - attribute \src "libresoc.v:192625.3-192626.37" + attribute \src "libresoc.v:187050.3-187071.6" + wire width 64 $0\data_r0__o$next[63:0]$12971 + attribute \src "libresoc.v:186821.3-186822.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:192854.3-192875.6" - wire $0\data_r0__o_ok$next[0:0]$13267 - attribute \src "libresoc.v:192627.3-192628.43" + attribute \src "libresoc.v:187050.3-187071.6" + wire $0\data_r0__o_ok$next[0:0]$12972 + attribute \src "libresoc.v:186823.3-186824.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:192876.3-192897.6" - wire width 64 $0\data_r1__spr1$next[63:0]$13274 - attribute \src "libresoc.v:192621.3-192622.43" + attribute \src "libresoc.v:187072.3-187093.6" + wire width 64 $0\data_r1__spr1$next[63:0]$12979 + attribute \src "libresoc.v:186817.3-186818.43" wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:192876.3-192897.6" - wire $0\data_r1__spr1_ok$next[0:0]$13275 - attribute \src "libresoc.v:192623.3-192624.49" + attribute \src "libresoc.v:187072.3-187093.6" + wire $0\data_r1__spr1_ok$next[0:0]$12980 + attribute \src "libresoc.v:186819.3-186820.49" wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:192898.3-192919.6" - wire width 64 $0\data_r2__fast1$next[63:0]$13282 - attribute \src "libresoc.v:192617.3-192618.45" + attribute \src "libresoc.v:187094.3-187115.6" + wire width 64 $0\data_r2__fast1$next[63:0]$12987 + attribute \src "libresoc.v:186813.3-186814.45" wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:192898.3-192919.6" - wire $0\data_r2__fast1_ok$next[0:0]$13283 - attribute \src "libresoc.v:192619.3-192620.51" + attribute \src "libresoc.v:187094.3-187115.6" + wire $0\data_r2__fast1_ok$next[0:0]$12988 + attribute \src "libresoc.v:186815.3-186816.51" wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:192920.3-192941.6" - wire $0\data_r3__xer_so$next[0:0]$13290 - attribute \src "libresoc.v:192613.3-192614.47" + attribute \src "libresoc.v:187116.3-187137.6" + wire $0\data_r3__xer_so$next[0:0]$12995 + attribute \src "libresoc.v:186809.3-186810.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:192920.3-192941.6" - wire $0\data_r3__xer_so_ok$next[0:0]$13291 - attribute \src "libresoc.v:192615.3-192616.53" + attribute \src "libresoc.v:187116.3-187137.6" + wire $0\data_r3__xer_so_ok$next[0:0]$12996 + attribute \src "libresoc.v:186811.3-186812.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:192942.3-192963.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$13298 - attribute \src "libresoc.v:192609.3-192610.47" + attribute \src "libresoc.v:187138.3-187159.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$13003 + attribute \src "libresoc.v:186805.3-186806.47" wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:192942.3-192963.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$13299 - attribute \src "libresoc.v:192611.3-192612.53" + attribute \src "libresoc.v:187138.3-187159.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$13004 + attribute \src "libresoc.v:186807.3-186808.53" wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:192964.3-192985.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$13306 - attribute \src "libresoc.v:192605.3-192606.47" + attribute \src "libresoc.v:187160.3-187181.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$13011 + attribute \src "libresoc.v:186801.3-186802.47" wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:192964.3-192985.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$13307 - attribute \src "libresoc.v:192607.3-192608.53" + attribute \src "libresoc.v:187160.3-187181.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$13012 + attribute \src "libresoc.v:186803.3-186804.53" wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:193064.3-193073.6" + attribute \src "libresoc.v:187260.3-187269.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:193074.3-193083.6" + attribute \src "libresoc.v:187270.3-187279.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:193084.3-193093.6" + attribute \src "libresoc.v:187280.3-187289.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:193094.3-193103.6" + attribute \src "libresoc.v:187290.3-187299.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:193104.3-193113.6" + attribute \src "libresoc.v:187300.3-187309.6" wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:193114.3-193123.6" + attribute \src "libresoc.v:187310.3-187319.6" wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:191916.7-191916.20" + attribute \src "libresoc.v:186112.7-186112.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192796.3-192804.6" - wire $0\opc_l_r_opc$next[0:0]$13242 - attribute \src "libresoc.v:192645.3-192646.39" + attribute \src "libresoc.v:186992.3-187000.6" + wire $0\opc_l_r_opc$next[0:0]$12947 + attribute \src "libresoc.v:186841.3-186842.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:192787.3-192795.6" - wire $0\opc_l_s_opc$next[0:0]$13239 - attribute \src "libresoc.v:192647.3-192648.39" + attribute \src "libresoc.v:186983.3-186991.6" + wire $0\opc_l_s_opc$next[0:0]$12944 + attribute \src "libresoc.v:186843.3-186844.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:193124.3-193132.6" - wire width 6 $0\prev_wr_go$next[5:0]$13344 - attribute \src "libresoc.v:192657.3-192658.37" + attribute \src "libresoc.v:187320.3-187328.6" + wire width 6 $0\prev_wr_go$next[5:0]$13049 + attribute \src "libresoc.v:186853.3-186854.37" wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:192741.3-192750.6" + attribute \src "libresoc.v:186937.3-186946.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:192832.3-192840.6" - wire width 6 $0\req_l_r_req$next[5:0]$13254 - attribute \src "libresoc.v:192637.3-192638.39" + attribute \src "libresoc.v:187028.3-187036.6" + wire width 6 $0\req_l_r_req$next[5:0]$12959 + attribute \src "libresoc.v:186833.3-186834.39" wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:192823.3-192831.6" - wire width 6 $0\req_l_s_req$next[5:0]$13251 - attribute \src "libresoc.v:192639.3-192640.39" + attribute \src "libresoc.v:187019.3-187027.6" + wire width 6 $0\req_l_s_req$next[5:0]$12956 + attribute \src "libresoc.v:186835.3-186836.39" wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:192760.3-192768.6" - wire $0\rok_l_r_rdok$next[0:0]$13230 - attribute \src "libresoc.v:192653.3-192654.41" + attribute \src "libresoc.v:186956.3-186964.6" + wire $0\rok_l_r_rdok$next[0:0]$12935 + attribute \src "libresoc.v:186849.3-186850.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:192751.3-192759.6" - wire $0\rok_l_s_rdok$next[0:0]$13227 - attribute \src "libresoc.v:192655.3-192656.41" + attribute \src "libresoc.v:186947.3-186955.6" + wire $0\rok_l_s_rdok$next[0:0]$12932 + attribute \src "libresoc.v:186851.3-186852.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:192778.3-192786.6" - wire $0\rst_l_r_rst$next[0:0]$13236 - attribute \src "libresoc.v:192649.3-192650.39" + attribute \src "libresoc.v:186974.3-186982.6" + wire $0\rst_l_r_rst$next[0:0]$12941 + attribute \src "libresoc.v:186845.3-186846.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:192769.3-192777.6" - wire $0\rst_l_s_rst$next[0:0]$13233 - attribute \src "libresoc.v:192651.3-192652.39" + attribute \src "libresoc.v:186965.3-186973.6" + wire $0\rst_l_s_rst$next[0:0]$12938 + attribute \src "libresoc.v:186847.3-186848.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:192814.3-192822.6" - wire width 6 $0\src_l_r_src$next[5:0]$13248 - attribute \src "libresoc.v:192641.3-192642.39" + attribute \src "libresoc.v:187010.3-187018.6" + wire width 6 $0\src_l_r_src$next[5:0]$12953 + attribute \src "libresoc.v:186837.3-186838.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:192805.3-192813.6" - wire width 6 $0\src_l_s_src$next[5:0]$13245 - attribute \src "libresoc.v:192643.3-192644.39" + attribute \src "libresoc.v:187001.3-187009.6" + wire width 6 $0\src_l_s_src$next[5:0]$12950 + attribute \src "libresoc.v:186839.3-186840.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:192986.3-192995.6" - wire width 64 $0\src_r0$next[63:0]$13314 - attribute \src "libresoc.v:192603.3-192604.29" + attribute \src "libresoc.v:187182.3-187191.6" + wire width 64 $0\src_r0$next[63:0]$13019 + attribute \src "libresoc.v:186799.3-186800.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:192996.3-193005.6" - wire width 64 $0\src_r1$next[63:0]$13317 - attribute \src "libresoc.v:192601.3-192602.29" + attribute \src "libresoc.v:187192.3-187201.6" + wire width 64 $0\src_r1$next[63:0]$13022 + attribute \src "libresoc.v:186797.3-186798.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:193006.3-193015.6" - wire width 64 $0\src_r2$next[63:0]$13320 - attribute \src "libresoc.v:192599.3-192600.29" + attribute \src "libresoc.v:187202.3-187211.6" + wire width 64 $0\src_r2$next[63:0]$13025 + attribute \src "libresoc.v:186795.3-186796.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:193016.3-193025.6" - wire $0\src_r3$next[0:0]$13323 - attribute \src "libresoc.v:192597.3-192598.29" + attribute \src "libresoc.v:187212.3-187221.6" + wire $0\src_r3$next[0:0]$13028 + attribute \src "libresoc.v:186793.3-186794.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:193026.3-193035.6" - wire width 2 $0\src_r4$next[1:0]$13326 - attribute \src "libresoc.v:192595.3-192596.29" + attribute \src "libresoc.v:187222.3-187231.6" + wire width 2 $0\src_r4$next[1:0]$13031 + attribute \src "libresoc.v:186791.3-186792.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:193036.3-193045.6" - wire width 2 $0\src_r5$next[1:0]$13329 - attribute \src "libresoc.v:192593.3-192594.29" + attribute \src "libresoc.v:187232.3-187241.6" + wire width 2 $0\src_r5$next[1:0]$13034 + attribute \src "libresoc.v:186789.3-186790.29" wire width 2 $0\src_r5[1:0] - attribute \src "libresoc.v:192052.7-192052.24" + attribute \src "libresoc.v:186248.7-186248.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:192062.7-192062.26" + attribute \src "libresoc.v:186258.7-186258.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:193055.3-193063.6" - wire $1\alu_l_r_alu$next[0:0]$13336 - attribute \src "libresoc.v:192070.7-192070.25" + attribute \src "libresoc.v:187251.3-187259.6" + wire $1\alu_l_r_alu$next[0:0]$13041 + attribute \src "libresoc.v:186266.7-186266.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:192841.3-192853.6" - wire width 13 $1\alu_spr0_spr_op__fn_unit$next[12:0]$13261 - attribute \src "libresoc.v:192114.14-192114.49" + attribute \src "libresoc.v:187037.3-187049.6" + wire width 13 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12966 + attribute \src "libresoc.v:186310.14-186310.49" wire width 13 $1\alu_spr0_spr_op__fn_unit[12:0] - attribute \src "libresoc.v:192841.3-192853.6" - wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$13262 - attribute \src "libresoc.v:192118.14-192118.43" + attribute \src "libresoc.v:187037.3-187049.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12967 + attribute \src "libresoc.v:186314.14-186314.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:192841.3-192853.6" - wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$13263 - attribute \src "libresoc.v:192196.13-192196.47" + attribute \src "libresoc.v:187037.3-187049.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12968 + attribute \src "libresoc.v:186392.13-186392.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:192841.3-192853.6" - wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$13264 - attribute \src "libresoc.v:192200.7-192200.39" + attribute \src "libresoc.v:187037.3-187049.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12969 + attribute \src "libresoc.v:186396.7-186396.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:193046.3-193054.6" - wire $1\alui_l_r_alui$next[0:0]$13333 - attribute \src "libresoc.v:192218.7-192218.27" + attribute \src "libresoc.v:187242.3-187250.6" + wire $1\alui_l_r_alui$next[0:0]$13038 + attribute \src "libresoc.v:186414.7-186414.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:192854.3-192875.6" - wire width 64 $1\data_r0__o$next[63:0]$13268 - attribute \src "libresoc.v:192250.14-192250.47" + attribute \src "libresoc.v:187050.3-187071.6" + wire width 64 $1\data_r0__o$next[63:0]$12973 + attribute \src "libresoc.v:186446.14-186446.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:192854.3-192875.6" - wire $1\data_r0__o_ok$next[0:0]$13269 - attribute \src "libresoc.v:192254.7-192254.27" + attribute \src "libresoc.v:187050.3-187071.6" + wire $1\data_r0__o_ok$next[0:0]$12974 + attribute \src "libresoc.v:186450.7-186450.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:192876.3-192897.6" - wire width 64 $1\data_r1__spr1$next[63:0]$13276 - attribute \src "libresoc.v:192258.14-192258.50" + attribute \src "libresoc.v:187072.3-187093.6" + wire width 64 $1\data_r1__spr1$next[63:0]$12981 + attribute \src "libresoc.v:186454.14-186454.50" wire width 64 $1\data_r1__spr1[63:0] - attribute \src "libresoc.v:192876.3-192897.6" - wire $1\data_r1__spr1_ok$next[0:0]$13277 - attribute \src "libresoc.v:192262.7-192262.30" + attribute \src "libresoc.v:187072.3-187093.6" + wire $1\data_r1__spr1_ok$next[0:0]$12982 + attribute \src "libresoc.v:186458.7-186458.30" wire $1\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:192898.3-192919.6" - wire width 64 $1\data_r2__fast1$next[63:0]$13284 - attribute \src "libresoc.v:192266.14-192266.51" + attribute \src "libresoc.v:187094.3-187115.6" + wire width 64 $1\data_r2__fast1$next[63:0]$12989 + attribute \src "libresoc.v:186462.14-186462.51" wire width 64 $1\data_r2__fast1[63:0] - attribute \src "libresoc.v:192898.3-192919.6" - wire $1\data_r2__fast1_ok$next[0:0]$13285 - attribute \src "libresoc.v:192270.7-192270.31" + attribute \src "libresoc.v:187094.3-187115.6" + wire $1\data_r2__fast1_ok$next[0:0]$12990 + attribute \src "libresoc.v:186466.7-186466.31" wire $1\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:192920.3-192941.6" - wire $1\data_r3__xer_so$next[0:0]$13292 - attribute \src "libresoc.v:192274.7-192274.29" + attribute \src "libresoc.v:187116.3-187137.6" + wire $1\data_r3__xer_so$next[0:0]$12997 + attribute \src "libresoc.v:186470.7-186470.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:192920.3-192941.6" - wire $1\data_r3__xer_so_ok$next[0:0]$13293 - attribute \src "libresoc.v:192278.7-192278.32" + attribute \src "libresoc.v:187116.3-187137.6" + wire $1\data_r3__xer_so_ok$next[0:0]$12998 + attribute \src "libresoc.v:186474.7-186474.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:192942.3-192963.6" - wire width 2 $1\data_r4__xer_ov$next[1:0]$13300 - attribute \src "libresoc.v:192282.13-192282.35" + attribute \src "libresoc.v:187138.3-187159.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$13005 + attribute \src "libresoc.v:186478.13-186478.35" wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:192942.3-192963.6" - wire $1\data_r4__xer_ov_ok$next[0:0]$13301 - attribute \src "libresoc.v:192286.7-192286.32" + attribute \src "libresoc.v:187138.3-187159.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$13006 + attribute \src "libresoc.v:186482.7-186482.32" wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:192964.3-192985.6" - wire width 2 $1\data_r5__xer_ca$next[1:0]$13308 - attribute \src "libresoc.v:192290.13-192290.35" + attribute \src "libresoc.v:187160.3-187181.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$13013 + attribute \src "libresoc.v:186486.13-186486.35" wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:192964.3-192985.6" - wire $1\data_r5__xer_ca_ok$next[0:0]$13309 - attribute \src "libresoc.v:192294.7-192294.32" + attribute \src "libresoc.v:187160.3-187181.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$13014 + attribute \src "libresoc.v:186490.7-186490.32" wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:193064.3-193073.6" + attribute \src "libresoc.v:187260.3-187269.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:193074.3-193083.6" + attribute \src "libresoc.v:187270.3-187279.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:193084.3-193093.6" + attribute \src "libresoc.v:187280.3-187289.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:193094.3-193103.6" + attribute \src "libresoc.v:187290.3-187299.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:193104.3-193113.6" + attribute \src "libresoc.v:187300.3-187309.6" wire width 2 $1\dest5_o[1:0] - attribute \src "libresoc.v:193114.3-193123.6" + attribute \src "libresoc.v:187310.3-187319.6" wire width 2 $1\dest6_o[1:0] - attribute \src "libresoc.v:192796.3-192804.6" - wire $1\opc_l_r_opc$next[0:0]$13243 - attribute \src "libresoc.v:192322.7-192322.25" + attribute \src "libresoc.v:186992.3-187000.6" + wire $1\opc_l_r_opc$next[0:0]$12948 + attribute \src "libresoc.v:186518.7-186518.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:192787.3-192795.6" - wire $1\opc_l_s_opc$next[0:0]$13240 - attribute \src "libresoc.v:192326.7-192326.25" + attribute \src "libresoc.v:186983.3-186991.6" + wire $1\opc_l_s_opc$next[0:0]$12945 + attribute \src "libresoc.v:186522.7-186522.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:193124.3-193132.6" - wire width 6 $1\prev_wr_go$next[5:0]$13345 - attribute \src "libresoc.v:192426.13-192426.31" + attribute \src "libresoc.v:187320.3-187328.6" + wire width 6 $1\prev_wr_go$next[5:0]$13050 + attribute \src "libresoc.v:186622.13-186622.31" wire width 6 $1\prev_wr_go[5:0] - attribute \src "libresoc.v:192741.3-192750.6" + attribute \src "libresoc.v:186937.3-186946.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:192832.3-192840.6" - wire width 6 $1\req_l_r_req$next[5:0]$13255 - attribute \src "libresoc.v:192434.13-192434.32" + attribute \src "libresoc.v:187028.3-187036.6" + wire width 6 $1\req_l_r_req$next[5:0]$12960 + attribute \src "libresoc.v:186630.13-186630.32" wire width 6 $1\req_l_r_req[5:0] - attribute \src "libresoc.v:192823.3-192831.6" - wire width 6 $1\req_l_s_req$next[5:0]$13252 - attribute \src "libresoc.v:192438.13-192438.32" + attribute \src "libresoc.v:187019.3-187027.6" + wire width 6 $1\req_l_s_req$next[5:0]$12957 + attribute \src "libresoc.v:186634.13-186634.32" wire width 6 $1\req_l_s_req[5:0] - attribute \src "libresoc.v:192760.3-192768.6" - wire $1\rok_l_r_rdok$next[0:0]$13231 - attribute \src "libresoc.v:192450.7-192450.26" + attribute \src "libresoc.v:186956.3-186964.6" + wire $1\rok_l_r_rdok$next[0:0]$12936 + attribute \src "libresoc.v:186646.7-186646.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:192751.3-192759.6" - wire $1\rok_l_s_rdok$next[0:0]$13228 - attribute \src "libresoc.v:192454.7-192454.26" + attribute \src "libresoc.v:186947.3-186955.6" + wire $1\rok_l_s_rdok$next[0:0]$12933 + attribute \src "libresoc.v:186650.7-186650.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:192778.3-192786.6" - wire $1\rst_l_r_rst$next[0:0]$13237 - attribute \src "libresoc.v:192458.7-192458.25" + attribute \src "libresoc.v:186974.3-186982.6" + wire $1\rst_l_r_rst$next[0:0]$12942 + attribute \src "libresoc.v:186654.7-186654.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:192769.3-192777.6" - wire $1\rst_l_s_rst$next[0:0]$13234 - attribute \src "libresoc.v:192462.7-192462.25" + attribute \src "libresoc.v:186965.3-186973.6" + wire $1\rst_l_s_rst$next[0:0]$12939 + attribute \src "libresoc.v:186658.7-186658.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:192814.3-192822.6" - wire width 6 $1\src_l_r_src$next[5:0]$13249 - attribute \src "libresoc.v:192484.13-192484.32" + attribute \src "libresoc.v:187010.3-187018.6" + wire width 6 $1\src_l_r_src$next[5:0]$12954 + attribute \src "libresoc.v:186680.13-186680.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:192805.3-192813.6" - wire width 6 $1\src_l_s_src$next[5:0]$13246 - attribute \src "libresoc.v:192488.13-192488.32" + attribute \src "libresoc.v:187001.3-187009.6" + wire width 6 $1\src_l_s_src$next[5:0]$12951 + attribute \src "libresoc.v:186684.13-186684.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:192986.3-192995.6" - wire width 64 $1\src_r0$next[63:0]$13315 - attribute \src "libresoc.v:192492.14-192492.43" + attribute \src "libresoc.v:187182.3-187191.6" + wire width 64 $1\src_r0$next[63:0]$13020 + attribute \src "libresoc.v:186688.14-186688.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:192996.3-193005.6" - wire width 64 $1\src_r1$next[63:0]$13318 - attribute \src "libresoc.v:192496.14-192496.43" + attribute \src "libresoc.v:187192.3-187201.6" + wire width 64 $1\src_r1$next[63:0]$13023 + attribute \src "libresoc.v:186692.14-186692.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:193006.3-193015.6" - wire width 64 $1\src_r2$next[63:0]$13321 - attribute \src "libresoc.v:192500.14-192500.43" + attribute \src "libresoc.v:187202.3-187211.6" + wire width 64 $1\src_r2$next[63:0]$13026 + attribute \src "libresoc.v:186696.14-186696.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:193016.3-193025.6" - wire $1\src_r3$next[0:0]$13324 - attribute \src "libresoc.v:192504.7-192504.20" + attribute \src "libresoc.v:187212.3-187221.6" + wire $1\src_r3$next[0:0]$13029 + attribute \src "libresoc.v:186700.7-186700.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:193026.3-193035.6" - wire width 2 $1\src_r4$next[1:0]$13327 - attribute \src "libresoc.v:192508.13-192508.26" + attribute \src "libresoc.v:187222.3-187231.6" + wire width 2 $1\src_r4$next[1:0]$13032 + attribute \src "libresoc.v:186704.13-186704.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:193036.3-193045.6" - wire width 2 $1\src_r5$next[1:0]$13330 - attribute \src "libresoc.v:192512.13-192512.26" + attribute \src "libresoc.v:187232.3-187241.6" + wire width 2 $1\src_r5$next[1:0]$13035 + attribute \src "libresoc.v:186708.13-186708.26" wire width 2 $1\src_r5[1:0] - attribute \src "libresoc.v:192854.3-192875.6" - wire width 64 $2\data_r0__o$next[63:0]$13270 - attribute \src "libresoc.v:192854.3-192875.6" - wire $2\data_r0__o_ok$next[0:0]$13271 - attribute \src "libresoc.v:192876.3-192897.6" - wire width 64 $2\data_r1__spr1$next[63:0]$13278 - attribute \src "libresoc.v:192876.3-192897.6" - wire $2\data_r1__spr1_ok$next[0:0]$13279 - attribute \src "libresoc.v:192898.3-192919.6" - wire width 64 $2\data_r2__fast1$next[63:0]$13286 - attribute \src "libresoc.v:192898.3-192919.6" - wire $2\data_r2__fast1_ok$next[0:0]$13287 - attribute \src "libresoc.v:192920.3-192941.6" - wire $2\data_r3__xer_so$next[0:0]$13294 - attribute \src "libresoc.v:192920.3-192941.6" - wire $2\data_r3__xer_so_ok$next[0:0]$13295 - attribute \src "libresoc.v:192942.3-192963.6" - wire width 2 $2\data_r4__xer_ov$next[1:0]$13302 - attribute \src "libresoc.v:192942.3-192963.6" - wire $2\data_r4__xer_ov_ok$next[0:0]$13303 - attribute \src "libresoc.v:192964.3-192985.6" - wire width 2 $2\data_r5__xer_ca$next[1:0]$13310 - attribute \src "libresoc.v:192964.3-192985.6" - wire $2\data_r5__xer_ca_ok$next[0:0]$13311 - attribute \src "libresoc.v:192854.3-192875.6" - wire $3\data_r0__o_ok$next[0:0]$13272 - attribute \src "libresoc.v:192876.3-192897.6" - wire $3\data_r1__spr1_ok$next[0:0]$13280 - attribute \src "libresoc.v:192898.3-192919.6" - wire $3\data_r2__fast1_ok$next[0:0]$13288 - attribute \src "libresoc.v:192920.3-192941.6" - wire $3\data_r3__xer_so_ok$next[0:0]$13296 - attribute \src "libresoc.v:192942.3-192963.6" - wire $3\data_r4__xer_ov_ok$next[0:0]$13304 - attribute \src "libresoc.v:192964.3-192985.6" - wire $3\data_r5__xer_ca_ok$next[0:0]$13312 - attribute \src "libresoc.v:192524.19-192524.133" - wire $and$libresoc.v:192524$13123_Y - attribute \src "libresoc.v:192525.19-192525.183" - wire width 6 $and$libresoc.v:192525$13124_Y - attribute \src "libresoc.v:192526.19-192526.115" - wire width 6 $and$libresoc.v:192526$13125_Y - attribute \src "libresoc.v:192528.19-192528.115" - wire width 6 $and$libresoc.v:192528$13127_Y - attribute \src "libresoc.v:192529.19-192529.125" - wire $and$libresoc.v:192529$13128_Y - attribute \src "libresoc.v:192530.19-192530.125" - wire $and$libresoc.v:192530$13129_Y - attribute \src "libresoc.v:192531.19-192531.125" - wire $and$libresoc.v:192531$13130_Y - attribute \src "libresoc.v:192532.19-192532.125" - wire $and$libresoc.v:192532$13131_Y - attribute \src "libresoc.v:192533.19-192533.125" - wire $and$libresoc.v:192533$13132_Y - attribute \src "libresoc.v:192535.19-192535.125" - wire $and$libresoc.v:192535$13134_Y - attribute \src "libresoc.v:192536.19-192536.165" - wire width 6 $and$libresoc.v:192536$13135_Y - attribute \src "libresoc.v:192537.19-192537.121" - wire width 6 $and$libresoc.v:192537$13136_Y - attribute \src "libresoc.v:192538.19-192538.127" - wire $and$libresoc.v:192538$13137_Y - attribute \src "libresoc.v:192539.19-192539.127" - wire $and$libresoc.v:192539$13138_Y - attribute \src "libresoc.v:192541.19-192541.127" - wire $and$libresoc.v:192541$13140_Y - attribute \src "libresoc.v:192542.19-192542.127" - wire $and$libresoc.v:192542$13141_Y - attribute \src "libresoc.v:192543.19-192543.127" - wire $and$libresoc.v:192543$13142_Y - attribute \src "libresoc.v:192544.19-192544.127" - wire $and$libresoc.v:192544$13143_Y - attribute \src "libresoc.v:192545.18-192545.110" - wire $and$libresoc.v:192545$13144_Y - attribute \src "libresoc.v:192547.18-192547.98" - wire $and$libresoc.v:192547$13146_Y - attribute \src "libresoc.v:192549.18-192549.100" - wire $and$libresoc.v:192549$13148_Y - attribute \src "libresoc.v:192550.18-192550.182" - wire width 6 $and$libresoc.v:192550$13149_Y - attribute \src "libresoc.v:192552.18-192552.119" - wire width 6 $and$libresoc.v:192552$13151_Y - attribute \src "libresoc.v:192555.18-192555.116" - wire $and$libresoc.v:192555$13154_Y - attribute \src "libresoc.v:192560.18-192560.113" - wire $and$libresoc.v:192560$13159_Y - attribute \src "libresoc.v:192561.18-192561.125" - wire width 6 $and$libresoc.v:192561$13160_Y - attribute \src "libresoc.v:192563.18-192563.112" - wire $and$libresoc.v:192563$13162_Y - attribute \src "libresoc.v:192565.18-192565.126" - wire $and$libresoc.v:192565$13164_Y - attribute \src "libresoc.v:192566.18-192566.126" - wire $and$libresoc.v:192566$13165_Y - attribute \src "libresoc.v:192567.18-192567.117" - wire $and$libresoc.v:192567$13166_Y - attribute \src "libresoc.v:192572.18-192572.130" - wire $and$libresoc.v:192572$13171_Y - attribute \src "libresoc.v:192573.17-192573.123" - wire $and$libresoc.v:192573$13172_Y - attribute \src "libresoc.v:192574.18-192574.124" - wire width 6 $and$libresoc.v:192574$13173_Y - attribute \src "libresoc.v:192576.18-192576.116" - wire $and$libresoc.v:192576$13175_Y - attribute \src "libresoc.v:192577.18-192577.119" - wire $and$libresoc.v:192577$13176_Y - attribute \src "libresoc.v:192578.18-192578.120" - wire $and$libresoc.v:192578$13177_Y - attribute \src "libresoc.v:192579.18-192579.121" - wire $and$libresoc.v:192579$13178_Y - attribute \src "libresoc.v:192580.18-192580.121" - wire $and$libresoc.v:192580$13179_Y - attribute \src "libresoc.v:192581.18-192581.121" - wire $and$libresoc.v:192581$13180_Y - attribute \src "libresoc.v:192588.18-192588.134" - wire $and$libresoc.v:192588$13187_Y - attribute \src "libresoc.v:192562.18-192562.113" - wire $eq$libresoc.v:192562$13161_Y - attribute \src "libresoc.v:192564.18-192564.119" - wire $eq$libresoc.v:192564$13163_Y - attribute \src "libresoc.v:192523.17-192523.113" - wire width 6 $not$libresoc.v:192523$13122_Y - attribute \src "libresoc.v:192527.19-192527.115" - wire width 6 $not$libresoc.v:192527$13126_Y - attribute \src "libresoc.v:192546.18-192546.97" - wire $not$libresoc.v:192546$13145_Y - attribute \src "libresoc.v:192548.18-192548.99" - wire $not$libresoc.v:192548$13147_Y - attribute \src "libresoc.v:192551.18-192551.113" - wire width 6 $not$libresoc.v:192551$13150_Y - attribute \src "libresoc.v:192554.18-192554.106" - wire $not$libresoc.v:192554$13153_Y - attribute \src "libresoc.v:192559.18-192559.120" - wire $not$libresoc.v:192559$13158_Y - attribute \src "libresoc.v:192534.18-192534.118" - wire width 6 $or$libresoc.v:192534$13133_Y - attribute \src "libresoc.v:192558.18-192558.112" - wire $or$libresoc.v:192558$13157_Y - attribute \src "libresoc.v:192568.18-192568.122" - wire $or$libresoc.v:192568$13167_Y - attribute \src "libresoc.v:192569.18-192569.124" - wire $or$libresoc.v:192569$13168_Y - attribute \src "libresoc.v:192570.18-192570.194" - wire width 6 $or$libresoc.v:192570$13169_Y - attribute \src "libresoc.v:192571.18-192571.194" - wire width 6 $or$libresoc.v:192571$13170_Y - attribute \src "libresoc.v:192575.18-192575.120" - wire width 6 $or$libresoc.v:192575$13174_Y - attribute \src "libresoc.v:192540.17-192540.105" - wire $reduce_and$libresoc.v:192540$13139_Y - attribute \src "libresoc.v:192553.18-192553.106" - wire $reduce_or$libresoc.v:192553$13152_Y - attribute \src "libresoc.v:192556.18-192556.113" - wire $reduce_or$libresoc.v:192556$13155_Y - attribute \src "libresoc.v:192557.18-192557.112" - wire $reduce_or$libresoc.v:192557$13156_Y - attribute \src "libresoc.v:192582.18-192582.118" - wire width 64 $ternary$libresoc.v:192582$13181_Y - attribute \src "libresoc.v:192583.18-192583.118" - wire width 64 $ternary$libresoc.v:192583$13182_Y - attribute \src "libresoc.v:192584.18-192584.118" - wire width 64 $ternary$libresoc.v:192584$13183_Y - attribute \src "libresoc.v:192585.18-192585.118" - wire $ternary$libresoc.v:192585$13184_Y - attribute \src "libresoc.v:192586.18-192586.118" - wire width 2 $ternary$libresoc.v:192586$13185_Y - attribute \src "libresoc.v:192587.18-192587.118" - wire width 2 $ternary$libresoc.v:192587$13186_Y + attribute \src "libresoc.v:187050.3-187071.6" + wire width 64 $2\data_r0__o$next[63:0]$12975 + attribute \src "libresoc.v:187050.3-187071.6" + wire $2\data_r0__o_ok$next[0:0]$12976 + attribute \src "libresoc.v:187072.3-187093.6" + wire width 64 $2\data_r1__spr1$next[63:0]$12983 + attribute \src "libresoc.v:187072.3-187093.6" + wire $2\data_r1__spr1_ok$next[0:0]$12984 + attribute \src "libresoc.v:187094.3-187115.6" + wire width 64 $2\data_r2__fast1$next[63:0]$12991 + attribute \src "libresoc.v:187094.3-187115.6" + wire $2\data_r2__fast1_ok$next[0:0]$12992 + attribute \src "libresoc.v:187116.3-187137.6" + wire $2\data_r3__xer_so$next[0:0]$12999 + attribute \src "libresoc.v:187116.3-187137.6" + wire $2\data_r3__xer_so_ok$next[0:0]$13000 + attribute \src "libresoc.v:187138.3-187159.6" + wire width 2 $2\data_r4__xer_ov$next[1:0]$13007 + attribute \src "libresoc.v:187138.3-187159.6" + wire $2\data_r4__xer_ov_ok$next[0:0]$13008 + attribute \src "libresoc.v:187160.3-187181.6" + wire width 2 $2\data_r5__xer_ca$next[1:0]$13015 + attribute \src "libresoc.v:187160.3-187181.6" + wire $2\data_r5__xer_ca_ok$next[0:0]$13016 + attribute \src "libresoc.v:187050.3-187071.6" + wire $3\data_r0__o_ok$next[0:0]$12977 + attribute \src "libresoc.v:187072.3-187093.6" + wire $3\data_r1__spr1_ok$next[0:0]$12985 + attribute \src "libresoc.v:187094.3-187115.6" + wire $3\data_r2__fast1_ok$next[0:0]$12993 + attribute \src "libresoc.v:187116.3-187137.6" + wire $3\data_r3__xer_so_ok$next[0:0]$13001 + attribute \src "libresoc.v:187138.3-187159.6" + wire $3\data_r4__xer_ov_ok$next[0:0]$13009 + attribute \src "libresoc.v:187160.3-187181.6" + wire $3\data_r5__xer_ca_ok$next[0:0]$13017 + attribute \src "libresoc.v:186720.19-186720.133" + wire $and$libresoc.v:186720$12828_Y + attribute \src "libresoc.v:186721.19-186721.183" + wire width 6 $and$libresoc.v:186721$12829_Y + attribute \src "libresoc.v:186722.19-186722.115" + wire width 6 $and$libresoc.v:186722$12830_Y + attribute \src "libresoc.v:186724.19-186724.115" + wire width 6 $and$libresoc.v:186724$12832_Y + attribute \src "libresoc.v:186725.19-186725.125" + wire $and$libresoc.v:186725$12833_Y + attribute \src "libresoc.v:186726.19-186726.125" + wire $and$libresoc.v:186726$12834_Y + attribute \src "libresoc.v:186727.19-186727.125" + wire $and$libresoc.v:186727$12835_Y + attribute \src "libresoc.v:186728.19-186728.125" + wire $and$libresoc.v:186728$12836_Y + attribute \src "libresoc.v:186729.19-186729.125" + wire $and$libresoc.v:186729$12837_Y + attribute \src "libresoc.v:186731.19-186731.125" + wire $and$libresoc.v:186731$12839_Y + attribute \src "libresoc.v:186732.19-186732.165" + wire width 6 $and$libresoc.v:186732$12840_Y + attribute \src "libresoc.v:186733.19-186733.121" + wire width 6 $and$libresoc.v:186733$12841_Y + attribute \src "libresoc.v:186734.19-186734.127" + wire $and$libresoc.v:186734$12842_Y + attribute \src "libresoc.v:186735.19-186735.127" + wire $and$libresoc.v:186735$12843_Y + attribute \src "libresoc.v:186737.19-186737.127" + wire $and$libresoc.v:186737$12845_Y + attribute \src "libresoc.v:186738.19-186738.127" + wire $and$libresoc.v:186738$12846_Y + attribute \src "libresoc.v:186739.19-186739.127" + wire $and$libresoc.v:186739$12847_Y + attribute \src "libresoc.v:186740.19-186740.127" + wire $and$libresoc.v:186740$12848_Y + attribute \src "libresoc.v:186741.18-186741.110" + wire $and$libresoc.v:186741$12849_Y + attribute \src "libresoc.v:186743.18-186743.98" + wire $and$libresoc.v:186743$12851_Y + attribute \src "libresoc.v:186745.18-186745.100" + wire $and$libresoc.v:186745$12853_Y + attribute \src "libresoc.v:186746.18-186746.182" + wire width 6 $and$libresoc.v:186746$12854_Y + attribute \src "libresoc.v:186748.18-186748.119" + wire width 6 $and$libresoc.v:186748$12856_Y + attribute \src "libresoc.v:186751.18-186751.116" + wire $and$libresoc.v:186751$12859_Y + attribute \src "libresoc.v:186756.18-186756.113" + wire $and$libresoc.v:186756$12864_Y + attribute \src "libresoc.v:186757.18-186757.125" + wire width 6 $and$libresoc.v:186757$12865_Y + attribute \src "libresoc.v:186759.18-186759.112" + wire $and$libresoc.v:186759$12867_Y + attribute \src "libresoc.v:186761.18-186761.126" + wire $and$libresoc.v:186761$12869_Y + attribute \src "libresoc.v:186762.18-186762.126" + wire $and$libresoc.v:186762$12870_Y + attribute \src "libresoc.v:186763.18-186763.117" + wire $and$libresoc.v:186763$12871_Y + attribute \src "libresoc.v:186768.18-186768.130" + wire $and$libresoc.v:186768$12876_Y + attribute \src "libresoc.v:186769.17-186769.123" + wire $and$libresoc.v:186769$12877_Y + attribute \src "libresoc.v:186770.18-186770.124" + wire width 6 $and$libresoc.v:186770$12878_Y + attribute \src "libresoc.v:186772.18-186772.116" + wire $and$libresoc.v:186772$12880_Y + attribute \src "libresoc.v:186773.18-186773.119" + wire $and$libresoc.v:186773$12881_Y + attribute \src "libresoc.v:186774.18-186774.120" + wire $and$libresoc.v:186774$12882_Y + attribute \src "libresoc.v:186775.18-186775.121" + wire $and$libresoc.v:186775$12883_Y + attribute \src "libresoc.v:186776.18-186776.121" + wire $and$libresoc.v:186776$12884_Y + attribute \src "libresoc.v:186777.18-186777.121" + wire $and$libresoc.v:186777$12885_Y + attribute \src "libresoc.v:186784.18-186784.134" + wire $and$libresoc.v:186784$12892_Y + attribute \src "libresoc.v:186758.18-186758.113" + wire $eq$libresoc.v:186758$12866_Y + attribute \src "libresoc.v:186760.18-186760.119" + wire $eq$libresoc.v:186760$12868_Y + attribute \src "libresoc.v:186719.17-186719.113" + wire width 6 $not$libresoc.v:186719$12827_Y + attribute \src "libresoc.v:186723.19-186723.115" + wire width 6 $not$libresoc.v:186723$12831_Y + attribute \src "libresoc.v:186742.18-186742.97" + wire $not$libresoc.v:186742$12850_Y + attribute \src "libresoc.v:186744.18-186744.99" + wire $not$libresoc.v:186744$12852_Y + attribute \src "libresoc.v:186747.18-186747.113" + wire width 6 $not$libresoc.v:186747$12855_Y + attribute \src "libresoc.v:186750.18-186750.106" + wire $not$libresoc.v:186750$12858_Y + attribute \src "libresoc.v:186755.18-186755.120" + wire $not$libresoc.v:186755$12863_Y + attribute \src "libresoc.v:186730.18-186730.118" + wire width 6 $or$libresoc.v:186730$12838_Y + attribute \src "libresoc.v:186754.18-186754.112" + wire $or$libresoc.v:186754$12862_Y + attribute \src "libresoc.v:186764.18-186764.122" + wire $or$libresoc.v:186764$12872_Y + attribute \src "libresoc.v:186765.18-186765.124" + wire $or$libresoc.v:186765$12873_Y + attribute \src "libresoc.v:186766.18-186766.194" + wire width 6 $or$libresoc.v:186766$12874_Y + attribute \src "libresoc.v:186767.18-186767.194" + wire width 6 $or$libresoc.v:186767$12875_Y + attribute \src "libresoc.v:186771.18-186771.120" + wire width 6 $or$libresoc.v:186771$12879_Y + attribute \src "libresoc.v:186736.17-186736.105" + wire $reduce_and$libresoc.v:186736$12844_Y + attribute \src "libresoc.v:186749.18-186749.106" + wire $reduce_or$libresoc.v:186749$12857_Y + attribute \src "libresoc.v:186752.18-186752.113" + wire $reduce_or$libresoc.v:186752$12860_Y + attribute \src "libresoc.v:186753.18-186753.112" + wire $reduce_or$libresoc.v:186753$12861_Y + attribute \src "libresoc.v:186778.18-186778.118" + wire width 64 $ternary$libresoc.v:186778$12886_Y + attribute \src "libresoc.v:186779.18-186779.118" + wire width 64 $ternary$libresoc.v:186779$12887_Y + attribute \src "libresoc.v:186780.18-186780.118" + wire width 64 $ternary$libresoc.v:186780$12888_Y + attribute \src "libresoc.v:186781.18-186781.118" + wire $ternary$libresoc.v:186781$12889_Y + attribute \src "libresoc.v:186782.18-186782.118" + wire width 2 $ternary$libresoc.v:186782$12890_Y + attribute \src "libresoc.v:186783.18-186783.118" + wire width 2 $ternary$libresoc.v:186783$12891_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -399556,9 +390111,9 @@ module \spr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 7 \cu_busy_o @@ -399644,7 +390199,7 @@ module \spr0 wire width 2 output 22 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 27 \fast1_ok - attribute \src "libresoc.v:191916.7-191916.15" + attribute \src "libresoc.v:186112.7-186112.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \o_ok @@ -399853,7 +390408,7 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:192524$13123 + cell $and $and$libresoc.v:186720$12828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399861,10 +390416,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:192524$13123_Y + connect \Y $and$libresoc.v:186720$12828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:192525$13124 + cell $and $and$libresoc.v:186721$12829 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -399872,10 +390427,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:192525$13124_Y + connect \Y $and$libresoc.v:186721$12829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:192526$13125 + cell $and $and$libresoc.v:186722$12830 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -399883,10 +390438,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 - connect \Y $and$libresoc.v:192526$13125_Y + connect \Y $and$libresoc.v:186722$12830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:192528$13127 + cell $and $and$libresoc.v:186724$12832 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -399894,10 +390449,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:192528$13127_Y + connect \Y $and$libresoc.v:186724$12832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:192529$13128 + cell $and $and$libresoc.v:186725$12833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399905,10 +390460,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:192529$13128_Y + connect \Y $and$libresoc.v:186725$12833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:192530$13129 + cell $and $and$libresoc.v:186726$12834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399916,10 +390471,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:192530$13129_Y + connect \Y $and$libresoc.v:186726$12834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:192531$13130 + cell $and $and$libresoc.v:186727$12835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399927,10 +390482,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:192531$13130_Y + connect \Y $and$libresoc.v:186727$12835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:192532$13131 + cell $and $and$libresoc.v:186728$12836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399938,10 +390493,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:192532$13131_Y + connect \Y $and$libresoc.v:186728$12836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:192533$13132 + cell $and $and$libresoc.v:186729$12837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399949,10 +390504,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:192533$13132_Y + connect \Y $and$libresoc.v:186729$12837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:192535$13134 + cell $and $and$libresoc.v:186731$12839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399960,10 +390515,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:192535$13134_Y + connect \Y $and$libresoc.v:186731$12839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:192536$13135 + cell $and $and$libresoc.v:186732$12840 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -399971,10 +390526,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } - connect \Y $and$libresoc.v:192536$13135_Y + connect \Y $and$libresoc.v:186732$12840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:192537$13136 + cell $and $and$libresoc.v:186733$12841 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -399982,10 +390537,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:192537$13136_Y + connect \Y $and$libresoc.v:186733$12841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:192538$13137 + cell $and $and$libresoc.v:186734$12842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399993,10 +390548,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:192538$13137_Y + connect \Y $and$libresoc.v:186734$12842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:192539$13138 + cell $and $and$libresoc.v:186735$12843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400004,10 +390559,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:192539$13138_Y + connect \Y $and$libresoc.v:186735$12843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:192541$13140 + cell $and $and$libresoc.v:186737$12845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400015,10 +390570,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:192541$13140_Y + connect \Y $and$libresoc.v:186737$12845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:192542$13141 + cell $and $and$libresoc.v:186738$12846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400026,10 +390581,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:192542$13141_Y + connect \Y $and$libresoc.v:186738$12846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:192543$13142 + cell $and $and$libresoc.v:186739$12847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400037,10 +390592,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:192543$13142_Y + connect \Y $and$libresoc.v:186739$12847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:192544$13143 + cell $and $and$libresoc.v:186740$12848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400048,10 +390603,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o - connect \Y $and$libresoc.v:192544$13143_Y + connect \Y $and$libresoc.v:186740$12848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:192545$13144 + cell $and $and$libresoc.v:186741$12849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400059,10 +390614,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 - connect \Y $and$libresoc.v:192545$13144_Y + connect \Y $and$libresoc.v:186741$12849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:192547$13146 + cell $and $and$libresoc.v:186743$12851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400070,10 +390625,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 - connect \Y $and$libresoc.v:192547$13146_Y + connect \Y $and$libresoc.v:186743$12851_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:192549$13148 + cell $and $and$libresoc.v:186745$12853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400081,10 +390636,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 - connect \Y $and$libresoc.v:192549$13148_Y + connect \Y $and$libresoc.v:186745$12853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:192550$13149 + cell $and $and$libresoc.v:186746$12854 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400092,10 +390647,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:192550$13149_Y + connect \Y $and$libresoc.v:186746$12854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:192552$13151 + cell $and $and$libresoc.v:186748$12856 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400103,10 +390658,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 - connect \Y $and$libresoc.v:192552$13151_Y + connect \Y $and$libresoc.v:186748$12856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:192555$13154 + cell $and $and$libresoc.v:186751$12859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400114,10 +390669,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 - connect \Y $and$libresoc.v:192555$13154_Y + connect \Y $and$libresoc.v:186751$12859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:192560$13159 + cell $and $and$libresoc.v:186756$12864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400125,10 +390680,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 - connect \Y $and$libresoc.v:192560$13159_Y + connect \Y $and$libresoc.v:186756$12864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:192561$13160 + cell $and $and$libresoc.v:186757$12865 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400136,10 +390691,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:192561$13160_Y + connect \Y $and$libresoc.v:186757$12865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:192563$13162 + cell $and $and$libresoc.v:186759$12867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400147,10 +390702,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 - connect \Y $and$libresoc.v:192563$13162_Y + connect \Y $and$libresoc.v:186759$12867_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:192565$13164 + cell $and $and$libresoc.v:186761$12869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400158,10 +390713,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:192565$13164_Y + connect \Y $and$libresoc.v:186761$12869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:192566$13165 + cell $and $and$libresoc.v:186762$12870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400169,10 +390724,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:192566$13165_Y + connect \Y $and$libresoc.v:186762$12870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:192567$13166 + cell $and $and$libresoc.v:186763$12871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400180,10 +390735,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o - connect \Y $and$libresoc.v:192567$13166_Y + connect \Y $and$libresoc.v:186763$12871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:192572$13171 + cell $and $and$libresoc.v:186768$12876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400191,10 +390746,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:192572$13171_Y + connect \Y $and$libresoc.v:186768$12876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:192573$13172 + cell $and $and$libresoc.v:186769$12877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400202,10 +390757,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:192573$13172_Y + connect \Y $and$libresoc.v:186769$12877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:192574$13173 + cell $and $and$libresoc.v:186770$12878 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400213,10 +390768,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:192574$13173_Y + connect \Y $and$libresoc.v:186770$12878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:192576$13175 + cell $and $and$libresoc.v:186772$12880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400224,10 +390779,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:192576$13175_Y + connect \Y $and$libresoc.v:186772$12880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:192577$13176 + cell $and $and$libresoc.v:186773$12881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400235,10 +390790,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:192577$13176_Y + connect \Y $and$libresoc.v:186773$12881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:192578$13177 + cell $and $and$libresoc.v:186774$12882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400246,10 +390801,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:192578$13177_Y + connect \Y $and$libresoc.v:186774$12882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:192579$13178 + cell $and $and$libresoc.v:186775$12883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400257,10 +390812,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:192579$13178_Y + connect \Y $and$libresoc.v:186775$12883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:192580$13179 + cell $and $and$libresoc.v:186776$12884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400268,10 +390823,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:192580$13179_Y + connect \Y $and$libresoc.v:186776$12884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:192581$13180 + cell $and $and$libresoc.v:186777$12885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400279,10 +390834,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:192581$13180_Y + connect \Y $and$libresoc.v:186777$12885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:192588$13187 + cell $and $and$libresoc.v:186784$12892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400290,10 +390845,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:192588$13187_Y + connect \Y $and$libresoc.v:186784$12892_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:192562$13161 + cell $eq $eq$libresoc.v:186758$12866 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400301,10 +390856,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 - connect \Y $eq$libresoc.v:192562$13161_Y + connect \Y $eq$libresoc.v:186758$12866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:192564$13163 + cell $eq $eq$libresoc.v:186760$12868 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400312,66 +390867,66 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:192564$13163_Y + connect \Y $eq$libresoc.v:186760$12868_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:192523$13122 + cell $not $not$libresoc.v:186719$12827 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:192523$13122_Y + connect \Y $not$libresoc.v:186719$12827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:192527$13126 + cell $not $not$libresoc.v:186723$12831 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:192527$13126_Y + connect \Y $not$libresoc.v:186723$12831_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:192546$13145 + cell $not $not$libresoc.v:186742$12850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:192546$13145_Y + connect \Y $not$libresoc.v:186742$12850_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:192548$13147 + cell $not $not$libresoc.v:186744$12852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:192548$13147_Y + connect \Y $not$libresoc.v:186744$12852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:192551$13150 + cell $not $not$libresoc.v:186747$12855 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:192551$13150_Y + connect \Y $not$libresoc.v:186747$12855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:192554$13153 + cell $not $not$libresoc.v:186750$12858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $not$libresoc.v:192554$13153_Y + connect \Y $not$libresoc.v:186750$12858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:192559$13158 + cell $not $not$libresoc.v:186755$12863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:192559$13158_Y + connect \Y $not$libresoc.v:186755$12863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:192534$13133 + cell $or $or$libresoc.v:186730$12838 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400379,10 +390934,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:192534$13133_Y + connect \Y $or$libresoc.v:186730$12838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:192558$13157 + cell $or $or$libresoc.v:186754$12862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400390,10 +390945,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:192558$13157_Y + connect \Y $or$libresoc.v:186754$12862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:192568$13167 + cell $or $or$libresoc.v:186764$12872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400401,10 +390956,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:192568$13167_Y + connect \Y $or$libresoc.v:186764$12872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:192569$13168 + cell $or $or$libresoc.v:186765$12873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -400412,10 +390967,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:192569$13168_Y + connect \Y $or$libresoc.v:186765$12873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:192570$13169 + cell $or $or$libresoc.v:186766$12874 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400423,10 +390978,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:192570$13169_Y + connect \Y $or$libresoc.v:186766$12874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:192571$13170 + cell $or $or$libresoc.v:186767$12875 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400434,10 +390989,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:192571$13170_Y + connect \Y $or$libresoc.v:186767$12875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:192575$13174 + cell $or $or$libresoc.v:186771$12879 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400445,90 +391000,90 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:192575$13174_Y + connect \Y $or$libresoc.v:186771$12879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:192540$13139 + cell $reduce_and $reduce_and$libresoc.v:186736$12844 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 - connect \Y $reduce_and$libresoc.v:192540$13139_Y + connect \Y $reduce_and$libresoc.v:186736$12844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:192553$13152 + cell $reduce_or $reduce_or$libresoc.v:186749$12857 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 - connect \Y $reduce_or$libresoc.v:192553$13152_Y + connect \Y $reduce_or$libresoc.v:186749$12857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:192556$13155 + cell $reduce_or $reduce_or$libresoc.v:186752$12860 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:192556$13155_Y + connect \Y $reduce_or$libresoc.v:186752$12860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:192557$13156 + cell $reduce_or $reduce_or$libresoc.v:186753$12861 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:192557$13156_Y + connect \Y $reduce_or$libresoc.v:186753$12861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:192582$13181 + cell $mux $ternary$libresoc.v:186778$12886 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:192582$13181_Y + connect \Y $ternary$libresoc.v:186778$12886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:192583$13182 + cell $mux $ternary$libresoc.v:186779$12887 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:192583$13182_Y + connect \Y $ternary$libresoc.v:186779$12887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:192584$13183 + cell $mux $ternary$libresoc.v:186780$12888 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:192584$13183_Y + connect \Y $ternary$libresoc.v:186780$12888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:192585$13184 + cell $mux $ternary$libresoc.v:186781$12889 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:192585$13184_Y + connect \Y $ternary$libresoc.v:186781$12889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:192586$13185 + cell $mux $ternary$libresoc.v:186782$12890 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:192586$13185_Y + connect \Y $ternary$libresoc.v:186782$12890_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:192587$13186 + cell $mux $ternary$libresoc.v:186783$12891 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:192587$13186_Y + connect \Y $ternary$libresoc.v:186783$12891_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:192663.14-192669.4" + attribute \src "libresoc.v:186859.14-186865.4" cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -400537,7 +391092,7 @@ module \spr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:192670.12-192699.4" + attribute \src "libresoc.v:186866.12-186895.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -400569,7 +391124,7 @@ module \spr0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:192700.15-192706.4" + attribute \src "libresoc.v:186896.15-186902.4" cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -400578,7 +391133,7 @@ module \spr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:192707.14-192713.4" + attribute \src "libresoc.v:186903.14-186909.4" cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -400587,7 +391142,7 @@ module \spr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:192714.14-192720.4" + attribute \src "libresoc.v:186910.14-186916.4" cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -400596,7 +391151,7 @@ module \spr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:192721.14-192727.4" + attribute \src "libresoc.v:186917.14-186923.4" cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -400605,7 +391160,7 @@ module \spr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:192728.14-192733.4" + attribute \src "libresoc.v:186924.14-186929.4" cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -400613,7 +391168,7 @@ module \spr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:192734.14-192740.4" + attribute \src "libresoc.v:186930.14-186936.4" cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -400621,577 +391176,577 @@ module \spr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:191916.7-191916.20" - process $proc$libresoc.v:191916$13346 + attribute \src "libresoc.v:186112.7-186112.20" + process $proc$libresoc.v:186112$13051 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192052.7-192052.24" - process $proc$libresoc.v:192052$13347 + attribute \src "libresoc.v:186248.7-186248.24" + process $proc$libresoc.v:186248$13052 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:192062.7-192062.26" - process $proc$libresoc.v:192062$13348 + attribute \src "libresoc.v:186258.7-186258.26" + process $proc$libresoc.v:186258$13053 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:192070.7-192070.25" - process $proc$libresoc.v:192070$13349 + attribute \src "libresoc.v:186266.7-186266.25" + process $proc$libresoc.v:186266$13054 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:192114.14-192114.49" - process $proc$libresoc.v:192114$13350 + attribute \src "libresoc.v:186310.14-186310.49" + process $proc$libresoc.v:186310$13055 assign { } { } assign $1\alu_spr0_spr_op__fn_unit[12:0] 13'0000000000000 sync always sync init update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[12:0] end - attribute \src "libresoc.v:192118.14-192118.43" - process $proc$libresoc.v:192118$13351 + attribute \src "libresoc.v:186314.14-186314.43" + process $proc$libresoc.v:186314$13056 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:192196.13-192196.47" - process $proc$libresoc.v:192196$13352 + attribute \src "libresoc.v:186392.13-186392.47" + process $proc$libresoc.v:186392$13057 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:192200.7-192200.39" - process $proc$libresoc.v:192200$13353 + attribute \src "libresoc.v:186396.7-186396.39" + process $proc$libresoc.v:186396$13058 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:192218.7-192218.27" - process $proc$libresoc.v:192218$13354 + attribute \src "libresoc.v:186414.7-186414.27" + process $proc$libresoc.v:186414$13059 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:192250.14-192250.47" - process $proc$libresoc.v:192250$13355 + attribute \src "libresoc.v:186446.14-186446.47" + process $proc$libresoc.v:186446$13060 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:192254.7-192254.27" - process $proc$libresoc.v:192254$13356 + attribute \src "libresoc.v:186450.7-186450.27" + process $proc$libresoc.v:186450$13061 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:192258.14-192258.50" - process $proc$libresoc.v:192258$13357 + attribute \src "libresoc.v:186454.14-186454.50" + process $proc$libresoc.v:186454$13062 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end - attribute \src "libresoc.v:192262.7-192262.30" - process $proc$libresoc.v:192262$13358 + attribute \src "libresoc.v:186458.7-186458.30" + process $proc$libresoc.v:186458$13063 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:192266.14-192266.51" - process $proc$libresoc.v:192266$13359 + attribute \src "libresoc.v:186462.14-186462.51" + process $proc$libresoc.v:186462$13064 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end - attribute \src "libresoc.v:192270.7-192270.31" - process $proc$libresoc.v:192270$13360 + attribute \src "libresoc.v:186466.7-186466.31" + process $proc$libresoc.v:186466$13065 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:192274.7-192274.29" - process $proc$libresoc.v:192274$13361 + attribute \src "libresoc.v:186470.7-186470.29" + process $proc$libresoc.v:186470$13066 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:192278.7-192278.32" - process $proc$libresoc.v:192278$13362 + attribute \src "libresoc.v:186474.7-186474.32" + process $proc$libresoc.v:186474$13067 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:192282.13-192282.35" - process $proc$libresoc.v:192282$13363 + attribute \src "libresoc.v:186478.13-186478.35" + process $proc$libresoc.v:186478$13068 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:192286.7-192286.32" - process $proc$libresoc.v:192286$13364 + attribute \src "libresoc.v:186482.7-186482.32" + process $proc$libresoc.v:186482$13069 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:192290.13-192290.35" - process $proc$libresoc.v:192290$13365 + attribute \src "libresoc.v:186486.13-186486.35" + process $proc$libresoc.v:186486$13070 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:192294.7-192294.32" - process $proc$libresoc.v:192294$13366 + attribute \src "libresoc.v:186490.7-186490.32" + process $proc$libresoc.v:186490$13071 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:192322.7-192322.25" - process $proc$libresoc.v:192322$13367 + attribute \src "libresoc.v:186518.7-186518.25" + process $proc$libresoc.v:186518$13072 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:192326.7-192326.25" - process $proc$libresoc.v:192326$13368 + attribute \src "libresoc.v:186522.7-186522.25" + process $proc$libresoc.v:186522$13073 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:192426.13-192426.31" - process $proc$libresoc.v:192426$13369 + attribute \src "libresoc.v:186622.13-186622.31" + process $proc$libresoc.v:186622$13074 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end - attribute \src "libresoc.v:192434.13-192434.32" - process $proc$libresoc.v:192434$13370 + attribute \src "libresoc.v:186630.13-186630.32" + process $proc$libresoc.v:186630$13075 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end - attribute \src "libresoc.v:192438.13-192438.32" - process $proc$libresoc.v:192438$13371 + attribute \src "libresoc.v:186634.13-186634.32" + process $proc$libresoc.v:186634$13076 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end - attribute \src "libresoc.v:192450.7-192450.26" - process $proc$libresoc.v:192450$13372 + attribute \src "libresoc.v:186646.7-186646.26" + process $proc$libresoc.v:186646$13077 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:192454.7-192454.26" - process $proc$libresoc.v:192454$13373 + attribute \src "libresoc.v:186650.7-186650.26" + process $proc$libresoc.v:186650$13078 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:192458.7-192458.25" - process $proc$libresoc.v:192458$13374 + attribute \src "libresoc.v:186654.7-186654.25" + process $proc$libresoc.v:186654$13079 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:192462.7-192462.25" - process $proc$libresoc.v:192462$13375 + attribute \src "libresoc.v:186658.7-186658.25" + process $proc$libresoc.v:186658$13080 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:192484.13-192484.32" - process $proc$libresoc.v:192484$13376 + attribute \src "libresoc.v:186680.13-186680.32" + process $proc$libresoc.v:186680$13081 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:192488.13-192488.32" - process $proc$libresoc.v:192488$13377 + attribute \src "libresoc.v:186684.13-186684.32" + process $proc$libresoc.v:186684$13082 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:192492.14-192492.43" - process $proc$libresoc.v:192492$13378 + attribute \src "libresoc.v:186688.14-186688.43" + process $proc$libresoc.v:186688$13083 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:192496.14-192496.43" - process $proc$libresoc.v:192496$13379 + attribute \src "libresoc.v:186692.14-186692.43" + process $proc$libresoc.v:186692$13084 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:192500.14-192500.43" - process $proc$libresoc.v:192500$13380 + attribute \src "libresoc.v:186696.14-186696.43" + process $proc$libresoc.v:186696$13085 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:192504.7-192504.20" - process $proc$libresoc.v:192504$13381 + attribute \src "libresoc.v:186700.7-186700.20" + process $proc$libresoc.v:186700$13086 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:192508.13-192508.26" - process $proc$libresoc.v:192508$13382 + attribute \src "libresoc.v:186704.13-186704.26" + process $proc$libresoc.v:186704$13087 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:192512.13-192512.26" - process $proc$libresoc.v:192512$13383 + attribute \src "libresoc.v:186708.13-186708.26" + process $proc$libresoc.v:186708$13088 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end - attribute \src "libresoc.v:192589.3-192590.39" - process $proc$libresoc.v:192589$13188 + attribute \src "libresoc.v:186785.3-186786.39" + process $proc$libresoc.v:186785$12893 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:192591.3-192592.43" - process $proc$libresoc.v:192591$13189 + attribute \src "libresoc.v:186787.3-186788.43" + process $proc$libresoc.v:186787$12894 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:192593.3-192594.29" - process $proc$libresoc.v:192593$13190 + attribute \src "libresoc.v:186789.3-186790.29" + process $proc$libresoc.v:186789$12895 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end - attribute \src "libresoc.v:192595.3-192596.29" - process $proc$libresoc.v:192595$13191 + attribute \src "libresoc.v:186791.3-186792.29" + process $proc$libresoc.v:186791$12896 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:192597.3-192598.29" - process $proc$libresoc.v:192597$13192 + attribute \src "libresoc.v:186793.3-186794.29" + process $proc$libresoc.v:186793$12897 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:192599.3-192600.29" - process $proc$libresoc.v:192599$13193 + attribute \src "libresoc.v:186795.3-186796.29" + process $proc$libresoc.v:186795$12898 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:192601.3-192602.29" - process $proc$libresoc.v:192601$13194 + attribute \src "libresoc.v:186797.3-186798.29" + process $proc$libresoc.v:186797$12899 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:192603.3-192604.29" - process $proc$libresoc.v:192603$13195 + attribute \src "libresoc.v:186799.3-186800.29" + process $proc$libresoc.v:186799$12900 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:192605.3-192606.47" - process $proc$libresoc.v:192605$13196 + attribute \src "libresoc.v:186801.3-186802.47" + process $proc$libresoc.v:186801$12901 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:192607.3-192608.53" - process $proc$libresoc.v:192607$13197 + attribute \src "libresoc.v:186803.3-186804.53" + process $proc$libresoc.v:186803$12902 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:192609.3-192610.47" - process $proc$libresoc.v:192609$13198 + attribute \src "libresoc.v:186805.3-186806.47" + process $proc$libresoc.v:186805$12903 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:192611.3-192612.53" - process $proc$libresoc.v:192611$13199 + attribute \src "libresoc.v:186807.3-186808.53" + process $proc$libresoc.v:186807$12904 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:192613.3-192614.47" - process $proc$libresoc.v:192613$13200 + attribute \src "libresoc.v:186809.3-186810.47" + process $proc$libresoc.v:186809$12905 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:192615.3-192616.53" - process $proc$libresoc.v:192615$13201 + attribute \src "libresoc.v:186811.3-186812.53" + process $proc$libresoc.v:186811$12906 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:192617.3-192618.45" - process $proc$libresoc.v:192617$13202 + attribute \src "libresoc.v:186813.3-186814.45" + process $proc$libresoc.v:186813$12907 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end - attribute \src "libresoc.v:192619.3-192620.51" - process $proc$libresoc.v:192619$13203 + attribute \src "libresoc.v:186815.3-186816.51" + process $proc$libresoc.v:186815$12908 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:192621.3-192622.43" - process $proc$libresoc.v:192621$13204 + attribute \src "libresoc.v:186817.3-186818.43" + process $proc$libresoc.v:186817$12909 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end - attribute \src "libresoc.v:192623.3-192624.49" - process $proc$libresoc.v:192623$13205 + attribute \src "libresoc.v:186819.3-186820.49" + process $proc$libresoc.v:186819$12910 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:192625.3-192626.37" - process $proc$libresoc.v:192625$13206 + attribute \src "libresoc.v:186821.3-186822.37" + process $proc$libresoc.v:186821$12911 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:192627.3-192628.43" - process $proc$libresoc.v:192627$13207 + attribute \src "libresoc.v:186823.3-186824.43" + process $proc$libresoc.v:186823$12912 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:192629.3-192630.69" - process $proc$libresoc.v:192629$13208 + attribute \src "libresoc.v:186825.3-186826.69" + process $proc$libresoc.v:186825$12913 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:192631.3-192632.65" - process $proc$libresoc.v:192631$13209 + attribute \src "libresoc.v:186827.3-186828.65" + process $proc$libresoc.v:186827$12914 assign { } { } assign $0\alu_spr0_spr_op__fn_unit[12:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[12:0] end - attribute \src "libresoc.v:192633.3-192634.59" - process $proc$libresoc.v:192633$13210 + attribute \src "libresoc.v:186829.3-186830.59" + process $proc$libresoc.v:186829$12915 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:192635.3-192636.67" - process $proc$libresoc.v:192635$13211 + attribute \src "libresoc.v:186831.3-186832.67" + process $proc$libresoc.v:186831$12916 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:192637.3-192638.39" - process $proc$libresoc.v:192637$13212 + attribute \src "libresoc.v:186833.3-186834.39" + process $proc$libresoc.v:186833$12917 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end - attribute \src "libresoc.v:192639.3-192640.39" - process $proc$libresoc.v:192639$13213 + attribute \src "libresoc.v:186835.3-186836.39" + process $proc$libresoc.v:186835$12918 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end - attribute \src "libresoc.v:192641.3-192642.39" - process $proc$libresoc.v:192641$13214 + attribute \src "libresoc.v:186837.3-186838.39" + process $proc$libresoc.v:186837$12919 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:192643.3-192644.39" - process $proc$libresoc.v:192643$13215 + attribute \src "libresoc.v:186839.3-186840.39" + process $proc$libresoc.v:186839$12920 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:192645.3-192646.39" - process $proc$libresoc.v:192645$13216 + attribute \src "libresoc.v:186841.3-186842.39" + process $proc$libresoc.v:186841$12921 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:192647.3-192648.39" - process $proc$libresoc.v:192647$13217 + attribute \src "libresoc.v:186843.3-186844.39" + process $proc$libresoc.v:186843$12922 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:192649.3-192650.39" - process $proc$libresoc.v:192649$13218 + attribute \src "libresoc.v:186845.3-186846.39" + process $proc$libresoc.v:186845$12923 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:192651.3-192652.39" - process $proc$libresoc.v:192651$13219 + attribute \src "libresoc.v:186847.3-186848.39" + process $proc$libresoc.v:186847$12924 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:192653.3-192654.41" - process $proc$libresoc.v:192653$13220 + attribute \src "libresoc.v:186849.3-186850.41" + process $proc$libresoc.v:186849$12925 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:192655.3-192656.41" - process $proc$libresoc.v:192655$13221 + attribute \src "libresoc.v:186851.3-186852.41" + process $proc$libresoc.v:186851$12926 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:192657.3-192658.37" - process $proc$libresoc.v:192657$13222 + attribute \src "libresoc.v:186853.3-186854.37" + process $proc$libresoc.v:186853$12927 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end - attribute \src "libresoc.v:192659.3-192660.40" - process $proc$libresoc.v:192659$13223 + attribute \src "libresoc.v:186855.3-186856.40" + process $proc$libresoc.v:186855$12928 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:192661.3-192662.25" - process $proc$libresoc.v:192661$13224 + attribute \src "libresoc.v:186857.3-186858.25" + process $proc$libresoc.v:186857$12929 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:192741.3-192750.6" - process $proc$libresoc.v:192741$13225 + attribute \src "libresoc.v:186937.3-186946.6" + process $proc$libresoc.v:186937$12930 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:192742.5-192742.29" + attribute \src "libresoc.v:186938.5-186938.29" switch \initial - attribute \src "libresoc.v:192742.9-192742.17" + attribute \src "libresoc.v:186938.9-186938.17" case 1'1 case end @@ -401207,14 +391762,14 @@ module \spr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:192751.3-192759.6" - process $proc$libresoc.v:192751$13226 + attribute \src "libresoc.v:186947.3-186955.6" + process $proc$libresoc.v:186947$12931 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$13227 $1\rok_l_s_rdok$next[0:0]$13228 - attribute \src "libresoc.v:192752.5-192752.29" + assign $0\rok_l_s_rdok$next[0:0]$12932 $1\rok_l_s_rdok$next[0:0]$12933 + attribute \src "libresoc.v:186948.5-186948.29" switch \initial - attribute \src "libresoc.v:192752.9-192752.17" + attribute \src "libresoc.v:186948.9-186948.17" case 1'1 case end @@ -401223,21 +391778,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$13228 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12933 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$13228 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12933 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13227 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12932 end - attribute \src "libresoc.v:192760.3-192768.6" - process $proc$libresoc.v:192760$13229 + attribute \src "libresoc.v:186956.3-186964.6" + process $proc$libresoc.v:186956$12934 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$13230 $1\rok_l_r_rdok$next[0:0]$13231 - attribute \src "libresoc.v:192761.5-192761.29" + assign $0\rok_l_r_rdok$next[0:0]$12935 $1\rok_l_r_rdok$next[0:0]$12936 + attribute \src "libresoc.v:186957.5-186957.29" switch \initial - attribute \src "libresoc.v:192761.9-192761.17" + attribute \src "libresoc.v:186957.9-186957.17" case 1'1 case end @@ -401246,21 +391801,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$13231 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12936 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$13231 \$68 + assign $1\rok_l_r_rdok$next[0:0]$12936 \$68 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13230 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12935 end - attribute \src "libresoc.v:192769.3-192777.6" - process $proc$libresoc.v:192769$13232 + attribute \src "libresoc.v:186965.3-186973.6" + process $proc$libresoc.v:186965$12937 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$13233 $1\rst_l_s_rst$next[0:0]$13234 - attribute \src "libresoc.v:192770.5-192770.29" + assign $0\rst_l_s_rst$next[0:0]$12938 $1\rst_l_s_rst$next[0:0]$12939 + attribute \src "libresoc.v:186966.5-186966.29" switch \initial - attribute \src "libresoc.v:192770.9-192770.17" + attribute \src "libresoc.v:186966.9-186966.17" case 1'1 case end @@ -401269,21 +391824,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$13234 1'0 + assign $1\rst_l_s_rst$next[0:0]$12939 1'0 case - assign $1\rst_l_s_rst$next[0:0]$13234 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12939 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13233 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12938 end - attribute \src "libresoc.v:192778.3-192786.6" - process $proc$libresoc.v:192778$13235 + attribute \src "libresoc.v:186974.3-186982.6" + process $proc$libresoc.v:186974$12940 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$13236 $1\rst_l_r_rst$next[0:0]$13237 - attribute \src "libresoc.v:192779.5-192779.29" + assign $0\rst_l_r_rst$next[0:0]$12941 $1\rst_l_r_rst$next[0:0]$12942 + attribute \src "libresoc.v:186975.5-186975.29" switch \initial - attribute \src "libresoc.v:192779.9-192779.17" + attribute \src "libresoc.v:186975.9-186975.17" case 1'1 case end @@ -401292,21 +391847,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$13237 1'1 + assign $1\rst_l_r_rst$next[0:0]$12942 1'1 case - assign $1\rst_l_r_rst$next[0:0]$13237 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12942 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13236 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12941 end - attribute \src "libresoc.v:192787.3-192795.6" - process $proc$libresoc.v:192787$13238 + attribute \src "libresoc.v:186983.3-186991.6" + process $proc$libresoc.v:186983$12943 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$13239 $1\opc_l_s_opc$next[0:0]$13240 - attribute \src "libresoc.v:192788.5-192788.29" + assign $0\opc_l_s_opc$next[0:0]$12944 $1\opc_l_s_opc$next[0:0]$12945 + attribute \src "libresoc.v:186984.5-186984.29" switch \initial - attribute \src "libresoc.v:192788.9-192788.17" + attribute \src "libresoc.v:186984.9-186984.17" case 1'1 case end @@ -401315,21 +391870,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$13240 1'0 + assign $1\opc_l_s_opc$next[0:0]$12945 1'0 case - assign $1\opc_l_s_opc$next[0:0]$13240 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12945 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13239 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12944 end - attribute \src "libresoc.v:192796.3-192804.6" - process $proc$libresoc.v:192796$13241 + attribute \src "libresoc.v:186992.3-187000.6" + process $proc$libresoc.v:186992$12946 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$13242 $1\opc_l_r_opc$next[0:0]$13243 - attribute \src "libresoc.v:192797.5-192797.29" + assign $0\opc_l_r_opc$next[0:0]$12947 $1\opc_l_r_opc$next[0:0]$12948 + attribute \src "libresoc.v:186993.5-186993.29" switch \initial - attribute \src "libresoc.v:192797.9-192797.17" + attribute \src "libresoc.v:186993.9-186993.17" case 1'1 case end @@ -401338,21 +391893,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$13243 1'1 + assign $1\opc_l_r_opc$next[0:0]$12948 1'1 case - assign $1\opc_l_r_opc$next[0:0]$13243 \req_done + assign $1\opc_l_r_opc$next[0:0]$12948 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13242 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12947 end - attribute \src "libresoc.v:192805.3-192813.6" - process $proc$libresoc.v:192805$13244 + attribute \src "libresoc.v:187001.3-187009.6" + process $proc$libresoc.v:187001$12949 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$13245 $1\src_l_s_src$next[5:0]$13246 - attribute \src "libresoc.v:192806.5-192806.29" + assign $0\src_l_s_src$next[5:0]$12950 $1\src_l_s_src$next[5:0]$12951 + attribute \src "libresoc.v:187002.5-187002.29" switch \initial - attribute \src "libresoc.v:192806.9-192806.17" + attribute \src "libresoc.v:187002.9-187002.17" case 1'1 case end @@ -401361,21 +391916,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$13246 6'000000 + assign $1\src_l_s_src$next[5:0]$12951 6'000000 case - assign $1\src_l_s_src$next[5:0]$13246 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$12951 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$13245 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12950 end - attribute \src "libresoc.v:192814.3-192822.6" - process $proc$libresoc.v:192814$13247 + attribute \src "libresoc.v:187010.3-187018.6" + process $proc$libresoc.v:187010$12952 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$13248 $1\src_l_r_src$next[5:0]$13249 - attribute \src "libresoc.v:192815.5-192815.29" + assign $0\src_l_r_src$next[5:0]$12953 $1\src_l_r_src$next[5:0]$12954 + attribute \src "libresoc.v:187011.5-187011.29" switch \initial - attribute \src "libresoc.v:192815.9-192815.17" + attribute \src "libresoc.v:187011.9-187011.17" case 1'1 case end @@ -401384,21 +391939,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$13249 6'111111 + assign $1\src_l_r_src$next[5:0]$12954 6'111111 case - assign $1\src_l_r_src$next[5:0]$13249 \reset_r + assign $1\src_l_r_src$next[5:0]$12954 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$13248 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12953 end - attribute \src "libresoc.v:192823.3-192831.6" - process $proc$libresoc.v:192823$13250 + attribute \src "libresoc.v:187019.3-187027.6" + process $proc$libresoc.v:187019$12955 assign { } { } assign { } { } - assign $0\req_l_s_req$next[5:0]$13251 $1\req_l_s_req$next[5:0]$13252 - attribute \src "libresoc.v:192824.5-192824.29" + assign $0\req_l_s_req$next[5:0]$12956 $1\req_l_s_req$next[5:0]$12957 + attribute \src "libresoc.v:187020.5-187020.29" switch \initial - attribute \src "libresoc.v:192824.9-192824.17" + attribute \src "libresoc.v:187020.9-187020.17" case 1'1 case end @@ -401407,21 +391962,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[5:0]$13252 6'000000 + assign $1\req_l_s_req$next[5:0]$12957 6'000000 case - assign $1\req_l_s_req$next[5:0]$13252 \$70 + assign $1\req_l_s_req$next[5:0]$12957 \$70 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$13251 + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12956 end - attribute \src "libresoc.v:192832.3-192840.6" - process $proc$libresoc.v:192832$13253 + attribute \src "libresoc.v:187028.3-187036.6" + process $proc$libresoc.v:187028$12958 assign { } { } assign { } { } - assign $0\req_l_r_req$next[5:0]$13254 $1\req_l_r_req$next[5:0]$13255 - attribute \src "libresoc.v:192833.5-192833.29" + assign $0\req_l_r_req$next[5:0]$12959 $1\req_l_r_req$next[5:0]$12960 + attribute \src "libresoc.v:187029.5-187029.29" switch \initial - attribute \src "libresoc.v:192833.9-192833.17" + attribute \src "libresoc.v:187029.9-187029.17" case 1'1 case end @@ -401430,15 +391985,15 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[5:0]$13255 6'111111 + assign $1\req_l_r_req$next[5:0]$12960 6'111111 case - assign $1\req_l_r_req$next[5:0]$13255 \$72 + assign $1\req_l_r_req$next[5:0]$12960 \$72 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$13254 + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12959 end - attribute \src "libresoc.v:192841.3-192853.6" - process $proc$libresoc.v:192841$13256 + attribute \src "libresoc.v:187037.3-187049.6" + process $proc$libresoc.v:187037$12961 assign { } { } assign { } { } assign { } { } @@ -401447,13 +392002,13 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[12:0]$13257 $1\alu_spr0_spr_op__fn_unit$next[12:0]$13261 - assign $0\alu_spr0_spr_op__insn$next[31:0]$13258 $1\alu_spr0_spr_op__insn$next[31:0]$13262 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$13259 $1\alu_spr0_spr_op__insn_type$next[6:0]$13263 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$13260 $1\alu_spr0_spr_op__is_32bit$next[0:0]$13264 - attribute \src "libresoc.v:192842.5-192842.29" + assign $0\alu_spr0_spr_op__fn_unit$next[12:0]$12962 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12966 + assign $0\alu_spr0_spr_op__insn$next[31:0]$12963 $1\alu_spr0_spr_op__insn$next[31:0]$12967 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12964 $1\alu_spr0_spr_op__insn_type$next[6:0]$12968 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12965 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12969 + attribute \src "libresoc.v:187038.5-187038.29" switch \initial - attribute \src "libresoc.v:192842.9-192842.17" + attribute \src "libresoc.v:187038.9-187038.17" case 1'1 case end @@ -401465,33 +392020,33 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$13264 $1\alu_spr0_spr_op__insn$next[31:0]$13262 $1\alu_spr0_spr_op__fn_unit$next[12:0]$13261 $1\alu_spr0_spr_op__insn_type$next[6:0]$13263 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12969 $1\alu_spr0_spr_op__insn$next[31:0]$12967 $1\alu_spr0_spr_op__fn_unit$next[12:0]$12966 $1\alu_spr0_spr_op__insn_type$next[6:0]$12968 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } case - assign $1\alu_spr0_spr_op__fn_unit$next[12:0]$13261 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$13262 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$13263 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$13264 \alu_spr0_spr_op__is_32bit + assign $1\alu_spr0_spr_op__fn_unit$next[12:0]$12966 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$12967 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12968 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12969 \alu_spr0_spr_op__is_32bit end sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[12:0]$13257 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$13258 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$13259 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$13260 + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[12:0]$12962 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12963 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12964 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12965 end - attribute \src "libresoc.v:192854.3-192875.6" - process $proc$libresoc.v:192854$13265 + attribute \src "libresoc.v:187050.3-187071.6" + process $proc$libresoc.v:187050$12970 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$13266 $2\data_r0__o$next[63:0]$13270 + assign $0\data_r0__o$next[63:0]$12971 $2\data_r0__o$next[63:0]$12975 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$13267 $3\data_r0__o_ok$next[0:0]$13272 - attribute \src "libresoc.v:192855.5-192855.29" + assign $0\data_r0__o_ok$next[0:0]$12972 $3\data_r0__o_ok$next[0:0]$12977 + attribute \src "libresoc.v:187051.5-187051.29" switch \initial - attribute \src "libresoc.v:192855.9-192855.17" + attribute \src "libresoc.v:187051.9-187051.17" case 1'1 case end @@ -401501,10 +392056,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$13269 $1\data_r0__o$next[63:0]$13268 } { \o_ok \alu_spr0_o } + assign { $1\data_r0__o_ok$next[0:0]$12974 $1\data_r0__o$next[63:0]$12973 } { \o_ok \alu_spr0_o } case - assign $1\data_r0__o$next[63:0]$13268 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$13269 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12973 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12974 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -401512,38 +392067,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$13271 $2\data_r0__o$next[63:0]$13270 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12976 $2\data_r0__o$next[63:0]$12975 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$13270 $1\data_r0__o$next[63:0]$13268 - assign $2\data_r0__o_ok$next[0:0]$13271 $1\data_r0__o_ok$next[0:0]$13269 + assign $2\data_r0__o$next[63:0]$12975 $1\data_r0__o$next[63:0]$12973 + assign $2\data_r0__o_ok$next[0:0]$12976 $1\data_r0__o_ok$next[0:0]$12974 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$13272 1'0 + assign $3\data_r0__o_ok$next[0:0]$12977 1'0 case - assign $3\data_r0__o_ok$next[0:0]$13272 $2\data_r0__o_ok$next[0:0]$13271 + assign $3\data_r0__o_ok$next[0:0]$12977 $2\data_r0__o_ok$next[0:0]$12976 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$13266 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13267 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12971 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12972 end - attribute \src "libresoc.v:192876.3-192897.6" - process $proc$libresoc.v:192876$13273 + attribute \src "libresoc.v:187072.3-187093.6" + process $proc$libresoc.v:187072$12978 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__spr1$next[63:0]$13274 $2\data_r1__spr1$next[63:0]$13278 + assign $0\data_r1__spr1$next[63:0]$12979 $2\data_r1__spr1$next[63:0]$12983 assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$13275 $3\data_r1__spr1_ok$next[0:0]$13280 - attribute \src "libresoc.v:192877.5-192877.29" + assign $0\data_r1__spr1_ok$next[0:0]$12980 $3\data_r1__spr1_ok$next[0:0]$12985 + attribute \src "libresoc.v:187073.5-187073.29" switch \initial - attribute \src "libresoc.v:192877.9-192877.17" + attribute \src "libresoc.v:187073.9-187073.17" case 1'1 case end @@ -401553,10 +392108,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$13277 $1\data_r1__spr1$next[63:0]$13276 } { \spr1_ok \alu_spr0_spr1 } + assign { $1\data_r1__spr1_ok$next[0:0]$12982 $1\data_r1__spr1$next[63:0]$12981 } { \spr1_ok \alu_spr0_spr1 } case - assign $1\data_r1__spr1$next[63:0]$13276 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$13277 \data_r1__spr1_ok + assign $1\data_r1__spr1$next[63:0]$12981 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$12982 \data_r1__spr1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -401564,38 +392119,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$13279 $2\data_r1__spr1$next[63:0]$13278 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__spr1_ok$next[0:0]$12984 $2\data_r1__spr1$next[63:0]$12983 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__spr1$next[63:0]$13278 $1\data_r1__spr1$next[63:0]$13276 - assign $2\data_r1__spr1_ok$next[0:0]$13279 $1\data_r1__spr1_ok$next[0:0]$13277 + assign $2\data_r1__spr1$next[63:0]$12983 $1\data_r1__spr1$next[63:0]$12981 + assign $2\data_r1__spr1_ok$next[0:0]$12984 $1\data_r1__spr1_ok$next[0:0]$12982 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$13280 1'0 + assign $3\data_r1__spr1_ok$next[0:0]$12985 1'0 case - assign $3\data_r1__spr1_ok$next[0:0]$13280 $2\data_r1__spr1_ok$next[0:0]$13279 + assign $3\data_r1__spr1_ok$next[0:0]$12985 $2\data_r1__spr1_ok$next[0:0]$12984 end sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$13274 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$13275 + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12979 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12980 end - attribute \src "libresoc.v:192898.3-192919.6" - process $proc$libresoc.v:192898$13281 + attribute \src "libresoc.v:187094.3-187115.6" + process $proc$libresoc.v:187094$12986 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast1$next[63:0]$13282 $2\data_r2__fast1$next[63:0]$13286 + assign $0\data_r2__fast1$next[63:0]$12987 $2\data_r2__fast1$next[63:0]$12991 assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$13283 $3\data_r2__fast1_ok$next[0:0]$13288 - attribute \src "libresoc.v:192899.5-192899.29" + assign $0\data_r2__fast1_ok$next[0:0]$12988 $3\data_r2__fast1_ok$next[0:0]$12993 + attribute \src "libresoc.v:187095.5-187095.29" switch \initial - attribute \src "libresoc.v:192899.9-192899.17" + attribute \src "libresoc.v:187095.9-187095.17" case 1'1 case end @@ -401605,10 +392160,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$13285 $1\data_r2__fast1$next[63:0]$13284 } { \fast1_ok \alu_spr0_fast1 } + assign { $1\data_r2__fast1_ok$next[0:0]$12990 $1\data_r2__fast1$next[63:0]$12989 } { \fast1_ok \alu_spr0_fast1 } case - assign $1\data_r2__fast1$next[63:0]$13284 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$13285 \data_r2__fast1_ok + assign $1\data_r2__fast1$next[63:0]$12989 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$12990 \data_r2__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -401616,38 +392171,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$13287 $2\data_r2__fast1$next[63:0]$13286 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast1_ok$next[0:0]$12992 $2\data_r2__fast1$next[63:0]$12991 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast1$next[63:0]$13286 $1\data_r2__fast1$next[63:0]$13284 - assign $2\data_r2__fast1_ok$next[0:0]$13287 $1\data_r2__fast1_ok$next[0:0]$13285 + assign $2\data_r2__fast1$next[63:0]$12991 $1\data_r2__fast1$next[63:0]$12989 + assign $2\data_r2__fast1_ok$next[0:0]$12992 $1\data_r2__fast1_ok$next[0:0]$12990 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$13288 1'0 + assign $3\data_r2__fast1_ok$next[0:0]$12993 1'0 case - assign $3\data_r2__fast1_ok$next[0:0]$13288 $2\data_r2__fast1_ok$next[0:0]$13287 + assign $3\data_r2__fast1_ok$next[0:0]$12993 $2\data_r2__fast1_ok$next[0:0]$12992 end sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$13282 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$13283 + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12987 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12988 end - attribute \src "libresoc.v:192920.3-192941.6" - process $proc$libresoc.v:192920$13289 + attribute \src "libresoc.v:187116.3-187137.6" + process $proc$libresoc.v:187116$12994 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$13290 $2\data_r3__xer_so$next[0:0]$13294 + assign $0\data_r3__xer_so$next[0:0]$12995 $2\data_r3__xer_so$next[0:0]$12999 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$13291 $3\data_r3__xer_so_ok$next[0:0]$13296 - attribute \src "libresoc.v:192921.5-192921.29" + assign $0\data_r3__xer_so_ok$next[0:0]$12996 $3\data_r3__xer_so_ok$next[0:0]$13001 + attribute \src "libresoc.v:187117.5-187117.29" switch \initial - attribute \src "libresoc.v:192921.9-192921.17" + attribute \src "libresoc.v:187117.9-187117.17" case 1'1 case end @@ -401657,10 +392212,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$13293 $1\data_r3__xer_so$next[0:0]$13292 } { \xer_so_ok \alu_spr0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$12998 $1\data_r3__xer_so$next[0:0]$12997 } { \xer_so_ok \alu_spr0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$13292 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$13293 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$12997 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$12998 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -401668,38 +392223,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$13295 $2\data_r3__xer_so$next[0:0]$13294 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$13000 $2\data_r3__xer_so$next[0:0]$12999 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$13294 $1\data_r3__xer_so$next[0:0]$13292 - assign $2\data_r3__xer_so_ok$next[0:0]$13295 $1\data_r3__xer_so_ok$next[0:0]$13293 + assign $2\data_r3__xer_so$next[0:0]$12999 $1\data_r3__xer_so$next[0:0]$12997 + assign $2\data_r3__xer_so_ok$next[0:0]$13000 $1\data_r3__xer_so_ok$next[0:0]$12998 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$13296 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$13001 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$13296 $2\data_r3__xer_so_ok$next[0:0]$13295 + assign $3\data_r3__xer_so_ok$next[0:0]$13001 $2\data_r3__xer_so_ok$next[0:0]$13000 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$13290 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$13291 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12995 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12996 end - attribute \src "libresoc.v:192942.3-192963.6" - process $proc$libresoc.v:192942$13297 + attribute \src "libresoc.v:187138.3-187159.6" + process $proc$libresoc.v:187138$13002 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$13298 $2\data_r4__xer_ov$next[1:0]$13302 + assign $0\data_r4__xer_ov$next[1:0]$13003 $2\data_r4__xer_ov$next[1:0]$13007 assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$13299 $3\data_r4__xer_ov_ok$next[0:0]$13304 - attribute \src "libresoc.v:192943.5-192943.29" + assign $0\data_r4__xer_ov_ok$next[0:0]$13004 $3\data_r4__xer_ov_ok$next[0:0]$13009 + attribute \src "libresoc.v:187139.5-187139.29" switch \initial - attribute \src "libresoc.v:192943.9-192943.17" + attribute \src "libresoc.v:187139.9-187139.17" case 1'1 case end @@ -401709,10 +392264,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$13301 $1\data_r4__xer_ov$next[1:0]$13300 } { \xer_ov_ok \alu_spr0_xer_ov } + assign { $1\data_r4__xer_ov_ok$next[0:0]$13006 $1\data_r4__xer_ov$next[1:0]$13005 } { \xer_ov_ok \alu_spr0_xer_ov } case - assign $1\data_r4__xer_ov$next[1:0]$13300 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$13301 \data_r4__xer_ov_ok + assign $1\data_r4__xer_ov$next[1:0]$13005 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$13006 \data_r4__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -401720,38 +392275,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$13303 $2\data_r4__xer_ov$next[1:0]$13302 } 3'000 + assign { $2\data_r4__xer_ov_ok$next[0:0]$13008 $2\data_r4__xer_ov$next[1:0]$13007 } 3'000 case - assign $2\data_r4__xer_ov$next[1:0]$13302 $1\data_r4__xer_ov$next[1:0]$13300 - assign $2\data_r4__xer_ov_ok$next[0:0]$13303 $1\data_r4__xer_ov_ok$next[0:0]$13301 + assign $2\data_r4__xer_ov$next[1:0]$13007 $1\data_r4__xer_ov$next[1:0]$13005 + assign $2\data_r4__xer_ov_ok$next[0:0]$13008 $1\data_r4__xer_ov_ok$next[0:0]$13006 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$13304 1'0 + assign $3\data_r4__xer_ov_ok$next[0:0]$13009 1'0 case - assign $3\data_r4__xer_ov_ok$next[0:0]$13304 $2\data_r4__xer_ov_ok$next[0:0]$13303 + assign $3\data_r4__xer_ov_ok$next[0:0]$13009 $2\data_r4__xer_ov_ok$next[0:0]$13008 end sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13298 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13299 + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13003 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13004 end - attribute \src "libresoc.v:192964.3-192985.6" - process $proc$libresoc.v:192964$13305 + attribute \src "libresoc.v:187160.3-187181.6" + process $proc$libresoc.v:187160$13010 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$13306 $2\data_r5__xer_ca$next[1:0]$13310 + assign $0\data_r5__xer_ca$next[1:0]$13011 $2\data_r5__xer_ca$next[1:0]$13015 assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$13307 $3\data_r5__xer_ca_ok$next[0:0]$13312 - attribute \src "libresoc.v:192965.5-192965.29" + assign $0\data_r5__xer_ca_ok$next[0:0]$13012 $3\data_r5__xer_ca_ok$next[0:0]$13017 + attribute \src "libresoc.v:187161.5-187161.29" switch \initial - attribute \src "libresoc.v:192965.9-192965.17" + attribute \src "libresoc.v:187161.9-187161.17" case 1'1 case end @@ -401761,10 +392316,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$13309 $1\data_r5__xer_ca$next[1:0]$13308 } { \xer_ca_ok \alu_spr0_xer_ca } + assign { $1\data_r5__xer_ca_ok$next[0:0]$13014 $1\data_r5__xer_ca$next[1:0]$13013 } { \xer_ca_ok \alu_spr0_xer_ca } case - assign $1\data_r5__xer_ca$next[1:0]$13308 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$13309 \data_r5__xer_ca_ok + assign $1\data_r5__xer_ca$next[1:0]$13013 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$13014 \data_r5__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -401772,32 +392327,32 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$13311 $2\data_r5__xer_ca$next[1:0]$13310 } 3'000 + assign { $2\data_r5__xer_ca_ok$next[0:0]$13016 $2\data_r5__xer_ca$next[1:0]$13015 } 3'000 case - assign $2\data_r5__xer_ca$next[1:0]$13310 $1\data_r5__xer_ca$next[1:0]$13308 - assign $2\data_r5__xer_ca_ok$next[0:0]$13311 $1\data_r5__xer_ca_ok$next[0:0]$13309 + assign $2\data_r5__xer_ca$next[1:0]$13015 $1\data_r5__xer_ca$next[1:0]$13013 + assign $2\data_r5__xer_ca_ok$next[0:0]$13016 $1\data_r5__xer_ca_ok$next[0:0]$13014 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$13312 1'0 + assign $3\data_r5__xer_ca_ok$next[0:0]$13017 1'0 case - assign $3\data_r5__xer_ca_ok$next[0:0]$13312 $2\data_r5__xer_ca_ok$next[0:0]$13311 + assign $3\data_r5__xer_ca_ok$next[0:0]$13017 $2\data_r5__xer_ca_ok$next[0:0]$13016 end sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13306 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13307 + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13011 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13012 end - attribute \src "libresoc.v:192986.3-192995.6" - process $proc$libresoc.v:192986$13313 + attribute \src "libresoc.v:187182.3-187191.6" + process $proc$libresoc.v:187182$13018 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$13314 $1\src_r0$next[63:0]$13315 - attribute \src "libresoc.v:192987.5-192987.29" + assign $0\src_r0$next[63:0]$13019 $1\src_r0$next[63:0]$13020 + attribute \src "libresoc.v:187183.5-187183.29" switch \initial - attribute \src "libresoc.v:192987.9-192987.17" + attribute \src "libresoc.v:187183.9-187183.17" case 1'1 case end @@ -401806,21 +392361,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$13315 \src1_i + assign $1\src_r0$next[63:0]$13020 \src1_i case - assign $1\src_r0$next[63:0]$13315 \src_r0 + assign $1\src_r0$next[63:0]$13020 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$13314 + update \src_r0$next $0\src_r0$next[63:0]$13019 end - attribute \src "libresoc.v:192996.3-193005.6" - process $proc$libresoc.v:192996$13316 + attribute \src "libresoc.v:187192.3-187201.6" + process $proc$libresoc.v:187192$13021 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$13317 $1\src_r1$next[63:0]$13318 - attribute \src "libresoc.v:192997.5-192997.29" + assign $0\src_r1$next[63:0]$13022 $1\src_r1$next[63:0]$13023 + attribute \src "libresoc.v:187193.5-187193.29" switch \initial - attribute \src "libresoc.v:192997.9-192997.17" + attribute \src "libresoc.v:187193.9-187193.17" case 1'1 case end @@ -401829,21 +392384,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$13318 \src2_i + assign $1\src_r1$next[63:0]$13023 \src2_i case - assign $1\src_r1$next[63:0]$13318 \src_r1 + assign $1\src_r1$next[63:0]$13023 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$13317 + update \src_r1$next $0\src_r1$next[63:0]$13022 end - attribute \src "libresoc.v:193006.3-193015.6" - process $proc$libresoc.v:193006$13319 + attribute \src "libresoc.v:187202.3-187211.6" + process $proc$libresoc.v:187202$13024 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$13320 $1\src_r2$next[63:0]$13321 - attribute \src "libresoc.v:193007.5-193007.29" + assign $0\src_r2$next[63:0]$13025 $1\src_r2$next[63:0]$13026 + attribute \src "libresoc.v:187203.5-187203.29" switch \initial - attribute \src "libresoc.v:193007.9-193007.17" + attribute \src "libresoc.v:187203.9-187203.17" case 1'1 case end @@ -401852,21 +392407,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$13321 \src3_i + assign $1\src_r2$next[63:0]$13026 \src3_i case - assign $1\src_r2$next[63:0]$13321 \src_r2 + assign $1\src_r2$next[63:0]$13026 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$13320 + update \src_r2$next $0\src_r2$next[63:0]$13025 end - attribute \src "libresoc.v:193016.3-193025.6" - process $proc$libresoc.v:193016$13322 + attribute \src "libresoc.v:187212.3-187221.6" + process $proc$libresoc.v:187212$13027 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$13323 $1\src_r3$next[0:0]$13324 - attribute \src "libresoc.v:193017.5-193017.29" + assign $0\src_r3$next[0:0]$13028 $1\src_r3$next[0:0]$13029 + attribute \src "libresoc.v:187213.5-187213.29" switch \initial - attribute \src "libresoc.v:193017.9-193017.17" + attribute \src "libresoc.v:187213.9-187213.17" case 1'1 case end @@ -401875,21 +392430,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$13324 \src4_i + assign $1\src_r3$next[0:0]$13029 \src4_i case - assign $1\src_r3$next[0:0]$13324 \src_r3 + assign $1\src_r3$next[0:0]$13029 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$13323 + update \src_r3$next $0\src_r3$next[0:0]$13028 end - attribute \src "libresoc.v:193026.3-193035.6" - process $proc$libresoc.v:193026$13325 + attribute \src "libresoc.v:187222.3-187231.6" + process $proc$libresoc.v:187222$13030 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$13326 $1\src_r4$next[1:0]$13327 - attribute \src "libresoc.v:193027.5-193027.29" + assign $0\src_r4$next[1:0]$13031 $1\src_r4$next[1:0]$13032 + attribute \src "libresoc.v:187223.5-187223.29" switch \initial - attribute \src "libresoc.v:193027.9-193027.17" + attribute \src "libresoc.v:187223.9-187223.17" case 1'1 case end @@ -401898,21 +392453,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$13327 \src5_i + assign $1\src_r4$next[1:0]$13032 \src5_i case - assign $1\src_r4$next[1:0]$13327 \src_r4 + assign $1\src_r4$next[1:0]$13032 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$13326 + update \src_r4$next $0\src_r4$next[1:0]$13031 end - attribute \src "libresoc.v:193036.3-193045.6" - process $proc$libresoc.v:193036$13328 + attribute \src "libresoc.v:187232.3-187241.6" + process $proc$libresoc.v:187232$13033 assign { } { } assign { } { } - assign $0\src_r5$next[1:0]$13329 $1\src_r5$next[1:0]$13330 - attribute \src "libresoc.v:193037.5-193037.29" + assign $0\src_r5$next[1:0]$13034 $1\src_r5$next[1:0]$13035 + attribute \src "libresoc.v:187233.5-187233.29" switch \initial - attribute \src "libresoc.v:193037.9-193037.17" + attribute \src "libresoc.v:187233.9-187233.17" case 1'1 case end @@ -401921,21 +392476,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[1:0]$13330 \src6_i + assign $1\src_r5$next[1:0]$13035 \src6_i case - assign $1\src_r5$next[1:0]$13330 \src_r5 + assign $1\src_r5$next[1:0]$13035 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[1:0]$13329 + update \src_r5$next $0\src_r5$next[1:0]$13034 end - attribute \src "libresoc.v:193046.3-193054.6" - process $proc$libresoc.v:193046$13331 + attribute \src "libresoc.v:187242.3-187250.6" + process $proc$libresoc.v:187242$13036 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$13332 $1\alui_l_r_alui$next[0:0]$13333 - attribute \src "libresoc.v:193047.5-193047.29" + assign $0\alui_l_r_alui$next[0:0]$13037 $1\alui_l_r_alui$next[0:0]$13038 + attribute \src "libresoc.v:187243.5-187243.29" switch \initial - attribute \src "libresoc.v:193047.9-193047.17" + attribute \src "libresoc.v:187243.9-187243.17" case 1'1 case end @@ -401944,21 +392499,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$13333 1'1 + assign $1\alui_l_r_alui$next[0:0]$13038 1'1 case - assign $1\alui_l_r_alui$next[0:0]$13333 \$98 + assign $1\alui_l_r_alui$next[0:0]$13038 \$98 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13332 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13037 end - attribute \src "libresoc.v:193055.3-193063.6" - process $proc$libresoc.v:193055$13334 + attribute \src "libresoc.v:187251.3-187259.6" + process $proc$libresoc.v:187251$13039 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$13335 $1\alu_l_r_alu$next[0:0]$13336 - attribute \src "libresoc.v:193056.5-193056.29" + assign $0\alu_l_r_alu$next[0:0]$13040 $1\alu_l_r_alu$next[0:0]$13041 + attribute \src "libresoc.v:187252.5-187252.29" switch \initial - attribute \src "libresoc.v:193056.9-193056.17" + attribute \src "libresoc.v:187252.9-187252.17" case 1'1 case end @@ -401967,21 +392522,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$13336 1'1 + assign $1\alu_l_r_alu$next[0:0]$13041 1'1 case - assign $1\alu_l_r_alu$next[0:0]$13336 \$100 + assign $1\alu_l_r_alu$next[0:0]$13041 \$100 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13335 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13040 end - attribute \src "libresoc.v:193064.3-193073.6" - process $proc$libresoc.v:193064$13337 + attribute \src "libresoc.v:187260.3-187269.6" + process $proc$libresoc.v:187260$13042 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:193065.5-193065.29" + attribute \src "libresoc.v:187261.5-187261.29" switch \initial - attribute \src "libresoc.v:193065.9-193065.17" + attribute \src "libresoc.v:187261.9-187261.17" case 1'1 case end @@ -401997,14 +392552,14 @@ module \spr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:193074.3-193083.6" - process $proc$libresoc.v:193074$13338 + attribute \src "libresoc.v:187270.3-187279.6" + process $proc$libresoc.v:187270$13043 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:193075.5-193075.29" + attribute \src "libresoc.v:187271.5-187271.29" switch \initial - attribute \src "libresoc.v:193075.9-193075.17" + attribute \src "libresoc.v:187271.9-187271.17" case 1'1 case end @@ -402020,14 +392575,14 @@ module \spr0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:193084.3-193093.6" - process $proc$libresoc.v:193084$13339 + attribute \src "libresoc.v:187280.3-187289.6" + process $proc$libresoc.v:187280$13044 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:193085.5-193085.29" + attribute \src "libresoc.v:187281.5-187281.29" switch \initial - attribute \src "libresoc.v:193085.9-193085.17" + attribute \src "libresoc.v:187281.9-187281.17" case 1'1 case end @@ -402043,14 +392598,14 @@ module \spr0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:193094.3-193103.6" - process $proc$libresoc.v:193094$13340 + attribute \src "libresoc.v:187290.3-187299.6" + process $proc$libresoc.v:187290$13045 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:193095.5-193095.29" + attribute \src "libresoc.v:187291.5-187291.29" switch \initial - attribute \src "libresoc.v:193095.9-193095.17" + attribute \src "libresoc.v:187291.9-187291.17" case 1'1 case end @@ -402066,14 +392621,14 @@ module \spr0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:193104.3-193113.6" - process $proc$libresoc.v:193104$13341 + attribute \src "libresoc.v:187300.3-187309.6" + process $proc$libresoc.v:187300$13046 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:193105.5-193105.29" + attribute \src "libresoc.v:187301.5-187301.29" switch \initial - attribute \src "libresoc.v:193105.9-193105.17" + attribute \src "libresoc.v:187301.9-187301.17" case 1'1 case end @@ -402089,14 +392644,14 @@ module \spr0 sync always update \dest5_o $0\dest5_o[1:0] end - attribute \src "libresoc.v:193114.3-193123.6" - process $proc$libresoc.v:193114$13342 + attribute \src "libresoc.v:187310.3-187319.6" + process $proc$libresoc.v:187310$13047 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:193115.5-193115.29" + attribute \src "libresoc.v:187311.5-187311.29" switch \initial - attribute \src "libresoc.v:193115.9-193115.17" + attribute \src "libresoc.v:187311.9-187311.17" case 1'1 case end @@ -402112,14 +392667,14 @@ module \spr0 sync always update \dest6_o $0\dest6_o[1:0] end - attribute \src "libresoc.v:193124.3-193132.6" - process $proc$libresoc.v:193124$13343 + attribute \src "libresoc.v:187320.3-187328.6" + process $proc$libresoc.v:187320$13048 assign { } { } assign { } { } - assign $0\prev_wr_go$next[5:0]$13344 $1\prev_wr_go$next[5:0]$13345 - attribute \src "libresoc.v:193125.5-193125.29" + assign $0\prev_wr_go$next[5:0]$13049 $1\prev_wr_go$next[5:0]$13050 + attribute \src "libresoc.v:187321.5-187321.29" switch \initial - attribute \src "libresoc.v:193125.9-193125.17" + attribute \src "libresoc.v:187321.9-187321.17" case 1'1 case end @@ -402128,79 +392683,79 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[5:0]$13345 6'000000 - case - assign $1\prev_wr_go$next[5:0]$13345 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13344 - end - connect \$9 $not$libresoc.v:192523$13122_Y - connect \$100 $and$libresoc.v:192524$13123_Y - connect \$102 $and$libresoc.v:192525$13124_Y - connect \$104 $and$libresoc.v:192526$13125_Y - connect \$106 $not$libresoc.v:192527$13126_Y - connect \$108 $and$libresoc.v:192528$13127_Y - connect \$110 $and$libresoc.v:192529$13128_Y - connect \$112 $and$libresoc.v:192530$13129_Y - connect \$114 $and$libresoc.v:192531$13130_Y - connect \$116 $and$libresoc.v:192532$13131_Y - connect \$118 $and$libresoc.v:192533$13132_Y - connect \$11 $or$libresoc.v:192534$13133_Y - connect \$120 $and$libresoc.v:192535$13134_Y - connect \$122 $and$libresoc.v:192536$13135_Y - connect \$124 $and$libresoc.v:192537$13136_Y - connect \$126 $and$libresoc.v:192538$13137_Y - connect \$128 $and$libresoc.v:192539$13138_Y - connect \$8 $reduce_and$libresoc.v:192540$13139_Y - connect \$130 $and$libresoc.v:192541$13140_Y - connect \$132 $and$libresoc.v:192542$13141_Y - connect \$134 $and$libresoc.v:192543$13142_Y - connect \$136 $and$libresoc.v:192544$13143_Y - connect \$14 $and$libresoc.v:192545$13144_Y - connect \$16 $not$libresoc.v:192546$13145_Y - connect \$18 $and$libresoc.v:192547$13146_Y - connect \$20 $not$libresoc.v:192548$13147_Y - connect \$22 $and$libresoc.v:192549$13148_Y - connect \$24 $and$libresoc.v:192550$13149_Y - connect \$28 $not$libresoc.v:192551$13150_Y - connect \$30 $and$libresoc.v:192552$13151_Y - connect \$27 $reduce_or$libresoc.v:192553$13152_Y - connect \$26 $not$libresoc.v:192554$13153_Y - connect \$34 $and$libresoc.v:192555$13154_Y - connect \$36 $reduce_or$libresoc.v:192556$13155_Y - connect \$38 $reduce_or$libresoc.v:192557$13156_Y - connect \$40 $or$libresoc.v:192558$13157_Y - connect \$42 $not$libresoc.v:192559$13158_Y - connect \$44 $and$libresoc.v:192560$13159_Y - connect \$46 $and$libresoc.v:192561$13160_Y - connect \$48 $eq$libresoc.v:192562$13161_Y - connect \$50 $and$libresoc.v:192563$13162_Y - connect \$52 $eq$libresoc.v:192564$13163_Y - connect \$54 $and$libresoc.v:192565$13164_Y - connect \$56 $and$libresoc.v:192566$13165_Y - connect \$58 $and$libresoc.v:192567$13166_Y - connect \$60 $or$libresoc.v:192568$13167_Y - connect \$62 $or$libresoc.v:192569$13168_Y - connect \$64 $or$libresoc.v:192570$13169_Y - connect \$66 $or$libresoc.v:192571$13170_Y - connect \$68 $and$libresoc.v:192572$13171_Y - connect \$6 $and$libresoc.v:192573$13172_Y - connect \$70 $and$libresoc.v:192574$13173_Y - connect \$72 $or$libresoc.v:192575$13174_Y - connect \$74 $and$libresoc.v:192576$13175_Y - connect \$76 $and$libresoc.v:192577$13176_Y - connect \$78 $and$libresoc.v:192578$13177_Y - connect \$80 $and$libresoc.v:192579$13178_Y - connect \$82 $and$libresoc.v:192580$13179_Y - connect \$84 $and$libresoc.v:192581$13180_Y - connect \$86 $ternary$libresoc.v:192582$13181_Y - connect \$88 $ternary$libresoc.v:192583$13182_Y - connect \$90 $ternary$libresoc.v:192584$13183_Y - connect \$92 $ternary$libresoc.v:192585$13184_Y - connect \$94 $ternary$libresoc.v:192586$13185_Y - connect \$96 $ternary$libresoc.v:192587$13186_Y - connect \$98 $and$libresoc.v:192588$13187_Y + assign $1\prev_wr_go$next[5:0]$13050 6'000000 + case + assign $1\prev_wr_go$next[5:0]$13050 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13049 + end + connect \$9 $not$libresoc.v:186719$12827_Y + connect \$100 $and$libresoc.v:186720$12828_Y + connect \$102 $and$libresoc.v:186721$12829_Y + connect \$104 $and$libresoc.v:186722$12830_Y + connect \$106 $not$libresoc.v:186723$12831_Y + connect \$108 $and$libresoc.v:186724$12832_Y + connect \$110 $and$libresoc.v:186725$12833_Y + connect \$112 $and$libresoc.v:186726$12834_Y + connect \$114 $and$libresoc.v:186727$12835_Y + connect \$116 $and$libresoc.v:186728$12836_Y + connect \$118 $and$libresoc.v:186729$12837_Y + connect \$11 $or$libresoc.v:186730$12838_Y + connect \$120 $and$libresoc.v:186731$12839_Y + connect \$122 $and$libresoc.v:186732$12840_Y + connect \$124 $and$libresoc.v:186733$12841_Y + connect \$126 $and$libresoc.v:186734$12842_Y + connect \$128 $and$libresoc.v:186735$12843_Y + connect \$8 $reduce_and$libresoc.v:186736$12844_Y + connect \$130 $and$libresoc.v:186737$12845_Y + connect \$132 $and$libresoc.v:186738$12846_Y + connect \$134 $and$libresoc.v:186739$12847_Y + connect \$136 $and$libresoc.v:186740$12848_Y + connect \$14 $and$libresoc.v:186741$12849_Y + connect \$16 $not$libresoc.v:186742$12850_Y + connect \$18 $and$libresoc.v:186743$12851_Y + connect \$20 $not$libresoc.v:186744$12852_Y + connect \$22 $and$libresoc.v:186745$12853_Y + connect \$24 $and$libresoc.v:186746$12854_Y + connect \$28 $not$libresoc.v:186747$12855_Y + connect \$30 $and$libresoc.v:186748$12856_Y + connect \$27 $reduce_or$libresoc.v:186749$12857_Y + connect \$26 $not$libresoc.v:186750$12858_Y + connect \$34 $and$libresoc.v:186751$12859_Y + connect \$36 $reduce_or$libresoc.v:186752$12860_Y + connect \$38 $reduce_or$libresoc.v:186753$12861_Y + connect \$40 $or$libresoc.v:186754$12862_Y + connect \$42 $not$libresoc.v:186755$12863_Y + connect \$44 $and$libresoc.v:186756$12864_Y + connect \$46 $and$libresoc.v:186757$12865_Y + connect \$48 $eq$libresoc.v:186758$12866_Y + connect \$50 $and$libresoc.v:186759$12867_Y + connect \$52 $eq$libresoc.v:186760$12868_Y + connect \$54 $and$libresoc.v:186761$12869_Y + connect \$56 $and$libresoc.v:186762$12870_Y + connect \$58 $and$libresoc.v:186763$12871_Y + connect \$60 $or$libresoc.v:186764$12872_Y + connect \$62 $or$libresoc.v:186765$12873_Y + connect \$64 $or$libresoc.v:186766$12874_Y + connect \$66 $or$libresoc.v:186767$12875_Y + connect \$68 $and$libresoc.v:186768$12876_Y + connect \$6 $and$libresoc.v:186769$12877_Y + connect \$70 $and$libresoc.v:186770$12878_Y + connect \$72 $or$libresoc.v:186771$12879_Y + connect \$74 $and$libresoc.v:186772$12880_Y + connect \$76 $and$libresoc.v:186773$12881_Y + connect \$78 $and$libresoc.v:186774$12882_Y + connect \$80 $and$libresoc.v:186775$12883_Y + connect \$82 $and$libresoc.v:186776$12884_Y + connect \$84 $and$libresoc.v:186777$12885_Y + connect \$86 $ternary$libresoc.v:186778$12886_Y + connect \$88 $ternary$libresoc.v:186779$12887_Y + connect \$90 $ternary$libresoc.v:186780$12888_Y + connect \$92 $ternary$libresoc.v:186781$12889_Y + connect \$94 $ternary$libresoc.v:186782$12890_Y + connect \$96 $ternary$libresoc.v:186783$12891_Y + connect \$98 $and$libresoc.v:186784$12892_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 @@ -402233,111 +392788,111 @@ module \spr0 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end -attribute \src "libresoc.v:193168.1-193684.10" +attribute \src "libresoc.v:187364.1-187880.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main - attribute \src "libresoc.v:193437.3-193452.6" - wire width 64 $0\fast1$7[63:0]$13392 - attribute \src "libresoc.v:193514.3-193529.6" + attribute \src "libresoc.v:187633.3-187648.6" + wire width 64 $0\fast1$7[63:0]$13097 + attribute \src "libresoc.v:187710.3-187725.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:193169.7-193169.20" + attribute \src "libresoc.v:187365.7-187365.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193472.3-193513.6" + attribute \src "libresoc.v:187668.3-187709.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:193472.3-193513.6" + attribute \src "libresoc.v:187668.3-187709.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:193662.3-193680.6" - wire width 64 $0\spr1$6[63:0]$13417 - attribute \src "libresoc.v:193453.3-193471.6" + attribute \src "libresoc.v:187858.3-187876.6" + wire width 64 $0\spr1$6[63:0]$13122 + attribute \src "libresoc.v:187649.3-187667.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:193617.3-193640.6" - wire width 2 $0\xer_ca$10[1:0]$13411 - attribute \src "libresoc.v:193641.3-193661.6" + attribute \src "libresoc.v:187813.3-187836.6" + wire width 2 $0\xer_ca$10[1:0]$13116 + attribute \src "libresoc.v:187837.3-187857.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:193572.3-193595.6" - wire width 2 $0\xer_ov$9[1:0]$13405 - attribute \src "libresoc.v:193596.3-193616.6" + attribute \src "libresoc.v:187768.3-187791.6" + wire width 2 $0\xer_ov$9[1:0]$13110 + attribute \src "libresoc.v:187792.3-187812.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:193530.3-193550.6" - wire $0\xer_so$8[0:0]$13399 - attribute \src "libresoc.v:193551.3-193571.6" + attribute \src "libresoc.v:187726.3-187746.6" + wire $0\xer_so$8[0:0]$13104 + attribute \src "libresoc.v:187747.3-187767.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:193437.3-193452.6" - wire width 64 $1\fast1$7[63:0]$13393 - attribute \src "libresoc.v:193514.3-193529.6" + attribute \src "libresoc.v:187633.3-187648.6" + wire width 64 $1\fast1$7[63:0]$13098 + attribute \src "libresoc.v:187710.3-187725.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:193472.3-193513.6" + attribute \src "libresoc.v:187668.3-187709.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:193472.3-193513.6" + attribute \src "libresoc.v:187668.3-187709.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:193662.3-193680.6" - wire width 64 $1\spr1$6[63:0]$13418 - attribute \src "libresoc.v:193453.3-193471.6" + attribute \src "libresoc.v:187858.3-187876.6" + wire width 64 $1\spr1$6[63:0]$13123 + attribute \src "libresoc.v:187649.3-187667.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:193617.3-193640.6" - wire width 2 $1\xer_ca$10[1:0]$13412 - attribute \src "libresoc.v:193641.3-193661.6" + attribute \src "libresoc.v:187813.3-187836.6" + wire width 2 $1\xer_ca$10[1:0]$13117 + attribute \src "libresoc.v:187837.3-187857.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:193572.3-193595.6" - wire width 2 $1\xer_ov$9[1:0]$13406 - attribute \src "libresoc.v:193596.3-193616.6" + attribute \src "libresoc.v:187768.3-187791.6" + wire width 2 $1\xer_ov$9[1:0]$13111 + attribute \src "libresoc.v:187792.3-187812.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:193530.3-193550.6" - wire $1\xer_so$8[0:0]$13400 - attribute \src "libresoc.v:193551.3-193571.6" + attribute \src "libresoc.v:187726.3-187746.6" + wire $1\xer_so$8[0:0]$13105 + attribute \src "libresoc.v:187747.3-187767.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:193437.3-193452.6" - wire width 64 $2\fast1$7[63:0]$13394 - attribute \src "libresoc.v:193514.3-193529.6" + attribute \src "libresoc.v:187633.3-187648.6" + wire width 64 $2\fast1$7[63:0]$13099 + attribute \src "libresoc.v:187710.3-187725.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:193472.3-193513.6" + attribute \src "libresoc.v:187668.3-187709.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:193662.3-193680.6" - wire width 64 $2\spr1$6[63:0]$13419 - attribute \src "libresoc.v:193453.3-193471.6" + attribute \src "libresoc.v:187858.3-187876.6" + wire width 64 $2\spr1$6[63:0]$13124 + attribute \src "libresoc.v:187649.3-187667.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:193617.3-193640.6" - wire width 2 $2\xer_ca$10[1:0]$13413 - attribute \src "libresoc.v:193641.3-193661.6" + attribute \src "libresoc.v:187813.3-187836.6" + wire width 2 $2\xer_ca$10[1:0]$13118 + attribute \src "libresoc.v:187837.3-187857.6" wire $2\xer_ca_ok[0:0] - attribute \src "libresoc.v:193572.3-193595.6" - wire width 2 $2\xer_ov$9[1:0]$13407 - attribute \src "libresoc.v:193596.3-193616.6" + attribute \src "libresoc.v:187768.3-187791.6" + wire width 2 $2\xer_ov$9[1:0]$13112 + attribute \src "libresoc.v:187792.3-187812.6" wire $2\xer_ov_ok[0:0] - attribute \src "libresoc.v:193530.3-193550.6" - wire $2\xer_so$8[0:0]$13401 - attribute \src "libresoc.v:193551.3-193571.6" + attribute \src "libresoc.v:187726.3-187746.6" + wire $2\xer_so$8[0:0]$13106 + attribute \src "libresoc.v:187747.3-187767.6" wire $2\xer_so_ok[0:0] - attribute \src "libresoc.v:193472.3-193513.6" + attribute \src "libresoc.v:187668.3-187709.6" wire width 46 $3\o[63:18] - attribute \src "libresoc.v:193617.3-193640.6" - wire width 2 $3\xer_ca$10[1:0]$13414 - attribute \src "libresoc.v:193641.3-193661.6" + attribute \src "libresoc.v:187813.3-187836.6" + wire width 2 $3\xer_ca$10[1:0]$13119 + attribute \src "libresoc.v:187837.3-187857.6" wire $3\xer_ca_ok[0:0] - attribute \src "libresoc.v:193572.3-193595.6" - wire width 2 $3\xer_ov$9[1:0]$13408 - attribute \src "libresoc.v:193596.3-193616.6" + attribute \src "libresoc.v:187768.3-187791.6" + wire width 2 $3\xer_ov$9[1:0]$13113 + attribute \src "libresoc.v:187792.3-187812.6" wire $3\xer_ov_ok[0:0] - attribute \src "libresoc.v:193530.3-193550.6" - wire $3\xer_so$8[0:0]$13402 - attribute \src "libresoc.v:193551.3-193571.6" + attribute \src "libresoc.v:187726.3-187746.6" + wire $3\xer_so$8[0:0]$13107 + attribute \src "libresoc.v:187747.3-187767.6" wire $3\xer_so_ok[0:0] - attribute \src "libresoc.v:193430.18-193430.106" - wire $eq$libresoc.v:193430$13384_Y - attribute \src "libresoc.v:193431.18-193431.106" - wire $eq$libresoc.v:193431$13385_Y - attribute \src "libresoc.v:193432.18-193432.106" - wire $eq$libresoc.v:193432$13386_Y - attribute \src "libresoc.v:193433.18-193433.106" - wire $eq$libresoc.v:193433$13387_Y - attribute \src "libresoc.v:193434.18-193434.106" - wire $eq$libresoc.v:193434$13388_Y - attribute \src "libresoc.v:193435.18-193435.106" - wire $eq$libresoc.v:193435$13389_Y - attribute \src "libresoc.v:193436.18-193436.106" - wire $eq$libresoc.v:193436$13390_Y + attribute \src "libresoc.v:187626.18-187626.106" + wire $eq$libresoc.v:187626$13089_Y + attribute \src "libresoc.v:187627.18-187627.106" + wire $eq$libresoc.v:187627$13090_Y + attribute \src "libresoc.v:187628.18-187628.106" + wire $eq$libresoc.v:187628$13091_Y + attribute \src "libresoc.v:187629.18-187629.106" + wire $eq$libresoc.v:187629$13092_Y + attribute \src "libresoc.v:187630.18-187630.106" + wire $eq$libresoc.v:187630$13093_Y + attribute \src "libresoc.v:187631.18-187631.106" + wire $eq$libresoc.v:187631$13094_Y + attribute \src "libresoc.v:187632.18-187632.106" + wire $eq$libresoc.v:187632$13095_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" @@ -402358,7 +392913,7 @@ module \spr_main wire width 64 output 20 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast1_ok - attribute \src "libresoc.v:193169.7-193169.15" + attribute \src "libresoc.v:187365.7-187365.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid @@ -402589,7 +393144,7 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:193430$13384 + cell $eq $eq$libresoc.v:187626$13089 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -402597,10 +393152,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:193430$13384_Y + connect \Y $eq$libresoc.v:187626$13089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:193431$13385 + cell $eq $eq$libresoc.v:187627$13090 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -402608,10 +393163,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:193431$13385_Y + connect \Y $eq$libresoc.v:187627$13090_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:193432$13386 + cell $eq $eq$libresoc.v:187628$13091 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -402619,10 +393174,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:193432$13386_Y + connect \Y $eq$libresoc.v:187628$13091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:193433$13387 + cell $eq $eq$libresoc.v:187629$13092 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -402630,10 +393185,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:193433$13387_Y + connect \Y $eq$libresoc.v:187629$13092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:193434$13388 + cell $eq $eq$libresoc.v:187630$13093 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -402641,10 +393196,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:193434$13388_Y + connect \Y $eq$libresoc.v:187630$13093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:193435$13389 + cell $eq $eq$libresoc.v:187631$13094 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -402652,10 +393207,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:193435$13389_Y + connect \Y $eq$libresoc.v:187631$13094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$libresoc.v:193436$13390 + cell $eq $eq$libresoc.v:187632$13095 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -402663,24 +393218,24 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:193436$13390_Y + connect \Y $eq$libresoc.v:187632$13095_Y end - attribute \src "libresoc.v:193169.7-193169.20" - process $proc$libresoc.v:193169$13420 + attribute \src "libresoc.v:187365.7-187365.20" + process $proc$libresoc.v:187365$13125 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193437.3-193452.6" - process $proc$libresoc.v:193437$13391 + attribute \src "libresoc.v:187633.3-187648.6" + process $proc$libresoc.v:187633$13096 assign { } { } assign { } { } - assign $0\fast1$7[63:0]$13392 $1\fast1$7[63:0]$13393 - attribute \src "libresoc.v:193438.5-193438.29" + assign $0\fast1$7[63:0]$13097 $1\fast1$7[63:0]$13098 + attribute \src "libresoc.v:187634.5-187634.29" switch \initial - attribute \src "libresoc.v:193438.9-193438.17" + attribute \src "libresoc.v:187634.9-187634.17" case 1'1 case end @@ -402689,30 +393244,30 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\fast1$7[63:0]$13393 $2\fast1$7[63:0]$13394 + assign $1\fast1$7[63:0]$13098 $2\fast1$7[63:0]$13099 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\fast1$7[63:0]$13394 \ra + assign $2\fast1$7[63:0]$13099 \ra case - assign $2\fast1$7[63:0]$13394 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$7[63:0]$13099 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\fast1$7[63:0]$13393 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$7[63:0]$13098 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$7 $0\fast1$7[63:0]$13392 + update \fast1$7 $0\fast1$7[63:0]$13097 end - attribute \src "libresoc.v:193453.3-193471.6" - process $proc$libresoc.v:193453$13395 + attribute \src "libresoc.v:187649.3-187667.6" + process $proc$libresoc.v:187649$13100 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:193454.5-193454.29" + attribute \src "libresoc.v:187650.5-187650.29" switch \initial - attribute \src "libresoc.v:193454.9-193454.17" + attribute \src "libresoc.v:187650.9-187650.17" case 1'1 case end @@ -402738,17 +393293,17 @@ module \spr_main sync always update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:193472.3-193513.6" - process $proc$libresoc.v:193472$13396 + attribute \src "libresoc.v:187668.3-187709.6" + process $proc$libresoc.v:187668$13101 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:193473.5-193473.29" + attribute \src "libresoc.v:187669.5-187669.29" switch \initial - attribute \src "libresoc.v:193473.9-193473.17" + attribute \src "libresoc.v:187669.9-187669.17" case 1'1 case end @@ -402799,14 +393354,14 @@ module \spr_main update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:193514.3-193529.6" - process $proc$libresoc.v:193514$13397 + attribute \src "libresoc.v:187710.3-187725.6" + process $proc$libresoc.v:187710$13102 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:193515.5-193515.29" + attribute \src "libresoc.v:187711.5-187711.29" switch \initial - attribute \src "libresoc.v:193515.9-193515.17" + attribute \src "libresoc.v:187711.9-187711.17" case 1'1 case end @@ -402831,14 +393386,14 @@ module \spr_main sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:193530.3-193550.6" - process $proc$libresoc.v:193530$13398 + attribute \src "libresoc.v:187726.3-187746.6" + process $proc$libresoc.v:187726$13103 assign { } { } assign { } { } - assign $0\xer_so$8[0:0]$13399 $1\xer_so$8[0:0]$13400 - attribute \src "libresoc.v:193531.5-193531.29" + assign $0\xer_so$8[0:0]$13104 $1\xer_so$8[0:0]$13105 + attribute \src "libresoc.v:187727.5-187727.29" switch \initial - attribute \src "libresoc.v:193531.9-193531.17" + attribute \src "libresoc.v:187727.9-187727.17" case 1'1 case end @@ -402847,39 +393402,39 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_so$8[0:0]$13400 $2\xer_so$8[0:0]$13401 + assign $1\xer_so$8[0:0]$13105 $2\xer_so$8[0:0]$13106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_so$8[0:0]$13401 $3\xer_so$8[0:0]$13402 + assign $2\xer_so$8[0:0]$13106 $3\xer_so$8[0:0]$13107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_so$8[0:0]$13402 \ra [31] + assign $3\xer_so$8[0:0]$13107 \ra [31] case - assign $3\xer_so$8[0:0]$13402 1'0 + assign $3\xer_so$8[0:0]$13107 1'0 end case - assign $2\xer_so$8[0:0]$13401 1'0 + assign $2\xer_so$8[0:0]$13106 1'0 end case - assign $1\xer_so$8[0:0]$13400 1'0 + assign $1\xer_so$8[0:0]$13105 1'0 end sync always - update \xer_so$8 $0\xer_so$8[0:0]$13399 + update \xer_so$8 $0\xer_so$8[0:0]$13104 end - attribute \src "libresoc.v:193551.3-193571.6" - process $proc$libresoc.v:193551$13403 + attribute \src "libresoc.v:187747.3-187767.6" + process $proc$libresoc.v:187747$13108 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:193552.5-193552.29" + attribute \src "libresoc.v:187748.5-187748.29" switch \initial - attribute \src "libresoc.v:193552.9-193552.17" + attribute \src "libresoc.v:187748.9-187748.17" case 1'1 case end @@ -402913,14 +393468,14 @@ module \spr_main sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:193572.3-193595.6" - process $proc$libresoc.v:193572$13404 + attribute \src "libresoc.v:187768.3-187791.6" + process $proc$libresoc.v:187768$13109 assign { } { } assign { } { } - assign $0\xer_ov$9[1:0]$13405 $1\xer_ov$9[1:0]$13406 - attribute \src "libresoc.v:193573.5-193573.29" + assign $0\xer_ov$9[1:0]$13110 $1\xer_ov$9[1:0]$13111 + attribute \src "libresoc.v:187769.5-187769.29" switch \initial - attribute \src "libresoc.v:193573.9-193573.17" + attribute \src "libresoc.v:187769.9-187769.17" case 1'1 case end @@ -402929,40 +393484,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ov$9[1:0]$13406 $2\xer_ov$9[1:0]$13407 + assign $1\xer_ov$9[1:0]$13111 $2\xer_ov$9[1:0]$13112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ov$9[1:0]$13407 $3\xer_ov$9[1:0]$13408 + assign $2\xer_ov$9[1:0]$13112 $3\xer_ov$9[1:0]$13113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ov$9[1:0]$13408 [0] \ra [30] - assign $3\xer_ov$9[1:0]$13408 [1] \ra [19] + assign $3\xer_ov$9[1:0]$13113 [0] \ra [30] + assign $3\xer_ov$9[1:0]$13113 [1] \ra [19] case - assign $3\xer_ov$9[1:0]$13408 2'00 + assign $3\xer_ov$9[1:0]$13113 2'00 end case - assign $2\xer_ov$9[1:0]$13407 2'00 + assign $2\xer_ov$9[1:0]$13112 2'00 end case - assign $1\xer_ov$9[1:0]$13406 2'00 + assign $1\xer_ov$9[1:0]$13111 2'00 end sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$13405 + update \xer_ov$9 $0\xer_ov$9[1:0]$13110 end - attribute \src "libresoc.v:193596.3-193616.6" - process $proc$libresoc.v:193596$13409 + attribute \src "libresoc.v:187792.3-187812.6" + process $proc$libresoc.v:187792$13114 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:193597.5-193597.29" + attribute \src "libresoc.v:187793.5-187793.29" switch \initial - attribute \src "libresoc.v:193597.9-193597.17" + attribute \src "libresoc.v:187793.9-187793.17" case 1'1 case end @@ -402996,14 +393551,14 @@ module \spr_main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:193617.3-193640.6" - process $proc$libresoc.v:193617$13410 + attribute \src "libresoc.v:187813.3-187836.6" + process $proc$libresoc.v:187813$13115 assign { } { } assign { } { } - assign $0\xer_ca$10[1:0]$13411 $1\xer_ca$10[1:0]$13412 - attribute \src "libresoc.v:193618.5-193618.29" + assign $0\xer_ca$10[1:0]$13116 $1\xer_ca$10[1:0]$13117 + attribute \src "libresoc.v:187814.5-187814.29" switch \initial - attribute \src "libresoc.v:193618.9-193618.17" + attribute \src "libresoc.v:187814.9-187814.17" case 1'1 case end @@ -403012,40 +393567,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ca$10[1:0]$13412 $2\xer_ca$10[1:0]$13413 + assign $1\xer_ca$10[1:0]$13117 $2\xer_ca$10[1:0]$13118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ca$10[1:0]$13413 $3\xer_ca$10[1:0]$13414 + assign $2\xer_ca$10[1:0]$13118 $3\xer_ca$10[1:0]$13119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ca$10[1:0]$13414 [0] \ra [29] - assign $3\xer_ca$10[1:0]$13414 [1] \ra [18] + assign $3\xer_ca$10[1:0]$13119 [0] \ra [29] + assign $3\xer_ca$10[1:0]$13119 [1] \ra [18] case - assign $3\xer_ca$10[1:0]$13414 2'00 + assign $3\xer_ca$10[1:0]$13119 2'00 end case - assign $2\xer_ca$10[1:0]$13413 2'00 + assign $2\xer_ca$10[1:0]$13118 2'00 end case - assign $1\xer_ca$10[1:0]$13412 2'00 + assign $1\xer_ca$10[1:0]$13117 2'00 end sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$13411 + update \xer_ca$10 $0\xer_ca$10[1:0]$13116 end - attribute \src "libresoc.v:193641.3-193661.6" - process $proc$libresoc.v:193641$13415 + attribute \src "libresoc.v:187837.3-187857.6" + process $proc$libresoc.v:187837$13120 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:193642.5-193642.29" + attribute \src "libresoc.v:187838.5-187838.29" switch \initial - attribute \src "libresoc.v:193642.9-193642.17" + attribute \src "libresoc.v:187838.9-187838.17" case 1'1 case end @@ -403079,14 +393634,14 @@ module \spr_main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:193662.3-193680.6" - process $proc$libresoc.v:193662$13416 + attribute \src "libresoc.v:187858.3-187876.6" + process $proc$libresoc.v:187858$13121 assign { } { } assign { } { } - assign $0\spr1$6[63:0]$13417 $1\spr1$6[63:0]$13418 - attribute \src "libresoc.v:193663.5-193663.29" + assign $0\spr1$6[63:0]$13122 $1\spr1$6[63:0]$13123 + attribute \src "libresoc.v:187859.5-187859.29" switch \initial - attribute \src "libresoc.v:193663.9-193663.17" + attribute \src "libresoc.v:187859.9-187859.17" case 1'1 case end @@ -403095,64 +393650,64 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\spr1$6[63:0]$13418 $2\spr1$6[63:0]$13419 + assign $1\spr1$6[63:0]$13123 $2\spr1$6[63:0]$13124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$13419 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\spr1$6[63:0]$13124 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\spr1$6[63:0]$13419 \ra + assign $2\spr1$6[63:0]$13124 \ra end case - assign $1\spr1$6[63:0]$13418 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr1$6[63:0]$13123 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spr1$6 $0\spr1$6[63:0]$13417 + update \spr1$6 $0\spr1$6[63:0]$13122 end - connect \$11 $eq$libresoc.v:193430$13384_Y - connect \$13 $eq$libresoc.v:193431$13385_Y - connect \$15 $eq$libresoc.v:193432$13386_Y - connect \$17 $eq$libresoc.v:193433$13387_Y - connect \$19 $eq$libresoc.v:193434$13388_Y - connect \$21 $eq$libresoc.v:193435$13389_Y - connect \$23 $eq$libresoc.v:193436$13390_Y + connect \$11 $eq$libresoc.v:187626$13089_Y + connect \$13 $eq$libresoc.v:187627$13090_Y + connect \$15 $eq$libresoc.v:187628$13091_Y + connect \$17 $eq$libresoc.v:187629$13092_Y + connect \$19 $eq$libresoc.v:187630$13093_Y + connect \$21 $eq$libresoc.v:187631$13094_Y + connect \$23 $eq$libresoc.v:187632$13095_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end -attribute \src "libresoc.v:193688.1-194517.10" +attribute \src "libresoc.v:187884.1-188720.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap - attribute \src "libresoc.v:193817.3-193847.6" + attribute \src "libresoc.v:188014.3-188044.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:193848.3-193878.6" + attribute \src "libresoc.v:188045.3-188075.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:193689.7-193689.20" + attribute \src "libresoc.v:187885.7-187885.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193879.3-194197.6" + attribute \src "libresoc.v:188076.3-188397.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:194198.3-194516.6" + attribute \src "libresoc.v:188398.3-188719.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:193817.3-193847.6" + attribute \src "libresoc.v:188014.3-188044.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:193848.3-193878.6" + attribute \src "libresoc.v:188045.3-188075.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:193879.3-194197.6" + attribute \src "libresoc.v:188076.3-188397.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:194198.3-194516.6" + attribute \src "libresoc.v:188398.3-188719.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:193689.7-193689.15" + attribute \src "libresoc.v:187885.7-187885.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -403220,7 +393775,8 @@ module \sprmap attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -403271,26 +393827,26 @@ module \sprmap wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:193689.7-193689.20" - process $proc$libresoc.v:193689$13425 + attribute \src "libresoc.v:187885.7-187885.20" + process $proc$libresoc.v:187885$13130 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193817.3-193847.6" - process $proc$libresoc.v:193817$13421 + attribute \src "libresoc.v:188014.3-188044.6" + process $proc$libresoc.v:188014$13126 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:193818.5-193818.29" + attribute \src "libresoc.v:188015.5-188015.29" switch \initial - attribute \src "libresoc.v:193818.9-193818.17" + attribute \src "libresoc.v:188015.9-188015.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -403330,18 +393886,18 @@ module \sprmap sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:193848.3-193878.6" - process $proc$libresoc.v:193848$13422 + attribute \src "libresoc.v:188045.3-188075.6" + process $proc$libresoc.v:188045$13127 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:193849.5-193849.29" + attribute \src "libresoc.v:188046.5-188046.29" switch \initial - attribute \src "libresoc.v:193849.9-193849.17" + attribute \src "libresoc.v:188046.9-188046.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -403381,18 +393937,18 @@ module \sprmap sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:193879.3-194197.6" - process $proc$libresoc.v:193879$13423 + attribute \src "libresoc.v:188076.3-188397.6" + process $proc$libresoc.v:188076$13128 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:193880.5-193880.29" + attribute \src "libresoc.v:188077.5-188077.29" switch \initial - attribute \src "libresoc.v:193880.9-193880.17" + attribute \src "libresoc.v:188077.9-188077.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -403631,203 +394187,207 @@ module \sprmap assign { } { } assign $1\spr_o[9:0] 10'0001000001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 + case 10'1011010001 assign { } { } assign $1\spr_o[9:0] 10'0001000010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 + case 10'1100000000 assign { } { } assign $1\spr_o[9:0] 10'0001000011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 + case 10'1100000001 assign { } { } assign $1\spr_o[9:0] 10'0001000100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 + case 10'1100000010 assign { } { } assign $1\spr_o[9:0] 10'0001000101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 + case 10'1100000011 assign { } { } assign $1\spr_o[9:0] 10'0001000110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 + case 10'1100000100 assign { } { } assign $1\spr_o[9:0] 10'0001000111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 + case 10'1100000101 assign { } { } assign $1\spr_o[9:0] 10'0001001000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 + case 10'1100000110 assign { } { } assign $1\spr_o[9:0] 10'0001001001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 + case 10'1100000111 assign { } { } assign $1\spr_o[9:0] 10'0001001010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 + case 10'1100001000 assign { } { } assign $1\spr_o[9:0] 10'0001001011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 + case 10'1100001011 assign { } { } assign $1\spr_o[9:0] 10'0001001100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 + case 10'1100001100 assign { } { } assign $1\spr_o[9:0] 10'0001001101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 + case 10'1100001101 assign { } { } assign $1\spr_o[9:0] 10'0001001110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 + case 10'1100001110 assign { } { } assign $1\spr_o[9:0] 10'0001001111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 + case 10'1100010000 assign { } { } assign $1\spr_o[9:0] 10'0001010000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 + case 10'1100010001 assign { } { } assign $1\spr_o[9:0] 10'0001010001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 + case 10'1100010010 assign { } { } assign $1\spr_o[9:0] 10'0001010010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 + case 10'1100010011 assign { } { } assign $1\spr_o[9:0] 10'0001010011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 + case 10'1100010100 assign { } { } assign $1\spr_o[9:0] 10'0001010100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 + case 10'1100010101 assign { } { } assign $1\spr_o[9:0] 10'0001010101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 + case 10'1100010110 assign { } { } assign $1\spr_o[9:0] 10'0001010110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 + case 10'1100010111 assign { } { } assign $1\spr_o[9:0] 10'0001010111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 + case 10'1100011000 assign { } { } assign $1\spr_o[9:0] 10'0001011000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 + case 10'1100011011 assign { } { } assign $1\spr_o[9:0] 10'0001011001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 + case 10'1100011100 assign { } { } assign $1\spr_o[9:0] 10'0001011010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 + case 10'1100011101 assign { } { } assign $1\spr_o[9:0] 10'0001011011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 + case 10'1100011110 assign { } { } assign $1\spr_o[9:0] 10'0001011100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 + case 10'1100100000 assign { } { } assign $1\spr_o[9:0] 10'0001011101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 + case 10'1100100001 assign { } { } assign $1\spr_o[9:0] 10'0001011110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 + case 10'1100100010 assign { } { } assign $1\spr_o[9:0] 10'0001011111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 + case 10'1100100011 assign { } { } assign $1\spr_o[9:0] 10'0001100000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 + case 10'1100100100 assign { } { } assign $1\spr_o[9:0] 10'0001100001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 + case 10'1100100101 assign { } { } assign $1\spr_o[9:0] 10'0001100010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 + case 10'1100100110 assign { } { } assign $1\spr_o[9:0] 10'0001100011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 + case 10'1100101000 assign { } { } assign $1\spr_o[9:0] 10'0001100100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 + case 10'1100101001 assign { } { } assign $1\spr_o[9:0] 10'0001100101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 + case 10'1100101010 assign { } { } assign $1\spr_o[9:0] 10'0001100110 attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } - assign $1\spr_o[9:0] 10'0001101000 + assign $1\spr_o[9:0] 10'0001101001 attribute \src "libresoc.v:0.0-0.0" case 10'1100110111 assign { } { } - assign $1\spr_o[9:0] 10'0001101001 + assign $1\spr_o[9:0] 10'0001101010 attribute \src "libresoc.v:0.0-0.0" case 10'1101010000 assign { } { } - assign $1\spr_o[9:0] 10'0001101010 + assign $1\spr_o[9:0] 10'0001101011 attribute \src "libresoc.v:0.0-0.0" case 10'1101010001 assign { } { } - assign $1\spr_o[9:0] 10'0001101011 + assign $1\spr_o[9:0] 10'0001101100 attribute \src "libresoc.v:0.0-0.0" case 10'1101010111 assign { } { } - assign $1\spr_o[9:0] 10'0001101100 + assign $1\spr_o[9:0] 10'0001101101 attribute \src "libresoc.v:0.0-0.0" case 10'1110000000 assign { } { } - assign $1\spr_o[9:0] 10'0001101101 + assign $1\spr_o[9:0] 10'0001101110 attribute \src "libresoc.v:0.0-0.0" case 10'1110000010 assign { } { } - assign $1\spr_o[9:0] 10'0001101110 + assign $1\spr_o[9:0] 10'0001101111 attribute \src "libresoc.v:0.0-0.0" case 10'1111111111 assign { } { } - assign $1\spr_o[9:0] 10'0001101111 + assign $1\spr_o[9:0] 10'0001110000 case assign $1\spr_o[9:0] 10'0000000000 end sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:194198.3-194516.6" - process $proc$libresoc.v:194198$13424 + attribute \src "libresoc.v:188398.3-188719.6" + process $proc$libresoc.v:188398$13129 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:194199.5-194199.29" + attribute \src "libresoc.v:188399.5-188399.29" switch \initial - attribute \src "libresoc.v:194199.9-194199.17" + attribute \src "libresoc.v:188399.9-188399.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -404066,6 +394626,10 @@ module \sprmap assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -404252,36 +394816,36 @@ module \sprmap update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:194521.1-195350.10" +attribute \src "libresoc.v:188724.1-189560.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" -module \sprmap$211 - attribute \src "libresoc.v:194650.3-194680.6" +module \sprmap$174 + attribute \src "libresoc.v:188854.3-188884.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:194681.3-194711.6" + attribute \src "libresoc.v:188885.3-188915.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:194522.7-194522.20" + attribute \src "libresoc.v:188725.7-188725.20" wire $0\initial[0:0] - attribute \src "libresoc.v:194712.3-195030.6" + attribute \src "libresoc.v:188916.3-189237.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:195031.3-195349.6" + attribute \src "libresoc.v:189238.3-189559.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:194650.3-194680.6" + attribute \src "libresoc.v:188854.3-188884.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:194681.3-194711.6" + attribute \src "libresoc.v:188885.3-188915.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:194712.3-195030.6" + attribute \src "libresoc.v:188916.3-189237.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:195031.3-195349.6" + attribute \src "libresoc.v:189238.3-189559.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:194522.7-194522.15" + attribute \src "libresoc.v:188725.7-188725.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" wire width 10 input 5 \spr_i attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" @@ -404349,7 +394913,8 @@ module \sprmap$211 attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -404400,26 +394965,26 @@ module \sprmap$211 wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:194522.7-194522.20" - process $proc$libresoc.v:194522$13430 + attribute \src "libresoc.v:188725.7-188725.20" + process $proc$libresoc.v:188725$13135 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:194650.3-194680.6" - process $proc$libresoc.v:194650$13426 + attribute \src "libresoc.v:188854.3-188884.6" + process $proc$libresoc.v:188854$13131 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:194651.5-194651.29" + attribute \src "libresoc.v:188855.5-188855.29" switch \initial - attribute \src "libresoc.v:194651.9-194651.17" + attribute \src "libresoc.v:188855.9-188855.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -404459,18 +395024,18 @@ module \sprmap$211 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:194681.3-194711.6" - process $proc$libresoc.v:194681$13427 + attribute \src "libresoc.v:188885.3-188915.6" + process $proc$libresoc.v:188885$13132 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:194682.5-194682.29" + attribute \src "libresoc.v:188886.5-188886.29" switch \initial - attribute \src "libresoc.v:194682.9-194682.17" + attribute \src "libresoc.v:188886.9-188886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000001 @@ -404510,18 +395075,18 @@ module \sprmap$211 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:194712.3-195030.6" - process $proc$libresoc.v:194712$13428 + attribute \src "libresoc.v:188916.3-189237.6" + process $proc$libresoc.v:188916$13133 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:194713.5-194713.29" + attribute \src "libresoc.v:188917.5-188917.29" switch \initial - attribute \src "libresoc.v:194713.9-194713.17" + attribute \src "libresoc.v:188917.9-188917.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -404760,203 +395325,207 @@ module \sprmap$211 assign { } { } assign $1\spr_o[9:0] 10'0001000001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 + case 10'1011010001 assign { } { } assign $1\spr_o[9:0] 10'0001000010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 + case 10'1100000000 assign { } { } assign $1\spr_o[9:0] 10'0001000011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 + case 10'1100000001 assign { } { } assign $1\spr_o[9:0] 10'0001000100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 + case 10'1100000010 assign { } { } assign $1\spr_o[9:0] 10'0001000101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 + case 10'1100000011 assign { } { } assign $1\spr_o[9:0] 10'0001000110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 + case 10'1100000100 assign { } { } assign $1\spr_o[9:0] 10'0001000111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 + case 10'1100000101 assign { } { } assign $1\spr_o[9:0] 10'0001001000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 + case 10'1100000110 assign { } { } assign $1\spr_o[9:0] 10'0001001001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 + case 10'1100000111 assign { } { } assign $1\spr_o[9:0] 10'0001001010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 + case 10'1100001000 assign { } { } assign $1\spr_o[9:0] 10'0001001011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 + case 10'1100001011 assign { } { } assign $1\spr_o[9:0] 10'0001001100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 + case 10'1100001100 assign { } { } assign $1\spr_o[9:0] 10'0001001101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 + case 10'1100001101 assign { } { } assign $1\spr_o[9:0] 10'0001001110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 + case 10'1100001110 assign { } { } assign $1\spr_o[9:0] 10'0001001111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 + case 10'1100010000 assign { } { } assign $1\spr_o[9:0] 10'0001010000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 + case 10'1100010001 assign { } { } assign $1\spr_o[9:0] 10'0001010001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 + case 10'1100010010 assign { } { } assign $1\spr_o[9:0] 10'0001010010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 + case 10'1100010011 assign { } { } assign $1\spr_o[9:0] 10'0001010011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 + case 10'1100010100 assign { } { } assign $1\spr_o[9:0] 10'0001010100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 + case 10'1100010101 assign { } { } assign $1\spr_o[9:0] 10'0001010101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 + case 10'1100010110 assign { } { } assign $1\spr_o[9:0] 10'0001010110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 + case 10'1100010111 assign { } { } assign $1\spr_o[9:0] 10'0001010111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 + case 10'1100011000 assign { } { } assign $1\spr_o[9:0] 10'0001011000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 + case 10'1100011011 assign { } { } assign $1\spr_o[9:0] 10'0001011001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 + case 10'1100011100 assign { } { } assign $1\spr_o[9:0] 10'0001011010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 + case 10'1100011101 assign { } { } assign $1\spr_o[9:0] 10'0001011011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 + case 10'1100011110 assign { } { } assign $1\spr_o[9:0] 10'0001011100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 + case 10'1100100000 assign { } { } assign $1\spr_o[9:0] 10'0001011101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 + case 10'1100100001 assign { } { } assign $1\spr_o[9:0] 10'0001011110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 + case 10'1100100010 assign { } { } assign $1\spr_o[9:0] 10'0001011111 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 + case 10'1100100011 assign { } { } assign $1\spr_o[9:0] 10'0001100000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 + case 10'1100100100 assign { } { } assign $1\spr_o[9:0] 10'0001100001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 + case 10'1100100101 assign { } { } assign $1\spr_o[9:0] 10'0001100010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 + case 10'1100100110 assign { } { } assign $1\spr_o[9:0] 10'0001100011 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 + case 10'1100101000 assign { } { } assign $1\spr_o[9:0] 10'0001100100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 + case 10'1100101001 assign { } { } assign $1\spr_o[9:0] 10'0001100101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 + case 10'1100101010 assign { } { } assign $1\spr_o[9:0] 10'0001100110 attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } - assign $1\spr_o[9:0] 10'0001101000 + assign $1\spr_o[9:0] 10'0001101001 attribute \src "libresoc.v:0.0-0.0" case 10'1100110111 assign { } { } - assign $1\spr_o[9:0] 10'0001101001 + assign $1\spr_o[9:0] 10'0001101010 attribute \src "libresoc.v:0.0-0.0" case 10'1101010000 assign { } { } - assign $1\spr_o[9:0] 10'0001101010 + assign $1\spr_o[9:0] 10'0001101011 attribute \src "libresoc.v:0.0-0.0" case 10'1101010001 assign { } { } - assign $1\spr_o[9:0] 10'0001101011 + assign $1\spr_o[9:0] 10'0001101100 attribute \src "libresoc.v:0.0-0.0" case 10'1101010111 assign { } { } - assign $1\spr_o[9:0] 10'0001101100 + assign $1\spr_o[9:0] 10'0001101101 attribute \src "libresoc.v:0.0-0.0" case 10'1110000000 assign { } { } - assign $1\spr_o[9:0] 10'0001101101 + assign $1\spr_o[9:0] 10'0001101110 attribute \src "libresoc.v:0.0-0.0" case 10'1110000010 assign { } { } - assign $1\spr_o[9:0] 10'0001101110 + assign $1\spr_o[9:0] 10'0001101111 attribute \src "libresoc.v:0.0-0.0" case 10'1111111111 assign { } { } - assign $1\spr_o[9:0] 10'0001101111 + assign $1\spr_o[9:0] 10'0001110000 case assign $1\spr_o[9:0] 10'0000000000 end sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:195031.3-195349.6" - process $proc$libresoc.v:195031$13429 + attribute \src "libresoc.v:189238.3-189559.6" + process $proc$libresoc.v:189238$13134 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:195032.5-195032.29" + attribute \src "libresoc.v:189239.5-189239.29" switch \initial - attribute \src "libresoc.v:195032.9-195032.17" + attribute \src "libresoc.v:189239.9-189239.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:74" switch \spr_i attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 @@ -405195,6 +395764,10 @@ module \sprmap$211 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" case 10'1100000000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -405381,107 +395954,107 @@ module \sprmap$211 update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:195354.1-195466.10" +attribute \src "libresoc.v:189564.1-189705.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_0" attribute \generator "nMigen" module \sram4k_0 - attribute \src "libresoc.v:195405.3-195414.6" + attribute \src "libresoc.v:189640.3-189654.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:195425.3-195434.6" + attribute \src "libresoc.v:189670.3-189684.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:195355.7-195355.20" + attribute \src "libresoc.v:189565.7-189565.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195450.3-195464.6" - wire $0\sram4k_0__ack$next[0:0]$13439 - attribute \src "libresoc.v:195396.3-195397.43" - wire $0\sram4k_0__ack[0:0] - attribute \src "libresoc.v:195415.3-195424.6" - wire width 64 $0\sram4k_0__dat_r[63:0] - attribute \src "libresoc.v:195435.3-195449.6" + attribute \src "libresoc.v:189625.3-189639.6" + wire $0\sram4k_0_wb__ack$next[0:0]$13140 + attribute \src "libresoc.v:189605.3-189606.49" + wire $0\sram4k_0_wb__ack[0:0] + attribute \src "libresoc.v:189655.3-189669.6" + wire width 64 $0\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189615.3-189624.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189685.3-189704.6" wire $0\we[0:0] - attribute \src "libresoc.v:195405.3-195414.6" + attribute \src "libresoc.v:189640.3-189654.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:195425.3-195434.6" + attribute \src "libresoc.v:189670.3-189684.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:195450.3-195464.6" - wire $1\sram4k_0__ack$next[0:0]$13440 - attribute \src "libresoc.v:195372.7-195372.27" - wire $1\sram4k_0__ack[0:0] - attribute \src "libresoc.v:195415.3-195424.6" - wire width 64 $1\sram4k_0__dat_r[63:0] - attribute \src "libresoc.v:195435.3-195449.6" + attribute \src "libresoc.v:189625.3-189639.6" + wire $1\sram4k_0_wb__ack$next[0:0]$13141 + attribute \src "libresoc.v:189582.7-189582.30" + wire $1\sram4k_0_wb__ack[0:0] + attribute \src "libresoc.v:189655.3-189669.6" + wire width 64 $1\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189615.3-189624.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189685.3-189704.6" wire $1\we[0:0] - attribute \src "libresoc.v:195450.3-195464.6" - wire $2\sram4k_0__ack$next[0:0]$13441 - attribute \src "libresoc.v:195435.3-195449.6" + attribute \src "libresoc.v:189640.3-189654.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189670.3-189684.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189625.3-189639.6" + wire $2\sram4k_0_wb__ack$next[0:0]$13142 + attribute \src "libresoc.v:189655.3-189669.6" + wire width 64 $2\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189685.3-189704.6" wire $2\we[0:0] - attribute \src "libresoc.v:195394.17-195394.123" - wire $and$libresoc.v:195394$13431_Y - attribute \src "libresoc.v:195395.17-195395.123" - wire $and$libresoc.v:195395$13432_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + attribute \src "libresoc.v:189685.3-189704.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189604.17-189604.129" + wire $and$libresoc.v:189604$13136_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" - wire input 10 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d - attribute \src "libresoc.v:195355.7-195355.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189565.7-189565.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 9 \sram4k_0__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire \sram4k_0__ack$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 4 \sram4k_0__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 2 \sram4k_0__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 5 \sram4k_0__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 6 \sram4k_0__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 8 \sram4k_0__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 3 \sram4k_0__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 7 \sram4k_0__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_0_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:54" wire \wb_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" - cell $and $and$libresoc.v:195394$13431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sram4k_0__cyc - connect \B \sram4k_0__stb - connect \Y $and$libresoc.v:195394$13431_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - cell $and $and$libresoc.v:195395$13432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + cell $and $and$libresoc.v:189604$13136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sram4k_0__cyc - connect \B \sram4k_0__stb - connect \Y $and$libresoc.v:195395$13432_Y + connect \A \sram4k_0_wb__cyc + connect \B \sram4k_0_wb__stb + connect \Y $and$libresoc.v:189604$13136_Y end + attribute \blackbox 1 attribute \module_not_derived 1 - attribute \src "libresoc.v:195398.21-195404.4" + attribute \src "libresoc.v:189608.21-189614.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -405489,269 +396062,325 @@ module \sram4k_0 connect \q \q connect \we \we end - attribute \src "libresoc.v:195355.7-195355.20" - process $proc$libresoc.v:195355$13442 + attribute \src "libresoc.v:189565.7-189565.20" + process $proc$libresoc.v:189565$13147 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195372.7-195372.27" - process $proc$libresoc.v:195372$13443 + attribute \src "libresoc.v:189582.7-189582.30" + process $proc$libresoc.v:189582$13148 assign { } { } - assign $1\sram4k_0__ack[0:0] 1'0 + assign $1\sram4k_0_wb__ack[0:0] 1'0 sync always sync init - update \sram4k_0__ack $1\sram4k_0__ack[0:0] + update \sram4k_0_wb__ack $1\sram4k_0_wb__ack[0:0] end - attribute \src "libresoc.v:195396.3-195397.43" - process $proc$libresoc.v:195396$13433 + attribute \src "libresoc.v:189605.3-189606.49" + process $proc$libresoc.v:189605$13137 assign { } { } - assign $0\sram4k_0__ack[0:0] \sram4k_0__ack$next + assign $0\sram4k_0_wb__ack[0:0] \sram4k_0_wb__ack$next sync posedge \clk - update \sram4k_0__ack $0\sram4k_0__ack[0:0] + update \sram4k_0_wb__ack $0\sram4k_0_wb__ack[0:0] end - attribute \src "libresoc.v:195405.3-195414.6" - process $proc$libresoc.v:195405$13434 + attribute \src "libresoc.v:189615.3-189624.6" + process $proc$libresoc.v:189615$13138 assign { } { } assign { } { } - assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:195406.5-195406.29" + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189616.5-189616.29" switch \initial - attribute \src "libresoc.v:195406.9-195406.17" + attribute \src "libresoc.v:189616.9-189616.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\a[8:0] \sram4k_0__adr + assign $1\wb_active[0:0] \$1 case - assign $1\a[8:0] 9'000000000 + assign $1\wb_active[0:0] 1'0 end sync always - update \a $0\a[8:0] + update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:195415.3-195424.6" - process $proc$libresoc.v:195415$13435 + attribute \src "libresoc.v:189625.3-189639.6" + process $proc$libresoc.v:189625$13139 assign { } { } assign { } { } - assign $0\sram4k_0__dat_r[63:0] $1\sram4k_0__dat_r[63:0] - attribute \src "libresoc.v:195416.5-195416.29" + assign { } { } + assign $0\sram4k_0_wb__ack$next[0:0]$13140 $2\sram4k_0_wb__ack$next[0:0]$13142 + attribute \src "libresoc.v:189626.5-189626.29" switch \initial - attribute \src "libresoc.v:195416.9-195416.17" + attribute \src "libresoc.v:189626.9-189626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $1\sram4k_0_wb__ack$next[0:0]$13141 \wb_active case + assign $1\sram4k_0_wb__ack$next[0:0]$13141 \sram4k_0_wb__ack end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_0__dat_r[63:0] \q + assign $2\sram4k_0_wb__ack$next[0:0]$13142 1'0 case - assign $1\sram4k_0__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sram4k_0_wb__ack$next[0:0]$13142 $1\sram4k_0_wb__ack$next[0:0]$13141 end sync always - update \sram4k_0__dat_r $0\sram4k_0__dat_r[63:0] + update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13140 end - attribute \src "libresoc.v:195425.3-195434.6" - process $proc$libresoc.v:195425$13436 + attribute \src "libresoc.v:189640.3-189654.6" + process $proc$libresoc.v:189640$13143 assign { } { } assign { } { } - assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:195426.5-195426.29" + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189641.5-189641.29" switch \initial - attribute \src "libresoc.v:195426.9-195426.17" + attribute \src "libresoc.v:189641.9-189641.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d[63:0] \sram4k_0__dat_w + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_0_wb__adr + case + assign $2\a[8:0] 9'000000000 + end case - assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\a[8:0] 9'000000000 end sync always - update \d $0\d[63:0] + update \a $0\a[8:0] end - attribute \src "libresoc.v:195435.3-195449.6" - process $proc$libresoc.v:195435$13437 + attribute \src "libresoc.v:189655.3-189669.6" + process $proc$libresoc.v:189655$13144 assign { } { } assign { } { } - assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:195436.5-195436.29" + assign $0\sram4k_0_wb__dat_r[63:0] $1\sram4k_0_wb__dat_r[63:0] + attribute \src "libresoc.v:189656.5-189656.29" switch \initial - attribute \src "libresoc.v:195436.9-195436.17" + attribute \src "libresoc.v:189656.9-189656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\we[0:0] $2\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" - switch \sram4k_0__we + assign $1\sram4k_0_wb__dat_r[63:0] $2\sram4k_0_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\we[0:0] \sram4k_0__sel [0] + assign $2\sram4k_0_wb__dat_r[63:0] \q case - assign $2\we[0:0] 1'0 + assign $2\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\we[0:0] 1'0 + assign $1\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \we $0\we[0:0] + update \sram4k_0_wb__dat_r $0\sram4k_0_wb__dat_r[63:0] end - attribute \src "libresoc.v:195450.3-195464.6" - process $proc$libresoc.v:195450$13438 - assign { } { } + attribute \src "libresoc.v:189670.3-189684.6" + process $proc$libresoc.v:189670$13145 assign { } { } assign { } { } - assign $0\sram4k_0__ack$next[0:0]$13439 $2\sram4k_0__ack$next[0:0]$13441 - attribute \src "libresoc.v:195451.5-195451.29" + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189671.5-189671.29" switch \initial - attribute \src "libresoc.v:195451.9-195451.17" + attribute \src "libresoc.v:189671.9-189671.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - switch \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_0__ack$next[0:0]$13440 1'1 + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_0_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end case - assign $1\sram4k_0__ack$next[0:0]$13440 1'0 + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189685.3-189704.6" + process $proc$libresoc.v:189685$13146 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189686.5-189686.29" + switch \initial + attribute \src "libresoc.v:189686.9-189686.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_0__ack$next[0:0]$13441 1'0 + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:70" + switch \sram4k_0_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_0_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end case - assign $2\sram4k_0__ack$next[0:0]$13441 $1\sram4k_0__ack$next[0:0]$13440 + assign $1\we[0:0] 1'0 end sync always - update \sram4k_0__ack$next $0\sram4k_0__ack$next[0:0]$13439 + update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:195394$13431_Y - connect \$3 $and$libresoc.v:195395$13432_Y - connect \wb_active \$1 + connect \$1 $and$libresoc.v:189604$13136_Y end -attribute \src "libresoc.v:195470.1-195582.10" +attribute \src "libresoc.v:189709.1-189850.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_1" attribute \generator "nMigen" module \sram4k_1 - attribute \src "libresoc.v:195521.3-195530.6" + attribute \src "libresoc.v:189785.3-189799.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:195541.3-195550.6" + attribute \src "libresoc.v:189815.3-189829.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:195471.7-195471.20" + attribute \src "libresoc.v:189710.7-189710.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195566.3-195580.6" - wire $0\sram4k_1__ack$next[0:0]$13452 - attribute \src "libresoc.v:195512.3-195513.43" - wire $0\sram4k_1__ack[0:0] - attribute \src "libresoc.v:195531.3-195540.6" - wire width 64 $0\sram4k_1__dat_r[63:0] - attribute \src "libresoc.v:195551.3-195565.6" + attribute \src "libresoc.v:189770.3-189784.6" + wire $0\sram4k_1_wb__ack$next[0:0]$13153 + attribute \src "libresoc.v:189750.3-189751.49" + wire $0\sram4k_1_wb__ack[0:0] + attribute \src "libresoc.v:189800.3-189814.6" + wire width 64 $0\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189760.3-189769.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189830.3-189849.6" wire $0\we[0:0] - attribute \src "libresoc.v:195521.3-195530.6" + attribute \src "libresoc.v:189785.3-189799.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:195541.3-195550.6" + attribute \src "libresoc.v:189815.3-189829.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:195566.3-195580.6" - wire $1\sram4k_1__ack$next[0:0]$13453 - attribute \src "libresoc.v:195488.7-195488.27" - wire $1\sram4k_1__ack[0:0] - attribute \src "libresoc.v:195531.3-195540.6" - wire width 64 $1\sram4k_1__dat_r[63:0] - attribute \src "libresoc.v:195551.3-195565.6" + attribute \src "libresoc.v:189770.3-189784.6" + wire $1\sram4k_1_wb__ack$next[0:0]$13154 + attribute \src "libresoc.v:189727.7-189727.30" + wire $1\sram4k_1_wb__ack[0:0] + attribute \src "libresoc.v:189800.3-189814.6" + wire width 64 $1\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189760.3-189769.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189830.3-189849.6" wire $1\we[0:0] - attribute \src "libresoc.v:195566.3-195580.6" - wire $2\sram4k_1__ack$next[0:0]$13454 - attribute \src "libresoc.v:195551.3-195565.6" + attribute \src "libresoc.v:189785.3-189799.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189815.3-189829.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189770.3-189784.6" + wire $2\sram4k_1_wb__ack$next[0:0]$13155 + attribute \src "libresoc.v:189800.3-189814.6" + wire width 64 $2\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189830.3-189849.6" wire $2\we[0:0] - attribute \src "libresoc.v:195510.17-195510.123" - wire $and$libresoc.v:195510$13444_Y - attribute \src "libresoc.v:195511.17-195511.123" - wire $and$libresoc.v:195511$13445_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + attribute \src "libresoc.v:189830.3-189849.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189749.17-189749.129" + wire $and$libresoc.v:189749$13149_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" - wire input 10 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d - attribute \src "libresoc.v:195471.7-195471.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189710.7-189710.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 9 \sram4k_1__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire \sram4k_1__ack$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 4 \sram4k_1__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 2 \sram4k_1__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 5 \sram4k_1__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 6 \sram4k_1__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 8 \sram4k_1__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 3 \sram4k_1__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 7 \sram4k_1__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_1_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:54" wire \wb_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" - cell $and $and$libresoc.v:195510$13444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + cell $and $and$libresoc.v:189749$13149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sram4k_1__cyc - connect \B \sram4k_1__stb - connect \Y $and$libresoc.v:195510$13444_Y + connect \A \sram4k_1_wb__cyc + connect \B \sram4k_1_wb__stb + connect \Y $and$libresoc.v:189749$13149_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - cell $and $and$libresoc.v:195511$13445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sram4k_1__cyc - connect \B \sram4k_1__stb - connect \Y $and$libresoc.v:195511$13445_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:195514.21-195520.4" attribute \blackbox 1 + attribute \module_not_derived 1 + attribute \src "libresoc.v:189753.21-189759.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -405759,268 +396388,325 @@ module \sram4k_1 connect \q \q connect \we \we end - attribute \src "libresoc.v:195471.7-195471.20" - process $proc$libresoc.v:195471$13455 + attribute \src "libresoc.v:189710.7-189710.20" + process $proc$libresoc.v:189710$13160 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195488.7-195488.27" - process $proc$libresoc.v:195488$13456 + attribute \src "libresoc.v:189727.7-189727.30" + process $proc$libresoc.v:189727$13161 assign { } { } - assign $1\sram4k_1__ack[0:0] 1'0 + assign $1\sram4k_1_wb__ack[0:0] 1'0 sync always sync init - update \sram4k_1__ack $1\sram4k_1__ack[0:0] + update \sram4k_1_wb__ack $1\sram4k_1_wb__ack[0:0] end - attribute \src "libresoc.v:195512.3-195513.43" - process $proc$libresoc.v:195512$13446 + attribute \src "libresoc.v:189750.3-189751.49" + process $proc$libresoc.v:189750$13150 assign { } { } - assign $0\sram4k_1__ack[0:0] \sram4k_1__ack$next + assign $0\sram4k_1_wb__ack[0:0] \sram4k_1_wb__ack$next sync posedge \clk - update \sram4k_1__ack $0\sram4k_1__ack[0:0] + update \sram4k_1_wb__ack $0\sram4k_1_wb__ack[0:0] end - attribute \src "libresoc.v:195521.3-195530.6" - process $proc$libresoc.v:195521$13447 + attribute \src "libresoc.v:189760.3-189769.6" + process $proc$libresoc.v:189760$13151 assign { } { } assign { } { } - assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:195522.5-195522.29" + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189761.5-189761.29" switch \initial - attribute \src "libresoc.v:195522.9-195522.17" + attribute \src "libresoc.v:189761.9-189761.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\a[8:0] \sram4k_1__adr + assign $1\wb_active[0:0] \$1 case - assign $1\a[8:0] 9'000000000 + assign $1\wb_active[0:0] 1'0 end sync always - update \a $0\a[8:0] + update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:195531.3-195540.6" - process $proc$libresoc.v:195531$13448 + attribute \src "libresoc.v:189770.3-189784.6" + process $proc$libresoc.v:189770$13152 + assign { } { } assign { } { } assign { } { } - assign $0\sram4k_1__dat_r[63:0] $1\sram4k_1__dat_r[63:0] - attribute \src "libresoc.v:195532.5-195532.29" + assign $0\sram4k_1_wb__ack$next[0:0]$13153 $2\sram4k_1_wb__ack$next[0:0]$13155 + attribute \src "libresoc.v:189771.5-189771.29" switch \initial - attribute \src "libresoc.v:195532.9-195532.17" + attribute \src "libresoc.v:189771.9-189771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $1\sram4k_1_wb__ack$next[0:0]$13154 \wb_active case + assign $1\sram4k_1_wb__ack$next[0:0]$13154 \sram4k_1_wb__ack end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_1__dat_r[63:0] \q + assign $2\sram4k_1_wb__ack$next[0:0]$13155 1'0 case - assign $1\sram4k_1__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sram4k_1_wb__ack$next[0:0]$13155 $1\sram4k_1_wb__ack$next[0:0]$13154 end sync always - update \sram4k_1__dat_r $0\sram4k_1__dat_r[63:0] + update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13153 end - attribute \src "libresoc.v:195541.3-195550.6" - process $proc$libresoc.v:195541$13449 + attribute \src "libresoc.v:189785.3-189799.6" + process $proc$libresoc.v:189785$13156 assign { } { } assign { } { } - assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:195542.5-195542.29" + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189786.5-189786.29" switch \initial - attribute \src "libresoc.v:195542.9-195542.17" + attribute \src "libresoc.v:189786.9-189786.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d[63:0] \sram4k_1__dat_w + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_1_wb__adr + case + assign $2\a[8:0] 9'000000000 + end case - assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\a[8:0] 9'000000000 end sync always - update \d $0\d[63:0] + update \a $0\a[8:0] end - attribute \src "libresoc.v:195551.3-195565.6" - process $proc$libresoc.v:195551$13450 + attribute \src "libresoc.v:189800.3-189814.6" + process $proc$libresoc.v:189800$13157 assign { } { } assign { } { } - assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:195552.5-195552.29" + assign $0\sram4k_1_wb__dat_r[63:0] $1\sram4k_1_wb__dat_r[63:0] + attribute \src "libresoc.v:189801.5-189801.29" switch \initial - attribute \src "libresoc.v:195552.9-195552.17" + attribute \src "libresoc.v:189801.9-189801.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\we[0:0] $2\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" - switch \sram4k_1__we + assign $1\sram4k_1_wb__dat_r[63:0] $2\sram4k_1_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\we[0:0] \sram4k_1__sel [0] + assign $2\sram4k_1_wb__dat_r[63:0] \q case - assign $2\we[0:0] 1'0 + assign $2\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\we[0:0] 1'0 + assign $1\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \we $0\we[0:0] + update \sram4k_1_wb__dat_r $0\sram4k_1_wb__dat_r[63:0] end - attribute \src "libresoc.v:195566.3-195580.6" - process $proc$libresoc.v:195566$13451 - assign { } { } + attribute \src "libresoc.v:189815.3-189829.6" + process $proc$libresoc.v:189815$13158 assign { } { } assign { } { } - assign $0\sram4k_1__ack$next[0:0]$13452 $2\sram4k_1__ack$next[0:0]$13454 - attribute \src "libresoc.v:195567.5-195567.29" + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189816.5-189816.29" switch \initial - attribute \src "libresoc.v:195567.9-195567.17" + attribute \src "libresoc.v:189816.9-189816.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - switch \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_1__ack$next[0:0]$13453 1'1 + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_1_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end case - assign $1\sram4k_1__ack$next[0:0]$13453 1'0 + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189830.3-189849.6" + process $proc$libresoc.v:189830$13159 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189831.5-189831.29" + switch \initial + attribute \src "libresoc.v:189831.9-189831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_1__ack$next[0:0]$13454 1'0 + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:70" + switch \sram4k_1_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_1_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end case - assign $2\sram4k_1__ack$next[0:0]$13454 $1\sram4k_1__ack$next[0:0]$13453 + assign $1\we[0:0] 1'0 end sync always - update \sram4k_1__ack$next $0\sram4k_1__ack$next[0:0]$13452 + update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:195510$13444_Y - connect \$3 $and$libresoc.v:195511$13445_Y - connect \wb_active \$1 + connect \$1 $and$libresoc.v:189749$13149_Y end -attribute \src "libresoc.v:195586.1-195698.10" +attribute \src "libresoc.v:189854.1-189995.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_2" attribute \generator "nMigen" module \sram4k_2 - attribute \src "libresoc.v:195637.3-195646.6" + attribute \src "libresoc.v:189930.3-189944.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:195657.3-195666.6" + attribute \src "libresoc.v:189960.3-189974.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:195587.7-195587.20" + attribute \src "libresoc.v:189855.7-189855.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195682.3-195696.6" - wire $0\sram4k_2__ack$next[0:0]$13465 - attribute \src "libresoc.v:195628.3-195629.43" - wire $0\sram4k_2__ack[0:0] - attribute \src "libresoc.v:195647.3-195656.6" - wire width 64 $0\sram4k_2__dat_r[63:0] - attribute \src "libresoc.v:195667.3-195681.6" + attribute \src "libresoc.v:189915.3-189929.6" + wire $0\sram4k_2_wb__ack$next[0:0]$13166 + attribute \src "libresoc.v:189895.3-189896.49" + wire $0\sram4k_2_wb__ack[0:0] + attribute \src "libresoc.v:189945.3-189959.6" + wire width 64 $0\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189905.3-189914.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:189975.3-189994.6" wire $0\we[0:0] - attribute \src "libresoc.v:195637.3-195646.6" + attribute \src "libresoc.v:189930.3-189944.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:195657.3-195666.6" + attribute \src "libresoc.v:189960.3-189974.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:195682.3-195696.6" - wire $1\sram4k_2__ack$next[0:0]$13466 - attribute \src "libresoc.v:195604.7-195604.27" - wire $1\sram4k_2__ack[0:0] - attribute \src "libresoc.v:195647.3-195656.6" - wire width 64 $1\sram4k_2__dat_r[63:0] - attribute \src "libresoc.v:195667.3-195681.6" + attribute \src "libresoc.v:189915.3-189929.6" + wire $1\sram4k_2_wb__ack$next[0:0]$13167 + attribute \src "libresoc.v:189872.7-189872.30" + wire $1\sram4k_2_wb__ack[0:0] + attribute \src "libresoc.v:189945.3-189959.6" + wire width 64 $1\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189905.3-189914.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:189975.3-189994.6" wire $1\we[0:0] - attribute \src "libresoc.v:195682.3-195696.6" - wire $2\sram4k_2__ack$next[0:0]$13467 - attribute \src "libresoc.v:195667.3-195681.6" + attribute \src "libresoc.v:189930.3-189944.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:189960.3-189974.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:189915.3-189929.6" + wire $2\sram4k_2_wb__ack$next[0:0]$13168 + attribute \src "libresoc.v:189945.3-189959.6" + wire width 64 $2\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189975.3-189994.6" wire $2\we[0:0] - attribute \src "libresoc.v:195626.17-195626.123" - wire $and$libresoc.v:195626$13457_Y - attribute \src "libresoc.v:195627.17-195627.123" - wire $and$libresoc.v:195627$13458_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + attribute \src "libresoc.v:189975.3-189994.6" + wire $3\we[0:0] + attribute \src "libresoc.v:189894.17-189894.129" + wire $and$libresoc.v:189894$13162_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" - wire input 10 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d - attribute \src "libresoc.v:195587.7-195587.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:189855.7-189855.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 9 \sram4k_2__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire \sram4k_2__ack$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 4 \sram4k_2__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 2 \sram4k_2__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 5 \sram4k_2__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 6 \sram4k_2__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 8 \sram4k_2__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 3 \sram4k_2__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 7 \sram4k_2__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_2_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:54" wire \wb_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" - cell $and $and$libresoc.v:195626$13457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + cell $and $and$libresoc.v:189894$13162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sram4k_2__cyc - connect \B \sram4k_2__stb - connect \Y $and$libresoc.v:195626$13457_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - cell $and $and$libresoc.v:195627$13458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sram4k_2__cyc - connect \B \sram4k_2__stb - connect \Y $and$libresoc.v:195627$13458_Y + connect \A \sram4k_2_wb__cyc + connect \B \sram4k_2_wb__stb + connect \Y $and$libresoc.v:189894$13162_Y end + attribute \blackbox 1 attribute \module_not_derived 1 - attribute \src "libresoc.v:195630.21-195636.4" + attribute \src "libresoc.v:189898.21-189904.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -406028,268 +396714,325 @@ module \sram4k_2 connect \q \q connect \we \we end - attribute \src "libresoc.v:195587.7-195587.20" - process $proc$libresoc.v:195587$13468 + attribute \src "libresoc.v:189855.7-189855.20" + process $proc$libresoc.v:189855$13173 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195604.7-195604.27" - process $proc$libresoc.v:195604$13469 + attribute \src "libresoc.v:189872.7-189872.30" + process $proc$libresoc.v:189872$13174 assign { } { } - assign $1\sram4k_2__ack[0:0] 1'0 + assign $1\sram4k_2_wb__ack[0:0] 1'0 sync always sync init - update \sram4k_2__ack $1\sram4k_2__ack[0:0] + update \sram4k_2_wb__ack $1\sram4k_2_wb__ack[0:0] end - attribute \src "libresoc.v:195628.3-195629.43" - process $proc$libresoc.v:195628$13459 + attribute \src "libresoc.v:189895.3-189896.49" + process $proc$libresoc.v:189895$13163 assign { } { } - assign $0\sram4k_2__ack[0:0] \sram4k_2__ack$next + assign $0\sram4k_2_wb__ack[0:0] \sram4k_2_wb__ack$next sync posedge \clk - update \sram4k_2__ack $0\sram4k_2__ack[0:0] + update \sram4k_2_wb__ack $0\sram4k_2_wb__ack[0:0] end - attribute \src "libresoc.v:195637.3-195646.6" - process $proc$libresoc.v:195637$13460 + attribute \src "libresoc.v:189905.3-189914.6" + process $proc$libresoc.v:189905$13164 assign { } { } assign { } { } - assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:195638.5-195638.29" + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:189906.5-189906.29" switch \initial - attribute \src "libresoc.v:195638.9-195638.17" + attribute \src "libresoc.v:189906.9-189906.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\a[8:0] \sram4k_2__adr + assign $1\wb_active[0:0] \$1 case - assign $1\a[8:0] 9'000000000 + assign $1\wb_active[0:0] 1'0 end sync always - update \a $0\a[8:0] + update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:195647.3-195656.6" - process $proc$libresoc.v:195647$13461 + attribute \src "libresoc.v:189915.3-189929.6" + process $proc$libresoc.v:189915$13165 + assign { } { } assign { } { } assign { } { } - assign $0\sram4k_2__dat_r[63:0] $1\sram4k_2__dat_r[63:0] - attribute \src "libresoc.v:195648.5-195648.29" + assign $0\sram4k_2_wb__ack$next[0:0]$13166 $2\sram4k_2_wb__ack$next[0:0]$13168 + attribute \src "libresoc.v:189916.5-189916.29" switch \initial - attribute \src "libresoc.v:195648.9-195648.17" + attribute \src "libresoc.v:189916.9-189916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $1\sram4k_2_wb__ack$next[0:0]$13167 \wb_active case + assign $1\sram4k_2_wb__ack$next[0:0]$13167 \sram4k_2_wb__ack end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_2__dat_r[63:0] \q + assign $2\sram4k_2_wb__ack$next[0:0]$13168 1'0 case - assign $1\sram4k_2__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sram4k_2_wb__ack$next[0:0]$13168 $1\sram4k_2_wb__ack$next[0:0]$13167 end sync always - update \sram4k_2__dat_r $0\sram4k_2__dat_r[63:0] + update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13166 end - attribute \src "libresoc.v:195657.3-195666.6" - process $proc$libresoc.v:195657$13462 + attribute \src "libresoc.v:189930.3-189944.6" + process $proc$libresoc.v:189930$13169 assign { } { } assign { } { } - assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:195658.5-195658.29" + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:189931.5-189931.29" switch \initial - attribute \src "libresoc.v:195658.9-195658.17" + attribute \src "libresoc.v:189931.9-189931.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d[63:0] \sram4k_2__dat_w + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_2_wb__adr + case + assign $2\a[8:0] 9'000000000 + end case - assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\a[8:0] 9'000000000 end sync always - update \d $0\d[63:0] + update \a $0\a[8:0] end - attribute \src "libresoc.v:195667.3-195681.6" - process $proc$libresoc.v:195667$13463 + attribute \src "libresoc.v:189945.3-189959.6" + process $proc$libresoc.v:189945$13170 assign { } { } assign { } { } - assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:195668.5-195668.29" + assign $0\sram4k_2_wb__dat_r[63:0] $1\sram4k_2_wb__dat_r[63:0] + attribute \src "libresoc.v:189946.5-189946.29" switch \initial - attribute \src "libresoc.v:195668.9-195668.17" + attribute \src "libresoc.v:189946.9-189946.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\we[0:0] $2\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" - switch \sram4k_2__we + assign $1\sram4k_2_wb__dat_r[63:0] $2\sram4k_2_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\we[0:0] \sram4k_2__sel [0] + assign $2\sram4k_2_wb__dat_r[63:0] \q case - assign $2\we[0:0] 1'0 + assign $2\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\we[0:0] 1'0 + assign $1\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \we $0\we[0:0] + update \sram4k_2_wb__dat_r $0\sram4k_2_wb__dat_r[63:0] end - attribute \src "libresoc.v:195682.3-195696.6" - process $proc$libresoc.v:195682$13464 + attribute \src "libresoc.v:189960.3-189974.6" + process $proc$libresoc.v:189960$13171 assign { } { } assign { } { } - assign { } { } - assign $0\sram4k_2__ack$next[0:0]$13465 $2\sram4k_2__ack$next[0:0]$13467 - attribute \src "libresoc.v:195683.5-195683.29" + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:189961.5-189961.29" switch \initial - attribute \src "libresoc.v:195683.9-195683.17" + attribute \src "libresoc.v:189961.9-189961.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - switch \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_2__ack$next[0:0]$13466 1'1 + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_2_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end case - assign $1\sram4k_2__ack$next[0:0]$13466 1'0 + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:189975.3-189994.6" + process $proc$libresoc.v:189975$13172 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:189976.5-189976.29" + switch \initial + attribute \src "libresoc.v:189976.9-189976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_2__ack$next[0:0]$13467 1'0 + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:70" + switch \sram4k_2_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_2_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end case - assign $2\sram4k_2__ack$next[0:0]$13467 $1\sram4k_2__ack$next[0:0]$13466 + assign $1\we[0:0] 1'0 end sync always - update \sram4k_2__ack$next $0\sram4k_2__ack$next[0:0]$13465 + update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:195626$13457_Y - connect \$3 $and$libresoc.v:195627$13458_Y - connect \wb_active \$1 + connect \$1 $and$libresoc.v:189894$13162_Y end -attribute \src "libresoc.v:195702.1-195814.10" +attribute \src "libresoc.v:189999.1-190140.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.sram4k_3" attribute \generator "nMigen" module \sram4k_3 - attribute \src "libresoc.v:195753.3-195762.6" + attribute \src "libresoc.v:190075.3-190089.6" wire width 9 $0\a[8:0] - attribute \src "libresoc.v:195773.3-195782.6" + attribute \src "libresoc.v:190105.3-190119.6" wire width 64 $0\d[63:0] - attribute \src "libresoc.v:195703.7-195703.20" + attribute \src "libresoc.v:190000.7-190000.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195798.3-195812.6" - wire $0\sram4k_3__ack$next[0:0]$13478 - attribute \src "libresoc.v:195744.3-195745.43" - wire $0\sram4k_3__ack[0:0] - attribute \src "libresoc.v:195763.3-195772.6" - wire width 64 $0\sram4k_3__dat_r[63:0] - attribute \src "libresoc.v:195783.3-195797.6" + attribute \src "libresoc.v:190060.3-190074.6" + wire $0\sram4k_3_wb__ack$next[0:0]$13179 + attribute \src "libresoc.v:190040.3-190041.49" + wire $0\sram4k_3_wb__ack[0:0] + attribute \src "libresoc.v:190090.3-190104.6" + wire width 64 $0\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:190050.3-190059.6" + wire $0\wb_active[0:0] + attribute \src "libresoc.v:190120.3-190139.6" wire $0\we[0:0] - attribute \src "libresoc.v:195753.3-195762.6" + attribute \src "libresoc.v:190075.3-190089.6" wire width 9 $1\a[8:0] - attribute \src "libresoc.v:195773.3-195782.6" + attribute \src "libresoc.v:190105.3-190119.6" wire width 64 $1\d[63:0] - attribute \src "libresoc.v:195798.3-195812.6" - wire $1\sram4k_3__ack$next[0:0]$13479 - attribute \src "libresoc.v:195720.7-195720.27" - wire $1\sram4k_3__ack[0:0] - attribute \src "libresoc.v:195763.3-195772.6" - wire width 64 $1\sram4k_3__dat_r[63:0] - attribute \src "libresoc.v:195783.3-195797.6" + attribute \src "libresoc.v:190060.3-190074.6" + wire $1\sram4k_3_wb__ack$next[0:0]$13180 + attribute \src "libresoc.v:190017.7-190017.30" + wire $1\sram4k_3_wb__ack[0:0] + attribute \src "libresoc.v:190090.3-190104.6" + wire width 64 $1\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:190050.3-190059.6" + wire $1\wb_active[0:0] + attribute \src "libresoc.v:190120.3-190139.6" wire $1\we[0:0] - attribute \src "libresoc.v:195798.3-195812.6" - wire $2\sram4k_3__ack$next[0:0]$13480 - attribute \src "libresoc.v:195783.3-195797.6" + attribute \src "libresoc.v:190075.3-190089.6" + wire width 9 $2\a[8:0] + attribute \src "libresoc.v:190105.3-190119.6" + wire width 64 $2\d[63:0] + attribute \src "libresoc.v:190060.3-190074.6" + wire $2\sram4k_3_wb__ack$next[0:0]$13181 + attribute \src "libresoc.v:190090.3-190104.6" + wire width 64 $2\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:190120.3-190139.6" wire $2\we[0:0] - attribute \src "libresoc.v:195742.17-195742.123" - wire $and$libresoc.v:195742$13470_Y - attribute \src "libresoc.v:195743.17-195743.123" - wire $and$libresoc.v:195743$13471_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + attribute \src "libresoc.v:190120.3-190139.6" + wire $3\we[0:0] + attribute \src "libresoc.v:190039.17-190039.129" + wire $and$libresoc.v:190039$13175_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:39" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" - wire input 10 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" + wire input 11 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" wire width 64 \d - attribute \src "libresoc.v:195703.7-195703.15" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire input 2 \enable + attribute \src "libresoc.v:190000.7-190000.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 9 \sram4k_3__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire \sram4k_3__ack$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 4 \sram4k_3__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 2 \sram4k_3__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 5 \sram4k_3__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 6 \sram4k_3__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 8 \sram4k_3__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 3 \sram4k_3__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 7 \sram4k_3__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:48" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 5 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire \sram4k_3_wb__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 6 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 3 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 7 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 8 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 10 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 4 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 9 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:54" wire \wb_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" wire \we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" - cell $and $and$libresoc.v:195742$13470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" + cell $and $and$libresoc.v:190039$13175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sram4k_3__cyc - connect \B \sram4k_3__stb - connect \Y $and$libresoc.v:195742$13470_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - cell $and $and$libresoc.v:195743$13471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sram4k_3__cyc - connect \B \sram4k_3__stb - connect \Y $and$libresoc.v:195743$13471_Y + connect \A \sram4k_3_wb__cyc + connect \B \sram4k_3_wb__stb + connect \Y $and$libresoc.v:190039$13175_Y end + attribute \blackbox 1 attribute \module_not_derived 1 - attribute \src "libresoc.v:195746.21-195752.4" + attribute \src "libresoc.v:190043.21-190049.4" cell \SPBlock_512W64B8W \U$$0 connect \a \a connect \clk \clk @@ -406297,198 +397040,255 @@ module \sram4k_3 connect \q \q connect \we \we end - attribute \src "libresoc.v:195703.7-195703.20" - process $proc$libresoc.v:195703$13481 + attribute \src "libresoc.v:190000.7-190000.20" + process $proc$libresoc.v:190000$13186 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195720.7-195720.27" - process $proc$libresoc.v:195720$13482 + attribute \src "libresoc.v:190017.7-190017.30" + process $proc$libresoc.v:190017$13187 assign { } { } - assign $1\sram4k_3__ack[0:0] 1'0 + assign $1\sram4k_3_wb__ack[0:0] 1'0 sync always sync init - update \sram4k_3__ack $1\sram4k_3__ack[0:0] + update \sram4k_3_wb__ack $1\sram4k_3_wb__ack[0:0] end - attribute \src "libresoc.v:195744.3-195745.43" - process $proc$libresoc.v:195744$13472 + attribute \src "libresoc.v:190040.3-190041.49" + process $proc$libresoc.v:190040$13176 assign { } { } - assign $0\sram4k_3__ack[0:0] \sram4k_3__ack$next + assign $0\sram4k_3_wb__ack[0:0] \sram4k_3_wb__ack$next sync posedge \clk - update \sram4k_3__ack $0\sram4k_3__ack[0:0] + update \sram4k_3_wb__ack $0\sram4k_3_wb__ack[0:0] end - attribute \src "libresoc.v:195753.3-195762.6" - process $proc$libresoc.v:195753$13473 + attribute \src "libresoc.v:190050.3-190059.6" + process $proc$libresoc.v:190050$13177 assign { } { } assign { } { } - assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:195754.5-195754.29" + assign $0\wb_active[0:0] $1\wb_active[0:0] + attribute \src "libresoc.v:190051.5-190051.29" switch \initial - attribute \src "libresoc.v:195754.9-195754.17" + attribute \src "libresoc.v:190051.9-190051.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\a[8:0] \sram4k_3__adr + assign $1\wb_active[0:0] \$1 case - assign $1\a[8:0] 9'000000000 + assign $1\wb_active[0:0] 1'0 end sync always - update \a $0\a[8:0] + update \wb_active $0\wb_active[0:0] end - attribute \src "libresoc.v:195763.3-195772.6" - process $proc$libresoc.v:195763$13474 + attribute \src "libresoc.v:190060.3-190074.6" + process $proc$libresoc.v:190060$13178 assign { } { } assign { } { } - assign $0\sram4k_3__dat_r[63:0] $1\sram4k_3__dat_r[63:0] - attribute \src "libresoc.v:195764.5-195764.29" + assign { } { } + assign $0\sram4k_3_wb__ack$next[0:0]$13179 $2\sram4k_3_wb__ack$next[0:0]$13181 + attribute \src "libresoc.v:190061.5-190061.29" switch \initial - attribute \src "libresoc.v:195764.9-195764.17" + attribute \src "libresoc.v:190061.9-190061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable + attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign { } { } + assign $1\sram4k_3_wb__ack$next[0:0]$13180 \wb_active case + assign $1\sram4k_3_wb__ack$next[0:0]$13180 \sram4k_3_wb__ack end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_3__dat_r[63:0] \q + assign $2\sram4k_3_wb__ack$next[0:0]$13181 1'0 case - assign $1\sram4k_3__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sram4k_3_wb__ack$next[0:0]$13181 $1\sram4k_3_wb__ack$next[0:0]$13180 end sync always - update \sram4k_3__dat_r $0\sram4k_3__dat_r[63:0] + update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13179 end - attribute \src "libresoc.v:195773.3-195782.6" - process $proc$libresoc.v:195773$13475 + attribute \src "libresoc.v:190075.3-190089.6" + process $proc$libresoc.v:190075$13182 assign { } { } assign { } { } - assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:195774.5-195774.29" + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:190076.5-190076.29" switch \initial - attribute \src "libresoc.v:195774.9-195774.17" + attribute \src "libresoc.v:190076.9-190076.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d[63:0] \sram4k_3__dat_w + assign $1\a[8:0] $2\a[8:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a[8:0] \sram4k_3_wb__adr + case + assign $2\a[8:0] 9'000000000 + end case - assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\a[8:0] 9'000000000 end sync always - update \d $0\d[63:0] + update \a $0\a[8:0] end - attribute \src "libresoc.v:195783.3-195797.6" - process $proc$libresoc.v:195783$13476 + attribute \src "libresoc.v:190090.3-190104.6" + process $proc$libresoc.v:190090$13183 assign { } { } assign { } { } - assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:195784.5-195784.29" + assign $0\sram4k_3_wb__dat_r[63:0] $1\sram4k_3_wb__dat_r[63:0] + attribute \src "libresoc.v:190091.5-190091.29" switch \initial - attribute \src "libresoc.v:195784.9-195784.17" + attribute \src "libresoc.v:190091.9-190091.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" - switch \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\we[0:0] $2\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" - switch \sram4k_3__we + assign $1\sram4k_3_wb__dat_r[63:0] $2\sram4k_3_wb__dat_r[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\we[0:0] \sram4k_3__sel [0] + assign $2\sram4k_3_wb__dat_r[63:0] \q case - assign $2\we[0:0] 1'0 + assign $2\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\we[0:0] 1'0 + assign $1\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \we $0\we[0:0] + update \sram4k_3_wb__dat_r $0\sram4k_3_wb__dat_r[63:0] end - attribute \src "libresoc.v:195798.3-195812.6" - process $proc$libresoc.v:195798$13477 - assign { } { } + attribute \src "libresoc.v:190105.3-190119.6" + process $proc$libresoc.v:190105$13184 assign { } { } assign { } { } - assign $0\sram4k_3__ack$next[0:0]$13478 $2\sram4k_3__ack$next[0:0]$13480 - attribute \src "libresoc.v:195799.5-195799.29" + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:190106.5-190106.29" switch \initial - attribute \src "libresoc.v:195799.9-195799.17" + attribute \src "libresoc.v:190106.9-190106.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" - switch \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sram4k_3__ack$next[0:0]$13479 1'1 + assign $1\d[63:0] $2\d[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\d[63:0] \sram4k_3_wb__dat_w + case + assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end case - assign $1\sram4k_3__ack$next[0:0]$13479 1'0 + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:190120.3-190139.6" + process $proc$libresoc.v:190120$13185 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:190121.5-190121.29" + switch \initial + attribute \src "libresoc.v:190121.9-190121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:52" + switch \enable attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sram4k_3__ack$next[0:0]$13480 1'0 + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:60" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] $3\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:70" + switch \sram4k_3_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\we[0:0] \sram4k_3_wb__sel [0] + case + assign $3\we[0:0] 1'0 + end + case + assign $2\we[0:0] 1'0 + end case - assign $2\sram4k_3__ack$next[0:0]$13480 $1\sram4k_3__ack$next[0:0]$13479 + assign $1\we[0:0] 1'0 end sync always - update \sram4k_3__ack$next $0\sram4k_3__ack$next[0:0]$13478 + update \we $0\we[0:0] end - connect \$1 $and$libresoc.v:195742$13470_Y - connect \$3 $and$libresoc.v:195743$13471_Y - connect \wb_active \$1 + connect \$1 $and$libresoc.v:190039$13175_Y end -attribute \src "libresoc.v:195818.1-195876.10" +attribute \src "libresoc.v:190144.1-190202.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l - attribute \src "libresoc.v:195819.7-195819.20" + attribute \src "libresoc.v:190145.7-190145.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195864.3-195872.6" - wire width 4 $0\q_int$next[3:0]$13493 - attribute \src "libresoc.v:195862.3-195863.27" + attribute \src "libresoc.v:190190.3-190198.6" + wire width 4 $0\q_int$next[3:0]$13198 + attribute \src "libresoc.v:190188.3-190189.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:195864.3-195872.6" - wire width 4 $1\q_int$next[3:0]$13494 - attribute \src "libresoc.v:195841.13-195841.25" + attribute \src "libresoc.v:190190.3-190198.6" + wire width 4 $1\q_int$next[3:0]$13199 + attribute \src "libresoc.v:190167.13-190167.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:195854.17-195854.96" - wire width 4 $and$libresoc.v:195854$13483_Y - attribute \src "libresoc.v:195859.17-195859.96" - wire width 4 $and$libresoc.v:195859$13488_Y - attribute \src "libresoc.v:195856.18-195856.93" - wire width 4 $not$libresoc.v:195856$13485_Y - attribute \src "libresoc.v:195858.17-195858.92" - wire width 4 $not$libresoc.v:195858$13487_Y - attribute \src "libresoc.v:195861.17-195861.92" - wire width 4 $not$libresoc.v:195861$13490_Y - attribute \src "libresoc.v:195855.18-195855.98" - wire width 4 $or$libresoc.v:195855$13484_Y - attribute \src "libresoc.v:195857.18-195857.99" - wire width 4 $or$libresoc.v:195857$13486_Y - attribute \src "libresoc.v:195860.17-195860.97" - wire width 4 $or$libresoc.v:195860$13489_Y + attribute \src "libresoc.v:190180.17-190180.96" + wire width 4 $and$libresoc.v:190180$13188_Y + attribute \src "libresoc.v:190185.17-190185.96" + wire width 4 $and$libresoc.v:190185$13193_Y + attribute \src "libresoc.v:190182.18-190182.93" + wire width 4 $not$libresoc.v:190182$13190_Y + attribute \src "libresoc.v:190184.17-190184.92" + wire width 4 $not$libresoc.v:190184$13192_Y + attribute \src "libresoc.v:190187.17-190187.92" + wire width 4 $not$libresoc.v:190187$13195_Y + attribute \src "libresoc.v:190181.18-190181.98" + wire width 4 $or$libresoc.v:190181$13189_Y + attribute \src "libresoc.v:190183.18-190183.99" + wire width 4 $or$libresoc.v:190183$13191_Y + attribute \src "libresoc.v:190186.17-190186.97" + wire width 4 $or$libresoc.v:190186$13194_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -406505,11 +397305,11 @@ module \src_l wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:195819.7-195819.15" + attribute \src "libresoc.v:190145.7-190145.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -406526,7 +397326,7 @@ module \src_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:195854$13483 + cell $and $and$libresoc.v:190180$13188 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -406534,10 +397334,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:195854$13483_Y + connect \Y $and$libresoc.v:190180$13188_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:195859$13488 + cell $and $and$libresoc.v:190185$13193 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -406545,34 +397345,34 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:195859$13488_Y + connect \Y $and$libresoc.v:190185$13193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:195856$13485 + cell $not $not$libresoc.v:190182$13190 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:195856$13485_Y + connect \Y $not$libresoc.v:190182$13190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:195858$13487 + cell $not $not$libresoc.v:190184$13192 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:195858$13487_Y + connect \Y $not$libresoc.v:190184$13192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:195861$13490 + cell $not $not$libresoc.v:190187$13195 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:195861$13490_Y + connect \Y $not$libresoc.v:190187$13195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:195855$13484 + cell $or $or$libresoc.v:190181$13189 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -406580,10 +397380,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:195855$13484_Y + connect \Y $or$libresoc.v:190181$13189_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:195857$13486 + cell $or $or$libresoc.v:190183$13191 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -406591,10 +397391,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:195857$13486_Y + connect \Y $or$libresoc.v:190183$13191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:195860$13489 + cell $or $or$libresoc.v:190186$13194 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -406602,39 +397402,39 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:195860$13489_Y + connect \Y $or$libresoc.v:190186$13194_Y end - attribute \src "libresoc.v:195819.7-195819.20" - process $proc$libresoc.v:195819$13495 + attribute \src "libresoc.v:190145.7-190145.20" + process $proc$libresoc.v:190145$13200 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195841.13-195841.25" - process $proc$libresoc.v:195841$13496 + attribute \src "libresoc.v:190167.13-190167.25" + process $proc$libresoc.v:190167$13201 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:195862.3-195863.27" - process $proc$libresoc.v:195862$13491 + attribute \src "libresoc.v:190188.3-190189.27" + process $proc$libresoc.v:190188$13196 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:195864.3-195872.6" - process $proc$libresoc.v:195864$13492 + attribute \src "libresoc.v:190190.3-190198.6" + process $proc$libresoc.v:190190$13197 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13493 $1\q_int$next[3:0]$13494 - attribute \src "libresoc.v:195865.5-195865.29" + assign $0\q_int$next[3:0]$13198 $1\q_int$next[3:0]$13199 + attribute \src "libresoc.v:190191.5-190191.29" switch \initial - attribute \src "libresoc.v:195865.9-195865.17" + attribute \src "libresoc.v:190191.9-190191.17" case 1'1 case end @@ -406643,56 +397443,56 @@ module \src_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13494 4'0000 + assign $1\q_int$next[3:0]$13199 4'0000 case - assign $1\q_int$next[3:0]$13494 \$5 + assign $1\q_int$next[3:0]$13199 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13493 + update \q_int$next $0\q_int$next[3:0]$13198 end - connect \$9 $and$libresoc.v:195854$13483_Y - connect \$11 $or$libresoc.v:195855$13484_Y - connect \$13 $not$libresoc.v:195856$13485_Y - connect \$15 $or$libresoc.v:195857$13486_Y - connect \$1 $not$libresoc.v:195858$13487_Y - connect \$3 $and$libresoc.v:195859$13488_Y - connect \$5 $or$libresoc.v:195860$13489_Y - connect \$7 $not$libresoc.v:195861$13490_Y + connect \$9 $and$libresoc.v:190180$13188_Y + connect \$11 $or$libresoc.v:190181$13189_Y + connect \$13 $not$libresoc.v:190182$13190_Y + connect \$15 $or$libresoc.v:190183$13191_Y + connect \$1 $not$libresoc.v:190184$13192_Y + connect \$3 $and$libresoc.v:190185$13193_Y + connect \$5 $or$libresoc.v:190186$13194_Y + connect \$7 $not$libresoc.v:190187$13195_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:195880.1-195938.10" +attribute \src "libresoc.v:190206.1-190264.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 - attribute \src "libresoc.v:195881.7-195881.20" + attribute \src "libresoc.v:190207.7-190207.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195926.3-195934.6" - wire width 6 $0\q_int$next[5:0]$13507 - attribute \src "libresoc.v:195924.3-195925.27" + attribute \src "libresoc.v:190252.3-190260.6" + wire width 6 $0\q_int$next[5:0]$13212 + attribute \src "libresoc.v:190250.3-190251.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:195926.3-195934.6" - wire width 6 $1\q_int$next[5:0]$13508 - attribute \src "libresoc.v:195903.13-195903.26" + attribute \src "libresoc.v:190252.3-190260.6" + wire width 6 $1\q_int$next[5:0]$13213 + attribute \src "libresoc.v:190229.13-190229.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:195916.17-195916.96" - wire width 6 $and$libresoc.v:195916$13497_Y - attribute \src "libresoc.v:195921.17-195921.96" - wire width 6 $and$libresoc.v:195921$13502_Y - attribute \src "libresoc.v:195918.18-195918.93" - wire width 6 $not$libresoc.v:195918$13499_Y - attribute \src "libresoc.v:195920.17-195920.92" - wire width 6 $not$libresoc.v:195920$13501_Y - attribute \src "libresoc.v:195923.17-195923.92" - wire width 6 $not$libresoc.v:195923$13504_Y - attribute \src "libresoc.v:195917.18-195917.98" - wire width 6 $or$libresoc.v:195917$13498_Y - attribute \src "libresoc.v:195919.18-195919.99" - wire width 6 $or$libresoc.v:195919$13500_Y - attribute \src "libresoc.v:195922.17-195922.97" - wire width 6 $or$libresoc.v:195922$13503_Y + attribute \src "libresoc.v:190242.17-190242.96" + wire width 6 $and$libresoc.v:190242$13202_Y + attribute \src "libresoc.v:190247.17-190247.96" + wire width 6 $and$libresoc.v:190247$13207_Y + attribute \src "libresoc.v:190244.18-190244.93" + wire width 6 $not$libresoc.v:190244$13204_Y + attribute \src "libresoc.v:190246.17-190246.92" + wire width 6 $not$libresoc.v:190246$13206_Y + attribute \src "libresoc.v:190249.17-190249.92" + wire width 6 $not$libresoc.v:190249$13209_Y + attribute \src "libresoc.v:190243.18-190243.98" + wire width 6 $or$libresoc.v:190243$13203_Y + attribute \src "libresoc.v:190245.18-190245.99" + wire width 6 $or$libresoc.v:190245$13205_Y + attribute \src "libresoc.v:190248.17-190248.97" + wire width 6 $or$libresoc.v:190248$13208_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -406709,11 +397509,11 @@ module \src_l$10 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:195881.7-195881.15" + attribute \src "libresoc.v:190207.7-190207.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -406730,7 +397530,7 @@ module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:195916$13497 + cell $and $and$libresoc.v:190242$13202 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -406738,10 +397538,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:195916$13497_Y + connect \Y $and$libresoc.v:190242$13202_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:195921$13502 + cell $and $and$libresoc.v:190247$13207 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -406749,34 +397549,34 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:195921$13502_Y + connect \Y $and$libresoc.v:190247$13207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:195918$13499 + cell $not $not$libresoc.v:190244$13204 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:195918$13499_Y + connect \Y $not$libresoc.v:190244$13204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:195920$13501 + cell $not $not$libresoc.v:190246$13206 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:195920$13501_Y + connect \Y $not$libresoc.v:190246$13206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:195923$13504 + cell $not $not$libresoc.v:190249$13209 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:195923$13504_Y + connect \Y $not$libresoc.v:190249$13209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:195917$13498 + cell $or $or$libresoc.v:190243$13203 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -406784,10 +397584,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:195917$13498_Y + connect \Y $or$libresoc.v:190243$13203_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:195919$13500 + cell $or $or$libresoc.v:190245$13205 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -406795,10 +397595,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:195919$13500_Y + connect \Y $or$libresoc.v:190245$13205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:195922$13503 + cell $or $or$libresoc.v:190248$13208 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -406806,39 +397606,39 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:195922$13503_Y + connect \Y $or$libresoc.v:190248$13208_Y end - attribute \src "libresoc.v:195881.7-195881.20" - process $proc$libresoc.v:195881$13509 + attribute \src "libresoc.v:190207.7-190207.20" + process $proc$libresoc.v:190207$13214 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195903.13-195903.26" - process $proc$libresoc.v:195903$13510 + attribute \src "libresoc.v:190229.13-190229.26" + process $proc$libresoc.v:190229$13215 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:195924.3-195925.27" - process $proc$libresoc.v:195924$13505 + attribute \src "libresoc.v:190250.3-190251.27" + process $proc$libresoc.v:190250$13210 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:195926.3-195934.6" - process $proc$libresoc.v:195926$13506 + attribute \src "libresoc.v:190252.3-190260.6" + process $proc$libresoc.v:190252$13211 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13507 $1\q_int$next[5:0]$13508 - attribute \src "libresoc.v:195927.5-195927.29" + assign $0\q_int$next[5:0]$13212 $1\q_int$next[5:0]$13213 + attribute \src "libresoc.v:190253.5-190253.29" switch \initial - attribute \src "libresoc.v:195927.9-195927.17" + attribute \src "libresoc.v:190253.9-190253.17" case 1'1 case end @@ -406847,56 +397647,56 @@ module \src_l$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13508 6'000000 + assign $1\q_int$next[5:0]$13213 6'000000 case - assign $1\q_int$next[5:0]$13508 \$5 + assign $1\q_int$next[5:0]$13213 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13507 + update \q_int$next $0\q_int$next[5:0]$13212 end - connect \$9 $and$libresoc.v:195916$13497_Y - connect \$11 $or$libresoc.v:195917$13498_Y - connect \$13 $not$libresoc.v:195918$13499_Y - connect \$15 $or$libresoc.v:195919$13500_Y - connect \$1 $not$libresoc.v:195920$13501_Y - connect \$3 $and$libresoc.v:195921$13502_Y - connect \$5 $or$libresoc.v:195922$13503_Y - connect \$7 $not$libresoc.v:195923$13504_Y + connect \$9 $and$libresoc.v:190242$13202_Y + connect \$11 $or$libresoc.v:190243$13203_Y + connect \$13 $not$libresoc.v:190244$13204_Y + connect \$15 $or$libresoc.v:190245$13205_Y + connect \$1 $not$libresoc.v:190246$13206_Y + connect \$3 $and$libresoc.v:190247$13207_Y + connect \$5 $or$libresoc.v:190248$13208_Y + connect \$7 $not$libresoc.v:190249$13209_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:195942.1-196000.10" +attribute \src "libresoc.v:190268.1-190326.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" module \src_l$101 - attribute \src "libresoc.v:195943.7-195943.20" + attribute \src "libresoc.v:190269.7-190269.20" wire $0\initial[0:0] - attribute \src "libresoc.v:195988.3-195996.6" - wire width 3 $0\q_int$next[2:0]$13521 - attribute \src "libresoc.v:195986.3-195987.27" + attribute \src "libresoc.v:190314.3-190322.6" + wire width 3 $0\q_int$next[2:0]$13226 + attribute \src "libresoc.v:190312.3-190313.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:195988.3-195996.6" - wire width 3 $1\q_int$next[2:0]$13522 - attribute \src "libresoc.v:195965.13-195965.25" + attribute \src "libresoc.v:190314.3-190322.6" + wire width 3 $1\q_int$next[2:0]$13227 + attribute \src "libresoc.v:190291.13-190291.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:195978.17-195978.96" - wire width 3 $and$libresoc.v:195978$13511_Y - attribute \src "libresoc.v:195983.17-195983.96" - wire width 3 $and$libresoc.v:195983$13516_Y - attribute \src "libresoc.v:195980.18-195980.93" - wire width 3 $not$libresoc.v:195980$13513_Y - attribute \src "libresoc.v:195982.17-195982.92" - wire width 3 $not$libresoc.v:195982$13515_Y - attribute \src "libresoc.v:195985.17-195985.92" - wire width 3 $not$libresoc.v:195985$13518_Y - attribute \src "libresoc.v:195979.18-195979.98" - wire width 3 $or$libresoc.v:195979$13512_Y - attribute \src "libresoc.v:195981.18-195981.99" - wire width 3 $or$libresoc.v:195981$13514_Y - attribute \src "libresoc.v:195984.17-195984.97" - wire width 3 $or$libresoc.v:195984$13517_Y + attribute \src "libresoc.v:190304.17-190304.96" + wire width 3 $and$libresoc.v:190304$13216_Y + attribute \src "libresoc.v:190309.17-190309.96" + wire width 3 $and$libresoc.v:190309$13221_Y + attribute \src "libresoc.v:190306.18-190306.93" + wire width 3 $not$libresoc.v:190306$13218_Y + attribute \src "libresoc.v:190308.17-190308.92" + wire width 3 $not$libresoc.v:190308$13220_Y + attribute \src "libresoc.v:190311.17-190311.92" + wire width 3 $not$libresoc.v:190311$13223_Y + attribute \src "libresoc.v:190305.18-190305.98" + wire width 3 $or$libresoc.v:190305$13217_Y + attribute \src "libresoc.v:190307.18-190307.99" + wire width 3 $or$libresoc.v:190307$13219_Y + attribute \src "libresoc.v:190310.17-190310.97" + wire width 3 $or$libresoc.v:190310$13222_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -406913,11 +397713,11 @@ module \src_l$101 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:195943.7-195943.15" + attribute \src "libresoc.v:190269.7-190269.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -406934,7 +397734,7 @@ module \src_l$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:195978$13511 + cell $and $and$libresoc.v:190304$13216 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -406942,10 +397742,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:195978$13511_Y + connect \Y $and$libresoc.v:190304$13216_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:195983$13516 + cell $and $and$libresoc.v:190309$13221 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -406953,34 +397753,34 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:195983$13516_Y + connect \Y $and$libresoc.v:190309$13221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:195980$13513 + cell $not $not$libresoc.v:190306$13218 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:195980$13513_Y + connect \Y $not$libresoc.v:190306$13218_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:195982$13515 + cell $not $not$libresoc.v:190308$13220 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:195982$13515_Y + connect \Y $not$libresoc.v:190308$13220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:195985$13518 + cell $not $not$libresoc.v:190311$13223 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:195985$13518_Y + connect \Y $not$libresoc.v:190311$13223_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:195979$13512 + cell $or $or$libresoc.v:190305$13217 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -406988,10 +397788,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:195979$13512_Y + connect \Y $or$libresoc.v:190305$13217_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:195981$13514 + cell $or $or$libresoc.v:190307$13219 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -406999,10 +397799,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:195981$13514_Y + connect \Y $or$libresoc.v:190307$13219_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:195984$13517 + cell $or $or$libresoc.v:190310$13222 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407010,39 +397810,39 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:195984$13517_Y + connect \Y $or$libresoc.v:190310$13222_Y end - attribute \src "libresoc.v:195943.7-195943.20" - process $proc$libresoc.v:195943$13523 + attribute \src "libresoc.v:190269.7-190269.20" + process $proc$libresoc.v:190269$13228 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:195965.13-195965.25" - process $proc$libresoc.v:195965$13524 + attribute \src "libresoc.v:190291.13-190291.25" + process $proc$libresoc.v:190291$13229 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:195986.3-195987.27" - process $proc$libresoc.v:195986$13519 + attribute \src "libresoc.v:190312.3-190313.27" + process $proc$libresoc.v:190312$13224 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:195988.3-195996.6" - process $proc$libresoc.v:195988$13520 + attribute \src "libresoc.v:190314.3-190322.6" + process $proc$libresoc.v:190314$13225 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13521 $1\q_int$next[2:0]$13522 - attribute \src "libresoc.v:195989.5-195989.29" + assign $0\q_int$next[2:0]$13226 $1\q_int$next[2:0]$13227 + attribute \src "libresoc.v:190315.5-190315.29" switch \initial - attribute \src "libresoc.v:195989.9-195989.17" + attribute \src "libresoc.v:190315.9-190315.17" case 1'1 case end @@ -407051,56 +397851,56 @@ module \src_l$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13522 3'000 + assign $1\q_int$next[2:0]$13227 3'000 case - assign $1\q_int$next[2:0]$13522 \$5 + assign $1\q_int$next[2:0]$13227 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13521 + update \q_int$next $0\q_int$next[2:0]$13226 end - connect \$9 $and$libresoc.v:195978$13511_Y - connect \$11 $or$libresoc.v:195979$13512_Y - connect \$13 $not$libresoc.v:195980$13513_Y - connect \$15 $or$libresoc.v:195981$13514_Y - connect \$1 $not$libresoc.v:195982$13515_Y - connect \$3 $and$libresoc.v:195983$13516_Y - connect \$5 $or$libresoc.v:195984$13517_Y - connect \$7 $not$libresoc.v:195985$13518_Y + connect \$9 $and$libresoc.v:190304$13216_Y + connect \$11 $or$libresoc.v:190305$13217_Y + connect \$13 $not$libresoc.v:190306$13218_Y + connect \$15 $or$libresoc.v:190307$13219_Y + connect \$1 $not$libresoc.v:190308$13220_Y + connect \$3 $and$libresoc.v:190309$13221_Y + connect \$5 $or$libresoc.v:190310$13222_Y + connect \$7 $not$libresoc.v:190311$13223_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:196004.1-196062.10" +attribute \src "libresoc.v:190330.1-190388.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" attribute \generator "nMigen" module \src_l$119 - attribute \src "libresoc.v:196005.7-196005.20" + attribute \src "libresoc.v:190331.7-190331.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196050.3-196058.6" - wire width 5 $0\q_int$next[4:0]$13535 - attribute \src "libresoc.v:196048.3-196049.27" + attribute \src "libresoc.v:190376.3-190384.6" + wire width 5 $0\q_int$next[4:0]$13240 + attribute \src "libresoc.v:190374.3-190375.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:196050.3-196058.6" - wire width 5 $1\q_int$next[4:0]$13536 - attribute \src "libresoc.v:196027.13-196027.26" + attribute \src "libresoc.v:190376.3-190384.6" + wire width 5 $1\q_int$next[4:0]$13241 + attribute \src "libresoc.v:190353.13-190353.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:196040.17-196040.96" - wire width 5 $and$libresoc.v:196040$13525_Y - attribute \src "libresoc.v:196045.17-196045.96" - wire width 5 $and$libresoc.v:196045$13530_Y - attribute \src "libresoc.v:196042.18-196042.93" - wire width 5 $not$libresoc.v:196042$13527_Y - attribute \src "libresoc.v:196044.17-196044.92" - wire width 5 $not$libresoc.v:196044$13529_Y - attribute \src "libresoc.v:196047.17-196047.92" - wire width 5 $not$libresoc.v:196047$13532_Y - attribute \src "libresoc.v:196041.18-196041.98" - wire width 5 $or$libresoc.v:196041$13526_Y - attribute \src "libresoc.v:196043.18-196043.99" - wire width 5 $or$libresoc.v:196043$13528_Y - attribute \src "libresoc.v:196046.17-196046.97" - wire width 5 $or$libresoc.v:196046$13531_Y + attribute \src "libresoc.v:190366.17-190366.96" + wire width 5 $and$libresoc.v:190366$13230_Y + attribute \src "libresoc.v:190371.17-190371.96" + wire width 5 $and$libresoc.v:190371$13235_Y + attribute \src "libresoc.v:190368.18-190368.93" + wire width 5 $not$libresoc.v:190368$13232_Y + attribute \src "libresoc.v:190370.17-190370.92" + wire width 5 $not$libresoc.v:190370$13234_Y + attribute \src "libresoc.v:190373.17-190373.92" + wire width 5 $not$libresoc.v:190373$13237_Y + attribute \src "libresoc.v:190367.18-190367.98" + wire width 5 $or$libresoc.v:190367$13231_Y + attribute \src "libresoc.v:190369.18-190369.99" + wire width 5 $or$libresoc.v:190369$13233_Y + attribute \src "libresoc.v:190372.17-190372.97" + wire width 5 $or$libresoc.v:190372$13236_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -407117,11 +397917,11 @@ module \src_l$119 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:196005.7-196005.15" + attribute \src "libresoc.v:190331.7-190331.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -407138,7 +397938,7 @@ module \src_l$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:196040$13525 + cell $and $and$libresoc.v:190366$13230 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -407146,10 +397946,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:196040$13525_Y + connect \Y $and$libresoc.v:190366$13230_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:196045$13530 + cell $and $and$libresoc.v:190371$13235 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -407157,34 +397957,34 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:196045$13530_Y + connect \Y $and$libresoc.v:190371$13235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:196042$13527 + cell $not $not$libresoc.v:190368$13232 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src - connect \Y $not$libresoc.v:196042$13527_Y + connect \Y $not$libresoc.v:190368$13232_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:196044$13529 + cell $not $not$libresoc.v:190370$13234 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:196044$13529_Y + connect \Y $not$libresoc.v:190370$13234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:196047$13532 + cell $not $not$libresoc.v:190373$13237 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:196047$13532_Y + connect \Y $not$libresoc.v:190373$13237_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:196041$13526 + cell $or $or$libresoc.v:190367$13231 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -407192,10 +397992,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:196041$13526_Y + connect \Y $or$libresoc.v:190367$13231_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:196043$13528 + cell $or $or$libresoc.v:190369$13233 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -407203,10 +398003,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:196043$13528_Y + connect \Y $or$libresoc.v:190369$13233_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:196046$13531 + cell $or $or$libresoc.v:190372$13236 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -407214,39 +398014,39 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:196046$13531_Y + connect \Y $or$libresoc.v:190372$13236_Y end - attribute \src "libresoc.v:196005.7-196005.20" - process $proc$libresoc.v:196005$13537 + attribute \src "libresoc.v:190331.7-190331.20" + process $proc$libresoc.v:190331$13242 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196027.13-196027.26" - process $proc$libresoc.v:196027$13538 + attribute \src "libresoc.v:190353.13-190353.26" + process $proc$libresoc.v:190353$13243 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:196048.3-196049.27" - process $proc$libresoc.v:196048$13533 + attribute \src "libresoc.v:190374.3-190375.27" + process $proc$libresoc.v:190374$13238 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:196050.3-196058.6" - process $proc$libresoc.v:196050$13534 + attribute \src "libresoc.v:190376.3-190384.6" + process $proc$libresoc.v:190376$13239 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$13535 $1\q_int$next[4:0]$13536 - attribute \src "libresoc.v:196051.5-196051.29" + assign $0\q_int$next[4:0]$13240 $1\q_int$next[4:0]$13241 + attribute \src "libresoc.v:190377.5-190377.29" switch \initial - attribute \src "libresoc.v:196051.9-196051.17" + attribute \src "libresoc.v:190377.9-190377.17" case 1'1 case end @@ -407255,56 +398055,56 @@ module \src_l$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$13536 5'00000 + assign $1\q_int$next[4:0]$13241 5'00000 case - assign $1\q_int$next[4:0]$13536 \$5 + assign $1\q_int$next[4:0]$13241 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$13535 + update \q_int$next $0\q_int$next[4:0]$13240 end - connect \$9 $and$libresoc.v:196040$13525_Y - connect \$11 $or$libresoc.v:196041$13526_Y - connect \$13 $not$libresoc.v:196042$13527_Y - connect \$15 $or$libresoc.v:196043$13528_Y - connect \$1 $not$libresoc.v:196044$13529_Y - connect \$3 $and$libresoc.v:196045$13530_Y - connect \$5 $or$libresoc.v:196046$13531_Y - connect \$7 $not$libresoc.v:196047$13532_Y + connect \$9 $and$libresoc.v:190366$13230_Y + connect \$11 $or$libresoc.v:190367$13231_Y + connect \$13 $not$libresoc.v:190368$13232_Y + connect \$15 $or$libresoc.v:190369$13233_Y + connect \$1 $not$libresoc.v:190370$13234_Y + connect \$3 $and$libresoc.v:190371$13235_Y + connect \$5 $or$libresoc.v:190372$13236_Y + connect \$7 $not$libresoc.v:190373$13237_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:196066.1-196124.10" +attribute \src "libresoc.v:190392.1-190450.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" module \src_l$127 - attribute \src "libresoc.v:196067.7-196067.20" + attribute \src "libresoc.v:190393.7-190393.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196112.3-196120.6" - wire width 3 $0\q_int$next[2:0]$13549 - attribute \src "libresoc.v:196110.3-196111.27" + attribute \src "libresoc.v:190438.3-190446.6" + wire width 3 $0\q_int$next[2:0]$13254 + attribute \src "libresoc.v:190436.3-190437.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:196112.3-196120.6" - wire width 3 $1\q_int$next[2:0]$13550 - attribute \src "libresoc.v:196089.13-196089.25" + attribute \src "libresoc.v:190438.3-190446.6" + wire width 3 $1\q_int$next[2:0]$13255 + attribute \src "libresoc.v:190415.13-190415.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:196102.17-196102.96" - wire width 3 $and$libresoc.v:196102$13539_Y - attribute \src "libresoc.v:196107.17-196107.96" - wire width 3 $and$libresoc.v:196107$13544_Y - attribute \src "libresoc.v:196104.18-196104.93" - wire width 3 $not$libresoc.v:196104$13541_Y - attribute \src "libresoc.v:196106.17-196106.92" - wire width 3 $not$libresoc.v:196106$13543_Y - attribute \src "libresoc.v:196109.17-196109.92" - wire width 3 $not$libresoc.v:196109$13546_Y - attribute \src "libresoc.v:196103.18-196103.98" - wire width 3 $or$libresoc.v:196103$13540_Y - attribute \src "libresoc.v:196105.18-196105.99" - wire width 3 $or$libresoc.v:196105$13542_Y - attribute \src "libresoc.v:196108.17-196108.97" - wire width 3 $or$libresoc.v:196108$13545_Y + attribute \src "libresoc.v:190428.17-190428.96" + wire width 3 $and$libresoc.v:190428$13244_Y + attribute \src "libresoc.v:190433.17-190433.96" + wire width 3 $and$libresoc.v:190433$13249_Y + attribute \src "libresoc.v:190430.18-190430.93" + wire width 3 $not$libresoc.v:190430$13246_Y + attribute \src "libresoc.v:190432.17-190432.92" + wire width 3 $not$libresoc.v:190432$13248_Y + attribute \src "libresoc.v:190435.17-190435.92" + wire width 3 $not$libresoc.v:190435$13251_Y + attribute \src "libresoc.v:190429.18-190429.98" + wire width 3 $or$libresoc.v:190429$13245_Y + attribute \src "libresoc.v:190431.18-190431.99" + wire width 3 $or$libresoc.v:190431$13247_Y + attribute \src "libresoc.v:190434.17-190434.97" + wire width 3 $or$libresoc.v:190434$13250_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -407321,11 +398121,11 @@ module \src_l$127 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:196067.7-196067.15" + attribute \src "libresoc.v:190393.7-190393.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -407342,7 +398142,7 @@ module \src_l$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:196102$13539 + cell $and $and$libresoc.v:190428$13244 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407350,10 +398150,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:196102$13539_Y + connect \Y $and$libresoc.v:190428$13244_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:196107$13544 + cell $and $and$libresoc.v:190433$13249 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407361,34 +398161,34 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:196107$13544_Y + connect \Y $and$libresoc.v:190433$13249_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:196104$13541 + cell $not $not$libresoc.v:190430$13246 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:196104$13541_Y + connect \Y $not$libresoc.v:190430$13246_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:196106$13543 + cell $not $not$libresoc.v:190432$13248 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:196106$13543_Y + connect \Y $not$libresoc.v:190432$13248_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:196109$13546 + cell $not $not$libresoc.v:190435$13251 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:196109$13546_Y + connect \Y $not$libresoc.v:190435$13251_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:196103$13540 + cell $or $or$libresoc.v:190429$13245 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407396,10 +398196,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:196103$13540_Y + connect \Y $or$libresoc.v:190429$13245_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:196105$13542 + cell $or $or$libresoc.v:190431$13247 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407407,10 +398207,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:196105$13542_Y + connect \Y $or$libresoc.v:190431$13247_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:196108$13545 + cell $or $or$libresoc.v:190434$13250 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407418,39 +398218,39 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:196108$13545_Y + connect \Y $or$libresoc.v:190434$13250_Y end - attribute \src "libresoc.v:196067.7-196067.20" - process $proc$libresoc.v:196067$13551 + attribute \src "libresoc.v:190393.7-190393.20" + process $proc$libresoc.v:190393$13256 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196089.13-196089.25" - process $proc$libresoc.v:196089$13552 + attribute \src "libresoc.v:190415.13-190415.25" + process $proc$libresoc.v:190415$13257 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:196110.3-196111.27" - process $proc$libresoc.v:196110$13547 + attribute \src "libresoc.v:190436.3-190437.27" + process $proc$libresoc.v:190436$13252 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:196112.3-196120.6" - process $proc$libresoc.v:196112$13548 + attribute \src "libresoc.v:190438.3-190446.6" + process $proc$libresoc.v:190438$13253 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13549 $1\q_int$next[2:0]$13550 - attribute \src "libresoc.v:196113.5-196113.29" + assign $0\q_int$next[2:0]$13254 $1\q_int$next[2:0]$13255 + attribute \src "libresoc.v:190439.5-190439.29" switch \initial - attribute \src "libresoc.v:196113.9-196113.17" + attribute \src "libresoc.v:190439.9-190439.17" case 1'1 case end @@ -407459,56 +398259,56 @@ module \src_l$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13550 3'000 + assign $1\q_int$next[2:0]$13255 3'000 case - assign $1\q_int$next[2:0]$13550 \$5 + assign $1\q_int$next[2:0]$13255 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13549 + update \q_int$next $0\q_int$next[2:0]$13254 end - connect \$9 $and$libresoc.v:196102$13539_Y - connect \$11 $or$libresoc.v:196103$13540_Y - connect \$13 $not$libresoc.v:196104$13541_Y - connect \$15 $or$libresoc.v:196105$13542_Y - connect \$1 $not$libresoc.v:196106$13543_Y - connect \$3 $and$libresoc.v:196107$13544_Y - connect \$5 $or$libresoc.v:196108$13545_Y - connect \$7 $not$libresoc.v:196109$13546_Y + connect \$9 $and$libresoc.v:190428$13244_Y + connect \$11 $or$libresoc.v:190429$13245_Y + connect \$13 $not$libresoc.v:190430$13246_Y + connect \$15 $or$libresoc.v:190431$13247_Y + connect \$1 $not$libresoc.v:190432$13248_Y + connect \$3 $and$libresoc.v:190433$13249_Y + connect \$5 $or$libresoc.v:190434$13250_Y + connect \$7 $not$libresoc.v:190435$13251_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:196128.1-196186.10" +attribute \src "libresoc.v:190454.1-190512.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 - attribute \src "libresoc.v:196129.7-196129.20" + attribute \src "libresoc.v:190455.7-190455.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196174.3-196182.6" - wire width 3 $0\q_int$next[2:0]$13563 - attribute \src "libresoc.v:196172.3-196173.27" + attribute \src "libresoc.v:190500.3-190508.6" + wire width 3 $0\q_int$next[2:0]$13268 + attribute \src "libresoc.v:190498.3-190499.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:196174.3-196182.6" - wire width 3 $1\q_int$next[2:0]$13564 - attribute \src "libresoc.v:196151.13-196151.25" + attribute \src "libresoc.v:190500.3-190508.6" + wire width 3 $1\q_int$next[2:0]$13269 + attribute \src "libresoc.v:190477.13-190477.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:196164.17-196164.96" - wire width 3 $and$libresoc.v:196164$13553_Y - attribute \src "libresoc.v:196169.17-196169.96" - wire width 3 $and$libresoc.v:196169$13558_Y - attribute \src "libresoc.v:196166.18-196166.93" - wire width 3 $not$libresoc.v:196166$13555_Y - attribute \src "libresoc.v:196168.17-196168.92" - wire width 3 $not$libresoc.v:196168$13557_Y - attribute \src "libresoc.v:196171.17-196171.92" - wire width 3 $not$libresoc.v:196171$13560_Y - attribute \src "libresoc.v:196165.18-196165.98" - wire width 3 $or$libresoc.v:196165$13554_Y - attribute \src "libresoc.v:196167.18-196167.99" - wire width 3 $or$libresoc.v:196167$13556_Y - attribute \src "libresoc.v:196170.17-196170.97" - wire width 3 $or$libresoc.v:196170$13559_Y + attribute \src "libresoc.v:190490.17-190490.96" + wire width 3 $and$libresoc.v:190490$13258_Y + attribute \src "libresoc.v:190495.17-190495.96" + wire width 3 $and$libresoc.v:190495$13263_Y + attribute \src "libresoc.v:190492.18-190492.93" + wire width 3 $not$libresoc.v:190492$13260_Y + attribute \src "libresoc.v:190494.17-190494.92" + wire width 3 $not$libresoc.v:190494$13262_Y + attribute \src "libresoc.v:190497.17-190497.92" + wire width 3 $not$libresoc.v:190497$13265_Y + attribute \src "libresoc.v:190491.18-190491.98" + wire width 3 $or$libresoc.v:190491$13259_Y + attribute \src "libresoc.v:190493.18-190493.99" + wire width 3 $or$libresoc.v:190493$13261_Y + attribute \src "libresoc.v:190496.17-190496.97" + wire width 3 $or$libresoc.v:190496$13264_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -407525,11 +398325,11 @@ module \src_l$23 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:196129.7-196129.15" + attribute \src "libresoc.v:190455.7-190455.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -407546,7 +398346,7 @@ module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:196164$13553 + cell $and $and$libresoc.v:190490$13258 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407554,10 +398354,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:196164$13553_Y + connect \Y $and$libresoc.v:190490$13258_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:196169$13558 + cell $and $and$libresoc.v:190495$13263 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407565,34 +398365,34 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:196169$13558_Y + connect \Y $and$libresoc.v:190495$13263_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:196166$13555 + cell $not $not$libresoc.v:190492$13260 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:196166$13555_Y + connect \Y $not$libresoc.v:190492$13260_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:196168$13557 + cell $not $not$libresoc.v:190494$13262 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:196168$13557_Y + connect \Y $not$libresoc.v:190494$13262_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:196171$13560 + cell $not $not$libresoc.v:190497$13265 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:196171$13560_Y + connect \Y $not$libresoc.v:190497$13265_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:196165$13554 + cell $or $or$libresoc.v:190491$13259 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407600,10 +398400,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:196165$13554_Y + connect \Y $or$libresoc.v:190491$13259_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:196167$13556 + cell $or $or$libresoc.v:190493$13261 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407611,10 +398411,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:196167$13556_Y + connect \Y $or$libresoc.v:190493$13261_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:196170$13559 + cell $or $or$libresoc.v:190496$13264 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407622,39 +398422,39 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:196170$13559_Y + connect \Y $or$libresoc.v:190496$13264_Y end - attribute \src "libresoc.v:196129.7-196129.20" - process $proc$libresoc.v:196129$13565 + attribute \src "libresoc.v:190455.7-190455.20" + process $proc$libresoc.v:190455$13270 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196151.13-196151.25" - process $proc$libresoc.v:196151$13566 + attribute \src "libresoc.v:190477.13-190477.25" + process $proc$libresoc.v:190477$13271 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:196172.3-196173.27" - process $proc$libresoc.v:196172$13561 + attribute \src "libresoc.v:190498.3-190499.27" + process $proc$libresoc.v:190498$13266 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:196174.3-196182.6" - process $proc$libresoc.v:196174$13562 + attribute \src "libresoc.v:190500.3-190508.6" + process $proc$libresoc.v:190500$13267 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13563 $1\q_int$next[2:0]$13564 - attribute \src "libresoc.v:196175.5-196175.29" + assign $0\q_int$next[2:0]$13268 $1\q_int$next[2:0]$13269 + attribute \src "libresoc.v:190501.5-190501.29" switch \initial - attribute \src "libresoc.v:196175.9-196175.17" + attribute \src "libresoc.v:190501.9-190501.17" case 1'1 case end @@ -407663,56 +398463,56 @@ module \src_l$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13564 3'000 + assign $1\q_int$next[2:0]$13269 3'000 case - assign $1\q_int$next[2:0]$13564 \$5 + assign $1\q_int$next[2:0]$13269 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13563 + update \q_int$next $0\q_int$next[2:0]$13268 end - connect \$9 $and$libresoc.v:196164$13553_Y - connect \$11 $or$libresoc.v:196165$13554_Y - connect \$13 $not$libresoc.v:196166$13555_Y - connect \$15 $or$libresoc.v:196167$13556_Y - connect \$1 $not$libresoc.v:196168$13557_Y - connect \$3 $and$libresoc.v:196169$13558_Y - connect \$5 $or$libresoc.v:196170$13559_Y - connect \$7 $not$libresoc.v:196171$13560_Y + connect \$9 $and$libresoc.v:190490$13258_Y + connect \$11 $or$libresoc.v:190491$13259_Y + connect \$13 $not$libresoc.v:190492$13260_Y + connect \$15 $or$libresoc.v:190493$13261_Y + connect \$1 $not$libresoc.v:190494$13262_Y + connect \$3 $and$libresoc.v:190495$13263_Y + connect \$5 $or$libresoc.v:190496$13264_Y + connect \$7 $not$libresoc.v:190497$13265_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:196190.1-196248.10" +attribute \src "libresoc.v:190516.1-190574.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" module \src_l$39 - attribute \src "libresoc.v:196191.7-196191.20" + attribute \src "libresoc.v:190517.7-190517.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196236.3-196244.6" - wire width 4 $0\q_int$next[3:0]$13577 - attribute \src "libresoc.v:196234.3-196235.27" + attribute \src "libresoc.v:190562.3-190570.6" + wire width 4 $0\q_int$next[3:0]$13282 + attribute \src "libresoc.v:190560.3-190561.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:196236.3-196244.6" - wire width 4 $1\q_int$next[3:0]$13578 - attribute \src "libresoc.v:196213.13-196213.25" + attribute \src "libresoc.v:190562.3-190570.6" + wire width 4 $1\q_int$next[3:0]$13283 + attribute \src "libresoc.v:190539.13-190539.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:196226.17-196226.96" - wire width 4 $and$libresoc.v:196226$13567_Y - attribute \src "libresoc.v:196231.17-196231.96" - wire width 4 $and$libresoc.v:196231$13572_Y - attribute \src "libresoc.v:196228.18-196228.93" - wire width 4 $not$libresoc.v:196228$13569_Y - attribute \src "libresoc.v:196230.17-196230.92" - wire width 4 $not$libresoc.v:196230$13571_Y - attribute \src "libresoc.v:196233.17-196233.92" - wire width 4 $not$libresoc.v:196233$13574_Y - attribute \src "libresoc.v:196227.18-196227.98" - wire width 4 $or$libresoc.v:196227$13568_Y - attribute \src "libresoc.v:196229.18-196229.99" - wire width 4 $or$libresoc.v:196229$13570_Y - attribute \src "libresoc.v:196232.17-196232.97" - wire width 4 $or$libresoc.v:196232$13573_Y + attribute \src "libresoc.v:190552.17-190552.96" + wire width 4 $and$libresoc.v:190552$13272_Y + attribute \src "libresoc.v:190557.17-190557.96" + wire width 4 $and$libresoc.v:190557$13277_Y + attribute \src "libresoc.v:190554.18-190554.93" + wire width 4 $not$libresoc.v:190554$13274_Y + attribute \src "libresoc.v:190556.17-190556.92" + wire width 4 $not$libresoc.v:190556$13276_Y + attribute \src "libresoc.v:190559.17-190559.92" + wire width 4 $not$libresoc.v:190559$13279_Y + attribute \src "libresoc.v:190553.18-190553.98" + wire width 4 $or$libresoc.v:190553$13273_Y + attribute \src "libresoc.v:190555.18-190555.99" + wire width 4 $or$libresoc.v:190555$13275_Y + attribute \src "libresoc.v:190558.17-190558.97" + wire width 4 $or$libresoc.v:190558$13278_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -407729,11 +398529,11 @@ module \src_l$39 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:196191.7-196191.15" + attribute \src "libresoc.v:190517.7-190517.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -407750,7 +398550,7 @@ module \src_l$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:196226$13567 + cell $and $and$libresoc.v:190552$13272 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -407758,10 +398558,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:196226$13567_Y + connect \Y $and$libresoc.v:190552$13272_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:196231$13572 + cell $and $and$libresoc.v:190557$13277 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -407769,34 +398569,34 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:196231$13572_Y + connect \Y $and$libresoc.v:190557$13277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:196228$13569 + cell $not $not$libresoc.v:190554$13274 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:196228$13569_Y + connect \Y $not$libresoc.v:190554$13274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:196230$13571 + cell $not $not$libresoc.v:190556$13276 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:196230$13571_Y + connect \Y $not$libresoc.v:190556$13276_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:196233$13574 + cell $not $not$libresoc.v:190559$13279 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:196233$13574_Y + connect \Y $not$libresoc.v:190559$13279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:196227$13568 + cell $or $or$libresoc.v:190553$13273 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -407804,10 +398604,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:196227$13568_Y + connect \Y $or$libresoc.v:190553$13273_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:196229$13570 + cell $or $or$libresoc.v:190555$13275 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -407815,10 +398615,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:196229$13570_Y + connect \Y $or$libresoc.v:190555$13275_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:196232$13573 + cell $or $or$libresoc.v:190558$13278 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -407826,39 +398626,39 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:196232$13573_Y + connect \Y $or$libresoc.v:190558$13278_Y end - attribute \src "libresoc.v:196191.7-196191.20" - process $proc$libresoc.v:196191$13579 + attribute \src "libresoc.v:190517.7-190517.20" + process $proc$libresoc.v:190517$13284 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196213.13-196213.25" - process $proc$libresoc.v:196213$13580 + attribute \src "libresoc.v:190539.13-190539.25" + process $proc$libresoc.v:190539$13285 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:196234.3-196235.27" - process $proc$libresoc.v:196234$13575 + attribute \src "libresoc.v:190560.3-190561.27" + process $proc$libresoc.v:190560$13280 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:196236.3-196244.6" - process $proc$libresoc.v:196236$13576 + attribute \src "libresoc.v:190562.3-190570.6" + process $proc$libresoc.v:190562$13281 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13577 $1\q_int$next[3:0]$13578 - attribute \src "libresoc.v:196237.5-196237.29" + assign $0\q_int$next[3:0]$13282 $1\q_int$next[3:0]$13283 + attribute \src "libresoc.v:190563.5-190563.29" switch \initial - attribute \src "libresoc.v:196237.9-196237.17" + attribute \src "libresoc.v:190563.9-190563.17" case 1'1 case end @@ -407867,56 +398667,56 @@ module \src_l$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13578 4'0000 + assign $1\q_int$next[3:0]$13283 4'0000 case - assign $1\q_int$next[3:0]$13578 \$5 + assign $1\q_int$next[3:0]$13283 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13577 + update \q_int$next $0\q_int$next[3:0]$13282 end - connect \$9 $and$libresoc.v:196226$13567_Y - connect \$11 $or$libresoc.v:196227$13568_Y - connect \$13 $not$libresoc.v:196228$13569_Y - connect \$15 $or$libresoc.v:196229$13570_Y - connect \$1 $not$libresoc.v:196230$13571_Y - connect \$3 $and$libresoc.v:196231$13572_Y - connect \$5 $or$libresoc.v:196232$13573_Y - connect \$7 $not$libresoc.v:196233$13574_Y + connect \$9 $and$libresoc.v:190552$13272_Y + connect \$11 $or$libresoc.v:190553$13273_Y + connect \$13 $not$libresoc.v:190554$13274_Y + connect \$15 $or$libresoc.v:190555$13275_Y + connect \$1 $not$libresoc.v:190556$13276_Y + connect \$3 $and$libresoc.v:190557$13277_Y + connect \$5 $or$libresoc.v:190558$13278_Y + connect \$7 $not$libresoc.v:190559$13279_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:196252.1-196310.10" +attribute \src "libresoc.v:190578.1-190636.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" module \src_l$55 - attribute \src "libresoc.v:196253.7-196253.20" + attribute \src "libresoc.v:190579.7-190579.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196298.3-196306.6" - wire width 3 $0\q_int$next[2:0]$13591 - attribute \src "libresoc.v:196296.3-196297.27" + attribute \src "libresoc.v:190624.3-190632.6" + wire width 3 $0\q_int$next[2:0]$13296 + attribute \src "libresoc.v:190622.3-190623.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:196298.3-196306.6" - wire width 3 $1\q_int$next[2:0]$13592 - attribute \src "libresoc.v:196275.13-196275.25" + attribute \src "libresoc.v:190624.3-190632.6" + wire width 3 $1\q_int$next[2:0]$13297 + attribute \src "libresoc.v:190601.13-190601.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:196288.17-196288.96" - wire width 3 $and$libresoc.v:196288$13581_Y - attribute \src "libresoc.v:196293.17-196293.96" - wire width 3 $and$libresoc.v:196293$13586_Y - attribute \src "libresoc.v:196290.18-196290.93" - wire width 3 $not$libresoc.v:196290$13583_Y - attribute \src "libresoc.v:196292.17-196292.92" - wire width 3 $not$libresoc.v:196292$13585_Y - attribute \src "libresoc.v:196295.17-196295.92" - wire width 3 $not$libresoc.v:196295$13588_Y - attribute \src "libresoc.v:196289.18-196289.98" - wire width 3 $or$libresoc.v:196289$13582_Y - attribute \src "libresoc.v:196291.18-196291.99" - wire width 3 $or$libresoc.v:196291$13584_Y - attribute \src "libresoc.v:196294.17-196294.97" - wire width 3 $or$libresoc.v:196294$13587_Y + attribute \src "libresoc.v:190614.17-190614.96" + wire width 3 $and$libresoc.v:190614$13286_Y + attribute \src "libresoc.v:190619.17-190619.96" + wire width 3 $and$libresoc.v:190619$13291_Y + attribute \src "libresoc.v:190616.18-190616.93" + wire width 3 $not$libresoc.v:190616$13288_Y + attribute \src "libresoc.v:190618.17-190618.92" + wire width 3 $not$libresoc.v:190618$13290_Y + attribute \src "libresoc.v:190621.17-190621.92" + wire width 3 $not$libresoc.v:190621$13293_Y + attribute \src "libresoc.v:190615.18-190615.98" + wire width 3 $or$libresoc.v:190615$13287_Y + attribute \src "libresoc.v:190617.18-190617.99" + wire width 3 $or$libresoc.v:190617$13289_Y + attribute \src "libresoc.v:190620.17-190620.97" + wire width 3 $or$libresoc.v:190620$13292_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -407933,11 +398733,11 @@ module \src_l$55 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:196253.7-196253.15" + attribute \src "libresoc.v:190579.7-190579.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -407954,7 +398754,7 @@ module \src_l$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:196288$13581 + cell $and $and$libresoc.v:190614$13286 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407962,10 +398762,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:196288$13581_Y + connect \Y $and$libresoc.v:190614$13286_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:196293$13586 + cell $and $and$libresoc.v:190619$13291 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -407973,34 +398773,34 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:196293$13586_Y + connect \Y $and$libresoc.v:190619$13291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:196290$13583 + cell $not $not$libresoc.v:190616$13288 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:196290$13583_Y + connect \Y $not$libresoc.v:190616$13288_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:196292$13585 + cell $not $not$libresoc.v:190618$13290 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:196292$13585_Y + connect \Y $not$libresoc.v:190618$13290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:196295$13588 + cell $not $not$libresoc.v:190621$13293 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:196295$13588_Y + connect \Y $not$libresoc.v:190621$13293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:196289$13582 + cell $or $or$libresoc.v:190615$13287 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -408008,10 +398808,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:196289$13582_Y + connect \Y $or$libresoc.v:190615$13287_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:196291$13584 + cell $or $or$libresoc.v:190617$13289 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -408019,10 +398819,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:196291$13584_Y + connect \Y $or$libresoc.v:190617$13289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:196294$13587 + cell $or $or$libresoc.v:190620$13292 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -408030,39 +398830,39 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:196294$13587_Y + connect \Y $or$libresoc.v:190620$13292_Y end - attribute \src "libresoc.v:196253.7-196253.20" - process $proc$libresoc.v:196253$13593 + attribute \src "libresoc.v:190579.7-190579.20" + process $proc$libresoc.v:190579$13298 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196275.13-196275.25" - process $proc$libresoc.v:196275$13594 + attribute \src "libresoc.v:190601.13-190601.25" + process $proc$libresoc.v:190601$13299 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:196296.3-196297.27" - process $proc$libresoc.v:196296$13589 + attribute \src "libresoc.v:190622.3-190623.27" + process $proc$libresoc.v:190622$13294 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:196298.3-196306.6" - process $proc$libresoc.v:196298$13590 + attribute \src "libresoc.v:190624.3-190632.6" + process $proc$libresoc.v:190624$13295 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13591 $1\q_int$next[2:0]$13592 - attribute \src "libresoc.v:196299.5-196299.29" + assign $0\q_int$next[2:0]$13296 $1\q_int$next[2:0]$13297 + attribute \src "libresoc.v:190625.5-190625.29" switch \initial - attribute \src "libresoc.v:196299.9-196299.17" + attribute \src "libresoc.v:190625.9-190625.17" case 1'1 case end @@ -408071,56 +398871,56 @@ module \src_l$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13592 3'000 + assign $1\q_int$next[2:0]$13297 3'000 case - assign $1\q_int$next[2:0]$13592 \$5 + assign $1\q_int$next[2:0]$13297 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13591 + update \q_int$next $0\q_int$next[2:0]$13296 end - connect \$9 $and$libresoc.v:196288$13581_Y - connect \$11 $or$libresoc.v:196289$13582_Y - connect \$13 $not$libresoc.v:196290$13583_Y - connect \$15 $or$libresoc.v:196291$13584_Y - connect \$1 $not$libresoc.v:196292$13585_Y - connect \$3 $and$libresoc.v:196293$13586_Y - connect \$5 $or$libresoc.v:196294$13587_Y - connect \$7 $not$libresoc.v:196295$13588_Y + connect \$9 $and$libresoc.v:190614$13286_Y + connect \$11 $or$libresoc.v:190615$13287_Y + connect \$13 $not$libresoc.v:190616$13288_Y + connect \$15 $or$libresoc.v:190617$13289_Y + connect \$1 $not$libresoc.v:190618$13290_Y + connect \$3 $and$libresoc.v:190619$13291_Y + connect \$5 $or$libresoc.v:190620$13292_Y + connect \$7 $not$libresoc.v:190621$13293_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:196314.1-196372.10" +attribute \src "libresoc.v:190640.1-190698.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" module \src_l$67 - attribute \src "libresoc.v:196315.7-196315.20" + attribute \src "libresoc.v:190641.7-190641.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196360.3-196368.6" - wire width 6 $0\q_int$next[5:0]$13605 - attribute \src "libresoc.v:196358.3-196359.27" + attribute \src "libresoc.v:190686.3-190694.6" + wire width 6 $0\q_int$next[5:0]$13310 + attribute \src "libresoc.v:190684.3-190685.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:196360.3-196368.6" - wire width 6 $1\q_int$next[5:0]$13606 - attribute \src "libresoc.v:196337.13-196337.26" + attribute \src "libresoc.v:190686.3-190694.6" + wire width 6 $1\q_int$next[5:0]$13311 + attribute \src "libresoc.v:190663.13-190663.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:196350.17-196350.96" - wire width 6 $and$libresoc.v:196350$13595_Y - attribute \src "libresoc.v:196355.17-196355.96" - wire width 6 $and$libresoc.v:196355$13600_Y - attribute \src "libresoc.v:196352.18-196352.93" - wire width 6 $not$libresoc.v:196352$13597_Y - attribute \src "libresoc.v:196354.17-196354.92" - wire width 6 $not$libresoc.v:196354$13599_Y - attribute \src "libresoc.v:196357.17-196357.92" - wire width 6 $not$libresoc.v:196357$13602_Y - attribute \src "libresoc.v:196351.18-196351.98" - wire width 6 $or$libresoc.v:196351$13596_Y - attribute \src "libresoc.v:196353.18-196353.99" - wire width 6 $or$libresoc.v:196353$13598_Y - attribute \src "libresoc.v:196356.17-196356.97" - wire width 6 $or$libresoc.v:196356$13601_Y + attribute \src "libresoc.v:190676.17-190676.96" + wire width 6 $and$libresoc.v:190676$13300_Y + attribute \src "libresoc.v:190681.17-190681.96" + wire width 6 $and$libresoc.v:190681$13305_Y + attribute \src "libresoc.v:190678.18-190678.93" + wire width 6 $not$libresoc.v:190678$13302_Y + attribute \src "libresoc.v:190680.17-190680.92" + wire width 6 $not$libresoc.v:190680$13304_Y + attribute \src "libresoc.v:190683.17-190683.92" + wire width 6 $not$libresoc.v:190683$13307_Y + attribute \src "libresoc.v:190677.18-190677.98" + wire width 6 $or$libresoc.v:190677$13301_Y + attribute \src "libresoc.v:190679.18-190679.99" + wire width 6 $or$libresoc.v:190679$13303_Y + attribute \src "libresoc.v:190682.17-190682.97" + wire width 6 $or$libresoc.v:190682$13306_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -408137,11 +398937,11 @@ module \src_l$67 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:196315.7-196315.15" + attribute \src "libresoc.v:190641.7-190641.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -408158,7 +398958,7 @@ module \src_l$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:196350$13595 + cell $and $and$libresoc.v:190676$13300 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -408166,10 +398966,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:196350$13595_Y + connect \Y $and$libresoc.v:190676$13300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:196355$13600 + cell $and $and$libresoc.v:190681$13305 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -408177,34 +398977,34 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:196355$13600_Y + connect \Y $and$libresoc.v:190681$13305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:196352$13597 + cell $not $not$libresoc.v:190678$13302 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:196352$13597_Y + connect \Y $not$libresoc.v:190678$13302_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:196354$13599 + cell $not $not$libresoc.v:190680$13304 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:196354$13599_Y + connect \Y $not$libresoc.v:190680$13304_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:196357$13602 + cell $not $not$libresoc.v:190683$13307 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:196357$13602_Y + connect \Y $not$libresoc.v:190683$13307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:196351$13596 + cell $or $or$libresoc.v:190677$13301 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -408212,10 +399012,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:196351$13596_Y + connect \Y $or$libresoc.v:190677$13301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:196353$13598 + cell $or $or$libresoc.v:190679$13303 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -408223,10 +399023,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:196353$13598_Y + connect \Y $or$libresoc.v:190679$13303_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:196356$13601 + cell $or $or$libresoc.v:190682$13306 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -408234,39 +399034,39 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:196356$13601_Y + connect \Y $or$libresoc.v:190682$13306_Y end - attribute \src "libresoc.v:196315.7-196315.20" - process $proc$libresoc.v:196315$13607 + attribute \src "libresoc.v:190641.7-190641.20" + process $proc$libresoc.v:190641$13312 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196337.13-196337.26" - process $proc$libresoc.v:196337$13608 + attribute \src "libresoc.v:190663.13-190663.26" + process $proc$libresoc.v:190663$13313 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:196358.3-196359.27" - process $proc$libresoc.v:196358$13603 + attribute \src "libresoc.v:190684.3-190685.27" + process $proc$libresoc.v:190684$13308 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:196360.3-196368.6" - process $proc$libresoc.v:196360$13604 + attribute \src "libresoc.v:190686.3-190694.6" + process $proc$libresoc.v:190686$13309 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13605 $1\q_int$next[5:0]$13606 - attribute \src "libresoc.v:196361.5-196361.29" + assign $0\q_int$next[5:0]$13310 $1\q_int$next[5:0]$13311 + attribute \src "libresoc.v:190687.5-190687.29" switch \initial - attribute \src "libresoc.v:196361.9-196361.17" + attribute \src "libresoc.v:190687.9-190687.17" case 1'1 case end @@ -408275,56 +399075,56 @@ module \src_l$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13606 6'000000 + assign $1\q_int$next[5:0]$13311 6'000000 case - assign $1\q_int$next[5:0]$13606 \$5 + assign $1\q_int$next[5:0]$13311 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13605 + update \q_int$next $0\q_int$next[5:0]$13310 end - connect \$9 $and$libresoc.v:196350$13595_Y - connect \$11 $or$libresoc.v:196351$13596_Y - connect \$13 $not$libresoc.v:196352$13597_Y - connect \$15 $or$libresoc.v:196353$13598_Y - connect \$1 $not$libresoc.v:196354$13599_Y - connect \$3 $and$libresoc.v:196355$13600_Y - connect \$5 $or$libresoc.v:196356$13601_Y - connect \$7 $not$libresoc.v:196357$13602_Y + connect \$9 $and$libresoc.v:190676$13300_Y + connect \$11 $or$libresoc.v:190677$13301_Y + connect \$13 $not$libresoc.v:190678$13302_Y + connect \$15 $or$libresoc.v:190679$13303_Y + connect \$1 $not$libresoc.v:190680$13304_Y + connect \$3 $and$libresoc.v:190681$13305_Y + connect \$5 $or$libresoc.v:190682$13306_Y + connect \$7 $not$libresoc.v:190683$13307_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:196376.1-196434.10" +attribute \src "libresoc.v:190702.1-190760.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" module \src_l$84 - attribute \src "libresoc.v:196377.7-196377.20" + attribute \src "libresoc.v:190703.7-190703.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196422.3-196430.6" - wire width 3 $0\q_int$next[2:0]$13619 - attribute \src "libresoc.v:196420.3-196421.27" + attribute \src "libresoc.v:190748.3-190756.6" + wire width 3 $0\q_int$next[2:0]$13324 + attribute \src "libresoc.v:190746.3-190747.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:196422.3-196430.6" - wire width 3 $1\q_int$next[2:0]$13620 - attribute \src "libresoc.v:196399.13-196399.25" + attribute \src "libresoc.v:190748.3-190756.6" + wire width 3 $1\q_int$next[2:0]$13325 + attribute \src "libresoc.v:190725.13-190725.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:196412.17-196412.96" - wire width 3 $and$libresoc.v:196412$13609_Y - attribute \src "libresoc.v:196417.17-196417.96" - wire width 3 $and$libresoc.v:196417$13614_Y - attribute \src "libresoc.v:196414.18-196414.93" - wire width 3 $not$libresoc.v:196414$13611_Y - attribute \src "libresoc.v:196416.17-196416.92" - wire width 3 $not$libresoc.v:196416$13613_Y - attribute \src "libresoc.v:196419.17-196419.92" - wire width 3 $not$libresoc.v:196419$13616_Y - attribute \src "libresoc.v:196413.18-196413.98" - wire width 3 $or$libresoc.v:196413$13610_Y - attribute \src "libresoc.v:196415.18-196415.99" - wire width 3 $or$libresoc.v:196415$13612_Y - attribute \src "libresoc.v:196418.17-196418.97" - wire width 3 $or$libresoc.v:196418$13615_Y + attribute \src "libresoc.v:190738.17-190738.96" + wire width 3 $and$libresoc.v:190738$13314_Y + attribute \src "libresoc.v:190743.17-190743.96" + wire width 3 $and$libresoc.v:190743$13319_Y + attribute \src "libresoc.v:190740.18-190740.93" + wire width 3 $not$libresoc.v:190740$13316_Y + attribute \src "libresoc.v:190742.17-190742.92" + wire width 3 $not$libresoc.v:190742$13318_Y + attribute \src "libresoc.v:190745.17-190745.92" + wire width 3 $not$libresoc.v:190745$13321_Y + attribute \src "libresoc.v:190739.18-190739.98" + wire width 3 $or$libresoc.v:190739$13315_Y + attribute \src "libresoc.v:190741.18-190741.99" + wire width 3 $or$libresoc.v:190741$13317_Y + attribute \src "libresoc.v:190744.17-190744.97" + wire width 3 $or$libresoc.v:190744$13320_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -408341,11 +399141,11 @@ module \src_l$84 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:196377.7-196377.15" + attribute \src "libresoc.v:190703.7-190703.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -408362,7 +399162,7 @@ module \src_l$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:196412$13609 + cell $and $and$libresoc.v:190738$13314 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -408370,10 +399170,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:196412$13609_Y + connect \Y $and$libresoc.v:190738$13314_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:196417$13614 + cell $and $and$libresoc.v:190743$13319 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -408381,34 +399181,34 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:196417$13614_Y + connect \Y $and$libresoc.v:190743$13319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:196414$13611 + cell $not $not$libresoc.v:190740$13316 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:196414$13611_Y + connect \Y $not$libresoc.v:190740$13316_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:196416$13613 + cell $not $not$libresoc.v:190742$13318 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:196416$13613_Y + connect \Y $not$libresoc.v:190742$13318_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:196419$13616 + cell $not $not$libresoc.v:190745$13321 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:196419$13616_Y + connect \Y $not$libresoc.v:190745$13321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:196413$13610 + cell $or $or$libresoc.v:190739$13315 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -408416,10 +399216,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:196413$13610_Y + connect \Y $or$libresoc.v:190739$13315_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:196415$13612 + cell $or $or$libresoc.v:190741$13317 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -408427,10 +399227,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:196415$13612_Y + connect \Y $or$libresoc.v:190741$13317_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:196418$13615 + cell $or $or$libresoc.v:190744$13320 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -408438,39 +399238,39 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:196418$13615_Y + connect \Y $or$libresoc.v:190744$13320_Y end - attribute \src "libresoc.v:196377.7-196377.20" - process $proc$libresoc.v:196377$13621 + attribute \src "libresoc.v:190703.7-190703.20" + process $proc$libresoc.v:190703$13326 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196399.13-196399.25" - process $proc$libresoc.v:196399$13622 + attribute \src "libresoc.v:190725.13-190725.25" + process $proc$libresoc.v:190725$13327 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:196420.3-196421.27" - process $proc$libresoc.v:196420$13617 + attribute \src "libresoc.v:190746.3-190747.27" + process $proc$libresoc.v:190746$13322 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:196422.3-196430.6" - process $proc$libresoc.v:196422$13618 + attribute \src "libresoc.v:190748.3-190756.6" + process $proc$libresoc.v:190748$13323 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13619 $1\q_int$next[2:0]$13620 - attribute \src "libresoc.v:196423.5-196423.29" + assign $0\q_int$next[2:0]$13324 $1\q_int$next[2:0]$13325 + attribute \src "libresoc.v:190749.5-190749.29" switch \initial - attribute \src "libresoc.v:196423.9-196423.17" + attribute \src "libresoc.v:190749.9-190749.17" case 1'1 case end @@ -408479,56 +399279,56 @@ module \src_l$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13620 3'000 + assign $1\q_int$next[2:0]$13325 3'000 case - assign $1\q_int$next[2:0]$13620 \$5 + assign $1\q_int$next[2:0]$13325 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13619 + update \q_int$next $0\q_int$next[2:0]$13324 end - connect \$9 $and$libresoc.v:196412$13609_Y - connect \$11 $or$libresoc.v:196413$13610_Y - connect \$13 $not$libresoc.v:196414$13611_Y - connect \$15 $or$libresoc.v:196415$13612_Y - connect \$1 $not$libresoc.v:196416$13613_Y - connect \$3 $and$libresoc.v:196417$13614_Y - connect \$5 $or$libresoc.v:196418$13615_Y - connect \$7 $not$libresoc.v:196419$13616_Y + connect \$9 $and$libresoc.v:190738$13314_Y + connect \$11 $or$libresoc.v:190739$13315_Y + connect \$13 $not$libresoc.v:190740$13316_Y + connect \$15 $or$libresoc.v:190741$13317_Y + connect \$1 $not$libresoc.v:190742$13318_Y + connect \$3 $and$libresoc.v:190743$13319_Y + connect \$5 $or$libresoc.v:190744$13320_Y + connect \$7 $not$libresoc.v:190745$13321_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:196438.1-196496.10" +attribute \src "libresoc.v:190764.1-190822.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active - attribute \src "libresoc.v:196439.7-196439.20" + attribute \src "libresoc.v:190765.7-190765.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196484.3-196492.6" - wire $0\q_int$next[0:0]$13633 - attribute \src "libresoc.v:196482.3-196483.27" + attribute \src "libresoc.v:190810.3-190818.6" + wire $0\q_int$next[0:0]$13338 + attribute \src "libresoc.v:190808.3-190809.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:196484.3-196492.6" - wire $1\q_int$next[0:0]$13634 - attribute \src "libresoc.v:196461.7-196461.19" + attribute \src "libresoc.v:190810.3-190818.6" + wire $1\q_int$next[0:0]$13339 + attribute \src "libresoc.v:190787.7-190787.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:196474.17-196474.96" - wire $and$libresoc.v:196474$13623_Y - attribute \src "libresoc.v:196479.17-196479.96" - wire $and$libresoc.v:196479$13628_Y - attribute \src "libresoc.v:196476.18-196476.99" - wire $not$libresoc.v:196476$13625_Y - attribute \src "libresoc.v:196478.17-196478.98" - wire $not$libresoc.v:196478$13627_Y - attribute \src "libresoc.v:196481.17-196481.98" - wire $not$libresoc.v:196481$13630_Y - attribute \src "libresoc.v:196475.18-196475.104" - wire $or$libresoc.v:196475$13624_Y - attribute \src "libresoc.v:196477.18-196477.105" - wire $or$libresoc.v:196477$13626_Y - attribute \src "libresoc.v:196480.17-196480.103" - wire $or$libresoc.v:196480$13629_Y + attribute \src "libresoc.v:190800.17-190800.96" + wire $and$libresoc.v:190800$13328_Y + attribute \src "libresoc.v:190805.17-190805.96" + wire $and$libresoc.v:190805$13333_Y + attribute \src "libresoc.v:190802.18-190802.99" + wire $not$libresoc.v:190802$13330_Y + attribute \src "libresoc.v:190804.17-190804.98" + wire $not$libresoc.v:190804$13332_Y + attribute \src "libresoc.v:190807.17-190807.98" + wire $not$libresoc.v:190807$13335_Y + attribute \src "libresoc.v:190801.18-190801.104" + wire $or$libresoc.v:190801$13329_Y + attribute \src "libresoc.v:190803.18-190803.105" + wire $or$libresoc.v:190803$13331_Y + attribute \src "libresoc.v:190806.17-190806.103" + wire $or$libresoc.v:190806$13334_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -408545,11 +399345,11 @@ module \st_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:196439.7-196439.15" + attribute \src "libresoc.v:190765.7-190765.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -408566,7 +399366,7 @@ module \st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:196474$13623 + cell $and $and$libresoc.v:190800$13328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -408574,10 +399374,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:196474$13623_Y + connect \Y $and$libresoc.v:190800$13328_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:196479$13628 + cell $and $and$libresoc.v:190805$13333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -408585,34 +399385,34 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:196479$13628_Y + connect \Y $and$libresoc.v:190805$13333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:196476$13625 + cell $not $not$libresoc.v:190802$13330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active - connect \Y $not$libresoc.v:196476$13625_Y + connect \Y $not$libresoc.v:190802$13330_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:196478$13627 + cell $not $not$libresoc.v:190804$13332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:196478$13627_Y + connect \Y $not$libresoc.v:190804$13332_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:196481$13630 + cell $not $not$libresoc.v:190807$13335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:196481$13630_Y + connect \Y $not$libresoc.v:190807$13335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:196475$13624 + cell $or $or$libresoc.v:190801$13329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -408620,10 +399420,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active - connect \Y $or$libresoc.v:196475$13624_Y + connect \Y $or$libresoc.v:190801$13329_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:196477$13626 + cell $or $or$libresoc.v:190803$13331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -408631,10 +399431,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int - connect \Y $or$libresoc.v:196477$13626_Y + connect \Y $or$libresoc.v:190803$13331_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:196480$13629 + cell $or $or$libresoc.v:190806$13334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -408642,39 +399442,39 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active - connect \Y $or$libresoc.v:196480$13629_Y + connect \Y $or$libresoc.v:190806$13334_Y end - attribute \src "libresoc.v:196439.7-196439.20" - process $proc$libresoc.v:196439$13635 + attribute \src "libresoc.v:190765.7-190765.20" + process $proc$libresoc.v:190765$13340 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196461.7-196461.19" - process $proc$libresoc.v:196461$13636 + attribute \src "libresoc.v:190787.7-190787.19" + process $proc$libresoc.v:190787$13341 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:196482.3-196483.27" - process $proc$libresoc.v:196482$13631 + attribute \src "libresoc.v:190808.3-190809.27" + process $proc$libresoc.v:190808$13336 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:196484.3-196492.6" - process $proc$libresoc.v:196484$13632 + attribute \src "libresoc.v:190810.3-190818.6" + process $proc$libresoc.v:190810$13337 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13633 $1\q_int$next[0:0]$13634 - attribute \src "libresoc.v:196485.5-196485.29" + assign $0\q_int$next[0:0]$13338 $1\q_int$next[0:0]$13339 + attribute \src "libresoc.v:190811.5-190811.29" switch \initial - attribute \src "libresoc.v:196485.9-196485.17" + attribute \src "libresoc.v:190811.9-190811.17" case 1'1 case end @@ -408683,56 +399483,56 @@ module \st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13634 1'0 + assign $1\q_int$next[0:0]$13339 1'0 case - assign $1\q_int$next[0:0]$13634 \$5 + assign $1\q_int$next[0:0]$13339 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13633 + update \q_int$next $0\q_int$next[0:0]$13338 end - connect \$9 $and$libresoc.v:196474$13623_Y - connect \$11 $or$libresoc.v:196475$13624_Y - connect \$13 $not$libresoc.v:196476$13625_Y - connect \$15 $or$libresoc.v:196477$13626_Y - connect \$1 $not$libresoc.v:196478$13627_Y - connect \$3 $and$libresoc.v:196479$13628_Y - connect \$5 $or$libresoc.v:196480$13629_Y - connect \$7 $not$libresoc.v:196481$13630_Y + connect \$9 $and$libresoc.v:190800$13328_Y + connect \$11 $or$libresoc.v:190801$13329_Y + connect \$13 $not$libresoc.v:190802$13330_Y + connect \$15 $or$libresoc.v:190803$13331_Y + connect \$1 $not$libresoc.v:190804$13332_Y + connect \$3 $and$libresoc.v:190805$13333_Y + connect \$5 $or$libresoc.v:190806$13334_Y + connect \$7 $not$libresoc.v:190807$13335_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end -attribute \src "libresoc.v:196500.1-196558.10" +attribute \src "libresoc.v:190826.1-190884.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done - attribute \src "libresoc.v:196501.7-196501.20" + attribute \src "libresoc.v:190827.7-190827.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196546.3-196554.6" - wire $0\q_int$next[0:0]$13647 - attribute \src "libresoc.v:196544.3-196545.27" + attribute \src "libresoc.v:190872.3-190880.6" + wire $0\q_int$next[0:0]$13352 + attribute \src "libresoc.v:190870.3-190871.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:196546.3-196554.6" - wire $1\q_int$next[0:0]$13648 - attribute \src "libresoc.v:196523.7-196523.19" + attribute \src "libresoc.v:190872.3-190880.6" + wire $1\q_int$next[0:0]$13353 + attribute \src "libresoc.v:190849.7-190849.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:196536.17-196536.96" - wire $and$libresoc.v:196536$13637_Y - attribute \src "libresoc.v:196541.17-196541.96" - wire $and$libresoc.v:196541$13642_Y - attribute \src "libresoc.v:196538.18-196538.97" - wire $not$libresoc.v:196538$13639_Y - attribute \src "libresoc.v:196540.17-196540.96" - wire $not$libresoc.v:196540$13641_Y - attribute \src "libresoc.v:196543.17-196543.96" - wire $not$libresoc.v:196543$13644_Y - attribute \src "libresoc.v:196537.18-196537.102" - wire $or$libresoc.v:196537$13638_Y - attribute \src "libresoc.v:196539.18-196539.103" - wire $or$libresoc.v:196539$13640_Y - attribute \src "libresoc.v:196542.17-196542.101" - wire $or$libresoc.v:196542$13643_Y + attribute \src "libresoc.v:190862.17-190862.96" + wire $and$libresoc.v:190862$13342_Y + attribute \src "libresoc.v:190867.17-190867.96" + wire $and$libresoc.v:190867$13347_Y + attribute \src "libresoc.v:190864.18-190864.97" + wire $not$libresoc.v:190864$13344_Y + attribute \src "libresoc.v:190866.17-190866.96" + wire $not$libresoc.v:190866$13346_Y + attribute \src "libresoc.v:190869.17-190869.96" + wire $not$libresoc.v:190869$13349_Y + attribute \src "libresoc.v:190863.18-190863.102" + wire $or$libresoc.v:190863$13343_Y + attribute \src "libresoc.v:190865.18-190865.103" + wire $or$libresoc.v:190865$13345_Y + attribute \src "libresoc.v:190868.17-190868.101" + wire $or$libresoc.v:190868$13348_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -408749,11 +399549,11 @@ module \st_done wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:196501.7-196501.15" + attribute \src "libresoc.v:190827.7-190827.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -408770,7 +399570,7 @@ module \st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:196536$13637 + cell $and $and$libresoc.v:190862$13342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -408778,10 +399578,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:196536$13637_Y + connect \Y $and$libresoc.v:190862$13342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:196541$13642 + cell $and $and$libresoc.v:190867$13347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -408789,34 +399589,34 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:196541$13642_Y + connect \Y $and$libresoc.v:190867$13347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:196538$13639 + cell $not $not$libresoc.v:190864$13344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done - connect \Y $not$libresoc.v:196538$13639_Y + connect \Y $not$libresoc.v:190864$13344_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:196540$13641 + cell $not $not$libresoc.v:190866$13346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:196540$13641_Y + connect \Y $not$libresoc.v:190866$13346_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:196543$13644 + cell $not $not$libresoc.v:190869$13349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:196543$13644_Y + connect \Y $not$libresoc.v:190869$13349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:196537$13638 + cell $or $or$libresoc.v:190863$13343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -408824,10 +399624,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done - connect \Y $or$libresoc.v:196537$13638_Y + connect \Y $or$libresoc.v:190863$13343_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:196539$13640 + cell $or $or$libresoc.v:190865$13345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -408835,10 +399635,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int - connect \Y $or$libresoc.v:196539$13640_Y + connect \Y $or$libresoc.v:190865$13345_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:196542$13643 + cell $or $or$libresoc.v:190868$13348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -408846,39 +399646,39 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done - connect \Y $or$libresoc.v:196542$13643_Y + connect \Y $or$libresoc.v:190868$13348_Y end - attribute \src "libresoc.v:196501.7-196501.20" - process $proc$libresoc.v:196501$13649 + attribute \src "libresoc.v:190827.7-190827.20" + process $proc$libresoc.v:190827$13354 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196523.7-196523.19" - process $proc$libresoc.v:196523$13650 + attribute \src "libresoc.v:190849.7-190849.19" + process $proc$libresoc.v:190849$13355 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:196544.3-196545.27" - process $proc$libresoc.v:196544$13645 + attribute \src "libresoc.v:190870.3-190871.27" + process $proc$libresoc.v:190870$13350 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:196546.3-196554.6" - process $proc$libresoc.v:196546$13646 + attribute \src "libresoc.v:190872.3-190880.6" + process $proc$libresoc.v:190872$13351 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13647 $1\q_int$next[0:0]$13648 - attribute \src "libresoc.v:196547.5-196547.29" + assign $0\q_int$next[0:0]$13352 $1\q_int$next[0:0]$13353 + attribute \src "libresoc.v:190873.5-190873.29" switch \initial - attribute \src "libresoc.v:196547.9-196547.17" + attribute \src "libresoc.v:190873.9-190873.17" case 1'1 case end @@ -408887,86 +399687,86 @@ module \st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13648 1'0 + assign $1\q_int$next[0:0]$13353 1'0 case - assign $1\q_int$next[0:0]$13648 \$5 + assign $1\q_int$next[0:0]$13353 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13647 + update \q_int$next $0\q_int$next[0:0]$13352 end - connect \$9 $and$libresoc.v:196536$13637_Y - connect \$11 $or$libresoc.v:196537$13638_Y - connect \$13 $not$libresoc.v:196538$13639_Y - connect \$15 $or$libresoc.v:196539$13640_Y - connect \$1 $not$libresoc.v:196540$13641_Y - connect \$3 $and$libresoc.v:196541$13642_Y - connect \$5 $or$libresoc.v:196542$13643_Y - connect \$7 $not$libresoc.v:196543$13644_Y + connect \$9 $and$libresoc.v:190862$13342_Y + connect \$11 $or$libresoc.v:190863$13343_Y + connect \$13 $not$libresoc.v:190864$13344_Y + connect \$15 $or$libresoc.v:190865$13345_Y + connect \$1 $not$libresoc.v:190866$13346_Y + connect \$3 $and$libresoc.v:190867$13347_Y + connect \$5 $or$libresoc.v:190868$13348_Y + connect \$7 $not$libresoc.v:190869$13349_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end -attribute \src "libresoc.v:196562.1-196858.10" +attribute \src "libresoc.v:190888.1-191184.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state - attribute \src "libresoc.v:196810.3-196819.6" + attribute \src "libresoc.v:191136.3-191145.6" wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:196563.7-196563.20" + attribute \src "libresoc.v:190889.7-190889.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196829.3-196838.6" + attribute \src "libresoc.v:191155.3-191164.6" wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:196820.3-196828.6" - wire width 3 $0\ren_delay$12$next[2:0]$13674 - attribute \src "libresoc.v:196724.3-196725.43" - wire width 3 $0\ren_delay$12[2:0]$13663 - attribute \src "libresoc.v:196691.13-196691.34" - wire width 3 $0\ren_delay$12[2:0]$13680 - attribute \src "libresoc.v:196782.3-196790.6" - wire width 3 $0\ren_delay$19$next[2:0]$13666 - attribute \src "libresoc.v:196722.3-196723.43" - wire width 3 $0\ren_delay$19[2:0]$13661 - attribute \src "libresoc.v:196695.13-196695.34" - wire width 3 $0\ren_delay$19[2:0]$13682 - attribute \src "libresoc.v:196801.3-196809.6" - wire width 3 $0\ren_delay$next[2:0]$13670 - attribute \src "libresoc.v:196726.3-196727.35" + attribute \src "libresoc.v:191146.3-191154.6" + wire width 3 $0\ren_delay$12$next[2:0]$13379 + attribute \src "libresoc.v:191050.3-191051.43" + wire width 3 $0\ren_delay$12[2:0]$13368 + attribute \src "libresoc.v:191017.13-191017.34" + wire width 3 $0\ren_delay$12[2:0]$13385 + attribute \src "libresoc.v:191108.3-191116.6" + wire width 3 $0\ren_delay$19$next[2:0]$13371 + attribute \src "libresoc.v:191048.3-191049.43" + wire width 3 $0\ren_delay$19[2:0]$13366 + attribute \src "libresoc.v:191021.13-191021.34" + wire width 3 $0\ren_delay$19[2:0]$13387 + attribute \src "libresoc.v:191127.3-191135.6" + wire width 3 $0\ren_delay$next[2:0]$13375 + attribute \src "libresoc.v:191052.3-191053.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:196791.3-196800.6" + attribute \src "libresoc.v:191117.3-191126.6" wire width 64 $0\sv__data_o[63:0] - attribute \src "libresoc.v:196810.3-196819.6" + attribute \src "libresoc.v:191136.3-191145.6" wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:196829.3-196838.6" + attribute \src "libresoc.v:191155.3-191164.6" wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:196820.3-196828.6" - wire width 3 $1\ren_delay$12$next[2:0]$13675 - attribute \src "libresoc.v:196782.3-196790.6" - wire width 3 $1\ren_delay$19$next[2:0]$13667 - attribute \src "libresoc.v:196801.3-196809.6" - wire width 3 $1\ren_delay$next[2:0]$13671 - attribute \src "libresoc.v:196689.13-196689.29" + attribute \src "libresoc.v:191146.3-191154.6" + wire width 3 $1\ren_delay$12$next[2:0]$13380 + attribute \src "libresoc.v:191108.3-191116.6" + wire width 3 $1\ren_delay$19$next[2:0]$13372 + attribute \src "libresoc.v:191127.3-191135.6" + wire width 3 $1\ren_delay$next[2:0]$13376 + attribute \src "libresoc.v:191015.13-191015.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:196791.3-196800.6" + attribute \src "libresoc.v:191117.3-191126.6" wire width 64 $1\sv__data_o[63:0] - attribute \src "libresoc.v:196713.18-196713.109" - wire width 64 $or$libresoc.v:196713$13651_Y - attribute \src "libresoc.v:196715.18-196715.124" - wire width 64 $or$libresoc.v:196715$13653_Y - attribute \src "libresoc.v:196716.18-196716.110" - wire width 64 $or$libresoc.v:196716$13654_Y - attribute \src "libresoc.v:196718.18-196718.122" - wire width 64 $or$libresoc.v:196718$13656_Y - attribute \src "libresoc.v:196719.18-196719.109" - wire width 64 $or$libresoc.v:196719$13657_Y - attribute \src "libresoc.v:196721.17-196721.123" - wire width 64 $or$libresoc.v:196721$13659_Y - attribute \src "libresoc.v:196714.18-196714.100" - wire $reduce_or$libresoc.v:196714$13652_Y - attribute \src "libresoc.v:196717.18-196717.100" - wire $reduce_or$libresoc.v:196717$13655_Y - attribute \src "libresoc.v:196720.17-196720.95" - wire $reduce_or$libresoc.v:196720$13658_Y + attribute \src "libresoc.v:191039.18-191039.109" + wire width 64 $or$libresoc.v:191039$13356_Y + attribute \src "libresoc.v:191041.18-191041.124" + wire width 64 $or$libresoc.v:191041$13358_Y + attribute \src "libresoc.v:191042.18-191042.110" + wire width 64 $or$libresoc.v:191042$13359_Y + attribute \src "libresoc.v:191044.18-191044.122" + wire width 64 $or$libresoc.v:191044$13361_Y + attribute \src "libresoc.v:191045.18-191045.109" + wire width 64 $or$libresoc.v:191045$13362_Y + attribute \src "libresoc.v:191047.17-191047.123" + wire width 64 $or$libresoc.v:191047$13364_Y + attribute \src "libresoc.v:191040.18-191040.100" + wire $reduce_or$libresoc.v:191040$13357_Y + attribute \src "libresoc.v:191043.18-191043.100" + wire $reduce_or$libresoc.v:191043$13360_Y + attribute \src "libresoc.v:191046.17-191046.95" + wire $reduce_or$libresoc.v:191046$13363_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" @@ -408989,24 +399789,24 @@ module \state wire width 64 output 3 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 5 \data_i + wire width 64 input 7 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 input 12 \data_i$2 + wire width 64 input 11 \data_i$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 13 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \data_i$4 - attribute \src "libresoc.v:196563.7-196563.15" + attribute \src "libresoc.v:190889.7-190889.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 8 \msr__data_o + wire width 64 output 9 \msr__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 7 \msr__ren + wire width 3 input 8 \msr__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \reg_0_cia0__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" @@ -409104,19 +399904,19 @@ module \state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" wire width 3 \ren_delay$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 10 \state_nia_wen + wire width 3 input 12 \state_nia_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 output 9 \sv__data_o + wire width 64 output 5 \sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 6 \sv__ren + wire width 3 input 4 \sv__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 4 \wen + wire width 3 input 6 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 3 input 11 \wen$1 + wire width 3 input 10 \wen$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:196713$13651 + cell $or $or$libresoc.v:191039$13356 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409124,10 +399924,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_cia0__data_o connect \B \$8 - connect \Y $or$libresoc.v:196713$13651_Y + connect \Y $or$libresoc.v:191039$13356_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:196715$13653 + cell $or $or$libresoc.v:191041$13358 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409135,10 +399935,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_msr1__data_o connect \B \reg_2_msr2__data_o - connect \Y $or$libresoc.v:196715$13653_Y + connect \Y $or$libresoc.v:191041$13358_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:196716$13654 + cell $or $or$libresoc.v:191042$13359 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409146,10 +399946,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \$15 - connect \Y $or$libresoc.v:196716$13654_Y + connect \Y $or$libresoc.v:191042$13359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:196718$13656 + cell $or $or$libresoc.v:191044$13361 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409157,10 +399957,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_sv1__data_o connect \B \reg_2_sv2__data_o - connect \Y $or$libresoc.v:196718$13656_Y + connect \Y $or$libresoc.v:191044$13361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:196719$13657 + cell $or $or$libresoc.v:191045$13362 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409168,10 +399968,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_sv0__data_o connect \B \$22 - connect \Y $or$libresoc.v:196719$13657_Y + connect \Y $or$libresoc.v:191045$13362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:196721$13659 + cell $or $or$libresoc.v:191047$13364 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409179,34 +399979,34 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_cia1__data_o connect \B \reg_2_cia2__data_o - connect \Y $or$libresoc.v:196721$13659_Y + connect \Y $or$libresoc.v:191047$13364_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:196714$13652 + cell $reduce_or $reduce_or$libresoc.v:191040$13357 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:196714$13652_Y + connect \Y $reduce_or$libresoc.v:191040$13357_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:196717$13655 + cell $reduce_or $reduce_or$libresoc.v:191043$13360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$19 - connect \Y $reduce_or$libresoc.v:196717$13655_Y + connect \Y $reduce_or$libresoc.v:191043$13360_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:196720$13658 + cell $reduce_or $reduce_or$libresoc.v:191046$13363 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:196720$13658_Y + connect \Y $reduce_or$libresoc.v:191046$13363_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:196728.15-196745.4" + attribute \src "libresoc.v:191054.15-191071.4" cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren @@ -409226,7 +400026,7 @@ module \state connect \sv0__wen \reg_0_sv0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:196746.15-196763.4" + attribute \src "libresoc.v:191072.15-191089.4" cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren @@ -409246,7 +400046,7 @@ module \state connect \sv1__wen \reg_1_sv1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:196764.15-196781.4" + attribute \src "libresoc.v:191090.15-191107.4" cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren @@ -409265,67 +400065,67 @@ module \state connect \sv2__ren \reg_2_sv2__ren connect \sv2__wen \reg_2_sv2__wen end - attribute \src "libresoc.v:196563.7-196563.20" - process $proc$libresoc.v:196563$13677 + attribute \src "libresoc.v:190889.7-190889.20" + process $proc$libresoc.v:190889$13382 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196689.13-196689.29" - process $proc$libresoc.v:196689$13678 + attribute \src "libresoc.v:191015.13-191015.29" + process $proc$libresoc.v:191015$13383 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:196691.13-196691.34" - process $proc$libresoc.v:196691$13679 + attribute \src "libresoc.v:191017.13-191017.34" + process $proc$libresoc.v:191017$13384 assign { } { } - assign $0\ren_delay$12[2:0]$13680 3'000 + assign $0\ren_delay$12[2:0]$13385 3'000 sync always sync init - update \ren_delay$12 $0\ren_delay$12[2:0]$13680 + update \ren_delay$12 $0\ren_delay$12[2:0]$13385 end - attribute \src "libresoc.v:196695.13-196695.34" - process $proc$libresoc.v:196695$13681 + attribute \src "libresoc.v:191021.13-191021.34" + process $proc$libresoc.v:191021$13386 assign { } { } - assign $0\ren_delay$19[2:0]$13682 3'000 + assign $0\ren_delay$19[2:0]$13387 3'000 sync always sync init - update \ren_delay$19 $0\ren_delay$19[2:0]$13682 + update \ren_delay$19 $0\ren_delay$19[2:0]$13387 end - attribute \src "libresoc.v:196722.3-196723.43" - process $proc$libresoc.v:196722$13660 + attribute \src "libresoc.v:191048.3-191049.43" + process $proc$libresoc.v:191048$13365 assign { } { } - assign $0\ren_delay$19[2:0]$13661 \ren_delay$19$next + assign $0\ren_delay$19[2:0]$13366 \ren_delay$19$next sync posedge \coresync_clk - update \ren_delay$19 $0\ren_delay$19[2:0]$13661 + update \ren_delay$19 $0\ren_delay$19[2:0]$13366 end - attribute \src "libresoc.v:196724.3-196725.43" - process $proc$libresoc.v:196724$13662 + attribute \src "libresoc.v:191050.3-191051.43" + process $proc$libresoc.v:191050$13367 assign { } { } - assign $0\ren_delay$12[2:0]$13663 \ren_delay$12$next + assign $0\ren_delay$12[2:0]$13368 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[2:0]$13663 + update \ren_delay$12 $0\ren_delay$12[2:0]$13368 end - attribute \src "libresoc.v:196726.3-196727.35" - process $proc$libresoc.v:196726$13664 + attribute \src "libresoc.v:191052.3-191053.35" + process $proc$libresoc.v:191052$13369 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:196782.3-196790.6" - process $proc$libresoc.v:196782$13665 + attribute \src "libresoc.v:191108.3-191116.6" + process $proc$libresoc.v:191108$13370 assign { } { } assign { } { } - assign $0\ren_delay$19$next[2:0]$13666 $1\ren_delay$19$next[2:0]$13667 - attribute \src "libresoc.v:196783.5-196783.29" + assign $0\ren_delay$19$next[2:0]$13371 $1\ren_delay$19$next[2:0]$13372 + attribute \src "libresoc.v:191109.5-191109.29" switch \initial - attribute \src "libresoc.v:196783.9-196783.17" + attribute \src "libresoc.v:191109.9-191109.17" case 1'1 case end @@ -409334,21 +400134,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$19$next[2:0]$13667 3'000 + assign $1\ren_delay$19$next[2:0]$13372 3'000 case - assign $1\ren_delay$19$next[2:0]$13667 \sv__ren + assign $1\ren_delay$19$next[2:0]$13372 \sv__ren end sync always - update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13666 + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13371 end - attribute \src "libresoc.v:196791.3-196800.6" - process $proc$libresoc.v:196791$13668 + attribute \src "libresoc.v:191117.3-191126.6" + process $proc$libresoc.v:191117$13373 assign { } { } assign { } { } assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] - attribute \src "libresoc.v:196792.5-196792.29" + attribute \src "libresoc.v:191118.5-191118.29" switch \initial - attribute \src "libresoc.v:196792.9-196792.17" + attribute \src "libresoc.v:191118.9-191118.17" case 1'1 case end @@ -409364,14 +400164,14 @@ module \state sync always update \sv__data_o $0\sv__data_o[63:0] end - attribute \src "libresoc.v:196801.3-196809.6" - process $proc$libresoc.v:196801$13669 + attribute \src "libresoc.v:191127.3-191135.6" + process $proc$libresoc.v:191127$13374 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$13670 $1\ren_delay$next[2:0]$13671 - attribute \src "libresoc.v:196802.5-196802.29" + assign $0\ren_delay$next[2:0]$13375 $1\ren_delay$next[2:0]$13376 + attribute \src "libresoc.v:191128.5-191128.29" switch \initial - attribute \src "libresoc.v:196802.9-196802.17" + attribute \src "libresoc.v:191128.9-191128.17" case 1'1 case end @@ -409380,21 +400180,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$13671 3'000 + assign $1\ren_delay$next[2:0]$13376 3'000 case - assign $1\ren_delay$next[2:0]$13671 \cia__ren + assign $1\ren_delay$next[2:0]$13376 \cia__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$13670 + update \ren_delay$next $0\ren_delay$next[2:0]$13375 end - attribute \src "libresoc.v:196810.3-196819.6" - process $proc$libresoc.v:196810$13672 + attribute \src "libresoc.v:191136.3-191145.6" + process $proc$libresoc.v:191136$13377 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:196811.5-196811.29" + attribute \src "libresoc.v:191137.5-191137.29" switch \initial - attribute \src "libresoc.v:196811.9-196811.17" + attribute \src "libresoc.v:191137.9-191137.17" case 1'1 case end @@ -409410,14 +400210,14 @@ module \state sync always update \cia__data_o $0\cia__data_o[63:0] end - attribute \src "libresoc.v:196820.3-196828.6" - process $proc$libresoc.v:196820$13673 + attribute \src "libresoc.v:191146.3-191154.6" + process $proc$libresoc.v:191146$13378 assign { } { } assign { } { } - assign $0\ren_delay$12$next[2:0]$13674 $1\ren_delay$12$next[2:0]$13675 - attribute \src "libresoc.v:196821.5-196821.29" + assign $0\ren_delay$12$next[2:0]$13379 $1\ren_delay$12$next[2:0]$13380 + attribute \src "libresoc.v:191147.5-191147.29" switch \initial - attribute \src "libresoc.v:196821.9-196821.17" + attribute \src "libresoc.v:191147.9-191147.17" case 1'1 case end @@ -409426,21 +400226,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[2:0]$13675 3'000 + assign $1\ren_delay$12$next[2:0]$13380 3'000 case - assign $1\ren_delay$12$next[2:0]$13675 \msr__ren + assign $1\ren_delay$12$next[2:0]$13380 \msr__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13674 + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13379 end - attribute \src "libresoc.v:196829.3-196838.6" - process $proc$libresoc.v:196829$13676 + attribute \src "libresoc.v:191155.3-191164.6" + process $proc$libresoc.v:191155$13381 assign { } { } assign { } { } assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:196830.5-196830.29" + attribute \src "libresoc.v:191156.5-191156.29" switch \initial - attribute \src "libresoc.v:196830.9-196830.17" + attribute \src "libresoc.v:191156.9-191156.17" case 1'1 case end @@ -409456,15 +400256,15 @@ module \state sync always update \msr__data_o $0\msr__data_o[63:0] end - connect \$10 $or$libresoc.v:196713$13651_Y - connect \$13 $reduce_or$libresoc.v:196714$13652_Y - connect \$15 $or$libresoc.v:196715$13653_Y - connect \$17 $or$libresoc.v:196716$13654_Y - connect \$20 $reduce_or$libresoc.v:196717$13655_Y - connect \$22 $or$libresoc.v:196718$13656_Y - connect \$24 $or$libresoc.v:196719$13657_Y - connect \$6 $reduce_or$libresoc.v:196720$13658_Y - connect \$8 $or$libresoc.v:196721$13659_Y + connect \$10 $or$libresoc.v:191039$13356_Y + connect \$13 $reduce_or$libresoc.v:191040$13357_Y + connect \$15 $or$libresoc.v:191041$13358_Y + connect \$17 $or$libresoc.v:191042$13359_Y + connect \$20 $reduce_or$libresoc.v:191043$13360_Y + connect \$22 $or$libresoc.v:191044$13361_Y + connect \$24 $or$libresoc.v:191045$13362_Y + connect \$6 $reduce_or$libresoc.v:191046$13363_Y + connect \$8 $or$libresoc.v:191047$13364_Y connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i connect \reg_0_d_wr10__data_i \data_i @@ -409485,37 +400285,37 @@ module \state connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end -attribute \src "libresoc.v:196862.1-196920.10" +attribute \src "libresoc.v:191188.1-191246.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l - attribute \src "libresoc.v:196863.7-196863.20" + attribute \src "libresoc.v:191189.7-191189.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196908.3-196916.6" - wire $0\q_int$next[0:0]$13693 - attribute \src "libresoc.v:196906.3-196907.27" + attribute \src "libresoc.v:191234.3-191242.6" + wire $0\q_int$next[0:0]$13398 + attribute \src "libresoc.v:191232.3-191233.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:196908.3-196916.6" - wire $1\q_int$next[0:0]$13694 - attribute \src "libresoc.v:196885.7-196885.19" + attribute \src "libresoc.v:191234.3-191242.6" + wire $1\q_int$next[0:0]$13399 + attribute \src "libresoc.v:191211.7-191211.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:196898.17-196898.96" - wire $and$libresoc.v:196898$13683_Y - attribute \src "libresoc.v:196903.17-196903.96" - wire $and$libresoc.v:196903$13688_Y - attribute \src "libresoc.v:196900.18-196900.93" - wire $not$libresoc.v:196900$13685_Y - attribute \src "libresoc.v:196902.17-196902.92" - wire $not$libresoc.v:196902$13687_Y - attribute \src "libresoc.v:196905.17-196905.92" - wire $not$libresoc.v:196905$13690_Y - attribute \src "libresoc.v:196899.18-196899.98" - wire $or$libresoc.v:196899$13684_Y - attribute \src "libresoc.v:196901.18-196901.99" - wire $or$libresoc.v:196901$13686_Y - attribute \src "libresoc.v:196904.17-196904.97" - wire $or$libresoc.v:196904$13689_Y + attribute \src "libresoc.v:191224.17-191224.96" + wire $and$libresoc.v:191224$13388_Y + attribute \src "libresoc.v:191229.17-191229.96" + wire $and$libresoc.v:191229$13393_Y + attribute \src "libresoc.v:191226.18-191226.93" + wire $not$libresoc.v:191226$13390_Y + attribute \src "libresoc.v:191228.17-191228.92" + wire $not$libresoc.v:191228$13392_Y + attribute \src "libresoc.v:191231.17-191231.92" + wire $not$libresoc.v:191231$13395_Y + attribute \src "libresoc.v:191225.18-191225.98" + wire $or$libresoc.v:191225$13389_Y + attribute \src "libresoc.v:191227.18-191227.99" + wire $or$libresoc.v:191227$13391_Y + attribute \src "libresoc.v:191230.17-191230.97" + wire $or$libresoc.v:191230$13394_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -409532,11 +400332,11 @@ module \sto_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:196863.7-196863.15" + attribute \src "libresoc.v:191189.7-191189.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -409553,7 +400353,7 @@ module \sto_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:196898$13683 + cell $and $and$libresoc.v:191224$13388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409561,10 +400361,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:196898$13683_Y + connect \Y $and$libresoc.v:191224$13388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:196903$13688 + cell $and $and$libresoc.v:191229$13393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409572,34 +400372,34 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:196903$13688_Y + connect \Y $and$libresoc.v:191229$13393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:196900$13685 + cell $not $not$libresoc.v:191226$13390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto - connect \Y $not$libresoc.v:196900$13685_Y + connect \Y $not$libresoc.v:191226$13390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:196902$13687 + cell $not $not$libresoc.v:191228$13392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:196902$13687_Y + connect \Y $not$libresoc.v:191228$13392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:196905$13690 + cell $not $not$libresoc.v:191231$13395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:196905$13690_Y + connect \Y $not$libresoc.v:191231$13395_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:196899$13684 + cell $or $or$libresoc.v:191225$13389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409607,10 +400407,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto - connect \Y $or$libresoc.v:196899$13684_Y + connect \Y $or$libresoc.v:191225$13389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:196901$13686 + cell $or $or$libresoc.v:191227$13391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409618,10 +400418,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int - connect \Y $or$libresoc.v:196901$13686_Y + connect \Y $or$libresoc.v:191227$13391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:196904$13689 + cell $or $or$libresoc.v:191230$13394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409629,39 +400429,39 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto - connect \Y $or$libresoc.v:196904$13689_Y + connect \Y $or$libresoc.v:191230$13394_Y end - attribute \src "libresoc.v:196863.7-196863.20" - process $proc$libresoc.v:196863$13695 + attribute \src "libresoc.v:191189.7-191189.20" + process $proc$libresoc.v:191189$13400 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196885.7-196885.19" - process $proc$libresoc.v:196885$13696 + attribute \src "libresoc.v:191211.7-191211.19" + process $proc$libresoc.v:191211$13401 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:196906.3-196907.27" - process $proc$libresoc.v:196906$13691 + attribute \src "libresoc.v:191232.3-191233.27" + process $proc$libresoc.v:191232$13396 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:196908.3-196916.6" - process $proc$libresoc.v:196908$13692 + attribute \src "libresoc.v:191234.3-191242.6" + process $proc$libresoc.v:191234$13397 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13693 $1\q_int$next[0:0]$13694 - attribute \src "libresoc.v:196909.5-196909.29" + assign $0\q_int$next[0:0]$13398 $1\q_int$next[0:0]$13399 + attribute \src "libresoc.v:191235.5-191235.29" switch \initial - attribute \src "libresoc.v:196909.9-196909.17" + attribute \src "libresoc.v:191235.9-191235.17" case 1'1 case end @@ -409670,70 +400470,76 @@ module \sto_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13694 1'0 + assign $1\q_int$next[0:0]$13399 1'0 case - assign $1\q_int$next[0:0]$13694 \$5 + assign $1\q_int$next[0:0]$13399 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13693 + update \q_int$next $0\q_int$next[0:0]$13398 end - connect \$9 $and$libresoc.v:196898$13683_Y - connect \$11 $or$libresoc.v:196899$13684_Y - connect \$13 $not$libresoc.v:196900$13685_Y - connect \$15 $or$libresoc.v:196901$13686_Y - connect \$1 $not$libresoc.v:196902$13687_Y - connect \$3 $and$libresoc.v:196903$13688_Y - connect \$5 $or$libresoc.v:196904$13689_Y - connect \$7 $not$libresoc.v:196905$13690_Y + connect \$9 $and$libresoc.v:191224$13388_Y + connect \$11 $or$libresoc.v:191225$13389_Y + connect \$13 $not$libresoc.v:191226$13390_Y + connect \$15 $or$libresoc.v:191227$13391_Y + connect \$1 $not$libresoc.v:191228$13392_Y + connect \$3 $and$libresoc.v:191229$13393_Y + connect \$5 $or$libresoc.v:191230$13394_Y + connect \$7 $not$libresoc.v:191231$13395_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end -attribute \src "libresoc.v:196924.1-196967.10" +attribute \src "libresoc.v:191250.1-191305.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.svp64" attribute \generator "nMigen" module \svp64 - attribute \src "libresoc.v:196925.7-196925.20" + attribute \src "libresoc.v:191251.7-191251.20" wire $0\initial[0:0] - attribute \src "libresoc.v:196953.3-196962.6" + attribute \src "libresoc.v:191281.3-191290.6" + wire width 24 $0\rm[23:0] + attribute \src "libresoc.v:191291.3-191300.6" wire width 24 $0\svp64_rm[23:0] - attribute \src "libresoc.v:196953.3-196962.6" + attribute \src "libresoc.v:191281.3-191290.6" + wire width 24 $1\rm[23:0] + attribute \src "libresoc.v:191291.3-191300.6" wire width 24 $1\svp64_rm[23:0] - attribute \src "libresoc.v:196952.17-196952.108" - wire $and$libresoc.v:196952$13700_Y - attribute \src "libresoc.v:196950.17-196950.112" - wire $eq$libresoc.v:196950$13698_Y - attribute \src "libresoc.v:196951.17-196951.111" - wire $eq$libresoc.v:196951$13699_Y - attribute \src "libresoc.v:196949.17-196949.213" - wire width 32 $ternary$libresoc.v:196949$13697_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1325" + attribute \src "libresoc.v:191280.17-191280.110" + wire $and$libresoc.v:191280$13405_Y + attribute \src "libresoc.v:191278.17-191278.114" + wire $eq$libresoc.v:191278$13403_Y + attribute \src "libresoc.v:191279.17-191279.113" + wire $eq$libresoc.v:191279$13404_Y + attribute \src "libresoc.v:191277.17-191277.215" + wire width 32 $ternary$libresoc.v:191277$13402_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:35" wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1335" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:42" wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1336" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:43" wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1336" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:43" wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1311" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:21" wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:39" wire width 2 \ident - attribute \src "libresoc.v:196925.7-196925.15" + attribute \src "libresoc.v:191251.7-191251.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:19" wire output 3 \is_svp64_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1328" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:38" wire width 6 \major - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1307" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:17" wire width 32 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1308" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:18" wire width 32 input 4 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:48" + wire width 24 \rm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:20" wire width 24 output 2 \svp64_rm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1336" - cell $and $and$libresoc.v:196952$13700 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:43" + cell $and $and$libresoc.v:191280$13405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409741,10 +400547,10 @@ module \svp64 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:196952$13700_Y + connect \Y $and$libresoc.v:191280$13405_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1335" - cell $eq $eq$libresoc.v:196950$13698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:42" + cell $eq $eq$libresoc.v:191278$13403 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -409752,10 +400558,10 @@ module \svp64 parameter \Y_WIDTH 1 connect \A \major connect \B 6'000001 - connect \Y $eq$libresoc.v:196950$13698_Y + connect \Y $eq$libresoc.v:191278$13403_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1336" - cell $eq $eq$libresoc.v:196951$13699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:43" + cell $eq $eq$libresoc.v:191279$13404 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -409763,57 +400569,80 @@ module \svp64 parameter \Y_WIDTH 1 connect \A \ident connect \B 2'11 - connect \Y $eq$libresoc.v:196951$13699_Y + connect \Y $eq$libresoc.v:191279$13404_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1325" - cell $mux $ternary$libresoc.v:196949$13697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:35" + cell $mux $ternary$libresoc.v:191277$13402 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:196949$13697_Y + connect \Y $ternary$libresoc.v:191277$13402_Y end - attribute \src "libresoc.v:196925.7-196925.20" - process $proc$libresoc.v:196925$13702 + attribute \src "libresoc.v:191251.7-191251.20" + process $proc$libresoc.v:191251$13408 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:196953.3-196962.6" - process $proc$libresoc.v:196953$13701 + attribute \src "libresoc.v:191281.3-191290.6" + process $proc$libresoc.v:191281$13406 + assign { } { } + assign { } { } + assign $0\rm[23:0] $1\rm[23:0] + attribute \src "libresoc.v:191282.5-191282.29" + switch \initial + attribute \src "libresoc.v:191282.9-191282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:46" + switch \is_svp64_mode + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rm[23:0] { \opcode_in [25] \opcode_in [23] \opcode_in [21:0] } + case + assign $1\rm[23:0] 24'000000000000000000000000 + end + sync always + update \rm $0\rm[23:0] + end + attribute \src "libresoc.v:191291.3-191300.6" + process $proc$libresoc.v:191291$13407 assign { } { } assign { } { } assign $0\svp64_rm[23:0] $1\svp64_rm[23:0] - attribute \src "libresoc.v:196954.5-196954.29" + attribute \src "libresoc.v:191292.5-191292.29" switch \initial - attribute \src "libresoc.v:196954.9-196954.17" + attribute \src "libresoc.v:191292.9-191292.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:46" switch \is_svp64_mode attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\svp64_rm[23:0] { \opcode_in [25] \opcode_in [23] \opcode_in [21:0] } + assign $1\svp64_rm[23:0] \rm case assign $1\svp64_rm[23:0] 24'000000000000000000000000 end sync always update \svp64_rm $0\svp64_rm[23:0] end - connect \$1 $ternary$libresoc.v:196949$13697_Y - connect \$3 $eq$libresoc.v:196950$13698_Y - connect \$5 $eq$libresoc.v:196951$13699_Y - connect \$7 $and$libresoc.v:196952$13700_Y + connect \$1 $ternary$libresoc.v:191277$13402_Y + connect \$3 $eq$libresoc.v:191278$13403_Y + connect \$5 $eq$libresoc.v:191279$13404_Y + connect \$7 $and$libresoc.v:191280$13405_Y connect \is_svp64_mode \$7 connect \ident { \opcode_in [24] \opcode_in [22] } connect \major \opcode_in [31:26] connect \opcode_in \$1 end -attribute \src "libresoc.v:196972.1-198201.10" +attribute \src "libresoc.v:191310.1-192539.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" @@ -409827,13 +400656,13 @@ module \test_issuer wire output 6 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 8 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:123" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:127" wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 400 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" wire width 2 input 402 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:126" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 344 \dbus__ack @@ -410139,7 +400968,7 @@ module \test_issuer wire output 15 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 16 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:124" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:128" wire input 3 \memerr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 121 \mspi0_clk__core__o @@ -410193,9 +401022,9 @@ module \test_issuer wire width 64 input 405 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:120" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:123" wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:582" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:716" wire output 403 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" wire \pll_clk_24_i @@ -410205,9 +401034,9 @@ module \test_issuer wire output 404 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire \pll_pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" wire \pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" wire \pllclk_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 145 \pwm_0__core__o @@ -410217,7 +401046,7 @@ module \test_issuer wire input 147 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 148 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 401 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 155 \sd0_clk__core__o @@ -410575,74 +401404,74 @@ module \test_issuer wire input 263 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 264 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 356 \sram4k_0__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 349 \sram4k_0__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 353 \sram4k_0__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 351 \sram4k_0__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 350 \sram4k_0__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 352 \sram4k_0__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 354 \sram4k_0__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 355 \sram4k_0__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 364 \sram4k_1__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 357 \sram4k_1__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 361 \sram4k_1__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 359 \sram4k_1__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 358 \sram4k_1__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 360 \sram4k_1__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 362 \sram4k_1__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 363 \sram4k_1__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 372 \sram4k_2__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 365 \sram4k_2__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 369 \sram4k_2__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 367 \sram4k_2__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 366 \sram4k_2__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 368 \sram4k_2__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 370 \sram4k_2__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 371 \sram4k_2__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 380 \sram4k_3__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 373 \sram4k_3__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 377 \sram4k_3__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 375 \sram4k_3__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 374 \sram4k_3__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 376 \sram4k_3__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 378 \sram4k_3__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 379 \sram4k_3__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 356 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 349 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 353 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 351 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 350 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 352 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 354 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 355 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 364 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 357 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 361 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 359 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 358 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 360 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 362 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 363 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 372 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 365 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 369 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 367 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 366 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 368 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 370 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 371 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 380 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 373 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 377 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 375 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 374 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 376 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 378 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 379 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire \ti_coresync_clk attribute \module_not_derived 1 - attribute \src "libresoc.v:197795.7-197801.4" + attribute \src "libresoc.v:192133.7-192139.4" cell \pll \pll connect \clk_24_i \pll_clk_24_i connect \clk_pll_o \pll_clk_pll_o @@ -410651,7 +401480,7 @@ module \test_issuer connect \pll_lck_o \pll_lck_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:197802.6-198195.4" + attribute \src "libresoc.v:192140.6-192533.4" cell \ti \ti connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -411013,38 +401842,38 @@ module \test_issuer connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o connect \sdr_we_n__core__o \sdr_we_n__core__o connect \sdr_we_n__pad__o \sdr_we_n__pad__o - connect \sram4k_0__ack \sram4k_0__ack - connect \sram4k_0__adr \sram4k_0__adr - connect \sram4k_0__cyc \sram4k_0__cyc - connect \sram4k_0__dat_r \sram4k_0__dat_r - connect \sram4k_0__dat_w \sram4k_0__dat_w - connect \sram4k_0__sel \sram4k_0__sel - connect \sram4k_0__stb \sram4k_0__stb - connect \sram4k_0__we \sram4k_0__we - connect \sram4k_1__ack \sram4k_1__ack - connect \sram4k_1__adr \sram4k_1__adr - connect \sram4k_1__cyc \sram4k_1__cyc - connect \sram4k_1__dat_r \sram4k_1__dat_r - connect \sram4k_1__dat_w \sram4k_1__dat_w - connect \sram4k_1__sel \sram4k_1__sel - connect \sram4k_1__stb \sram4k_1__stb - connect \sram4k_1__we \sram4k_1__we - connect \sram4k_2__ack \sram4k_2__ack - connect \sram4k_2__adr \sram4k_2__adr - connect \sram4k_2__cyc \sram4k_2__cyc - connect \sram4k_2__dat_r \sram4k_2__dat_r - connect \sram4k_2__dat_w \sram4k_2__dat_w - connect \sram4k_2__sel \sram4k_2__sel - connect \sram4k_2__stb \sram4k_2__stb - connect \sram4k_2__we \sram4k_2__we - connect \sram4k_3__ack \sram4k_3__ack - connect \sram4k_3__adr \sram4k_3__adr - connect \sram4k_3__cyc \sram4k_3__cyc - connect \sram4k_3__dat_r \sram4k_3__dat_r - connect \sram4k_3__dat_w \sram4k_3__dat_w - connect \sram4k_3__sel \sram4k_3__sel - connect \sram4k_3__stb \sram4k_3__stb - connect \sram4k_3__we \sram4k_3__we + connect \sram4k_0_wb__ack \sram4k_0_wb__ack + connect \sram4k_0_wb__adr \sram4k_0_wb__adr + connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc + connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r + connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w + connect \sram4k_0_wb__sel \sram4k_0_wb__sel + connect \sram4k_0_wb__stb \sram4k_0_wb__stb + connect \sram4k_0_wb__we \sram4k_0_wb__we + connect \sram4k_1_wb__ack \sram4k_1_wb__ack + connect \sram4k_1_wb__adr \sram4k_1_wb__adr + connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc + connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r + connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w + connect \sram4k_1_wb__sel \sram4k_1_wb__sel + connect \sram4k_1_wb__stb \sram4k_1_wb__stb + connect \sram4k_1_wb__we \sram4k_1_wb__we + connect \sram4k_2_wb__ack \sram4k_2_wb__ack + connect \sram4k_2_wb__adr \sram4k_2_wb__adr + connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc + connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r + connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w + connect \sram4k_2_wb__sel \sram4k_2_wb__sel + connect \sram4k_2_wb__stb \sram4k_2_wb__stb + connect \sram4k_2_wb__we \sram4k_2_wb__we + connect \sram4k_3_wb__ack \sram4k_3_wb__ack + connect \sram4k_3_wb__adr \sram4k_3_wb__adr + connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc + connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r + connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w + connect \sram4k_3_wb__sel \sram4k_3_wb__sel + connect \sram4k_3_wb__stb \sram4k_3_wb__stb + connect \sram4k_3_wb__we \sram4k_3_wb__we end connect \ti_coresync_clk \pll_clk_pll_o connect \pllclk_rst \rst @@ -411052,1904 +401881,2042 @@ module \test_issuer connect \pll_clk_24_i \clk connect \pllclk_clk \pll_clk_pll_o end -attribute \src "libresoc.v:198205.1-202906.10" +attribute \src "libresoc.v:192543.1-197394.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" module \ti - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $0\core_asmcode$next[7:0]$14161 - attribute \src "libresoc.v:200667.3-200668.41" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $0\core_asmcode$next[7:0]$13879 + attribute \src "libresoc.v:195029.3-195030.41" wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:201555.3-201584.6" - wire $0\core_bigendian_i$10$next[0:0]$13962 - attribute \src "libresoc.v:200797.3-200798.57" - wire $0\core_bigendian_i$10[0:0]$13886 - attribute \src "libresoc.v:198404.7-198404.35" - wire $0\core_bigendian_i$10[0:0]$14433 - attribute \src "libresoc.v:201984.3-201996.6" + attribute \src "libresoc.v:195942.3-195974.6" + wire $0\core_bigendian_i$10$next[0:0]$13668 + attribute \src "libresoc.v:195179.3-195180.57" + wire $0\core_bigendian_i$10[0:0]$13596 + attribute \src "libresoc.v:192724.7-192724.35" + wire $0\core_bigendian_i$10[0:0]$14204 + attribute \src "libresoc.v:196501.3-196513.6" wire width 3 $0\core_cia__ren[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 64 $0\core_core_core_cia$next[63:0]$14162 - attribute \src "libresoc.v:200741.3-200742.53" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 64 $0\core_core_core_cia$next[63:0]$13880 + attribute \src "libresoc.v:195103.3-195104.53" wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$14163 - attribute \src "libresoc.v:200785.3-200786.57" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$13881 + attribute \src "libresoc.v:195147.3-195148.57" wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$14164 - attribute \src "libresoc.v:200787.3-200788.63" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$13882 + attribute \src "libresoc.v:195149.3-195150.63" wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$14165 - attribute \src "libresoc.v:200789.3-200790.57" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$13883 + attribute \src "libresoc.v:195151.3-195152.57" wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_exc_$signal$3$next[0:0]$14166 - attribute \src "libresoc.v:200767.3-200768.75" - wire $0\core_core_core_exc_$signal$3[0:0]$13864 - attribute \src "libresoc.v:198430.7-198430.44" - wire $0\core_core_core_exc_$signal$3[0:0]$14441 - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_exc_$signal$4$next[0:0]$14167 - attribute \src "libresoc.v:200769.3-200770.75" - wire $0\core_core_core_exc_$signal$4[0:0]$13866 - attribute \src "libresoc.v:198434.7-198434.44" - wire $0\core_core_core_exc_$signal$4[0:0]$14443 - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_exc_$signal$5$next[0:0]$14168 - attribute \src "libresoc.v:200771.3-200772.75" - wire $0\core_core_core_exc_$signal$5[0:0]$13868 - attribute \src "libresoc.v:198438.7-198438.44" - wire $0\core_core_core_exc_$signal$5[0:0]$14445 - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_exc_$signal$6$next[0:0]$14169 - attribute \src "libresoc.v:200773.3-200774.75" - wire $0\core_core_core_exc_$signal$6[0:0]$13870 - attribute \src "libresoc.v:198442.7-198442.44" - wire $0\core_core_core_exc_$signal$6[0:0]$14447 - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_exc_$signal$7$next[0:0]$14170 - attribute \src "libresoc.v:200777.3-200778.75" - wire $0\core_core_core_exc_$signal$7[0:0]$13873 - attribute \src "libresoc.v:198446.7-198446.44" - wire $0\core_core_core_exc_$signal$7[0:0]$14449 - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_exc_$signal$8$next[0:0]$14171 - attribute \src "libresoc.v:200779.3-200780.75" - wire $0\core_core_core_exc_$signal$8[0:0]$13875 - attribute \src "libresoc.v:198450.7-198450.44" - wire $0\core_core_core_exc_$signal$8[0:0]$14451 - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_exc_$signal$9$next[0:0]$14172 - attribute \src "libresoc.v:200781.3-200782.75" - wire $0\core_core_core_exc_$signal$9[0:0]$13877 - attribute \src "libresoc.v:198454.7-198454.44" - wire $0\core_core_core_exc_$signal$9[0:0]$14453 - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_exc_$signal$next[0:0]$14173 - attribute \src "libresoc.v:200765.3-200766.71" - wire $0\core_core_core_exc_$signal[0:0]$13862 - attribute \src "libresoc.v:198428.7-198428.42" - wire $0\core_core_core_exc_$signal[0:0]$14439 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 13 $0\core_core_core_fn_unit$next[12:0]$14174 - attribute \src "libresoc.v:200747.3-200748.61" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$13884 + attribute \src "libresoc.v:195129.3-195130.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13564 + attribute \src "libresoc.v:192750.7-192750.44" + wire $0\core_core_core_exc_$signal$3[0:0]$14212 + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$13885 + attribute \src "libresoc.v:195131.3-195132.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13566 + attribute \src "libresoc.v:192754.7-192754.44" + wire $0\core_core_core_exc_$signal$4[0:0]$14214 + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$13886 + attribute \src "libresoc.v:195133.3-195134.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13568 + attribute \src "libresoc.v:192758.7-192758.44" + wire $0\core_core_core_exc_$signal$5[0:0]$14216 + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$13887 + attribute \src "libresoc.v:195137.3-195138.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13571 + attribute \src "libresoc.v:192762.7-192762.44" + wire $0\core_core_core_exc_$signal$6[0:0]$14218 + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$13888 + attribute \src "libresoc.v:195139.3-195140.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13573 + attribute \src "libresoc.v:192766.7-192766.44" + wire $0\core_core_core_exc_$signal$7[0:0]$14220 + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$13889 + attribute \src "libresoc.v:195141.3-195142.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13575 + attribute \src "libresoc.v:192770.7-192770.44" + wire $0\core_core_core_exc_$signal$8[0:0]$14222 + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$13890 + attribute \src "libresoc.v:195143.3-195144.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13577 + attribute \src "libresoc.v:192774.7-192774.44" + wire $0\core_core_core_exc_$signal$9[0:0]$14224 + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_exc_$signal$next[0:0]$13891 + attribute \src "libresoc.v:195127.3-195128.71" + wire $0\core_core_core_exc_$signal[0:0]$13562 + attribute \src "libresoc.v:192748.7-192748.42" + wire $0\core_core_core_exc_$signal[0:0]$14210 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 13 $0\core_core_core_fn_unit$next[12:0]$13892 + attribute \src "libresoc.v:195109.3-195110.61" wire width 13 $0\core_core_core_fn_unit[12:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$14175 - attribute \src "libresoc.v:200761.3-200762.69" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$13893 + attribute \src "libresoc.v:195123.3-195124.69" wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 32 $0\core_core_core_insn$next[31:0]$14176 - attribute \src "libresoc.v:200743.3-200744.55" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 32 $0\core_core_core_insn$next[31:0]$13894 + attribute \src "libresoc.v:195105.3-195106.55" wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$14177 - attribute \src "libresoc.v:200745.3-200746.65" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$13895 + attribute \src "libresoc.v:195107.3-195108.65" wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_is_32bit$next[0:0]$14178 - attribute \src "libresoc.v:200793.3-200794.63" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_is_32bit$next[0:0]$13896 + attribute \src "libresoc.v:195155.3-195156.63" wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 64 $0\core_core_core_msr$next[63:0]$14179 - attribute \src "libresoc.v:200739.3-200740.53" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 64 $0\core_core_core_msr$next[63:0]$13897 + attribute \src "libresoc.v:195101.3-195102.53" wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_oe$next[0:0]$14180 - attribute \src "libresoc.v:200757.3-200758.51" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_oe$next[0:0]$13898 + attribute \src "libresoc.v:195119.3-195120.51" wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_oe_ok$next[0:0]$14181 - attribute \src "libresoc.v:200759.3-200760.57" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_oe_ok$next[0:0]$13899 + attribute \src "libresoc.v:195121.3-195122.57" wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_rc$next[0:0]$14182 - attribute \src "libresoc.v:200751.3-200752.51" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_rc$next[0:0]$13900 + attribute \src "libresoc.v:195115.3-195116.51" wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_core_rc_ok$next[0:0]$14183 - attribute \src "libresoc.v:200755.3-200756.57" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_core_rc_ok$next[0:0]$13901 + attribute \src "libresoc.v:195117.3-195118.57" wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$14184 - attribute \src "libresoc.v:200783.3-200784.63" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$13902 + attribute \src "libresoc.v:195145.3-195146.63" wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $0\core_core_core_traptype$next[7:0]$14185 - attribute \src "libresoc.v:200763.3-200764.63" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$13903 + attribute \src "libresoc.v:195125.3-195126.63" wire width 8 $0\core_core_core_traptype[7:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $0\core_core_cr_in1$next[6:0]$14186 - attribute \src "libresoc.v:200721.3-200722.49" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$13904 + attribute \src "libresoc.v:195083.3-195084.49" wire width 7 $0\core_core_cr_in1[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_cr_in1_ok$next[0:0]$14187 - attribute \src "libresoc.v:200723.3-200724.55" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_cr_in1_ok$next[0:0]$13905 + attribute \src "libresoc.v:195085.3-195086.55" wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $0\core_core_cr_in2$1$next[6:0]$14188 - attribute \src "libresoc.v:200729.3-200730.55" - wire width 7 $0\core_core_cr_in2$1[6:0]$13842 - attribute \src "libresoc.v:198610.13-198610.41" - wire width 7 $0\core_core_cr_in2$1[6:0]$14470 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $0\core_core_cr_in2$next[6:0]$14189 - attribute \src "libresoc.v:200725.3-200726.49" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$13906 + attribute \src "libresoc.v:195093.3-195094.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13543 + attribute \src "libresoc.v:192930.13-192930.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$14241 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$13907 + attribute \src "libresoc.v:195087.3-195088.49" wire width 7 $0\core_core_cr_in2[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$14190 - attribute \src "libresoc.v:200733.3-200734.61" - wire $0\core_core_cr_in2_ok$2[0:0]$13845 - attribute \src "libresoc.v:198618.7-198618.37" - wire $0\core_core_cr_in2_ok$2[0:0]$14473 - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_cr_in2_ok$next[0:0]$14191 - attribute \src "libresoc.v:200727.3-200728.55" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$13908 + attribute \src "libresoc.v:195095.3-195096.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13545 + attribute \src "libresoc.v:192938.7-192938.37" + wire $0\core_core_cr_in2_ok$2[0:0]$14244 + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_cr_in2_ok$next[0:0]$13909 + attribute \src "libresoc.v:195089.3-195090.55" wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $0\core_core_cr_out$next[6:0]$14192 - attribute \src "libresoc.v:200735.3-200736.49" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $0\core_core_cr_out$next[6:0]$13910 + attribute \src "libresoc.v:195097.3-195098.49" wire width 7 $0\core_core_cr_out[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_cr_wr_ok$next[0:0]$14193 - attribute \src "libresoc.v:200791.3-200792.53" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_cr_wr_ok$next[0:0]$13911 + attribute \src "libresoc.v:195153.3-195154.53" wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $0\core_core_dststep$next[6:0]$13915 - attribute \src "libresoc.v:200657.3-200658.51" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $0\core_core_dststep$next[6:0]$13620 + attribute \src "libresoc.v:195019.3-195020.51" wire width 7 $0\core_core_dststep[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $0\core_core_ea$next[6:0]$14194 - attribute \src "libresoc.v:200673.3-200674.41" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $0\core_core_ea$next[6:0]$13912 + attribute \src "libresoc.v:195035.3-195036.41" wire width 7 $0\core_core_ea[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $0\core_core_fast1$next[2:0]$14195 - attribute \src "libresoc.v:200703.3-200704.47" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $0\core_core_fast1$next[2:0]$13913 + attribute \src "libresoc.v:195065.3-195066.47" wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_fast1_ok$next[0:0]$14196 - attribute \src "libresoc.v:200705.3-200706.53" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_fast1_ok$next[0:0]$13914 + attribute \src "libresoc.v:195067.3-195068.53" wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $0\core_core_fast2$next[2:0]$14197 - attribute \src "libresoc.v:200707.3-200708.47" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $0\core_core_fast2$next[2:0]$13915 + attribute \src "libresoc.v:195071.3-195072.47" wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_fast2_ok$next[0:0]$14198 - attribute \src "libresoc.v:200711.3-200712.53" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_fast2_ok$next[0:0]$13916 + attribute \src "libresoc.v:195073.3-195074.53" wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $0\core_core_fasto1$next[2:0]$14199 - attribute \src "libresoc.v:200713.3-200714.49" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $0\core_core_fasto1$next[2:0]$13917 + attribute \src "libresoc.v:195075.3-195076.49" wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $0\core_core_fasto2$next[2:0]$14200 - attribute \src "libresoc.v:200717.3-200718.49" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $0\core_core_fasto2$next[2:0]$13918 + attribute \src "libresoc.v:195079.3-195080.49" wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_lk$next[0:0]$14201 - attribute \src "libresoc.v:200749.3-200750.41" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_lk$next[0:0]$13919 + attribute \src "libresoc.v:195111.3-195112.41" wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $0\core_core_maxvl$next[6:0]$13916 - attribute \src "libresoc.v:200663.3-200664.47" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13621 + attribute \src "libresoc.v:195027.3-195028.47" wire width 7 $0\core_core_maxvl[6:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $0\core_core_pc$next[63:0]$13917 - attribute \src "libresoc.v:200625.3-200626.41" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $0\core_core_pc$next[63:0]$13622 + attribute \src "libresoc.v:195005.3-195006.41" wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $0\core_core_reg1$next[6:0]$14202 - attribute \src "libresoc.v:200677.3-200678.45" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $0\core_core_reg1$next[6:0]$13920 + attribute \src "libresoc.v:195039.3-195040.45" wire width 7 $0\core_core_reg1[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_reg1_ok$next[0:0]$14203 - attribute \src "libresoc.v:200679.3-200680.51" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_reg1_ok$next[0:0]$13921 + attribute \src "libresoc.v:195041.3-195042.51" wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $0\core_core_reg2$next[6:0]$14204 - attribute \src "libresoc.v:200681.3-200682.45" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $0\core_core_reg2$next[6:0]$13922 + attribute \src "libresoc.v:195043.3-195044.45" wire width 7 $0\core_core_reg2[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_reg2_ok$next[0:0]$14205 - attribute \src "libresoc.v:200683.3-200684.51" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_reg2_ok$next[0:0]$13923 + attribute \src "libresoc.v:195045.3-195046.51" wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $0\core_core_reg3$next[6:0]$14206 - attribute \src "libresoc.v:200685.3-200686.45" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $0\core_core_reg3$next[6:0]$13924 + attribute \src "libresoc.v:195049.3-195050.45" wire width 7 $0\core_core_reg3[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_reg3_ok$next[0:0]$14207 - attribute \src "libresoc.v:200689.3-200690.51" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_reg3_ok$next[0:0]$13925 + attribute \src "libresoc.v:195051.3-195052.51" wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $0\core_core_rego$next[6:0]$14208 - attribute \src "libresoc.v:200669.3-200670.45" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $0\core_core_rego$next[6:0]$13926 + attribute \src "libresoc.v:195031.3-195032.45" wire width 7 $0\core_core_rego[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 10 $0\core_core_spr1$next[9:0]$14209 - attribute \src "libresoc.v:200695.3-200696.45" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 10 $0\core_core_spr1$next[9:0]$13927 + attribute \src "libresoc.v:195057.3-195058.45" wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_core_spr1_ok$next[0:0]$14210 - attribute \src "libresoc.v:200697.3-200698.51" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_core_spr1_ok$next[0:0]$13928 + attribute \src "libresoc.v:195059.3-195060.51" wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 10 $0\core_core_spro$next[9:0]$14211 - attribute \src "libresoc.v:200691.3-200692.45" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 10 $0\core_core_spro$next[9:0]$13929 + attribute \src "libresoc.v:195053.3-195054.45" wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $0\core_core_srcstep$next[6:0]$13918 - attribute \src "libresoc.v:200659.3-200660.51" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13623 + attribute \src "libresoc.v:195021.3-195022.51" wire width 7 $0\core_core_srcstep[6:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 2 $0\core_core_subvl$next[1:0]$13919 - attribute \src "libresoc.v:200655.3-200656.47" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 2 $0\core_core_subvl$next[1:0]$13624 + attribute \src "libresoc.v:195017.3-195018.47" wire width 2 $0\core_core_subvl[1:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 2 $0\core_core_svstep$next[1:0]$13920 - attribute \src "libresoc.v:200653.3-200654.49" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 2 $0\core_core_svstep$next[1:0]$13625 + attribute \src "libresoc.v:195015.3-195016.49" wire width 2 $0\core_core_svstep[1:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $0\core_core_vl$next[6:0]$13921 - attribute \src "libresoc.v:200661.3-200662.41" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $0\core_core_vl$next[6:0]$13626 + attribute \src "libresoc.v:195023.3-195024.41" wire width 7 $0\core_core_vl[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $0\core_core_xer_in$next[2:0]$14212 - attribute \src "libresoc.v:200699.3-200700.49" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $0\core_core_xer_in$next[2:0]$13930 + attribute \src "libresoc.v:195061.3-195062.49" wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_cr_out_ok$next[0:0]$14213 - attribute \src "libresoc.v:200737.3-200738.45" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_cr_out_ok$next[0:0]$13931 + attribute \src "libresoc.v:195099.3-195100.45" wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:201672.3-201681.6" - wire width 64 $0\core_data_i$12[63:0]$13983 - attribute \src "libresoc.v:202018.3-202038.6" + attribute \src "libresoc.v:196012.3-196021.6" + wire width 64 $0\core_data_i$12[63:0]$13680 + attribute \src "libresoc.v:196587.3-196612.6" wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $0\core_dec$next[63:0]$13922 - attribute \src "libresoc.v:200651.3-200652.33" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $0\core_dec$next[63:0]$13627 + attribute \src "libresoc.v:195013.3-195014.33" wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:201682.3-201691.6" + attribute \src "libresoc.v:196199.3-196208.6" wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:201692.3-201701.6" + attribute \src "libresoc.v:196209.3-196218.6" wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_ea_ok$next[0:0]$14214 - attribute \src "libresoc.v:200675.3-200676.37" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_ea_ok$next[0:0]$13932 + attribute \src "libresoc.v:195037.3-195038.37" wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire $0\core_eint$next[0:0]$13923 - attribute \src "libresoc.v:200649.3-200650.35" + attribute \src "libresoc.v:195868.3-195908.6" + wire $0\core_eint$next[0:0]$13628 + attribute \src "libresoc.v:195011.3-195012.35" wire $0\core_eint[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_fasto1_ok$next[0:0]$14215 - attribute \src "libresoc.v:200715.3-200716.45" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_fasto1_ok$next[0:0]$13933 + attribute \src "libresoc.v:195077.3-195078.45" wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_fasto2_ok$next[0:0]$14216 - attribute \src "libresoc.v:200719.3-200720.45" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_fasto2_ok$next[0:0]$13934 + attribute \src "libresoc.v:195081.3-195082.45" wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:201731.3-201740.6" + attribute \src "libresoc.v:196248.3-196257.6" wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:201770.3-201779.6" + attribute \src "libresoc.v:196287.3-196296.6" wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:201878.3-201892.6" - wire width 3 $0\core_issue__addr$13[2:0]$14012 - attribute \src "libresoc.v:201809.3-201823.6" + attribute \src "libresoc.v:196395.3-196409.6" + wire width 3 $0\core_issue__addr$13[2:0]$13733 + attribute \src "libresoc.v:196326.3-196340.6" wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:201908.3-201922.6" + attribute \src "libresoc.v:196425.3-196439.6" wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:201824.3-201838.6" + attribute \src "libresoc.v:196341.3-196355.6" wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:201893.3-201907.6" + attribute \src "libresoc.v:196410.3-196424.6" wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:201626.3-201636.6" + attribute \src "libresoc.v:196058.3-196073.6" wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:201606.3-201625.6" + attribute \src "libresoc.v:196033.3-196057.6" wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $0\core_msr$next[63:0]$13924 - attribute \src "libresoc.v:200647.3-200648.33" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $0\core_msr$next[63:0]$13629 + attribute \src "libresoc.v:195009.3-195010.33" wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:202060.3-202080.6" + attribute \src "libresoc.v:196613.3-196628.6" wire width 3 $0\core_msr__ren[2:0] - attribute \src "libresoc.v:201525.3-201554.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13956 - attribute \src "libresoc.v:200819.3-200820.47" + attribute \src "libresoc.v:195909.3-195941.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13661 + attribute \src "libresoc.v:194983.3-194984.47" wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_rego_ok$next[0:0]$14217 - attribute \src "libresoc.v:200671.3-200672.41" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_rego_ok$next[0:0]$13935 + attribute \src "libresoc.v:195033.3-195034.41" wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_spro_ok$next[0:0]$14218 - attribute \src "libresoc.v:200693.3-200694.41" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_spro_ok$next[0:0]$13936 + attribute \src "libresoc.v:195055.3-195056.41" wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:202410.3-202428.6" + attribute \src "libresoc.v:197161.3-197191.6" wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:202039.3-202059.6" + attribute \src "libresoc.v:196539.3-196551.6" wire width 3 $0\core_sv__ren[2:0] - attribute \src "libresoc.v:201662.3-201671.6" - wire width 3 $0\core_wen$11[2:0]$13980 - attribute \src "libresoc.v:201997.3-202017.6" + attribute \src "libresoc.v:196002.3-196011.6" + wire width 3 $0\core_wen$11[2:0]$13677 + attribute \src "libresoc.v:196561.3-196586.6" wire width 3 $0\core_wen[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $0\core_xer_out$next[0:0]$14219 - attribute \src "libresoc.v:200701.3-200702.41" + attribute \src "libresoc.v:197245.3-197363.6" + wire $0\core_xer_out$next[0:0]$13937 + attribute \src "libresoc.v:195063.3-195064.41" wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:200629.3-200630.43" + attribute \src "libresoc.v:194989.3-194990.43" wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $0\cur_cur_dststep$next[6:0]$14081 - attribute \src "libresoc.v:200823.3-200824.47" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$13774 + attribute \src "libresoc.v:195189.3-195190.47" wire width 7 $0\cur_cur_dststep[6:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $0\cur_cur_maxvl$next[6:0]$14082 - attribute \src "libresoc.v:200829.3-200830.43" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$13775 + attribute \src "libresoc.v:195195.3-195196.43" wire width 7 $0\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 2 $0\cur_cur_subvl$next[1:0]$14083 - attribute \src "libresoc.v:200821.3-200822.43" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$13776 + attribute \src "libresoc.v:195187.3-195188.43" wire width 2 $0\cur_cur_subvl[1:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 2 $0\cur_cur_svstep$next[1:0]$14084 - attribute \src "libresoc.v:200817.3-200818.45" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$13777 + attribute \src "libresoc.v:195185.3-195186.45" wire width 2 $0\cur_cur_svstep[1:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $0\cur_cur_vl$next[6:0]$14085 - attribute \src "libresoc.v:200827.3-200828.37" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $0\cur_cur_vl$next[6:0]$13778 + attribute \src "libresoc.v:195193.3-195194.37" wire width 7 $0\cur_cur_vl[6:0] - attribute \src "libresoc.v:201741.3-201749.6" - wire $0\d_cr_delay$next[0:0]$13994 - attribute \src "libresoc.v:200709.3-200710.37" + attribute \src "libresoc.v:196258.3-196266.6" + wire $0\d_cr_delay$next[0:0]$13715 + attribute \src "libresoc.v:195069.3-195070.37" wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:201702.3-201710.6" - wire $0\d_reg_delay$next[0:0]$13988 - attribute \src "libresoc.v:200731.3-200732.39" + attribute \src "libresoc.v:196219.3-196227.6" + wire $0\d_reg_delay$next[0:0]$13709 + attribute \src "libresoc.v:195091.3-195092.39" wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:201780.3-201788.6" - wire $0\d_xer_delay$next[0:0]$14000 - attribute \src "libresoc.v:200687.3-200688.39" + attribute \src "libresoc.v:196297.3-196305.6" + wire $0\d_xer_delay$next[0:0]$13721 + attribute \src "libresoc.v:195047.3-195048.39" wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:202429.3-202447.6" + attribute \src "libresoc.v:197192.3-197222.6" wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:201760.3-201769.6" + attribute \src "libresoc.v:196277.3-196286.6" wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:201750.3-201759.6" + attribute \src "libresoc.v:196267.3-196276.6" wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:201721.3-201730.6" + attribute \src "libresoc.v:196238.3-196247.6" wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:201711.3-201720.6" + attribute \src "libresoc.v:196228.3-196237.6" wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:201799.3-201808.6" + attribute \src "libresoc.v:196316.3-196325.6" wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:201789.3-201798.6" + attribute \src "libresoc.v:196306.3-196315.6" wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:201466.3-201474.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13909 - attribute \src "libresoc.v:200645.3-200646.45" + attribute \src "libresoc.v:195831.3-195839.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13608 + attribute \src "libresoc.v:195007.3-195008.45" wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:202081.3-202089.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$14034 - attribute \src "libresoc.v:200639.3-200640.39" + attribute \src "libresoc.v:196552.3-196560.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13756 + attribute \src "libresoc.v:194999.3-195000.39" wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:201475.3-201483.6" - wire $0\dbg_dmi_req_i$next[0:0]$13912 - attribute \src "libresoc.v:200643.3-200644.43" + attribute \src "libresoc.v:195840.3-195848.6" + wire $0\dbg_dmi_req_i$next[0:0]$13611 + attribute \src "libresoc.v:195003.3-195004.43" wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:201950.3-201958.6" - wire $0\dbg_dmi_we_i$next[0:0]$14022 - attribute \src "libresoc.v:200641.3-200642.41" + attribute \src "libresoc.v:196467.3-196475.6" + wire $0\dbg_dmi_we_i$next[0:0]$13743 + attribute \src "libresoc.v:195001.3-195002.41" wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $0\dec2_cur_cur_srcstep$next[6:0]$14086 - attribute \src "libresoc.v:200825.3-200826.57" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $0\dec2_cur_cur_srcstep$next[6:0]$13779 + attribute \src "libresoc.v:195191.3-195192.57" wire width 7 $0\dec2_cur_cur_srcstep[6:0] - attribute \src "libresoc.v:201923.3-201938.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$14017 - attribute \src "libresoc.v:200623.3-200624.41" + attribute \src "libresoc.v:196440.3-196455.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13738 + attribute \src "libresoc.v:194981.3-194982.41" wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:202859.3-202867.6" - wire $0\dec2_cur_eint$next[0:0]$14425 - attribute \src "libresoc.v:200633.3-200634.43" + attribute \src "libresoc.v:195849.3-195857.6" + wire $0\dec2_cur_eint$next[0:0]$13614 + attribute \src "libresoc.v:194993.3-194994.43" wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:202457.3-202477.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$14076 - attribute \src "libresoc.v:200831.3-200832.41" + attribute \src "libresoc.v:196936.3-196956.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13823 + attribute \src "libresoc.v:195177.3-195178.41" wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:202247.3-202272.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$14041 - attribute \src "libresoc.v:200839.3-200840.39" + attribute \src "libresoc.v:196775.3-196795.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13769 + attribute \src "libresoc.v:195197.3-195198.39" wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 9 $0\dec2_dec_svp64__extra$next[8:0]$14108 - attribute \src "libresoc.v:200805.3-200806.59" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 9 $0\dec2_dec_svp64__extra$next[8:0]$13830 + attribute \src "libresoc.v:195165.3-195166.59" wire width 9 $0\dec2_dec_svp64__extra[8:0] - attribute \src "libresoc.v:202727.3-202742.6" + attribute \src "libresoc.v:195199.3-195200.40" wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $0\dec_svp64__elwidth$next[1:0]$14109 - attribute \src "libresoc.v:200811.3-200812.53" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $0\dec_svp64__elwidth$next[1:0]$13831 + attribute \src "libresoc.v:195171.3-195172.53" wire width 2 $0\dec_svp64__elwidth[1:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $0\dec_svp64__ewsrc$next[1:0]$14110 - attribute \src "libresoc.v:200809.3-200810.49" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $0\dec_svp64__ewsrc$next[1:0]$13832 + attribute \src "libresoc.v:195169.3-195170.49" wire width 2 $0\dec_svp64__ewsrc[1:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 3 $0\dec_svp64__mask$next[2:0]$14111 - attribute \src "libresoc.v:200813.3-200814.47" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 3 $0\dec_svp64__mask$next[2:0]$13833 + attribute \src "libresoc.v:195173.3-195174.47" wire width 3 $0\dec_svp64__mask[2:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire $0\dec_svp64__mmode$next[0:0]$14112 - attribute \src "libresoc.v:200815.3-200816.49" + attribute \src "libresoc.v:196995.3-197032.6" + wire $0\dec_svp64__mmode$next[0:0]$13834 + attribute \src "libresoc.v:195175.3-195176.49" wire $0\dec_svp64__mmode[0:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 5 $0\dec_svp64__mode$next[4:0]$14113 - attribute \src "libresoc.v:200803.3-200804.47" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 5 $0\dec_svp64__mode$next[4:0]$13835 + attribute \src "libresoc.v:195163.3-195164.47" wire width 5 $0\dec_svp64__mode[4:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $0\dec_svp64__subvl$next[1:0]$14114 - attribute \src "libresoc.v:200807.3-200808.49" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $0\dec_svp64__subvl$next[1:0]$13836 + attribute \src "libresoc.v:195167.3-195168.49" wire width 2 $0\dec_svp64__subvl[1:0] - attribute \src "libresoc.v:202868.3-202877.6" - wire width 2 $0\delay$next[1:0]$14428 - attribute \src "libresoc.v:200631.3-200632.27" + attribute \src "libresoc.v:195858.3-195867.6" + wire width 2 $0\delay$next[1:0]$13617 + attribute \src "libresoc.v:194991.3-194992.27" wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:202343.3-202409.6" - wire width 2 $0\fetch_fsm_state$next[1:0]$14061 - attribute \src "libresoc.v:200833.3-200834.47" + attribute \src "libresoc.v:196074.3-196108.6" + wire $0\exec_fsm_state$next[0:0]$13686 + attribute \src "libresoc.v:195157.3-195158.45" + wire $0\exec_fsm_state[0:0] + attribute \src "libresoc.v:196022.3-196032.6" + wire $0\exec_insn_ready_o[0:0] + attribute \src "libresoc.v:195975.3-195985.6" + wire $0\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:196183.3-196198.6" + wire $0\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:195986.3-196001.6" + wire $0\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:196874.3-196935.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$13814 + attribute \src "libresoc.v:195181.3-195182.47" wire width 2 $0\fetch_fsm_state[1:0] - attribute \src "libresoc.v:202615.3-202650.6" - wire width 32 $0\fetch_insn_o$next[31:0]$14144 - attribute \src "libresoc.v:200799.3-200800.41" + attribute \src "libresoc.v:197052.3-197087.6" wire width 32 $0\fetch_insn_o[31:0] - attribute \src "libresoc.v:202716.3-202726.6" + attribute \src "libresoc.v:197234.3-197244.6" wire $0\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:202651.3-202661.6" + attribute \src "libresoc.v:197088.3-197098.6" wire $0\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:202090.3-202105.6" + attribute \src "libresoc.v:196638.3-196648.6" wire $0\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:202662.3-202672.6" + attribute \src "libresoc.v:197223.3-197233.6" wire $0\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:201839.3-201866.6" - wire width 2 $0\fsm_state$188$next[1:0]$14007 - attribute \src "libresoc.v:200665.3-200666.45" - wire width 2 $0\fsm_state$188[1:0]$13809 - attribute \src "libresoc.v:199704.13-199704.35" - wire width 2 $0\fsm_state$188[1:0]$14543 - attribute \src "libresoc.v:202673.3-202715.6" - wire width 2 $0\fsm_state$next[1:0]$14152 - attribute \src "libresoc.v:200795.3-200796.35" + attribute \src "libresoc.v:196356.3-196383.6" + wire width 2 $0\fsm_state$next[1:0]$13728 + attribute \src "libresoc.v:195025.3-195026.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:201585.3-201605.6" - wire width 32 $0\ilatch$next[31:0]$13968 - attribute \src "libresoc.v:200775.3-200776.29" - wire width 32 $0\ilatch[31:0] - attribute \src "libresoc.v:202106.3-202146.6" + attribute \src "libresoc.v:196649.3-196684.6" wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:202147.3-202196.6" + attribute \src "libresoc.v:196685.3-196729.6" wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:202197.3-202246.6" + attribute \src "libresoc.v:196730.3-196774.6" wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198206.7-198206.20" + attribute \src "libresoc.v:192544.7-192544.20" wire $0\initial[0:0] - attribute \src "libresoc.v:202448.3-202456.6" - wire $0\jtag_dmi0__ack_o$next[0:0]$14073 - attribute \src "libresoc.v:200637.3-200638.49" + attribute \src "libresoc.v:196167.3-196182.6" + wire $0\insn_done[0:0] + attribute \src "libresoc.v:197099.3-197160.6" + wire width 3 $0\issue_fsm_state$next[2:0]$13865 + attribute \src "libresoc.v:195159.3-195160.47" + wire width 3 $0\issue_fsm_state[2:0] + attribute \src "libresoc.v:196629.3-196637.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13762 + attribute \src "libresoc.v:194997.3-194998.49" wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:202587.3-202595.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$14137 - attribute \src "libresoc.v:200635.3-200636.47" + attribute \src "libresoc.v:196835.3-196843.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13805 + attribute \src "libresoc.v:194995.3-194996.47" wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:202273.3-202307.6" - wire $0\msr_read$next[0:0]$14047 - attribute \src "libresoc.v:200837.3-200838.33" + attribute \src "libresoc.v:196844.3-196873.6" + wire $0\msr_read$next[0:0]$13808 + attribute \src "libresoc.v:195183.3-195184.33" wire $0\msr_read[0:0] - attribute \src "libresoc.v:201867.3-201877.6" + attribute \src "libresoc.v:196384.3-196394.6" wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:201939.3-201949.6" + attribute \src "libresoc.v:196456.3-196466.6" wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:202596.3-202614.6" - wire width 64 $0\nia$next[63:0]$14140 - attribute \src "libresoc.v:200801.3-200802.23" + attribute \src "libresoc.v:197033.3-197051.6" + wire width 64 $0\nia$next[63:0]$13859 + attribute \src "libresoc.v:195161.3-195162.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:201968.3-201983.6" + attribute \src "libresoc.v:196485.3-196500.6" wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:201637.3-201661.6" - wire $0\pc_changed$next[0:0]$13975 - attribute \src "libresoc.v:200753.3-200754.37" + attribute \src "libresoc.v:196138.3-196166.6" + wire $0\pc_changed$next[0:0]$13699 + attribute \src "libresoc.v:195113.3-195114.37" wire $0\pc_changed[0:0] - attribute \src "libresoc.v:201959.3-201967.6" - wire $0\pc_ok_delay$next[0:0]$14025 - attribute \src "libresoc.v:200627.3-200628.39" + attribute \src "libresoc.v:196476.3-196484.6" + wire $0\pc_ok_delay$next[0:0]$13746 + attribute \src "libresoc.v:194987.3-194988.39" wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:202308.3-202342.6" - wire $0\sv_read$next[0:0]$14054 - attribute \src "libresoc.v:200835.3-200836.31" - wire $0\sv_read[0:0] - attribute \src "libresoc.v:202530.3-202548.6" + attribute \src "libresoc.v:196109.3-196137.6" + wire $0\sv_changed$next[0:0]$13693 + attribute \src "libresoc.v:195135.3-195136.37" + wire $0\sv_changed[0:0] + attribute \src "libresoc.v:196976.3-196994.6" wire $0\svp64_bigendian[0:0] - attribute \src "libresoc.v:202511.3-202529.6" + attribute \src "libresoc.v:196957.3-196975.6" wire width 32 $0\svp64_raw_opcode_in[31:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $1\core_asmcode$next[7:0]$14220 - attribute \src "libresoc.v:198398.13-198398.33" + attribute \src "libresoc.v:196523.3-196538.6" + wire width 64 $0\svstate[63:0] + attribute \src "libresoc.v:196514.3-196522.6" + wire $0\svstate_ok_delay$next[0:0]$13751 + attribute \src "libresoc.v:194985.3-194986.49" + wire $0\svstate_ok_delay[0:0] + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $1\core_asmcode$next[7:0]$13938 + attribute \src "libresoc.v:192718.13-192718.33" wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:201555.3-201584.6" - wire $1\core_bigendian_i$10$next[0:0]$13963 - attribute \src "libresoc.v:201984.3-201996.6" + attribute \src "libresoc.v:195942.3-195974.6" + wire $1\core_bigendian_i$10$next[0:0]$13669 + attribute \src "libresoc.v:196501.3-196513.6" wire width 3 $1\core_cia__ren[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 64 $1\core_core_core_cia$next[63:0]$14221 - attribute \src "libresoc.v:198412.14-198412.55" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 64 $1\core_core_core_cia$next[63:0]$13939 + attribute \src "libresoc.v:192732.14-192732.55" wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$14222 - attribute \src "libresoc.v:198416.13-198416.41" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$13940 + attribute \src "libresoc.v:192736.13-192736.41" wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$14223 - attribute \src "libresoc.v:198420.7-198420.37" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$13941 + attribute \src "libresoc.v:192740.7-192740.37" wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$14224 - attribute \src "libresoc.v:198424.13-198424.41" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$13942 + attribute \src "libresoc.v:192744.13-192744.41" wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_exc_$signal$3$next[0:0]$14225 - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_exc_$signal$4$next[0:0]$14226 - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_exc_$signal$5$next[0:0]$14227 - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_exc_$signal$6$next[0:0]$14228 - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_exc_$signal$7$next[0:0]$14229 - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_exc_$signal$8$next[0:0]$14230 - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_exc_$signal$9$next[0:0]$14231 - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_exc_$signal$next[0:0]$14232 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 13 $1\core_core_core_fn_unit$next[12:0]$14233 - attribute \src "libresoc.v:198474.14-198474.47" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$13943 + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$13944 + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$13945 + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$13946 + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$13947 + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$13948 + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$13949 + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_exc_$signal$next[0:0]$13950 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 13 $1\core_core_core_fn_unit$next[12:0]$13951 + attribute \src "libresoc.v:192794.14-192794.47" wire width 13 $1\core_core_core_fn_unit[12:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$14234 - attribute \src "libresoc.v:198482.13-198482.46" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$13952 + attribute \src "libresoc.v:192802.13-192802.46" wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 32 $1\core_core_core_insn$next[31:0]$14235 - attribute \src "libresoc.v:198486.14-198486.41" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 32 $1\core_core_core_insn$next[31:0]$13953 + attribute \src "libresoc.v:192806.14-192806.41" wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$14236 - attribute \src "libresoc.v:198564.13-198564.45" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$13954 + attribute \src "libresoc.v:192884.13-192884.45" wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_is_32bit$next[0:0]$14237 - attribute \src "libresoc.v:198568.7-198568.37" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_is_32bit$next[0:0]$13955 + attribute \src "libresoc.v:192888.7-192888.37" wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 64 $1\core_core_core_msr$next[63:0]$14238 - attribute \src "libresoc.v:198572.14-198572.55" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 64 $1\core_core_core_msr$next[63:0]$13956 + attribute \src "libresoc.v:192892.14-192892.55" wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_oe$next[0:0]$14239 - attribute \src "libresoc.v:198576.7-198576.31" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_oe$next[0:0]$13957 + attribute \src "libresoc.v:192896.7-192896.31" wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_oe_ok$next[0:0]$14240 - attribute \src "libresoc.v:198580.7-198580.34" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_oe_ok$next[0:0]$13958 + attribute \src "libresoc.v:192900.7-192900.34" wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_rc$next[0:0]$14241 - attribute \src "libresoc.v:198584.7-198584.31" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_rc$next[0:0]$13959 + attribute \src "libresoc.v:192904.7-192904.31" wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_core_rc_ok$next[0:0]$14242 - attribute \src "libresoc.v:198588.7-198588.34" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_core_rc_ok$next[0:0]$13960 + attribute \src "libresoc.v:192908.7-192908.34" wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$14243 - attribute \src "libresoc.v:198592.14-198592.48" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$13961 + attribute \src "libresoc.v:192912.14-192912.48" wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $1\core_core_core_traptype$next[7:0]$14244 - attribute \src "libresoc.v:198596.13-198596.44" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$13962 + attribute \src "libresoc.v:192916.13-192916.44" wire width 8 $1\core_core_core_traptype[7:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $1\core_core_cr_in1$next[6:0]$14245 - attribute \src "libresoc.v:198600.13-198600.37" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$13963 + attribute \src "libresoc.v:192920.13-192920.37" wire width 7 $1\core_core_cr_in1[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_cr_in1_ok$next[0:0]$14246 - attribute \src "libresoc.v:198604.7-198604.33" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_cr_in1_ok$next[0:0]$13964 + attribute \src "libresoc.v:192924.7-192924.33" wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $1\core_core_cr_in2$1$next[6:0]$14247 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $1\core_core_cr_in2$next[6:0]$14248 - attribute \src "libresoc.v:198608.13-198608.37" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$13965 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$13966 + attribute \src "libresoc.v:192928.13-192928.37" wire width 7 $1\core_core_cr_in2[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$14249 - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_cr_in2_ok$next[0:0]$14250 - attribute \src "libresoc.v:198616.7-198616.33" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$13967 + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_cr_in2_ok$next[0:0]$13968 + attribute \src "libresoc.v:192936.7-192936.33" wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $1\core_core_cr_out$next[6:0]$14251 - attribute \src "libresoc.v:198624.13-198624.37" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $1\core_core_cr_out$next[6:0]$13969 + attribute \src "libresoc.v:192944.13-192944.37" wire width 7 $1\core_core_cr_out[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_cr_wr_ok$next[0:0]$14252 - attribute \src "libresoc.v:198628.7-198628.32" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_cr_wr_ok$next[0:0]$13970 + attribute \src "libresoc.v:192948.7-192948.32" wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $1\core_core_dststep$next[6:0]$13925 - attribute \src "libresoc.v:198632.13-198632.38" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $1\core_core_dststep$next[6:0]$13630 + attribute \src "libresoc.v:192952.13-192952.38" wire width 7 $1\core_core_dststep[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $1\core_core_ea$next[6:0]$14253 - attribute \src "libresoc.v:198636.13-198636.33" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $1\core_core_ea$next[6:0]$13971 + attribute \src "libresoc.v:192956.13-192956.33" wire width 7 $1\core_core_ea[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $1\core_core_fast1$next[2:0]$14254 - attribute \src "libresoc.v:198640.13-198640.35" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $1\core_core_fast1$next[2:0]$13972 + attribute \src "libresoc.v:192960.13-192960.35" wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_fast1_ok$next[0:0]$14255 - attribute \src "libresoc.v:198644.7-198644.32" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_fast1_ok$next[0:0]$13973 + attribute \src "libresoc.v:192964.7-192964.32" wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $1\core_core_fast2$next[2:0]$14256 - attribute \src "libresoc.v:198648.13-198648.35" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $1\core_core_fast2$next[2:0]$13974 + attribute \src "libresoc.v:192968.13-192968.35" wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_fast2_ok$next[0:0]$14257 - attribute \src "libresoc.v:198652.7-198652.32" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_fast2_ok$next[0:0]$13975 + attribute \src "libresoc.v:192972.7-192972.32" wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $1\core_core_fasto1$next[2:0]$14258 - attribute \src "libresoc.v:198656.13-198656.36" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $1\core_core_fasto1$next[2:0]$13976 + attribute \src "libresoc.v:192976.13-192976.36" wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $1\core_core_fasto2$next[2:0]$14259 - attribute \src "libresoc.v:198660.13-198660.36" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $1\core_core_fasto2$next[2:0]$13977 + attribute \src "libresoc.v:192980.13-192980.36" wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_lk$next[0:0]$14260 - attribute \src "libresoc.v:198664.7-198664.26" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_lk$next[0:0]$13978 + attribute \src "libresoc.v:192984.7-192984.26" wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $1\core_core_maxvl$next[6:0]$13926 - attribute \src "libresoc.v:198668.13-198668.36" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13631 + attribute \src "libresoc.v:192988.13-192988.36" wire width 7 $1\core_core_maxvl[6:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $1\core_core_pc$next[63:0]$13927 - attribute \src "libresoc.v:198672.14-198672.49" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $1\core_core_pc$next[63:0]$13632 + attribute \src "libresoc.v:192992.14-192992.49" wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $1\core_core_reg1$next[6:0]$14261 - attribute \src "libresoc.v:198676.13-198676.35" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $1\core_core_reg1$next[6:0]$13979 + attribute \src "libresoc.v:192996.13-192996.35" wire width 7 $1\core_core_reg1[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_reg1_ok$next[0:0]$14262 - attribute \src "libresoc.v:198680.7-198680.31" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_reg1_ok$next[0:0]$13980 + attribute \src "libresoc.v:193000.7-193000.31" wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $1\core_core_reg2$next[6:0]$14263 - attribute \src "libresoc.v:198684.13-198684.35" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $1\core_core_reg2$next[6:0]$13981 + attribute \src "libresoc.v:193004.13-193004.35" wire width 7 $1\core_core_reg2[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_reg2_ok$next[0:0]$14264 - attribute \src "libresoc.v:198688.7-198688.31" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_reg2_ok$next[0:0]$13982 + attribute \src "libresoc.v:193008.7-193008.31" wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $1\core_core_reg3$next[6:0]$14265 - attribute \src "libresoc.v:198692.13-198692.35" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $1\core_core_reg3$next[6:0]$13983 + attribute \src "libresoc.v:193012.13-193012.35" wire width 7 $1\core_core_reg3[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_reg3_ok$next[0:0]$14266 - attribute \src "libresoc.v:198696.7-198696.31" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_reg3_ok$next[0:0]$13984 + attribute \src "libresoc.v:193016.7-193016.31" wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $1\core_core_rego$next[6:0]$14267 - attribute \src "libresoc.v:198700.13-198700.35" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $1\core_core_rego$next[6:0]$13985 + attribute \src "libresoc.v:193020.13-193020.35" wire width 7 $1\core_core_rego[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 10 $1\core_core_spr1$next[9:0]$14268 - attribute \src "libresoc.v:198817.13-198817.37" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 10 $1\core_core_spr1$next[9:0]$13986 + attribute \src "libresoc.v:193138.13-193138.37" wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_core_spr1_ok$next[0:0]$14269 - attribute \src "libresoc.v:198821.7-198821.31" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_core_spr1_ok$next[0:0]$13987 + attribute \src "libresoc.v:193142.7-193142.31" wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 10 $1\core_core_spro$next[9:0]$14270 - attribute \src "libresoc.v:198938.13-198938.37" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 10 $1\core_core_spro$next[9:0]$13988 + attribute \src "libresoc.v:193260.13-193260.37" wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $1\core_core_srcstep$next[6:0]$13928 - attribute \src "libresoc.v:198942.13-198942.38" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13633 + attribute \src "libresoc.v:193264.13-193264.38" wire width 7 $1\core_core_srcstep[6:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 2 $1\core_core_subvl$next[1:0]$13929 - attribute \src "libresoc.v:198946.13-198946.35" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 2 $1\core_core_subvl$next[1:0]$13634 + attribute \src "libresoc.v:193268.13-193268.35" wire width 2 $1\core_core_subvl[1:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 2 $1\core_core_svstep$next[1:0]$13930 - attribute \src "libresoc.v:198950.13-198950.36" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 2 $1\core_core_svstep$next[1:0]$13635 + attribute \src "libresoc.v:193272.13-193272.36" wire width 2 $1\core_core_svstep[1:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $1\core_core_vl$next[6:0]$13931 - attribute \src "libresoc.v:198956.13-198956.33" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $1\core_core_vl$next[6:0]$13636 + attribute \src "libresoc.v:193278.13-193278.33" wire width 7 $1\core_core_vl[6:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $1\core_core_xer_in$next[2:0]$14271 - attribute \src "libresoc.v:198960.13-198960.36" + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $1\core_core_xer_in$next[2:0]$13989 + attribute \src "libresoc.v:193282.13-193282.36" wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_cr_out_ok$next[0:0]$14272 - attribute \src "libresoc.v:198968.7-198968.28" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_cr_out_ok$next[0:0]$13990 + attribute \src "libresoc.v:193290.7-193290.28" wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:201672.3-201681.6" - wire width 64 $1\core_data_i$12[63:0]$13984 - attribute \src "libresoc.v:202018.3-202038.6" + attribute \src "libresoc.v:196012.3-196021.6" + wire width 64 $1\core_data_i$12[63:0]$13681 + attribute \src "libresoc.v:196587.3-196612.6" wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $1\core_dec$next[63:0]$13932 - attribute \src "libresoc.v:198984.14-198984.45" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $1\core_dec$next[63:0]$13637 + attribute \src "libresoc.v:193318.14-193318.45" wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:201682.3-201691.6" + attribute \src "libresoc.v:196199.3-196208.6" wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:201692.3-201701.6" + attribute \src "libresoc.v:196209.3-196218.6" wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_ea_ok$next[0:0]$14273 - attribute \src "libresoc.v:198994.7-198994.24" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_ea_ok$next[0:0]$13991 + attribute \src "libresoc.v:193328.7-193328.24" wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire $1\core_eint$next[0:0]$13933 - attribute \src "libresoc.v:198998.7-198998.23" + attribute \src "libresoc.v:195868.3-195908.6" + wire $1\core_eint$next[0:0]$13638 + attribute \src "libresoc.v:193332.7-193332.23" wire $1\core_eint[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_fasto1_ok$next[0:0]$14274 - attribute \src "libresoc.v:199002.7-199002.28" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_fasto1_ok$next[0:0]$13992 + attribute \src "libresoc.v:193336.7-193336.28" wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_fasto2_ok$next[0:0]$14275 - attribute \src "libresoc.v:199006.7-199006.28" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_fasto2_ok$next[0:0]$13993 + attribute \src "libresoc.v:193340.7-193340.28" wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:201731.3-201740.6" + attribute \src "libresoc.v:196248.3-196257.6" wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:201770.3-201779.6" + attribute \src "libresoc.v:196287.3-196296.6" wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:201878.3-201892.6" - wire width 3 $1\core_issue__addr$13[2:0]$14013 - attribute \src "libresoc.v:201809.3-201823.6" + attribute \src "libresoc.v:196395.3-196409.6" + wire width 3 $1\core_issue__addr$13[2:0]$13734 + attribute \src "libresoc.v:196326.3-196340.6" wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:201908.3-201922.6" + attribute \src "libresoc.v:196425.3-196439.6" wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:201824.3-201838.6" + attribute \src "libresoc.v:196341.3-196355.6" wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:201893.3-201907.6" + attribute \src "libresoc.v:196410.3-196424.6" wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:201626.3-201636.6" + attribute \src "libresoc.v:196058.3-196073.6" wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:201606.3-201625.6" + attribute \src "libresoc.v:196033.3-196057.6" wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $1\core_msr$next[63:0]$13934 - attribute \src "libresoc.v:199034.14-199034.45" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $1\core_msr$next[63:0]$13639 + attribute \src "libresoc.v:193368.14-193368.45" wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:202060.3-202080.6" + attribute \src "libresoc.v:196613.3-196628.6" wire width 3 $1\core_msr__ren[2:0] - attribute \src "libresoc.v:201525.3-201554.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13957 - attribute \src "libresoc.v:199042.14-199042.37" + attribute \src "libresoc.v:195909.3-195941.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13662 + attribute \src "libresoc.v:193376.14-193376.37" wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_rego_ok$next[0:0]$14276 - attribute \src "libresoc.v:199046.7-199046.26" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_rego_ok$next[0:0]$13994 + attribute \src "libresoc.v:193380.7-193380.26" wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_spro_ok$next[0:0]$14277 - attribute \src "libresoc.v:199050.7-199050.26" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_spro_ok$next[0:0]$13995 + attribute \src "libresoc.v:193384.7-193384.26" wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:202410.3-202428.6" + attribute \src "libresoc.v:197161.3-197191.6" wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:202039.3-202059.6" + attribute \src "libresoc.v:196539.3-196551.6" wire width 3 $1\core_sv__ren[2:0] - attribute \src "libresoc.v:201662.3-201671.6" - wire width 3 $1\core_wen$11[2:0]$13981 - attribute \src "libresoc.v:201997.3-202017.6" + attribute \src "libresoc.v:196002.3-196011.6" + wire width 3 $1\core_wen$11[2:0]$13678 + attribute \src "libresoc.v:196561.3-196586.6" wire width 3 $1\core_wen[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $1\core_xer_out$next[0:0]$14278 - attribute \src "libresoc.v:199068.7-199068.26" + attribute \src "libresoc.v:197245.3-197363.6" + wire $1\core_xer_out$next[0:0]$13996 + attribute \src "libresoc.v:193402.7-193402.26" wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:199074.7-199074.30" + attribute \src "libresoc.v:193408.7-193408.30" wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $1\cur_cur_dststep$next[6:0]$14087 - attribute \src "libresoc.v:199080.13-199080.36" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$13780 + attribute \src "libresoc.v:193414.13-193414.36" wire width 7 $1\cur_cur_dststep[6:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $1\cur_cur_maxvl$next[6:0]$14088 - attribute \src "libresoc.v:199084.13-199084.34" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$13781 + attribute \src "libresoc.v:193418.13-193418.34" wire width 7 $1\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 2 $1\cur_cur_subvl$next[1:0]$14089 - attribute \src "libresoc.v:199088.13-199088.33" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$13782 + attribute \src "libresoc.v:193422.13-193422.33" wire width 2 $1\cur_cur_subvl[1:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 2 $1\cur_cur_svstep$next[1:0]$14090 - attribute \src "libresoc.v:199092.13-199092.34" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$13783 + attribute \src "libresoc.v:193426.13-193426.34" wire width 2 $1\cur_cur_svstep[1:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $1\cur_cur_vl$next[6:0]$14091 - attribute \src "libresoc.v:199096.13-199096.31" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $1\cur_cur_vl$next[6:0]$13784 + attribute \src "libresoc.v:193430.13-193430.31" wire width 7 $1\cur_cur_vl[6:0] - attribute \src "libresoc.v:201741.3-201749.6" - wire $1\d_cr_delay$next[0:0]$13995 - attribute \src "libresoc.v:199100.7-199100.24" + attribute \src "libresoc.v:196258.3-196266.6" + wire $1\d_cr_delay$next[0:0]$13716 + attribute \src "libresoc.v:193434.7-193434.24" wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:201702.3-201710.6" - wire $1\d_reg_delay$next[0:0]$13989 - attribute \src "libresoc.v:199104.7-199104.25" + attribute \src "libresoc.v:196219.3-196227.6" + wire $1\d_reg_delay$next[0:0]$13710 + attribute \src "libresoc.v:193438.7-193438.25" wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:201780.3-201788.6" - wire $1\d_xer_delay$next[0:0]$14001 - attribute \src "libresoc.v:199108.7-199108.25" + attribute \src "libresoc.v:196297.3-196305.6" + wire $1\d_xer_delay$next[0:0]$13722 + attribute \src "libresoc.v:193442.7-193442.25" wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:202429.3-202447.6" + attribute \src "libresoc.v:197192.3-197222.6" wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:201760.3-201769.6" + attribute \src "libresoc.v:196277.3-196286.6" wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:201750.3-201759.6" + attribute \src "libresoc.v:196267.3-196276.6" wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:201721.3-201730.6" + attribute \src "libresoc.v:196238.3-196247.6" wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:201711.3-201720.6" + attribute \src "libresoc.v:196228.3-196237.6" wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:201799.3-201808.6" + attribute \src "libresoc.v:196316.3-196325.6" wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:201789.3-201798.6" + attribute \src "libresoc.v:196306.3-196315.6" wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:201466.3-201474.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13910 - attribute \src "libresoc.v:199144.13-199144.34" + attribute \src "libresoc.v:195831.3-195839.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13609 + attribute \src "libresoc.v:193478.13-193478.34" wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:202081.3-202089.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$14035 - attribute \src "libresoc.v:199148.14-199148.48" + attribute \src "libresoc.v:196552.3-196560.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13757 + attribute \src "libresoc.v:193482.14-193482.48" wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:201475.3-201483.6" - wire $1\dbg_dmi_req_i$next[0:0]$13913 - attribute \src "libresoc.v:199154.7-199154.27" + attribute \src "libresoc.v:195840.3-195848.6" + wire $1\dbg_dmi_req_i$next[0:0]$13612 + attribute \src "libresoc.v:193488.7-193488.27" wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:201950.3-201958.6" - wire $1\dbg_dmi_we_i$next[0:0]$14023 - attribute \src "libresoc.v:199158.7-199158.26" + attribute \src "libresoc.v:196467.3-196475.6" + wire $1\dbg_dmi_we_i$next[0:0]$13744 + attribute \src "libresoc.v:193492.7-193492.26" wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $1\dec2_cur_cur_srcstep$next[6:0]$14092 - attribute \src "libresoc.v:199212.13-199212.41" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $1\dec2_cur_cur_srcstep$next[6:0]$13785 + attribute \src "libresoc.v:193546.13-193546.41" wire width 7 $1\dec2_cur_cur_srcstep[6:0] - attribute \src "libresoc.v:201923.3-201938.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$14018 - attribute \src "libresoc.v:199216.14-199216.49" + attribute \src "libresoc.v:196440.3-196455.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13739 + attribute \src "libresoc.v:193550.14-193550.49" wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:202859.3-202867.6" - wire $1\dec2_cur_eint$next[0:0]$14426 - attribute \src "libresoc.v:199220.7-199220.27" + attribute \src "libresoc.v:195849.3-195857.6" + wire $1\dec2_cur_eint$next[0:0]$13615 + attribute \src "libresoc.v:193554.7-193554.27" wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:202457.3-202477.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$14077 - attribute \src "libresoc.v:199224.14-199224.49" + attribute \src "libresoc.v:196936.3-196956.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13824 + attribute \src "libresoc.v:193558.14-193558.49" wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:202247.3-202272.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$14042 - attribute \src "libresoc.v:199228.14-199228.48" + attribute \src "libresoc.v:196775.3-196795.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13770 + attribute \src "libresoc.v:193562.14-193562.48" wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 9 $1\dec2_dec_svp64__extra$next[8:0]$14115 - attribute \src "libresoc.v:199232.13-199232.43" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 9 $1\dec2_dec_svp64__extra$next[8:0]$13837 + attribute \src "libresoc.v:193566.13-193566.43" wire width 9 $1\dec2_dec_svp64__extra[8:0] - attribute \src "libresoc.v:202727.3-202742.6" + attribute \src "libresoc.v:193716.14-193716.40" wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $1\dec_svp64__elwidth$next[1:0]$14116 - attribute \src "libresoc.v:199646.13-199646.38" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $1\dec_svp64__elwidth$next[1:0]$13838 + attribute \src "libresoc.v:193984.13-193984.38" wire width 2 $1\dec_svp64__elwidth[1:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $1\dec_svp64__ewsrc$next[1:0]$14117 - attribute \src "libresoc.v:199650.13-199650.36" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $1\dec_svp64__ewsrc$next[1:0]$13839 + attribute \src "libresoc.v:193988.13-193988.36" wire width 2 $1\dec_svp64__ewsrc[1:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 3 $1\dec_svp64__mask$next[2:0]$14118 - attribute \src "libresoc.v:199654.13-199654.35" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 3 $1\dec_svp64__mask$next[2:0]$13840 + attribute \src "libresoc.v:193992.13-193992.35" wire width 3 $1\dec_svp64__mask[2:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire $1\dec_svp64__mmode$next[0:0]$14119 - attribute \src "libresoc.v:199658.7-199658.30" + attribute \src "libresoc.v:196995.3-197032.6" + wire $1\dec_svp64__mmode$next[0:0]$13841 + attribute \src "libresoc.v:193996.7-193996.30" wire $1\dec_svp64__mmode[0:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 5 $1\dec_svp64__mode$next[4:0]$14120 - attribute \src "libresoc.v:199662.13-199662.36" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 5 $1\dec_svp64__mode$next[4:0]$13842 + attribute \src "libresoc.v:194000.13-194000.36" wire width 5 $1\dec_svp64__mode[4:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $1\dec_svp64__subvl$next[1:0]$14121 - attribute \src "libresoc.v:199666.13-199666.36" + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $1\dec_svp64__subvl$next[1:0]$13843 + attribute \src "libresoc.v:194004.13-194004.36" wire width 2 $1\dec_svp64__subvl[1:0] - attribute \src "libresoc.v:202868.3-202877.6" - wire width 2 $1\delay$next[1:0]$14429 - attribute \src "libresoc.v:199670.13-199670.25" + attribute \src "libresoc.v:195858.3-195867.6" + wire width 2 $1\delay$next[1:0]$13618 + attribute \src "libresoc.v:194008.13-194008.25" wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:202343.3-202409.6" - wire width 2 $1\fetch_fsm_state$next[1:0]$14062 - attribute \src "libresoc.v:199686.13-199686.35" + attribute \src "libresoc.v:196074.3-196108.6" + wire $1\exec_fsm_state$next[0:0]$13687 + attribute \src "libresoc.v:194024.7-194024.28" + wire $1\exec_fsm_state[0:0] + attribute \src "libresoc.v:196022.3-196032.6" + wire $1\exec_insn_ready_o[0:0] + attribute \src "libresoc.v:195975.3-195985.6" + wire $1\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:196183.3-196198.6" + wire $1\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:195986.3-196001.6" + wire $1\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:196874.3-196935.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$13815 + attribute \src "libresoc.v:194036.13-194036.35" wire width 2 $1\fetch_fsm_state[1:0] - attribute \src "libresoc.v:202615.3-202650.6" - wire width 32 $1\fetch_insn_o$next[31:0]$14145 - attribute \src "libresoc.v:199690.14-199690.34" + attribute \src "libresoc.v:197052.3-197087.6" wire width 32 $1\fetch_insn_o[31:0] - attribute \src "libresoc.v:202716.3-202726.6" + attribute \src "libresoc.v:197234.3-197244.6" wire $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:202651.3-202661.6" + attribute \src "libresoc.v:197088.3-197098.6" wire $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:202090.3-202105.6" + attribute \src "libresoc.v:196638.3-196648.6" wire $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:202662.3-202672.6" + attribute \src "libresoc.v:197223.3-197233.6" wire $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:201839.3-201866.6" - wire width 2 $1\fsm_state$188$next[1:0]$14008 - attribute \src "libresoc.v:202673.3-202715.6" - wire width 2 $1\fsm_state$next[1:0]$14153 - attribute \src "libresoc.v:199702.13-199702.29" + attribute \src "libresoc.v:196356.3-196383.6" + wire width 2 $1\fsm_state$next[1:0]$13729 + attribute \src "libresoc.v:194050.13-194050.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:201585.3-201605.6" - wire width 32 $1\ilatch$next[31:0]$13969 - attribute \src "libresoc.v:199946.14-199946.28" - wire width 32 $1\ilatch[31:0] - attribute \src "libresoc.v:202106.3-202146.6" + attribute \src "libresoc.v:196649.3-196684.6" wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:202147.3-202196.6" + attribute \src "libresoc.v:196685.3-196729.6" wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:202197.3-202246.6" + attribute \src "libresoc.v:196730.3-196774.6" wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:202448.3-202456.6" - wire $1\jtag_dmi0__ack_o$next[0:0]$14074 - attribute \src "libresoc.v:199964.7-199964.30" + attribute \src "libresoc.v:196167.3-196182.6" + wire $1\insn_done[0:0] + attribute \src "libresoc.v:197099.3-197160.6" + wire width 3 $1\issue_fsm_state$next[2:0]$13866 + attribute \src "libresoc.v:194306.13-194306.35" + wire width 3 $1\issue_fsm_state[2:0] + attribute \src "libresoc.v:196629.3-196637.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13763 + attribute \src "libresoc.v:194310.7-194310.30" wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:202587.3-202595.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$14138 - attribute \src "libresoc.v:199972.14-199972.52" + attribute \src "libresoc.v:196835.3-196843.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13806 + attribute \src "libresoc.v:194318.14-194318.52" wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:202273.3-202307.6" - wire $1\msr_read$next[0:0]$14048 - attribute \src "libresoc.v:200028.7-200028.22" + attribute \src "libresoc.v:196844.3-196873.6" + wire $1\msr_read$next[0:0]$13809 + attribute \src "libresoc.v:194376.7-194376.22" wire $1\msr_read[0:0] - attribute \src "libresoc.v:201867.3-201877.6" + attribute \src "libresoc.v:196384.3-196394.6" wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:201939.3-201949.6" + attribute \src "libresoc.v:196456.3-196466.6" wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:202596.3-202614.6" - wire width 64 $1\nia$next[63:0]$14141 - attribute \src "libresoc.v:200064.14-200064.40" + attribute \src "libresoc.v:197033.3-197051.6" + wire width 64 $1\nia$next[63:0]$13860 + attribute \src "libresoc.v:194412.14-194412.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:201968.3-201983.6" + attribute \src "libresoc.v:196485.3-196500.6" wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:201637.3-201661.6" - wire $1\pc_changed$next[0:0]$13976 - attribute \src "libresoc.v:200070.7-200070.24" + attribute \src "libresoc.v:196138.3-196166.6" + wire $1\pc_changed$next[0:0]$13700 + attribute \src "libresoc.v:194418.7-194418.24" wire $1\pc_changed[0:0] - attribute \src "libresoc.v:201959.3-201967.6" - wire $1\pc_ok_delay$next[0:0]$14026 - attribute \src "libresoc.v:200080.7-200080.25" + attribute \src "libresoc.v:196476.3-196484.6" + wire $1\pc_ok_delay$next[0:0]$13747 + attribute \src "libresoc.v:194428.7-194428.25" wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:202308.3-202342.6" - wire $1\sv_read$next[0:0]$14055 - attribute \src "libresoc.v:200516.7-200516.21" - wire $1\sv_read[0:0] - attribute \src "libresoc.v:202530.3-202548.6" + attribute \src "libresoc.v:196109.3-196137.6" + wire $1\sv_changed$next[0:0]$13694 + attribute \src "libresoc.v:194872.7-194872.24" + wire $1\sv_changed[0:0] + attribute \src "libresoc.v:196976.3-196994.6" wire $1\svp64_bigendian[0:0] - attribute \src "libresoc.v:202511.3-202529.6" + attribute \src "libresoc.v:196957.3-196975.6" wire width 32 $1\svp64_raw_opcode_in[31:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $2\core_asmcode$next[7:0]$14279 - attribute \src "libresoc.v:201555.3-201584.6" - wire $2\core_bigendian_i$10$next[0:0]$13964 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 64 $2\core_core_core_cia$next[63:0]$14280 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$14281 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$14282 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$14283 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_exc_$signal$3$next[0:0]$14284 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_exc_$signal$4$next[0:0]$14285 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_exc_$signal$5$next[0:0]$14286 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_exc_$signal$6$next[0:0]$14287 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_exc_$signal$7$next[0:0]$14288 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_exc_$signal$8$next[0:0]$14289 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_exc_$signal$9$next[0:0]$14290 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_exc_$signal$next[0:0]$14291 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 13 $2\core_core_core_fn_unit$next[12:0]$14292 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$14293 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 32 $2\core_core_core_insn$next[31:0]$14294 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$14295 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_is_32bit$next[0:0]$14296 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 64 $2\core_core_core_msr$next[63:0]$14297 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_oe$next[0:0]$14298 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_oe_ok$next[0:0]$14299 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_rc$next[0:0]$14300 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_core_rc_ok$next[0:0]$14301 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$14302 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $2\core_core_core_traptype$next[7:0]$14303 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $2\core_core_cr_in1$next[6:0]$14304 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_cr_in1_ok$next[0:0]$14305 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $2\core_core_cr_in2$1$next[6:0]$14306 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $2\core_core_cr_in2$next[6:0]$14307 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$14308 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_cr_in2_ok$next[0:0]$14309 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $2\core_core_cr_out$next[6:0]$14310 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_cr_wr_ok$next[0:0]$14311 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $2\core_core_dststep$next[6:0]$13935 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $2\core_core_ea$next[6:0]$14312 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $2\core_core_fast1$next[2:0]$14313 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_fast1_ok$next[0:0]$14314 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $2\core_core_fast2$next[2:0]$14315 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_fast2_ok$next[0:0]$14316 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $2\core_core_fasto1$next[2:0]$14317 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $2\core_core_fasto2$next[2:0]$14318 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_lk$next[0:0]$14319 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $2\core_core_maxvl$next[6:0]$13936 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $2\core_core_pc$next[63:0]$13937 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $2\core_core_reg1$next[6:0]$14320 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_reg1_ok$next[0:0]$14321 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $2\core_core_reg2$next[6:0]$14322 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_reg2_ok$next[0:0]$14323 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $2\core_core_reg3$next[6:0]$14324 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_reg3_ok$next[0:0]$14325 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $2\core_core_rego$next[6:0]$14326 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 10 $2\core_core_spr1$next[9:0]$14327 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_core_spr1_ok$next[0:0]$14328 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 10 $2\core_core_spro$next[9:0]$14329 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $2\core_core_srcstep$next[6:0]$13938 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 2 $2\core_core_subvl$next[1:0]$13939 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 2 $2\core_core_svstep$next[1:0]$13940 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $2\core_core_vl$next[6:0]$13941 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $2\core_core_xer_in$next[2:0]$14330 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_cr_out_ok$next[0:0]$14331 - attribute \src "libresoc.v:202018.3-202038.6" + attribute \src "libresoc.v:196523.3-196538.6" + wire width 64 $1\svstate[63:0] + attribute \src "libresoc.v:196514.3-196522.6" + wire $1\svstate_ok_delay$next[0:0]$13752 + attribute \src "libresoc.v:194890.7-194890.30" + wire $1\svstate_ok_delay[0:0] + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $2\core_asmcode$next[7:0]$13997 + attribute \src "libresoc.v:195942.3-195974.6" + wire $2\core_bigendian_i$10$next[0:0]$13670 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 64 $2\core_core_core_cia$next[63:0]$13998 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$13999 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$14000 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$14001 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$14002 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$14003 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$14004 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$14005 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$14006 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$14007 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$14008 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_exc_$signal$next[0:0]$14009 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 13 $2\core_core_core_fn_unit$next[12:0]$14010 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$14011 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 32 $2\core_core_core_insn$next[31:0]$14012 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$14013 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_is_32bit$next[0:0]$14014 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 64 $2\core_core_core_msr$next[63:0]$14015 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_oe$next[0:0]$14016 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_oe_ok$next[0:0]$14017 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_rc$next[0:0]$14018 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_core_rc_ok$next[0:0]$14019 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$14020 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$14021 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $2\core_core_cr_in1$next[6:0]$14022 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_cr_in1_ok$next[0:0]$14023 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $2\core_core_cr_in2$1$next[6:0]$14024 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $2\core_core_cr_in2$next[6:0]$14025 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$14026 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_cr_in2_ok$next[0:0]$14027 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $2\core_core_cr_out$next[6:0]$14028 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_cr_wr_ok$next[0:0]$14029 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $2\core_core_dststep$next[6:0]$13640 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $2\core_core_ea$next[6:0]$14030 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $2\core_core_fast1$next[2:0]$14031 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_fast1_ok$next[0:0]$14032 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $2\core_core_fast2$next[2:0]$14033 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_fast2_ok$next[0:0]$14034 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $2\core_core_fasto1$next[2:0]$14035 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $2\core_core_fasto2$next[2:0]$14036 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_lk$next[0:0]$14037 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13641 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $2\core_core_pc$next[63:0]$13642 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $2\core_core_reg1$next[6:0]$14038 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_reg1_ok$next[0:0]$14039 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $2\core_core_reg2$next[6:0]$14040 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_reg2_ok$next[0:0]$14041 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $2\core_core_reg3$next[6:0]$14042 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_reg3_ok$next[0:0]$14043 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $2\core_core_rego$next[6:0]$14044 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 10 $2\core_core_spr1$next[9:0]$14045 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_core_spr1_ok$next[0:0]$14046 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 10 $2\core_core_spro$next[9:0]$14047 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13643 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 2 $2\core_core_subvl$next[1:0]$13644 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 2 $2\core_core_svstep$next[1:0]$13645 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $2\core_core_vl$next[6:0]$13646 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $2\core_core_xer_in$next[2:0]$14048 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_cr_out_ok$next[0:0]$14049 + attribute \src "libresoc.v:196587.3-196612.6" wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $2\core_dec$next[63:0]$13942 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_ea_ok$next[0:0]$14332 - attribute \src "libresoc.v:201484.3-201524.6" - wire $2\core_eint$next[0:0]$13943 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_fasto1_ok$next[0:0]$14333 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_fasto2_ok$next[0:0]$14334 - attribute \src "libresoc.v:201606.3-201625.6" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $2\core_dec$next[63:0]$13647 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_ea_ok$next[0:0]$14050 + attribute \src "libresoc.v:195868.3-195908.6" + wire $2\core_eint$next[0:0]$13648 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_fasto1_ok$next[0:0]$14051 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_fasto2_ok$next[0:0]$14052 + attribute \src "libresoc.v:196058.3-196073.6" + wire $2\core_issue_i[0:0] + attribute \src "libresoc.v:196033.3-196057.6" wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $2\core_msr$next[63:0]$13944 - attribute \src "libresoc.v:202060.3-202080.6" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $2\core_msr$next[63:0]$13649 + attribute \src "libresoc.v:196613.3-196628.6" wire width 3 $2\core_msr__ren[2:0] - attribute \src "libresoc.v:201525.3-201554.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13958 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_rego_ok$next[0:0]$14335 - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_spro_ok$next[0:0]$14336 - attribute \src "libresoc.v:202410.3-202428.6" + attribute \src "libresoc.v:195909.3-195941.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13663 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_rego_ok$next[0:0]$14053 + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_spro_ok$next[0:0]$14054 + attribute \src "libresoc.v:197161.3-197191.6" wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:202039.3-202059.6" - wire width 3 $2\core_sv__ren[2:0] - attribute \src "libresoc.v:201997.3-202017.6" + attribute \src "libresoc.v:196561.3-196586.6" wire width 3 $2\core_wen[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $2\core_xer_out$next[0:0]$14337 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $2\cur_cur_dststep$next[6:0]$14093 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $2\cur_cur_maxvl$next[6:0]$14094 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 2 $2\cur_cur_subvl$next[1:0]$14095 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 2 $2\cur_cur_svstep$next[1:0]$14096 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $2\cur_cur_vl$next[6:0]$14097 - attribute \src "libresoc.v:202429.3-202447.6" + attribute \src "libresoc.v:197245.3-197363.6" + wire $2\core_xer_out$next[0:0]$14055 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$13786 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$13787 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$13788 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$13789 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $2\cur_cur_vl$next[6:0]$13790 + attribute \src "libresoc.v:197192.3-197222.6" wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $2\dec2_cur_cur_srcstep$next[6:0]$14098 - attribute \src "libresoc.v:201923.3-201938.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$14019 - attribute \src "libresoc.v:202457.3-202477.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$14078 - attribute \src "libresoc.v:202247.3-202272.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$14043 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 9 $2\dec2_dec_svp64__extra$next[8:0]$14122 - attribute \src "libresoc.v:202727.3-202742.6" - wire width 32 $2\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $2\dec_svp64__elwidth$next[1:0]$14123 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $2\dec_svp64__ewsrc$next[1:0]$14124 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 3 $2\dec_svp64__mask$next[2:0]$14125 - attribute \src "libresoc.v:202549.3-202586.6" - wire $2\dec_svp64__mmode$next[0:0]$14126 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 5 $2\dec_svp64__mode$next[4:0]$14127 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $2\dec_svp64__subvl$next[1:0]$14128 - attribute \src "libresoc.v:202343.3-202409.6" - wire width 2 $2\fetch_fsm_state$next[1:0]$14063 - attribute \src "libresoc.v:202615.3-202650.6" - wire width 32 $2\fetch_insn_o$next[31:0]$14146 - attribute \src "libresoc.v:202090.3-202105.6" - wire $2\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:201839.3-201866.6" - wire width 2 $2\fsm_state$188$next[1:0]$14009 - attribute \src "libresoc.v:202673.3-202715.6" - wire width 2 $2\fsm_state$next[1:0]$14154 - attribute \src "libresoc.v:201585.3-201605.6" - wire width 32 $2\ilatch$next[31:0]$13970 - attribute \src "libresoc.v:202106.3-202146.6" + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $2\dec2_cur_cur_srcstep$next[6:0]$13791 + attribute \src "libresoc.v:196440.3-196455.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13740 + attribute \src "libresoc.v:196936.3-196956.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13825 + attribute \src "libresoc.v:196775.3-196795.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13771 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 9 $2\dec2_dec_svp64__extra$next[8:0]$13844 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $2\dec_svp64__elwidth$next[1:0]$13845 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $2\dec_svp64__ewsrc$next[1:0]$13846 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 3 $2\dec_svp64__mask$next[2:0]$13847 + attribute \src "libresoc.v:196995.3-197032.6" + wire $2\dec_svp64__mmode$next[0:0]$13848 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 5 $2\dec_svp64__mode$next[4:0]$13849 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $2\dec_svp64__subvl$next[1:0]$13850 + attribute \src "libresoc.v:196074.3-196108.6" + wire $2\exec_fsm_state$next[0:0]$13688 + attribute \src "libresoc.v:196183.3-196198.6" + wire $2\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:195986.3-196001.6" + wire $2\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:196874.3-196935.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$13816 + attribute \src "libresoc.v:197052.3-197087.6" + wire width 32 $2\fetch_insn_o[31:0] + attribute \src "libresoc.v:196356.3-196383.6" + wire width 2 $2\fsm_state$next[1:0]$13730 + attribute \src "libresoc.v:196649.3-196684.6" wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:202147.3-202196.6" + attribute \src "libresoc.v:196685.3-196729.6" wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:202197.3-202246.6" + attribute \src "libresoc.v:196730.3-196774.6" wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:202273.3-202307.6" - wire $2\msr_read$next[0:0]$14049 - attribute \src "libresoc.v:202596.3-202614.6" - wire width 64 $2\nia$next[63:0]$14142 - attribute \src "libresoc.v:201968.3-201983.6" + attribute \src "libresoc.v:196167.3-196182.6" + wire $2\insn_done[0:0] + attribute \src "libresoc.v:197099.3-197160.6" + wire width 3 $2\issue_fsm_state$next[2:0]$13867 + attribute \src "libresoc.v:196844.3-196873.6" + wire $2\msr_read$next[0:0]$13810 + attribute \src "libresoc.v:197033.3-197051.6" + wire width 64 $2\nia$next[63:0]$13861 + attribute \src "libresoc.v:196485.3-196500.6" wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:201637.3-201661.6" - wire $2\pc_changed$next[0:0]$13977 - attribute \src "libresoc.v:202308.3-202342.6" - wire $2\sv_read$next[0:0]$14056 - attribute \src "libresoc.v:202530.3-202548.6" + attribute \src "libresoc.v:196138.3-196166.6" + wire $2\pc_changed$next[0:0]$13701 + attribute \src "libresoc.v:196109.3-196137.6" + wire $2\sv_changed$next[0:0]$13695 + attribute \src "libresoc.v:196976.3-196994.6" wire $2\svp64_bigendian[0:0] - attribute \src "libresoc.v:202511.3-202529.6" + attribute \src "libresoc.v:196957.3-196975.6" wire width 32 $2\svp64_raw_opcode_in[31:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $3\core_asmcode$next[7:0]$14338 - attribute \src "libresoc.v:201555.3-201584.6" - wire $3\core_bigendian_i$10$next[0:0]$13965 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 64 $3\core_core_core_cia$next[63:0]$14339 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $3\core_core_core_cr_rd$next[7:0]$14340 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$14341 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $3\core_core_core_cr_wr$next[7:0]$14342 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_exc_$signal$3$next[0:0]$14343 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_exc_$signal$4$next[0:0]$14344 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_exc_$signal$5$next[0:0]$14345 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_exc_$signal$6$next[0:0]$14346 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_exc_$signal$7$next[0:0]$14347 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_exc_$signal$8$next[0:0]$14348 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_exc_$signal$9$next[0:0]$14349 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_exc_$signal$next[0:0]$14350 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 13 $3\core_core_core_fn_unit$next[12:0]$14351 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 2 $3\core_core_core_input_carry$next[1:0]$14352 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 32 $3\core_core_core_insn$next[31:0]$14353 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $3\core_core_core_insn_type$next[6:0]$14354 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_is_32bit$next[0:0]$14355 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 64 $3\core_core_core_msr$next[63:0]$14356 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_oe$next[0:0]$14357 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_oe_ok$next[0:0]$14358 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_rc$next[0:0]$14359 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_core_rc_ok$next[0:0]$14360 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 13 $3\core_core_core_trapaddr$next[12:0]$14361 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 8 $3\core_core_core_traptype$next[7:0]$14362 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $3\core_core_cr_in1$next[6:0]$14363 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_cr_in1_ok$next[0:0]$14364 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $3\core_core_cr_in2$1$next[6:0]$14365 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $3\core_core_cr_in2$next[6:0]$14366 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$14367 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_cr_in2_ok$next[0:0]$14368 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $3\core_core_cr_out$next[6:0]$14369 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_cr_wr_ok$next[0:0]$14370 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $3\core_core_dststep$next[6:0]$13945 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $3\core_core_ea$next[6:0]$14371 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $3\core_core_fast1$next[2:0]$14372 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_fast1_ok$next[0:0]$14373 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $3\core_core_fast2$next[2:0]$14374 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_fast2_ok$next[0:0]$14375 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $3\core_core_fasto1$next[2:0]$14376 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $3\core_core_fasto2$next[2:0]$14377 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_lk$next[0:0]$14378 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $3\core_core_maxvl$next[6:0]$13946 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $3\core_core_pc$next[63:0]$13947 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $3\core_core_reg1$next[6:0]$14379 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_reg1_ok$next[0:0]$14380 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $3\core_core_reg2$next[6:0]$14381 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_reg2_ok$next[0:0]$14382 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $3\core_core_reg3$next[6:0]$14383 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_reg3_ok$next[0:0]$14384 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 7 $3\core_core_rego$next[6:0]$14385 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 10 $3\core_core_spr1$next[9:0]$14386 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_core_spr1_ok$next[0:0]$14387 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 10 $3\core_core_spro$next[9:0]$14388 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $3\core_core_srcstep$next[6:0]$13948 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 2 $3\core_core_subvl$next[1:0]$13949 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 2 $3\core_core_svstep$next[1:0]$13950 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 7 $3\core_core_vl$next[6:0]$13951 - attribute \src "libresoc.v:202743.3-202858.6" - wire width 3 $3\core_core_xer_in$next[2:0]$14389 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_cr_out_ok$next[0:0]$14390 - attribute \src "libresoc.v:202018.3-202038.6" + attribute \src "libresoc.v:196523.3-196538.6" + wire width 64 $2\svstate[63:0] + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $3\core_asmcode$next[7:0]$14056 + attribute \src "libresoc.v:195942.3-195974.6" + wire $3\core_bigendian_i$10$next[0:0]$13671 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 64 $3\core_core_core_cia$next[63:0]$14057 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $3\core_core_core_cr_rd$next[7:0]$14058 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$14059 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $3\core_core_core_cr_wr$next[7:0]$14060 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$14061 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$14062 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$14063 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$14064 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$14065 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$14066 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$14067 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_exc_$signal$next[0:0]$14068 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 13 $3\core_core_core_fn_unit$next[12:0]$14069 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 2 $3\core_core_core_input_carry$next[1:0]$14070 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 32 $3\core_core_core_insn$next[31:0]$14071 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $3\core_core_core_insn_type$next[6:0]$14072 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_is_32bit$next[0:0]$14073 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 64 $3\core_core_core_msr$next[63:0]$14074 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_oe$next[0:0]$14075 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_oe_ok$next[0:0]$14076 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_rc$next[0:0]$14077 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_core_rc_ok$next[0:0]$14078 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 13 $3\core_core_core_trapaddr$next[12:0]$14079 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $3\core_core_core_traptype$next[7:0]$14080 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $3\core_core_cr_in1$next[6:0]$14081 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_cr_in1_ok$next[0:0]$14082 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $3\core_core_cr_in2$1$next[6:0]$14083 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $3\core_core_cr_in2$next[6:0]$14084 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$14085 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_cr_in2_ok$next[0:0]$14086 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $3\core_core_cr_out$next[6:0]$14087 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_cr_wr_ok$next[0:0]$14088 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $3\core_core_dststep$next[6:0]$13650 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $3\core_core_ea$next[6:0]$14089 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $3\core_core_fast1$next[2:0]$14090 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_fast1_ok$next[0:0]$14091 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $3\core_core_fast2$next[2:0]$14092 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_fast2_ok$next[0:0]$14093 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $3\core_core_fasto1$next[2:0]$14094 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $3\core_core_fasto2$next[2:0]$14095 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_lk$next[0:0]$14096 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $3\core_core_maxvl$next[6:0]$13651 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $3\core_core_pc$next[63:0]$13652 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $3\core_core_reg1$next[6:0]$14097 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_reg1_ok$next[0:0]$14098 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $3\core_core_reg2$next[6:0]$14099 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_reg2_ok$next[0:0]$14100 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $3\core_core_reg3$next[6:0]$14101 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_reg3_ok$next[0:0]$14102 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $3\core_core_rego$next[6:0]$14103 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 10 $3\core_core_spr1$next[9:0]$14104 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_core_spr1_ok$next[0:0]$14105 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 10 $3\core_core_spro$next[9:0]$14106 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $3\core_core_srcstep$next[6:0]$13653 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 2 $3\core_core_subvl$next[1:0]$13654 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 2 $3\core_core_svstep$next[1:0]$13655 + attribute \src "libresoc.v:195868.3-195908.6" + wire width 7 $3\core_core_vl$next[6:0]$13656 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $3\core_core_xer_in$next[2:0]$14107 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_cr_out_ok$next[0:0]$14108 + attribute \src "libresoc.v:196587.3-196612.6" wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $3\core_dec$next[63:0]$13952 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_ea_ok$next[0:0]$14391 - attribute \src "libresoc.v:201484.3-201524.6" - wire $3\core_eint$next[0:0]$13953 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_fasto1_ok$next[0:0]$14392 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_fasto2_ok$next[0:0]$14393 - attribute \src "libresoc.v:201484.3-201524.6" - wire width 64 $3\core_msr$next[63:0]$13954 - attribute \src "libresoc.v:202060.3-202080.6" - wire width 3 $3\core_msr__ren[2:0] - attribute \src "libresoc.v:201525.3-201554.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13959 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_rego_ok$next[0:0]$14394 - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_spro_ok$next[0:0]$14395 - attribute \src "libresoc.v:202039.3-202059.6" - wire width 3 $3\core_sv__ren[2:0] - attribute \src "libresoc.v:201997.3-202017.6" + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $3\core_dec$next[63:0]$13657 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_ea_ok$next[0:0]$14109 + attribute \src "libresoc.v:195868.3-195908.6" + wire $3\core_eint$next[0:0]$13658 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_fasto1_ok$next[0:0]$14110 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_fasto2_ok$next[0:0]$14111 + attribute \src "libresoc.v:196033.3-196057.6" + wire $3\core_ivalid_i[0:0] + attribute \src "libresoc.v:195868.3-195908.6" + wire width 64 $3\core_msr$next[63:0]$13659 + attribute \src "libresoc.v:195909.3-195941.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13664 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_rego_ok$next[0:0]$14112 + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_spro_ok$next[0:0]$14113 + attribute \src "libresoc.v:197161.3-197191.6" + wire $3\core_stopped_i[0:0] + attribute \src "libresoc.v:196561.3-196586.6" wire width 3 $3\core_wen[2:0] - attribute \src "libresoc.v:202743.3-202858.6" - wire $3\core_xer_out$next[0:0]$14396 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $3\cur_cur_dststep$next[6:0]$14099 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $3\cur_cur_maxvl$next[6:0]$14100 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 2 $3\cur_cur_subvl$next[1:0]$14101 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 2 $3\cur_cur_svstep$next[1:0]$14102 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $3\cur_cur_vl$next[6:0]$14103 - attribute \src "libresoc.v:202478.3-202510.6" - wire width 7 $3\dec2_cur_cur_srcstep$next[6:0]$14104 - attribute \src "libresoc.v:202457.3-202477.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$14079 - attribute \src "libresoc.v:202247.3-202272.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$14044 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 9 $3\dec2_dec_svp64__extra$next[8:0]$14129 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $3\dec_svp64__elwidth$next[1:0]$14130 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $3\dec_svp64__ewsrc$next[1:0]$14131 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 3 $3\dec_svp64__mask$next[2:0]$14132 - attribute \src "libresoc.v:202549.3-202586.6" - wire $3\dec_svp64__mmode$next[0:0]$14133 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 5 $3\dec_svp64__mode$next[4:0]$14134 - attribute \src "libresoc.v:202549.3-202586.6" - wire width 2 $3\dec_svp64__subvl$next[1:0]$14135 - attribute \src "libresoc.v:202343.3-202409.6" - wire width 2 $3\fetch_fsm_state$next[1:0]$14064 - attribute \src "libresoc.v:202615.3-202650.6" - wire width 32 $3\fetch_insn_o$next[31:0]$14147 - attribute \src "libresoc.v:202673.3-202715.6" - wire width 2 $3\fsm_state$next[1:0]$14155 - attribute \src "libresoc.v:201585.3-201605.6" - wire width 32 $3\ilatch$next[31:0]$13971 - attribute \src "libresoc.v:202106.3-202146.6" + attribute \src "libresoc.v:197245.3-197363.6" + wire $3\core_xer_out$next[0:0]$14114 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$13792 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$13793 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$13794 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$13795 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $3\cur_cur_vl$next[6:0]$13796 + attribute \src "libresoc.v:197192.3-197222.6" + wire $3\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $3\dec2_cur_cur_srcstep$next[6:0]$13797 + attribute \src "libresoc.v:196936.3-196956.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13826 + attribute \src "libresoc.v:196775.3-196795.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13772 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 9 $3\dec2_dec_svp64__extra$next[8:0]$13851 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $3\dec_svp64__elwidth$next[1:0]$13852 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $3\dec_svp64__ewsrc$next[1:0]$13853 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 3 $3\dec_svp64__mask$next[2:0]$13854 + attribute \src "libresoc.v:196995.3-197032.6" + wire $3\dec_svp64__mmode$next[0:0]$13855 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 5 $3\dec_svp64__mode$next[4:0]$13856 + attribute \src "libresoc.v:196995.3-197032.6" + wire width 2 $3\dec_svp64__subvl$next[1:0]$13857 + attribute \src "libresoc.v:196074.3-196108.6" + wire $3\exec_fsm_state$next[0:0]$13689 + attribute \src "libresoc.v:196874.3-196935.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$13817 + attribute \src "libresoc.v:197052.3-197087.6" + wire width 32 $3\fetch_insn_o[31:0] + attribute \src "libresoc.v:196649.3-196684.6" wire width 48 $3\imem_a_pc_i[47:0] - attribute \src "libresoc.v:202147.3-202196.6" + attribute \src "libresoc.v:196685.3-196729.6" wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:202197.3-202246.6" + attribute \src "libresoc.v:196730.3-196774.6" wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:202273.3-202307.6" - wire $3\msr_read$next[0:0]$14050 - attribute \src "libresoc.v:201637.3-201661.6" - wire $3\pc_changed$next[0:0]$13978 - attribute \src "libresoc.v:202308.3-202342.6" - wire $3\sv_read$next[0:0]$14057 - attribute \src "libresoc.v:201555.3-201584.6" - wire $4\core_bigendian_i$10$next[0:0]$13966 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_cr_rd_ok$next[0:0]$14397 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_exc_$signal$3$next[0:0]$14398 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_exc_$signal$4$next[0:0]$14399 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_exc_$signal$5$next[0:0]$14400 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_exc_$signal$6$next[0:0]$14401 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_exc_$signal$7$next[0:0]$14402 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_exc_$signal$8$next[0:0]$14403 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_exc_$signal$9$next[0:0]$14404 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_exc_$signal$next[0:0]$14405 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_oe_ok$next[0:0]$14406 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_core_rc_ok$next[0:0]$14407 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_cr_in1_ok$next[0:0]$14408 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_cr_in2_ok$2$next[0:0]$14409 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_cr_in2_ok$next[0:0]$14410 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_cr_wr_ok$next[0:0]$14411 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_fast1_ok$next[0:0]$14412 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_fast2_ok$next[0:0]$14413 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_reg1_ok$next[0:0]$14414 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_reg2_ok$next[0:0]$14415 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_reg3_ok$next[0:0]$14416 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_core_spr1_ok$next[0:0]$14417 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_cr_out_ok$next[0:0]$14418 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_ea_ok$next[0:0]$14419 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_fasto1_ok$next[0:0]$14420 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_fasto2_ok$next[0:0]$14421 - attribute \src "libresoc.v:201525.3-201554.6" - wire width 32 $4\core_raw_insn_i$next[31:0]$13960 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_rego_ok$next[0:0]$14422 - attribute \src "libresoc.v:202743.3-202858.6" - wire $4\core_spro_ok$next[0:0]$14423 - attribute \src "libresoc.v:202247.3-202272.6" - wire width 64 $4\dec2_cur_pc$next[63:0]$14045 - attribute \src "libresoc.v:202343.3-202409.6" - wire width 2 $4\fetch_fsm_state$next[1:0]$14065 - attribute \src "libresoc.v:202615.3-202650.6" - wire width 32 $4\fetch_insn_o$next[31:0]$14148 - attribute \src "libresoc.v:202673.3-202715.6" - wire width 2 $4\fsm_state$next[1:0]$14156 - attribute \src "libresoc.v:202106.3-202146.6" + attribute \src "libresoc.v:197099.3-197160.6" + wire width 3 $3\issue_fsm_state$next[2:0]$13868 + attribute \src "libresoc.v:196844.3-196873.6" + wire $3\msr_read$next[0:0]$13811 + attribute \src "libresoc.v:196138.3-196166.6" + wire $3\pc_changed$next[0:0]$13702 + attribute \src "libresoc.v:196109.3-196137.6" + wire $3\sv_changed$next[0:0]$13696 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $4\core_asmcode$next[7:0]$14115 + attribute \src "libresoc.v:195942.3-195974.6" + wire $4\core_bigendian_i$10$next[0:0]$13672 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 64 $4\core_core_core_cia$next[63:0]$14116 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $4\core_core_core_cr_rd$next[7:0]$14117 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_cr_rd_ok$next[0:0]$14118 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $4\core_core_core_cr_wr$next[7:0]$14119 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_exc_$signal$3$next[0:0]$14120 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_exc_$signal$4$next[0:0]$14121 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_exc_$signal$5$next[0:0]$14122 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_exc_$signal$6$next[0:0]$14123 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_exc_$signal$7$next[0:0]$14124 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_exc_$signal$8$next[0:0]$14125 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_exc_$signal$9$next[0:0]$14126 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_exc_$signal$next[0:0]$14127 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 13 $4\core_core_core_fn_unit$next[12:0]$14128 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 2 $4\core_core_core_input_carry$next[1:0]$14129 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 32 $4\core_core_core_insn$next[31:0]$14130 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $4\core_core_core_insn_type$next[6:0]$14131 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_is_32bit$next[0:0]$14132 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 64 $4\core_core_core_msr$next[63:0]$14133 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_oe$next[0:0]$14134 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_oe_ok$next[0:0]$14135 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_rc$next[0:0]$14136 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_core_rc_ok$next[0:0]$14137 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 13 $4\core_core_core_trapaddr$next[12:0]$14138 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 8 $4\core_core_core_traptype$next[7:0]$14139 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $4\core_core_cr_in1$next[6:0]$14140 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_cr_in1_ok$next[0:0]$14141 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $4\core_core_cr_in2$1$next[6:0]$14142 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $4\core_core_cr_in2$next[6:0]$14143 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_cr_in2_ok$2$next[0:0]$14144 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_cr_in2_ok$next[0:0]$14145 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $4\core_core_cr_out$next[6:0]$14146 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_cr_wr_ok$next[0:0]$14147 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $4\core_core_ea$next[6:0]$14148 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $4\core_core_fast1$next[2:0]$14149 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_fast1_ok$next[0:0]$14150 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $4\core_core_fast2$next[2:0]$14151 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_fast2_ok$next[0:0]$14152 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $4\core_core_fasto1$next[2:0]$14153 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $4\core_core_fasto2$next[2:0]$14154 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_lk$next[0:0]$14155 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $4\core_core_reg1$next[6:0]$14156 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_reg1_ok$next[0:0]$14157 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $4\core_core_reg2$next[6:0]$14158 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_reg2_ok$next[0:0]$14159 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $4\core_core_reg3$next[6:0]$14160 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_reg3_ok$next[0:0]$14161 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 7 $4\core_core_rego$next[6:0]$14162 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 10 $4\core_core_spr1$next[9:0]$14163 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_core_spr1_ok$next[0:0]$14164 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 10 $4\core_core_spro$next[9:0]$14165 + attribute \src "libresoc.v:197245.3-197363.6" + wire width 3 $4\core_core_xer_in$next[2:0]$14166 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_cr_out_ok$next[0:0]$14167 + attribute \src "libresoc.v:196587.3-196612.6" + wire width 64 $4\core_data_i[63:0] + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_ea_ok$next[0:0]$14168 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_fasto1_ok$next[0:0]$14169 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_fasto2_ok$next[0:0]$14170 + attribute \src "libresoc.v:195909.3-195941.6" + wire width 32 $4\core_raw_insn_i$next[31:0]$13665 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_rego_ok$next[0:0]$14171 + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_spro_ok$next[0:0]$14172 + attribute \src "libresoc.v:196561.3-196586.6" + wire width 3 $4\core_wen[2:0] + attribute \src "libresoc.v:197245.3-197363.6" + wire $4\core_xer_out$next[0:0]$14173 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $4\cur_cur_dststep$next[6:0]$13798 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $4\cur_cur_maxvl$next[6:0]$13799 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 2 $4\cur_cur_subvl$next[1:0]$13800 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 2 $4\cur_cur_svstep$next[1:0]$13801 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $4\cur_cur_vl$next[6:0]$13802 + attribute \src "libresoc.v:196796.3-196834.6" + wire width 7 $4\dec2_cur_cur_srcstep$next[6:0]$13803 + attribute \src "libresoc.v:196074.3-196108.6" + wire $4\exec_fsm_state$next[0:0]$13690 + attribute \src "libresoc.v:196874.3-196935.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$13818 + attribute \src "libresoc.v:197052.3-197087.6" + wire width 32 $4\fetch_insn_o[31:0] + attribute \src "libresoc.v:196649.3-196684.6" wire width 48 $4\imem_a_pc_i[47:0] - attribute \src "libresoc.v:202147.3-202196.6" + attribute \src "libresoc.v:196685.3-196729.6" wire $4\imem_a_valid_i[0:0] - attribute \src "libresoc.v:202197.3-202246.6" + attribute \src "libresoc.v:196730.3-196774.6" wire $4\imem_f_valid_i[0:0] - attribute \src "libresoc.v:202273.3-202307.6" - wire $4\msr_read$next[0:0]$14051 - attribute \src "libresoc.v:202308.3-202342.6" - wire $4\sv_read$next[0:0]$14058 - attribute \src "libresoc.v:202343.3-202409.6" - wire width 2 $5\fetch_fsm_state$next[1:0]$14066 - attribute \src "libresoc.v:202673.3-202715.6" - wire width 2 $5\fsm_state$next[1:0]$14157 - attribute \src "libresoc.v:202106.3-202146.6" - wire width 48 $5\imem_a_pc_i[47:0] - attribute \src "libresoc.v:202147.3-202196.6" + attribute \src "libresoc.v:197099.3-197160.6" + wire width 3 $4\issue_fsm_state$next[2:0]$13869 + attribute \src "libresoc.v:196844.3-196873.6" + wire $4\msr_read$next[0:0]$13812 + attribute \src "libresoc.v:196138.3-196166.6" + wire $4\pc_changed$next[0:0]$13703 + attribute \src "libresoc.v:196109.3-196137.6" + wire $4\sv_changed$next[0:0]$13697 + attribute \src "libresoc.v:195942.3-195974.6" + wire $5\core_bigendian_i$10$next[0:0]$13673 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_cr_rd_ok$next[0:0]$14174 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_exc_$signal$3$next[0:0]$14175 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_exc_$signal$4$next[0:0]$14176 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_exc_$signal$5$next[0:0]$14177 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_exc_$signal$6$next[0:0]$14178 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_exc_$signal$7$next[0:0]$14179 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_exc_$signal$8$next[0:0]$14180 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_exc_$signal$9$next[0:0]$14181 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_exc_$signal$next[0:0]$14182 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_oe_ok$next[0:0]$14183 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_core_rc_ok$next[0:0]$14184 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_cr_in1_ok$next[0:0]$14185 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_cr_in2_ok$2$next[0:0]$14186 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_cr_in2_ok$next[0:0]$14187 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_cr_wr_ok$next[0:0]$14188 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_fast1_ok$next[0:0]$14189 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_fast2_ok$next[0:0]$14190 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_reg1_ok$next[0:0]$14191 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_reg2_ok$next[0:0]$14192 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_reg3_ok$next[0:0]$14193 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_core_spr1_ok$next[0:0]$14194 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_cr_out_ok$next[0:0]$14195 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_ea_ok$next[0:0]$14196 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_fasto1_ok$next[0:0]$14197 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_fasto2_ok$next[0:0]$14198 + attribute \src "libresoc.v:195909.3-195941.6" + wire width 32 $5\core_raw_insn_i$next[31:0]$13666 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_rego_ok$next[0:0]$14199 + attribute \src "libresoc.v:197245.3-197363.6" + wire $5\core_spro_ok$next[0:0]$14200 + attribute \src "libresoc.v:196074.3-196108.6" + wire $5\exec_fsm_state$next[0:0]$13691 + attribute \src "libresoc.v:196874.3-196935.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$13819 + attribute \src "libresoc.v:196685.3-196729.6" wire $5\imem_a_valid_i[0:0] - attribute \src "libresoc.v:202197.3-202246.6" + attribute \src "libresoc.v:196730.3-196774.6" wire $5\imem_f_valid_i[0:0] - attribute \src "libresoc.v:202273.3-202307.6" - wire $5\msr_read$next[0:0]$14052 - attribute \src "libresoc.v:202308.3-202342.6" - wire $5\sv_read$next[0:0]$14059 - attribute \src "libresoc.v:202343.3-202409.6" - wire width 2 $6\fetch_fsm_state$next[1:0]$14067 - attribute \src "libresoc.v:202147.3-202196.6" - wire $6\imem_a_valid_i[0:0] - attribute \src "libresoc.v:202197.3-202246.6" - wire $6\imem_f_valid_i[0:0] - attribute \src "libresoc.v:202343.3-202409.6" - wire width 2 $7\fetch_fsm_state$next[1:0]$14068 - attribute \src "libresoc.v:202343.3-202409.6" - wire width 2 $8\fetch_fsm_state$next[1:0]$14069 - attribute \src "libresoc.v:200564.19-200564.109" - wire width 65 $add$libresoc.v:200564$13726_Y - attribute \src "libresoc.v:200568.19-200568.108" - wire width 65 $add$libresoc.v:200568$13730_Y - attribute \src "libresoc.v:200575.19-200575.108" - wire width 65 $add$libresoc.v:200575$13737_Y - attribute \src "libresoc.v:200585.19-200585.115" - wire width 65 $add$libresoc.v:200585$13749_Y - attribute \src "libresoc.v:200611.18-200611.107" - wire width 65 $add$libresoc.v:200611$13775_Y - attribute \src "libresoc.v:200543.19-200543.103" - wire $and$libresoc.v:200543$13705_Y - attribute \src "libresoc.v:200547.19-200547.104" - wire $and$libresoc.v:200547$13709_Y - attribute \src "libresoc.v:200551.19-200551.104" - wire $and$libresoc.v:200551$13713_Y - attribute \src "libresoc.v:200555.19-200555.104" - wire $and$libresoc.v:200555$13717_Y - attribute \src "libresoc.v:200558.19-200558.104" - wire $and$libresoc.v:200558$13720_Y - attribute \src "libresoc.v:200579.19-200579.115" - wire width 3 $and$libresoc.v:200579$13741_Y - attribute \src "libresoc.v:200592.18-200592.109" - wire $and$libresoc.v:200592$13756_Y - attribute \src "libresoc.v:200600.18-200600.101" - wire $and$libresoc.v:200600$13764_Y - attribute \src "libresoc.v:200603.18-200603.101" - wire $and$libresoc.v:200603$13767_Y - attribute \src "libresoc.v:200606.18-200606.101" - wire $and$libresoc.v:200606$13770_Y - attribute \src "libresoc.v:200609.18-200609.101" - wire $and$libresoc.v:200609$13773_Y - attribute \src "libresoc.v:200614.18-200614.101" - wire $and$libresoc.v:200614$13778_Y - attribute \src "libresoc.v:200618.18-200618.101" - wire $and$libresoc.v:200618$13782_Y - attribute \src "libresoc.v:200622.18-200622.101" - wire $and$libresoc.v:200622$13786_Y - attribute \src "libresoc.v:200582.19-200582.114" - wire width 64 $extend$libresoc.v:200582$13744_Y - attribute \src "libresoc.v:200583.19-200583.113" - wire width 64 $extend$libresoc.v:200583$13746_Y - attribute \src "libresoc.v:200561.19-200561.111" - wire width 7 $mul$libresoc.v:200561$13723_Y - attribute \src "libresoc.v:200566.19-200566.111" - wire width 7 $mul$libresoc.v:200566$13728_Y - attribute \src "libresoc.v:200569.19-200569.106" - wire width 7 $mul$libresoc.v:200569$13731_Y - attribute \src "libresoc.v:200576.19-200576.106" - wire width 7 $mul$libresoc.v:200576$13738_Y - attribute \src "libresoc.v:200578.19-200578.123" - wire $ne$libresoc.v:200578$13740_Y - attribute \src "libresoc.v:200586.18-200586.102" - wire $ne$libresoc.v:200586$13750_Y - attribute \src "libresoc.v:200590.18-200590.102" - wire $ne$libresoc.v:200590$13754_Y - attribute \src "libresoc.v:200541.18-200541.106" - wire $not$libresoc.v:200541$13703_Y - attribute \src "libresoc.v:200542.19-200542.109" - wire $not$libresoc.v:200542$13704_Y - attribute \src "libresoc.v:200544.19-200544.100" - wire $not$libresoc.v:200544$13706_Y - attribute \src "libresoc.v:200545.19-200545.107" - wire $not$libresoc.v:200545$13707_Y - attribute \src "libresoc.v:200546.19-200546.109" - wire $not$libresoc.v:200546$13708_Y - attribute \src "libresoc.v:200548.19-200548.99" - wire $not$libresoc.v:200548$13710_Y - attribute \src "libresoc.v:200549.19-200549.107" - wire $not$libresoc.v:200549$13711_Y - attribute \src "libresoc.v:200550.19-200550.109" - wire $not$libresoc.v:200550$13712_Y - attribute \src "libresoc.v:200552.19-200552.111" - wire $not$libresoc.v:200552$13714_Y - attribute \src "libresoc.v:200553.19-200553.107" - wire $not$libresoc.v:200553$13715_Y - attribute \src "libresoc.v:200554.19-200554.109" - wire $not$libresoc.v:200554$13716_Y - attribute \src "libresoc.v:200556.19-200556.107" - wire $not$libresoc.v:200556$13718_Y - attribute \src "libresoc.v:200557.19-200557.109" - wire $not$libresoc.v:200557$13719_Y - attribute \src "libresoc.v:200559.19-200559.100" - wire $not$libresoc.v:200559$13721_Y - attribute \src "libresoc.v:200560.19-200560.99" - wire $not$libresoc.v:200560$13722_Y - attribute \src "libresoc.v:200565.19-200565.111" - wire $not$libresoc.v:200565$13727_Y - attribute \src "libresoc.v:200571.19-200571.107" - wire $not$libresoc.v:200571$13733_Y - attribute \src "libresoc.v:200572.19-200572.107" - wire $not$libresoc.v:200572$13734_Y - attribute \src "libresoc.v:200573.19-200573.107" - wire $not$libresoc.v:200573$13735_Y - attribute \src "libresoc.v:200574.19-200574.107" - wire $not$libresoc.v:200574$13736_Y - attribute \src "libresoc.v:200591.18-200591.103" - wire $not$libresoc.v:200591$13755_Y - attribute \src "libresoc.v:200593.18-200593.98" - wire $not$libresoc.v:200593$13757_Y - attribute \src "libresoc.v:200594.18-200594.106" - wire $not$libresoc.v:200594$13758_Y - attribute \src "libresoc.v:200595.18-200595.101" - wire $not$libresoc.v:200595$13759_Y - attribute \src "libresoc.v:200596.18-200596.106" - wire $not$libresoc.v:200596$13760_Y - attribute \src "libresoc.v:200597.18-200597.101" - wire $not$libresoc.v:200597$13761_Y - attribute \src "libresoc.v:200598.18-200598.106" - wire $not$libresoc.v:200598$13762_Y - attribute \src "libresoc.v:200599.18-200599.108" - wire $not$libresoc.v:200599$13763_Y - attribute \src "libresoc.v:200601.18-200601.106" - wire $not$libresoc.v:200601$13765_Y - attribute \src "libresoc.v:200602.18-200602.108" - wire $not$libresoc.v:200602$13766_Y - attribute \src "libresoc.v:200604.18-200604.106" - wire $not$libresoc.v:200604$13768_Y - attribute \src "libresoc.v:200605.18-200605.108" - wire $not$libresoc.v:200605$13769_Y - attribute \src "libresoc.v:200607.18-200607.106" - wire $not$libresoc.v:200607$13771_Y - attribute \src "libresoc.v:200608.18-200608.108" - wire $not$libresoc.v:200608$13772_Y - attribute \src "libresoc.v:200610.18-200610.110" - wire $not$libresoc.v:200610$13774_Y - attribute \src "libresoc.v:200612.18-200612.106" - wire $not$libresoc.v:200612$13776_Y - attribute \src "libresoc.v:200613.18-200613.108" - wire $not$libresoc.v:200613$13777_Y - attribute \src "libresoc.v:200615.18-200615.110" - wire $not$libresoc.v:200615$13779_Y - attribute \src "libresoc.v:200616.18-200616.106" - wire $not$libresoc.v:200616$13780_Y - attribute \src "libresoc.v:200617.18-200617.108" - wire $not$libresoc.v:200617$13781_Y - attribute \src "libresoc.v:200619.18-200619.110" - wire $not$libresoc.v:200619$13783_Y - attribute \src "libresoc.v:200620.18-200620.106" - wire $not$libresoc.v:200620$13784_Y - attribute \src "libresoc.v:200621.18-200621.108" - wire $not$libresoc.v:200621$13785_Y - attribute \src "libresoc.v:200588.18-200588.110" - wire $or$libresoc.v:200588$13752_Y - attribute \src "libresoc.v:200589.18-200589.100" - wire $or$libresoc.v:200589$13753_Y - attribute \src "libresoc.v:200581.19-200581.211" - wire width 64 $pos$libresoc.v:200581$13743_Y - attribute \src "libresoc.v:200582.19-200582.114" - wire width 64 $pos$libresoc.v:200582$13745_Y - attribute \src "libresoc.v:200583.19-200583.113" - wire width 64 $pos$libresoc.v:200583$13747_Y - attribute \src "libresoc.v:200580.19-200580.93" - wire $reduce_or$libresoc.v:200580$13742_Y - attribute \src "libresoc.v:200562.19-200562.42" - wire width 64 $shr$libresoc.v:200562$13724_Y - attribute \src "libresoc.v:200567.19-200567.42" - wire width 64 $shr$libresoc.v:200567$13729_Y - attribute \src "libresoc.v:200570.19-200570.42" - wire width 64 $shr$libresoc.v:200570$13732_Y - attribute \src "libresoc.v:200577.19-200577.42" - wire width 64 $shr$libresoc.v:200577$13739_Y - attribute \src "libresoc.v:200584.19-200584.115" - wire width 65 $sub$libresoc.v:200584$13748_Y - attribute \src "libresoc.v:200587.18-200587.101" - wire width 3 $sub$libresoc.v:200587$13751_Y - attribute \src "libresoc.v:200563.19-200563.123" - wire width 4 $ternary$libresoc.v:200563$13725_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "libresoc.v:197099.3-197160.6" + wire width 3 $5\issue_fsm_state$next[2:0]$13870 + attribute \src "libresoc.v:196874.3-196935.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$13820 + attribute \src "libresoc.v:197099.3-197160.6" + wire width 3 $6\issue_fsm_state$next[2:0]$13871 + attribute \src "libresoc.v:196874.3-196935.6" + wire width 2 $7\fetch_fsm_state$next[1:0]$13821 + attribute \src "libresoc.v:197099.3-197160.6" + wire width 3 $7\issue_fsm_state$next[2:0]$13872 + attribute \src "libresoc.v:197099.3-197160.6" + wire width 3 $8\issue_fsm_state$next[2:0]$13873 + attribute \src "libresoc.v:194944.19-194944.115" + wire width 65 $add$libresoc.v:194944$13448_Y + attribute \src "libresoc.v:194964.18-194964.107" + wire width 65 $add$libresoc.v:194964$13469_Y + attribute \src "libresoc.v:194973.18-194973.107" + wire width 65 $add$libresoc.v:194973$13478_Y + attribute \src "libresoc.v:194977.18-194977.107" + wire width 65 $add$libresoc.v:194977$13482_Y + attribute \src "libresoc.v:194908.19-194908.102" + wire $and$libresoc.v:194908$13410_Y + attribute \src "libresoc.v:194911.19-194911.104" + wire $and$libresoc.v:194911$13413_Y + attribute \src "libresoc.v:194914.19-194914.104" + wire $and$libresoc.v:194914$13416_Y + attribute \src "libresoc.v:194917.19-194917.104" + wire $and$libresoc.v:194917$13419_Y + attribute \src "libresoc.v:194920.19-194920.104" + wire $and$libresoc.v:194920$13422_Y + attribute \src "libresoc.v:194923.19-194923.104" + wire $and$libresoc.v:194923$13425_Y + attribute \src "libresoc.v:194929.19-194929.104" + wire $and$libresoc.v:194929$13431_Y + attribute \src "libresoc.v:194933.19-194933.115" + wire width 3 $and$libresoc.v:194933$13435_Y + attribute \src "libresoc.v:194936.19-194936.115" + wire width 3 $and$libresoc.v:194936$13438_Y + attribute \src "libresoc.v:194951.18-194951.109" + wire $and$libresoc.v:194951$13455_Y + attribute \src "libresoc.v:194957.18-194957.101" + wire $and$libresoc.v:194957$13462_Y + attribute \src "libresoc.v:194961.18-194961.101" + wire $and$libresoc.v:194961$13466_Y + attribute \src "libresoc.v:194941.19-194941.114" + wire width 64 $extend$libresoc.v:194941$13443_Y + attribute \src "libresoc.v:194942.19-194942.113" + wire width 64 $extend$libresoc.v:194942$13445_Y + attribute \src "libresoc.v:194954.18-194954.109" + wire width 64 $extend$libresoc.v:194954$13458_Y + attribute \src "libresoc.v:194970.18-194970.110" + wire width 7 $mul$libresoc.v:194970$13475_Y + attribute \src "libresoc.v:194975.18-194975.110" + wire width 7 $mul$libresoc.v:194975$13480_Y + attribute \src "libresoc.v:194978.18-194978.104" + wire width 7 $mul$libresoc.v:194978$13483_Y + attribute \src "libresoc.v:194931.19-194931.123" + wire $ne$libresoc.v:194931$13433_Y + attribute \src "libresoc.v:194945.18-194945.102" + wire $ne$libresoc.v:194945$13449_Y + attribute \src "libresoc.v:194949.18-194949.102" + wire $ne$libresoc.v:194949$13453_Y + attribute \src "libresoc.v:194907.18-194907.108" + wire $not$libresoc.v:194907$13409_Y + attribute \src "libresoc.v:194909.19-194909.107" + wire $not$libresoc.v:194909$13411_Y + attribute \src "libresoc.v:194910.19-194910.109" + wire $not$libresoc.v:194910$13412_Y + attribute \src "libresoc.v:194912.19-194912.107" + wire $not$libresoc.v:194912$13414_Y + attribute \src "libresoc.v:194913.19-194913.109" + wire $not$libresoc.v:194913$13415_Y + attribute \src "libresoc.v:194915.19-194915.107" + wire $not$libresoc.v:194915$13417_Y + attribute \src "libresoc.v:194916.19-194916.109" + wire $not$libresoc.v:194916$13418_Y + attribute \src "libresoc.v:194918.19-194918.107" + wire $not$libresoc.v:194918$13420_Y + attribute \src "libresoc.v:194919.19-194919.109" + wire $not$libresoc.v:194919$13421_Y + attribute \src "libresoc.v:194921.19-194921.107" + wire $not$libresoc.v:194921$13423_Y + attribute \src "libresoc.v:194922.19-194922.109" + wire $not$libresoc.v:194922$13424_Y + attribute \src "libresoc.v:194924.19-194924.107" + wire $not$libresoc.v:194924$13426_Y + attribute \src "libresoc.v:194925.19-194925.107" + wire $not$libresoc.v:194925$13427_Y + attribute \src "libresoc.v:194926.19-194926.107" + wire $not$libresoc.v:194926$13428_Y + attribute \src "libresoc.v:194927.19-194927.107" + wire $not$libresoc.v:194927$13429_Y + attribute \src "libresoc.v:194928.19-194928.109" + wire $not$libresoc.v:194928$13430_Y + attribute \src "libresoc.v:194932.19-194932.107" + wire $not$libresoc.v:194932$13434_Y + attribute \src "libresoc.v:194935.19-194935.107" + wire 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$or$libresoc.v:194948$13452_Y + attribute \src "libresoc.v:194930.19-194930.211" + wire width 64 $pos$libresoc.v:194930$13432_Y + attribute \src "libresoc.v:194941.19-194941.114" + wire width 64 $pos$libresoc.v:194941$13444_Y + attribute \src "libresoc.v:194942.19-194942.113" + wire width 64 $pos$libresoc.v:194942$13446_Y + attribute \src "libresoc.v:194954.18-194954.109" + wire width 64 $pos$libresoc.v:194954$13459_Y + attribute \src "libresoc.v:194934.19-194934.93" + wire $reduce_or$libresoc.v:194934$13436_Y + attribute \src "libresoc.v:194937.19-194937.93" + wire $reduce_or$libresoc.v:194937$13439_Y + attribute \src "libresoc.v:194971.18-194971.40" + wire width 64 $shr$libresoc.v:194971$13476_Y + attribute \src "libresoc.v:194976.18-194976.40" + wire width 64 $shr$libresoc.v:194976$13481_Y + attribute \src "libresoc.v:194979.18-194979.40" + wire width 64 $shr$libresoc.v:194979$13484_Y + attribute \src "libresoc.v:194943.19-194943.115" + wire width 65 $sub$libresoc.v:194943$13447_Y + attribute \src "libresoc.v:194946.18-194946.101" + wire width 3 $sub$libresoc.v:194946$13450_Y + attribute \src "libresoc.v:194972.18-194972.122" + wire width 4 $ternary$libresoc.v:194972$13477_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire \$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire \$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire \$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire \$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire \$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire \$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire \$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" wire \$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" wire \$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" wire \$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" - wire width 32 \$139 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 \$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" - wire width 65 \$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339" - wire width 4 \$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" - wire width 65 \$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - wire \$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" - wire width 32 \$150 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 \$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" - wire width 32 \$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - wire width 65 \$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - wire width 65 \$156 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 \$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + wire \$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + wire \$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + wire \$143 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:379" + wire \$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + wire \$149 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:382" + wire width 3 \$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + wire \$155 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" + wire width 3 \$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" wire \$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" wire \$163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" wire \$165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - wire \$167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" - wire width 32 \$169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - wire width 65 \$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - wire width 65 \$171 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 \$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" - wire \$176 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" - wire width 3 \$179 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$182 + wire width 64 \$167 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$184 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - wire width 64 \$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" - wire width 65 \$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" - wire width 65 \$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" - wire width 65 \$192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" - wire width 65 \$193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + wire width 64 \$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:638" + wire width 65 \$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:638" + wire width 65 \$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" + wire width 65 \$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" + wire width 65 \$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:452" wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453" wire width 3 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453" wire width 3 \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:232" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:481" wire \$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:495" wire \$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:417" - wire \$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:417" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328" wire \$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - wire \$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" - wire width 65 \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" - wire width 65 \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + wire width 65 \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + wire width 65 \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" + wire width 32 \$75 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213" + wire width 65 \$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:212" + wire width 4 \$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213" + wire width 65 \$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + wire \$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" + wire width 32 \$86 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:53" + wire width 32 \$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire width 65 \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + wire width 65 \$92 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 342 \TAP_bus__tck @@ -412959,15 +403926,15 @@ module \ti wire output 333 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" wire input 343 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:123" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:127" wire output 3 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 392 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:122" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:126" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:90" wire \core_bigendian_i$10 @@ -413237,9 +404204,9 @@ module \ti wire width 7 \core_core_maxvl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" wire width 7 \core_core_maxvl$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \core_core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \core_core_pc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \core_core_reg1 @@ -413335,7 +404302,8 @@ module \ti attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -413456,7 +404424,8 @@ module \ti attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -413531,7 +404500,7 @@ module \ti wire width 3 \core_core_xer_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:95" wire \core_corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire \core_coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_cr_out_ok @@ -413549,9 +404518,21 @@ module \ti wire width 64 \core_data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_data_i$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:12" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 \core_dbg_core_dbg_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 \core_dbg_core_dbg_maxvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 \core_dbg_core_dbg_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 \core_dbg_core_dbg_subvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 \core_dbg_core_dbg_svstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 \core_dbg_core_dbg_vl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \core_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:12" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \core_dec$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \core_dmi__addr @@ -413563,9 +404544,9 @@ module \ti wire \core_ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_ea_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \core_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \core_eint$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_fasto1_ok @@ -413599,9 +404580,9 @@ module \ti wire \core_issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" wire \core_ivalid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \core_msr$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \core_msr__data_o @@ -413627,7 +404608,7 @@ module \ti wire width 64 \core_sv__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_sv__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire \core_wb_dcache_en attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \core_wen @@ -413637,7 +404618,7 @@ module \ti wire \core_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 2 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly @@ -413665,21 +404646,21 @@ module \ti wire width 7 \cur_cur_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \cur_cur_vl$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:587" wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:443" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:463" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" wire \d_xer_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \dbg_core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \dbg_core_dbg_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" wire \dbg_core_rst_o @@ -413781,25 +404762,25 @@ module \ti wire width 7 \dec2_cur_cur_srcstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" wire width 7 \dec2_cur_cur_srcstep$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:12" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \dec2_cur_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:12" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" wire width 64 \dec2_cur_dec$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \dec2_cur_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" wire \dec2_cur_eint$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \dec2_cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" wire width 64 \dec2_cur_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \dec2_cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" wire width 64 \dec2_cur_pc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 9 \dec2_dec_svp64__extra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 9 \dec2_dec_svp64__extra$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \dec2_ea @@ -413949,6 +404930,8 @@ module \ti wire \dec2_oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" wire width 32 \dec2_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 \dec2_raw_opcode_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \dec2_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -414035,7 +405018,8 @@ module \ti attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -414152,7 +405136,8 @@ module \ti attribute \enum_value_0110111110 "TIR" attribute \enum_value_0111010000 "PTCR" attribute \enum_value_1011000000 "SVSTATE" - attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1011010000 "PRTBL" + attribute \enum_value_1011010001 "SVSRR0" attribute \enum_value_1100000000 "SIER" attribute \enum_value_1100000001 "MMCR2" attribute \enum_value_1100000010 "MMCRA" @@ -414211,33 +405196,33 @@ module \ti wire width 3 \dec2_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 2 \dec_svp64__elwidth - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 2 \dec_svp64__elwidth$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 2 \dec_svp64__ewsrc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 2 \dec_svp64__ewsrc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 3 \dec_svp64__mask - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 3 \dec_svp64__mask$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire \dec_svp64__mmode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire \dec_svp64__mmode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 5 \dec_svp64__mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 5 \dec_svp64__mode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 2 \dec_svp64__subvl - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:30" wire width 2 \dec_svp64__subvl$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" wire width 2 \delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 179 \eint_0__core__i @@ -414251,29 +405236,35 @@ module \ti wire output 181 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + wire \exec_fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + wire \exec_fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537" + wire \exec_insn_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" + wire \exec_insn_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:541" + wire \exec_pc_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:540" + wire \exec_pc_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" wire width 2 \fetch_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" wire width 2 \fetch_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:165" wire width 32 \fetch_insn_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" - wire width 32 \fetch_insn_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:533" wire \fetch_insn_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:532" wire \fetch_insn_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:272" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:529" wire \fetch_pc_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:528" wire \fetch_pc_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - wire width 2 \fsm_state$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - wire width 2 \fsm_state$188$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 188 \gpio_e10__core__i @@ -414511,10 +405502,6 @@ module \ti wire input 387 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 391 \ics_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" - wire width 32 \ilatch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" - wire width 32 \ilatch$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 \imem_a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" @@ -414525,12 +405512,18 @@ module \ti wire width 64 \imem_f_instr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" wire \imem_f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \imem_wb_icache_en - attribute \src "libresoc.v:198206.7-198206.15" + attribute \src "libresoc.v:192544.7-192544.15" wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:476" + wire \insn_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 385 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + wire width 3 \issue_fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + wire width 3 \issue_fsm_state$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" @@ -414563,6 +405556,8 @@ module \ti wire output 337 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 338 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" + wire \jtag_wb_sram_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -414595,9 +405590,9 @@ module \ti wire input 81 \mspi1_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 236 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:250" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" wire \msr_read$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 86 \mtwi_scl__core__o @@ -414615,7 +405610,7 @@ module \ti wire output 239 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 240 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:502" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" wire width 64 \new_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \new_svstate_dststep @@ -414629,29 +405624,29 @@ module \ti wire width 2 \new_svstate_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \new_svstate_vl - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:519" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:515" wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:479" wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:474" wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:474" wire \pc_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 7 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 6 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:120" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:123" wire width 64 output 5 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:193" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:445" wire \por_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 87 \pwm_0__core__o @@ -414661,7 +405656,7 @@ module \ti wire input 88 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 243 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 92 \sd0_clk__core__o @@ -415019,85 +406014,103 @@ module \ti wire input 146 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 301 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 351 \sram4k_0__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 346 \sram4k_0__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 344 \sram4k_0__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 347 \sram4k_0__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 348 \sram4k_0__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 350 \sram4k_0__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 345 \sram4k_0__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 349 \sram4k_0__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 359 \sram4k_1__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 354 \sram4k_1__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 352 \sram4k_1__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 355 \sram4k_1__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 356 \sram4k_1__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 358 \sram4k_1__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 353 \sram4k_1__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 357 \sram4k_1__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 367 \sram4k_2__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 362 \sram4k_2__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 360 \sram4k_2__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 363 \sram4k_2__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 364 \sram4k_2__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 366 \sram4k_2__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 361 \sram4k_2__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 365 \sram4k_2__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire output 375 \sram4k_3__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 9 input 370 \sram4k_3__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 368 \sram4k_3__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 output 371 \sram4k_3__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 64 input 372 \sram4k_3__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire width 8 input 374 \sram4k_3__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 369 \sram4k_3__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" - wire input 373 \sram4k_3__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:251" - wire \sv_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:251" - wire \sv_read$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1311" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_0_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 346 \sram4k_0_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 347 \sram4k_0_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 344 \sram4k_0_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 348 \sram4k_0_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 349 \sram4k_0_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 351 \sram4k_0_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 345 \sram4k_0_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 350 \sram4k_0_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_1_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 354 \sram4k_1_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 355 \sram4k_1_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 352 \sram4k_1_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 356 \sram4k_1_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 357 \sram4k_1_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 359 \sram4k_1_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 353 \sram4k_1_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 358 \sram4k_1_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_2_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 362 \sram4k_2_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 363 \sram4k_2_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 360 \sram4k_2_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 364 \sram4k_2_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 365 \sram4k_2_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 367 \sram4k_2_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 361 \sram4k_2_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 366 \sram4k_2_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" + wire \sram4k_3_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire output 370 \sram4k_3_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 9 input 371 \sram4k_3_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 368 \sram4k_3_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 output 372 \sram4k_3_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 64 input 373 \sram4k_3_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire width 8 input 375 \sram4k_3_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 369 \sram4k_3_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" + wire input 374 \sram4k_3_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:475" + wire \sv_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:475" + wire \sv_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:21" wire \svp64_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:19" wire \svp64_is_svp64_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1308" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:18" wire width 32 \svp64_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_svp64_prefix.py:20" wire width 24 \svp64_svp64_rm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:493" + wire width 64 \svstate + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \svstate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \svstate_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:494" + wire \svstate_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:494" + wire \svstate_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:450" wire \ti_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:426" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:269" wire \update_svstate attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire \xics_icp_core_irq_o @@ -415109,19 +406122,19 @@ module \ti wire width 8 \xics_ics_icp_o_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" - cell $add $add$libresoc.v:200564$13726 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" + cell $add $add$libresoc.v:194944$13448 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 1 parameter \Y_WIDTH 65 - connect \A \dec2_cur_pc - connect \B \$144 - connect \Y $add$libresoc.v:200564$13726_Y + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $add$libresoc.v:194944$13448_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $add $add$libresoc.v:200568$13730 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + cell $add $add$libresoc.v:194964$13469 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -415129,32 +406142,21 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:200568$13730_Y + connect \Y $add$libresoc.v:194964$13469_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" - cell $add $add$libresoc.v:200575$13737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213" + cell $add $add$libresoc.v:194973$13478 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 4 parameter \Y_WIDTH 65 connect \A \dec2_cur_pc - connect \B 3'100 - connect \Y $add$libresoc.v:200575$13737_Y + connect \B \$80 + connect \Y $add$libresoc.v:194973$13478_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" - cell $add $add$libresoc.v:200585$13749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \core_issue__data_o - connect \B 1'1 - connect \Y $add$libresoc.v:200585$13749_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" - cell $add $add$libresoc.v:200611$13775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + cell $add $add$libresoc.v:194977$13482 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -415162,191 +406164,166 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:200611$13775_Y + connect \Y $add$libresoc.v:194977$13482_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200543$13705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + cell $and $and$libresoc.v:194908$13410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$99 - connect \B \$101 - connect \Y $and$libresoc.v:200543$13705_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200547$13709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$107 - connect \B \$109 - connect \Y $and$libresoc.v:200547$13709_Y + connect \A \$97 + connect \B \$99 + connect \Y $and$libresoc.v:194908$13410_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200551$13713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $and $and$libresoc.v:194911$13413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$115 - connect \B \$117 - connect \Y $and$libresoc.v:200551$13713_Y + connect \A \$103 + connect \B \$105 + connect \Y $and$libresoc.v:194911$13413_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200555$13717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + cell $and $and$libresoc.v:194914$13416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$123 - connect \B \$125 - connect \Y $and$libresoc.v:200555$13717_Y + connect \A \$109 + connect \B \$111 + connect \Y $and$libresoc.v:194914$13416_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200558$13720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $and $and$libresoc.v:194917$13419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$129 - connect \B \$131 - connect \Y $and$libresoc.v:200558$13720_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" - cell $and $and$libresoc.v:200579$13741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_state_nia_wen - connect \B 1'1 - connect \Y $and$libresoc.v:200579$13741_Y + connect \A \$115 + connect \B \$117 + connect \Y $and$libresoc.v:194917$13419_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:200592$13756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + cell $and $and$libresoc.v:194920$13422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_cu_st__rel_o - connect \B \$34 - connect \Y $and$libresoc.v:200592$13756_Y + connect \A \$121 + connect \B \$123 + connect \Y $and$libresoc.v:194920$13422_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200600$13764 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $and $and$libresoc.v:194923$13425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$48 - connect \B \$50 - connect \Y $and$libresoc.v:200600$13764_Y + connect \A \$127 + connect \B \$129 + connect \Y $and$libresoc.v:194923$13425_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200603$13767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $and $and$libresoc.v:194929$13431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$54 - connect \B \$56 - connect \Y $and$libresoc.v:200603$13767_Y + connect \A \$139 + connect \B \$141 + connect \Y $and$libresoc.v:194929$13431_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200606$13770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:382" + cell $and $and$libresoc.v:194933$13435 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$60 - connect \B \$62 - connect \Y $and$libresoc.v:200606$13770_Y + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \core_state_nia_wen + connect \B 3'100 + connect \Y $and$libresoc.v:194933$13435_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200609$13773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" + cell $and $and$libresoc.v:194936$13438 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$66 - connect \B \$68 - connect \Y $and$libresoc.v:200609$13773_Y + parameter \Y_WIDTH 3 + connect \A \core_state_nia_wen + connect \B 1'1 + connect \Y $and$libresoc.v:194936$13438_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200614$13778 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:194951$13455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$77 - connect \B \$79 - connect \Y $and$libresoc.v:200614$13778_Y + connect \A \core_cu_st__rel_o + connect \B \$34 + connect \Y $and$libresoc.v:194951$13455_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200618$13782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $and $and$libresoc.v:194957$13462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$85 - connect \B \$87 - connect \Y $and$libresoc.v:200618$13782_Y + connect \A \$44 + connect \B \$46 + connect \Y $and$libresoc.v:194957$13462_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $and $and$libresoc.v:200622$13786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $and $and$libresoc.v:194961$13466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$93 - connect \B \$95 - connect \Y $and$libresoc.v:200622$13786_Y + connect \A \$52 + connect \B \$54 + connect \Y $and$libresoc.v:194961$13466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:200582$13744 + cell $pos $extend$libresoc.v:194941$13443 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:200582$13744_Y + connect \Y $extend$libresoc.v:194941$13443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:200583$13746 + cell $pos $extend$libresoc.v:194942$13445 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:200583$13746_Y + connect \Y $extend$libresoc.v:194942$13445_Y end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:200561$13723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:194954$13458 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $mul$libresoc.v:200561$13723_Y + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \svstate_i + connect \Y $extend$libresoc.v:194954$13458_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:200566$13728 + cell $mul $mul$libresoc.v:194970$13475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415354,32 +406331,32 @@ module \ti parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:200566$13728_Y + connect \Y $mul$libresoc.v:194970$13475_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:200569$13731 + cell $mul $mul$libresoc.v:194975$13480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 7 - connect \A \$155 [2] + connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:200569$13731_Y + connect \Y $mul$libresoc.v:194975$13480_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:200576$13738 + cell $mul $mul$libresoc.v:194978$13483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 6 parameter \Y_WIDTH 7 - connect \A \$170 [2] + connect \A \$91 [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:200576$13738_Y + connect \Y $mul$libresoc.v:194978$13483_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" - cell $ne $ne$libresoc.v:200578$13740 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:379" + cell $ne $ne$libresoc.v:194931$13433 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -415387,10 +406364,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $ne$libresoc.v:200578$13740_Y + connect \Y $ne$libresoc.v:194931$13433_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" - cell $ne $ne$libresoc.v:200586$13750 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:452" + cell $ne $ne$libresoc.v:194945$13449 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -415398,10 +406375,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 - connect \Y $ne$libresoc.v:200586$13750_Y + connect \Y $ne$libresoc.v:194945$13449_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" - cell $ne $ne$libresoc.v:200590$13754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + cell $ne $ne$libresoc.v:194949$13453 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -415409,354 +406386,314 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B \$30 - connect \Y $ne$libresoc.v:200590$13754_Y + connect \Y $ne$libresoc.v:194949$13453_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200541$13703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + cell $not $not$libresoc.v:194907$13409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200541$13703_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194907$13409_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200542$13704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194909$13411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200542$13704_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194909$13411_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" - cell $not $not$libresoc.v:200544$13706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194910$13412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:200544$13706_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194910$13412_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200545$13707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + cell $not $not$libresoc.v:194912$13414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200545$13707_Y + connect \Y $not$libresoc.v:194912$13414_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200546$13708 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + cell $not $not$libresoc.v:194913$13415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200546$13708_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" - cell $not $not$libresoc.v:200548$13710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sv_read - connect \Y $not$libresoc.v:200548$13710_Y + connect \Y $not$libresoc.v:194913$13415_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200549$13711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194915$13417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200549$13711_Y + connect \Y $not$libresoc.v:194915$13417_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200550$13712 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194916$13418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200550$13712_Y + connect \Y $not$libresoc.v:194916$13418_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - cell $not $not$libresoc.v:200552$13714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \svp64_is_svp64_mode - connect \Y $not$libresoc.v:200552$13714_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200553$13715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + cell $not $not$libresoc.v:194918$13420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200553$13715_Y + connect \Y $not$libresoc.v:194918$13420_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200554$13716 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + cell $not $not$libresoc.v:194919$13421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200554$13716_Y + connect \Y $not$libresoc.v:194919$13421_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200556$13718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194921$13423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200556$13718_Y + connect \Y $not$libresoc.v:194921$13423_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200557$13719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194922$13424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200557$13719_Y + connect \Y $not$libresoc.v:194922$13424_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" - cell $not $not$libresoc.v:200559$13721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + cell $not $not$libresoc.v:194924$13426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:200559$13721_Y + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:194924$13426_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" - cell $not $not$libresoc.v:200560$13722 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + cell $not $not$libresoc.v:194925$13427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sv_read - connect \Y $not$libresoc.v:200560$13722_Y + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:194925$13427_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - cell $not $not$libresoc.v:200565$13727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + cell $not $not$libresoc.v:194926$13428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \svp64_is_svp64_mode - connect \Y $not$libresoc.v:200565$13727_Y + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:194926$13428_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - cell $not $not$libresoc.v:200571$13733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194927$13429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:200571$13733_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:194927$13429_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - cell $not $not$libresoc.v:200572$13734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194928$13430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:200572$13734_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:194928$13430_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - cell $not $not$libresoc.v:200573$13735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + cell $not $not$libresoc.v:194932$13434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:200573$13735_Y + connect \Y $not$libresoc.v:194932$13434_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - cell $not $not$libresoc.v:200574$13736 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + cell $not $not$libresoc.v:194935$13437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:200574$13736_Y + connect \Y $not$libresoc.v:194935$13437_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:200591$13755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + cell $not $not$libresoc.v:194938$13440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:200591$13755_Y + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:194938$13440_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:232" - cell $not $not$libresoc.v:200593$13757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + cell $not $not$libresoc.v:194939$13441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \pc_i_ok - connect \Y $not$libresoc.v:200593$13757_Y + connect \A \core_corebusy_o + connect \Y $not$libresoc.v:194939$13441_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - cell $not $not$libresoc.v:200594$13758 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + cell $not $not$libresoc.v:194940$13442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:200594$13758_Y + connect \Y $not$libresoc.v:194940$13442_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:417" - cell $not $not$libresoc.v:200595$13759 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:194950$13454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:200595$13759_Y + connect \A \cu_st__rel_o_dly + connect \Y $not$libresoc.v:194950$13454_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - cell $not $not$libresoc.v:200596$13760 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:481" + cell $not $not$libresoc.v:194952$13456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:200596$13760_Y + connect \A \pc_i_ok + connect \Y $not$libresoc.v:194952$13456_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:417" - cell $not $not$libresoc.v:200597$13761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:495" + cell $not $not$libresoc.v:194953$13457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:200597$13761_Y + connect \A \svstate_i_ok + connect \Y $not$libresoc.v:194953$13457_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200598$13762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194955$13460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200598$13762_Y + connect \Y $not$libresoc.v:194955$13460_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200599$13763 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194956$13461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200599$13763_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200601$13765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200601$13765_Y + connect \Y $not$libresoc.v:194956$13461_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200602$13766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328" + cell $not $not$libresoc.v:194958$13463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200602$13766_Y + connect \A \pc_changed + connect \Y $not$libresoc.v:194958$13463_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200604$13768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194959$13464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200604$13768_Y + connect \Y $not$libresoc.v:194959$13464_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200605$13769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + cell $not $not$libresoc.v:194960$13465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200605$13769_Y + connect \Y $not$libresoc.v:194960$13465_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200607$13771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328" + cell $not $not$libresoc.v:194962$13467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200607$13771_Y + connect \A \pc_changed + connect \Y $not$libresoc.v:194962$13467_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200608$13772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + cell $not $not$libresoc.v:194963$13468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200608$13772_Y + connect \A \svp64_is_svp64_mode + connect \Y $not$libresoc.v:194963$13468_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - cell $not $not$libresoc.v:200610$13774 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + cell $not $not$libresoc.v:194965$13470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svp64_is_svp64_mode - connect \Y $not$libresoc.v:200610$13774_Y + connect \Y $not$libresoc.v:194965$13470_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200612$13776 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + cell $not $not$libresoc.v:194966$13471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200612$13776_Y + connect \A \svp64_is_svp64_mode + connect \Y $not$libresoc.v:194966$13471_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200613$13777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" + cell $not $not$libresoc.v:194967$13472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200613$13777_Y + connect \A \msr_read + connect \Y $not$libresoc.v:194967$13472_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - cell $not $not$libresoc.v:200615$13779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + cell $not $not$libresoc.v:194968$13473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svp64_is_svp64_mode - connect \Y $not$libresoc.v:200615$13779_Y + connect \Y $not$libresoc.v:194968$13473_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200616$13780 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" + cell $not $not$libresoc.v:194969$13474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200616$13780_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200617$13781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200617$13781_Y + connect \A \msr_read + connect \Y $not$libresoc.v:194969$13474_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - cell $not $not$libresoc.v:200619$13783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + cell $not $not$libresoc.v:194974$13479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svp64_is_svp64_mode - connect \Y $not$libresoc.v:200619$13783_Y + connect \Y $not$libresoc.v:194974$13479_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200620$13784 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + cell $not $not$libresoc.v:194980$13485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:200620$13784_Y + connect \Y $not$libresoc.v:194980$13485_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - cell $not $not$libresoc.v:200621$13785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:200621$13785_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" - cell $or $or$libresoc.v:200588$13752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + cell $or $or$libresoc.v:194947$13451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415764,10 +406701,10 @@ module \ti parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:200588$13752_Y + connect \Y $or$libresoc.v:194947$13451_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" - cell $or $or$libresoc.v:200589$13753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:458" + cell $or $or$libresoc.v:194948$13452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415775,86 +406712,91 @@ module \ti parameter \Y_WIDTH 1 connect \A \$28 connect \B \rst - connect \Y $or$libresoc.v:200589$13753_Y + connect \Y $or$libresoc.v:194948$13452_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:200581$13743 + cell $pos $pos$libresoc.v:194930$13432 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } - connect \Y $pos$libresoc.v:200581$13743_Y + connect \Y $pos$libresoc.v:194930$13432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:200582$13745 + cell $pos $pos$libresoc.v:194941$13444 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:200582$13744_Y - connect \Y $pos$libresoc.v:200582$13745_Y + connect \A $extend$libresoc.v:194941$13443_Y + connect \Y $pos$libresoc.v:194941$13444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:200583$13747 + cell $pos $pos$libresoc.v:194942$13446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:194942$13445_Y + connect \Y $pos$libresoc.v:194942$13446_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:194954$13459 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:200583$13746_Y - connect \Y $pos$libresoc.v:200583$13747_Y + connect \A $extend$libresoc.v:194954$13458_Y + connect \Y $pos$libresoc.v:194954$13459_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:200580$13742 + cell $reduce_or $reduce_or$libresoc.v:194934$13436 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$179 - connect \Y $reduce_or$libresoc.v:200580$13742_Y + connect \A \$152 + connect \Y $reduce_or$libresoc.v:194934$13436_Y end - attribute \src "libresoc.v:200562.19-200562.42" - cell $shr $shr$libresoc.v:200562$13724 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:194937$13439 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \imem_f_instr_o - connect \B \$140 - connect \Y $shr$libresoc.v:200562$13724_Y + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$158 + connect \Y $reduce_or$libresoc.v:194937$13439_Y end - attribute \src "libresoc.v:200567.19-200567.42" - cell $shr $shr$libresoc.v:200567$13729 + attribute \src "libresoc.v:194971.18-194971.40" + cell $shr $shr$libresoc.v:194971$13476 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 64 connect \A \imem_f_instr_o - connect \B \$151 - connect \Y $shr$libresoc.v:200567$13729_Y + connect \B \$76 + connect \Y $shr$libresoc.v:194971$13476_Y end - attribute \src "libresoc.v:200570.19-200570.42" - cell $shr $shr$libresoc.v:200570$13732 + attribute \src "libresoc.v:194976.18-194976.40" + cell $shr $shr$libresoc.v:194976$13481 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 64 connect \A \imem_f_instr_o - connect \B \$158 - connect \Y $shr$libresoc.v:200570$13732_Y + connect \B \$87 + connect \Y $shr$libresoc.v:194976$13481_Y end - attribute \src "libresoc.v:200577.19-200577.42" - cell $shr $shr$libresoc.v:200577$13739 + attribute \src "libresoc.v:194979.18-194979.40" + cell $shr $shr$libresoc.v:194979$13484 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 64 connect \A \imem_f_instr_o - connect \B \$173 - connect \Y $shr$libresoc.v:200577$13739_Y + connect \B \$94 + connect \Y $shr$libresoc.v:194979$13484_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" - cell $sub $sub$libresoc.v:200584$13748 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:638" + cell $sub $sub$libresoc.v:194943$13447 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -415862,10 +406804,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $sub$libresoc.v:200584$13748_Y + connect \Y $sub$libresoc.v:194943$13447_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" - cell $sub $sub$libresoc.v:200587$13751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:453" + cell $sub $sub$libresoc.v:194946$13450 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -415873,18 +406815,18 @@ module \ti parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $sub$libresoc.v:200587$13751_Y + connect \Y $sub$libresoc.v:194946$13450_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339" - cell $mux $ternary$libresoc.v:200563$13725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:212" + cell $mux $ternary$libresoc.v:194972$13477 parameter \WIDTH 4 connect \A 4'0100 connect \B 4'1000 connect \S \svp64_is_svp64_mode - connect \Y $ternary$libresoc.v:200563$13725_Y + connect \Y $ternary$libresoc.v:194972$13477_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:200841.8-200938.4" + attribute \src "libresoc.v:195201.8-195298.4" cell \core \core connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o @@ -415984,7 +406926,7 @@ module \ti connect \wen$10 \core_wen$11 end attribute \module_not_derived 1 - attribute \src "libresoc.v:200939.7-200964.4" + attribute \src "libresoc.v:195299.7-195324.4" cell \dbg \dbg connect \clk \clk connect \core_dbg_msr \dbg_core_dbg_msr @@ -416012,7 +406954,7 @@ module \ti connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:200965.8-201033.4" + attribute \src "libresoc.v:195325.8-195393.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian @@ -416083,7 +407025,7 @@ module \ti connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:201034.8-201050.4" + attribute \src "libresoc.v:195394.8-195410.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i @@ -416102,7 +407044,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:201051.8-201382.4" + attribute \src "libresoc.v:195411.8-195743.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -416434,65 +407376,70 @@ module \ti connect \sdr_we_n__pad__o \sdr_we_n__pad__o connect \wb_dcache_en \core_wb_dcache_en connect \wb_icache_en \imem_wb_icache_en + connect \wb_sram_en \jtag_wb_sram_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:201383.12-201394.4" + attribute \src "libresoc.v:195744.12-195756.4" cell \sram4k_0 \sram4k_0 connect \clk \clk + connect \enable \sram4k_0_enable connect \rst \rst - connect \sram4k_0__ack \sram4k_0__ack - connect \sram4k_0__adr \sram4k_0__adr - connect \sram4k_0__cyc \sram4k_0__cyc - connect \sram4k_0__dat_r \sram4k_0__dat_r - connect \sram4k_0__dat_w \sram4k_0__dat_w - connect \sram4k_0__sel \sram4k_0__sel - connect \sram4k_0__stb \sram4k_0__stb - connect \sram4k_0__we \sram4k_0__we + connect \sram4k_0_wb__ack \sram4k_0_wb__ack + connect \sram4k_0_wb__adr \sram4k_0_wb__adr + connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc + connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r + connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w + connect \sram4k_0_wb__sel \sram4k_0_wb__sel + connect \sram4k_0_wb__stb \sram4k_0_wb__stb + connect \sram4k_0_wb__we \sram4k_0_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:201395.12-201406.4" + attribute \src "libresoc.v:195757.12-195769.4" cell \sram4k_1 \sram4k_1 connect \clk \clk + connect \enable \sram4k_1_enable connect \rst \rst - connect \sram4k_1__ack \sram4k_1__ack - connect \sram4k_1__adr \sram4k_1__adr - connect \sram4k_1__cyc \sram4k_1__cyc - connect \sram4k_1__dat_r \sram4k_1__dat_r - connect \sram4k_1__dat_w \sram4k_1__dat_w - connect \sram4k_1__sel \sram4k_1__sel - connect \sram4k_1__stb \sram4k_1__stb - connect \sram4k_1__we \sram4k_1__we + connect \sram4k_1_wb__ack \sram4k_1_wb__ack + connect \sram4k_1_wb__adr \sram4k_1_wb__adr + connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc + connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r + connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w + connect \sram4k_1_wb__sel \sram4k_1_wb__sel + connect \sram4k_1_wb__stb \sram4k_1_wb__stb + connect \sram4k_1_wb__we \sram4k_1_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:201407.12-201418.4" + attribute \src "libresoc.v:195770.12-195782.4" cell \sram4k_2 \sram4k_2 connect \clk \clk + connect \enable \sram4k_2_enable connect \rst \rst - connect \sram4k_2__ack \sram4k_2__ack - connect \sram4k_2__adr \sram4k_2__adr - connect \sram4k_2__cyc \sram4k_2__cyc - connect \sram4k_2__dat_r \sram4k_2__dat_r - connect \sram4k_2__dat_w \sram4k_2__dat_w - connect \sram4k_2__sel \sram4k_2__sel - connect \sram4k_2__stb \sram4k_2__stb - connect \sram4k_2__we \sram4k_2__we + connect \sram4k_2_wb__ack \sram4k_2_wb__ack + connect \sram4k_2_wb__adr \sram4k_2_wb__adr + connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc + connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r + connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w + connect \sram4k_2_wb__sel \sram4k_2_wb__sel + connect \sram4k_2_wb__stb \sram4k_2_wb__stb + connect \sram4k_2_wb__we \sram4k_2_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:201419.12-201430.4" + attribute \src "libresoc.v:195783.12-195795.4" cell \sram4k_3 \sram4k_3 connect \clk \clk + connect \enable \sram4k_3_enable connect \rst \rst - connect \sram4k_3__ack \sram4k_3__ack - connect \sram4k_3__adr \sram4k_3__adr - connect \sram4k_3__cyc \sram4k_3__cyc - connect \sram4k_3__dat_r \sram4k_3__dat_r - connect \sram4k_3__dat_w \sram4k_3__dat_w - connect \sram4k_3__sel \sram4k_3__sel - connect \sram4k_3__stb \sram4k_3__stb - connect \sram4k_3__we \sram4k_3__we + connect \sram4k_3_wb__ack \sram4k_3_wb__ack + connect \sram4k_3_wb__adr \sram4k_3_wb__adr + connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc + connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r + connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w + connect \sram4k_3_wb__sel \sram4k_3_wb__sel + connect \sram4k_3_wb__stb \sram4k_3_wb__stb + connect \sram4k_3_wb__we \sram4k_3_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:201431.9-201436.4" + attribute \src "libresoc.v:195796.9-195801.4" cell \svp64 \svp64 connect \bigendian \svp64_bigendian connect \is_svp64_mode \svp64_is_svp64_mode @@ -416500,7 +407447,7 @@ module \ti connect \svp64_rm \svp64_svp64_rm end attribute \module_not_derived 1 - attribute \src "libresoc.v:201437.12-201451.4" + attribute \src "libresoc.v:195802.12-195816.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o @@ -416517,7 +407464,7 @@ module \ti connect \rst \rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:201452.12-201465.4" + attribute \src "libresoc.v:195817.12-195830.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri @@ -416532,1657 +407479,1695 @@ module \ti connect \int_level_i \int_level_i connect \rst \rst end - attribute \src "libresoc.v:198206.7-198206.20" - process $proc$libresoc.v:198206$14430 + attribute \src "libresoc.v:192544.7-192544.20" + process $proc$libresoc.v:192544$14201 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:198398.13-198398.33" - process $proc$libresoc.v:198398$14431 + attribute \src "libresoc.v:192718.13-192718.33" + process $proc$libresoc.v:192718$14202 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "libresoc.v:198404.7-198404.35" - process $proc$libresoc.v:198404$14432 + attribute \src "libresoc.v:192724.7-192724.35" + process $proc$libresoc.v:192724$14203 assign { } { } - assign $0\core_bigendian_i$10[0:0]$14433 1'0 + assign $0\core_bigendian_i$10[0:0]$14204 1'0 sync always sync init - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14433 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14204 end - attribute \src "libresoc.v:198412.14-198412.55" - process $proc$libresoc.v:198412$14434 + attribute \src "libresoc.v:192732.14-192732.55" + process $proc$libresoc.v:192732$14205 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:198416.13-198416.41" - process $proc$libresoc.v:198416$14435 + attribute \src "libresoc.v:192736.13-192736.41" + process $proc$libresoc.v:192736$14206 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:198420.7-198420.37" - process $proc$libresoc.v:198420$14436 + attribute \src "libresoc.v:192740.7-192740.37" + process $proc$libresoc.v:192740$14207 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:198424.13-198424.41" - process $proc$libresoc.v:198424$14437 + attribute \src "libresoc.v:192744.13-192744.41" + process $proc$libresoc.v:192744$14208 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:198428.7-198428.42" - process $proc$libresoc.v:198428$14438 + attribute \src "libresoc.v:192748.7-192748.42" + process $proc$libresoc.v:192748$14209 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$14439 1'0 + assign $0\core_core_core_exc_$signal[0:0]$14210 1'0 sync always sync init - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14439 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14210 end - attribute \src "libresoc.v:198430.7-198430.44" - process $proc$libresoc.v:198430$14440 + attribute \src "libresoc.v:192750.7-192750.44" + process $proc$libresoc.v:192750$14211 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$14441 1'0 + assign $0\core_core_core_exc_$signal$3[0:0]$14212 1'0 sync always sync init - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14441 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14212 end - attribute \src "libresoc.v:198434.7-198434.44" - process $proc$libresoc.v:198434$14442 + attribute \src "libresoc.v:192754.7-192754.44" + process $proc$libresoc.v:192754$14213 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$14443 1'0 + assign $0\core_core_core_exc_$signal$4[0:0]$14214 1'0 sync always sync init - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14443 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14214 end - attribute \src "libresoc.v:198438.7-198438.44" - process $proc$libresoc.v:198438$14444 + attribute \src "libresoc.v:192758.7-192758.44" + process $proc$libresoc.v:192758$14215 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$14445 1'0 + assign $0\core_core_core_exc_$signal$5[0:0]$14216 1'0 sync always sync init - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14445 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14216 end - attribute \src "libresoc.v:198442.7-198442.44" - process $proc$libresoc.v:198442$14446 + attribute \src "libresoc.v:192762.7-192762.44" + process $proc$libresoc.v:192762$14217 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$14447 1'0 + assign $0\core_core_core_exc_$signal$6[0:0]$14218 1'0 sync always sync init - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14447 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14218 end - attribute \src "libresoc.v:198446.7-198446.44" - process $proc$libresoc.v:198446$14448 + attribute \src "libresoc.v:192766.7-192766.44" + process $proc$libresoc.v:192766$14219 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$14449 1'0 + assign $0\core_core_core_exc_$signal$7[0:0]$14220 1'0 sync always sync init - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14449 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14220 end - attribute \src "libresoc.v:198450.7-198450.44" - process $proc$libresoc.v:198450$14450 + attribute \src "libresoc.v:192770.7-192770.44" + process $proc$libresoc.v:192770$14221 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$14451 1'0 + assign $0\core_core_core_exc_$signal$8[0:0]$14222 1'0 sync always sync init - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14451 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14222 end - attribute \src "libresoc.v:198454.7-198454.44" - process $proc$libresoc.v:198454$14452 + attribute \src "libresoc.v:192774.7-192774.44" + process $proc$libresoc.v:192774$14223 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$14453 1'0 + assign $0\core_core_core_exc_$signal$9[0:0]$14224 1'0 sync always sync init - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14453 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14224 end - attribute \src "libresoc.v:198474.14-198474.47" - process $proc$libresoc.v:198474$14454 + attribute \src "libresoc.v:192794.14-192794.47" + process $proc$libresoc.v:192794$14225 assign { } { } assign $1\core_core_core_fn_unit[12:0] 13'0000000000000 sync always sync init update \core_core_core_fn_unit $1\core_core_core_fn_unit[12:0] end - attribute \src "libresoc.v:198482.13-198482.46" - process $proc$libresoc.v:198482$14455 + attribute \src "libresoc.v:192802.13-192802.46" + process $proc$libresoc.v:192802$14226 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:198486.14-198486.41" - process $proc$libresoc.v:198486$14456 + attribute \src "libresoc.v:192806.14-192806.41" + process $proc$libresoc.v:192806$14227 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "libresoc.v:198564.13-198564.45" - process $proc$libresoc.v:198564$14457 + attribute \src "libresoc.v:192884.13-192884.45" + process $proc$libresoc.v:192884$14228 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:198568.7-198568.37" - process $proc$libresoc.v:198568$14458 + attribute \src "libresoc.v:192888.7-192888.37" + process $proc$libresoc.v:192888$14229 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:198572.14-198572.55" - process $proc$libresoc.v:198572$14459 + attribute \src "libresoc.v:192892.14-192892.55" + process $proc$libresoc.v:192892$14230 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end - attribute \src "libresoc.v:198576.7-198576.31" - process $proc$libresoc.v:198576$14460 + attribute \src "libresoc.v:192896.7-192896.31" + process $proc$libresoc.v:192896$14231 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end - attribute \src "libresoc.v:198580.7-198580.34" - process $proc$libresoc.v:198580$14461 + attribute \src "libresoc.v:192900.7-192900.34" + process $proc$libresoc.v:192900$14232 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:198584.7-198584.31" - process $proc$libresoc.v:198584$14462 + attribute \src "libresoc.v:192904.7-192904.31" + process $proc$libresoc.v:192904$14233 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end - attribute \src "libresoc.v:198588.7-198588.34" - process $proc$libresoc.v:198588$14463 + attribute \src "libresoc.v:192908.7-192908.34" + process $proc$libresoc.v:192908$14234 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:198592.14-198592.48" - process $proc$libresoc.v:198592$14464 + attribute \src "libresoc.v:192912.14-192912.48" + process $proc$libresoc.v:192912$14235 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:198596.13-198596.44" - process $proc$libresoc.v:198596$14465 + attribute \src "libresoc.v:192916.13-192916.44" + process $proc$libresoc.v:192916$14236 assign { } { } assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init update \core_core_core_traptype $1\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:198600.13-198600.37" - process $proc$libresoc.v:198600$14466 + attribute \src "libresoc.v:192920.13-192920.37" + process $proc$libresoc.v:192920$14237 assign { } { } assign $1\core_core_cr_in1[6:0] 7'0000000 sync always sync init update \core_core_cr_in1 $1\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:198604.7-198604.33" - process $proc$libresoc.v:198604$14467 + attribute \src "libresoc.v:192924.7-192924.33" + process $proc$libresoc.v:192924$14238 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:198608.13-198608.37" - process $proc$libresoc.v:198608$14468 + attribute \src "libresoc.v:192928.13-192928.37" + process $proc$libresoc.v:192928$14239 assign { } { } assign $1\core_core_cr_in2[6:0] 7'0000000 sync always sync init update \core_core_cr_in2 $1\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:198610.13-198610.41" - process $proc$libresoc.v:198610$14469 + attribute \src "libresoc.v:192930.13-192930.41" + process $proc$libresoc.v:192930$14240 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$14470 7'0000000 + assign $0\core_core_cr_in2$1[6:0]$14241 7'0000000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14470 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14241 end - attribute \src "libresoc.v:198616.7-198616.33" - process $proc$libresoc.v:198616$14471 + attribute \src "libresoc.v:192936.7-192936.33" + process $proc$libresoc.v:192936$14242 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:198618.7-198618.37" - process $proc$libresoc.v:198618$14472 + attribute \src "libresoc.v:192938.7-192938.37" + process $proc$libresoc.v:192938$14243 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$14473 1'0 + assign $0\core_core_cr_in2_ok$2[0:0]$14244 1'0 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14473 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14244 end - attribute \src "libresoc.v:198624.13-198624.37" - process $proc$libresoc.v:198624$14474 + attribute \src "libresoc.v:192944.13-192944.37" + process $proc$libresoc.v:192944$14245 assign { } { } assign $1\core_core_cr_out[6:0] 7'0000000 sync always sync init update \core_core_cr_out $1\core_core_cr_out[6:0] end - attribute \src "libresoc.v:198628.7-198628.32" - process $proc$libresoc.v:198628$14475 + attribute \src "libresoc.v:192948.7-192948.32" + process $proc$libresoc.v:192948$14246 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:198632.13-198632.38" - process $proc$libresoc.v:198632$14476 + attribute \src "libresoc.v:192952.13-192952.38" + process $proc$libresoc.v:192952$14247 assign { } { } assign $1\core_core_dststep[6:0] 7'0000000 sync always sync init update \core_core_dststep $1\core_core_dststep[6:0] end - attribute \src "libresoc.v:198636.13-198636.33" - process $proc$libresoc.v:198636$14477 + attribute \src "libresoc.v:192956.13-192956.33" + process $proc$libresoc.v:192956$14248 assign { } { } assign $1\core_core_ea[6:0] 7'0000000 sync always sync init update \core_core_ea $1\core_core_ea[6:0] end - attribute \src "libresoc.v:198640.13-198640.35" - process $proc$libresoc.v:198640$14478 + attribute \src "libresoc.v:192960.13-192960.35" + process $proc$libresoc.v:192960$14249 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end - attribute \src "libresoc.v:198644.7-198644.32" - process $proc$libresoc.v:198644$14479 + attribute \src "libresoc.v:192964.7-192964.32" + process $proc$libresoc.v:192964$14250 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:198648.13-198648.35" - process $proc$libresoc.v:198648$14480 + attribute \src "libresoc.v:192968.13-192968.35" + process $proc$libresoc.v:192968$14251 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "libresoc.v:198652.7-198652.32" - process $proc$libresoc.v:198652$14481 + attribute \src "libresoc.v:192972.7-192972.32" + process $proc$libresoc.v:192972$14252 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:198656.13-198656.36" - process $proc$libresoc.v:198656$14482 + attribute \src "libresoc.v:192976.13-192976.36" + process $proc$libresoc.v:192976$14253 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "libresoc.v:198660.13-198660.36" - process $proc$libresoc.v:198660$14483 + attribute \src "libresoc.v:192980.13-192980.36" + process $proc$libresoc.v:192980$14254 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:198664.7-198664.26" - process $proc$libresoc.v:198664$14484 + attribute \src "libresoc.v:192984.7-192984.26" + process $proc$libresoc.v:192984$14255 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:198668.13-198668.36" - process $proc$libresoc.v:198668$14485 + attribute \src "libresoc.v:192988.13-192988.36" + process $proc$libresoc.v:192988$14256 assign { } { } assign $1\core_core_maxvl[6:0] 7'0000000 sync always sync init update \core_core_maxvl $1\core_core_maxvl[6:0] end - attribute \src "libresoc.v:198672.14-198672.49" - process $proc$libresoc.v:198672$14486 + attribute \src "libresoc.v:192992.14-192992.49" + process $proc$libresoc.v:192992$14257 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "libresoc.v:198676.13-198676.35" - process $proc$libresoc.v:198676$14487 + attribute \src "libresoc.v:192996.13-192996.35" + process $proc$libresoc.v:192996$14258 assign { } { } assign $1\core_core_reg1[6:0] 7'0000000 sync always sync init update \core_core_reg1 $1\core_core_reg1[6:0] end - attribute \src "libresoc.v:198680.7-198680.31" - process $proc$libresoc.v:198680$14488 + attribute \src "libresoc.v:193000.7-193000.31" + process $proc$libresoc.v:193000$14259 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:198684.13-198684.35" - process $proc$libresoc.v:198684$14489 + attribute \src "libresoc.v:193004.13-193004.35" + process $proc$libresoc.v:193004$14260 assign { } { } assign $1\core_core_reg2[6:0] 7'0000000 sync always sync init update \core_core_reg2 $1\core_core_reg2[6:0] end - attribute \src "libresoc.v:198688.7-198688.31" - process $proc$libresoc.v:198688$14490 + attribute \src "libresoc.v:193008.7-193008.31" + process $proc$libresoc.v:193008$14261 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:198692.13-198692.35" - process $proc$libresoc.v:198692$14491 + attribute \src "libresoc.v:193012.13-193012.35" + process $proc$libresoc.v:193012$14262 assign { } { } assign $1\core_core_reg3[6:0] 7'0000000 sync always sync init update \core_core_reg3 $1\core_core_reg3[6:0] end - attribute \src "libresoc.v:198696.7-198696.31" - process $proc$libresoc.v:198696$14492 + attribute \src "libresoc.v:193016.7-193016.31" + process $proc$libresoc.v:193016$14263 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:198700.13-198700.35" - process $proc$libresoc.v:198700$14493 + attribute \src "libresoc.v:193020.13-193020.35" + process $proc$libresoc.v:193020$14264 assign { } { } assign $1\core_core_rego[6:0] 7'0000000 sync always sync init update \core_core_rego $1\core_core_rego[6:0] end - attribute \src "libresoc.v:198817.13-198817.37" - process $proc$libresoc.v:198817$14494 + attribute \src "libresoc.v:193138.13-193138.37" + process $proc$libresoc.v:193138$14265 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "libresoc.v:198821.7-198821.31" - process $proc$libresoc.v:198821$14495 + attribute \src "libresoc.v:193142.7-193142.31" + process $proc$libresoc.v:193142$14266 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:198938.13-198938.37" - process $proc$libresoc.v:198938$14496 + attribute \src "libresoc.v:193260.13-193260.37" + process $proc$libresoc.v:193260$14267 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "libresoc.v:198942.13-198942.38" - process $proc$libresoc.v:198942$14497 + attribute \src "libresoc.v:193264.13-193264.38" + process $proc$libresoc.v:193264$14268 assign { } { } assign $1\core_core_srcstep[6:0] 7'0000000 sync always sync init update \core_core_srcstep $1\core_core_srcstep[6:0] end - attribute \src "libresoc.v:198946.13-198946.35" - process $proc$libresoc.v:198946$14498 + attribute \src "libresoc.v:193268.13-193268.35" + process $proc$libresoc.v:193268$14269 assign { } { } assign $1\core_core_subvl[1:0] 2'00 sync always sync init update \core_core_subvl $1\core_core_subvl[1:0] end - attribute \src "libresoc.v:198950.13-198950.36" - process $proc$libresoc.v:198950$14499 + attribute \src "libresoc.v:193272.13-193272.36" + process $proc$libresoc.v:193272$14270 assign { } { } assign $1\core_core_svstep[1:0] 2'00 sync always sync init update \core_core_svstep $1\core_core_svstep[1:0] end - attribute \src "libresoc.v:198956.13-198956.33" - process $proc$libresoc.v:198956$14500 + attribute \src "libresoc.v:193278.13-193278.33" + process $proc$libresoc.v:193278$14271 assign { } { } assign $1\core_core_vl[6:0] 7'0000000 sync always sync init update \core_core_vl $1\core_core_vl[6:0] end - attribute \src "libresoc.v:198960.13-198960.36" - process $proc$libresoc.v:198960$14501 + attribute \src "libresoc.v:193282.13-193282.36" + process $proc$libresoc.v:193282$14272 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "libresoc.v:198968.7-198968.28" - process $proc$libresoc.v:198968$14502 + attribute \src "libresoc.v:193290.7-193290.28" + process $proc$libresoc.v:193290$14273 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:198984.14-198984.45" - process $proc$libresoc.v:198984$14503 + attribute \src "libresoc.v:193318.14-193318.45" + process $proc$libresoc.v:193318$14274 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end - attribute \src "libresoc.v:198994.7-198994.24" - process $proc$libresoc.v:198994$14504 + attribute \src "libresoc.v:193328.7-193328.24" + process $proc$libresoc.v:193328$14275 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "libresoc.v:198998.7-198998.23" - process $proc$libresoc.v:198998$14505 + attribute \src "libresoc.v:193332.7-193332.23" + process $proc$libresoc.v:193332$14276 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end - attribute \src "libresoc.v:199002.7-199002.28" - process $proc$libresoc.v:199002$14506 + attribute \src "libresoc.v:193336.7-193336.28" + process $proc$libresoc.v:193336$14277 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:199006.7-199006.28" - process $proc$libresoc.v:199006$14507 + attribute \src "libresoc.v:193340.7-193340.28" + process $proc$libresoc.v:193340$14278 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:199034.14-199034.45" - process $proc$libresoc.v:199034$14508 + attribute \src "libresoc.v:193368.14-193368.45" + process $proc$libresoc.v:193368$14279 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:199042.14-199042.37" - process $proc$libresoc.v:199042$14509 + attribute \src "libresoc.v:193376.14-193376.37" + process $proc$libresoc.v:193376$14280 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:199046.7-199046.26" - process $proc$libresoc.v:199046$14510 + attribute \src "libresoc.v:193380.7-193380.26" + process $proc$libresoc.v:193380$14281 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:199050.7-199050.26" - process $proc$libresoc.v:199050$14511 + attribute \src "libresoc.v:193384.7-193384.26" + process $proc$libresoc.v:193384$14282 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:199068.7-199068.26" - process $proc$libresoc.v:199068$14512 + attribute \src "libresoc.v:193402.7-193402.26" + process $proc$libresoc.v:193402$14283 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:199074.7-199074.30" - process $proc$libresoc.v:199074$14513 + attribute \src "libresoc.v:193408.7-193408.30" + process $proc$libresoc.v:193408$14284 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:199080.13-199080.36" - process $proc$libresoc.v:199080$14514 + attribute \src "libresoc.v:193414.13-193414.36" + process $proc$libresoc.v:193414$14285 assign { } { } assign $1\cur_cur_dststep[6:0] 7'0000000 sync always sync init update \cur_cur_dststep $1\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:199084.13-199084.34" - process $proc$libresoc.v:199084$14515 + attribute \src "libresoc.v:193418.13-193418.34" + process $proc$libresoc.v:193418$14286 assign { } { } assign $1\cur_cur_maxvl[6:0] 7'0000000 sync always sync init update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:199088.13-199088.33" - process $proc$libresoc.v:199088$14516 + attribute \src "libresoc.v:193422.13-193422.33" + process $proc$libresoc.v:193422$14287 assign { } { } assign $1\cur_cur_subvl[1:0] 2'00 sync always sync init update \cur_cur_subvl $1\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:199092.13-199092.34" - process $proc$libresoc.v:199092$14517 + attribute \src "libresoc.v:193426.13-193426.34" + process $proc$libresoc.v:193426$14288 assign { } { } assign $1\cur_cur_svstep[1:0] 2'00 sync always sync init update \cur_cur_svstep $1\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:199096.13-199096.31" - process $proc$libresoc.v:199096$14518 + attribute \src "libresoc.v:193430.13-193430.31" + process $proc$libresoc.v:193430$14289 assign { } { } assign $1\cur_cur_vl[6:0] 7'0000000 sync always sync init update \cur_cur_vl $1\cur_cur_vl[6:0] end - attribute \src "libresoc.v:199100.7-199100.24" - process $proc$libresoc.v:199100$14519 + attribute \src "libresoc.v:193434.7-193434.24" + process $proc$libresoc.v:193434$14290 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:199104.7-199104.25" - process $proc$libresoc.v:199104$14520 + attribute \src "libresoc.v:193438.7-193438.25" + process $proc$libresoc.v:193438$14291 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:199108.7-199108.25" - process $proc$libresoc.v:199108$14521 + attribute \src "libresoc.v:193442.7-193442.25" + process $proc$libresoc.v:193442$14292 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:199144.13-199144.34" - process $proc$libresoc.v:199144$14522 + attribute \src "libresoc.v:193478.13-193478.34" + process $proc$libresoc.v:193478$14293 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:199148.14-199148.48" - process $proc$libresoc.v:199148$14523 + attribute \src "libresoc.v:193482.14-193482.48" + process $proc$libresoc.v:193482$14294 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:199154.7-199154.27" - process $proc$libresoc.v:199154$14524 + attribute \src "libresoc.v:193488.7-193488.27" + process $proc$libresoc.v:193488$14295 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:199158.7-199158.26" - process $proc$libresoc.v:199158$14525 + attribute \src "libresoc.v:193492.7-193492.26" + process $proc$libresoc.v:193492$14296 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:199212.13-199212.41" - process $proc$libresoc.v:199212$14526 + attribute \src "libresoc.v:193546.13-193546.41" + process $proc$libresoc.v:193546$14297 assign { } { } assign $1\dec2_cur_cur_srcstep[6:0] 7'0000000 sync always sync init update \dec2_cur_cur_srcstep $1\dec2_cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:199216.14-199216.49" - process $proc$libresoc.v:199216$14527 + attribute \src "libresoc.v:193550.14-193550.49" + process $proc$libresoc.v:193550$14298 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:199220.7-199220.27" - process $proc$libresoc.v:199220$14528 + attribute \src "libresoc.v:193554.7-193554.27" + process $proc$libresoc.v:193554$14299 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:199224.14-199224.49" - process $proc$libresoc.v:199224$14529 + attribute \src "libresoc.v:193558.14-193558.49" + process $proc$libresoc.v:193558$14300 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:199228.14-199228.48" - process $proc$libresoc.v:199228$14530 + attribute \src "libresoc.v:193562.14-193562.48" + process $proc$libresoc.v:193562$14301 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:199232.13-199232.43" - process $proc$libresoc.v:199232$14531 + attribute \src "libresoc.v:193566.13-193566.43" + process $proc$libresoc.v:193566$14302 assign { } { } assign $1\dec2_dec_svp64__extra[8:0] 9'000000000 sync always sync init update \dec2_dec_svp64__extra $1\dec2_dec_svp64__extra[8:0] end - attribute \src "libresoc.v:199646.13-199646.38" - process $proc$libresoc.v:199646$14532 + attribute \src "libresoc.v:193716.14-193716.40" + process $proc$libresoc.v:193716$14303 + assign { } { } + assign $1\dec2_raw_opcode_in[31:0] 0 + sync always + sync init + update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:193984.13-193984.38" + process $proc$libresoc.v:193984$14304 assign { } { } assign $1\dec_svp64__elwidth[1:0] 2'00 sync always sync init update \dec_svp64__elwidth $1\dec_svp64__elwidth[1:0] end - attribute \src "libresoc.v:199650.13-199650.36" - process $proc$libresoc.v:199650$14533 + attribute \src "libresoc.v:193988.13-193988.36" + process $proc$libresoc.v:193988$14305 assign { } { } assign $1\dec_svp64__ewsrc[1:0] 2'00 sync always sync init update \dec_svp64__ewsrc $1\dec_svp64__ewsrc[1:0] end - attribute \src "libresoc.v:199654.13-199654.35" - process $proc$libresoc.v:199654$14534 + attribute \src "libresoc.v:193992.13-193992.35" + process $proc$libresoc.v:193992$14306 assign { } { } assign $1\dec_svp64__mask[2:0] 3'000 sync always sync init update \dec_svp64__mask $1\dec_svp64__mask[2:0] end - attribute \src "libresoc.v:199658.7-199658.30" - process $proc$libresoc.v:199658$14535 + attribute \src "libresoc.v:193996.7-193996.30" + process $proc$libresoc.v:193996$14307 assign { } { } assign $1\dec_svp64__mmode[0:0] 1'0 sync always sync init update \dec_svp64__mmode $1\dec_svp64__mmode[0:0] end - attribute \src "libresoc.v:199662.13-199662.36" - process $proc$libresoc.v:199662$14536 + attribute \src "libresoc.v:194000.13-194000.36" + process $proc$libresoc.v:194000$14308 assign { } { } assign $1\dec_svp64__mode[4:0] 5'00000 sync always sync init update \dec_svp64__mode $1\dec_svp64__mode[4:0] end - attribute \src "libresoc.v:199666.13-199666.36" - process $proc$libresoc.v:199666$14537 + attribute \src "libresoc.v:194004.13-194004.36" + process $proc$libresoc.v:194004$14309 assign { } { } assign $1\dec_svp64__subvl[1:0] 2'00 sync always sync init update \dec_svp64__subvl $1\dec_svp64__subvl[1:0] end - attribute \src "libresoc.v:199670.13-199670.25" - process $proc$libresoc.v:199670$14538 + attribute \src "libresoc.v:194008.13-194008.25" + process $proc$libresoc.v:194008$14310 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end - attribute \src "libresoc.v:199686.13-199686.35" - process $proc$libresoc.v:199686$14539 + attribute \src "libresoc.v:194024.7-194024.28" + process $proc$libresoc.v:194024$14311 assign { } { } - assign $1\fetch_fsm_state[1:0] 2'00 + assign $1\exec_fsm_state[0:0] 1'0 sync always sync init - update \fetch_fsm_state $1\fetch_fsm_state[1:0] + update \exec_fsm_state $1\exec_fsm_state[0:0] end - attribute \src "libresoc.v:199690.14-199690.34" - process $proc$libresoc.v:199690$14540 + attribute \src "libresoc.v:194036.13-194036.35" + process $proc$libresoc.v:194036$14312 assign { } { } - assign $1\fetch_insn_o[31:0] 0 + assign $1\fetch_fsm_state[1:0] 2'00 sync always sync init - update \fetch_insn_o $1\fetch_insn_o[31:0] + update \fetch_fsm_state $1\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:199702.13-199702.29" - process $proc$libresoc.v:199702$14541 + attribute \src "libresoc.v:194050.13-194050.29" + process $proc$libresoc.v:194050$14313 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:199704.13-199704.35" - process $proc$libresoc.v:199704$14542 - assign { } { } - assign $0\fsm_state$188[1:0]$14543 2'00 - sync always - sync init - update \fsm_state$188 $0\fsm_state$188[1:0]$14543 - end - attribute \src "libresoc.v:199946.14-199946.28" - process $proc$libresoc.v:199946$14544 + attribute \src "libresoc.v:194306.13-194306.35" + process $proc$libresoc.v:194306$14314 assign { } { } - assign $1\ilatch[31:0] 0 + assign $1\issue_fsm_state[2:0] 3'000 sync always sync init - update \ilatch $1\ilatch[31:0] + update \issue_fsm_state $1\issue_fsm_state[2:0] end - attribute \src "libresoc.v:199964.7-199964.30" - process $proc$libresoc.v:199964$14545 + attribute \src "libresoc.v:194310.7-194310.30" + process $proc$libresoc.v:194310$14315 assign { } { } assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:199972.14-199972.52" - process $proc$libresoc.v:199972$14546 + attribute \src "libresoc.v:194318.14-194318.52" + process $proc$libresoc.v:194318$14316 assign { } { } assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:200028.7-200028.22" - process $proc$libresoc.v:200028$14547 + attribute \src "libresoc.v:194376.7-194376.22" + process $proc$libresoc.v:194376$14317 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:200064.14-200064.40" - process $proc$libresoc.v:200064$14548 + attribute \src "libresoc.v:194412.14-194412.40" + process $proc$libresoc.v:194412$14318 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:200070.7-200070.24" - process $proc$libresoc.v:200070$14549 + attribute \src "libresoc.v:194418.7-194418.24" + process $proc$libresoc.v:194418$14319 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:200080.7-200080.25" - process $proc$libresoc.v:200080$14550 + attribute \src "libresoc.v:194428.7-194428.25" + process $proc$libresoc.v:194428$14320 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:200516.7-200516.21" - process $proc$libresoc.v:200516$14551 + attribute \src "libresoc.v:194872.7-194872.24" + process $proc$libresoc.v:194872$14321 + assign { } { } + assign $1\sv_changed[0:0] 1'0 + sync always + sync init + update \sv_changed $1\sv_changed[0:0] + end + attribute \src "libresoc.v:194890.7-194890.30" + process $proc$libresoc.v:194890$14322 assign { } { } - assign $1\sv_read[0:0] 1'1 + assign $1\svstate_ok_delay[0:0] 1'0 sync always sync init - update \sv_read $1\sv_read[0:0] + update \svstate_ok_delay $1\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:200623.3-200624.41" - process $proc$libresoc.v:200623$13787 + attribute \src "libresoc.v:194981.3-194982.41" + process $proc$libresoc.v:194981$13486 assign { } { } assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next sync posedge \clk update \dec2_cur_dec $0\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:200625.3-200626.41" - process $proc$libresoc.v:200625$13788 + attribute \src "libresoc.v:194983.3-194984.47" + process $proc$libresoc.v:194983$13487 assign { } { } - assign $0\core_core_pc[63:0] \core_core_pc$next + assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk - update \core_core_pc $0\core_core_pc[63:0] + update \core_raw_insn_i $0\core_raw_insn_i[31:0] + end + attribute \src "libresoc.v:194985.3-194986.49" + process $proc$libresoc.v:194985$13488 + assign { } { } + assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next + sync posedge \clk + update \svstate_ok_delay $0\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:200627.3-200628.39" - process $proc$libresoc.v:200627$13789 + attribute \src "libresoc.v:194987.3-194988.39" + process $proc$libresoc.v:194987$13489 assign { } { } assign $0\pc_ok_delay[0:0] \pc_ok_delay$next sync posedge \clk update \pc_ok_delay $0\pc_ok_delay[0:0] end - attribute \src "libresoc.v:200629.3-200630.43" - process $proc$libresoc.v:200629$13790 + attribute \src "libresoc.v:194989.3-194990.43" + process $proc$libresoc.v:194989$13490 assign { } { } assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o sync posedge \clk update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:200631.3-200632.27" - process $proc$libresoc.v:200631$13791 + attribute \src "libresoc.v:194991.3-194992.27" + process $proc$libresoc.v:194991$13491 assign { } { } assign $0\delay[1:0] \delay$next sync posedge \por_clk update \delay $0\delay[1:0] end - attribute \src "libresoc.v:200633.3-200634.43" - process $proc$libresoc.v:200633$13792 + attribute \src "libresoc.v:194993.3-194994.43" + process $proc$libresoc.v:194993$13492 assign { } { } assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next sync posedge \clk update \dec2_cur_eint $0\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:200635.3-200636.47" - process $proc$libresoc.v:200635$13793 + attribute \src "libresoc.v:194995.3-194996.47" + process $proc$libresoc.v:194995$13493 assign { } { } assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next sync posedge \clk update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:200637.3-200638.49" - process $proc$libresoc.v:200637$13794 + attribute \src "libresoc.v:194997.3-194998.49" + process $proc$libresoc.v:194997$13494 assign { } { } assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next sync posedge \clk update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:200639.3-200640.39" - process $proc$libresoc.v:200639$13795 + attribute \src "libresoc.v:194999.3-195000.39" + process $proc$libresoc.v:194999$13495 assign { } { } assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next sync posedge \clk update \dbg_dmi_din $0\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:200641.3-200642.41" - process $proc$libresoc.v:200641$13796 + attribute \src "libresoc.v:195001.3-195002.41" + process $proc$libresoc.v:195001$13496 assign { } { } assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next sync posedge \clk update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:200643.3-200644.43" - process $proc$libresoc.v:200643$13797 + attribute \src "libresoc.v:195003.3-195004.43" + process $proc$libresoc.v:195003$13497 assign { } { } assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next sync posedge \clk update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:200645.3-200646.45" - process $proc$libresoc.v:200645$13798 + attribute \src "libresoc.v:195005.3-195006.41" + process $proc$libresoc.v:195005$13498 + assign { } { } + assign $0\core_core_pc[63:0] \core_core_pc$next + sync posedge \clk + update \core_core_pc $0\core_core_pc[63:0] + end + attribute \src "libresoc.v:195007.3-195008.45" + process $proc$libresoc.v:195007$13499 assign { } { } assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next sync posedge \clk update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:200647.3-200648.33" - process $proc$libresoc.v:200647$13799 + attribute \src "libresoc.v:195009.3-195010.33" + process $proc$libresoc.v:195009$13500 assign { } { } assign $0\core_msr[63:0] \core_msr$next sync posedge \clk update \core_msr $0\core_msr[63:0] end - attribute \src "libresoc.v:200649.3-200650.35" - process $proc$libresoc.v:200649$13800 + attribute \src "libresoc.v:195011.3-195012.35" + process $proc$libresoc.v:195011$13501 assign { } { } assign $0\core_eint[0:0] \core_eint$next sync posedge \clk update \core_eint $0\core_eint[0:0] end - attribute \src "libresoc.v:200651.3-200652.33" - process $proc$libresoc.v:200651$13801 + attribute \src "libresoc.v:195013.3-195014.33" + process $proc$libresoc.v:195013$13502 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:200653.3-200654.49" - process $proc$libresoc.v:200653$13802 + attribute \src "libresoc.v:195015.3-195016.49" + process $proc$libresoc.v:195015$13503 assign { } { } assign $0\core_core_svstep[1:0] \core_core_svstep$next sync posedge \clk update \core_core_svstep $0\core_core_svstep[1:0] end - attribute \src "libresoc.v:200655.3-200656.47" - process $proc$libresoc.v:200655$13803 + attribute \src "libresoc.v:195017.3-195018.47" + process $proc$libresoc.v:195017$13504 assign { } { } assign $0\core_core_subvl[1:0] \core_core_subvl$next sync posedge \clk update \core_core_subvl $0\core_core_subvl[1:0] end - attribute \src "libresoc.v:200657.3-200658.51" - process $proc$libresoc.v:200657$13804 + attribute \src "libresoc.v:195019.3-195020.51" + process $proc$libresoc.v:195019$13505 assign { } { } assign $0\core_core_dststep[6:0] \core_core_dststep$next sync posedge \clk update \core_core_dststep $0\core_core_dststep[6:0] end - attribute \src "libresoc.v:200659.3-200660.51" - process $proc$libresoc.v:200659$13805 + attribute \src "libresoc.v:195021.3-195022.51" + process $proc$libresoc.v:195021$13506 assign { } { } assign $0\core_core_srcstep[6:0] \core_core_srcstep$next sync posedge \clk update \core_core_srcstep $0\core_core_srcstep[6:0] end - attribute \src "libresoc.v:200661.3-200662.41" - process $proc$libresoc.v:200661$13806 + attribute \src "libresoc.v:195023.3-195024.41" + process $proc$libresoc.v:195023$13507 assign { } { } assign $0\core_core_vl[6:0] \core_core_vl$next sync posedge \clk update \core_core_vl $0\core_core_vl[6:0] end - attribute \src "libresoc.v:200663.3-200664.47" - process $proc$libresoc.v:200663$13807 + attribute \src "libresoc.v:195025.3-195026.35" + process $proc$libresoc.v:195025$13508 assign { } { } - assign $0\core_core_maxvl[6:0] \core_core_maxvl$next + assign $0\fsm_state[1:0] \fsm_state$next sync posedge \clk - update \core_core_maxvl $0\core_core_maxvl[6:0] + update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:200665.3-200666.45" - process $proc$libresoc.v:200665$13808 + attribute \src "libresoc.v:195027.3-195028.47" + process $proc$libresoc.v:195027$13509 assign { } { } - assign $0\fsm_state$188[1:0]$13809 \fsm_state$188$next + assign $0\core_core_maxvl[6:0] \core_core_maxvl$next sync posedge \clk - update \fsm_state$188 $0\fsm_state$188[1:0]$13809 + update \core_core_maxvl $0\core_core_maxvl[6:0] end - attribute \src "libresoc.v:200667.3-200668.41" - process $proc$libresoc.v:200667$13810 + attribute \src "libresoc.v:195029.3-195030.41" + process $proc$libresoc.v:195029$13510 assign { } { } assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:200669.3-200670.45" - process $proc$libresoc.v:200669$13811 + attribute \src "libresoc.v:195031.3-195032.45" + process $proc$libresoc.v:195031$13511 assign { } { } assign $0\core_core_rego[6:0] \core_core_rego$next sync posedge \clk update \core_core_rego $0\core_core_rego[6:0] end - attribute \src "libresoc.v:200671.3-200672.41" - process $proc$libresoc.v:200671$13812 + attribute \src "libresoc.v:195033.3-195034.41" + process $proc$libresoc.v:195033$13512 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:200673.3-200674.41" - process $proc$libresoc.v:200673$13813 + attribute \src "libresoc.v:195035.3-195036.41" + process $proc$libresoc.v:195035$13513 assign { } { } assign $0\core_core_ea[6:0] \core_core_ea$next sync posedge \clk update \core_core_ea $0\core_core_ea[6:0] end - attribute \src "libresoc.v:200675.3-200676.37" - process $proc$libresoc.v:200675$13814 + attribute \src "libresoc.v:195037.3-195038.37" + process $proc$libresoc.v:195037$13514 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:200677.3-200678.45" - process $proc$libresoc.v:200677$13815 + attribute \src "libresoc.v:195039.3-195040.45" + process $proc$libresoc.v:195039$13515 assign { } { } assign $0\core_core_reg1[6:0] \core_core_reg1$next sync posedge \clk update \core_core_reg1 $0\core_core_reg1[6:0] end - attribute \src "libresoc.v:200679.3-200680.51" - process $proc$libresoc.v:200679$13816 + attribute \src "libresoc.v:195041.3-195042.51" + process $proc$libresoc.v:195041$13516 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:200681.3-200682.45" - process $proc$libresoc.v:200681$13817 + attribute \src "libresoc.v:195043.3-195044.45" + process $proc$libresoc.v:195043$13517 assign { } { } assign $0\core_core_reg2[6:0] \core_core_reg2$next sync posedge \clk update \core_core_reg2 $0\core_core_reg2[6:0] end - attribute \src "libresoc.v:200683.3-200684.51" - process $proc$libresoc.v:200683$13818 + attribute \src "libresoc.v:195045.3-195046.51" + process $proc$libresoc.v:195045$13518 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:200685.3-200686.45" - process $proc$libresoc.v:200685$13819 + attribute \src "libresoc.v:195047.3-195048.39" + process $proc$libresoc.v:195047$13519 assign { } { } - assign $0\core_core_reg3[6:0] \core_core_reg3$next + assign $0\d_xer_delay[0:0] \d_xer_delay$next sync posedge \clk - update \core_core_reg3 $0\core_core_reg3[6:0] + update \d_xer_delay $0\d_xer_delay[0:0] end - attribute \src "libresoc.v:200687.3-200688.39" - process $proc$libresoc.v:200687$13820 + attribute \src "libresoc.v:195049.3-195050.45" + process $proc$libresoc.v:195049$13520 assign { } { } - assign $0\d_xer_delay[0:0] \d_xer_delay$next + assign $0\core_core_reg3[6:0] \core_core_reg3$next sync posedge \clk - update \d_xer_delay $0\d_xer_delay[0:0] + update \core_core_reg3 $0\core_core_reg3[6:0] end - attribute \src "libresoc.v:200689.3-200690.51" - process $proc$libresoc.v:200689$13821 + attribute \src "libresoc.v:195051.3-195052.51" + process $proc$libresoc.v:195051$13521 assign { } { } assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:200691.3-200692.45" - process $proc$libresoc.v:200691$13822 + attribute \src "libresoc.v:195053.3-195054.45" + process $proc$libresoc.v:195053$13522 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end - attribute \src "libresoc.v:200693.3-200694.41" - process $proc$libresoc.v:200693$13823 + attribute \src "libresoc.v:195055.3-195056.41" + process $proc$libresoc.v:195055$13523 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:200695.3-200696.45" - process $proc$libresoc.v:200695$13824 + attribute \src "libresoc.v:195057.3-195058.45" + process $proc$libresoc.v:195057$13524 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end - attribute \src "libresoc.v:200697.3-200698.51" - process $proc$libresoc.v:200697$13825 + attribute \src "libresoc.v:195059.3-195060.51" + process $proc$libresoc.v:195059$13525 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:200699.3-200700.49" - process $proc$libresoc.v:200699$13826 + attribute \src "libresoc.v:195061.3-195062.49" + process $proc$libresoc.v:195061$13526 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end - attribute \src "libresoc.v:200701.3-200702.41" - process $proc$libresoc.v:200701$13827 + attribute \src "libresoc.v:195063.3-195064.41" + process $proc$libresoc.v:195063$13527 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:200703.3-200704.47" - process $proc$libresoc.v:200703$13828 + attribute \src "libresoc.v:195065.3-195066.47" + process $proc$libresoc.v:195065$13528 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end - attribute \src "libresoc.v:200705.3-200706.53" - process $proc$libresoc.v:200705$13829 + attribute \src "libresoc.v:195067.3-195068.53" + process $proc$libresoc.v:195067$13529 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:200707.3-200708.47" - process $proc$libresoc.v:200707$13830 + attribute \src "libresoc.v:195069.3-195070.37" + process $proc$libresoc.v:195069$13530 assign { } { } - assign $0\core_core_fast2[2:0] \core_core_fast2$next + assign $0\d_cr_delay[0:0] \d_cr_delay$next sync posedge \clk - update \core_core_fast2 $0\core_core_fast2[2:0] + update \d_cr_delay $0\d_cr_delay[0:0] end - attribute \src "libresoc.v:200709.3-200710.37" - process $proc$libresoc.v:200709$13831 + attribute \src "libresoc.v:195071.3-195072.47" + process $proc$libresoc.v:195071$13531 assign { } { } - assign $0\d_cr_delay[0:0] \d_cr_delay$next + assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk - update \d_cr_delay $0\d_cr_delay[0:0] + update \core_core_fast2 $0\core_core_fast2[2:0] end - attribute \src "libresoc.v:200711.3-200712.53" - process $proc$libresoc.v:200711$13832 + attribute \src "libresoc.v:195073.3-195074.53" + process $proc$libresoc.v:195073$13532 assign { } { } assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:200713.3-200714.49" - process $proc$libresoc.v:200713$13833 + attribute \src "libresoc.v:195075.3-195076.49" + process $proc$libresoc.v:195075$13533 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end - attribute \src "libresoc.v:200715.3-200716.45" - process $proc$libresoc.v:200715$13834 + attribute \src "libresoc.v:195077.3-195078.45" + process $proc$libresoc.v:195077$13534 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:200717.3-200718.49" - process $proc$libresoc.v:200717$13835 + attribute \src "libresoc.v:195079.3-195080.49" + process $proc$libresoc.v:195079$13535 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end - attribute \src "libresoc.v:200719.3-200720.45" - process $proc$libresoc.v:200719$13836 + attribute \src "libresoc.v:195081.3-195082.45" + process $proc$libresoc.v:195081$13536 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:200721.3-200722.49" - process $proc$libresoc.v:200721$13837 + attribute \src "libresoc.v:195083.3-195084.49" + process $proc$libresoc.v:195083$13537 assign { } { } assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next sync posedge \clk update \core_core_cr_in1 $0\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:200723.3-200724.55" - process $proc$libresoc.v:200723$13838 + attribute \src "libresoc.v:195085.3-195086.55" + process $proc$libresoc.v:195085$13538 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:200725.3-200726.49" - process $proc$libresoc.v:200725$13839 + attribute \src "libresoc.v:195087.3-195088.49" + process $proc$libresoc.v:195087$13539 assign { } { } assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next sync posedge \clk update \core_core_cr_in2 $0\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:200727.3-200728.55" - process $proc$libresoc.v:200727$13840 + attribute \src "libresoc.v:195089.3-195090.55" + process $proc$libresoc.v:195089$13540 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:200729.3-200730.55" - process $proc$libresoc.v:200729$13841 + attribute \src "libresoc.v:195091.3-195092.39" + process $proc$libresoc.v:195091$13541 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$13842 \core_core_cr_in2$1$next + assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13842 + update \d_reg_delay $0\d_reg_delay[0:0] end - attribute \src "libresoc.v:200731.3-200732.39" - process $proc$libresoc.v:200731$13843 + attribute \src "libresoc.v:195093.3-195094.55" + process $proc$libresoc.v:195093$13542 assign { } { } - assign $0\d_reg_delay[0:0] \d_reg_delay$next + assign $0\core_core_cr_in2$1[6:0]$13543 \core_core_cr_in2$1$next sync posedge \clk - update \d_reg_delay $0\d_reg_delay[0:0] + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13543 end - attribute \src "libresoc.v:200733.3-200734.61" - process $proc$libresoc.v:200733$13844 + attribute \src "libresoc.v:195095.3-195096.61" + process $proc$libresoc.v:195095$13544 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13845 \core_core_cr_in2_ok$2$next + assign $0\core_core_cr_in2_ok$2[0:0]$13545 \core_core_cr_in2_ok$2$next sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13845 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13545 end - attribute \src "libresoc.v:200735.3-200736.49" - process $proc$libresoc.v:200735$13846 + attribute \src "libresoc.v:195097.3-195098.49" + process $proc$libresoc.v:195097$13546 assign { } { } assign $0\core_core_cr_out[6:0] \core_core_cr_out$next sync posedge \clk update \core_core_cr_out $0\core_core_cr_out[6:0] end - attribute \src "libresoc.v:200737.3-200738.45" - process $proc$libresoc.v:200737$13847 + attribute \src "libresoc.v:195099.3-195100.45" + process $proc$libresoc.v:195099$13547 assign { } { } assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk update \core_cr_out_ok $0\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:200739.3-200740.53" - process $proc$libresoc.v:200739$13848 + attribute \src "libresoc.v:195101.3-195102.53" + process $proc$libresoc.v:195101$13548 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end - attribute \src "libresoc.v:200741.3-200742.53" - process $proc$libresoc.v:200741$13849 + attribute \src "libresoc.v:195103.3-195104.53" + process $proc$libresoc.v:195103$13549 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end - attribute \src "libresoc.v:200743.3-200744.55" - process $proc$libresoc.v:200743$13850 + attribute \src "libresoc.v:195105.3-195106.55" + process $proc$libresoc.v:195105$13550 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end - attribute \src "libresoc.v:200745.3-200746.65" - process $proc$libresoc.v:200745$13851 + attribute \src "libresoc.v:195107.3-195108.65" + process $proc$libresoc.v:195107$13551 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:200747.3-200748.61" - process $proc$libresoc.v:200747$13852 + attribute \src "libresoc.v:195109.3-195110.61" + process $proc$libresoc.v:195109$13552 assign { } { } assign $0\core_core_core_fn_unit[12:0] \core_core_core_fn_unit$next sync posedge \clk update \core_core_core_fn_unit $0\core_core_core_fn_unit[12:0] end - attribute \src "libresoc.v:200749.3-200750.41" - process $proc$libresoc.v:200749$13853 + attribute \src "libresoc.v:195111.3-195112.41" + process $proc$libresoc.v:195111$13553 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end - attribute \src "libresoc.v:200751.3-200752.51" - process $proc$libresoc.v:200751$13854 + attribute \src "libresoc.v:195113.3-195114.37" + process $proc$libresoc.v:195113$13554 assign { } { } - assign $0\core_core_core_rc[0:0] \core_core_core_rc$next + assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk - update \core_core_core_rc $0\core_core_core_rc[0:0] + update \pc_changed $0\pc_changed[0:0] end - attribute \src "libresoc.v:200753.3-200754.37" - process $proc$libresoc.v:200753$13855 + attribute \src "libresoc.v:195115.3-195116.51" + process $proc$libresoc.v:195115$13555 assign { } { } - assign $0\pc_changed[0:0] \pc_changed$next + assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk - update \pc_changed $0\pc_changed[0:0] + update \core_core_core_rc $0\core_core_core_rc[0:0] end - attribute \src "libresoc.v:200755.3-200756.57" - process $proc$libresoc.v:200755$13856 + attribute \src "libresoc.v:195117.3-195118.57" + process $proc$libresoc.v:195117$13556 assign { } { } assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:200757.3-200758.51" - process $proc$libresoc.v:200757$13857 + attribute \src "libresoc.v:195119.3-195120.51" + process $proc$libresoc.v:195119$13557 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end - attribute \src "libresoc.v:200759.3-200760.57" - process $proc$libresoc.v:200759$13858 + attribute \src "libresoc.v:195121.3-195122.57" + process $proc$libresoc.v:195121$13558 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:200761.3-200762.69" - process $proc$libresoc.v:200761$13859 + attribute \src "libresoc.v:195123.3-195124.69" + process $proc$libresoc.v:195123$13559 assign { } { } assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:200763.3-200764.63" - process $proc$libresoc.v:200763$13860 + attribute \src "libresoc.v:195125.3-195126.63" + process $proc$libresoc.v:195125$13560 assign { } { } assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk update \core_core_core_traptype $0\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:200765.3-200766.71" - process $proc$libresoc.v:200765$13861 + attribute \src "libresoc.v:195127.3-195128.71" + process $proc$libresoc.v:195127$13561 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13862 \core_core_core_exc_$signal$next + assign $0\core_core_core_exc_$signal[0:0]$13562 \core_core_core_exc_$signal$next sync posedge \clk - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13862 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13562 end - attribute \src "libresoc.v:200767.3-200768.75" - process $proc$libresoc.v:200767$13863 + attribute \src "libresoc.v:195129.3-195130.75" + process $proc$libresoc.v:195129$13563 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13864 \core_core_core_exc_$signal$3$next + assign $0\core_core_core_exc_$signal$3[0:0]$13564 \core_core_core_exc_$signal$3$next sync posedge \clk - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13864 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13564 end - attribute \src "libresoc.v:200769.3-200770.75" - process $proc$libresoc.v:200769$13865 + attribute \src "libresoc.v:195131.3-195132.75" + process $proc$libresoc.v:195131$13565 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13866 \core_core_core_exc_$signal$4$next + assign $0\core_core_core_exc_$signal$4[0:0]$13566 \core_core_core_exc_$signal$4$next sync posedge \clk - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13866 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13566 end - attribute \src "libresoc.v:200771.3-200772.75" - process $proc$libresoc.v:200771$13867 + attribute \src "libresoc.v:195133.3-195134.75" + process $proc$libresoc.v:195133$13567 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13868 \core_core_core_exc_$signal$5$next + assign $0\core_core_core_exc_$signal$5[0:0]$13568 \core_core_core_exc_$signal$5$next sync posedge \clk - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13868 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13568 end - attribute \src "libresoc.v:200773.3-200774.75" - process $proc$libresoc.v:200773$13869 + attribute \src "libresoc.v:195135.3-195136.37" + process $proc$libresoc.v:195135$13569 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13870 \core_core_core_exc_$signal$6$next + assign $0\sv_changed[0:0] \sv_changed$next sync posedge \clk - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13870 + update \sv_changed $0\sv_changed[0:0] end - attribute \src "libresoc.v:200775.3-200776.29" - process $proc$libresoc.v:200775$13871 + attribute \src "libresoc.v:195137.3-195138.75" + process $proc$libresoc.v:195137$13570 assign { } { } - assign $0\ilatch[31:0] \ilatch$next + assign $0\core_core_core_exc_$signal$6[0:0]$13571 \core_core_core_exc_$signal$6$next sync posedge \clk - update \ilatch $0\ilatch[31:0] + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13571 end - attribute \src "libresoc.v:200777.3-200778.75" - process $proc$libresoc.v:200777$13872 + attribute \src "libresoc.v:195139.3-195140.75" + process $proc$libresoc.v:195139$13572 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13873 \core_core_core_exc_$signal$7$next + assign $0\core_core_core_exc_$signal$7[0:0]$13573 \core_core_core_exc_$signal$7$next sync posedge \clk - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13873 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13573 end - attribute \src "libresoc.v:200779.3-200780.75" - process $proc$libresoc.v:200779$13874 + attribute \src "libresoc.v:195141.3-195142.75" + process $proc$libresoc.v:195141$13574 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13875 \core_core_core_exc_$signal$8$next + assign $0\core_core_core_exc_$signal$8[0:0]$13575 \core_core_core_exc_$signal$8$next sync posedge \clk - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13875 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13575 end - attribute \src "libresoc.v:200781.3-200782.75" - process $proc$libresoc.v:200781$13876 + attribute \src "libresoc.v:195143.3-195144.75" + process $proc$libresoc.v:195143$13576 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13877 \core_core_core_exc_$signal$9$next + assign $0\core_core_core_exc_$signal$9[0:0]$13577 \core_core_core_exc_$signal$9$next sync posedge \clk - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13877 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13577 end - attribute \src "libresoc.v:200783.3-200784.63" - process $proc$libresoc.v:200783$13878 + attribute \src "libresoc.v:195145.3-195146.63" + process $proc$libresoc.v:195145$13578 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:200785.3-200786.57" - process $proc$libresoc.v:200785$13879 + attribute \src "libresoc.v:195147.3-195148.57" + process $proc$libresoc.v:195147$13579 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:200787.3-200788.63" - process $proc$libresoc.v:200787$13880 + attribute \src "libresoc.v:195149.3-195150.63" + process $proc$libresoc.v:195149$13580 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:200789.3-200790.57" - process $proc$libresoc.v:200789$13881 + attribute \src "libresoc.v:195151.3-195152.57" + process $proc$libresoc.v:195151$13581 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:200791.3-200792.53" - process $proc$libresoc.v:200791$13882 + attribute \src "libresoc.v:195153.3-195154.53" + process $proc$libresoc.v:195153$13582 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:200793.3-200794.63" - process $proc$libresoc.v:200793$13883 + attribute \src "libresoc.v:195155.3-195156.63" + process $proc$libresoc.v:195155$13583 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:200795.3-200796.35" - process $proc$libresoc.v:200795$13884 + attribute \src "libresoc.v:195157.3-195158.45" + process $proc$libresoc.v:195157$13584 assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next + assign $0\exec_fsm_state[0:0] \exec_fsm_state$next sync posedge \clk - update \fsm_state $0\fsm_state[1:0] - end - attribute \src "libresoc.v:200797.3-200798.57" - process $proc$libresoc.v:200797$13885 - assign { } { } - assign $0\core_bigendian_i$10[0:0]$13886 \core_bigendian_i$10$next - sync posedge \clk - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13886 + update \exec_fsm_state $0\exec_fsm_state[0:0] end - attribute \src "libresoc.v:200799.3-200800.41" - process $proc$libresoc.v:200799$13887 + attribute \src "libresoc.v:195159.3-195160.47" + process $proc$libresoc.v:195159$13585 assign { } { } - assign $0\fetch_insn_o[31:0] \fetch_insn_o$next + assign $0\issue_fsm_state[2:0] \issue_fsm_state$next sync posedge \clk - update \fetch_insn_o $0\fetch_insn_o[31:0] + update \issue_fsm_state $0\issue_fsm_state[2:0] end - attribute \src "libresoc.v:200801.3-200802.23" - process $proc$libresoc.v:200801$13888 + attribute \src "libresoc.v:195161.3-195162.23" + process $proc$libresoc.v:195161$13586 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:200803.3-200804.47" - process $proc$libresoc.v:200803$13889 + attribute \src "libresoc.v:195163.3-195164.47" + process $proc$libresoc.v:195163$13587 assign { } { } assign $0\dec_svp64__mode[4:0] \dec_svp64__mode$next sync posedge \clk update \dec_svp64__mode $0\dec_svp64__mode[4:0] end - attribute \src "libresoc.v:200805.3-200806.59" - process $proc$libresoc.v:200805$13890 + attribute \src "libresoc.v:195165.3-195166.59" + process $proc$libresoc.v:195165$13588 assign { } { } assign $0\dec2_dec_svp64__extra[8:0] \dec2_dec_svp64__extra$next sync posedge \clk update \dec2_dec_svp64__extra $0\dec2_dec_svp64__extra[8:0] end - attribute \src "libresoc.v:200807.3-200808.49" - process $proc$libresoc.v:200807$13891 + attribute \src "libresoc.v:195167.3-195168.49" + process $proc$libresoc.v:195167$13589 assign { } { } assign $0\dec_svp64__subvl[1:0] \dec_svp64__subvl$next sync posedge \clk update \dec_svp64__subvl $0\dec_svp64__subvl[1:0] end - attribute \src "libresoc.v:200809.3-200810.49" - process $proc$libresoc.v:200809$13892 + attribute \src "libresoc.v:195169.3-195170.49" + process $proc$libresoc.v:195169$13590 assign { } { } assign $0\dec_svp64__ewsrc[1:0] \dec_svp64__ewsrc$next sync posedge \clk update \dec_svp64__ewsrc $0\dec_svp64__ewsrc[1:0] end - attribute \src "libresoc.v:200811.3-200812.53" - process $proc$libresoc.v:200811$13893 + attribute \src "libresoc.v:195171.3-195172.53" + process $proc$libresoc.v:195171$13591 assign { } { } assign $0\dec_svp64__elwidth[1:0] \dec_svp64__elwidth$next sync posedge \clk update \dec_svp64__elwidth $0\dec_svp64__elwidth[1:0] end - attribute \src "libresoc.v:200813.3-200814.47" - process $proc$libresoc.v:200813$13894 + attribute \src "libresoc.v:195173.3-195174.47" + process $proc$libresoc.v:195173$13592 assign { } { } assign $0\dec_svp64__mask[2:0] \dec_svp64__mask$next sync posedge \clk update \dec_svp64__mask $0\dec_svp64__mask[2:0] end - attribute \src "libresoc.v:200815.3-200816.49" - process $proc$libresoc.v:200815$13895 + attribute \src "libresoc.v:195175.3-195176.49" + process $proc$libresoc.v:195175$13593 assign { } { } assign $0\dec_svp64__mmode[0:0] \dec_svp64__mmode$next sync posedge \clk update \dec_svp64__mmode $0\dec_svp64__mmode[0:0] end - attribute \src "libresoc.v:200817.3-200818.45" - process $proc$libresoc.v:200817$13896 + attribute \src "libresoc.v:195177.3-195178.41" + process $proc$libresoc.v:195177$13594 assign { } { } - assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk - update \cur_cur_svstep $0\cur_cur_svstep[1:0] + update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:200819.3-200820.47" - process $proc$libresoc.v:200819$13897 + attribute \src "libresoc.v:195179.3-195180.57" + process $proc$libresoc.v:195179$13595 assign { } { } - assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next + assign $0\core_bigendian_i$10[0:0]$13596 \core_bigendian_i$10$next sync posedge \clk - update \core_raw_insn_i $0\core_raw_insn_i[31:0] + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13596 + end + attribute \src "libresoc.v:195181.3-195182.47" + process $proc$libresoc.v:195181$13597 + assign { } { } + assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next + sync posedge \clk + update \fetch_fsm_state $0\fetch_fsm_state[1:0] + end + attribute \src "libresoc.v:195183.3-195184.33" + process $proc$libresoc.v:195183$13598 + assign { } { } + assign $0\msr_read[0:0] \msr_read$next + sync posedge \clk + update \msr_read $0\msr_read[0:0] + end + attribute \src "libresoc.v:195185.3-195186.45" + process $proc$libresoc.v:195185$13599 + assign { } { } + assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next + sync posedge \clk + update \cur_cur_svstep $0\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:200821.3-200822.43" - process $proc$libresoc.v:200821$13898 + attribute \src "libresoc.v:195187.3-195188.43" + process $proc$libresoc.v:195187$13600 assign { } { } assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next sync posedge \clk update \cur_cur_subvl $0\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:200823.3-200824.47" - process $proc$libresoc.v:200823$13899 + attribute \src "libresoc.v:195189.3-195190.47" + process $proc$libresoc.v:195189$13601 assign { } { } assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next sync posedge \clk update \cur_cur_dststep $0\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:200825.3-200826.57" - process $proc$libresoc.v:200825$13900 + attribute \src "libresoc.v:195191.3-195192.57" + process $proc$libresoc.v:195191$13602 assign { } { } assign $0\dec2_cur_cur_srcstep[6:0] \dec2_cur_cur_srcstep$next sync posedge \clk update \dec2_cur_cur_srcstep $0\dec2_cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:200827.3-200828.37" - process $proc$libresoc.v:200827$13901 + attribute \src "libresoc.v:195193.3-195194.37" + process $proc$libresoc.v:195193$13603 assign { } { } assign $0\cur_cur_vl[6:0] \cur_cur_vl$next sync posedge \clk update \cur_cur_vl $0\cur_cur_vl[6:0] end - attribute \src "libresoc.v:200829.3-200830.43" - process $proc$libresoc.v:200829$13902 + attribute \src "libresoc.v:195195.3-195196.43" + process $proc$libresoc.v:195195$13604 assign { } { } assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next sync posedge \clk update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:200831.3-200832.41" - process $proc$libresoc.v:200831$13903 + attribute \src "libresoc.v:195197.3-195198.39" + process $proc$libresoc.v:195197$13605 assign { } { } - assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next - sync posedge \clk - update \dec2_cur_msr $0\dec2_cur_msr[63:0] - end - attribute \src "libresoc.v:200833.3-200834.47" - process $proc$libresoc.v:200833$13904 - assign { } { } - assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next sync posedge \clk - update \fetch_fsm_state $0\fetch_fsm_state[1:0] + update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:200835.3-200836.31" - process $proc$libresoc.v:200835$13905 + attribute \src "libresoc.v:195199.3-195200.40" + process $proc$libresoc.v:195199$13606 assign { } { } - assign $0\sv_read[0:0] \sv_read$next + assign $0\dec2_raw_opcode_in[31:0] \fetch_insn_o sync posedge \clk - update \sv_read $0\sv_read[0:0] + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:200837.3-200838.33" - process $proc$libresoc.v:200837$13906 + attribute \src "libresoc.v:195831.3-195839.6" + process $proc$libresoc.v:195831$13607 assign { } { } - assign $0\msr_read[0:0] \msr_read$next - sync posedge \clk - update \msr_read $0\msr_read[0:0] - end - attribute \src "libresoc.v:200839.3-200840.39" - process $proc$libresoc.v:200839$13907 assign { } { } - assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next - sync posedge \clk - update \dec2_cur_pc $0\dec2_cur_pc[63:0] + assign $0\dbg_dmi_addr_i$next[3:0]$13608 $1\dbg_dmi_addr_i$next[3:0]$13609 + attribute \src "libresoc.v:195832.5-195832.29" + switch \initial + attribute \src "libresoc.v:195832.9-195832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_addr_i$next[3:0]$13609 4'0000 + case + assign $1\dbg_dmi_addr_i$next[3:0]$13609 \jtag_dmi0__addr_i + end + sync always + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13608 end - attribute \src "libresoc.v:201466.3-201474.6" - process $proc$libresoc.v:201466$13908 + attribute \src "libresoc.v:195840.3-195848.6" + process $proc$libresoc.v:195840$13610 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13909 $1\dbg_dmi_addr_i$next[3:0]$13910 - attribute \src "libresoc.v:201467.5-201467.29" + assign $0\dbg_dmi_req_i$next[0:0]$13611 $1\dbg_dmi_req_i$next[0:0]$13612 + attribute \src "libresoc.v:195841.5-195841.29" switch \initial - attribute \src "libresoc.v:201467.9-201467.17" + attribute \src "libresoc.v:195841.9-195841.17" case 1'1 case end @@ -418191,21 +409176,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13910 4'0000 + assign $1\dbg_dmi_req_i$next[0:0]$13612 1'0 case - assign $1\dbg_dmi_addr_i$next[3:0]$13910 \jtag_dmi0__addr_i + assign $1\dbg_dmi_req_i$next[0:0]$13612 \jtag_dmi0__req_i end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13909 + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13611 end - attribute \src "libresoc.v:201475.3-201483.6" - process $proc$libresoc.v:201475$13911 + attribute \src "libresoc.v:195849.3-195857.6" + process $proc$libresoc.v:195849$13613 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13912 $1\dbg_dmi_req_i$next[0:0]$13913 - attribute \src "libresoc.v:201476.5-201476.29" + assign $0\dec2_cur_eint$next[0:0]$13614 $1\dec2_cur_eint$next[0:0]$13615 + attribute \src "libresoc.v:195850.5-195850.29" switch \initial - attribute \src "libresoc.v:201476.9-201476.17" + attribute \src "libresoc.v:195850.9-195850.17" case 1'1 case end @@ -418214,15 +409199,38 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13913 1'0 + assign $1\dec2_cur_eint$next[0:0]$13615 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$13615 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13614 + end + attribute \src "libresoc.v:195858.3-195867.6" + process $proc$libresoc.v:195858$13616 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$13617 $1\delay$next[1:0]$13618 + attribute \src "libresoc.v:195859.5-195859.29" + switch \initial + attribute \src "libresoc.v:195859.9-195859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:452" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$13618 \$25 [1:0] case - assign $1\dbg_dmi_req_i$next[0:0]$13913 \jtag_dmi0__req_i + assign $1\delay$next[1:0]$13618 \delay end sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13912 + update \delay$next $0\delay$next[1:0]$13617 end - attribute \src "libresoc.v:201484.3-201524.6" - process $proc$libresoc.v:201484$13914 + attribute \src "libresoc.v:195868.3-195908.6" + process $proc$libresoc.v:195868$13619 assign { } { } assign { } { } assign { } { } @@ -418253,26 +409261,26 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_dststep$next[6:0]$13915 $3\core_core_dststep$next[6:0]$13945 - assign $0\core_core_maxvl$next[6:0]$13916 $3\core_core_maxvl$next[6:0]$13946 - assign $0\core_core_pc$next[63:0]$13917 $3\core_core_pc$next[63:0]$13947 - assign $0\core_core_srcstep$next[6:0]$13918 $3\core_core_srcstep$next[6:0]$13948 - assign $0\core_core_subvl$next[1:0]$13919 $3\core_core_subvl$next[1:0]$13949 - assign $0\core_core_svstep$next[1:0]$13920 $3\core_core_svstep$next[1:0]$13950 - assign $0\core_core_vl$next[6:0]$13921 $3\core_core_vl$next[6:0]$13951 - assign $0\core_dec$next[63:0]$13922 $3\core_dec$next[63:0]$13952 - assign $0\core_eint$next[0:0]$13923 $3\core_eint$next[0:0]$13953 - assign $0\core_msr$next[63:0]$13924 $3\core_msr$next[63:0]$13954 - attribute \src "libresoc.v:201485.5-201485.29" + assign $0\core_core_dststep$next[6:0]$13620 $3\core_core_dststep$next[6:0]$13650 + assign $0\core_core_maxvl$next[6:0]$13621 $3\core_core_maxvl$next[6:0]$13651 + assign $0\core_core_pc$next[63:0]$13622 $3\core_core_pc$next[63:0]$13652 + assign $0\core_core_srcstep$next[6:0]$13623 $3\core_core_srcstep$next[6:0]$13653 + assign $0\core_core_subvl$next[1:0]$13624 $3\core_core_subvl$next[1:0]$13654 + assign $0\core_core_svstep$next[1:0]$13625 $3\core_core_svstep$next[1:0]$13655 + assign $0\core_core_vl$next[6:0]$13626 $3\core_core_vl$next[6:0]$13656 + assign $0\core_dec$next[63:0]$13627 $3\core_dec$next[63:0]$13657 + assign $0\core_eint$next[0:0]$13628 $3\core_eint$next[0:0]$13658 + assign $0\core_msr$next[63:0]$13629 $3\core_msr$next[63:0]$13659 + attribute \src "libresoc.v:195869.5-195869.29" switch \initial - attribute \src "libresoc.v:201485.9-201485.17" + attribute \src "libresoc.v:195869.9-195869.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'010 assign { } { } assign { } { } assign { } { } @@ -418283,17 +409291,17 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_core_dststep$next[6:0]$13925 $2\core_core_dststep$next[6:0]$13935 - assign $1\core_core_maxvl$next[6:0]$13926 $2\core_core_maxvl$next[6:0]$13936 - assign $1\core_core_pc$next[63:0]$13927 $2\core_core_pc$next[63:0]$13937 - assign $1\core_core_srcstep$next[6:0]$13928 $2\core_core_srcstep$next[6:0]$13938 - assign $1\core_core_subvl$next[1:0]$13929 $2\core_core_subvl$next[1:0]$13939 - assign $1\core_core_svstep$next[1:0]$13930 $2\core_core_svstep$next[1:0]$13940 - assign $1\core_core_vl$next[6:0]$13931 $2\core_core_vl$next[6:0]$13941 - assign $1\core_dec$next[63:0]$13932 $2\core_dec$next[63:0]$13942 - assign $1\core_eint$next[0:0]$13933 $2\core_eint$next[0:0]$13943 - assign $1\core_msr$next[63:0]$13934 $2\core_msr$next[63:0]$13944 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + assign $1\core_core_dststep$next[6:0]$13630 $2\core_core_dststep$next[6:0]$13640 + assign $1\core_core_maxvl$next[6:0]$13631 $2\core_core_maxvl$next[6:0]$13641 + assign $1\core_core_pc$next[63:0]$13632 $2\core_core_pc$next[63:0]$13642 + assign $1\core_core_srcstep$next[6:0]$13633 $2\core_core_srcstep$next[6:0]$13643 + assign $1\core_core_subvl$next[1:0]$13634 $2\core_core_subvl$next[1:0]$13644 + assign $1\core_core_svstep$next[1:0]$13635 $2\core_core_svstep$next[1:0]$13645 + assign $1\core_core_vl$next[6:0]$13636 $2\core_core_vl$next[6:0]$13646 + assign $1\core_dec$next[63:0]$13637 $2\core_dec$next[63:0]$13647 + assign $1\core_eint$next[0:0]$13638 $2\core_eint$next[0:0]$13648 + assign $1\core_msr$next[63:0]$13639 $2\core_msr$next[63:0]$13649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -418307,30 +409315,30 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_maxvl$next[6:0]$13936 $2\core_core_vl$next[6:0]$13941 $2\core_core_srcstep$next[6:0]$13938 $2\core_core_dststep$next[6:0]$13935 $2\core_core_subvl$next[1:0]$13939 $2\core_core_svstep$next[1:0]$13940 $2\core_dec$next[63:0]$13942 $2\core_eint$next[0:0]$13943 $2\core_msr$next[63:0]$13944 $2\core_core_pc$next[63:0]$13937 } { \cur_cur_maxvl \cur_cur_vl \dec2_cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $2\core_core_maxvl$next[6:0]$13641 $2\core_core_vl$next[6:0]$13646 $2\core_core_srcstep$next[6:0]$13643 $2\core_core_dststep$next[6:0]$13640 $2\core_core_subvl$next[1:0]$13644 $2\core_core_svstep$next[1:0]$13645 $2\core_dec$next[63:0]$13647 $2\core_eint$next[0:0]$13648 $2\core_msr$next[63:0]$13649 $2\core_core_pc$next[63:0]$13642 } { \cur_cur_maxvl \cur_cur_vl \dec2_cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $2\core_core_dststep$next[6:0]$13935 \core_core_dststep - assign $2\core_core_maxvl$next[6:0]$13936 \core_core_maxvl - assign $2\core_core_pc$next[63:0]$13937 \core_core_pc - assign $2\core_core_srcstep$next[6:0]$13938 \core_core_srcstep - assign $2\core_core_subvl$next[1:0]$13939 \core_core_subvl - assign $2\core_core_svstep$next[1:0]$13940 \core_core_svstep - assign $2\core_core_vl$next[6:0]$13941 \core_core_vl - assign $2\core_dec$next[63:0]$13942 \core_dec - assign $2\core_eint$next[0:0]$13943 \core_eint - assign $2\core_msr$next[63:0]$13944 \core_msr + assign $2\core_core_dststep$next[6:0]$13640 \core_core_dststep + assign $2\core_core_maxvl$next[6:0]$13641 \core_core_maxvl + assign $2\core_core_pc$next[63:0]$13642 \core_core_pc + assign $2\core_core_srcstep$next[6:0]$13643 \core_core_srcstep + assign $2\core_core_subvl$next[1:0]$13644 \core_core_subvl + assign $2\core_core_svstep$next[1:0]$13645 \core_core_svstep + assign $2\core_core_vl$next[6:0]$13646 \core_core_vl + assign $2\core_dec$next[63:0]$13647 \core_dec + assign $2\core_eint$next[0:0]$13648 \core_eint + assign $2\core_msr$next[63:0]$13649 \core_msr end case - assign $1\core_core_dststep$next[6:0]$13925 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13926 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13927 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13928 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13929 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13930 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13931 \core_core_vl - assign $1\core_dec$next[63:0]$13932 \core_dec - assign $1\core_eint$next[0:0]$13933 \core_eint - assign $1\core_msr$next[63:0]$13934 \core_msr + assign $1\core_core_dststep$next[6:0]$13630 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13631 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13632 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13633 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13634 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13635 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13636 \core_core_vl + assign $1\core_dec$next[63:0]$13637 \core_dec + assign $1\core_eint$next[0:0]$13638 \core_eint + assign $1\core_msr$next[63:0]$13639 \core_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -418346,215 +409354,305 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_core_pc$next[63:0]$13947 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13954 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13953 1'0 - assign $3\core_dec$next[63:0]$13952 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_core_svstep$next[1:0]$13950 2'00 - assign $3\core_core_subvl$next[1:0]$13949 2'00 - assign $3\core_core_dststep$next[6:0]$13945 7'0000000 - assign $3\core_core_srcstep$next[6:0]$13948 7'0000000 - assign $3\core_core_vl$next[6:0]$13951 7'0000000 - assign $3\core_core_maxvl$next[6:0]$13946 7'0000000 + assign $3\core_core_pc$next[63:0]$13652 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13659 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13658 1'0 + assign $3\core_dec$next[63:0]$13657 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_core_svstep$next[1:0]$13655 2'00 + assign $3\core_core_subvl$next[1:0]$13654 2'00 + assign $3\core_core_dststep$next[6:0]$13650 7'0000000 + assign $3\core_core_srcstep$next[6:0]$13653 7'0000000 + assign $3\core_core_vl$next[6:0]$13656 7'0000000 + assign $3\core_core_maxvl$next[6:0]$13651 7'0000000 case - assign $3\core_core_dststep$next[6:0]$13945 $1\core_core_dststep$next[6:0]$13925 - assign $3\core_core_maxvl$next[6:0]$13946 $1\core_core_maxvl$next[6:0]$13926 - assign $3\core_core_pc$next[63:0]$13947 $1\core_core_pc$next[63:0]$13927 - assign $3\core_core_srcstep$next[6:0]$13948 $1\core_core_srcstep$next[6:0]$13928 - assign $3\core_core_subvl$next[1:0]$13949 $1\core_core_subvl$next[1:0]$13929 - assign $3\core_core_svstep$next[1:0]$13950 $1\core_core_svstep$next[1:0]$13930 - assign $3\core_core_vl$next[6:0]$13951 $1\core_core_vl$next[6:0]$13931 - assign $3\core_dec$next[63:0]$13952 $1\core_dec$next[63:0]$13932 - assign $3\core_eint$next[0:0]$13953 $1\core_eint$next[0:0]$13933 - assign $3\core_msr$next[63:0]$13954 $1\core_msr$next[63:0]$13934 + assign $3\core_core_dststep$next[6:0]$13650 $1\core_core_dststep$next[6:0]$13630 + assign $3\core_core_maxvl$next[6:0]$13651 $1\core_core_maxvl$next[6:0]$13631 + assign $3\core_core_pc$next[63:0]$13652 $1\core_core_pc$next[63:0]$13632 + assign $3\core_core_srcstep$next[6:0]$13653 $1\core_core_srcstep$next[6:0]$13633 + assign $3\core_core_subvl$next[1:0]$13654 $1\core_core_subvl$next[1:0]$13634 + assign $3\core_core_svstep$next[1:0]$13655 $1\core_core_svstep$next[1:0]$13635 + assign $3\core_core_vl$next[6:0]$13656 $1\core_core_vl$next[6:0]$13636 + assign $3\core_dec$next[63:0]$13657 $1\core_dec$next[63:0]$13637 + assign $3\core_eint$next[0:0]$13658 $1\core_eint$next[0:0]$13638 + assign $3\core_msr$next[63:0]$13659 $1\core_msr$next[63:0]$13639 end sync always - update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13915 - update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13916 - update \core_core_pc$next $0\core_core_pc$next[63:0]$13917 - update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13918 - update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13919 - update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13920 - update \core_core_vl$next $0\core_core_vl$next[6:0]$13921 - update \core_dec$next $0\core_dec$next[63:0]$13922 - update \core_eint$next $0\core_eint$next[0:0]$13923 - update \core_msr$next $0\core_msr$next[63:0]$13924 + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13620 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13621 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13622 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13623 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13624 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13625 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13626 + update \core_dec$next $0\core_dec$next[63:0]$13627 + update \core_eint$next $0\core_eint$next[0:0]$13628 + update \core_msr$next $0\core_msr$next[63:0]$13629 end - attribute \src "libresoc.v:201525.3-201554.6" - process $proc$libresoc.v:201525$13955 + attribute \src "libresoc.v:195909.3-195941.6" + process $proc$libresoc.v:195909$13660 assign { } { } assign { } { } assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13956 $4\core_raw_insn_i$next[31:0]$13960 - attribute \src "libresoc.v:201526.5-201526.29" + assign { } { } + assign $0\core_raw_insn_i$next[31:0]$13661 $5\core_raw_insn_i$next[31:0]$13666 + attribute \src "libresoc.v:195910.5-195910.29" switch \initial - attribute \src "libresoc.v:201526.9-201526.17" + attribute \src "libresoc.v:195910.9-195910.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'010 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13957 $2\core_raw_insn_i$next[31:0]$13958 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + assign $1\core_raw_insn_i$next[31:0]$13662 $2\core_raw_insn_i$next[31:0]$13663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13958 \dec2_raw_opcode_in + assign $2\core_raw_insn_i$next[31:0]$13663 \dec2_raw_opcode_in case - assign $2\core_raw_insn_i$next[31:0]$13958 \core_raw_insn_i + assign $2\core_raw_insn_i$next[31:0]$13663 \core_raw_insn_i end + case + assign $1\core_raw_insn_i$next[31:0]$13662 \core_raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13957 $3\core_raw_insn_i$next[31:0]$13959 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - switch \$165 + assign $3\core_raw_insn_i$next[31:0]$13664 $4\core_raw_insn_i$next[31:0]$13665 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + switch \$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13959 0 + assign $4\core_raw_insn_i$next[31:0]$13665 0 case - assign $3\core_raw_insn_i$next[31:0]$13959 \core_raw_insn_i + assign $4\core_raw_insn_i$next[31:0]$13665 $1\core_raw_insn_i$next[31:0]$13662 end case - assign $1\core_raw_insn_i$next[31:0]$13957 \core_raw_insn_i + assign $3\core_raw_insn_i$next[31:0]$13664 $1\core_raw_insn_i$next[31:0]$13662 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\core_raw_insn_i$next[31:0]$13960 0 + assign $5\core_raw_insn_i$next[31:0]$13666 0 case - assign $4\core_raw_insn_i$next[31:0]$13960 $1\core_raw_insn_i$next[31:0]$13957 + assign $5\core_raw_insn_i$next[31:0]$13666 $3\core_raw_insn_i$next[31:0]$13664 end sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13956 + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13661 end - attribute \src "libresoc.v:201555.3-201584.6" - process $proc$libresoc.v:201555$13961 + attribute \src "libresoc.v:195942.3-195974.6" + process $proc$libresoc.v:195942$13667 + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\core_bigendian_i$10$next[0:0]$13962 $4\core_bigendian_i$10$next[0:0]$13966 - attribute \src "libresoc.v:201556.5-201556.29" + assign $0\core_bigendian_i$10$next[0:0]$13668 $5\core_bigendian_i$10$next[0:0]$13673 + attribute \src "libresoc.v:195943.5-195943.29" switch \initial - attribute \src "libresoc.v:201556.9-201556.17" + attribute \src "libresoc.v:195943.9-195943.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'010 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13963 $2\core_bigendian_i$10$next[0:0]$13964 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + assign $1\core_bigendian_i$10$next[0:0]$13669 $2\core_bigendian_i$10$next[0:0]$13670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_bigendian_i$10$next[0:0]$13964 \core_bigendian_i + assign $2\core_bigendian_i$10$next[0:0]$13670 \core_bigendian_i case - assign $2\core_bigendian_i$10$next[0:0]$13964 \core_bigendian_i$10 + assign $2\core_bigendian_i$10$next[0:0]$13670 \core_bigendian_i$10 end + case + assign $1\core_bigendian_i$10$next[0:0]$13669 \core_bigendian_i$10 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13963 $3\core_bigendian_i$10$next[0:0]$13965 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - switch \$167 + assign $3\core_bigendian_i$10$next[0:0]$13671 $4\core_bigendian_i$10$next[0:0]$13672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + switch \$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_bigendian_i$10$next[0:0]$13965 1'0 + assign $4\core_bigendian_i$10$next[0:0]$13672 1'0 case - assign $3\core_bigendian_i$10$next[0:0]$13965 \core_bigendian_i$10 + assign $4\core_bigendian_i$10$next[0:0]$13672 $1\core_bigendian_i$10$next[0:0]$13669 end case - assign $1\core_bigendian_i$10$next[0:0]$13963 \core_bigendian_i$10 + assign $3\core_bigendian_i$10$next[0:0]$13671 $1\core_bigendian_i$10$next[0:0]$13669 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\core_bigendian_i$10$next[0:0]$13966 1'0 + assign $5\core_bigendian_i$10$next[0:0]$13673 1'0 case - assign $4\core_bigendian_i$10$next[0:0]$13966 $1\core_bigendian_i$10$next[0:0]$13963 + assign $5\core_bigendian_i$10$next[0:0]$13673 $3\core_bigendian_i$10$next[0:0]$13671 end sync always - update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13962 + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13668 end - attribute \src "libresoc.v:201585.3-201605.6" - process $proc$libresoc.v:201585$13967 + attribute \src "libresoc.v:195975.3-195985.6" + process $proc$libresoc.v:195975$13674 assign { } { } + assign { } { } + assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] + attribute \src "libresoc.v:195976.5-195976.29" + switch \initial + attribute \src "libresoc.v:195976.9-195976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\exec_insn_valid_i[0:0] 1'1 + case + assign $1\exec_insn_valid_i[0:0] 1'0 + end + sync always + update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] + end + attribute \src "libresoc.v:195986.3-196001.6" + process $proc$libresoc.v:195986$13675 assign { } { } assign { } { } - assign $0\ilatch$next[31:0]$13968 $3\ilatch$next[31:0]$13971 - attribute \src "libresoc.v:201586.5-201586.29" + assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] + attribute \src "libresoc.v:195987.5-195987.29" switch \initial - attribute \src "libresoc.v:201586.9-201586.17" + attribute \src "libresoc.v:195987.9-195987.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'100 assign { } { } - assign $1\ilatch$next[31:0]$13969 $2\ilatch$next[31:0]$13970 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" - switch \fetch_insn_valid_o + assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + switch \$143 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ilatch$next[31:0]$13970 \$169 + assign $2\exec_pc_valid_o[0:0] 1'1 case - assign $2\ilatch$next[31:0]$13970 \ilatch + assign $2\exec_pc_valid_o[0:0] 1'0 end case - assign $1\ilatch$next[31:0]$13969 \ilatch + assign $1\exec_pc_valid_o[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + sync always + update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] + end + attribute \src "libresoc.v:196002.3-196011.6" + process $proc$libresoc.v:196002$13676 + assign { } { } + assign { } { } + assign $0\core_wen$11[2:0]$13677 $1\core_wen$11[2:0]$13678 + attribute \src "libresoc.v:196003.5-196003.29" + switch \initial + attribute \src "libresoc.v:196003.9-196003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" + switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ilatch$next[31:0]$13971 0 + assign $1\core_wen$11[2:0]$13678 3'100 case - assign $3\ilatch$next[31:0]$13971 $1\ilatch$next[31:0]$13969 + assign $1\core_wen$11[2:0]$13678 3'000 end sync always - update \ilatch$next $0\ilatch$next[31:0]$13968 + update \core_wen$11 $0\core_wen$11[2:0]$13677 end - attribute \src "libresoc.v:201606.3-201625.6" - process $proc$libresoc.v:201606$13972 + attribute \src "libresoc.v:196012.3-196021.6" + process $proc$libresoc.v:196012$13679 assign { } { } assign { } { } - assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:201607.5-201607.29" + assign $0\core_data_i$12[63:0]$13680 $1\core_data_i$12[63:0]$13681 + attribute \src "libresoc.v:196013.5-196013.29" switch \initial - attribute \src "libresoc.v:201607.9-201607.17" + attribute \src "libresoc.v:196013.9-196013.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" + switch \update_svstate attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'1 assign { } { } - assign $1\core_ivalid_i[0:0] 1'1 + assign $1\core_data_i$12[63:0]$13681 \$145 + case + assign $1\core_data_i$12[63:0]$13681 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_data_i$12 $0\core_data_i$12[63:0]$13680 + end + attribute \src "libresoc.v:196022.3-196032.6" + process $proc$libresoc.v:196022$13682 + assign { } { } + assign { } { } + assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] + attribute \src "libresoc.v:196023.5-196023.29" + switch \initial + attribute \src "libresoc.v:196023.9-196023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'0 + assign { } { } + assign $1\exec_insn_ready_o[0:0] 1'1 + case + assign $1\exec_insn_ready_o[0:0] 1'0 + end + sync always + update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] + end + attribute \src "libresoc.v:196033.3-196057.6" + process $proc$libresoc.v:196033$13683 + assign { } { } + assign { } { } + assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:196034.5-196034.29" + switch \initial + attribute \src "libresoc.v:196034.9-196034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'0 assign { } { } assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" - switch \$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:372" + switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -418562,139 +409660,301 @@ module \ti case assign $2\core_ivalid_i[0:0] 1'0 end + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:379" + switch \$147 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_ivalid_i[0:0] 1'1 + case + assign $3\core_ivalid_i[0:0] 1'0 + end case assign $1\core_ivalid_i[0:0] 1'0 end sync always update \core_ivalid_i $0\core_ivalid_i[0:0] end - attribute \src "libresoc.v:201626.3-201636.6" - process $proc$libresoc.v:201626$13973 + attribute \src "libresoc.v:196058.3-196073.6" + process $proc$libresoc.v:196058$13684 assign { } { } assign { } { } assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:201627.5-201627.29" + attribute \src "libresoc.v:196059.5-196059.29" switch \initial - attribute \src "libresoc.v:201627.9-201627.17" + attribute \src "libresoc.v:196059.9-196059.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'0 assign { } { } - assign $1\core_issue_i[0:0] 1'1 + assign $1\core_issue_i[0:0] $2\core_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:372" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_issue_i[0:0] 1'1 + case + assign $2\core_issue_i[0:0] 1'0 + end case assign $1\core_issue_i[0:0] 1'0 end sync always update \core_issue_i $0\core_issue_i[0:0] end - attribute \src "libresoc.v:201637.3-201661.6" - process $proc$libresoc.v:201637$13974 + attribute \src "libresoc.v:196074.3-196108.6" + process $proc$libresoc.v:196074$13685 assign { } { } assign { } { } assign { } { } - assign $0\pc_changed$next[0:0]$13975 $3\pc_changed$next[0:0]$13978 - attribute \src "libresoc.v:201638.5-201638.29" + assign $0\exec_fsm_state$next[0:0]$13686 $5\exec_fsm_state$next[0:0]$13691 + attribute \src "libresoc.v:196075.5-196075.29" switch \initial - attribute \src "libresoc.v:201638.9-201638.17" + attribute \src "libresoc.v:196075.9-196075.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'0 assign { } { } - assign $1\pc_changed$next[0:0]$13976 1'0 + assign $1\exec_fsm_state$next[0:0]$13687 $2\exec_fsm_state$next[0:0]$13688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:372" + switch \exec_insn_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\exec_fsm_state$next[0:0]$13688 1'1 + case + assign $2\exec_fsm_state$next[0:0]$13688 \exec_fsm_state + end attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } - assign $1\pc_changed$next[0:0]$13976 $2\pc_changed$next[0:0]$13977 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" - switch \$178 + assign $1\exec_fsm_state$next[0:0]$13687 $3\exec_fsm_state$next[0:0]$13689 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + switch \$149 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\pc_changed$next[0:0]$13977 1'1 + assign $3\exec_fsm_state$next[0:0]$13689 $4\exec_fsm_state$next[0:0]$13690 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:394" + switch \exec_pc_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\exec_fsm_state$next[0:0]$13690 1'0 + case + assign $4\exec_fsm_state$next[0:0]$13690 \exec_fsm_state + end case - assign $2\pc_changed$next[0:0]$13977 \pc_changed + assign $3\exec_fsm_state$next[0:0]$13689 \exec_fsm_state end case - assign $1\pc_changed$next[0:0]$13976 \pc_changed + assign $1\exec_fsm_state$next[0:0]$13687 \exec_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\pc_changed$next[0:0]$13978 1'0 + assign $5\exec_fsm_state$next[0:0]$13691 1'0 case - assign $3\pc_changed$next[0:0]$13978 $1\pc_changed$next[0:0]$13976 + assign $5\exec_fsm_state$next[0:0]$13691 $1\exec_fsm_state$next[0:0]$13687 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$13975 + update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13686 end - attribute \src "libresoc.v:201662.3-201671.6" - process $proc$libresoc.v:201662$13979 + attribute \src "libresoc.v:196109.3-196137.6" + process $proc$libresoc.v:196109$13692 assign { } { } assign { } { } - assign $0\core_wen$11[2:0]$13980 $1\core_wen$11[2:0]$13981 - attribute \src "libresoc.v:201663.5-201663.29" + assign { } { } + assign $0\sv_changed$next[0:0]$13693 $4\sv_changed$next[0:0]$13697 + attribute \src "libresoc.v:196110.5-196110.29" switch \initial - attribute \src "libresoc.v:201663.9-201663.17" + attribute \src "libresoc.v:196110.9-196110.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:429" - switch \update_svstate + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_wen$11[2:0]$13981 3'100 + assign { } { } + assign $1\sv_changed$next[0:0]$13694 $3\sv_changed$next[0:0]$13696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:382" + switch \$151 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sv_changed$next[0:0]$13695 1'1 + case + assign $2\sv_changed$next[0:0]$13695 \sv_changed + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + switch \$155 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv_changed$next[0:0]$13696 1'0 + case + assign $3\sv_changed$next[0:0]$13696 $2\sv_changed$next[0:0]$13695 + end case - assign $1\core_wen$11[2:0]$13981 3'000 + assign $1\sv_changed$next[0:0]$13694 \sv_changed + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\sv_changed$next[0:0]$13697 1'0 + case + assign $4\sv_changed$next[0:0]$13697 $1\sv_changed$next[0:0]$13694 end sync always - update \core_wen$11 $0\core_wen$11[2:0]$13980 + update \sv_changed$next $0\sv_changed$next[0:0]$13693 end - attribute \src "libresoc.v:201672.3-201681.6" - process $proc$libresoc.v:201672$13982 + attribute \src "libresoc.v:196138.3-196166.6" + process $proc$libresoc.v:196138$13698 + assign { } { } assign { } { } assign { } { } - assign $0\core_data_i$12[63:0]$13983 $1\core_data_i$12[63:0]$13984 - attribute \src "libresoc.v:201673.5-201673.29" + assign $0\pc_changed$next[0:0]$13699 $4\pc_changed$next[0:0]$13703 + attribute \src "libresoc.v:196139.5-196139.29" switch \initial - attribute \src "libresoc.v:201673.9-201673.17" + attribute \src "libresoc.v:196139.9-196139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:429" - switch \update_svstate + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\pc_changed$next[0:0]$13700 $3\pc_changed$next[0:0]$13702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc_changed$next[0:0]$13701 1'1 + case + assign $2\pc_changed$next[0:0]$13701 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + switch \$161 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$13702 1'0 + case + assign $3\pc_changed$next[0:0]$13702 $2\pc_changed$next[0:0]$13701 + end + case + assign $1\pc_changed$next[0:0]$13700 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_data_i$12[63:0]$13984 \$182 + assign $4\pc_changed$next[0:0]$13703 1'0 + case + assign $4\pc_changed$next[0:0]$13703 $1\pc_changed$next[0:0]$13700 + end + sync always + update \pc_changed$next $0\pc_changed$next[0:0]$13699 + end + attribute \src "libresoc.v:196167.3-196182.6" + process $proc$libresoc.v:196167$13704 + assign { } { } + assign { } { } + assign $0\insn_done[0:0] $1\insn_done[0:0] + attribute \src "libresoc.v:196168.5-196168.29" + switch \initial + attribute \src "libresoc.v:196168.9-196168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\insn_done[0:0] $2\insn_done[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + switch \$163 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\insn_done[0:0] 1'1 + case + assign $2\insn_done[0:0] 1'0 + end + case + assign $1\insn_done[0:0] 1'0 + end + sync always + update \insn_done $0\insn_done[0:0] + end + attribute \src "libresoc.v:196183.3-196198.6" + process $proc$libresoc.v:196183$13705 + assign { } { } + assign { } { } + assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] + attribute \src "libresoc.v:196184.5-196184.29" + switch \initial + attribute \src "libresoc.v:196184.9-196184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\exec_pc_ready_i[0:0] 1'1 + case + assign $2\exec_pc_ready_i[0:0] 1'0 + end case - assign $1\core_data_i$12[63:0]$13984 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\exec_pc_ready_i[0:0] 1'0 end sync always - update \core_data_i$12 $0\core_data_i$12[63:0]$13983 + update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] end - attribute \src "libresoc.v:201682.3-201691.6" - process $proc$libresoc.v:201682$13985 + attribute \src "libresoc.v:196199.3-196208.6" + process $proc$libresoc.v:196199$13706 assign { } { } assign { } { } assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:201683.5-201683.29" + attribute \src "libresoc.v:196200.5-196200.29" switch \initial - attribute \src "libresoc.v:201683.9-201683.17" + attribute \src "libresoc.v:196200.9-196200.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:435" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:569" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -418706,18 +409966,18 @@ module \ti sync always update \core_dmi__addr $0\core_dmi__addr[4:0] end - attribute \src "libresoc.v:201692.3-201701.6" - process $proc$libresoc.v:201692$13986 + attribute \src "libresoc.v:196209.3-196218.6" + process $proc$libresoc.v:196209$13707 assign { } { } assign { } { } assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:201693.5-201693.29" + attribute \src "libresoc.v:196210.5-196210.29" switch \initial - attribute \src "libresoc.v:201693.9-201693.17" + attribute \src "libresoc.v:196210.9-196210.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:435" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:569" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -418729,14 +409989,14 @@ module \ti sync always update \core_dmi__ren $0\core_dmi__ren[0:0] end - attribute \src "libresoc.v:201702.3-201710.6" - process $proc$libresoc.v:201702$13987 + attribute \src "libresoc.v:196219.3-196227.6" + process $proc$libresoc.v:196219$13708 assign { } { } assign { } { } - assign $0\d_reg_delay$next[0:0]$13988 $1\d_reg_delay$next[0:0]$13989 - attribute \src "libresoc.v:201703.5-201703.29" + assign $0\d_reg_delay$next[0:0]$13709 $1\d_reg_delay$next[0:0]$13710 + attribute \src "libresoc.v:196220.5-196220.29" switch \initial - attribute \src "libresoc.v:201703.9-201703.17" + attribute \src "libresoc.v:196220.9-196220.17" case 1'1 case end @@ -418745,25 +410005,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_reg_delay$next[0:0]$13989 1'0 + assign $1\d_reg_delay$next[0:0]$13710 1'0 case - assign $1\d_reg_delay$next[0:0]$13989 \dbg_d_gpr_req + assign $1\d_reg_delay$next[0:0]$13710 \dbg_d_gpr_req end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13988 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13709 end - attribute \src "libresoc.v:201711.3-201720.6" - process $proc$libresoc.v:201711$13990 + attribute \src "libresoc.v:196228.3-196237.6" + process $proc$libresoc.v:196228$13711 assign { } { } assign { } { } assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:201712.5-201712.29" + attribute \src "libresoc.v:196229.5-196229.29" switch \initial - attribute \src "libresoc.v:201712.9-201712.17" + attribute \src "libresoc.v:196229.9-196229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -418775,18 +410035,18 @@ module \ti sync always update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "libresoc.v:201721.3-201730.6" - process $proc$libresoc.v:201721$13991 + attribute \src "libresoc.v:196238.3-196247.6" + process $proc$libresoc.v:196238$13712 assign { } { } assign { } { } assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:201722.5-201722.29" + attribute \src "libresoc.v:196239.5-196239.29" switch \initial - attribute \src "libresoc.v:201722.9-201722.17" + attribute \src "libresoc.v:196239.9-196239.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -418798,18 +410058,18 @@ module \ti sync always update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "libresoc.v:201731.3-201740.6" - process $proc$libresoc.v:201731$13992 + attribute \src "libresoc.v:196248.3-196257.6" + process $proc$libresoc.v:196248$13713 assign { } { } assign { } { } assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:201732.5-201732.29" + attribute \src "libresoc.v:196249.5-196249.29" switch \initial - attribute \src "libresoc.v:201732.9-201732.17" + attribute \src "libresoc.v:196249.9-196249.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -418821,14 +410081,14 @@ module \ti sync always update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] end - attribute \src "libresoc.v:201741.3-201749.6" - process $proc$libresoc.v:201741$13993 + attribute \src "libresoc.v:196258.3-196266.6" + process $proc$libresoc.v:196258$13714 assign { } { } assign { } { } - assign $0\d_cr_delay$next[0:0]$13994 $1\d_cr_delay$next[0:0]$13995 - attribute \src "libresoc.v:201742.5-201742.29" + assign $0\d_cr_delay$next[0:0]$13715 $1\d_cr_delay$next[0:0]$13716 + attribute \src "libresoc.v:196259.5-196259.29" switch \initial - attribute \src "libresoc.v:201742.9-201742.17" + attribute \src "libresoc.v:196259.9-196259.17" case 1'1 case end @@ -418837,48 +410097,48 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$13995 1'0 + assign $1\d_cr_delay$next[0:0]$13716 1'0 case - assign $1\d_cr_delay$next[0:0]$13995 \dbg_d_cr_req + assign $1\d_cr_delay$next[0:0]$13716 \dbg_d_cr_req end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13994 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13715 end - attribute \src "libresoc.v:201750.3-201759.6" - process $proc$libresoc.v:201750$13996 + attribute \src "libresoc.v:196267.3-196276.6" + process $proc$libresoc.v:196267$13717 assign { } { } assign { } { } assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:201751.5-201751.29" + attribute \src "libresoc.v:196268.5-196268.29" switch \initial - attribute \src "libresoc.v:201751.9-201751.17" + attribute \src "libresoc.v:196268.9-196268.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:455" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:589" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_cr_data[63:0] \$184 + assign $1\dbg_d_cr_data[63:0] \$167 case assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "libresoc.v:201760.3-201769.6" - process $proc$libresoc.v:201760$13997 + attribute \src "libresoc.v:196277.3-196286.6" + process $proc$libresoc.v:196277$13718 assign { } { } assign { } { } assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:201761.5-201761.29" + attribute \src "libresoc.v:196278.5-196278.29" switch \initial - attribute \src "libresoc.v:201761.9-201761.17" + attribute \src "libresoc.v:196278.9-196278.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:455" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:589" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -418890,18 +410150,18 @@ module \ti sync always update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "libresoc.v:201770.3-201779.6" - process $proc$libresoc.v:201770$13998 + attribute \src "libresoc.v:196287.3-196296.6" + process $proc$libresoc.v:196287$13719 assign { } { } assign { } { } assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:201771.5-201771.29" + attribute \src "libresoc.v:196288.5-196288.29" switch \initial - attribute \src "libresoc.v:201771.9-201771.17" + attribute \src "libresoc.v:196288.9-196288.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:461" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -418913,14 +410173,14 @@ module \ti sync always update \core_full_rd__ren $0\core_full_rd__ren[2:0] end - attribute \src "libresoc.v:201780.3-201788.6" - process $proc$libresoc.v:201780$13999 + attribute \src "libresoc.v:196297.3-196305.6" + process $proc$libresoc.v:196297$13720 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$14000 $1\d_xer_delay$next[0:0]$14001 - attribute \src "libresoc.v:201781.5-201781.29" + assign $0\d_xer_delay$next[0:0]$13721 $1\d_xer_delay$next[0:0]$13722 + attribute \src "libresoc.v:196298.5-196298.29" switch \initial - attribute \src "libresoc.v:201781.9-201781.17" + attribute \src "libresoc.v:196298.9-196298.17" case 1'1 case end @@ -418929,48 +410189,48 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$14001 1'0 + assign $1\d_xer_delay$next[0:0]$13722 1'0 case - assign $1\d_xer_delay$next[0:0]$14001 \dbg_d_xer_req + assign $1\d_xer_delay$next[0:0]$13722 \dbg_d_xer_req end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$14000 + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13721 end - attribute \src "libresoc.v:201789.3-201798.6" - process $proc$libresoc.v:201789$14002 + attribute \src "libresoc.v:196306.3-196315.6" + process $proc$libresoc.v:196306$13723 assign { } { } assign { } { } assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:201790.5-201790.29" + attribute \src "libresoc.v:196307.5-196307.29" switch \initial - attribute \src "libresoc.v:201790.9-201790.17" + attribute \src "libresoc.v:196307.9-196307.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:465" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_d_xer_data[63:0] \$186 + assign $1\dbg_d_xer_data[63:0] \$169 case assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "libresoc.v:201799.3-201808.6" - process $proc$libresoc.v:201799$14003 + attribute \src "libresoc.v:196316.3-196325.6" + process $proc$libresoc.v:196316$13724 assign { } { } assign { } { } assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:201800.5-201800.29" + attribute \src "libresoc.v:196317.5-196317.29" switch \initial - attribute \src "libresoc.v:201800.9-201800.17" + attribute \src "libresoc.v:196317.9-196317.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:465" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -418982,19 +410242,19 @@ module \ti sync always update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "libresoc.v:201809.3-201823.6" - process $proc$libresoc.v:201809$14004 + attribute \src "libresoc.v:196326.3-196340.6" + process $proc$libresoc.v:196326$13725 assign { } { } assign { } { } assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:201810.5-201810.29" + attribute \src "libresoc.v:196327.5-196327.29" switch \initial - attribute \src "libresoc.v:201810.9-201810.17" + attribute \src "libresoc.v:196327.9-196327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - switch \fsm_state$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } @@ -419009,19 +410269,19 @@ module \ti sync always update \core_issue__addr $0\core_issue__addr[2:0] end - attribute \src "libresoc.v:201824.3-201838.6" - process $proc$libresoc.v:201824$14005 + attribute \src "libresoc.v:196341.3-196355.6" + process $proc$libresoc.v:196341$13726 assign { } { } assign { } { } assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:201825.5-201825.29" + attribute \src "libresoc.v:196342.5-196342.29" switch \initial - attribute \src "libresoc.v:201825.9-201825.17" + attribute \src "libresoc.v:196342.9-196342.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - switch \fsm_state$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } @@ -419036,114 +410296,114 @@ module \ti sync always update \core_issue__ren $0\core_issue__ren[0:0] end - attribute \src "libresoc.v:201839.3-201866.6" - process $proc$libresoc.v:201839$14006 + attribute \src "libresoc.v:196356.3-196383.6" + process $proc$libresoc.v:196356$13727 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$188$next[1:0]$14007 $2\fsm_state$188$next[1:0]$14009 - attribute \src "libresoc.v:201840.5-201840.29" + assign $0\fsm_state$next[1:0]$13728 $2\fsm_state$next[1:0]$13730 + attribute \src "libresoc.v:196357.5-196357.29" switch \initial - attribute \src "libresoc.v:201840.9-201840.17" + attribute \src "libresoc.v:196357.9-196357.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - switch \fsm_state$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$188$next[1:0]$14008 2'01 + assign $1\fsm_state$next[1:0]$13729 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$188$next[1:0]$14008 2'10 + assign $1\fsm_state$next[1:0]$13729 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$188$next[1:0]$14008 2'11 + assign $1\fsm_state$next[1:0]$13729 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fsm_state$188$next[1:0]$14008 2'00 + assign $1\fsm_state$next[1:0]$13729 2'00 case - assign $1\fsm_state$188$next[1:0]$14008 \fsm_state$188 + assign $1\fsm_state$next[1:0]$13729 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$188$next[1:0]$14009 2'00 + assign $2\fsm_state$next[1:0]$13730 2'00 case - assign $2\fsm_state$188$next[1:0]$14009 $1\fsm_state$188$next[1:0]$14008 + assign $2\fsm_state$next[1:0]$13730 $1\fsm_state$next[1:0]$13729 end sync always - update \fsm_state$188$next $0\fsm_state$188$next[1:0]$14007 + update \fsm_state$next $0\fsm_state$next[1:0]$13728 end - attribute \src "libresoc.v:201867.3-201877.6" - process $proc$libresoc.v:201867$14010 + attribute \src "libresoc.v:196384.3-196394.6" + process $proc$libresoc.v:196384$13731 assign { } { } assign { } { } assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:201868.5-201868.29" + attribute \src "libresoc.v:196385.5-196385.29" switch \initial - attribute \src "libresoc.v:201868.9-201868.17" + attribute \src "libresoc.v:196385.9-196385.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - switch \fsm_state$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\new_dec[63:0] \$189 [63:0] + assign $1\new_dec[63:0] \$171 [63:0] case assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_dec $0\new_dec[63:0] end - attribute \src "libresoc.v:201878.3-201892.6" - process $proc$libresoc.v:201878$14011 + attribute \src "libresoc.v:196395.3-196409.6" + process $proc$libresoc.v:196395$13732 assign { } { } assign { } { } - assign $0\core_issue__addr$13[2:0]$14012 $1\core_issue__addr$13[2:0]$14013 - attribute \src "libresoc.v:201879.5-201879.29" + assign $0\core_issue__addr$13[2:0]$13733 $1\core_issue__addr$13[2:0]$13734 + attribute \src "libresoc.v:196396.5-196396.29" switch \initial - attribute \src "libresoc.v:201879.9-201879.17" + attribute \src "libresoc.v:196396.9-196396.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - switch \fsm_state$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__addr$13[2:0]$14013 3'110 + assign $1\core_issue__addr$13[2:0]$13734 3'110 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_issue__addr$13[2:0]$14013 3'111 + assign $1\core_issue__addr$13[2:0]$13734 3'111 case - assign $1\core_issue__addr$13[2:0]$14013 3'000 + assign $1\core_issue__addr$13[2:0]$13734 3'000 end sync always - update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$14012 + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13733 end - attribute \src "libresoc.v:201893.3-201907.6" - process $proc$libresoc.v:201893$14014 + attribute \src "libresoc.v:196410.3-196424.6" + process $proc$libresoc.v:196410$13735 assign { } { } assign { } { } assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:201894.5-201894.29" + attribute \src "libresoc.v:196411.5-196411.29" switch \initial - attribute \src "libresoc.v:201894.9-201894.17" + attribute \src "libresoc.v:196411.9-196411.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - switch \fsm_state$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } @@ -419158,19 +410418,19 @@ module \ti sync always update \core_issue__wen $0\core_issue__wen[0:0] end - attribute \src "libresoc.v:201908.3-201922.6" - process $proc$libresoc.v:201908$14015 + attribute \src "libresoc.v:196425.3-196439.6" + process $proc$libresoc.v:196425$13736 assign { } { } assign { } { } assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:201909.5-201909.29" + attribute \src "libresoc.v:196426.5-196426.29" switch \initial - attribute \src "libresoc.v:201909.9-201909.17" + attribute \src "libresoc.v:196426.9-196426.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - switch \fsm_state$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } @@ -419185,70 +410445,70 @@ module \ti sync always update \core_issue__data_i $0\core_issue__data_i[63:0] end - attribute \src "libresoc.v:201923.3-201938.6" - process $proc$libresoc.v:201923$14016 + attribute \src "libresoc.v:196440.3-196455.6" + process $proc$libresoc.v:196440$13737 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$14017 $2\dec2_cur_dec$next[63:0]$14019 - attribute \src "libresoc.v:201924.5-201924.29" + assign $0\dec2_cur_dec$next[63:0]$13738 $2\dec2_cur_dec$next[63:0]$13740 + attribute \src "libresoc.v:196441.5-196441.29" switch \initial - attribute \src "libresoc.v:201924.9-201924.17" + attribute \src "libresoc.v:196441.9-196441.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - switch \fsm_state$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$14018 \new_dec + assign $1\dec2_cur_dec$next[63:0]$13739 \new_dec case - assign $1\dec2_cur_dec$next[63:0]$14018 \dec2_cur_dec + assign $1\dec2_cur_dec$next[63:0]$13739 \dec2_cur_dec end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$14019 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dec2_cur_dec$next[63:0]$13740 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dec2_cur_dec$next[63:0]$14019 $1\dec2_cur_dec$next[63:0]$14018 + assign $2\dec2_cur_dec$next[63:0]$13740 $1\dec2_cur_dec$next[63:0]$13739 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$14017 + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13738 end - attribute \src "libresoc.v:201939.3-201949.6" - process $proc$libresoc.v:201939$14020 + attribute \src "libresoc.v:196456.3-196466.6" + process $proc$libresoc.v:196456$13741 assign { } { } assign { } { } assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:201940.5-201940.29" + attribute \src "libresoc.v:196457.5-196457.29" switch \initial - attribute \src "libresoc.v:201940.9-201940.17" + attribute \src "libresoc.v:196457.9-196457.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" - switch \fsm_state$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\new_tb[63:0] \$192 [63:0] + assign $1\new_tb[63:0] \$174 [63:0] case assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:201950.3-201958.6" - process $proc$libresoc.v:201950$14021 + attribute \src "libresoc.v:196467.3-196475.6" + process $proc$libresoc.v:196467$13742 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$14022 $1\dbg_dmi_we_i$next[0:0]$14023 - attribute \src "libresoc.v:201951.5-201951.29" + assign $0\dbg_dmi_we_i$next[0:0]$13743 $1\dbg_dmi_we_i$next[0:0]$13744 + attribute \src "libresoc.v:196468.5-196468.29" switch \initial - attribute \src "libresoc.v:201951.9-201951.17" + attribute \src "libresoc.v:196468.9-196468.17" case 1'1 case end @@ -419257,21 +410517,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$14023 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$13744 1'0 case - assign $1\dbg_dmi_we_i$next[0:0]$14023 \jtag_dmi0__we_i + assign $1\dbg_dmi_we_i$next[0:0]$13744 \jtag_dmi0__we_i end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$14022 + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13743 end - attribute \src "libresoc.v:201959.3-201967.6" - process $proc$libresoc.v:201959$14024 + attribute \src "libresoc.v:196476.3-196484.6" + process $proc$libresoc.v:196476$13745 assign { } { } assign { } { } - assign $0\pc_ok_delay$next[0:0]$14025 $1\pc_ok_delay$next[0:0]$14026 - attribute \src "libresoc.v:201960.5-201960.29" + assign $0\pc_ok_delay$next[0:0]$13746 $1\pc_ok_delay$next[0:0]$13747 + attribute \src "libresoc.v:196477.5-196477.29" switch \initial - attribute \src "libresoc.v:201960.9-201960.17" + attribute \src "libresoc.v:196477.9-196477.17" case 1'1 case end @@ -419280,26 +410540,26 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\pc_ok_delay$next[0:0]$14026 1'0 + assign $1\pc_ok_delay$next[0:0]$13747 1'0 case - assign $1\pc_ok_delay$next[0:0]$14026 \$38 + assign $1\pc_ok_delay$next[0:0]$13747 \$38 end sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$14025 + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13746 end - attribute \src "libresoc.v:201968.3-201983.6" - process $proc$libresoc.v:201968$14027 + attribute \src "libresoc.v:196485.3-196500.6" + process $proc$libresoc.v:196485$13748 assign { } { } assign { } { } assign { } { } assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:201969.5-201969.29" + attribute \src "libresoc.v:196486.5-196486.29" switch \initial - attribute \src "libresoc.v:201969.9-201969.17" + attribute \src "libresoc.v:196486.9-196486.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -419308,7 +410568,7 @@ module \ti case assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:489" switch \pc_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -419320,18 +410580,18 @@ module \ti sync always update \pc $0\pc[63:0] end - attribute \src "libresoc.v:201984.3-201996.6" - process $proc$libresoc.v:201984$14028 + attribute \src "libresoc.v:196501.3-196513.6" + process $proc$libresoc.v:196501$13749 assign { } { } assign { } { } assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] - attribute \src "libresoc.v:201985.5-201985.29" + attribute \src "libresoc.v:196502.5-196502.29" switch \initial - attribute \src "libresoc.v:201985.9-201985.17" + attribute \src "libresoc.v:196502.9-196502.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:482" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -419344,35 +410604,147 @@ module \ti sync always update \core_cia__ren $0\core_cia__ren[2:0] end - attribute \src "libresoc.v:201997.3-202017.6" - process $proc$libresoc.v:201997$14029 + attribute \src "libresoc.v:196514.3-196522.6" + process $proc$libresoc.v:196514$13750 + assign { } { } + assign { } { } + assign $0\svstate_ok_delay$next[0:0]$13751 $1\svstate_ok_delay$next[0:0]$13752 + attribute \src "libresoc.v:196515.5-196515.29" + switch \initial + attribute \src "libresoc.v:196515.9-196515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\svstate_ok_delay$next[0:0]$13752 1'0 + case + assign $1\svstate_ok_delay$next[0:0]$13752 \$40 + end + sync always + update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13751 + end + attribute \src "libresoc.v:196523.3-196538.6" + process $proc$libresoc.v:196523$13753 + assign { } { } + assign { } { } + assign { } { } + assign $0\svstate[63:0] $2\svstate[63:0] + attribute \src "libresoc.v:196524.5-196524.29" + switch \initial + attribute \src "libresoc.v:196524.9-196524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:496" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\svstate[63:0] \$42 + case + assign $1\svstate[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:503" + switch \svstate_ok_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\svstate[63:0] \core_sv__data_o + case + assign $2\svstate[63:0] $1\svstate[63:0] + end + sync always + update \svstate $0\svstate[63:0] + end + attribute \src "libresoc.v:196539.3-196551.6" + process $proc$libresoc.v:196539$13754 + assign { } { } + assign { } { } + assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] + attribute \src "libresoc.v:196540.5-196540.29" + switch \initial + attribute \src "libresoc.v:196540.9-196540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:496" + switch \svstate_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\core_sv__ren[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\core_sv__ren[2:0] 3'100 + end + sync always + update \core_sv__ren $0\core_sv__ren[2:0] + end + attribute \src "libresoc.v:196552.3-196560.6" + process $proc$libresoc.v:196552$13755 + assign { } { } + assign { } { } + assign $0\dbg_dmi_din$next[63:0]$13756 $1\dbg_dmi_din$next[63:0]$13757 + attribute \src "libresoc.v:196553.5-196553.29" + switch \initial + attribute \src "libresoc.v:196553.9-196553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_din$next[63:0]$13757 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\dbg_dmi_din$next[63:0]$13757 \jtag_dmi0__din + end + sync always + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13756 + end + attribute \src "libresoc.v:196561.3-196586.6" + process $proc$libresoc.v:196561$13758 assign { } { } assign { } { } assign $0\core_wen[2:0] $1\core_wen[2:0] - attribute \src "libresoc.v:201998.5-201998.29" + attribute \src "libresoc.v:196562.5-196562.29" switch \initial - attribute \src "libresoc.v:201998.9-201998.17" + attribute \src "libresoc.v:196562.9-196562.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'100 assign { } { } assign $1\core_wen[2:0] $2\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - switch \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\core_wen[2:0] $3\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:417" - switch \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_wen[2:0] 3'001 + assign $3\core_wen[2:0] $4\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328" + switch \$50 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_wen[2:0] 3'001 + case + assign $4\core_wen[2:0] 3'000 + end case assign $3\core_wen[2:0] 3'000 end @@ -419385,35 +410757,44 @@ module \ti sync always update \core_wen $0\core_wen[2:0] end - attribute \src "libresoc.v:202018.3-202038.6" - process $proc$libresoc.v:202018$14030 + attribute \src "libresoc.v:196587.3-196612.6" + process $proc$libresoc.v:196587$13759 assign { } { } assign { } { } assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:202019.5-202019.29" + attribute \src "libresoc.v:196588.5-196588.29" switch \initial - attribute \src "libresoc.v:202019.9-202019.17" + attribute \src "libresoc.v:196588.9-196588.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'100 assign { } { } assign $1\core_data_i[63:0] $2\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - switch \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + switch \$56 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\core_data_i[63:0] $3\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:417" - switch \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_data_i[63:0] \nia + assign $3\core_data_i[63:0] $4\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:328" + switch \$58 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_data_i[63:0] \nia + case + assign $4\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end case assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end @@ -419426,79 +410807,29 @@ module \ti sync always update \core_data_i $0\core_data_i[63:0] end - attribute \src "libresoc.v:202039.3-202059.6" - process $proc$libresoc.v:202039$14031 - assign { } { } - assign { } { } - assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] - attribute \src "libresoc.v:202040.5-202040.29" - switch \initial - attribute \src "libresoc.v:202040.9-202040.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" - switch \fetch_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\core_sv__ren[2:0] $2\core_sv__ren[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$52 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_sv__ren[2:0] $3\core_sv__ren[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" - switch \fetch_pc_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_sv__ren[2:0] 3'100 - case - assign $3\core_sv__ren[2:0] 3'000 - end - case - assign $2\core_sv__ren[2:0] 3'000 - end - case - assign $1\core_sv__ren[2:0] 3'000 - end - sync always - update \core_sv__ren $0\core_sv__ren[2:0] - end - attribute \src "libresoc.v:202060.3-202080.6" - process $proc$libresoc.v:202060$14032 + attribute \src "libresoc.v:196613.3-196628.6" + process $proc$libresoc.v:196613$13760 assign { } { } assign { } { } assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] - attribute \src "libresoc.v:202061.5-202061.29" + attribute \src "libresoc.v:196614.5-196614.29" switch \initial - attribute \src "libresoc.v:202061.9-202061.17" + attribute \src "libresoc.v:196614.9-196614.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" + switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_msr__ren[2:0] $3\core_msr__ren[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" - switch \fetch_pc_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_msr__ren[2:0] 3'010 - case - assign $3\core_msr__ren[2:0] 3'000 - end + assign $2\core_msr__ren[2:0] 3'010 case assign $2\core_msr__ren[2:0] 3'000 end @@ -419508,14 +410839,14 @@ module \ti sync always update \core_msr__ren $0\core_msr__ren[2:0] end - attribute \src "libresoc.v:202081.3-202089.6" - process $proc$libresoc.v:202081$14033 + attribute \src "libresoc.v:196629.3-196637.6" + process $proc$libresoc.v:196629$13761 assign { } { } assign { } { } - assign $0\dbg_dmi_din$next[63:0]$14034 $1\dbg_dmi_din$next[63:0]$14035 - attribute \src "libresoc.v:202082.5-202082.29" + assign $0\jtag_dmi0__ack_o$next[0:0]$13762 $1\jtag_dmi0__ack_o$next[0:0]$13763 + attribute \src "libresoc.v:196630.5-196630.29" switch \initial - attribute \src "libresoc.v:202082.9-202082.17" + attribute \src "libresoc.v:196630.9-196630.17" case 1'1 case end @@ -419524,102 +410855,84 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_din$next[63:0]$14035 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_dmi0__ack_o$next[0:0]$13763 1'0 case - assign $1\dbg_dmi_din$next[63:0]$14035 \jtag_dmi0__din + assign $1\jtag_dmi0__ack_o$next[0:0]$13763 \dbg_dmi_ack_o end sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$14034 + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13762 end - attribute \src "libresoc.v:202090.3-202105.6" - process $proc$libresoc.v:202090$14036 + attribute \src "libresoc.v:196638.3-196648.6" + process $proc$libresoc.v:196638$13764 assign { } { } assign { } { } assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:202091.5-202091.29" + attribute \src "libresoc.v:196639.5-196639.29" switch \initial - attribute \src "libresoc.v:202091.9-202091.17" + attribute \src "libresoc.v:196639.9-196639.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fetch_pc_ready_o[0:0] $2\fetch_pc_ready_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$64 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fetch_pc_ready_o[0:0] 1'1 - case - assign $2\fetch_pc_ready_o[0:0] 1'0 - end + assign $1\fetch_pc_ready_o[0:0] 1'1 case assign $1\fetch_pc_ready_o[0:0] 1'0 end sync always update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] end - attribute \src "libresoc.v:202106.3-202146.6" - process $proc$libresoc.v:202106$14037 + attribute \src "libresoc.v:196649.3-196684.6" + process $proc$libresoc.v:196649$13765 assign { } { } assign { } { } assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:202107.5-202107.29" + attribute \src "libresoc.v:196650.5-196650.29" switch \initial - attribute \src "libresoc.v:202107.9-202107.17" + attribute \src "libresoc.v:196650.9-196650.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" + switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\imem_a_pc_i[47:0] $3\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" - switch \fetch_pc_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_a_pc_i[47:0] \pc [47:0] - case - assign $3\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 - end + assign $2\imem_a_pc_i[47:0] \pc [47:0] case assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\imem_a_pc_i[47:0] $4\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + assign $1\imem_a_pc_i[47:0] $3\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + assign $3\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\imem_a_pc_i[47:0] $5\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - switch \$72 + assign $3\imem_a_pc_i[47:0] $4\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \$60 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $5\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + assign $4\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\imem_a_pc_i[47:0] \$74 [47:0] + assign $4\imem_a_pc_i[47:0] \$62 [47:0] end end case @@ -419628,78 +410941,69 @@ module \ti sync always update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "libresoc.v:202147.3-202196.6" - process $proc$libresoc.v:202147$14038 + attribute \src "libresoc.v:196685.3-196729.6" + process $proc$libresoc.v:196685$13766 assign { } { } assign { } { } assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:202148.5-202148.29" + attribute \src "libresoc.v:196686.5-196686.29" switch \initial - attribute \src "libresoc.v:202148.9-202148.17" + attribute \src "libresoc.v:196686.9-196686.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" + switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" - switch \fetch_pc_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_a_valid_i[0:0] 1'1 - case - assign $3\imem_a_valid_i[0:0] 1'0 - end + assign $2\imem_a_valid_i[0:0] 1'1 case assign $2\imem_a_valid_i[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\imem_a_valid_i[0:0] 1'1 + assign $3\imem_a_valid_i[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\imem_a_valid_i[0:0] $5\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - switch \$83 + assign $3\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \$65 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $5\imem_a_valid_i[0:0] 1'0 + assign $4\imem_a_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\imem_a_valid_i[0:0] 1'1 + assign $4\imem_a_valid_i[0:0] 1'1 end end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\imem_a_valid_i[0:0] $6\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" + assign $1\imem_a_valid_i[0:0] $5\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\imem_a_valid_i[0:0] 1'1 + assign $5\imem_a_valid_i[0:0] 1'1 case - assign $6\imem_a_valid_i[0:0] 1'0 + assign $5\imem_a_valid_i[0:0] 1'0 end case assign $1\imem_a_valid_i[0:0] 1'0 @@ -419707,78 +411011,69 @@ module \ti sync always update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "libresoc.v:202197.3-202246.6" - process $proc$libresoc.v:202197$14039 + attribute \src "libresoc.v:196730.3-196774.6" + process $proc$libresoc.v:196730$13767 assign { } { } assign { } { } assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:202198.5-202198.29" + attribute \src "libresoc.v:196731.5-196731.29" switch \initial - attribute \src "libresoc.v:202198.9-202198.17" + attribute \src "libresoc.v:196731.9-196731.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" + switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" - switch \fetch_pc_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_f_valid_i[0:0] 1'1 - case - assign $3\imem_f_valid_i[0:0] 1'0 - end + assign $2\imem_f_valid_i[0:0] 1'1 case assign $2\imem_f_valid_i[0:0] 1'0 end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\imem_f_valid_i[0:0] 1'1 + assign $3\imem_f_valid_i[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\imem_f_valid_i[0:0] $5\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - switch \$91 + assign $3\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $5\imem_f_valid_i[0:0] 1'0 + assign $4\imem_f_valid_i[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\imem_f_valid_i[0:0] 1'1 + assign $4\imem_f_valid_i[0:0] 1'1 end end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\imem_f_valid_i[0:0] $6\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" + assign $1\imem_f_valid_i[0:0] $5\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\imem_f_valid_i[0:0] 1'1 + assign $5\imem_f_valid_i[0:0] 1'1 case - assign $6\imem_f_valid_i[0:0] 1'0 + assign $5\imem_f_valid_i[0:0] 1'0 end case assign $1\imem_f_valid_i[0:0] 1'0 @@ -419786,362 +411081,188 @@ module \ti sync always update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:202247.3-202272.6" - process $proc$libresoc.v:202247$14040 + attribute \src "libresoc.v:196775.3-196795.6" + process $proc$libresoc.v:196775$13768 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_pc$next[63:0]$14041 $4\dec2_cur_pc$next[63:0]$14045 - attribute \src "libresoc.v:202248.5-202248.29" + assign $0\dec2_cur_pc$next[63:0]$13769 $3\dec2_cur_pc$next[63:0]$13772 + attribute \src "libresoc.v:196776.5-196776.29" switch \initial - attribute \src "libresoc.v:202248.9-202248.17" + attribute \src "libresoc.v:196776.9-196776.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$14042 $2\dec2_cur_pc$next[63:0]$14043 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$97 + assign $1\dec2_cur_pc$next[63:0]$13770 $2\dec2_cur_pc$next[63:0]$13771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" + switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_pc$next[63:0]$14043 $3\dec2_cur_pc$next[63:0]$14044 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" - switch \fetch_pc_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dec2_cur_pc$next[63:0]$14044 \pc - case - assign $3\dec2_cur_pc$next[63:0]$14044 \dec2_cur_pc - end + assign $2\dec2_cur_pc$next[63:0]$13771 \pc case - assign $2\dec2_cur_pc$next[63:0]$14043 \dec2_cur_pc + assign $2\dec2_cur_pc$next[63:0]$13771 \dec2_cur_pc end case - assign $1\dec2_cur_pc$next[63:0]$14042 \dec2_cur_pc + assign $1\dec2_cur_pc$next[63:0]$13770 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dec2_cur_pc$next[63:0]$14045 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_pc$next[63:0]$13772 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\dec2_cur_pc$next[63:0]$14045 $1\dec2_cur_pc$next[63:0]$14042 + assign $3\dec2_cur_pc$next[63:0]$13772 $1\dec2_cur_pc$next[63:0]$13770 end sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$14041 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13769 end - attribute \src "libresoc.v:202273.3-202307.6" - process $proc$libresoc.v:202273$14046 + attribute \src "libresoc.v:196796.3-196834.6" + process $proc$libresoc.v:196796$13773 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\msr_read$next[0:0]$14047 $5\msr_read$next[0:0]$14052 - attribute \src "libresoc.v:202274.5-202274.29" - switch \initial - attribute \src "libresoc.v:202274.9-202274.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" - switch \fetch_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\msr_read$next[0:0]$14048 $2\msr_read$next[0:0]$14049 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$103 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr_read$next[0:0]$14049 $3\msr_read$next[0:0]$14050 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" - switch \fetch_pc_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr_read$next[0:0]$14050 1'0 - case - assign $3\msr_read$next[0:0]$14050 \msr_read - end - case - assign $2\msr_read$next[0:0]$14049 \msr_read - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\msr_read$next[0:0]$14048 $4\msr_read$next[0:0]$14051 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" - switch \$105 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr_read$next[0:0]$14051 1'1 - case - assign $4\msr_read$next[0:0]$14051 \msr_read - end - case - assign $1\msr_read$next[0:0]$14048 \msr_read - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\msr_read$next[0:0]$14052 1'1 - case - assign $5\msr_read$next[0:0]$14052 $1\msr_read$next[0:0]$14048 - end - sync always - update \msr_read$next $0\msr_read$next[0:0]$14047 - end - attribute \src "libresoc.v:202308.3-202342.6" - process $proc$libresoc.v:202308$14053 assign { } { } assign { } { } assign { } { } - assign $0\sv_read$next[0:0]$14054 $5\sv_read$next[0:0]$14059 - attribute \src "libresoc.v:202309.5-202309.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cur_cur_dststep$next[6:0]$13774 $4\cur_cur_dststep$next[6:0]$13798 + assign $0\cur_cur_maxvl$next[6:0]$13775 $4\cur_cur_maxvl$next[6:0]$13799 + assign $0\cur_cur_subvl$next[1:0]$13776 $4\cur_cur_subvl$next[1:0]$13800 + assign $0\cur_cur_svstep$next[1:0]$13777 $4\cur_cur_svstep$next[1:0]$13801 + assign $0\cur_cur_vl$next[6:0]$13778 $4\cur_cur_vl$next[6:0]$13802 + assign $0\dec2_cur_cur_srcstep$next[6:0]$13779 $4\dec2_cur_cur_srcstep$next[6:0]$13803 + attribute \src "libresoc.v:196797.5-196797.29" switch \initial - attribute \src "libresoc.v:202309.9-202309.17" + attribute \src "libresoc.v:196797.9-196797.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\sv_read$next[0:0]$14055 $2\sv_read$next[0:0]$14056 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$111 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sv_read$next[0:0]$14056 $3\sv_read$next[0:0]$14057 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" - switch \fetch_pc_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\sv_read$next[0:0]$14057 1'0 - case - assign $3\sv_read$next[0:0]$14057 \sv_read - end - case - assign $2\sv_read$next[0:0]$14056 \sv_read - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 assign { } { } - assign $1\sv_read$next[0:0]$14055 $4\sv_read$next[0:0]$14058 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" - switch \$113 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cur_cur_dststep$next[6:0]$13780 $2\cur_cur_dststep$next[6:0]$13786 + assign $1\cur_cur_maxvl$next[6:0]$13781 $2\cur_cur_maxvl$next[6:0]$13787 + assign $1\cur_cur_subvl$next[1:0]$13782 $2\cur_cur_subvl$next[1:0]$13788 + assign $1\cur_cur_svstep$next[1:0]$13783 $2\cur_cur_svstep$next[1:0]$13789 + assign $1\cur_cur_vl$next[6:0]$13784 $2\cur_cur_vl$next[6:0]$13790 + assign $1\dec2_cur_cur_srcstep$next[6:0]$13785 $2\dec2_cur_cur_srcstep$next[6:0]$13791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" + switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv_read$next[0:0]$14058 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\cur_cur_maxvl$next[6:0]$13787 $2\cur_cur_vl$next[6:0]$13790 $2\dec2_cur_cur_srcstep$next[6:0]$13791 $2\cur_cur_dststep$next[6:0]$13786 $2\cur_cur_subvl$next[1:0]$13788 $2\cur_cur_svstep$next[1:0]$13789 } \svstate [31:0] case - assign $4\sv_read$next[0:0]$14058 \sv_read + assign $2\cur_cur_dststep$next[6:0]$13786 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$13787 \cur_cur_maxvl + assign $2\cur_cur_subvl$next[1:0]$13788 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$13789 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$13790 \cur_cur_vl + assign $2\dec2_cur_cur_srcstep$next[6:0]$13791 \dec2_cur_cur_srcstep end case - assign $1\sv_read$next[0:0]$14055 \sv_read + assign $1\cur_cur_dststep$next[6:0]$13780 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$13781 \cur_cur_maxvl + assign $1\cur_cur_subvl$next[1:0]$13782 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$13783 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$13784 \cur_cur_vl + assign $1\dec2_cur_cur_srcstep$next[6:0]$13785 \dec2_cur_cur_srcstep end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" + switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv_read$next[0:0]$14059 1'1 - case - assign $5\sv_read$next[0:0]$14059 $1\sv_read$next[0:0]$14055 - end - sync always - update \sv_read$next $0\sv_read$next[0:0]$14054 - end - attribute \src "libresoc.v:202343.3-202409.6" - process $proc$libresoc.v:202343$14060 - assign { } { } - assign { } { } - assign { } { } - assign $0\fetch_fsm_state$next[1:0]$14061 $8\fetch_fsm_state$next[1:0]$14069 - attribute \src "libresoc.v:202344.5-202344.29" - switch \initial - attribute \src "libresoc.v:202344.9-202344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" - switch \fetch_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$14062 $2\fetch_fsm_state$next[1:0]$14063 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$119 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fetch_fsm_state$next[1:0]$14063 $3\fetch_fsm_state$next[1:0]$14064 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" - switch \fetch_pc_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fetch_fsm_state$next[1:0]$14064 2'01 - case - assign $3\fetch_fsm_state$next[1:0]$14064 \fetch_fsm_state - end - case - assign $2\fetch_fsm_state$next[1:0]$14063 \fetch_fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 2'01 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$14062 $4\fetch_fsm_state$next[1:0]$14065 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $4\fetch_fsm_state$next[1:0]$14065 \fetch_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\fetch_fsm_state$next[1:0]$14065 $5\fetch_fsm_state$next[1:0]$14066 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - switch \$121 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fetch_fsm_state$next[1:0]$14066 2'10 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $5\fetch_fsm_state$next[1:0]$14066 2'11 - end - end - attribute \src "libresoc.v:0.0-0.0" - case 2'11 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$14062 $6\fetch_fsm_state$next[1:0]$14067 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $6\fetch_fsm_state$next[1:0]$14067 \fetch_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $6\fetch_fsm_state$next[1:0]$14067 2'10 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'10 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$14062 $7\fetch_fsm_state$next[1:0]$14068 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" - switch \fetch_insn_ready_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\fetch_fsm_state$next[1:0]$14068 2'00 - case - assign $7\fetch_fsm_state$next[1:0]$14068 \fetch_fsm_state - end + assign { } { } + assign { $3\cur_cur_maxvl$next[6:0]$13793 $3\cur_cur_vl$next[6:0]$13796 $3\dec2_cur_cur_srcstep$next[6:0]$13797 $3\cur_cur_dststep$next[6:0]$13792 $3\cur_cur_subvl$next[1:0]$13794 $3\cur_cur_svstep$next[1:0]$13795 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } case - assign $1\fetch_fsm_state$next[1:0]$14062 \fetch_fsm_state + assign $3\cur_cur_dststep$next[6:0]$13792 $1\cur_cur_dststep$next[6:0]$13780 + assign $3\cur_cur_maxvl$next[6:0]$13793 $1\cur_cur_maxvl$next[6:0]$13781 + assign $3\cur_cur_subvl$next[1:0]$13794 $1\cur_cur_subvl$next[1:0]$13782 + assign $3\cur_cur_svstep$next[1:0]$13795 $1\cur_cur_svstep$next[1:0]$13783 + assign $3\cur_cur_vl$next[6:0]$13796 $1\cur_cur_vl$next[6:0]$13784 + assign $3\dec2_cur_cur_srcstep$next[6:0]$13797 $1\dec2_cur_cur_srcstep$next[6:0]$13785 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\fetch_fsm_state$next[1:0]$14069 2'00 - case - assign $8\fetch_fsm_state$next[1:0]$14069 $1\fetch_fsm_state$next[1:0]$14062 - end - sync always - update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$14061 - end - attribute \src "libresoc.v:202410.3-202428.6" - process $proc$libresoc.v:202410$14070 - assign { } { } - assign { } { } - assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:202411.5-202411.29" - switch \initial - attribute \src "libresoc.v:202411.9-202411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" - switch \fetch_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$127 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_stopped_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\core_stopped_i[0:0] 1'1 - end - case - assign $1\core_stopped_i[0:0] 1'0 - end - sync always - update \core_stopped_i $0\core_stopped_i[0:0] - end - attribute \src "libresoc.v:202429.3-202447.6" - process $proc$libresoc.v:202429$14071 - assign { } { } - assign { } { } - assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:202430.5-202430.29" - switch \initial - attribute \src "libresoc.v:202430.9-202430.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" - switch \fetch_fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 assign { } { } - assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" - switch \$133 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\dbg_core_stopped_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbg_core_stopped_i[0:0] 1'1 - end + assign { } { } + assign { } { } + assign { } { } + assign $4\cur_cur_svstep$next[1:0]$13801 2'00 + assign $4\cur_cur_subvl$next[1:0]$13800 2'00 + assign $4\cur_cur_dststep$next[6:0]$13798 7'0000000 + assign $4\dec2_cur_cur_srcstep$next[6:0]$13803 7'0000000 + assign $4\cur_cur_vl$next[6:0]$13802 7'0000000 + assign $4\cur_cur_maxvl$next[6:0]$13799 7'0000000 case - assign $1\dbg_core_stopped_i[0:0] 1'0 + assign $4\cur_cur_dststep$next[6:0]$13798 $3\cur_cur_dststep$next[6:0]$13792 + assign $4\cur_cur_maxvl$next[6:0]$13799 $3\cur_cur_maxvl$next[6:0]$13793 + assign $4\cur_cur_subvl$next[1:0]$13800 $3\cur_cur_subvl$next[1:0]$13794 + assign $4\cur_cur_svstep$next[1:0]$13801 $3\cur_cur_svstep$next[1:0]$13795 + assign $4\cur_cur_vl$next[6:0]$13802 $3\cur_cur_vl$next[6:0]$13796 + assign $4\dec2_cur_cur_srcstep$next[6:0]$13803 $3\dec2_cur_cur_srcstep$next[6:0]$13797 end sync always - update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13774 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13775 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13776 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13777 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13778 + update \dec2_cur_cur_srcstep$next $0\dec2_cur_cur_srcstep$next[6:0]$13779 end - attribute \src "libresoc.v:202448.3-202456.6" - process $proc$libresoc.v:202448$14072 + attribute \src "libresoc.v:196835.3-196843.6" + process $proc$libresoc.v:196835$13804 assign { } { } assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$14073 $1\jtag_dmi0__ack_o$next[0:0]$14074 - attribute \src "libresoc.v:202449.5-202449.29" + assign $0\jtag_dmi0__dout$next[63:0]$13805 $1\jtag_dmi0__dout$next[63:0]$13806 + attribute \src "libresoc.v:196836.5-196836.29" switch \initial - attribute \src "libresoc.v:202449.9-202449.17" + attribute \src "libresoc.v:196836.9-196836.17" case 1'1 case end @@ -420150,180 +411271,222 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$14074 1'0 + assign $1\jtag_dmi0__dout$next[63:0]$13806 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\jtag_dmi0__ack_o$next[0:0]$14074 \dbg_dmi_ack_o + assign $1\jtag_dmi0__dout$next[63:0]$13806 \dbg_dmi_dout end sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$14073 + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13805 end - attribute \src "libresoc.v:202457.3-202477.6" - process $proc$libresoc.v:202457$14075 + attribute \src "libresoc.v:196844.3-196873.6" + process $proc$libresoc.v:196844$13807 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_msr$next[63:0]$14076 $3\dec2_cur_msr$next[63:0]$14079 - attribute \src "libresoc.v:202458.5-202458.29" + assign $0\msr_read$next[0:0]$13808 $4\msr_read$next[0:0]$13812 + attribute \src "libresoc.v:196845.5-196845.29" switch \initial - attribute \src "libresoc.v:202458.9-202458.17" + attribute \src "libresoc.v:196845.9-196845.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$13809 $2\msr_read$next[0:0]$13810 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$13810 1'0 + case + assign $2\msr_read$next[0:0]$13810 \msr_read + end + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$14077 $2\dec2_cur_msr$next[63:0]$14078 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" - switch \$135 + assign $1\msr_read$next[0:0]$13809 $3\msr_read$next[0:0]$13811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" + switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_msr$next[63:0]$14078 \core_msr__data_o + assign $3\msr_read$next[0:0]$13811 1'1 case - assign $2\dec2_cur_msr$next[63:0]$14078 \dec2_cur_msr + assign $3\msr_read$next[0:0]$13811 \msr_read end case - assign $1\dec2_cur_msr$next[63:0]$14077 \dec2_cur_msr + assign $1\msr_read$next[0:0]$13809 \msr_read end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$14079 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\msr_read$next[0:0]$13812 1'1 case - assign $3\dec2_cur_msr$next[63:0]$14079 $1\dec2_cur_msr$next[63:0]$14077 + assign $4\msr_read$next[0:0]$13812 $1\msr_read$next[0:0]$13809 end sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$14076 + update \msr_read$next $0\msr_read$next[0:0]$13808 end - attribute \src "libresoc.v:202478.3-202510.6" - process $proc$libresoc.v:202478$14080 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:196874.3-196935.6" + process $proc$libresoc.v:196874$13813 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cur_cur_dststep$next[6:0]$14081 $3\cur_cur_dststep$next[6:0]$14099 - assign $0\cur_cur_maxvl$next[6:0]$14082 $3\cur_cur_maxvl$next[6:0]$14100 - assign $0\cur_cur_subvl$next[1:0]$14083 $3\cur_cur_subvl$next[1:0]$14101 - assign $0\cur_cur_svstep$next[1:0]$14084 $3\cur_cur_svstep$next[1:0]$14102 - assign $0\cur_cur_vl$next[6:0]$14085 $3\cur_cur_vl$next[6:0]$14103 - assign $0\dec2_cur_cur_srcstep$next[6:0]$14086 $3\dec2_cur_cur_srcstep$next[6:0]$14104 - attribute \src "libresoc.v:202479.5-202479.29" + assign $0\fetch_fsm_state$next[1:0]$13814 $7\fetch_fsm_state$next[1:0]$13821 + attribute \src "libresoc.v:196875.5-196875.29" switch \initial - attribute \src "libresoc.v:202479.9-202479.17" + attribute \src "libresoc.v:196875.9-196875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + case 2'00 assign { } { } - assign $1\cur_cur_dststep$next[6:0]$14087 $2\cur_cur_dststep$next[6:0]$14093 - assign $1\cur_cur_maxvl$next[6:0]$14088 $2\cur_cur_maxvl$next[6:0]$14094 - assign $1\cur_cur_subvl$next[1:0]$14089 $2\cur_cur_subvl$next[1:0]$14095 - assign $1\cur_cur_svstep$next[1:0]$14090 $2\cur_cur_svstep$next[1:0]$14096 - assign $1\cur_cur_vl$next[6:0]$14091 $2\cur_cur_vl$next[6:0]$14097 - assign $1\dec2_cur_cur_srcstep$next[6:0]$14092 $2\dec2_cur_cur_srcstep$next[6:0]$14098 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" - switch \$137 + assign $1\fetch_fsm_state$next[1:0]$13815 $2\fetch_fsm_state$next[1:0]$13816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" + switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $2\fetch_fsm_state$next[1:0]$13816 2'01 + case + assign $2\fetch_fsm_state$next[1:0]$13816 \fetch_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$13815 $3\fetch_fsm_state$next[1:0]$13817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\fetch_fsm_state$next[1:0]$13817 \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } + assign $3\fetch_fsm_state$next[1:0]$13817 $4\fetch_fsm_state$next[1:0]$13818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fetch_fsm_state$next[1:0]$13818 2'10 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fetch_fsm_state$next[1:0]$13818 2'11 + end + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$13815 $5\fetch_fsm_state$next[1:0]$13819 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $5\fetch_fsm_state$next[1:0]$13819 \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } + assign $5\fetch_fsm_state$next[1:0]$13819 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$13815 $6\fetch_fsm_state$next[1:0]$13820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" + switch \fetch_insn_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { $2\cur_cur_maxvl$next[6:0]$14094 $2\cur_cur_vl$next[6:0]$14097 $2\dec2_cur_cur_srcstep$next[6:0]$14098 $2\cur_cur_dststep$next[6:0]$14093 $2\cur_cur_subvl$next[1:0]$14095 $2\cur_cur_svstep$next[1:0]$14096 } \core_sv__data_o [31:0] + assign $6\fetch_fsm_state$next[1:0]$13820 2'00 case - assign $2\cur_cur_dststep$next[6:0]$14093 \cur_cur_dststep - assign $2\cur_cur_maxvl$next[6:0]$14094 \cur_cur_maxvl - assign $2\cur_cur_subvl$next[1:0]$14095 \cur_cur_subvl - assign $2\cur_cur_svstep$next[1:0]$14096 \cur_cur_svstep - assign $2\cur_cur_vl$next[6:0]$14097 \cur_cur_vl - assign $2\dec2_cur_cur_srcstep$next[6:0]$14098 \dec2_cur_cur_srcstep + assign $6\fetch_fsm_state$next[1:0]$13820 \fetch_fsm_state end case - assign $1\cur_cur_dststep$next[6:0]$14087 \cur_cur_dststep - assign $1\cur_cur_maxvl$next[6:0]$14088 \cur_cur_maxvl - assign $1\cur_cur_subvl$next[1:0]$14089 \cur_cur_subvl - assign $1\cur_cur_svstep$next[1:0]$14090 \cur_cur_svstep - assign $1\cur_cur_vl$next[6:0]$14091 \cur_cur_vl - assign $1\dec2_cur_cur_srcstep$next[6:0]$14092 \dec2_cur_cur_srcstep + assign $1\fetch_fsm_state$next[1:0]$13815 \fetch_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } + assign $7\fetch_fsm_state$next[1:0]$13821 2'00 + case + assign $7\fetch_fsm_state$next[1:0]$13821 $1\fetch_fsm_state$next[1:0]$13815 + end + sync always + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13814 + end + attribute \src "libresoc.v:196936.3-196956.6" + process $proc$libresoc.v:196936$13822 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_msr$next[63:0]$13823 $3\dec2_cur_msr$next[63:0]$13826 + attribute \src "libresoc.v:196937.5-196937.29" + switch \initial + attribute \src "libresoc.v:196937.9-196937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 assign { } { } + assign $1\dec2_cur_msr$next[63:0]$13824 $2\dec2_cur_msr$next[63:0]$13825 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$13825 \core_msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$13825 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$13824 \dec2_cur_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $3\cur_cur_svstep$next[1:0]$14102 2'00 - assign $3\cur_cur_subvl$next[1:0]$14101 2'00 - assign $3\cur_cur_dststep$next[6:0]$14099 7'0000000 - assign $3\dec2_cur_cur_srcstep$next[6:0]$14104 7'0000000 - assign $3\cur_cur_vl$next[6:0]$14103 7'0000000 - assign $3\cur_cur_maxvl$next[6:0]$14100 7'0000000 + assign $3\dec2_cur_msr$next[63:0]$13826 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\cur_cur_dststep$next[6:0]$14099 $1\cur_cur_dststep$next[6:0]$14087 - assign $3\cur_cur_maxvl$next[6:0]$14100 $1\cur_cur_maxvl$next[6:0]$14088 - assign $3\cur_cur_subvl$next[1:0]$14101 $1\cur_cur_subvl$next[1:0]$14089 - assign $3\cur_cur_svstep$next[1:0]$14102 $1\cur_cur_svstep$next[1:0]$14090 - assign $3\cur_cur_vl$next[6:0]$14103 $1\cur_cur_vl$next[6:0]$14091 - assign $3\dec2_cur_cur_srcstep$next[6:0]$14104 $1\dec2_cur_cur_srcstep$next[6:0]$14092 + assign $3\dec2_cur_msr$next[63:0]$13826 $1\dec2_cur_msr$next[63:0]$13824 end sync always - update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$14081 - update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$14082 - update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$14083 - update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$14084 - update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$14085 - update \dec2_cur_cur_srcstep$next $0\dec2_cur_cur_srcstep$next[6:0]$14086 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13823 end - attribute \src "libresoc.v:202511.3-202529.6" - process $proc$libresoc.v:202511$14105 + attribute \src "libresoc.v:196957.3-196975.6" + process $proc$libresoc.v:196957$13827 assign { } { } assign { } { } assign $0\svp64_raw_opcode_in[31:0] $1\svp64_raw_opcode_in[31:0] - attribute \src "libresoc.v:202512.5-202512.29" + attribute \src "libresoc.v:196958.5-196958.29" switch \initial - attribute \src "libresoc.v:202512.9-202512.17" + attribute \src "libresoc.v:196958.9-196958.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\svp64_raw_opcode_in[31:0] $2\svp64_raw_opcode_in[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -420331,7 +411494,7 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\svp64_raw_opcode_in[31:0] \$139 + assign $2\svp64_raw_opcode_in[31:0] \$75 end case assign $1\svp64_raw_opcode_in[31:0] 0 @@ -420339,24 +411502,24 @@ module \ti sync always update \svp64_raw_opcode_in $0\svp64_raw_opcode_in[31:0] end - attribute \src "libresoc.v:202530.3-202548.6" - process $proc$libresoc.v:202530$14106 + attribute \src "libresoc.v:196976.3-196994.6" + process $proc$libresoc.v:196976$13828 assign { } { } assign { } { } assign $0\svp64_bigendian[0:0] $1\svp64_bigendian[0:0] - attribute \src "libresoc.v:202531.5-202531.29" + attribute \src "libresoc.v:196977.5-196977.29" switch \initial - attribute \src "libresoc.v:202531.9-202531.17" + attribute \src "libresoc.v:196977.9-196977.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\svp64_bigendian[0:0] $2\svp64_bigendian[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -420372,8 +411535,8 @@ module \ti sync always update \svp64_bigendian $0\svp64_bigendian[0:0] end - attribute \src "libresoc.v:202549.3-202586.6" - process $proc$libresoc.v:202549$14107 + attribute \src "libresoc.v:196995.3-197032.6" + process $proc$libresoc.v:196995$13829 assign { } { } assign { } { } assign { } { } @@ -420395,20 +411558,20 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\dec2_dec_svp64__extra$next[8:0]$14108 $3\dec2_dec_svp64__extra$next[8:0]$14129 - assign $0\dec_svp64__elwidth$next[1:0]$14109 $3\dec_svp64__elwidth$next[1:0]$14130 - assign $0\dec_svp64__ewsrc$next[1:0]$14110 $3\dec_svp64__ewsrc$next[1:0]$14131 - assign $0\dec_svp64__mask$next[2:0]$14111 $3\dec_svp64__mask$next[2:0]$14132 - assign $0\dec_svp64__mmode$next[0:0]$14112 $3\dec_svp64__mmode$next[0:0]$14133 - assign $0\dec_svp64__mode$next[4:0]$14113 $3\dec_svp64__mode$next[4:0]$14134 - assign $0\dec_svp64__subvl$next[1:0]$14114 $3\dec_svp64__subvl$next[1:0]$14135 - attribute \src "libresoc.v:202550.5-202550.29" + assign $0\dec2_dec_svp64__extra$next[8:0]$13830 $3\dec2_dec_svp64__extra$next[8:0]$13851 + assign $0\dec_svp64__elwidth$next[1:0]$13831 $3\dec_svp64__elwidth$next[1:0]$13852 + assign $0\dec_svp64__ewsrc$next[1:0]$13832 $3\dec_svp64__ewsrc$next[1:0]$13853 + assign $0\dec_svp64__mask$next[2:0]$13833 $3\dec_svp64__mask$next[2:0]$13854 + assign $0\dec_svp64__mmode$next[0:0]$13834 $3\dec_svp64__mmode$next[0:0]$13855 + assign $0\dec_svp64__mode$next[4:0]$13835 $3\dec_svp64__mode$next[4:0]$13856 + assign $0\dec_svp64__subvl$next[1:0]$13836 $3\dec_svp64__subvl$next[1:0]$13857 + attribute \src "libresoc.v:196996.5-196996.29" switch \initial - attribute \src "libresoc.v:202550.9-202550.17" + attribute \src "libresoc.v:196996.9-196996.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 @@ -420419,24 +411582,24 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\dec2_dec_svp64__extra$next[8:0]$14115 $2\dec2_dec_svp64__extra$next[8:0]$14122 - assign $1\dec_svp64__elwidth$next[1:0]$14116 $2\dec_svp64__elwidth$next[1:0]$14123 - assign $1\dec_svp64__ewsrc$next[1:0]$14117 $2\dec_svp64__ewsrc$next[1:0]$14124 - assign $1\dec_svp64__mask$next[2:0]$14118 $2\dec_svp64__mask$next[2:0]$14125 - assign $1\dec_svp64__mmode$next[0:0]$14119 $2\dec_svp64__mmode$next[0:0]$14126 - assign $1\dec_svp64__mode$next[4:0]$14120 $2\dec_svp64__mode$next[4:0]$14127 - assign $1\dec_svp64__subvl$next[1:0]$14121 $2\dec_svp64__subvl$next[1:0]$14128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + assign $1\dec2_dec_svp64__extra$next[8:0]$13837 $2\dec2_dec_svp64__extra$next[8:0]$13844 + assign $1\dec_svp64__elwidth$next[1:0]$13838 $2\dec_svp64__elwidth$next[1:0]$13845 + assign $1\dec_svp64__ewsrc$next[1:0]$13839 $2\dec_svp64__ewsrc$next[1:0]$13846 + assign $1\dec_svp64__mask$next[2:0]$13840 $2\dec_svp64__mask$next[2:0]$13847 + assign $1\dec_svp64__mmode$next[0:0]$13841 $2\dec_svp64__mmode$next[0:0]$13848 + assign $1\dec_svp64__mode$next[4:0]$13842 $2\dec_svp64__mode$next[4:0]$13849 + assign $1\dec_svp64__subvl$next[1:0]$13843 $2\dec_svp64__subvl$next[1:0]$13850 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\dec2_dec_svp64__extra$next[8:0]$14122 \dec2_dec_svp64__extra - assign $2\dec_svp64__elwidth$next[1:0]$14123 \dec_svp64__elwidth - assign $2\dec_svp64__ewsrc$next[1:0]$14124 \dec_svp64__ewsrc - assign $2\dec_svp64__mask$next[2:0]$14125 \dec_svp64__mask - assign $2\dec_svp64__mmode$next[0:0]$14126 \dec_svp64__mmode - assign $2\dec_svp64__mode$next[4:0]$14127 \dec_svp64__mode - assign $2\dec_svp64__subvl$next[1:0]$14128 \dec_svp64__subvl + assign $2\dec2_dec_svp64__extra$next[8:0]$13844 \dec2_dec_svp64__extra + assign $2\dec_svp64__elwidth$next[1:0]$13845 \dec_svp64__elwidth + assign $2\dec_svp64__ewsrc$next[1:0]$13846 \dec_svp64__ewsrc + assign $2\dec_svp64__mask$next[2:0]$13847 \dec_svp64__mask + assign $2\dec_svp64__mmode$next[0:0]$13848 \dec_svp64__mmode + assign $2\dec_svp64__mode$next[4:0]$13849 \dec_svp64__mode + assign $2\dec_svp64__subvl$next[1:0]$13850 \dec_svp64__subvl attribute \src "libresoc.v:0.0-0.0" case assign { } { } @@ -420446,16 +411609,16 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\dec_svp64__mmode$next[0:0]$14126 $2\dec_svp64__mask$next[2:0]$14125 $2\dec_svp64__elwidth$next[1:0]$14123 $2\dec_svp64__ewsrc$next[1:0]$14124 $2\dec_svp64__subvl$next[1:0]$14128 $2\dec2_dec_svp64__extra$next[8:0]$14122 $2\dec_svp64__mode$next[4:0]$14127 } \svp64_svp64_rm + assign { $2\dec_svp64__mmode$next[0:0]$13848 $2\dec_svp64__mask$next[2:0]$13847 $2\dec_svp64__elwidth$next[1:0]$13845 $2\dec_svp64__ewsrc$next[1:0]$13846 $2\dec_svp64__subvl$next[1:0]$13850 $2\dec2_dec_svp64__extra$next[8:0]$13844 $2\dec_svp64__mode$next[4:0]$13849 } \svp64_svp64_rm end case - assign $1\dec2_dec_svp64__extra$next[8:0]$14115 \dec2_dec_svp64__extra - assign $1\dec_svp64__elwidth$next[1:0]$14116 \dec_svp64__elwidth - assign $1\dec_svp64__ewsrc$next[1:0]$14117 \dec_svp64__ewsrc - assign $1\dec_svp64__mask$next[2:0]$14118 \dec_svp64__mask - assign $1\dec_svp64__mmode$next[0:0]$14119 \dec_svp64__mmode - assign $1\dec_svp64__mode$next[4:0]$14120 \dec_svp64__mode - assign $1\dec_svp64__subvl$next[1:0]$14121 \dec_svp64__subvl + assign $1\dec2_dec_svp64__extra$next[8:0]$13837 \dec2_dec_svp64__extra + assign $1\dec_svp64__elwidth$next[1:0]$13838 \dec_svp64__elwidth + assign $1\dec_svp64__ewsrc$next[1:0]$13839 \dec_svp64__ewsrc + assign $1\dec_svp64__mask$next[2:0]$13840 \dec_svp64__mask + assign $1\dec_svp64__mmode$next[0:0]$13841 \dec_svp64__mmode + assign $1\dec_svp64__mode$next[4:0]$13842 \dec_svp64__mode + assign $1\dec_svp64__subvl$next[1:0]$13843 \dec_svp64__subvl end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -420468,155 +411631,132 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\dec_svp64__mode$next[4:0]$14134 5'00000 - assign $3\dec2_dec_svp64__extra$next[8:0]$14129 9'000000000 - assign $3\dec_svp64__subvl$next[1:0]$14135 2'00 - assign $3\dec_svp64__ewsrc$next[1:0]$14131 2'00 - assign $3\dec_svp64__elwidth$next[1:0]$14130 2'00 - assign $3\dec_svp64__mask$next[2:0]$14132 3'000 - assign $3\dec_svp64__mmode$next[0:0]$14133 1'0 - case - assign $3\dec2_dec_svp64__extra$next[8:0]$14129 $1\dec2_dec_svp64__extra$next[8:0]$14115 - assign $3\dec_svp64__elwidth$next[1:0]$14130 $1\dec_svp64__elwidth$next[1:0]$14116 - assign $3\dec_svp64__ewsrc$next[1:0]$14131 $1\dec_svp64__ewsrc$next[1:0]$14117 - assign $3\dec_svp64__mask$next[2:0]$14132 $1\dec_svp64__mask$next[2:0]$14118 - assign $3\dec_svp64__mmode$next[0:0]$14133 $1\dec_svp64__mmode$next[0:0]$14119 - assign $3\dec_svp64__mode$next[4:0]$14134 $1\dec_svp64__mode$next[4:0]$14120 - assign $3\dec_svp64__subvl$next[1:0]$14135 $1\dec_svp64__subvl$next[1:0]$14121 - end - sync always - update \dec2_dec_svp64__extra$next $0\dec2_dec_svp64__extra$next[8:0]$14108 - update \dec_svp64__elwidth$next $0\dec_svp64__elwidth$next[1:0]$14109 - update \dec_svp64__ewsrc$next $0\dec_svp64__ewsrc$next[1:0]$14110 - update \dec_svp64__mask$next $0\dec_svp64__mask$next[2:0]$14111 - update \dec_svp64__mmode$next $0\dec_svp64__mmode$next[0:0]$14112 - update \dec_svp64__mode$next $0\dec_svp64__mode$next[4:0]$14113 - update \dec_svp64__subvl$next $0\dec_svp64__subvl$next[1:0]$14114 - end - attribute \src "libresoc.v:202587.3-202595.6" - process $proc$libresoc.v:202587$14136 - assign { } { } - assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$14137 $1\jtag_dmi0__dout$next[63:0]$14138 - attribute \src "libresoc.v:202588.5-202588.29" - switch \initial - attribute \src "libresoc.v:202588.9-202588.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$14138 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec_svp64__mode$next[4:0]$13856 5'00000 + assign $3\dec2_dec_svp64__extra$next[8:0]$13851 9'000000000 + assign $3\dec_svp64__subvl$next[1:0]$13857 2'00 + assign $3\dec_svp64__ewsrc$next[1:0]$13853 2'00 + assign $3\dec_svp64__elwidth$next[1:0]$13852 2'00 + assign $3\dec_svp64__mask$next[2:0]$13854 3'000 + assign $3\dec_svp64__mmode$next[0:0]$13855 1'0 case - assign $1\jtag_dmi0__dout$next[63:0]$14138 \dbg_dmi_dout + assign $3\dec2_dec_svp64__extra$next[8:0]$13851 $1\dec2_dec_svp64__extra$next[8:0]$13837 + assign $3\dec_svp64__elwidth$next[1:0]$13852 $1\dec_svp64__elwidth$next[1:0]$13838 + assign $3\dec_svp64__ewsrc$next[1:0]$13853 $1\dec_svp64__ewsrc$next[1:0]$13839 + assign $3\dec_svp64__mask$next[2:0]$13854 $1\dec_svp64__mask$next[2:0]$13840 + assign $3\dec_svp64__mmode$next[0:0]$13855 $1\dec_svp64__mmode$next[0:0]$13841 + assign $3\dec_svp64__mode$next[4:0]$13856 $1\dec_svp64__mode$next[4:0]$13842 + assign $3\dec_svp64__subvl$next[1:0]$13857 $1\dec_svp64__subvl$next[1:0]$13843 end sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$14137 + update \dec2_dec_svp64__extra$next $0\dec2_dec_svp64__extra$next[8:0]$13830 + update \dec_svp64__elwidth$next $0\dec_svp64__elwidth$next[1:0]$13831 + update \dec_svp64__ewsrc$next $0\dec_svp64__ewsrc$next[1:0]$13832 + update \dec_svp64__mask$next $0\dec_svp64__mask$next[2:0]$13833 + update \dec_svp64__mmode$next $0\dec_svp64__mmode$next[0:0]$13834 + update \dec_svp64__mode$next $0\dec_svp64__mode$next[4:0]$13835 + update \dec_svp64__subvl$next $0\dec_svp64__subvl$next[1:0]$13836 end - attribute \src "libresoc.v:202596.3-202614.6" - process $proc$libresoc.v:202596$14139 + attribute \src "libresoc.v:197033.3-197051.6" + process $proc$libresoc.v:197033$13858 assign { } { } assign { } { } - assign $0\nia$next[63:0]$14140 $1\nia$next[63:0]$14141 - attribute \src "libresoc.v:202597.5-202597.29" + assign $0\nia$next[63:0]$13859 $1\nia$next[63:0]$13860 + attribute \src "libresoc.v:197034.5-197034.29" switch \initial - attribute \src "libresoc.v:202597.9-202597.17" + attribute \src "libresoc.v:197034.9-197034.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\nia$next[63:0]$14141 $2\nia$next[63:0]$14142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + assign $1\nia$next[63:0]$13860 $2\nia$next[63:0]$13861 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\nia$next[63:0]$14142 \nia + assign $2\nia$next[63:0]$13861 \nia attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\nia$next[63:0]$14142 \$143 [63:0] + assign $2\nia$next[63:0]$13861 \$79 [63:0] end case - assign $1\nia$next[63:0]$14141 \nia + assign $1\nia$next[63:0]$13860 \nia end sync always - update \nia$next $0\nia$next[63:0]$14140 + update \nia$next $0\nia$next[63:0]$13859 end - attribute \src "libresoc.v:202615.3-202650.6" - process $proc$libresoc.v:202615$14143 + attribute \src "libresoc.v:197052.3-197087.6" + process $proc$libresoc.v:197052$13862 assign { } { } assign { } { } - assign $0\fetch_insn_o$next[31:0]$14144 $1\fetch_insn_o$next[31:0]$14145 - attribute \src "libresoc.v:202616.5-202616.29" + assign $0\fetch_insn_o[31:0] $1\fetch_insn_o[31:0] + attribute \src "libresoc.v:197053.5-197053.29" switch \initial - attribute \src "libresoc.v:202616.9-202616.17" + attribute \src "libresoc.v:197053.9-197053.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fetch_insn_o$next[31:0]$14145 $2\fetch_insn_o$next[31:0]$14146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + assign $1\fetch_insn_o[31:0] $2\fetch_insn_o[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\fetch_insn_o$next[31:0]$14146 \fetch_insn_o + assign $2\fetch_insn_o[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\fetch_insn_o$next[31:0]$14146 $3\fetch_insn_o$next[31:0]$14147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" - switch \$148 + assign $2\fetch_insn_o[31:0] $3\fetch_insn_o[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fetch_insn_o$next[31:0]$14147 \$150 + assign $3\fetch_insn_o[31:0] \$86 case - assign $3\fetch_insn_o$next[31:0]$14147 \fetch_insn_o + assign $3\fetch_insn_o[31:0] 0 end end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fetch_insn_o$next[31:0]$14145 $4\fetch_insn_o$next[31:0]$14148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" + assign $1\fetch_insn_o[31:0] $4\fetch_insn_o[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\fetch_insn_o$next[31:0]$14148 \fetch_insn_o + assign $4\fetch_insn_o[31:0] 0 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\fetch_insn_o$next[31:0]$14148 \$154 + assign $4\fetch_insn_o[31:0] \$90 end case - assign $1\fetch_insn_o$next[31:0]$14145 \fetch_insn_o + assign $1\fetch_insn_o[31:0] 0 end sync always - update \fetch_insn_o$next $0\fetch_insn_o$next[31:0]$14144 + update \fetch_insn_o $0\fetch_insn_o[31:0] end - attribute \src "libresoc.v:202651.3-202661.6" - process $proc$libresoc.v:202651$14149 + attribute \src "libresoc.v:197088.3-197098.6" + process $proc$libresoc.v:197088$13863 assign { } { } assign { } { } assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:202652.5-202652.29" + attribute \src "libresoc.v:197089.5-197089.29" switch \initial - attribute \src "libresoc.v:202652.9-202652.17" + attribute \src "libresoc.v:197089.9-197089.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'10 @@ -420628,158 +411768,261 @@ module \ti sync always update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] end - attribute \src "libresoc.v:202662.3-202672.6" - process $proc$libresoc.v:202662$14150 + attribute \src "libresoc.v:197099.3-197160.6" + process $proc$libresoc.v:197099$13864 assign { } { } assign { } { } - assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:202663.5-202663.29" + assign { } { } + assign $0\issue_fsm_state$next[2:0]$13865 $8\issue_fsm_state$next[2:0]$13873 + attribute \src "libresoc.v:197100.5-197100.29" switch \initial - attribute \src "libresoc.v:202663.9-202663.17" + attribute \src "libresoc.v:197100.9-197100.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 3'000 assign { } { } - assign $1\fetch_pc_valid_i[0:0] 1'1 - case - assign $1\fetch_pc_valid_i[0:0] 1'0 - end - sync always - update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] - end - attribute \src "libresoc.v:202673.3-202715.6" - process $proc$libresoc.v:202673$14151 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$next[1:0]$14152 $5\fsm_state$next[1:0]$14157 - attribute \src "libresoc.v:202674.5-202674.29" - switch \initial - attribute \src "libresoc.v:202674.9-202674.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + assign $1\issue_fsm_state$next[2:0]$13866 $2\issue_fsm_state$next[2:0]$13867 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\issue_fsm_state$next[2:0]$13867 3'001 + case + assign $2\issue_fsm_state$next[2:0]$13867 \issue_fsm_state + end attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 3'001 assign { } { } - assign $1\fsm_state$next[1:0]$14153 $2\fsm_state$next[1:0]$14154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:382" + assign $1\issue_fsm_state$next[2:0]$13866 $3\issue_fsm_state$next[2:0]$13868 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:289" switch \fetch_pc_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$14154 2'01 + assign $3\issue_fsm_state$next[2:0]$13868 3'010 case - assign $2\fsm_state$next[1:0]$14154 \fsm_state + assign $3\issue_fsm_state$next[2:0]$13868 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'010 assign { } { } - assign $1\fsm_state$next[1:0]$14153 $3\fsm_state$next[1:0]$14155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + assign $1\issue_fsm_state$next[2:0]$13866 $4\issue_fsm_state$next[2:0]$13869 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[1:0]$14155 2'10 + assign $4\issue_fsm_state$next[2:0]$13869 3'011 case - assign $3\fsm_state$next[1:0]$14155 \fsm_state + assign $4\issue_fsm_state$next[2:0]$13869 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 3'011 assign { } { } - assign $1\fsm_state$next[1:0]$14153 2'11 + assign $1\issue_fsm_state$next[2:0]$13866 $5\issue_fsm_state$next[2:0]$13870 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" + switch \exec_insn_ready_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\issue_fsm_state$next[2:0]$13870 3'100 + case + assign $5\issue_fsm_state$next[2:0]$13870 \issue_fsm_state + end attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 3'100 assign { } { } - assign $1\fsm_state$next[1:0]$14153 $4\fsm_state$next[1:0]$14156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - switch \$161 + assign $1\issue_fsm_state$next[2:0]$13866 $6\issue_fsm_state$next[2:0]$13871 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + switch \$107 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[1:0]$14156 2'00 + assign $6\issue_fsm_state$next[2:0]$13871 $7\issue_fsm_state$next[2:0]$13872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \exec_pc_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\issue_fsm_state$next[2:0]$13872 3'001 + case + assign $7\issue_fsm_state$next[2:0]$13872 \issue_fsm_state + end case - assign $4\fsm_state$next[1:0]$14156 \fsm_state + assign $6\issue_fsm_state$next[2:0]$13871 \issue_fsm_state end case - assign $1\fsm_state$next[1:0]$14153 \fsm_state + assign $1\issue_fsm_state$next[2:0]$13866 \issue_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$14157 2'00 + assign $8\issue_fsm_state$next[2:0]$13873 3'000 case - assign $5\fsm_state$next[1:0]$14157 $1\fsm_state$next[1:0]$14153 + assign $8\issue_fsm_state$next[2:0]$13873 $1\issue_fsm_state$next[2:0]$13866 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$14152 + update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13865 end - attribute \src "libresoc.v:202716.3-202726.6" - process $proc$libresoc.v:202716$14158 + attribute \src "libresoc.v:197161.3-197191.6" + process $proc$libresoc.v:197161$13874 assign { } { } assign { } { } - assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:202717.5-202717.29" + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "libresoc.v:197162.5-197162.29" switch \initial - attribute \src "libresoc.v:202717.9-202717.17" + attribute \src "libresoc.v:197162.9-197162.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'000 assign { } { } - assign $1\fetch_insn_ready_i[0:0] 1'1 + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_stopped_i[0:0] 1'1 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\core_stopped_i[0:0] 1'1 + end case - assign $1\fetch_insn_ready_i[0:0] 1'0 + assign $1\core_stopped_i[0:0] 1'0 end sync always - update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] + update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:202727.3-202742.6" - process $proc$libresoc.v:202727$14159 + attribute \src "libresoc.v:197192.3-197222.6" + process $proc$libresoc.v:197192$13875 assign { } { } assign { } { } - assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:202728.5-202728.29" + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:197193.5-197193.29" switch \initial - attribute \src "libresoc.v:202728.9-202728.17" + attribute \src "libresoc.v:197193.9-197193.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'000 assign { } { } - assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" - switch \fetch_insn_valid_o + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" + switch \$125 attribute \src "libresoc.v:0.0-0.0" case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case assign { } { } - assign $2\dec2_raw_opcode_in[31:0] \fetch_insn_o + assign $2\dbg_core_stopped_i[0:0] 1'1 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:313" + switch \$131 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case - assign $2\dec2_raw_opcode_in[31:0] 0 + assign { } { } + assign $3\dbg_core_stopped_i[0:0] 1'1 end case - assign $1\dec2_raw_opcode_in[31:0] 0 + assign $1\dbg_core_stopped_i[0:0] 1'0 end sync always - update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "libresoc.v:202743.3-202858.6" - process $proc$libresoc.v:202743$14160 + attribute \src "libresoc.v:197223.3-197233.6" + process $proc$libresoc.v:197223$13876 + assign { } { } + assign { } { } + assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:197224.5-197224.29" + switch \initial + attribute \src "libresoc.v:197224.9-197224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fetch_pc_valid_i[0:0] 1'1 + case + assign $1\fetch_pc_valid_i[0:0] 1'0 + end + sync always + update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] + end + attribute \src "libresoc.v:197234.3-197244.6" + process $proc$libresoc.v:197234$13877 + assign { } { } + assign { } { } + assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] + attribute \src "libresoc.v:197235.5-197235.29" + switch \initial + attribute \src "libresoc.v:197235.9-197235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fetch_insn_ready_i[0:0] 1'1 + case + assign $1\fetch_insn_ready_i[0:0] 1'0 + end + sync always + update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] + end + attribute \src "libresoc.v:197245.3-197363.6" + process $proc$libresoc.v:197245$13878 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -420898,11 +412141,7 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_asmcode$next[7:0]$14161 $1\core_asmcode$next[7:0]$14220 - assign $0\core_core_core_cia$next[63:0]$14162 $1\core_core_core_cia$next[63:0]$14221 - assign $0\core_core_core_cr_rd$next[7:0]$14163 $1\core_core_core_cr_rd$next[7:0]$14222 assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$14165 $1\core_core_core_cr_wr$next[7:0]$14224 assign { } { } assign { } { } assign { } { } @@ -420911,89 +412150,142 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_core_fn_unit$next[12:0]$14174 $1\core_core_core_fn_unit$next[12:0]$14233 - assign $0\core_core_core_input_carry$next[1:0]$14175 $1\core_core_core_input_carry$next[1:0]$14234 - assign $0\core_core_core_insn$next[31:0]$14176 $1\core_core_core_insn$next[31:0]$14235 - assign $0\core_core_core_insn_type$next[6:0]$14177 $1\core_core_core_insn_type$next[6:0]$14236 - assign $0\core_core_core_is_32bit$next[0:0]$14178 $1\core_core_core_is_32bit$next[0:0]$14237 - assign $0\core_core_core_msr$next[63:0]$14179 $1\core_core_core_msr$next[63:0]$14238 - assign $0\core_core_core_oe$next[0:0]$14180 $1\core_core_core_oe$next[0:0]$14239 assign { } { } - assign $0\core_core_core_rc$next[0:0]$14182 $1\core_core_core_rc$next[0:0]$14241 assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$14184 $1\core_core_core_trapaddr$next[12:0]$14243 - assign $0\core_core_core_traptype$next[7:0]$14185 $1\core_core_core_traptype$next[7:0]$14244 - assign $0\core_core_cr_in1$next[6:0]$14186 $1\core_core_cr_in1$next[6:0]$14245 assign { } { } - assign $0\core_core_cr_in2$1$next[6:0]$14188 $1\core_core_cr_in2$1$next[6:0]$14247 - assign $0\core_core_cr_in2$next[6:0]$14189 $1\core_core_cr_in2$next[6:0]$14248 assign { } { } assign { } { } - assign $0\core_core_cr_out$next[6:0]$14192 $1\core_core_cr_out$next[6:0]$14251 assign { } { } - assign $0\core_core_ea$next[6:0]$14194 $1\core_core_ea$next[6:0]$14253 - assign $0\core_core_fast1$next[2:0]$14195 $1\core_core_fast1$next[2:0]$14254 assign { } { } - assign $0\core_core_fast2$next[2:0]$14197 $1\core_core_fast2$next[2:0]$14256 assign { } { } - assign $0\core_core_fasto1$next[2:0]$14199 $1\core_core_fasto1$next[2:0]$14258 - assign $0\core_core_fasto2$next[2:0]$14200 $1\core_core_fasto2$next[2:0]$14259 - assign $0\core_core_lk$next[0:0]$14201 $1\core_core_lk$next[0:0]$14260 - assign $0\core_core_reg1$next[6:0]$14202 $1\core_core_reg1$next[6:0]$14261 assign { } { } - assign $0\core_core_reg2$next[6:0]$14204 $1\core_core_reg2$next[6:0]$14263 assign { } { } - assign $0\core_core_reg3$next[6:0]$14206 $1\core_core_reg3$next[6:0]$14265 assign { } { } - assign $0\core_core_rego$next[6:0]$14208 $1\core_core_rego$next[6:0]$14267 - assign $0\core_core_spr1$next[9:0]$14209 $1\core_core_spr1$next[9:0]$14268 assign { } { } - assign $0\core_core_spro$next[9:0]$14211 $1\core_core_spro$next[9:0]$14270 - assign $0\core_core_xer_in$next[2:0]$14212 $1\core_core_xer_in$next[2:0]$14271 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\core_xer_out$next[0:0]$14219 $1\core_xer_out$next[0:0]$14278 - assign $0\core_core_core_cr_rd_ok$next[0:0]$14164 $4\core_core_core_cr_rd_ok$next[0:0]$14397 - assign $0\core_core_core_exc_$signal$3$next[0:0]$14166 $4\core_core_core_exc_$signal$3$next[0:0]$14398 - assign $0\core_core_core_exc_$signal$4$next[0:0]$14167 $4\core_core_core_exc_$signal$4$next[0:0]$14399 - assign $0\core_core_core_exc_$signal$5$next[0:0]$14168 $4\core_core_core_exc_$signal$5$next[0:0]$14400 - assign $0\core_core_core_exc_$signal$6$next[0:0]$14169 $4\core_core_core_exc_$signal$6$next[0:0]$14401 - assign $0\core_core_core_exc_$signal$7$next[0:0]$14170 $4\core_core_core_exc_$signal$7$next[0:0]$14402 - assign $0\core_core_core_exc_$signal$8$next[0:0]$14171 $4\core_core_core_exc_$signal$8$next[0:0]$14403 - assign $0\core_core_core_exc_$signal$9$next[0:0]$14172 $4\core_core_core_exc_$signal$9$next[0:0]$14404 - assign $0\core_core_core_exc_$signal$next[0:0]$14173 $4\core_core_core_exc_$signal$next[0:0]$14405 - assign $0\core_core_core_oe_ok$next[0:0]$14181 $4\core_core_core_oe_ok$next[0:0]$14406 - assign $0\core_core_core_rc_ok$next[0:0]$14183 $4\core_core_core_rc_ok$next[0:0]$14407 - assign $0\core_core_cr_in1_ok$next[0:0]$14187 $4\core_core_cr_in1_ok$next[0:0]$14408 - assign $0\core_core_cr_in2_ok$2$next[0:0]$14190 $4\core_core_cr_in2_ok$2$next[0:0]$14409 - assign $0\core_core_cr_in2_ok$next[0:0]$14191 $4\core_core_cr_in2_ok$next[0:0]$14410 - assign $0\core_core_cr_wr_ok$next[0:0]$14193 $4\core_core_cr_wr_ok$next[0:0]$14411 - assign $0\core_core_fast1_ok$next[0:0]$14196 $4\core_core_fast1_ok$next[0:0]$14412 - assign $0\core_core_fast2_ok$next[0:0]$14198 $4\core_core_fast2_ok$next[0:0]$14413 - assign $0\core_core_reg1_ok$next[0:0]$14203 $4\core_core_reg1_ok$next[0:0]$14414 - assign $0\core_core_reg2_ok$next[0:0]$14205 $4\core_core_reg2_ok$next[0:0]$14415 - assign $0\core_core_reg3_ok$next[0:0]$14207 $4\core_core_reg3_ok$next[0:0]$14416 - assign $0\core_core_spr1_ok$next[0:0]$14210 $4\core_core_spr1_ok$next[0:0]$14417 - assign $0\core_cr_out_ok$next[0:0]$14213 $4\core_cr_out_ok$next[0:0]$14418 - assign $0\core_ea_ok$next[0:0]$14214 $4\core_ea_ok$next[0:0]$14419 - assign $0\core_fasto1_ok$next[0:0]$14215 $4\core_fasto1_ok$next[0:0]$14420 - assign $0\core_fasto2_ok$next[0:0]$14216 $4\core_fasto2_ok$next[0:0]$14421 - assign $0\core_rego_ok$next[0:0]$14217 $4\core_rego_ok$next[0:0]$14422 - assign $0\core_spro_ok$next[0:0]$14218 $4\core_spro_ok$next[0:0]$14423 - attribute \src "libresoc.v:202744.5-202744.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_asmcode$next[7:0]$13879 $3\core_asmcode$next[7:0]$14056 + assign $0\core_core_core_cia$next[63:0]$13880 $3\core_core_core_cia$next[63:0]$14057 + assign $0\core_core_core_cr_rd$next[7:0]$13881 $3\core_core_core_cr_rd$next[7:0]$14058 + assign { } { } + assign $0\core_core_core_cr_wr$next[7:0]$13883 $3\core_core_core_cr_wr$next[7:0]$14060 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_core_fn_unit$next[12:0]$13892 $3\core_core_core_fn_unit$next[12:0]$14069 + assign $0\core_core_core_input_carry$next[1:0]$13893 $3\core_core_core_input_carry$next[1:0]$14070 + assign $0\core_core_core_insn$next[31:0]$13894 $3\core_core_core_insn$next[31:0]$14071 + assign $0\core_core_core_insn_type$next[6:0]$13895 $3\core_core_core_insn_type$next[6:0]$14072 + assign $0\core_core_core_is_32bit$next[0:0]$13896 $3\core_core_core_is_32bit$next[0:0]$14073 + assign $0\core_core_core_msr$next[63:0]$13897 $3\core_core_core_msr$next[63:0]$14074 + assign $0\core_core_core_oe$next[0:0]$13898 $3\core_core_core_oe$next[0:0]$14075 + assign { } { } + assign $0\core_core_core_rc$next[0:0]$13900 $3\core_core_core_rc$next[0:0]$14077 + assign { } { } + assign $0\core_core_core_trapaddr$next[12:0]$13902 $3\core_core_core_trapaddr$next[12:0]$14079 + assign $0\core_core_core_traptype$next[7:0]$13903 $3\core_core_core_traptype$next[7:0]$14080 + assign $0\core_core_cr_in1$next[6:0]$13904 $3\core_core_cr_in1$next[6:0]$14081 + assign { } { } + assign $0\core_core_cr_in2$1$next[6:0]$13906 $3\core_core_cr_in2$1$next[6:0]$14083 + assign $0\core_core_cr_in2$next[6:0]$13907 $3\core_core_cr_in2$next[6:0]$14084 + assign { } { } + assign { } { } + assign $0\core_core_cr_out$next[6:0]$13910 $3\core_core_cr_out$next[6:0]$14087 + assign { } { } + assign $0\core_core_ea$next[6:0]$13912 $3\core_core_ea$next[6:0]$14089 + assign $0\core_core_fast1$next[2:0]$13913 $3\core_core_fast1$next[2:0]$14090 + assign { } { } + assign $0\core_core_fast2$next[2:0]$13915 $3\core_core_fast2$next[2:0]$14092 + assign { } { } + assign $0\core_core_fasto1$next[2:0]$13917 $3\core_core_fasto1$next[2:0]$14094 + assign $0\core_core_fasto2$next[2:0]$13918 $3\core_core_fasto2$next[2:0]$14095 + assign $0\core_core_lk$next[0:0]$13919 $3\core_core_lk$next[0:0]$14096 + assign $0\core_core_reg1$next[6:0]$13920 $3\core_core_reg1$next[6:0]$14097 + assign { } { } + assign $0\core_core_reg2$next[6:0]$13922 $3\core_core_reg2$next[6:0]$14099 + assign { } { } + assign $0\core_core_reg3$next[6:0]$13924 $3\core_core_reg3$next[6:0]$14101 + assign { } { } + assign $0\core_core_rego$next[6:0]$13926 $3\core_core_rego$next[6:0]$14103 + assign $0\core_core_spr1$next[9:0]$13927 $3\core_core_spr1$next[9:0]$14104 + assign { } { } + assign $0\core_core_spro$next[9:0]$13929 $3\core_core_spro$next[9:0]$14106 + assign $0\core_core_xer_in$next[2:0]$13930 $3\core_core_xer_in$next[2:0]$14107 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_xer_out$next[0:0]$13937 $3\core_xer_out$next[0:0]$14114 + assign $0\core_core_core_cr_rd_ok$next[0:0]$13882 $5\core_core_core_cr_rd_ok$next[0:0]$14174 + assign $0\core_core_core_exc_$signal$3$next[0:0]$13884 $5\core_core_core_exc_$signal$3$next[0:0]$14175 + assign $0\core_core_core_exc_$signal$4$next[0:0]$13885 $5\core_core_core_exc_$signal$4$next[0:0]$14176 + assign $0\core_core_core_exc_$signal$5$next[0:0]$13886 $5\core_core_core_exc_$signal$5$next[0:0]$14177 + assign $0\core_core_core_exc_$signal$6$next[0:0]$13887 $5\core_core_core_exc_$signal$6$next[0:0]$14178 + assign $0\core_core_core_exc_$signal$7$next[0:0]$13888 $5\core_core_core_exc_$signal$7$next[0:0]$14179 + assign $0\core_core_core_exc_$signal$8$next[0:0]$13889 $5\core_core_core_exc_$signal$8$next[0:0]$14180 + assign $0\core_core_core_exc_$signal$9$next[0:0]$13890 $5\core_core_core_exc_$signal$9$next[0:0]$14181 + assign $0\core_core_core_exc_$signal$next[0:0]$13891 $5\core_core_core_exc_$signal$next[0:0]$14182 + assign $0\core_core_core_oe_ok$next[0:0]$13899 $5\core_core_core_oe_ok$next[0:0]$14183 + assign $0\core_core_core_rc_ok$next[0:0]$13901 $5\core_core_core_rc_ok$next[0:0]$14184 + assign $0\core_core_cr_in1_ok$next[0:0]$13905 $5\core_core_cr_in1_ok$next[0:0]$14185 + assign $0\core_core_cr_in2_ok$2$next[0:0]$13908 $5\core_core_cr_in2_ok$2$next[0:0]$14186 + assign $0\core_core_cr_in2_ok$next[0:0]$13909 $5\core_core_cr_in2_ok$next[0:0]$14187 + assign $0\core_core_cr_wr_ok$next[0:0]$13911 $5\core_core_cr_wr_ok$next[0:0]$14188 + assign $0\core_core_fast1_ok$next[0:0]$13914 $5\core_core_fast1_ok$next[0:0]$14189 + assign $0\core_core_fast2_ok$next[0:0]$13916 $5\core_core_fast2_ok$next[0:0]$14190 + assign $0\core_core_reg1_ok$next[0:0]$13921 $5\core_core_reg1_ok$next[0:0]$14191 + assign $0\core_core_reg2_ok$next[0:0]$13923 $5\core_core_reg2_ok$next[0:0]$14192 + assign $0\core_core_reg3_ok$next[0:0]$13925 $5\core_core_reg3_ok$next[0:0]$14193 + assign $0\core_core_spr1_ok$next[0:0]$13928 $5\core_core_spr1_ok$next[0:0]$14194 + assign $0\core_cr_out_ok$next[0:0]$13931 $5\core_cr_out_ok$next[0:0]$14195 + assign $0\core_ea_ok$next[0:0]$13932 $5\core_ea_ok$next[0:0]$14196 + assign $0\core_fasto1_ok$next[0:0]$13933 $5\core_fasto1_ok$next[0:0]$14197 + assign $0\core_fasto2_ok$next[0:0]$13934 $5\core_fasto2_ok$next[0:0]$14198 + assign $0\core_rego_ok$next[0:0]$13935 $5\core_rego_ok$next[0:0]$14199 + assign $0\core_spro_ok$next[0:0]$13936 $5\core_spro_ok$next[0:0]$14200 + attribute \src "libresoc.v:197246.5-197246.29" switch \initial - attribute \src "libresoc.v:202744.9-202744.17" + attribute \src "libresoc.v:197246.9-197246.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:273" + switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 3'010 assign { } { } assign { } { } assign { } { } @@ -421053,66 +412345,66 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$14220 $2\core_asmcode$next[7:0]$14279 - assign $1\core_core_core_cia$next[63:0]$14221 $2\core_core_core_cia$next[63:0]$14280 - assign $1\core_core_core_cr_rd$next[7:0]$14222 $2\core_core_core_cr_rd$next[7:0]$14281 - assign $1\core_core_core_cr_rd_ok$next[0:0]$14223 $2\core_core_core_cr_rd_ok$next[0:0]$14282 - assign $1\core_core_core_cr_wr$next[7:0]$14224 $2\core_core_core_cr_wr$next[7:0]$14283 - assign $1\core_core_core_exc_$signal$3$next[0:0]$14225 $2\core_core_core_exc_$signal$3$next[0:0]$14284 - assign $1\core_core_core_exc_$signal$4$next[0:0]$14226 $2\core_core_core_exc_$signal$4$next[0:0]$14285 - assign $1\core_core_core_exc_$signal$5$next[0:0]$14227 $2\core_core_core_exc_$signal$5$next[0:0]$14286 - assign $1\core_core_core_exc_$signal$6$next[0:0]$14228 $2\core_core_core_exc_$signal$6$next[0:0]$14287 - assign $1\core_core_core_exc_$signal$7$next[0:0]$14229 $2\core_core_core_exc_$signal$7$next[0:0]$14288 - assign $1\core_core_core_exc_$signal$8$next[0:0]$14230 $2\core_core_core_exc_$signal$8$next[0:0]$14289 - assign $1\core_core_core_exc_$signal$9$next[0:0]$14231 $2\core_core_core_exc_$signal$9$next[0:0]$14290 - assign $1\core_core_core_exc_$signal$next[0:0]$14232 $2\core_core_core_exc_$signal$next[0:0]$14291 - assign $1\core_core_core_fn_unit$next[12:0]$14233 $2\core_core_core_fn_unit$next[12:0]$14292 - assign $1\core_core_core_input_carry$next[1:0]$14234 $2\core_core_core_input_carry$next[1:0]$14293 - assign $1\core_core_core_insn$next[31:0]$14235 $2\core_core_core_insn$next[31:0]$14294 - assign $1\core_core_core_insn_type$next[6:0]$14236 $2\core_core_core_insn_type$next[6:0]$14295 - assign $1\core_core_core_is_32bit$next[0:0]$14237 $2\core_core_core_is_32bit$next[0:0]$14296 - assign $1\core_core_core_msr$next[63:0]$14238 $2\core_core_core_msr$next[63:0]$14297 - assign $1\core_core_core_oe$next[0:0]$14239 $2\core_core_core_oe$next[0:0]$14298 - assign $1\core_core_core_oe_ok$next[0:0]$14240 $2\core_core_core_oe_ok$next[0:0]$14299 - assign $1\core_core_core_rc$next[0:0]$14241 $2\core_core_core_rc$next[0:0]$14300 - assign $1\core_core_core_rc_ok$next[0:0]$14242 $2\core_core_core_rc_ok$next[0:0]$14301 - assign $1\core_core_core_trapaddr$next[12:0]$14243 $2\core_core_core_trapaddr$next[12:0]$14302 - assign $1\core_core_core_traptype$next[7:0]$14244 $2\core_core_core_traptype$next[7:0]$14303 - assign $1\core_core_cr_in1$next[6:0]$14245 $2\core_core_cr_in1$next[6:0]$14304 - assign $1\core_core_cr_in1_ok$next[0:0]$14246 $2\core_core_cr_in1_ok$next[0:0]$14305 - assign $1\core_core_cr_in2$1$next[6:0]$14247 $2\core_core_cr_in2$1$next[6:0]$14306 - assign $1\core_core_cr_in2$next[6:0]$14248 $2\core_core_cr_in2$next[6:0]$14307 - assign $1\core_core_cr_in2_ok$2$next[0:0]$14249 $2\core_core_cr_in2_ok$2$next[0:0]$14308 - assign $1\core_core_cr_in2_ok$next[0:0]$14250 $2\core_core_cr_in2_ok$next[0:0]$14309 - assign $1\core_core_cr_out$next[6:0]$14251 $2\core_core_cr_out$next[6:0]$14310 - assign $1\core_core_cr_wr_ok$next[0:0]$14252 $2\core_core_cr_wr_ok$next[0:0]$14311 - assign $1\core_core_ea$next[6:0]$14253 $2\core_core_ea$next[6:0]$14312 - assign $1\core_core_fast1$next[2:0]$14254 $2\core_core_fast1$next[2:0]$14313 - assign $1\core_core_fast1_ok$next[0:0]$14255 $2\core_core_fast1_ok$next[0:0]$14314 - assign $1\core_core_fast2$next[2:0]$14256 $2\core_core_fast2$next[2:0]$14315 - assign $1\core_core_fast2_ok$next[0:0]$14257 $2\core_core_fast2_ok$next[0:0]$14316 - assign $1\core_core_fasto1$next[2:0]$14258 $2\core_core_fasto1$next[2:0]$14317 - assign $1\core_core_fasto2$next[2:0]$14259 $2\core_core_fasto2$next[2:0]$14318 - assign $1\core_core_lk$next[0:0]$14260 $2\core_core_lk$next[0:0]$14319 - assign $1\core_core_reg1$next[6:0]$14261 $2\core_core_reg1$next[6:0]$14320 - assign $1\core_core_reg1_ok$next[0:0]$14262 $2\core_core_reg1_ok$next[0:0]$14321 - assign $1\core_core_reg2$next[6:0]$14263 $2\core_core_reg2$next[6:0]$14322 - assign $1\core_core_reg2_ok$next[0:0]$14264 $2\core_core_reg2_ok$next[0:0]$14323 - assign $1\core_core_reg3$next[6:0]$14265 $2\core_core_reg3$next[6:0]$14324 - assign $1\core_core_reg3_ok$next[0:0]$14266 $2\core_core_reg3_ok$next[0:0]$14325 - assign $1\core_core_rego$next[6:0]$14267 $2\core_core_rego$next[6:0]$14326 - assign $1\core_core_spr1$next[9:0]$14268 $2\core_core_spr1$next[9:0]$14327 - assign $1\core_core_spr1_ok$next[0:0]$14269 $2\core_core_spr1_ok$next[0:0]$14328 - assign $1\core_core_spro$next[9:0]$14270 $2\core_core_spro$next[9:0]$14329 - assign $1\core_core_xer_in$next[2:0]$14271 $2\core_core_xer_in$next[2:0]$14330 - assign $1\core_cr_out_ok$next[0:0]$14272 $2\core_cr_out_ok$next[0:0]$14331 - assign $1\core_ea_ok$next[0:0]$14273 $2\core_ea_ok$next[0:0]$14332 - assign $1\core_fasto1_ok$next[0:0]$14274 $2\core_fasto1_ok$next[0:0]$14333 - assign $1\core_fasto2_ok$next[0:0]$14275 $2\core_fasto2_ok$next[0:0]$14334 - assign $1\core_rego_ok$next[0:0]$14276 $2\core_rego_ok$next[0:0]$14335 - assign $1\core_spro_ok$next[0:0]$14277 $2\core_spro_ok$next[0:0]$14336 - assign $1\core_xer_out$next[0:0]$14278 $2\core_xer_out$next[0:0]$14337 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + assign $1\core_asmcode$next[7:0]$13938 $2\core_asmcode$next[7:0]$13997 + assign $1\core_core_core_cia$next[63:0]$13939 $2\core_core_core_cia$next[63:0]$13998 + assign $1\core_core_core_cr_rd$next[7:0]$13940 $2\core_core_core_cr_rd$next[7:0]$13999 + assign $1\core_core_core_cr_rd_ok$next[0:0]$13941 $2\core_core_core_cr_rd_ok$next[0:0]$14000 + assign $1\core_core_core_cr_wr$next[7:0]$13942 $2\core_core_core_cr_wr$next[7:0]$14001 + assign $1\core_core_core_exc_$signal$3$next[0:0]$13943 $2\core_core_core_exc_$signal$3$next[0:0]$14002 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13944 $2\core_core_core_exc_$signal$4$next[0:0]$14003 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13945 $2\core_core_core_exc_$signal$5$next[0:0]$14004 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13946 $2\core_core_core_exc_$signal$6$next[0:0]$14005 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13947 $2\core_core_core_exc_$signal$7$next[0:0]$14006 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13948 $2\core_core_core_exc_$signal$8$next[0:0]$14007 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13949 $2\core_core_core_exc_$signal$9$next[0:0]$14008 + assign $1\core_core_core_exc_$signal$next[0:0]$13950 $2\core_core_core_exc_$signal$next[0:0]$14009 + assign $1\core_core_core_fn_unit$next[12:0]$13951 $2\core_core_core_fn_unit$next[12:0]$14010 + assign $1\core_core_core_input_carry$next[1:0]$13952 $2\core_core_core_input_carry$next[1:0]$14011 + assign $1\core_core_core_insn$next[31:0]$13953 $2\core_core_core_insn$next[31:0]$14012 + assign $1\core_core_core_insn_type$next[6:0]$13954 $2\core_core_core_insn_type$next[6:0]$14013 + assign $1\core_core_core_is_32bit$next[0:0]$13955 $2\core_core_core_is_32bit$next[0:0]$14014 + assign $1\core_core_core_msr$next[63:0]$13956 $2\core_core_core_msr$next[63:0]$14015 + assign $1\core_core_core_oe$next[0:0]$13957 $2\core_core_core_oe$next[0:0]$14016 + assign $1\core_core_core_oe_ok$next[0:0]$13958 $2\core_core_core_oe_ok$next[0:0]$14017 + assign $1\core_core_core_rc$next[0:0]$13959 $2\core_core_core_rc$next[0:0]$14018 + assign $1\core_core_core_rc_ok$next[0:0]$13960 $2\core_core_core_rc_ok$next[0:0]$14019 + assign $1\core_core_core_trapaddr$next[12:0]$13961 $2\core_core_core_trapaddr$next[12:0]$14020 + assign $1\core_core_core_traptype$next[7:0]$13962 $2\core_core_core_traptype$next[7:0]$14021 + assign $1\core_core_cr_in1$next[6:0]$13963 $2\core_core_cr_in1$next[6:0]$14022 + assign $1\core_core_cr_in1_ok$next[0:0]$13964 $2\core_core_cr_in1_ok$next[0:0]$14023 + assign $1\core_core_cr_in2$1$next[6:0]$13965 $2\core_core_cr_in2$1$next[6:0]$14024 + assign $1\core_core_cr_in2$next[6:0]$13966 $2\core_core_cr_in2$next[6:0]$14025 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13967 $2\core_core_cr_in2_ok$2$next[0:0]$14026 + assign $1\core_core_cr_in2_ok$next[0:0]$13968 $2\core_core_cr_in2_ok$next[0:0]$14027 + assign $1\core_core_cr_out$next[6:0]$13969 $2\core_core_cr_out$next[6:0]$14028 + assign $1\core_core_cr_wr_ok$next[0:0]$13970 $2\core_core_cr_wr_ok$next[0:0]$14029 + assign $1\core_core_ea$next[6:0]$13971 $2\core_core_ea$next[6:0]$14030 + assign $1\core_core_fast1$next[2:0]$13972 $2\core_core_fast1$next[2:0]$14031 + assign $1\core_core_fast1_ok$next[0:0]$13973 $2\core_core_fast1_ok$next[0:0]$14032 + assign $1\core_core_fast2$next[2:0]$13974 $2\core_core_fast2$next[2:0]$14033 + assign $1\core_core_fast2_ok$next[0:0]$13975 $2\core_core_fast2_ok$next[0:0]$14034 + assign $1\core_core_fasto1$next[2:0]$13976 $2\core_core_fasto1$next[2:0]$14035 + assign $1\core_core_fasto2$next[2:0]$13977 $2\core_core_fasto2$next[2:0]$14036 + assign $1\core_core_lk$next[0:0]$13978 $2\core_core_lk$next[0:0]$14037 + assign $1\core_core_reg1$next[6:0]$13979 $2\core_core_reg1$next[6:0]$14038 + assign $1\core_core_reg1_ok$next[0:0]$13980 $2\core_core_reg1_ok$next[0:0]$14039 + assign $1\core_core_reg2$next[6:0]$13981 $2\core_core_reg2$next[6:0]$14040 + assign $1\core_core_reg2_ok$next[0:0]$13982 $2\core_core_reg2_ok$next[0:0]$14041 + assign $1\core_core_reg3$next[6:0]$13983 $2\core_core_reg3$next[6:0]$14042 + assign $1\core_core_reg3_ok$next[0:0]$13984 $2\core_core_reg3_ok$next[0:0]$14043 + assign $1\core_core_rego$next[6:0]$13985 $2\core_core_rego$next[6:0]$14044 + assign $1\core_core_spr1$next[9:0]$13986 $2\core_core_spr1$next[9:0]$14045 + assign $1\core_core_spr1_ok$next[0:0]$13987 $2\core_core_spr1_ok$next[0:0]$14046 + assign $1\core_core_spro$next[9:0]$13988 $2\core_core_spro$next[9:0]$14047 + assign $1\core_core_xer_in$next[2:0]$13989 $2\core_core_xer_in$next[2:0]$14048 + assign $1\core_cr_out_ok$next[0:0]$13990 $2\core_cr_out_ok$next[0:0]$14049 + assign $1\core_ea_ok$next[0:0]$13991 $2\core_ea_ok$next[0:0]$14050 + assign $1\core_fasto1_ok$next[0:0]$13992 $2\core_fasto1_ok$next[0:0]$14051 + assign $1\core_fasto2_ok$next[0:0]$13993 $2\core_fasto2_ok$next[0:0]$14052 + assign $1\core_rego_ok$next[0:0]$13994 $2\core_rego_ok$next[0:0]$14053 + assign $1\core_spro_ok$next[0:0]$13995 $2\core_spro_ok$next[0:0]$14054 + assign $1\core_xer_out$next[0:0]$13996 $2\core_xer_out$next[0:0]$14055 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:295" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -421175,70 +412467,133 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$14296 $2\core_core_cr_wr_ok$next[0:0]$14311 $2\core_core_core_cr_wr$next[7:0]$14283 $2\core_core_core_cr_rd_ok$next[0:0]$14282 $2\core_core_core_cr_rd$next[7:0]$14281 $2\core_core_core_trapaddr$next[12:0]$14302 $2\core_core_core_exc_$signal$9$next[0:0]$14290 $2\core_core_core_exc_$signal$8$next[0:0]$14289 $2\core_core_core_exc_$signal$7$next[0:0]$14288 $2\core_core_core_exc_$signal$6$next[0:0]$14287 $2\core_core_core_exc_$signal$5$next[0:0]$14286 $2\core_core_core_exc_$signal$4$next[0:0]$14285 $2\core_core_core_exc_$signal$3$next[0:0]$14284 $2\core_core_core_exc_$signal$next[0:0]$14291 $2\core_core_core_traptype$next[7:0]$14303 $2\core_core_core_input_carry$next[1:0]$14293 $2\core_core_core_oe_ok$next[0:0]$14299 $2\core_core_core_oe$next[0:0]$14298 $2\core_core_core_rc_ok$next[0:0]$14301 $2\core_core_core_rc$next[0:0]$14300 $2\core_core_lk$next[0:0]$14319 $2\core_core_core_fn_unit$next[12:0]$14292 $2\core_core_core_insn_type$next[6:0]$14295 $2\core_core_core_insn$next[31:0]$14294 $2\core_core_core_cia$next[63:0]$14280 $2\core_core_core_msr$next[63:0]$14297 $2\core_cr_out_ok$next[0:0]$14331 $2\core_core_cr_out$next[6:0]$14310 $2\core_core_cr_in2_ok$2$next[0:0]$14308 $2\core_core_cr_in2$1$next[6:0]$14306 $2\core_core_cr_in2_ok$next[0:0]$14309 $2\core_core_cr_in2$next[6:0]$14307 $2\core_core_cr_in1_ok$next[0:0]$14305 $2\core_core_cr_in1$next[6:0]$14304 $2\core_fasto2_ok$next[0:0]$14334 $2\core_core_fasto2$next[2:0]$14318 $2\core_fasto1_ok$next[0:0]$14333 $2\core_core_fasto1$next[2:0]$14317 $2\core_core_fast2_ok$next[0:0]$14316 $2\core_core_fast2$next[2:0]$14315 $2\core_core_fast1_ok$next[0:0]$14314 $2\core_core_fast1$next[2:0]$14313 $2\core_xer_out$next[0:0]$14337 $2\core_core_xer_in$next[2:0]$14330 $2\core_core_spr1_ok$next[0:0]$14328 $2\core_core_spr1$next[9:0]$14327 $2\core_spro_ok$next[0:0]$14336 $2\core_core_spro$next[9:0]$14329 $2\core_core_reg3_ok$next[0:0]$14325 $2\core_core_reg3$next[6:0]$14324 $2\core_core_reg2_ok$next[0:0]$14323 $2\core_core_reg2$next[6:0]$14322 $2\core_core_reg1_ok$next[0:0]$14321 $2\core_core_reg1$next[6:0]$14320 $2\core_ea_ok$next[0:0]$14332 $2\core_core_ea$next[6:0]$14312 $2\core_rego_ok$next[0:0]$14335 $2\core_core_rego$next[6:0]$14326 $2\core_asmcode$next[7:0]$14279 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $2\core_core_core_is_32bit$next[0:0]$14014 $2\core_core_cr_wr_ok$next[0:0]$14029 $2\core_core_core_cr_wr$next[7:0]$14001 $2\core_core_core_cr_rd_ok$next[0:0]$14000 $2\core_core_core_cr_rd$next[7:0]$13999 $2\core_core_core_trapaddr$next[12:0]$14020 $2\core_core_core_exc_$signal$9$next[0:0]$14008 $2\core_core_core_exc_$signal$8$next[0:0]$14007 $2\core_core_core_exc_$signal$7$next[0:0]$14006 $2\core_core_core_exc_$signal$6$next[0:0]$14005 $2\core_core_core_exc_$signal$5$next[0:0]$14004 $2\core_core_core_exc_$signal$4$next[0:0]$14003 $2\core_core_core_exc_$signal$3$next[0:0]$14002 $2\core_core_core_exc_$signal$next[0:0]$14009 $2\core_core_core_traptype$next[7:0]$14021 $2\core_core_core_input_carry$next[1:0]$14011 $2\core_core_core_oe_ok$next[0:0]$14017 $2\core_core_core_oe$next[0:0]$14016 $2\core_core_core_rc_ok$next[0:0]$14019 $2\core_core_core_rc$next[0:0]$14018 $2\core_core_lk$next[0:0]$14037 $2\core_core_core_fn_unit$next[12:0]$14010 $2\core_core_core_insn_type$next[6:0]$14013 $2\core_core_core_insn$next[31:0]$14012 $2\core_core_core_cia$next[63:0]$13998 $2\core_core_core_msr$next[63:0]$14015 $2\core_cr_out_ok$next[0:0]$14049 $2\core_core_cr_out$next[6:0]$14028 $2\core_core_cr_in2_ok$2$next[0:0]$14026 $2\core_core_cr_in2$1$next[6:0]$14024 $2\core_core_cr_in2_ok$next[0:0]$14027 $2\core_core_cr_in2$next[6:0]$14025 $2\core_core_cr_in1_ok$next[0:0]$14023 $2\core_core_cr_in1$next[6:0]$14022 $2\core_fasto2_ok$next[0:0]$14052 $2\core_core_fasto2$next[2:0]$14036 $2\core_fasto1_ok$next[0:0]$14051 $2\core_core_fasto1$next[2:0]$14035 $2\core_core_fast2_ok$next[0:0]$14034 $2\core_core_fast2$next[2:0]$14033 $2\core_core_fast1_ok$next[0:0]$14032 $2\core_core_fast1$next[2:0]$14031 $2\core_xer_out$next[0:0]$14055 $2\core_core_xer_in$next[2:0]$14048 $2\core_core_spr1_ok$next[0:0]$14046 $2\core_core_spr1$next[9:0]$14045 $2\core_spro_ok$next[0:0]$14054 $2\core_core_spro$next[9:0]$14047 $2\core_core_reg3_ok$next[0:0]$14043 $2\core_core_reg3$next[6:0]$14042 $2\core_core_reg2_ok$next[0:0]$14041 $2\core_core_reg2$next[6:0]$14040 $2\core_core_reg1_ok$next[0:0]$14039 $2\core_core_reg1$next[6:0]$14038 $2\core_ea_ok$next[0:0]$14050 $2\core_core_ea$next[6:0]$14030 $2\core_rego_ok$next[0:0]$14053 $2\core_core_rego$next[6:0]$14044 $2\core_asmcode$next[7:0]$13997 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $2\core_asmcode$next[7:0]$14279 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$14280 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$14281 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$14282 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$14283 \core_core_core_cr_wr - assign $2\core_core_core_exc_$signal$3$next[0:0]$14284 \core_core_core_exc_$signal$3 - assign $2\core_core_core_exc_$signal$4$next[0:0]$14285 \core_core_core_exc_$signal$4 - assign $2\core_core_core_exc_$signal$5$next[0:0]$14286 \core_core_core_exc_$signal$5 - assign $2\core_core_core_exc_$signal$6$next[0:0]$14287 \core_core_core_exc_$signal$6 - assign $2\core_core_core_exc_$signal$7$next[0:0]$14288 \core_core_core_exc_$signal$7 - assign $2\core_core_core_exc_$signal$8$next[0:0]$14289 \core_core_core_exc_$signal$8 - assign $2\core_core_core_exc_$signal$9$next[0:0]$14290 \core_core_core_exc_$signal$9 - assign $2\core_core_core_exc_$signal$next[0:0]$14291 \core_core_core_exc_$signal - assign $2\core_core_core_fn_unit$next[12:0]$14292 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$14293 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$14294 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$14295 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$14296 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$14297 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$14298 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$14299 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$14300 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$14301 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$14302 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[7:0]$14303 \core_core_core_traptype - assign $2\core_core_cr_in1$next[6:0]$14304 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$14305 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[6:0]$14306 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[6:0]$14307 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$14308 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$14309 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[6:0]$14310 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$14311 \core_core_cr_wr_ok - assign $2\core_core_ea$next[6:0]$14312 \core_core_ea - assign $2\core_core_fast1$next[2:0]$14313 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$14314 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$14315 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$14316 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$14317 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$14318 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$14319 \core_core_lk - assign $2\core_core_reg1$next[6:0]$14320 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$14321 \core_core_reg1_ok - assign $2\core_core_reg2$next[6:0]$14322 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$14323 \core_core_reg2_ok - assign $2\core_core_reg3$next[6:0]$14324 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$14325 \core_core_reg3_ok - assign $2\core_core_rego$next[6:0]$14326 \core_core_rego - assign $2\core_core_spr1$next[9:0]$14327 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$14328 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$14329 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$14330 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$14331 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$14332 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$14333 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$14334 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$14335 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$14336 \core_spro_ok - assign $2\core_xer_out$next[0:0]$14337 \core_xer_out + assign $2\core_asmcode$next[7:0]$13997 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$13998 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$13999 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$14000 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$14001 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$14002 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$14003 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$14004 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$14005 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$14006 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$14007 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$14008 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$14009 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[12:0]$14010 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$14011 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$14012 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$14013 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$14014 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$14015 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$14016 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$14017 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$14018 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$14019 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$14020 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$14021 \core_core_core_traptype + assign $2\core_core_cr_in1$next[6:0]$14022 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$14023 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[6:0]$14024 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[6:0]$14025 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$14026 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$14027 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[6:0]$14028 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$14029 \core_core_cr_wr_ok + assign $2\core_core_ea$next[6:0]$14030 \core_core_ea + assign $2\core_core_fast1$next[2:0]$14031 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$14032 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$14033 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$14034 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$14035 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$14036 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$14037 \core_core_lk + assign $2\core_core_reg1$next[6:0]$14038 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$14039 \core_core_reg1_ok + assign $2\core_core_reg2$next[6:0]$14040 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$14041 \core_core_reg2_ok + assign $2\core_core_reg3$next[6:0]$14042 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$14043 \core_core_reg3_ok + assign $2\core_core_rego$next[6:0]$14044 \core_core_rego + assign $2\core_core_spr1$next[9:0]$14045 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$14046 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$14047 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$14048 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$14049 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$14050 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$14051 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$14052 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$14053 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$14054 \core_spro_ok + assign $2\core_xer_out$next[0:0]$14055 \core_xer_out end + case + assign $1\core_asmcode$next[7:0]$13938 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$13939 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$13940 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$13941 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$13942 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$13943 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$13944 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$13945 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$13946 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$13947 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$13948 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$13949 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$13950 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[12:0]$13951 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$13952 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$13953 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$13954 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$13955 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$13956 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$13957 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$13958 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$13959 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$13960 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$13961 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$13962 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$13963 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$13964 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$13965 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$13966 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$13967 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$13968 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$13969 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$13970 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$13971 \core_core_ea + assign $1\core_core_fast1$next[2:0]$13972 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$13973 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$13974 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$13975 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$13976 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$13977 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$13978 \core_core_lk + assign $1\core_core_reg1$next[6:0]$13979 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$13980 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$13981 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$13982 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$13983 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$13984 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$13985 \core_core_rego + assign $1\core_core_spr1$next[9:0]$13986 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$13987 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$13988 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$13989 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$13990 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$13991 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$13992 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$13993 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$13994 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$13995 \core_spro_ok + assign $1\core_xer_out$next[0:0]$13996 \core_xer_out + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 1'1 assign { } { } assign { } { } assign { } { } @@ -421298,67 +412653,67 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$14220 $3\core_asmcode$next[7:0]$14338 - assign $1\core_core_core_cia$next[63:0]$14221 $3\core_core_core_cia$next[63:0]$14339 - assign $1\core_core_core_cr_rd$next[7:0]$14222 $3\core_core_core_cr_rd$next[7:0]$14340 - assign $1\core_core_core_cr_rd_ok$next[0:0]$14223 $3\core_core_core_cr_rd_ok$next[0:0]$14341 - assign $1\core_core_core_cr_wr$next[7:0]$14224 $3\core_core_core_cr_wr$next[7:0]$14342 - assign $1\core_core_core_exc_$signal$3$next[0:0]$14225 $3\core_core_core_exc_$signal$3$next[0:0]$14343 - assign $1\core_core_core_exc_$signal$4$next[0:0]$14226 $3\core_core_core_exc_$signal$4$next[0:0]$14344 - assign $1\core_core_core_exc_$signal$5$next[0:0]$14227 $3\core_core_core_exc_$signal$5$next[0:0]$14345 - assign $1\core_core_core_exc_$signal$6$next[0:0]$14228 $3\core_core_core_exc_$signal$6$next[0:0]$14346 - assign $1\core_core_core_exc_$signal$7$next[0:0]$14229 $3\core_core_core_exc_$signal$7$next[0:0]$14347 - assign $1\core_core_core_exc_$signal$8$next[0:0]$14230 $3\core_core_core_exc_$signal$8$next[0:0]$14348 - assign $1\core_core_core_exc_$signal$9$next[0:0]$14231 $3\core_core_core_exc_$signal$9$next[0:0]$14349 - assign $1\core_core_core_exc_$signal$next[0:0]$14232 $3\core_core_core_exc_$signal$next[0:0]$14350 - assign $1\core_core_core_fn_unit$next[12:0]$14233 $3\core_core_core_fn_unit$next[12:0]$14351 - assign $1\core_core_core_input_carry$next[1:0]$14234 $3\core_core_core_input_carry$next[1:0]$14352 - assign $1\core_core_core_insn$next[31:0]$14235 $3\core_core_core_insn$next[31:0]$14353 - assign $1\core_core_core_insn_type$next[6:0]$14236 $3\core_core_core_insn_type$next[6:0]$14354 - assign $1\core_core_core_is_32bit$next[0:0]$14237 $3\core_core_core_is_32bit$next[0:0]$14355 - assign $1\core_core_core_msr$next[63:0]$14238 $3\core_core_core_msr$next[63:0]$14356 - assign $1\core_core_core_oe$next[0:0]$14239 $3\core_core_core_oe$next[0:0]$14357 - assign $1\core_core_core_oe_ok$next[0:0]$14240 $3\core_core_core_oe_ok$next[0:0]$14358 - assign $1\core_core_core_rc$next[0:0]$14241 $3\core_core_core_rc$next[0:0]$14359 - assign $1\core_core_core_rc_ok$next[0:0]$14242 $3\core_core_core_rc_ok$next[0:0]$14360 - assign $1\core_core_core_trapaddr$next[12:0]$14243 $3\core_core_core_trapaddr$next[12:0]$14361 - assign $1\core_core_core_traptype$next[7:0]$14244 $3\core_core_core_traptype$next[7:0]$14362 - assign $1\core_core_cr_in1$next[6:0]$14245 $3\core_core_cr_in1$next[6:0]$14363 - assign $1\core_core_cr_in1_ok$next[0:0]$14246 $3\core_core_cr_in1_ok$next[0:0]$14364 - assign $1\core_core_cr_in2$1$next[6:0]$14247 $3\core_core_cr_in2$1$next[6:0]$14365 - assign $1\core_core_cr_in2$next[6:0]$14248 $3\core_core_cr_in2$next[6:0]$14366 - assign $1\core_core_cr_in2_ok$2$next[0:0]$14249 $3\core_core_cr_in2_ok$2$next[0:0]$14367 - assign $1\core_core_cr_in2_ok$next[0:0]$14250 $3\core_core_cr_in2_ok$next[0:0]$14368 - assign $1\core_core_cr_out$next[6:0]$14251 $3\core_core_cr_out$next[6:0]$14369 - assign $1\core_core_cr_wr_ok$next[0:0]$14252 $3\core_core_cr_wr_ok$next[0:0]$14370 - assign $1\core_core_ea$next[6:0]$14253 $3\core_core_ea$next[6:0]$14371 - assign $1\core_core_fast1$next[2:0]$14254 $3\core_core_fast1$next[2:0]$14372 - assign $1\core_core_fast1_ok$next[0:0]$14255 $3\core_core_fast1_ok$next[0:0]$14373 - assign $1\core_core_fast2$next[2:0]$14256 $3\core_core_fast2$next[2:0]$14374 - assign $1\core_core_fast2_ok$next[0:0]$14257 $3\core_core_fast2_ok$next[0:0]$14375 - assign $1\core_core_fasto1$next[2:0]$14258 $3\core_core_fasto1$next[2:0]$14376 - assign $1\core_core_fasto2$next[2:0]$14259 $3\core_core_fasto2$next[2:0]$14377 - assign $1\core_core_lk$next[0:0]$14260 $3\core_core_lk$next[0:0]$14378 - assign $1\core_core_reg1$next[6:0]$14261 $3\core_core_reg1$next[6:0]$14379 - assign $1\core_core_reg1_ok$next[0:0]$14262 $3\core_core_reg1_ok$next[0:0]$14380 - assign $1\core_core_reg2$next[6:0]$14263 $3\core_core_reg2$next[6:0]$14381 - assign $1\core_core_reg2_ok$next[0:0]$14264 $3\core_core_reg2_ok$next[0:0]$14382 - assign $1\core_core_reg3$next[6:0]$14265 $3\core_core_reg3$next[6:0]$14383 - assign $1\core_core_reg3_ok$next[0:0]$14266 $3\core_core_reg3_ok$next[0:0]$14384 - assign $1\core_core_rego$next[6:0]$14267 $3\core_core_rego$next[6:0]$14385 - assign $1\core_core_spr1$next[9:0]$14268 $3\core_core_spr1$next[9:0]$14386 - assign $1\core_core_spr1_ok$next[0:0]$14269 $3\core_core_spr1_ok$next[0:0]$14387 - assign $1\core_core_spro$next[9:0]$14270 $3\core_core_spro$next[9:0]$14388 - assign $1\core_core_xer_in$next[2:0]$14271 $3\core_core_xer_in$next[2:0]$14389 - assign $1\core_cr_out_ok$next[0:0]$14272 $3\core_cr_out_ok$next[0:0]$14390 - assign $1\core_ea_ok$next[0:0]$14273 $3\core_ea_ok$next[0:0]$14391 - assign $1\core_fasto1_ok$next[0:0]$14274 $3\core_fasto1_ok$next[0:0]$14392 - assign $1\core_fasto2_ok$next[0:0]$14275 $3\core_fasto2_ok$next[0:0]$14393 - assign $1\core_rego_ok$next[0:0]$14276 $3\core_rego_ok$next[0:0]$14394 - assign $1\core_spro_ok$next[0:0]$14277 $3\core_spro_ok$next[0:0]$14395 - assign $1\core_xer_out$next[0:0]$14278 $3\core_xer_out$next[0:0]$14396 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" - switch \$163 + assign $3\core_asmcode$next[7:0]$14056 $4\core_asmcode$next[7:0]$14115 + assign $3\core_core_core_cia$next[63:0]$14057 $4\core_core_core_cia$next[63:0]$14116 + assign $3\core_core_core_cr_rd$next[7:0]$14058 $4\core_core_core_cr_rd$next[7:0]$14117 + assign $3\core_core_core_cr_rd_ok$next[0:0]$14059 $4\core_core_core_cr_rd_ok$next[0:0]$14118 + assign $3\core_core_core_cr_wr$next[7:0]$14060 $4\core_core_core_cr_wr$next[7:0]$14119 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14061 $4\core_core_core_exc_$signal$3$next[0:0]$14120 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14062 $4\core_core_core_exc_$signal$4$next[0:0]$14121 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14063 $4\core_core_core_exc_$signal$5$next[0:0]$14122 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14064 $4\core_core_core_exc_$signal$6$next[0:0]$14123 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14065 $4\core_core_core_exc_$signal$7$next[0:0]$14124 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14066 $4\core_core_core_exc_$signal$8$next[0:0]$14125 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14067 $4\core_core_core_exc_$signal$9$next[0:0]$14126 + assign $3\core_core_core_exc_$signal$next[0:0]$14068 $4\core_core_core_exc_$signal$next[0:0]$14127 + assign $3\core_core_core_fn_unit$next[12:0]$14069 $4\core_core_core_fn_unit$next[12:0]$14128 + assign $3\core_core_core_input_carry$next[1:0]$14070 $4\core_core_core_input_carry$next[1:0]$14129 + assign $3\core_core_core_insn$next[31:0]$14071 $4\core_core_core_insn$next[31:0]$14130 + assign $3\core_core_core_insn_type$next[6:0]$14072 $4\core_core_core_insn_type$next[6:0]$14131 + assign $3\core_core_core_is_32bit$next[0:0]$14073 $4\core_core_core_is_32bit$next[0:0]$14132 + assign $3\core_core_core_msr$next[63:0]$14074 $4\core_core_core_msr$next[63:0]$14133 + assign $3\core_core_core_oe$next[0:0]$14075 $4\core_core_core_oe$next[0:0]$14134 + assign $3\core_core_core_oe_ok$next[0:0]$14076 $4\core_core_core_oe_ok$next[0:0]$14135 + assign $3\core_core_core_rc$next[0:0]$14077 $4\core_core_core_rc$next[0:0]$14136 + assign $3\core_core_core_rc_ok$next[0:0]$14078 $4\core_core_core_rc_ok$next[0:0]$14137 + assign $3\core_core_core_trapaddr$next[12:0]$14079 $4\core_core_core_trapaddr$next[12:0]$14138 + assign $3\core_core_core_traptype$next[7:0]$14080 $4\core_core_core_traptype$next[7:0]$14139 + assign $3\core_core_cr_in1$next[6:0]$14081 $4\core_core_cr_in1$next[6:0]$14140 + assign $3\core_core_cr_in1_ok$next[0:0]$14082 $4\core_core_cr_in1_ok$next[0:0]$14141 + assign $3\core_core_cr_in2$1$next[6:0]$14083 $4\core_core_cr_in2$1$next[6:0]$14142 + assign $3\core_core_cr_in2$next[6:0]$14084 $4\core_core_cr_in2$next[6:0]$14143 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14085 $4\core_core_cr_in2_ok$2$next[0:0]$14144 + assign $3\core_core_cr_in2_ok$next[0:0]$14086 $4\core_core_cr_in2_ok$next[0:0]$14145 + assign $3\core_core_cr_out$next[6:0]$14087 $4\core_core_cr_out$next[6:0]$14146 + assign $3\core_core_cr_wr_ok$next[0:0]$14088 $4\core_core_cr_wr_ok$next[0:0]$14147 + assign $3\core_core_ea$next[6:0]$14089 $4\core_core_ea$next[6:0]$14148 + assign $3\core_core_fast1$next[2:0]$14090 $4\core_core_fast1$next[2:0]$14149 + assign $3\core_core_fast1_ok$next[0:0]$14091 $4\core_core_fast1_ok$next[0:0]$14150 + assign $3\core_core_fast2$next[2:0]$14092 $4\core_core_fast2$next[2:0]$14151 + assign $3\core_core_fast2_ok$next[0:0]$14093 $4\core_core_fast2_ok$next[0:0]$14152 + assign $3\core_core_fasto1$next[2:0]$14094 $4\core_core_fasto1$next[2:0]$14153 + assign $3\core_core_fasto2$next[2:0]$14095 $4\core_core_fasto2$next[2:0]$14154 + assign $3\core_core_lk$next[0:0]$14096 $4\core_core_lk$next[0:0]$14155 + assign $3\core_core_reg1$next[6:0]$14097 $4\core_core_reg1$next[6:0]$14156 + assign $3\core_core_reg1_ok$next[0:0]$14098 $4\core_core_reg1_ok$next[0:0]$14157 + assign $3\core_core_reg2$next[6:0]$14099 $4\core_core_reg2$next[6:0]$14158 + assign $3\core_core_reg2_ok$next[0:0]$14100 $4\core_core_reg2_ok$next[0:0]$14159 + assign $3\core_core_reg3$next[6:0]$14101 $4\core_core_reg3$next[6:0]$14160 + assign $3\core_core_reg3_ok$next[0:0]$14102 $4\core_core_reg3_ok$next[0:0]$14161 + assign $3\core_core_rego$next[6:0]$14103 $4\core_core_rego$next[6:0]$14162 + assign $3\core_core_spr1$next[9:0]$14104 $4\core_core_spr1$next[9:0]$14163 + assign $3\core_core_spr1_ok$next[0:0]$14105 $4\core_core_spr1_ok$next[0:0]$14164 + assign $3\core_core_spro$next[9:0]$14106 $4\core_core_spro$next[9:0]$14165 + assign $3\core_core_xer_in$next[2:0]$14107 $4\core_core_xer_in$next[2:0]$14166 + assign $3\core_cr_out_ok$next[0:0]$14108 $4\core_cr_out_ok$next[0:0]$14167 + assign $3\core_ea_ok$next[0:0]$14109 $4\core_ea_ok$next[0:0]$14168 + assign $3\core_fasto1_ok$next[0:0]$14110 $4\core_fasto1_ok$next[0:0]$14169 + assign $3\core_fasto2_ok$next[0:0]$14111 $4\core_fasto2_ok$next[0:0]$14170 + assign $3\core_rego_ok$next[0:0]$14112 $4\core_rego_ok$next[0:0]$14171 + assign $3\core_spro_ok$next[0:0]$14113 $4\core_spro_ok$next[0:0]$14172 + assign $3\core_xer_out$next[0:0]$14114 $4\core_xer_out$next[0:0]$14173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" + switch \$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } @@ -421420,128 +412775,128 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $3\core_core_core_is_32bit$next[0:0]$14355 $3\core_core_cr_wr_ok$next[0:0]$14370 $3\core_core_core_cr_wr$next[7:0]$14342 $3\core_core_core_cr_rd_ok$next[0:0]$14341 $3\core_core_core_cr_rd$next[7:0]$14340 $3\core_core_core_trapaddr$next[12:0]$14361 $3\core_core_core_exc_$signal$9$next[0:0]$14349 $3\core_core_core_exc_$signal$8$next[0:0]$14348 $3\core_core_core_exc_$signal$7$next[0:0]$14347 $3\core_core_core_exc_$signal$6$next[0:0]$14346 $3\core_core_core_exc_$signal$5$next[0:0]$14345 $3\core_core_core_exc_$signal$4$next[0:0]$14344 $3\core_core_core_exc_$signal$3$next[0:0]$14343 $3\core_core_core_exc_$signal$next[0:0]$14350 $3\core_core_core_traptype$next[7:0]$14362 $3\core_core_core_input_carry$next[1:0]$14352 $3\core_core_core_oe_ok$next[0:0]$14358 $3\core_core_core_oe$next[0:0]$14357 $3\core_core_core_rc_ok$next[0:0]$14360 $3\core_core_core_rc$next[0:0]$14359 $3\core_core_lk$next[0:0]$14378 $3\core_core_core_fn_unit$next[12:0]$14351 $3\core_core_core_insn_type$next[6:0]$14354 $3\core_core_core_insn$next[31:0]$14353 $3\core_core_core_cia$next[63:0]$14339 $3\core_core_core_msr$next[63:0]$14356 $3\core_cr_out_ok$next[0:0]$14390 $3\core_core_cr_out$next[6:0]$14369 $3\core_core_cr_in2_ok$2$next[0:0]$14367 $3\core_core_cr_in2$1$next[6:0]$14365 $3\core_core_cr_in2_ok$next[0:0]$14368 $3\core_core_cr_in2$next[6:0]$14366 $3\core_core_cr_in1_ok$next[0:0]$14364 $3\core_core_cr_in1$next[6:0]$14363 $3\core_fasto2_ok$next[0:0]$14393 $3\core_core_fasto2$next[2:0]$14377 $3\core_fasto1_ok$next[0:0]$14392 $3\core_core_fasto1$next[2:0]$14376 $3\core_core_fast2_ok$next[0:0]$14375 $3\core_core_fast2$next[2:0]$14374 $3\core_core_fast1_ok$next[0:0]$14373 $3\core_core_fast1$next[2:0]$14372 $3\core_xer_out$next[0:0]$14396 $3\core_core_xer_in$next[2:0]$14389 $3\core_core_spr1_ok$next[0:0]$14387 $3\core_core_spr1$next[9:0]$14386 $3\core_spro_ok$next[0:0]$14395 $3\core_core_spro$next[9:0]$14388 $3\core_core_reg3_ok$next[0:0]$14384 $3\core_core_reg3$next[6:0]$14383 $3\core_core_reg2_ok$next[0:0]$14382 $3\core_core_reg2$next[6:0]$14381 $3\core_core_reg1_ok$next[0:0]$14380 $3\core_core_reg1$next[6:0]$14379 $3\core_ea_ok$next[0:0]$14391 $3\core_core_ea$next[6:0]$14371 $3\core_rego_ok$next[0:0]$14394 $3\core_core_rego$next[6:0]$14385 $3\core_asmcode$next[7:0]$14338 } 357'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $4\core_core_core_is_32bit$next[0:0]$14132 $4\core_core_cr_wr_ok$next[0:0]$14147 $4\core_core_core_cr_wr$next[7:0]$14119 $4\core_core_core_cr_rd_ok$next[0:0]$14118 $4\core_core_core_cr_rd$next[7:0]$14117 $4\core_core_core_trapaddr$next[12:0]$14138 $4\core_core_core_exc_$signal$9$next[0:0]$14126 $4\core_core_core_exc_$signal$8$next[0:0]$14125 $4\core_core_core_exc_$signal$7$next[0:0]$14124 $4\core_core_core_exc_$signal$6$next[0:0]$14123 $4\core_core_core_exc_$signal$5$next[0:0]$14122 $4\core_core_core_exc_$signal$4$next[0:0]$14121 $4\core_core_core_exc_$signal$3$next[0:0]$14120 $4\core_core_core_exc_$signal$next[0:0]$14127 $4\core_core_core_traptype$next[7:0]$14139 $4\core_core_core_input_carry$next[1:0]$14129 $4\core_core_core_oe_ok$next[0:0]$14135 $4\core_core_core_oe$next[0:0]$14134 $4\core_core_core_rc_ok$next[0:0]$14137 $4\core_core_core_rc$next[0:0]$14136 $4\core_core_lk$next[0:0]$14155 $4\core_core_core_fn_unit$next[12:0]$14128 $4\core_core_core_insn_type$next[6:0]$14131 $4\core_core_core_insn$next[31:0]$14130 $4\core_core_core_cia$next[63:0]$14116 $4\core_core_core_msr$next[63:0]$14133 $4\core_cr_out_ok$next[0:0]$14167 $4\core_core_cr_out$next[6:0]$14146 $4\core_core_cr_in2_ok$2$next[0:0]$14144 $4\core_core_cr_in2$1$next[6:0]$14142 $4\core_core_cr_in2_ok$next[0:0]$14145 $4\core_core_cr_in2$next[6:0]$14143 $4\core_core_cr_in1_ok$next[0:0]$14141 $4\core_core_cr_in1$next[6:0]$14140 $4\core_fasto2_ok$next[0:0]$14170 $4\core_core_fasto2$next[2:0]$14154 $4\core_fasto1_ok$next[0:0]$14169 $4\core_core_fasto1$next[2:0]$14153 $4\core_core_fast2_ok$next[0:0]$14152 $4\core_core_fast2$next[2:0]$14151 $4\core_core_fast1_ok$next[0:0]$14150 $4\core_core_fast1$next[2:0]$14149 $4\core_xer_out$next[0:0]$14173 $4\core_core_xer_in$next[2:0]$14166 $4\core_core_spr1_ok$next[0:0]$14164 $4\core_core_spr1$next[9:0]$14163 $4\core_spro_ok$next[0:0]$14172 $4\core_core_spro$next[9:0]$14165 $4\core_core_reg3_ok$next[0:0]$14161 $4\core_core_reg3$next[6:0]$14160 $4\core_core_reg2_ok$next[0:0]$14159 $4\core_core_reg2$next[6:0]$14158 $4\core_core_reg1_ok$next[0:0]$14157 $4\core_core_reg1$next[6:0]$14156 $4\core_ea_ok$next[0:0]$14168 $4\core_core_ea$next[6:0]$14148 $4\core_rego_ok$next[0:0]$14171 $4\core_core_rego$next[6:0]$14162 $4\core_asmcode$next[7:0]$14115 } 357'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $3\core_asmcode$next[7:0]$14338 \core_asmcode - assign $3\core_core_core_cia$next[63:0]$14339 \core_core_core_cia - assign $3\core_core_core_cr_rd$next[7:0]$14340 \core_core_core_cr_rd - assign $3\core_core_core_cr_rd_ok$next[0:0]$14341 \core_core_core_cr_rd_ok - assign $3\core_core_core_cr_wr$next[7:0]$14342 \core_core_core_cr_wr - assign $3\core_core_core_exc_$signal$3$next[0:0]$14343 \core_core_core_exc_$signal$3 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14344 \core_core_core_exc_$signal$4 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14345 \core_core_core_exc_$signal$5 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14346 \core_core_core_exc_$signal$6 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14347 \core_core_core_exc_$signal$7 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14348 \core_core_core_exc_$signal$8 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14349 \core_core_core_exc_$signal$9 - assign $3\core_core_core_exc_$signal$next[0:0]$14350 \core_core_core_exc_$signal - assign $3\core_core_core_fn_unit$next[12:0]$14351 \core_core_core_fn_unit - assign $3\core_core_core_input_carry$next[1:0]$14352 \core_core_core_input_carry - assign $3\core_core_core_insn$next[31:0]$14353 \core_core_core_insn - assign $3\core_core_core_insn_type$next[6:0]$14354 \core_core_core_insn_type - assign $3\core_core_core_is_32bit$next[0:0]$14355 \core_core_core_is_32bit - assign $3\core_core_core_msr$next[63:0]$14356 \core_core_core_msr - assign $3\core_core_core_oe$next[0:0]$14357 \core_core_core_oe - assign $3\core_core_core_oe_ok$next[0:0]$14358 \core_core_core_oe_ok - assign $3\core_core_core_rc$next[0:0]$14359 \core_core_core_rc - assign $3\core_core_core_rc_ok$next[0:0]$14360 \core_core_core_rc_ok - assign $3\core_core_core_trapaddr$next[12:0]$14361 \core_core_core_trapaddr - assign $3\core_core_core_traptype$next[7:0]$14362 \core_core_core_traptype - assign $3\core_core_cr_in1$next[6:0]$14363 \core_core_cr_in1 - assign $3\core_core_cr_in1_ok$next[0:0]$14364 \core_core_cr_in1_ok - assign $3\core_core_cr_in2$1$next[6:0]$14365 \core_core_cr_in2$1 - assign $3\core_core_cr_in2$next[6:0]$14366 \core_core_cr_in2 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14367 \core_core_cr_in2_ok$2 - assign $3\core_core_cr_in2_ok$next[0:0]$14368 \core_core_cr_in2_ok - assign $3\core_core_cr_out$next[6:0]$14369 \core_core_cr_out - assign $3\core_core_cr_wr_ok$next[0:0]$14370 \core_core_cr_wr_ok - assign $3\core_core_ea$next[6:0]$14371 \core_core_ea - assign $3\core_core_fast1$next[2:0]$14372 \core_core_fast1 - assign $3\core_core_fast1_ok$next[0:0]$14373 \core_core_fast1_ok - assign $3\core_core_fast2$next[2:0]$14374 \core_core_fast2 - assign $3\core_core_fast2_ok$next[0:0]$14375 \core_core_fast2_ok - assign $3\core_core_fasto1$next[2:0]$14376 \core_core_fasto1 - assign $3\core_core_fasto2$next[2:0]$14377 \core_core_fasto2 - assign $3\core_core_lk$next[0:0]$14378 \core_core_lk - assign $3\core_core_reg1$next[6:0]$14379 \core_core_reg1 - assign $3\core_core_reg1_ok$next[0:0]$14380 \core_core_reg1_ok - assign $3\core_core_reg2$next[6:0]$14381 \core_core_reg2 - assign $3\core_core_reg2_ok$next[0:0]$14382 \core_core_reg2_ok - assign $3\core_core_reg3$next[6:0]$14383 \core_core_reg3 - assign $3\core_core_reg3_ok$next[0:0]$14384 \core_core_reg3_ok - assign $3\core_core_rego$next[6:0]$14385 \core_core_rego - assign $3\core_core_spr1$next[9:0]$14386 \core_core_spr1 - assign $3\core_core_spr1_ok$next[0:0]$14387 \core_core_spr1_ok - assign $3\core_core_spro$next[9:0]$14388 \core_core_spro - assign $3\core_core_xer_in$next[2:0]$14389 \core_core_xer_in - assign $3\core_cr_out_ok$next[0:0]$14390 \core_cr_out_ok - assign $3\core_ea_ok$next[0:0]$14391 \core_ea_ok - assign $3\core_fasto1_ok$next[0:0]$14392 \core_fasto1_ok - assign $3\core_fasto2_ok$next[0:0]$14393 \core_fasto2_ok - assign $3\core_rego_ok$next[0:0]$14394 \core_rego_ok - assign $3\core_spro_ok$next[0:0]$14395 \core_spro_ok - assign $3\core_xer_out$next[0:0]$14396 \core_xer_out + assign $4\core_asmcode$next[7:0]$14115 $1\core_asmcode$next[7:0]$13938 + assign $4\core_core_core_cia$next[63:0]$14116 $1\core_core_core_cia$next[63:0]$13939 + assign $4\core_core_core_cr_rd$next[7:0]$14117 $1\core_core_core_cr_rd$next[7:0]$13940 + assign $4\core_core_core_cr_rd_ok$next[0:0]$14118 $1\core_core_core_cr_rd_ok$next[0:0]$13941 + assign $4\core_core_core_cr_wr$next[7:0]$14119 $1\core_core_core_cr_wr$next[7:0]$13942 + assign $4\core_core_core_exc_$signal$3$next[0:0]$14120 $1\core_core_core_exc_$signal$3$next[0:0]$13943 + assign $4\core_core_core_exc_$signal$4$next[0:0]$14121 $1\core_core_core_exc_$signal$4$next[0:0]$13944 + assign $4\core_core_core_exc_$signal$5$next[0:0]$14122 $1\core_core_core_exc_$signal$5$next[0:0]$13945 + assign $4\core_core_core_exc_$signal$6$next[0:0]$14123 $1\core_core_core_exc_$signal$6$next[0:0]$13946 + assign $4\core_core_core_exc_$signal$7$next[0:0]$14124 $1\core_core_core_exc_$signal$7$next[0:0]$13947 + assign $4\core_core_core_exc_$signal$8$next[0:0]$14125 $1\core_core_core_exc_$signal$8$next[0:0]$13948 + assign $4\core_core_core_exc_$signal$9$next[0:0]$14126 $1\core_core_core_exc_$signal$9$next[0:0]$13949 + assign $4\core_core_core_exc_$signal$next[0:0]$14127 $1\core_core_core_exc_$signal$next[0:0]$13950 + assign $4\core_core_core_fn_unit$next[12:0]$14128 $1\core_core_core_fn_unit$next[12:0]$13951 + assign $4\core_core_core_input_carry$next[1:0]$14129 $1\core_core_core_input_carry$next[1:0]$13952 + assign $4\core_core_core_insn$next[31:0]$14130 $1\core_core_core_insn$next[31:0]$13953 + assign $4\core_core_core_insn_type$next[6:0]$14131 $1\core_core_core_insn_type$next[6:0]$13954 + assign $4\core_core_core_is_32bit$next[0:0]$14132 $1\core_core_core_is_32bit$next[0:0]$13955 + assign $4\core_core_core_msr$next[63:0]$14133 $1\core_core_core_msr$next[63:0]$13956 + assign $4\core_core_core_oe$next[0:0]$14134 $1\core_core_core_oe$next[0:0]$13957 + assign $4\core_core_core_oe_ok$next[0:0]$14135 $1\core_core_core_oe_ok$next[0:0]$13958 + assign $4\core_core_core_rc$next[0:0]$14136 $1\core_core_core_rc$next[0:0]$13959 + assign $4\core_core_core_rc_ok$next[0:0]$14137 $1\core_core_core_rc_ok$next[0:0]$13960 + assign $4\core_core_core_trapaddr$next[12:0]$14138 $1\core_core_core_trapaddr$next[12:0]$13961 + assign $4\core_core_core_traptype$next[7:0]$14139 $1\core_core_core_traptype$next[7:0]$13962 + assign $4\core_core_cr_in1$next[6:0]$14140 $1\core_core_cr_in1$next[6:0]$13963 + assign $4\core_core_cr_in1_ok$next[0:0]$14141 $1\core_core_cr_in1_ok$next[0:0]$13964 + assign $4\core_core_cr_in2$1$next[6:0]$14142 $1\core_core_cr_in2$1$next[6:0]$13965 + assign $4\core_core_cr_in2$next[6:0]$14143 $1\core_core_cr_in2$next[6:0]$13966 + assign $4\core_core_cr_in2_ok$2$next[0:0]$14144 $1\core_core_cr_in2_ok$2$next[0:0]$13967 + assign $4\core_core_cr_in2_ok$next[0:0]$14145 $1\core_core_cr_in2_ok$next[0:0]$13968 + assign $4\core_core_cr_out$next[6:0]$14146 $1\core_core_cr_out$next[6:0]$13969 + assign $4\core_core_cr_wr_ok$next[0:0]$14147 $1\core_core_cr_wr_ok$next[0:0]$13970 + assign $4\core_core_ea$next[6:0]$14148 $1\core_core_ea$next[6:0]$13971 + assign $4\core_core_fast1$next[2:0]$14149 $1\core_core_fast1$next[2:0]$13972 + assign $4\core_core_fast1_ok$next[0:0]$14150 $1\core_core_fast1_ok$next[0:0]$13973 + assign $4\core_core_fast2$next[2:0]$14151 $1\core_core_fast2$next[2:0]$13974 + assign $4\core_core_fast2_ok$next[0:0]$14152 $1\core_core_fast2_ok$next[0:0]$13975 + assign $4\core_core_fasto1$next[2:0]$14153 $1\core_core_fasto1$next[2:0]$13976 + assign $4\core_core_fasto2$next[2:0]$14154 $1\core_core_fasto2$next[2:0]$13977 + assign $4\core_core_lk$next[0:0]$14155 $1\core_core_lk$next[0:0]$13978 + assign $4\core_core_reg1$next[6:0]$14156 $1\core_core_reg1$next[6:0]$13979 + assign $4\core_core_reg1_ok$next[0:0]$14157 $1\core_core_reg1_ok$next[0:0]$13980 + assign $4\core_core_reg2$next[6:0]$14158 $1\core_core_reg2$next[6:0]$13981 + assign $4\core_core_reg2_ok$next[0:0]$14159 $1\core_core_reg2_ok$next[0:0]$13982 + assign $4\core_core_reg3$next[6:0]$14160 $1\core_core_reg3$next[6:0]$13983 + assign $4\core_core_reg3_ok$next[0:0]$14161 $1\core_core_reg3_ok$next[0:0]$13984 + assign $4\core_core_rego$next[6:0]$14162 $1\core_core_rego$next[6:0]$13985 + assign $4\core_core_spr1$next[9:0]$14163 $1\core_core_spr1$next[9:0]$13986 + assign $4\core_core_spr1_ok$next[0:0]$14164 $1\core_core_spr1_ok$next[0:0]$13987 + assign $4\core_core_spro$next[9:0]$14165 $1\core_core_spro$next[9:0]$13988 + assign $4\core_core_xer_in$next[2:0]$14166 $1\core_core_xer_in$next[2:0]$13989 + assign $4\core_cr_out_ok$next[0:0]$14167 $1\core_cr_out_ok$next[0:0]$13990 + assign $4\core_ea_ok$next[0:0]$14168 $1\core_ea_ok$next[0:0]$13991 + assign $4\core_fasto1_ok$next[0:0]$14169 $1\core_fasto1_ok$next[0:0]$13992 + assign $4\core_fasto2_ok$next[0:0]$14170 $1\core_fasto2_ok$next[0:0]$13993 + assign $4\core_rego_ok$next[0:0]$14171 $1\core_rego_ok$next[0:0]$13994 + assign $4\core_spro_ok$next[0:0]$14172 $1\core_spro_ok$next[0:0]$13995 + assign $4\core_xer_out$next[0:0]$14173 $1\core_xer_out$next[0:0]$13996 end case - assign $1\core_asmcode$next[7:0]$14220 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$14221 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$14222 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$14223 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$14224 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$14225 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$14226 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$14227 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$14228 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$14229 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$14230 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$14231 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$14232 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[12:0]$14233 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$14234 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$14235 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$14236 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$14237 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$14238 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$14239 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$14240 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$14241 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$14242 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$14243 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$14244 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$14245 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$14246 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$14247 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$14248 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$14249 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$14250 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$14251 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$14252 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$14253 \core_core_ea - assign $1\core_core_fast1$next[2:0]$14254 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$14255 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$14256 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$14257 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$14258 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$14259 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$14260 \core_core_lk - assign $1\core_core_reg1$next[6:0]$14261 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$14262 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$14263 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$14264 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$14265 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$14266 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$14267 \core_core_rego - assign $1\core_core_spr1$next[9:0]$14268 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$14269 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$14270 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$14271 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$14272 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$14273 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$14274 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$14275 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$14276 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$14277 \core_spro_ok - assign $1\core_xer_out$next[0:0]$14278 \core_xer_out + assign $3\core_asmcode$next[7:0]$14056 $1\core_asmcode$next[7:0]$13938 + assign $3\core_core_core_cia$next[63:0]$14057 $1\core_core_core_cia$next[63:0]$13939 + assign $3\core_core_core_cr_rd$next[7:0]$14058 $1\core_core_core_cr_rd$next[7:0]$13940 + assign $3\core_core_core_cr_rd_ok$next[0:0]$14059 $1\core_core_core_cr_rd_ok$next[0:0]$13941 + assign $3\core_core_core_cr_wr$next[7:0]$14060 $1\core_core_core_cr_wr$next[7:0]$13942 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14061 $1\core_core_core_exc_$signal$3$next[0:0]$13943 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14062 $1\core_core_core_exc_$signal$4$next[0:0]$13944 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14063 $1\core_core_core_exc_$signal$5$next[0:0]$13945 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14064 $1\core_core_core_exc_$signal$6$next[0:0]$13946 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14065 $1\core_core_core_exc_$signal$7$next[0:0]$13947 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14066 $1\core_core_core_exc_$signal$8$next[0:0]$13948 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14067 $1\core_core_core_exc_$signal$9$next[0:0]$13949 + assign $3\core_core_core_exc_$signal$next[0:0]$14068 $1\core_core_core_exc_$signal$next[0:0]$13950 + assign $3\core_core_core_fn_unit$next[12:0]$14069 $1\core_core_core_fn_unit$next[12:0]$13951 + assign $3\core_core_core_input_carry$next[1:0]$14070 $1\core_core_core_input_carry$next[1:0]$13952 + assign $3\core_core_core_insn$next[31:0]$14071 $1\core_core_core_insn$next[31:0]$13953 + assign $3\core_core_core_insn_type$next[6:0]$14072 $1\core_core_core_insn_type$next[6:0]$13954 + assign $3\core_core_core_is_32bit$next[0:0]$14073 $1\core_core_core_is_32bit$next[0:0]$13955 + assign $3\core_core_core_msr$next[63:0]$14074 $1\core_core_core_msr$next[63:0]$13956 + assign $3\core_core_core_oe$next[0:0]$14075 $1\core_core_core_oe$next[0:0]$13957 + assign $3\core_core_core_oe_ok$next[0:0]$14076 $1\core_core_core_oe_ok$next[0:0]$13958 + assign $3\core_core_core_rc$next[0:0]$14077 $1\core_core_core_rc$next[0:0]$13959 + assign $3\core_core_core_rc_ok$next[0:0]$14078 $1\core_core_core_rc_ok$next[0:0]$13960 + assign $3\core_core_core_trapaddr$next[12:0]$14079 $1\core_core_core_trapaddr$next[12:0]$13961 + assign $3\core_core_core_traptype$next[7:0]$14080 $1\core_core_core_traptype$next[7:0]$13962 + assign $3\core_core_cr_in1$next[6:0]$14081 $1\core_core_cr_in1$next[6:0]$13963 + assign $3\core_core_cr_in1_ok$next[0:0]$14082 $1\core_core_cr_in1_ok$next[0:0]$13964 + assign $3\core_core_cr_in2$1$next[6:0]$14083 $1\core_core_cr_in2$1$next[6:0]$13965 + assign $3\core_core_cr_in2$next[6:0]$14084 $1\core_core_cr_in2$next[6:0]$13966 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14085 $1\core_core_cr_in2_ok$2$next[0:0]$13967 + assign $3\core_core_cr_in2_ok$next[0:0]$14086 $1\core_core_cr_in2_ok$next[0:0]$13968 + assign $3\core_core_cr_out$next[6:0]$14087 $1\core_core_cr_out$next[6:0]$13969 + assign $3\core_core_cr_wr_ok$next[0:0]$14088 $1\core_core_cr_wr_ok$next[0:0]$13970 + assign $3\core_core_ea$next[6:0]$14089 $1\core_core_ea$next[6:0]$13971 + assign $3\core_core_fast1$next[2:0]$14090 $1\core_core_fast1$next[2:0]$13972 + assign $3\core_core_fast1_ok$next[0:0]$14091 $1\core_core_fast1_ok$next[0:0]$13973 + assign $3\core_core_fast2$next[2:0]$14092 $1\core_core_fast2$next[2:0]$13974 + assign $3\core_core_fast2_ok$next[0:0]$14093 $1\core_core_fast2_ok$next[0:0]$13975 + assign $3\core_core_fasto1$next[2:0]$14094 $1\core_core_fasto1$next[2:0]$13976 + assign $3\core_core_fasto2$next[2:0]$14095 $1\core_core_fasto2$next[2:0]$13977 + assign $3\core_core_lk$next[0:0]$14096 $1\core_core_lk$next[0:0]$13978 + assign $3\core_core_reg1$next[6:0]$14097 $1\core_core_reg1$next[6:0]$13979 + assign $3\core_core_reg1_ok$next[0:0]$14098 $1\core_core_reg1_ok$next[0:0]$13980 + assign $3\core_core_reg2$next[6:0]$14099 $1\core_core_reg2$next[6:0]$13981 + assign $3\core_core_reg2_ok$next[0:0]$14100 $1\core_core_reg2_ok$next[0:0]$13982 + assign $3\core_core_reg3$next[6:0]$14101 $1\core_core_reg3$next[6:0]$13983 + assign $3\core_core_reg3_ok$next[0:0]$14102 $1\core_core_reg3_ok$next[0:0]$13984 + assign $3\core_core_rego$next[6:0]$14103 $1\core_core_rego$next[6:0]$13985 + assign $3\core_core_spr1$next[9:0]$14104 $1\core_core_spr1$next[9:0]$13986 + assign $3\core_core_spr1_ok$next[0:0]$14105 $1\core_core_spr1_ok$next[0:0]$13987 + assign $3\core_core_spro$next[9:0]$14106 $1\core_core_spro$next[9:0]$13988 + assign $3\core_core_xer_in$next[2:0]$14107 $1\core_core_xer_in$next[2:0]$13989 + assign $3\core_cr_out_ok$next[0:0]$14108 $1\core_cr_out_ok$next[0:0]$13990 + assign $3\core_ea_ok$next[0:0]$14109 $1\core_ea_ok$next[0:0]$13991 + assign $3\core_fasto1_ok$next[0:0]$14110 $1\core_fasto1_ok$next[0:0]$13992 + assign $3\core_fasto2_ok$next[0:0]$14111 $1\core_fasto2_ok$next[0:0]$13993 + assign $3\core_rego_ok$next[0:0]$14112 $1\core_rego_ok$next[0:0]$13994 + assign $3\core_spro_ok$next[0:0]$14113 $1\core_spro_ok$next[0:0]$13995 + assign $3\core_xer_out$next[0:0]$14114 $1\core_xer_out$next[0:0]$13996 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -421574,266 +412929,210 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\core_rego_ok$next[0:0]$14422 1'0 - assign $4\core_ea_ok$next[0:0]$14419 1'0 - assign $4\core_core_reg1_ok$next[0:0]$14414 1'0 - assign $4\core_core_reg2_ok$next[0:0]$14415 1'0 - assign $4\core_core_reg3_ok$next[0:0]$14416 1'0 - assign $4\core_spro_ok$next[0:0]$14423 1'0 - assign $4\core_core_spr1_ok$next[0:0]$14417 1'0 - assign $4\core_core_fast1_ok$next[0:0]$14412 1'0 - assign $4\core_core_fast2_ok$next[0:0]$14413 1'0 - assign $4\core_fasto1_ok$next[0:0]$14420 1'0 - assign $4\core_fasto2_ok$next[0:0]$14421 1'0 - assign $4\core_core_cr_in1_ok$next[0:0]$14408 1'0 - assign $4\core_core_cr_in2_ok$next[0:0]$14410 1'0 - assign $4\core_core_cr_in2_ok$2$next[0:0]$14409 1'0 - assign $4\core_cr_out_ok$next[0:0]$14418 1'0 - assign $4\core_core_core_rc_ok$next[0:0]$14407 1'0 - assign $4\core_core_core_oe_ok$next[0:0]$14406 1'0 - assign $4\core_core_core_exc_$signal$next[0:0]$14405 1'0 - assign $4\core_core_core_exc_$signal$3$next[0:0]$14398 1'0 - assign $4\core_core_core_exc_$signal$4$next[0:0]$14399 1'0 - assign $4\core_core_core_exc_$signal$5$next[0:0]$14400 1'0 - assign $4\core_core_core_exc_$signal$6$next[0:0]$14401 1'0 - assign $4\core_core_core_exc_$signal$7$next[0:0]$14402 1'0 - assign $4\core_core_core_exc_$signal$8$next[0:0]$14403 1'0 - assign $4\core_core_core_exc_$signal$9$next[0:0]$14404 1'0 - assign $4\core_core_core_cr_rd_ok$next[0:0]$14397 1'0 - assign $4\core_core_cr_wr_ok$next[0:0]$14411 1'0 - case - assign $4\core_core_core_cr_rd_ok$next[0:0]$14397 $1\core_core_core_cr_rd_ok$next[0:0]$14223 - assign $4\core_core_core_exc_$signal$3$next[0:0]$14398 $1\core_core_core_exc_$signal$3$next[0:0]$14225 - assign $4\core_core_core_exc_$signal$4$next[0:0]$14399 $1\core_core_core_exc_$signal$4$next[0:0]$14226 - assign $4\core_core_core_exc_$signal$5$next[0:0]$14400 $1\core_core_core_exc_$signal$5$next[0:0]$14227 - assign $4\core_core_core_exc_$signal$6$next[0:0]$14401 $1\core_core_core_exc_$signal$6$next[0:0]$14228 - assign $4\core_core_core_exc_$signal$7$next[0:0]$14402 $1\core_core_core_exc_$signal$7$next[0:0]$14229 - assign $4\core_core_core_exc_$signal$8$next[0:0]$14403 $1\core_core_core_exc_$signal$8$next[0:0]$14230 - assign $4\core_core_core_exc_$signal$9$next[0:0]$14404 $1\core_core_core_exc_$signal$9$next[0:0]$14231 - assign $4\core_core_core_exc_$signal$next[0:0]$14405 $1\core_core_core_exc_$signal$next[0:0]$14232 - assign $4\core_core_core_oe_ok$next[0:0]$14406 $1\core_core_core_oe_ok$next[0:0]$14240 - assign $4\core_core_core_rc_ok$next[0:0]$14407 $1\core_core_core_rc_ok$next[0:0]$14242 - assign $4\core_core_cr_in1_ok$next[0:0]$14408 $1\core_core_cr_in1_ok$next[0:0]$14246 - assign $4\core_core_cr_in2_ok$2$next[0:0]$14409 $1\core_core_cr_in2_ok$2$next[0:0]$14249 - assign $4\core_core_cr_in2_ok$next[0:0]$14410 $1\core_core_cr_in2_ok$next[0:0]$14250 - assign $4\core_core_cr_wr_ok$next[0:0]$14411 $1\core_core_cr_wr_ok$next[0:0]$14252 - assign $4\core_core_fast1_ok$next[0:0]$14412 $1\core_core_fast1_ok$next[0:0]$14255 - assign $4\core_core_fast2_ok$next[0:0]$14413 $1\core_core_fast2_ok$next[0:0]$14257 - assign $4\core_core_reg1_ok$next[0:0]$14414 $1\core_core_reg1_ok$next[0:0]$14262 - assign $4\core_core_reg2_ok$next[0:0]$14415 $1\core_core_reg2_ok$next[0:0]$14264 - assign $4\core_core_reg3_ok$next[0:0]$14416 $1\core_core_reg3_ok$next[0:0]$14266 - assign $4\core_core_spr1_ok$next[0:0]$14417 $1\core_core_spr1_ok$next[0:0]$14269 - assign $4\core_cr_out_ok$next[0:0]$14418 $1\core_cr_out_ok$next[0:0]$14272 - assign $4\core_ea_ok$next[0:0]$14419 $1\core_ea_ok$next[0:0]$14273 - assign $4\core_fasto1_ok$next[0:0]$14420 $1\core_fasto1_ok$next[0:0]$14274 - assign $4\core_fasto2_ok$next[0:0]$14421 $1\core_fasto2_ok$next[0:0]$14275 - assign $4\core_rego_ok$next[0:0]$14422 $1\core_rego_ok$next[0:0]$14276 - assign $4\core_spro_ok$next[0:0]$14423 $1\core_spro_ok$next[0:0]$14277 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$14161 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$14162 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$14163 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$14164 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$14165 - update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$14166 - update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$14167 - update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$14168 - update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$14169 - update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$14170 - update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$14171 - update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$14172 - update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$14173 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[12:0]$14174 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$14175 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$14176 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$14177 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$14178 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$14179 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$14180 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$14181 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$14182 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$14183 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$14184 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$14185 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$14186 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$14187 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$14188 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$14189 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$14190 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14191 - update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14192 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14193 - update \core_core_ea$next $0\core_core_ea$next[6:0]$14194 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14195 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14196 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14197 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14198 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14199 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14200 - update \core_core_lk$next $0\core_core_lk$next[0:0]$14201 - update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14202 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14203 - update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14204 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14205 - update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14206 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14207 - update \core_core_rego$next $0\core_core_rego$next[6:0]$14208 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14209 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14210 - update \core_core_spro$next $0\core_core_spro$next[9:0]$14211 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14212 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14213 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14214 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14215 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14216 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14217 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14218 - update \core_xer_out$next $0\core_xer_out$next[0:0]$14219 - end - attribute \src "libresoc.v:202859.3-202867.6" - process $proc$libresoc.v:202859$14424 - assign { } { } - assign { } { } - assign $0\dec2_cur_eint$next[0:0]$14425 $1\dec2_cur_eint$next[0:0]$14426 - attribute \src "libresoc.v:202860.5-202860.29" - switch \initial - attribute \src "libresoc.v:202860.9-202860.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dec2_cur_eint$next[0:0]$14426 1'0 - case - assign $1\dec2_cur_eint$next[0:0]$14426 \xics_icp_core_irq_o - end - sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$14425 - end - attribute \src "libresoc.v:202868.3-202877.6" - process $proc$libresoc.v:202868$14427 - assign { } { } - assign { } { } - assign $0\delay$next[1:0]$14428 $1\delay$next[1:0]$14429 - attribute \src "libresoc.v:202869.5-202869.29" - switch \initial - attribute \src "libresoc.v:202869.9-202869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\delay$next[1:0]$14429 \$25 [1:0] - case - assign $1\delay$next[1:0]$14429 \delay - end - sync always - update \delay$next $0\delay$next[1:0]$14428 - end - connect \$99 $not$libresoc.v:200541$13703_Y - connect \$101 $not$libresoc.v:200542$13704_Y - connect \$103 $and$libresoc.v:200543$13705_Y - connect \$105 $not$libresoc.v:200544$13706_Y - connect \$107 $not$libresoc.v:200545$13707_Y - connect \$109 $not$libresoc.v:200546$13708_Y - connect \$111 $and$libresoc.v:200547$13709_Y - connect \$113 $not$libresoc.v:200548$13710_Y - connect \$115 $not$libresoc.v:200549$13711_Y - connect \$117 $not$libresoc.v:200550$13712_Y - connect \$119 $and$libresoc.v:200551$13713_Y - connect \$121 $not$libresoc.v:200552$13714_Y - connect \$123 $not$libresoc.v:200553$13715_Y - connect \$125 $not$libresoc.v:200554$13716_Y - connect \$127 $and$libresoc.v:200555$13717_Y - connect \$129 $not$libresoc.v:200556$13718_Y - connect \$131 $not$libresoc.v:200557$13719_Y - connect \$133 $and$libresoc.v:200558$13720_Y - connect \$135 $not$libresoc.v:200559$13721_Y - connect \$137 $not$libresoc.v:200560$13722_Y - connect \$140 $mul$libresoc.v:200561$13723_Y - connect \$139 $shr$libresoc.v:200562$13724_Y [31:0] - connect \$144 $ternary$libresoc.v:200563$13725_Y - connect \$146 $add$libresoc.v:200564$13726_Y - connect \$148 $not$libresoc.v:200565$13727_Y - connect \$151 $mul$libresoc.v:200566$13728_Y - connect \$150 $shr$libresoc.v:200567$13729_Y [31:0] - connect \$156 $add$libresoc.v:200568$13730_Y - connect \$158 $mul$libresoc.v:200569$13731_Y - connect \$154 $shr$libresoc.v:200570$13732_Y [31:0] - connect \$161 $not$libresoc.v:200571$13733_Y - connect \$163 $not$libresoc.v:200572$13734_Y - connect \$165 $not$libresoc.v:200573$13735_Y - connect \$167 $not$libresoc.v:200574$13736_Y - connect \$171 $add$libresoc.v:200575$13737_Y - connect \$173 $mul$libresoc.v:200576$13738_Y - connect \$169 $shr$libresoc.v:200577$13739_Y [31:0] - connect \$176 $ne$libresoc.v:200578$13740_Y - connect \$179 $and$libresoc.v:200579$13741_Y - connect \$178 $reduce_or$libresoc.v:200580$13742_Y - connect \$182 $pos$libresoc.v:200581$13743_Y - connect \$184 $pos$libresoc.v:200582$13745_Y - connect \$186 $pos$libresoc.v:200583$13747_Y - connect \$190 $sub$libresoc.v:200584$13748_Y - connect \$193 $add$libresoc.v:200585$13749_Y - connect \$23 $ne$libresoc.v:200586$13750_Y - connect \$26 $sub$libresoc.v:200587$13751_Y - connect \$28 $or$libresoc.v:200588$13752_Y - connect \$30 $or$libresoc.v:200589$13753_Y - connect \$32 $ne$libresoc.v:200590$13754_Y - connect \$34 $not$libresoc.v:200591$13755_Y - connect \$36 $and$libresoc.v:200592$13756_Y - connect \$38 $not$libresoc.v:200593$13757_Y - connect \$40 $not$libresoc.v:200594$13758_Y - connect \$42 $not$libresoc.v:200595$13759_Y - connect \$44 $not$libresoc.v:200596$13760_Y - connect \$46 $not$libresoc.v:200597$13761_Y - connect \$48 $not$libresoc.v:200598$13762_Y - connect \$50 $not$libresoc.v:200599$13763_Y - connect \$52 $and$libresoc.v:200600$13764_Y - connect \$54 $not$libresoc.v:200601$13765_Y - connect \$56 $not$libresoc.v:200602$13766_Y - connect \$58 $and$libresoc.v:200603$13767_Y - connect \$60 $not$libresoc.v:200604$13768_Y - connect \$62 $not$libresoc.v:200605$13769_Y - connect \$64 $and$libresoc.v:200606$13770_Y - connect \$66 $not$libresoc.v:200607$13771_Y - connect \$68 $not$libresoc.v:200608$13772_Y - connect \$70 $and$libresoc.v:200609$13773_Y - connect \$72 $not$libresoc.v:200610$13774_Y - connect \$75 $add$libresoc.v:200611$13775_Y - connect \$77 $not$libresoc.v:200612$13776_Y - connect \$79 $not$libresoc.v:200613$13777_Y - connect \$81 $and$libresoc.v:200614$13778_Y - connect \$83 $not$libresoc.v:200615$13779_Y - connect \$85 $not$libresoc.v:200616$13780_Y - connect \$87 $not$libresoc.v:200617$13781_Y - connect \$89 $and$libresoc.v:200618$13782_Y - connect \$91 $not$libresoc.v:200619$13783_Y - connect \$93 $not$libresoc.v:200620$13784_Y - connect \$95 $not$libresoc.v:200621$13785_Y - connect \$97 $and$libresoc.v:200622$13786_Y + assign $5\core_rego_ok$next[0:0]$14199 1'0 + assign $5\core_ea_ok$next[0:0]$14196 1'0 + assign $5\core_core_reg1_ok$next[0:0]$14191 1'0 + assign $5\core_core_reg2_ok$next[0:0]$14192 1'0 + assign $5\core_core_reg3_ok$next[0:0]$14193 1'0 + assign $5\core_spro_ok$next[0:0]$14200 1'0 + assign $5\core_core_spr1_ok$next[0:0]$14194 1'0 + assign $5\core_core_fast1_ok$next[0:0]$14189 1'0 + assign $5\core_core_fast2_ok$next[0:0]$14190 1'0 + assign $5\core_fasto1_ok$next[0:0]$14197 1'0 + assign $5\core_fasto2_ok$next[0:0]$14198 1'0 + assign $5\core_core_cr_in1_ok$next[0:0]$14185 1'0 + assign $5\core_core_cr_in2_ok$next[0:0]$14187 1'0 + assign $5\core_core_cr_in2_ok$2$next[0:0]$14186 1'0 + assign $5\core_cr_out_ok$next[0:0]$14195 1'0 + assign $5\core_core_core_rc_ok$next[0:0]$14184 1'0 + assign $5\core_core_core_oe_ok$next[0:0]$14183 1'0 + assign $5\core_core_core_exc_$signal$next[0:0]$14182 1'0 + assign $5\core_core_core_exc_$signal$3$next[0:0]$14175 1'0 + assign $5\core_core_core_exc_$signal$4$next[0:0]$14176 1'0 + assign $5\core_core_core_exc_$signal$5$next[0:0]$14177 1'0 + assign $5\core_core_core_exc_$signal$6$next[0:0]$14178 1'0 + assign $5\core_core_core_exc_$signal$7$next[0:0]$14179 1'0 + assign $5\core_core_core_exc_$signal$8$next[0:0]$14180 1'0 + assign $5\core_core_core_exc_$signal$9$next[0:0]$14181 1'0 + assign $5\core_core_core_cr_rd_ok$next[0:0]$14174 1'0 + assign $5\core_core_cr_wr_ok$next[0:0]$14188 1'0 + case + assign $5\core_core_core_cr_rd_ok$next[0:0]$14174 $3\core_core_core_cr_rd_ok$next[0:0]$14059 + assign $5\core_core_core_exc_$signal$3$next[0:0]$14175 $3\core_core_core_exc_$signal$3$next[0:0]$14061 + assign $5\core_core_core_exc_$signal$4$next[0:0]$14176 $3\core_core_core_exc_$signal$4$next[0:0]$14062 + assign $5\core_core_core_exc_$signal$5$next[0:0]$14177 $3\core_core_core_exc_$signal$5$next[0:0]$14063 + assign $5\core_core_core_exc_$signal$6$next[0:0]$14178 $3\core_core_core_exc_$signal$6$next[0:0]$14064 + assign $5\core_core_core_exc_$signal$7$next[0:0]$14179 $3\core_core_core_exc_$signal$7$next[0:0]$14065 + assign $5\core_core_core_exc_$signal$8$next[0:0]$14180 $3\core_core_core_exc_$signal$8$next[0:0]$14066 + assign $5\core_core_core_exc_$signal$9$next[0:0]$14181 $3\core_core_core_exc_$signal$9$next[0:0]$14067 + assign $5\core_core_core_exc_$signal$next[0:0]$14182 $3\core_core_core_exc_$signal$next[0:0]$14068 + assign $5\core_core_core_oe_ok$next[0:0]$14183 $3\core_core_core_oe_ok$next[0:0]$14076 + assign $5\core_core_core_rc_ok$next[0:0]$14184 $3\core_core_core_rc_ok$next[0:0]$14078 + assign $5\core_core_cr_in1_ok$next[0:0]$14185 $3\core_core_cr_in1_ok$next[0:0]$14082 + assign $5\core_core_cr_in2_ok$2$next[0:0]$14186 $3\core_core_cr_in2_ok$2$next[0:0]$14085 + assign $5\core_core_cr_in2_ok$next[0:0]$14187 $3\core_core_cr_in2_ok$next[0:0]$14086 + assign $5\core_core_cr_wr_ok$next[0:0]$14188 $3\core_core_cr_wr_ok$next[0:0]$14088 + assign $5\core_core_fast1_ok$next[0:0]$14189 $3\core_core_fast1_ok$next[0:0]$14091 + assign $5\core_core_fast2_ok$next[0:0]$14190 $3\core_core_fast2_ok$next[0:0]$14093 + assign $5\core_core_reg1_ok$next[0:0]$14191 $3\core_core_reg1_ok$next[0:0]$14098 + assign $5\core_core_reg2_ok$next[0:0]$14192 $3\core_core_reg2_ok$next[0:0]$14100 + assign $5\core_core_reg3_ok$next[0:0]$14193 $3\core_core_reg3_ok$next[0:0]$14102 + assign $5\core_core_spr1_ok$next[0:0]$14194 $3\core_core_spr1_ok$next[0:0]$14105 + assign $5\core_cr_out_ok$next[0:0]$14195 $3\core_cr_out_ok$next[0:0]$14108 + assign $5\core_ea_ok$next[0:0]$14196 $3\core_ea_ok$next[0:0]$14109 + assign $5\core_fasto1_ok$next[0:0]$14197 $3\core_fasto1_ok$next[0:0]$14110 + assign $5\core_fasto2_ok$next[0:0]$14198 $3\core_fasto2_ok$next[0:0]$14111 + assign $5\core_rego_ok$next[0:0]$14199 $3\core_rego_ok$next[0:0]$14112 + assign $5\core_spro_ok$next[0:0]$14200 $3\core_spro_ok$next[0:0]$14113 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$13879 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13880 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13881 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13882 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13883 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13884 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13885 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13886 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13887 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13888 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13889 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13890 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13891 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[12:0]$13892 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13893 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13894 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13895 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13896 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13897 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13898 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13899 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13900 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13901 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13902 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13903 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13904 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13905 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13906 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13907 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13908 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13909 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$13910 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13911 + update \core_core_ea$next $0\core_core_ea$next[6:0]$13912 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13913 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13914 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13915 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13916 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13917 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13918 + update \core_core_lk$next $0\core_core_lk$next[0:0]$13919 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$13920 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13921 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$13922 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13923 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$13924 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13925 + update \core_core_rego$next $0\core_core_rego$next[6:0]$13926 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13927 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13928 + update \core_core_spro$next $0\core_core_spro$next[9:0]$13929 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13930 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13931 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13932 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13933 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13934 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13935 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13936 + update \core_xer_out$next $0\core_xer_out$next[0:0]$13937 + end + connect \$99 $not$libresoc.v:194907$13409_Y + connect \$101 $and$libresoc.v:194908$13410_Y + connect \$103 $not$libresoc.v:194909$13411_Y + connect \$105 $not$libresoc.v:194910$13412_Y + connect \$107 $and$libresoc.v:194911$13413_Y + connect \$109 $not$libresoc.v:194912$13414_Y + connect \$111 $not$libresoc.v:194913$13415_Y + connect \$113 $and$libresoc.v:194914$13416_Y + connect \$115 $not$libresoc.v:194915$13417_Y + connect \$117 $not$libresoc.v:194916$13418_Y + connect \$119 $and$libresoc.v:194917$13419_Y + connect \$121 $not$libresoc.v:194918$13420_Y + connect \$123 $not$libresoc.v:194919$13421_Y + connect \$125 $and$libresoc.v:194920$13422_Y + connect \$127 $not$libresoc.v:194921$13423_Y + connect \$129 $not$libresoc.v:194922$13424_Y + connect \$131 $and$libresoc.v:194923$13425_Y + connect \$133 $not$libresoc.v:194924$13426_Y + connect \$135 $not$libresoc.v:194925$13427_Y + connect \$137 $not$libresoc.v:194926$13428_Y + connect \$139 $not$libresoc.v:194927$13429_Y + connect \$141 $not$libresoc.v:194928$13430_Y + connect \$143 $and$libresoc.v:194929$13431_Y + connect \$145 $pos$libresoc.v:194930$13432_Y + connect \$147 $ne$libresoc.v:194931$13433_Y + connect \$149 $not$libresoc.v:194932$13434_Y + connect \$152 $and$libresoc.v:194933$13435_Y + connect \$151 $reduce_or$libresoc.v:194934$13436_Y + connect \$155 $not$libresoc.v:194935$13437_Y + connect \$158 $and$libresoc.v:194936$13438_Y + connect \$157 $reduce_or$libresoc.v:194937$13439_Y + connect \$161 $not$libresoc.v:194938$13440_Y + connect \$163 $not$libresoc.v:194939$13441_Y + connect \$165 $not$libresoc.v:194940$13442_Y + connect \$167 $pos$libresoc.v:194941$13444_Y + connect \$169 $pos$libresoc.v:194942$13446_Y + connect \$172 $sub$libresoc.v:194943$13447_Y + connect \$175 $add$libresoc.v:194944$13448_Y + connect \$23 $ne$libresoc.v:194945$13449_Y + connect \$26 $sub$libresoc.v:194946$13450_Y + connect \$28 $or$libresoc.v:194947$13451_Y + connect \$30 $or$libresoc.v:194948$13452_Y + connect \$32 $ne$libresoc.v:194949$13453_Y + connect \$34 $not$libresoc.v:194950$13454_Y + connect \$36 $and$libresoc.v:194951$13455_Y + connect \$38 $not$libresoc.v:194952$13456_Y + connect \$40 $not$libresoc.v:194953$13457_Y + connect \$42 $pos$libresoc.v:194954$13459_Y + connect \$44 $not$libresoc.v:194955$13460_Y + connect \$46 $not$libresoc.v:194956$13461_Y + connect \$48 $and$libresoc.v:194957$13462_Y + connect \$50 $not$libresoc.v:194958$13463_Y + connect \$52 $not$libresoc.v:194959$13464_Y + connect \$54 $not$libresoc.v:194960$13465_Y + connect \$56 $and$libresoc.v:194961$13466_Y + connect \$58 $not$libresoc.v:194962$13467_Y + connect \$60 $not$libresoc.v:194963$13468_Y + connect \$63 $add$libresoc.v:194964$13469_Y + connect \$65 $not$libresoc.v:194965$13470_Y + connect \$67 $not$libresoc.v:194966$13471_Y + connect \$69 $not$libresoc.v:194967$13472_Y + connect \$71 $not$libresoc.v:194968$13473_Y + connect \$73 $not$libresoc.v:194969$13474_Y + connect \$76 $mul$libresoc.v:194970$13475_Y + connect \$75 $shr$libresoc.v:194971$13476_Y [31:0] + connect \$80 $ternary$libresoc.v:194972$13477_Y + connect \$82 $add$libresoc.v:194973$13478_Y + connect \$84 $not$libresoc.v:194974$13479_Y + connect \$87 $mul$libresoc.v:194975$13480_Y + connect \$86 $shr$libresoc.v:194976$13481_Y [31:0] + connect \$92 $add$libresoc.v:194977$13482_Y + connect \$94 $mul$libresoc.v:194978$13483_Y + connect \$90 $shr$libresoc.v:194979$13484_Y [31:0] + connect \$97 $not$libresoc.v:194980$13485_Y connect \$25 \$26 - connect \$74 \$75 - connect \$143 \$146 - connect \$155 \$156 - connect \$170 \$171 - connect \$189 \$190 - connect \$192 \$193 + connect \$62 \$63 + connect \$79 \$82 + connect \$91 \$92 + connect \$171 \$172 + connect \$174 \$175 + connect \svstate_i_ok 1'0 + connect \svstate_i 0 connect \update_svstate 1'0 - connect \new_svstate_svstep 2'00 - connect \new_svstate_subvl 2'00 - connect \new_svstate_dststep 7'0000000 - connect \new_svstate_srcstep 7'0000000 - connect \new_svstate_vl 7'0000000 - connect \new_svstate_maxvl 7'0000000 + connect { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } { \cur_cur_maxvl \cur_cur_vl \dec2_cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep } + connect \dec2_raw_opcode_in$next \fetch_insn_o connect \dbg_core_dbg_msr \dec2_cur_msr + connect { \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } \svstate [31:0] connect \dbg_core_dbg_pc \pc connect \dbg_terminate_i \core_core_terminate_o connect \pc_o \dec2_cur_pc @@ -421847,486 +413146,490 @@ module \ti connect \ti_rst \$32 connect \por_clk \clk connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } + connect \sram4k_3_enable \jtag_wb_sram_en + connect \sram4k_2_enable \jtag_wb_sram_en + connect \sram4k_1_enable \jtag_wb_sram_en + connect \sram4k_0_enable \jtag_wb_sram_en end -attribute \src "libresoc.v:202910.1-204097.10" +attribute \src "libresoc.v:197398.1-198585.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 - attribute \src "libresoc.v:203642.3-203643.25" + attribute \src "libresoc.v:198130.3-198131.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:203640.3-203641.41" + attribute \src "libresoc.v:198128.3-198129.41" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:204000.3-204008.6" - wire $0\alu_l_r_alu$next[0:0]$14757 - attribute \src "libresoc.v:203568.3-203569.39" + attribute \src "libresoc.v:198488.3-198496.6" + wire $0\alu_l_r_alu$next[0:0]$14528 + attribute \src "libresoc.v:198056.3-198057.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14683 - attribute \src "libresoc.v:203608.3-203609.61" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14454 + attribute \src "libresoc.v:198096.3-198097.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 13 $0\alu_trap0_trap_op__fn_unit$next[12:0]$14684 - attribute \src "libresoc.v:203602.3-203603.69" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 13 $0\alu_trap0_trap_op__fn_unit$next[12:0]$14455 + attribute \src "libresoc.v:198090.3-198091.69" wire width 13 $0\alu_trap0_trap_op__fn_unit[12:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14685 - attribute \src "libresoc.v:203604.3-203605.63" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14456 + attribute \src "libresoc.v:198092.3-198093.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14686 - attribute \src "libresoc.v:203600.3-203601.73" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14457 + attribute \src "libresoc.v:198088.3-198089.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14687 - attribute \src "libresoc.v:203610.3-203611.71" + attribute \src "libresoc.v:198311.3-198328.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14458 + attribute \src "libresoc.v:198098.3-198099.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14688 - attribute \src "libresoc.v:203616.3-203617.71" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14459 + attribute \src "libresoc.v:198104.3-198105.71" wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14689 - attribute \src "libresoc.v:203606.3-203607.61" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14460 + attribute \src "libresoc.v:198094.3-198095.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14690 - attribute \src "libresoc.v:203614.3-203615.71" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14461 + attribute \src "libresoc.v:198102.3-198103.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14691 - attribute \src "libresoc.v:203612.3-203613.71" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14462 + attribute \src "libresoc.v:198100.3-198101.71" wire width 8 $0\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:203991.3-203999.6" - wire $0\alui_l_r_alui$next[0:0]$14754 - attribute \src "libresoc.v:203570.3-203571.43" + attribute \src "libresoc.v:198479.3-198487.6" + wire $0\alui_l_r_alui$next[0:0]$14525 + attribute \src "libresoc.v:198058.3-198059.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:203841.3-203862.6" - wire width 64 $0\data_r0__o$next[63:0]$14702 - attribute \src "libresoc.v:203596.3-203597.37" + attribute \src "libresoc.v:198329.3-198350.6" + wire width 64 $0\data_r0__o$next[63:0]$14473 + attribute \src "libresoc.v:198084.3-198085.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:203841.3-203862.6" - wire $0\data_r0__o_ok$next[0:0]$14703 - attribute \src "libresoc.v:203598.3-203599.43" + attribute \src "libresoc.v:198329.3-198350.6" + wire $0\data_r0__o_ok$next[0:0]$14474 + attribute \src "libresoc.v:198086.3-198087.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:203863.3-203884.6" - wire width 64 $0\data_r1__fast1$next[63:0]$14710 - attribute \src "libresoc.v:203592.3-203593.45" + attribute \src "libresoc.v:198351.3-198372.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14481 + attribute \src "libresoc.v:198080.3-198081.45" wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:203863.3-203884.6" - wire $0\data_r1__fast1_ok$next[0:0]$14711 - attribute \src "libresoc.v:203594.3-203595.51" + attribute \src "libresoc.v:198351.3-198372.6" + wire $0\data_r1__fast1_ok$next[0:0]$14482 + attribute \src "libresoc.v:198082.3-198083.51" wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:203885.3-203906.6" - wire width 64 $0\data_r2__fast2$next[63:0]$14718 - attribute \src "libresoc.v:203588.3-203589.45" + attribute \src "libresoc.v:198373.3-198394.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14489 + attribute \src "libresoc.v:198076.3-198077.45" wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:203885.3-203906.6" - wire $0\data_r2__fast2_ok$next[0:0]$14719 - attribute \src "libresoc.v:203590.3-203591.51" + attribute \src "libresoc.v:198373.3-198394.6" + wire $0\data_r2__fast2_ok$next[0:0]$14490 + attribute \src "libresoc.v:198078.3-198079.51" wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:203907.3-203928.6" - wire width 64 $0\data_r3__nia$next[63:0]$14726 - attribute \src "libresoc.v:203584.3-203585.41" + attribute \src "libresoc.v:198395.3-198416.6" + wire width 64 $0\data_r3__nia$next[63:0]$14497 + attribute \src "libresoc.v:198072.3-198073.41" wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:203907.3-203928.6" - wire $0\data_r3__nia_ok$next[0:0]$14727 - attribute \src "libresoc.v:203586.3-203587.47" + attribute \src "libresoc.v:198395.3-198416.6" + wire $0\data_r3__nia_ok$next[0:0]$14498 + attribute \src "libresoc.v:198074.3-198075.47" wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:203929.3-203950.6" - wire width 64 $0\data_r4__msr$next[63:0]$14734 - attribute \src "libresoc.v:203580.3-203581.41" + attribute \src "libresoc.v:198417.3-198438.6" + wire width 64 $0\data_r4__msr$next[63:0]$14505 + attribute \src "libresoc.v:198068.3-198069.41" wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:203929.3-203950.6" - wire $0\data_r4__msr_ok$next[0:0]$14735 - attribute \src "libresoc.v:203582.3-203583.47" + attribute \src "libresoc.v:198417.3-198438.6" + wire $0\data_r4__msr_ok$next[0:0]$14506 + attribute \src "libresoc.v:198070.3-198071.47" wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:204009.3-204018.6" + attribute \src "libresoc.v:198497.3-198506.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:204019.3-204028.6" + attribute \src "libresoc.v:198507.3-198516.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:204029.3-204038.6" + attribute \src "libresoc.v:198517.3-198526.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:204039.3-204048.6" + attribute \src "libresoc.v:198527.3-198536.6" wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:204049.3-204058.6" + attribute \src "libresoc.v:198537.3-198546.6" wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:202911.7-202911.20" + attribute \src "libresoc.v:197399.7-197399.20" wire $0\initial[0:0] - attribute \src "libresoc.v:203778.3-203786.6" - wire $0\opc_l_r_opc$next[0:0]$14668 - attribute \src "libresoc.v:203626.3-203627.39" + attribute \src "libresoc.v:198266.3-198274.6" + wire $0\opc_l_r_opc$next[0:0]$14439 + attribute \src "libresoc.v:198114.3-198115.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:203769.3-203777.6" - wire $0\opc_l_s_opc$next[0:0]$14665 - attribute \src "libresoc.v:203628.3-203629.39" + attribute \src "libresoc.v:198257.3-198265.6" + wire $0\opc_l_s_opc$next[0:0]$14436 + attribute \src "libresoc.v:198116.3-198117.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:204059.3-204067.6" - wire width 5 $0\prev_wr_go$next[4:0]$14765 - attribute \src "libresoc.v:203638.3-203639.37" + attribute \src "libresoc.v:198547.3-198555.6" + wire width 5 $0\prev_wr_go$next[4:0]$14536 + attribute \src "libresoc.v:198126.3-198127.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:203723.3-203732.6" + attribute \src "libresoc.v:198211.3-198220.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:203814.3-203822.6" - wire width 5 $0\req_l_r_req$next[4:0]$14680 - attribute \src "libresoc.v:203618.3-203619.39" + attribute \src "libresoc.v:198302.3-198310.6" + wire width 5 $0\req_l_r_req$next[4:0]$14451 + attribute \src "libresoc.v:198106.3-198107.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:203805.3-203813.6" - wire width 5 $0\req_l_s_req$next[4:0]$14677 - attribute \src "libresoc.v:203620.3-203621.39" + attribute \src "libresoc.v:198293.3-198301.6" + wire width 5 $0\req_l_s_req$next[4:0]$14448 + attribute \src "libresoc.v:198108.3-198109.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:203742.3-203750.6" - wire $0\rok_l_r_rdok$next[0:0]$14656 - attribute \src "libresoc.v:203634.3-203635.41" + attribute \src "libresoc.v:198230.3-198238.6" + wire $0\rok_l_r_rdok$next[0:0]$14427 + attribute \src "libresoc.v:198122.3-198123.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:203733.3-203741.6" - wire $0\rok_l_s_rdok$next[0:0]$14653 - attribute \src "libresoc.v:203636.3-203637.41" + attribute \src "libresoc.v:198221.3-198229.6" + wire $0\rok_l_s_rdok$next[0:0]$14424 + attribute \src "libresoc.v:198124.3-198125.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:203760.3-203768.6" - wire $0\rst_l_r_rst$next[0:0]$14662 - attribute \src "libresoc.v:203630.3-203631.39" + attribute \src "libresoc.v:198248.3-198256.6" + wire $0\rst_l_r_rst$next[0:0]$14433 + attribute \src "libresoc.v:198118.3-198119.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:203751.3-203759.6" - wire $0\rst_l_s_rst$next[0:0]$14659 - attribute \src "libresoc.v:203632.3-203633.39" + attribute \src "libresoc.v:198239.3-198247.6" + wire $0\rst_l_s_rst$next[0:0]$14430 + attribute \src "libresoc.v:198120.3-198121.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:203796.3-203804.6" - wire width 4 $0\src_l_r_src$next[3:0]$14674 - attribute \src "libresoc.v:203622.3-203623.39" + attribute \src "libresoc.v:198284.3-198292.6" + wire width 4 $0\src_l_r_src$next[3:0]$14445 + attribute \src "libresoc.v:198110.3-198111.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:203787.3-203795.6" - wire width 4 $0\src_l_s_src$next[3:0]$14671 - attribute \src "libresoc.v:203624.3-203625.39" + attribute \src "libresoc.v:198275.3-198283.6" + wire width 4 $0\src_l_s_src$next[3:0]$14442 + attribute \src "libresoc.v:198112.3-198113.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:203951.3-203960.6" - wire width 64 $0\src_r0$next[63:0]$14742 - attribute \src "libresoc.v:203578.3-203579.29" + attribute \src "libresoc.v:198439.3-198448.6" + wire width 64 $0\src_r0$next[63:0]$14513 + attribute \src "libresoc.v:198066.3-198067.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:203961.3-203970.6" - wire width 64 $0\src_r1$next[63:0]$14745 - attribute \src "libresoc.v:203576.3-203577.29" + attribute \src "libresoc.v:198449.3-198458.6" + wire width 64 $0\src_r1$next[63:0]$14516 + attribute \src "libresoc.v:198064.3-198065.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:203971.3-203980.6" - wire width 64 $0\src_r2$next[63:0]$14748 - attribute \src "libresoc.v:203574.3-203575.29" + attribute \src "libresoc.v:198459.3-198468.6" + wire width 64 $0\src_r2$next[63:0]$14519 + attribute \src "libresoc.v:198062.3-198063.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:203981.3-203990.6" - wire width 64 $0\src_r3$next[63:0]$14751 - attribute \src "libresoc.v:203572.3-203573.29" + attribute \src "libresoc.v:198469.3-198478.6" + wire width 64 $0\src_r3$next[63:0]$14522 + attribute \src "libresoc.v:198060.3-198061.29" wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:203037.7-203037.24" + attribute \src "libresoc.v:197525.7-197525.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:203047.7-203047.26" + attribute \src "libresoc.v:197535.7-197535.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:204000.3-204008.6" - wire $1\alu_l_r_alu$next[0:0]$14758 - attribute \src "libresoc.v:203055.7-203055.25" + attribute \src "libresoc.v:198488.3-198496.6" + wire $1\alu_l_r_alu$next[0:0]$14529 + attribute \src "libresoc.v:197543.7-197543.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14692 - attribute \src "libresoc.v:203091.14-203091.59" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14463 + attribute \src "libresoc.v:197579.14-197579.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 13 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14693 - attribute \src "libresoc.v:203109.14-203109.51" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 13 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14464 + attribute \src "libresoc.v:197597.14-197597.51" wire width 13 $1\alu_trap0_trap_op__fn_unit[12:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14694 - attribute \src "libresoc.v:203113.14-203113.45" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14465 + attribute \src "libresoc.v:197601.14-197601.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14695 - attribute \src "libresoc.v:203191.13-203191.49" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14466 + attribute \src "libresoc.v:197679.13-197679.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14696 - attribute \src "libresoc.v:203195.7-203195.41" + attribute \src "libresoc.v:198311.3-198328.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14467 + attribute \src "libresoc.v:197683.7-197683.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14697 - attribute \src "libresoc.v:203199.13-203199.48" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14468 + attribute \src "libresoc.v:197687.13-197687.48" wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14698 - attribute \src "libresoc.v:203203.14-203203.59" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14469 + attribute \src "libresoc.v:197691.14-197691.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14699 - attribute \src "libresoc.v:203207.14-203207.52" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14470 + attribute \src "libresoc.v:197695.14-197695.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:203823.3-203840.6" - wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14700 - attribute \src "libresoc.v:203211.13-203211.48" + attribute \src "libresoc.v:198311.3-198328.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14471 + attribute \src "libresoc.v:197699.13-197699.48" wire width 8 $1\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:203991.3-203999.6" - wire $1\alui_l_r_alui$next[0:0]$14755 - attribute \src "libresoc.v:203217.7-203217.27" + attribute \src "libresoc.v:198479.3-198487.6" + wire $1\alui_l_r_alui$next[0:0]$14526 + attribute \src "libresoc.v:197705.7-197705.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:203841.3-203862.6" - wire width 64 $1\data_r0__o$next[63:0]$14704 - attribute \src "libresoc.v:203249.14-203249.47" + attribute \src "libresoc.v:198329.3-198350.6" + wire width 64 $1\data_r0__o$next[63:0]$14475 + attribute \src "libresoc.v:197737.14-197737.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:203841.3-203862.6" - wire $1\data_r0__o_ok$next[0:0]$14705 - attribute \src "libresoc.v:203253.7-203253.27" + attribute \src "libresoc.v:198329.3-198350.6" + wire $1\data_r0__o_ok$next[0:0]$14476 + attribute \src "libresoc.v:197741.7-197741.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:203863.3-203884.6" - wire width 64 $1\data_r1__fast1$next[63:0]$14712 - attribute \src "libresoc.v:203257.14-203257.51" + attribute \src "libresoc.v:198351.3-198372.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14483 + attribute \src "libresoc.v:197745.14-197745.51" wire width 64 $1\data_r1__fast1[63:0] - attribute \src "libresoc.v:203863.3-203884.6" - wire $1\data_r1__fast1_ok$next[0:0]$14713 - attribute \src "libresoc.v:203261.7-203261.31" + attribute \src "libresoc.v:198351.3-198372.6" + wire $1\data_r1__fast1_ok$next[0:0]$14484 + attribute \src "libresoc.v:197749.7-197749.31" wire $1\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:203885.3-203906.6" - wire width 64 $1\data_r2__fast2$next[63:0]$14720 - attribute \src "libresoc.v:203265.14-203265.51" + attribute \src "libresoc.v:198373.3-198394.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14491 + attribute \src "libresoc.v:197753.14-197753.51" wire width 64 $1\data_r2__fast2[63:0] - attribute \src "libresoc.v:203885.3-203906.6" - wire $1\data_r2__fast2_ok$next[0:0]$14721 - attribute \src "libresoc.v:203269.7-203269.31" + attribute \src "libresoc.v:198373.3-198394.6" + wire $1\data_r2__fast2_ok$next[0:0]$14492 + attribute \src "libresoc.v:197757.7-197757.31" wire $1\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:203907.3-203928.6" - wire width 64 $1\data_r3__nia$next[63:0]$14728 - attribute \src "libresoc.v:203273.14-203273.49" + attribute \src "libresoc.v:198395.3-198416.6" + wire width 64 $1\data_r3__nia$next[63:0]$14499 + attribute \src "libresoc.v:197761.14-197761.49" wire width 64 $1\data_r3__nia[63:0] - attribute \src "libresoc.v:203907.3-203928.6" - wire $1\data_r3__nia_ok$next[0:0]$14729 - attribute \src "libresoc.v:203277.7-203277.29" + attribute \src "libresoc.v:198395.3-198416.6" + wire $1\data_r3__nia_ok$next[0:0]$14500 + attribute \src "libresoc.v:197765.7-197765.29" wire $1\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:203929.3-203950.6" - wire width 64 $1\data_r4__msr$next[63:0]$14736 - attribute \src "libresoc.v:203281.14-203281.49" + attribute \src "libresoc.v:198417.3-198438.6" + wire width 64 $1\data_r4__msr$next[63:0]$14507 + attribute \src "libresoc.v:197769.14-197769.49" wire width 64 $1\data_r4__msr[63:0] - attribute \src "libresoc.v:203929.3-203950.6" - wire $1\data_r4__msr_ok$next[0:0]$14737 - attribute \src "libresoc.v:203285.7-203285.29" + attribute \src "libresoc.v:198417.3-198438.6" + wire $1\data_r4__msr_ok$next[0:0]$14508 + attribute \src "libresoc.v:197773.7-197773.29" wire $1\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:204009.3-204018.6" + attribute \src "libresoc.v:198497.3-198506.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:204019.3-204028.6" + attribute \src "libresoc.v:198507.3-198516.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:204029.3-204038.6" + attribute \src "libresoc.v:198517.3-198526.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:204039.3-204048.6" + attribute \src "libresoc.v:198527.3-198536.6" wire width 64 $1\dest4_o[63:0] - attribute \src "libresoc.v:204049.3-204058.6" + attribute \src "libresoc.v:198537.3-198546.6" wire width 64 $1\dest5_o[63:0] - attribute \src "libresoc.v:203778.3-203786.6" - wire $1\opc_l_r_opc$next[0:0]$14669 - attribute \src "libresoc.v:203316.7-203316.25" + attribute \src "libresoc.v:198266.3-198274.6" + wire $1\opc_l_r_opc$next[0:0]$14440 + attribute \src "libresoc.v:197804.7-197804.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:203769.3-203777.6" - wire $1\opc_l_s_opc$next[0:0]$14666 - attribute \src "libresoc.v:203320.7-203320.25" + attribute \src "libresoc.v:198257.3-198265.6" + wire $1\opc_l_s_opc$next[0:0]$14437 + attribute \src "libresoc.v:197808.7-197808.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:204059.3-204067.6" - wire width 5 $1\prev_wr_go$next[4:0]$14766 - attribute \src "libresoc.v:203430.13-203430.31" + attribute \src "libresoc.v:198547.3-198555.6" + wire width 5 $1\prev_wr_go$next[4:0]$14537 + attribute \src "libresoc.v:197918.13-197918.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:203723.3-203732.6" + attribute \src "libresoc.v:198211.3-198220.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:203814.3-203822.6" - wire width 5 $1\req_l_r_req$next[4:0]$14681 - attribute \src "libresoc.v:203438.13-203438.32" + attribute \src "libresoc.v:198302.3-198310.6" + wire width 5 $1\req_l_r_req$next[4:0]$14452 + attribute \src "libresoc.v:197926.13-197926.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:203805.3-203813.6" - wire width 5 $1\req_l_s_req$next[4:0]$14678 - attribute \src "libresoc.v:203442.13-203442.32" + attribute \src "libresoc.v:198293.3-198301.6" + wire width 5 $1\req_l_s_req$next[4:0]$14449 + attribute \src "libresoc.v:197930.13-197930.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:203742.3-203750.6" - wire $1\rok_l_r_rdok$next[0:0]$14657 - attribute \src "libresoc.v:203454.7-203454.26" + attribute \src "libresoc.v:198230.3-198238.6" + wire $1\rok_l_r_rdok$next[0:0]$14428 + attribute \src "libresoc.v:197942.7-197942.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:203733.3-203741.6" - wire $1\rok_l_s_rdok$next[0:0]$14654 - attribute \src "libresoc.v:203458.7-203458.26" + attribute \src "libresoc.v:198221.3-198229.6" + wire $1\rok_l_s_rdok$next[0:0]$14425 + attribute \src "libresoc.v:197946.7-197946.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:203760.3-203768.6" - wire $1\rst_l_r_rst$next[0:0]$14663 - attribute \src "libresoc.v:203462.7-203462.25" + attribute \src "libresoc.v:198248.3-198256.6" + wire $1\rst_l_r_rst$next[0:0]$14434 + attribute \src "libresoc.v:197950.7-197950.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:203751.3-203759.6" - wire $1\rst_l_s_rst$next[0:0]$14660 - attribute \src "libresoc.v:203466.7-203466.25" + attribute \src "libresoc.v:198239.3-198247.6" + wire $1\rst_l_s_rst$next[0:0]$14431 + attribute \src "libresoc.v:197954.7-197954.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:203796.3-203804.6" - wire width 4 $1\src_l_r_src$next[3:0]$14675 - attribute \src "libresoc.v:203482.13-203482.31" + attribute \src "libresoc.v:198284.3-198292.6" + wire width 4 $1\src_l_r_src$next[3:0]$14446 + attribute \src "libresoc.v:197970.13-197970.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:203787.3-203795.6" - wire width 4 $1\src_l_s_src$next[3:0]$14672 - attribute \src "libresoc.v:203486.13-203486.31" + attribute \src "libresoc.v:198275.3-198283.6" + wire width 4 $1\src_l_s_src$next[3:0]$14443 + attribute \src "libresoc.v:197974.13-197974.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:203951.3-203960.6" - wire width 64 $1\src_r0$next[63:0]$14743 - attribute \src "libresoc.v:203490.14-203490.43" + attribute \src "libresoc.v:198439.3-198448.6" + wire width 64 $1\src_r0$next[63:0]$14514 + attribute \src "libresoc.v:197978.14-197978.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:203961.3-203970.6" - wire width 64 $1\src_r1$next[63:0]$14746 - attribute \src "libresoc.v:203494.14-203494.43" + attribute \src "libresoc.v:198449.3-198458.6" + wire width 64 $1\src_r1$next[63:0]$14517 + attribute \src "libresoc.v:197982.14-197982.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:203971.3-203980.6" - wire width 64 $1\src_r2$next[63:0]$14749 - attribute \src "libresoc.v:203498.14-203498.43" + attribute \src "libresoc.v:198459.3-198468.6" + wire width 64 $1\src_r2$next[63:0]$14520 + attribute \src "libresoc.v:197986.14-197986.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:203981.3-203990.6" - wire width 64 $1\src_r3$next[63:0]$14752 - attribute \src "libresoc.v:203502.14-203502.43" + attribute \src "libresoc.v:198469.3-198478.6" + wire width 64 $1\src_r3$next[63:0]$14523 + attribute \src "libresoc.v:197990.14-197990.43" wire width 64 $1\src_r3[63:0] - attribute \src "libresoc.v:203841.3-203862.6" - wire width 64 $2\data_r0__o$next[63:0]$14706 - attribute \src "libresoc.v:203841.3-203862.6" - wire $2\data_r0__o_ok$next[0:0]$14707 - attribute \src "libresoc.v:203863.3-203884.6" - wire width 64 $2\data_r1__fast1$next[63:0]$14714 - attribute \src "libresoc.v:203863.3-203884.6" - wire $2\data_r1__fast1_ok$next[0:0]$14715 - attribute \src "libresoc.v:203885.3-203906.6" - wire width 64 $2\data_r2__fast2$next[63:0]$14722 - attribute \src "libresoc.v:203885.3-203906.6" - wire $2\data_r2__fast2_ok$next[0:0]$14723 - attribute \src "libresoc.v:203907.3-203928.6" - wire width 64 $2\data_r3__nia$next[63:0]$14730 - attribute \src "libresoc.v:203907.3-203928.6" - wire $2\data_r3__nia_ok$next[0:0]$14731 - attribute \src "libresoc.v:203929.3-203950.6" - wire width 64 $2\data_r4__msr$next[63:0]$14738 - attribute \src "libresoc.v:203929.3-203950.6" - wire $2\data_r4__msr_ok$next[0:0]$14739 - attribute \src "libresoc.v:203841.3-203862.6" - wire $3\data_r0__o_ok$next[0:0]$14708 - attribute \src "libresoc.v:203863.3-203884.6" - wire $3\data_r1__fast1_ok$next[0:0]$14716 - attribute \src "libresoc.v:203885.3-203906.6" - wire $3\data_r2__fast2_ok$next[0:0]$14724 - attribute \src "libresoc.v:203907.3-203928.6" - wire $3\data_r3__nia_ok$next[0:0]$14732 - attribute \src "libresoc.v:203929.3-203950.6" - wire $3\data_r4__msr_ok$next[0:0]$14740 - attribute \src "libresoc.v:203508.18-203508.112" - wire width 4 $and$libresoc.v:203508$14553_Y - attribute \src "libresoc.v:203509.19-203509.125" - wire $and$libresoc.v:203509$14554_Y - attribute \src "libresoc.v:203510.19-203510.125" - wire $and$libresoc.v:203510$14555_Y - attribute \src "libresoc.v:203511.19-203511.125" - wire $and$libresoc.v:203511$14556_Y - attribute \src "libresoc.v:203512.19-203512.125" - wire $and$libresoc.v:203512$14557_Y - attribute \src "libresoc.v:203513.19-203513.125" - wire $and$libresoc.v:203513$14558_Y - attribute \src "libresoc.v:203514.19-203514.157" - wire width 5 $and$libresoc.v:203514$14559_Y - attribute \src "libresoc.v:203515.19-203515.121" - wire width 5 $and$libresoc.v:203515$14560_Y - attribute \src "libresoc.v:203516.19-203516.127" - wire $and$libresoc.v:203516$14561_Y - attribute \src "libresoc.v:203517.19-203517.127" - wire $and$libresoc.v:203517$14562_Y - attribute \src "libresoc.v:203518.18-203518.110" - wire $and$libresoc.v:203518$14563_Y - attribute \src "libresoc.v:203519.19-203519.127" - wire $and$libresoc.v:203519$14564_Y - attribute \src "libresoc.v:203520.19-203520.127" - wire $and$libresoc.v:203520$14565_Y - attribute \src "libresoc.v:203521.19-203521.127" - wire $and$libresoc.v:203521$14566_Y - attribute \src "libresoc.v:203523.18-203523.98" - wire $and$libresoc.v:203523$14568_Y - attribute \src "libresoc.v:203525.18-203525.100" - wire $and$libresoc.v:203525$14570_Y - attribute \src "libresoc.v:203526.18-203526.171" - wire width 5 $and$libresoc.v:203526$14571_Y - attribute \src "libresoc.v:203528.18-203528.119" - wire width 5 $and$libresoc.v:203528$14573_Y - attribute \src "libresoc.v:203531.18-203531.116" - wire $and$libresoc.v:203531$14576_Y - attribute \src "libresoc.v:203535.17-203535.123" - wire $and$libresoc.v:203535$14580_Y - attribute \src "libresoc.v:203537.18-203537.113" - wire $and$libresoc.v:203537$14582_Y - attribute \src "libresoc.v:203538.18-203538.125" - wire width 5 $and$libresoc.v:203538$14583_Y - attribute \src "libresoc.v:203540.18-203540.112" - wire $and$libresoc.v:203540$14585_Y - attribute \src "libresoc.v:203542.18-203542.127" - wire $and$libresoc.v:203542$14587_Y - attribute \src "libresoc.v:203543.18-203543.127" - wire $and$libresoc.v:203543$14588_Y - attribute \src "libresoc.v:203544.18-203544.117" - wire $and$libresoc.v:203544$14589_Y - attribute \src "libresoc.v:203549.18-203549.131" - wire $and$libresoc.v:203549$14594_Y - attribute \src "libresoc.v:203550.18-203550.124" - wire width 5 $and$libresoc.v:203550$14595_Y - attribute \src "libresoc.v:203553.18-203553.116" - wire $and$libresoc.v:203553$14598_Y - attribute \src "libresoc.v:203554.18-203554.120" - wire $and$libresoc.v:203554$14599_Y - attribute \src "libresoc.v:203555.18-203555.120" - wire $and$libresoc.v:203555$14600_Y - attribute \src "libresoc.v:203556.18-203556.118" - wire $and$libresoc.v:203556$14601_Y - attribute \src "libresoc.v:203557.18-203557.118" - wire $and$libresoc.v:203557$14602_Y - attribute \src "libresoc.v:203563.18-203563.135" - wire $and$libresoc.v:203563$14608_Y - attribute \src "libresoc.v:203564.18-203564.133" - wire $and$libresoc.v:203564$14609_Y - attribute \src "libresoc.v:203565.18-203565.160" - wire width 4 $and$libresoc.v:203565$14610_Y - attribute \src "libresoc.v:203566.18-203566.112" - wire width 4 $and$libresoc.v:203566$14611_Y - attribute \src "libresoc.v:203539.18-203539.113" - wire $eq$libresoc.v:203539$14584_Y - attribute \src "libresoc.v:203541.18-203541.119" - wire $eq$libresoc.v:203541$14586_Y - attribute \src "libresoc.v:203522.18-203522.97" - wire $not$libresoc.v:203522$14567_Y - attribute \src "libresoc.v:203524.18-203524.99" - wire $not$libresoc.v:203524$14569_Y - attribute \src "libresoc.v:203527.18-203527.113" - wire width 5 $not$libresoc.v:203527$14572_Y - attribute \src "libresoc.v:203530.18-203530.106" - wire $not$libresoc.v:203530$14575_Y - attribute \src "libresoc.v:203536.18-203536.121" - wire $not$libresoc.v:203536$14581_Y - attribute \src "libresoc.v:203551.17-203551.113" - wire width 4 $not$libresoc.v:203551$14596_Y - attribute \src "libresoc.v:203567.18-203567.114" - wire width 4 $not$libresoc.v:203567$14612_Y - attribute \src "libresoc.v:203534.18-203534.112" - wire $or$libresoc.v:203534$14579_Y - attribute \src "libresoc.v:203545.18-203545.122" - wire $or$libresoc.v:203545$14590_Y - attribute \src "libresoc.v:203546.18-203546.124" - wire $or$libresoc.v:203546$14591_Y - attribute \src "libresoc.v:203547.18-203547.181" - wire width 5 $or$libresoc.v:203547$14592_Y - attribute \src "libresoc.v:203548.18-203548.168" - wire width 4 $or$libresoc.v:203548$14593_Y - attribute \src "libresoc.v:203552.18-203552.120" - wire width 5 $or$libresoc.v:203552$14597_Y - attribute \src "libresoc.v:203562.17-203562.117" - wire width 4 $or$libresoc.v:203562$14607_Y - attribute \src "libresoc.v:203507.17-203507.104" - wire $reduce_and$libresoc.v:203507$14552_Y - attribute \src "libresoc.v:203529.18-203529.106" - wire $reduce_or$libresoc.v:203529$14574_Y - attribute \src "libresoc.v:203532.18-203532.113" - wire $reduce_or$libresoc.v:203532$14577_Y - attribute \src "libresoc.v:203533.18-203533.112" - wire $reduce_or$libresoc.v:203533$14578_Y - attribute \src "libresoc.v:203558.18-203558.118" - wire width 64 $ternary$libresoc.v:203558$14603_Y - attribute \src "libresoc.v:203559.18-203559.118" - wire width 64 $ternary$libresoc.v:203559$14604_Y - attribute \src "libresoc.v:203560.18-203560.118" - wire width 64 $ternary$libresoc.v:203560$14605_Y - attribute \src "libresoc.v:203561.18-203561.118" - wire width 64 $ternary$libresoc.v:203561$14606_Y + attribute \src "libresoc.v:198329.3-198350.6" + wire width 64 $2\data_r0__o$next[63:0]$14477 + attribute \src "libresoc.v:198329.3-198350.6" + wire $2\data_r0__o_ok$next[0:0]$14478 + attribute \src "libresoc.v:198351.3-198372.6" + wire width 64 $2\data_r1__fast1$next[63:0]$14485 + attribute \src "libresoc.v:198351.3-198372.6" + wire $2\data_r1__fast1_ok$next[0:0]$14486 + attribute \src "libresoc.v:198373.3-198394.6" + wire width 64 $2\data_r2__fast2$next[63:0]$14493 + attribute \src "libresoc.v:198373.3-198394.6" + wire $2\data_r2__fast2_ok$next[0:0]$14494 + attribute \src "libresoc.v:198395.3-198416.6" + wire width 64 $2\data_r3__nia$next[63:0]$14501 + attribute \src "libresoc.v:198395.3-198416.6" + wire $2\data_r3__nia_ok$next[0:0]$14502 + attribute \src "libresoc.v:198417.3-198438.6" + wire width 64 $2\data_r4__msr$next[63:0]$14509 + attribute \src "libresoc.v:198417.3-198438.6" + wire $2\data_r4__msr_ok$next[0:0]$14510 + attribute \src "libresoc.v:198329.3-198350.6" + wire $3\data_r0__o_ok$next[0:0]$14479 + attribute \src "libresoc.v:198351.3-198372.6" + wire $3\data_r1__fast1_ok$next[0:0]$14487 + attribute \src "libresoc.v:198373.3-198394.6" + wire $3\data_r2__fast2_ok$next[0:0]$14495 + attribute \src "libresoc.v:198395.3-198416.6" + wire $3\data_r3__nia_ok$next[0:0]$14503 + attribute \src "libresoc.v:198417.3-198438.6" + wire $3\data_r4__msr_ok$next[0:0]$14511 + attribute \src "libresoc.v:197996.18-197996.112" + wire width 4 $and$libresoc.v:197996$14324_Y + attribute \src "libresoc.v:197997.19-197997.125" + wire $and$libresoc.v:197997$14325_Y + attribute \src "libresoc.v:197998.19-197998.125" + wire $and$libresoc.v:197998$14326_Y + attribute \src "libresoc.v:197999.19-197999.125" + wire $and$libresoc.v:197999$14327_Y + attribute \src "libresoc.v:198000.19-198000.125" + wire $and$libresoc.v:198000$14328_Y + attribute \src "libresoc.v:198001.19-198001.125" + wire $and$libresoc.v:198001$14329_Y + attribute \src "libresoc.v:198002.19-198002.157" + wire width 5 $and$libresoc.v:198002$14330_Y + attribute \src "libresoc.v:198003.19-198003.121" + wire width 5 $and$libresoc.v:198003$14331_Y + attribute \src "libresoc.v:198004.19-198004.127" + wire $and$libresoc.v:198004$14332_Y + attribute \src "libresoc.v:198005.19-198005.127" + wire $and$libresoc.v:198005$14333_Y + attribute \src "libresoc.v:198006.18-198006.110" + wire $and$libresoc.v:198006$14334_Y + attribute \src "libresoc.v:198007.19-198007.127" + wire $and$libresoc.v:198007$14335_Y + attribute \src "libresoc.v:198008.19-198008.127" + wire $and$libresoc.v:198008$14336_Y + attribute \src "libresoc.v:198009.19-198009.127" + wire $and$libresoc.v:198009$14337_Y + attribute \src "libresoc.v:198011.18-198011.98" + wire $and$libresoc.v:198011$14339_Y + attribute \src "libresoc.v:198013.18-198013.100" + wire $and$libresoc.v:198013$14341_Y + attribute \src "libresoc.v:198014.18-198014.171" + wire width 5 $and$libresoc.v:198014$14342_Y + attribute \src "libresoc.v:198016.18-198016.119" + wire width 5 $and$libresoc.v:198016$14344_Y + attribute \src "libresoc.v:198019.18-198019.116" + wire $and$libresoc.v:198019$14347_Y + attribute \src "libresoc.v:198023.17-198023.123" + wire $and$libresoc.v:198023$14351_Y + attribute \src "libresoc.v:198025.18-198025.113" + wire $and$libresoc.v:198025$14353_Y + attribute \src "libresoc.v:198026.18-198026.125" + wire width 5 $and$libresoc.v:198026$14354_Y + attribute \src "libresoc.v:198028.18-198028.112" + wire $and$libresoc.v:198028$14356_Y + attribute \src "libresoc.v:198030.18-198030.127" + wire $and$libresoc.v:198030$14358_Y + attribute \src "libresoc.v:198031.18-198031.127" + wire $and$libresoc.v:198031$14359_Y + attribute \src "libresoc.v:198032.18-198032.117" + wire $and$libresoc.v:198032$14360_Y + attribute \src "libresoc.v:198037.18-198037.131" + wire $and$libresoc.v:198037$14365_Y + attribute \src "libresoc.v:198038.18-198038.124" + wire width 5 $and$libresoc.v:198038$14366_Y + attribute \src "libresoc.v:198041.18-198041.116" + wire $and$libresoc.v:198041$14369_Y + attribute \src "libresoc.v:198042.18-198042.120" + wire $and$libresoc.v:198042$14370_Y + attribute \src "libresoc.v:198043.18-198043.120" + wire $and$libresoc.v:198043$14371_Y + attribute \src "libresoc.v:198044.18-198044.118" + wire $and$libresoc.v:198044$14372_Y + attribute \src "libresoc.v:198045.18-198045.118" + wire $and$libresoc.v:198045$14373_Y + attribute \src "libresoc.v:198051.18-198051.135" + wire $and$libresoc.v:198051$14379_Y + attribute \src "libresoc.v:198052.18-198052.133" + wire $and$libresoc.v:198052$14380_Y + attribute \src "libresoc.v:198053.18-198053.160" + wire width 4 $and$libresoc.v:198053$14381_Y + attribute \src "libresoc.v:198054.18-198054.112" + wire width 4 $and$libresoc.v:198054$14382_Y + attribute \src "libresoc.v:198027.18-198027.113" + wire $eq$libresoc.v:198027$14355_Y + attribute \src "libresoc.v:198029.18-198029.119" + wire $eq$libresoc.v:198029$14357_Y + attribute \src "libresoc.v:198010.18-198010.97" + wire $not$libresoc.v:198010$14338_Y + attribute \src "libresoc.v:198012.18-198012.99" + wire $not$libresoc.v:198012$14340_Y + attribute \src "libresoc.v:198015.18-198015.113" + wire width 5 $not$libresoc.v:198015$14343_Y + attribute \src "libresoc.v:198018.18-198018.106" + wire $not$libresoc.v:198018$14346_Y + attribute \src "libresoc.v:198024.18-198024.121" + wire $not$libresoc.v:198024$14352_Y + attribute \src "libresoc.v:198039.17-198039.113" + wire width 4 $not$libresoc.v:198039$14367_Y + attribute \src "libresoc.v:198055.18-198055.114" + wire width 4 $not$libresoc.v:198055$14383_Y + attribute \src "libresoc.v:198022.18-198022.112" + wire $or$libresoc.v:198022$14350_Y + attribute \src "libresoc.v:198033.18-198033.122" + wire $or$libresoc.v:198033$14361_Y + attribute \src "libresoc.v:198034.18-198034.124" + wire $or$libresoc.v:198034$14362_Y + attribute \src "libresoc.v:198035.18-198035.181" + wire width 5 $or$libresoc.v:198035$14363_Y + attribute \src "libresoc.v:198036.18-198036.168" + wire width 4 $or$libresoc.v:198036$14364_Y + attribute \src "libresoc.v:198040.18-198040.120" + wire width 5 $or$libresoc.v:198040$14368_Y + attribute \src "libresoc.v:198050.17-198050.117" + wire width 4 $or$libresoc.v:198050$14378_Y + attribute \src "libresoc.v:197995.17-197995.104" + wire $reduce_and$libresoc.v:197995$14323_Y + attribute \src "libresoc.v:198017.18-198017.106" + wire $reduce_or$libresoc.v:198017$14345_Y + attribute \src "libresoc.v:198020.18-198020.113" + wire $reduce_or$libresoc.v:198020$14348_Y + attribute \src "libresoc.v:198021.18-198021.112" + wire $reduce_or$libresoc.v:198021$14349_Y + attribute \src "libresoc.v:198046.18-198046.118" + wire width 64 $ternary$libresoc.v:198046$14374_Y + attribute \src "libresoc.v:198047.18-198047.118" + wire width 64 $ternary$libresoc.v:198047$14375_Y + attribute \src "libresoc.v:198048.18-198048.118" + wire width 64 $ternary$libresoc.v:198048$14376_Y + attribute \src "libresoc.v:198049.18-198049.118" + wire width 64 $ternary$libresoc.v:198049$14377_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -422637,9 +413940,9 @@ module \trap0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 12 \cu_busy_o @@ -422717,7 +414020,7 @@ module \trap0 wire output 24 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \fast2_ok - attribute \src "libresoc.v:202911.7-202911.15" + attribute \src "libresoc.v:197399.7-197399.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \msr_ok @@ -422920,7 +414223,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:203508$14553 + cell $and $and$libresoc.v:197996$14324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -422928,10 +414231,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:203508$14553_Y + connect \Y $and$libresoc.v:197996$14324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:203509$14554 + cell $and $and$libresoc.v:197997$14325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422939,10 +414242,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:203509$14554_Y + connect \Y $and$libresoc.v:197997$14325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:203510$14555 + cell $and $and$libresoc.v:197998$14326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422950,10 +414253,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:203510$14555_Y + connect \Y $and$libresoc.v:197998$14326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:203511$14556 + cell $and $and$libresoc.v:197999$14327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422961,10 +414264,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:203511$14556_Y + connect \Y $and$libresoc.v:197999$14327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:203512$14557 + cell $and $and$libresoc.v:198000$14328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422972,10 +414275,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:203512$14557_Y + connect \Y $and$libresoc.v:198000$14328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:203513$14558 + cell $and $and$libresoc.v:198001$14329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422983,10 +414286,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:203513$14558_Y + connect \Y $and$libresoc.v:198001$14329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:203514$14559 + cell $and $and$libresoc.v:198002$14330 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -422994,10 +414297,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:203514$14559_Y + connect \Y $and$libresoc.v:198002$14330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:203515$14560 + cell $and $and$libresoc.v:198003$14331 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -423005,10 +414308,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:203515$14560_Y + connect \Y $and$libresoc.v:198003$14331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:203516$14561 + cell $and $and$libresoc.v:198004$14332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423016,10 +414319,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:203516$14561_Y + connect \Y $and$libresoc.v:198004$14332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:203517$14562 + cell $and $and$libresoc.v:198005$14333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423027,10 +414330,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:203517$14562_Y + connect \Y $and$libresoc.v:198005$14333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:203518$14563 + cell $and $and$libresoc.v:198006$14334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423038,10 +414341,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:203518$14563_Y + connect \Y $and$libresoc.v:198006$14334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:203519$14564 + cell $and $and$libresoc.v:198007$14335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423049,10 +414352,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:203519$14564_Y + connect \Y $and$libresoc.v:198007$14335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:203520$14565 + cell $and $and$libresoc.v:198008$14336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423060,10 +414363,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:203520$14565_Y + connect \Y $and$libresoc.v:198008$14336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:203521$14566 + cell $and $and$libresoc.v:198009$14337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423071,10 +414374,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:203521$14566_Y + connect \Y $and$libresoc.v:198009$14337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:203523$14568 + cell $and $and$libresoc.v:198011$14339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423082,10 +414385,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:203523$14568_Y + connect \Y $and$libresoc.v:198011$14339_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:203525$14570 + cell $and $and$libresoc.v:198013$14341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423093,10 +414396,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:203525$14570_Y + connect \Y $and$libresoc.v:198013$14341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:203526$14571 + cell $and $and$libresoc.v:198014$14342 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -423104,10 +414407,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:203526$14571_Y + connect \Y $and$libresoc.v:198014$14342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:203528$14573 + cell $and $and$libresoc.v:198016$14344 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -423115,10 +414418,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:203528$14573_Y + connect \Y $and$libresoc.v:198016$14344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:203531$14576 + cell $and $and$libresoc.v:198019$14347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423126,10 +414429,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:203531$14576_Y + connect \Y $and$libresoc.v:198019$14347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:203535$14580 + cell $and $and$libresoc.v:198023$14351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423137,10 +414440,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:203535$14580_Y + connect \Y $and$libresoc.v:198023$14351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:203537$14582 + cell $and $and$libresoc.v:198025$14353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423148,10 +414451,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:203537$14582_Y + connect \Y $and$libresoc.v:198025$14353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:203538$14583 + cell $and $and$libresoc.v:198026$14354 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -423159,10 +414462,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:203538$14583_Y + connect \Y $and$libresoc.v:198026$14354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:203540$14585 + cell $and $and$libresoc.v:198028$14356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423170,10 +414473,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:203540$14585_Y + connect \Y $and$libresoc.v:198028$14356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:203542$14587 + cell $and $and$libresoc.v:198030$14358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423181,10 +414484,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:203542$14587_Y + connect \Y $and$libresoc.v:198030$14358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:203543$14588 + cell $and $and$libresoc.v:198031$14359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423192,10 +414495,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:203543$14588_Y + connect \Y $and$libresoc.v:198031$14359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:203544$14589 + cell $and $and$libresoc.v:198032$14360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423203,10 +414506,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:203544$14589_Y + connect \Y $and$libresoc.v:198032$14360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:203549$14594 + cell $and $and$libresoc.v:198037$14365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423214,10 +414517,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:203549$14594_Y + connect \Y $and$libresoc.v:198037$14365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:203550$14595 + cell $and $and$libresoc.v:198038$14366 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -423225,10 +414528,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:203550$14595_Y + connect \Y $and$libresoc.v:198038$14366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:203553$14598 + cell $and $and$libresoc.v:198041$14369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423236,10 +414539,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:203553$14598_Y + connect \Y $and$libresoc.v:198041$14369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:203554$14599 + cell $and $and$libresoc.v:198042$14370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423247,10 +414550,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:203554$14599_Y + connect \Y $and$libresoc.v:198042$14370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:203555$14600 + cell $and $and$libresoc.v:198043$14371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423258,10 +414561,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:203555$14600_Y + connect \Y $and$libresoc.v:198043$14371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:203556$14601 + cell $and $and$libresoc.v:198044$14372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423269,10 +414572,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:203556$14601_Y + connect \Y $and$libresoc.v:198044$14372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:203557$14602 + cell $and $and$libresoc.v:198045$14373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423280,10 +414583,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:203557$14602_Y + connect \Y $and$libresoc.v:198045$14373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:203563$14608 + cell $and $and$libresoc.v:198051$14379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423291,10 +414594,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:203563$14608_Y + connect \Y $and$libresoc.v:198051$14379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:203564$14609 + cell $and $and$libresoc.v:198052$14380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423302,10 +414605,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:203564$14609_Y + connect \Y $and$libresoc.v:198052$14380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:203565$14610 + cell $and $and$libresoc.v:198053$14381 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -423313,10 +414616,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:203565$14610_Y + connect \Y $and$libresoc.v:198053$14381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:203566$14611 + cell $and $and$libresoc.v:198054$14382 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -423324,10 +414627,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 - connect \Y $and$libresoc.v:203566$14611_Y + connect \Y $and$libresoc.v:198054$14382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:203539$14584 + cell $eq $eq$libresoc.v:198027$14355 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -423335,10 +414638,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:203539$14584_Y + connect \Y $eq$libresoc.v:198027$14355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:203541$14586 + cell $eq $eq$libresoc.v:198029$14357 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -423346,66 +414649,66 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:203541$14586_Y + connect \Y $eq$libresoc.v:198029$14357_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:203522$14567 + cell $not $not$libresoc.v:198010$14338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:203522$14567_Y + connect \Y $not$libresoc.v:198010$14338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:203524$14569 + cell $not $not$libresoc.v:198012$14340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:203524$14569_Y + connect \Y $not$libresoc.v:198012$14340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:203527$14572 + cell $not $not$libresoc.v:198015$14343 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:203527$14572_Y + connect \Y $not$libresoc.v:198015$14343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:203530$14575 + cell $not $not$libresoc.v:198018$14346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:203530$14575_Y + connect \Y $not$libresoc.v:198018$14346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:203536$14581 + cell $not $not$libresoc.v:198024$14352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:203536$14581_Y + connect \Y $not$libresoc.v:198024$14352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:203551$14596 + cell $not $not$libresoc.v:198039$14367 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:203551$14596_Y + connect \Y $not$libresoc.v:198039$14367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:203567$14612 + cell $not $not$libresoc.v:198055$14383 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:203567$14612_Y + connect \Y $not$libresoc.v:198055$14383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:203534$14579 + cell $or $or$libresoc.v:198022$14350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423413,10 +414716,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:203534$14579_Y + connect \Y $or$libresoc.v:198022$14350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:203545$14590 + cell $or $or$libresoc.v:198033$14361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423424,10 +414727,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:203545$14590_Y + connect \Y $or$libresoc.v:198033$14361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:203546$14591 + cell $or $or$libresoc.v:198034$14362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -423435,10 +414738,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:203546$14591_Y + connect \Y $or$libresoc.v:198034$14362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:203547$14592 + cell $or $or$libresoc.v:198035$14363 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -423446,10 +414749,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:203547$14592_Y + connect \Y $or$libresoc.v:198035$14363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:203548$14593 + cell $or $or$libresoc.v:198036$14364 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -423457,10 +414760,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:203548$14593_Y + connect \Y $or$libresoc.v:198036$14364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:203552$14597 + cell $or $or$libresoc.v:198040$14368 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -423468,10 +414771,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:203552$14597_Y + connect \Y $or$libresoc.v:198040$14368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:203562$14607 + cell $or $or$libresoc.v:198050$14378 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -423479,74 +414782,74 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:203562$14607_Y + connect \Y $or$libresoc.v:198050$14378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:203507$14552 + cell $reduce_and $reduce_and$libresoc.v:197995$14323 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:203507$14552_Y + connect \Y $reduce_and$libresoc.v:197995$14323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:203529$14574 + cell $reduce_or $reduce_or$libresoc.v:198017$14345 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:203529$14574_Y + connect \Y $reduce_or$libresoc.v:198017$14345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:203532$14577 + cell $reduce_or $reduce_or$libresoc.v:198020$14348 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:203532$14577_Y + connect \Y $reduce_or$libresoc.v:198020$14348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:203533$14578 + cell $reduce_or $reduce_or$libresoc.v:198021$14349 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:203533$14578_Y + connect \Y $reduce_or$libresoc.v:198021$14349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:203558$14603 + cell $mux $ternary$libresoc.v:198046$14374 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:203558$14603_Y + connect \Y $ternary$libresoc.v:198046$14374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:203559$14604 + cell $mux $ternary$libresoc.v:198047$14375 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:203559$14604_Y + connect \Y $ternary$libresoc.v:198047$14375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:203560$14605 + cell $mux $ternary$libresoc.v:198048$14376 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:203560$14605_Y + connect \Y $ternary$libresoc.v:198048$14376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:203561$14606 + cell $mux $ternary$libresoc.v:198049$14377 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:203561$14606_Y + connect \Y $ternary$libresoc.v:198049$14377_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:203644.14-203650.4" + attribute \src "libresoc.v:198132.14-198138.4" cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -423555,7 +414858,7 @@ module \trap0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:203651.13-203681.4" + attribute \src "libresoc.v:198139.13-198169.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -423588,7 +414891,7 @@ module \trap0 connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 - attribute \src "libresoc.v:203682.15-203688.4" + attribute \src "libresoc.v:198170.15-198176.4" cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -423597,7 +414900,7 @@ module \trap0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:203689.14-203695.4" + attribute \src "libresoc.v:198177.14-198183.4" cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -423606,7 +414909,7 @@ module \trap0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:203696.14-203702.4" + attribute \src "libresoc.v:198184.14-198190.4" cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -423615,7 +414918,7 @@ module \trap0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:203703.14-203709.4" + attribute \src "libresoc.v:198191.14-198197.4" cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -423624,7 +414927,7 @@ module \trap0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:203710.14-203715.4" + attribute \src "libresoc.v:198198.14-198203.4" cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -423632,7 +414935,7 @@ module \trap0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:203716.14-203722.4" + attribute \src "libresoc.v:198204.14-198210.4" cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -423640,592 +414943,592 @@ module \trap0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:202911.7-202911.20" - process $proc$libresoc.v:202911$14767 + attribute \src "libresoc.v:197399.7-197399.20" + process $proc$libresoc.v:197399$14538 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:203037.7-203037.24" - process $proc$libresoc.v:203037$14768 + attribute \src "libresoc.v:197525.7-197525.24" + process $proc$libresoc.v:197525$14539 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:203047.7-203047.26" - process $proc$libresoc.v:203047$14769 + attribute \src "libresoc.v:197535.7-197535.26" + process $proc$libresoc.v:197535$14540 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:203055.7-203055.25" - process $proc$libresoc.v:203055$14770 + attribute \src "libresoc.v:197543.7-197543.25" + process $proc$libresoc.v:197543$14541 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:203091.14-203091.59" - process $proc$libresoc.v:203091$14771 + attribute \src "libresoc.v:197579.14-197579.59" + process $proc$libresoc.v:197579$14542 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:203109.14-203109.51" - process $proc$libresoc.v:203109$14772 + attribute \src "libresoc.v:197597.14-197597.51" + process $proc$libresoc.v:197597$14543 assign { } { } assign $1\alu_trap0_trap_op__fn_unit[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[12:0] end - attribute \src "libresoc.v:203113.14-203113.45" - process $proc$libresoc.v:203113$14773 + attribute \src "libresoc.v:197601.14-197601.45" + process $proc$libresoc.v:197601$14544 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:203191.13-203191.49" - process $proc$libresoc.v:203191$14774 + attribute \src "libresoc.v:197679.13-197679.49" + process $proc$libresoc.v:197679$14545 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:203195.7-203195.41" - process $proc$libresoc.v:203195$14775 + attribute \src "libresoc.v:197683.7-197683.41" + process $proc$libresoc.v:197683$14546 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:203199.13-203199.48" - process $proc$libresoc.v:203199$14776 + attribute \src "libresoc.v:197687.13-197687.48" + process $proc$libresoc.v:197687$14547 assign { } { } assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:203203.14-203203.59" - process $proc$libresoc.v:203203$14777 + attribute \src "libresoc.v:197691.14-197691.59" + process $proc$libresoc.v:197691$14548 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:203207.14-203207.52" - process $proc$libresoc.v:203207$14778 + attribute \src "libresoc.v:197695.14-197695.52" + process $proc$libresoc.v:197695$14549 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:203211.13-203211.48" - process $proc$libresoc.v:203211$14779 + attribute \src "libresoc.v:197699.13-197699.48" + process $proc$libresoc.v:197699$14550 assign { } { } assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:203217.7-203217.27" - process $proc$libresoc.v:203217$14780 + attribute \src "libresoc.v:197705.7-197705.27" + process $proc$libresoc.v:197705$14551 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:203249.14-203249.47" - process $proc$libresoc.v:203249$14781 + attribute \src "libresoc.v:197737.14-197737.47" + process $proc$libresoc.v:197737$14552 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:203253.7-203253.27" - process $proc$libresoc.v:203253$14782 + attribute \src "libresoc.v:197741.7-197741.27" + process $proc$libresoc.v:197741$14553 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:203257.14-203257.51" - process $proc$libresoc.v:203257$14783 + attribute \src "libresoc.v:197745.14-197745.51" + process $proc$libresoc.v:197745$14554 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:203261.7-203261.31" - process $proc$libresoc.v:203261$14784 + attribute \src "libresoc.v:197749.7-197749.31" + process $proc$libresoc.v:197749$14555 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:203265.14-203265.51" - process $proc$libresoc.v:203265$14785 + attribute \src "libresoc.v:197753.14-197753.51" + process $proc$libresoc.v:197753$14556 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:203269.7-203269.31" - process $proc$libresoc.v:203269$14786 + attribute \src "libresoc.v:197757.7-197757.31" + process $proc$libresoc.v:197757$14557 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:203273.14-203273.49" - process $proc$libresoc.v:203273$14787 + attribute \src "libresoc.v:197761.14-197761.49" + process $proc$libresoc.v:197761$14558 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:203277.7-203277.29" - process $proc$libresoc.v:203277$14788 + attribute \src "libresoc.v:197765.7-197765.29" + process $proc$libresoc.v:197765$14559 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:203281.14-203281.49" - process $proc$libresoc.v:203281$14789 + attribute \src "libresoc.v:197769.14-197769.49" + process $proc$libresoc.v:197769$14560 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:203285.7-203285.29" - process $proc$libresoc.v:203285$14790 + attribute \src "libresoc.v:197773.7-197773.29" + process $proc$libresoc.v:197773$14561 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:203316.7-203316.25" - process $proc$libresoc.v:203316$14791 + attribute \src "libresoc.v:197804.7-197804.25" + process $proc$libresoc.v:197804$14562 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:203320.7-203320.25" - process $proc$libresoc.v:203320$14792 + attribute \src "libresoc.v:197808.7-197808.25" + process $proc$libresoc.v:197808$14563 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:203430.13-203430.31" - process $proc$libresoc.v:203430$14793 + attribute \src "libresoc.v:197918.13-197918.31" + process $proc$libresoc.v:197918$14564 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:203438.13-203438.32" - process $proc$libresoc.v:203438$14794 + attribute \src "libresoc.v:197926.13-197926.32" + process $proc$libresoc.v:197926$14565 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:203442.13-203442.32" - process $proc$libresoc.v:203442$14795 + attribute \src "libresoc.v:197930.13-197930.32" + process $proc$libresoc.v:197930$14566 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:203454.7-203454.26" - process $proc$libresoc.v:203454$14796 + attribute \src "libresoc.v:197942.7-197942.26" + process $proc$libresoc.v:197942$14567 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:203458.7-203458.26" - process $proc$libresoc.v:203458$14797 + attribute \src "libresoc.v:197946.7-197946.26" + process $proc$libresoc.v:197946$14568 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:203462.7-203462.25" - process $proc$libresoc.v:203462$14798 + attribute \src "libresoc.v:197950.7-197950.25" + process $proc$libresoc.v:197950$14569 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:203466.7-203466.25" - process $proc$libresoc.v:203466$14799 + attribute \src "libresoc.v:197954.7-197954.25" + process $proc$libresoc.v:197954$14570 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:203482.13-203482.31" - process $proc$libresoc.v:203482$14800 + attribute \src "libresoc.v:197970.13-197970.31" + process $proc$libresoc.v:197970$14571 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:203486.13-203486.31" - process $proc$libresoc.v:203486$14801 + attribute \src "libresoc.v:197974.13-197974.31" + process $proc$libresoc.v:197974$14572 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:203490.14-203490.43" - process $proc$libresoc.v:203490$14802 + attribute \src "libresoc.v:197978.14-197978.43" + process $proc$libresoc.v:197978$14573 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:203494.14-203494.43" - process $proc$libresoc.v:203494$14803 + attribute \src "libresoc.v:197982.14-197982.43" + process $proc$libresoc.v:197982$14574 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:203498.14-203498.43" - process $proc$libresoc.v:203498$14804 + attribute \src "libresoc.v:197986.14-197986.43" + process $proc$libresoc.v:197986$14575 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:203502.14-203502.43" - process $proc$libresoc.v:203502$14805 + attribute \src "libresoc.v:197990.14-197990.43" + process $proc$libresoc.v:197990$14576 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:203568.3-203569.39" - process $proc$libresoc.v:203568$14613 + attribute \src "libresoc.v:198056.3-198057.39" + process $proc$libresoc.v:198056$14384 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:203570.3-203571.43" - process $proc$libresoc.v:203570$14614 + attribute \src "libresoc.v:198058.3-198059.43" + process $proc$libresoc.v:198058$14385 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:203572.3-203573.29" - process $proc$libresoc.v:203572$14615 + attribute \src "libresoc.v:198060.3-198061.29" + process $proc$libresoc.v:198060$14386 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:203574.3-203575.29" - process $proc$libresoc.v:203574$14616 + attribute \src "libresoc.v:198062.3-198063.29" + process $proc$libresoc.v:198062$14387 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:203576.3-203577.29" - process $proc$libresoc.v:203576$14617 + attribute \src "libresoc.v:198064.3-198065.29" + process $proc$libresoc.v:198064$14388 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:203578.3-203579.29" - process $proc$libresoc.v:203578$14618 + attribute \src "libresoc.v:198066.3-198067.29" + process $proc$libresoc.v:198066$14389 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:203580.3-203581.41" - process $proc$libresoc.v:203580$14619 + attribute \src "libresoc.v:198068.3-198069.41" + process $proc$libresoc.v:198068$14390 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:203582.3-203583.47" - process $proc$libresoc.v:203582$14620 + attribute \src "libresoc.v:198070.3-198071.47" + process $proc$libresoc.v:198070$14391 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:203584.3-203585.41" - process $proc$libresoc.v:203584$14621 + attribute \src "libresoc.v:198072.3-198073.41" + process $proc$libresoc.v:198072$14392 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:203586.3-203587.47" - process $proc$libresoc.v:203586$14622 + attribute \src "libresoc.v:198074.3-198075.47" + process $proc$libresoc.v:198074$14393 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:203588.3-203589.45" - process $proc$libresoc.v:203588$14623 + attribute \src "libresoc.v:198076.3-198077.45" + process $proc$libresoc.v:198076$14394 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:203590.3-203591.51" - process $proc$libresoc.v:203590$14624 + attribute \src "libresoc.v:198078.3-198079.51" + process $proc$libresoc.v:198078$14395 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:203592.3-203593.45" - process $proc$libresoc.v:203592$14625 + attribute \src "libresoc.v:198080.3-198081.45" + process $proc$libresoc.v:198080$14396 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:203594.3-203595.51" - process $proc$libresoc.v:203594$14626 + attribute \src "libresoc.v:198082.3-198083.51" + process $proc$libresoc.v:198082$14397 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:203596.3-203597.37" - process $proc$libresoc.v:203596$14627 + attribute \src "libresoc.v:198084.3-198085.37" + process $proc$libresoc.v:198084$14398 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:203598.3-203599.43" - process $proc$libresoc.v:203598$14628 + attribute \src "libresoc.v:198086.3-198087.43" + process $proc$libresoc.v:198086$14399 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:203600.3-203601.73" - process $proc$libresoc.v:203600$14629 + attribute \src "libresoc.v:198088.3-198089.73" + process $proc$libresoc.v:198088$14400 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:203602.3-203603.69" - process $proc$libresoc.v:203602$14630 + attribute \src "libresoc.v:198090.3-198091.69" + process $proc$libresoc.v:198090$14401 assign { } { } assign $0\alu_trap0_trap_op__fn_unit[12:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[12:0] end - attribute \src "libresoc.v:203604.3-203605.63" - process $proc$libresoc.v:203604$14631 + attribute \src "libresoc.v:198092.3-198093.63" + process $proc$libresoc.v:198092$14402 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:203606.3-203607.61" - process $proc$libresoc.v:203606$14632 + attribute \src "libresoc.v:198094.3-198095.61" + process $proc$libresoc.v:198094$14403 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:203608.3-203609.61" - process $proc$libresoc.v:203608$14633 + attribute \src "libresoc.v:198096.3-198097.61" + process $proc$libresoc.v:198096$14404 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:203610.3-203611.71" - process $proc$libresoc.v:203610$14634 + attribute \src "libresoc.v:198098.3-198099.71" + process $proc$libresoc.v:198098$14405 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:203612.3-203613.71" - process $proc$libresoc.v:203612$14635 + attribute \src "libresoc.v:198100.3-198101.71" + process $proc$libresoc.v:198100$14406 assign { } { } assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:203614.3-203615.71" - process $proc$libresoc.v:203614$14636 + attribute \src "libresoc.v:198102.3-198103.71" + process $proc$libresoc.v:198102$14407 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:203616.3-203617.71" - process $proc$libresoc.v:203616$14637 + attribute \src "libresoc.v:198104.3-198105.71" + process $proc$libresoc.v:198104$14408 assign { } { } assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next sync posedge \coresync_clk update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:203618.3-203619.39" - process $proc$libresoc.v:203618$14638 + attribute \src "libresoc.v:198106.3-198107.39" + process $proc$libresoc.v:198106$14409 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:203620.3-203621.39" - process $proc$libresoc.v:203620$14639 + attribute \src "libresoc.v:198108.3-198109.39" + process $proc$libresoc.v:198108$14410 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:203622.3-203623.39" - process $proc$libresoc.v:203622$14640 + attribute \src "libresoc.v:198110.3-198111.39" + process $proc$libresoc.v:198110$14411 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:203624.3-203625.39" - process $proc$libresoc.v:203624$14641 + attribute \src "libresoc.v:198112.3-198113.39" + process $proc$libresoc.v:198112$14412 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:203626.3-203627.39" - process $proc$libresoc.v:203626$14642 + attribute \src "libresoc.v:198114.3-198115.39" + process $proc$libresoc.v:198114$14413 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:203628.3-203629.39" - process $proc$libresoc.v:203628$14643 + attribute \src "libresoc.v:198116.3-198117.39" + process $proc$libresoc.v:198116$14414 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:203630.3-203631.39" - process $proc$libresoc.v:203630$14644 + attribute \src "libresoc.v:198118.3-198119.39" + process $proc$libresoc.v:198118$14415 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:203632.3-203633.39" - process $proc$libresoc.v:203632$14645 + attribute \src "libresoc.v:198120.3-198121.39" + process $proc$libresoc.v:198120$14416 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:203634.3-203635.41" - process $proc$libresoc.v:203634$14646 + attribute \src "libresoc.v:198122.3-198123.41" + process $proc$libresoc.v:198122$14417 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:203636.3-203637.41" - process $proc$libresoc.v:203636$14647 + attribute \src "libresoc.v:198124.3-198125.41" + process $proc$libresoc.v:198124$14418 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:203638.3-203639.37" - process $proc$libresoc.v:203638$14648 + attribute \src "libresoc.v:198126.3-198127.37" + process $proc$libresoc.v:198126$14419 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:203640.3-203641.41" - process $proc$libresoc.v:203640$14649 + attribute \src "libresoc.v:198128.3-198129.41" + process $proc$libresoc.v:198128$14420 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:203642.3-203643.25" - process $proc$libresoc.v:203642$14650 + attribute \src "libresoc.v:198130.3-198131.25" + process $proc$libresoc.v:198130$14421 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:203723.3-203732.6" - process $proc$libresoc.v:203723$14651 + attribute \src "libresoc.v:198211.3-198220.6" + process $proc$libresoc.v:198211$14422 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:203724.5-203724.29" + attribute \src "libresoc.v:198212.5-198212.29" switch \initial - attribute \src "libresoc.v:203724.9-203724.17" + attribute \src "libresoc.v:198212.9-198212.17" case 1'1 case end @@ -424241,14 +415544,14 @@ module \trap0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:203733.3-203741.6" - process $proc$libresoc.v:203733$14652 + attribute \src "libresoc.v:198221.3-198229.6" + process $proc$libresoc.v:198221$14423 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$14653 $1\rok_l_s_rdok$next[0:0]$14654 - attribute \src "libresoc.v:203734.5-203734.29" + assign $0\rok_l_s_rdok$next[0:0]$14424 $1\rok_l_s_rdok$next[0:0]$14425 + attribute \src "libresoc.v:198222.5-198222.29" switch \initial - attribute \src "libresoc.v:203734.9-203734.17" + attribute \src "libresoc.v:198222.9-198222.17" case 1'1 case end @@ -424257,21 +415560,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$14654 1'0 + assign $1\rok_l_s_rdok$next[0:0]$14425 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$14654 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$14425 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14653 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14424 end - attribute \src "libresoc.v:203742.3-203750.6" - process $proc$libresoc.v:203742$14655 + attribute \src "libresoc.v:198230.3-198238.6" + process $proc$libresoc.v:198230$14426 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$14656 $1\rok_l_r_rdok$next[0:0]$14657 - attribute \src "libresoc.v:203743.5-203743.29" + assign $0\rok_l_r_rdok$next[0:0]$14427 $1\rok_l_r_rdok$next[0:0]$14428 + attribute \src "libresoc.v:198231.5-198231.29" switch \initial - attribute \src "libresoc.v:203743.9-203743.17" + attribute \src "libresoc.v:198231.9-198231.17" case 1'1 case end @@ -424280,21 +415583,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$14657 1'1 + assign $1\rok_l_r_rdok$next[0:0]$14428 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$14657 \$65 + assign $1\rok_l_r_rdok$next[0:0]$14428 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14656 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14427 end - attribute \src "libresoc.v:203751.3-203759.6" - process $proc$libresoc.v:203751$14658 + attribute \src "libresoc.v:198239.3-198247.6" + process $proc$libresoc.v:198239$14429 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$14659 $1\rst_l_s_rst$next[0:0]$14660 - attribute \src "libresoc.v:203752.5-203752.29" + assign $0\rst_l_s_rst$next[0:0]$14430 $1\rst_l_s_rst$next[0:0]$14431 + attribute \src "libresoc.v:198240.5-198240.29" switch \initial - attribute \src "libresoc.v:203752.9-203752.17" + attribute \src "libresoc.v:198240.9-198240.17" case 1'1 case end @@ -424303,21 +415606,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$14660 1'0 + assign $1\rst_l_s_rst$next[0:0]$14431 1'0 case - assign $1\rst_l_s_rst$next[0:0]$14660 \all_rd + assign $1\rst_l_s_rst$next[0:0]$14431 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14659 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14430 end - attribute \src "libresoc.v:203760.3-203768.6" - process $proc$libresoc.v:203760$14661 + attribute \src "libresoc.v:198248.3-198256.6" + process $proc$libresoc.v:198248$14432 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$14662 $1\rst_l_r_rst$next[0:0]$14663 - attribute \src "libresoc.v:203761.5-203761.29" + assign $0\rst_l_r_rst$next[0:0]$14433 $1\rst_l_r_rst$next[0:0]$14434 + attribute \src "libresoc.v:198249.5-198249.29" switch \initial - attribute \src "libresoc.v:203761.9-203761.17" + attribute \src "libresoc.v:198249.9-198249.17" case 1'1 case end @@ -424326,21 +415629,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$14663 1'1 + assign $1\rst_l_r_rst$next[0:0]$14434 1'1 case - assign $1\rst_l_r_rst$next[0:0]$14663 \rst_r + assign $1\rst_l_r_rst$next[0:0]$14434 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14662 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14433 end - attribute \src "libresoc.v:203769.3-203777.6" - process $proc$libresoc.v:203769$14664 + attribute \src "libresoc.v:198257.3-198265.6" + process $proc$libresoc.v:198257$14435 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$14665 $1\opc_l_s_opc$next[0:0]$14666 - attribute \src "libresoc.v:203770.5-203770.29" + assign $0\opc_l_s_opc$next[0:0]$14436 $1\opc_l_s_opc$next[0:0]$14437 + attribute \src "libresoc.v:198258.5-198258.29" switch \initial - attribute \src "libresoc.v:203770.9-203770.17" + attribute \src "libresoc.v:198258.9-198258.17" case 1'1 case end @@ -424349,21 +415652,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$14666 1'0 + assign $1\opc_l_s_opc$next[0:0]$14437 1'0 case - assign $1\opc_l_s_opc$next[0:0]$14666 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$14437 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14665 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14436 end - attribute \src "libresoc.v:203778.3-203786.6" - process $proc$libresoc.v:203778$14667 + attribute \src "libresoc.v:198266.3-198274.6" + process $proc$libresoc.v:198266$14438 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$14668 $1\opc_l_r_opc$next[0:0]$14669 - attribute \src "libresoc.v:203779.5-203779.29" + assign $0\opc_l_r_opc$next[0:0]$14439 $1\opc_l_r_opc$next[0:0]$14440 + attribute \src "libresoc.v:198267.5-198267.29" switch \initial - attribute \src "libresoc.v:203779.9-203779.17" + attribute \src "libresoc.v:198267.9-198267.17" case 1'1 case end @@ -424372,21 +415675,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$14669 1'1 + assign $1\opc_l_r_opc$next[0:0]$14440 1'1 case - assign $1\opc_l_r_opc$next[0:0]$14669 \req_done + assign $1\opc_l_r_opc$next[0:0]$14440 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14668 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14439 end - attribute \src "libresoc.v:203787.3-203795.6" - process $proc$libresoc.v:203787$14670 + attribute \src "libresoc.v:198275.3-198283.6" + process $proc$libresoc.v:198275$14441 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$14671 $1\src_l_s_src$next[3:0]$14672 - attribute \src "libresoc.v:203788.5-203788.29" + assign $0\src_l_s_src$next[3:0]$14442 $1\src_l_s_src$next[3:0]$14443 + attribute \src "libresoc.v:198276.5-198276.29" switch \initial - attribute \src "libresoc.v:203788.9-203788.17" + attribute \src "libresoc.v:198276.9-198276.17" case 1'1 case end @@ -424395,21 +415698,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$14672 4'0000 + assign $1\src_l_s_src$next[3:0]$14443 4'0000 case - assign $1\src_l_s_src$next[3:0]$14672 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$14443 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14671 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14442 end - attribute \src "libresoc.v:203796.3-203804.6" - process $proc$libresoc.v:203796$14673 + attribute \src "libresoc.v:198284.3-198292.6" + process $proc$libresoc.v:198284$14444 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$14674 $1\src_l_r_src$next[3:0]$14675 - attribute \src "libresoc.v:203797.5-203797.29" + assign $0\src_l_r_src$next[3:0]$14445 $1\src_l_r_src$next[3:0]$14446 + attribute \src "libresoc.v:198285.5-198285.29" switch \initial - attribute \src "libresoc.v:203797.9-203797.17" + attribute \src "libresoc.v:198285.9-198285.17" case 1'1 case end @@ -424418,21 +415721,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$14675 4'1111 + assign $1\src_l_r_src$next[3:0]$14446 4'1111 case - assign $1\src_l_r_src$next[3:0]$14675 \reset_r + assign $1\src_l_r_src$next[3:0]$14446 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14674 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14445 end - attribute \src "libresoc.v:203805.3-203813.6" - process $proc$libresoc.v:203805$14676 + attribute \src "libresoc.v:198293.3-198301.6" + process $proc$libresoc.v:198293$14447 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$14677 $1\req_l_s_req$next[4:0]$14678 - attribute \src "libresoc.v:203806.5-203806.29" + assign $0\req_l_s_req$next[4:0]$14448 $1\req_l_s_req$next[4:0]$14449 + attribute \src "libresoc.v:198294.5-198294.29" switch \initial - attribute \src "libresoc.v:203806.9-203806.17" + attribute \src "libresoc.v:198294.9-198294.17" case 1'1 case end @@ -424441,21 +415744,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$14678 5'00000 + assign $1\req_l_s_req$next[4:0]$14449 5'00000 case - assign $1\req_l_s_req$next[4:0]$14678 \$67 + assign $1\req_l_s_req$next[4:0]$14449 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14677 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14448 end - attribute \src "libresoc.v:203814.3-203822.6" - process $proc$libresoc.v:203814$14679 + attribute \src "libresoc.v:198302.3-198310.6" + process $proc$libresoc.v:198302$14450 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$14680 $1\req_l_r_req$next[4:0]$14681 - attribute \src "libresoc.v:203815.5-203815.29" + assign $0\req_l_r_req$next[4:0]$14451 $1\req_l_r_req$next[4:0]$14452 + attribute \src "libresoc.v:198303.5-198303.29" switch \initial - attribute \src "libresoc.v:203815.9-203815.17" + attribute \src "libresoc.v:198303.9-198303.17" case 1'1 case end @@ -424464,15 +415767,15 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$14681 5'11111 + assign $1\req_l_r_req$next[4:0]$14452 5'11111 case - assign $1\req_l_r_req$next[4:0]$14681 \$69 + assign $1\req_l_r_req$next[4:0]$14452 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14680 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14451 end - attribute \src "libresoc.v:203823.3-203840.6" - process $proc$libresoc.v:203823$14682 + attribute \src "libresoc.v:198311.3-198328.6" + process $proc$libresoc.v:198311$14453 assign { } { } assign { } { } assign { } { } @@ -424491,18 +415794,18 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$14683 $1\alu_trap0_trap_op__cia$next[63:0]$14692 - assign $0\alu_trap0_trap_op__fn_unit$next[12:0]$14684 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14693 - assign $0\alu_trap0_trap_op__insn$next[31:0]$14685 $1\alu_trap0_trap_op__insn$next[31:0]$14694 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14686 $1\alu_trap0_trap_op__insn_type$next[6:0]$14695 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14687 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14696 - assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14688 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14697 - assign $0\alu_trap0_trap_op__msr$next[63:0]$14689 $1\alu_trap0_trap_op__msr$next[63:0]$14698 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14690 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14699 - assign $0\alu_trap0_trap_op__traptype$next[7:0]$14691 $1\alu_trap0_trap_op__traptype$next[7:0]$14700 - attribute \src "libresoc.v:203824.5-203824.29" + assign $0\alu_trap0_trap_op__cia$next[63:0]$14454 $1\alu_trap0_trap_op__cia$next[63:0]$14463 + assign $0\alu_trap0_trap_op__fn_unit$next[12:0]$14455 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14464 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14456 $1\alu_trap0_trap_op__insn$next[31:0]$14465 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14457 $1\alu_trap0_trap_op__insn_type$next[6:0]$14466 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14458 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14467 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14459 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14468 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14460 $1\alu_trap0_trap_op__msr$next[63:0]$14469 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14461 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14470 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14462 $1\alu_trap0_trap_op__traptype$next[7:0]$14471 + attribute \src "libresoc.v:198312.5-198312.29" switch \initial - attribute \src "libresoc.v:203824.9-203824.17" + attribute \src "libresoc.v:198312.9-198312.17" case 1'1 case end @@ -424519,43 +415822,43 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14697 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14699 $1\alu_trap0_trap_op__traptype$next[7:0]$14700 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14696 $1\alu_trap0_trap_op__cia$next[63:0]$14692 $1\alu_trap0_trap_op__msr$next[63:0]$14698 $1\alu_trap0_trap_op__insn$next[31:0]$14694 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14693 $1\alu_trap0_trap_op__insn_type$next[6:0]$14695 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14468 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14470 $1\alu_trap0_trap_op__traptype$next[7:0]$14471 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14467 $1\alu_trap0_trap_op__cia$next[63:0]$14463 $1\alu_trap0_trap_op__msr$next[63:0]$14469 $1\alu_trap0_trap_op__insn$next[31:0]$14465 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14464 $1\alu_trap0_trap_op__insn_type$next[6:0]$14466 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $1\alu_trap0_trap_op__cia$next[63:0]$14692 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[12:0]$14693 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$14694 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14695 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14696 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14697 \alu_trap0_trap_op__ldst_exc - assign $1\alu_trap0_trap_op__msr$next[63:0]$14698 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14699 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[7:0]$14700 \alu_trap0_trap_op__traptype + assign $1\alu_trap0_trap_op__cia$next[63:0]$14463 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[12:0]$14464 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14465 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14466 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14467 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14468 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14469 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14470 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14471 \alu_trap0_trap_op__traptype end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14683 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[12:0]$14684 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14685 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14686 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14687 - update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14688 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14689 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14690 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14691 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14454 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[12:0]$14455 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14456 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14457 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14458 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14459 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14460 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14461 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14462 end - attribute \src "libresoc.v:203841.3-203862.6" - process $proc$libresoc.v:203841$14701 + attribute \src "libresoc.v:198329.3-198350.6" + process $proc$libresoc.v:198329$14472 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$14702 $2\data_r0__o$next[63:0]$14706 + assign $0\data_r0__o$next[63:0]$14473 $2\data_r0__o$next[63:0]$14477 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$14703 $3\data_r0__o_ok$next[0:0]$14708 - attribute \src "libresoc.v:203842.5-203842.29" + assign $0\data_r0__o_ok$next[0:0]$14474 $3\data_r0__o_ok$next[0:0]$14479 + attribute \src "libresoc.v:198330.5-198330.29" switch \initial - attribute \src "libresoc.v:203842.9-203842.17" + attribute \src "libresoc.v:198330.9-198330.17" case 1'1 case end @@ -424565,10 +415868,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$14705 $1\data_r0__o$next[63:0]$14704 } { \o_ok \alu_trap0_o } + assign { $1\data_r0__o_ok$next[0:0]$14476 $1\data_r0__o$next[63:0]$14475 } { \o_ok \alu_trap0_o } case - assign $1\data_r0__o$next[63:0]$14704 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$14705 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$14475 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14476 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -424576,38 +415879,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$14707 $2\data_r0__o$next[63:0]$14706 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$14478 $2\data_r0__o$next[63:0]$14477 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$14706 $1\data_r0__o$next[63:0]$14704 - assign $2\data_r0__o_ok$next[0:0]$14707 $1\data_r0__o_ok$next[0:0]$14705 + assign $2\data_r0__o$next[63:0]$14477 $1\data_r0__o$next[63:0]$14475 + assign $2\data_r0__o_ok$next[0:0]$14478 $1\data_r0__o_ok$next[0:0]$14476 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$14708 1'0 + assign $3\data_r0__o_ok$next[0:0]$14479 1'0 case - assign $3\data_r0__o_ok$next[0:0]$14708 $2\data_r0__o_ok$next[0:0]$14707 + assign $3\data_r0__o_ok$next[0:0]$14479 $2\data_r0__o_ok$next[0:0]$14478 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$14702 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14703 + update \data_r0__o$next $0\data_r0__o$next[63:0]$14473 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14474 end - attribute \src "libresoc.v:203863.3-203884.6" - process $proc$libresoc.v:203863$14709 + attribute \src "libresoc.v:198351.3-198372.6" + process $proc$libresoc.v:198351$14480 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__fast1$next[63:0]$14710 $2\data_r1__fast1$next[63:0]$14714 + assign $0\data_r1__fast1$next[63:0]$14481 $2\data_r1__fast1$next[63:0]$14485 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$14711 $3\data_r1__fast1_ok$next[0:0]$14716 - attribute \src "libresoc.v:203864.5-203864.29" + assign $0\data_r1__fast1_ok$next[0:0]$14482 $3\data_r1__fast1_ok$next[0:0]$14487 + attribute \src "libresoc.v:198352.5-198352.29" switch \initial - attribute \src "libresoc.v:203864.9-203864.17" + attribute \src "libresoc.v:198352.9-198352.17" case 1'1 case end @@ -424617,10 +415920,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$14713 $1\data_r1__fast1$next[63:0]$14712 } { \fast1_ok \alu_trap0_fast1 } + assign { $1\data_r1__fast1_ok$next[0:0]$14484 $1\data_r1__fast1$next[63:0]$14483 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\data_r1__fast1$next[63:0]$14712 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$14713 \data_r1__fast1_ok + assign $1\data_r1__fast1$next[63:0]$14483 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14484 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -424628,38 +415931,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$14715 $2\data_r1__fast1$next[63:0]$14714 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__fast1_ok$next[0:0]$14486 $2\data_r1__fast1$next[63:0]$14485 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$14714 $1\data_r1__fast1$next[63:0]$14712 - assign $2\data_r1__fast1_ok$next[0:0]$14715 $1\data_r1__fast1_ok$next[0:0]$14713 + assign $2\data_r1__fast1$next[63:0]$14485 $1\data_r1__fast1$next[63:0]$14483 + assign $2\data_r1__fast1_ok$next[0:0]$14486 $1\data_r1__fast1_ok$next[0:0]$14484 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$14716 1'0 + assign $3\data_r1__fast1_ok$next[0:0]$14487 1'0 case - assign $3\data_r1__fast1_ok$next[0:0]$14716 $2\data_r1__fast1_ok$next[0:0]$14715 + assign $3\data_r1__fast1_ok$next[0:0]$14487 $2\data_r1__fast1_ok$next[0:0]$14486 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14710 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14711 + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14481 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14482 end - attribute \src "libresoc.v:203885.3-203906.6" - process $proc$libresoc.v:203885$14717 + attribute \src "libresoc.v:198373.3-198394.6" + process $proc$libresoc.v:198373$14488 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast2$next[63:0]$14718 $2\data_r2__fast2$next[63:0]$14722 + assign $0\data_r2__fast2$next[63:0]$14489 $2\data_r2__fast2$next[63:0]$14493 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$14719 $3\data_r2__fast2_ok$next[0:0]$14724 - attribute \src "libresoc.v:203886.5-203886.29" + assign $0\data_r2__fast2_ok$next[0:0]$14490 $3\data_r2__fast2_ok$next[0:0]$14495 + attribute \src "libresoc.v:198374.5-198374.29" switch \initial - attribute \src "libresoc.v:203886.9-203886.17" + attribute \src "libresoc.v:198374.9-198374.17" case 1'1 case end @@ -424669,10 +415972,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$14721 $1\data_r2__fast2$next[63:0]$14720 } { \fast2_ok \alu_trap0_fast2 } + assign { $1\data_r2__fast2_ok$next[0:0]$14492 $1\data_r2__fast2$next[63:0]$14491 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\data_r2__fast2$next[63:0]$14720 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$14721 \data_r2__fast2_ok + assign $1\data_r2__fast2$next[63:0]$14491 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14492 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -424680,38 +415983,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$14723 $2\data_r2__fast2$next[63:0]$14722 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast2_ok$next[0:0]$14494 $2\data_r2__fast2$next[63:0]$14493 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast2$next[63:0]$14722 $1\data_r2__fast2$next[63:0]$14720 - assign $2\data_r2__fast2_ok$next[0:0]$14723 $1\data_r2__fast2_ok$next[0:0]$14721 + assign $2\data_r2__fast2$next[63:0]$14493 $1\data_r2__fast2$next[63:0]$14491 + assign $2\data_r2__fast2_ok$next[0:0]$14494 $1\data_r2__fast2_ok$next[0:0]$14492 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$14724 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14495 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$14724 $2\data_r2__fast2_ok$next[0:0]$14723 + assign $3\data_r2__fast2_ok$next[0:0]$14495 $2\data_r2__fast2_ok$next[0:0]$14494 end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14718 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14719 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14489 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14490 end - attribute \src "libresoc.v:203907.3-203928.6" - process $proc$libresoc.v:203907$14725 + attribute \src "libresoc.v:198395.3-198416.6" + process $proc$libresoc.v:198395$14496 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__nia$next[63:0]$14726 $2\data_r3__nia$next[63:0]$14730 + assign $0\data_r3__nia$next[63:0]$14497 $2\data_r3__nia$next[63:0]$14501 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$14727 $3\data_r3__nia_ok$next[0:0]$14732 - attribute \src "libresoc.v:203908.5-203908.29" + assign $0\data_r3__nia_ok$next[0:0]$14498 $3\data_r3__nia_ok$next[0:0]$14503 + attribute \src "libresoc.v:198396.5-198396.29" switch \initial - attribute \src "libresoc.v:203908.9-203908.17" + attribute \src "libresoc.v:198396.9-198396.17" case 1'1 case end @@ -424721,10 +416024,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$14729 $1\data_r3__nia$next[63:0]$14728 } { \nia_ok \alu_trap0_nia } + assign { $1\data_r3__nia_ok$next[0:0]$14500 $1\data_r3__nia$next[63:0]$14499 } { \nia_ok \alu_trap0_nia } case - assign $1\data_r3__nia$next[63:0]$14728 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$14729 \data_r3__nia_ok + assign $1\data_r3__nia$next[63:0]$14499 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14500 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -424732,38 +416035,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$14731 $2\data_r3__nia$next[63:0]$14730 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r3__nia_ok$next[0:0]$14502 $2\data_r3__nia$next[63:0]$14501 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$14730 $1\data_r3__nia$next[63:0]$14728 - assign $2\data_r3__nia_ok$next[0:0]$14731 $1\data_r3__nia_ok$next[0:0]$14729 + assign $2\data_r3__nia$next[63:0]$14501 $1\data_r3__nia$next[63:0]$14499 + assign $2\data_r3__nia_ok$next[0:0]$14502 $1\data_r3__nia_ok$next[0:0]$14500 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$14732 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14503 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$14732 $2\data_r3__nia_ok$next[0:0]$14731 + assign $3\data_r3__nia_ok$next[0:0]$14503 $2\data_r3__nia_ok$next[0:0]$14502 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14726 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14727 + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14497 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14498 end - attribute \src "libresoc.v:203929.3-203950.6" - process $proc$libresoc.v:203929$14733 + attribute \src "libresoc.v:198417.3-198438.6" + process $proc$libresoc.v:198417$14504 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__msr$next[63:0]$14734 $2\data_r4__msr$next[63:0]$14738 + assign $0\data_r4__msr$next[63:0]$14505 $2\data_r4__msr$next[63:0]$14509 assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$14735 $3\data_r4__msr_ok$next[0:0]$14740 - attribute \src "libresoc.v:203930.5-203930.29" + assign $0\data_r4__msr_ok$next[0:0]$14506 $3\data_r4__msr_ok$next[0:0]$14511 + attribute \src "libresoc.v:198418.5-198418.29" switch \initial - attribute \src "libresoc.v:203930.9-203930.17" + attribute \src "libresoc.v:198418.9-198418.17" case 1'1 case end @@ -424773,10 +416076,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$14737 $1\data_r4__msr$next[63:0]$14736 } { \msr_ok \alu_trap0_msr } + assign { $1\data_r4__msr_ok$next[0:0]$14508 $1\data_r4__msr$next[63:0]$14507 } { \msr_ok \alu_trap0_msr } case - assign $1\data_r4__msr$next[63:0]$14736 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$14737 \data_r4__msr_ok + assign $1\data_r4__msr$next[63:0]$14507 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14508 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -424784,32 +416087,32 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$14739 $2\data_r4__msr$next[63:0]$14738 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r4__msr_ok$next[0:0]$14510 $2\data_r4__msr$next[63:0]$14509 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$14738 $1\data_r4__msr$next[63:0]$14736 - assign $2\data_r4__msr_ok$next[0:0]$14739 $1\data_r4__msr_ok$next[0:0]$14737 + assign $2\data_r4__msr$next[63:0]$14509 $1\data_r4__msr$next[63:0]$14507 + assign $2\data_r4__msr_ok$next[0:0]$14510 $1\data_r4__msr_ok$next[0:0]$14508 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$14740 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14511 1'0 case - assign $3\data_r4__msr_ok$next[0:0]$14740 $2\data_r4__msr_ok$next[0:0]$14739 + assign $3\data_r4__msr_ok$next[0:0]$14511 $2\data_r4__msr_ok$next[0:0]$14510 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14734 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14735 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14505 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14506 end - attribute \src "libresoc.v:203951.3-203960.6" - process $proc$libresoc.v:203951$14741 + attribute \src "libresoc.v:198439.3-198448.6" + process $proc$libresoc.v:198439$14512 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$14742 $1\src_r0$next[63:0]$14743 - attribute \src "libresoc.v:203952.5-203952.29" + assign $0\src_r0$next[63:0]$14513 $1\src_r0$next[63:0]$14514 + attribute \src "libresoc.v:198440.5-198440.29" switch \initial - attribute \src "libresoc.v:203952.9-203952.17" + attribute \src "libresoc.v:198440.9-198440.17" case 1'1 case end @@ -424818,21 +416121,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$14743 \src1_i + assign $1\src_r0$next[63:0]$14514 \src1_i case - assign $1\src_r0$next[63:0]$14743 \src_r0 + assign $1\src_r0$next[63:0]$14514 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$14742 + update \src_r0$next $0\src_r0$next[63:0]$14513 end - attribute \src "libresoc.v:203961.3-203970.6" - process $proc$libresoc.v:203961$14744 + attribute \src "libresoc.v:198449.3-198458.6" + process $proc$libresoc.v:198449$14515 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$14745 $1\src_r1$next[63:0]$14746 - attribute \src "libresoc.v:203962.5-203962.29" + assign $0\src_r1$next[63:0]$14516 $1\src_r1$next[63:0]$14517 + attribute \src "libresoc.v:198450.5-198450.29" switch \initial - attribute \src "libresoc.v:203962.9-203962.17" + attribute \src "libresoc.v:198450.9-198450.17" case 1'1 case end @@ -424841,21 +416144,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$14746 \src2_i + assign $1\src_r1$next[63:0]$14517 \src2_i case - assign $1\src_r1$next[63:0]$14746 \src_r1 + assign $1\src_r1$next[63:0]$14517 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$14745 + update \src_r1$next $0\src_r1$next[63:0]$14516 end - attribute \src "libresoc.v:203971.3-203980.6" - process $proc$libresoc.v:203971$14747 + attribute \src "libresoc.v:198459.3-198468.6" + process $proc$libresoc.v:198459$14518 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$14748 $1\src_r2$next[63:0]$14749 - attribute \src "libresoc.v:203972.5-203972.29" + assign $0\src_r2$next[63:0]$14519 $1\src_r2$next[63:0]$14520 + attribute \src "libresoc.v:198460.5-198460.29" switch \initial - attribute \src "libresoc.v:203972.9-203972.17" + attribute \src "libresoc.v:198460.9-198460.17" case 1'1 case end @@ -424864,21 +416167,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$14749 \src3_i + assign $1\src_r2$next[63:0]$14520 \src3_i case - assign $1\src_r2$next[63:0]$14749 \src_r2 + assign $1\src_r2$next[63:0]$14520 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$14748 + update \src_r2$next $0\src_r2$next[63:0]$14519 end - attribute \src "libresoc.v:203981.3-203990.6" - process $proc$libresoc.v:203981$14750 + attribute \src "libresoc.v:198469.3-198478.6" + process $proc$libresoc.v:198469$14521 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$14751 $1\src_r3$next[63:0]$14752 - attribute \src "libresoc.v:203982.5-203982.29" + assign $0\src_r3$next[63:0]$14522 $1\src_r3$next[63:0]$14523 + attribute \src "libresoc.v:198470.5-198470.29" switch \initial - attribute \src "libresoc.v:203982.9-203982.17" + attribute \src "libresoc.v:198470.9-198470.17" case 1'1 case end @@ -424887,21 +416190,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$14752 \src4_i + assign $1\src_r3$next[63:0]$14523 \src4_i case - assign $1\src_r3$next[63:0]$14752 \src_r3 + assign $1\src_r3$next[63:0]$14523 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[63:0]$14751 + update \src_r3$next $0\src_r3$next[63:0]$14522 end - attribute \src "libresoc.v:203991.3-203999.6" - process $proc$libresoc.v:203991$14753 + attribute \src "libresoc.v:198479.3-198487.6" + process $proc$libresoc.v:198479$14524 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$14754 $1\alui_l_r_alui$next[0:0]$14755 - attribute \src "libresoc.v:203992.5-203992.29" + assign $0\alui_l_r_alui$next[0:0]$14525 $1\alui_l_r_alui$next[0:0]$14526 + attribute \src "libresoc.v:198480.5-198480.29" switch \initial - attribute \src "libresoc.v:203992.9-203992.17" + attribute \src "libresoc.v:198480.9-198480.17" case 1'1 case end @@ -424910,21 +416213,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$14755 1'1 + assign $1\alui_l_r_alui$next[0:0]$14526 1'1 case - assign $1\alui_l_r_alui$next[0:0]$14755 \$89 + assign $1\alui_l_r_alui$next[0:0]$14526 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14754 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14525 end - attribute \src "libresoc.v:204000.3-204008.6" - process $proc$libresoc.v:204000$14756 + attribute \src "libresoc.v:198488.3-198496.6" + process $proc$libresoc.v:198488$14527 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$14757 $1\alu_l_r_alu$next[0:0]$14758 - attribute \src "libresoc.v:204001.5-204001.29" + assign $0\alu_l_r_alu$next[0:0]$14528 $1\alu_l_r_alu$next[0:0]$14529 + attribute \src "libresoc.v:198489.5-198489.29" switch \initial - attribute \src "libresoc.v:204001.9-204001.17" + attribute \src "libresoc.v:198489.9-198489.17" case 1'1 case end @@ -424933,21 +416236,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$14758 1'1 + assign $1\alu_l_r_alu$next[0:0]$14529 1'1 case - assign $1\alu_l_r_alu$next[0:0]$14758 \$91 + assign $1\alu_l_r_alu$next[0:0]$14529 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14757 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14528 end - attribute \src "libresoc.v:204009.3-204018.6" - process $proc$libresoc.v:204009$14759 + attribute \src "libresoc.v:198497.3-198506.6" + process $proc$libresoc.v:198497$14530 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:204010.5-204010.29" + attribute \src "libresoc.v:198498.5-198498.29" switch \initial - attribute \src "libresoc.v:204010.9-204010.17" + attribute \src "libresoc.v:198498.9-198498.17" case 1'1 case end @@ -424963,14 +416266,14 @@ module \trap0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:204019.3-204028.6" - process $proc$libresoc.v:204019$14760 + attribute \src "libresoc.v:198507.3-198516.6" + process $proc$libresoc.v:198507$14531 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:204020.5-204020.29" + attribute \src "libresoc.v:198508.5-198508.29" switch \initial - attribute \src "libresoc.v:204020.9-204020.17" + attribute \src "libresoc.v:198508.9-198508.17" case 1'1 case end @@ -424986,14 +416289,14 @@ module \trap0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:204029.3-204038.6" - process $proc$libresoc.v:204029$14761 + attribute \src "libresoc.v:198517.3-198526.6" + process $proc$libresoc.v:198517$14532 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:204030.5-204030.29" + attribute \src "libresoc.v:198518.5-198518.29" switch \initial - attribute \src "libresoc.v:204030.9-204030.17" + attribute \src "libresoc.v:198518.9-198518.17" case 1'1 case end @@ -425009,14 +416312,14 @@ module \trap0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:204039.3-204048.6" - process $proc$libresoc.v:204039$14762 + attribute \src "libresoc.v:198527.3-198536.6" + process $proc$libresoc.v:198527$14533 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:204040.5-204040.29" + attribute \src "libresoc.v:198528.5-198528.29" switch \initial - attribute \src "libresoc.v:204040.9-204040.17" + attribute \src "libresoc.v:198528.9-198528.17" case 1'1 case end @@ -425032,14 +416335,14 @@ module \trap0 sync always update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:204049.3-204058.6" - process $proc$libresoc.v:204049$14763 + attribute \src "libresoc.v:198537.3-198546.6" + process $proc$libresoc.v:198537$14534 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:204050.5-204050.29" + attribute \src "libresoc.v:198538.5-198538.29" switch \initial - attribute \src "libresoc.v:204050.9-204050.17" + attribute \src "libresoc.v:198538.9-198538.17" case 1'1 case end @@ -425055,14 +416358,14 @@ module \trap0 sync always update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:204059.3-204067.6" - process $proc$libresoc.v:204059$14764 + attribute \src "libresoc.v:198547.3-198555.6" + process $proc$libresoc.v:198547$14535 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$14765 $1\prev_wr_go$next[4:0]$14766 - attribute \src "libresoc.v:204060.5-204060.29" + assign $0\prev_wr_go$next[4:0]$14536 $1\prev_wr_go$next[4:0]$14537 + attribute \src "libresoc.v:198548.5-198548.29" switch \initial - attribute \src "libresoc.v:204060.9-204060.17" + attribute \src "libresoc.v:198548.9-198548.17" case 1'1 case end @@ -425071,74 +416374,74 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$14766 5'00000 - case - assign $1\prev_wr_go$next[4:0]$14766 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14765 - end - connect \$5 $reduce_and$libresoc.v:203507$14552_Y - connect \$99 $and$libresoc.v:203508$14553_Y - connect \$101 $and$libresoc.v:203509$14554_Y - connect \$103 $and$libresoc.v:203510$14555_Y - connect \$105 $and$libresoc.v:203511$14556_Y - connect \$107 $and$libresoc.v:203512$14557_Y - connect \$109 $and$libresoc.v:203513$14558_Y - connect \$111 $and$libresoc.v:203514$14559_Y - connect \$113 $and$libresoc.v:203515$14560_Y - connect \$115 $and$libresoc.v:203516$14561_Y - connect \$117 $and$libresoc.v:203517$14562_Y - connect \$11 $and$libresoc.v:203518$14563_Y - connect \$119 $and$libresoc.v:203519$14564_Y - connect \$121 $and$libresoc.v:203520$14565_Y - connect \$123 $and$libresoc.v:203521$14566_Y - connect \$13 $not$libresoc.v:203522$14567_Y - connect \$15 $and$libresoc.v:203523$14568_Y - connect \$17 $not$libresoc.v:203524$14569_Y - connect \$19 $and$libresoc.v:203525$14570_Y - connect \$21 $and$libresoc.v:203526$14571_Y - connect \$25 $not$libresoc.v:203527$14572_Y - connect \$27 $and$libresoc.v:203528$14573_Y - connect \$24 $reduce_or$libresoc.v:203529$14574_Y - connect \$23 $not$libresoc.v:203530$14575_Y - connect \$31 $and$libresoc.v:203531$14576_Y - connect \$33 $reduce_or$libresoc.v:203532$14577_Y - connect \$35 $reduce_or$libresoc.v:203533$14578_Y - connect \$37 $or$libresoc.v:203534$14579_Y - connect \$3 $and$libresoc.v:203535$14580_Y - connect \$39 $not$libresoc.v:203536$14581_Y - connect \$41 $and$libresoc.v:203537$14582_Y - connect \$43 $and$libresoc.v:203538$14583_Y - connect \$45 $eq$libresoc.v:203539$14584_Y - connect \$47 $and$libresoc.v:203540$14585_Y - connect \$49 $eq$libresoc.v:203541$14586_Y - connect \$51 $and$libresoc.v:203542$14587_Y - connect \$53 $and$libresoc.v:203543$14588_Y - connect \$55 $and$libresoc.v:203544$14589_Y - connect \$57 $or$libresoc.v:203545$14590_Y - connect \$59 $or$libresoc.v:203546$14591_Y - connect \$61 $or$libresoc.v:203547$14592_Y - connect \$63 $or$libresoc.v:203548$14593_Y - connect \$65 $and$libresoc.v:203549$14594_Y - connect \$67 $and$libresoc.v:203550$14595_Y - connect \$6 $not$libresoc.v:203551$14596_Y - connect \$69 $or$libresoc.v:203552$14597_Y - connect \$71 $and$libresoc.v:203553$14598_Y - connect \$73 $and$libresoc.v:203554$14599_Y - connect \$75 $and$libresoc.v:203555$14600_Y - connect \$77 $and$libresoc.v:203556$14601_Y - connect \$79 $and$libresoc.v:203557$14602_Y - connect \$81 $ternary$libresoc.v:203558$14603_Y - connect \$83 $ternary$libresoc.v:203559$14604_Y - connect \$85 $ternary$libresoc.v:203560$14605_Y - connect \$87 $ternary$libresoc.v:203561$14606_Y - connect \$8 $or$libresoc.v:203562$14607_Y - connect \$89 $and$libresoc.v:203563$14608_Y - connect \$91 $and$libresoc.v:203564$14609_Y - connect \$93 $and$libresoc.v:203565$14610_Y - connect \$95 $and$libresoc.v:203566$14611_Y - connect \$97 $not$libresoc.v:203567$14612_Y + assign $1\prev_wr_go$next[4:0]$14537 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14537 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14536 + end + connect \$5 $reduce_and$libresoc.v:197995$14323_Y + connect \$99 $and$libresoc.v:197996$14324_Y + connect \$101 $and$libresoc.v:197997$14325_Y + connect \$103 $and$libresoc.v:197998$14326_Y + connect \$105 $and$libresoc.v:197999$14327_Y + connect \$107 $and$libresoc.v:198000$14328_Y + connect \$109 $and$libresoc.v:198001$14329_Y + connect \$111 $and$libresoc.v:198002$14330_Y + connect \$113 $and$libresoc.v:198003$14331_Y + connect \$115 $and$libresoc.v:198004$14332_Y + connect \$117 $and$libresoc.v:198005$14333_Y + connect \$11 $and$libresoc.v:198006$14334_Y + connect \$119 $and$libresoc.v:198007$14335_Y + connect \$121 $and$libresoc.v:198008$14336_Y + connect \$123 $and$libresoc.v:198009$14337_Y + connect \$13 $not$libresoc.v:198010$14338_Y + connect \$15 $and$libresoc.v:198011$14339_Y + connect \$17 $not$libresoc.v:198012$14340_Y + connect \$19 $and$libresoc.v:198013$14341_Y + connect \$21 $and$libresoc.v:198014$14342_Y + connect \$25 $not$libresoc.v:198015$14343_Y + connect \$27 $and$libresoc.v:198016$14344_Y + connect \$24 $reduce_or$libresoc.v:198017$14345_Y + connect \$23 $not$libresoc.v:198018$14346_Y + connect \$31 $and$libresoc.v:198019$14347_Y + connect \$33 $reduce_or$libresoc.v:198020$14348_Y + connect \$35 $reduce_or$libresoc.v:198021$14349_Y + connect \$37 $or$libresoc.v:198022$14350_Y + connect \$3 $and$libresoc.v:198023$14351_Y + connect \$39 $not$libresoc.v:198024$14352_Y + connect \$41 $and$libresoc.v:198025$14353_Y + connect \$43 $and$libresoc.v:198026$14354_Y + connect \$45 $eq$libresoc.v:198027$14355_Y + connect \$47 $and$libresoc.v:198028$14356_Y + connect \$49 $eq$libresoc.v:198029$14357_Y + connect \$51 $and$libresoc.v:198030$14358_Y + connect \$53 $and$libresoc.v:198031$14359_Y + connect \$55 $and$libresoc.v:198032$14360_Y + connect \$57 $or$libresoc.v:198033$14361_Y + connect \$59 $or$libresoc.v:198034$14362_Y + connect \$61 $or$libresoc.v:198035$14363_Y + connect \$63 $or$libresoc.v:198036$14364_Y + connect \$65 $and$libresoc.v:198037$14365_Y + connect \$67 $and$libresoc.v:198038$14366_Y + connect \$6 $not$libresoc.v:198039$14367_Y + connect \$69 $or$libresoc.v:198040$14368_Y + connect \$71 $and$libresoc.v:198041$14369_Y + connect \$73 $and$libresoc.v:198042$14370_Y + connect \$75 $and$libresoc.v:198043$14371_Y + connect \$77 $and$libresoc.v:198044$14372_Y + connect \$79 $and$libresoc.v:198045$14373_Y + connect \$81 $ternary$libresoc.v:198046$14374_Y + connect \$83 $ternary$libresoc.v:198047$14375_Y + connect \$85 $ternary$libresoc.v:198048$14376_Y + connect \$87 $ternary$libresoc.v:198049$14377_Y + connect \$8 $or$libresoc.v:198050$14378_Y + connect \$89 $and$libresoc.v:198051$14379_Y + connect \$91 $and$libresoc.v:198052$14380_Y + connect \$93 $and$libresoc.v:198053$14381_Y + connect \$95 $and$libresoc.v:198054$14382_Y + connect \$97 $not$libresoc.v:198055$14383_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 @@ -425169,37 +416472,37 @@ module \trap0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:204101.1-204159.10" +attribute \src "libresoc.v:198589.1-198647.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l - attribute \src "libresoc.v:204102.7-204102.20" + attribute \src "libresoc.v:198590.7-198590.20" wire $0\initial[0:0] - attribute \src "libresoc.v:204147.3-204155.6" - wire $0\q_int$next[0:0]$14816 - attribute \src "libresoc.v:204145.3-204146.27" + attribute \src "libresoc.v:198635.3-198643.6" + wire $0\q_int$next[0:0]$14587 + attribute \src "libresoc.v:198633.3-198634.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:204147.3-204155.6" - wire $1\q_int$next[0:0]$14817 - attribute \src "libresoc.v:204124.7-204124.19" + attribute \src "libresoc.v:198635.3-198643.6" + wire $1\q_int$next[0:0]$14588 + attribute \src "libresoc.v:198612.7-198612.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:204137.17-204137.96" - wire $and$libresoc.v:204137$14806_Y - attribute \src "libresoc.v:204142.17-204142.96" - wire $and$libresoc.v:204142$14811_Y - attribute \src "libresoc.v:204139.18-204139.93" - wire $not$libresoc.v:204139$14808_Y - attribute \src "libresoc.v:204141.17-204141.92" - wire $not$libresoc.v:204141$14810_Y - attribute \src "libresoc.v:204144.17-204144.92" - wire $not$libresoc.v:204144$14813_Y - attribute \src "libresoc.v:204138.18-204138.98" - wire $or$libresoc.v:204138$14807_Y - attribute \src "libresoc.v:204140.18-204140.99" - wire $or$libresoc.v:204140$14809_Y - attribute \src "libresoc.v:204143.17-204143.97" - wire $or$libresoc.v:204143$14812_Y + attribute \src "libresoc.v:198625.17-198625.96" + wire $and$libresoc.v:198625$14577_Y + attribute \src "libresoc.v:198630.17-198630.96" + wire $and$libresoc.v:198630$14582_Y + attribute \src "libresoc.v:198627.18-198627.93" + wire $not$libresoc.v:198627$14579_Y + attribute \src "libresoc.v:198629.17-198629.92" + wire $not$libresoc.v:198629$14581_Y + attribute \src "libresoc.v:198632.17-198632.92" + wire $not$libresoc.v:198632$14584_Y + attribute \src "libresoc.v:198626.18-198626.98" + wire $or$libresoc.v:198626$14578_Y + attribute \src "libresoc.v:198628.18-198628.99" + wire $or$libresoc.v:198628$14580_Y + attribute \src "libresoc.v:198631.17-198631.97" + wire $or$libresoc.v:198631$14583_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -425216,11 +416519,11 @@ module \upd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:204102.7-204102.15" + attribute \src "libresoc.v:198590.7-198590.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -425237,7 +416540,7 @@ module \upd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:204137$14806 + cell $and $and$libresoc.v:198625$14577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425245,10 +416548,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:204137$14806_Y + connect \Y $and$libresoc.v:198625$14577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:204142$14811 + cell $and $and$libresoc.v:198630$14582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425256,34 +416559,34 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:204142$14811_Y + connect \Y $and$libresoc.v:198630$14582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:204139$14808 + cell $not $not$libresoc.v:198627$14579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd - connect \Y $not$libresoc.v:204139$14808_Y + connect \Y $not$libresoc.v:198627$14579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:204141$14810 + cell $not $not$libresoc.v:198629$14581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:204141$14810_Y + connect \Y $not$libresoc.v:198629$14581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:204144$14813 + cell $not $not$libresoc.v:198632$14584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:204144$14813_Y + connect \Y $not$libresoc.v:198632$14584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:204138$14807 + cell $or $or$libresoc.v:198626$14578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425291,10 +416594,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd - connect \Y $or$libresoc.v:204138$14807_Y + connect \Y $or$libresoc.v:198626$14578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:204140$14809 + cell $or $or$libresoc.v:198628$14580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425302,10 +416605,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int - connect \Y $or$libresoc.v:204140$14809_Y + connect \Y $or$libresoc.v:198628$14580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:204143$14812 + cell $or $or$libresoc.v:198631$14583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425313,39 +416616,39 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd - connect \Y $or$libresoc.v:204143$14812_Y + connect \Y $or$libresoc.v:198631$14583_Y end - attribute \src "libresoc.v:204102.7-204102.20" - process $proc$libresoc.v:204102$14818 + attribute \src "libresoc.v:198590.7-198590.20" + process $proc$libresoc.v:198590$14589 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:204124.7-204124.19" - process $proc$libresoc.v:204124$14819 + attribute \src "libresoc.v:198612.7-198612.19" + process $proc$libresoc.v:198612$14590 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:204145.3-204146.27" - process $proc$libresoc.v:204145$14814 + attribute \src "libresoc.v:198633.3-198634.27" + process $proc$libresoc.v:198633$14585 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:204147.3-204155.6" - process $proc$libresoc.v:204147$14815 + attribute \src "libresoc.v:198635.3-198643.6" + process $proc$libresoc.v:198635$14586 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14816 $1\q_int$next[0:0]$14817 - attribute \src "libresoc.v:204148.5-204148.29" + assign $0\q_int$next[0:0]$14587 $1\q_int$next[0:0]$14588 + attribute \src "libresoc.v:198636.5-198636.29" switch \initial - attribute \src "libresoc.v:204148.9-204148.17" + attribute \src "libresoc.v:198636.9-198636.17" case 1'1 case end @@ -425354,56 +416657,56 @@ module \upd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14817 1'0 + assign $1\q_int$next[0:0]$14588 1'0 case - assign $1\q_int$next[0:0]$14817 \$5 + assign $1\q_int$next[0:0]$14588 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14816 + update \q_int$next $0\q_int$next[0:0]$14587 end - connect \$9 $and$libresoc.v:204137$14806_Y - connect \$11 $or$libresoc.v:204138$14807_Y - connect \$13 $not$libresoc.v:204139$14808_Y - connect \$15 $or$libresoc.v:204140$14809_Y - connect \$1 $not$libresoc.v:204141$14810_Y - connect \$3 $and$libresoc.v:204142$14811_Y - connect \$5 $or$libresoc.v:204143$14812_Y - connect \$7 $not$libresoc.v:204144$14813_Y + connect \$9 $and$libresoc.v:198625$14577_Y + connect \$11 $or$libresoc.v:198626$14578_Y + connect \$13 $not$libresoc.v:198627$14579_Y + connect \$15 $or$libresoc.v:198628$14580_Y + connect \$1 $not$libresoc.v:198629$14581_Y + connect \$3 $and$libresoc.v:198630$14582_Y + connect \$5 $or$libresoc.v:198631$14583_Y + connect \$7 $not$libresoc.v:198632$14584_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end -attribute \src "libresoc.v:204163.1-204221.10" +attribute \src "libresoc.v:198651.1-198709.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l - attribute \src "libresoc.v:204164.7-204164.20" + attribute \src "libresoc.v:198652.7-198652.20" wire $0\initial[0:0] - attribute \src "libresoc.v:204209.3-204217.6" - wire $0\q_int$next[0:0]$14830 - attribute \src "libresoc.v:204207.3-204208.27" + attribute \src "libresoc.v:198697.3-198705.6" + wire $0\q_int$next[0:0]$14601 + attribute \src "libresoc.v:198695.3-198696.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:204209.3-204217.6" - wire $1\q_int$next[0:0]$14831 - attribute \src "libresoc.v:204186.7-204186.19" + attribute \src "libresoc.v:198697.3-198705.6" + wire $1\q_int$next[0:0]$14602 + attribute \src "libresoc.v:198674.7-198674.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:204199.17-204199.96" - wire $and$libresoc.v:204199$14820_Y - attribute \src "libresoc.v:204204.17-204204.96" - wire $and$libresoc.v:204204$14825_Y - attribute \src "libresoc.v:204201.18-204201.95" - wire $not$libresoc.v:204201$14822_Y - attribute \src "libresoc.v:204203.17-204203.94" - wire $not$libresoc.v:204203$14824_Y - attribute \src "libresoc.v:204206.17-204206.94" - wire $not$libresoc.v:204206$14827_Y - attribute \src "libresoc.v:204200.18-204200.100" - wire $or$libresoc.v:204200$14821_Y - attribute \src "libresoc.v:204202.18-204202.101" - wire $or$libresoc.v:204202$14823_Y - attribute \src "libresoc.v:204205.17-204205.99" - wire $or$libresoc.v:204205$14826_Y + attribute \src "libresoc.v:198687.17-198687.96" + wire $and$libresoc.v:198687$14591_Y + attribute \src "libresoc.v:198692.17-198692.96" + wire $and$libresoc.v:198692$14596_Y + attribute \src "libresoc.v:198689.18-198689.95" + wire $not$libresoc.v:198689$14593_Y + attribute \src "libresoc.v:198691.17-198691.94" + wire $not$libresoc.v:198691$14595_Y + attribute \src "libresoc.v:198694.17-198694.94" + wire $not$libresoc.v:198694$14598_Y + attribute \src "libresoc.v:198688.18-198688.100" + wire $or$libresoc.v:198688$14592_Y + attribute \src "libresoc.v:198690.18-198690.101" + wire $or$libresoc.v:198690$14594_Y + attribute \src "libresoc.v:198693.17-198693.99" + wire $or$libresoc.v:198693$14597_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -425420,11 +416723,11 @@ module \valid_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:204164.7-204164.15" + attribute \src "libresoc.v:198652.7-198652.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -425441,7 +416744,7 @@ module \valid_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:204199$14820 + cell $and $and$libresoc.v:198687$14591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425449,10 +416752,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:204199$14820_Y + connect \Y $and$libresoc.v:198687$14591_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:204204$14825 + cell $and $and$libresoc.v:198692$14596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425460,34 +416763,34 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:204204$14825_Y + connect \Y $and$libresoc.v:198692$14596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:204201$14822 + cell $not $not$libresoc.v:198689$14593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid - connect \Y $not$libresoc.v:204201$14822_Y + connect \Y $not$libresoc.v:198689$14593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:204203$14824 + cell $not $not$libresoc.v:198691$14595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:204203$14824_Y + connect \Y $not$libresoc.v:198691$14595_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:204206$14827 + cell $not $not$libresoc.v:198694$14598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:204206$14827_Y + connect \Y $not$libresoc.v:198694$14598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:204200$14821 + cell $or $or$libresoc.v:198688$14592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425495,10 +416798,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid - connect \Y $or$libresoc.v:204200$14821_Y + connect \Y $or$libresoc.v:198688$14592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:204202$14823 + cell $or $or$libresoc.v:198690$14594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425506,10 +416809,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int - connect \Y $or$libresoc.v:204202$14823_Y + connect \Y $or$libresoc.v:198690$14594_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:204205$14826 + cell $or $or$libresoc.v:198693$14597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425517,39 +416820,39 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid - connect \Y $or$libresoc.v:204205$14826_Y + connect \Y $or$libresoc.v:198693$14597_Y end - attribute \src "libresoc.v:204164.7-204164.20" - process $proc$libresoc.v:204164$14832 + attribute \src "libresoc.v:198652.7-198652.20" + process $proc$libresoc.v:198652$14603 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:204186.7-204186.19" - process $proc$libresoc.v:204186$14833 + attribute \src "libresoc.v:198674.7-198674.19" + process $proc$libresoc.v:198674$14604 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:204207.3-204208.27" - process $proc$libresoc.v:204207$14828 + attribute \src "libresoc.v:198695.3-198696.27" + process $proc$libresoc.v:198695$14599 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:204209.3-204217.6" - process $proc$libresoc.v:204209$14829 + attribute \src "libresoc.v:198697.3-198705.6" + process $proc$libresoc.v:198697$14600 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14830 $1\q_int$next[0:0]$14831 - attribute \src "libresoc.v:204210.5-204210.29" + assign $0\q_int$next[0:0]$14601 $1\q_int$next[0:0]$14602 + attribute \src "libresoc.v:198698.5-198698.29" switch \initial - attribute \src "libresoc.v:204210.9-204210.17" + attribute \src "libresoc.v:198698.9-198698.17" case 1'1 case end @@ -425558,56 +416861,56 @@ module \valid_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14831 1'0 + assign $1\q_int$next[0:0]$14602 1'0 case - assign $1\q_int$next[0:0]$14831 \$5 + assign $1\q_int$next[0:0]$14602 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14830 + update \q_int$next $0\q_int$next[0:0]$14601 end - connect \$9 $and$libresoc.v:204199$14820_Y - connect \$11 $or$libresoc.v:204200$14821_Y - connect \$13 $not$libresoc.v:204201$14822_Y - connect \$15 $or$libresoc.v:204202$14823_Y - connect \$1 $not$libresoc.v:204203$14824_Y - connect \$3 $and$libresoc.v:204204$14825_Y - connect \$5 $or$libresoc.v:204205$14826_Y - connect \$7 $not$libresoc.v:204206$14827_Y + connect \$9 $and$libresoc.v:198687$14591_Y + connect \$11 $or$libresoc.v:198688$14592_Y + connect \$13 $not$libresoc.v:198689$14593_Y + connect \$15 $or$libresoc.v:198690$14594_Y + connect \$1 $not$libresoc.v:198691$14595_Y + connect \$3 $and$libresoc.v:198692$14596_Y + connect \$5 $or$libresoc.v:198693$14597_Y + connect \$7 $not$libresoc.v:198694$14598_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end -attribute \src "libresoc.v:204225.1-204283.10" +attribute \src "libresoc.v:198713.1-198771.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l - attribute \src "libresoc.v:204226.7-204226.20" + attribute \src "libresoc.v:198714.7-198714.20" wire $0\initial[0:0] - attribute \src "libresoc.v:204271.3-204279.6" - wire $0\q_int$next[0:0]$14844 - attribute \src "libresoc.v:204269.3-204270.27" + attribute \src "libresoc.v:198759.3-198767.6" + wire $0\q_int$next[0:0]$14615 + attribute \src "libresoc.v:198757.3-198758.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:204271.3-204279.6" - wire $1\q_int$next[0:0]$14845 - attribute \src "libresoc.v:204248.7-204248.19" + attribute \src "libresoc.v:198759.3-198767.6" + wire $1\q_int$next[0:0]$14616 + attribute \src "libresoc.v:198736.7-198736.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:204261.17-204261.96" - wire $and$libresoc.v:204261$14834_Y - attribute \src "libresoc.v:204266.17-204266.96" - wire $and$libresoc.v:204266$14839_Y - attribute \src "libresoc.v:204263.18-204263.93" - wire $not$libresoc.v:204263$14836_Y - attribute \src "libresoc.v:204265.17-204265.92" - wire $not$libresoc.v:204265$14838_Y - attribute \src "libresoc.v:204268.17-204268.92" - wire $not$libresoc.v:204268$14841_Y - attribute \src "libresoc.v:204262.18-204262.98" - wire $or$libresoc.v:204262$14835_Y - attribute \src "libresoc.v:204264.18-204264.99" - wire $or$libresoc.v:204264$14837_Y - attribute \src "libresoc.v:204267.17-204267.97" - wire $or$libresoc.v:204267$14840_Y + attribute \src "libresoc.v:198749.17-198749.96" + wire $and$libresoc.v:198749$14605_Y + attribute \src "libresoc.v:198754.17-198754.96" + wire $and$libresoc.v:198754$14610_Y + attribute \src "libresoc.v:198751.18-198751.93" + wire $not$libresoc.v:198751$14607_Y + attribute \src "libresoc.v:198753.17-198753.92" + wire $not$libresoc.v:198753$14609_Y + attribute \src "libresoc.v:198756.17-198756.92" + wire $not$libresoc.v:198756$14612_Y + attribute \src "libresoc.v:198750.18-198750.98" + wire $or$libresoc.v:198750$14606_Y + attribute \src "libresoc.v:198752.18-198752.99" + wire $or$libresoc.v:198752$14608_Y + attribute \src "libresoc.v:198755.17-198755.97" + wire $or$libresoc.v:198755$14611_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -425624,11 +416927,11 @@ module \wri_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst - attribute \src "libresoc.v:204226.7-204226.15" + attribute \src "libresoc.v:198714.7-198714.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -425645,7 +416948,7 @@ module \wri_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:204261$14834 + cell $and $and$libresoc.v:198749$14605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425653,10 +416956,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:204261$14834_Y + connect \Y $and$libresoc.v:198749$14605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:204266$14839 + cell $and $and$libresoc.v:198754$14610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425664,34 +416967,34 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:204266$14839_Y + connect \Y $and$libresoc.v:198754$14610_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:204263$14836 + cell $not $not$libresoc.v:198751$14607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri - connect \Y $not$libresoc.v:204263$14836_Y + connect \Y $not$libresoc.v:198751$14607_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:204265$14838 + cell $not $not$libresoc.v:198753$14609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:204265$14838_Y + connect \Y $not$libresoc.v:198753$14609_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:204268$14841 + cell $not $not$libresoc.v:198756$14612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:204268$14841_Y + connect \Y $not$libresoc.v:198756$14612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:204262$14835 + cell $or $or$libresoc.v:198750$14606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425699,10 +417002,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri - connect \Y $or$libresoc.v:204262$14835_Y + connect \Y $or$libresoc.v:198750$14606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:204264$14837 + cell $or $or$libresoc.v:198752$14608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425710,10 +417013,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int - connect \Y $or$libresoc.v:204264$14837_Y + connect \Y $or$libresoc.v:198752$14608_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:204267$14840 + cell $or $or$libresoc.v:198755$14611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -425721,39 +417024,39 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri - connect \Y $or$libresoc.v:204267$14840_Y + connect \Y $or$libresoc.v:198755$14611_Y end - attribute \src "libresoc.v:204226.7-204226.20" - process $proc$libresoc.v:204226$14846 + attribute \src "libresoc.v:198714.7-198714.20" + process $proc$libresoc.v:198714$14617 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:204248.7-204248.19" - process $proc$libresoc.v:204248$14847 + attribute \src "libresoc.v:198736.7-198736.19" + process $proc$libresoc.v:198736$14618 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:204269.3-204270.27" - process $proc$libresoc.v:204269$14842 + attribute \src "libresoc.v:198757.3-198758.27" + process $proc$libresoc.v:198757$14613 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:204271.3-204279.6" - process $proc$libresoc.v:204271$14843 + attribute \src "libresoc.v:198759.3-198767.6" + process $proc$libresoc.v:198759$14614 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14844 $1\q_int$next[0:0]$14845 - attribute \src "libresoc.v:204272.5-204272.29" + assign $0\q_int$next[0:0]$14615 $1\q_int$next[0:0]$14616 + attribute \src "libresoc.v:198760.5-198760.29" switch \initial - attribute \src "libresoc.v:204272.9-204272.17" + attribute \src "libresoc.v:198760.9-198760.17" case 1'1 case end @@ -425762,54 +417065,54 @@ module \wri_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14845 1'0 + assign $1\q_int$next[0:0]$14616 1'0 case - assign $1\q_int$next[0:0]$14845 \$5 + assign $1\q_int$next[0:0]$14616 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14844 + update \q_int$next $0\q_int$next[0:0]$14615 end - connect \$9 $and$libresoc.v:204261$14834_Y - connect \$11 $or$libresoc.v:204262$14835_Y - connect \$13 $not$libresoc.v:204263$14836_Y - connect \$15 $or$libresoc.v:204264$14837_Y - connect \$1 $not$libresoc.v:204265$14838_Y - connect \$3 $and$libresoc.v:204266$14839_Y - connect \$5 $or$libresoc.v:204267$14840_Y - connect \$7 $not$libresoc.v:204268$14841_Y + connect \$9 $and$libresoc.v:198749$14605_Y + connect \$11 $or$libresoc.v:198750$14606_Y + connect \$13 $not$libresoc.v:198751$14607_Y + connect \$15 $or$libresoc.v:198752$14608_Y + connect \$1 $not$libresoc.v:198753$14609_Y + connect \$3 $and$libresoc.v:198754$14610_Y + connect \$5 $or$libresoc.v:198755$14611_Y + connect \$7 $not$libresoc.v:198756$14612_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end -attribute \src "libresoc.v:204287.1-204353.10" +attribute \src "libresoc.v:198775.1-198841.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a - attribute \src "libresoc.v:204332.17-204332.91" - wire $not$libresoc.v:204332$14848_Y - attribute \src "libresoc.v:204334.18-204334.93" - wire $not$libresoc.v:204334$14850_Y - attribute \src "libresoc.v:204336.18-204336.93" - wire $not$libresoc.v:204336$14852_Y - attribute \src "libresoc.v:204337.17-204337.89" - wire width 6 $not$libresoc.v:204337$14853_Y - attribute \src "libresoc.v:204339.18-204339.93" - wire $not$libresoc.v:204339$14855_Y - attribute \src "libresoc.v:204342.17-204342.91" - wire $not$libresoc.v:204342$14858_Y - attribute \src "libresoc.v:204333.18-204333.106" - wire $reduce_or$libresoc.v:204333$14849_Y - attribute \src "libresoc.v:204335.18-204335.106" - wire $reduce_or$libresoc.v:204335$14851_Y - attribute \src "libresoc.v:204338.18-204338.106" - wire $reduce_or$libresoc.v:204338$14854_Y - attribute \src "libresoc.v:204340.18-204340.90" - wire $reduce_or$libresoc.v:204340$14856_Y - attribute \src "libresoc.v:204341.17-204341.103" - wire $reduce_or$libresoc.v:204341$14857_Y - attribute \src "libresoc.v:204343.17-204343.105" - wire $reduce_or$libresoc.v:204343$14859_Y + attribute \src "libresoc.v:198820.17-198820.91" + wire $not$libresoc.v:198820$14619_Y + attribute \src "libresoc.v:198822.18-198822.93" + wire $not$libresoc.v:198822$14621_Y + attribute \src "libresoc.v:198824.18-198824.93" + wire $not$libresoc.v:198824$14623_Y + attribute \src "libresoc.v:198825.17-198825.89" + wire width 6 $not$libresoc.v:198825$14624_Y + attribute \src "libresoc.v:198827.18-198827.93" + wire $not$libresoc.v:198827$14626_Y + attribute \src "libresoc.v:198830.17-198830.91" + wire $not$libresoc.v:198830$14629_Y + attribute \src "libresoc.v:198821.18-198821.106" + wire $reduce_or$libresoc.v:198821$14620_Y + attribute \src "libresoc.v:198823.18-198823.106" + wire $reduce_or$libresoc.v:198823$14622_Y + attribute \src "libresoc.v:198826.18-198826.106" + wire $reduce_or$libresoc.v:198826$14625_Y + attribute \src "libresoc.v:198828.18-198828.90" + wire $reduce_or$libresoc.v:198828$14627_Y + attribute \src "libresoc.v:198829.17-198829.103" + wire $reduce_or$libresoc.v:198829$14628_Y + attribute \src "libresoc.v:198831.17-198831.105" + wire $reduce_or$libresoc.v:198831$14630_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -425855,113 +417158,113 @@ module \wrpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204332$14848 + cell $not $not$libresoc.v:198820$14619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:204332$14848_Y + connect \Y $not$libresoc.v:198820$14619_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204334$14850 + cell $not $not$libresoc.v:198822$14621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:204334$14850_Y + connect \Y $not$libresoc.v:198822$14621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204336$14852 + cell $not $not$libresoc.v:198824$14623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:204336$14852_Y + connect \Y $not$libresoc.v:198824$14623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:204337$14853 + cell $not $not$libresoc.v:198825$14624 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:204337$14853_Y + connect \Y $not$libresoc.v:198825$14624_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204339$14855 + cell $not $not$libresoc.v:198827$14626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:204339$14855_Y + connect \Y $not$libresoc.v:198827$14626_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204342$14858 + cell $not $not$libresoc.v:198830$14629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:204342$14858_Y + connect \Y $not$libresoc.v:198830$14629_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204333$14849 + cell $reduce_or $reduce_or$libresoc.v:198821$14620 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:204333$14849_Y + connect \Y $reduce_or$libresoc.v:198821$14620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204335$14851 + cell $reduce_or $reduce_or$libresoc.v:198823$14622 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:204335$14851_Y + connect \Y $reduce_or$libresoc.v:198823$14622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204338$14854 + cell $reduce_or $reduce_or$libresoc.v:198826$14625 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:204338$14854_Y + connect \Y $reduce_or$libresoc.v:198826$14625_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:204340$14856 + cell $reduce_or $reduce_or$libresoc.v:198828$14627 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:204340$14856_Y + connect \Y $reduce_or$libresoc.v:198828$14627_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204341$14857 + cell $reduce_or $reduce_or$libresoc.v:198829$14628 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:204341$14857_Y + connect \Y $reduce_or$libresoc.v:198829$14628_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204343$14859 + cell $reduce_or $reduce_or$libresoc.v:198831$14630 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:204343$14859_Y - end - connect \$7 $not$libresoc.v:204332$14848_Y - connect \$12 $reduce_or$libresoc.v:204333$14849_Y - connect \$11 $not$libresoc.v:204334$14850_Y - connect \$16 $reduce_or$libresoc.v:204335$14851_Y - connect \$15 $not$libresoc.v:204336$14852_Y - connect \$1 $not$libresoc.v:204337$14853_Y - connect \$20 $reduce_or$libresoc.v:204338$14854_Y - connect \$19 $not$libresoc.v:204339$14855_Y - connect \$23 $reduce_or$libresoc.v:204340$14856_Y - connect \$4 $reduce_or$libresoc.v:204341$14857_Y - connect \$3 $not$libresoc.v:204342$14858_Y - connect \$8 $reduce_or$libresoc.v:204343$14859_Y + connect \Y $reduce_or$libresoc.v:198831$14630_Y + end + connect \$7 $not$libresoc.v:198820$14619_Y + connect \$12 $reduce_or$libresoc.v:198821$14620_Y + connect \$11 $not$libresoc.v:198822$14621_Y + connect \$16 $reduce_or$libresoc.v:198823$14622_Y + connect \$15 $not$libresoc.v:198824$14623_Y + connect \$1 $not$libresoc.v:198825$14624_Y + connect \$20 $reduce_or$libresoc.v:198826$14625_Y + connect \$19 $not$libresoc.v:198827$14626_Y + connect \$23 $reduce_or$libresoc.v:198828$14627_Y + connect \$4 $reduce_or$libresoc.v:198829$14628_Y + connect \$3 $not$libresoc.v:198830$14629_Y + connect \$8 $reduce_or$libresoc.v:198831$14630_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -425972,15 +417275,15 @@ module \wrpick_CR_cr_a connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:204357.1-204378.10" +attribute \src "libresoc.v:198845.1-198866.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr - attribute \src "libresoc.v:204372.17-204372.89" - wire $not$libresoc.v:204372$14860_Y - attribute \src "libresoc.v:204373.17-204373.89" - wire $reduce_or$libresoc.v:204373$14861_Y + attribute \src "libresoc.v:198860.17-198860.89" + wire $not$libresoc.v:198860$14631_Y + attribute \src "libresoc.v:198861.17-198861.89" + wire $reduce_or$libresoc.v:198861$14632_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -425996,53 +417299,53 @@ module \wrpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:204372$14860 + cell $not $not$libresoc.v:198860$14631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:204372$14860_Y + connect \Y $not$libresoc.v:198860$14631_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:204373$14861 + cell $reduce_or $reduce_or$libresoc.v:198861$14632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:204373$14861_Y + connect \Y $reduce_or$libresoc.v:198861$14632_Y end - connect \$1 $not$libresoc.v:204372$14860_Y - connect \$3 $reduce_or$libresoc.v:204373$14861_Y + connect \$1 $not$libresoc.v:198860$14631_Y + connect \$3 $reduce_or$libresoc.v:198861$14632_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:204382.1-204439.10" +attribute \src "libresoc.v:198870.1-198927.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 - attribute \src "libresoc.v:204421.17-204421.91" - wire $not$libresoc.v:204421$14862_Y - attribute \src "libresoc.v:204423.18-204423.93" - wire $not$libresoc.v:204423$14864_Y - attribute \src "libresoc.v:204425.18-204425.93" - wire $not$libresoc.v:204425$14866_Y - attribute \src "libresoc.v:204426.17-204426.89" - wire width 5 $not$libresoc.v:204426$14867_Y - attribute \src "libresoc.v:204429.17-204429.91" - wire $not$libresoc.v:204429$14870_Y - attribute \src "libresoc.v:204422.18-204422.106" - wire $reduce_or$libresoc.v:204422$14863_Y - attribute \src "libresoc.v:204424.18-204424.106" - wire $reduce_or$libresoc.v:204424$14865_Y - attribute \src "libresoc.v:204427.18-204427.90" - wire $reduce_or$libresoc.v:204427$14868_Y - attribute \src "libresoc.v:204428.17-204428.103" - wire $reduce_or$libresoc.v:204428$14869_Y - attribute \src "libresoc.v:204430.17-204430.105" - wire $reduce_or$libresoc.v:204430$14871_Y + attribute \src "libresoc.v:198909.17-198909.91" + wire $not$libresoc.v:198909$14633_Y + attribute \src "libresoc.v:198911.18-198911.93" + wire $not$libresoc.v:198911$14635_Y + attribute \src "libresoc.v:198913.18-198913.93" + wire $not$libresoc.v:198913$14637_Y + attribute \src "libresoc.v:198914.17-198914.89" + wire width 5 $not$libresoc.v:198914$14638_Y + attribute \src "libresoc.v:198917.17-198917.91" + wire $not$libresoc.v:198917$14641_Y + attribute \src "libresoc.v:198910.18-198910.106" + wire $reduce_or$libresoc.v:198910$14634_Y + attribute \src "libresoc.v:198912.18-198912.106" + wire $reduce_or$libresoc.v:198912$14636_Y + attribute \src "libresoc.v:198915.18-198915.90" + wire $reduce_or$libresoc.v:198915$14639_Y + attribute \src "libresoc.v:198916.17-198916.103" + wire $reduce_or$libresoc.v:198916$14640_Y + attribute \src "libresoc.v:198918.17-198918.105" + wire $reduce_or$libresoc.v:198918$14642_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -426082,95 +417385,95 @@ module \wrpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204421$14862 + cell $not $not$libresoc.v:198909$14633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:204421$14862_Y + connect \Y $not$libresoc.v:198909$14633_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204423$14864 + cell $not $not$libresoc.v:198911$14635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:204423$14864_Y + connect \Y $not$libresoc.v:198911$14635_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204425$14866 + cell $not $not$libresoc.v:198913$14637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:204425$14866_Y + connect \Y $not$libresoc.v:198913$14637_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:204426$14867 + cell $not $not$libresoc.v:198914$14638 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:204426$14867_Y + connect \Y $not$libresoc.v:198914$14638_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204429$14870 + cell $not $not$libresoc.v:198917$14641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:204429$14870_Y + connect \Y $not$libresoc.v:198917$14641_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204422$14863 + cell $reduce_or $reduce_or$libresoc.v:198910$14634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:204422$14863_Y + connect \Y $reduce_or$libresoc.v:198910$14634_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204424$14865 + cell $reduce_or $reduce_or$libresoc.v:198912$14636 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:204424$14865_Y + connect \Y $reduce_or$libresoc.v:198912$14636_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:204427$14868 + cell $reduce_or $reduce_or$libresoc.v:198915$14639 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:204427$14868_Y + connect \Y $reduce_or$libresoc.v:198915$14639_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204428$14869 + cell $reduce_or $reduce_or$libresoc.v:198916$14640 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:204428$14869_Y + connect \Y $reduce_or$libresoc.v:198916$14640_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204430$14871 + cell $reduce_or $reduce_or$libresoc.v:198918$14642 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:204430$14871_Y - end - connect \$7 $not$libresoc.v:204421$14862_Y - connect \$12 $reduce_or$libresoc.v:204422$14863_Y - connect \$11 $not$libresoc.v:204423$14864_Y - connect \$16 $reduce_or$libresoc.v:204424$14865_Y - connect \$15 $not$libresoc.v:204425$14866_Y - connect \$1 $not$libresoc.v:204426$14867_Y - connect \$19 $reduce_or$libresoc.v:204427$14868_Y - connect \$4 $reduce_or$libresoc.v:204428$14869_Y - connect \$3 $not$libresoc.v:204429$14870_Y - connect \$8 $reduce_or$libresoc.v:204430$14871_Y + connect \Y $reduce_or$libresoc.v:198918$14642_Y + end + connect \$7 $not$libresoc.v:198909$14633_Y + connect \$12 $reduce_or$libresoc.v:198910$14634_Y + connect \$11 $not$libresoc.v:198911$14635_Y + connect \$16 $reduce_or$libresoc.v:198912$14636_Y + connect \$15 $not$libresoc.v:198913$14637_Y + connect \$1 $not$libresoc.v:198914$14638_Y + connect \$19 $reduce_or$libresoc.v:198915$14639_Y + connect \$4 $reduce_or$libresoc.v:198916$14640_Y + connect \$3 $not$libresoc.v:198917$14641_Y + connect \$8 $reduce_or$libresoc.v:198918$14642_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -426180,51 +417483,51 @@ module \wrpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:204443.1-204545.10" +attribute \src "libresoc.v:198931.1-199033.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o - attribute \src "libresoc.v:204512.17-204512.91" - wire $not$libresoc.v:204512$14872_Y - attribute \src "libresoc.v:204514.18-204514.93" - wire $not$libresoc.v:204514$14874_Y - attribute \src "libresoc.v:204516.18-204516.93" - wire $not$libresoc.v:204516$14876_Y - attribute \src "libresoc.v:204517.17-204517.89" - wire width 10 $not$libresoc.v:204517$14877_Y - attribute \src "libresoc.v:204519.18-204519.93" - wire $not$libresoc.v:204519$14879_Y - attribute \src "libresoc.v:204521.18-204521.93" - wire $not$libresoc.v:204521$14881_Y - attribute \src "libresoc.v:204523.18-204523.93" - wire $not$libresoc.v:204523$14883_Y - attribute \src "libresoc.v:204525.18-204525.93" - wire $not$libresoc.v:204525$14885_Y - attribute \src "libresoc.v:204527.18-204527.93" - wire $not$libresoc.v:204527$14887_Y - attribute \src "libresoc.v:204530.17-204530.91" - wire $not$libresoc.v:204530$14890_Y - attribute \src "libresoc.v:204513.18-204513.106" - wire $reduce_or$libresoc.v:204513$14873_Y - attribute \src "libresoc.v:204515.18-204515.106" - wire $reduce_or$libresoc.v:204515$14875_Y - attribute \src "libresoc.v:204518.18-204518.106" - wire $reduce_or$libresoc.v:204518$14878_Y - attribute \src "libresoc.v:204520.18-204520.106" - wire $reduce_or$libresoc.v:204520$14880_Y - attribute \src "libresoc.v:204522.18-204522.106" - wire $reduce_or$libresoc.v:204522$14882_Y - attribute \src "libresoc.v:204524.18-204524.106" - wire $reduce_or$libresoc.v:204524$14884_Y - attribute \src "libresoc.v:204526.18-204526.106" - wire $reduce_or$libresoc.v:204526$14886_Y - attribute \src "libresoc.v:204528.18-204528.90" - wire $reduce_or$libresoc.v:204528$14888_Y - attribute \src "libresoc.v:204529.17-204529.103" - wire $reduce_or$libresoc.v:204529$14889_Y - attribute \src "libresoc.v:204531.17-204531.105" - wire $reduce_or$libresoc.v:204531$14891_Y + attribute \src "libresoc.v:199000.17-199000.91" + wire $not$libresoc.v:199000$14643_Y + attribute \src "libresoc.v:199002.18-199002.93" + wire $not$libresoc.v:199002$14645_Y + attribute \src "libresoc.v:199004.18-199004.93" + wire $not$libresoc.v:199004$14647_Y + attribute \src "libresoc.v:199005.17-199005.89" + wire width 10 $not$libresoc.v:199005$14648_Y + attribute \src "libresoc.v:199007.18-199007.93" + wire $not$libresoc.v:199007$14650_Y + attribute \src "libresoc.v:199009.18-199009.93" + wire $not$libresoc.v:199009$14652_Y + attribute \src "libresoc.v:199011.18-199011.93" + wire $not$libresoc.v:199011$14654_Y + attribute \src "libresoc.v:199013.18-199013.93" + wire $not$libresoc.v:199013$14656_Y + attribute \src "libresoc.v:199015.18-199015.93" + wire $not$libresoc.v:199015$14658_Y + attribute \src "libresoc.v:199018.17-199018.91" + wire $not$libresoc.v:199018$14661_Y + attribute \src "libresoc.v:199001.18-199001.106" + wire $reduce_or$libresoc.v:199001$14644_Y + attribute \src "libresoc.v:199003.18-199003.106" + wire $reduce_or$libresoc.v:199003$14646_Y + attribute \src "libresoc.v:199006.18-199006.106" + wire $reduce_or$libresoc.v:199006$14649_Y + attribute \src "libresoc.v:199008.18-199008.106" + wire $reduce_or$libresoc.v:199008$14651_Y + attribute \src "libresoc.v:199010.18-199010.106" + wire $reduce_or$libresoc.v:199010$14653_Y + attribute \src "libresoc.v:199012.18-199012.106" + wire $reduce_or$libresoc.v:199012$14655_Y + attribute \src "libresoc.v:199014.18-199014.106" + wire $reduce_or$libresoc.v:199014$14657_Y + attribute \src "libresoc.v:199016.18-199016.90" + wire $reduce_or$libresoc.v:199016$14659_Y + attribute \src "libresoc.v:199017.17-199017.103" + wire $reduce_or$libresoc.v:199017$14660_Y + attribute \src "libresoc.v:199019.17-199019.105" + wire $reduce_or$libresoc.v:199019$14662_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 10 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -426294,185 +417597,185 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204512$14872 + cell $not $not$libresoc.v:199000$14643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:204512$14872_Y + connect \Y $not$libresoc.v:199000$14643_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204514$14874 + cell $not $not$libresoc.v:199002$14645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:204514$14874_Y + connect \Y $not$libresoc.v:199002$14645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204516$14876 + cell $not $not$libresoc.v:199004$14647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:204516$14876_Y + connect \Y $not$libresoc.v:199004$14647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:204517$14877 + cell $not $not$libresoc.v:199005$14648 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i - connect \Y $not$libresoc.v:204517$14877_Y + connect \Y $not$libresoc.v:199005$14648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204519$14879 + cell $not $not$libresoc.v:199007$14650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:204519$14879_Y + connect \Y $not$libresoc.v:199007$14650_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204521$14881 + cell $not $not$libresoc.v:199009$14652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:204521$14881_Y + connect \Y $not$libresoc.v:199009$14652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204523$14883 + cell $not $not$libresoc.v:199011$14654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:204523$14883_Y + connect \Y $not$libresoc.v:199011$14654_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204525$14885 + cell $not $not$libresoc.v:199013$14656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:204525$14885_Y + connect \Y $not$libresoc.v:199013$14656_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204527$14887 + cell $not $not$libresoc.v:199015$14658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:204527$14887_Y + connect \Y $not$libresoc.v:199015$14658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204530$14890 + cell $not $not$libresoc.v:199018$14661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:204530$14890_Y + connect \Y $not$libresoc.v:199018$14661_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204513$14873 + cell $reduce_or $reduce_or$libresoc.v:199001$14644 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:204513$14873_Y + connect \Y $reduce_or$libresoc.v:199001$14644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204515$14875 + cell $reduce_or $reduce_or$libresoc.v:199003$14646 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:204515$14875_Y + connect \Y $reduce_or$libresoc.v:199003$14646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204518$14878 + cell $reduce_or $reduce_or$libresoc.v:199006$14649 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:204518$14878_Y + connect \Y $reduce_or$libresoc.v:199006$14649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204520$14880 + cell $reduce_or $reduce_or$libresoc.v:199008$14651 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:204520$14880_Y + connect \Y $reduce_or$libresoc.v:199008$14651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204522$14882 + cell $reduce_or $reduce_or$libresoc.v:199010$14653 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:204522$14882_Y + connect \Y $reduce_or$libresoc.v:199010$14653_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204524$14884 + cell $reduce_or $reduce_or$libresoc.v:199012$14655 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:204524$14884_Y + connect \Y $reduce_or$libresoc.v:199012$14655_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204526$14886 + cell $reduce_or $reduce_or$libresoc.v:199014$14657 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:204526$14886_Y + connect \Y $reduce_or$libresoc.v:199014$14657_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:204528$14888 + cell $reduce_or $reduce_or$libresoc.v:199016$14659 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:204528$14888_Y + connect \Y $reduce_or$libresoc.v:199016$14659_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204529$14889 + cell $reduce_or $reduce_or$libresoc.v:199017$14660 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:204529$14889_Y + connect \Y $reduce_or$libresoc.v:199017$14660_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204531$14891 + cell $reduce_or $reduce_or$libresoc.v:199019$14662 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:204531$14891_Y - end - connect \$7 $not$libresoc.v:204512$14872_Y - connect \$12 $reduce_or$libresoc.v:204513$14873_Y - connect \$11 $not$libresoc.v:204514$14874_Y - connect \$16 $reduce_or$libresoc.v:204515$14875_Y - connect \$15 $not$libresoc.v:204516$14876_Y - connect \$1 $not$libresoc.v:204517$14877_Y - connect \$20 $reduce_or$libresoc.v:204518$14878_Y - connect \$19 $not$libresoc.v:204519$14879_Y - connect \$24 $reduce_or$libresoc.v:204520$14880_Y - connect \$23 $not$libresoc.v:204521$14881_Y - connect \$28 $reduce_or$libresoc.v:204522$14882_Y - connect \$27 $not$libresoc.v:204523$14883_Y - connect \$32 $reduce_or$libresoc.v:204524$14884_Y - connect \$31 $not$libresoc.v:204525$14885_Y - connect \$36 $reduce_or$libresoc.v:204526$14886_Y - connect \$35 $not$libresoc.v:204527$14887_Y - connect \$39 $reduce_or$libresoc.v:204528$14888_Y - connect \$4 $reduce_or$libresoc.v:204529$14889_Y - connect \$3 $not$libresoc.v:204530$14890_Y - connect \$8 $reduce_or$libresoc.v:204531$14891_Y + connect \Y $reduce_or$libresoc.v:199019$14662_Y + end + connect \$7 $not$libresoc.v:199000$14643_Y + connect \$12 $reduce_or$libresoc.v:199001$14644_Y + connect \$11 $not$libresoc.v:199002$14645_Y + connect \$16 $reduce_or$libresoc.v:199003$14646_Y + connect \$15 $not$libresoc.v:199004$14647_Y + connect \$1 $not$libresoc.v:199005$14648_Y + connect \$20 $reduce_or$libresoc.v:199006$14649_Y + connect \$19 $not$libresoc.v:199007$14650_Y + connect \$24 $reduce_or$libresoc.v:199008$14651_Y + connect \$23 $not$libresoc.v:199009$14652_Y + connect \$28 $reduce_or$libresoc.v:199010$14653_Y + connect \$27 $not$libresoc.v:199011$14654_Y + connect \$32 $reduce_or$libresoc.v:199012$14655_Y + connect \$31 $not$libresoc.v:199013$14656_Y + connect \$36 $reduce_or$libresoc.v:199014$14657_Y + connect \$35 $not$libresoc.v:199015$14658_Y + connect \$39 $reduce_or$libresoc.v:199016$14659_Y + connect \$4 $reduce_or$libresoc.v:199017$14660_Y + connect \$3 $not$libresoc.v:199018$14661_Y + connect \$8 $reduce_or$libresoc.v:199019$14662_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 @@ -426487,15 +417790,15 @@ module \wrpick_INT_o connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:204549.1-204570.10" +attribute \src "libresoc.v:199037.1-199058.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 - attribute \src "libresoc.v:204564.17-204564.89" - wire $not$libresoc.v:204564$14892_Y - attribute \src "libresoc.v:204565.17-204565.89" - wire $reduce_or$libresoc.v:204565$14893_Y + attribute \src "libresoc.v:199052.17-199052.89" + wire $not$libresoc.v:199052$14663_Y + attribute \src "libresoc.v:199053.17-199053.89" + wire $reduce_or$libresoc.v:199053$14664_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -426511,37 +417814,37 @@ module \wrpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:204564$14892 + cell $not $not$libresoc.v:199052$14663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:204564$14892_Y + connect \Y $not$libresoc.v:199052$14663_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:204565$14893 + cell $reduce_or $reduce_or$libresoc.v:199053$14664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:204565$14893_Y + connect \Y $reduce_or$libresoc.v:199053$14664_Y end - connect \$1 $not$libresoc.v:204564$14892_Y - connect \$3 $reduce_or$libresoc.v:204565$14893_Y + connect \$1 $not$libresoc.v:199052$14663_Y + connect \$3 $reduce_or$libresoc.v:199053$14664_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:204574.1-204595.10" +attribute \src "libresoc.v:199062.1-199083.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr - attribute \src "libresoc.v:204589.17-204589.89" - wire $not$libresoc.v:204589$14894_Y - attribute \src "libresoc.v:204590.17-204590.89" - wire $reduce_or$libresoc.v:204590$14895_Y + attribute \src "libresoc.v:199077.17-199077.89" + wire $not$libresoc.v:199077$14665_Y + attribute \src "libresoc.v:199078.17-199078.89" + wire $reduce_or$libresoc.v:199078$14666_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -426557,41 +417860,41 @@ module \wrpick_STATE_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:204589$14894 + cell $not $not$libresoc.v:199077$14665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:204589$14894_Y + connect \Y $not$libresoc.v:199077$14665_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:204590$14895 + cell $reduce_or $reduce_or$libresoc.v:199078$14666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:204590$14895_Y + connect \Y $reduce_or$libresoc.v:199078$14666_Y end - connect \$1 $not$libresoc.v:204589$14894_Y - connect \$3 $reduce_or$libresoc.v:204590$14895_Y + connect \$1 $not$libresoc.v:199077$14665_Y + connect \$3 $reduce_or$libresoc.v:199078$14666_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:204599.1-204629.10" +attribute \src "libresoc.v:199087.1-199117.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia - attribute \src "libresoc.v:204620.17-204620.89" - wire width 2 $not$libresoc.v:204620$14896_Y - attribute \src "libresoc.v:204622.17-204622.91" - wire $not$libresoc.v:204622$14898_Y - attribute \src "libresoc.v:204621.17-204621.103" - wire $reduce_or$libresoc.v:204621$14897_Y - attribute \src "libresoc.v:204623.17-204623.89" - wire $reduce_or$libresoc.v:204623$14899_Y + attribute \src "libresoc.v:199108.17-199108.89" + wire width 2 $not$libresoc.v:199108$14667_Y + attribute \src "libresoc.v:199110.17-199110.91" + wire $not$libresoc.v:199110$14669_Y + attribute \src "libresoc.v:199109.17-199109.103" + wire $reduce_or$libresoc.v:199109$14668_Y + attribute \src "libresoc.v:199111.17-199111.89" + wire $reduce_or$libresoc.v:199111$14670_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -426613,64 +417916,64 @@ module \wrpick_STATE_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:204620$14896 + cell $not $not$libresoc.v:199108$14667 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:204620$14896_Y + connect \Y $not$libresoc.v:199108$14667_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204622$14898 + cell $not $not$libresoc.v:199110$14669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:204622$14898_Y + connect \Y $not$libresoc.v:199110$14669_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204621$14897 + cell $reduce_or $reduce_or$libresoc.v:199109$14668 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:204621$14897_Y + connect \Y $reduce_or$libresoc.v:199109$14668_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:204623$14899 + cell $reduce_or $reduce_or$libresoc.v:199111$14670 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:204623$14899_Y + connect \Y $reduce_or$libresoc.v:199111$14670_Y end - connect \$1 $not$libresoc.v:204620$14896_Y - connect \$4 $reduce_or$libresoc.v:204621$14897_Y - connect \$3 $not$libresoc.v:204622$14898_Y - connect \$7 $reduce_or$libresoc.v:204623$14899_Y + connect \$1 $not$libresoc.v:199108$14667_Y + connect \$4 $reduce_or$libresoc.v:199109$14668_Y + connect \$3 $not$libresoc.v:199110$14669_Y + connect \$7 $reduce_or$libresoc.v:199111$14670_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:204633.1-204672.10" +attribute \src "libresoc.v:199121.1-199160.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca - attribute \src "libresoc.v:204660.17-204660.91" - wire $not$libresoc.v:204660$14900_Y - attribute \src "libresoc.v:204662.17-204662.89" - wire width 3 $not$libresoc.v:204662$14902_Y - attribute \src "libresoc.v:204664.17-204664.91" - wire $not$libresoc.v:204664$14904_Y - attribute \src "libresoc.v:204661.18-204661.90" - wire $reduce_or$libresoc.v:204661$14901_Y - attribute \src "libresoc.v:204663.17-204663.103" - wire $reduce_or$libresoc.v:204663$14903_Y - attribute \src "libresoc.v:204665.17-204665.105" - wire $reduce_or$libresoc.v:204665$14905_Y + attribute \src "libresoc.v:199148.17-199148.91" + wire $not$libresoc.v:199148$14671_Y + attribute \src "libresoc.v:199150.17-199150.89" + wire width 3 $not$libresoc.v:199150$14673_Y + attribute \src "libresoc.v:199152.17-199152.91" + wire $not$libresoc.v:199152$14675_Y + attribute \src "libresoc.v:199149.18-199149.90" + wire $reduce_or$libresoc.v:199149$14672_Y + attribute \src "libresoc.v:199151.17-199151.103" + wire $reduce_or$libresoc.v:199151$14674_Y + attribute \src "libresoc.v:199153.17-199153.105" + wire $reduce_or$libresoc.v:199153$14676_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -426698,59 +418001,59 @@ module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204660$14900 + cell $not $not$libresoc.v:199148$14671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:204660$14900_Y + connect \Y $not$libresoc.v:199148$14671_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:204662$14902 + cell $not $not$libresoc.v:199150$14673 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:204662$14902_Y + connect \Y $not$libresoc.v:199150$14673_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204664$14904 + cell $not $not$libresoc.v:199152$14675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:204664$14904_Y + connect \Y $not$libresoc.v:199152$14675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:204661$14901 + cell $reduce_or $reduce_or$libresoc.v:199149$14672 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:204661$14901_Y + connect \Y $reduce_or$libresoc.v:199149$14672_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204663$14903 + cell $reduce_or $reduce_or$libresoc.v:199151$14674 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:204663$14903_Y + connect \Y $reduce_or$libresoc.v:199151$14674_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204665$14905 + cell $reduce_or $reduce_or$libresoc.v:199153$14676 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:204665$14905_Y - end - connect \$7 $not$libresoc.v:204660$14900_Y - connect \$11 $reduce_or$libresoc.v:204661$14901_Y - connect \$1 $not$libresoc.v:204662$14902_Y - connect \$4 $reduce_or$libresoc.v:204663$14903_Y - connect \$3 $not$libresoc.v:204664$14904_Y - connect \$8 $reduce_or$libresoc.v:204665$14905_Y + connect \Y $reduce_or$libresoc.v:199153$14676_Y + end + connect \$7 $not$libresoc.v:199148$14671_Y + connect \$11 $reduce_or$libresoc.v:199149$14672_Y + connect \$1 $not$libresoc.v:199150$14673_Y + connect \$4 $reduce_or$libresoc.v:199151$14674_Y + connect \$3 $not$libresoc.v:199152$14675_Y + connect \$8 $reduce_or$libresoc.v:199153$14676_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -426758,27 +418061,27 @@ module \wrpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:204676.1-204724.10" +attribute \src "libresoc.v:199164.1-199212.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov - attribute \src "libresoc.v:204709.17-204709.91" - wire $not$libresoc.v:204709$14906_Y - attribute \src "libresoc.v:204711.18-204711.93" - wire $not$libresoc.v:204711$14908_Y - attribute \src "libresoc.v:204713.17-204713.89" - wire width 4 $not$libresoc.v:204713$14910_Y - attribute \src "libresoc.v:204715.17-204715.91" - wire $not$libresoc.v:204715$14912_Y - attribute \src "libresoc.v:204710.18-204710.106" - wire $reduce_or$libresoc.v:204710$14907_Y - attribute \src "libresoc.v:204712.18-204712.90" - wire $reduce_or$libresoc.v:204712$14909_Y - attribute \src "libresoc.v:204714.17-204714.103" - wire $reduce_or$libresoc.v:204714$14911_Y - attribute \src "libresoc.v:204716.17-204716.105" - wire $reduce_or$libresoc.v:204716$14913_Y + attribute \src "libresoc.v:199197.17-199197.91" + wire $not$libresoc.v:199197$14677_Y + attribute \src "libresoc.v:199199.18-199199.93" + wire $not$libresoc.v:199199$14679_Y + attribute \src "libresoc.v:199201.17-199201.89" + wire width 4 $not$libresoc.v:199201$14681_Y + attribute \src "libresoc.v:199203.17-199203.91" + wire $not$libresoc.v:199203$14683_Y + attribute \src "libresoc.v:199198.18-199198.106" + wire $reduce_or$libresoc.v:199198$14678_Y + attribute \src "libresoc.v:199200.18-199200.90" + wire $reduce_or$libresoc.v:199200$14680_Y + attribute \src "libresoc.v:199202.17-199202.103" + wire $reduce_or$libresoc.v:199202$14682_Y + attribute \src "libresoc.v:199204.17-199204.105" + wire $reduce_or$libresoc.v:199204$14684_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -426812,77 +418115,77 @@ module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204709$14906 + cell $not $not$libresoc.v:199197$14677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:204709$14906_Y + connect \Y $not$libresoc.v:199197$14677_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204711$14908 + cell $not $not$libresoc.v:199199$14679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:204711$14908_Y + connect \Y $not$libresoc.v:199199$14679_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:204713$14910 + cell $not $not$libresoc.v:199201$14681 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:204713$14910_Y + connect \Y $not$libresoc.v:199201$14681_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204715$14912 + cell $not $not$libresoc.v:199203$14683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:204715$14912_Y + connect \Y $not$libresoc.v:199203$14683_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204710$14907 + cell $reduce_or $reduce_or$libresoc.v:199198$14678 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:204710$14907_Y + connect \Y $reduce_or$libresoc.v:199198$14678_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:204712$14909 + cell $reduce_or $reduce_or$libresoc.v:199200$14680 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:204712$14909_Y + connect \Y $reduce_or$libresoc.v:199200$14680_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204714$14911 + cell $reduce_or $reduce_or$libresoc.v:199202$14682 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:204714$14911_Y + connect \Y $reduce_or$libresoc.v:199202$14682_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204716$14913 + cell $reduce_or $reduce_or$libresoc.v:199204$14684 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:204716$14913_Y - end - connect \$7 $not$libresoc.v:204709$14906_Y - connect \$12 $reduce_or$libresoc.v:204710$14907_Y - connect \$11 $not$libresoc.v:204711$14908_Y - connect \$15 $reduce_or$libresoc.v:204712$14909_Y - connect \$1 $not$libresoc.v:204713$14910_Y - connect \$4 $reduce_or$libresoc.v:204714$14911_Y - connect \$3 $not$libresoc.v:204715$14912_Y - connect \$8 $reduce_or$libresoc.v:204716$14913_Y + connect \Y $reduce_or$libresoc.v:199204$14684_Y + end + connect \$7 $not$libresoc.v:199197$14677_Y + connect \$12 $reduce_or$libresoc.v:199198$14678_Y + connect \$11 $not$libresoc.v:199199$14679_Y + connect \$15 $reduce_or$libresoc.v:199200$14680_Y + connect \$1 $not$libresoc.v:199201$14681_Y + connect \$4 $reduce_or$libresoc.v:199202$14682_Y + connect \$3 $not$libresoc.v:199203$14683_Y + connect \$8 $reduce_or$libresoc.v:199204$14684_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -426891,27 +418194,27 @@ module \wrpick_XER_xer_ov connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:204728.1-204776.10" +attribute \src "libresoc.v:199216.1-199264.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so - attribute \src "libresoc.v:204761.17-204761.91" - wire $not$libresoc.v:204761$14914_Y - attribute \src "libresoc.v:204763.18-204763.93" - wire $not$libresoc.v:204763$14916_Y - attribute \src "libresoc.v:204765.17-204765.89" - wire width 4 $not$libresoc.v:204765$14918_Y - attribute \src "libresoc.v:204767.17-204767.91" - wire $not$libresoc.v:204767$14920_Y - attribute \src "libresoc.v:204762.18-204762.106" - wire $reduce_or$libresoc.v:204762$14915_Y - attribute \src "libresoc.v:204764.18-204764.90" - wire $reduce_or$libresoc.v:204764$14917_Y - attribute \src "libresoc.v:204766.17-204766.103" - wire $reduce_or$libresoc.v:204766$14919_Y - attribute \src "libresoc.v:204768.17-204768.105" - wire $reduce_or$libresoc.v:204768$14921_Y + attribute \src "libresoc.v:199249.17-199249.91" + wire $not$libresoc.v:199249$14685_Y + attribute \src "libresoc.v:199251.18-199251.93" + wire $not$libresoc.v:199251$14687_Y + attribute \src "libresoc.v:199253.17-199253.89" + wire width 4 $not$libresoc.v:199253$14689_Y + attribute \src "libresoc.v:199255.17-199255.91" + wire $not$libresoc.v:199255$14691_Y + attribute \src "libresoc.v:199250.18-199250.106" + wire $reduce_or$libresoc.v:199250$14686_Y + attribute \src "libresoc.v:199252.18-199252.90" + wire $reduce_or$libresoc.v:199252$14688_Y + attribute \src "libresoc.v:199254.17-199254.103" + wire $reduce_or$libresoc.v:199254$14690_Y + attribute \src "libresoc.v:199256.17-199256.105" + wire $reduce_or$libresoc.v:199256$14692_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -426945,77 +418248,77 @@ module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204761$14914 + cell $not $not$libresoc.v:199249$14685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:204761$14914_Y + connect \Y $not$libresoc.v:199249$14685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204763$14916 + cell $not $not$libresoc.v:199251$14687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:204763$14916_Y + connect \Y $not$libresoc.v:199251$14687_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:204765$14918 + cell $not $not$libresoc.v:199253$14689 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:204765$14918_Y + connect \Y $not$libresoc.v:199253$14689_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:204767$14920 + cell $not $not$libresoc.v:199255$14691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:204767$14920_Y + connect \Y $not$libresoc.v:199255$14691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204762$14915 + cell $reduce_or $reduce_or$libresoc.v:199250$14686 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:204762$14915_Y + connect \Y $reduce_or$libresoc.v:199250$14686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:204764$14917 + cell $reduce_or $reduce_or$libresoc.v:199252$14688 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:204764$14917_Y + connect \Y $reduce_or$libresoc.v:199252$14688_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204766$14919 + cell $reduce_or $reduce_or$libresoc.v:199254$14690 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:204766$14919_Y + connect \Y $reduce_or$libresoc.v:199254$14690_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:204768$14921 + cell $reduce_or $reduce_or$libresoc.v:199256$14692 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:204768$14921_Y - end - connect \$7 $not$libresoc.v:204761$14914_Y - connect \$12 $reduce_or$libresoc.v:204762$14915_Y - connect \$11 $not$libresoc.v:204763$14916_Y - connect \$15 $reduce_or$libresoc.v:204764$14917_Y - connect \$1 $not$libresoc.v:204765$14918_Y - connect \$4 $reduce_or$libresoc.v:204766$14919_Y - connect \$3 $not$libresoc.v:204767$14920_Y - connect \$8 $reduce_or$libresoc.v:204768$14921_Y + connect \Y $reduce_or$libresoc.v:199256$14692_Y + end + connect \$7 $not$libresoc.v:199249$14685_Y + connect \$12 $reduce_or$libresoc.v:199250$14686_Y + connect \$11 $not$libresoc.v:199251$14687_Y + connect \$15 $reduce_or$libresoc.v:199252$14688_Y + connect \$1 $not$libresoc.v:199253$14689_Y + connect \$4 $reduce_or$libresoc.v:199254$14690_Y + connect \$3 $not$libresoc.v:199255$14691_Y + connect \$8 $reduce_or$libresoc.v:199256$14692_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -427024,67 +418327,67 @@ module \wrpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:204780.1-205100.10" +attribute \src "libresoc.v:199268.1-199588.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer - attribute \src "libresoc.v:204781.7-204781.20" + attribute \src "libresoc.v:199269.7-199269.20" wire $0\initial[0:0] - attribute \src "libresoc.v:205060.3-205068.6" - wire width 3 $0\ren_delay$11$next[2:0]$14945 - attribute \src "libresoc.v:204958.3-204959.43" - wire width 3 $0\ren_delay$11[2:0]$14934 - attribute \src "libresoc.v:204917.13-204917.34" - wire width 3 $0\ren_delay$11[2:0]$14951 - attribute \src "libresoc.v:205022.3-205030.6" - wire width 3 $0\ren_delay$18$next[2:0]$14937 - attribute \src "libresoc.v:204956.3-204957.43" - wire width 3 $0\ren_delay$18[2:0]$14932 - attribute \src "libresoc.v:204921.13-204921.34" - wire width 3 $0\ren_delay$18[2:0]$14953 - attribute \src "libresoc.v:205041.3-205049.6" - wire width 3 $0\ren_delay$next[2:0]$14941 - attribute \src "libresoc.v:204960.3-204961.35" + attribute \src "libresoc.v:199548.3-199556.6" + wire width 3 $0\ren_delay$11$next[2:0]$14716 + attribute \src "libresoc.v:199446.3-199447.43" + wire width 3 $0\ren_delay$11[2:0]$14705 + attribute \src "libresoc.v:199405.13-199405.34" + wire width 3 $0\ren_delay$11[2:0]$14722 + attribute \src "libresoc.v:199510.3-199518.6" + wire width 3 $0\ren_delay$18$next[2:0]$14708 + attribute \src "libresoc.v:199444.3-199445.43" + wire width 3 $0\ren_delay$18[2:0]$14703 + attribute \src "libresoc.v:199409.13-199409.34" + wire width 3 $0\ren_delay$18[2:0]$14724 + attribute \src "libresoc.v:199529.3-199537.6" + wire width 3 $0\ren_delay$next[2:0]$14712 + attribute \src "libresoc.v:199448.3-199449.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:205050.3-205059.6" + attribute \src "libresoc.v:199538.3-199547.6" wire width 2 $0\src1__data_o[1:0] - attribute \src "libresoc.v:205069.3-205078.6" + attribute \src "libresoc.v:199557.3-199566.6" wire width 2 $0\src2__data_o[1:0] - attribute \src "libresoc.v:205031.3-205040.6" + attribute \src "libresoc.v:199519.3-199528.6" wire width 2 $0\src3__data_o[1:0] - attribute \src "libresoc.v:205060.3-205068.6" - wire width 3 $1\ren_delay$11$next[2:0]$14946 - attribute \src "libresoc.v:205022.3-205030.6" - wire width 3 $1\ren_delay$18$next[2:0]$14938 - attribute \src "libresoc.v:205041.3-205049.6" - wire width 3 $1\ren_delay$next[2:0]$14942 - attribute \src "libresoc.v:204915.13-204915.29" + attribute \src "libresoc.v:199548.3-199556.6" + wire width 3 $1\ren_delay$11$next[2:0]$14717 + attribute \src "libresoc.v:199510.3-199518.6" + wire width 3 $1\ren_delay$18$next[2:0]$14709 + attribute \src "libresoc.v:199529.3-199537.6" + wire width 3 $1\ren_delay$next[2:0]$14713 + attribute \src "libresoc.v:199403.13-199403.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:205050.3-205059.6" + attribute \src "libresoc.v:199538.3-199547.6" wire width 2 $1\src1__data_o[1:0] - attribute \src "libresoc.v:205069.3-205078.6" + attribute \src "libresoc.v:199557.3-199566.6" wire width 2 $1\src2__data_o[1:0] - attribute \src "libresoc.v:205031.3-205040.6" + attribute \src "libresoc.v:199519.3-199528.6" wire width 2 $1\src3__data_o[1:0] - attribute \src "libresoc.v:204947.17-204947.109" - wire width 2 $or$libresoc.v:204947$14922_Y - attribute \src "libresoc.v:204949.18-204949.126" - wire width 2 $or$libresoc.v:204949$14924_Y - attribute \src "libresoc.v:204950.18-204950.111" - wire width 2 $or$libresoc.v:204950$14925_Y - attribute \src "libresoc.v:204952.18-204952.126" - wire width 2 $or$libresoc.v:204952$14927_Y - attribute \src "libresoc.v:204953.18-204953.111" - wire width 2 $or$libresoc.v:204953$14928_Y - attribute \src "libresoc.v:204955.17-204955.125" - wire width 2 $or$libresoc.v:204955$14930_Y - attribute \src "libresoc.v:204948.18-204948.100" - wire $reduce_or$libresoc.v:204948$14923_Y - attribute \src "libresoc.v:204951.18-204951.100" - wire $reduce_or$libresoc.v:204951$14926_Y - attribute \src "libresoc.v:204954.17-204954.95" - wire $reduce_or$libresoc.v:204954$14929_Y + attribute \src "libresoc.v:199435.17-199435.109" + wire width 2 $or$libresoc.v:199435$14693_Y + attribute \src "libresoc.v:199437.18-199437.126" + wire width 2 $or$libresoc.v:199437$14695_Y + attribute \src "libresoc.v:199438.18-199438.111" + wire width 2 $or$libresoc.v:199438$14696_Y + attribute \src "libresoc.v:199440.18-199440.126" + wire width 2 $or$libresoc.v:199440$14698_Y + attribute \src "libresoc.v:199441.18-199441.111" + wire width 2 $or$libresoc.v:199441$14699_Y + attribute \src "libresoc.v:199443.17-199443.125" + wire width 2 $or$libresoc.v:199443$14701_Y + attribute \src "libresoc.v:199436.18-199436.100" + wire $reduce_or$libresoc.v:199436$14694_Y + attribute \src "libresoc.v:199439.18-199439.100" + wire $reduce_or$libresoc.v:199439$14697_Y + attribute \src "libresoc.v:199442.17-199442.95" + wire $reduce_or$libresoc.v:199442$14700_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -427103,9 +418406,9 @@ module \xer wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:447" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 10 \data_i @@ -427121,7 +418424,7 @@ module \xer wire width 6 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \full_wr__wen - attribute \src "libresoc.v:204781.7-204781.15" + attribute \src "libresoc.v:199269.7-199269.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest10__data_i @@ -427250,7 +418553,7 @@ module \xer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:204947$14922 + cell $or $or$libresoc.v:199435$14693 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -427258,10 +418561,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 - connect \Y $or$libresoc.v:204947$14922_Y + connect \Y $or$libresoc.v:199435$14693_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:204949$14924 + cell $or $or$libresoc.v:199437$14695 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -427269,10 +418572,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:204949$14924_Y + connect \Y $or$libresoc.v:199437$14695_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:204950$14925 + cell $or $or$libresoc.v:199438$14696 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -427280,10 +418583,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 - connect \Y $or$libresoc.v:204950$14925_Y + connect \Y $or$libresoc.v:199438$14696_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:204952$14927 + cell $or $or$libresoc.v:199440$14698 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -427291,10 +418594,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:204952$14927_Y + connect \Y $or$libresoc.v:199440$14698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:204953$14928 + cell $or $or$libresoc.v:199441$14699 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -427302,10 +418605,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 - connect \Y $or$libresoc.v:204953$14928_Y + connect \Y $or$libresoc.v:199441$14699_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:204955$14930 + cell $or $or$libresoc.v:199443$14701 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -427313,34 +418616,34 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:204955$14930_Y + connect \Y $or$libresoc.v:199443$14701_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:204948$14923 + cell $reduce_or $reduce_or$libresoc.v:199436$14694 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:204948$14923_Y + connect \Y $reduce_or$libresoc.v:199436$14694_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:204951$14926 + cell $reduce_or $reduce_or$libresoc.v:199439$14697 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:204951$14926_Y + connect \Y $reduce_or$libresoc.v:199439$14697_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:204954$14929 + cell $reduce_or $reduce_or$libresoc.v:199442$14700 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:204954$14929_Y + connect \Y $reduce_or$libresoc.v:199442$14700_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:204962.15-204981.4" + attribute \src "libresoc.v:199450.15-199469.4" cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -427362,7 +418665,7 @@ module \xer connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:204982.15-205001.4" + attribute \src "libresoc.v:199470.15-199489.4" cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -427384,7 +418687,7 @@ module \xer connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:205002.15-205021.4" + attribute \src "libresoc.v:199490.15-199509.4" cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -427405,67 +418708,67 @@ module \xer connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end - attribute \src "libresoc.v:204781.7-204781.20" - process $proc$libresoc.v:204781$14948 + attribute \src "libresoc.v:199269.7-199269.20" + process $proc$libresoc.v:199269$14719 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:204915.13-204915.29" - process $proc$libresoc.v:204915$14949 + attribute \src "libresoc.v:199403.13-199403.29" + process $proc$libresoc.v:199403$14720 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:204917.13-204917.34" - process $proc$libresoc.v:204917$14950 + attribute \src "libresoc.v:199405.13-199405.34" + process $proc$libresoc.v:199405$14721 assign { } { } - assign $0\ren_delay$11[2:0]$14951 3'000 + assign $0\ren_delay$11[2:0]$14722 3'000 sync always sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$14951 + update \ren_delay$11 $0\ren_delay$11[2:0]$14722 end - attribute \src "libresoc.v:204921.13-204921.34" - process $proc$libresoc.v:204921$14952 + attribute \src "libresoc.v:199409.13-199409.34" + process $proc$libresoc.v:199409$14723 assign { } { } - assign $0\ren_delay$18[2:0]$14953 3'000 + assign $0\ren_delay$18[2:0]$14724 3'000 sync always sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$14953 + update \ren_delay$18 $0\ren_delay$18[2:0]$14724 end - attribute \src "libresoc.v:204956.3-204957.43" - process $proc$libresoc.v:204956$14931 + attribute \src "libresoc.v:199444.3-199445.43" + process $proc$libresoc.v:199444$14702 assign { } { } - assign $0\ren_delay$18[2:0]$14932 \ren_delay$18$next + assign $0\ren_delay$18[2:0]$14703 \ren_delay$18$next sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$14932 + update \ren_delay$18 $0\ren_delay$18[2:0]$14703 end - attribute \src "libresoc.v:204958.3-204959.43" - process $proc$libresoc.v:204958$14933 + attribute \src "libresoc.v:199446.3-199447.43" + process $proc$libresoc.v:199446$14704 assign { } { } - assign $0\ren_delay$11[2:0]$14934 \ren_delay$11$next + assign $0\ren_delay$11[2:0]$14705 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$14934 + update \ren_delay$11 $0\ren_delay$11[2:0]$14705 end - attribute \src "libresoc.v:204960.3-204961.35" - process $proc$libresoc.v:204960$14935 + attribute \src "libresoc.v:199448.3-199449.35" + process $proc$libresoc.v:199448$14706 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:205022.3-205030.6" - process $proc$libresoc.v:205022$14936 + attribute \src "libresoc.v:199510.3-199518.6" + process $proc$libresoc.v:199510$14707 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$14937 $1\ren_delay$18$next[2:0]$14938 - attribute \src "libresoc.v:205023.5-205023.29" + assign $0\ren_delay$18$next[2:0]$14708 $1\ren_delay$18$next[2:0]$14709 + attribute \src "libresoc.v:199511.5-199511.29" switch \initial - attribute \src "libresoc.v:205023.9-205023.17" + attribute \src "libresoc.v:199511.9-199511.17" case 1'1 case end @@ -427474,21 +418777,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$14938 3'000 + assign $1\ren_delay$18$next[2:0]$14709 3'000 case - assign $1\ren_delay$18$next[2:0]$14938 \src3__ren + assign $1\ren_delay$18$next[2:0]$14709 \src3__ren end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14937 + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14708 end - attribute \src "libresoc.v:205031.3-205040.6" - process $proc$libresoc.v:205031$14939 + attribute \src "libresoc.v:199519.3-199528.6" + process $proc$libresoc.v:199519$14710 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:205032.5-205032.29" + attribute \src "libresoc.v:199520.5-199520.29" switch \initial - attribute \src "libresoc.v:205032.9-205032.17" + attribute \src "libresoc.v:199520.9-199520.17" case 1'1 case end @@ -427504,14 +418807,14 @@ module \xer sync always update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:205041.3-205049.6" - process $proc$libresoc.v:205041$14940 + attribute \src "libresoc.v:199529.3-199537.6" + process $proc$libresoc.v:199529$14711 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$14941 $1\ren_delay$next[2:0]$14942 - attribute \src "libresoc.v:205042.5-205042.29" + assign $0\ren_delay$next[2:0]$14712 $1\ren_delay$next[2:0]$14713 + attribute \src "libresoc.v:199530.5-199530.29" switch \initial - attribute \src "libresoc.v:205042.9-205042.17" + attribute \src "libresoc.v:199530.9-199530.17" case 1'1 case end @@ -427520,21 +418823,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$14942 3'000 + assign $1\ren_delay$next[2:0]$14713 3'000 case - assign $1\ren_delay$next[2:0]$14942 \src1__ren + assign $1\ren_delay$next[2:0]$14713 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$14941 + update \ren_delay$next $0\ren_delay$next[2:0]$14712 end - attribute \src "libresoc.v:205050.3-205059.6" - process $proc$libresoc.v:205050$14943 + attribute \src "libresoc.v:199538.3-199547.6" + process $proc$libresoc.v:199538$14714 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:205051.5-205051.29" + attribute \src "libresoc.v:199539.5-199539.29" switch \initial - attribute \src "libresoc.v:205051.9-205051.17" + attribute \src "libresoc.v:199539.9-199539.17" case 1'1 case end @@ -427550,14 +418853,14 @@ module \xer sync always update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:205060.3-205068.6" - process $proc$libresoc.v:205060$14944 + attribute \src "libresoc.v:199548.3-199556.6" + process $proc$libresoc.v:199548$14715 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$14945 $1\ren_delay$11$next[2:0]$14946 - attribute \src "libresoc.v:205061.5-205061.29" + assign $0\ren_delay$11$next[2:0]$14716 $1\ren_delay$11$next[2:0]$14717 + attribute \src "libresoc.v:199549.5-199549.29" switch \initial - attribute \src "libresoc.v:205061.9-205061.17" + attribute \src "libresoc.v:199549.9-199549.17" case 1'1 case end @@ -427566,21 +418869,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$14946 3'000 + assign $1\ren_delay$11$next[2:0]$14717 3'000 case - assign $1\ren_delay$11$next[2:0]$14946 \src2__ren + assign $1\ren_delay$11$next[2:0]$14717 \src2__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14945 + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14716 end - attribute \src "libresoc.v:205069.3-205078.6" - process $proc$libresoc.v:205069$14947 + attribute \src "libresoc.v:199557.3-199566.6" + process $proc$libresoc.v:199557$14718 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:205070.5-205070.29" + attribute \src "libresoc.v:199558.5-199558.29" switch \initial - attribute \src "libresoc.v:205070.9-205070.17" + attribute \src "libresoc.v:199558.9-199558.17" case 1'1 case end @@ -427596,15 +418899,15 @@ module \xer sync always update \src2__data_o $0\src2__data_o[1:0] end - connect \$9 $or$libresoc.v:204947$14922_Y - connect \$12 $reduce_or$libresoc.v:204948$14923_Y - connect \$14 $or$libresoc.v:204949$14924_Y - connect \$16 $or$libresoc.v:204950$14925_Y - connect \$19 $reduce_or$libresoc.v:204951$14926_Y - connect \$21 $or$libresoc.v:204952$14927_Y - connect \$23 $or$libresoc.v:204953$14928_Y - connect \$5 $reduce_or$libresoc.v:204954$14929_Y - connect \$7 $or$libresoc.v:204955$14930_Y + connect \$9 $or$libresoc.v:199435$14693_Y + connect \$12 $reduce_or$libresoc.v:199436$14694_Y + connect \$14 $or$libresoc.v:199437$14695_Y + connect \$16 $or$libresoc.v:199438$14696_Y + connect \$19 $reduce_or$libresoc.v:199439$14697_Y + connect \$21 $or$libresoc.v:199440$14698_Y + connect \$23 $or$libresoc.v:199441$14699_Y + connect \$5 $reduce_or$libresoc.v:199442$14700_Y + connect \$7 $or$libresoc.v:199443$14701_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 @@ -427627,153 +418930,153 @@ module \xer connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:205104.1-205418.10" +attribute \src "libresoc.v:199592.1-199906.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:205282.3-205310.6" + attribute \src "libresoc.v:199770.3-199798.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:205333.3-205341.6" - wire $0\core_irq_o$next[0:0]$14989 - attribute \src "libresoc.v:205224.3-205225.37" + attribute \src "libresoc.v:199821.3-199829.6" + wire $0\core_irq_o$next[0:0]$14760 + attribute \src "libresoc.v:199712.3-199713.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 8 $0\cppr$10[7:0]$14993 - attribute \src "libresoc.v:205238.3-205253.6" - wire width 8 $0\cppr$next[7:0]$14972 - attribute \src "libresoc.v:205228.3-205229.25" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 8 $0\cppr$10[7:0]$14764 + attribute \src "libresoc.v:199726.3-199741.6" + wire width 8 $0\cppr$next[7:0]$14743 + attribute \src "libresoc.v:199716.3-199717.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:205342.3-205351.6" + attribute \src "libresoc.v:199830.3-199839.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:205105.7-205105.20" + attribute \src "libresoc.v:199593.7-199593.20" wire $0\initial[0:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire $0\irq$12[0:0]$14994 - attribute \src "libresoc.v:205238.3-205253.6" - wire $0\irq$next[0:0]$14973 - attribute \src "libresoc.v:205232.3-205233.23" + attribute \src "libresoc.v:199840.3-199902.6" + wire $0\irq$12[0:0]$14765 + attribute \src "libresoc.v:199726.3-199741.6" + wire $0\irq$next[0:0]$14744 + attribute \src "libresoc.v:199720.3-199721.23" wire $0\irq[0:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 8 $0\mfrr$11[7:0]$14995 - attribute \src "libresoc.v:205238.3-205253.6" - wire width 8 $0\mfrr$next[7:0]$14974 - attribute \src "libresoc.v:205230.3-205231.25" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 8 $0\mfrr$11[7:0]$14766 + attribute \src "libresoc.v:199726.3-199741.6" + wire width 8 $0\mfrr$next[7:0]$14745 + attribute \src "libresoc.v:199718.3-199719.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:205321.3-205332.6" + attribute \src "libresoc.v:199809.3-199820.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:205311.3-205320.6" + attribute \src "libresoc.v:199799.3-199808.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire $0\wb_ack$14[0:0]$14996 - attribute \src "libresoc.v:205238.3-205253.6" - wire $0\wb_ack$next[0:0]$14975 - attribute \src "libresoc.v:205236.3-205237.29" + attribute \src "libresoc.v:199840.3-199902.6" + wire $0\wb_ack$14[0:0]$14767 + attribute \src "libresoc.v:199726.3-199741.6" + wire $0\wb_ack$next[0:0]$14746 + attribute \src "libresoc.v:199724.3-199725.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 32 $0\wb_rd_data$13[31:0]$14997 - attribute \src "libresoc.v:205238.3-205253.6" - wire width 32 $0\wb_rd_data$next[31:0]$14976 - attribute \src "libresoc.v:205234.3-205235.37" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 32 $0\wb_rd_data$13[31:0]$14768 + attribute \src "libresoc.v:199726.3-199741.6" + wire width 32 $0\wb_rd_data$next[31:0]$14747 + attribute \src "libresoc.v:199722.3-199723.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:205254.3-205281.6" + attribute \src "libresoc.v:199742.3-199769.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 24 $0\xisr$9[23:0]$14998 - attribute \src "libresoc.v:205238.3-205253.6" - wire width 24 $0\xisr$next[23:0]$14977 - attribute \src "libresoc.v:205226.3-205227.25" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 24 $0\xisr$9[23:0]$14769 + attribute \src "libresoc.v:199726.3-199741.6" + wire width 24 $0\xisr$next[23:0]$14748 + attribute \src "libresoc.v:199714.3-199715.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:205282.3-205310.6" + attribute \src "libresoc.v:199770.3-199798.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:205333.3-205341.6" - wire $1\core_irq_o$next[0:0]$14990 - attribute \src "libresoc.v:205134.7-205134.24" + attribute \src "libresoc.v:199821.3-199829.6" + wire $1\core_irq_o$next[0:0]$14761 + attribute \src "libresoc.v:199622.7-199622.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 8 $1\cppr$10[7:0]$14999 - attribute \src "libresoc.v:205238.3-205253.6" - wire width 8 $1\cppr$next[7:0]$14978 - attribute \src "libresoc.v:205138.13-205138.25" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 8 $1\cppr$10[7:0]$14770 + attribute \src "libresoc.v:199726.3-199741.6" + wire width 8 $1\cppr$next[7:0]$14749 + attribute \src "libresoc.v:199626.13-199626.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:205342.3-205351.6" + attribute \src "libresoc.v:199830.3-199839.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire $1\irq$12[0:0]$15009 - attribute \src "libresoc.v:205238.3-205253.6" - wire $1\irq$next[0:0]$14979 - attribute \src "libresoc.v:205167.7-205167.17" + attribute \src "libresoc.v:199840.3-199902.6" + wire $1\irq$12[0:0]$14780 + attribute \src "libresoc.v:199726.3-199741.6" + wire $1\irq$next[0:0]$14750 + attribute \src "libresoc.v:199655.7-199655.17" wire $1\irq[0:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 8 $1\mfrr$11[7:0]$15000 - attribute \src "libresoc.v:205238.3-205253.6" - wire width 8 $1\mfrr$next[7:0]$14980 - attribute \src "libresoc.v:205175.13-205175.25" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 8 $1\mfrr$11[7:0]$14771 + attribute \src "libresoc.v:199726.3-199741.6" + wire width 8 $1\mfrr$next[7:0]$14751 + attribute \src "libresoc.v:199663.13-199663.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:205321.3-205332.6" + attribute \src "libresoc.v:199809.3-199820.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:205311.3-205320.6" + attribute \src "libresoc.v:199799.3-199808.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire $1\wb_ack$14[0:0]$15001 - attribute \src "libresoc.v:205238.3-205253.6" - wire $1\wb_ack$next[0:0]$14981 - attribute \src "libresoc.v:205189.7-205189.20" + attribute \src "libresoc.v:199840.3-199902.6" + wire $1\wb_ack$14[0:0]$14772 + attribute \src "libresoc.v:199726.3-199741.6" + wire $1\wb_ack$next[0:0]$14752 + attribute \src "libresoc.v:199677.7-199677.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:205238.3-205253.6" - wire width 32 $1\wb_rd_data$next[31:0]$14982 - attribute \src "libresoc.v:205197.14-205197.32" + attribute \src "libresoc.v:199726.3-199741.6" + wire width 32 $1\wb_rd_data$next[31:0]$14753 + attribute \src "libresoc.v:199685.14-199685.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:205254.3-205281.6" + attribute \src "libresoc.v:199742.3-199769.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 24 $1\xisr$9[23:0]$15006 - attribute \src "libresoc.v:205238.3-205253.6" - wire width 24 $1\xisr$next[23:0]$14983 - attribute \src "libresoc.v:205207.14-205207.31" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 24 $1\xisr$9[23:0]$14777 + attribute \src "libresoc.v:199726.3-199741.6" + wire width 24 $1\xisr$next[23:0]$14754 + attribute \src "libresoc.v:199695.14-199695.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:205282.3-205310.6" + attribute \src "libresoc.v:199770.3-199798.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 8 $2\cppr$10[7:0]$15002 - attribute \src "libresoc.v:205352.3-205414.6" - wire width 8 $2\mfrr$11[7:0]$15003 - attribute \src "libresoc.v:205254.3-205281.6" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 8 $2\cppr$10[7:0]$14773 + attribute \src "libresoc.v:199840.3-199902.6" + wire width 8 $2\mfrr$11[7:0]$14774 + attribute \src "libresoc.v:199742.3-199769.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 24 $2\xisr$9[23:0]$15007 - attribute \src "libresoc.v:205282.3-205310.6" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 24 $2\xisr$9[23:0]$14778 + attribute \src "libresoc.v:199770.3-199798.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 8 $3\cppr$10[7:0]$15004 - attribute \src "libresoc.v:205352.3-205414.6" - wire width 8 $3\mfrr$11[7:0]$15005 - attribute \src "libresoc.v:205254.3-205281.6" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 8 $3\cppr$10[7:0]$14775 + attribute \src "libresoc.v:199840.3-199902.6" + wire width 8 $3\mfrr$11[7:0]$14776 + attribute \src "libresoc.v:199742.3-199769.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:205352.3-205414.6" - wire width 8 $4\cppr$10[7:0]$15008 - attribute \src "libresoc.v:205254.3-205281.6" + attribute \src "libresoc.v:199840.3-199902.6" + wire width 8 $4\cppr$10[7:0]$14779 + attribute \src "libresoc.v:199742.3-199769.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:205214.18-205214.116" - wire $and$libresoc.v:205214$14954_Y - attribute \src "libresoc.v:205218.18-205218.116" - wire $and$libresoc.v:205218$14958_Y - attribute \src "libresoc.v:205220.18-205220.116" - wire $and$libresoc.v:205220$14960_Y - attribute \src "libresoc.v:205223.17-205223.109" - wire $and$libresoc.v:205223$14963_Y - attribute \src "libresoc.v:205219.18-205219.110" - wire $eq$libresoc.v:205219$14959_Y - attribute \src "libresoc.v:205216.18-205216.114" - wire $lt$libresoc.v:205216$14956_Y - attribute \src "libresoc.v:205217.18-205217.109" - wire $lt$libresoc.v:205217$14957_Y - attribute \src "libresoc.v:205222.18-205222.114" - wire $lt$libresoc.v:205222$14962_Y - attribute \src "libresoc.v:205215.18-205215.109" - wire $ne$libresoc.v:205215$14955_Y - attribute \src "libresoc.v:205221.18-205221.109" - wire $ne$libresoc.v:205221$14961_Y + attribute \src "libresoc.v:199702.18-199702.116" + wire $and$libresoc.v:199702$14725_Y + attribute \src "libresoc.v:199706.18-199706.116" + wire $and$libresoc.v:199706$14729_Y + attribute \src "libresoc.v:199708.18-199708.116" + wire $and$libresoc.v:199708$14731_Y + attribute \src "libresoc.v:199711.17-199711.109" + wire $and$libresoc.v:199711$14734_Y + attribute \src "libresoc.v:199707.18-199707.110" + wire $eq$libresoc.v:199707$14730_Y + attribute \src "libresoc.v:199704.18-199704.114" + wire $lt$libresoc.v:199704$14727_Y + attribute \src "libresoc.v:199705.18-199705.109" + wire $lt$libresoc.v:199705$14728_Y + attribute \src "libresoc.v:199710.18-199710.114" + wire $lt$libresoc.v:199710$14733_Y + attribute \src "libresoc.v:199703.18-199703.109" + wire $ne$libresoc.v:199703$14726_Y + attribute \src "libresoc.v:199709.18-199709.109" + wire $ne$libresoc.v:199709$14732_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -427798,7 +419101,7 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire output 4 \core_irq_o @@ -427832,7 +419135,7 @@ module \xics_icp wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 2 \ics_i_src - attribute \src "libresoc.v:205105.7-205105.15" + attribute \src "libresoc.v:199593.7-199593.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -427854,7 +419157,7 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack @@ -427883,7 +419186,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:205214$14954 + cell $and $and$libresoc.v:199702$14725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -427891,10 +419194,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:205214$14954_Y + connect \Y $and$libresoc.v:199702$14725_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:205218$14958 + cell $and $and$libresoc.v:199706$14729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -427902,10 +419205,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:205218$14958_Y + connect \Y $and$libresoc.v:199706$14729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:205220$14960 + cell $and $and$libresoc.v:199708$14731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -427913,10 +419216,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:205220$14960_Y + connect \Y $and$libresoc.v:199708$14731_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:205223$14963 + cell $and $and$libresoc.v:199711$14734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -427924,10 +419227,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:205223$14963_Y + connect \Y $and$libresoc.v:199711$14734_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:205219$14959 + cell $eq $eq$libresoc.v:199707$14730 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -427935,10 +419238,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:205219$14959_Y + connect \Y $eq$libresoc.v:199707$14730_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:205216$14956 + cell $lt $lt$libresoc.v:199704$14727 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -427946,10 +419249,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:205216$14956_Y + connect \Y $lt$libresoc.v:199704$14727_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:205217$14957 + cell $lt $lt$libresoc.v:199705$14728 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -427957,10 +419260,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:205217$14957_Y + connect \Y $lt$libresoc.v:199705$14728_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:205222$14962 + cell $lt $lt$libresoc.v:199710$14733 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -427968,10 +419271,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:205222$14962_Y + connect \Y $lt$libresoc.v:199710$14733_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:205215$14955 + cell $ne $ne$libresoc.v:199703$14726 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -427979,10 +419282,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:205215$14955_Y + connect \Y $ne$libresoc.v:199703$14726_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:205221$14961 + cell $ne $ne$libresoc.v:199709$14732 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -427990,123 +419293,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:205221$14961_Y + connect \Y $ne$libresoc.v:199709$14732_Y end - attribute \src "libresoc.v:205105.7-205105.20" - process $proc$libresoc.v:205105$15010 + attribute \src "libresoc.v:199593.7-199593.20" + process $proc$libresoc.v:199593$14781 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:205134.7-205134.24" - process $proc$libresoc.v:205134$15011 + attribute \src "libresoc.v:199622.7-199622.24" + process $proc$libresoc.v:199622$14782 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:205138.13-205138.25" - process $proc$libresoc.v:205138$15012 + attribute \src "libresoc.v:199626.13-199626.25" + process $proc$libresoc.v:199626$14783 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:205167.7-205167.17" - process $proc$libresoc.v:205167$15013 + attribute \src "libresoc.v:199655.7-199655.17" + process $proc$libresoc.v:199655$14784 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:205175.13-205175.25" - process $proc$libresoc.v:205175$15014 + attribute \src "libresoc.v:199663.13-199663.25" + process $proc$libresoc.v:199663$14785 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:205189.7-205189.20" - process $proc$libresoc.v:205189$15015 + attribute \src "libresoc.v:199677.7-199677.20" + process $proc$libresoc.v:199677$14786 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:205197.14-205197.32" - process $proc$libresoc.v:205197$15016 + attribute \src "libresoc.v:199685.14-199685.32" + process $proc$libresoc.v:199685$14787 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:205207.14-205207.31" - process $proc$libresoc.v:205207$15017 + attribute \src "libresoc.v:199695.14-199695.31" + process $proc$libresoc.v:199695$14788 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:205224.3-205225.37" - process $proc$libresoc.v:205224$14964 + attribute \src "libresoc.v:199712.3-199713.37" + process $proc$libresoc.v:199712$14735 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:205226.3-205227.25" - process $proc$libresoc.v:205226$14965 + attribute \src "libresoc.v:199714.3-199715.25" + process $proc$libresoc.v:199714$14736 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:205228.3-205229.25" - process $proc$libresoc.v:205228$14966 + attribute \src "libresoc.v:199716.3-199717.25" + process $proc$libresoc.v:199716$14737 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:205230.3-205231.25" - process $proc$libresoc.v:205230$14967 + attribute \src "libresoc.v:199718.3-199719.25" + process $proc$libresoc.v:199718$14738 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:205232.3-205233.23" - process $proc$libresoc.v:205232$14968 + attribute \src "libresoc.v:199720.3-199721.23" + process $proc$libresoc.v:199720$14739 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:205234.3-205235.37" - process $proc$libresoc.v:205234$14969 + attribute \src "libresoc.v:199722.3-199723.37" + process $proc$libresoc.v:199722$14740 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:205236.3-205237.29" - process $proc$libresoc.v:205236$14970 + attribute \src "libresoc.v:199724.3-199725.29" + process $proc$libresoc.v:199724$14741 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:205238.3-205253.6" - process $proc$libresoc.v:205238$14971 + attribute \src "libresoc.v:199726.3-199741.6" + process $proc$libresoc.v:199726$14742 assign { } { } assign { } { } assign { } { } @@ -428114,15 +419417,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$14972 $1\cppr$next[7:0]$14978 - assign $0\irq$next[0:0]$14973 $1\irq$next[0:0]$14979 - assign $0\mfrr$next[7:0]$14974 $1\mfrr$next[7:0]$14980 - assign $0\wb_ack$next[0:0]$14975 $1\wb_ack$next[0:0]$14981 - assign $0\wb_rd_data$next[31:0]$14976 $1\wb_rd_data$next[31:0]$14982 - assign $0\xisr$next[23:0]$14977 $1\xisr$next[23:0]$14983 - attribute \src "libresoc.v:205239.5-205239.29" + assign $0\cppr$next[7:0]$14743 $1\cppr$next[7:0]$14749 + assign $0\irq$next[0:0]$14744 $1\irq$next[0:0]$14750 + assign $0\mfrr$next[7:0]$14745 $1\mfrr$next[7:0]$14751 + assign $0\wb_ack$next[0:0]$14746 $1\wb_ack$next[0:0]$14752 + assign $0\wb_rd_data$next[31:0]$14747 $1\wb_rd_data$next[31:0]$14753 + assign $0\xisr$next[23:0]$14748 $1\xisr$next[23:0]$14754 + attribute \src "libresoc.v:199727.5-199727.29" switch \initial - attribute \src "libresoc.v:205239.9-205239.17" + attribute \src "libresoc.v:199727.9-199727.17" case 1'1 case end @@ -428136,36 +419439,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$14983 24'000000000000000000000000 - assign $1\cppr$next[7:0]$14978 8'00000000 - assign $1\mfrr$next[7:0]$14980 8'11111111 - assign $1\irq$next[0:0]$14979 1'0 - assign $1\wb_rd_data$next[31:0]$14982 0 - assign $1\wb_ack$next[0:0]$14981 1'0 + assign $1\xisr$next[23:0]$14754 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14749 8'00000000 + assign $1\mfrr$next[7:0]$14751 8'11111111 + assign $1\irq$next[0:0]$14750 1'0 + assign $1\wb_rd_data$next[31:0]$14753 0 + assign $1\wb_ack$next[0:0]$14752 1'0 case - assign $1\cppr$next[7:0]$14978 \cppr$2 - assign $1\irq$next[0:0]$14979 \irq$4 - assign $1\mfrr$next[7:0]$14980 \mfrr$3 - assign $1\wb_ack$next[0:0]$14981 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$14982 \wb_rd_data$5 - assign $1\xisr$next[23:0]$14983 \xisr$1 + assign $1\cppr$next[7:0]$14749 \cppr$2 + assign $1\irq$next[0:0]$14750 \irq$4 + assign $1\mfrr$next[7:0]$14751 \mfrr$3 + assign $1\wb_ack$next[0:0]$14752 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14753 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14754 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$14972 - update \irq$next $0\irq$next[0:0]$14973 - update \mfrr$next $0\mfrr$next[7:0]$14974 - update \wb_ack$next $0\wb_ack$next[0:0]$14975 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14976 - update \xisr$next $0\xisr$next[23:0]$14977 + update \cppr$next $0\cppr$next[7:0]$14743 + update \irq$next $0\irq$next[0:0]$14744 + update \mfrr$next $0\mfrr$next[7:0]$14745 + update \wb_ack$next $0\wb_ack$next[0:0]$14746 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14747 + update \xisr$next $0\xisr$next[23:0]$14748 end - attribute \src "libresoc.v:205254.3-205281.6" - process $proc$libresoc.v:205254$14984 + attribute \src "libresoc.v:199742.3-199769.6" + process $proc$libresoc.v:199742$14755 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:205255.5-205255.29" + attribute \src "libresoc.v:199743.5-199743.29" switch \initial - attribute \src "libresoc.v:205255.9-205255.17" + attribute \src "libresoc.v:199743.9-199743.17" case 1'1 case end @@ -428209,14 +419512,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:205282.3-205310.6" - process $proc$libresoc.v:205282$14985 + attribute \src "libresoc.v:199770.3-199798.6" + process $proc$libresoc.v:199770$14756 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:205283.5-205283.29" + attribute \src "libresoc.v:199771.5-199771.29" switch \initial - attribute \src "libresoc.v:205283.9-205283.17" + attribute \src "libresoc.v:199771.9-199771.17" case 1'1 case end @@ -428259,14 +419562,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:205311.3-205320.6" - process $proc$libresoc.v:205311$14986 + attribute \src "libresoc.v:199799.3-199808.6" + process $proc$libresoc.v:199799$14757 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:205312.5-205312.29" + attribute \src "libresoc.v:199800.5-199800.29" switch \initial - attribute \src "libresoc.v:205312.9-205312.17" + attribute \src "libresoc.v:199800.9-199800.17" case 1'1 case end @@ -428282,13 +419585,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:205321.3-205332.6" - process $proc$libresoc.v:205321$14987 + attribute \src "libresoc.v:199809.3-199820.6" + process $proc$libresoc.v:199809$14758 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:205322.5-205322.29" + attribute \src "libresoc.v:199810.5-199810.29" switch \initial - attribute \src "libresoc.v:205322.9-205322.17" + attribute \src "libresoc.v:199810.9-199810.17" case 1'1 case end @@ -428306,14 +419609,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:205333.3-205341.6" - process $proc$libresoc.v:205333$14988 + attribute \src "libresoc.v:199821.3-199829.6" + process $proc$libresoc.v:199821$14759 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$14989 $1\core_irq_o$next[0:0]$14990 - attribute \src "libresoc.v:205334.5-205334.29" + assign $0\core_irq_o$next[0:0]$14760 $1\core_irq_o$next[0:0]$14761 + attribute \src "libresoc.v:199822.5-199822.29" switch \initial - attribute \src "libresoc.v:205334.9-205334.17" + attribute \src "libresoc.v:199822.9-199822.17" case 1'1 case end @@ -428322,21 +419625,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$14990 1'0 + assign $1\core_irq_o$next[0:0]$14761 1'0 case - assign $1\core_irq_o$next[0:0]$14990 \irq + assign $1\core_irq_o$next[0:0]$14761 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$14989 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14760 end - attribute \src "libresoc.v:205342.3-205351.6" - process $proc$libresoc.v:205342$14991 + attribute \src "libresoc.v:199830.3-199839.6" + process $proc$libresoc.v:199830$14762 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:205343.5-205343.29" + attribute \src "libresoc.v:199831.5-199831.29" switch \initial - attribute \src "libresoc.v:205343.9-205343.17" + attribute \src "libresoc.v:199831.9-199831.17" case 1'1 case end @@ -428352,8 +419655,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:205352.3-205414.6" - process $proc$libresoc.v:205352$14992 + attribute \src "libresoc.v:199840.3-199902.6" + process $proc$libresoc.v:199840$14763 assign { } { } assign { } { } assign { } { } @@ -428363,18 +419666,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$14995 $1\mfrr$11[7:0]$15000 - assign $0\wb_ack$14[0:0]$14996 $1\wb_ack$14[0:0]$15001 + assign $0\mfrr$11[7:0]$14766 $1\mfrr$11[7:0]$14771 + assign $0\wb_ack$14[0:0]$14767 $1\wb_ack$14[0:0]$14772 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$14998 $2\xisr$9[23:0]$15007 - assign $0\cppr$10[7:0]$14993 $4\cppr$10[7:0]$15008 - assign $0\wb_rd_data$13[31:0]$14997 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$14994 $1\irq$12[0:0]$15009 - attribute \src "libresoc.v:205353.5-205353.29" + assign $0\xisr$9[23:0]$14769 $2\xisr$9[23:0]$14778 + assign $0\cppr$10[7:0]$14764 $4\cppr$10[7:0]$14779 + assign $0\wb_rd_data$13[31:0]$14768 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14765 $1\irq$12[0:0]$14780 + attribute \src "libresoc.v:199841.5-199841.29" switch \initial - attribute \src "libresoc.v:205353.9-205353.17" + attribute \src "libresoc.v:199841.9-199841.17" case 1'1 case end @@ -428385,712 +419688,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$15001 1'1 - assign $1\cppr$10[7:0]$14999 $2\cppr$10[7:0]$15002 - assign $1\mfrr$11[7:0]$15000 $2\mfrr$11[7:0]$15003 + assign $1\wb_ack$14[0:0]$14772 1'1 + assign $1\cppr$10[7:0]$14770 $2\cppr$10[7:0]$14773 + assign $1\mfrr$11[7:0]$14771 $2\mfrr$11[7:0]$14774 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$15002 $3\cppr$10[7:0]$15004 - assign $2\mfrr$11[7:0]$15003 $3\mfrr$11[7:0]$15005 + assign $2\cppr$10[7:0]$14773 $3\cppr$10[7:0]$14775 + assign $2\mfrr$11[7:0]$14774 $3\mfrr$11[7:0]$14776 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$15005 \mfrr - assign $3\cppr$10[7:0]$15004 \be_in [31:24] + assign $3\mfrr$11[7:0]$14776 \mfrr + assign $3\cppr$10[7:0]$14775 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$15005 \mfrr - assign $3\cppr$10[7:0]$15004 \be_in [31:24] + assign $3\mfrr$11[7:0]$14776 \mfrr + assign $3\cppr$10[7:0]$14775 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$15004 \cppr + assign $3\cppr$10[7:0]$14775 \cppr assign { } { } - assign $3\mfrr$11[7:0]$15005 \be_in [31:24] + assign $3\mfrr$11[7:0]$14776 \be_in [31:24] case - assign $3\cppr$10[7:0]$15004 \cppr - assign $3\mfrr$11[7:0]$15005 \mfrr + assign $3\cppr$10[7:0]$14775 \cppr + assign $3\mfrr$11[7:0]$14776 \mfrr end case - assign $2\cppr$10[7:0]$15002 \cppr - assign $2\mfrr$11[7:0]$15003 \mfrr + assign $2\cppr$10[7:0]$14773 \cppr + assign $2\mfrr$11[7:0]$14774 \mfrr end case - assign $1\cppr$10[7:0]$14999 \cppr - assign $1\mfrr$11[7:0]$15000 \mfrr - assign $1\wb_ack$14[0:0]$15001 1'0 + assign $1\cppr$10[7:0]$14770 \cppr + assign $1\mfrr$11[7:0]$14771 \mfrr + assign $1\wb_ack$14[0:0]$14772 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$15006 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14777 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$15006 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14777 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$15007 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14778 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$15007 $1\xisr$9[23:0]$15006 + assign $2\xisr$9[23:0]$14778 $1\xisr$9[23:0]$14777 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$15008 \min_pri + assign $4\cppr$10[7:0]$14779 \min_pri case - assign $4\cppr$10[7:0]$15008 $1\cppr$10[7:0]$14999 + assign $4\cppr$10[7:0]$14779 $1\cppr$10[7:0]$14770 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$15009 1'1 + assign $1\irq$12[0:0]$14780 1'1 case - assign $1\irq$12[0:0]$15009 1'0 + assign $1\irq$12[0:0]$14780 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$14993 - update \irq$12 $0\irq$12[0:0]$14994 - update \mfrr$11 $0\mfrr$11[7:0]$14995 - update \wb_ack$14 $0\wb_ack$14[0:0]$14996 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14997 - update \xisr$9 $0\xisr$9[23:0]$14998 + update \cppr$10 $0\cppr$10[7:0]$14764 + update \irq$12 $0\irq$12[0:0]$14765 + update \mfrr$11 $0\mfrr$11[7:0]$14766 + update \wb_ack$14 $0\wb_ack$14[0:0]$14767 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14768 + update \xisr$9 $0\xisr$9[23:0]$14769 end - connect \$15 $and$libresoc.v:205214$14954_Y - connect \$17 $ne$libresoc.v:205215$14955_Y - connect \$19 $lt$libresoc.v:205216$14956_Y - connect \$21 $lt$libresoc.v:205217$14957_Y - connect \$23 $and$libresoc.v:205218$14958_Y - connect \$25 $eq$libresoc.v:205219$14959_Y - connect \$27 $and$libresoc.v:205220$14960_Y - connect \$29 $ne$libresoc.v:205221$14961_Y - connect \$31 $lt$libresoc.v:205222$14962_Y - connect \$7 $and$libresoc.v:205223$14963_Y + connect \$15 $and$libresoc.v:199702$14725_Y + connect \$17 $ne$libresoc.v:199703$14726_Y + connect \$19 $lt$libresoc.v:199704$14727_Y + connect \$21 $lt$libresoc.v:199705$14728_Y + connect \$23 $and$libresoc.v:199706$14729_Y + connect \$25 $eq$libresoc.v:199707$14730_Y + connect \$27 $and$libresoc.v:199708$14731_Y + connect \$29 $ne$libresoc.v:199709$14732_Y + connect \$31 $lt$libresoc.v:199710$14733_Y + connect \$7 $and$libresoc.v:199711$14734_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:205422.1-206471.10" +attribute \src "libresoc.v:199910.1-200959.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:206352.3-206401.6" + attribute \src "libresoc.v:200840.3-200889.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:206063.3-206072.6" + attribute \src "libresoc.v:200551.3-200560.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:206272.3-206281.6" + attribute \src "libresoc.v:200760.3-200769.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:206292.3-206301.6" + attribute \src "libresoc.v:200780.3-200789.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:206312.3-206321.6" + attribute \src "libresoc.v:200800.3-200809.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:206332.3-206341.6" + attribute \src "libresoc.v:200820.3-200829.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:206402.3-206411.6" + attribute \src "libresoc.v:200890.3-200899.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:206422.3-206431.6" + attribute \src "libresoc.v:200910.3-200919.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:206083.3-206092.6" + attribute \src "libresoc.v:200571.3-200580.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:206103.3-206112.6" + attribute \src "libresoc.v:200591.3-200600.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:206123.3-206132.6" + attribute \src "libresoc.v:200611.3-200620.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:206152.3-206161.6" + attribute \src "libresoc.v:200640.3-200649.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:206172.3-206181.6" + attribute \src "libresoc.v:200660.3-200669.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:206192.3-206201.6" + attribute \src "libresoc.v:200680.3-200689.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:206212.3-206221.6" + attribute \src "libresoc.v:200700.3-200709.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:206232.3-206241.6" + attribute \src "libresoc.v:200720.3-200729.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:206252.3-206261.6" + attribute \src "libresoc.v:200740.3-200749.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:206053.3-206062.6" + attribute \src "libresoc.v:200541.3-200550.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:206262.3-206271.6" + attribute \src "libresoc.v:200750.3-200759.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:206282.3-206291.6" + attribute \src "libresoc.v:200770.3-200779.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:206302.3-206311.6" + attribute \src "libresoc.v:200790.3-200799.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:206322.3-206331.6" + attribute \src "libresoc.v:200810.3-200819.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:206342.3-206351.6" + attribute \src "libresoc.v:200830.3-200839.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:206412.3-206421.6" + attribute \src "libresoc.v:200900.3-200909.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:206073.3-206082.6" + attribute \src "libresoc.v:200561.3-200570.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:206093.3-206102.6" + attribute \src "libresoc.v:200581.3-200590.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:206113.3-206122.6" + attribute \src "libresoc.v:200601.3-200610.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:206133.3-206142.6" + attribute \src "libresoc.v:200621.3-200630.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:206162.3-206171.6" + attribute \src "libresoc.v:200650.3-200659.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:206182.3-206191.6" + attribute \src "libresoc.v:200670.3-200679.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:206202.3-206211.6" + attribute \src "libresoc.v:200690.3-200699.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:206222.3-206231.6" + attribute \src "libresoc.v:200710.3-200719.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:206242.3-206251.6" + attribute \src "libresoc.v:200730.3-200739.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:206432.3-206441.6" + attribute \src "libresoc.v:200920.3-200929.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:205927.3-205928.25" + attribute \src "libresoc.v:200415.3-200416.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:205925.3-205926.28" + attribute \src "libresoc.v:200413.3-200414.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:206451.3-206459.6" - wire $0\ics_wb__ack$next[0:0]$15264 - attribute \src "libresoc.v:205961.3-205962.39" + attribute \src "libresoc.v:200939.3-200947.6" + wire $0\ics_wb__ack$next[0:0]$15035 + attribute \src "libresoc.v:200449.3-200450.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:206442.3-206450.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$15261 - attribute \src "libresoc.v:205963.3-205964.43" + attribute \src "libresoc.v:200930.3-200938.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$15032 + attribute \src "libresoc.v:200451.3-200452.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:205423.7-205423.20" + attribute \src "libresoc.v:199911.7-199911.20" wire $0\initial[0:0] - attribute \src "libresoc.v:206143.3-206151.6" - wire width 16 $0\int_level_l$next[15:0]$15233 - attribute \src "libresoc.v:205965.3-205966.39" + attribute \src "libresoc.v:200631.3-200639.6" + wire width 16 $0\int_level_l$next[15:0]$15004 + attribute \src "libresoc.v:200453.3-200454.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive0_pri$next[7:0]$15143 - attribute \src "libresoc.v:205929.3-205930.35" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive0_pri$next[7:0]$14914 + attribute \src "libresoc.v:200417.3-200418.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive10_pri$next[7:0]$15144 - attribute \src "libresoc.v:205949.3-205950.37" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive10_pri$next[7:0]$14915 + attribute \src "libresoc.v:200437.3-200438.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive11_pri$next[7:0]$15145 - attribute \src "libresoc.v:205951.3-205952.37" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive11_pri$next[7:0]$14916 + attribute \src "libresoc.v:200439.3-200440.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive12_pri$next[7:0]$15146 - attribute \src "libresoc.v:205953.3-205954.37" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive12_pri$next[7:0]$14917 + attribute \src "libresoc.v:200441.3-200442.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive13_pri$next[7:0]$15147 - attribute \src "libresoc.v:205955.3-205956.37" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive13_pri$next[7:0]$14918 + attribute \src "libresoc.v:200443.3-200444.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive14_pri$next[7:0]$15148 - attribute \src "libresoc.v:205957.3-205958.37" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive14_pri$next[7:0]$14919 + attribute \src "libresoc.v:200445.3-200446.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive15_pri$next[7:0]$15149 - attribute \src "libresoc.v:205959.3-205960.37" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive15_pri$next[7:0]$14920 + attribute \src "libresoc.v:200447.3-200448.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive1_pri$next[7:0]$15150 - attribute \src "libresoc.v:205931.3-205932.35" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive1_pri$next[7:0]$14921 + attribute \src "libresoc.v:200419.3-200420.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive2_pri$next[7:0]$15151 - attribute \src "libresoc.v:205933.3-205934.35" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive2_pri$next[7:0]$14922 + attribute \src "libresoc.v:200421.3-200422.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive3_pri$next[7:0]$15152 - attribute \src "libresoc.v:205935.3-205936.35" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive3_pri$next[7:0]$14923 + attribute \src "libresoc.v:200423.3-200424.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive4_pri$next[7:0]$15153 - attribute \src "libresoc.v:205937.3-205938.35" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive4_pri$next[7:0]$14924 + attribute \src "libresoc.v:200425.3-200426.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive5_pri$next[7:0]$15154 - attribute \src "libresoc.v:205939.3-205940.35" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive5_pri$next[7:0]$14925 + attribute \src "libresoc.v:200427.3-200428.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive6_pri$next[7:0]$15155 - attribute \src "libresoc.v:205941.3-205942.35" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive6_pri$next[7:0]$14926 + attribute \src "libresoc.v:200429.3-200430.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive7_pri$next[7:0]$15156 - attribute \src "libresoc.v:205943.3-205944.35" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive7_pri$next[7:0]$14927 + attribute \src "libresoc.v:200431.3-200432.35" wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive8_pri$next[7:0]$15157 - attribute \src "libresoc.v:205945.3-205946.35" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive8_pri$next[7:0]$14928 + attribute \src "libresoc.v:200433.3-200434.35" wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $0\xive9_pri$next[7:0]$15158 - attribute \src "libresoc.v:205947.3-205948.35" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $0\xive9_pri$next[7:0]$14929 + attribute \src "libresoc.v:200435.3-200436.35" wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:206352.3-206401.6" + attribute \src "libresoc.v:200840.3-200889.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:206063.3-206072.6" + attribute \src "libresoc.v:200551.3-200560.6" wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:206272.3-206281.6" + attribute \src "libresoc.v:200760.3-200769.6" wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:206292.3-206301.6" + attribute \src "libresoc.v:200780.3-200789.6" wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:206312.3-206321.6" + attribute \src "libresoc.v:200800.3-200809.6" wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:206332.3-206341.6" + attribute \src "libresoc.v:200820.3-200829.6" wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:206402.3-206411.6" + attribute \src "libresoc.v:200890.3-200899.6" wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:206422.3-206431.6" + attribute \src "libresoc.v:200910.3-200919.6" wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:206083.3-206092.6" + attribute \src "libresoc.v:200571.3-200580.6" wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:206103.3-206112.6" + attribute \src "libresoc.v:200591.3-200600.6" wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:206123.3-206132.6" + attribute \src "libresoc.v:200611.3-200620.6" wire width 4 $1\cur_idx3[3:0] - attribute \src "libresoc.v:206152.3-206161.6" + attribute \src "libresoc.v:200640.3-200649.6" wire width 4 $1\cur_idx4[3:0] - attribute \src "libresoc.v:206172.3-206181.6" + attribute \src "libresoc.v:200660.3-200669.6" wire width 4 $1\cur_idx5[3:0] - attribute \src "libresoc.v:206192.3-206201.6" + attribute \src "libresoc.v:200680.3-200689.6" wire width 4 $1\cur_idx6[3:0] - attribute \src "libresoc.v:206212.3-206221.6" + attribute \src "libresoc.v:200700.3-200709.6" wire width 4 $1\cur_idx7[3:0] - attribute \src "libresoc.v:206232.3-206241.6" + attribute \src "libresoc.v:200720.3-200729.6" wire width 4 $1\cur_idx8[3:0] - attribute \src "libresoc.v:206252.3-206261.6" + attribute \src "libresoc.v:200740.3-200749.6" wire width 4 $1\cur_idx9[3:0] - attribute \src "libresoc.v:206053.3-206062.6" + attribute \src "libresoc.v:200541.3-200550.6" wire width 8 $1\cur_pri0[7:0] - attribute \src "libresoc.v:206262.3-206271.6" + attribute \src "libresoc.v:200750.3-200759.6" wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:206282.3-206291.6" + attribute \src "libresoc.v:200770.3-200779.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:206302.3-206311.6" + attribute \src "libresoc.v:200790.3-200799.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:206322.3-206331.6" + attribute \src "libresoc.v:200810.3-200819.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:206342.3-206351.6" + attribute \src "libresoc.v:200830.3-200839.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:206412.3-206421.6" + attribute \src "libresoc.v:200900.3-200909.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:206073.3-206082.6" + attribute \src "libresoc.v:200561.3-200570.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:206093.3-206102.6" + attribute \src "libresoc.v:200581.3-200590.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:206113.3-206122.6" + attribute \src "libresoc.v:200601.3-200610.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:206133.3-206142.6" + attribute \src "libresoc.v:200621.3-200630.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:206162.3-206171.6" + attribute \src "libresoc.v:200650.3-200659.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:206182.3-206191.6" + attribute \src "libresoc.v:200670.3-200679.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:206202.3-206211.6" + attribute \src "libresoc.v:200690.3-200699.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:206222.3-206231.6" + attribute \src "libresoc.v:200710.3-200719.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:206242.3-206251.6" + attribute \src "libresoc.v:200730.3-200739.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:206432.3-206441.6" + attribute \src "libresoc.v:200920.3-200929.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:205704.13-205704.30" + attribute \src "libresoc.v:200192.13-200192.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:205709.13-205709.29" + attribute \src "libresoc.v:200197.13-200197.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:206451.3-206459.6" - wire $1\ics_wb__ack$next[0:0]$15265 - attribute \src "libresoc.v:205718.7-205718.25" + attribute \src "libresoc.v:200939.3-200947.6" + wire $1\ics_wb__ack$next[0:0]$15036 + attribute \src "libresoc.v:200206.7-200206.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:206442.3-206450.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$15262 - attribute \src "libresoc.v:205727.14-205727.35" + attribute \src "libresoc.v:200930.3-200938.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$15033 + attribute \src "libresoc.v:200215.14-200215.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:206143.3-206151.6" - wire width 16 $1\int_level_l$next[15:0]$15234 - attribute \src "libresoc.v:205739.14-205739.36" + attribute \src "libresoc.v:200631.3-200639.6" + wire width 16 $1\int_level_l$next[15:0]$15005 + attribute \src "libresoc.v:200227.14-200227.36" wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive0_pri$next[7:0]$15159 - attribute \src "libresoc.v:205759.13-205759.30" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $1\xive0_pri$next[7:0]$14930 + attribute \src "libresoc.v:200247.13-200247.30" wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive10_pri$next[7:0]$15160 - attribute \src "libresoc.v:205763.13-205763.31" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $1\xive10_pri$next[7:0]$14931 + attribute \src "libresoc.v:200251.13-200251.31" wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive11_pri$next[7:0]$15161 - attribute \src "libresoc.v:205767.13-205767.31" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $1\xive11_pri$next[7:0]$14932 + attribute \src "libresoc.v:200255.13-200255.31" wire width 8 $1\xive11_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive12_pri$next[7:0]$15162 - attribute \src "libresoc.v:205771.13-205771.31" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $1\xive12_pri$next[7:0]$14933 + attribute \src "libresoc.v:200259.13-200259.31" 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\src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive1_pri$next[7:0]$15166 - attribute \src "libresoc.v:205787.13-205787.30" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $1\xive1_pri$next[7:0]$14937 + attribute \src "libresoc.v:200275.13-200275.30" wire width 8 $1\xive1_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive2_pri$next[7:0]$15167 - attribute \src "libresoc.v:205791.13-205791.30" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $1\xive2_pri$next[7:0]$14938 + attribute \src "libresoc.v:200279.13-200279.30" wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive3_pri$next[7:0]$15168 - attribute \src "libresoc.v:205795.13-205795.30" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $1\xive3_pri$next[7:0]$14939 + attribute \src "libresoc.v:200283.13-200283.30" wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive4_pri$next[7:0]$15169 - attribute \src "libresoc.v:205799.13-205799.30" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $1\xive4_pri$next[7:0]$14940 + attribute \src "libresoc.v:200287.13-200287.30" wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive5_pri$next[7:0]$15170 - attribute \src "libresoc.v:205803.13-205803.30" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $1\xive5_pri$next[7:0]$14941 + attribute \src "libresoc.v:200291.13-200291.30" wire width 8 $1\xive5_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive6_pri$next[7:0]$15171 - attribute \src "libresoc.v:205807.13-205807.30" + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $1\xive6_pri$next[7:0]$14942 + attribute \src "libresoc.v:200295.13-200295.30" wire width 8 $1\xive6_pri[7:0] - attribute \src "libresoc.v:205967.3-206052.6" - wire width 8 $1\xive7_pri$next[7:0]$15172 - attribute \src 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$2\xive4_pri$next[7:0]$14956 + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $2\xive5_pri$next[7:0]$14957 + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $2\xive6_pri$next[7:0]$14958 + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $2\xive7_pri$next[7:0]$14959 + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $2\xive8_pri$next[7:0]$14960 + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $2\xive9_pri$next[7:0]$14961 + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $3\xive0_pri$next[7:0]$14962 + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $3\xive10_pri$next[7:0]$14963 + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $3\xive11_pri$next[7:0]$14964 + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $3\xive12_pri$next[7:0]$14965 + attribute \src "libresoc.v:200455.3-200540.6" + wire width 8 $3\xive13_pri$next[7:0]$14966 + attribute \src "libresoc.v:200455.3-200540.6" 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"libresoc.v:200352.19-200352.114" + wire $lt$libresoc.v:200352$14831_Y + attribute \src "libresoc.v:200355.19-200355.114" + wire $lt$libresoc.v:200355$14834_Y + attribute \src "libresoc.v:200357.19-200357.114" + wire $lt$libresoc.v:200357$14836_Y + attribute \src "libresoc.v:200359.19-200359.114" + wire $lt$libresoc.v:200359$14838_Y + attribute \src "libresoc.v:200361.19-200361.114" + wire $lt$libresoc.v:200361$14840_Y + attribute \src "libresoc.v:200363.19-200363.114" + wire $lt$libresoc.v:200363$14842_Y + attribute \src "libresoc.v:200366.19-200366.114" + wire $lt$libresoc.v:200366$14845_Y + attribute \src "libresoc.v:200400.18-200400.110" + wire $lt$libresoc.v:200400$14879_Y + attribute \src "libresoc.v:200402.18-200402.110" + wire $lt$libresoc.v:200402$14881_Y + attribute \src "libresoc.v:200404.18-200404.111" + wire $lt$libresoc.v:200404$14883_Y + attribute \src "libresoc.v:200406.18-200406.111" + wire $lt$libresoc.v:200406$14885_Y + attribute \src "libresoc.v:200409.18-200409.111" + wire $lt$libresoc.v:200409$14888_Y + attribute \src "libresoc.v:200411.18-200411.111" + wire $lt$libresoc.v:200411$14890_Y + attribute \src "libresoc.v:200398.18-200398.40" + wire width 16 $shr$libresoc.v:200398$14877_Y + attribute \src "libresoc.v:200310.17-200310.114" + wire width 8 $ternary$libresoc.v:200310$14789_Y + attribute \src "libresoc.v:200332.18-200332.116" + wire width 8 $ternary$libresoc.v:200332$14811_Y + attribute \src "libresoc.v:200354.18-200354.116" + wire width 8 $ternary$libresoc.v:200354$14833_Y + attribute \src "libresoc.v:200369.19-200369.118" + wire width 8 $ternary$libresoc.v:200369$14848_Y + attribute \src "libresoc.v:200371.18-200371.116" + wire width 8 $ternary$libresoc.v:200371$14850_Y + attribute \src "libresoc.v:200373.18-200373.116" + wire width 8 $ternary$libresoc.v:200373$14852_Y + attribute \src "libresoc.v:200375.18-200375.116" + wire width 8 $ternary$libresoc.v:200375$14854_Y + attribute \src "libresoc.v:200377.18-200377.116" + wire width 8 $ternary$libresoc.v:200377$14856_Y + attribute \src "libresoc.v:200379.18-200379.116" + wire width 8 $ternary$libresoc.v:200379$14858_Y + attribute \src "libresoc.v:200382.18-200382.116" + wire width 8 $ternary$libresoc.v:200382$14861_Y + attribute \src "libresoc.v:200384.18-200384.116" + wire width 8 $ternary$libresoc.v:200384$14863_Y + attribute \src "libresoc.v:200386.18-200386.117" + wire width 8 $ternary$libresoc.v:200386$14865_Y + attribute \src "libresoc.v:200388.18-200388.117" + wire width 8 $ternary$libresoc.v:200388$14867_Y + attribute \src "libresoc.v:200390.18-200390.117" + wire width 8 $ternary$libresoc.v:200390$14869_Y + attribute \src "libresoc.v:200393.18-200393.117" + wire width 8 $ternary$libresoc.v:200393$14872_Y + attribute \src "libresoc.v:200395.18-200395.117" + wire width 8 $ternary$libresoc.v:200395$14874_Y + attribute \src "libresoc.v:200397.18-200397.117" + wire width 8 $ternary$libresoc.v:200397$14876_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -429301,7 +420604,7 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 @@ -429399,7 +420702,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:205423.7-205423.15" + attribute \src "libresoc.v:199911.7-199911.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -429419,7 +420722,7 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:446" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid @@ -429488,7 +420791,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205824$15020 + cell $and $and$libresoc.v:200312$14791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429496,10 +420799,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:205824$15020_Y + connect \Y $and$libresoc.v:200312$14791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205826$15022 + cell $and $and$libresoc.v:200314$14793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429507,10 +420810,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:205826$15022_Y + connect \Y $and$libresoc.v:200314$14793_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205828$15024 + cell $and $and$libresoc.v:200316$14795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429518,10 +420821,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:205828$15024_Y + connect \Y $and$libresoc.v:200316$14795_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205830$15026 + cell $and $and$libresoc.v:200318$14797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429529,10 +420832,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:205830$15026_Y + connect \Y $and$libresoc.v:200318$14797_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205832$15028 + cell $and $and$libresoc.v:200320$14799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429540,10 +420843,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:205832$15028_Y + connect \Y $and$libresoc.v:200320$14799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205834$15030 + cell $and $and$libresoc.v:200322$14801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429551,10 +420854,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:205834$15030_Y + connect \Y $and$libresoc.v:200322$14801_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205836$15032 + cell $and $and$libresoc.v:200324$14803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429562,10 +420865,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:205836$15032_Y + connect \Y $and$libresoc.v:200324$14803_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205839$15035 + cell $and $and$libresoc.v:200327$14806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429573,10 +420876,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:205839$15035_Y + connect \Y $and$libresoc.v:200327$14806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205841$15037 + cell $and $and$libresoc.v:200329$14808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429584,10 +420887,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:205841$15037_Y + connect \Y $and$libresoc.v:200329$14808_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205843$15039 + cell $and $and$libresoc.v:200331$14810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429595,10 +420898,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:205843$15039_Y + connect \Y $and$libresoc.v:200331$14810_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205846$15042 + cell $and $and$libresoc.v:200334$14813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429606,10 +420909,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:205846$15042_Y + connect \Y $and$libresoc.v:200334$14813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205848$15044 + cell $and $and$libresoc.v:200336$14815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429617,10 +420920,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:205848$15044_Y + connect \Y $and$libresoc.v:200336$14815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205850$15046 + cell $and $and$libresoc.v:200338$14817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429628,10 +420931,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:205850$15046_Y + connect \Y $and$libresoc.v:200338$14817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205852$15048 + cell $and $and$libresoc.v:200340$14819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429639,10 +420942,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:205852$15048_Y + connect \Y $and$libresoc.v:200340$14819_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205854$15050 + cell $and $and$libresoc.v:200342$14821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429650,10 +420953,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:205854$15050_Y + connect \Y $and$libresoc.v:200342$14821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205856$15052 + cell $and $and$libresoc.v:200344$14823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429661,10 +420964,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:205856$15052_Y + connect \Y $and$libresoc.v:200344$14823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205858$15054 + cell $and $and$libresoc.v:200346$14825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429672,10 +420975,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:205858$15054_Y + connect \Y $and$libresoc.v:200346$14825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205861$15057 + cell $and $and$libresoc.v:200349$14828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429683,10 +420986,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:205861$15057_Y + connect \Y $and$libresoc.v:200349$14828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205863$15059 + cell $and $and$libresoc.v:200351$14830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429694,10 +420997,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:205863$15059_Y + connect \Y $and$libresoc.v:200351$14830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205865$15061 + cell $and $and$libresoc.v:200353$14832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429705,10 +421008,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:205865$15061_Y + connect \Y $and$libresoc.v:200353$14832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205868$15064 + cell $and $and$libresoc.v:200356$14835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429716,10 +421019,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:205868$15064_Y + connect \Y $and$libresoc.v:200356$14835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205870$15066 + cell $and $and$libresoc.v:200358$14837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429727,10 +421030,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:205870$15066_Y + connect \Y $and$libresoc.v:200358$14837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205872$15068 + cell $and $and$libresoc.v:200360$14839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429738,10 +421041,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:205872$15068_Y + connect \Y $and$libresoc.v:200360$14839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205874$15070 + cell $and $and$libresoc.v:200362$14841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429749,10 +421052,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:205874$15070_Y + connect \Y $and$libresoc.v:200362$14841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205876$15072 + cell $and $and$libresoc.v:200364$14843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429760,10 +421063,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:205876$15072_Y + connect \Y $and$libresoc.v:200364$14843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205879$15075 + cell $and $and$libresoc.v:200367$14846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429771,10 +421074,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:205879$15075_Y + connect \Y $and$libresoc.v:200367$14846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:205903$15099 + cell $and $and$libresoc.v:200391$14870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429782,10 +421085,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:205903$15099_Y + connect \Y $and$libresoc.v:200391$14870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:205911$15107 + cell $and $and$libresoc.v:200399$14878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429793,10 +421096,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:205911$15107_Y + connect \Y $and$libresoc.v:200399$14878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205913$15109 + cell $and $and$libresoc.v:200401$14880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429804,10 +421107,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:205913$15109_Y + connect \Y $and$libresoc.v:200401$14880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205915$15111 + cell $and $and$libresoc.v:200403$14882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429815,10 +421118,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:205915$15111_Y + connect \Y $and$libresoc.v:200403$14882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205917$15113 + cell $and $and$libresoc.v:200405$14884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429826,10 +421129,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:205917$15113_Y + connect \Y $and$libresoc.v:200405$14884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205920$15116 + cell $and $and$libresoc.v:200408$14887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429837,10 +421140,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:205920$15116_Y + connect \Y $and$libresoc.v:200408$14887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205922$15118 + cell $and $and$libresoc.v:200410$14889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429848,10 +421151,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:205922$15118_Y + connect \Y $and$libresoc.v:200410$14889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:205924$15120 + cell $and $and$libresoc.v:200412$14891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -429859,10 +421162,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:205924$15120_Y + connect \Y $and$libresoc.v:200412$14891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205838$15034 + cell $eq $eq$libresoc.v:200326$14805 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -429870,10 +421173,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205838$15034_Y + connect \Y $eq$libresoc.v:200326$14805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205860$15056 + cell $eq $eq$libresoc.v:200348$14827 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -429881,10 +421184,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205860$15056_Y + connect \Y $eq$libresoc.v:200348$14827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:205877$15073 + cell $eq $eq$libresoc.v:200365$14844 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -429892,10 +421195,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:205877$15073_Y + connect \Y $eq$libresoc.v:200365$14844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205880$15076 + cell $eq $eq$libresoc.v:200368$14847 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -429903,10 +421206,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:205880$15076_Y + connect \Y $eq$libresoc.v:200368$14847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205882$15078 + cell $eq $eq$libresoc.v:200370$14849 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -429914,10 +421217,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205882$15078_Y + connect \Y $eq$libresoc.v:200370$14849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205884$15080 + cell $eq $eq$libresoc.v:200372$14851 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -429925,10 +421228,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205884$15080_Y + connect \Y $eq$libresoc.v:200372$14851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205886$15082 + cell $eq $eq$libresoc.v:200374$14853 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -429936,10 +421239,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205886$15082_Y + connect \Y $eq$libresoc.v:200374$14853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205888$15084 + cell $eq $eq$libresoc.v:200376$14855 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -429947,10 +421250,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205888$15084_Y + connect \Y $eq$libresoc.v:200376$14855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205890$15086 + cell $eq $eq$libresoc.v:200378$14857 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -429958,10 +421261,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205890$15086_Y + connect \Y $eq$libresoc.v:200378$14857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:205892$15088 + cell $eq $eq$libresoc.v:200380$14859 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -429969,10 +421272,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:205892$15088_Y + connect \Y $eq$libresoc.v:200380$14859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205893$15089 + cell $eq $eq$libresoc.v:200381$14860 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -429980,10 +421283,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205893$15089_Y + connect \Y $eq$libresoc.v:200381$14860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205895$15091 + cell $eq $eq$libresoc.v:200383$14862 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -429991,10 +421294,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205895$15091_Y + connect \Y $eq$libresoc.v:200383$14862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205897$15093 + cell $eq $eq$libresoc.v:200385$14864 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430002,10 +421305,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205897$15093_Y + connect \Y $eq$libresoc.v:200385$14864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205899$15095 + cell $eq $eq$libresoc.v:200387$14866 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430013,10 +421316,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205899$15095_Y + connect \Y $eq$libresoc.v:200387$14866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205901$15097 + cell $eq $eq$libresoc.v:200389$14868 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430024,10 +421327,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205901$15097_Y + connect \Y $eq$libresoc.v:200389$14868_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205904$15100 + cell $eq $eq$libresoc.v:200392$14871 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430035,10 +421338,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205904$15100_Y + connect \Y $eq$libresoc.v:200392$14871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205906$15102 + cell $eq $eq$libresoc.v:200394$14873 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430046,10 +421349,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205906$15102_Y + connect \Y $eq$libresoc.v:200394$14873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205908$15104 + cell $eq $eq$libresoc.v:200396$14875 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430057,10 +421360,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205908$15104_Y + connect \Y $eq$libresoc.v:200396$14875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:205919$15115 + cell $eq $eq$libresoc.v:200407$14886 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430068,10 +421371,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:205919$15115_Y + connect \Y $eq$libresoc.v:200407$14886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205823$15019 + cell $lt $lt$libresoc.v:200311$14790 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430079,10 +421382,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:205823$15019_Y + connect \Y $lt$libresoc.v:200311$14790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205825$15021 + cell $lt $lt$libresoc.v:200313$14792 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430090,10 +421393,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:205825$15021_Y + connect \Y $lt$libresoc.v:200313$14792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205827$15023 + cell $lt $lt$libresoc.v:200315$14794 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430101,10 +421404,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:205827$15023_Y + connect \Y $lt$libresoc.v:200315$14794_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205829$15025 + cell $lt $lt$libresoc.v:200317$14796 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430112,10 +421415,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:205829$15025_Y + connect \Y $lt$libresoc.v:200317$14796_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205831$15027 + cell $lt $lt$libresoc.v:200319$14798 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430123,10 +421426,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:205831$15027_Y + connect \Y $lt$libresoc.v:200319$14798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205833$15029 + cell $lt $lt$libresoc.v:200321$14800 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430134,10 +421437,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:205833$15029_Y + connect \Y $lt$libresoc.v:200321$14800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205835$15031 + cell $lt $lt$libresoc.v:200323$14802 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430145,10 +421448,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:205835$15031_Y + connect \Y $lt$libresoc.v:200323$14802_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205837$15033 + cell $lt $lt$libresoc.v:200325$14804 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430156,10 +421459,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:205837$15033_Y + connect \Y $lt$libresoc.v:200325$14804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205840$15036 + cell $lt $lt$libresoc.v:200328$14807 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430167,10 +421470,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:205840$15036_Y + connect \Y $lt$libresoc.v:200328$14807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205842$15038 + cell $lt $lt$libresoc.v:200330$14809 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430178,10 +421481,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:205842$15038_Y + connect \Y $lt$libresoc.v:200330$14809_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205845$15041 + cell $lt $lt$libresoc.v:200333$14812 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430189,10 +421492,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:205845$15041_Y + connect \Y $lt$libresoc.v:200333$14812_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205847$15043 + cell $lt $lt$libresoc.v:200335$14814 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430200,10 +421503,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:205847$15043_Y + connect \Y $lt$libresoc.v:200335$14814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205849$15045 + cell $lt $lt$libresoc.v:200337$14816 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430211,10 +421514,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:205849$15045_Y + connect \Y $lt$libresoc.v:200337$14816_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205851$15047 + cell $lt $lt$libresoc.v:200339$14818 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430222,10 +421525,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:205851$15047_Y + connect \Y $lt$libresoc.v:200339$14818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205853$15049 + cell $lt $lt$libresoc.v:200341$14820 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430233,10 +421536,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:205853$15049_Y + connect \Y $lt$libresoc.v:200341$14820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205855$15051 + cell $lt $lt$libresoc.v:200343$14822 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430244,10 +421547,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:205855$15051_Y + connect \Y $lt$libresoc.v:200343$14822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205857$15053 + cell $lt $lt$libresoc.v:200345$14824 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430255,10 +421558,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:205857$15053_Y + connect \Y $lt$libresoc.v:200345$14824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205859$15055 + cell $lt $lt$libresoc.v:200347$14826 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430266,10 +421569,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:205859$15055_Y + connect \Y $lt$libresoc.v:200347$14826_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205862$15058 + cell $lt $lt$libresoc.v:200350$14829 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430277,10 +421580,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:205862$15058_Y + connect \Y $lt$libresoc.v:200350$14829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205864$15060 + cell $lt $lt$libresoc.v:200352$14831 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430288,10 +421591,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:205864$15060_Y + connect \Y $lt$libresoc.v:200352$14831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205867$15063 + cell $lt $lt$libresoc.v:200355$14834 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430299,10 +421602,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:205867$15063_Y + connect \Y $lt$libresoc.v:200355$14834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205869$15065 + cell $lt $lt$libresoc.v:200357$14836 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430310,10 +421613,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:205869$15065_Y + connect \Y $lt$libresoc.v:200357$14836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205871$15067 + cell $lt $lt$libresoc.v:200359$14838 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430321,10 +421624,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:205871$15067_Y + connect \Y $lt$libresoc.v:200359$14838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205873$15069 + cell $lt $lt$libresoc.v:200361$14840 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430332,10 +421635,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:205873$15069_Y + connect \Y $lt$libresoc.v:200361$14840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205875$15071 + cell $lt $lt$libresoc.v:200363$14842 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430343,10 +421646,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:205875$15071_Y + connect \Y $lt$libresoc.v:200363$14842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205878$15074 + cell $lt $lt$libresoc.v:200366$14845 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430354,10 +421657,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:205878$15074_Y + connect \Y $lt$libresoc.v:200366$14845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205912$15108 + cell $lt $lt$libresoc.v:200400$14879 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430365,10 +421668,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:205912$15108_Y + connect \Y $lt$libresoc.v:200400$14879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205914$15110 + cell $lt $lt$libresoc.v:200402$14881 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430376,10 +421679,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:205914$15110_Y + connect \Y $lt$libresoc.v:200402$14881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205916$15112 + cell $lt $lt$libresoc.v:200404$14883 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430387,10 +421690,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:205916$15112_Y + connect \Y $lt$libresoc.v:200404$14883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205918$15114 + cell $lt $lt$libresoc.v:200406$14885 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430398,10 +421701,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:205918$15114_Y + connect \Y $lt$libresoc.v:200406$14885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205921$15117 + cell $lt $lt$libresoc.v:200409$14888 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430409,10 +421712,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:205921$15117_Y + connect \Y $lt$libresoc.v:200409$14888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:205923$15119 + cell $lt $lt$libresoc.v:200411$14890 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -430420,10 +421723,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:205923$15119_Y + connect \Y $lt$libresoc.v:200411$14890_Y end - attribute \src "libresoc.v:205910.18-205910.40" - cell $shr $shr$libresoc.v:205910$15106 + attribute \src "libresoc.v:200398.18-200398.40" + cell $shr $shr$libresoc.v:200398$14877 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -430431,469 +421734,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:205910$15106_Y + connect \Y $shr$libresoc.v:200398$14877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205822$15018 + cell $mux $ternary$libresoc.v:200310$14789 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:205822$15018_Y + connect \Y $ternary$libresoc.v:200310$14789_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205844$15040 + cell $mux $ternary$libresoc.v:200332$14811 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:205844$15040_Y + connect \Y $ternary$libresoc.v:200332$14811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205866$15062 + cell $mux $ternary$libresoc.v:200354$14833 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:205866$15062_Y + connect \Y $ternary$libresoc.v:200354$14833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205881$15077 + cell $mux $ternary$libresoc.v:200369$14848 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:205881$15077_Y + connect \Y $ternary$libresoc.v:200369$14848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205883$15079 + cell $mux $ternary$libresoc.v:200371$14850 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:205883$15079_Y + connect \Y $ternary$libresoc.v:200371$14850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205885$15081 + cell $mux $ternary$libresoc.v:200373$14852 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:205885$15081_Y + connect \Y $ternary$libresoc.v:200373$14852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205887$15083 + cell $mux $ternary$libresoc.v:200375$14854 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:205887$15083_Y + connect \Y $ternary$libresoc.v:200375$14854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205889$15085 + cell $mux $ternary$libresoc.v:200377$14856 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:205889$15085_Y + connect \Y $ternary$libresoc.v:200377$14856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205891$15087 + cell $mux $ternary$libresoc.v:200379$14858 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:205891$15087_Y + connect \Y $ternary$libresoc.v:200379$14858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205894$15090 + cell $mux $ternary$libresoc.v:200382$14861 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:205894$15090_Y + connect \Y $ternary$libresoc.v:200382$14861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205896$15092 + cell $mux $ternary$libresoc.v:200384$14863 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:205896$15092_Y + connect \Y $ternary$libresoc.v:200384$14863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205898$15094 + cell $mux $ternary$libresoc.v:200386$14865 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:205898$15094_Y + connect \Y $ternary$libresoc.v:200386$14865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205900$15096 + cell $mux $ternary$libresoc.v:200388$14867 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:205900$15096_Y + connect \Y $ternary$libresoc.v:200388$14867_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205902$15098 + cell $mux $ternary$libresoc.v:200390$14869 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:205902$15098_Y + connect \Y $ternary$libresoc.v:200390$14869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205905$15101 + cell $mux $ternary$libresoc.v:200393$14872 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:205905$15101_Y + connect \Y $ternary$libresoc.v:200393$14872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205907$15103 + cell $mux $ternary$libresoc.v:200395$14874 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:205907$15103_Y + connect \Y $ternary$libresoc.v:200395$14874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:205909$15105 + cell $mux $ternary$libresoc.v:200397$14876 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:205909$15105_Y + connect \Y $ternary$libresoc.v:200397$14876_Y end - attribute \src "libresoc.v:205423.7-205423.20" - process $proc$libresoc.v:205423$15266 + attribute \src "libresoc.v:199911.7-199911.20" + process $proc$libresoc.v:199911$15037 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:205704.13-205704.30" - process $proc$libresoc.v:205704$15267 + attribute \src "libresoc.v:200192.13-200192.30" + process $proc$libresoc.v:200192$15038 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:205709.13-205709.29" - process $proc$libresoc.v:205709$15268 + attribute \src "libresoc.v:200197.13-200197.29" + process $proc$libresoc.v:200197$15039 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:205718.7-205718.25" - process $proc$libresoc.v:205718$15269 + attribute \src "libresoc.v:200206.7-200206.25" + process $proc$libresoc.v:200206$15040 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:205727.14-205727.35" - process $proc$libresoc.v:205727$15270 + attribute \src "libresoc.v:200215.14-200215.35" + process $proc$libresoc.v:200215$15041 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:205739.14-205739.36" - process $proc$libresoc.v:205739$15271 + attribute \src "libresoc.v:200227.14-200227.36" + process $proc$libresoc.v:200227$15042 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:205759.13-205759.30" - process $proc$libresoc.v:205759$15272 + attribute \src "libresoc.v:200247.13-200247.30" + process $proc$libresoc.v:200247$15043 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:205763.13-205763.31" - process $proc$libresoc.v:205763$15273 + attribute \src "libresoc.v:200251.13-200251.31" + process $proc$libresoc.v:200251$15044 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:205767.13-205767.31" - process $proc$libresoc.v:205767$15274 + attribute \src "libresoc.v:200255.13-200255.31" + process $proc$libresoc.v:200255$15045 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:205771.13-205771.31" - process $proc$libresoc.v:205771$15275 + attribute \src "libresoc.v:200259.13-200259.31" + process $proc$libresoc.v:200259$15046 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:205775.13-205775.31" - process $proc$libresoc.v:205775$15276 + attribute \src "libresoc.v:200263.13-200263.31" + process $proc$libresoc.v:200263$15047 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:205779.13-205779.31" - process $proc$libresoc.v:205779$15277 + attribute \src "libresoc.v:200267.13-200267.31" + process $proc$libresoc.v:200267$15048 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:205783.13-205783.31" - process $proc$libresoc.v:205783$15278 + attribute \src "libresoc.v:200271.13-200271.31" + process $proc$libresoc.v:200271$15049 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:205787.13-205787.30" - process $proc$libresoc.v:205787$15279 + attribute \src "libresoc.v:200275.13-200275.30" + process $proc$libresoc.v:200275$15050 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:205791.13-205791.30" - process $proc$libresoc.v:205791$15280 + attribute \src "libresoc.v:200279.13-200279.30" + process $proc$libresoc.v:200279$15051 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:205795.13-205795.30" - process $proc$libresoc.v:205795$15281 + attribute \src "libresoc.v:200283.13-200283.30" + process $proc$libresoc.v:200283$15052 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:205799.13-205799.30" - process $proc$libresoc.v:205799$15282 + attribute \src "libresoc.v:200287.13-200287.30" + process $proc$libresoc.v:200287$15053 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:205803.13-205803.30" - process $proc$libresoc.v:205803$15283 + attribute \src "libresoc.v:200291.13-200291.30" + process $proc$libresoc.v:200291$15054 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:205807.13-205807.30" - process $proc$libresoc.v:205807$15284 + attribute \src "libresoc.v:200295.13-200295.30" + process $proc$libresoc.v:200295$15055 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:205811.13-205811.30" - process $proc$libresoc.v:205811$15285 + attribute \src "libresoc.v:200299.13-200299.30" + process $proc$libresoc.v:200299$15056 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:205815.13-205815.30" - process $proc$libresoc.v:205815$15286 + attribute \src "libresoc.v:200303.13-200303.30" + process $proc$libresoc.v:200303$15057 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:205819.13-205819.30" - process $proc$libresoc.v:205819$15287 + attribute \src "libresoc.v:200307.13-200307.30" + process $proc$libresoc.v:200307$15058 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:205925.3-205926.28" - process $proc$libresoc.v:205925$15121 + attribute \src "libresoc.v:200413.3-200414.28" + process $proc$libresoc.v:200413$14892 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:205927.3-205928.25" - process $proc$libresoc.v:205927$15122 + attribute \src "libresoc.v:200415.3-200416.25" + process $proc$libresoc.v:200415$14893 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:205929.3-205930.35" - process $proc$libresoc.v:205929$15123 + attribute \src "libresoc.v:200417.3-200418.35" + process $proc$libresoc.v:200417$14894 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:205931.3-205932.35" - process $proc$libresoc.v:205931$15124 + attribute \src "libresoc.v:200419.3-200420.35" + process $proc$libresoc.v:200419$14895 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:205933.3-205934.35" - process $proc$libresoc.v:205933$15125 + attribute \src "libresoc.v:200421.3-200422.35" + process $proc$libresoc.v:200421$14896 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:205935.3-205936.35" - process $proc$libresoc.v:205935$15126 + attribute \src "libresoc.v:200423.3-200424.35" + process $proc$libresoc.v:200423$14897 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:205937.3-205938.35" - process $proc$libresoc.v:205937$15127 + attribute \src "libresoc.v:200425.3-200426.35" + process $proc$libresoc.v:200425$14898 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:205939.3-205940.35" - process $proc$libresoc.v:205939$15128 + attribute \src "libresoc.v:200427.3-200428.35" + process $proc$libresoc.v:200427$14899 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:205941.3-205942.35" - process $proc$libresoc.v:205941$15129 + attribute \src "libresoc.v:200429.3-200430.35" + process $proc$libresoc.v:200429$14900 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:205943.3-205944.35" - process $proc$libresoc.v:205943$15130 + attribute \src "libresoc.v:200431.3-200432.35" + process $proc$libresoc.v:200431$14901 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:205945.3-205946.35" - process $proc$libresoc.v:205945$15131 + attribute \src "libresoc.v:200433.3-200434.35" + process $proc$libresoc.v:200433$14902 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:205947.3-205948.35" - process $proc$libresoc.v:205947$15132 + attribute \src "libresoc.v:200435.3-200436.35" + process $proc$libresoc.v:200435$14903 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:205949.3-205950.37" - process $proc$libresoc.v:205949$15133 + attribute \src "libresoc.v:200437.3-200438.37" + process $proc$libresoc.v:200437$14904 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:205951.3-205952.37" - process $proc$libresoc.v:205951$15134 + attribute \src "libresoc.v:200439.3-200440.37" + process $proc$libresoc.v:200439$14905 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:205953.3-205954.37" - process $proc$libresoc.v:205953$15135 + attribute \src "libresoc.v:200441.3-200442.37" + process $proc$libresoc.v:200441$14906 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:205955.3-205956.37" - process $proc$libresoc.v:205955$15136 + attribute \src "libresoc.v:200443.3-200444.37" + process $proc$libresoc.v:200443$14907 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:205957.3-205958.37" - process $proc$libresoc.v:205957$15137 + attribute \src "libresoc.v:200445.3-200446.37" + process $proc$libresoc.v:200445$14908 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:205959.3-205960.37" - process $proc$libresoc.v:205959$15138 + attribute \src "libresoc.v:200447.3-200448.37" + process $proc$libresoc.v:200447$14909 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:205961.3-205962.39" - process $proc$libresoc.v:205961$15139 + attribute \src "libresoc.v:200449.3-200450.39" + process $proc$libresoc.v:200449$14910 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:205963.3-205964.43" - process $proc$libresoc.v:205963$15140 + attribute \src "libresoc.v:200451.3-200452.43" + process $proc$libresoc.v:200451$14911 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:205965.3-205966.39" - process $proc$libresoc.v:205965$15141 + attribute \src "libresoc.v:200453.3-200454.39" + process $proc$libresoc.v:200453$14912 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:205967.3-206052.6" - process $proc$libresoc.v:205967$15142 + attribute \src "libresoc.v:200455.3-200540.6" + process $proc$libresoc.v:200455$14913 assign { } { } assign { } { } assign { } { } @@ -430942,25 +422245,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$15143 $4\xive0_pri$next[7:0]$15207 - assign $0\xive10_pri$next[7:0]$15144 $4\xive10_pri$next[7:0]$15208 - assign $0\xive11_pri$next[7:0]$15145 $4\xive11_pri$next[7:0]$15209 - assign $0\xive12_pri$next[7:0]$15146 $4\xive12_pri$next[7:0]$15210 - assign $0\xive13_pri$next[7:0]$15147 $4\xive13_pri$next[7:0]$15211 - assign $0\xive14_pri$next[7:0]$15148 $4\xive14_pri$next[7:0]$15212 - assign $0\xive15_pri$next[7:0]$15149 $4\xive15_pri$next[7:0]$15213 - assign $0\xive1_pri$next[7:0]$15150 $4\xive1_pri$next[7:0]$15214 - assign $0\xive2_pri$next[7:0]$15151 $4\xive2_pri$next[7:0]$15215 - assign $0\xive3_pri$next[7:0]$15152 $4\xive3_pri$next[7:0]$15216 - assign $0\xive4_pri$next[7:0]$15153 $4\xive4_pri$next[7:0]$15217 - assign $0\xive5_pri$next[7:0]$15154 $4\xive5_pri$next[7:0]$15218 - assign $0\xive6_pri$next[7:0]$15155 $4\xive6_pri$next[7:0]$15219 - assign $0\xive7_pri$next[7:0]$15156 $4\xive7_pri$next[7:0]$15220 - assign $0\xive8_pri$next[7:0]$15157 $4\xive8_pri$next[7:0]$15221 - assign $0\xive9_pri$next[7:0]$15158 $4\xive9_pri$next[7:0]$15222 - attribute \src "libresoc.v:205968.5-205968.29" + assign $0\xive0_pri$next[7:0]$14914 $4\xive0_pri$next[7:0]$14978 + assign $0\xive10_pri$next[7:0]$14915 $4\xive10_pri$next[7:0]$14979 + assign $0\xive11_pri$next[7:0]$14916 $4\xive11_pri$next[7:0]$14980 + assign $0\xive12_pri$next[7:0]$14917 $4\xive12_pri$next[7:0]$14981 + assign $0\xive13_pri$next[7:0]$14918 $4\xive13_pri$next[7:0]$14982 + assign $0\xive14_pri$next[7:0]$14919 $4\xive14_pri$next[7:0]$14983 + assign $0\xive15_pri$next[7:0]$14920 $4\xive15_pri$next[7:0]$14984 + assign $0\xive1_pri$next[7:0]$14921 $4\xive1_pri$next[7:0]$14985 + assign $0\xive2_pri$next[7:0]$14922 $4\xive2_pri$next[7:0]$14986 + assign $0\xive3_pri$next[7:0]$14923 $4\xive3_pri$next[7:0]$14987 + assign $0\xive4_pri$next[7:0]$14924 $4\xive4_pri$next[7:0]$14988 + assign $0\xive5_pri$next[7:0]$14925 $4\xive5_pri$next[7:0]$14989 + assign $0\xive6_pri$next[7:0]$14926 $4\xive6_pri$next[7:0]$14990 + assign $0\xive7_pri$next[7:0]$14927 $4\xive7_pri$next[7:0]$14991 + assign $0\xive8_pri$next[7:0]$14928 $4\xive8_pri$next[7:0]$14992 + assign $0\xive9_pri$next[7:0]$14929 $4\xive9_pri$next[7:0]$14993 + attribute \src "libresoc.v:200456.5-200456.29" switch \initial - attribute \src "libresoc.v:205968.9-205968.17" + attribute \src "libresoc.v:200456.9-200456.17" case 1'1 case end @@ -430984,22 +422287,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$15159 $2\xive0_pri$next[7:0]$15175 - assign $1\xive10_pri$next[7:0]$15160 $2\xive10_pri$next[7:0]$15176 - assign $1\xive11_pri$next[7:0]$15161 $2\xive11_pri$next[7:0]$15177 - assign $1\xive12_pri$next[7:0]$15162 $2\xive12_pri$next[7:0]$15178 - assign $1\xive13_pri$next[7:0]$15163 $2\xive13_pri$next[7:0]$15179 - assign $1\xive14_pri$next[7:0]$15164 $2\xive14_pri$next[7:0]$15180 - assign $1\xive15_pri$next[7:0]$15165 $2\xive15_pri$next[7:0]$15181 - assign $1\xive1_pri$next[7:0]$15166 $2\xive1_pri$next[7:0]$15182 - assign $1\xive2_pri$next[7:0]$15167 $2\xive2_pri$next[7:0]$15183 - assign $1\xive3_pri$next[7:0]$15168 $2\xive3_pri$next[7:0]$15184 - assign $1\xive4_pri$next[7:0]$15169 $2\xive4_pri$next[7:0]$15185 - assign $1\xive5_pri$next[7:0]$15170 $2\xive5_pri$next[7:0]$15186 - assign $1\xive6_pri$next[7:0]$15171 $2\xive6_pri$next[7:0]$15187 - assign $1\xive7_pri$next[7:0]$15172 $2\xive7_pri$next[7:0]$15188 - assign $1\xive8_pri$next[7:0]$15173 $2\xive8_pri$next[7:0]$15189 - assign $1\xive9_pri$next[7:0]$15174 $2\xive9_pri$next[7:0]$15190 + assign $1\xive0_pri$next[7:0]$14930 $2\xive0_pri$next[7:0]$14946 + assign $1\xive10_pri$next[7:0]$14931 $2\xive10_pri$next[7:0]$14947 + assign $1\xive11_pri$next[7:0]$14932 $2\xive11_pri$next[7:0]$14948 + assign $1\xive12_pri$next[7:0]$14933 $2\xive12_pri$next[7:0]$14949 + assign $1\xive13_pri$next[7:0]$14934 $2\xive13_pri$next[7:0]$14950 + assign $1\xive14_pri$next[7:0]$14935 $2\xive14_pri$next[7:0]$14951 + assign $1\xive15_pri$next[7:0]$14936 $2\xive15_pri$next[7:0]$14952 + assign $1\xive1_pri$next[7:0]$14937 $2\xive1_pri$next[7:0]$14953 + assign $1\xive2_pri$next[7:0]$14938 $2\xive2_pri$next[7:0]$14954 + assign $1\xive3_pri$next[7:0]$14939 $2\xive3_pri$next[7:0]$14955 + assign $1\xive4_pri$next[7:0]$14940 $2\xive4_pri$next[7:0]$14956 + assign $1\xive5_pri$next[7:0]$14941 $2\xive5_pri$next[7:0]$14957 + assign $1\xive6_pri$next[7:0]$14942 $2\xive6_pri$next[7:0]$14958 + assign $1\xive7_pri$next[7:0]$14943 $2\xive7_pri$next[7:0]$14959 + assign $1\xive8_pri$next[7:0]$14944 $2\xive8_pri$next[7:0]$14960 + assign $1\xive9_pri$next[7:0]$14945 $2\xive9_pri$next[7:0]$14961 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -431020,381 +422323,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$15175 $3\xive0_pri$next[7:0]$15191 - assign $2\xive10_pri$next[7:0]$15176 $3\xive10_pri$next[7:0]$15192 - assign $2\xive11_pri$next[7:0]$15177 $3\xive11_pri$next[7:0]$15193 - assign $2\xive12_pri$next[7:0]$15178 $3\xive12_pri$next[7:0]$15194 - assign $2\xive13_pri$next[7:0]$15179 $3\xive13_pri$next[7:0]$15195 - assign $2\xive14_pri$next[7:0]$15180 $3\xive14_pri$next[7:0]$15196 - assign $2\xive15_pri$next[7:0]$15181 $3\xive15_pri$next[7:0]$15197 - assign $2\xive1_pri$next[7:0]$15182 $3\xive1_pri$next[7:0]$15198 - assign $2\xive2_pri$next[7:0]$15183 $3\xive2_pri$next[7:0]$15199 - assign $2\xive3_pri$next[7:0]$15184 $3\xive3_pri$next[7:0]$15200 - assign $2\xive4_pri$next[7:0]$15185 $3\xive4_pri$next[7:0]$15201 - assign $2\xive5_pri$next[7:0]$15186 $3\xive5_pri$next[7:0]$15202 - assign $2\xive6_pri$next[7:0]$15187 $3\xive6_pri$next[7:0]$15203 - assign $2\xive7_pri$next[7:0]$15188 $3\xive7_pri$next[7:0]$15204 - assign $2\xive8_pri$next[7:0]$15189 $3\xive8_pri$next[7:0]$15205 - assign $2\xive9_pri$next[7:0]$15190 $3\xive9_pri$next[7:0]$15206 + assign $2\xive0_pri$next[7:0]$14946 $3\xive0_pri$next[7:0]$14962 + assign $2\xive10_pri$next[7:0]$14947 $3\xive10_pri$next[7:0]$14963 + assign $2\xive11_pri$next[7:0]$14948 $3\xive11_pri$next[7:0]$14964 + assign $2\xive12_pri$next[7:0]$14949 $3\xive12_pri$next[7:0]$14965 + assign $2\xive13_pri$next[7:0]$14950 $3\xive13_pri$next[7:0]$14966 + assign $2\xive14_pri$next[7:0]$14951 $3\xive14_pri$next[7:0]$14967 + assign $2\xive15_pri$next[7:0]$14952 $3\xive15_pri$next[7:0]$14968 + assign $2\xive1_pri$next[7:0]$14953 $3\xive1_pri$next[7:0]$14969 + assign $2\xive2_pri$next[7:0]$14954 $3\xive2_pri$next[7:0]$14970 + assign $2\xive3_pri$next[7:0]$14955 $3\xive3_pri$next[7:0]$14971 + assign $2\xive4_pri$next[7:0]$14956 $3\xive4_pri$next[7:0]$14972 + assign $2\xive5_pri$next[7:0]$14957 $3\xive5_pri$next[7:0]$14973 + assign $2\xive6_pri$next[7:0]$14958 $3\xive6_pri$next[7:0]$14974 + assign $2\xive7_pri$next[7:0]$14959 $3\xive7_pri$next[7:0]$14975 + assign $2\xive8_pri$next[7:0]$14960 $3\xive8_pri$next[7:0]$14976 + assign $2\xive9_pri$next[7:0]$14961 $3\xive9_pri$next[7:0]$14977 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive0_pri$next[7:0]$15191 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive0_pri$next[7:0]$14962 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive1_pri$next[7:0]$15198 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive1_pri$next[7:0]$14969 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive2_pri$next[7:0]$15199 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive2_pri$next[7:0]$14970 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive3_pri$next[7:0]$15200 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive3_pri$next[7:0]$14971 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive4_pri$next[7:0]$15201 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive4_pri$next[7:0]$14972 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive5_pri$next[7:0]$15202 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive5_pri$next[7:0]$14973 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive6_pri$next[7:0]$15203 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive6_pri$next[7:0]$14974 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive7_pri$next[7:0]$15204 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive7_pri$next[7:0]$14975 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive8_pri$next[7:0]$15205 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive8_pri$next[7:0]$14976 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$15206 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14977 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive10_pri$next[7:0]$15192 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive10_pri$next[7:0]$14963 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive11_pri$next[7:0]$15193 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive11_pri$next[7:0]$14964 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive12_pri$next[7:0]$15194 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive12_pri$next[7:0]$14965 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive13_pri$next[7:0]$15195 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive13_pri$next[7:0]$14966 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive14_pri$next[7:0]$15196 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive14_pri$next[7:0]$14967 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri - assign $3\xive15_pri$next[7:0]$15197 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri + assign $3\xive15_pri$next[7:0]$14968 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$15191 \xive0_pri - assign $3\xive10_pri$next[7:0]$15192 \xive10_pri - assign $3\xive11_pri$next[7:0]$15193 \xive11_pri - assign $3\xive12_pri$next[7:0]$15194 \xive12_pri - assign $3\xive13_pri$next[7:0]$15195 \xive13_pri - assign $3\xive14_pri$next[7:0]$15196 \xive14_pri - assign $3\xive15_pri$next[7:0]$15197 \xive15_pri - assign $3\xive1_pri$next[7:0]$15198 \xive1_pri - assign $3\xive2_pri$next[7:0]$15199 \xive2_pri - assign $3\xive3_pri$next[7:0]$15200 \xive3_pri - assign $3\xive4_pri$next[7:0]$15201 \xive4_pri - assign $3\xive5_pri$next[7:0]$15202 \xive5_pri - assign $3\xive6_pri$next[7:0]$15203 \xive6_pri - assign $3\xive7_pri$next[7:0]$15204 \xive7_pri - assign $3\xive8_pri$next[7:0]$15205 \xive8_pri - assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive0_pri$next[7:0]$14962 \xive0_pri + assign $3\xive10_pri$next[7:0]$14963 \xive10_pri + assign $3\xive11_pri$next[7:0]$14964 \xive11_pri + assign $3\xive12_pri$next[7:0]$14965 \xive12_pri + assign $3\xive13_pri$next[7:0]$14966 \xive13_pri + assign $3\xive14_pri$next[7:0]$14967 \xive14_pri + assign $3\xive15_pri$next[7:0]$14968 \xive15_pri + assign $3\xive1_pri$next[7:0]$14969 \xive1_pri + assign $3\xive2_pri$next[7:0]$14970 \xive2_pri + assign $3\xive3_pri$next[7:0]$14971 \xive3_pri + assign $3\xive4_pri$next[7:0]$14972 \xive4_pri + assign $3\xive5_pri$next[7:0]$14973 \xive5_pri + assign $3\xive6_pri$next[7:0]$14974 \xive6_pri + assign $3\xive7_pri$next[7:0]$14975 \xive7_pri + assign $3\xive8_pri$next[7:0]$14976 \xive8_pri + assign $3\xive9_pri$next[7:0]$14977 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$15175 \xive0_pri - assign $2\xive10_pri$next[7:0]$15176 \xive10_pri - assign $2\xive11_pri$next[7:0]$15177 \xive11_pri - assign $2\xive12_pri$next[7:0]$15178 \xive12_pri - assign $2\xive13_pri$next[7:0]$15179 \xive13_pri - assign $2\xive14_pri$next[7:0]$15180 \xive14_pri - assign $2\xive15_pri$next[7:0]$15181 \xive15_pri - assign $2\xive1_pri$next[7:0]$15182 \xive1_pri - assign $2\xive2_pri$next[7:0]$15183 \xive2_pri - assign $2\xive3_pri$next[7:0]$15184 \xive3_pri - assign $2\xive4_pri$next[7:0]$15185 \xive4_pri - assign $2\xive5_pri$next[7:0]$15186 \xive5_pri - assign $2\xive6_pri$next[7:0]$15187 \xive6_pri - assign $2\xive7_pri$next[7:0]$15188 \xive7_pri - assign $2\xive8_pri$next[7:0]$15189 \xive8_pri - assign $2\xive9_pri$next[7:0]$15190 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$15159 \xive0_pri - assign $1\xive10_pri$next[7:0]$15160 \xive10_pri - assign $1\xive11_pri$next[7:0]$15161 \xive11_pri - assign $1\xive12_pri$next[7:0]$15162 \xive12_pri - assign $1\xive13_pri$next[7:0]$15163 \xive13_pri - assign $1\xive14_pri$next[7:0]$15164 \xive14_pri - assign $1\xive15_pri$next[7:0]$15165 \xive15_pri - assign $1\xive1_pri$next[7:0]$15166 \xive1_pri - assign $1\xive2_pri$next[7:0]$15167 \xive2_pri - assign $1\xive3_pri$next[7:0]$15168 \xive3_pri - assign $1\xive4_pri$next[7:0]$15169 \xive4_pri - assign $1\xive5_pri$next[7:0]$15170 \xive5_pri - assign $1\xive6_pri$next[7:0]$15171 \xive6_pri - assign $1\xive7_pri$next[7:0]$15172 \xive7_pri - assign $1\xive8_pri$next[7:0]$15173 \xive8_pri - assign $1\xive9_pri$next[7:0]$15174 \xive9_pri + assign $2\xive0_pri$next[7:0]$14946 \xive0_pri + assign $2\xive10_pri$next[7:0]$14947 \xive10_pri + assign $2\xive11_pri$next[7:0]$14948 \xive11_pri + assign $2\xive12_pri$next[7:0]$14949 \xive12_pri + assign $2\xive13_pri$next[7:0]$14950 \xive13_pri + assign $2\xive14_pri$next[7:0]$14951 \xive14_pri + assign $2\xive15_pri$next[7:0]$14952 \xive15_pri + assign $2\xive1_pri$next[7:0]$14953 \xive1_pri + assign $2\xive2_pri$next[7:0]$14954 \xive2_pri + assign $2\xive3_pri$next[7:0]$14955 \xive3_pri + assign $2\xive4_pri$next[7:0]$14956 \xive4_pri + assign $2\xive5_pri$next[7:0]$14957 \xive5_pri + assign $2\xive6_pri$next[7:0]$14958 \xive6_pri + assign $2\xive7_pri$next[7:0]$14959 \xive7_pri + assign $2\xive8_pri$next[7:0]$14960 \xive8_pri + assign $2\xive9_pri$next[7:0]$14961 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14930 \xive0_pri + assign $1\xive10_pri$next[7:0]$14931 \xive10_pri + assign $1\xive11_pri$next[7:0]$14932 \xive11_pri + assign $1\xive12_pri$next[7:0]$14933 \xive12_pri + assign $1\xive13_pri$next[7:0]$14934 \xive13_pri + assign $1\xive14_pri$next[7:0]$14935 \xive14_pri + assign $1\xive15_pri$next[7:0]$14936 \xive15_pri + assign $1\xive1_pri$next[7:0]$14937 \xive1_pri + assign $1\xive2_pri$next[7:0]$14938 \xive2_pri + assign $1\xive3_pri$next[7:0]$14939 \xive3_pri + assign $1\xive4_pri$next[7:0]$14940 \xive4_pri + assign $1\xive5_pri$next[7:0]$14941 \xive5_pri + assign $1\xive6_pri$next[7:0]$14942 \xive6_pri + assign $1\xive7_pri$next[7:0]$14943 \xive7_pri + assign $1\xive8_pri$next[7:0]$14944 \xive8_pri + assign $1\xive9_pri$next[7:0]$14945 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -431416,66 +422719,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$15207 8'11111111 - assign $4\xive1_pri$next[7:0]$15214 8'11111111 - assign $4\xive2_pri$next[7:0]$15215 8'11111111 - assign $4\xive3_pri$next[7:0]$15216 8'11111111 - assign $4\xive4_pri$next[7:0]$15217 8'11111111 - assign $4\xive5_pri$next[7:0]$15218 8'11111111 - assign $4\xive6_pri$next[7:0]$15219 8'11111111 - assign $4\xive7_pri$next[7:0]$15220 8'11111111 - assign $4\xive8_pri$next[7:0]$15221 8'11111111 - assign $4\xive9_pri$next[7:0]$15222 8'11111111 - assign $4\xive10_pri$next[7:0]$15208 8'11111111 - assign $4\xive11_pri$next[7:0]$15209 8'11111111 - assign $4\xive12_pri$next[7:0]$15210 8'11111111 - assign $4\xive13_pri$next[7:0]$15211 8'11111111 - assign $4\xive14_pri$next[7:0]$15212 8'11111111 - assign $4\xive15_pri$next[7:0]$15213 8'11111111 + assign $4\xive0_pri$next[7:0]$14978 8'11111111 + assign $4\xive1_pri$next[7:0]$14985 8'11111111 + assign $4\xive2_pri$next[7:0]$14986 8'11111111 + assign $4\xive3_pri$next[7:0]$14987 8'11111111 + assign $4\xive4_pri$next[7:0]$14988 8'11111111 + assign $4\xive5_pri$next[7:0]$14989 8'11111111 + assign $4\xive6_pri$next[7:0]$14990 8'11111111 + assign $4\xive7_pri$next[7:0]$14991 8'11111111 + assign $4\xive8_pri$next[7:0]$14992 8'11111111 + assign $4\xive9_pri$next[7:0]$14993 8'11111111 + assign $4\xive10_pri$next[7:0]$14979 8'11111111 + assign $4\xive11_pri$next[7:0]$14980 8'11111111 + assign $4\xive12_pri$next[7:0]$14981 8'11111111 + assign $4\xive13_pri$next[7:0]$14982 8'11111111 + assign $4\xive14_pri$next[7:0]$14983 8'11111111 + assign $4\xive15_pri$next[7:0]$14984 8'11111111 case - assign $4\xive0_pri$next[7:0]$15207 $1\xive0_pri$next[7:0]$15159 - assign $4\xive10_pri$next[7:0]$15208 $1\xive10_pri$next[7:0]$15160 - assign $4\xive11_pri$next[7:0]$15209 $1\xive11_pri$next[7:0]$15161 - assign $4\xive12_pri$next[7:0]$15210 $1\xive12_pri$next[7:0]$15162 - assign $4\xive13_pri$next[7:0]$15211 $1\xive13_pri$next[7:0]$15163 - assign $4\xive14_pri$next[7:0]$15212 $1\xive14_pri$next[7:0]$15164 - assign $4\xive15_pri$next[7:0]$15213 $1\xive15_pri$next[7:0]$15165 - assign $4\xive1_pri$next[7:0]$15214 $1\xive1_pri$next[7:0]$15166 - assign $4\xive2_pri$next[7:0]$15215 $1\xive2_pri$next[7:0]$15167 - assign $4\xive3_pri$next[7:0]$15216 $1\xive3_pri$next[7:0]$15168 - assign $4\xive4_pri$next[7:0]$15217 $1\xive4_pri$next[7:0]$15169 - assign $4\xive5_pri$next[7:0]$15218 $1\xive5_pri$next[7:0]$15170 - assign $4\xive6_pri$next[7:0]$15219 $1\xive6_pri$next[7:0]$15171 - assign $4\xive7_pri$next[7:0]$15220 $1\xive7_pri$next[7:0]$15172 - assign $4\xive8_pri$next[7:0]$15221 $1\xive8_pri$next[7:0]$15173 - assign $4\xive9_pri$next[7:0]$15222 $1\xive9_pri$next[7:0]$15174 + assign $4\xive0_pri$next[7:0]$14978 $1\xive0_pri$next[7:0]$14930 + assign $4\xive10_pri$next[7:0]$14979 $1\xive10_pri$next[7:0]$14931 + assign $4\xive11_pri$next[7:0]$14980 $1\xive11_pri$next[7:0]$14932 + assign $4\xive12_pri$next[7:0]$14981 $1\xive12_pri$next[7:0]$14933 + assign $4\xive13_pri$next[7:0]$14982 $1\xive13_pri$next[7:0]$14934 + assign $4\xive14_pri$next[7:0]$14983 $1\xive14_pri$next[7:0]$14935 + assign $4\xive15_pri$next[7:0]$14984 $1\xive15_pri$next[7:0]$14936 + assign $4\xive1_pri$next[7:0]$14985 $1\xive1_pri$next[7:0]$14937 + assign $4\xive2_pri$next[7:0]$14986 $1\xive2_pri$next[7:0]$14938 + assign $4\xive3_pri$next[7:0]$14987 $1\xive3_pri$next[7:0]$14939 + assign $4\xive4_pri$next[7:0]$14988 $1\xive4_pri$next[7:0]$14940 + assign $4\xive5_pri$next[7:0]$14989 $1\xive5_pri$next[7:0]$14941 + assign $4\xive6_pri$next[7:0]$14990 $1\xive6_pri$next[7:0]$14942 + assign $4\xive7_pri$next[7:0]$14991 $1\xive7_pri$next[7:0]$14943 + assign $4\xive8_pri$next[7:0]$14992 $1\xive8_pri$next[7:0]$14944 + assign $4\xive9_pri$next[7:0]$14993 $1\xive9_pri$next[7:0]$14945 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$15143 - update \xive10_pri$next $0\xive10_pri$next[7:0]$15144 - update \xive11_pri$next $0\xive11_pri$next[7:0]$15145 - update \xive12_pri$next $0\xive12_pri$next[7:0]$15146 - update \xive13_pri$next $0\xive13_pri$next[7:0]$15147 - update \xive14_pri$next $0\xive14_pri$next[7:0]$15148 - update \xive15_pri$next $0\xive15_pri$next[7:0]$15149 - update \xive1_pri$next $0\xive1_pri$next[7:0]$15150 - update \xive2_pri$next $0\xive2_pri$next[7:0]$15151 - update \xive3_pri$next $0\xive3_pri$next[7:0]$15152 - update \xive4_pri$next $0\xive4_pri$next[7:0]$15153 - update \xive5_pri$next $0\xive5_pri$next[7:0]$15154 - update \xive6_pri$next $0\xive6_pri$next[7:0]$15155 - update \xive7_pri$next $0\xive7_pri$next[7:0]$15156 - update \xive8_pri$next $0\xive8_pri$next[7:0]$15157 - update \xive9_pri$next $0\xive9_pri$next[7:0]$15158 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14914 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14915 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14916 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14917 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14918 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14919 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14920 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14921 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14922 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14923 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14924 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14925 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14926 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14927 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14928 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14929 end - attribute \src "libresoc.v:206053.3-206062.6" - process $proc$libresoc.v:206053$15223 + attribute \src "libresoc.v:200541.3-200550.6" + process $proc$libresoc.v:200541$14994 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:206054.5-206054.29" + attribute \src "libresoc.v:200542.5-200542.29" switch \initial - attribute \src "libresoc.v:206054.9-206054.17" + attribute \src "libresoc.v:200542.9-200542.17" case 1'1 case end @@ -431491,14 +422794,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:206063.3-206072.6" - process $proc$libresoc.v:206063$15224 + attribute \src "libresoc.v:200551.3-200560.6" + process $proc$libresoc.v:200551$14995 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:206064.5-206064.29" + attribute \src "libresoc.v:200552.5-200552.29" switch \initial - attribute \src "libresoc.v:206064.9-206064.17" + attribute \src "libresoc.v:200552.9-200552.17" case 1'1 case end @@ -431514,14 +422817,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:206073.3-206082.6" - process $proc$libresoc.v:206073$15225 + attribute \src "libresoc.v:200561.3-200570.6" + process $proc$libresoc.v:200561$14996 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:206074.5-206074.29" + attribute \src "libresoc.v:200562.5-200562.29" switch \initial - attribute \src "libresoc.v:206074.9-206074.17" + attribute \src "libresoc.v:200562.9-200562.17" case 1'1 case end @@ -431537,14 +422840,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:206083.3-206092.6" - process $proc$libresoc.v:206083$15226 + attribute \src "libresoc.v:200571.3-200580.6" + process $proc$libresoc.v:200571$14997 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:206084.5-206084.29" + attribute \src "libresoc.v:200572.5-200572.29" switch \initial - attribute \src "libresoc.v:206084.9-206084.17" + attribute \src "libresoc.v:200572.9-200572.17" case 1'1 case end @@ -431560,14 +422863,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:206093.3-206102.6" - process $proc$libresoc.v:206093$15227 + attribute \src "libresoc.v:200581.3-200590.6" + process $proc$libresoc.v:200581$14998 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:206094.5-206094.29" + attribute \src "libresoc.v:200582.5-200582.29" switch \initial - attribute \src "libresoc.v:206094.9-206094.17" + attribute \src "libresoc.v:200582.9-200582.17" case 1'1 case end @@ -431583,14 +422886,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:206103.3-206112.6" - process $proc$libresoc.v:206103$15228 + attribute \src "libresoc.v:200591.3-200600.6" + process $proc$libresoc.v:200591$14999 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:206104.5-206104.29" + attribute \src "libresoc.v:200592.5-200592.29" switch \initial - attribute \src "libresoc.v:206104.9-206104.17" + attribute \src "libresoc.v:200592.9-200592.17" case 1'1 case end @@ -431606,14 +422909,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:206113.3-206122.6" - process $proc$libresoc.v:206113$15229 + attribute \src "libresoc.v:200601.3-200610.6" + process $proc$libresoc.v:200601$15000 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:206114.5-206114.29" + attribute \src "libresoc.v:200602.5-200602.29" switch \initial - attribute \src "libresoc.v:206114.9-206114.17" + attribute \src "libresoc.v:200602.9-200602.17" case 1'1 case end @@ -431629,14 +422932,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:206123.3-206132.6" - process $proc$libresoc.v:206123$15230 + attribute \src "libresoc.v:200611.3-200620.6" + process $proc$libresoc.v:200611$15001 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:206124.5-206124.29" + attribute \src "libresoc.v:200612.5-200612.29" switch \initial - attribute \src "libresoc.v:206124.9-206124.17" + attribute \src "libresoc.v:200612.9-200612.17" case 1'1 case end @@ -431652,14 +422955,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:206133.3-206142.6" - process $proc$libresoc.v:206133$15231 + attribute \src "libresoc.v:200621.3-200630.6" + process $proc$libresoc.v:200621$15002 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:206134.5-206134.29" + attribute \src "libresoc.v:200622.5-200622.29" switch \initial - attribute \src "libresoc.v:206134.9-206134.17" + attribute \src "libresoc.v:200622.9-200622.17" case 1'1 case end @@ -431675,14 +422978,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:206143.3-206151.6" - process $proc$libresoc.v:206143$15232 + attribute \src "libresoc.v:200631.3-200639.6" + process $proc$libresoc.v:200631$15003 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$15233 $1\int_level_l$next[15:0]$15234 - attribute \src "libresoc.v:206144.5-206144.29" + assign $0\int_level_l$next[15:0]$15004 $1\int_level_l$next[15:0]$15005 + attribute \src "libresoc.v:200632.5-200632.29" switch \initial - attribute \src "libresoc.v:206144.9-206144.17" + attribute \src "libresoc.v:200632.9-200632.17" case 1'1 case end @@ -431691,21 +422994,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$15234 16'0000000000000000 + assign $1\int_level_l$next[15:0]$15005 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$15234 \int_level_i + assign $1\int_level_l$next[15:0]$15005 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$15233 + update \int_level_l$next $0\int_level_l$next[15:0]$15004 end - attribute \src "libresoc.v:206152.3-206161.6" - process $proc$libresoc.v:206152$15235 + attribute \src "libresoc.v:200640.3-200649.6" + process $proc$libresoc.v:200640$15006 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:206153.5-206153.29" + attribute \src "libresoc.v:200641.5-200641.29" switch \initial - attribute \src "libresoc.v:206153.9-206153.17" + attribute \src "libresoc.v:200641.9-200641.17" case 1'1 case end @@ -431721,14 +423024,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:206162.3-206171.6" - process $proc$libresoc.v:206162$15236 + attribute \src "libresoc.v:200650.3-200659.6" + process $proc$libresoc.v:200650$15007 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:206163.5-206163.29" + attribute \src "libresoc.v:200651.5-200651.29" switch \initial - attribute \src "libresoc.v:206163.9-206163.17" + attribute \src "libresoc.v:200651.9-200651.17" case 1'1 case end @@ -431744,14 +423047,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:206172.3-206181.6" - process $proc$libresoc.v:206172$15237 + attribute \src "libresoc.v:200660.3-200669.6" + process $proc$libresoc.v:200660$15008 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:206173.5-206173.29" + attribute \src "libresoc.v:200661.5-200661.29" switch \initial - attribute \src "libresoc.v:206173.9-206173.17" + attribute \src "libresoc.v:200661.9-200661.17" case 1'1 case end @@ -431767,14 +423070,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:206182.3-206191.6" - process $proc$libresoc.v:206182$15238 + attribute \src "libresoc.v:200670.3-200679.6" + process $proc$libresoc.v:200670$15009 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:206183.5-206183.29" + attribute \src "libresoc.v:200671.5-200671.29" switch \initial - attribute \src "libresoc.v:206183.9-206183.17" + attribute \src "libresoc.v:200671.9-200671.17" case 1'1 case end @@ -431790,14 +423093,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:206192.3-206201.6" - process $proc$libresoc.v:206192$15239 + attribute \src "libresoc.v:200680.3-200689.6" + process $proc$libresoc.v:200680$15010 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:206193.5-206193.29" + attribute \src "libresoc.v:200681.5-200681.29" switch \initial - attribute \src "libresoc.v:206193.9-206193.17" + attribute \src "libresoc.v:200681.9-200681.17" case 1'1 case end @@ -431813,14 +423116,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:206202.3-206211.6" - process $proc$libresoc.v:206202$15240 + attribute \src "libresoc.v:200690.3-200699.6" + process $proc$libresoc.v:200690$15011 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:206203.5-206203.29" + attribute \src "libresoc.v:200691.5-200691.29" switch \initial - attribute \src "libresoc.v:206203.9-206203.17" + attribute \src "libresoc.v:200691.9-200691.17" case 1'1 case end @@ -431836,14 +423139,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:206212.3-206221.6" - process $proc$libresoc.v:206212$15241 + attribute \src "libresoc.v:200700.3-200709.6" + process $proc$libresoc.v:200700$15012 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:206213.5-206213.29" + attribute \src "libresoc.v:200701.5-200701.29" switch \initial - attribute \src "libresoc.v:206213.9-206213.17" + attribute \src "libresoc.v:200701.9-200701.17" case 1'1 case end @@ -431859,14 +423162,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:206222.3-206231.6" - process $proc$libresoc.v:206222$15242 + attribute \src "libresoc.v:200710.3-200719.6" + process $proc$libresoc.v:200710$15013 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:206223.5-206223.29" + attribute \src "libresoc.v:200711.5-200711.29" switch \initial - attribute \src "libresoc.v:206223.9-206223.17" + attribute \src "libresoc.v:200711.9-200711.17" case 1'1 case end @@ -431882,14 +423185,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:206232.3-206241.6" - process $proc$libresoc.v:206232$15243 + attribute \src "libresoc.v:200720.3-200729.6" + process $proc$libresoc.v:200720$15014 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:206233.5-206233.29" + attribute \src "libresoc.v:200721.5-200721.29" switch \initial - attribute \src "libresoc.v:206233.9-206233.17" + attribute \src "libresoc.v:200721.9-200721.17" case 1'1 case end @@ -431905,14 +423208,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:206242.3-206251.6" - process $proc$libresoc.v:206242$15244 + attribute \src "libresoc.v:200730.3-200739.6" + process $proc$libresoc.v:200730$15015 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:206243.5-206243.29" + attribute \src "libresoc.v:200731.5-200731.29" switch \initial - attribute \src "libresoc.v:206243.9-206243.17" + attribute \src "libresoc.v:200731.9-200731.17" case 1'1 case end @@ -431928,14 +423231,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:206252.3-206261.6" - process $proc$libresoc.v:206252$15245 + attribute \src "libresoc.v:200740.3-200749.6" + process $proc$libresoc.v:200740$15016 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:206253.5-206253.29" + attribute \src "libresoc.v:200741.5-200741.29" switch \initial - attribute \src "libresoc.v:206253.9-206253.17" + attribute \src "libresoc.v:200741.9-200741.17" case 1'1 case end @@ -431951,14 +423254,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:206262.3-206271.6" - process $proc$libresoc.v:206262$15246 + attribute \src "libresoc.v:200750.3-200759.6" + process $proc$libresoc.v:200750$15017 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:206263.5-206263.29" + attribute \src "libresoc.v:200751.5-200751.29" switch \initial - attribute \src "libresoc.v:206263.9-206263.17" + attribute \src "libresoc.v:200751.9-200751.17" case 1'1 case end @@ -431974,14 +423277,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:206272.3-206281.6" - process $proc$libresoc.v:206272$15247 + attribute \src "libresoc.v:200760.3-200769.6" + process $proc$libresoc.v:200760$15018 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:206273.5-206273.29" + attribute \src "libresoc.v:200761.5-200761.29" switch \initial - attribute \src "libresoc.v:206273.9-206273.17" + attribute \src "libresoc.v:200761.9-200761.17" case 1'1 case end @@ -431997,14 +423300,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:206282.3-206291.6" - process $proc$libresoc.v:206282$15248 + attribute \src "libresoc.v:200770.3-200779.6" + process $proc$libresoc.v:200770$15019 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:206283.5-206283.29" + attribute \src "libresoc.v:200771.5-200771.29" switch \initial - attribute \src "libresoc.v:206283.9-206283.17" + attribute \src "libresoc.v:200771.9-200771.17" case 1'1 case end @@ -432020,14 +423323,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:206292.3-206301.6" - process $proc$libresoc.v:206292$15249 + attribute \src "libresoc.v:200780.3-200789.6" + process $proc$libresoc.v:200780$15020 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:206293.5-206293.29" + attribute \src "libresoc.v:200781.5-200781.29" switch \initial - attribute \src "libresoc.v:206293.9-206293.17" + attribute \src "libresoc.v:200781.9-200781.17" case 1'1 case end @@ -432043,14 +423346,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:206302.3-206311.6" - process $proc$libresoc.v:206302$15250 + attribute \src "libresoc.v:200790.3-200799.6" + process $proc$libresoc.v:200790$15021 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:206303.5-206303.29" + attribute \src "libresoc.v:200791.5-200791.29" switch \initial - attribute \src "libresoc.v:206303.9-206303.17" + attribute \src "libresoc.v:200791.9-200791.17" case 1'1 case end @@ -432066,14 +423369,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:206312.3-206321.6" - process $proc$libresoc.v:206312$15251 + attribute \src "libresoc.v:200800.3-200809.6" + process $proc$libresoc.v:200800$15022 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:206313.5-206313.29" + attribute \src "libresoc.v:200801.5-200801.29" switch \initial - attribute \src "libresoc.v:206313.9-206313.17" + attribute \src "libresoc.v:200801.9-200801.17" case 1'1 case end @@ -432089,14 +423392,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:206322.3-206331.6" - process $proc$libresoc.v:206322$15252 + attribute \src "libresoc.v:200810.3-200819.6" + process $proc$libresoc.v:200810$15023 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:206323.5-206323.29" + attribute \src "libresoc.v:200811.5-200811.29" switch \initial - attribute \src "libresoc.v:206323.9-206323.17" + attribute \src "libresoc.v:200811.9-200811.17" case 1'1 case end @@ -432112,14 +423415,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:206332.3-206341.6" - process $proc$libresoc.v:206332$15253 + attribute \src "libresoc.v:200820.3-200829.6" + process $proc$libresoc.v:200820$15024 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:206333.5-206333.29" + attribute \src "libresoc.v:200821.5-200821.29" switch \initial - attribute \src "libresoc.v:206333.9-206333.17" + attribute \src "libresoc.v:200821.9-200821.17" case 1'1 case end @@ -432135,14 +423438,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:206342.3-206351.6" - process $proc$libresoc.v:206342$15254 + attribute \src "libresoc.v:200830.3-200839.6" + process $proc$libresoc.v:200830$15025 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:206343.5-206343.29" + attribute \src "libresoc.v:200831.5-200831.29" switch \initial - attribute \src "libresoc.v:206343.9-206343.17" + attribute \src "libresoc.v:200831.9-200831.17" case 1'1 case end @@ -432158,14 +423461,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:206352.3-206401.6" - process $proc$libresoc.v:206352$15255 + attribute \src "libresoc.v:200840.3-200889.6" + process $proc$libresoc.v:200840$15026 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:206353.5-206353.29" + attribute \src "libresoc.v:200841.5-200841.29" switch \initial - attribute \src "libresoc.v:206353.9-206353.17" + attribute \src "libresoc.v:200841.9-200841.17" case 1'1 case end @@ -432258,14 +423561,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:206402.3-206411.6" - process $proc$libresoc.v:206402$15256 + attribute \src "libresoc.v:200890.3-200899.6" + process $proc$libresoc.v:200890$15027 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:206403.5-206403.29" + attribute \src "libresoc.v:200891.5-200891.29" switch \initial - attribute \src "libresoc.v:206403.9-206403.17" + attribute \src "libresoc.v:200891.9-200891.17" case 1'1 case end @@ -432281,14 +423584,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:206412.3-206421.6" - process $proc$libresoc.v:206412$15257 + attribute \src "libresoc.v:200900.3-200909.6" + process $proc$libresoc.v:200900$15028 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:206413.5-206413.29" + attribute \src "libresoc.v:200901.5-200901.29" switch \initial - attribute \src "libresoc.v:206413.9-206413.17" + attribute \src "libresoc.v:200901.9-200901.17" case 1'1 case end @@ -432304,14 +423607,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:206422.3-206431.6" - process $proc$libresoc.v:206422$15258 + attribute \src "libresoc.v:200910.3-200919.6" + process $proc$libresoc.v:200910$15029 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:206423.5-206423.29" + attribute \src "libresoc.v:200911.5-200911.29" switch \initial - attribute \src "libresoc.v:206423.9-206423.17" + attribute \src "libresoc.v:200911.9-200911.17" case 1'1 case end @@ -432327,14 +423630,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:206432.3-206441.6" - process $proc$libresoc.v:206432$15259 + attribute \src "libresoc.v:200920.3-200929.6" + process $proc$libresoc.v:200920$15030 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:206433.5-206433.29" + attribute \src "libresoc.v:200921.5-200921.29" switch \initial - attribute \src "libresoc.v:206433.9-206433.17" + attribute \src "libresoc.v:200921.9-200921.17" case 1'1 case end @@ -432350,14 +423653,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:206442.3-206450.6" - process $proc$libresoc.v:206442$15260 + attribute \src "libresoc.v:200930.3-200938.6" + process $proc$libresoc.v:200930$15031 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$15261 $1\ics_wb__dat_r$next[31:0]$15262 - attribute \src "libresoc.v:206443.5-206443.29" + assign $0\ics_wb__dat_r$next[31:0]$15032 $1\ics_wb__dat_r$next[31:0]$15033 + attribute \src "libresoc.v:200931.5-200931.29" switch \initial - attribute \src "libresoc.v:206443.9-206443.17" + attribute \src "libresoc.v:200931.9-200931.17" case 1'1 case end @@ -432366,21 +423669,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$15262 0 + assign $1\ics_wb__dat_r$next[31:0]$15033 0 case - assign $1\ics_wb__dat_r$next[31:0]$15262 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$15033 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15261 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15032 end - attribute \src "libresoc.v:206451.3-206459.6" - process $proc$libresoc.v:206451$15263 + attribute \src "libresoc.v:200939.3-200947.6" + process $proc$libresoc.v:200939$15034 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$15264 $1\ics_wb__ack$next[0:0]$15265 - attribute \src "libresoc.v:206452.5-206452.29" + assign $0\ics_wb__ack$next[0:0]$15035 $1\ics_wb__ack$next[0:0]$15036 + attribute \src "libresoc.v:200940.5-200940.29" switch \initial - attribute \src "libresoc.v:206452.9-206452.17" + attribute \src "libresoc.v:200940.9-200940.17" case 1'1 case end @@ -432389,116 +423692,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$15265 1'0 - case - assign $1\ics_wb__ack$next[0:0]$15265 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15264 - end - connect \$7 $ternary$libresoc.v:205822$15018_Y - connect \$99 $lt$libresoc.v:205823$15019_Y - connect \$101 $and$libresoc.v:205824$15020_Y - connect \$103 $lt$libresoc.v:205825$15021_Y - connect \$105 $and$libresoc.v:205826$15022_Y - connect \$107 $lt$libresoc.v:205827$15023_Y - connect \$109 $and$libresoc.v:205828$15024_Y - connect \$111 $lt$libresoc.v:205829$15025_Y - connect \$113 $and$libresoc.v:205830$15026_Y - connect \$115 $lt$libresoc.v:205831$15027_Y - connect \$117 $and$libresoc.v:205832$15028_Y - connect \$119 $lt$libresoc.v:205833$15029_Y - connect \$121 $and$libresoc.v:205834$15030_Y - connect \$123 $lt$libresoc.v:205835$15031_Y - connect \$125 $and$libresoc.v:205836$15032_Y - connect \$127 $lt$libresoc.v:205837$15033_Y - connect \$12 $eq$libresoc.v:205838$15034_Y - connect \$129 $and$libresoc.v:205839$15035_Y - connect \$131 $lt$libresoc.v:205840$15036_Y - connect \$133 $and$libresoc.v:205841$15037_Y - connect \$135 $lt$libresoc.v:205842$15038_Y - connect \$137 $and$libresoc.v:205843$15039_Y - connect \$11 $ternary$libresoc.v:205844$15040_Y - connect \$139 $lt$libresoc.v:205845$15041_Y - connect \$141 $and$libresoc.v:205846$15042_Y - connect \$143 $lt$libresoc.v:205847$15043_Y - connect \$145 $and$libresoc.v:205848$15044_Y - connect \$147 $lt$libresoc.v:205849$15045_Y - connect \$149 $and$libresoc.v:205850$15046_Y - connect \$151 $lt$libresoc.v:205851$15047_Y - connect \$153 $and$libresoc.v:205852$15048_Y - connect \$155 $lt$libresoc.v:205853$15049_Y - connect \$157 $and$libresoc.v:205854$15050_Y - connect \$159 $lt$libresoc.v:205855$15051_Y - connect \$161 $and$libresoc.v:205856$15052_Y - connect \$163 $lt$libresoc.v:205857$15053_Y - connect \$165 $and$libresoc.v:205858$15054_Y - connect \$167 $lt$libresoc.v:205859$15055_Y - connect \$16 $eq$libresoc.v:205860$15056_Y - connect \$169 $and$libresoc.v:205861$15057_Y - connect \$171 $lt$libresoc.v:205862$15058_Y - connect \$173 $and$libresoc.v:205863$15059_Y - connect \$175 $lt$libresoc.v:205864$15060_Y - connect \$177 $and$libresoc.v:205865$15061_Y - connect \$15 $ternary$libresoc.v:205866$15062_Y - connect \$179 $lt$libresoc.v:205867$15063_Y - connect \$181 $and$libresoc.v:205868$15064_Y - connect \$183 $lt$libresoc.v:205869$15065_Y - connect \$185 $and$libresoc.v:205870$15066_Y - connect \$187 $lt$libresoc.v:205871$15067_Y - connect \$189 $and$libresoc.v:205872$15068_Y - connect \$191 $lt$libresoc.v:205873$15069_Y - connect \$193 $and$libresoc.v:205874$15070_Y - connect \$195 $lt$libresoc.v:205875$15071_Y - connect \$197 $and$libresoc.v:205876$15072_Y - connect \$1 $eq$libresoc.v:205877$15073_Y - connect \$199 $lt$libresoc.v:205878$15074_Y - connect \$201 $and$libresoc.v:205879$15075_Y - connect \$204 $eq$libresoc.v:205880$15076_Y - connect \$203 $ternary$libresoc.v:205881$15077_Y - connect \$20 $eq$libresoc.v:205882$15078_Y - connect \$19 $ternary$libresoc.v:205883$15079_Y - connect \$24 $eq$libresoc.v:205884$15080_Y - connect \$23 $ternary$libresoc.v:205885$15081_Y - connect \$28 $eq$libresoc.v:205886$15082_Y - connect \$27 $ternary$libresoc.v:205887$15083_Y - connect \$32 $eq$libresoc.v:205888$15084_Y - connect \$31 $ternary$libresoc.v:205889$15085_Y - connect \$36 $eq$libresoc.v:205890$15086_Y - connect \$35 $ternary$libresoc.v:205891$15087_Y - connect \$3 $eq$libresoc.v:205892$15088_Y - connect \$40 $eq$libresoc.v:205893$15089_Y - connect \$39 $ternary$libresoc.v:205894$15090_Y - connect \$44 $eq$libresoc.v:205895$15091_Y - connect \$43 $ternary$libresoc.v:205896$15092_Y - connect \$48 $eq$libresoc.v:205897$15093_Y - connect \$47 $ternary$libresoc.v:205898$15094_Y - connect \$52 $eq$libresoc.v:205899$15095_Y - connect \$51 $ternary$libresoc.v:205900$15096_Y - connect \$56 $eq$libresoc.v:205901$15097_Y - connect \$55 $ternary$libresoc.v:205902$15098_Y - connect \$5 $and$libresoc.v:205903$15099_Y - connect \$60 $eq$libresoc.v:205904$15100_Y - connect \$59 $ternary$libresoc.v:205905$15101_Y - connect \$64 $eq$libresoc.v:205906$15102_Y - connect \$63 $ternary$libresoc.v:205907$15103_Y - connect \$68 $eq$libresoc.v:205908$15104_Y - connect \$67 $ternary$libresoc.v:205909$15105_Y - connect \$71 $shr$libresoc.v:205910$15106_Y [0] - connect \$73 $and$libresoc.v:205911$15107_Y - connect \$75 $lt$libresoc.v:205912$15108_Y - connect \$77 $and$libresoc.v:205913$15109_Y - connect \$79 $lt$libresoc.v:205914$15110_Y - connect \$81 $and$libresoc.v:205915$15111_Y - connect \$83 $lt$libresoc.v:205916$15112_Y - connect \$85 $and$libresoc.v:205917$15113_Y - connect \$87 $lt$libresoc.v:205918$15114_Y - connect \$8 $eq$libresoc.v:205919$15115_Y - connect \$89 $and$libresoc.v:205920$15116_Y - connect \$91 $lt$libresoc.v:205921$15117_Y - connect \$93 $and$libresoc.v:205922$15118_Y - connect \$95 $lt$libresoc.v:205923$15119_Y - connect \$97 $and$libresoc.v:205924$15120_Y + assign $1\ics_wb__ack$next[0:0]$15036 1'0 + case + assign $1\ics_wb__ack$next[0:0]$15036 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15035 + end + connect \$7 $ternary$libresoc.v:200310$14789_Y + connect \$99 $lt$libresoc.v:200311$14790_Y + connect \$101 $and$libresoc.v:200312$14791_Y + connect \$103 $lt$libresoc.v:200313$14792_Y + connect \$105 $and$libresoc.v:200314$14793_Y + connect \$107 $lt$libresoc.v:200315$14794_Y + connect \$109 $and$libresoc.v:200316$14795_Y + connect \$111 $lt$libresoc.v:200317$14796_Y + connect \$113 $and$libresoc.v:200318$14797_Y + connect \$115 $lt$libresoc.v:200319$14798_Y + connect \$117 $and$libresoc.v:200320$14799_Y + connect \$119 $lt$libresoc.v:200321$14800_Y + connect \$121 $and$libresoc.v:200322$14801_Y + connect \$123 $lt$libresoc.v:200323$14802_Y + connect \$125 $and$libresoc.v:200324$14803_Y + connect \$127 $lt$libresoc.v:200325$14804_Y + connect \$12 $eq$libresoc.v:200326$14805_Y + connect \$129 $and$libresoc.v:200327$14806_Y + connect \$131 $lt$libresoc.v:200328$14807_Y + connect \$133 $and$libresoc.v:200329$14808_Y + connect \$135 $lt$libresoc.v:200330$14809_Y + connect \$137 $and$libresoc.v:200331$14810_Y + connect \$11 $ternary$libresoc.v:200332$14811_Y + connect \$139 $lt$libresoc.v:200333$14812_Y + connect \$141 $and$libresoc.v:200334$14813_Y + connect \$143 $lt$libresoc.v:200335$14814_Y + connect \$145 $and$libresoc.v:200336$14815_Y + connect \$147 $lt$libresoc.v:200337$14816_Y + connect \$149 $and$libresoc.v:200338$14817_Y + connect \$151 $lt$libresoc.v:200339$14818_Y + connect \$153 $and$libresoc.v:200340$14819_Y + connect \$155 $lt$libresoc.v:200341$14820_Y + connect \$157 $and$libresoc.v:200342$14821_Y + connect \$159 $lt$libresoc.v:200343$14822_Y + connect \$161 $and$libresoc.v:200344$14823_Y + connect \$163 $lt$libresoc.v:200345$14824_Y + connect \$165 $and$libresoc.v:200346$14825_Y + connect \$167 $lt$libresoc.v:200347$14826_Y + connect \$16 $eq$libresoc.v:200348$14827_Y + connect \$169 $and$libresoc.v:200349$14828_Y + connect \$171 $lt$libresoc.v:200350$14829_Y + connect \$173 $and$libresoc.v:200351$14830_Y + connect \$175 $lt$libresoc.v:200352$14831_Y + connect \$177 $and$libresoc.v:200353$14832_Y + connect \$15 $ternary$libresoc.v:200354$14833_Y + connect \$179 $lt$libresoc.v:200355$14834_Y + connect \$181 $and$libresoc.v:200356$14835_Y + connect \$183 $lt$libresoc.v:200357$14836_Y + connect \$185 $and$libresoc.v:200358$14837_Y + connect \$187 $lt$libresoc.v:200359$14838_Y + connect \$189 $and$libresoc.v:200360$14839_Y + connect \$191 $lt$libresoc.v:200361$14840_Y + connect \$193 $and$libresoc.v:200362$14841_Y + connect \$195 $lt$libresoc.v:200363$14842_Y + connect \$197 $and$libresoc.v:200364$14843_Y + connect \$1 $eq$libresoc.v:200365$14844_Y + connect \$199 $lt$libresoc.v:200366$14845_Y + connect \$201 $and$libresoc.v:200367$14846_Y + connect \$204 $eq$libresoc.v:200368$14847_Y + connect \$203 $ternary$libresoc.v:200369$14848_Y + connect \$20 $eq$libresoc.v:200370$14849_Y + connect \$19 $ternary$libresoc.v:200371$14850_Y + connect \$24 $eq$libresoc.v:200372$14851_Y + connect \$23 $ternary$libresoc.v:200373$14852_Y + connect \$28 $eq$libresoc.v:200374$14853_Y + connect \$27 $ternary$libresoc.v:200375$14854_Y + connect \$32 $eq$libresoc.v:200376$14855_Y + connect \$31 $ternary$libresoc.v:200377$14856_Y + connect \$36 $eq$libresoc.v:200378$14857_Y + connect \$35 $ternary$libresoc.v:200379$14858_Y + connect \$3 $eq$libresoc.v:200380$14859_Y + connect \$40 $eq$libresoc.v:200381$14860_Y + connect \$39 $ternary$libresoc.v:200382$14861_Y + connect \$44 $eq$libresoc.v:200383$14862_Y + connect \$43 $ternary$libresoc.v:200384$14863_Y + connect \$48 $eq$libresoc.v:200385$14864_Y + connect \$47 $ternary$libresoc.v:200386$14865_Y + connect \$52 $eq$libresoc.v:200387$14866_Y + connect \$51 $ternary$libresoc.v:200388$14867_Y + connect \$56 $eq$libresoc.v:200389$14868_Y + connect \$55 $ternary$libresoc.v:200390$14869_Y + connect \$5 $and$libresoc.v:200391$14870_Y + connect \$60 $eq$libresoc.v:200392$14871_Y + connect \$59 $ternary$libresoc.v:200393$14872_Y + connect \$64 $eq$libresoc.v:200394$14873_Y + connect \$63 $ternary$libresoc.v:200395$14874_Y + connect \$68 $eq$libresoc.v:200396$14875_Y + connect \$67 $ternary$libresoc.v:200397$14876_Y + connect \$71 $shr$libresoc.v:200398$14877_Y [0] + connect \$73 $and$libresoc.v:200399$14878_Y + connect \$75 $lt$libresoc.v:200400$14879_Y + connect \$77 $and$libresoc.v:200401$14880_Y + connect \$79 $lt$libresoc.v:200402$14881_Y + connect \$81 $and$libresoc.v:200403$14882_Y + connect \$83 $lt$libresoc.v:200404$14883_Y + connect \$85 $and$libresoc.v:200405$14884_Y + connect \$87 $lt$libresoc.v:200406$14885_Y + connect \$8 $eq$libresoc.v:200407$14886_Y + connect \$89 $and$libresoc.v:200408$14887_Y + connect \$91 $lt$libresoc.v:200409$14888_Y + connect \$93 $and$libresoc.v:200410$14889_Y + connect \$95 $lt$libresoc.v:200411$14890_Y + connect \$97 $and$libresoc.v:200412$14891_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000